diff --git a/Makefile b/Makefile index 10c8144..fb591a4 100644 --- a/Makefile +++ b/Makefile @@ -164,7 +164,7 @@ RAM_INIT_FILE ?=hello_world/hello_world.hex #MEMORY_SIZE=393216 #RAM_INIT_FILE=micropython/firmware.hex -FPGA_TARGET ?= ORANGE-CRAB-0.21 +FPGA_TARGET ?= ECPIX-5 clkgen=fpga/clk_gen_ecp5.vhd toplevel=fpga/top-generic.vhdl @@ -199,7 +199,7 @@ DFU_PRODUCT=5af0 ECP_FLASH_OFFSET=0x80000 toplevel=fpga/top-orangecrab0.2.vhdl litedram_target=orangecrab-85-0.2 -soc_extra_v += litesdcard/generated/lattice/litesdcard_core.v +soc_extra_v += litesdcard/generated/lattice.48e6/litesdcard_core.v dmi_dtm=dmi_dtm_ecp5.vhdl endif @@ -215,6 +215,23 @@ OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg endif +# ECPIX-5 +ifeq ($(FPGA_TARGET), ECPIX-5) +RESET_LOW=true +CLK_INPUT=100000000 +CLK_FREQUENCY=50000000 +LPF=constraints/ecpix-5.lpf +PACKAGE=CABGA554 +NEXTPNR_FLAGS=--um5g-85k --speed 8 --freq 50 --timing-allow-fail --ignore-loops +OPENOCD_JTAG_CONFIG=openocd/ecpix-5.cfg +OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg +toplevel=fpga/top-ecpix5.vhdl +litedram_target=ecpix-5 +soc_extra_v += litesdcard/generated/lattice.50e6/litesdcard_core.v +soc_extra_v += liteeth/generated/ecpix-5/liteeth_core.v +dmi_dtm=dmi_dtm_ecp5.vhdl +endif + ifneq ($(litedram_target),) soc_extra_synth += litedram/extras/litedram-wrapper-l2.vhdl \ litedram/generated/$(litedram_target)/litedram-initmem.vhdl diff --git a/constraints/ecpix-5.lpf b/constraints/ecpix-5.lpf new file mode 100644 index 0000000..b4da68d --- /dev/null +++ b/constraints/ecpix-5.lpf @@ -0,0 +1,359 @@ +LOCATE COMP "ext_clk" SITE "K23"; +IOBUF PORT "ext_clk" IO_TYPE=LVCMOS33; + +LOCATE COMP "ext_rst_n" SITE "N5"; +LOCATE COMP "gsrn" SITE "AB1"; +IOBUF PORT "ext_rst_n" IO_TYPE=LVCMOS33; +IOBUF PORT "gsrn" IO_TYPE=LVCMOS33; + +LOCATE COMP "uart0_txd" SITE "R24"; +LOCATE COMP "uart0_rxd" SITE "R26"; + +IOBUF PORT "uart0_txd" IO_TYPE=LVCMOS33; +IOBUF PORT "uart0_rxd" IO_TYPE=LVCMOS33; + +LOCATE COMP "led5_r_n" SITE "T23"; +LOCATE COMP "led5_g_n" SITE "R21"; +LOCATE COMP "led5_b_n" SITE "T22"; + +IOBUF PORT "led5_r_n" IO_TYPE=LVCMOS33; +IOBUF PORT "led5_g_n" IO_TYPE=LVCMOS33; +IOBUF PORT "led5_b_n" IO_TYPE=LVCMOS33; + +LOCATE COMP "led6_r_n" SITE "U21"; +LOCATE COMP "led6_g_n" SITE "W21"; +LOCATE COMP "led6_b_n" SITE "T24"; + +IOBUF PORT "led6_r_n" IO_TYPE=LVCMOS33; +IOBUF PORT "led6_g_n" IO_TYPE=LVCMOS33; +IOBUF PORT "led6_b_n" IO_TYPE=LVCMOS33; + +LOCATE COMP "led7_r_n" SITE "K21"; +LOCATE COMP "led7_g_n" SITE "K24"; +LOCATE COMP "led7_b_n" SITE "M21"; + +IOBUF PORT "led7_r_n" IO_TYPE=LVCMOS33; +IOBUF PORT "led7_g_n" IO_TYPE=LVCMOS33; +IOBUF PORT "led7_b_n" IO_TYPE=LVCMOS33; + +LOCATE COMP "led8_r_n" SITE "P21"; +LOCATE COMP "led8_g_n" SITE "R23"; +LOCATE COMP "led8_b_n" SITE "P22"; + +IOBUF PORT "led8_r_n" IO_TYPE=LVCMOS33; +IOBUF PORT "led8_g_n" IO_TYPE=LVCMOS33; +IOBUF PORT "led8_b_n" IO_TYPE=LVCMOS33; + +// We use USRMCLK instead for clk +// LOCATE COMP "spi_flash_clk" SITE "U16"; +// IOBUF PORT "spi_flash_clk" IO_TYPE=LVCMOS33; +LOCATE COMP "spi_flash_cs_n" SITE "AA2"; +IOBUF PORT "spi_flash_cs_n" IO_TYPE=LVCMOS33; +LOCATE COMP "spi_flash_mosi" SITE "AE2"; +IOBUF PORT "spi_flash_mosi" IO_TYPE=LVCMOS33; +LOCATE COMP "spi_flash_miso" SITE "AD2"; +IOBUF PORT "spi_flash_miso" IO_TYPE=LVCMOS33; +LOCATE COMP "spi_flash_wp_n" SITE "AF2"; +IOBUF PORT "spi_flash_wp_n" IO_TYPE=LVCMOS33; +LOCATE COMP "spi_flash_hold_n" SITE "AE1"; +IOBUF PORT "spi_flash_hold_n" IO_TYPE=LVCMOS33; + +// Ethernet +LOCATE COMP "rgmii_clocks_rx" SITE "E11"; +LOCATE COMP "rgmii_clocks_tx" SITE "A12"; +LOCATE COMP "rgmii_rst_n" SITE "C13"; +LOCATE COMP "rgmii_int_n" SITE "B13"; +LOCATE COMP "rgmii_mdc" SITE "C11"; +LOCATE COMP "rgmii_mdio" SITE "A13"; +LOCATE COMP "rgmii_rx_ctl" SITE "A11"; +LOCATE COMP "rgmii_rx_data[0]" SITE "B11"; +LOCATE COMP "rgmii_rx_data[1]" SITE "A10"; +LOCATE COMP "rgmii_rx_data[2]" SITE "B10"; +LOCATE COMP "rgmii_rx_data[3]" SITE "A9"; +LOCATE COMP "rgmii_tx_ctl" SITE "C9"; +LOCATE COMP "rgmii_tx_data[0]" SITE "D8"; +LOCATE COMP "rgmii_tx_data[1]" SITE "C8"; +LOCATE COMP "rgmii_tx_data[2]" SITE "B8"; +LOCATE COMP "rgmii_tx_data[3]" SITE "A8"; +IOBUF PORT "rgmii_clocks_rx" IO_TYPE=LVCMOS33; +IOBUF PORT "rgmii_clocks_tx" IO_TYPE=LVCMOS33; +IOBUF PORT "rgmii_rst_n" IO_TYPE=LVCMOS33; +IOBUF PORT "rgmii_int_n" IO_TYPE=LVCMOS33; +IOBUF PORT "rgmii_mdc" IO_TYPE=LVCMOS33; +IOBUF PORT "rgmii_mdio" IO_TYPE=LVCMOS33; +IOBUF PORT "rgmii_rx_ctl" IO_TYPE=LVCMOS33; +IOBUF PORT "rgmii_rx_data[0]" IO_TYPE=LVCMOS33 PULLMODE=UP; +IOBUF PORT "rgmii_rx_data[1]" IO_TYPE=LVCMOS33 PULLMODE=UP; +IOBUF PORT "rgmii_rx_data[2]" IO_TYPE=LVCMOS33 PULLMODE=UP; +IOBUF PORT "rgmii_rx_data[3]" IO_TYPE=LVCMOS33 PULLMODE=UP; +IOBUF PORT "rgmii_tx_ctl" IO_TYPE=LVCMOS33; +IOBUF PORT "rgmii_tx_data[0]" IO_TYPE=LVCMOS33; +IOBUF PORT "rgmii_tx_data[1]" IO_TYPE=LVCMOS33; +IOBUF PORT "rgmii_tx_data[2]" IO_TYPE=LVCMOS33; +IOBUF PORT "rgmii_tx_data[3]" IO_TYPE=LVCMOS33; +FREQUENCY PORT "eth_rx_clk" 125.0 MHz; +FREQUENCY PORT "eth_tx_clk" 125.0 MHz; +FREQUENCY PORT "rgmii_clocks_rx" 125.0 MHz; + +// SD card slot and level translator +LOCATE COMP "sdcard_data[0]" SITE "N26"; +LOCATE COMP "sdcard_data[1]" SITE "N25"; +LOCATE COMP "sdcard_data[2]" SITE "N23"; +LOCATE COMP "sdcard_data[3]" SITE "N21"; +LOCATE COMP "sdcard_cmd" SITE "M24"; +LOCATE COMP "sdcard_clk" SITE "P24"; +LOCATE COMP "sdcard_cd" SITE "L22"; +LOCATE COMP "sdcard_cmd_dir" SITE "M23"; +LOCATE COMP "sdcard_dat0_dir" SITE "N24"; +LOCATE COMP "sdcard_dat13_dir" SITE "P26"; +LOCATE COMP "sdcard_vsel" SITE "L24"; + +IOBUF PORT "sdcard_data[0]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP; +IOBUF PORT "sdcard_data[1]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP; +IOBUF PORT "sdcard_data[2]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP; +IOBUF PORT "sdcard_data[3]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP; +IOBUF PORT "sdcard_cmd" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP; +IOBUF PORT "sdcard_clk" IO_TYPE=LVCMOS33 SLEWRATE=FAST; +IOBUF PORT "sdcard_cd" IO_TYPE=LVCMOS33; +IOBUF PORT "sdcard_cmd_dir" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP; +IOBUF PORT "sdcard_dat0_dir" IO_TYPE=LVCMOS33 SLEWRATE=FAST; +IOBUF PORT "sdcard_dat13_dir" IO_TYPE=LVCMOS33 SLEWRATE=FAST; +IOBUF PORT "sdcard_vsel" IO_TYPE=LVCMOS33 PULLMODE=DOWN; + +// DDR3 SDRAM +LOCATE COMP "ddram_a[0]" SITE "T5"; +LOCATE COMP "ddram_a[1]" SITE "M3"; +LOCATE COMP "ddram_a[2]" SITE "L3"; +LOCATE COMP "ddram_a[3]" SITE "V6"; +LOCATE COMP "ddram_a[4]" SITE "K2"; +LOCATE COMP "ddram_a[5]" SITE "W6"; +LOCATE COMP "ddram_a[6]" SITE "K3"; +LOCATE COMP "ddram_a[7]" SITE "L1"; +LOCATE COMP "ddram_a[8]" SITE "H2"; +LOCATE COMP "ddram_a[9]" SITE "L2"; +LOCATE COMP "ddram_a[10]" SITE "N1"; +LOCATE COMP "ddram_a[11]" SITE "J1"; +LOCATE COMP "ddram_a[12]" SITE "M1"; +LOCATE COMP "ddram_a[13]" SITE "K1"; +LOCATE COMP "ddram_a[14]" SITE "H1"; +IOBUF PORT "ddram_a[0]" IO_TYPE=SSTL15_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[1]" IO_TYPE=SSTL15_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[2]" IO_TYPE=SSTL15_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[3]" IO_TYPE=SSTL15_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[4]" IO_TYPE=SSTL15_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[5]" IO_TYPE=SSTL15_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[6]" IO_TYPE=SSTL15_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[7]" IO_TYPE=SSTL15_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[8]" IO_TYPE=SSTL15_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[9]" IO_TYPE=SSTL15_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[10]" IO_TYPE=SSTL15_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[11]" IO_TYPE=SSTL15_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[12]" IO_TYPE=SSTL15_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[13]" IO_TYPE=SSTL15_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[14]" IO_TYPE=SSTL15_I SLEWRATE=FAST; + +LOCATE COMP "ddram_ba[0]" SITE "U6"; +LOCATE COMP "ddram_ba[1]" SITE "N3"; +LOCATE COMP "ddram_ba[2]" SITE "N4"; +LOCATE COMP "ddram_ras_n" SITE "T3"; +LOCATE COMP "ddram_cas_n" SITE "P2"; +LOCATE COMP "ddram_we_n" SITE "R3"; +LOCATE COMP "ddram_dm[0]" SITE "U4"; +LOCATE COMP "ddram_dm[1]" SITE "U1"; +IOBUF PORT "ddram_ba[0]" IO_TYPE=SSTL15_I SLEWRATE=FAST; +IOBUF PORT "ddram_ba[1]" IO_TYPE=SSTL15_I SLEWRATE=FAST; +IOBUF PORT "ddram_ba[2]" IO_TYPE=SSTL15_I SLEWRATE=FAST; +IOBUF PORT "ddram_ras_n" IO_TYPE=SSTL15_I SLEWRATE=FAST; +IOBUF PORT "ddram_cas_n" IO_TYPE=SSTL15_I SLEWRATE=FAST; +IOBUF PORT "ddram_we_n" IO_TYPE=SSTL15_I SLEWRATE=FAST; +IOBUF PORT "ddram_dm[0]" IO_TYPE=SSTL15_I SLEWRATE=FAST; +IOBUF PORT "ddram_dm[1]" IO_TYPE=SSTL15_I SLEWRATE=FAST; + +LOCATE COMP "ddram_dq[0]" SITE "T4"; +LOCATE COMP "ddram_dq[1]" SITE "W4"; +LOCATE COMP "ddram_dq[2]" SITE "R4"; +LOCATE COMP "ddram_dq[3]" SITE "W5"; +LOCATE COMP "ddram_dq[4]" SITE "R6"; +LOCATE COMP "ddram_dq[5]" SITE "P6"; +LOCATE COMP "ddram_dq[6]" SITE "P5"; +LOCATE COMP "ddram_dq[7]" SITE "P4"; +LOCATE COMP "ddram_dq[8]" SITE "R1"; +LOCATE COMP "ddram_dq[9]" SITE "W3"; +LOCATE COMP "ddram_dq[10]" SITE "T2"; +LOCATE COMP "ddram_dq[11]" SITE "V3"; +LOCATE COMP "ddram_dq[12]" SITE "U3"; +LOCATE COMP "ddram_dq[13]" SITE "W1"; +LOCATE COMP "ddram_dq[14]" SITE "T1"; +LOCATE COMP "ddram_dq[15]" SITE "W2"; +IOBUF PORT "ddram_dq[0]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75; +IOBUF PORT "ddram_dq[1]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75; +IOBUF PORT "ddram_dq[2]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75; +IOBUF PORT "ddram_dq[3]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75; +IOBUF PORT "ddram_dq[4]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75; +IOBUF PORT "ddram_dq[5]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75; +IOBUF PORT "ddram_dq[6]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75; +IOBUF PORT "ddram_dq[7]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75; +IOBUF PORT "ddram_dq[8]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75; +IOBUF PORT "ddram_dq[9]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75; +IOBUF PORT "ddram_dq[10]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75; +IOBUF PORT "ddram_dq[11]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75; +IOBUF PORT "ddram_dq[12]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75; +IOBUF PORT "ddram_dq[13]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75; +IOBUF PORT "ddram_dq[14]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75; +IOBUF PORT "ddram_dq[15]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75; + +LOCATE COMP "ddram_dqs_n[0]" SITE "U5"; +LOCATE COMP "ddram_dqs_n[1]" SITE "U2"; +LOCATE COMP "ddram_dqs_p[0]" SITE "V4"; +LOCATE COMP "ddram_dqs_p[1]" SITE "V1"; +IOBUF PORT "ddram_dqs_n[0]" IO_TYPE=SSTL15D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF; +IOBUF PORT "ddram_dqs_n[1]" IO_TYPE=SSTL15D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF; +IOBUF PORT "ddram_dqs_p[0]" IO_TYPE=SSTL15D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF; +IOBUF PORT "ddram_dqs_p[1]" IO_TYPE=SSTL15D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF; + +LOCATE COMP "ddram_clk_p" SITE "H3"; +LOCATE COMP "ddram_clk_n" SITE "J3"; +IOBUF PORT "ddram_clk_p" IO_TYPE=SSTL15D_I SLEWRATE=FAST; +IOBUF PORT "ddram_clk_n" IO_TYPE=SSTL15D_I SLEWRATE=FAST; + +LOCATE COMP "ddram_cke" SITE "P1"; +LOCATE COMP "ddram_odt" SITE "P3"; +IOBUF PORT "ddram_cke" IO_TYPE=SSTL15_I SLEWRATE=FAST; +IOBUF PORT "ddram_odt" IO_TYPE=SSTL15_I SLEWRATE=FAST; + +// PMOD signals +LOCATE COMP "pmod0_0" SITE "T25"; +IOBUF PORT "pmod0_0" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod0_1" SITE "U25"; +IOBUF PORT "pmod0_1" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod0_2" SITE "U24"; +IOBUF PORT "pmod0_2" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod0_3" SITE "V24"; +IOBUF PORT "pmod0_3" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod0_4" SITE "T26"; +IOBUF PORT "pmod0_4" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod0_5" SITE "U26"; +IOBUF PORT "pmod0_5" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod0_6" SITE "V26"; +IOBUF PORT "pmod0_6" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod0_7" SITE "W26"; +IOBUF PORT "pmod0_7" IO_TYPE=LVCMOS33; + +LOCATE COMP "pmod1_0" SITE "U23"; +IOBUF PORT "pmod1_0" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod1_1" SITE "V23"; +IOBUF PORT "pmod1_1" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod1_2" SITE "U22"; +IOBUF PORT "pmod1_2" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod1_3" SITE "V21"; +IOBUF PORT "pmod1_3" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod1_4" SITE "W25"; +IOBUF PORT "pmod1_4" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod1_5" SITE "W24"; +IOBUF PORT "pmod1_5" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod1_6" SITE "W23"; +IOBUF PORT "pmod1_6" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod1_7" SITE "W22"; +IOBUF PORT "pmod1_7" IO_TYPE=LVCMOS33; + +LOCATE COMP "pmod2_0" SITE "J24"; +IOBUF PORT "pmod2_0" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod2_1" SITE "H22"; +IOBUF PORT "pmod2_1" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod2_2" SITE "E21"; +IOBUF PORT "pmod2_2" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod2_3" SITE "D18"; +IOBUF PORT "pmod2_3" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod2_4" SITE "K22"; +IOBUF PORT "pmod2_4" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod2_5" SITE "J21"; +IOBUF PORT "pmod2_5" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod2_6" SITE "H21"; +IOBUF PORT "pmod2_6" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod2_7" SITE "D22"; +IOBUF PORT "pmod2_7" IO_TYPE=LVCMOS33; + +LOCATE COMP "pmod3_0" SITE "E4"; +IOBUF PORT "pmod3_0" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod3_1" SITE "F4"; +IOBUF PORT "pmod3_1" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod3_2" SITE "E6"; +IOBUF PORT "pmod3_2" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod3_3" SITE "H4"; +IOBUF PORT "pmod3_3" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod3_4" SITE "F3"; +IOBUF PORT "pmod3_4" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod3_5" SITE "D4"; +IOBUF PORT "pmod3_5" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod3_6" SITE "D5"; +IOBUF PORT "pmod3_6" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod3_7" SITE "F5"; +IOBUF PORT "pmod3_7" IO_TYPE=LVCMOS33; + +LOCATE COMP "pmod4_0" SITE "E26"; +IOBUF PORT "pmod4_0" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod4_1" SITE "D25"; +IOBUF PORT "pmod4_1" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod4_2" SITE "F26"; +IOBUF PORT "pmod4_2" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod4_3" SITE "F25"; +IOBUF PORT "pmod4_3" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod4_4" SITE "C26"; +IOBUF PORT "pmod4_4" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod4_5" SITE "C25"; +IOBUF PORT "pmod4_5" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod4_6" SITE "A25"; +IOBUF PORT "pmod4_6" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod4_7" SITE "A24"; +IOBUF PORT "pmod4_7" IO_TYPE=LVCMOS33; + +LOCATE COMP "pmod5_0" SITE "D19"; +IOBUF PORT "pmod5_0" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod5_1" SITE "C21"; +IOBUF PORT "pmod5_1" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod5_2" SITE "B21"; +IOBUF PORT "pmod5_2" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod5_3" SITE "C22"; +IOBUF PORT "pmod5_3" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod5_4" SITE "D21"; +IOBUF PORT "pmod5_4" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod5_5" SITE "A21"; +IOBUF PORT "pmod5_5" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod5_6" SITE "A22"; +IOBUF PORT "pmod5_6" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod5_7" SITE "A23"; +IOBUF PORT "pmod5_7" IO_TYPE=LVCMOS33; + +LOCATE COMP "pmod6_0" SITE "C16"; +IOBUF PORT "pmod6_0" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod6_1" SITE "B17"; +IOBUF PORT "pmod6_1" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod6_2" SITE "C18"; +IOBUF PORT "pmod6_2" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod6_3" SITE "B19"; +IOBUF PORT "pmod6_3" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod6_4" SITE "A17"; +IOBUF PORT "pmod6_4" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod6_5" SITE "A18"; +IOBUF PORT "pmod6_5" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod6_6" SITE "A19"; +IOBUF PORT "pmod6_6" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod6_7" SITE "C19"; +IOBUF PORT "pmod6_7" IO_TYPE=LVCMOS33; + +LOCATE COMP "pmod7_0" SITE "D14"; +IOBUF PORT "pmod7_0" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod7_1" SITE "B14"; +IOBUF PORT "pmod7_1" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod7_2" SITE "E14"; +IOBUF PORT "pmod7_2" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod7_3" SITE "B16"; +IOBUF PORT "pmod7_3" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod7_4" SITE "C14"; +IOBUF PORT "pmod7_4" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod7_5" SITE "A14"; +IOBUF PORT "pmod7_5" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod7_6" SITE "A15"; +IOBUF PORT "pmod7_6" IO_TYPE=LVCMOS33; +LOCATE COMP "pmod7_7" SITE "A16"; +IOBUF PORT "pmod7_7" IO_TYPE=LVCMOS33; diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl index 508202c..0980667 100644 --- a/fpga/top-arty.vhdl +++ b/fpga/top-arty.vhdl @@ -488,18 +488,18 @@ begin component liteeth_core port ( sys_clock : in std_ulogic; sys_reset : in std_ulogic; - mii_eth_clocks_tx : in std_ulogic; - mii_eth_clocks_rx : in std_ulogic; - mii_eth_rst_n : out std_ulogic; - mii_eth_mdio : in std_ulogic; - mii_eth_mdc : out std_ulogic; - mii_eth_rx_dv : in std_ulogic; - mii_eth_rx_er : in std_ulogic; - mii_eth_rx_data : in std_ulogic_vector(3 downto 0); - mii_eth_tx_en : out std_ulogic; - mii_eth_tx_data : out std_ulogic_vector(3 downto 0); - mii_eth_col : in std_ulogic; - mii_eth_crs : in std_ulogic; + mii_clocks_tx : in std_ulogic; + mii_clocks_rx : in std_ulogic; + mii_rst_n : out std_ulogic; + mii_mdio : in std_ulogic; + mii_mdc : out std_ulogic; + mii_rx_dv : in std_ulogic; + mii_rx_er : in std_ulogic; + mii_rx_data : in std_ulogic_vector(3 downto 0); + mii_tx_en : out std_ulogic; + mii_tx_data : out std_ulogic_vector(3 downto 0); + mii_col : in std_ulogic; + mii_crs : in std_ulogic; wishbone_adr : in std_ulogic_vector(29 downto 0); wishbone_dat_w : in std_ulogic_vector(31 downto 0); wishbone_dat_r : out std_ulogic_vector(31 downto 0); @@ -573,18 +573,18 @@ begin port map( sys_clock => system_clk, sys_reset => periph_rst, - mii_eth_clocks_tx => eth_clocks_tx, - mii_eth_clocks_rx => eth_clocks_rx, - mii_eth_rst_n => eth_rst_n, - mii_eth_mdio => eth_mdio, - mii_eth_mdc => eth_mdc, - mii_eth_rx_dv => eth_rx_dv, - mii_eth_rx_er => eth_rx_er, - mii_eth_rx_data => eth_rx_data, - mii_eth_tx_en => eth_tx_en, - mii_eth_tx_data => eth_tx_data, - mii_eth_col => eth_col, - mii_eth_crs => eth_crs, + mii_clocks_tx => eth_clocks_tx, + mii_clocks_rx => eth_clocks_rx, + mii_rst_n => eth_rst_n, + mii_mdio => eth_mdio, + mii_mdc => eth_mdc, + mii_rx_dv => eth_rx_dv, + mii_rx_er => eth_rx_er, + mii_rx_data => eth_rx_data, + mii_tx_en => eth_tx_en, + mii_tx_data => eth_tx_data, + mii_col => eth_col, + mii_crs => eth_crs, wishbone_adr => wb_eth_adr, wishbone_dat_w => wb_ext_io_in.dat, wishbone_dat_r => wb_eth_out.dat, diff --git a/fpga/top-ecpix5.vhdl b/fpga/top-ecpix5.vhdl new file mode 100644 index 0000000..301f573 --- /dev/null +++ b/fpga/top-ecpix5.vhdl @@ -0,0 +1,652 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.wishbone_types.all; + +entity toplevel is + generic ( + MEMORY_SIZE : integer := 16384; + RAM_INIT_FILE : string := "firmware.hex"; + RESET_LOW : boolean := true; + CLK_INPUT : positive := 100000000; + CLK_FREQUENCY : positive := 50000000; + HAS_FPU : boolean := true; + HAS_BTC : boolean := true; + USE_LITEDRAM : boolean := true; + NO_BRAM : boolean := true; + SCLK_STARTUPE2 : boolean := false; + SPI_FLASH_OFFSET : integer := 4194304; + SPI_FLASH_DEF_CKDV : natural := 0; + SPI_FLASH_DEF_QUAD : boolean := true; + LOG_LENGTH : natural := 0; + UART_IS_16550 : boolean := true; + HAS_UART1 : boolean := false; + USE_LITEETH : boolean := true; + USE_LITESDCARD : boolean := true; + ICACHE_NUM_LINES : natural := 64; + NGPIO : natural := 0 + ); + port( + ext_clk : in std_ulogic; + ext_rst_n : in std_ulogic; + gsrn : in std_ulogic; + + -- UART0 signals: + uart0_txd : out std_ulogic; + uart0_rxd : in std_ulogic; + + -- LEDs + led5_r_n : out std_ulogic; + led5_g_n : out std_ulogic; + led5_b_n : out std_ulogic; + led6_r_n : out std_ulogic; + led6_g_n : out std_ulogic; + led6_b_n : out std_ulogic; + led7_r_n : out std_ulogic; + led7_g_n : out std_ulogic; + led7_b_n : out std_ulogic; + led8_r_n : out std_ulogic; + led8_g_n : out std_ulogic; + led8_b_n : out std_ulogic; + + -- SPI + spi_flash_cs_n : out std_ulogic; + spi_flash_mosi : inout std_ulogic; + spi_flash_miso : inout std_ulogic; + spi_flash_wp_n : inout std_ulogic; + spi_flash_hold_n : inout std_ulogic; + + -- Ethernet + rgmii_clocks_rx : in std_ulogic; + rgmii_clocks_tx : out std_ulogic; + rgmii_rst_n : out std_ulogic; + rgmii_int_n : in std_ulogic; + rgmii_mdc : out std_ulogic; + rgmii_mdio : inout std_ulogic; + rgmii_rx_ctl : in std_ulogic; + rgmii_rx_data : in std_ulogic_vector(3 downto 0); + rgmii_tx_ctl : out std_ulogic; + rgmii_tx_data : out std_ulogic_vector(3 downto 0); + + -- SD card wires + sdcard_data : inout std_ulogic_vector(3 downto 0); + sdcard_cmd : inout std_ulogic; + sdcard_clk : out std_ulogic; + sdcard_cd : in std_ulogic; + sdcard_cmd_dir : out std_ulogic; + sdcard_dat0_dir : out std_ulogic; + sdcard_dat13_dir : out std_ulogic; + sdcard_vsel : out std_ulogic; + + -- PMOD ports 0 - 7 + pmod0_0 : inout std_ulogic; + pmod0_1 : inout std_ulogic; + pmod0_2 : inout std_ulogic; + pmod0_3 : inout std_ulogic; + pmod0_4 : inout std_ulogic; + pmod0_5 : inout std_ulogic; + pmod0_6 : inout std_ulogic; + pmod0_7 : inout std_ulogic; + pmod1_0 : inout std_ulogic; + pmod1_1 : inout std_ulogic; + pmod1_2 : inout std_ulogic; + pmod1_3 : inout std_ulogic; + pmod1_4 : inout std_ulogic; + pmod1_5 : inout std_ulogic; + pmod1_6 : inout std_ulogic; + pmod1_7 : inout std_ulogic; + pmod2_0 : inout std_ulogic; + pmod2_1 : inout std_ulogic; + pmod2_2 : inout std_ulogic; + pmod2_3 : inout std_ulogic; + pmod2_4 : inout std_ulogic; + pmod2_5 : inout std_ulogic; + pmod2_6 : inout std_ulogic; + pmod2_7 : inout std_ulogic; + pmod3_0 : inout std_ulogic; + pmod3_1 : inout std_ulogic; + pmod3_2 : inout std_ulogic; + pmod3_3 : inout std_ulogic; + pmod3_4 : inout std_ulogic; + pmod3_5 : inout std_ulogic; + pmod3_6 : inout std_ulogic; + pmod3_7 : inout std_ulogic; + pmod4_0 : inout std_ulogic; -- 0n + pmod4_1 : inout std_ulogic; -- 0p + pmod4_2 : inout std_ulogic; -- 1n + pmod4_3 : inout std_ulogic; -- 1p + pmod4_4 : inout std_ulogic; -- 2n + pmod4_5 : inout std_ulogic; -- 2p + pmod4_6 : inout std_ulogic; -- 3n + pmod4_7 : inout std_ulogic; -- 3p + pmod5_0 : inout std_ulogic; + pmod5_1 : inout std_ulogic; + pmod5_2 : inout std_ulogic; + pmod5_3 : inout std_ulogic; + pmod5_4 : inout std_ulogic; + pmod5_5 : inout std_ulogic; + pmod5_6 : inout std_ulogic; + pmod5_7 : inout std_ulogic; + pmod6_0 : inout std_ulogic; + pmod6_1 : inout std_ulogic; + pmod6_2 : inout std_ulogic; + pmod6_3 : inout std_ulogic; + pmod6_4 : inout std_ulogic; + pmod6_5 : inout std_ulogic; + pmod6_6 : inout std_ulogic; + pmod6_7 : inout std_ulogic; + pmod7_0 : inout std_ulogic; + pmod7_1 : inout std_ulogic; + pmod7_2 : inout std_ulogic; + pmod7_3 : inout std_ulogic; + pmod7_4 : inout std_ulogic; + pmod7_5 : inout std_ulogic; + pmod7_6 : inout std_ulogic; + pmod7_7 : inout std_ulogic; + + -- DRAM wires + ddram_a : out std_ulogic_vector(14 downto 0); + ddram_ba : out std_ulogic_vector(2 downto 0); + ddram_ras_n : out std_ulogic; + ddram_cas_n : out std_ulogic; + ddram_we_n : out std_ulogic; + ddram_dm : out std_ulogic_vector(1 downto 0); + ddram_dq : inout std_ulogic_vector(15 downto 0); + ddram_dqs_p : inout std_ulogic_vector(1 downto 0); + ddram_clk_p : out std_ulogic_vector(0 downto 0); + -- only the positive differential pin is instantiated + --ddram_dqs_n : inout std_ulogic_vector(1 downto 0); + --ddram_clk_n : out std_ulogic_vector(0 downto 0); + ddram_cke : out std_ulogic; + ddram_odt : out std_ulogic + ); +end entity toplevel; + +architecture behaviour of toplevel is + + -- Reset signals: + signal soc_rst : std_ulogic; + signal pll_rst : std_ulogic; + + -- Internal clock signals: + signal system_clk : std_ulogic; + signal system_clk_locked : std_ulogic; + + -- External IOs from the SoC + signal wb_ext_io_in : wb_io_master_out; + signal wb_ext_io_out : wb_io_slave_out; + signal wb_ext_is_dram_csr : std_ulogic; + signal wb_ext_is_dram_init : std_ulogic; + signal wb_ext_is_eth : std_ulogic; + signal wb_ext_is_sdcard : std_ulogic; + + -- DRAM main data wishbone connection + signal wb_dram_in : wishbone_master_out; + signal wb_dram_out : wishbone_slave_out; + + -- DRAM control wishbone connection + signal wb_dram_ctrl_out : wb_io_slave_out := wb_io_slave_out_init; + + -- LiteEth connection + signal ext_irq_eth : std_ulogic; + signal wb_eth_out : wb_io_slave_out := wb_io_slave_out_init; + + -- LiteSDCard connection + signal ext_irq_sdcard : std_ulogic := '0'; + signal wb_sdcard_out : wb_io_slave_out := wb_io_slave_out_init; + signal wb_sddma_out : wb_io_master_out := wb_io_master_out_init; + signal wb_sddma_in : wb_io_slave_out; + signal wb_sddma_nr : wb_io_master_out; + signal wb_sddma_ir : wb_io_slave_out; + -- for conversion from non-pipelined wishbone to pipelined + signal wb_sddma_stb_sent : std_ulogic; + + -- SPI flash + signal spi_sck : std_ulogic; + signal spi_sck_ts : std_ulogic; + signal spi_cs_n : std_ulogic; + signal spi_sdat_o : std_ulogic_vector(3 downto 0); + signal spi_sdat_oe : std_ulogic_vector(3 downto 0); + signal spi_sdat_i : std_ulogic_vector(3 downto 0); + + -- Fixup various memory sizes based on generics + function get_bram_size return natural is + begin + if USE_LITEDRAM and NO_BRAM then + return 0; + else + return MEMORY_SIZE; + end if; + end function; + + function get_payload_size return natural is + begin + if USE_LITEDRAM and NO_BRAM then + return MEMORY_SIZE; + else + return 0; + end if; + end function; + + constant BRAM_SIZE : natural := get_bram_size; + constant PAYLOAD_SIZE : natural := get_payload_size; + + COMPONENT USRMCLK + PORT( + USRMCLKI : IN STD_ULOGIC; + USRMCLKTS : IN STD_ULOGIC + ); + END COMPONENT; + attribute syn_noprune: boolean ; + attribute syn_noprune of USRMCLK: component is true; + +begin + + -- Main SoC + soc0: entity work.soc + generic map( + MEMORY_SIZE => BRAM_SIZE, + RAM_INIT_FILE => RAM_INIT_FILE, + SIM => false, + CLK_FREQ => CLK_FREQUENCY, + HAS_FPU => HAS_FPU, + HAS_BTC => HAS_BTC, + HAS_DRAM => USE_LITEDRAM, + DRAM_SIZE => 512 * 1024 * 1024, + DRAM_INIT_SIZE => PAYLOAD_SIZE, + HAS_SPI_FLASH => true, + SPI_FLASH_DLINES => 4, + SPI_FLASH_OFFSET => SPI_FLASH_OFFSET, + SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV, + SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD, + LOG_LENGTH => LOG_LENGTH, + UART0_IS_16550 => UART_IS_16550, + HAS_UART1 => HAS_UART1, + HAS_LITEETH => USE_LITEETH, + HAS_SD_CARD => USE_LITESDCARD, + ICACHE_NUM_LINES => ICACHE_NUM_LINES, + NGPIO => NGPIO + ) + port map ( + -- System signals + system_clk => system_clk, + rst => soc_rst, + + -- UART signals + uart0_txd => uart0_txd, + uart0_rxd => uart0_rxd, + + -- SPI signals + spi_flash_sck => spi_sck, + spi_flash_cs_n => spi_cs_n, + spi_flash_sdat_o => spi_sdat_o, + spi_flash_sdat_oe => spi_sdat_oe, + spi_flash_sdat_i => spi_sdat_i, + + -- External interrupts + ext_irq_eth => ext_irq_eth, + ext_irq_sdcard => ext_irq_sdcard, + + -- DRAM wishbone + wb_dram_in => wb_dram_in, + wb_dram_out => wb_dram_out, + + -- IO wishbone + wb_ext_io_in => wb_ext_io_in, + wb_ext_io_out => wb_ext_io_out, + wb_ext_is_dram_csr => wb_ext_is_dram_csr, + wb_ext_is_dram_init => wb_ext_is_dram_init, + wb_ext_is_eth => wb_ext_is_eth, + wb_ext_is_sdcard => wb_ext_is_sdcard, + + -- DMA wishbone + wishbone_dma_in => wb_sddma_in, + wishbone_dma_out => wb_sddma_out + ); + + -- SPI Flash + -- + spi_flash_cs_n <= spi_cs_n; + spi_flash_mosi <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z'; + spi_flash_miso <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z'; + spi_flash_wp_n <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z'; + spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z'; + spi_sdat_i(0) <= spi_flash_mosi; + spi_sdat_i(1) <= spi_flash_miso; + spi_sdat_i(2) <= spi_flash_wp_n; + spi_sdat_i(3) <= spi_flash_hold_n; + spi_sck_ts <= '0'; + + uclk: USRMCLK port map ( + USRMCLKI => spi_sck, + USRMCLKTS => spi_sck_ts + ); + + nodram: if not USE_LITEDRAM generate + signal div2 : std_ulogic := '0'; + begin + reset_controller: entity work.soc_reset + generic map( + RESET_LOW => RESET_LOW + ) + port map( + ext_clk => ext_clk, + pll_clk => system_clk, + pll_locked_in => system_clk_locked, + ext_rst_in => ext_rst_n and gsrn, + pll_rst_out => pll_rst, + rst_out => soc_rst + ); + + process(ext_clk) + begin + if rising_edge(ext_clk) then + div2 <= not div2; + end if; + end process; + + system_clk <= div2; + system_clk_locked <= '1'; + + led8_r_n <= '1'; + led8_g_n <= '1'; + led8_b_n <= '1'; + + end generate; + + has_dram: if USE_LITEDRAM generate + signal dram_init_done : std_ulogic; + signal dram_init_error : std_ulogic; + signal dram_sys_rst : std_ulogic; + begin + + -- Eventually dig out the frequency from + -- litesdram generate.py sys_clk_freq + -- but for now, assert it's 50Mhz for ECPIX-5 + assert CLK_FREQUENCY = 50000000; + + reset_controller: entity work.soc_reset + generic map( + RESET_LOW => RESET_LOW, + PLL_RESET_BITS => 18, + SOC_RESET_BITS => 20 + ) + port map( + ext_clk => ext_clk, + pll_clk => system_clk, + pll_locked_in => system_clk_locked and not dram_sys_rst, + ext_rst_in => ext_rst_n and gsrn, + pll_rst_out => pll_rst, + rst_out => soc_rst + ); + + -- Generate SoC reset + soc_rst_gen: process(system_clk) + begin + if ext_rst_n = '0' then + soc_rst <= '1'; + elsif rising_edge(system_clk) then + soc_rst <= dram_sys_rst or not system_clk_locked; + end if; + end process; + + dram: entity work.litedram_wrapper + generic map( + DRAM_ABITS => 25, + DRAM_ALINES => 15, + DRAM_DLINES => 16, + DRAM_CKLINES => 1, + DRAM_PORT_WIDTH => 128, + PAYLOAD_FILE => RAM_INIT_FILE, + PAYLOAD_SIZE => PAYLOAD_SIZE + ) + port map( + clk_in => ext_clk, + rst => pll_rst, + system_clk => system_clk, + system_reset => dram_sys_rst, + pll_locked => system_clk_locked, + + wb_in => wb_dram_in, + wb_out => wb_dram_out, + wb_ctrl_in => wb_ext_io_in, + wb_ctrl_out => wb_dram_ctrl_out, + wb_ctrl_is_csr => wb_ext_is_dram_csr, + wb_ctrl_is_init => wb_ext_is_dram_init, + + init_done => dram_init_done, + init_error => dram_init_error, + + ddram_a => ddram_a, + ddram_ba => ddram_ba, + ddram_ras_n => ddram_ras_n, + ddram_cas_n => ddram_cas_n, + ddram_we_n => ddram_we_n, + ddram_dm => ddram_dm, + ddram_dq => ddram_dq, + ddram_dqs_p => ddram_dqs_p, + ddram_clk_p => ddram_clk_p, + -- only the positive differential pin is instantiated + --ddram_dqs_n => ddram_dqs_n, + --ddram_clk_n => ddram_clk_n, + ddram_cke => ddram_cke, + ddram_odt => ddram_odt + ); + + -- active-low outputs to the LED + led8_b_n <= dram_init_done; + led8_r_n <= not dram_init_error; + led8_g_n <= not (dram_init_done and not dram_init_error); + end generate; + + has_liteeth : if USE_LITEETH generate + + component liteeth_core port ( + sys_clock : in std_ulogic; + sys_reset : in std_ulogic; + rgmii_clocks_tx : out std_ulogic; + rgmii_clocks_rx : in std_ulogic; + rgmii_rst_n : out std_ulogic; + rgmii_int_n : in std_ulogic; + rgmii_mdio : inout std_ulogic; + rgmii_mdc : out std_ulogic; + rgmii_rx_ctl : in std_ulogic; + rgmii_rx_data : in std_ulogic_vector(3 downto 0); + rgmii_tx_ctl : out std_ulogic; + rgmii_tx_data : out std_ulogic_vector(3 downto 0); + wishbone_adr : in std_ulogic_vector(29 downto 0); + wishbone_dat_w : in std_ulogic_vector(31 downto 0); + wishbone_dat_r : out std_ulogic_vector(31 downto 0); + wishbone_sel : in std_ulogic_vector(3 downto 0); + wishbone_cyc : in std_ulogic; + wishbone_stb : in std_ulogic; + wishbone_ack : out std_ulogic; + wishbone_we : in std_ulogic; + wishbone_cti : in std_ulogic_vector(2 downto 0); + wishbone_bte : in std_ulogic_vector(1 downto 0); + wishbone_err : out std_ulogic; + interrupt : out std_ulogic + ); + end component; + + signal wb_eth_cyc : std_ulogic; + signal wb_eth_adr : std_ulogic_vector(29 downto 0); + + begin + liteeth : liteeth_core + port map( + sys_clock => system_clk, + sys_reset => soc_rst, + rgmii_clocks_tx => rgmii_clocks_tx, + rgmii_clocks_rx => rgmii_clocks_rx, + rgmii_rst_n => rgmii_rst_n, + rgmii_int_n => rgmii_int_n, + rgmii_mdio => rgmii_mdio, + rgmii_mdc => rgmii_mdc, + rgmii_rx_ctl => rgmii_rx_ctl, + rgmii_rx_data => rgmii_rx_data, + rgmii_tx_ctl => rgmii_tx_ctl, + rgmii_tx_data => rgmii_tx_data, + wishbone_adr => wb_eth_adr, + wishbone_dat_w => wb_ext_io_in.dat, + wishbone_dat_r => wb_eth_out.dat, + wishbone_sel => wb_ext_io_in.sel, + wishbone_cyc => wb_eth_cyc, + wishbone_stb => wb_ext_io_in.stb, + wishbone_ack => wb_eth_out.ack, + wishbone_we => wb_ext_io_in.we, + wishbone_cti => "000", + wishbone_bte => "00", + wishbone_err => open, + interrupt => ext_irq_eth + ); + + -- Gate cyc with "chip select" from soc + wb_eth_cyc <= wb_ext_io_in.cyc and wb_ext_is_eth; + + -- Remove top address bits as liteeth decoder doesn't know about them + wb_eth_adr <= x"000" & "000" & wb_ext_io_in.adr(14 downto 0); + + -- LiteETH isn't pipelined + wb_eth_out.stall <= not wb_eth_out.ack; + + end generate; + + no_liteeth : if not USE_LITEETH generate + ext_irq_eth <= '0'; + end generate; + + -- SD card + -- The ECPIX-5 has a buffer/level translator chip in order to be able to + -- support 1.8V signalling to the SD card as well as 3V signalling. + -- Litesdcard doesn't currently support voltage selection, or the higher + -- data transfer rates that require the lower voltage. + has_sdcard : if USE_LITESDCARD generate + component litesdcard_core port ( + clk : in std_ulogic; + rst : in std_ulogic; + irq : out std_ulogic; + -- wishbone for accessing control registers + wb_ctrl_adr : in std_ulogic_vector(29 downto 0); + wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0); + wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0); + wb_ctrl_sel : in std_ulogic_vector(3 downto 0); + wb_ctrl_cyc : in std_ulogic; + wb_ctrl_stb : in std_ulogic; + wb_ctrl_ack : out std_ulogic; + wb_ctrl_we : in std_ulogic; + wb_ctrl_cti : in std_ulogic_vector(2 downto 0); + wb_ctrl_bte : in std_ulogic_vector(1 downto 0); + wb_ctrl_err : out std_ulogic; + -- wishbone for SD card core to use for DMA + wb_dma_adr : out std_ulogic_vector(29 downto 0); + wb_dma_dat_w : out std_ulogic_vector(31 downto 0); + wb_dma_dat_r : in std_ulogic_vector(31 downto 0); + wb_dma_sel : out std_ulogic_vector(3 downto 0); + wb_dma_cyc : out std_ulogic; + wb_dma_stb : out std_ulogic; + wb_dma_ack : in std_ulogic; + wb_dma_we : out std_ulogic; + wb_dma_cti : out std_ulogic_vector(2 downto 0); + wb_dma_bte : out std_ulogic_vector(1 downto 0); + wb_dma_err : in std_ulogic; + -- connections to SD card + sdcard_data : inout std_ulogic_vector(3 downto 0); + sdcard_cmd : inout std_ulogic; + sdcard_clk : out std_ulogic; + sdcard_cd : in std_ulogic; + sdcard_cmd_dir : out std_ulogic; + sdcard_dat0_dir : out std_ulogic; + sdcard_dat13_dir : out std_ulogic + ); + end component; + + signal wb_sdcard_cyc : std_ulogic; + signal wb_sdcard_adr : std_ulogic_vector(29 downto 0); + + begin + litesdcard : litesdcard_core + port map ( + clk => system_clk, + rst => soc_rst, + irq => ext_irq_sdcard, + wb_ctrl_adr => wb_sdcard_adr, + wb_ctrl_dat_w => wb_ext_io_in.dat, + wb_ctrl_dat_r => wb_sdcard_out.dat, + wb_ctrl_sel => wb_ext_io_in.sel, + wb_ctrl_cyc => wb_sdcard_cyc, + wb_ctrl_stb => wb_ext_io_in.stb, + wb_ctrl_ack => wb_sdcard_out.ack, + wb_ctrl_we => wb_ext_io_in.we, + wb_ctrl_cti => "000", + wb_ctrl_bte => "00", + wb_ctrl_err => open, + wb_dma_adr => wb_sddma_nr.adr, + wb_dma_dat_w => wb_sddma_nr.dat, + wb_dma_dat_r => wb_sddma_ir.dat, + wb_dma_sel => wb_sddma_nr.sel, + wb_dma_cyc => wb_sddma_nr.cyc, + wb_dma_stb => wb_sddma_nr.stb, + wb_dma_ack => wb_sddma_ir.ack, + wb_dma_we => wb_sddma_nr.we, + wb_dma_cti => open, + wb_dma_bte => open, + wb_dma_err => '0', + sdcard_data => sdcard_data, + sdcard_cmd => sdcard_cmd, + sdcard_clk => sdcard_clk, + sdcard_cd => sdcard_cd, + sdcard_cmd_dir => sdcard_cmd_dir, + sdcard_dat0_dir => sdcard_dat0_dir, + sdcard_dat13_dir => sdcard_dat13_dir + ); + + -- Select 3V signalling + sdcard_vsel <= '0'; + + -- Gate cyc with chip select from SoC + wb_sdcard_cyc <= wb_ext_io_in.cyc and wb_ext_is_sdcard; + + wb_sdcard_adr <= x"0000" & wb_ext_io_in.adr(13 downto 0); + + wb_sdcard_out.stall <= not wb_sdcard_out.ack; + + -- Convert non-pipelined DMA wishbone to pipelined by suppressing + -- non-acknowledged strobes + process(system_clk) + begin + if rising_edge(system_clk) then + wb_sddma_out <= wb_sddma_nr; + if wb_sddma_stb_sent = '1' or + (wb_sddma_out.stb = '1' and wb_sddma_in.stall = '0') then + wb_sddma_out.stb <= '0'; + end if; + if wb_sddma_nr.cyc = '0' or wb_sddma_ir.ack = '1' then + wb_sddma_stb_sent <= '0'; + elsif wb_sddma_in.stall = '0' then + wb_sddma_stb_sent <= wb_sddma_nr.stb; + end if; + wb_sddma_ir <= wb_sddma_in; + end if; + end process; + + end generate; + + -- Mux WB response on the IO bus + wb_ext_io_out <= wb_eth_out when wb_ext_is_eth = '1' else + wb_sdcard_out when wb_ext_is_sdcard = '1' else + wb_dram_ctrl_out; + + led5_r_n <= '1'; + led5_g_n <= '1'; + led5_b_n <= '1'; + led6_r_n <= '1'; + led6_g_n <= '1'; + led6_b_n <= '1'; + led7_r_n <= not soc_rst; + led7_g_n <= not system_clk_locked; + led7_b_n <= '1'; + +end architecture behaviour; diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl index f18f80e..156fc97 100644 --- a/fpga/top-nexys-video.vhdl +++ b/fpga/top-nexys-video.vhdl @@ -384,16 +384,16 @@ begin component liteeth_core port ( sys_clock : in std_ulogic; sys_reset : in std_ulogic; - rgmii_eth_clocks_tx : out std_ulogic; - rgmii_eth_clocks_rx : in std_ulogic; - rgmii_eth_rst_n : out std_ulogic; - rgmii_eth_int_n : in std_ulogic; - rgmii_eth_mdio : inout std_ulogic; - rgmii_eth_mdc : out std_ulogic; - rgmii_eth_rx_ctl : in std_ulogic; - rgmii_eth_rx_data : in std_ulogic_vector(3 downto 0); - rgmii_eth_tx_ctl : out std_ulogic; - rgmii_eth_tx_data : out std_ulogic_vector(3 downto 0); + rgmii_clocks_tx : out std_ulogic; + rgmii_clocks_rx : in std_ulogic; + rgmii_rst_n : out std_ulogic; + rgmii_int_n : in std_ulogic; + rgmii_mdio : inout std_ulogic; + rgmii_mdc : out std_ulogic; + rgmii_rx_ctl : in std_ulogic; + rgmii_rx_data : in std_ulogic_vector(3 downto 0); + rgmii_tx_ctl : out std_ulogic; + rgmii_tx_data : out std_ulogic_vector(3 downto 0); wishbone_adr : in std_ulogic_vector(29 downto 0); wishbone_dat_w : in std_ulogic_vector(31 downto 0); wishbone_dat_r : out std_ulogic_vector(31 downto 0); @@ -417,16 +417,16 @@ begin port map( sys_clock => system_clk, sys_reset => soc_rst, - rgmii_eth_clocks_tx => eth_clocks_tx, - rgmii_eth_clocks_rx => eth_clocks_rx, - rgmii_eth_rst_n => eth_rst_n, - rgmii_eth_int_n => eth_int_n, - rgmii_eth_mdio => eth_mdio, - rgmii_eth_mdc => eth_mdc, - rgmii_eth_rx_ctl => eth_rx_ctl, - rgmii_eth_rx_data => eth_rx_data, - rgmii_eth_tx_ctl => eth_tx_ctl, - rgmii_eth_tx_data => eth_tx_data, + rgmii_clocks_tx => eth_clocks_tx, + rgmii_clocks_rx => eth_clocks_rx, + rgmii_rst_n => eth_rst_n, + rgmii_int_n => eth_int_n, + rgmii_mdio => eth_mdio, + rgmii_mdc => eth_mdc, + rgmii_rx_ctl => eth_rx_ctl, + rgmii_rx_data => eth_rx_data, + rgmii_tx_ctl => eth_tx_ctl, + rgmii_tx_data => eth_tx_data, wishbone_adr => wb_eth_adr, wishbone_dat_w => wb_ext_io_in.dat, wishbone_dat_r => wb_eth_out.dat, diff --git a/fpga/top-wukong-v2.vhdl b/fpga/top-wukong-v2.vhdl index 2b6d4e1..b6c7262 100644 --- a/fpga/top-wukong-v2.vhdl +++ b/fpga/top-wukong-v2.vhdl @@ -380,20 +380,20 @@ begin component liteeth_core port ( sys_clock : in std_ulogic; sys_reset : in std_ulogic; - gmii_eth_clocks_tx : in std_ulogic; - gmii_eth_clocks_gtx : out std_ulogic; - gmii_eth_clocks_rx : in std_ulogic; - gmii_eth_rst_n : out std_ulogic; - gmii_eth_mdio : inout std_ulogic; - gmii_eth_mdc : out std_ulogic; - gmii_eth_rx_dv : in std_ulogic; - gmii_eth_rx_er : in std_ulogic; - gmii_eth_rx_data : in std_ulogic_vector(7 downto 0); - gmii_eth_tx_en : out std_ulogic; - gmii_eth_tx_er : out std_ulogic; - gmii_eth_tx_data : out std_ulogic_vector(7 downto 0); - gmii_eth_col : in std_ulogic; - gmii_eth_crs : in std_ulogic; + gmii_clocks_tx : in std_ulogic; + gmii_clocks_gtx : out std_ulogic; + gmii_clocks_rx : in std_ulogic; + gmii_rst_n : out std_ulogic; + gmii_mdio : inout std_ulogic; + gmii_mdc : out std_ulogic; + gmii_rx_dv : in std_ulogic; + gmii_rx_er : in std_ulogic; + gmii_rx_data : in std_ulogic_vector(7 downto 0); + gmii_tx_en : out std_ulogic; + gmii_tx_er : out std_ulogic; + gmii_tx_data : out std_ulogic_vector(7 downto 0); + gmii_col : in std_ulogic; + gmii_crs : in std_ulogic; wishbone_adr : in std_ulogic_vector(29 downto 0); wishbone_dat_w : in std_ulogic_vector(31 downto 0); wishbone_dat_r : out std_ulogic_vector(31 downto 0); @@ -420,20 +420,20 @@ begin port map( sys_clock => system_clk, sys_reset => soc_rst, - gmii_eth_clocks_tx => eth_clocks_tx, - gmii_eth_clocks_gtx => eth_clocks_gtx, - gmii_eth_clocks_rx => eth_clocks_rx, - gmii_eth_rst_n => eth_rst_n, - gmii_eth_mdio => eth_mdio, - gmii_eth_mdc => eth_mdc, - gmii_eth_rx_dv => eth_rx_dv, - gmii_eth_rx_er => eth_rx_er, - gmii_eth_rx_data => eth_rx_data, - gmii_eth_tx_en => eth_tx_en, - gmii_eth_tx_er => eth_tx_er, - gmii_eth_tx_data => eth_tx_data, - gmii_eth_col => eth_col, - gmii_eth_crs => eth_crs, + gmii_clocks_tx => eth_clocks_tx, + gmii_clocks_gtx => eth_clocks_gtx, + gmii_clocks_rx => eth_clocks_rx, + gmii_rst_n => eth_rst_n, + gmii_mdio => eth_mdio, + gmii_mdc => eth_mdc, + gmii_rx_dv => eth_rx_dv, + gmii_rx_er => eth_rx_er, + gmii_rx_data => eth_rx_data, + gmii_tx_en => eth_tx_en, + gmii_tx_er => eth_tx_er, + gmii_tx_data => eth_tx_data, + gmii_col => eth_col, + gmii_crs => eth_crs, wishbone_adr => wb_eth_adr, wishbone_dat_w => wb_ext_io_in.dat, wishbone_dat_r => wb_eth_out.dat, diff --git a/litedram/gen-src/ecpix-5.yml b/litedram/gen-src/ecpix-5.yml new file mode 100644 index 0000000..3e6ca3a --- /dev/null +++ b/litedram/gen-src/ecpix-5.yml @@ -0,0 +1,34 @@ +# Based on orangecrab-85-0.2.yml and arty.yml + +{ + "cpu": "None", # CPU type (ex vexriscv, serv, None) + "device": "LFE5UM5G-85F-8BG554I", + "memtype": "DDR3", # DRAM type + + "cmd_latency": 0, + "sdram_module": "MT41K256M16", # SDRAM modules of the board or SO-DIMM + "sdram_module_nb": 2, # Number of byte groups + "sdram_rank_nb": 1, # Number of ranks + "sdram_phy": "ECP5DDRPHY", # Type of FPGA PHY + + # Electrical --------------------------------------------------------------- + "rtt_nom": "60ohm", # Nominal termination. (Default) + "rtt_wr": "60ohm", # Write termination. (Default) + "ron": "34ohm", # Output driver impedance. (Default) + + # Frequency ---------------------------------------------------------------- + "input_clk_freq": 100e6, # Input clock frequency + "sys_clk_freq": 50e6, # System clock frequency (DDR_clk = 4 x sys_clk) + "init_clk_freq": 50e6, # ? + + # Core --------------------------------------------------------------------- + "cmd_buffer_depth": 16, # Depth of the command buffer + + # User Ports --------------------------------------------------------------- + "user_ports": { + "native_0": { + "type": "native", + "block_until_ready": False, + }, + }, +} diff --git a/litedram/gen-src/generate.py b/litedram/gen-src/generate.py index 0710b6a..bb66bbf 100755 --- a/litedram/gen-src/generate.py +++ b/litedram/gen-src/generate.py @@ -100,7 +100,8 @@ def generate_one(t): def main(): - targets = ['arty','nexys-video', 'genesys2', 'acorn-cle-215', 'wukong-v2', 'orangecrab-85-0.2', 'sim'] + targets = ['arty','nexys-video', 'genesys2', 'acorn-cle-215', 'wukong-v2', 'orangecrab-85-0.2', + 'ecpix-5', 'sim'] for t in targets: generate_one(t) diff --git a/litedram/gen-src/sdram_init/Makefile b/litedram/gen-src/sdram_init/Makefile index 6f50dae..1744f3b 100644 --- a/litedram/gen-src/sdram_init/Makefile +++ b/litedram/gen-src/sdram_init/Makefile @@ -5,7 +5,8 @@ OBJ = $(BUILD_DIR)/obj LXINC_DIR=$(LXSRC_DIR)/include PROGRAM = sdram_init -OBJECTS = $(OBJ)/head.o $(OBJ)/main.o $(OBJ)/sdram.o $(OBJ)/memtest.o $(OBJ)/console.o +OBJECTS = $(OBJ)/head.o $(OBJ)/main.o $(OBJ)/sdram.o $(OBJ)/accessors.o \ + $(OBJ)/memtest.o $(OBJ)/console.o #### Compiler @@ -58,6 +59,8 @@ all: objdir $(OBJ)/$(PROGRAM).hex $(OBJ)/sdram.o: $(LXSRC_DIR)/liblitedram/sdram.c $(call Q,CC, $(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@, $@) +$(OBJ)/accessors.o: $(LXSRC_DIR)/liblitedram/accessors.c + $(call Q,CC, $(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@, $@) $(OBJ)/memtest.o: $(LXSRC_DIR)/libbase/memtest.c $(call Q,CC, $(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@, $@) $(OBJ)/console.o: $(SRC_DIR)/../../../lib/console.c diff --git a/litedram/gen-src/sdram_init/main.c b/litedram/gen-src/sdram_init/main.c index 2d99410..9bf98d4 100644 --- a/litedram/gen-src/sdram_init/main.c +++ b/litedram/gen-src/sdram_init/main.c @@ -41,6 +41,7 @@ void flush_cpu_icache(void) #define SPI_CMD_READ 0x03 #define SPI_CMD_DUAL_FREAD 0x3b #define SPI_CMD_QUAD_FREAD 0x6b +#define SPI_CMD_QUAD_FREAD_4BA 0x6c #define SPI_CMD_RDCR 0x35 #define SPI_CMD_WREN 0x06 #define SPI_CMD_PP 0x02 @@ -106,10 +107,44 @@ static void check_spansion_quad_mode(void) wait_wip(); } +static uint32_t check_enable_issi_quad(void) +{ + uint8_t sr; + + /* Read status register to see if quad mode is already enabled */ + fl_cs_on(); + writeb(SPI_CMD_RDSR, SPI_FCTRL_BASE + SPI_REG_DATA); + sr = readb(SPI_FCTRL_BASE + SPI_REG_DATA); + fl_cs_off(); + if ((sr & 0x40) == 0) { + printf(" [enabling quad]"); + send_wren(); + fl_cs_on(); + writeb(SPI_CMD_WWR, SPI_FCTRL_BASE + SPI_REG_DATA); + writeb(sr | 0x40, SPI_FCTRL_BASE + SPI_REG_DATA); + fl_cs_off(); + wait_wip(); + } + + /* Enable quad mode and 4B addresses, 8 dummy cycles */ + return SPI_CMD_QUAD_FREAD_4BA | + (0x07 << SPI_REG_AUTO_CFG_DUMMIES_SHIFT) | + SPI_REG_AUT_CFG_MODE_QUAD | SPI_REG_AUTO_CFG_ADDR4 | + (0x20 << SPI_REG_AUTO_CFG_CSTOUT_SHIFT); +} + static bool check_flash(void) { bool quad = false; uint8_t id[3]; + uint32_t autocfg; + + /* default auto mode configuration for quad reads: */ + /* Enable quad mode, 8 dummy clocks, 32 cycles CS timeout */ + autocfg = SPI_CMD_QUAD_FREAD | + (0x07 << SPI_REG_AUTO_CFG_DUMMIES_SHIFT) | + SPI_REG_AUT_CFG_MODE_QUAD | + (0x20 << SPI_REG_AUTO_CFG_CSTOUT_SHIFT); fl_cs_on(); writeb(SPI_CMD_RDID, SPI_FCTRL_BASE + SPI_REG_DATA); @@ -134,6 +169,13 @@ static bool check_flash(void) printf(" Micron"); quad = true; } + if (id[0] == 0x9d && (id[1] & ~0x10) == 0x60 && + id[2] == 0x19) { + /* ISSI IS25LP256D or IS25WP256D */ + printf(" ISSI"); + autocfg = check_enable_issi_quad(); + quad = true; + } if (quad) { uint32_t cfg; printf(" [quad IO mode]"); @@ -141,12 +183,8 @@ static bool check_flash(void) /* Preserve the default clock div for the board */ cfg = readl(SPI_FCTRL_BASE + SPI_REG_AUTO_CFG); cfg &= SPI_REG_AUTO_CFG_CKDIV_MASK; + cfg |= autocfg; - /* Enable quad mode, 8 dummy clocks, 32 cycles CS timeout */ - cfg |= SPI_CMD_QUAD_FREAD | - (0x07 << SPI_REG_AUTO_CFG_DUMMIES_SHIFT) | - SPI_REG_AUT_CFG_MODE_QUAD | - (0x20 << SPI_REG_AUTO_CFG_CSTOUT_SHIFT); writel(cfg, SPI_FCTRL_BASE + SPI_REG_AUTO_CFG); } printf("\n"); diff --git a/litedram/generated/acorn-cle-215/litedram_core.init b/litedram/generated/acorn-cle-215/litedram_core.init index 61e54f3..0573632 100644 --- a/litedram/generated/acorn-cle-215/litedram_core.init +++ b/litedram/generated/acorn-cle-215/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ff00782107c6 3d80000060215f00 798c07c6618c0000 -618c10e0658cff00 +618c10d4658cff00 4e8004217d8903a6 4e8004207c6903a6 0000000000000000 @@ -510,677 +510,687 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 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+eb01ffc0eae1ffb8 +eb41ffd0eb21ffc8 +eb81ffe0eb61ffd8 +eba1ffe8e8010010 +ebc1fff07c0803a6 +4e800020ebe1fff8 +e8010010ebc1fff0 +7c0803a6ebe1fff8 +600000004e800020 6d6f636c65570a0a 63694d206f742065 2120747461776f72 @@ -1875,7 +1859,7 @@ ebe1fff8e8010010 203a46464f204853 7479622078257830 00000000000a7365 -2d2d2d2d2d2d2d2d +3033633733313738 0000000000000000 4d4152446574694c 6620746c69756220 @@ -1944,6 +1928,8 @@ ebe1fff8e8010010 52445320676e697a 3025783040204d41 000a2e2e2e786c38 +000000540000002a +6000000000000024 0000000042756c25 4b756c252e756c25 0000000000004269 diff --git a/litedram/generated/acorn-cle-215/litedram_core.v b/litedram/generated/acorn-cle-215/litedram_core.v index 22c0e22..6125302 100644 --- a/litedram/generated/acorn-cle-215/litedram_core.v +++ b/litedram/generated/acorn-cle-215/litedram_core.v @@ -8,10 +8,11 @@ // // Filename : litedram_core.v // Device : -// LiteX sha1 : -------- -// Date : 2022-10-28 19:01:23 +// LiteX sha1 : 87137c30 +// Date : 2024-04-01 10:12:09 //------------------------------------------------------------------------------ +`timescale 1ns / 1ps //------------------------------------------------------------------------------ // Module @@ -19,4868 +20,5328 @@ module litedram_core ( input wire clk, - input wire rst, - output wire pll_locked, output wire [15:0] ddram_a, output wire [2:0] ddram_ba, - output wire ddram_ras_n, output wire ddram_cas_n, - output wire ddram_we_n, + output wire ddram_cke, + output wire ddram_clk_n, + output wire ddram_clk_p, output wire ddram_cs_n, output wire [1:0] ddram_dm, inout wire [15:0] ddram_dq, - inout wire [1:0] ddram_dqs_p, inout wire [1:0] ddram_dqs_n, - output wire ddram_clk_p, - output wire ddram_clk_n, - output wire ddram_cke, + inout wire [1:0] ddram_dqs_p, output wire ddram_odt, + output wire ddram_ras_n, output wire ddram_reset_n, + output wire ddram_we_n, output wire init_done, output wire init_error, - input wire [29:0] wb_ctrl_adr, - input wire [31:0] wb_ctrl_dat_w, - output wire [31:0] wb_ctrl_dat_r, - input wire [3:0] wb_ctrl_sel, - input wire wb_ctrl_cyc, - input wire wb_ctrl_stb, - output wire wb_ctrl_ack, - input wire wb_ctrl_we, - input wire [2:0] wb_ctrl_cti, - input wire [1:0] wb_ctrl_bte, - output wire wb_ctrl_err, + output wire pll_locked, + input wire rst, output wire user_clk, - output wire user_rst, - input wire user_port_native_0_cmd_valid, + input wire [25:0] user_port_native_0_cmd_addr, output wire user_port_native_0_cmd_ready, + input wire user_port_native_0_cmd_valid, input wire user_port_native_0_cmd_we, - input wire [25:0] user_port_native_0_cmd_addr, - input wire user_port_native_0_wdata_valid, + output wire [127:0] user_port_native_0_rdata_data, + input wire user_port_native_0_rdata_ready, + output wire user_port_native_0_rdata_valid, + input wire [127:0] user_port_native_0_wdata_data, output wire user_port_native_0_wdata_ready, + input wire user_port_native_0_wdata_valid, input wire [15:0] user_port_native_0_wdata_we, - input wire [127:0] user_port_native_0_wdata_data, - output wire user_port_native_0_rdata_valid, - input wire user_port_native_0_rdata_ready, - output wire [127:0] user_port_native_0_rdata_data + output wire user_rst, + output wire wb_ctrl_ack, + input wire [29:0] wb_ctrl_adr, + input wire [1:0] wb_ctrl_bte, + input wire [2:0] wb_ctrl_cti, + input wire wb_ctrl_cyc, + output wire [31:0] wb_ctrl_dat_r, + input wire [31:0] wb_ctrl_dat_w, + output wire wb_ctrl_err, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_stb, + input wire wb_ctrl_we ); +//------------------------------------------------------------------------------ +// Hierarchy +//------------------------------------------------------------------------------ + +/* +LiteDRAMCore +└─── bus (SoCBusHandler) +│ └─── _interconnect (InterconnectPointToPoint) +└─── csr (SoCCSRHandler) +└─── irq (SoCIRQHandler) +└─── cpu (CPUNone) +└─── crg (LiteDRAMS7DDRPHYCRG) +│ └─── pll (S7PLL) +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [BUFG] +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [BUFG] +│ │ └─── [BUFG] +│ │ └─── [BUFG] +│ │ └─── [PLLE2_ADV] +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ └─── idelayctrl (S7IDELAYCTRL) +│ │ └─── [IDELAYCTRL] +└─── ddrphy (A7DDRPHY) +│ └─── tappeddelayline_0* (TappedDelayLine) +│ └─── dqspattern_0* (DQSPattern) +│ └─── bitslip_0* (BitSlip) +│ └─── bitslip_1* (BitSlip) +│ └─── bitslip_2* (BitSlip) +│ └─── bitslip_3* (BitSlip) +│ └─── tappeddelayline_1* (TappedDelayLine) +│ └─── bitslip_4* (BitSlip) +│ └─── bitslip_5* (BitSlip) +│ └─── bitslip_6* (BitSlip) +│ └─── bitslip_7* (BitSlip) +│ └─── bitslip_8* (BitSlip) +│ └─── bitslip_9* (BitSlip) +│ └─── bitslip_10* (BitSlip) +│ └─── bitslip_11* (BitSlip) +│ └─── bitslip_12* (BitSlip) +│ └─── bitslip_13* (BitSlip) +│ └─── bitslip_14* (BitSlip) +│ └─── bitslip_15* (BitSlip) +│ └─── bitslip_16* (BitSlip) +│ └─── bitslip_17* (BitSlip) +│ └─── bitslip_18* (BitSlip) +│ └─── bitslip_19* (BitSlip) +│ └─── bitslip_20* (BitSlip) +│ └─── bitslip_21* (BitSlip) +│ └─── bitslip_22* (BitSlip) +│ └─── bitslip_23* (BitSlip) +│ └─── bitslip_24* (BitSlip) +│ └─── bitslip_25* (BitSlip) +│ └─── bitslip_26* (BitSlip) +│ └─── bitslip_27* (BitSlip) +│ └─── bitslip_28* (BitSlip) +│ └─── bitslip_29* (BitSlip) +│ └─── bitslip_30* (BitSlip) +│ └─── bitslip_31* (BitSlip) +│ └─── bitslip_32* (BitSlip) +│ └─── bitslip_33* (BitSlip) +│ └─── bitslip_34* (BitSlip) +│ └─── bitslip_35* (BitSlip) +│ └─── tappeddelayline_2* (TappedDelayLine) +│ └─── tappeddelayline_3* (TappedDelayLine) +│ └─── [IDELAYE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [ISERDESE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OBUFDS] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [ISERDESE2] +│ └─── [IOBUFDS] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [IOBUFDS] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +└─── sdram (LiteDRAMCore) +│ └─── dfii (DFIInjector) +│ │ └─── pi0 (PhaseInjector) +│ │ └─── pi1 (PhaseInjector) +│ │ └─── pi2 (PhaseInjector) +│ │ └─── pi3 (PhaseInjector) +│ └─── controller (LiteDRAMController) +│ │ └─── refresher (Refresher) +│ │ │ └─── timer (RefreshTimer) +│ │ │ └─── postponer (RefreshPostponer) +│ │ │ └─── sequencer (RefreshSequencer) +│ │ │ │ └─── refreshexecuter_0* (RefreshExecuter) +│ │ │ └─── zqcs_timer (RefreshTimer) +│ │ │ └─── zqs_executer (ZQCSExecuter) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_0* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_1* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_2* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_3* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_4* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_5* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_6* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_7* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── multiplexer (Multiplexer) +│ │ │ └─── choose_cmd (_CommandChooser) +│ │ │ │ └─── roundrobin_0* (RoundRobin) +│ │ │ └─── choose_req (_CommandChooser) +│ │ │ │ └─── roundrobin_0* (RoundRobin) +│ │ │ └─── _steerer_0* (_Steerer) +│ │ │ └─── trrdcon (tXXDController) +│ │ │ └─── tfawcon (tFAWController) +│ │ │ └─── tccdcon (tXXDController) +│ │ │ └─── twtrcon (tXXDController) +│ │ │ └─── fsm (FSM) +│ └─── crossbar (LiteDRAMCrossbar) +│ │ └─── roundrobin_0* (RoundRobin) +│ │ └─── roundrobin_1* (RoundRobin) +│ │ └─── roundrobin_2* (RoundRobin) +│ │ └─── roundrobin_3* (RoundRobin) +│ │ └─── roundrobin_4* (RoundRobin) +│ │ └─── roundrobin_5* (RoundRobin) +│ │ └─── roundrobin_6* (RoundRobin) +│ │ └─── roundrobin_7* (RoundRobin) +└─── ddrctrl (LiteDRAMCoreControl) +└─── csr_bridge (Wishbone2CSR) +│ └─── fsm (FSM) +└─── csr_bankarray (CSRBankArray) +│ └─── csrbank_0* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ └─── csrbank_1* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstorage_4* (CSRStorage) +│ │ └─── csrstorage_5* (CSRStorage) +│ └─── csrbank_2* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstorage_4* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstorage_5* (CSRStorage) +│ │ └─── csrstorage_6* (CSRStorage) +│ │ └─── csrstorage_7* (CSRStorage) +│ │ └─── csrstorage_8* (CSRStorage) +│ │ └─── csrstatus_1* (CSRStatus) +│ │ └─── csrstorage_9* (CSRStorage) +│ │ └─── csrstorage_10* (CSRStorage) +│ │ └─── csrstorage_11* (CSRStorage) +│ │ └─── csrstorage_12* (CSRStorage) +│ │ └─── csrstatus_2* (CSRStatus) +│ │ └─── csrstorage_13* (CSRStorage) +│ │ └─── csrstorage_14* (CSRStorage) +│ │ └─── csrstorage_15* (CSRStorage) +│ │ └─── csrstorage_16* (CSRStorage) +│ │ └─── csrstatus_3* (CSRStatus) +└─── csr_interconnect (InterconnectShared) +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +* : Generated name. +[]: BlackBox. +*/ + //------------------------------------------------------------------------------ // Signals //------------------------------------------------------------------------------ -reg rst_1 = 1'd0; -wire sys_clk; -wire sys_rst; -wire sys4x_clk; -wire sys4x_dqs_clk; +wire [13:0] builder_adr; +reg [3:0] builder_bankmachine0_next_state = 4'd0; +reg [3:0] builder_bankmachine0_state = 4'd0; +reg [3:0] builder_bankmachine1_next_state = 4'd0; +reg [3:0] builder_bankmachine1_state = 4'd0; +reg [3:0] builder_bankmachine2_next_state = 4'd0; +reg [3:0] builder_bankmachine2_state = 4'd0; +reg [3:0] builder_bankmachine3_next_state = 4'd0; +reg [3:0] builder_bankmachine3_state = 4'd0; +reg [3:0] builder_bankmachine4_next_state = 4'd0; +reg [3:0] builder_bankmachine4_state = 4'd0; +reg [3:0] builder_bankmachine5_next_state = 4'd0; +reg [3:0] builder_bankmachine5_state = 4'd0; +reg [3:0] builder_bankmachine6_next_state = 4'd0; +reg [3:0] builder_bankmachine6_state = 4'd0; +reg [3:0] builder_bankmachine7_next_state = 4'd0; +reg [3:0] builder_bankmachine7_state = 4'd0; +wire builder_csrbank0_init_done0_r; +reg builder_csrbank0_init_done0_re = 1'd0; +wire builder_csrbank0_init_done0_w; +reg builder_csrbank0_init_done0_we = 1'd0; +wire builder_csrbank0_init_error0_r; +reg builder_csrbank0_init_error0_re = 1'd0; +wire builder_csrbank0_init_error0_w; +reg builder_csrbank0_init_error0_we = 1'd0; +wire builder_csrbank0_sel; +wire [1:0] builder_csrbank1_dly_sel0_r; +reg builder_csrbank1_dly_sel0_re = 1'd0; +wire [1:0] builder_csrbank1_dly_sel0_w; +reg builder_csrbank1_dly_sel0_we = 1'd0; +wire [4:0] builder_csrbank1_half_sys8x_taps0_r; +reg builder_csrbank1_half_sys8x_taps0_re = 1'd0; +wire [4:0] builder_csrbank1_half_sys8x_taps0_w; +reg builder_csrbank1_half_sys8x_taps0_we = 1'd0; +wire [1:0] builder_csrbank1_rdphase0_r; +reg builder_csrbank1_rdphase0_re = 1'd0; +wire [1:0] builder_csrbank1_rdphase0_w; +reg builder_csrbank1_rdphase0_we = 1'd0; +wire builder_csrbank1_rst0_r; +reg builder_csrbank1_rst0_re = 1'd0; +wire builder_csrbank1_rst0_w; +reg builder_csrbank1_rst0_we = 1'd0; +wire builder_csrbank1_sel; +wire builder_csrbank1_wlevel_en0_r; +reg builder_csrbank1_wlevel_en0_re = 1'd0; +wire builder_csrbank1_wlevel_en0_w; +reg builder_csrbank1_wlevel_en0_we = 1'd0; +wire [1:0] builder_csrbank1_wrphase0_r; +reg builder_csrbank1_wrphase0_re = 1'd0; +wire [1:0] builder_csrbank1_wrphase0_w; +reg builder_csrbank1_wrphase0_we = 1'd0; +wire [3:0] builder_csrbank2_dfii_control0_r; +reg builder_csrbank2_dfii_control0_re = 1'd0; +wire [3:0] builder_csrbank2_dfii_control0_w; +reg builder_csrbank2_dfii_control0_we = 1'd0; +wire [15:0] builder_csrbank2_dfii_pi0_address0_r; +reg builder_csrbank2_dfii_pi0_address0_re = 1'd0; +wire [15:0] builder_csrbank2_dfii_pi0_address0_w; +reg builder_csrbank2_dfii_pi0_address0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r; +reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w; +reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_command0_r; +reg builder_csrbank2_dfii_pi0_command0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_command0_w; +reg builder_csrbank2_dfii_pi0_command0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_rddata_r; +reg builder_csrbank2_dfii_pi0_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_rddata_w; +reg builder_csrbank2_dfii_pi0_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_r; +reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_w; +reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0; +wire [15:0] builder_csrbank2_dfii_pi1_address0_r; +reg builder_csrbank2_dfii_pi1_address0_re = 1'd0; +wire [15:0] builder_csrbank2_dfii_pi1_address0_w; +reg builder_csrbank2_dfii_pi1_address0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r; +reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w; +reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_command0_r; +reg builder_csrbank2_dfii_pi1_command0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_command0_w; +reg builder_csrbank2_dfii_pi1_command0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_rddata_r; +reg builder_csrbank2_dfii_pi1_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_rddata_w; +reg builder_csrbank2_dfii_pi1_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_r; +reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_w; +reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0; +wire [15:0] builder_csrbank2_dfii_pi2_address0_r; +reg builder_csrbank2_dfii_pi2_address0_re = 1'd0; +wire [15:0] builder_csrbank2_dfii_pi2_address0_w; +reg builder_csrbank2_dfii_pi2_address0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r; +reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w; +reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_command0_r; +reg builder_csrbank2_dfii_pi2_command0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_command0_w; +reg builder_csrbank2_dfii_pi2_command0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_rddata_r; +reg builder_csrbank2_dfii_pi2_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_rddata_w; +reg builder_csrbank2_dfii_pi2_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_r; +reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_w; +reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0; +wire [15:0] builder_csrbank2_dfii_pi3_address0_r; +reg builder_csrbank2_dfii_pi3_address0_re = 1'd0; +wire [15:0] builder_csrbank2_dfii_pi3_address0_w; +reg builder_csrbank2_dfii_pi3_address0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r; +reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w; +reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_command0_r; +reg builder_csrbank2_dfii_pi3_command0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_command0_w; +reg builder_csrbank2_dfii_pi3_command0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_rddata_r; +reg builder_csrbank2_dfii_pi3_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_rddata_w; +reg builder_csrbank2_dfii_pi3_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_r; +reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_w; +reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0; +wire builder_csrbank2_sel; +wire [31:0] builder_dat_r; +wire [31:0] builder_dat_w; +reg builder_interface0_ack = 1'd0; +wire [29:0] builder_interface0_adr; +wire [13:0] builder_interface0_bank_bus_adr; +reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface0_bank_bus_dat_w; +wire builder_interface0_bank_bus_we; +wire [1:0] builder_interface0_bte; +wire [2:0] builder_interface0_cti; +wire builder_interface0_cyc; +reg [31:0] builder_interface0_dat_r = 32'd0; +wire [31:0] builder_interface0_dat_w; +reg builder_interface0_err = 1'd0; +wire [3:0] builder_interface0_sel; +wire builder_interface0_stb; +wire builder_interface0_we; +reg [13:0] builder_interface1_adr = 14'd0; +reg [13:0] builder_interface1_adr_next_value1 = 14'd0; +reg builder_interface1_adr_next_value_ce1 = 1'd0; +wire [13:0] builder_interface1_bank_bus_adr; +reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface1_bank_bus_dat_w; +wire builder_interface1_bank_bus_we; +wire [31:0] builder_interface1_dat_r; +reg [31:0] builder_interface1_dat_w = 32'd0; +reg [31:0] builder_interface1_dat_w_next_value0 = 32'd0; +reg builder_interface1_dat_w_next_value_ce0 = 1'd0; +reg builder_interface1_we = 1'd0; +reg builder_interface1_we_next_value2 = 1'd0; +reg builder_interface1_we_next_value_ce2 = 1'd0; +wire [13:0] builder_interface2_bank_bus_adr; +reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface2_bank_bus_dat_w; +wire builder_interface2_bank_bus_we; +reg builder_locked0 = 1'd0; +reg builder_locked1 = 1'd0; +reg builder_locked2 = 1'd0; +reg builder_locked3 = 1'd0; +reg builder_locked4 = 1'd0; +reg builder_locked5 = 1'd0; +reg builder_locked6 = 1'd0; +reg builder_locked7 = 1'd0; +reg [3:0] builder_multiplexer_next_state = 4'd0; +reg [3:0] builder_multiplexer_state = 4'd0; +reg builder_new_master_rdata_valid0 = 1'd0; +reg builder_new_master_rdata_valid1 = 1'd0; +reg builder_new_master_rdata_valid2 = 1'd0; +reg builder_new_master_rdata_valid3 = 1'd0; +reg builder_new_master_rdata_valid4 = 1'd0; +reg builder_new_master_rdata_valid5 = 1'd0; +reg builder_new_master_rdata_valid6 = 1'd0; +reg builder_new_master_rdata_valid7 = 1'd0; +reg builder_new_master_rdata_valid8 = 1'd0; +reg builder_new_master_wdata_ready0 = 1'd0; +reg builder_new_master_wdata_ready1 = 1'd0; +reg [1:0] builder_next_state = 2'd0; +wire builder_pll_fb; +reg [1:0] builder_refresher_next_state = 2'd0; +reg [1:0] builder_refresher_state = 2'd0; +wire builder_reset0; +wire builder_reset1; +wire builder_reset2; +wire builder_reset3; +wire builder_reset4; +wire builder_reset5; +wire builder_reset6; +wire builder_reset7; +reg builder_rhs_self0 = 1'd0; +reg [15:0] builder_rhs_self1 = 16'd0; +reg builder_rhs_self10 = 1'd0; +reg builder_rhs_self11 = 1'd0; +reg [22:0] builder_rhs_self12 = 23'd0; +reg builder_rhs_self13 = 1'd0; +reg builder_rhs_self14 = 1'd0; +reg [22:0] builder_rhs_self15 = 23'd0; +reg builder_rhs_self16 = 1'd0; +reg builder_rhs_self17 = 1'd0; +reg [22:0] builder_rhs_self18 = 23'd0; +reg builder_rhs_self19 = 1'd0; +reg [2:0] builder_rhs_self2 = 3'd0; +reg builder_rhs_self20 = 1'd0; +reg [22:0] builder_rhs_self21 = 23'd0; +reg builder_rhs_self22 = 1'd0; +reg builder_rhs_self23 = 1'd0; +reg [22:0] builder_rhs_self24 = 23'd0; +reg builder_rhs_self25 = 1'd0; +reg builder_rhs_self26 = 1'd0; +reg [22:0] builder_rhs_self27 = 23'd0; +reg builder_rhs_self28 = 1'd0; +reg builder_rhs_self29 = 1'd0; +reg builder_rhs_self3 = 1'd0; +reg [22:0] builder_rhs_self30 = 23'd0; +reg builder_rhs_self31 = 1'd0; +reg builder_rhs_self32 = 1'd0; +reg [22:0] builder_rhs_self33 = 23'd0; +reg builder_rhs_self34 = 1'd0; +reg builder_rhs_self35 = 1'd0; +reg builder_rhs_self4 = 1'd0; +reg builder_rhs_self5 = 1'd0; +reg builder_rhs_self6 = 1'd0; +reg [15:0] builder_rhs_self7 = 16'd0; +reg [2:0] builder_rhs_self8 = 3'd0; +reg builder_rhs_self9 = 1'd0; +wire builder_roundrobin0_ce; +wire builder_roundrobin0_grant; +wire builder_roundrobin0_request; +wire builder_roundrobin1_ce; +wire builder_roundrobin1_grant; +wire builder_roundrobin1_request; +wire builder_roundrobin2_ce; +wire builder_roundrobin2_grant; +wire builder_roundrobin2_request; +wire builder_roundrobin3_ce; +wire builder_roundrobin3_grant; +wire builder_roundrobin3_request; +wire builder_roundrobin4_ce; +wire builder_roundrobin4_grant; +wire builder_roundrobin4_request; +wire builder_roundrobin5_ce; +wire builder_roundrobin5_grant; +wire builder_roundrobin5_request; +wire builder_roundrobin6_ce; +wire builder_roundrobin6_grant; +wire builder_roundrobin6_request; +wire builder_roundrobin7_ce; +wire builder_roundrobin7_grant; +wire builder_roundrobin7_request; +reg [2:0] builder_self0 = 3'd0; +reg [15:0] builder_self1 = 16'd0; +reg builder_self10 = 1'd0; +reg builder_self11 = 1'd0; +reg builder_self12 = 1'd0; +reg builder_self13 = 1'd0; +reg [2:0] builder_self14 = 3'd0; +reg [15:0] builder_self15 = 16'd0; +reg builder_self16 = 1'd0; +reg builder_self17 = 1'd0; +reg builder_self18 = 1'd0; +reg builder_self19 = 1'd0; +reg builder_self2 = 1'd0; +reg builder_self20 = 1'd0; +reg [2:0] builder_self21 = 3'd0; +reg [15:0] builder_self22 = 16'd0; +reg builder_self23 = 1'd0; +reg builder_self24 = 1'd0; +reg builder_self25 = 1'd0; +reg builder_self26 = 1'd0; +reg builder_self27 = 1'd0; +reg builder_self3 = 1'd0; +reg builder_self4 = 1'd0; +reg builder_self5 = 1'd0; +reg builder_self6 = 1'd0; +reg [2:0] builder_self7 = 3'd0; +reg [15:0] builder_self8 = 16'd0; +reg builder_self9 = 1'd0; +reg [1:0] builder_state = 2'd0; +reg builder_t_self0 = 1'd0; +reg builder_t_self1 = 1'd0; +reg builder_t_self2 = 1'd0; +reg builder_t_self3 = 1'd0; +reg builder_t_self4 = 1'd0; +reg builder_t_self5 = 1'd0; +wire builder_we; +wire builder_xilinxasyncresetsynchronizerimpl0_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl1_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl2_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl2_expr; +wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl3_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl3_expr; +wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta; wire iodelay_clk; wire iodelay_rst; -wire reset; -reg power_down = 1'd0; -wire locked; -wire clkin; -wire clkout0; -wire clkout_buf0; -wire clkout1; -wire clkout_buf1; -wire clkout2; -wire clkout_buf2; -wire clkout3; -wire clkout_buf3; -reg [3:0] reset_counter = 4'd15; -reg ic_reset = 1'd1; -reg a7ddrphy_rst_storage = 1'd0; -reg a7ddrphy_rst_re = 1'd0; -reg [1:0] a7ddrphy_dly_sel_storage = 2'd0; -reg a7ddrphy_dly_sel_re = 1'd0; -reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8; -reg a7ddrphy_half_sys8x_taps_re = 1'd0; -reg a7ddrphy_wlevel_en_storage = 1'd0; -reg a7ddrphy_wlevel_en_re = 1'd0; -reg a7ddrphy_wlevel_strobe_re = 1'd0; -wire a7ddrphy_wlevel_strobe_r; -reg a7ddrphy_wlevel_strobe_we = 1'd0; -reg a7ddrphy_wlevel_strobe_w = 1'd0; -reg a7ddrphy_rdly_dq_rst_re = 1'd0; -wire a7ddrphy_rdly_dq_rst_r; -reg a7ddrphy_rdly_dq_rst_we = 1'd0; -reg a7ddrphy_rdly_dq_rst_w = 1'd0; -reg a7ddrphy_rdly_dq_inc_re = 1'd0; -wire a7ddrphy_rdly_dq_inc_r; -reg a7ddrphy_rdly_dq_inc_we = 1'd0; -reg a7ddrphy_rdly_dq_inc_w = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; -wire a7ddrphy_rdly_dq_bitslip_rst_r; -reg a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_re = 1'd0; -wire a7ddrphy_rdly_dq_bitslip_r; -reg a7ddrphy_rdly_dq_bitslip_we = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_w = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; -wire a7ddrphy_wdly_dq_bitslip_rst_r; -reg a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_re = 1'd0; -wire a7ddrphy_wdly_dq_bitslip_r; -reg a7ddrphy_wdly_dq_bitslip_we = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_w = 1'd0; -reg [1:0] a7ddrphy_rdphase_storage = 2'd2; -reg a7ddrphy_rdphase_re = 1'd0; -reg [1:0] a7ddrphy_wrphase_storage = 2'd3; -reg a7ddrphy_wrphase_re = 1'd0; -wire [15:0] a7ddrphy_dfi_p0_address; -wire [2:0] a7ddrphy_dfi_p0_bank; -wire a7ddrphy_dfi_p0_cas_n; -wire a7ddrphy_dfi_p0_cs_n; -wire a7ddrphy_dfi_p0_ras_n; -wire a7ddrphy_dfi_p0_we_n; -wire a7ddrphy_dfi_p0_cke; -wire a7ddrphy_dfi_p0_odt; -wire a7ddrphy_dfi_p0_reset_n; -wire a7ddrphy_dfi_p0_act_n; -wire [31:0] a7ddrphy_dfi_p0_wrdata; -wire a7ddrphy_dfi_p0_wrdata_en; -wire [3:0] a7ddrphy_dfi_p0_wrdata_mask; -wire a7ddrphy_dfi_p0_rddata_en; -reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0; -wire a7ddrphy_dfi_p0_rddata_valid; -wire [15:0] a7ddrphy_dfi_p1_address; -wire [2:0] a7ddrphy_dfi_p1_bank; -wire a7ddrphy_dfi_p1_cas_n; -wire a7ddrphy_dfi_p1_cs_n; -wire a7ddrphy_dfi_p1_ras_n; -wire a7ddrphy_dfi_p1_we_n; -wire a7ddrphy_dfi_p1_cke; -wire a7ddrphy_dfi_p1_odt; -wire a7ddrphy_dfi_p1_reset_n; -wire a7ddrphy_dfi_p1_act_n; -wire [31:0] a7ddrphy_dfi_p1_wrdata; -wire a7ddrphy_dfi_p1_wrdata_en; -wire [3:0] a7ddrphy_dfi_p1_wrdata_mask; -wire a7ddrphy_dfi_p1_rddata_en; -reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0; -wire a7ddrphy_dfi_p1_rddata_valid; -wire [15:0] a7ddrphy_dfi_p2_address; -wire [2:0] a7ddrphy_dfi_p2_bank; -wire a7ddrphy_dfi_p2_cas_n; -wire a7ddrphy_dfi_p2_cs_n; -wire a7ddrphy_dfi_p2_ras_n; -wire a7ddrphy_dfi_p2_we_n; -wire a7ddrphy_dfi_p2_cke; -wire a7ddrphy_dfi_p2_odt; -wire a7ddrphy_dfi_p2_reset_n; -wire a7ddrphy_dfi_p2_act_n; -wire [31:0] a7ddrphy_dfi_p2_wrdata; -wire a7ddrphy_dfi_p2_wrdata_en; -wire [3:0] a7ddrphy_dfi_p2_wrdata_mask; -wire a7ddrphy_dfi_p2_rddata_en; -reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0; -wire a7ddrphy_dfi_p2_rddata_valid; -wire [15:0] a7ddrphy_dfi_p3_address; -wire [2:0] a7ddrphy_dfi_p3_bank; -wire a7ddrphy_dfi_p3_cas_n; -wire a7ddrphy_dfi_p3_cs_n; -wire a7ddrphy_dfi_p3_ras_n; -wire a7ddrphy_dfi_p3_we_n; -wire a7ddrphy_dfi_p3_cke; -wire a7ddrphy_dfi_p3_odt; -wire a7ddrphy_dfi_p3_reset_n; -wire a7ddrphy_dfi_p3_act_n; -wire [31:0] a7ddrphy_dfi_p3_wrdata; -wire a7ddrphy_dfi_p3_wrdata_en; -wire [3:0] a7ddrphy_dfi_p3_wrdata_mask; -wire a7ddrphy_dfi_p3_rddata_en; -reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0; -wire a7ddrphy_dfi_p3_rddata_valid; -wire a7ddrphy_sd_clk_se_nodelay; -wire [2:0] a7ddrphy_pads_ba; -reg a7ddrphy_dqs_oe = 1'd0; -wire a7ddrphy_dqs_preamble; -wire a7ddrphy_dqs_postamble; -wire a7ddrphy_dqs_oe_delay_tappeddelayline; -reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -reg a7ddrphy_dqspattern0 = 1'd0; -reg a7ddrphy_dqspattern1 = 1'd0; -reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0; -reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0; -wire a7ddrphy_dqs_o_no_delay0; -wire a7ddrphy_dqs_t0; -reg [7:0] a7ddrphy_bitslip00 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r0 = 16'd0; -wire a7ddrphy0; -wire a7ddrphy_dqs_o_no_delay1; -wire a7ddrphy_dqs_t1; -reg [7:0] a7ddrphy_bitslip10 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r0 = 16'd0; -wire a7ddrphy1; -reg [7:0] a7ddrphy_bitslip01 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r1 = 16'd0; -reg [7:0] a7ddrphy_bitslip11 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r1 = 16'd0; -wire a7ddrphy_dq_oe; -wire a7ddrphy_dq_oe_delay_tappeddelayline; -reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -wire a7ddrphy_dq_o_nodelay0; -wire a7ddrphy_dq_i_nodelay0; -wire a7ddrphy_dq_i_delayed0; -wire a7ddrphy_dq_t0; -reg [7:0] a7ddrphy_bitslip02 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value2 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r2 = 16'd0; -wire [7:0] a7ddrphy_bitslip03; -reg [7:0] a7ddrphy_bitslip04 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value3 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r3 = 16'd0; -wire a7ddrphy_dq_o_nodelay1; -wire a7ddrphy_dq_i_nodelay1; -wire a7ddrphy_dq_i_delayed1; -wire a7ddrphy_dq_t1; -reg [7:0] a7ddrphy_bitslip12 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value2 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r2 = 16'd0; -wire [7:0] a7ddrphy_bitslip13; -reg [7:0] a7ddrphy_bitslip14 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value3 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r3 = 16'd0; -wire a7ddrphy_dq_o_nodelay2; -wire a7ddrphy_dq_i_nodelay2; -wire a7ddrphy_dq_i_delayed2; -wire a7ddrphy_dq_t2; -reg [7:0] a7ddrphy_bitslip20 = 8'd0; -reg [2:0] a7ddrphy_bitslip2_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip2_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip21; -reg [7:0] a7ddrphy_bitslip22 = 8'd0; -reg [2:0] a7ddrphy_bitslip2_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip2_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay3; -wire a7ddrphy_dq_i_nodelay3; -wire a7ddrphy_dq_i_delayed3; -wire a7ddrphy_dq_t3; -reg [7:0] a7ddrphy_bitslip30 = 8'd0; -reg [2:0] a7ddrphy_bitslip3_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip3_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip31; -reg [7:0] a7ddrphy_bitslip32 = 8'd0; -reg [2:0] a7ddrphy_bitslip3_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip3_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay4; -wire a7ddrphy_dq_i_nodelay4; -wire a7ddrphy_dq_i_delayed4; -wire a7ddrphy_dq_t4; -reg [7:0] a7ddrphy_bitslip40 = 8'd0; -reg [2:0] a7ddrphy_bitslip4_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip4_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip41; -reg [7:0] a7ddrphy_bitslip42 = 8'd0; -reg [2:0] a7ddrphy_bitslip4_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip4_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay5; -wire a7ddrphy_dq_i_nodelay5; -wire a7ddrphy_dq_i_delayed5; -wire a7ddrphy_dq_t5; -reg [7:0] a7ddrphy_bitslip50 = 8'd0; -reg [2:0] a7ddrphy_bitslip5_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip5_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip51; -reg [7:0] a7ddrphy_bitslip52 = 8'd0; -reg [2:0] a7ddrphy_bitslip5_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip5_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay6; -wire a7ddrphy_dq_i_nodelay6; -wire a7ddrphy_dq_i_delayed6; -wire a7ddrphy_dq_t6; -reg [7:0] a7ddrphy_bitslip60 = 8'd0; -reg [2:0] a7ddrphy_bitslip6_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip6_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip61; -reg [7:0] a7ddrphy_bitslip62 = 8'd0; -reg [2:0] a7ddrphy_bitslip6_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip6_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay7; -wire a7ddrphy_dq_i_nodelay7; -wire a7ddrphy_dq_i_delayed7; -wire a7ddrphy_dq_t7; -reg [7:0] a7ddrphy_bitslip70 = 8'd0; -reg [2:0] a7ddrphy_bitslip7_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip7_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip71; -reg [7:0] a7ddrphy_bitslip72 = 8'd0; -reg [2:0] a7ddrphy_bitslip7_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip7_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay8; -wire a7ddrphy_dq_i_nodelay8; -wire a7ddrphy_dq_i_delayed8; -wire a7ddrphy_dq_t8; -reg [7:0] a7ddrphy_bitslip80 = 8'd0; -reg [2:0] a7ddrphy_bitslip8_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip8_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip81; -reg [7:0] a7ddrphy_bitslip82 = 8'd0; -reg [2:0] a7ddrphy_bitslip8_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip8_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay9; -wire a7ddrphy_dq_i_nodelay9; -wire a7ddrphy_dq_i_delayed9; -wire a7ddrphy_dq_t9; -reg [7:0] a7ddrphy_bitslip90 = 8'd0; -reg [2:0] a7ddrphy_bitslip9_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip9_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip91; -reg [7:0] a7ddrphy_bitslip92 = 8'd0; -reg [2:0] a7ddrphy_bitslip9_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip9_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay10; -wire a7ddrphy_dq_i_nodelay10; -wire a7ddrphy_dq_i_delayed10; -wire a7ddrphy_dq_t10; -reg [7:0] a7ddrphy_bitslip100 = 8'd0; -reg [2:0] a7ddrphy_bitslip10_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip10_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip101; -reg [7:0] a7ddrphy_bitslip102 = 8'd0; -reg [2:0] a7ddrphy_bitslip10_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip10_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay11; -wire a7ddrphy_dq_i_nodelay11; -wire a7ddrphy_dq_i_delayed11; -wire a7ddrphy_dq_t11; -reg [7:0] a7ddrphy_bitslip110 = 8'd0; -reg [2:0] a7ddrphy_bitslip11_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip11_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip111; -reg [7:0] a7ddrphy_bitslip112 = 8'd0; -reg [2:0] a7ddrphy_bitslip11_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip11_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay12; -wire a7ddrphy_dq_i_nodelay12; -wire a7ddrphy_dq_i_delayed12; -wire a7ddrphy_dq_t12; -reg [7:0] a7ddrphy_bitslip120 = 8'd0; -reg [2:0] a7ddrphy_bitslip12_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip12_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip121; -reg [7:0] a7ddrphy_bitslip122 = 8'd0; -reg [2:0] a7ddrphy_bitslip12_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip12_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay13; -wire a7ddrphy_dq_i_nodelay13; -wire a7ddrphy_dq_i_delayed13; -wire a7ddrphy_dq_t13; -reg [7:0] a7ddrphy_bitslip130 = 8'd0; -reg [2:0] a7ddrphy_bitslip13_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip13_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip131; -reg [7:0] a7ddrphy_bitslip132 = 8'd0; -reg [2:0] a7ddrphy_bitslip13_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip13_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay14; -wire a7ddrphy_dq_i_nodelay14; -wire a7ddrphy_dq_i_delayed14; -wire a7ddrphy_dq_t14; -reg [7:0] a7ddrphy_bitslip140 = 8'd0; -reg [2:0] a7ddrphy_bitslip14_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip14_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip141; -reg [7:0] a7ddrphy_bitslip142 = 8'd0; -reg [2:0] a7ddrphy_bitslip14_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip14_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay15; -wire a7ddrphy_dq_i_nodelay15; -wire a7ddrphy_dq_i_delayed15; -wire a7ddrphy_dq_t15; -reg [7:0] a7ddrphy_bitslip150 = 8'd0; -reg [2:0] a7ddrphy_bitslip15_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip15_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip151; -reg [7:0] a7ddrphy_bitslip152 = 8'd0; -reg [2:0] a7ddrphy_bitslip15_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip15_r1 = 16'd0; -reg a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; -reg a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; -reg a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; -reg a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; -wire [15:0] litedramcore_slave_p0_address; -wire [2:0] litedramcore_slave_p0_bank; -wire litedramcore_slave_p0_cas_n; -wire litedramcore_slave_p0_cs_n; -wire litedramcore_slave_p0_ras_n; -wire litedramcore_slave_p0_we_n; -wire litedramcore_slave_p0_cke; -wire litedramcore_slave_p0_odt; -wire litedramcore_slave_p0_reset_n; -wire litedramcore_slave_p0_act_n; -wire [31:0] litedramcore_slave_p0_wrdata; -wire litedramcore_slave_p0_wrdata_en; -wire [3:0] litedramcore_slave_p0_wrdata_mask; -wire litedramcore_slave_p0_rddata_en; -reg [31:0] litedramcore_slave_p0_rddata = 32'd0; -reg litedramcore_slave_p0_rddata_valid = 1'd0; -wire [15:0] litedramcore_slave_p1_address; -wire [2:0] litedramcore_slave_p1_bank; -wire litedramcore_slave_p1_cas_n; -wire litedramcore_slave_p1_cs_n; -wire litedramcore_slave_p1_ras_n; -wire litedramcore_slave_p1_we_n; -wire litedramcore_slave_p1_cke; -wire litedramcore_slave_p1_odt; -wire litedramcore_slave_p1_reset_n; -wire litedramcore_slave_p1_act_n; -wire [31:0] litedramcore_slave_p1_wrdata; -wire litedramcore_slave_p1_wrdata_en; -wire [3:0] litedramcore_slave_p1_wrdata_mask; -wire litedramcore_slave_p1_rddata_en; -reg [31:0] litedramcore_slave_p1_rddata = 32'd0; -reg litedramcore_slave_p1_rddata_valid = 1'd0; -wire [15:0] litedramcore_slave_p2_address; -wire [2:0] litedramcore_slave_p2_bank; -wire litedramcore_slave_p2_cas_n; -wire litedramcore_slave_p2_cs_n; -wire litedramcore_slave_p2_ras_n; -wire litedramcore_slave_p2_we_n; -wire litedramcore_slave_p2_cke; -wire litedramcore_slave_p2_odt; -wire litedramcore_slave_p2_reset_n; -wire litedramcore_slave_p2_act_n; -wire [31:0] litedramcore_slave_p2_wrdata; -wire litedramcore_slave_p2_wrdata_en; -wire [3:0] litedramcore_slave_p2_wrdata_mask; -wire litedramcore_slave_p2_rddata_en; -reg [31:0] litedramcore_slave_p2_rddata = 32'd0; -reg litedramcore_slave_p2_rddata_valid = 1'd0; -wire [15:0] litedramcore_slave_p3_address; -wire [2:0] litedramcore_slave_p3_bank; -wire litedramcore_slave_p3_cas_n; -wire litedramcore_slave_p3_cs_n; -wire litedramcore_slave_p3_ras_n; -wire litedramcore_slave_p3_we_n; -wire litedramcore_slave_p3_cke; -wire litedramcore_slave_p3_odt; -wire litedramcore_slave_p3_reset_n; -wire litedramcore_slave_p3_act_n; -wire [31:0] litedramcore_slave_p3_wrdata; -wire litedramcore_slave_p3_wrdata_en; -wire [3:0] litedramcore_slave_p3_wrdata_mask; -wire litedramcore_slave_p3_rddata_en; -reg [31:0] litedramcore_slave_p3_rddata = 32'd0; -reg litedramcore_slave_p3_rddata_valid = 1'd0; -reg [15:0] litedramcore_master_p0_address = 16'd0; -reg [2:0] litedramcore_master_p0_bank = 3'd0; -reg litedramcore_master_p0_cas_n = 1'd1; -reg litedramcore_master_p0_cs_n = 1'd1; -reg litedramcore_master_p0_ras_n = 1'd1; -reg litedramcore_master_p0_we_n = 1'd1; -reg litedramcore_master_p0_cke = 1'd0; -reg litedramcore_master_p0_odt = 1'd0; -reg litedramcore_master_p0_reset_n = 1'd0; -reg litedramcore_master_p0_act_n = 1'd1; -reg [31:0] litedramcore_master_p0_wrdata = 32'd0; -reg litedramcore_master_p0_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0; -reg litedramcore_master_p0_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p0_rddata; -wire litedramcore_master_p0_rddata_valid; -reg [15:0] litedramcore_master_p1_address = 16'd0; -reg [2:0] litedramcore_master_p1_bank = 3'd0; -reg litedramcore_master_p1_cas_n = 1'd1; -reg litedramcore_master_p1_cs_n = 1'd1; -reg litedramcore_master_p1_ras_n = 1'd1; -reg litedramcore_master_p1_we_n = 1'd1; -reg litedramcore_master_p1_cke = 1'd0; -reg litedramcore_master_p1_odt = 1'd0; -reg litedramcore_master_p1_reset_n = 1'd0; -reg litedramcore_master_p1_act_n = 1'd1; -reg [31:0] litedramcore_master_p1_wrdata = 32'd0; -reg litedramcore_master_p1_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0; -reg litedramcore_master_p1_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p1_rddata; -wire litedramcore_master_p1_rddata_valid; -reg [15:0] litedramcore_master_p2_address = 16'd0; -reg [2:0] litedramcore_master_p2_bank = 3'd0; -reg litedramcore_master_p2_cas_n = 1'd1; -reg litedramcore_master_p2_cs_n = 1'd1; -reg litedramcore_master_p2_ras_n = 1'd1; -reg litedramcore_master_p2_we_n = 1'd1; -reg litedramcore_master_p2_cke = 1'd0; -reg litedramcore_master_p2_odt = 1'd0; -reg litedramcore_master_p2_reset_n = 1'd0; -reg litedramcore_master_p2_act_n = 1'd1; -reg [31:0] litedramcore_master_p2_wrdata = 32'd0; -reg litedramcore_master_p2_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0; -reg litedramcore_master_p2_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p2_rddata; -wire litedramcore_master_p2_rddata_valid; -reg [15:0] litedramcore_master_p3_address = 16'd0; -reg [2:0] litedramcore_master_p3_bank = 3'd0; -reg litedramcore_master_p3_cas_n = 1'd1; -reg litedramcore_master_p3_cs_n = 1'd1; -reg litedramcore_master_p3_ras_n = 1'd1; -reg litedramcore_master_p3_we_n = 1'd1; -reg litedramcore_master_p3_cke = 1'd0; -reg litedramcore_master_p3_odt = 1'd0; -reg litedramcore_master_p3_reset_n = 1'd0; -reg litedramcore_master_p3_act_n = 1'd1; -reg [31:0] litedramcore_master_p3_wrdata = 32'd0; -reg litedramcore_master_p3_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0; -reg litedramcore_master_p3_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p3_rddata; -wire litedramcore_master_p3_rddata_valid; -wire [15:0] litedramcore_csr_dfi_p0_address; -wire [2:0] litedramcore_csr_dfi_p0_bank; -reg litedramcore_csr_dfi_p0_cas_n = 1'd1; -reg litedramcore_csr_dfi_p0_cs_n = 1'd1; -reg litedramcore_csr_dfi_p0_ras_n = 1'd1; -reg litedramcore_csr_dfi_p0_we_n = 1'd1; -wire litedramcore_csr_dfi_p0_cke; -wire litedramcore_csr_dfi_p0_odt; -wire litedramcore_csr_dfi_p0_reset_n; -reg litedramcore_csr_dfi_p0_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p0_wrdata; -wire litedramcore_csr_dfi_p0_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask; -wire litedramcore_csr_dfi_p0_rddata_en; -reg [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0; -reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0; -wire [15:0] litedramcore_csr_dfi_p1_address; -wire [2:0] litedramcore_csr_dfi_p1_bank; -reg litedramcore_csr_dfi_p1_cas_n = 1'd1; -reg litedramcore_csr_dfi_p1_cs_n = 1'd1; -reg litedramcore_csr_dfi_p1_ras_n = 1'd1; -reg litedramcore_csr_dfi_p1_we_n = 1'd1; -wire litedramcore_csr_dfi_p1_cke; -wire litedramcore_csr_dfi_p1_odt; -wire litedramcore_csr_dfi_p1_reset_n; -reg litedramcore_csr_dfi_p1_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p1_wrdata; -wire litedramcore_csr_dfi_p1_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask; -wire litedramcore_csr_dfi_p1_rddata_en; -reg [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0; -reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0; -wire [15:0] litedramcore_csr_dfi_p2_address; -wire [2:0] litedramcore_csr_dfi_p2_bank; -reg litedramcore_csr_dfi_p2_cas_n = 1'd1; -reg litedramcore_csr_dfi_p2_cs_n = 1'd1; -reg litedramcore_csr_dfi_p2_ras_n = 1'd1; -reg litedramcore_csr_dfi_p2_we_n = 1'd1; -wire litedramcore_csr_dfi_p2_cke; -wire litedramcore_csr_dfi_p2_odt; -wire litedramcore_csr_dfi_p2_reset_n; -reg litedramcore_csr_dfi_p2_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p2_wrdata; -wire litedramcore_csr_dfi_p2_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask; -wire litedramcore_csr_dfi_p2_rddata_en; -reg [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0; -reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0; -wire [15:0] litedramcore_csr_dfi_p3_address; -wire [2:0] litedramcore_csr_dfi_p3_bank; -reg litedramcore_csr_dfi_p3_cas_n = 1'd1; -reg litedramcore_csr_dfi_p3_cs_n = 1'd1; -reg litedramcore_csr_dfi_p3_ras_n = 1'd1; -reg litedramcore_csr_dfi_p3_we_n = 1'd1; -wire litedramcore_csr_dfi_p3_cke; -wire litedramcore_csr_dfi_p3_odt; -wire litedramcore_csr_dfi_p3_reset_n; -reg litedramcore_csr_dfi_p3_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p3_wrdata; -wire litedramcore_csr_dfi_p3_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask; -wire litedramcore_csr_dfi_p3_rddata_en; -reg [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0; -reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0; -reg [15:0] litedramcore_ext_dfi_p0_address = 16'd0; -reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0; -reg litedramcore_ext_dfi_p0_cas_n = 1'd1; -reg litedramcore_ext_dfi_p0_cs_n = 1'd1; -reg litedramcore_ext_dfi_p0_ras_n = 1'd1; -reg litedramcore_ext_dfi_p0_we_n = 1'd1; -reg litedramcore_ext_dfi_p0_cke = 1'd0; -reg litedramcore_ext_dfi_p0_odt = 1'd0; -reg litedramcore_ext_dfi_p0_reset_n = 1'd0; -reg litedramcore_ext_dfi_p0_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0; -reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p0_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0; -reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0; -reg [15:0] litedramcore_ext_dfi_p1_address = 16'd0; -reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0; -reg litedramcore_ext_dfi_p1_cas_n = 1'd1; -reg litedramcore_ext_dfi_p1_cs_n = 1'd1; -reg litedramcore_ext_dfi_p1_ras_n = 1'd1; -reg litedramcore_ext_dfi_p1_we_n = 1'd1; -reg litedramcore_ext_dfi_p1_cke = 1'd0; -reg litedramcore_ext_dfi_p1_odt = 1'd0; -reg litedramcore_ext_dfi_p1_reset_n = 1'd0; -reg litedramcore_ext_dfi_p1_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0; -reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p1_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0; -reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0; -reg [15:0] litedramcore_ext_dfi_p2_address = 16'd0; -reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0; -reg litedramcore_ext_dfi_p2_cas_n = 1'd1; -reg litedramcore_ext_dfi_p2_cs_n = 1'd1; -reg litedramcore_ext_dfi_p2_ras_n = 1'd1; -reg litedramcore_ext_dfi_p2_we_n = 1'd1; -reg litedramcore_ext_dfi_p2_cke = 1'd0; -reg litedramcore_ext_dfi_p2_odt = 1'd0; -reg litedramcore_ext_dfi_p2_reset_n = 1'd0; -reg litedramcore_ext_dfi_p2_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0; -reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p2_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0; -reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0; -reg [15:0] litedramcore_ext_dfi_p3_address = 16'd0; -reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0; -reg litedramcore_ext_dfi_p3_cas_n = 1'd1; -reg litedramcore_ext_dfi_p3_cs_n = 1'd1; -reg litedramcore_ext_dfi_p3_ras_n = 1'd1; -reg litedramcore_ext_dfi_p3_we_n = 1'd1; -reg litedramcore_ext_dfi_p3_cke = 1'd0; -reg litedramcore_ext_dfi_p3_odt = 1'd0; -reg litedramcore_ext_dfi_p3_reset_n = 1'd0; -reg litedramcore_ext_dfi_p3_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0; -reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p3_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0; -reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0; -reg litedramcore_ext_dfi_sel = 1'd0; -wire litedramcore_sel; -wire litedramcore_cke; -wire litedramcore_odt; -wire litedramcore_reset_n; -reg [3:0] litedramcore_storage = 4'd1; -reg litedramcore_re = 1'd0; -wire litedramcore_phaseinjector0_csrfield_cs; -wire litedramcore_phaseinjector0_csrfield_we; -wire litedramcore_phaseinjector0_csrfield_cas; -wire litedramcore_phaseinjector0_csrfield_ras; -wire litedramcore_phaseinjector0_csrfield_wren; -wire litedramcore_phaseinjector0_csrfield_rden; -reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; -reg litedramcore_phaseinjector0_command_re = 1'd0; -reg litedramcore_phaseinjector0_command_issue_re = 1'd0; -wire litedramcore_phaseinjector0_command_issue_r; -reg litedramcore_phaseinjector0_command_issue_we = 1'd0; -reg litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [15:0] litedramcore_phaseinjector0_address_storage = 16'd0; -reg litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0; -wire litedramcore_phaseinjector0_rddata_we; -reg litedramcore_phaseinjector0_rddata_re = 1'd0; -wire litedramcore_phaseinjector1_csrfield_cs; -wire litedramcore_phaseinjector1_csrfield_we; -wire litedramcore_phaseinjector1_csrfield_cas; -wire litedramcore_phaseinjector1_csrfield_ras; -wire litedramcore_phaseinjector1_csrfield_wren; -wire litedramcore_phaseinjector1_csrfield_rden; -reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0; -reg litedramcore_phaseinjector1_command_re = 1'd0; -reg litedramcore_phaseinjector1_command_issue_re = 1'd0; -wire litedramcore_phaseinjector1_command_issue_r; -reg litedramcore_phaseinjector1_command_issue_we = 1'd0; -reg litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [15:0] litedramcore_phaseinjector1_address_storage = 16'd0; -reg litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0; -wire litedramcore_phaseinjector1_rddata_we; -reg litedramcore_phaseinjector1_rddata_re = 1'd0; -wire litedramcore_phaseinjector2_csrfield_cs; -wire litedramcore_phaseinjector2_csrfield_we; -wire litedramcore_phaseinjector2_csrfield_cas; -wire litedramcore_phaseinjector2_csrfield_ras; -wire litedramcore_phaseinjector2_csrfield_wren; -wire litedramcore_phaseinjector2_csrfield_rden; -reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0; -reg litedramcore_phaseinjector2_command_re = 1'd0; -reg litedramcore_phaseinjector2_command_issue_re = 1'd0; -wire litedramcore_phaseinjector2_command_issue_r; -reg litedramcore_phaseinjector2_command_issue_we = 1'd0; -reg litedramcore_phaseinjector2_command_issue_w = 1'd0; -reg [15:0] litedramcore_phaseinjector2_address_storage = 16'd0; -reg litedramcore_phaseinjector2_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0; -reg litedramcore_phaseinjector2_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector2_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0; -wire litedramcore_phaseinjector2_rddata_we; -reg litedramcore_phaseinjector2_rddata_re = 1'd0; -wire litedramcore_phaseinjector3_csrfield_cs; -wire litedramcore_phaseinjector3_csrfield_we; -wire litedramcore_phaseinjector3_csrfield_cas; -wire litedramcore_phaseinjector3_csrfield_ras; -wire litedramcore_phaseinjector3_csrfield_wren; -wire litedramcore_phaseinjector3_csrfield_rden; -reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0; -reg litedramcore_phaseinjector3_command_re = 1'd0; -reg litedramcore_phaseinjector3_command_issue_re = 1'd0; -wire litedramcore_phaseinjector3_command_issue_r; -reg litedramcore_phaseinjector3_command_issue_we = 1'd0; -reg litedramcore_phaseinjector3_command_issue_w = 1'd0; -reg [15:0] litedramcore_phaseinjector3_address_storage = 16'd0; -reg litedramcore_phaseinjector3_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0; -reg litedramcore_phaseinjector3_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector3_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0; -wire litedramcore_phaseinjector3_rddata_we; -reg litedramcore_phaseinjector3_rddata_re = 1'd0; -wire litedramcore_interface_bank0_valid; -wire litedramcore_interface_bank0_ready; -wire litedramcore_interface_bank0_we; -wire [22:0] litedramcore_interface_bank0_addr; -wire litedramcore_interface_bank0_lock; -wire litedramcore_interface_bank0_wdata_ready; -wire litedramcore_interface_bank0_rdata_valid; -wire litedramcore_interface_bank1_valid; -wire litedramcore_interface_bank1_ready; -wire litedramcore_interface_bank1_we; -wire [22:0] litedramcore_interface_bank1_addr; -wire litedramcore_interface_bank1_lock; -wire litedramcore_interface_bank1_wdata_ready; -wire litedramcore_interface_bank1_rdata_valid; -wire litedramcore_interface_bank2_valid; -wire litedramcore_interface_bank2_ready; -wire litedramcore_interface_bank2_we; -wire [22:0] litedramcore_interface_bank2_addr; -wire litedramcore_interface_bank2_lock; -wire litedramcore_interface_bank2_wdata_ready; -wire litedramcore_interface_bank2_rdata_valid; -wire litedramcore_interface_bank3_valid; -wire litedramcore_interface_bank3_ready; -wire litedramcore_interface_bank3_we; -wire [22:0] litedramcore_interface_bank3_addr; -wire litedramcore_interface_bank3_lock; -wire litedramcore_interface_bank3_wdata_ready; -wire litedramcore_interface_bank3_rdata_valid; -wire litedramcore_interface_bank4_valid; -wire litedramcore_interface_bank4_ready; -wire litedramcore_interface_bank4_we; -wire [22:0] litedramcore_interface_bank4_addr; -wire litedramcore_interface_bank4_lock; -wire litedramcore_interface_bank4_wdata_ready; -wire litedramcore_interface_bank4_rdata_valid; -wire litedramcore_interface_bank5_valid; -wire litedramcore_interface_bank5_ready; -wire litedramcore_interface_bank5_we; -wire [22:0] litedramcore_interface_bank5_addr; -wire litedramcore_interface_bank5_lock; -wire litedramcore_interface_bank5_wdata_ready; -wire litedramcore_interface_bank5_rdata_valid; -wire litedramcore_interface_bank6_valid; -wire litedramcore_interface_bank6_ready; -wire litedramcore_interface_bank6_we; -wire [22:0] litedramcore_interface_bank6_addr; -wire litedramcore_interface_bank6_lock; -wire litedramcore_interface_bank6_wdata_ready; -wire litedramcore_interface_bank6_rdata_valid; -wire litedramcore_interface_bank7_valid; -wire litedramcore_interface_bank7_ready; -wire litedramcore_interface_bank7_we; -wire [22:0] litedramcore_interface_bank7_addr; -wire litedramcore_interface_bank7_lock; -wire litedramcore_interface_bank7_wdata_ready; -wire litedramcore_interface_bank7_rdata_valid; -reg [127:0] litedramcore_interface_wdata = 128'd0; -reg [15:0] litedramcore_interface_wdata_we = 16'd0; -wire [127:0] litedramcore_interface_rdata; -reg [15:0] litedramcore_dfi_p0_address = 16'd0; -reg [2:0] litedramcore_dfi_p0_bank = 3'd0; -reg litedramcore_dfi_p0_cas_n = 1'd1; -reg litedramcore_dfi_p0_cs_n = 1'd1; -reg litedramcore_dfi_p0_ras_n = 1'd1; -reg litedramcore_dfi_p0_we_n = 1'd1; -wire litedramcore_dfi_p0_cke; -wire litedramcore_dfi_p0_odt; -wire litedramcore_dfi_p0_reset_n; -reg litedramcore_dfi_p0_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p0_wrdata; -reg litedramcore_dfi_p0_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p0_wrdata_mask; -reg litedramcore_dfi_p0_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p0_rddata; -wire litedramcore_dfi_p0_rddata_valid; -reg [15:0] litedramcore_dfi_p1_address = 16'd0; -reg [2:0] litedramcore_dfi_p1_bank = 3'd0; -reg litedramcore_dfi_p1_cas_n = 1'd1; -reg litedramcore_dfi_p1_cs_n = 1'd1; -reg litedramcore_dfi_p1_ras_n = 1'd1; -reg litedramcore_dfi_p1_we_n = 1'd1; -wire litedramcore_dfi_p1_cke; -wire litedramcore_dfi_p1_odt; -wire litedramcore_dfi_p1_reset_n; -reg litedramcore_dfi_p1_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p1_wrdata; -reg litedramcore_dfi_p1_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p1_wrdata_mask; -reg litedramcore_dfi_p1_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p1_rddata; -wire litedramcore_dfi_p1_rddata_valid; -reg [15:0] litedramcore_dfi_p2_address = 16'd0; -reg [2:0] litedramcore_dfi_p2_bank = 3'd0; -reg litedramcore_dfi_p2_cas_n = 1'd1; -reg litedramcore_dfi_p2_cs_n = 1'd1; -reg litedramcore_dfi_p2_ras_n = 1'd1; -reg litedramcore_dfi_p2_we_n = 1'd1; -wire litedramcore_dfi_p2_cke; -wire litedramcore_dfi_p2_odt; -wire litedramcore_dfi_p2_reset_n; -reg litedramcore_dfi_p2_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p2_wrdata; -reg litedramcore_dfi_p2_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p2_wrdata_mask; -reg litedramcore_dfi_p2_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p2_rddata; -wire litedramcore_dfi_p2_rddata_valid; -reg [15:0] litedramcore_dfi_p3_address = 16'd0; -reg [2:0] litedramcore_dfi_p3_bank = 3'd0; -reg litedramcore_dfi_p3_cas_n = 1'd1; -reg litedramcore_dfi_p3_cs_n = 1'd1; -reg litedramcore_dfi_p3_ras_n = 1'd1; -reg litedramcore_dfi_p3_we_n = 1'd1; -wire litedramcore_dfi_p3_cke; -wire litedramcore_dfi_p3_odt; -wire litedramcore_dfi_p3_reset_n; -reg litedramcore_dfi_p3_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p3_wrdata; -reg litedramcore_dfi_p3_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p3_wrdata_mask; -reg litedramcore_dfi_p3_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p3_rddata; -wire litedramcore_dfi_p3_rddata_valid; -reg litedramcore_cmd_valid = 1'd0; -reg litedramcore_cmd_ready = 1'd0; -reg litedramcore_cmd_last = 1'd0; -reg [15:0] litedramcore_cmd_payload_a = 16'd0; -reg [2:0] litedramcore_cmd_payload_ba = 3'd0; -reg litedramcore_cmd_payload_cas = 1'd0; -reg litedramcore_cmd_payload_ras = 1'd0; -reg litedramcore_cmd_payload_we = 1'd0; -reg litedramcore_cmd_payload_is_read = 1'd0; -reg litedramcore_cmd_payload_is_write = 1'd0; -wire litedramcore_wants_refresh; -wire litedramcore_wants_zqcs; -wire litedramcore_timer_wait; -wire litedramcore_timer_done0; -wire [9:0] litedramcore_timer_count0; -wire litedramcore_timer_done1; -reg [9:0] litedramcore_timer_count1 = 10'd781; -wire litedramcore_postponer_req_i; -reg litedramcore_postponer_req_o = 1'd0; -reg litedramcore_postponer_count = 1'd0; -reg litedramcore_sequencer_start0 = 1'd0; -wire litedramcore_sequencer_done0; -wire litedramcore_sequencer_start1; -reg litedramcore_sequencer_done1 = 1'd0; -reg [6:0] litedramcore_sequencer_counter = 7'd0; -reg litedramcore_sequencer_count = 1'd0; -wire litedramcore_zqcs_timer_wait; -wire litedramcore_zqcs_timer_done0; -wire [26:0] litedramcore_zqcs_timer_count0; -wire litedramcore_zqcs_timer_done1; -reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999; -reg litedramcore_zqcs_executer_start = 1'd0; -reg litedramcore_zqcs_executer_done = 1'd0; -reg [4:0] litedramcore_zqcs_executer_counter = 5'd0; -wire litedramcore_bankmachine0_req_valid; -wire litedramcore_bankmachine0_req_ready; -wire litedramcore_bankmachine0_req_we; -wire [22:0] litedramcore_bankmachine0_req_addr; -wire litedramcore_bankmachine0_req_lock; -reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine0_refresh_req; -reg litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg litedramcore_bankmachine0_cmd_valid = 1'd0; -reg litedramcore_bankmachine0_cmd_ready = 1'd0; -reg [15:0] litedramcore_bankmachine0_cmd_payload_a = 16'd0; -wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; -reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine0_auto_precharge = 1'd0; -wire litedramcore_bankmachine0_sink_valid; -wire litedramcore_bankmachine0_sink_ready; -reg litedramcore_bankmachine0_sink_first = 1'd0; -reg litedramcore_bankmachine0_sink_last = 1'd0; -wire litedramcore_bankmachine0_sink_payload_we; -wire [22:0] litedramcore_bankmachine0_sink_payload_addr; -wire litedramcore_bankmachine0_source_valid; -wire litedramcore_bankmachine0_source_ready; -wire litedramcore_bankmachine0_source_first; -wire litedramcore_bankmachine0_source_last; -wire litedramcore_bankmachine0_source_payload_we; -wire [22:0] litedramcore_bankmachine0_source_payload_addr; -wire litedramcore_bankmachine0_syncfifo0_we; -wire litedramcore_bankmachine0_syncfifo0_writable; -wire litedramcore_bankmachine0_syncfifo0_re; -wire litedramcore_bankmachine0_syncfifo0_readable; -wire [25:0] litedramcore_bankmachine0_syncfifo0_din; -wire [25:0] litedramcore_bankmachine0_syncfifo0_dout; -reg [4:0] litedramcore_bankmachine0_level = 5'd0; -reg litedramcore_bankmachine0_replace = 1'd0; -reg [3:0] litedramcore_bankmachine0_produce = 4'd0; -reg [3:0] litedramcore_bankmachine0_consume = 4'd0; -reg [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0; -wire [25:0] litedramcore_bankmachine0_wrport_dat_r; -wire litedramcore_bankmachine0_wrport_we; -wire [25:0] litedramcore_bankmachine0_wrport_dat_w; -wire litedramcore_bankmachine0_do_read; -wire [3:0] litedramcore_bankmachine0_rdport_adr; -wire [25:0] litedramcore_bankmachine0_rdport_dat_r; -wire litedramcore_bankmachine0_fifo_in_payload_we; -wire [22:0] litedramcore_bankmachine0_fifo_in_payload_addr; -wire litedramcore_bankmachine0_fifo_in_first; -wire litedramcore_bankmachine0_fifo_in_last; -wire litedramcore_bankmachine0_fifo_out_payload_we; -wire [22:0] litedramcore_bankmachine0_fifo_out_payload_addr; -wire litedramcore_bankmachine0_fifo_out_first; -wire litedramcore_bankmachine0_fifo_out_last; -wire litedramcore_bankmachine0_sink_sink_valid; -wire litedramcore_bankmachine0_sink_sink_ready; -wire litedramcore_bankmachine0_sink_sink_first; -wire litedramcore_bankmachine0_sink_sink_last; -wire litedramcore_bankmachine0_sink_sink_payload_we; -wire [22:0] litedramcore_bankmachine0_sink_sink_payload_addr; -wire litedramcore_bankmachine0_source_source_valid; -wire litedramcore_bankmachine0_source_source_ready; -wire litedramcore_bankmachine0_source_source_first; -wire litedramcore_bankmachine0_source_source_last; -wire litedramcore_bankmachine0_source_source_payload_we; -wire [22:0] litedramcore_bankmachine0_source_source_payload_addr; -wire litedramcore_bankmachine0_pipe_valid_sink_valid; -wire litedramcore_bankmachine0_pipe_valid_sink_ready; -wire litedramcore_bankmachine0_pipe_valid_sink_first; -wire litedramcore_bankmachine0_pipe_valid_sink_last; -wire litedramcore_bankmachine0_pipe_valid_sink_payload_we; -wire [22:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine0_pipe_valid_source_ready; -reg litedramcore_bankmachine0_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine0_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; -reg [22:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 23'd0; -reg [15:0] litedramcore_bankmachine0_row = 16'd0; -reg litedramcore_bankmachine0_row_opened = 1'd0; -wire litedramcore_bankmachine0_row_hit; -reg litedramcore_bankmachine0_row_open = 1'd0; -reg litedramcore_bankmachine0_row_close = 1'd0; -reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine0_twtpcon_valid; +wire main_a7ddrphy0; +wire main_a7ddrphy1; +reg [7:0] main_a7ddrphy_bitslip00 = 8'd0; +reg [7:0] main_a7ddrphy_bitslip01 = 8'd0; +reg [7:0] main_a7ddrphy_bitslip02 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip03; +reg [7:0] main_a7ddrphy_bitslip04 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip10 = 8'd0; +reg [7:0] main_a7ddrphy_bitslip100 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip101; +reg [7:0] main_a7ddrphy_bitslip102 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip11 = 8'd0; +reg [7:0] main_a7ddrphy_bitslip110 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip111; +reg [7:0] main_a7ddrphy_bitslip112 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip12 = 8'd0; +reg [7:0] main_a7ddrphy_bitslip120 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip121; +reg [7:0] main_a7ddrphy_bitslip122 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7; +wire [7:0] main_a7ddrphy_bitslip13; +reg [7:0] main_a7ddrphy_bitslip130 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip131; +reg [7:0] main_a7ddrphy_bitslip132 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip14 = 8'd0; +reg [7:0] main_a7ddrphy_bitslip140 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip141; +reg [7:0] main_a7ddrphy_bitslip142 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip150 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip151; +reg [7:0] main_a7ddrphy_bitslip152 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip20 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip21; +reg [7:0] main_a7ddrphy_bitslip22 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip30 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip31; +reg [7:0] main_a7ddrphy_bitslip32 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip40 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip41; +reg [7:0] main_a7ddrphy_bitslip42 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip50 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip51; +reg [7:0] main_a7ddrphy_bitslip52 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip60 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip61; +reg [7:0] main_a7ddrphy_bitslip62 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip70 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip71; +reg [7:0] main_a7ddrphy_bitslip72 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip80 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip81; +reg [7:0] main_a7ddrphy_bitslip82 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip90 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip91; +reg [7:0] main_a7ddrphy_bitslip92 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7; +wire main_a7ddrphy_dfi_p0_act_n; +wire [15:0] main_a7ddrphy_dfi_p0_address; +wire [2:0] main_a7ddrphy_dfi_p0_bank; +wire main_a7ddrphy_dfi_p0_cas_n; +wire main_a7ddrphy_dfi_p0_cke; +wire main_a7ddrphy_dfi_p0_cs_n; +wire main_a7ddrphy_dfi_p0_odt; +wire main_a7ddrphy_dfi_p0_ras_n; +reg [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0; +wire main_a7ddrphy_dfi_p0_rddata_en; +wire main_a7ddrphy_dfi_p0_rddata_valid; +wire main_a7ddrphy_dfi_p0_reset_n; +wire main_a7ddrphy_dfi_p0_we_n; +wire [31:0] main_a7ddrphy_dfi_p0_wrdata; +wire main_a7ddrphy_dfi_p0_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p0_wrdata_mask; +wire main_a7ddrphy_dfi_p1_act_n; +wire [15:0] main_a7ddrphy_dfi_p1_address; +wire [2:0] main_a7ddrphy_dfi_p1_bank; +wire main_a7ddrphy_dfi_p1_cas_n; +wire main_a7ddrphy_dfi_p1_cke; +wire main_a7ddrphy_dfi_p1_cs_n; +wire main_a7ddrphy_dfi_p1_odt; +wire main_a7ddrphy_dfi_p1_ras_n; +reg [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0; +wire main_a7ddrphy_dfi_p1_rddata_en; +wire main_a7ddrphy_dfi_p1_rddata_valid; +wire main_a7ddrphy_dfi_p1_reset_n; +wire main_a7ddrphy_dfi_p1_we_n; +wire [31:0] main_a7ddrphy_dfi_p1_wrdata; +wire main_a7ddrphy_dfi_p1_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p1_wrdata_mask; +wire main_a7ddrphy_dfi_p2_act_n; +wire [15:0] main_a7ddrphy_dfi_p2_address; +wire [2:0] main_a7ddrphy_dfi_p2_bank; +wire main_a7ddrphy_dfi_p2_cas_n; +wire main_a7ddrphy_dfi_p2_cke; +wire main_a7ddrphy_dfi_p2_cs_n; +wire main_a7ddrphy_dfi_p2_odt; +wire main_a7ddrphy_dfi_p2_ras_n; +reg [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0; +wire main_a7ddrphy_dfi_p2_rddata_en; +wire main_a7ddrphy_dfi_p2_rddata_valid; +wire main_a7ddrphy_dfi_p2_reset_n; +wire main_a7ddrphy_dfi_p2_we_n; +wire [31:0] main_a7ddrphy_dfi_p2_wrdata; +wire main_a7ddrphy_dfi_p2_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p2_wrdata_mask; +wire main_a7ddrphy_dfi_p3_act_n; +wire [15:0] main_a7ddrphy_dfi_p3_address; +wire [2:0] main_a7ddrphy_dfi_p3_bank; +wire main_a7ddrphy_dfi_p3_cas_n; +wire main_a7ddrphy_dfi_p3_cke; +wire main_a7ddrphy_dfi_p3_cs_n; +wire main_a7ddrphy_dfi_p3_odt; +wire main_a7ddrphy_dfi_p3_ras_n; +reg [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0; +wire main_a7ddrphy_dfi_p3_rddata_en; +wire main_a7ddrphy_dfi_p3_rddata_valid; +wire main_a7ddrphy_dfi_p3_reset_n; +wire main_a7ddrphy_dfi_p3_we_n; +wire [31:0] main_a7ddrphy_dfi_p3_wrdata; +wire main_a7ddrphy_dfi_p3_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p3_wrdata_mask; +reg main_a7ddrphy_dly_sel_re = 1'd0; +reg [1:0] main_a7ddrphy_dly_sel_storage = 2'd0; +wire main_a7ddrphy_dq_i_delayed0; +wire main_a7ddrphy_dq_i_delayed1; +wire main_a7ddrphy_dq_i_delayed10; +wire main_a7ddrphy_dq_i_delayed11; +wire main_a7ddrphy_dq_i_delayed12; +wire main_a7ddrphy_dq_i_delayed13; +wire main_a7ddrphy_dq_i_delayed14; +wire main_a7ddrphy_dq_i_delayed15; +wire main_a7ddrphy_dq_i_delayed2; +wire main_a7ddrphy_dq_i_delayed3; +wire main_a7ddrphy_dq_i_delayed4; +wire main_a7ddrphy_dq_i_delayed5; +wire main_a7ddrphy_dq_i_delayed6; +wire main_a7ddrphy_dq_i_delayed7; +wire main_a7ddrphy_dq_i_delayed8; +wire main_a7ddrphy_dq_i_delayed9; +wire main_a7ddrphy_dq_i_nodelay0; +wire main_a7ddrphy_dq_i_nodelay1; +wire main_a7ddrphy_dq_i_nodelay10; +wire main_a7ddrphy_dq_i_nodelay11; +wire main_a7ddrphy_dq_i_nodelay12; +wire main_a7ddrphy_dq_i_nodelay13; +wire main_a7ddrphy_dq_i_nodelay14; +wire main_a7ddrphy_dq_i_nodelay15; +wire main_a7ddrphy_dq_i_nodelay2; +wire main_a7ddrphy_dq_i_nodelay3; +wire main_a7ddrphy_dq_i_nodelay4; +wire main_a7ddrphy_dq_i_nodelay5; +wire main_a7ddrphy_dq_i_nodelay6; +wire main_a7ddrphy_dq_i_nodelay7; +wire main_a7ddrphy_dq_i_nodelay8; +wire main_a7ddrphy_dq_i_nodelay9; +wire main_a7ddrphy_dq_o_nodelay0; +wire main_a7ddrphy_dq_o_nodelay1; +wire main_a7ddrphy_dq_o_nodelay10; +wire main_a7ddrphy_dq_o_nodelay11; +wire main_a7ddrphy_dq_o_nodelay12; +wire main_a7ddrphy_dq_o_nodelay13; +wire main_a7ddrphy_dq_o_nodelay14; +wire main_a7ddrphy_dq_o_nodelay15; +wire main_a7ddrphy_dq_o_nodelay2; +wire main_a7ddrphy_dq_o_nodelay3; +wire main_a7ddrphy_dq_o_nodelay4; +wire main_a7ddrphy_dq_o_nodelay5; +wire main_a7ddrphy_dq_o_nodelay6; +wire main_a7ddrphy_dq_o_nodelay7; +wire main_a7ddrphy_dq_o_nodelay8; +wire main_a7ddrphy_dq_o_nodelay9; +wire main_a7ddrphy_dq_oe; +wire main_a7ddrphy_dq_oe_delay_tappeddelayline; +reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +wire main_a7ddrphy_dq_t0; +wire main_a7ddrphy_dq_t1; +wire main_a7ddrphy_dq_t10; +wire main_a7ddrphy_dq_t11; +wire main_a7ddrphy_dq_t12; +wire main_a7ddrphy_dq_t13; +wire main_a7ddrphy_dq_t14; +wire main_a7ddrphy_dq_t15; +wire main_a7ddrphy_dq_t2; +wire main_a7ddrphy_dq_t3; +wire main_a7ddrphy_dq_t4; +wire main_a7ddrphy_dq_t5; +wire main_a7ddrphy_dq_t6; +wire main_a7ddrphy_dq_t7; +wire main_a7ddrphy_dq_t8; +wire main_a7ddrphy_dq_t9; +wire main_a7ddrphy_dqs_o_no_delay0; +wire main_a7ddrphy_dqs_o_no_delay1; +reg main_a7ddrphy_dqs_oe = 1'd0; +wire main_a7ddrphy_dqs_oe_delay_tappeddelayline; +reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +wire main_a7ddrphy_dqs_postamble; +wire main_a7ddrphy_dqs_preamble; +wire main_a7ddrphy_dqs_t0; +wire main_a7ddrphy_dqs_t1; +reg main_a7ddrphy_dqspattern0 = 1'd0; +reg main_a7ddrphy_dqspattern1 = 1'd0; +reg [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0; +reg [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0; +reg main_a7ddrphy_half_sys8x_taps_re = 1'd0; +reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8; +wire [2:0] main_a7ddrphy_pads_ba; +reg main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; +wire main_a7ddrphy_rdly_dq_bitslip_r; +reg main_a7ddrphy_rdly_dq_bitslip_re = 1'd0; +wire main_a7ddrphy_rdly_dq_bitslip_rst_r; +reg main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_w = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_we = 1'd0; +wire main_a7ddrphy_rdly_dq_inc_r; +reg main_a7ddrphy_rdly_dq_inc_re = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_w = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_we = 1'd0; +wire main_a7ddrphy_rdly_dq_rst_r; +reg main_a7ddrphy_rdly_dq_rst_re = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_w = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_we = 1'd0; +reg main_a7ddrphy_rdphase_re = 1'd0; +reg [1:0] main_a7ddrphy_rdphase_storage = 2'd2; +reg main_a7ddrphy_rst_re = 1'd0; +reg main_a7ddrphy_rst_storage = 1'd0; +wire main_a7ddrphy_sd_clk_se_nodelay; +wire main_a7ddrphy_wdly_dq_bitslip_r; +reg main_a7ddrphy_wdly_dq_bitslip_re = 1'd0; +wire main_a7ddrphy_wdly_dq_bitslip_rst_r; +reg main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_w = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_we = 1'd0; +reg main_a7ddrphy_wlevel_en_re = 1'd0; +reg main_a7ddrphy_wlevel_en_storage = 1'd0; +wire main_a7ddrphy_wlevel_strobe_r; +reg main_a7ddrphy_wlevel_strobe_re = 1'd0; +reg main_a7ddrphy_wlevel_strobe_w = 1'd0; +reg main_a7ddrphy_wlevel_strobe_we = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +reg main_a7ddrphy_wrphase_re = 1'd0; +reg [1:0] main_a7ddrphy_wrphase_storage = 2'd3; +wire main_clkin; +wire main_clkout0; +wire main_clkout1; +wire main_clkout2; +wire main_clkout3; +wire main_clkout_buf0; +wire main_clkout_buf1; +wire main_clkout_buf2; +wire main_clkout_buf3; +reg main_ic_reset = 1'd1; +reg main_init_done_re = 1'd0; +reg main_init_done_storage = 1'd0; +reg main_init_error_re = 1'd0; +reg main_init_error_storage = 1'd0; +reg main_litedramcore_bankmachine0_auto_precharge = 1'd0; +reg [15:0] main_litedramcore_bankmachine0_cmd_payload_a = 16'd0; +wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba; +reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine0_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine0_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine0_consume = 4'd0; +wire main_litedramcore_bankmachine0_do_read; +wire main_litedramcore_bankmachine0_fifo_in_first; +wire main_litedramcore_bankmachine0_fifo_in_last; +wire [22:0] main_litedramcore_bankmachine0_fifo_in_payload_addr; +wire main_litedramcore_bankmachine0_fifo_in_payload_we; +wire main_litedramcore_bankmachine0_fifo_out_first; +wire main_litedramcore_bankmachine0_fifo_out_last; +wire [22:0] main_litedramcore_bankmachine0_fifo_out_payload_addr; +wire main_litedramcore_bankmachine0_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine0_level = 5'd0; +wire main_litedramcore_bankmachine0_pipe_valid_sink_first; +wire main_litedramcore_bankmachine0_pipe_valid_sink_last; +wire [22:0] main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine0_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine0_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine0_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine0_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine0_pipe_valid_source_last = 1'd0; +reg [22:0] main_litedramcore_bankmachine0_pipe_valid_source_payload_addr = 23'd0; +reg main_litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine0_pipe_valid_source_ready; +reg main_litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine0_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine0_rdport_adr; +wire [25:0] main_litedramcore_bankmachine0_rdport_dat_r; +reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine0_refresh_req; +reg main_litedramcore_bankmachine0_replace = 1'd0; +wire [22:0] main_litedramcore_bankmachine0_req_addr; +wire main_litedramcore_bankmachine0_req_lock; +reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine0_req_ready; +wire main_litedramcore_bankmachine0_req_valid; +reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine0_req_we; +reg [15:0] main_litedramcore_bankmachine0_row = 16'd0; +reg main_litedramcore_bankmachine0_row_close = 1'd0; +reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine0_row_hit; +reg main_litedramcore_bankmachine0_row_open = 1'd0; +reg main_litedramcore_bankmachine0_row_opened = 1'd0; +reg main_litedramcore_bankmachine0_sink_first = 1'd0; +reg main_litedramcore_bankmachine0_sink_last = 1'd0; +wire [22:0] main_litedramcore_bankmachine0_sink_payload_addr; +wire main_litedramcore_bankmachine0_sink_payload_we; +wire main_litedramcore_bankmachine0_sink_ready; +wire main_litedramcore_bankmachine0_sink_sink_first; +wire main_litedramcore_bankmachine0_sink_sink_last; +wire [22:0] main_litedramcore_bankmachine0_sink_sink_payload_addr; +wire main_litedramcore_bankmachine0_sink_sink_payload_we; +wire main_litedramcore_bankmachine0_sink_sink_ready; +wire main_litedramcore_bankmachine0_sink_sink_valid; +wire main_litedramcore_bankmachine0_sink_valid; +wire main_litedramcore_bankmachine0_source_first; +wire main_litedramcore_bankmachine0_source_last; +wire [22:0] main_litedramcore_bankmachine0_source_payload_addr; +wire main_litedramcore_bankmachine0_source_payload_we; +wire main_litedramcore_bankmachine0_source_ready; +wire main_litedramcore_bankmachine0_source_source_first; +wire main_litedramcore_bankmachine0_source_source_last; +wire [22:0] main_litedramcore_bankmachine0_source_source_payload_addr; +wire main_litedramcore_bankmachine0_source_source_payload_we; +wire main_litedramcore_bankmachine0_source_source_ready; +wire main_litedramcore_bankmachine0_source_source_valid; +wire main_litedramcore_bankmachine0_source_valid; +wire [25:0] main_litedramcore_bankmachine0_syncfifo0_din; +wire [25:0] main_litedramcore_bankmachine0_syncfifo0_dout; +wire main_litedramcore_bankmachine0_syncfifo0_re; +wire main_litedramcore_bankmachine0_syncfifo0_readable; +wire main_litedramcore_bankmachine0_syncfifo0_we; +wire main_litedramcore_bankmachine0_syncfifo0_writable; +reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; -wire litedramcore_bankmachine0_trccon_valid; +reg main_litedramcore_bankmachine0_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine0_trascon_valid; +reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0; -wire litedramcore_bankmachine0_trascon_valid; +reg main_litedramcore_bankmachine0_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine0_trccon_valid; +reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine0_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0; -wire litedramcore_bankmachine1_req_valid; -wire litedramcore_bankmachine1_req_ready; -wire litedramcore_bankmachine1_req_we; -wire [22:0] litedramcore_bankmachine1_req_addr; -wire litedramcore_bankmachine1_req_lock; -reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine1_refresh_req; -reg litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg litedramcore_bankmachine1_cmd_valid = 1'd0; -reg litedramcore_bankmachine1_cmd_ready = 1'd0; -reg [15:0] litedramcore_bankmachine1_cmd_payload_a = 16'd0; -wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; -reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine1_auto_precharge = 1'd0; -wire litedramcore_bankmachine1_sink_valid; -wire litedramcore_bankmachine1_sink_ready; -reg litedramcore_bankmachine1_sink_first = 1'd0; -reg litedramcore_bankmachine1_sink_last = 1'd0; -wire litedramcore_bankmachine1_sink_payload_we; -wire [22:0] litedramcore_bankmachine1_sink_payload_addr; -wire litedramcore_bankmachine1_source_valid; -wire litedramcore_bankmachine1_source_ready; -wire litedramcore_bankmachine1_source_first; -wire litedramcore_bankmachine1_source_last; -wire litedramcore_bankmachine1_source_payload_we; -wire [22:0] litedramcore_bankmachine1_source_payload_addr; -wire litedramcore_bankmachine1_syncfifo1_we; -wire litedramcore_bankmachine1_syncfifo1_writable; -wire litedramcore_bankmachine1_syncfifo1_re; -wire litedramcore_bankmachine1_syncfifo1_readable; -wire [25:0] litedramcore_bankmachine1_syncfifo1_din; -wire [25:0] litedramcore_bankmachine1_syncfifo1_dout; -reg [4:0] litedramcore_bankmachine1_level = 5'd0; -reg litedramcore_bankmachine1_replace = 1'd0; -reg [3:0] litedramcore_bankmachine1_produce = 4'd0; -reg [3:0] litedramcore_bankmachine1_consume = 4'd0; -reg [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0; -wire [25:0] litedramcore_bankmachine1_wrport_dat_r; -wire litedramcore_bankmachine1_wrport_we; -wire [25:0] litedramcore_bankmachine1_wrport_dat_w; -wire litedramcore_bankmachine1_do_read; -wire [3:0] litedramcore_bankmachine1_rdport_adr; -wire [25:0] litedramcore_bankmachine1_rdport_dat_r; -wire litedramcore_bankmachine1_fifo_in_payload_we; -wire [22:0] litedramcore_bankmachine1_fifo_in_payload_addr; -wire litedramcore_bankmachine1_fifo_in_first; -wire litedramcore_bankmachine1_fifo_in_last; -wire litedramcore_bankmachine1_fifo_out_payload_we; -wire [22:0] litedramcore_bankmachine1_fifo_out_payload_addr; -wire litedramcore_bankmachine1_fifo_out_first; -wire litedramcore_bankmachine1_fifo_out_last; -wire litedramcore_bankmachine1_sink_sink_valid; -wire litedramcore_bankmachine1_sink_sink_ready; -wire litedramcore_bankmachine1_sink_sink_first; -wire litedramcore_bankmachine1_sink_sink_last; -wire litedramcore_bankmachine1_sink_sink_payload_we; -wire [22:0] litedramcore_bankmachine1_sink_sink_payload_addr; -wire litedramcore_bankmachine1_source_source_valid; -wire litedramcore_bankmachine1_source_source_ready; -wire litedramcore_bankmachine1_source_source_first; -wire litedramcore_bankmachine1_source_source_last; -wire litedramcore_bankmachine1_source_source_payload_we; -wire [22:0] litedramcore_bankmachine1_source_source_payload_addr; -wire litedramcore_bankmachine1_pipe_valid_sink_valid; -wire litedramcore_bankmachine1_pipe_valid_sink_ready; -wire litedramcore_bankmachine1_pipe_valid_sink_first; -wire litedramcore_bankmachine1_pipe_valid_sink_last; -wire litedramcore_bankmachine1_pipe_valid_sink_payload_we; -wire [22:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine1_pipe_valid_source_ready; -reg litedramcore_bankmachine1_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine1_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; -reg [22:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 23'd0; -reg [15:0] litedramcore_bankmachine1_row = 16'd0; -reg litedramcore_bankmachine1_row_opened = 1'd0; -wire litedramcore_bankmachine1_row_hit; -reg litedramcore_bankmachine1_row_open = 1'd0; -reg litedramcore_bankmachine1_row_close = 1'd0; -reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine1_twtpcon_valid; +reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine0_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine0_wrport_adr = 4'd0; +wire [25:0] main_litedramcore_bankmachine0_wrport_dat_r; +wire [25:0] main_litedramcore_bankmachine0_wrport_dat_w; +wire main_litedramcore_bankmachine0_wrport_we; +reg main_litedramcore_bankmachine1_auto_precharge = 1'd0; +reg [15:0] main_litedramcore_bankmachine1_cmd_payload_a = 16'd0; +wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba; +reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine1_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine1_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine1_consume = 4'd0; +wire main_litedramcore_bankmachine1_do_read; +wire main_litedramcore_bankmachine1_fifo_in_first; +wire main_litedramcore_bankmachine1_fifo_in_last; +wire [22:0] main_litedramcore_bankmachine1_fifo_in_payload_addr; +wire main_litedramcore_bankmachine1_fifo_in_payload_we; +wire main_litedramcore_bankmachine1_fifo_out_first; +wire main_litedramcore_bankmachine1_fifo_out_last; +wire [22:0] main_litedramcore_bankmachine1_fifo_out_payload_addr; +wire main_litedramcore_bankmachine1_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine1_level = 5'd0; +wire main_litedramcore_bankmachine1_pipe_valid_sink_first; +wire main_litedramcore_bankmachine1_pipe_valid_sink_last; +wire [22:0] main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine1_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine1_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine1_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine1_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine1_pipe_valid_source_last = 1'd0; +reg [22:0] main_litedramcore_bankmachine1_pipe_valid_source_payload_addr = 23'd0; +reg main_litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine1_pipe_valid_source_ready; +reg main_litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine1_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine1_rdport_adr; +wire [25:0] main_litedramcore_bankmachine1_rdport_dat_r; +reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine1_refresh_req; +reg main_litedramcore_bankmachine1_replace = 1'd0; +wire [22:0] main_litedramcore_bankmachine1_req_addr; +wire main_litedramcore_bankmachine1_req_lock; +reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine1_req_ready; +wire main_litedramcore_bankmachine1_req_valid; +reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine1_req_we; +reg [15:0] main_litedramcore_bankmachine1_row = 16'd0; +reg main_litedramcore_bankmachine1_row_close = 1'd0; +reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine1_row_hit; +reg main_litedramcore_bankmachine1_row_open = 1'd0; +reg main_litedramcore_bankmachine1_row_opened = 1'd0; +reg main_litedramcore_bankmachine1_sink_first = 1'd0; +reg main_litedramcore_bankmachine1_sink_last = 1'd0; +wire [22:0] main_litedramcore_bankmachine1_sink_payload_addr; +wire main_litedramcore_bankmachine1_sink_payload_we; +wire main_litedramcore_bankmachine1_sink_ready; +wire main_litedramcore_bankmachine1_sink_sink_first; +wire main_litedramcore_bankmachine1_sink_sink_last; +wire [22:0] main_litedramcore_bankmachine1_sink_sink_payload_addr; +wire main_litedramcore_bankmachine1_sink_sink_payload_we; +wire main_litedramcore_bankmachine1_sink_sink_ready; +wire main_litedramcore_bankmachine1_sink_sink_valid; +wire main_litedramcore_bankmachine1_sink_valid; +wire main_litedramcore_bankmachine1_source_first; +wire main_litedramcore_bankmachine1_source_last; +wire [22:0] main_litedramcore_bankmachine1_source_payload_addr; +wire main_litedramcore_bankmachine1_source_payload_we; +wire main_litedramcore_bankmachine1_source_ready; +wire main_litedramcore_bankmachine1_source_source_first; +wire main_litedramcore_bankmachine1_source_source_last; +wire [22:0] main_litedramcore_bankmachine1_source_source_payload_addr; +wire main_litedramcore_bankmachine1_source_source_payload_we; +wire main_litedramcore_bankmachine1_source_source_ready; +wire main_litedramcore_bankmachine1_source_source_valid; +wire main_litedramcore_bankmachine1_source_valid; +wire [25:0] main_litedramcore_bankmachine1_syncfifo1_din; +wire [25:0] main_litedramcore_bankmachine1_syncfifo1_dout; +wire main_litedramcore_bankmachine1_syncfifo1_re; +wire main_litedramcore_bankmachine1_syncfifo1_readable; +wire main_litedramcore_bankmachine1_syncfifo1_we; +wire main_litedramcore_bankmachine1_syncfifo1_writable; +reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; -wire litedramcore_bankmachine1_trccon_valid; +reg main_litedramcore_bankmachine1_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine1_trascon_valid; +reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0; -wire litedramcore_bankmachine1_trascon_valid; +reg main_litedramcore_bankmachine1_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine1_trccon_valid; +reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine1_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0; -wire litedramcore_bankmachine2_req_valid; -wire litedramcore_bankmachine2_req_ready; -wire litedramcore_bankmachine2_req_we; -wire [22:0] litedramcore_bankmachine2_req_addr; -wire litedramcore_bankmachine2_req_lock; -reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine2_refresh_req; -reg litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg litedramcore_bankmachine2_cmd_valid = 1'd0; -reg litedramcore_bankmachine2_cmd_ready = 1'd0; -reg [15:0] litedramcore_bankmachine2_cmd_payload_a = 16'd0; -wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; -reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine2_auto_precharge = 1'd0; -wire litedramcore_bankmachine2_sink_valid; -wire litedramcore_bankmachine2_sink_ready; -reg litedramcore_bankmachine2_sink_first = 1'd0; -reg litedramcore_bankmachine2_sink_last = 1'd0; -wire litedramcore_bankmachine2_sink_payload_we; -wire [22:0] litedramcore_bankmachine2_sink_payload_addr; -wire litedramcore_bankmachine2_source_valid; -wire litedramcore_bankmachine2_source_ready; -wire litedramcore_bankmachine2_source_first; -wire litedramcore_bankmachine2_source_last; -wire litedramcore_bankmachine2_source_payload_we; -wire [22:0] litedramcore_bankmachine2_source_payload_addr; -wire litedramcore_bankmachine2_syncfifo2_we; -wire litedramcore_bankmachine2_syncfifo2_writable; -wire litedramcore_bankmachine2_syncfifo2_re; -wire litedramcore_bankmachine2_syncfifo2_readable; -wire [25:0] litedramcore_bankmachine2_syncfifo2_din; -wire [25:0] litedramcore_bankmachine2_syncfifo2_dout; -reg [4:0] litedramcore_bankmachine2_level = 5'd0; -reg litedramcore_bankmachine2_replace = 1'd0; -reg [3:0] litedramcore_bankmachine2_produce = 4'd0; -reg [3:0] litedramcore_bankmachine2_consume = 4'd0; -reg [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0; -wire [25:0] litedramcore_bankmachine2_wrport_dat_r; -wire litedramcore_bankmachine2_wrport_we; -wire [25:0] litedramcore_bankmachine2_wrport_dat_w; -wire litedramcore_bankmachine2_do_read; -wire [3:0] litedramcore_bankmachine2_rdport_adr; -wire [25:0] litedramcore_bankmachine2_rdport_dat_r; -wire litedramcore_bankmachine2_fifo_in_payload_we; -wire [22:0] litedramcore_bankmachine2_fifo_in_payload_addr; -wire litedramcore_bankmachine2_fifo_in_first; -wire litedramcore_bankmachine2_fifo_in_last; -wire litedramcore_bankmachine2_fifo_out_payload_we; -wire [22:0] litedramcore_bankmachine2_fifo_out_payload_addr; -wire litedramcore_bankmachine2_fifo_out_first; -wire litedramcore_bankmachine2_fifo_out_last; -wire litedramcore_bankmachine2_sink_sink_valid; -wire litedramcore_bankmachine2_sink_sink_ready; -wire litedramcore_bankmachine2_sink_sink_first; -wire litedramcore_bankmachine2_sink_sink_last; -wire litedramcore_bankmachine2_sink_sink_payload_we; -wire [22:0] litedramcore_bankmachine2_sink_sink_payload_addr; -wire litedramcore_bankmachine2_source_source_valid; -wire litedramcore_bankmachine2_source_source_ready; -wire litedramcore_bankmachine2_source_source_first; -wire litedramcore_bankmachine2_source_source_last; -wire litedramcore_bankmachine2_source_source_payload_we; -wire [22:0] litedramcore_bankmachine2_source_source_payload_addr; -wire litedramcore_bankmachine2_pipe_valid_sink_valid; -wire litedramcore_bankmachine2_pipe_valid_sink_ready; -wire litedramcore_bankmachine2_pipe_valid_sink_first; -wire litedramcore_bankmachine2_pipe_valid_sink_last; -wire litedramcore_bankmachine2_pipe_valid_sink_payload_we; -wire [22:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine2_pipe_valid_source_ready; -reg litedramcore_bankmachine2_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine2_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; -reg [22:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 23'd0; -reg [15:0] litedramcore_bankmachine2_row = 16'd0; -reg litedramcore_bankmachine2_row_opened = 1'd0; -wire litedramcore_bankmachine2_row_hit; -reg litedramcore_bankmachine2_row_open = 1'd0; -reg litedramcore_bankmachine2_row_close = 1'd0; -reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine2_twtpcon_valid; +reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine1_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine1_wrport_adr = 4'd0; +wire [25:0] main_litedramcore_bankmachine1_wrport_dat_r; +wire [25:0] main_litedramcore_bankmachine1_wrport_dat_w; +wire main_litedramcore_bankmachine1_wrport_we; +reg main_litedramcore_bankmachine2_auto_precharge = 1'd0; +reg [15:0] main_litedramcore_bankmachine2_cmd_payload_a = 16'd0; +wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba; +reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine2_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine2_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine2_consume = 4'd0; +wire main_litedramcore_bankmachine2_do_read; +wire main_litedramcore_bankmachine2_fifo_in_first; +wire main_litedramcore_bankmachine2_fifo_in_last; +wire [22:0] main_litedramcore_bankmachine2_fifo_in_payload_addr; +wire main_litedramcore_bankmachine2_fifo_in_payload_we; +wire main_litedramcore_bankmachine2_fifo_out_first; +wire main_litedramcore_bankmachine2_fifo_out_last; +wire [22:0] main_litedramcore_bankmachine2_fifo_out_payload_addr; +wire main_litedramcore_bankmachine2_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine2_level = 5'd0; +wire main_litedramcore_bankmachine2_pipe_valid_sink_first; +wire main_litedramcore_bankmachine2_pipe_valid_sink_last; +wire [22:0] main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine2_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine2_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine2_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine2_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine2_pipe_valid_source_last = 1'd0; +reg [22:0] main_litedramcore_bankmachine2_pipe_valid_source_payload_addr = 23'd0; +reg main_litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine2_pipe_valid_source_ready; +reg main_litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine2_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine2_rdport_adr; +wire [25:0] main_litedramcore_bankmachine2_rdport_dat_r; +reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine2_refresh_req; +reg main_litedramcore_bankmachine2_replace = 1'd0; +wire [22:0] main_litedramcore_bankmachine2_req_addr; +wire main_litedramcore_bankmachine2_req_lock; +reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine2_req_ready; +wire main_litedramcore_bankmachine2_req_valid; +reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine2_req_we; +reg [15:0] main_litedramcore_bankmachine2_row = 16'd0; +reg main_litedramcore_bankmachine2_row_close = 1'd0; +reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine2_row_hit; +reg main_litedramcore_bankmachine2_row_open = 1'd0; +reg main_litedramcore_bankmachine2_row_opened = 1'd0; +reg main_litedramcore_bankmachine2_sink_first = 1'd0; +reg main_litedramcore_bankmachine2_sink_last = 1'd0; +wire [22:0] main_litedramcore_bankmachine2_sink_payload_addr; +wire main_litedramcore_bankmachine2_sink_payload_we; +wire main_litedramcore_bankmachine2_sink_ready; +wire main_litedramcore_bankmachine2_sink_sink_first; +wire main_litedramcore_bankmachine2_sink_sink_last; +wire [22:0] main_litedramcore_bankmachine2_sink_sink_payload_addr; +wire main_litedramcore_bankmachine2_sink_sink_payload_we; +wire main_litedramcore_bankmachine2_sink_sink_ready; +wire main_litedramcore_bankmachine2_sink_sink_valid; +wire main_litedramcore_bankmachine2_sink_valid; +wire main_litedramcore_bankmachine2_source_first; +wire main_litedramcore_bankmachine2_source_last; +wire [22:0] main_litedramcore_bankmachine2_source_payload_addr; +wire main_litedramcore_bankmachine2_source_payload_we; +wire main_litedramcore_bankmachine2_source_ready; +wire main_litedramcore_bankmachine2_source_source_first; +wire main_litedramcore_bankmachine2_source_source_last; +wire [22:0] main_litedramcore_bankmachine2_source_source_payload_addr; +wire main_litedramcore_bankmachine2_source_source_payload_we; +wire main_litedramcore_bankmachine2_source_source_ready; +wire main_litedramcore_bankmachine2_source_source_valid; +wire main_litedramcore_bankmachine2_source_valid; +wire [25:0] main_litedramcore_bankmachine2_syncfifo2_din; +wire [25:0] main_litedramcore_bankmachine2_syncfifo2_dout; +wire main_litedramcore_bankmachine2_syncfifo2_re; +wire main_litedramcore_bankmachine2_syncfifo2_readable; +wire main_litedramcore_bankmachine2_syncfifo2_we; +wire main_litedramcore_bankmachine2_syncfifo2_writable; +reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; -wire litedramcore_bankmachine2_trccon_valid; +reg main_litedramcore_bankmachine2_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine2_trascon_valid; +reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0; -wire litedramcore_bankmachine2_trascon_valid; +reg main_litedramcore_bankmachine2_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine2_trccon_valid; +reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine2_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0; -wire litedramcore_bankmachine3_req_valid; -wire litedramcore_bankmachine3_req_ready; -wire litedramcore_bankmachine3_req_we; -wire [22:0] litedramcore_bankmachine3_req_addr; -wire litedramcore_bankmachine3_req_lock; -reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine3_refresh_req; -reg litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg litedramcore_bankmachine3_cmd_valid = 1'd0; -reg litedramcore_bankmachine3_cmd_ready = 1'd0; -reg [15:0] litedramcore_bankmachine3_cmd_payload_a = 16'd0; -wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; -reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine3_auto_precharge = 1'd0; -wire litedramcore_bankmachine3_sink_valid; -wire litedramcore_bankmachine3_sink_ready; -reg litedramcore_bankmachine3_sink_first = 1'd0; -reg litedramcore_bankmachine3_sink_last = 1'd0; -wire litedramcore_bankmachine3_sink_payload_we; -wire [22:0] litedramcore_bankmachine3_sink_payload_addr; -wire litedramcore_bankmachine3_source_valid; -wire litedramcore_bankmachine3_source_ready; -wire litedramcore_bankmachine3_source_first; -wire litedramcore_bankmachine3_source_last; -wire litedramcore_bankmachine3_source_payload_we; -wire [22:0] litedramcore_bankmachine3_source_payload_addr; -wire litedramcore_bankmachine3_syncfifo3_we; -wire litedramcore_bankmachine3_syncfifo3_writable; -wire litedramcore_bankmachine3_syncfifo3_re; -wire litedramcore_bankmachine3_syncfifo3_readable; -wire [25:0] litedramcore_bankmachine3_syncfifo3_din; -wire [25:0] litedramcore_bankmachine3_syncfifo3_dout; -reg [4:0] litedramcore_bankmachine3_level = 5'd0; -reg litedramcore_bankmachine3_replace = 1'd0; -reg [3:0] litedramcore_bankmachine3_produce = 4'd0; -reg [3:0] litedramcore_bankmachine3_consume = 4'd0; -reg [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0; -wire [25:0] litedramcore_bankmachine3_wrport_dat_r; -wire litedramcore_bankmachine3_wrport_we; -wire [25:0] litedramcore_bankmachine3_wrport_dat_w; -wire litedramcore_bankmachine3_do_read; -wire [3:0] litedramcore_bankmachine3_rdport_adr; -wire [25:0] litedramcore_bankmachine3_rdport_dat_r; -wire litedramcore_bankmachine3_fifo_in_payload_we; -wire [22:0] litedramcore_bankmachine3_fifo_in_payload_addr; -wire litedramcore_bankmachine3_fifo_in_first; -wire litedramcore_bankmachine3_fifo_in_last; -wire litedramcore_bankmachine3_fifo_out_payload_we; -wire [22:0] litedramcore_bankmachine3_fifo_out_payload_addr; -wire litedramcore_bankmachine3_fifo_out_first; -wire litedramcore_bankmachine3_fifo_out_last; -wire litedramcore_bankmachine3_sink_sink_valid; -wire litedramcore_bankmachine3_sink_sink_ready; -wire litedramcore_bankmachine3_sink_sink_first; -wire litedramcore_bankmachine3_sink_sink_last; -wire litedramcore_bankmachine3_sink_sink_payload_we; -wire [22:0] litedramcore_bankmachine3_sink_sink_payload_addr; -wire litedramcore_bankmachine3_source_source_valid; -wire litedramcore_bankmachine3_source_source_ready; -wire litedramcore_bankmachine3_source_source_first; -wire litedramcore_bankmachine3_source_source_last; -wire litedramcore_bankmachine3_source_source_payload_we; -wire [22:0] litedramcore_bankmachine3_source_source_payload_addr; -wire litedramcore_bankmachine3_pipe_valid_sink_valid; -wire litedramcore_bankmachine3_pipe_valid_sink_ready; -wire litedramcore_bankmachine3_pipe_valid_sink_first; -wire litedramcore_bankmachine3_pipe_valid_sink_last; -wire litedramcore_bankmachine3_pipe_valid_sink_payload_we; -wire [22:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine3_pipe_valid_source_ready; -reg litedramcore_bankmachine3_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine3_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; -reg [22:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 23'd0; -reg [15:0] litedramcore_bankmachine3_row = 16'd0; -reg litedramcore_bankmachine3_row_opened = 1'd0; -wire litedramcore_bankmachine3_row_hit; -reg litedramcore_bankmachine3_row_open = 1'd0; -reg litedramcore_bankmachine3_row_close = 1'd0; -reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine3_twtpcon_valid; +reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine2_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine2_wrport_adr = 4'd0; +wire [25:0] main_litedramcore_bankmachine2_wrport_dat_r; +wire [25:0] main_litedramcore_bankmachine2_wrport_dat_w; +wire main_litedramcore_bankmachine2_wrport_we; +reg main_litedramcore_bankmachine3_auto_precharge = 1'd0; +reg [15:0] main_litedramcore_bankmachine3_cmd_payload_a = 16'd0; +wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba; +reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine3_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine3_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine3_consume = 4'd0; +wire main_litedramcore_bankmachine3_do_read; +wire main_litedramcore_bankmachine3_fifo_in_first; +wire main_litedramcore_bankmachine3_fifo_in_last; +wire [22:0] main_litedramcore_bankmachine3_fifo_in_payload_addr; +wire main_litedramcore_bankmachine3_fifo_in_payload_we; +wire main_litedramcore_bankmachine3_fifo_out_first; +wire main_litedramcore_bankmachine3_fifo_out_last; +wire [22:0] main_litedramcore_bankmachine3_fifo_out_payload_addr; +wire main_litedramcore_bankmachine3_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine3_level = 5'd0; +wire main_litedramcore_bankmachine3_pipe_valid_sink_first; +wire main_litedramcore_bankmachine3_pipe_valid_sink_last; +wire [22:0] main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine3_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine3_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine3_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine3_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine3_pipe_valid_source_last = 1'd0; +reg [22:0] main_litedramcore_bankmachine3_pipe_valid_source_payload_addr = 23'd0; +reg main_litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine3_pipe_valid_source_ready; +reg main_litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine3_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine3_rdport_adr; +wire [25:0] main_litedramcore_bankmachine3_rdport_dat_r; +reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine3_refresh_req; +reg main_litedramcore_bankmachine3_replace = 1'd0; +wire [22:0] main_litedramcore_bankmachine3_req_addr; +wire main_litedramcore_bankmachine3_req_lock; +reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine3_req_ready; +wire main_litedramcore_bankmachine3_req_valid; +reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine3_req_we; +reg [15:0] main_litedramcore_bankmachine3_row = 16'd0; +reg main_litedramcore_bankmachine3_row_close = 1'd0; +reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine3_row_hit; +reg main_litedramcore_bankmachine3_row_open = 1'd0; +reg main_litedramcore_bankmachine3_row_opened = 1'd0; +reg main_litedramcore_bankmachine3_sink_first = 1'd0; +reg main_litedramcore_bankmachine3_sink_last = 1'd0; +wire [22:0] main_litedramcore_bankmachine3_sink_payload_addr; +wire main_litedramcore_bankmachine3_sink_payload_we; +wire main_litedramcore_bankmachine3_sink_ready; +wire main_litedramcore_bankmachine3_sink_sink_first; +wire main_litedramcore_bankmachine3_sink_sink_last; +wire [22:0] main_litedramcore_bankmachine3_sink_sink_payload_addr; +wire main_litedramcore_bankmachine3_sink_sink_payload_we; +wire main_litedramcore_bankmachine3_sink_sink_ready; +wire main_litedramcore_bankmachine3_sink_sink_valid; +wire main_litedramcore_bankmachine3_sink_valid; +wire main_litedramcore_bankmachine3_source_first; +wire main_litedramcore_bankmachine3_source_last; +wire [22:0] main_litedramcore_bankmachine3_source_payload_addr; +wire main_litedramcore_bankmachine3_source_payload_we; +wire main_litedramcore_bankmachine3_source_ready; +wire main_litedramcore_bankmachine3_source_source_first; +wire main_litedramcore_bankmachine3_source_source_last; +wire [22:0] main_litedramcore_bankmachine3_source_source_payload_addr; +wire main_litedramcore_bankmachine3_source_source_payload_we; +wire main_litedramcore_bankmachine3_source_source_ready; +wire main_litedramcore_bankmachine3_source_source_valid; +wire main_litedramcore_bankmachine3_source_valid; +wire [25:0] main_litedramcore_bankmachine3_syncfifo3_din; +wire [25:0] main_litedramcore_bankmachine3_syncfifo3_dout; +wire main_litedramcore_bankmachine3_syncfifo3_re; +wire main_litedramcore_bankmachine3_syncfifo3_readable; +wire main_litedramcore_bankmachine3_syncfifo3_we; +wire main_litedramcore_bankmachine3_syncfifo3_writable; +reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; -wire litedramcore_bankmachine3_trccon_valid; +reg main_litedramcore_bankmachine3_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine3_trascon_valid; +reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0; -wire litedramcore_bankmachine3_trascon_valid; +reg main_litedramcore_bankmachine3_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine3_trccon_valid; +reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine3_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0; -wire litedramcore_bankmachine4_req_valid; -wire litedramcore_bankmachine4_req_ready; -wire litedramcore_bankmachine4_req_we; -wire [22:0] litedramcore_bankmachine4_req_addr; -wire litedramcore_bankmachine4_req_lock; -reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine4_refresh_req; -reg litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg litedramcore_bankmachine4_cmd_valid = 1'd0; -reg litedramcore_bankmachine4_cmd_ready = 1'd0; -reg [15:0] litedramcore_bankmachine4_cmd_payload_a = 16'd0; -wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; -reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine4_auto_precharge = 1'd0; -wire litedramcore_bankmachine4_sink_valid; -wire litedramcore_bankmachine4_sink_ready; -reg litedramcore_bankmachine4_sink_first = 1'd0; -reg litedramcore_bankmachine4_sink_last = 1'd0; -wire litedramcore_bankmachine4_sink_payload_we; -wire [22:0] litedramcore_bankmachine4_sink_payload_addr; -wire litedramcore_bankmachine4_source_valid; -wire litedramcore_bankmachine4_source_ready; -wire litedramcore_bankmachine4_source_first; -wire litedramcore_bankmachine4_source_last; -wire litedramcore_bankmachine4_source_payload_we; -wire [22:0] litedramcore_bankmachine4_source_payload_addr; -wire litedramcore_bankmachine4_syncfifo4_we; -wire litedramcore_bankmachine4_syncfifo4_writable; -wire litedramcore_bankmachine4_syncfifo4_re; -wire litedramcore_bankmachine4_syncfifo4_readable; -wire [25:0] litedramcore_bankmachine4_syncfifo4_din; -wire [25:0] litedramcore_bankmachine4_syncfifo4_dout; -reg [4:0] litedramcore_bankmachine4_level = 5'd0; -reg litedramcore_bankmachine4_replace = 1'd0; -reg [3:0] litedramcore_bankmachine4_produce = 4'd0; -reg [3:0] litedramcore_bankmachine4_consume = 4'd0; -reg [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0; -wire [25:0] litedramcore_bankmachine4_wrport_dat_r; -wire litedramcore_bankmachine4_wrport_we; -wire [25:0] litedramcore_bankmachine4_wrport_dat_w; -wire litedramcore_bankmachine4_do_read; -wire [3:0] litedramcore_bankmachine4_rdport_adr; -wire [25:0] litedramcore_bankmachine4_rdport_dat_r; -wire litedramcore_bankmachine4_fifo_in_payload_we; -wire [22:0] litedramcore_bankmachine4_fifo_in_payload_addr; -wire litedramcore_bankmachine4_fifo_in_first; -wire litedramcore_bankmachine4_fifo_in_last; -wire litedramcore_bankmachine4_fifo_out_payload_we; -wire [22:0] litedramcore_bankmachine4_fifo_out_payload_addr; -wire litedramcore_bankmachine4_fifo_out_first; -wire litedramcore_bankmachine4_fifo_out_last; -wire litedramcore_bankmachine4_sink_sink_valid; -wire litedramcore_bankmachine4_sink_sink_ready; -wire litedramcore_bankmachine4_sink_sink_first; -wire litedramcore_bankmachine4_sink_sink_last; -wire litedramcore_bankmachine4_sink_sink_payload_we; -wire [22:0] litedramcore_bankmachine4_sink_sink_payload_addr; -wire litedramcore_bankmachine4_source_source_valid; -wire litedramcore_bankmachine4_source_source_ready; -wire litedramcore_bankmachine4_source_source_first; -wire litedramcore_bankmachine4_source_source_last; -wire litedramcore_bankmachine4_source_source_payload_we; -wire [22:0] litedramcore_bankmachine4_source_source_payload_addr; -wire litedramcore_bankmachine4_pipe_valid_sink_valid; -wire litedramcore_bankmachine4_pipe_valid_sink_ready; -wire litedramcore_bankmachine4_pipe_valid_sink_first; -wire litedramcore_bankmachine4_pipe_valid_sink_last; -wire litedramcore_bankmachine4_pipe_valid_sink_payload_we; -wire [22:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine4_pipe_valid_source_ready; -reg litedramcore_bankmachine4_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine4_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; -reg [22:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 23'd0; -reg [15:0] litedramcore_bankmachine4_row = 16'd0; -reg litedramcore_bankmachine4_row_opened = 1'd0; -wire litedramcore_bankmachine4_row_hit; -reg litedramcore_bankmachine4_row_open = 1'd0; -reg litedramcore_bankmachine4_row_close = 1'd0; -reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine4_twtpcon_valid; +reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine3_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine3_wrport_adr = 4'd0; +wire [25:0] main_litedramcore_bankmachine3_wrport_dat_r; +wire [25:0] main_litedramcore_bankmachine3_wrport_dat_w; +wire main_litedramcore_bankmachine3_wrport_we; +reg main_litedramcore_bankmachine4_auto_precharge = 1'd0; +reg [15:0] main_litedramcore_bankmachine4_cmd_payload_a = 16'd0; +wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba; +reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine4_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine4_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine4_consume = 4'd0; +wire main_litedramcore_bankmachine4_do_read; +wire main_litedramcore_bankmachine4_fifo_in_first; +wire main_litedramcore_bankmachine4_fifo_in_last; +wire [22:0] main_litedramcore_bankmachine4_fifo_in_payload_addr; +wire main_litedramcore_bankmachine4_fifo_in_payload_we; +wire main_litedramcore_bankmachine4_fifo_out_first; +wire main_litedramcore_bankmachine4_fifo_out_last; +wire [22:0] main_litedramcore_bankmachine4_fifo_out_payload_addr; +wire main_litedramcore_bankmachine4_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine4_level = 5'd0; +wire main_litedramcore_bankmachine4_pipe_valid_sink_first; +wire main_litedramcore_bankmachine4_pipe_valid_sink_last; +wire [22:0] main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine4_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine4_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine4_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine4_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine4_pipe_valid_source_last = 1'd0; +reg [22:0] main_litedramcore_bankmachine4_pipe_valid_source_payload_addr = 23'd0; +reg main_litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine4_pipe_valid_source_ready; +reg main_litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine4_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine4_rdport_adr; +wire [25:0] main_litedramcore_bankmachine4_rdport_dat_r; +reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine4_refresh_req; +reg main_litedramcore_bankmachine4_replace = 1'd0; +wire [22:0] main_litedramcore_bankmachine4_req_addr; +wire main_litedramcore_bankmachine4_req_lock; +reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine4_req_ready; +wire main_litedramcore_bankmachine4_req_valid; +reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine4_req_we; +reg [15:0] main_litedramcore_bankmachine4_row = 16'd0; +reg main_litedramcore_bankmachine4_row_close = 1'd0; +reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine4_row_hit; +reg main_litedramcore_bankmachine4_row_open = 1'd0; +reg main_litedramcore_bankmachine4_row_opened = 1'd0; +reg main_litedramcore_bankmachine4_sink_first = 1'd0; +reg main_litedramcore_bankmachine4_sink_last = 1'd0; +wire [22:0] main_litedramcore_bankmachine4_sink_payload_addr; +wire main_litedramcore_bankmachine4_sink_payload_we; +wire main_litedramcore_bankmachine4_sink_ready; +wire main_litedramcore_bankmachine4_sink_sink_first; +wire main_litedramcore_bankmachine4_sink_sink_last; +wire [22:0] main_litedramcore_bankmachine4_sink_sink_payload_addr; +wire main_litedramcore_bankmachine4_sink_sink_payload_we; +wire main_litedramcore_bankmachine4_sink_sink_ready; +wire main_litedramcore_bankmachine4_sink_sink_valid; +wire main_litedramcore_bankmachine4_sink_valid; +wire main_litedramcore_bankmachine4_source_first; +wire main_litedramcore_bankmachine4_source_last; +wire [22:0] main_litedramcore_bankmachine4_source_payload_addr; +wire main_litedramcore_bankmachine4_source_payload_we; +wire main_litedramcore_bankmachine4_source_ready; +wire main_litedramcore_bankmachine4_source_source_first; +wire main_litedramcore_bankmachine4_source_source_last; +wire [22:0] main_litedramcore_bankmachine4_source_source_payload_addr; +wire main_litedramcore_bankmachine4_source_source_payload_we; +wire main_litedramcore_bankmachine4_source_source_ready; +wire main_litedramcore_bankmachine4_source_source_valid; +wire main_litedramcore_bankmachine4_source_valid; +wire [25:0] main_litedramcore_bankmachine4_syncfifo4_din; +wire [25:0] main_litedramcore_bankmachine4_syncfifo4_dout; +wire main_litedramcore_bankmachine4_syncfifo4_re; +wire main_litedramcore_bankmachine4_syncfifo4_readable; +wire main_litedramcore_bankmachine4_syncfifo4_we; +wire main_litedramcore_bankmachine4_syncfifo4_writable; +reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; -wire litedramcore_bankmachine4_trccon_valid; +reg main_litedramcore_bankmachine4_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine4_trascon_valid; +reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0; -wire litedramcore_bankmachine4_trascon_valid; +reg main_litedramcore_bankmachine4_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine4_trccon_valid; +reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine4_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0; -wire litedramcore_bankmachine5_req_valid; -wire litedramcore_bankmachine5_req_ready; -wire litedramcore_bankmachine5_req_we; -wire [22:0] litedramcore_bankmachine5_req_addr; -wire litedramcore_bankmachine5_req_lock; -reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine5_refresh_req; -reg litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg litedramcore_bankmachine5_cmd_valid = 1'd0; -reg litedramcore_bankmachine5_cmd_ready = 1'd0; -reg [15:0] litedramcore_bankmachine5_cmd_payload_a = 16'd0; -wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; -reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine5_auto_precharge = 1'd0; -wire litedramcore_bankmachine5_sink_valid; -wire litedramcore_bankmachine5_sink_ready; -reg litedramcore_bankmachine5_sink_first = 1'd0; -reg litedramcore_bankmachine5_sink_last = 1'd0; -wire litedramcore_bankmachine5_sink_payload_we; -wire [22:0] litedramcore_bankmachine5_sink_payload_addr; -wire litedramcore_bankmachine5_source_valid; -wire litedramcore_bankmachine5_source_ready; -wire litedramcore_bankmachine5_source_first; -wire litedramcore_bankmachine5_source_last; -wire litedramcore_bankmachine5_source_payload_we; -wire [22:0] litedramcore_bankmachine5_source_payload_addr; -wire litedramcore_bankmachine5_syncfifo5_we; -wire litedramcore_bankmachine5_syncfifo5_writable; -wire litedramcore_bankmachine5_syncfifo5_re; -wire litedramcore_bankmachine5_syncfifo5_readable; -wire [25:0] litedramcore_bankmachine5_syncfifo5_din; -wire [25:0] litedramcore_bankmachine5_syncfifo5_dout; -reg [4:0] litedramcore_bankmachine5_level = 5'd0; -reg litedramcore_bankmachine5_replace = 1'd0; -reg [3:0] litedramcore_bankmachine5_produce = 4'd0; -reg [3:0] litedramcore_bankmachine5_consume = 4'd0; -reg [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0; -wire [25:0] litedramcore_bankmachine5_wrport_dat_r; -wire litedramcore_bankmachine5_wrport_we; -wire [25:0] litedramcore_bankmachine5_wrport_dat_w; -wire litedramcore_bankmachine5_do_read; -wire [3:0] litedramcore_bankmachine5_rdport_adr; -wire [25:0] litedramcore_bankmachine5_rdport_dat_r; -wire litedramcore_bankmachine5_fifo_in_payload_we; -wire [22:0] litedramcore_bankmachine5_fifo_in_payload_addr; -wire litedramcore_bankmachine5_fifo_in_first; -wire litedramcore_bankmachine5_fifo_in_last; -wire litedramcore_bankmachine5_fifo_out_payload_we; -wire [22:0] litedramcore_bankmachine5_fifo_out_payload_addr; -wire litedramcore_bankmachine5_fifo_out_first; -wire litedramcore_bankmachine5_fifo_out_last; -wire litedramcore_bankmachine5_sink_sink_valid; -wire litedramcore_bankmachine5_sink_sink_ready; -wire litedramcore_bankmachine5_sink_sink_first; -wire litedramcore_bankmachine5_sink_sink_last; -wire litedramcore_bankmachine5_sink_sink_payload_we; -wire [22:0] litedramcore_bankmachine5_sink_sink_payload_addr; -wire litedramcore_bankmachine5_source_source_valid; -wire litedramcore_bankmachine5_source_source_ready; -wire litedramcore_bankmachine5_source_source_first; -wire litedramcore_bankmachine5_source_source_last; -wire litedramcore_bankmachine5_source_source_payload_we; -wire [22:0] litedramcore_bankmachine5_source_source_payload_addr; -wire litedramcore_bankmachine5_pipe_valid_sink_valid; -wire litedramcore_bankmachine5_pipe_valid_sink_ready; -wire litedramcore_bankmachine5_pipe_valid_sink_first; -wire litedramcore_bankmachine5_pipe_valid_sink_last; -wire litedramcore_bankmachine5_pipe_valid_sink_payload_we; -wire [22:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine5_pipe_valid_source_ready; -reg litedramcore_bankmachine5_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine5_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; -reg [22:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 23'd0; -reg [15:0] litedramcore_bankmachine5_row = 16'd0; -reg litedramcore_bankmachine5_row_opened = 1'd0; -wire litedramcore_bankmachine5_row_hit; -reg litedramcore_bankmachine5_row_open = 1'd0; -reg litedramcore_bankmachine5_row_close = 1'd0; -reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine5_twtpcon_valid; +reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine4_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine4_wrport_adr = 4'd0; +wire [25:0] main_litedramcore_bankmachine4_wrport_dat_r; +wire [25:0] main_litedramcore_bankmachine4_wrport_dat_w; +wire main_litedramcore_bankmachine4_wrport_we; +reg main_litedramcore_bankmachine5_auto_precharge = 1'd0; +reg [15:0] main_litedramcore_bankmachine5_cmd_payload_a = 16'd0; +wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba; +reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine5_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine5_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine5_consume = 4'd0; +wire main_litedramcore_bankmachine5_do_read; +wire main_litedramcore_bankmachine5_fifo_in_first; +wire main_litedramcore_bankmachine5_fifo_in_last; +wire [22:0] main_litedramcore_bankmachine5_fifo_in_payload_addr; +wire main_litedramcore_bankmachine5_fifo_in_payload_we; +wire main_litedramcore_bankmachine5_fifo_out_first; +wire main_litedramcore_bankmachine5_fifo_out_last; +wire [22:0] main_litedramcore_bankmachine5_fifo_out_payload_addr; +wire main_litedramcore_bankmachine5_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine5_level = 5'd0; +wire main_litedramcore_bankmachine5_pipe_valid_sink_first; +wire main_litedramcore_bankmachine5_pipe_valid_sink_last; +wire [22:0] main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine5_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine5_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine5_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine5_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine5_pipe_valid_source_last = 1'd0; +reg [22:0] main_litedramcore_bankmachine5_pipe_valid_source_payload_addr = 23'd0; +reg main_litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine5_pipe_valid_source_ready; +reg main_litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine5_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine5_rdport_adr; +wire [25:0] main_litedramcore_bankmachine5_rdport_dat_r; +reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine5_refresh_req; +reg main_litedramcore_bankmachine5_replace = 1'd0; +wire [22:0] main_litedramcore_bankmachine5_req_addr; +wire main_litedramcore_bankmachine5_req_lock; +reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine5_req_ready; +wire main_litedramcore_bankmachine5_req_valid; +reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine5_req_we; +reg [15:0] main_litedramcore_bankmachine5_row = 16'd0; +reg main_litedramcore_bankmachine5_row_close = 1'd0; +reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine5_row_hit; +reg main_litedramcore_bankmachine5_row_open = 1'd0; +reg main_litedramcore_bankmachine5_row_opened = 1'd0; +reg main_litedramcore_bankmachine5_sink_first = 1'd0; +reg main_litedramcore_bankmachine5_sink_last = 1'd0; +wire [22:0] main_litedramcore_bankmachine5_sink_payload_addr; +wire main_litedramcore_bankmachine5_sink_payload_we; +wire main_litedramcore_bankmachine5_sink_ready; +wire main_litedramcore_bankmachine5_sink_sink_first; +wire main_litedramcore_bankmachine5_sink_sink_last; +wire [22:0] main_litedramcore_bankmachine5_sink_sink_payload_addr; +wire main_litedramcore_bankmachine5_sink_sink_payload_we; +wire main_litedramcore_bankmachine5_sink_sink_ready; +wire main_litedramcore_bankmachine5_sink_sink_valid; +wire main_litedramcore_bankmachine5_sink_valid; +wire main_litedramcore_bankmachine5_source_first; +wire main_litedramcore_bankmachine5_source_last; +wire [22:0] main_litedramcore_bankmachine5_source_payload_addr; +wire main_litedramcore_bankmachine5_source_payload_we; +wire main_litedramcore_bankmachine5_source_ready; +wire main_litedramcore_bankmachine5_source_source_first; +wire main_litedramcore_bankmachine5_source_source_last; +wire [22:0] main_litedramcore_bankmachine5_source_source_payload_addr; +wire main_litedramcore_bankmachine5_source_source_payload_we; +wire main_litedramcore_bankmachine5_source_source_ready; +wire main_litedramcore_bankmachine5_source_source_valid; +wire main_litedramcore_bankmachine5_source_valid; +wire [25:0] main_litedramcore_bankmachine5_syncfifo5_din; +wire [25:0] main_litedramcore_bankmachine5_syncfifo5_dout; +wire main_litedramcore_bankmachine5_syncfifo5_re; +wire main_litedramcore_bankmachine5_syncfifo5_readable; +wire main_litedramcore_bankmachine5_syncfifo5_we; +wire main_litedramcore_bankmachine5_syncfifo5_writable; +reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; -wire litedramcore_bankmachine5_trccon_valid; +reg main_litedramcore_bankmachine5_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine5_trascon_valid; +reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0; -wire litedramcore_bankmachine5_trascon_valid; +reg main_litedramcore_bankmachine5_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine5_trccon_valid; +reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine5_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0; -wire litedramcore_bankmachine6_req_valid; -wire litedramcore_bankmachine6_req_ready; -wire litedramcore_bankmachine6_req_we; -wire [22:0] litedramcore_bankmachine6_req_addr; -wire litedramcore_bankmachine6_req_lock; -reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine6_refresh_req; -reg litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg litedramcore_bankmachine6_cmd_valid = 1'd0; -reg litedramcore_bankmachine6_cmd_ready = 1'd0; -reg [15:0] litedramcore_bankmachine6_cmd_payload_a = 16'd0; -wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; -reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine6_auto_precharge = 1'd0; -wire litedramcore_bankmachine6_sink_valid; -wire litedramcore_bankmachine6_sink_ready; -reg litedramcore_bankmachine6_sink_first = 1'd0; -reg litedramcore_bankmachine6_sink_last = 1'd0; -wire litedramcore_bankmachine6_sink_payload_we; -wire [22:0] litedramcore_bankmachine6_sink_payload_addr; -wire litedramcore_bankmachine6_source_valid; -wire litedramcore_bankmachine6_source_ready; -wire litedramcore_bankmachine6_source_first; -wire litedramcore_bankmachine6_source_last; -wire litedramcore_bankmachine6_source_payload_we; -wire [22:0] litedramcore_bankmachine6_source_payload_addr; -wire litedramcore_bankmachine6_syncfifo6_we; -wire litedramcore_bankmachine6_syncfifo6_writable; -wire litedramcore_bankmachine6_syncfifo6_re; -wire litedramcore_bankmachine6_syncfifo6_readable; -wire [25:0] litedramcore_bankmachine6_syncfifo6_din; -wire [25:0] litedramcore_bankmachine6_syncfifo6_dout; -reg [4:0] litedramcore_bankmachine6_level = 5'd0; -reg litedramcore_bankmachine6_replace = 1'd0; -reg [3:0] litedramcore_bankmachine6_produce = 4'd0; -reg [3:0] litedramcore_bankmachine6_consume = 4'd0; -reg [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0; -wire [25:0] litedramcore_bankmachine6_wrport_dat_r; -wire litedramcore_bankmachine6_wrport_we; -wire [25:0] litedramcore_bankmachine6_wrport_dat_w; -wire litedramcore_bankmachine6_do_read; -wire [3:0] litedramcore_bankmachine6_rdport_adr; -wire [25:0] litedramcore_bankmachine6_rdport_dat_r; -wire litedramcore_bankmachine6_fifo_in_payload_we; -wire [22:0] litedramcore_bankmachine6_fifo_in_payload_addr; -wire litedramcore_bankmachine6_fifo_in_first; -wire litedramcore_bankmachine6_fifo_in_last; -wire litedramcore_bankmachine6_fifo_out_payload_we; -wire [22:0] litedramcore_bankmachine6_fifo_out_payload_addr; -wire litedramcore_bankmachine6_fifo_out_first; -wire litedramcore_bankmachine6_fifo_out_last; -wire litedramcore_bankmachine6_sink_sink_valid; -wire litedramcore_bankmachine6_sink_sink_ready; -wire litedramcore_bankmachine6_sink_sink_first; -wire litedramcore_bankmachine6_sink_sink_last; -wire litedramcore_bankmachine6_sink_sink_payload_we; -wire [22:0] litedramcore_bankmachine6_sink_sink_payload_addr; -wire litedramcore_bankmachine6_source_source_valid; -wire litedramcore_bankmachine6_source_source_ready; -wire litedramcore_bankmachine6_source_source_first; -wire litedramcore_bankmachine6_source_source_last; -wire litedramcore_bankmachine6_source_source_payload_we; -wire [22:0] litedramcore_bankmachine6_source_source_payload_addr; -wire litedramcore_bankmachine6_pipe_valid_sink_valid; -wire litedramcore_bankmachine6_pipe_valid_sink_ready; -wire litedramcore_bankmachine6_pipe_valid_sink_first; -wire litedramcore_bankmachine6_pipe_valid_sink_last; -wire litedramcore_bankmachine6_pipe_valid_sink_payload_we; -wire [22:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine6_pipe_valid_source_ready; -reg litedramcore_bankmachine6_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine6_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; -reg [22:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 23'd0; -reg [15:0] litedramcore_bankmachine6_row = 16'd0; -reg litedramcore_bankmachine6_row_opened = 1'd0; -wire litedramcore_bankmachine6_row_hit; -reg litedramcore_bankmachine6_row_open = 1'd0; -reg litedramcore_bankmachine6_row_close = 1'd0; -reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine6_twtpcon_valid; +reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine5_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine5_wrport_adr = 4'd0; +wire [25:0] main_litedramcore_bankmachine5_wrport_dat_r; +wire [25:0] main_litedramcore_bankmachine5_wrport_dat_w; +wire main_litedramcore_bankmachine5_wrport_we; +reg main_litedramcore_bankmachine6_auto_precharge = 1'd0; +reg [15:0] main_litedramcore_bankmachine6_cmd_payload_a = 16'd0; +wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba; +reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine6_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine6_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine6_consume = 4'd0; +wire main_litedramcore_bankmachine6_do_read; +wire main_litedramcore_bankmachine6_fifo_in_first; +wire main_litedramcore_bankmachine6_fifo_in_last; +wire [22:0] main_litedramcore_bankmachine6_fifo_in_payload_addr; +wire main_litedramcore_bankmachine6_fifo_in_payload_we; +wire main_litedramcore_bankmachine6_fifo_out_first; +wire main_litedramcore_bankmachine6_fifo_out_last; +wire [22:0] main_litedramcore_bankmachine6_fifo_out_payload_addr; +wire main_litedramcore_bankmachine6_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine6_level = 5'd0; +wire main_litedramcore_bankmachine6_pipe_valid_sink_first; +wire main_litedramcore_bankmachine6_pipe_valid_sink_last; +wire [22:0] main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine6_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine6_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine6_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine6_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine6_pipe_valid_source_last = 1'd0; +reg [22:0] main_litedramcore_bankmachine6_pipe_valid_source_payload_addr = 23'd0; +reg main_litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine6_pipe_valid_source_ready; +reg main_litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine6_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine6_rdport_adr; +wire [25:0] main_litedramcore_bankmachine6_rdport_dat_r; +reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine6_refresh_req; +reg main_litedramcore_bankmachine6_replace = 1'd0; +wire [22:0] main_litedramcore_bankmachine6_req_addr; +wire main_litedramcore_bankmachine6_req_lock; +reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine6_req_ready; +wire main_litedramcore_bankmachine6_req_valid; +reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine6_req_we; +reg [15:0] main_litedramcore_bankmachine6_row = 16'd0; +reg main_litedramcore_bankmachine6_row_close = 1'd0; +reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine6_row_hit; +reg main_litedramcore_bankmachine6_row_open = 1'd0; +reg main_litedramcore_bankmachine6_row_opened = 1'd0; +reg main_litedramcore_bankmachine6_sink_first = 1'd0; +reg main_litedramcore_bankmachine6_sink_last = 1'd0; +wire [22:0] main_litedramcore_bankmachine6_sink_payload_addr; +wire main_litedramcore_bankmachine6_sink_payload_we; +wire main_litedramcore_bankmachine6_sink_ready; +wire main_litedramcore_bankmachine6_sink_sink_first; +wire main_litedramcore_bankmachine6_sink_sink_last; +wire [22:0] main_litedramcore_bankmachine6_sink_sink_payload_addr; +wire main_litedramcore_bankmachine6_sink_sink_payload_we; +wire main_litedramcore_bankmachine6_sink_sink_ready; +wire main_litedramcore_bankmachine6_sink_sink_valid; +wire main_litedramcore_bankmachine6_sink_valid; +wire main_litedramcore_bankmachine6_source_first; +wire main_litedramcore_bankmachine6_source_last; +wire [22:0] main_litedramcore_bankmachine6_source_payload_addr; +wire main_litedramcore_bankmachine6_source_payload_we; +wire main_litedramcore_bankmachine6_source_ready; +wire main_litedramcore_bankmachine6_source_source_first; +wire main_litedramcore_bankmachine6_source_source_last; +wire [22:0] main_litedramcore_bankmachine6_source_source_payload_addr; +wire main_litedramcore_bankmachine6_source_source_payload_we; +wire main_litedramcore_bankmachine6_source_source_ready; +wire main_litedramcore_bankmachine6_source_source_valid; +wire main_litedramcore_bankmachine6_source_valid; +wire [25:0] main_litedramcore_bankmachine6_syncfifo6_din; +wire [25:0] main_litedramcore_bankmachine6_syncfifo6_dout; +wire main_litedramcore_bankmachine6_syncfifo6_re; +wire main_litedramcore_bankmachine6_syncfifo6_readable; +wire main_litedramcore_bankmachine6_syncfifo6_we; +wire main_litedramcore_bankmachine6_syncfifo6_writable; +reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; -wire litedramcore_bankmachine6_trccon_valid; +reg main_litedramcore_bankmachine6_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine6_trascon_valid; +reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0; -wire litedramcore_bankmachine6_trascon_valid; +reg main_litedramcore_bankmachine6_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine6_trccon_valid; +reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine6_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0; -wire litedramcore_bankmachine7_req_valid; -wire litedramcore_bankmachine7_req_ready; -wire litedramcore_bankmachine7_req_we; -wire [22:0] litedramcore_bankmachine7_req_addr; -wire litedramcore_bankmachine7_req_lock; -reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine7_refresh_req; -reg litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg litedramcore_bankmachine7_cmd_valid = 1'd0; -reg litedramcore_bankmachine7_cmd_ready = 1'd0; -reg [15:0] litedramcore_bankmachine7_cmd_payload_a = 16'd0; -wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; -reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine7_auto_precharge = 1'd0; -wire litedramcore_bankmachine7_sink_valid; -wire litedramcore_bankmachine7_sink_ready; -reg litedramcore_bankmachine7_sink_first = 1'd0; -reg litedramcore_bankmachine7_sink_last = 1'd0; -wire litedramcore_bankmachine7_sink_payload_we; -wire [22:0] litedramcore_bankmachine7_sink_payload_addr; -wire litedramcore_bankmachine7_source_valid; -wire litedramcore_bankmachine7_source_ready; -wire litedramcore_bankmachine7_source_first; -wire litedramcore_bankmachine7_source_last; -wire litedramcore_bankmachine7_source_payload_we; -wire [22:0] litedramcore_bankmachine7_source_payload_addr; -wire litedramcore_bankmachine7_syncfifo7_we; -wire litedramcore_bankmachine7_syncfifo7_writable; -wire litedramcore_bankmachine7_syncfifo7_re; -wire litedramcore_bankmachine7_syncfifo7_readable; -wire [25:0] litedramcore_bankmachine7_syncfifo7_din; -wire [25:0] litedramcore_bankmachine7_syncfifo7_dout; -reg [4:0] litedramcore_bankmachine7_level = 5'd0; -reg litedramcore_bankmachine7_replace = 1'd0; -reg [3:0] litedramcore_bankmachine7_produce = 4'd0; -reg [3:0] litedramcore_bankmachine7_consume = 4'd0; -reg [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0; -wire [25:0] litedramcore_bankmachine7_wrport_dat_r; -wire litedramcore_bankmachine7_wrport_we; -wire [25:0] litedramcore_bankmachine7_wrport_dat_w; -wire litedramcore_bankmachine7_do_read; -wire [3:0] litedramcore_bankmachine7_rdport_adr; -wire [25:0] litedramcore_bankmachine7_rdport_dat_r; -wire litedramcore_bankmachine7_fifo_in_payload_we; -wire [22:0] litedramcore_bankmachine7_fifo_in_payload_addr; -wire litedramcore_bankmachine7_fifo_in_first; -wire litedramcore_bankmachine7_fifo_in_last; -wire litedramcore_bankmachine7_fifo_out_payload_we; -wire [22:0] litedramcore_bankmachine7_fifo_out_payload_addr; -wire litedramcore_bankmachine7_fifo_out_first; -wire litedramcore_bankmachine7_fifo_out_last; -wire litedramcore_bankmachine7_sink_sink_valid; -wire litedramcore_bankmachine7_sink_sink_ready; -wire litedramcore_bankmachine7_sink_sink_first; -wire litedramcore_bankmachine7_sink_sink_last; -wire litedramcore_bankmachine7_sink_sink_payload_we; -wire [22:0] litedramcore_bankmachine7_sink_sink_payload_addr; -wire litedramcore_bankmachine7_source_source_valid; -wire litedramcore_bankmachine7_source_source_ready; -wire litedramcore_bankmachine7_source_source_first; -wire litedramcore_bankmachine7_source_source_last; -wire litedramcore_bankmachine7_source_source_payload_we; -wire [22:0] litedramcore_bankmachine7_source_source_payload_addr; -wire litedramcore_bankmachine7_pipe_valid_sink_valid; -wire litedramcore_bankmachine7_pipe_valid_sink_ready; -wire litedramcore_bankmachine7_pipe_valid_sink_first; -wire litedramcore_bankmachine7_pipe_valid_sink_last; -wire litedramcore_bankmachine7_pipe_valid_sink_payload_we; -wire [22:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine7_pipe_valid_source_ready; -reg litedramcore_bankmachine7_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine7_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; -reg [22:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 23'd0; -reg [15:0] litedramcore_bankmachine7_row = 16'd0; -reg litedramcore_bankmachine7_row_opened = 1'd0; -wire litedramcore_bankmachine7_row_hit; -reg litedramcore_bankmachine7_row_open = 1'd0; -reg litedramcore_bankmachine7_row_close = 1'd0; -reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine7_twtpcon_valid; +reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine6_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine6_wrport_adr = 4'd0; +wire [25:0] main_litedramcore_bankmachine6_wrport_dat_r; +wire [25:0] main_litedramcore_bankmachine6_wrport_dat_w; +wire main_litedramcore_bankmachine6_wrport_we; +reg main_litedramcore_bankmachine7_auto_precharge = 1'd0; +reg [15:0] main_litedramcore_bankmachine7_cmd_payload_a = 16'd0; +wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba; +reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine7_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine7_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine7_consume = 4'd0; +wire main_litedramcore_bankmachine7_do_read; +wire main_litedramcore_bankmachine7_fifo_in_first; +wire main_litedramcore_bankmachine7_fifo_in_last; +wire [22:0] main_litedramcore_bankmachine7_fifo_in_payload_addr; +wire main_litedramcore_bankmachine7_fifo_in_payload_we; +wire main_litedramcore_bankmachine7_fifo_out_first; +wire main_litedramcore_bankmachine7_fifo_out_last; +wire [22:0] main_litedramcore_bankmachine7_fifo_out_payload_addr; +wire main_litedramcore_bankmachine7_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine7_level = 5'd0; +wire main_litedramcore_bankmachine7_pipe_valid_sink_first; +wire main_litedramcore_bankmachine7_pipe_valid_sink_last; +wire [22:0] main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine7_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine7_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine7_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine7_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine7_pipe_valid_source_last = 1'd0; +reg [22:0] main_litedramcore_bankmachine7_pipe_valid_source_payload_addr = 23'd0; +reg main_litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine7_pipe_valid_source_ready; +reg main_litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine7_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine7_rdport_adr; +wire [25:0] main_litedramcore_bankmachine7_rdport_dat_r; +reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine7_refresh_req; +reg main_litedramcore_bankmachine7_replace = 1'd0; +wire [22:0] main_litedramcore_bankmachine7_req_addr; +wire main_litedramcore_bankmachine7_req_lock; +reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine7_req_ready; +wire main_litedramcore_bankmachine7_req_valid; +reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine7_req_we; +reg [15:0] main_litedramcore_bankmachine7_row = 16'd0; +reg main_litedramcore_bankmachine7_row_close = 1'd0; +reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine7_row_hit; +reg main_litedramcore_bankmachine7_row_open = 1'd0; +reg main_litedramcore_bankmachine7_row_opened = 1'd0; +reg main_litedramcore_bankmachine7_sink_first = 1'd0; +reg main_litedramcore_bankmachine7_sink_last = 1'd0; +wire [22:0] main_litedramcore_bankmachine7_sink_payload_addr; +wire main_litedramcore_bankmachine7_sink_payload_we; +wire main_litedramcore_bankmachine7_sink_ready; +wire main_litedramcore_bankmachine7_sink_sink_first; +wire main_litedramcore_bankmachine7_sink_sink_last; +wire [22:0] main_litedramcore_bankmachine7_sink_sink_payload_addr; +wire main_litedramcore_bankmachine7_sink_sink_payload_we; +wire main_litedramcore_bankmachine7_sink_sink_ready; +wire main_litedramcore_bankmachine7_sink_sink_valid; +wire main_litedramcore_bankmachine7_sink_valid; +wire main_litedramcore_bankmachine7_source_first; +wire main_litedramcore_bankmachine7_source_last; +wire [22:0] main_litedramcore_bankmachine7_source_payload_addr; +wire main_litedramcore_bankmachine7_source_payload_we; +wire main_litedramcore_bankmachine7_source_ready; +wire main_litedramcore_bankmachine7_source_source_first; +wire main_litedramcore_bankmachine7_source_source_last; +wire [22:0] main_litedramcore_bankmachine7_source_source_payload_addr; +wire main_litedramcore_bankmachine7_source_source_payload_we; +wire main_litedramcore_bankmachine7_source_source_ready; +wire main_litedramcore_bankmachine7_source_source_valid; +wire main_litedramcore_bankmachine7_source_valid; +wire [25:0] main_litedramcore_bankmachine7_syncfifo7_din; +wire [25:0] main_litedramcore_bankmachine7_syncfifo7_dout; +wire main_litedramcore_bankmachine7_syncfifo7_re; +wire main_litedramcore_bankmachine7_syncfifo7_readable; +wire main_litedramcore_bankmachine7_syncfifo7_we; +wire main_litedramcore_bankmachine7_syncfifo7_writable; +reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; -wire litedramcore_bankmachine7_trccon_valid; +reg main_litedramcore_bankmachine7_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine7_trascon_valid; +reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0; -wire litedramcore_bankmachine7_trascon_valid; +reg main_litedramcore_bankmachine7_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine7_trccon_valid; +reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine7_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0; -wire litedramcore_ras_allowed; -wire litedramcore_cas_allowed; -wire [1:0] litedramcore_rdcmdphase; -wire [1:0] litedramcore_wrcmdphase; -reg litedramcore_choose_cmd_want_reads = 1'd0; -reg litedramcore_choose_cmd_want_writes = 1'd0; -reg litedramcore_choose_cmd_want_cmds = 1'd0; -reg litedramcore_choose_cmd_want_activates = 1'd0; -wire litedramcore_choose_cmd_cmd_valid; -reg litedramcore_choose_cmd_cmd_ready = 1'd0; -wire [15:0] litedramcore_choose_cmd_cmd_payload_a; -wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; -reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; -wire litedramcore_choose_cmd_cmd_payload_is_cmd; -wire litedramcore_choose_cmd_cmd_payload_is_read; -wire litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] litedramcore_choose_cmd_valids = 8'd0; -wire [7:0] litedramcore_choose_cmd_request; -reg [2:0] litedramcore_choose_cmd_grant = 3'd0; -wire litedramcore_choose_cmd_ce; -reg litedramcore_choose_req_want_reads = 1'd0; -reg litedramcore_choose_req_want_writes = 1'd0; -reg litedramcore_choose_req_want_cmds = 1'd0; -reg litedramcore_choose_req_want_activates = 1'd0; -wire litedramcore_choose_req_cmd_valid; -reg litedramcore_choose_req_cmd_ready = 1'd0; -wire [15:0] litedramcore_choose_req_cmd_payload_a; -wire [2:0] litedramcore_choose_req_cmd_payload_ba; -reg litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg litedramcore_choose_req_cmd_payload_we = 1'd0; -wire litedramcore_choose_req_cmd_payload_is_cmd; -wire litedramcore_choose_req_cmd_payload_is_read; -wire litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] litedramcore_choose_req_valids = 8'd0; -wire [7:0] litedramcore_choose_req_request; -reg [2:0] litedramcore_choose_req_grant = 3'd0; -wire litedramcore_choose_req_ce; -reg [15:0] litedramcore_nop_a = 16'd0; -reg [2:0] litedramcore_nop_ba = 3'd0; -reg [1:0] litedramcore_steerer_sel0 = 2'd0; -reg [1:0] litedramcore_steerer_sel1 = 2'd0; -reg [1:0] litedramcore_steerer_sel2 = 2'd0; -reg [1:0] litedramcore_steerer_sel3 = 2'd0; -reg litedramcore_steerer0 = 1'd1; -reg litedramcore_steerer1 = 1'd1; -reg litedramcore_steerer2 = 1'd1; -reg litedramcore_steerer3 = 1'd1; -reg litedramcore_steerer4 = 1'd1; -reg litedramcore_steerer5 = 1'd1; -reg litedramcore_steerer6 = 1'd1; -reg litedramcore_steerer7 = 1'd1; -wire litedramcore_trrdcon_valid; +reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine7_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine7_wrport_adr = 4'd0; +wire [25:0] main_litedramcore_bankmachine7_wrport_dat_r; +wire [25:0] main_litedramcore_bankmachine7_wrport_dat_w; +wire main_litedramcore_bankmachine7_wrport_we; +wire main_litedramcore_cas_allowed; +wire main_litedramcore_choose_cmd_ce; +wire [15:0] main_litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba; +reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +wire main_litedramcore_choose_cmd_cmd_payload_is_cmd; +wire main_litedramcore_choose_cmd_cmd_payload_is_read; +wire main_litedramcore_choose_cmd_cmd_payload_is_write; +reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0; +reg main_litedramcore_choose_cmd_cmd_ready = 1'd0; +wire main_litedramcore_choose_cmd_cmd_valid; +reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0; +wire [7:0] main_litedramcore_choose_cmd_request; +reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0; +reg main_litedramcore_choose_cmd_want_activates = 1'd0; +reg main_litedramcore_choose_cmd_want_cmds = 1'd0; +reg main_litedramcore_choose_cmd_want_reads = 1'd0; +reg main_litedramcore_choose_cmd_want_writes = 1'd0; +wire main_litedramcore_choose_req_ce; +wire [15:0] main_litedramcore_choose_req_cmd_payload_a; +wire [2:0] main_litedramcore_choose_req_cmd_payload_ba; +reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0; +wire main_litedramcore_choose_req_cmd_payload_is_cmd; +wire main_litedramcore_choose_req_cmd_payload_is_read; +wire main_litedramcore_choose_req_cmd_payload_is_write; +reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_we = 1'd0; +reg main_litedramcore_choose_req_cmd_ready = 1'd0; +wire main_litedramcore_choose_req_cmd_valid; +reg [2:0] main_litedramcore_choose_req_grant = 3'd0; +wire [7:0] main_litedramcore_choose_req_request; +reg [7:0] main_litedramcore_choose_req_valids = 8'd0; +reg main_litedramcore_choose_req_want_activates = 1'd0; +reg main_litedramcore_choose_req_want_cmds = 1'd0; +reg main_litedramcore_choose_req_want_reads = 1'd0; +reg main_litedramcore_choose_req_want_writes = 1'd0; +wire main_litedramcore_cke; +reg main_litedramcore_cmd_last = 1'd0; +reg [15:0] main_litedramcore_cmd_payload_a = 16'd0; +reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0; +reg main_litedramcore_cmd_payload_cas = 1'd0; +reg main_litedramcore_cmd_payload_is_read = 1'd0; +reg main_litedramcore_cmd_payload_is_write = 1'd0; +reg main_litedramcore_cmd_payload_ras = 1'd0; +reg main_litedramcore_cmd_payload_we = 1'd0; +reg main_litedramcore_cmd_ready = 1'd0; +reg main_litedramcore_cmd_valid = 1'd0; +reg main_litedramcore_csr_dfi_p0_act_n = 1'd1; +wire [15:0] main_litedramcore_csr_dfi_p0_address; +wire [2:0] main_litedramcore_csr_dfi_p0_bank; +reg main_litedramcore_csr_dfi_p0_cas_n = 1'd1; +reg main_litedramcore_csr_dfi_p0_cke = 1'd0; +reg main_litedramcore_csr_dfi_p0_cs_n = 1'd1; +reg main_litedramcore_csr_dfi_p0_odt = 1'd0; +reg main_litedramcore_csr_dfi_p0_ras_n = 1'd1; +reg [31:0] main_litedramcore_csr_dfi_p0_rddata = 32'd0; +wire main_litedramcore_csr_dfi_p0_rddata_en; +reg main_litedramcore_csr_dfi_p0_rddata_valid = 1'd0; +wire main_litedramcore_csr_dfi_p0_reset_n; +reg main_litedramcore_csr_dfi_p0_we_n = 1'd1; +wire [31:0] main_litedramcore_csr_dfi_p0_wrdata; +wire main_litedramcore_csr_dfi_p0_wrdata_en; +wire [3:0] main_litedramcore_csr_dfi_p0_wrdata_mask; +reg main_litedramcore_csr_dfi_p1_act_n = 1'd1; +wire [15:0] main_litedramcore_csr_dfi_p1_address; +wire [2:0] main_litedramcore_csr_dfi_p1_bank; +reg main_litedramcore_csr_dfi_p1_cas_n = 1'd1; +reg main_litedramcore_csr_dfi_p1_cke = 1'd0; +reg main_litedramcore_csr_dfi_p1_cs_n = 1'd1; +reg main_litedramcore_csr_dfi_p1_odt = 1'd0; +reg main_litedramcore_csr_dfi_p1_ras_n = 1'd1; +reg [31:0] main_litedramcore_csr_dfi_p1_rddata = 32'd0; +wire main_litedramcore_csr_dfi_p1_rddata_en; +reg main_litedramcore_csr_dfi_p1_rddata_valid = 1'd0; +wire main_litedramcore_csr_dfi_p1_reset_n; +reg main_litedramcore_csr_dfi_p1_we_n = 1'd1; +wire [31:0] main_litedramcore_csr_dfi_p1_wrdata; +wire main_litedramcore_csr_dfi_p1_wrdata_en; +wire [3:0] main_litedramcore_csr_dfi_p1_wrdata_mask; +reg main_litedramcore_csr_dfi_p2_act_n = 1'd1; +wire [15:0] main_litedramcore_csr_dfi_p2_address; +wire [2:0] main_litedramcore_csr_dfi_p2_bank; +reg main_litedramcore_csr_dfi_p2_cas_n = 1'd1; +reg main_litedramcore_csr_dfi_p2_cke = 1'd0; +reg main_litedramcore_csr_dfi_p2_cs_n = 1'd1; +reg main_litedramcore_csr_dfi_p2_odt = 1'd0; +reg main_litedramcore_csr_dfi_p2_ras_n = 1'd1; +reg [31:0] main_litedramcore_csr_dfi_p2_rddata = 32'd0; +wire main_litedramcore_csr_dfi_p2_rddata_en; +reg main_litedramcore_csr_dfi_p2_rddata_valid = 1'd0; +wire main_litedramcore_csr_dfi_p2_reset_n; +reg main_litedramcore_csr_dfi_p2_we_n = 1'd1; +wire [31:0] main_litedramcore_csr_dfi_p2_wrdata; +wire main_litedramcore_csr_dfi_p2_wrdata_en; +wire [3:0] main_litedramcore_csr_dfi_p2_wrdata_mask; +reg main_litedramcore_csr_dfi_p3_act_n = 1'd1; +wire [15:0] main_litedramcore_csr_dfi_p3_address; +wire [2:0] main_litedramcore_csr_dfi_p3_bank; +reg main_litedramcore_csr_dfi_p3_cas_n = 1'd1; +reg main_litedramcore_csr_dfi_p3_cke = 1'd0; +reg main_litedramcore_csr_dfi_p3_cs_n = 1'd1; +reg main_litedramcore_csr_dfi_p3_odt = 1'd0; +reg main_litedramcore_csr_dfi_p3_ras_n = 1'd1; +reg [31:0] main_litedramcore_csr_dfi_p3_rddata = 32'd0; +wire main_litedramcore_csr_dfi_p3_rddata_en; +reg main_litedramcore_csr_dfi_p3_rddata_valid = 1'd0; +wire main_litedramcore_csr_dfi_p3_reset_n; +reg main_litedramcore_csr_dfi_p3_we_n = 1'd1; +wire [31:0] main_litedramcore_csr_dfi_p3_wrdata; +wire main_litedramcore_csr_dfi_p3_wrdata_en; +wire [3:0] main_litedramcore_csr_dfi_p3_wrdata_mask; +reg main_litedramcore_dfi_p0_act_n = 1'd1; +reg [15:0] main_litedramcore_dfi_p0_address = 16'd0; +reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0; +reg main_litedramcore_dfi_p0_cas_n = 1'd1; +wire main_litedramcore_dfi_p0_cke; +reg main_litedramcore_dfi_p0_cs_n = 1'd1; +wire main_litedramcore_dfi_p0_odt; +reg main_litedramcore_dfi_p0_ras_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p0_rddata; +reg main_litedramcore_dfi_p0_rddata_en = 1'd0; +wire main_litedramcore_dfi_p0_rddata_valid; +wire main_litedramcore_dfi_p0_reset_n; +reg main_litedramcore_dfi_p0_we_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p0_wrdata; +reg main_litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p0_wrdata_mask; +reg main_litedramcore_dfi_p1_act_n = 1'd1; +reg [15:0] main_litedramcore_dfi_p1_address = 16'd0; +reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0; +reg main_litedramcore_dfi_p1_cas_n = 1'd1; +wire main_litedramcore_dfi_p1_cke; +reg main_litedramcore_dfi_p1_cs_n = 1'd1; +wire main_litedramcore_dfi_p1_odt; +reg main_litedramcore_dfi_p1_ras_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p1_rddata; +reg main_litedramcore_dfi_p1_rddata_en = 1'd0; +wire main_litedramcore_dfi_p1_rddata_valid; +wire main_litedramcore_dfi_p1_reset_n; +reg main_litedramcore_dfi_p1_we_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p1_wrdata; +reg main_litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p1_wrdata_mask; +reg main_litedramcore_dfi_p2_act_n = 1'd1; +reg [15:0] main_litedramcore_dfi_p2_address = 16'd0; +reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0; +reg main_litedramcore_dfi_p2_cas_n = 1'd1; +wire main_litedramcore_dfi_p2_cke; +reg main_litedramcore_dfi_p2_cs_n = 1'd1; +wire main_litedramcore_dfi_p2_odt; +reg main_litedramcore_dfi_p2_ras_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p2_rddata; +reg main_litedramcore_dfi_p2_rddata_en = 1'd0; +wire main_litedramcore_dfi_p2_rddata_valid; +wire main_litedramcore_dfi_p2_reset_n; +reg main_litedramcore_dfi_p2_we_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p2_wrdata; +reg main_litedramcore_dfi_p2_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p2_wrdata_mask; +reg main_litedramcore_dfi_p3_act_n = 1'd1; +reg [15:0] main_litedramcore_dfi_p3_address = 16'd0; +reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0; +reg main_litedramcore_dfi_p3_cas_n = 1'd1; +wire main_litedramcore_dfi_p3_cke; +reg main_litedramcore_dfi_p3_cs_n = 1'd1; +wire main_litedramcore_dfi_p3_odt; +reg main_litedramcore_dfi_p3_ras_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p3_rddata; +reg main_litedramcore_dfi_p3_rddata_en = 1'd0; +wire main_litedramcore_dfi_p3_rddata_valid; +wire main_litedramcore_dfi_p3_reset_n; +reg main_litedramcore_dfi_p3_we_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p3_wrdata; +reg main_litedramcore_dfi_p3_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p3_wrdata_mask; +reg main_litedramcore_en0 = 1'd0; +reg main_litedramcore_en1 = 1'd0; +reg main_litedramcore_ext_dfi_p0_act_n = 1'd1; +reg [15:0] main_litedramcore_ext_dfi_p0_address = 16'd0; +reg [2:0] main_litedramcore_ext_dfi_p0_bank = 3'd0; +reg main_litedramcore_ext_dfi_p0_cas_n = 1'd1; +reg main_litedramcore_ext_dfi_p0_cke = 1'd0; +reg main_litedramcore_ext_dfi_p0_cs_n = 1'd1; +reg main_litedramcore_ext_dfi_p0_odt = 1'd0; +reg main_litedramcore_ext_dfi_p0_ras_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p0_rddata = 32'd0; +reg main_litedramcore_ext_dfi_p0_rddata_en = 1'd0; +reg main_litedramcore_ext_dfi_p0_rddata_valid = 1'd0; +reg main_litedramcore_ext_dfi_p0_reset_n = 1'd0; +reg main_litedramcore_ext_dfi_p0_we_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p0_wrdata = 32'd0; +reg main_litedramcore_ext_dfi_p0_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_ext_dfi_p0_wrdata_mask = 4'd0; +reg main_litedramcore_ext_dfi_p1_act_n = 1'd1; +reg [15:0] main_litedramcore_ext_dfi_p1_address = 16'd0; +reg [2:0] main_litedramcore_ext_dfi_p1_bank = 3'd0; +reg main_litedramcore_ext_dfi_p1_cas_n = 1'd1; +reg main_litedramcore_ext_dfi_p1_cke = 1'd0; +reg main_litedramcore_ext_dfi_p1_cs_n = 1'd1; +reg main_litedramcore_ext_dfi_p1_odt = 1'd0; +reg main_litedramcore_ext_dfi_p1_ras_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p1_rddata = 32'd0; +reg main_litedramcore_ext_dfi_p1_rddata_en = 1'd0; +reg main_litedramcore_ext_dfi_p1_rddata_valid = 1'd0; +reg main_litedramcore_ext_dfi_p1_reset_n = 1'd0; +reg main_litedramcore_ext_dfi_p1_we_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p1_wrdata = 32'd0; +reg main_litedramcore_ext_dfi_p1_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_ext_dfi_p1_wrdata_mask = 4'd0; +reg main_litedramcore_ext_dfi_p2_act_n = 1'd1; +reg [15:0] main_litedramcore_ext_dfi_p2_address = 16'd0; +reg [2:0] main_litedramcore_ext_dfi_p2_bank = 3'd0; +reg main_litedramcore_ext_dfi_p2_cas_n = 1'd1; +reg main_litedramcore_ext_dfi_p2_cke = 1'd0; +reg main_litedramcore_ext_dfi_p2_cs_n = 1'd1; +reg main_litedramcore_ext_dfi_p2_odt = 1'd0; +reg main_litedramcore_ext_dfi_p2_ras_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p2_rddata = 32'd0; +reg main_litedramcore_ext_dfi_p2_rddata_en = 1'd0; +reg main_litedramcore_ext_dfi_p2_rddata_valid = 1'd0; +reg main_litedramcore_ext_dfi_p2_reset_n = 1'd0; +reg main_litedramcore_ext_dfi_p2_we_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p2_wrdata = 32'd0; +reg main_litedramcore_ext_dfi_p2_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_ext_dfi_p2_wrdata_mask = 4'd0; +reg main_litedramcore_ext_dfi_p3_act_n = 1'd1; +reg [15:0] main_litedramcore_ext_dfi_p3_address = 16'd0; +reg [2:0] main_litedramcore_ext_dfi_p3_bank = 3'd0; +reg main_litedramcore_ext_dfi_p3_cas_n = 1'd1; +reg main_litedramcore_ext_dfi_p3_cke = 1'd0; +reg main_litedramcore_ext_dfi_p3_cs_n = 1'd1; +reg main_litedramcore_ext_dfi_p3_odt = 1'd0; +reg main_litedramcore_ext_dfi_p3_ras_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p3_rddata = 32'd0; +reg main_litedramcore_ext_dfi_p3_rddata_en = 1'd0; +reg main_litedramcore_ext_dfi_p3_rddata_valid = 1'd0; +reg main_litedramcore_ext_dfi_p3_reset_n = 1'd0; +reg main_litedramcore_ext_dfi_p3_we_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p3_wrdata = 32'd0; +reg main_litedramcore_ext_dfi_p3_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_ext_dfi_p3_wrdata_mask = 4'd0; +reg main_litedramcore_ext_dfi_sel = 1'd0; +wire main_litedramcore_go_to_refresh; +wire [22:0] main_litedramcore_interface_bank0_addr; +wire main_litedramcore_interface_bank0_lock; +wire main_litedramcore_interface_bank0_rdata_valid; +wire main_litedramcore_interface_bank0_ready; +wire main_litedramcore_interface_bank0_valid; +wire main_litedramcore_interface_bank0_wdata_ready; +wire main_litedramcore_interface_bank0_we; +wire [22:0] main_litedramcore_interface_bank1_addr; +wire main_litedramcore_interface_bank1_lock; +wire main_litedramcore_interface_bank1_rdata_valid; +wire main_litedramcore_interface_bank1_ready; +wire main_litedramcore_interface_bank1_valid; +wire main_litedramcore_interface_bank1_wdata_ready; +wire main_litedramcore_interface_bank1_we; +wire [22:0] main_litedramcore_interface_bank2_addr; +wire main_litedramcore_interface_bank2_lock; +wire main_litedramcore_interface_bank2_rdata_valid; +wire main_litedramcore_interface_bank2_ready; +wire main_litedramcore_interface_bank2_valid; +wire main_litedramcore_interface_bank2_wdata_ready; +wire main_litedramcore_interface_bank2_we; +wire [22:0] main_litedramcore_interface_bank3_addr; +wire main_litedramcore_interface_bank3_lock; +wire main_litedramcore_interface_bank3_rdata_valid; +wire main_litedramcore_interface_bank3_ready; +wire main_litedramcore_interface_bank3_valid; +wire main_litedramcore_interface_bank3_wdata_ready; +wire main_litedramcore_interface_bank3_we; +wire [22:0] main_litedramcore_interface_bank4_addr; +wire main_litedramcore_interface_bank4_lock; +wire main_litedramcore_interface_bank4_rdata_valid; +wire main_litedramcore_interface_bank4_ready; +wire main_litedramcore_interface_bank4_valid; +wire main_litedramcore_interface_bank4_wdata_ready; +wire main_litedramcore_interface_bank4_we; +wire [22:0] main_litedramcore_interface_bank5_addr; +wire main_litedramcore_interface_bank5_lock; +wire main_litedramcore_interface_bank5_rdata_valid; +wire main_litedramcore_interface_bank5_ready; +wire main_litedramcore_interface_bank5_valid; +wire main_litedramcore_interface_bank5_wdata_ready; +wire main_litedramcore_interface_bank5_we; +wire [22:0] main_litedramcore_interface_bank6_addr; +wire main_litedramcore_interface_bank6_lock; +wire main_litedramcore_interface_bank6_rdata_valid; +wire main_litedramcore_interface_bank6_ready; +wire main_litedramcore_interface_bank6_valid; +wire main_litedramcore_interface_bank6_wdata_ready; +wire main_litedramcore_interface_bank6_we; +wire [22:0] main_litedramcore_interface_bank7_addr; +wire main_litedramcore_interface_bank7_lock; +wire main_litedramcore_interface_bank7_rdata_valid; +wire main_litedramcore_interface_bank7_ready; +wire main_litedramcore_interface_bank7_valid; +wire main_litedramcore_interface_bank7_wdata_ready; +wire main_litedramcore_interface_bank7_we; +wire [127:0] main_litedramcore_interface_rdata; +reg [127:0] main_litedramcore_interface_wdata = 128'd0; +reg [15:0] main_litedramcore_interface_wdata_we = 16'd0; +reg main_litedramcore_master_p0_act_n = 1'd1; +reg [15:0] main_litedramcore_master_p0_address = 16'd0; +reg [2:0] main_litedramcore_master_p0_bank = 3'd0; +reg main_litedramcore_master_p0_cas_n = 1'd1; +reg main_litedramcore_master_p0_cke = 1'd0; +reg main_litedramcore_master_p0_cs_n = 1'd1; +reg main_litedramcore_master_p0_odt = 1'd0; +reg main_litedramcore_master_p0_ras_n = 1'd1; +wire [31:0] main_litedramcore_master_p0_rddata; +reg main_litedramcore_master_p0_rddata_en = 1'd0; +wire main_litedramcore_master_p0_rddata_valid; +reg main_litedramcore_master_p0_reset_n = 1'd0; +reg main_litedramcore_master_p0_we_n = 1'd1; +reg [31:0] main_litedramcore_master_p0_wrdata = 32'd0; +reg main_litedramcore_master_p0_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0; +reg main_litedramcore_master_p1_act_n = 1'd1; +reg [15:0] main_litedramcore_master_p1_address = 16'd0; +reg [2:0] main_litedramcore_master_p1_bank = 3'd0; +reg main_litedramcore_master_p1_cas_n = 1'd1; +reg main_litedramcore_master_p1_cke = 1'd0; +reg main_litedramcore_master_p1_cs_n = 1'd1; +reg main_litedramcore_master_p1_odt = 1'd0; +reg main_litedramcore_master_p1_ras_n = 1'd1; +wire [31:0] main_litedramcore_master_p1_rddata; +reg main_litedramcore_master_p1_rddata_en = 1'd0; +wire main_litedramcore_master_p1_rddata_valid; +reg main_litedramcore_master_p1_reset_n = 1'd0; +reg main_litedramcore_master_p1_we_n = 1'd1; +reg [31:0] main_litedramcore_master_p1_wrdata = 32'd0; +reg main_litedramcore_master_p1_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0; +reg main_litedramcore_master_p2_act_n = 1'd1; +reg [15:0] main_litedramcore_master_p2_address = 16'd0; +reg [2:0] main_litedramcore_master_p2_bank = 3'd0; +reg main_litedramcore_master_p2_cas_n = 1'd1; +reg main_litedramcore_master_p2_cke = 1'd0; +reg main_litedramcore_master_p2_cs_n = 1'd1; +reg main_litedramcore_master_p2_odt = 1'd0; +reg main_litedramcore_master_p2_ras_n = 1'd1; +wire [31:0] main_litedramcore_master_p2_rddata; +reg main_litedramcore_master_p2_rddata_en = 1'd0; +wire main_litedramcore_master_p2_rddata_valid; +reg main_litedramcore_master_p2_reset_n = 1'd0; +reg main_litedramcore_master_p2_we_n = 1'd1; +reg [31:0] main_litedramcore_master_p2_wrdata = 32'd0; +reg main_litedramcore_master_p2_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0; +reg main_litedramcore_master_p3_act_n = 1'd1; +reg [15:0] main_litedramcore_master_p3_address = 16'd0; +reg [2:0] main_litedramcore_master_p3_bank = 3'd0; +reg main_litedramcore_master_p3_cas_n = 1'd1; +reg main_litedramcore_master_p3_cke = 1'd0; +reg main_litedramcore_master_p3_cs_n = 1'd1; +reg main_litedramcore_master_p3_odt = 1'd0; +reg main_litedramcore_master_p3_ras_n = 1'd1; +wire [31:0] main_litedramcore_master_p3_rddata; +reg main_litedramcore_master_p3_rddata_en = 1'd0; +wire main_litedramcore_master_p3_rddata_valid; +reg main_litedramcore_master_p3_reset_n = 1'd0; +reg main_litedramcore_master_p3_we_n = 1'd1; +reg [31:0] main_litedramcore_master_p3_wrdata = 32'd0; +reg main_litedramcore_master_p3_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0; +wire main_litedramcore_max_time0; +wire main_litedramcore_max_time1; +reg [15:0] main_litedramcore_nop_a = 16'd0; +reg [2:0] main_litedramcore_nop_ba = 3'd0; +wire [1:0] main_litedramcore_nphases; +wire main_litedramcore_odt; +reg main_litedramcore_phaseinjector0_address_re = 1'd0; +reg [15:0] main_litedramcore_phaseinjector0_address_storage = 16'd0; +reg main_litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0; +wire main_litedramcore_phaseinjector0_command_issue_r; +reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector0_command_re = 1'd0; +reg [7:0] main_litedramcore_phaseinjector0_command_storage = 8'd0; +wire main_litedramcore_phaseinjector0_csrfield_cas; +wire main_litedramcore_phaseinjector0_csrfield_cs; +wire main_litedramcore_phaseinjector0_csrfield_cs_bottom; +wire main_litedramcore_phaseinjector0_csrfield_cs_top; +wire main_litedramcore_phaseinjector0_csrfield_ras; +wire main_litedramcore_phaseinjector0_csrfield_rden; +wire main_litedramcore_phaseinjector0_csrfield_we; +wire main_litedramcore_phaseinjector0_csrfield_wren; +reg main_litedramcore_phaseinjector0_rddata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector0_rddata_we; +reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector1_address_re = 1'd0; +reg [15:0] main_litedramcore_phaseinjector1_address_storage = 16'd0; +reg main_litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0; +wire main_litedramcore_phaseinjector1_command_issue_r; +reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector1_command_re = 1'd0; +reg [7:0] main_litedramcore_phaseinjector1_command_storage = 8'd0; +wire main_litedramcore_phaseinjector1_csrfield_cas; +wire main_litedramcore_phaseinjector1_csrfield_cs; +wire main_litedramcore_phaseinjector1_csrfield_cs_bottom; +wire main_litedramcore_phaseinjector1_csrfield_cs_top; +wire main_litedramcore_phaseinjector1_csrfield_ras; +wire main_litedramcore_phaseinjector1_csrfield_rden; +wire main_litedramcore_phaseinjector1_csrfield_we; +wire main_litedramcore_phaseinjector1_csrfield_wren; +reg main_litedramcore_phaseinjector1_rddata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector1_rddata_we; +reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector2_address_re = 1'd0; +reg [15:0] main_litedramcore_phaseinjector2_address_storage = 16'd0; +reg main_litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0; +wire main_litedramcore_phaseinjector2_command_issue_r; +reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector2_command_re = 1'd0; +reg [7:0] main_litedramcore_phaseinjector2_command_storage = 8'd0; +wire main_litedramcore_phaseinjector2_csrfield_cas; +wire main_litedramcore_phaseinjector2_csrfield_cs; +wire main_litedramcore_phaseinjector2_csrfield_cs_bottom; +wire main_litedramcore_phaseinjector2_csrfield_cs_top; +wire main_litedramcore_phaseinjector2_csrfield_ras; +wire main_litedramcore_phaseinjector2_csrfield_rden; +wire main_litedramcore_phaseinjector2_csrfield_we; +wire main_litedramcore_phaseinjector2_csrfield_wren; +reg main_litedramcore_phaseinjector2_rddata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector2_rddata_we; +reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector3_address_re = 1'd0; +reg [15:0] main_litedramcore_phaseinjector3_address_storage = 16'd0; +reg main_litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0; +wire main_litedramcore_phaseinjector3_command_issue_r; +reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector3_command_re = 1'd0; +reg [7:0] main_litedramcore_phaseinjector3_command_storage = 8'd0; +wire main_litedramcore_phaseinjector3_csrfield_cas; +wire main_litedramcore_phaseinjector3_csrfield_cs; +wire main_litedramcore_phaseinjector3_csrfield_cs_bottom; +wire main_litedramcore_phaseinjector3_csrfield_cs_top; +wire main_litedramcore_phaseinjector3_csrfield_ras; +wire main_litedramcore_phaseinjector3_csrfield_rden; +wire main_litedramcore_phaseinjector3_csrfield_we; +wire main_litedramcore_phaseinjector3_csrfield_wren; +reg main_litedramcore_phaseinjector3_rddata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector3_rddata_we; +reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0; +reg main_litedramcore_postponer_count = 1'd0; +wire main_litedramcore_postponer_req_i; +reg main_litedramcore_postponer_req_o = 1'd0; +wire main_litedramcore_ras_allowed; +wire [1:0] main_litedramcore_rdphase; +reg main_litedramcore_re = 1'd0; +wire main_litedramcore_read_available; +wire main_litedramcore_reset_n; +wire main_litedramcore_sel; +reg main_litedramcore_sequencer_count = 1'd0; +wire main_litedramcore_sequencer_done0; +reg main_litedramcore_sequencer_done1 = 1'd0; +reg main_litedramcore_sequencer_start0 = 1'd0; +wire main_litedramcore_sequencer_start1; +reg [6:0] main_litedramcore_sequencer_trigger = 7'd0; +wire main_litedramcore_slave_p0_act_n; +wire [15:0] main_litedramcore_slave_p0_address; +wire [2:0] main_litedramcore_slave_p0_bank; +wire main_litedramcore_slave_p0_cas_n; +wire main_litedramcore_slave_p0_cke; +wire main_litedramcore_slave_p0_cs_n; +wire main_litedramcore_slave_p0_odt; +wire main_litedramcore_slave_p0_ras_n; +reg [31:0] main_litedramcore_slave_p0_rddata = 32'd0; +wire main_litedramcore_slave_p0_rddata_en; +reg main_litedramcore_slave_p0_rddata_valid = 1'd0; +wire main_litedramcore_slave_p0_reset_n; +wire main_litedramcore_slave_p0_we_n; +wire [31:0] main_litedramcore_slave_p0_wrdata; +wire main_litedramcore_slave_p0_wrdata_en; +wire [3:0] main_litedramcore_slave_p0_wrdata_mask; +wire main_litedramcore_slave_p1_act_n; +wire [15:0] main_litedramcore_slave_p1_address; +wire [2:0] main_litedramcore_slave_p1_bank; +wire main_litedramcore_slave_p1_cas_n; +wire main_litedramcore_slave_p1_cke; +wire main_litedramcore_slave_p1_cs_n; +wire main_litedramcore_slave_p1_odt; +wire main_litedramcore_slave_p1_ras_n; +reg [31:0] main_litedramcore_slave_p1_rddata = 32'd0; +wire main_litedramcore_slave_p1_rddata_en; +reg main_litedramcore_slave_p1_rddata_valid = 1'd0; +wire main_litedramcore_slave_p1_reset_n; +wire main_litedramcore_slave_p1_we_n; +wire [31:0] main_litedramcore_slave_p1_wrdata; +wire main_litedramcore_slave_p1_wrdata_en; +wire [3:0] main_litedramcore_slave_p1_wrdata_mask; +wire main_litedramcore_slave_p2_act_n; +wire [15:0] main_litedramcore_slave_p2_address; +wire [2:0] main_litedramcore_slave_p2_bank; +wire main_litedramcore_slave_p2_cas_n; +wire main_litedramcore_slave_p2_cke; +wire main_litedramcore_slave_p2_cs_n; +wire main_litedramcore_slave_p2_odt; +wire main_litedramcore_slave_p2_ras_n; +reg [31:0] main_litedramcore_slave_p2_rddata = 32'd0; +wire main_litedramcore_slave_p2_rddata_en; +reg main_litedramcore_slave_p2_rddata_valid = 1'd0; +wire main_litedramcore_slave_p2_reset_n; +wire main_litedramcore_slave_p2_we_n; +wire [31:0] main_litedramcore_slave_p2_wrdata; +wire main_litedramcore_slave_p2_wrdata_en; +wire [3:0] main_litedramcore_slave_p2_wrdata_mask; +wire main_litedramcore_slave_p3_act_n; +wire [15:0] main_litedramcore_slave_p3_address; +wire [2:0] main_litedramcore_slave_p3_bank; +wire main_litedramcore_slave_p3_cas_n; +wire main_litedramcore_slave_p3_cke; +wire main_litedramcore_slave_p3_cs_n; +wire main_litedramcore_slave_p3_odt; +wire main_litedramcore_slave_p3_ras_n; +reg [31:0] main_litedramcore_slave_p3_rddata = 32'd0; +wire main_litedramcore_slave_p3_rddata_en; +reg main_litedramcore_slave_p3_rddata_valid = 1'd0; +wire main_litedramcore_slave_p3_reset_n; +wire main_litedramcore_slave_p3_we_n; +wire [31:0] main_litedramcore_slave_p3_wrdata; +wire main_litedramcore_slave_p3_wrdata_en; +wire [3:0] main_litedramcore_slave_p3_wrdata_mask; +reg [1:0] main_litedramcore_steerer0 = 2'd0; +reg [1:0] main_litedramcore_steerer1 = 2'd0; +reg main_litedramcore_steerer10 = 1'd1; +reg main_litedramcore_steerer11 = 1'd1; +reg [1:0] main_litedramcore_steerer2 = 2'd0; +reg [1:0] main_litedramcore_steerer3 = 2'd0; +reg main_litedramcore_steerer4 = 1'd1; +reg main_litedramcore_steerer5 = 1'd1; +reg main_litedramcore_steerer6 = 1'd1; +reg main_litedramcore_steerer7 = 1'd1; +reg main_litedramcore_steerer8 = 1'd1; +reg main_litedramcore_steerer9 = 1'd1; +reg [3:0] main_litedramcore_storage = 4'd1; +reg main_litedramcore_tccdcon_count = 1'd0; (* dont_touch = "true" *) -reg litedramcore_trrdcon_ready = 1'd0; -reg litedramcore_trrdcon_count = 1'd0; -wire litedramcore_tfawcon_valid; +reg main_litedramcore_tccdcon_ready = 1'd0; +wire main_litedramcore_tccdcon_valid; +wire [2:0] main_litedramcore_tfawcon_count; (* dont_touch = "true" *) -reg litedramcore_tfawcon_ready = 1'd1; -wire [2:0] litedramcore_tfawcon_count; -reg [4:0] litedramcore_tfawcon_window = 5'd0; -wire litedramcore_tccdcon_valid; +reg main_litedramcore_tfawcon_ready = 1'd1; +wire main_litedramcore_tfawcon_valid; +reg [4:0] main_litedramcore_tfawcon_window = 5'd0; +reg [4:0] main_litedramcore_time0 = 5'd0; +reg [3:0] main_litedramcore_time1 = 4'd0; +wire [9:0] main_litedramcore_timer_count0; +reg [9:0] main_litedramcore_timer_count1 = 10'd781; +wire main_litedramcore_timer_done0; +wire main_litedramcore_timer_done1; +wire main_litedramcore_timer_wait; +reg main_litedramcore_trrdcon_count = 1'd0; (* dont_touch = "true" *) -reg litedramcore_tccdcon_ready = 1'd0; -reg litedramcore_tccdcon_count = 1'd0; -wire litedramcore_twtrcon_valid; +reg main_litedramcore_trrdcon_ready = 1'd0; +wire main_litedramcore_trrdcon_valid; +reg [2:0] main_litedramcore_twtrcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_twtrcon_ready = 1'd0; -reg [2:0] litedramcore_twtrcon_count = 3'd0; -wire litedramcore_read_available; -wire litedramcore_write_available; -reg litedramcore_en0 = 1'd0; -wire litedramcore_max_time0; -reg [4:0] litedramcore_time0 = 5'd0; -reg litedramcore_en1 = 1'd0; -wire litedramcore_max_time1; -reg [3:0] litedramcore_time1 = 4'd0; -wire litedramcore_go_to_refresh; -reg init_done_storage = 1'd0; -reg init_done_re = 1'd0; -reg init_error_storage = 1'd0; -reg init_error_re = 1'd0; -wire [29:0] wb_bus_adr; -wire [31:0] wb_bus_dat_w; -wire [31:0] wb_bus_dat_r; -wire [3:0] wb_bus_sel; -wire wb_bus_cyc; -wire wb_bus_stb; -wire wb_bus_ack; -wire wb_bus_we; -wire [2:0] wb_bus_cti; -wire [1:0] wb_bus_bte; -wire wb_bus_err; -wire user_enable; -wire user_port_cmd_valid; -wire user_port_cmd_ready; -wire user_port_cmd_payload_we; -wire [25:0] user_port_cmd_payload_addr; -wire user_port_wdata_valid; -wire user_port_wdata_ready; -wire [127:0] user_port_wdata_payload_data; -wire [15:0] user_port_wdata_payload_we; -wire user_port_rdata_valid; -wire user_port_rdata_ready; -wire [127:0] user_port_rdata_payload_data; -reg [13:0] litedramcore_adr = 14'd0; -reg litedramcore_we = 1'd0; -reg [31:0] litedramcore_dat_w = 32'd0; -wire [31:0] litedramcore_dat_r; -wire [29:0] litedramcore_wishbone_adr; -wire [31:0] litedramcore_wishbone_dat_w; -reg [31:0] litedramcore_wishbone_dat_r = 32'd0; -wire [3:0] litedramcore_wishbone_sel; -wire litedramcore_wishbone_cyc; -wire litedramcore_wishbone_stb; -reg litedramcore_wishbone_ack = 1'd0; -wire litedramcore_wishbone_we; -wire [2:0] litedramcore_wishbone_cti; -wire [1:0] litedramcore_wishbone_bte; -reg litedramcore_wishbone_err = 1'd0; -wire [13:0] interface0_bank_bus_adr; -wire interface0_bank_bus_we; -wire [31:0] interface0_bank_bus_dat_w; -reg [31:0] interface0_bank_bus_dat_r = 32'd0; -reg csrbank0_init_done0_re = 1'd0; -wire csrbank0_init_done0_r; -reg csrbank0_init_done0_we = 1'd0; -wire csrbank0_init_done0_w; -reg csrbank0_init_error0_re = 1'd0; -wire csrbank0_init_error0_r; -reg csrbank0_init_error0_we = 1'd0; -wire csrbank0_init_error0_w; -wire csrbank0_sel; -wire [13:0] interface1_bank_bus_adr; -wire interface1_bank_bus_we; -wire [31:0] interface1_bank_bus_dat_w; -reg [31:0] interface1_bank_bus_dat_r = 32'd0; -reg csrbank1_rst0_re = 1'd0; -wire csrbank1_rst0_r; -reg csrbank1_rst0_we = 1'd0; -wire csrbank1_rst0_w; -reg csrbank1_dly_sel0_re = 1'd0; -wire [1:0] csrbank1_dly_sel0_r; -reg csrbank1_dly_sel0_we = 1'd0; -wire [1:0] csrbank1_dly_sel0_w; -reg csrbank1_half_sys8x_taps0_re = 1'd0; -wire [4:0] csrbank1_half_sys8x_taps0_r; -reg csrbank1_half_sys8x_taps0_we = 1'd0; -wire [4:0] csrbank1_half_sys8x_taps0_w; -reg csrbank1_wlevel_en0_re = 1'd0; -wire csrbank1_wlevel_en0_r; -reg csrbank1_wlevel_en0_we = 1'd0; -wire csrbank1_wlevel_en0_w; -reg csrbank1_rdphase0_re = 1'd0; -wire [1:0] csrbank1_rdphase0_r; -reg csrbank1_rdphase0_we = 1'd0; -wire [1:0] csrbank1_rdphase0_w; -reg csrbank1_wrphase0_re = 1'd0; -wire [1:0] csrbank1_wrphase0_r; -reg csrbank1_wrphase0_we = 1'd0; -wire [1:0] csrbank1_wrphase0_w; -wire csrbank1_sel; -wire [13:0] interface2_bank_bus_adr; -wire interface2_bank_bus_we; -wire [31:0] interface2_bank_bus_dat_w; -reg [31:0] interface2_bank_bus_dat_r = 32'd0; -reg csrbank2_dfii_control0_re = 1'd0; -wire [3:0] csrbank2_dfii_control0_r; -reg csrbank2_dfii_control0_we = 1'd0; -wire [3:0] csrbank2_dfii_control0_w; -reg csrbank2_dfii_pi0_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi0_command0_r; -reg csrbank2_dfii_pi0_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi0_command0_w; -reg csrbank2_dfii_pi0_address0_re = 1'd0; -wire [15:0] csrbank2_dfii_pi0_address0_r; -reg csrbank2_dfii_pi0_address0_we = 1'd0; -wire [15:0] csrbank2_dfii_pi0_address0_w; -reg csrbank2_dfii_pi0_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi0_baddress0_r; -reg csrbank2_dfii_pi0_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi0_baddress0_w; -reg csrbank2_dfii_pi0_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata0_r; -reg csrbank2_dfii_pi0_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata0_w; -reg csrbank2_dfii_pi0_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata_r; -reg csrbank2_dfii_pi0_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata_w; -reg csrbank2_dfii_pi1_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi1_command0_r; -reg csrbank2_dfii_pi1_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi1_command0_w; -reg csrbank2_dfii_pi1_address0_re = 1'd0; -wire [15:0] csrbank2_dfii_pi1_address0_r; -reg csrbank2_dfii_pi1_address0_we = 1'd0; -wire [15:0] csrbank2_dfii_pi1_address0_w; -reg csrbank2_dfii_pi1_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi1_baddress0_r; -reg csrbank2_dfii_pi1_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi1_baddress0_w; -reg csrbank2_dfii_pi1_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata0_r; -reg csrbank2_dfii_pi1_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata0_w; -reg csrbank2_dfii_pi1_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata_r; -reg csrbank2_dfii_pi1_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata_w; -reg csrbank2_dfii_pi2_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi2_command0_r; -reg csrbank2_dfii_pi2_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi2_command0_w; -reg csrbank2_dfii_pi2_address0_re = 1'd0; -wire [15:0] csrbank2_dfii_pi2_address0_r; -reg csrbank2_dfii_pi2_address0_we = 1'd0; -wire [15:0] csrbank2_dfii_pi2_address0_w; -reg csrbank2_dfii_pi2_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi2_baddress0_r; -reg csrbank2_dfii_pi2_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi2_baddress0_w; -reg csrbank2_dfii_pi2_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi2_wrdata0_r; -reg csrbank2_dfii_pi2_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi2_wrdata0_w; -reg csrbank2_dfii_pi2_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi2_rddata_r; -reg csrbank2_dfii_pi2_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi2_rddata_w; -reg csrbank2_dfii_pi3_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi3_command0_r; -reg csrbank2_dfii_pi3_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi3_command0_w; -reg csrbank2_dfii_pi3_address0_re = 1'd0; -wire [15:0] csrbank2_dfii_pi3_address0_r; -reg csrbank2_dfii_pi3_address0_we = 1'd0; -wire [15:0] csrbank2_dfii_pi3_address0_w; -reg csrbank2_dfii_pi3_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi3_baddress0_r; -reg csrbank2_dfii_pi3_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi3_baddress0_w; -reg csrbank2_dfii_pi3_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi3_wrdata0_r; -reg csrbank2_dfii_pi3_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi3_wrdata0_w; -reg csrbank2_dfii_pi3_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi3_rddata_r; -reg csrbank2_dfii_pi3_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi3_rddata_w; -wire csrbank2_sel; -wire [13:0] csr_interconnect_adr; -wire csr_interconnect_we; -wire [31:0] csr_interconnect_dat_w; -wire [31:0] csr_interconnect_dat_r; -wire litedramcore_reset0; -wire litedramcore_reset1; -wire litedramcore_reset2; -wire litedramcore_reset3; -wire litedramcore_reset4; -wire litedramcore_reset5; -wire litedramcore_reset6; -wire litedramcore_reset7; -wire litedramcore_pll_fb; -reg [1:0] litedramcore_refresher_state = 2'd0; -reg [1:0] litedramcore_refresher_next_state = 2'd0; -reg [3:0] litedramcore_bankmachine0_state = 4'd0; -reg [3:0] litedramcore_bankmachine0_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine1_state = 4'd0; -reg [3:0] litedramcore_bankmachine1_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine2_state = 4'd0; -reg [3:0] litedramcore_bankmachine2_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine3_state = 4'd0; -reg [3:0] litedramcore_bankmachine3_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine4_state = 4'd0; -reg [3:0] litedramcore_bankmachine4_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine5_state = 4'd0; -reg [3:0] litedramcore_bankmachine5_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine6_state = 4'd0; -reg [3:0] litedramcore_bankmachine6_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine7_state = 4'd0; -reg [3:0] litedramcore_bankmachine7_next_state = 4'd0; -reg [3:0] litedramcore_multiplexer_state = 4'd0; -reg [3:0] litedramcore_multiplexer_next_state = 4'd0; -wire litedramcore_roundrobin0_request; -wire litedramcore_roundrobin0_grant; -wire litedramcore_roundrobin0_ce; -wire litedramcore_roundrobin1_request; -wire litedramcore_roundrobin1_grant; -wire litedramcore_roundrobin1_ce; -wire litedramcore_roundrobin2_request; -wire litedramcore_roundrobin2_grant; -wire litedramcore_roundrobin2_ce; -wire litedramcore_roundrobin3_request; -wire litedramcore_roundrobin3_grant; -wire litedramcore_roundrobin3_ce; -wire litedramcore_roundrobin4_request; -wire litedramcore_roundrobin4_grant; -wire litedramcore_roundrobin4_ce; -wire litedramcore_roundrobin5_request; -wire litedramcore_roundrobin5_grant; -wire litedramcore_roundrobin5_ce; -wire litedramcore_roundrobin6_request; -wire litedramcore_roundrobin6_grant; -wire litedramcore_roundrobin6_ce; -wire litedramcore_roundrobin7_request; -wire litedramcore_roundrobin7_grant; -wire litedramcore_roundrobin7_ce; -reg litedramcore_locked0 = 1'd0; -reg litedramcore_locked1 = 1'd0; -reg litedramcore_locked2 = 1'd0; -reg litedramcore_locked3 = 1'd0; -reg litedramcore_locked4 = 1'd0; -reg litedramcore_locked5 = 1'd0; -reg litedramcore_locked6 = 1'd0; -reg litedramcore_locked7 = 1'd0; -reg litedramcore_new_master_wdata_ready0 = 1'd0; -reg litedramcore_new_master_wdata_ready1 = 1'd0; -reg litedramcore_new_master_rdata_valid0 = 1'd0; -reg litedramcore_new_master_rdata_valid1 = 1'd0; -reg litedramcore_new_master_rdata_valid2 = 1'd0; -reg litedramcore_new_master_rdata_valid3 = 1'd0; -reg litedramcore_new_master_rdata_valid4 = 1'd0; -reg litedramcore_new_master_rdata_valid5 = 1'd0; -reg litedramcore_new_master_rdata_valid6 = 1'd0; -reg litedramcore_new_master_rdata_valid7 = 1'd0; -reg litedramcore_new_master_rdata_valid8 = 1'd0; -reg [1:0] litedramcore_state = 2'd0; -reg [1:0] litedramcore_next_state = 2'd0; -reg [31:0] litedramcore_dat_w_next_value0 = 32'd0; -reg litedramcore_dat_w_next_value_ce0 = 1'd0; -reg [13:0] litedramcore_adr_next_value1 = 14'd0; -reg litedramcore_adr_next_value_ce1 = 1'd0; -reg litedramcore_we_next_value2 = 1'd0; -reg litedramcore_we_next_value_ce2 = 1'd0; -reg rhs_array_muxed0 = 1'd0; -reg [15:0] rhs_array_muxed1 = 16'd0; -reg [2:0] rhs_array_muxed2 = 3'd0; -reg rhs_array_muxed3 = 1'd0; -reg rhs_array_muxed4 = 1'd0; -reg rhs_array_muxed5 = 1'd0; -reg t_array_muxed0 = 1'd0; -reg t_array_muxed1 = 1'd0; -reg t_array_muxed2 = 1'd0; -reg rhs_array_muxed6 = 1'd0; -reg [15:0] rhs_array_muxed7 = 16'd0; -reg [2:0] rhs_array_muxed8 = 3'd0; -reg rhs_array_muxed9 = 1'd0; -reg rhs_array_muxed10 = 1'd0; -reg rhs_array_muxed11 = 1'd0; -reg t_array_muxed3 = 1'd0; -reg t_array_muxed4 = 1'd0; -reg t_array_muxed5 = 1'd0; -reg [22:0] rhs_array_muxed12 = 23'd0; -reg rhs_array_muxed13 = 1'd0; -reg rhs_array_muxed14 = 1'd0; -reg [22:0] rhs_array_muxed15 = 23'd0; -reg rhs_array_muxed16 = 1'd0; -reg rhs_array_muxed17 = 1'd0; -reg [22:0] rhs_array_muxed18 = 23'd0; -reg rhs_array_muxed19 = 1'd0; -reg rhs_array_muxed20 = 1'd0; -reg [22:0] rhs_array_muxed21 = 23'd0; -reg rhs_array_muxed22 = 1'd0; -reg rhs_array_muxed23 = 1'd0; -reg [22:0] rhs_array_muxed24 = 23'd0; -reg rhs_array_muxed25 = 1'd0; -reg rhs_array_muxed26 = 1'd0; -reg [22:0] rhs_array_muxed27 = 23'd0; -reg rhs_array_muxed28 = 1'd0; -reg rhs_array_muxed29 = 1'd0; -reg [22:0] rhs_array_muxed30 = 23'd0; -reg rhs_array_muxed31 = 1'd0; -reg rhs_array_muxed32 = 1'd0; -reg [22:0] rhs_array_muxed33 = 23'd0; -reg rhs_array_muxed34 = 1'd0; -reg rhs_array_muxed35 = 1'd0; -reg [2:0] array_muxed0 = 3'd0; -reg [15:0] array_muxed1 = 16'd0; -reg array_muxed2 = 1'd0; -reg array_muxed3 = 1'd0; -reg array_muxed4 = 1'd0; -reg array_muxed5 = 1'd0; -reg array_muxed6 = 1'd0; -reg [2:0] array_muxed7 = 3'd0; -reg [15:0] array_muxed8 = 16'd0; -reg array_muxed9 = 1'd0; -reg array_muxed10 = 1'd0; -reg array_muxed11 = 1'd0; -reg array_muxed12 = 1'd0; -reg array_muxed13 = 1'd0; -reg [2:0] array_muxed14 = 3'd0; -reg [15:0] array_muxed15 = 16'd0; -reg array_muxed16 = 1'd0; -reg array_muxed17 = 1'd0; -reg array_muxed18 = 1'd0; -reg array_muxed19 = 1'd0; -reg array_muxed20 = 1'd0; -reg [2:0] array_muxed21 = 3'd0; -reg [15:0] array_muxed22 = 16'd0; -reg array_muxed23 = 1'd0; -reg array_muxed24 = 1'd0; -reg array_muxed25 = 1'd0; -reg array_muxed26 = 1'd0; -reg array_muxed27 = 1'd0; -wire xilinxasyncresetsynchronizerimpl0; -wire xilinxasyncresetsynchronizerimpl0_rst_meta; -wire xilinxasyncresetsynchronizerimpl1; -wire xilinxasyncresetsynchronizerimpl1_rst_meta; -wire xilinxasyncresetsynchronizerimpl2; -wire xilinxasyncresetsynchronizerimpl2_rst_meta; -wire xilinxasyncresetsynchronizerimpl2_expr; -wire xilinxasyncresetsynchronizerimpl3; -wire xilinxasyncresetsynchronizerimpl3_rst_meta; -wire xilinxasyncresetsynchronizerimpl3_expr; +reg main_litedramcore_twtrcon_ready = 1'd0; +wire main_litedramcore_twtrcon_valid; +wire main_litedramcore_wants_refresh; +wire main_litedramcore_wants_zqcs; +wire main_litedramcore_write_available; +reg main_litedramcore_zqcs_executer_done = 1'd0; +reg main_litedramcore_zqcs_executer_start = 1'd0; +reg [4:0] main_litedramcore_zqcs_executer_trigger = 5'd0; +wire [26:0] main_litedramcore_zqcs_timer_count0; +reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999; +wire main_litedramcore_zqcs_timer_done0; +wire main_litedramcore_zqcs_timer_done1; +wire main_litedramcore_zqcs_timer_wait; +wire main_locked; +reg main_power_down = 1'd0; +wire main_reset; +reg [3:0] main_reset_counter = 4'd15; +reg main_rst = 1'd0; +wire main_user_enable; +wire [25:0] main_user_port_cmd_payload_addr; +wire main_user_port_cmd_payload_we; +wire main_user_port_cmd_ready; +wire main_user_port_cmd_valid; +wire [127:0] main_user_port_rdata_payload_data; +wire main_user_port_rdata_ready; +wire main_user_port_rdata_valid; +wire [127:0] main_user_port_wdata_payload_data; +wire [15:0] main_user_port_wdata_payload_we; +wire main_user_port_wdata_ready; +wire main_user_port_wdata_valid; +wire main_wb_bus_ack; +wire [29:0] main_wb_bus_adr; +wire [1:0] main_wb_bus_bte; +wire [2:0] main_wb_bus_cti; +wire main_wb_bus_cyc; +wire [31:0] main_wb_bus_dat_r; +wire [31:0] main_wb_bus_dat_w; +wire main_wb_bus_err; +wire [3:0] main_wb_bus_sel; +wire main_wb_bus_stb; +wire main_wb_bus_we; +wire sys4x_clk; +wire sys4x_dqs_clk; +wire sys_clk; +wire sys_rst; //------------------------------------------------------------------------------ // Combinatorial Logic //------------------------------------------------------------------------------ -assign init_done = init_done_storage; -assign init_error = init_error_storage; -assign wb_bus_adr = wb_ctrl_adr; -assign wb_bus_dat_w = wb_ctrl_dat_w; -assign wb_ctrl_dat_r = wb_bus_dat_r; -assign wb_bus_sel = wb_ctrl_sel; -assign wb_bus_cyc = wb_ctrl_cyc; -assign wb_bus_stb = wb_ctrl_stb; -assign wb_ctrl_ack = wb_bus_ack; -assign wb_bus_we = wb_ctrl_we; -assign wb_bus_cti = wb_ctrl_cti; -assign wb_bus_bte = wb_ctrl_bte; -assign wb_ctrl_err = wb_bus_err; +assign init_done = main_init_done_storage; +assign init_error = main_init_error_storage; +assign main_wb_bus_adr = wb_ctrl_adr; +assign main_wb_bus_dat_w = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = main_wb_bus_dat_r; +assign main_wb_bus_sel = wb_ctrl_sel; +assign main_wb_bus_cyc = wb_ctrl_cyc; +assign main_wb_bus_stb = wb_ctrl_stb; +assign wb_ctrl_ack = main_wb_bus_ack; +assign main_wb_bus_we = wb_ctrl_we; +assign main_wb_bus_cti = wb_ctrl_cti; +assign main_wb_bus_bte = wb_ctrl_bte; +assign wb_ctrl_err = main_wb_bus_err; assign user_clk = sys_clk; assign user_rst = sys_rst; -assign user_enable = 1'd1; -assign user_port_cmd_valid = (user_port_native_0_cmd_valid & user_enable); -assign user_port_native_0_cmd_ready = (user_port_cmd_ready & user_enable); -assign user_port_cmd_payload_we = user_port_native_0_cmd_we; -assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr; -assign user_port_wdata_valid = (user_port_native_0_wdata_valid & user_enable); -assign user_port_native_0_wdata_ready = (user_port_wdata_ready & user_enable); -assign user_port_wdata_payload_we = user_port_native_0_wdata_we; -assign user_port_wdata_payload_data = user_port_native_0_wdata_data; -assign user_port_native_0_rdata_valid = (user_port_rdata_valid & user_enable); -assign user_port_rdata_ready = (user_port_native_0_rdata_ready & user_enable); -assign user_port_native_0_rdata_data = user_port_rdata_payload_data; -assign reset = (rst | rst_1); -assign pll_locked = locked; -assign clkin = clk; -assign iodelay_clk = clkout_buf0; -assign sys_clk = clkout_buf1; -assign sys4x_clk = clkout_buf2; -assign sys4x_dqs_clk = clkout_buf3; -assign ddram_ba = a7ddrphy_pads_ba; -assign a7ddrphy_dqs_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dqs_oe) | a7ddrphy_dqs_postamble); -assign a7ddrphy_dq_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dq_oe) | a7ddrphy_dqs_postamble); -always @(*) begin - a7ddrphy_dfi_p0_rddata <= 32'd0; - a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0]; - a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1]; - a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0]; - a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1]; - a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0]; - a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1]; - a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0]; - a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1]; - a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0]; - a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1]; - a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0]; - a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1]; - a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0]; - a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1]; - a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0]; - a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1]; - a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0]; - a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1]; - a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0]; - a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1]; - a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0]; - a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1]; - a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0]; - a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1]; - a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0]; - a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1]; - a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0]; - a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1]; - a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0]; - a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1]; - a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0]; - a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1]; -end -always @(*) begin - a7ddrphy_dfi_p1_rddata <= 32'd0; - a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2]; - a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3]; - a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2]; - a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3]; - a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2]; - a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3]; - a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2]; - a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3]; - a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2]; - a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3]; - a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2]; - a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3]; - a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2]; - a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3]; - a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2]; - a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3]; - a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2]; - a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3]; - a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2]; - a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3]; - a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2]; - a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3]; - a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2]; - a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3]; - a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2]; - a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3]; - a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2]; - a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3]; - a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2]; - a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3]; - a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2]; - a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3]; -end -always @(*) begin - a7ddrphy_dfi_p2_rddata <= 32'd0; - a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4]; - a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5]; - a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4]; - a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5]; - a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4]; - a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5]; - a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4]; - a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5]; - a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4]; - a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5]; - a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4]; - a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5]; - a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4]; - a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5]; - a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4]; - a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5]; - a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4]; - a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5]; - a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4]; - a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5]; - a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4]; - a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5]; - a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4]; - a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5]; - a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4]; - a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5]; - a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4]; - a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5]; - a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4]; - a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5]; - a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4]; - a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5]; -end -always @(*) begin - a7ddrphy_dfi_p3_rddata <= 32'd0; - a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6]; - a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7]; - a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6]; - a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7]; - a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6]; - a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7]; - a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6]; - a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7]; - a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6]; - a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7]; - a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6]; - a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7]; - a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6]; - a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7]; - a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6]; - a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7]; - a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6]; - a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7]; - a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6]; - a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7]; - a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6]; - a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7]; - a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6]; - a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7]; - a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6]; - a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7]; - a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6]; - a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7]; - a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6]; - a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7]; - a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6]; - a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7]; -end -assign a7ddrphy_dfi_p0_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); -assign a7ddrphy_dfi_p1_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); -assign a7ddrphy_dfi_p2_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); -assign a7ddrphy_dfi_p3_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); -assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en_tappeddelayline1; -always @(*) begin - a7ddrphy_dqs_oe <= 1'd0; - if (a7ddrphy_wlevel_en_storage) begin - a7ddrphy_dqs_oe <= 1'd1; +assign main_user_enable = 1'd1; +assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable); +assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable); +assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we; +assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr; +assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable); +assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable); +assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we; +assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data; +assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable); +assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable); +assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data; +assign builder_interface0_adr = main_wb_bus_adr; +assign builder_interface0_dat_w = main_wb_bus_dat_w; +assign main_wb_bus_dat_r = builder_interface0_dat_r; +assign builder_interface0_sel = main_wb_bus_sel; +assign builder_interface0_cyc = main_wb_bus_cyc; +assign builder_interface0_stb = main_wb_bus_stb; +assign main_wb_bus_ack = builder_interface0_ack; +assign builder_interface0_we = main_wb_bus_we; +assign builder_interface0_cti = main_wb_bus_cti; +assign builder_interface0_bte = main_wb_bus_bte; +assign main_wb_bus_err = builder_interface0_err; +assign main_reset = (rst | main_rst); +assign pll_locked = main_locked; +assign main_clkin = clk; +assign iodelay_clk = main_clkout_buf0; +assign sys_clk = main_clkout_buf1; +assign sys4x_clk = main_clkout_buf2; +assign sys4x_dqs_clk = main_clkout_buf3; +assign ddram_ba = main_a7ddrphy_pads_ba; +assign main_a7ddrphy_dqs_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_oe) | main_a7ddrphy_dqs_postamble); +assign main_a7ddrphy_dq_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dq_oe) | main_a7ddrphy_dqs_postamble); +always @(*) begin + main_a7ddrphy_dfi_p0_rddata <= 32'd0; + main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip04[0]; + main_a7ddrphy_dfi_p0_rddata[16] <= main_a7ddrphy_bitslip04[1]; + main_a7ddrphy_dfi_p0_rddata[1] <= main_a7ddrphy_bitslip14[0]; + main_a7ddrphy_dfi_p0_rddata[17] <= main_a7ddrphy_bitslip14[1]; + main_a7ddrphy_dfi_p0_rddata[2] <= main_a7ddrphy_bitslip22[0]; + main_a7ddrphy_dfi_p0_rddata[18] <= main_a7ddrphy_bitslip22[1]; + main_a7ddrphy_dfi_p0_rddata[3] <= main_a7ddrphy_bitslip32[0]; + main_a7ddrphy_dfi_p0_rddata[19] <= main_a7ddrphy_bitslip32[1]; + main_a7ddrphy_dfi_p0_rddata[4] <= main_a7ddrphy_bitslip42[0]; + main_a7ddrphy_dfi_p0_rddata[20] <= main_a7ddrphy_bitslip42[1]; + main_a7ddrphy_dfi_p0_rddata[5] <= main_a7ddrphy_bitslip52[0]; + main_a7ddrphy_dfi_p0_rddata[21] <= main_a7ddrphy_bitslip52[1]; + main_a7ddrphy_dfi_p0_rddata[6] <= main_a7ddrphy_bitslip62[0]; + main_a7ddrphy_dfi_p0_rddata[22] <= main_a7ddrphy_bitslip62[1]; + main_a7ddrphy_dfi_p0_rddata[7] <= main_a7ddrphy_bitslip72[0]; + main_a7ddrphy_dfi_p0_rddata[23] <= main_a7ddrphy_bitslip72[1]; + main_a7ddrphy_dfi_p0_rddata[8] <= main_a7ddrphy_bitslip82[0]; + main_a7ddrphy_dfi_p0_rddata[24] <= main_a7ddrphy_bitslip82[1]; + main_a7ddrphy_dfi_p0_rddata[9] <= main_a7ddrphy_bitslip92[0]; + main_a7ddrphy_dfi_p0_rddata[25] <= main_a7ddrphy_bitslip92[1]; + main_a7ddrphy_dfi_p0_rddata[10] <= main_a7ddrphy_bitslip102[0]; + main_a7ddrphy_dfi_p0_rddata[26] <= main_a7ddrphy_bitslip102[1]; + main_a7ddrphy_dfi_p0_rddata[11] <= main_a7ddrphy_bitslip112[0]; + main_a7ddrphy_dfi_p0_rddata[27] <= main_a7ddrphy_bitslip112[1]; + main_a7ddrphy_dfi_p0_rddata[12] <= main_a7ddrphy_bitslip122[0]; + main_a7ddrphy_dfi_p0_rddata[28] <= main_a7ddrphy_bitslip122[1]; + main_a7ddrphy_dfi_p0_rddata[13] <= main_a7ddrphy_bitslip132[0]; + main_a7ddrphy_dfi_p0_rddata[29] <= main_a7ddrphy_bitslip132[1]; + main_a7ddrphy_dfi_p0_rddata[14] <= main_a7ddrphy_bitslip142[0]; + main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip142[1]; + main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip152[0]; + main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip152[1]; +end +always @(*) begin + main_a7ddrphy_dfi_p1_rddata <= 32'd0; + main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip04[2]; + main_a7ddrphy_dfi_p1_rddata[16] <= main_a7ddrphy_bitslip04[3]; + main_a7ddrphy_dfi_p1_rddata[1] <= main_a7ddrphy_bitslip14[2]; + main_a7ddrphy_dfi_p1_rddata[17] <= main_a7ddrphy_bitslip14[3]; + main_a7ddrphy_dfi_p1_rddata[2] <= main_a7ddrphy_bitslip22[2]; + main_a7ddrphy_dfi_p1_rddata[18] <= main_a7ddrphy_bitslip22[3]; + main_a7ddrphy_dfi_p1_rddata[3] <= main_a7ddrphy_bitslip32[2]; + main_a7ddrphy_dfi_p1_rddata[19] <= main_a7ddrphy_bitslip32[3]; + main_a7ddrphy_dfi_p1_rddata[4] <= main_a7ddrphy_bitslip42[2]; + main_a7ddrphy_dfi_p1_rddata[20] <= main_a7ddrphy_bitslip42[3]; + main_a7ddrphy_dfi_p1_rddata[5] <= main_a7ddrphy_bitslip52[2]; + main_a7ddrphy_dfi_p1_rddata[21] <= main_a7ddrphy_bitslip52[3]; + main_a7ddrphy_dfi_p1_rddata[6] <= main_a7ddrphy_bitslip62[2]; + main_a7ddrphy_dfi_p1_rddata[22] <= main_a7ddrphy_bitslip62[3]; + main_a7ddrphy_dfi_p1_rddata[7] <= main_a7ddrphy_bitslip72[2]; + main_a7ddrphy_dfi_p1_rddata[23] <= main_a7ddrphy_bitslip72[3]; + main_a7ddrphy_dfi_p1_rddata[8] <= main_a7ddrphy_bitslip82[2]; + main_a7ddrphy_dfi_p1_rddata[24] <= main_a7ddrphy_bitslip82[3]; + main_a7ddrphy_dfi_p1_rddata[9] <= main_a7ddrphy_bitslip92[2]; + main_a7ddrphy_dfi_p1_rddata[25] <= main_a7ddrphy_bitslip92[3]; + main_a7ddrphy_dfi_p1_rddata[10] <= main_a7ddrphy_bitslip102[2]; + main_a7ddrphy_dfi_p1_rddata[26] <= main_a7ddrphy_bitslip102[3]; + main_a7ddrphy_dfi_p1_rddata[11] <= main_a7ddrphy_bitslip112[2]; + main_a7ddrphy_dfi_p1_rddata[27] <= main_a7ddrphy_bitslip112[3]; + main_a7ddrphy_dfi_p1_rddata[12] <= main_a7ddrphy_bitslip122[2]; + main_a7ddrphy_dfi_p1_rddata[28] <= main_a7ddrphy_bitslip122[3]; + main_a7ddrphy_dfi_p1_rddata[13] <= main_a7ddrphy_bitslip132[2]; + main_a7ddrphy_dfi_p1_rddata[29] <= main_a7ddrphy_bitslip132[3]; + main_a7ddrphy_dfi_p1_rddata[14] <= main_a7ddrphy_bitslip142[2]; + main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip142[3]; + main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip152[2]; + main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip152[3]; +end +always @(*) begin + main_a7ddrphy_dfi_p2_rddata <= 32'd0; + main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip04[4]; + main_a7ddrphy_dfi_p2_rddata[16] <= main_a7ddrphy_bitslip04[5]; + main_a7ddrphy_dfi_p2_rddata[1] <= main_a7ddrphy_bitslip14[4]; + main_a7ddrphy_dfi_p2_rddata[17] <= main_a7ddrphy_bitslip14[5]; + main_a7ddrphy_dfi_p2_rddata[2] <= main_a7ddrphy_bitslip22[4]; + main_a7ddrphy_dfi_p2_rddata[18] <= main_a7ddrphy_bitslip22[5]; + main_a7ddrphy_dfi_p2_rddata[3] <= main_a7ddrphy_bitslip32[4]; + main_a7ddrphy_dfi_p2_rddata[19] <= main_a7ddrphy_bitslip32[5]; + main_a7ddrphy_dfi_p2_rddata[4] <= main_a7ddrphy_bitslip42[4]; + main_a7ddrphy_dfi_p2_rddata[20] <= main_a7ddrphy_bitslip42[5]; + main_a7ddrphy_dfi_p2_rddata[5] <= main_a7ddrphy_bitslip52[4]; + main_a7ddrphy_dfi_p2_rddata[21] <= main_a7ddrphy_bitslip52[5]; + main_a7ddrphy_dfi_p2_rddata[6] <= main_a7ddrphy_bitslip62[4]; + main_a7ddrphy_dfi_p2_rddata[22] <= main_a7ddrphy_bitslip62[5]; + main_a7ddrphy_dfi_p2_rddata[7] <= main_a7ddrphy_bitslip72[4]; + main_a7ddrphy_dfi_p2_rddata[23] <= main_a7ddrphy_bitslip72[5]; + main_a7ddrphy_dfi_p2_rddata[8] <= main_a7ddrphy_bitslip82[4]; + main_a7ddrphy_dfi_p2_rddata[24] <= main_a7ddrphy_bitslip82[5]; + main_a7ddrphy_dfi_p2_rddata[9] <= main_a7ddrphy_bitslip92[4]; + main_a7ddrphy_dfi_p2_rddata[25] <= main_a7ddrphy_bitslip92[5]; + main_a7ddrphy_dfi_p2_rddata[10] <= main_a7ddrphy_bitslip102[4]; + main_a7ddrphy_dfi_p2_rddata[26] <= main_a7ddrphy_bitslip102[5]; + main_a7ddrphy_dfi_p2_rddata[11] <= main_a7ddrphy_bitslip112[4]; + main_a7ddrphy_dfi_p2_rddata[27] <= main_a7ddrphy_bitslip112[5]; + main_a7ddrphy_dfi_p2_rddata[12] <= main_a7ddrphy_bitslip122[4]; + main_a7ddrphy_dfi_p2_rddata[28] <= main_a7ddrphy_bitslip122[5]; + main_a7ddrphy_dfi_p2_rddata[13] <= main_a7ddrphy_bitslip132[4]; + main_a7ddrphy_dfi_p2_rddata[29] <= main_a7ddrphy_bitslip132[5]; + main_a7ddrphy_dfi_p2_rddata[14] <= main_a7ddrphy_bitslip142[4]; + main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip142[5]; + main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip152[4]; + main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip152[5]; +end +always @(*) begin + main_a7ddrphy_dfi_p3_rddata <= 32'd0; + main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip04[6]; + main_a7ddrphy_dfi_p3_rddata[16] <= main_a7ddrphy_bitslip04[7]; + main_a7ddrphy_dfi_p3_rddata[1] <= main_a7ddrphy_bitslip14[6]; + main_a7ddrphy_dfi_p3_rddata[17] <= main_a7ddrphy_bitslip14[7]; + main_a7ddrphy_dfi_p3_rddata[2] <= main_a7ddrphy_bitslip22[6]; + main_a7ddrphy_dfi_p3_rddata[18] <= main_a7ddrphy_bitslip22[7]; + main_a7ddrphy_dfi_p3_rddata[3] <= main_a7ddrphy_bitslip32[6]; + main_a7ddrphy_dfi_p3_rddata[19] <= main_a7ddrphy_bitslip32[7]; + main_a7ddrphy_dfi_p3_rddata[4] <= main_a7ddrphy_bitslip42[6]; + main_a7ddrphy_dfi_p3_rddata[20] <= main_a7ddrphy_bitslip42[7]; + main_a7ddrphy_dfi_p3_rddata[5] <= main_a7ddrphy_bitslip52[6]; + main_a7ddrphy_dfi_p3_rddata[21] <= main_a7ddrphy_bitslip52[7]; + main_a7ddrphy_dfi_p3_rddata[6] <= main_a7ddrphy_bitslip62[6]; + main_a7ddrphy_dfi_p3_rddata[22] <= main_a7ddrphy_bitslip62[7]; + main_a7ddrphy_dfi_p3_rddata[7] <= main_a7ddrphy_bitslip72[6]; + main_a7ddrphy_dfi_p3_rddata[23] <= main_a7ddrphy_bitslip72[7]; + main_a7ddrphy_dfi_p3_rddata[8] <= main_a7ddrphy_bitslip82[6]; + main_a7ddrphy_dfi_p3_rddata[24] <= main_a7ddrphy_bitslip82[7]; + main_a7ddrphy_dfi_p3_rddata[9] <= main_a7ddrphy_bitslip92[6]; + main_a7ddrphy_dfi_p3_rddata[25] <= main_a7ddrphy_bitslip92[7]; + main_a7ddrphy_dfi_p3_rddata[10] <= main_a7ddrphy_bitslip102[6]; + main_a7ddrphy_dfi_p3_rddata[26] <= main_a7ddrphy_bitslip102[7]; + main_a7ddrphy_dfi_p3_rddata[11] <= main_a7ddrphy_bitslip112[6]; + main_a7ddrphy_dfi_p3_rddata[27] <= main_a7ddrphy_bitslip112[7]; + main_a7ddrphy_dfi_p3_rddata[12] <= main_a7ddrphy_bitslip122[6]; + main_a7ddrphy_dfi_p3_rddata[28] <= main_a7ddrphy_bitslip122[7]; + main_a7ddrphy_dfi_p3_rddata[13] <= main_a7ddrphy_bitslip132[6]; + main_a7ddrphy_dfi_p3_rddata[29] <= main_a7ddrphy_bitslip132[7]; + main_a7ddrphy_dfi_p3_rddata[14] <= main_a7ddrphy_bitslip142[6]; + main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip142[7]; + main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip152[6]; + main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip152[7]; +end +assign main_a7ddrphy_dfi_p0_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dfi_p1_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dfi_p2_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dfi_p3_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dq_oe = main_a7ddrphy_wrdata_en_tappeddelayline1; +always @(*) begin + main_a7ddrphy_dqs_oe <= 1'd0; + if (main_a7ddrphy_wlevel_en_storage) begin + main_a7ddrphy_dqs_oe <= 1'd1; end else begin - a7ddrphy_dqs_oe <= a7ddrphy_dq_oe; + main_a7ddrphy_dqs_oe <= main_a7ddrphy_dq_oe; end end -assign a7ddrphy_dqs_preamble = (a7ddrphy_wrdata_en_tappeddelayline0 & (~a7ddrphy_wrdata_en_tappeddelayline1)); -assign a7ddrphy_dqs_postamble = (a7ddrphy_wrdata_en_tappeddelayline2 & (~a7ddrphy_wrdata_en_tappeddelayline1)); +assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_wrdata_en_tappeddelayline0 & (~main_a7ddrphy_wrdata_en_tappeddelayline1)); +assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_wrdata_en_tappeddelayline2 & (~main_a7ddrphy_wrdata_en_tappeddelayline1)); always @(*) begin - a7ddrphy_dqspattern_o0 <= 8'd0; - a7ddrphy_dqspattern_o0 <= 7'd85; - if (a7ddrphy_dqspattern0) begin - a7ddrphy_dqspattern_o0 <= 5'd21; + main_a7ddrphy_dqspattern_o0 <= 8'd0; + main_a7ddrphy_dqspattern_o0 <= 7'd85; + if (main_a7ddrphy_dqspattern0) begin + main_a7ddrphy_dqspattern_o0 <= 5'd21; end - if (a7ddrphy_dqspattern1) begin - a7ddrphy_dqspattern_o0 <= 7'd84; + if (main_a7ddrphy_dqspattern1) begin + main_a7ddrphy_dqspattern_o0 <= 7'd84; end - if (a7ddrphy_wlevel_en_storage) begin - a7ddrphy_dqspattern_o0 <= 1'd0; - if (a7ddrphy_wlevel_strobe_re) begin - a7ddrphy_dqspattern_o0 <= 1'd1; + if (main_a7ddrphy_wlevel_en_storage) begin + main_a7ddrphy_dqspattern_o0 <= 1'd0; + if (main_a7ddrphy_wlevel_strobe_re) begin + main_a7ddrphy_dqspattern_o0 <= 1'd1; end end end always @(*) begin - a7ddrphy_bitslip00 <= 8'd0; - case (a7ddrphy_bitslip0_value0) + main_a7ddrphy_bitslip00 <= 8'd0; + case (main_a7ddrphy_bitslip0_value0) 1'd0: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip10 <= 8'd0; - case (a7ddrphy_bitslip1_value0) + main_a7ddrphy_bitslip10 <= 8'd0; + case (main_a7ddrphy_bitslip1_value0) 1'd0: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip01 <= 8'd0; - case (a7ddrphy_bitslip0_value1) + main_a7ddrphy_bitslip01 <= 8'd0; + case (main_a7ddrphy_bitslip0_value1) 1'd0: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip11 <= 8'd0; - case (a7ddrphy_bitslip1_value1) + main_a7ddrphy_bitslip11 <= 8'd0; + case (main_a7ddrphy_bitslip1_value1) 1'd0: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip02 <= 8'd0; - case (a7ddrphy_bitslip0_value2) + main_a7ddrphy_bitslip02 <= 8'd0; + case (main_a7ddrphy_bitslip0_value2) 1'd0: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[8:1]; end 1'd1: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[9:2]; end 2'd2: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[10:3]; end 2'd3: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[11:4]; end 3'd4: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[12:5]; end 3'd5: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[13:6]; end 3'd6: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[14:7]; end 3'd7: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip04 <= 8'd0; - case (a7ddrphy_bitslip0_value3) + main_a7ddrphy_bitslip04 <= 8'd0; + case (main_a7ddrphy_bitslip0_value3) 1'd0: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[8:1]; end 1'd1: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[9:2]; end 2'd2: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[10:3]; end 2'd3: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[11:4]; end 3'd4: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[12:5]; end 3'd5: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[13:6]; end 3'd6: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[14:7]; end 3'd7: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip12 <= 8'd0; - case (a7ddrphy_bitslip1_value2) + main_a7ddrphy_bitslip12 <= 8'd0; + case (main_a7ddrphy_bitslip1_value2) 1'd0: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[8:1]; end 1'd1: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[9:2]; end 2'd2: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[10:3]; end 2'd3: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[11:4]; end 3'd4: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[12:5]; end 3'd5: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[13:6]; end 3'd6: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[14:7]; end 3'd7: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip14 <= 8'd0; - case (a7ddrphy_bitslip1_value3) + main_a7ddrphy_bitslip14 <= 8'd0; + case (main_a7ddrphy_bitslip1_value3) 1'd0: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[8:1]; end 1'd1: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[9:2]; end 2'd2: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[10:3]; end 2'd3: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[11:4]; end 3'd4: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[12:5]; end 3'd5: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[13:6]; end 3'd6: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[14:7]; end 3'd7: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip20 <= 8'd0; - case (a7ddrphy_bitslip2_value0) + main_a7ddrphy_bitslip20 <= 8'd0; + case (main_a7ddrphy_bitslip2_value0) 1'd0: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip22 <= 8'd0; - case (a7ddrphy_bitslip2_value1) + main_a7ddrphy_bitslip22 <= 8'd0; + case (main_a7ddrphy_bitslip2_value1) 1'd0: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip30 <= 8'd0; - case (a7ddrphy_bitslip3_value0) + main_a7ddrphy_bitslip30 <= 8'd0; + case (main_a7ddrphy_bitslip3_value0) 1'd0: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip32 <= 8'd0; - case (a7ddrphy_bitslip3_value1) + main_a7ddrphy_bitslip32 <= 8'd0; + case (main_a7ddrphy_bitslip3_value1) 1'd0: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip40 <= 8'd0; - case (a7ddrphy_bitslip4_value0) + main_a7ddrphy_bitslip40 <= 8'd0; + case (main_a7ddrphy_bitslip4_value0) 1'd0: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip42 <= 8'd0; - case (a7ddrphy_bitslip4_value1) + main_a7ddrphy_bitslip42 <= 8'd0; + case (main_a7ddrphy_bitslip4_value1) 1'd0: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip50 <= 8'd0; - case (a7ddrphy_bitslip5_value0) + main_a7ddrphy_bitslip50 <= 8'd0; + case (main_a7ddrphy_bitslip5_value0) 1'd0: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip52 <= 8'd0; - case (a7ddrphy_bitslip5_value1) + main_a7ddrphy_bitslip52 <= 8'd0; + case (main_a7ddrphy_bitslip5_value1) 1'd0: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip60 <= 8'd0; - case (a7ddrphy_bitslip6_value0) + main_a7ddrphy_bitslip60 <= 8'd0; + case (main_a7ddrphy_bitslip6_value0) 1'd0: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip62 <= 8'd0; - case (a7ddrphy_bitslip6_value1) + main_a7ddrphy_bitslip62 <= 8'd0; + case (main_a7ddrphy_bitslip6_value1) 1'd0: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip70 <= 8'd0; - case (a7ddrphy_bitslip7_value0) + main_a7ddrphy_bitslip70 <= 8'd0; + case (main_a7ddrphy_bitslip7_value0) 1'd0: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip72 <= 8'd0; - case (a7ddrphy_bitslip7_value1) + main_a7ddrphy_bitslip72 <= 8'd0; + case (main_a7ddrphy_bitslip7_value1) 1'd0: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip80 <= 8'd0; - case (a7ddrphy_bitslip8_value0) + main_a7ddrphy_bitslip80 <= 8'd0; + case (main_a7ddrphy_bitslip8_value0) 1'd0: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip82 <= 8'd0; - case (a7ddrphy_bitslip8_value1) + main_a7ddrphy_bitslip82 <= 8'd0; + case (main_a7ddrphy_bitslip8_value1) 1'd0: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip90 <= 8'd0; - case (a7ddrphy_bitslip9_value0) + main_a7ddrphy_bitslip90 <= 8'd0; + case (main_a7ddrphy_bitslip9_value0) 1'd0: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip92 <= 8'd0; - case (a7ddrphy_bitslip9_value1) + main_a7ddrphy_bitslip92 <= 8'd0; + case (main_a7ddrphy_bitslip9_value1) 1'd0: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip100 <= 8'd0; - case (a7ddrphy_bitslip10_value0) + main_a7ddrphy_bitslip100 <= 8'd0; + case (main_a7ddrphy_bitslip10_value0) 1'd0: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip102 <= 8'd0; - case (a7ddrphy_bitslip10_value1) + main_a7ddrphy_bitslip102 <= 8'd0; + case (main_a7ddrphy_bitslip10_value1) 1'd0: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip110 <= 8'd0; - case (a7ddrphy_bitslip11_value0) + main_a7ddrphy_bitslip110 <= 8'd0; + case (main_a7ddrphy_bitslip11_value0) 1'd0: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip112 <= 8'd0; - case (a7ddrphy_bitslip11_value1) + main_a7ddrphy_bitslip112 <= 8'd0; + case (main_a7ddrphy_bitslip11_value1) 1'd0: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip120 <= 8'd0; - case (a7ddrphy_bitslip12_value0) + main_a7ddrphy_bitslip120 <= 8'd0; + case (main_a7ddrphy_bitslip12_value0) 1'd0: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip122 <= 8'd0; - case (a7ddrphy_bitslip12_value1) + main_a7ddrphy_bitslip122 <= 8'd0; + case (main_a7ddrphy_bitslip12_value1) 1'd0: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip130 <= 8'd0; - case (a7ddrphy_bitslip13_value0) + main_a7ddrphy_bitslip130 <= 8'd0; + case (main_a7ddrphy_bitslip13_value0) 1'd0: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip132 <= 8'd0; - case (a7ddrphy_bitslip13_value1) + main_a7ddrphy_bitslip132 <= 8'd0; + case (main_a7ddrphy_bitslip13_value1) 1'd0: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip140 <= 8'd0; - case (a7ddrphy_bitslip14_value0) + main_a7ddrphy_bitslip140 <= 8'd0; + case (main_a7ddrphy_bitslip14_value0) 1'd0: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip142 <= 8'd0; - case (a7ddrphy_bitslip14_value1) + main_a7ddrphy_bitslip142 <= 8'd0; + case (main_a7ddrphy_bitslip14_value1) 1'd0: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip150 <= 8'd0; - case (a7ddrphy_bitslip15_value0) + main_a7ddrphy_bitslip150 <= 8'd0; + case (main_a7ddrphy_bitslip15_value0) 1'd0: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip152 <= 8'd0; - case (a7ddrphy_bitslip15_value1) + main_a7ddrphy_bitslip152 <= 8'd0; + case (main_a7ddrphy_bitslip15_value1) 1'd0: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1]; + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2]; + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3]; + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4]; + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5]; + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6]; + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7]; + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8]; + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[15:8]; end endcase end -assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address; -assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank; -assign a7ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n; -assign a7ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n; -assign a7ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n; -assign a7ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n; -assign a7ddrphy_dfi_p0_cke = litedramcore_master_p0_cke; -assign a7ddrphy_dfi_p0_odt = litedramcore_master_p0_odt; -assign a7ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n; -assign a7ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n; -assign a7ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata; -assign a7ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en; -assign a7ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask; -assign a7ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en; -assign litedramcore_master_p0_rddata = a7ddrphy_dfi_p0_rddata; -assign litedramcore_master_p0_rddata_valid = a7ddrphy_dfi_p0_rddata_valid; -assign a7ddrphy_dfi_p1_address = litedramcore_master_p1_address; -assign a7ddrphy_dfi_p1_bank = litedramcore_master_p1_bank; -assign a7ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n; -assign a7ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n; -assign a7ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n; -assign a7ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n; -assign a7ddrphy_dfi_p1_cke = litedramcore_master_p1_cke; -assign a7ddrphy_dfi_p1_odt = litedramcore_master_p1_odt; -assign a7ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n; -assign a7ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n; -assign a7ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata; -assign a7ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en; -assign a7ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask; -assign a7ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en; -assign litedramcore_master_p1_rddata = a7ddrphy_dfi_p1_rddata; -assign litedramcore_master_p1_rddata_valid = a7ddrphy_dfi_p1_rddata_valid; -assign a7ddrphy_dfi_p2_address = litedramcore_master_p2_address; -assign a7ddrphy_dfi_p2_bank = litedramcore_master_p2_bank; -assign a7ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n; -assign a7ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n; -assign a7ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n; -assign a7ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n; -assign a7ddrphy_dfi_p2_cke = litedramcore_master_p2_cke; -assign a7ddrphy_dfi_p2_odt = litedramcore_master_p2_odt; -assign a7ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n; -assign a7ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n; -assign a7ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata; -assign a7ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en; -assign a7ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask; -assign a7ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en; -assign litedramcore_master_p2_rddata = a7ddrphy_dfi_p2_rddata; -assign litedramcore_master_p2_rddata_valid = a7ddrphy_dfi_p2_rddata_valid; -assign a7ddrphy_dfi_p3_address = litedramcore_master_p3_address; -assign a7ddrphy_dfi_p3_bank = litedramcore_master_p3_bank; -assign a7ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n; -assign a7ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n; -assign a7ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n; -assign a7ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n; -assign a7ddrphy_dfi_p3_cke = litedramcore_master_p3_cke; -assign a7ddrphy_dfi_p3_odt = litedramcore_master_p3_odt; -assign a7ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n; -assign a7ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n; -assign a7ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata; -assign a7ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en; -assign a7ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask; -assign a7ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en; -assign litedramcore_master_p3_rddata = a7ddrphy_dfi_p3_rddata; -assign litedramcore_master_p3_rddata_valid = a7ddrphy_dfi_p3_rddata_valid; -assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address; -assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank; -assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n; -assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n; -assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n; -assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n; -assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke; -assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt; -assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n; -assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n; -assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata; -assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en; -assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask; -assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en; -assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata; -assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid; -assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address; -assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank; -assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n; -assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n; -assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n; -assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n; -assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke; -assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt; -assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n; -assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n; -assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata; -assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en; -assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask; -assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en; -assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata; -assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid; -assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address; -assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank; -assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n; -assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n; -assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n; -assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n; -assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke; -assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt; -assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n; -assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n; -assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata; -assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en; -assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask; -assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en; -assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata; -assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid; -assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address; -assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank; -assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n; -assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n; -assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n; -assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n; -assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke; -assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt; -assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n; -assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n; -assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata; -assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en; -assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask; -assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en; -assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata; -assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; -always @(*) begin - litedramcore_master_p3_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n; +assign main_a7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address; +assign main_a7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank; +assign main_a7ddrphy_dfi_p0_cas_n = main_litedramcore_master_p0_cas_n; +assign main_a7ddrphy_dfi_p0_cs_n = main_litedramcore_master_p0_cs_n; +assign main_a7ddrphy_dfi_p0_ras_n = main_litedramcore_master_p0_ras_n; +assign main_a7ddrphy_dfi_p0_we_n = main_litedramcore_master_p0_we_n; +assign main_a7ddrphy_dfi_p0_cke = main_litedramcore_master_p0_cke; +assign main_a7ddrphy_dfi_p0_odt = main_litedramcore_master_p0_odt; +assign main_a7ddrphy_dfi_p0_reset_n = main_litedramcore_master_p0_reset_n; +assign main_a7ddrphy_dfi_p0_act_n = main_litedramcore_master_p0_act_n; +assign main_a7ddrphy_dfi_p0_wrdata = main_litedramcore_master_p0_wrdata; +assign main_a7ddrphy_dfi_p0_wrdata_en = main_litedramcore_master_p0_wrdata_en; +assign main_a7ddrphy_dfi_p0_wrdata_mask = main_litedramcore_master_p0_wrdata_mask; +assign main_a7ddrphy_dfi_p0_rddata_en = main_litedramcore_master_p0_rddata_en; +assign main_litedramcore_master_p0_rddata = main_a7ddrphy_dfi_p0_rddata; +assign main_litedramcore_master_p0_rddata_valid = main_a7ddrphy_dfi_p0_rddata_valid; +assign main_a7ddrphy_dfi_p1_address = main_litedramcore_master_p1_address; +assign main_a7ddrphy_dfi_p1_bank = main_litedramcore_master_p1_bank; +assign main_a7ddrphy_dfi_p1_cas_n = main_litedramcore_master_p1_cas_n; +assign main_a7ddrphy_dfi_p1_cs_n = main_litedramcore_master_p1_cs_n; +assign main_a7ddrphy_dfi_p1_ras_n = main_litedramcore_master_p1_ras_n; +assign main_a7ddrphy_dfi_p1_we_n = main_litedramcore_master_p1_we_n; +assign main_a7ddrphy_dfi_p1_cke = main_litedramcore_master_p1_cke; +assign main_a7ddrphy_dfi_p1_odt = main_litedramcore_master_p1_odt; +assign main_a7ddrphy_dfi_p1_reset_n = main_litedramcore_master_p1_reset_n; +assign main_a7ddrphy_dfi_p1_act_n = main_litedramcore_master_p1_act_n; +assign main_a7ddrphy_dfi_p1_wrdata = main_litedramcore_master_p1_wrdata; +assign main_a7ddrphy_dfi_p1_wrdata_en = main_litedramcore_master_p1_wrdata_en; +assign main_a7ddrphy_dfi_p1_wrdata_mask = main_litedramcore_master_p1_wrdata_mask; +assign main_a7ddrphy_dfi_p1_rddata_en = main_litedramcore_master_p1_rddata_en; +assign main_litedramcore_master_p1_rddata = main_a7ddrphy_dfi_p1_rddata; +assign main_litedramcore_master_p1_rddata_valid = main_a7ddrphy_dfi_p1_rddata_valid; +assign main_a7ddrphy_dfi_p2_address = main_litedramcore_master_p2_address; +assign main_a7ddrphy_dfi_p2_bank = main_litedramcore_master_p2_bank; +assign main_a7ddrphy_dfi_p2_cas_n = main_litedramcore_master_p2_cas_n; +assign main_a7ddrphy_dfi_p2_cs_n = main_litedramcore_master_p2_cs_n; +assign main_a7ddrphy_dfi_p2_ras_n = main_litedramcore_master_p2_ras_n; +assign main_a7ddrphy_dfi_p2_we_n = main_litedramcore_master_p2_we_n; +assign main_a7ddrphy_dfi_p2_cke = main_litedramcore_master_p2_cke; +assign main_a7ddrphy_dfi_p2_odt = main_litedramcore_master_p2_odt; +assign main_a7ddrphy_dfi_p2_reset_n = main_litedramcore_master_p2_reset_n; +assign main_a7ddrphy_dfi_p2_act_n = main_litedramcore_master_p2_act_n; +assign main_a7ddrphy_dfi_p2_wrdata = main_litedramcore_master_p2_wrdata; +assign main_a7ddrphy_dfi_p2_wrdata_en = main_litedramcore_master_p2_wrdata_en; +assign main_a7ddrphy_dfi_p2_wrdata_mask = main_litedramcore_master_p2_wrdata_mask; +assign main_a7ddrphy_dfi_p2_rddata_en = main_litedramcore_master_p2_rddata_en; +assign main_litedramcore_master_p2_rddata = main_a7ddrphy_dfi_p2_rddata; +assign main_litedramcore_master_p2_rddata_valid = main_a7ddrphy_dfi_p2_rddata_valid; +assign main_a7ddrphy_dfi_p3_address = main_litedramcore_master_p3_address; +assign main_a7ddrphy_dfi_p3_bank = main_litedramcore_master_p3_bank; +assign main_a7ddrphy_dfi_p3_cas_n = main_litedramcore_master_p3_cas_n; +assign main_a7ddrphy_dfi_p3_cs_n = main_litedramcore_master_p3_cs_n; +assign main_a7ddrphy_dfi_p3_ras_n = main_litedramcore_master_p3_ras_n; +assign main_a7ddrphy_dfi_p3_we_n = main_litedramcore_master_p3_we_n; +assign main_a7ddrphy_dfi_p3_cke = main_litedramcore_master_p3_cke; +assign main_a7ddrphy_dfi_p3_odt = main_litedramcore_master_p3_odt; +assign main_a7ddrphy_dfi_p3_reset_n = main_litedramcore_master_p3_reset_n; +assign main_a7ddrphy_dfi_p3_act_n = main_litedramcore_master_p3_act_n; +assign main_a7ddrphy_dfi_p3_wrdata = main_litedramcore_master_p3_wrdata; +assign main_a7ddrphy_dfi_p3_wrdata_en = main_litedramcore_master_p3_wrdata_en; +assign main_a7ddrphy_dfi_p3_wrdata_mask = main_litedramcore_master_p3_wrdata_mask; +assign main_a7ddrphy_dfi_p3_rddata_en = main_litedramcore_master_p3_rddata_en; +assign main_litedramcore_master_p3_rddata = main_a7ddrphy_dfi_p3_rddata; +assign main_litedramcore_master_p3_rddata_valid = main_a7ddrphy_dfi_p3_rddata_valid; +assign main_litedramcore_slave_p0_address = main_litedramcore_dfi_p0_address; +assign main_litedramcore_slave_p0_bank = main_litedramcore_dfi_p0_bank; +assign main_litedramcore_slave_p0_cas_n = main_litedramcore_dfi_p0_cas_n; +assign main_litedramcore_slave_p0_cs_n = main_litedramcore_dfi_p0_cs_n; +assign main_litedramcore_slave_p0_ras_n = main_litedramcore_dfi_p0_ras_n; +assign main_litedramcore_slave_p0_we_n = main_litedramcore_dfi_p0_we_n; +assign main_litedramcore_slave_p0_cke = main_litedramcore_dfi_p0_cke; +assign main_litedramcore_slave_p0_odt = main_litedramcore_dfi_p0_odt; +assign main_litedramcore_slave_p0_reset_n = main_litedramcore_dfi_p0_reset_n; +assign main_litedramcore_slave_p0_act_n = main_litedramcore_dfi_p0_act_n; +assign main_litedramcore_slave_p0_wrdata = main_litedramcore_dfi_p0_wrdata; +assign main_litedramcore_slave_p0_wrdata_en = main_litedramcore_dfi_p0_wrdata_en; +assign main_litedramcore_slave_p0_wrdata_mask = main_litedramcore_dfi_p0_wrdata_mask; +assign main_litedramcore_slave_p0_rddata_en = main_litedramcore_dfi_p0_rddata_en; +assign main_litedramcore_dfi_p0_rddata = main_litedramcore_slave_p0_rddata; +assign main_litedramcore_dfi_p0_rddata_valid = main_litedramcore_slave_p0_rddata_valid; +assign main_litedramcore_slave_p1_address = main_litedramcore_dfi_p1_address; +assign main_litedramcore_slave_p1_bank = main_litedramcore_dfi_p1_bank; +assign main_litedramcore_slave_p1_cas_n = main_litedramcore_dfi_p1_cas_n; +assign main_litedramcore_slave_p1_cs_n = main_litedramcore_dfi_p1_cs_n; +assign main_litedramcore_slave_p1_ras_n = main_litedramcore_dfi_p1_ras_n; +assign main_litedramcore_slave_p1_we_n = main_litedramcore_dfi_p1_we_n; +assign main_litedramcore_slave_p1_cke = main_litedramcore_dfi_p1_cke; +assign main_litedramcore_slave_p1_odt = main_litedramcore_dfi_p1_odt; +assign main_litedramcore_slave_p1_reset_n = main_litedramcore_dfi_p1_reset_n; +assign main_litedramcore_slave_p1_act_n = main_litedramcore_dfi_p1_act_n; +assign main_litedramcore_slave_p1_wrdata = main_litedramcore_dfi_p1_wrdata; +assign main_litedramcore_slave_p1_wrdata_en = main_litedramcore_dfi_p1_wrdata_en; +assign main_litedramcore_slave_p1_wrdata_mask = main_litedramcore_dfi_p1_wrdata_mask; +assign main_litedramcore_slave_p1_rddata_en = main_litedramcore_dfi_p1_rddata_en; +assign main_litedramcore_dfi_p1_rddata = main_litedramcore_slave_p1_rddata; +assign main_litedramcore_dfi_p1_rddata_valid = main_litedramcore_slave_p1_rddata_valid; +assign main_litedramcore_slave_p2_address = main_litedramcore_dfi_p2_address; +assign main_litedramcore_slave_p2_bank = main_litedramcore_dfi_p2_bank; +assign main_litedramcore_slave_p2_cas_n = main_litedramcore_dfi_p2_cas_n; +assign main_litedramcore_slave_p2_cs_n = main_litedramcore_dfi_p2_cs_n; +assign main_litedramcore_slave_p2_ras_n = main_litedramcore_dfi_p2_ras_n; +assign main_litedramcore_slave_p2_we_n = main_litedramcore_dfi_p2_we_n; +assign main_litedramcore_slave_p2_cke = main_litedramcore_dfi_p2_cke; +assign main_litedramcore_slave_p2_odt = main_litedramcore_dfi_p2_odt; +assign main_litedramcore_slave_p2_reset_n = main_litedramcore_dfi_p2_reset_n; +assign main_litedramcore_slave_p2_act_n = main_litedramcore_dfi_p2_act_n; +assign main_litedramcore_slave_p2_wrdata = main_litedramcore_dfi_p2_wrdata; +assign main_litedramcore_slave_p2_wrdata_en = main_litedramcore_dfi_p2_wrdata_en; +assign main_litedramcore_slave_p2_wrdata_mask = main_litedramcore_dfi_p2_wrdata_mask; +assign main_litedramcore_slave_p2_rddata_en = main_litedramcore_dfi_p2_rddata_en; +assign main_litedramcore_dfi_p2_rddata = main_litedramcore_slave_p2_rddata; +assign main_litedramcore_dfi_p2_rddata_valid = main_litedramcore_slave_p2_rddata_valid; +assign main_litedramcore_slave_p3_address = main_litedramcore_dfi_p3_address; +assign main_litedramcore_slave_p3_bank = main_litedramcore_dfi_p3_bank; +assign main_litedramcore_slave_p3_cas_n = main_litedramcore_dfi_p3_cas_n; +assign main_litedramcore_slave_p3_cs_n = main_litedramcore_dfi_p3_cs_n; +assign main_litedramcore_slave_p3_ras_n = main_litedramcore_dfi_p3_ras_n; +assign main_litedramcore_slave_p3_we_n = main_litedramcore_dfi_p3_we_n; +assign main_litedramcore_slave_p3_cke = main_litedramcore_dfi_p3_cke; +assign main_litedramcore_slave_p3_odt = main_litedramcore_dfi_p3_odt; +assign main_litedramcore_slave_p3_reset_n = main_litedramcore_dfi_p3_reset_n; +assign main_litedramcore_slave_p3_act_n = main_litedramcore_dfi_p3_act_n; +assign main_litedramcore_slave_p3_wrdata = main_litedramcore_dfi_p3_wrdata; +assign main_litedramcore_slave_p3_wrdata_en = main_litedramcore_dfi_p3_wrdata_en; +assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_mask; +assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en; +assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata; +assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid; +always @(*) begin + main_litedramcore_master_p3_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_ras_n <= main_litedramcore_ext_dfi_p3_ras_n; end else begin - litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; + main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n; end end else begin - litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n; + main_litedramcore_master_p3_ras_n <= main_litedramcore_csr_dfi_p3_ras_n; end end always @(*) begin - litedramcore_master_p3_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n; + main_litedramcore_master_p3_we_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_we_n <= main_litedramcore_ext_dfi_p3_we_n; end else begin - litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; + main_litedramcore_master_p3_we_n <= main_litedramcore_slave_p3_we_n; end end else begin - litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n; + main_litedramcore_master_p3_we_n <= main_litedramcore_csr_dfi_p3_we_n; end end always @(*) begin - litedramcore_master_p3_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke; + main_litedramcore_master_p3_cke <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_cke <= main_litedramcore_ext_dfi_p3_cke; end else begin - litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; + main_litedramcore_master_p3_cke <= main_litedramcore_slave_p3_cke; end end else begin - litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke; + main_litedramcore_master_p3_cke <= main_litedramcore_csr_dfi_p3_cke; end end always @(*) begin - litedramcore_master_p3_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt; + main_litedramcore_master_p3_odt <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_odt <= main_litedramcore_ext_dfi_p3_odt; end else begin - litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; + main_litedramcore_master_p3_odt <= main_litedramcore_slave_p3_odt; end end else begin - litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt; + main_litedramcore_master_p3_odt <= main_litedramcore_csr_dfi_p3_odt; end end always @(*) begin - litedramcore_master_p3_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n; + main_litedramcore_master_p3_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_reset_n <= main_litedramcore_ext_dfi_p3_reset_n; end else begin - litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; + main_litedramcore_master_p3_reset_n <= main_litedramcore_slave_p3_reset_n; end end else begin - litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n; + main_litedramcore_master_p3_reset_n <= main_litedramcore_csr_dfi_p3_reset_n; end end always @(*) begin - litedramcore_master_p3_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n; + main_litedramcore_master_p3_act_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_act_n <= main_litedramcore_ext_dfi_p3_act_n; end else begin - litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; + main_litedramcore_master_p3_act_n <= main_litedramcore_slave_p3_act_n; end end else begin - litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n; + main_litedramcore_master_p3_act_n <= main_litedramcore_csr_dfi_p3_act_n; end end always @(*) begin - litedramcore_master_p3_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata; + main_litedramcore_master_p3_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_wrdata <= main_litedramcore_ext_dfi_p3_wrdata; end else begin - litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; + main_litedramcore_master_p3_wrdata <= main_litedramcore_slave_p3_wrdata; end end else begin - litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata; + main_litedramcore_master_p3_wrdata <= main_litedramcore_csr_dfi_p3_wrdata; end end always @(*) begin - litedramcore_master_p3_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en; + main_litedramcore_master_p3_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_wrdata_en <= main_litedramcore_ext_dfi_p3_wrdata_en; end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; + main_litedramcore_master_p3_wrdata_en <= main_litedramcore_slave_p3_wrdata_en; end end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en; + main_litedramcore_master_p3_wrdata_en <= main_litedramcore_csr_dfi_p3_wrdata_en; end end always @(*) begin - litedramcore_master_p3_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask; + main_litedramcore_master_p3_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_ext_dfi_p3_wrdata_mask; end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; + main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_slave_p3_wrdata_mask; end end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask; + main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_csr_dfi_p3_wrdata_mask; end end always @(*) begin - litedramcore_master_p3_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en; + main_litedramcore_master_p3_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_rddata_en <= main_litedramcore_ext_dfi_p3_rddata_en; end else begin - litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; + main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en; end end else begin - litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en; + main_litedramcore_master_p3_rddata_en <= main_litedramcore_csr_dfi_p3_rddata_en; end end always @(*) begin - litedramcore_csr_dfi_p0_rddata <= 32'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p0_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata; + main_litedramcore_csr_dfi_p0_rddata <= main_litedramcore_master_p0_rddata; end end always @(*) begin - litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + main_litedramcore_csr_dfi_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end end always @(*) begin - litedramcore_csr_dfi_p1_rddata <= 32'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p1_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata; + main_litedramcore_csr_dfi_p1_rddata <= main_litedramcore_master_p1_rddata; end end always @(*) begin - litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + main_litedramcore_csr_dfi_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end end always @(*) begin - litedramcore_csr_dfi_p2_rddata <= 32'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p2_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata; + main_litedramcore_csr_dfi_p2_rddata <= main_litedramcore_master_p2_rddata; end end always @(*) begin - litedramcore_csr_dfi_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p2_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + main_litedramcore_csr_dfi_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end end always @(*) begin - litedramcore_csr_dfi_p3_rddata <= 32'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p3_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata; + main_litedramcore_csr_dfi_p3_rddata <= main_litedramcore_master_p3_rddata; end end always @(*) begin - litedramcore_csr_dfi_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p3_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + main_litedramcore_csr_dfi_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end end always @(*) begin - litedramcore_ext_dfi_p0_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata; + main_litedramcore_ext_dfi_p0_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p0_rddata <= main_litedramcore_master_p0_rddata; end else begin end end else begin end end always @(*) begin - litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + main_litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end else begin end end else begin end end always @(*) begin - litedramcore_ext_dfi_p1_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata; + main_litedramcore_ext_dfi_p1_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p1_rddata <= main_litedramcore_master_p1_rddata; end else begin end end else begin end end always @(*) begin - litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + main_litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end else begin end end else begin end end always @(*) begin - litedramcore_ext_dfi_p2_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata; + main_litedramcore_ext_dfi_p2_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p2_rddata <= main_litedramcore_master_p2_rddata; end else begin end end else begin end end always @(*) begin - litedramcore_ext_dfi_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + main_litedramcore_ext_dfi_p2_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end else begin end end else begin end end always @(*) begin - litedramcore_slave_p0_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p0_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; + main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata; end end else begin end end always @(*) begin - litedramcore_slave_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end end else begin end end always @(*) begin - litedramcore_ext_dfi_p3_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata; + main_litedramcore_ext_dfi_p3_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p3_rddata <= main_litedramcore_master_p3_rddata; end else begin end end else begin end end always @(*) begin - litedramcore_ext_dfi_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + main_litedramcore_ext_dfi_p3_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end else begin end end else begin end end always @(*) begin - litedramcore_slave_p1_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p1_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; + main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata; end end else begin end end always @(*) begin - litedramcore_slave_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p1_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end end else begin end end always @(*) begin - litedramcore_slave_p2_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p2_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; + main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata; end end else begin end end always @(*) begin - litedramcore_slave_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p2_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end end else begin end end always @(*) begin - litedramcore_slave_p3_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p3_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; + main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata; end end else begin end end always @(*) begin - litedramcore_slave_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p3_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end end else begin end end always @(*) begin - litedramcore_master_p0_address <= 16'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address; + main_litedramcore_master_p0_address <= 16'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_address <= main_litedramcore_ext_dfi_p0_address; end else begin - litedramcore_master_p0_address <= litedramcore_slave_p0_address; + main_litedramcore_master_p0_address <= main_litedramcore_slave_p0_address; end end else begin - litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address; + main_litedramcore_master_p0_address <= main_litedramcore_csr_dfi_p0_address; end end always @(*) begin - litedramcore_master_p0_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank; + main_litedramcore_master_p0_bank <= 3'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_bank <= main_litedramcore_ext_dfi_p0_bank; end else begin - litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; + main_litedramcore_master_p0_bank <= main_litedramcore_slave_p0_bank; end end else begin - litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank; + main_litedramcore_master_p0_bank <= main_litedramcore_csr_dfi_p0_bank; end end always @(*) begin - litedramcore_master_p0_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n; + main_litedramcore_master_p0_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_cas_n <= main_litedramcore_ext_dfi_p0_cas_n; end else begin - litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; + main_litedramcore_master_p0_cas_n <= main_litedramcore_slave_p0_cas_n; end end else begin - litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n; + main_litedramcore_master_p0_cas_n <= main_litedramcore_csr_dfi_p0_cas_n; end end always @(*) begin - litedramcore_master_p0_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n; + main_litedramcore_master_p0_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_cs_n <= main_litedramcore_ext_dfi_p0_cs_n; end else begin - litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; + main_litedramcore_master_p0_cs_n <= main_litedramcore_slave_p0_cs_n; + if (1'd0) begin + main_litedramcore_master_p0_cs_n <= {2{main_litedramcore_slave_p0_cs_n}}; + end end end else begin - litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n; + main_litedramcore_master_p0_cs_n <= main_litedramcore_csr_dfi_p0_cs_n; end end always @(*) begin - litedramcore_master_p0_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n; + main_litedramcore_master_p0_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_ras_n <= main_litedramcore_ext_dfi_p0_ras_n; end else begin - litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; + main_litedramcore_master_p0_ras_n <= main_litedramcore_slave_p0_ras_n; end end else begin - litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n; + main_litedramcore_master_p0_ras_n <= main_litedramcore_csr_dfi_p0_ras_n; end end always @(*) begin - litedramcore_master_p0_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n; + main_litedramcore_master_p0_we_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_we_n <= main_litedramcore_ext_dfi_p0_we_n; end else begin - litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + main_litedramcore_master_p0_we_n <= main_litedramcore_slave_p0_we_n; end end else begin - litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n; + main_litedramcore_master_p0_we_n <= main_litedramcore_csr_dfi_p0_we_n; end end always @(*) begin - litedramcore_master_p0_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke; + main_litedramcore_master_p0_cke <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_cke <= main_litedramcore_ext_dfi_p0_cke; end else begin - litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; + main_litedramcore_master_p0_cke <= main_litedramcore_slave_p0_cke; end end else begin - litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke; + main_litedramcore_master_p0_cke <= main_litedramcore_csr_dfi_p0_cke; end end always @(*) begin - litedramcore_master_p0_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt; + main_litedramcore_master_p0_odt <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_odt <= main_litedramcore_ext_dfi_p0_odt; end else begin - litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; + main_litedramcore_master_p0_odt <= main_litedramcore_slave_p0_odt; end end else begin - litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt; + main_litedramcore_master_p0_odt <= main_litedramcore_csr_dfi_p0_odt; end end always @(*) begin - litedramcore_master_p0_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n; + main_litedramcore_master_p0_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_reset_n <= main_litedramcore_ext_dfi_p0_reset_n; end else begin - litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; + main_litedramcore_master_p0_reset_n <= main_litedramcore_slave_p0_reset_n; end end else begin - litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n; + main_litedramcore_master_p0_reset_n <= main_litedramcore_csr_dfi_p0_reset_n; end end always @(*) begin - litedramcore_master_p0_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n; + main_litedramcore_master_p0_act_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_act_n <= main_litedramcore_ext_dfi_p0_act_n; end else begin - litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; + main_litedramcore_master_p0_act_n <= main_litedramcore_slave_p0_act_n; end end else begin - litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n; + main_litedramcore_master_p0_act_n <= main_litedramcore_csr_dfi_p0_act_n; end end always @(*) begin - litedramcore_master_p0_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata; + main_litedramcore_master_p0_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_wrdata <= main_litedramcore_ext_dfi_p0_wrdata; end else begin - litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; + main_litedramcore_master_p0_wrdata <= main_litedramcore_slave_p0_wrdata; end end else begin - litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata; + main_litedramcore_master_p0_wrdata <= main_litedramcore_csr_dfi_p0_wrdata; end end always @(*) begin - litedramcore_master_p0_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en; + main_litedramcore_master_p0_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_wrdata_en <= main_litedramcore_ext_dfi_p0_wrdata_en; end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; + main_litedramcore_master_p0_wrdata_en <= main_litedramcore_slave_p0_wrdata_en; end end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en; + main_litedramcore_master_p0_wrdata_en <= main_litedramcore_csr_dfi_p0_wrdata_en; end end always @(*) begin - litedramcore_master_p0_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask; + main_litedramcore_master_p0_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_ext_dfi_p0_wrdata_mask; end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_slave_p0_wrdata_mask; end end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask; + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_csr_dfi_p0_wrdata_mask; end end always @(*) begin - litedramcore_master_p0_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en; + main_litedramcore_master_p0_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_rddata_en <= main_litedramcore_ext_dfi_p0_rddata_en; end else begin - litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; + main_litedramcore_master_p0_rddata_en <= main_litedramcore_slave_p0_rddata_en; end end else begin - litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en; + main_litedramcore_master_p0_rddata_en <= main_litedramcore_csr_dfi_p0_rddata_en; end end always @(*) begin - litedramcore_master_p1_address <= 16'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address; + main_litedramcore_master_p1_address <= 16'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_address <= main_litedramcore_ext_dfi_p1_address; end else begin - litedramcore_master_p1_address <= litedramcore_slave_p1_address; + main_litedramcore_master_p1_address <= main_litedramcore_slave_p1_address; end end else begin - litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address; + main_litedramcore_master_p1_address <= main_litedramcore_csr_dfi_p1_address; end end always @(*) begin - litedramcore_master_p1_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank; + main_litedramcore_master_p1_bank <= 3'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_bank <= main_litedramcore_ext_dfi_p1_bank; end else begin - litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; + main_litedramcore_master_p1_bank <= main_litedramcore_slave_p1_bank; end end else begin - litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank; + main_litedramcore_master_p1_bank <= main_litedramcore_csr_dfi_p1_bank; end end always @(*) begin - litedramcore_master_p1_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n; + main_litedramcore_master_p1_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_cas_n <= main_litedramcore_ext_dfi_p1_cas_n; end else begin - litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; + main_litedramcore_master_p1_cas_n <= main_litedramcore_slave_p1_cas_n; end end else begin - litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n; + main_litedramcore_master_p1_cas_n <= main_litedramcore_csr_dfi_p1_cas_n; end end always @(*) begin - litedramcore_master_p1_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n; + main_litedramcore_master_p1_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_cs_n <= main_litedramcore_ext_dfi_p1_cs_n; end else begin - litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; + main_litedramcore_master_p1_cs_n <= main_litedramcore_slave_p1_cs_n; + if (1'd0) begin + main_litedramcore_master_p1_cs_n <= {2{main_litedramcore_slave_p1_cs_n}}; + end end end else begin - litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n; + main_litedramcore_master_p1_cs_n <= main_litedramcore_csr_dfi_p1_cs_n; end end always @(*) begin - litedramcore_master_p1_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n; + main_litedramcore_master_p1_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_ras_n <= main_litedramcore_ext_dfi_p1_ras_n; end else begin - litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; + main_litedramcore_master_p1_ras_n <= main_litedramcore_slave_p1_ras_n; end end else begin - litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n; + main_litedramcore_master_p1_ras_n <= main_litedramcore_csr_dfi_p1_ras_n; end end always @(*) begin - litedramcore_master_p1_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n; + main_litedramcore_master_p1_we_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_we_n <= main_litedramcore_ext_dfi_p1_we_n; end else begin - litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; + main_litedramcore_master_p1_we_n <= main_litedramcore_slave_p1_we_n; end end else begin - litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n; + main_litedramcore_master_p1_we_n <= main_litedramcore_csr_dfi_p1_we_n; end end always @(*) begin - litedramcore_master_p1_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke; + main_litedramcore_master_p1_cke <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_cke <= main_litedramcore_ext_dfi_p1_cke; end else begin - litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; + main_litedramcore_master_p1_cke <= main_litedramcore_slave_p1_cke; end end else begin - litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke; + main_litedramcore_master_p1_cke <= main_litedramcore_csr_dfi_p1_cke; end end always @(*) begin - litedramcore_master_p1_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt; + main_litedramcore_master_p1_odt <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_odt <= main_litedramcore_ext_dfi_p1_odt; end else begin - litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; + main_litedramcore_master_p1_odt <= main_litedramcore_slave_p1_odt; end end else begin - litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt; + main_litedramcore_master_p1_odt <= main_litedramcore_csr_dfi_p1_odt; end end always @(*) begin - litedramcore_master_p1_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n; + main_litedramcore_master_p1_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_reset_n <= main_litedramcore_ext_dfi_p1_reset_n; end else begin - litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; + main_litedramcore_master_p1_reset_n <= main_litedramcore_slave_p1_reset_n; end end else begin - litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n; + main_litedramcore_master_p1_reset_n <= main_litedramcore_csr_dfi_p1_reset_n; end end always @(*) begin - litedramcore_master_p1_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n; + main_litedramcore_master_p1_act_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_act_n <= main_litedramcore_ext_dfi_p1_act_n; end else begin - litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; + main_litedramcore_master_p1_act_n <= main_litedramcore_slave_p1_act_n; end end else begin - litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n; + main_litedramcore_master_p1_act_n <= main_litedramcore_csr_dfi_p1_act_n; end end always @(*) begin - litedramcore_master_p1_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata; + main_litedramcore_master_p1_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_wrdata <= main_litedramcore_ext_dfi_p1_wrdata; end else begin - litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; + main_litedramcore_master_p1_wrdata <= main_litedramcore_slave_p1_wrdata; end end else begin - litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata; + main_litedramcore_master_p1_wrdata <= main_litedramcore_csr_dfi_p1_wrdata; end end always @(*) begin - litedramcore_master_p1_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en; + main_litedramcore_master_p1_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_wrdata_en <= main_litedramcore_ext_dfi_p1_wrdata_en; end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; + main_litedramcore_master_p1_wrdata_en <= main_litedramcore_slave_p1_wrdata_en; end end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en; + main_litedramcore_master_p1_wrdata_en <= main_litedramcore_csr_dfi_p1_wrdata_en; end end always @(*) begin - litedramcore_master_p1_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask; + main_litedramcore_master_p1_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_ext_dfi_p1_wrdata_mask; end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; + main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_slave_p1_wrdata_mask; end end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask; + main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_csr_dfi_p1_wrdata_mask; end end always @(*) begin - litedramcore_master_p1_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en; + main_litedramcore_master_p1_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_rddata_en <= main_litedramcore_ext_dfi_p1_rddata_en; end else begin - litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; + main_litedramcore_master_p1_rddata_en <= main_litedramcore_slave_p1_rddata_en; end end else begin - litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en; + main_litedramcore_master_p1_rddata_en <= main_litedramcore_csr_dfi_p1_rddata_en; end end always @(*) begin - litedramcore_master_p2_address <= 16'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address; + main_litedramcore_master_p2_address <= 16'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_address <= main_litedramcore_ext_dfi_p2_address; end else begin - litedramcore_master_p2_address <= litedramcore_slave_p2_address; + main_litedramcore_master_p2_address <= main_litedramcore_slave_p2_address; end end else begin - litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address; + main_litedramcore_master_p2_address <= main_litedramcore_csr_dfi_p2_address; end end always @(*) begin - litedramcore_master_p2_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank; + main_litedramcore_master_p2_bank <= 3'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_bank <= main_litedramcore_ext_dfi_p2_bank; end else begin - litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; + main_litedramcore_master_p2_bank <= main_litedramcore_slave_p2_bank; end end else begin - litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank; + main_litedramcore_master_p2_bank <= main_litedramcore_csr_dfi_p2_bank; end end always @(*) begin - litedramcore_master_p2_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n; + main_litedramcore_master_p2_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_cas_n <= main_litedramcore_ext_dfi_p2_cas_n; end else begin - litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; + main_litedramcore_master_p2_cas_n <= main_litedramcore_slave_p2_cas_n; end end else begin - litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n; + main_litedramcore_master_p2_cas_n <= main_litedramcore_csr_dfi_p2_cas_n; end end always @(*) begin - litedramcore_master_p2_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n; + main_litedramcore_master_p2_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_cs_n <= main_litedramcore_ext_dfi_p2_cs_n; end else begin - litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; + main_litedramcore_master_p2_cs_n <= main_litedramcore_slave_p2_cs_n; + if (1'd0) begin + main_litedramcore_master_p2_cs_n <= {2{main_litedramcore_slave_p2_cs_n}}; + end end end else begin - litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n; + main_litedramcore_master_p2_cs_n <= main_litedramcore_csr_dfi_p2_cs_n; end end always @(*) begin - litedramcore_master_p2_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n; + main_litedramcore_master_p2_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_ras_n <= main_litedramcore_ext_dfi_p2_ras_n; end else begin - litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; + main_litedramcore_master_p2_ras_n <= main_litedramcore_slave_p2_ras_n; end end else begin - litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n; + main_litedramcore_master_p2_ras_n <= main_litedramcore_csr_dfi_p2_ras_n; end end always @(*) begin - litedramcore_master_p2_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n; + main_litedramcore_master_p2_we_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_we_n <= main_litedramcore_ext_dfi_p2_we_n; end else begin - litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; + main_litedramcore_master_p2_we_n <= main_litedramcore_slave_p2_we_n; end end else begin - litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n; + main_litedramcore_master_p2_we_n <= main_litedramcore_csr_dfi_p2_we_n; end end always @(*) begin - litedramcore_master_p2_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke; + main_litedramcore_master_p2_cke <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_cke <= main_litedramcore_ext_dfi_p2_cke; end else begin - litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; + main_litedramcore_master_p2_cke <= main_litedramcore_slave_p2_cke; end end else begin - litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke; + main_litedramcore_master_p2_cke <= main_litedramcore_csr_dfi_p2_cke; end end always @(*) begin - litedramcore_master_p2_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt; + main_litedramcore_master_p2_odt <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_odt <= main_litedramcore_ext_dfi_p2_odt; end else begin - litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; + main_litedramcore_master_p2_odt <= main_litedramcore_slave_p2_odt; end end else begin - litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt; + main_litedramcore_master_p2_odt <= main_litedramcore_csr_dfi_p2_odt; end end always @(*) begin - litedramcore_master_p2_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n; + main_litedramcore_master_p2_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_reset_n <= main_litedramcore_ext_dfi_p2_reset_n; end else begin - litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; + main_litedramcore_master_p2_reset_n <= main_litedramcore_slave_p2_reset_n; end end else begin - litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n; + main_litedramcore_master_p2_reset_n <= main_litedramcore_csr_dfi_p2_reset_n; end end always @(*) begin - litedramcore_master_p2_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n; + main_litedramcore_master_p2_act_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_act_n <= main_litedramcore_ext_dfi_p2_act_n; end else begin - litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; + main_litedramcore_master_p2_act_n <= main_litedramcore_slave_p2_act_n; end end else begin - litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n; + main_litedramcore_master_p2_act_n <= main_litedramcore_csr_dfi_p2_act_n; end end always @(*) begin - litedramcore_master_p2_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata; + main_litedramcore_master_p2_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_wrdata <= main_litedramcore_ext_dfi_p2_wrdata; end else begin - litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; + main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata; end end else begin - litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata; + main_litedramcore_master_p2_wrdata <= main_litedramcore_csr_dfi_p2_wrdata; end end always @(*) begin - litedramcore_master_p2_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en; + main_litedramcore_master_p2_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_wrdata_en <= main_litedramcore_ext_dfi_p2_wrdata_en; end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; + main_litedramcore_master_p2_wrdata_en <= main_litedramcore_slave_p2_wrdata_en; end end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en; + main_litedramcore_master_p2_wrdata_en <= main_litedramcore_csr_dfi_p2_wrdata_en; end end always @(*) begin - litedramcore_master_p2_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask; + main_litedramcore_master_p2_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_ext_dfi_p2_wrdata_mask; end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; + main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_slave_p2_wrdata_mask; end end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask; + main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_csr_dfi_p2_wrdata_mask; end end always @(*) begin - litedramcore_master_p2_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en; + main_litedramcore_master_p2_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_rddata_en <= main_litedramcore_ext_dfi_p2_rddata_en; end else begin - litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; + main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en; end end else begin - litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en; + main_litedramcore_master_p2_rddata_en <= main_litedramcore_csr_dfi_p2_rddata_en; end end always @(*) begin - litedramcore_master_p3_address <= 16'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address; + main_litedramcore_master_p3_address <= 16'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_address <= main_litedramcore_ext_dfi_p3_address; end else begin - litedramcore_master_p3_address <= litedramcore_slave_p3_address; + main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address; end end else begin - litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address; + main_litedramcore_master_p3_address <= main_litedramcore_csr_dfi_p3_address; end end always @(*) begin - litedramcore_master_p3_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank; + main_litedramcore_master_p3_bank <= 3'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_bank <= main_litedramcore_ext_dfi_p3_bank; end else begin - litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; + main_litedramcore_master_p3_bank <= main_litedramcore_slave_p3_bank; end end else begin - litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank; + main_litedramcore_master_p3_bank <= main_litedramcore_csr_dfi_p3_bank; end end always @(*) begin - litedramcore_master_p3_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n; + main_litedramcore_master_p3_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_cas_n <= main_litedramcore_ext_dfi_p3_cas_n; end else begin - litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; + main_litedramcore_master_p3_cas_n <= main_litedramcore_slave_p3_cas_n; end end else begin - litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n; + main_litedramcore_master_p3_cas_n <= main_litedramcore_csr_dfi_p3_cas_n; end end always @(*) begin - litedramcore_master_p3_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n; + main_litedramcore_master_p3_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_cs_n <= main_litedramcore_ext_dfi_p3_cs_n; end else begin - litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; + main_litedramcore_master_p3_cs_n <= main_litedramcore_slave_p3_cs_n; + if (1'd0) begin + main_litedramcore_master_p3_cs_n <= {2{main_litedramcore_slave_p3_cs_n}}; + end end end else begin - litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n; - end -end -assign litedramcore_csr_dfi_p0_cke = litedramcore_cke; -assign litedramcore_csr_dfi_p1_cke = litedramcore_cke; -assign litedramcore_csr_dfi_p2_cke = litedramcore_cke; -assign litedramcore_csr_dfi_p3_cke = litedramcore_cke; -assign litedramcore_csr_dfi_p0_odt = litedramcore_odt; -assign litedramcore_csr_dfi_p1_odt = litedramcore_odt; -assign litedramcore_csr_dfi_p2_odt = litedramcore_odt; -assign litedramcore_csr_dfi_p3_odt = litedramcore_odt; -assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n; -assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n; -assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n; -assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n; -always @(*) begin - litedramcore_csr_dfi_p0_cas_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas); + main_litedramcore_master_p3_cs_n <= main_litedramcore_csr_dfi_p3_cs_n; + end +end +always @(*) begin + main_litedramcore_csr_dfi_p0_cke <= 1'd0; + main_litedramcore_csr_dfi_p0_cke <= main_litedramcore_cke; +end +always @(*) begin + main_litedramcore_csr_dfi_p1_cke <= 1'd0; + main_litedramcore_csr_dfi_p1_cke <= main_litedramcore_cke; +end +always @(*) begin + main_litedramcore_csr_dfi_p2_cke <= 1'd0; + main_litedramcore_csr_dfi_p2_cke <= main_litedramcore_cke; +end +always @(*) begin + main_litedramcore_csr_dfi_p3_cke <= 1'd0; + main_litedramcore_csr_dfi_p3_cke <= main_litedramcore_cke; +end +always @(*) begin + main_litedramcore_csr_dfi_p0_odt <= 1'd0; + main_litedramcore_csr_dfi_p0_odt <= main_litedramcore_odt; +end +always @(*) begin + main_litedramcore_csr_dfi_p1_odt <= 1'd0; + main_litedramcore_csr_dfi_p1_odt <= main_litedramcore_odt; +end +always @(*) begin + main_litedramcore_csr_dfi_p2_odt <= 1'd0; + main_litedramcore_csr_dfi_p2_odt <= main_litedramcore_odt; +end +always @(*) begin + main_litedramcore_csr_dfi_p3_odt <= 1'd0; + main_litedramcore_csr_dfi_p3_odt <= main_litedramcore_odt; +end +assign main_litedramcore_csr_dfi_p0_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_csr_dfi_p1_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_csr_dfi_p2_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_csr_dfi_p3_reset_n = main_litedramcore_reset_n; +always @(*) begin + main_litedramcore_csr_dfi_p0_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_csr_dfi_p0_cas_n <= (~main_litedramcore_phaseinjector0_csrfield_cas); end else begin - litedramcore_csr_dfi_p0_cas_n <= 1'd1; + main_litedramcore_csr_dfi_p0_cas_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p0_cs_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}}; + main_litedramcore_csr_dfi_p0_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + if (main_litedramcore_phaseinjector0_csrfield_cs_top) begin + main_litedramcore_csr_dfi_p0_cs_n <= 2'd2; + end else begin + if (main_litedramcore_phaseinjector0_csrfield_cs_bottom) begin + main_litedramcore_csr_dfi_p0_cs_n <= 1'd1; + end else begin + main_litedramcore_csr_dfi_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_csrfield_cs)}}; + end + end end else begin - litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; + main_litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; end end always @(*) begin - litedramcore_csr_dfi_p0_ras_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras); + main_litedramcore_csr_dfi_p0_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_csr_dfi_p0_ras_n <= (~main_litedramcore_phaseinjector0_csrfield_ras); end else begin - litedramcore_csr_dfi_p0_ras_n <= 1'd1; + main_litedramcore_csr_dfi_p0_ras_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we); + main_litedramcore_csr_dfi_p0_we_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_csr_dfi_p0_we_n <= (~main_litedramcore_phaseinjector0_csrfield_we); end else begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; + main_litedramcore_csr_dfi_p0_we_n <= 1'd1; end end -assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage; -assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage; -assign litedramcore_csr_dfi_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_wren); -assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_rden); -assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; -assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; +assign main_litedramcore_csr_dfi_p0_address = main_litedramcore_phaseinjector0_address_storage; +assign main_litedramcore_csr_dfi_p0_bank = main_litedramcore_phaseinjector0_baddress_storage; +assign main_litedramcore_csr_dfi_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_wren); +assign main_litedramcore_csr_dfi_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_rden); +assign main_litedramcore_csr_dfi_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage; +assign main_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p1_cas_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas); + main_litedramcore_csr_dfi_p1_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_csr_dfi_p1_cas_n <= (~main_litedramcore_phaseinjector1_csrfield_cas); end else begin - litedramcore_csr_dfi_p1_cas_n <= 1'd1; + main_litedramcore_csr_dfi_p1_cas_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p1_cs_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}}; + main_litedramcore_csr_dfi_p1_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + if (main_litedramcore_phaseinjector1_csrfield_cs_top) begin + main_litedramcore_csr_dfi_p1_cs_n <= 2'd2; + end else begin + if (main_litedramcore_phaseinjector1_csrfield_cs_bottom) begin + main_litedramcore_csr_dfi_p1_cs_n <= 1'd1; + end else begin + main_litedramcore_csr_dfi_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_csrfield_cs)}}; + end + end end else begin - litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; + main_litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; end end always @(*) begin - litedramcore_csr_dfi_p1_ras_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras); + main_litedramcore_csr_dfi_p1_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_csr_dfi_p1_ras_n <= (~main_litedramcore_phaseinjector1_csrfield_ras); end else begin - litedramcore_csr_dfi_p1_ras_n <= 1'd1; + main_litedramcore_csr_dfi_p1_ras_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we); + main_litedramcore_csr_dfi_p1_we_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_csr_dfi_p1_we_n <= (~main_litedramcore_phaseinjector1_csrfield_we); end else begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; + main_litedramcore_csr_dfi_p1_we_n <= 1'd1; end end -assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage; -assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage; -assign litedramcore_csr_dfi_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_wren); -assign litedramcore_csr_dfi_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_rden); -assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; -assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; +assign main_litedramcore_csr_dfi_p1_address = main_litedramcore_phaseinjector1_address_storage; +assign main_litedramcore_csr_dfi_p1_bank = main_litedramcore_phaseinjector1_baddress_storage; +assign main_litedramcore_csr_dfi_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_wren); +assign main_litedramcore_csr_dfi_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_rden); +assign main_litedramcore_csr_dfi_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage; +assign main_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p2_cas_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas); + main_litedramcore_csr_dfi_p2_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_csr_dfi_p2_cas_n <= (~main_litedramcore_phaseinjector2_csrfield_cas); end else begin - litedramcore_csr_dfi_p2_cas_n <= 1'd1; + main_litedramcore_csr_dfi_p2_cas_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p2_cs_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}}; + main_litedramcore_csr_dfi_p2_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + if (main_litedramcore_phaseinjector2_csrfield_cs_top) begin + main_litedramcore_csr_dfi_p2_cs_n <= 2'd2; + end else begin + if (main_litedramcore_phaseinjector2_csrfield_cs_bottom) begin + main_litedramcore_csr_dfi_p2_cs_n <= 1'd1; + end else begin + main_litedramcore_csr_dfi_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_csrfield_cs)}}; + end + end end else begin - litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; + main_litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; end end always @(*) begin - litedramcore_csr_dfi_p2_ras_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras); + main_litedramcore_csr_dfi_p2_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_csr_dfi_p2_ras_n <= (~main_litedramcore_phaseinjector2_csrfield_ras); end else begin - litedramcore_csr_dfi_p2_ras_n <= 1'd1; + main_litedramcore_csr_dfi_p2_ras_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p2_we_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we); + main_litedramcore_csr_dfi_p2_we_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_csr_dfi_p2_we_n <= (~main_litedramcore_phaseinjector2_csrfield_we); end else begin - litedramcore_csr_dfi_p2_we_n <= 1'd1; + main_litedramcore_csr_dfi_p2_we_n <= 1'd1; end end -assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage; -assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage; -assign litedramcore_csr_dfi_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_wren); -assign litedramcore_csr_dfi_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_rden); -assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage; -assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; +assign main_litedramcore_csr_dfi_p2_address = main_litedramcore_phaseinjector2_address_storage; +assign main_litedramcore_csr_dfi_p2_bank = main_litedramcore_phaseinjector2_baddress_storage; +assign main_litedramcore_csr_dfi_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_wren); +assign main_litedramcore_csr_dfi_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_rden); +assign main_litedramcore_csr_dfi_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage; +assign main_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p3_cas_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas); + main_litedramcore_csr_dfi_p3_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_csr_dfi_p3_cas_n <= (~main_litedramcore_phaseinjector3_csrfield_cas); end else begin - litedramcore_csr_dfi_p3_cas_n <= 1'd1; + main_litedramcore_csr_dfi_p3_cas_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p3_cs_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}}; + main_litedramcore_csr_dfi_p3_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + if (main_litedramcore_phaseinjector3_csrfield_cs_top) begin + main_litedramcore_csr_dfi_p3_cs_n <= 2'd2; + end else begin + if (main_litedramcore_phaseinjector3_csrfield_cs_bottom) begin + main_litedramcore_csr_dfi_p3_cs_n <= 1'd1; + end else begin + main_litedramcore_csr_dfi_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_csrfield_cs)}}; + end + end end else begin - litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; + main_litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; end end always @(*) begin - litedramcore_csr_dfi_p3_ras_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras); + main_litedramcore_csr_dfi_p3_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_csr_dfi_p3_ras_n <= (~main_litedramcore_phaseinjector3_csrfield_ras); end else begin - litedramcore_csr_dfi_p3_ras_n <= 1'd1; + main_litedramcore_csr_dfi_p3_ras_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p3_we_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we); + main_litedramcore_csr_dfi_p3_we_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_csr_dfi_p3_we_n <= (~main_litedramcore_phaseinjector3_csrfield_we); end else begin - litedramcore_csr_dfi_p3_we_n <= 1'd1; - end -end -assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage; -assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage; -assign litedramcore_csr_dfi_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_wren); -assign litedramcore_csr_dfi_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_rden); -assign litedramcore_csr_dfi_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage; -assign litedramcore_csr_dfi_p3_wrdata_mask = 1'd0; -assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid; -assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready; -assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we; -assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr; -assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock; -assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready; -assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid; -assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid; -assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready; -assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we; -assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr; -assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock; -assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready; -assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid; -assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid; -assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready; -assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we; -assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr; -assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock; -assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready; -assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid; -assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid; -assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready; -assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we; -assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr; -assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock; -assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready; -assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid; -assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid; -assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready; -assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we; -assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr; -assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock; -assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready; -assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid; -assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid; -assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready; -assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we; -assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr; -assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock; -assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready; -assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid; -assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid; -assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready; -assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we; -assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr; -assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock; -assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready; -assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid; -assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid; -assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready; -assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we; -assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr; -assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock; -assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready; -assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid; -assign litedramcore_timer_wait = (~litedramcore_timer_done0); -assign litedramcore_postponer_req_i = litedramcore_timer_done0; -assign litedramcore_wants_refresh = litedramcore_postponer_req_o; -assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0; -assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done); -assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0); -assign litedramcore_timer_done0 = litedramcore_timer_done1; -assign litedramcore_timer_count0 = litedramcore_timer_count1; -assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0)); -assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0)); -assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0); -assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1; -assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1; -always @(*) begin - litedramcore_refresher_next_state <= 2'd0; - litedramcore_refresher_next_state <= litedramcore_refresher_state; - case (litedramcore_refresher_state) + main_litedramcore_csr_dfi_p3_we_n <= 1'd1; + end +end +assign main_litedramcore_csr_dfi_p3_address = main_litedramcore_phaseinjector3_address_storage; +assign main_litedramcore_csr_dfi_p3_bank = main_litedramcore_phaseinjector3_baddress_storage; +assign main_litedramcore_csr_dfi_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_wren); +assign main_litedramcore_csr_dfi_p3_rddata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_rden); +assign main_litedramcore_csr_dfi_p3_wrdata = main_litedramcore_phaseinjector3_wrdata_storage; +assign main_litedramcore_csr_dfi_p3_wrdata_mask = 1'd0; +assign main_litedramcore_bankmachine0_req_valid = main_litedramcore_interface_bank0_valid; +assign main_litedramcore_interface_bank0_ready = main_litedramcore_bankmachine0_req_ready; +assign main_litedramcore_bankmachine0_req_we = main_litedramcore_interface_bank0_we; +assign main_litedramcore_bankmachine0_req_addr = main_litedramcore_interface_bank0_addr; +assign main_litedramcore_interface_bank0_lock = main_litedramcore_bankmachine0_req_lock; +assign main_litedramcore_interface_bank0_wdata_ready = main_litedramcore_bankmachine0_req_wdata_ready; +assign main_litedramcore_interface_bank0_rdata_valid = main_litedramcore_bankmachine0_req_rdata_valid; +assign main_litedramcore_bankmachine1_req_valid = main_litedramcore_interface_bank1_valid; +assign main_litedramcore_interface_bank1_ready = main_litedramcore_bankmachine1_req_ready; +assign main_litedramcore_bankmachine1_req_we = main_litedramcore_interface_bank1_we; +assign main_litedramcore_bankmachine1_req_addr = main_litedramcore_interface_bank1_addr; +assign main_litedramcore_interface_bank1_lock = main_litedramcore_bankmachine1_req_lock; +assign main_litedramcore_interface_bank1_wdata_ready = main_litedramcore_bankmachine1_req_wdata_ready; +assign main_litedramcore_interface_bank1_rdata_valid = main_litedramcore_bankmachine1_req_rdata_valid; +assign main_litedramcore_bankmachine2_req_valid = main_litedramcore_interface_bank2_valid; +assign main_litedramcore_interface_bank2_ready = main_litedramcore_bankmachine2_req_ready; +assign main_litedramcore_bankmachine2_req_we = main_litedramcore_interface_bank2_we; +assign main_litedramcore_bankmachine2_req_addr = main_litedramcore_interface_bank2_addr; +assign main_litedramcore_interface_bank2_lock = main_litedramcore_bankmachine2_req_lock; +assign main_litedramcore_interface_bank2_wdata_ready = main_litedramcore_bankmachine2_req_wdata_ready; +assign main_litedramcore_interface_bank2_rdata_valid = main_litedramcore_bankmachine2_req_rdata_valid; +assign main_litedramcore_bankmachine3_req_valid = main_litedramcore_interface_bank3_valid; +assign main_litedramcore_interface_bank3_ready = main_litedramcore_bankmachine3_req_ready; +assign main_litedramcore_bankmachine3_req_we = main_litedramcore_interface_bank3_we; +assign main_litedramcore_bankmachine3_req_addr = main_litedramcore_interface_bank3_addr; +assign main_litedramcore_interface_bank3_lock = main_litedramcore_bankmachine3_req_lock; +assign main_litedramcore_interface_bank3_wdata_ready = main_litedramcore_bankmachine3_req_wdata_ready; +assign main_litedramcore_interface_bank3_rdata_valid = main_litedramcore_bankmachine3_req_rdata_valid; +assign main_litedramcore_bankmachine4_req_valid = main_litedramcore_interface_bank4_valid; +assign main_litedramcore_interface_bank4_ready = main_litedramcore_bankmachine4_req_ready; +assign main_litedramcore_bankmachine4_req_we = main_litedramcore_interface_bank4_we; +assign main_litedramcore_bankmachine4_req_addr = main_litedramcore_interface_bank4_addr; +assign main_litedramcore_interface_bank4_lock = main_litedramcore_bankmachine4_req_lock; +assign main_litedramcore_interface_bank4_wdata_ready = main_litedramcore_bankmachine4_req_wdata_ready; +assign main_litedramcore_interface_bank4_rdata_valid = main_litedramcore_bankmachine4_req_rdata_valid; +assign main_litedramcore_bankmachine5_req_valid = main_litedramcore_interface_bank5_valid; +assign main_litedramcore_interface_bank5_ready = main_litedramcore_bankmachine5_req_ready; +assign main_litedramcore_bankmachine5_req_we = main_litedramcore_interface_bank5_we; +assign main_litedramcore_bankmachine5_req_addr = main_litedramcore_interface_bank5_addr; +assign main_litedramcore_interface_bank5_lock = main_litedramcore_bankmachine5_req_lock; +assign main_litedramcore_interface_bank5_wdata_ready = main_litedramcore_bankmachine5_req_wdata_ready; +assign main_litedramcore_interface_bank5_rdata_valid = main_litedramcore_bankmachine5_req_rdata_valid; +assign main_litedramcore_bankmachine6_req_valid = main_litedramcore_interface_bank6_valid; +assign main_litedramcore_interface_bank6_ready = main_litedramcore_bankmachine6_req_ready; +assign main_litedramcore_bankmachine6_req_we = main_litedramcore_interface_bank6_we; +assign main_litedramcore_bankmachine6_req_addr = main_litedramcore_interface_bank6_addr; +assign main_litedramcore_interface_bank6_lock = main_litedramcore_bankmachine6_req_lock; +assign main_litedramcore_interface_bank6_wdata_ready = main_litedramcore_bankmachine6_req_wdata_ready; +assign main_litedramcore_interface_bank6_rdata_valid = main_litedramcore_bankmachine6_req_rdata_valid; +assign main_litedramcore_bankmachine7_req_valid = main_litedramcore_interface_bank7_valid; +assign main_litedramcore_interface_bank7_ready = main_litedramcore_bankmachine7_req_ready; +assign main_litedramcore_bankmachine7_req_we = main_litedramcore_interface_bank7_we; +assign main_litedramcore_bankmachine7_req_addr = main_litedramcore_interface_bank7_addr; +assign main_litedramcore_interface_bank7_lock = main_litedramcore_bankmachine7_req_lock; +assign main_litedramcore_interface_bank7_wdata_ready = main_litedramcore_bankmachine7_req_wdata_ready; +assign main_litedramcore_interface_bank7_rdata_valid = main_litedramcore_bankmachine7_req_rdata_valid; +assign main_litedramcore_timer_wait = (~main_litedramcore_timer_done0); +assign main_litedramcore_postponer_req_i = main_litedramcore_timer_done0; +assign main_litedramcore_wants_refresh = main_litedramcore_postponer_req_o; +assign main_litedramcore_wants_zqcs = main_litedramcore_zqcs_timer_done0; +assign main_litedramcore_zqcs_timer_wait = (~main_litedramcore_zqcs_executer_done); +assign main_litedramcore_timer_done1 = (main_litedramcore_timer_count1 == 1'd0); +assign main_litedramcore_timer_done0 = main_litedramcore_timer_done1; +assign main_litedramcore_timer_count0 = main_litedramcore_timer_count1; +assign main_litedramcore_sequencer_start1 = (main_litedramcore_sequencer_start0 | (main_litedramcore_sequencer_count != 1'd0)); +assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & (main_litedramcore_sequencer_count == 1'd0)); +assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0); +assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1; +assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1; +always @(*) begin + builder_refresher_next_state <= 2'd0; + builder_refresher_next_state <= builder_refresher_state; + case (builder_refresher_state) 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_refresher_next_state <= 2'd2; + if (main_litedramcore_cmd_ready) begin + builder_refresher_next_state <= 2'd2; end end 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - litedramcore_refresher_next_state <= 2'd3; + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + builder_refresher_next_state <= 2'd3; end else begin - litedramcore_refresher_next_state <= 1'd0; + builder_refresher_next_state <= 1'd0; end end end 2'd3: begin - if (litedramcore_zqcs_executer_done) begin - litedramcore_refresher_next_state <= 1'd0; + if (main_litedramcore_zqcs_executer_done) begin + builder_refresher_next_state <= 1'd0; end end default: begin if (1'd1) begin - if (litedramcore_wants_refresh) begin - litedramcore_refresher_next_state <= 1'd1; + if (main_litedramcore_wants_refresh) begin + builder_refresher_next_state <= 1'd1; end end end endcase end always @(*) begin - litedramcore_cmd_valid <= 1'd0; - case (litedramcore_refresher_state) + main_litedramcore_sequencer_start0 <= 1'd0; + case (builder_refresher_state) 1'd1: begin - litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_cmd_ready) begin + main_litedramcore_sequencer_start0 <= 1'd1; + end end 2'd2: begin - litedramcore_cmd_valid <= 1'd1; - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - end else begin - litedramcore_cmd_valid <= 1'd0; - end - end end 2'd3: begin - litedramcore_cmd_valid <= 1'd1; - if (litedramcore_zqcs_executer_done) begin - litedramcore_cmd_valid <= 1'd0; - end end default: begin end endcase end always @(*) begin - litedramcore_zqcs_executer_start <= 1'd0; - case (litedramcore_refresher_state) + main_litedramcore_cmd_valid <= 1'd0; + case (builder_refresher_state) 1'd1: begin + main_litedramcore_cmd_valid <= 1'd1; end 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - litedramcore_zqcs_executer_start <= 1'd1; + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin end else begin + main_litedramcore_cmd_valid <= 1'd0; end end end 2'd3: begin + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_valid <= 1'd0; + end end default: begin end endcase end always @(*) begin - litedramcore_cmd_last <= 1'd0; - case (litedramcore_refresher_state) + main_litedramcore_zqcs_executer_start <= 1'd0; + case (builder_refresher_state) 1'd1: begin end 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + main_litedramcore_zqcs_executer_start <= 1'd1; end else begin - litedramcore_cmd_last <= 1'd1; end end end 2'd3: begin - if (litedramcore_zqcs_executer_done) begin - litedramcore_cmd_last <= 1'd1; - end end default: begin end endcase end always @(*) begin - litedramcore_sequencer_start0 <= 1'd0; - case (litedramcore_refresher_state) + main_litedramcore_cmd_last <= 1'd0; + case (builder_refresher_state) 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_sequencer_start0 <= 1'd1; - end end 2'd2: begin + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + end else begin + main_litedramcore_cmd_last <= 1'd1; + end + end end 2'd3: begin + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_last <= 1'd1; + end end default: begin end endcase end -assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid; -assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready; -assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we; -assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr; -assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid; -assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready; -assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first; -assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last; -assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we; -assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr; -assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); -assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid); -assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[22:7]); -assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0; -always @(*) begin - litedramcore_bankmachine0_cmd_payload_a <= 16'd0; - if (litedramcore_bankmachine0_row_col_n_addr_sel) begin - litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_source_source_payload_addr[22:7]; +assign main_litedramcore_bankmachine0_sink_valid = main_litedramcore_bankmachine0_req_valid; +assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_sink_ready; +assign main_litedramcore_bankmachine0_sink_payload_we = main_litedramcore_bankmachine0_req_we; +assign main_litedramcore_bankmachine0_sink_payload_addr = main_litedramcore_bankmachine0_req_addr; +assign main_litedramcore_bankmachine0_sink_sink_valid = main_litedramcore_bankmachine0_source_valid; +assign main_litedramcore_bankmachine0_source_ready = main_litedramcore_bankmachine0_sink_sink_ready; +assign main_litedramcore_bankmachine0_sink_sink_first = main_litedramcore_bankmachine0_source_first; +assign main_litedramcore_bankmachine0_sink_sink_last = main_litedramcore_bankmachine0_source_last; +assign main_litedramcore_bankmachine0_sink_sink_payload_we = main_litedramcore_bankmachine0_source_payload_we; +assign main_litedramcore_bankmachine0_sink_sink_payload_addr = main_litedramcore_bankmachine0_source_payload_addr; +assign main_litedramcore_bankmachine0_source_source_ready = (main_litedramcore_bankmachine0_req_wdata_ready | main_litedramcore_bankmachine0_req_rdata_valid); +assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_source_valid | main_litedramcore_bankmachine0_source_source_valid); +assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_source_source_payload_addr[22:7]); +assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0; +always @(*) begin + main_litedramcore_bankmachine0_cmd_payload_a <= 16'd0; + if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin + main_litedramcore_bankmachine0_cmd_payload_a <= main_litedramcore_bankmachine0_source_source_payload_addr[22:7]; end else begin - litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write); -assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); -assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); -always @(*) begin - litedramcore_bankmachine0_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin - if ((litedramcore_bankmachine0_source_payload_addr[22:7] != litedramcore_bankmachine0_source_source_payload_addr[22:7])) begin - litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we}; -assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; -assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; -assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; -assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; -assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable; -assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid; -assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first; -assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last; -assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we; -assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr; -assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable; -assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first; -assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last; -assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we; -assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr; -assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready; -always @(*) begin - litedramcore_bankmachine0_wrport_adr <= 4'd0; - if (litedramcore_bankmachine0_replace) begin - litedramcore_bankmachine0_wrport_adr <= (litedramcore_bankmachine0_produce - 1'd1); + main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write); +assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); +assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); +always @(*) begin + main_litedramcore_bankmachine0_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine0_source_valid & main_litedramcore_bankmachine0_source_source_valid)) begin + if ((main_litedramcore_bankmachine0_source_payload_addr[22:7] != main_litedramcore_bankmachine0_source_source_payload_addr[22:7])) begin + main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine0_syncfifo0_din = {main_litedramcore_bankmachine0_fifo_in_last, main_litedramcore_bankmachine0_fifo_in_first, main_litedramcore_bankmachine0_fifo_in_payload_addr, main_litedramcore_bankmachine0_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout; +assign main_litedramcore_bankmachine0_sink_ready = main_litedramcore_bankmachine0_syncfifo0_writable; +assign main_litedramcore_bankmachine0_syncfifo0_we = main_litedramcore_bankmachine0_sink_valid; +assign main_litedramcore_bankmachine0_fifo_in_first = main_litedramcore_bankmachine0_sink_first; +assign main_litedramcore_bankmachine0_fifo_in_last = main_litedramcore_bankmachine0_sink_last; +assign main_litedramcore_bankmachine0_fifo_in_payload_we = main_litedramcore_bankmachine0_sink_payload_we; +assign main_litedramcore_bankmachine0_fifo_in_payload_addr = main_litedramcore_bankmachine0_sink_payload_addr; +assign main_litedramcore_bankmachine0_source_valid = main_litedramcore_bankmachine0_syncfifo0_readable; +assign main_litedramcore_bankmachine0_source_first = main_litedramcore_bankmachine0_fifo_out_first; +assign main_litedramcore_bankmachine0_source_last = main_litedramcore_bankmachine0_fifo_out_last; +assign main_litedramcore_bankmachine0_source_payload_we = main_litedramcore_bankmachine0_fifo_out_payload_we; +assign main_litedramcore_bankmachine0_source_payload_addr = main_litedramcore_bankmachine0_fifo_out_payload_addr; +assign main_litedramcore_bankmachine0_syncfifo0_re = main_litedramcore_bankmachine0_source_ready; +always @(*) begin + main_litedramcore_bankmachine0_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine0_replace) begin + main_litedramcore_bankmachine0_wrport_adr <= (main_litedramcore_bankmachine0_produce - 1'd1); end else begin - litedramcore_bankmachine0_wrport_adr <= litedramcore_bankmachine0_produce; - end -end -assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din; -assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace)); -assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re); -assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume; -assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r; -assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 5'd16); -assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0); -assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready); -assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid; -assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready; -assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first; -assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last; -assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we; -assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr; -assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid; -assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready; -assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first; -assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last; -assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we; -assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine0_next_state <= 4'd0; - litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_wrport_adr <= main_litedramcore_bankmachine0_produce; + end +end +assign main_litedramcore_bankmachine0_wrport_dat_w = main_litedramcore_bankmachine0_syncfifo0_din; +assign main_litedramcore_bankmachine0_wrport_we = (main_litedramcore_bankmachine0_syncfifo0_we & (main_litedramcore_bankmachine0_syncfifo0_writable | main_litedramcore_bankmachine0_replace)); +assign main_litedramcore_bankmachine0_do_read = (main_litedramcore_bankmachine0_syncfifo0_readable & main_litedramcore_bankmachine0_syncfifo0_re); +assign main_litedramcore_bankmachine0_rdport_adr = main_litedramcore_bankmachine0_consume; +assign main_litedramcore_bankmachine0_syncfifo0_dout = main_litedramcore_bankmachine0_rdport_dat_r; +assign main_litedramcore_bankmachine0_syncfifo0_writable = (main_litedramcore_bankmachine0_level != 5'd16); +assign main_litedramcore_bankmachine0_syncfifo0_readable = (main_litedramcore_bankmachine0_level != 1'd0); +assign main_litedramcore_bankmachine0_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine0_pipe_valid_source_valid) | main_litedramcore_bankmachine0_pipe_valid_source_ready); +assign main_litedramcore_bankmachine0_pipe_valid_sink_valid = main_litedramcore_bankmachine0_sink_sink_valid; +assign main_litedramcore_bankmachine0_sink_sink_ready = main_litedramcore_bankmachine0_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine0_pipe_valid_sink_first = main_litedramcore_bankmachine0_sink_sink_first; +assign main_litedramcore_bankmachine0_pipe_valid_sink_last = main_litedramcore_bankmachine0_sink_sink_last; +assign main_litedramcore_bankmachine0_pipe_valid_sink_payload_we = main_litedramcore_bankmachine0_sink_sink_payload_we; +assign main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine0_sink_sink_payload_addr; +assign main_litedramcore_bankmachine0_source_source_valid = main_litedramcore_bankmachine0_pipe_valid_source_valid; +assign main_litedramcore_bankmachine0_pipe_valid_source_ready = main_litedramcore_bankmachine0_source_source_ready; +assign main_litedramcore_bankmachine0_source_source_first = main_litedramcore_bankmachine0_pipe_valid_source_first; +assign main_litedramcore_bankmachine0_source_source_last = main_litedramcore_bankmachine0_pipe_valid_source_last; +assign main_litedramcore_bankmachine0_source_source_payload_we = main_litedramcore_bankmachine0_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine0_source_source_payload_addr = main_litedramcore_bankmachine0_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine0_next_state <= 4'd0; + builder_bankmachine0_next_state <= builder_bankmachine0_state; + case (builder_bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - if (litedramcore_bankmachine0_cmd_ready) begin - litedramcore_bankmachine0_next_state <= 3'd5; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + if (main_litedramcore_bankmachine0_cmd_ready) begin + builder_bankmachine0_next_state <= 3'd5; end end end 2'd2: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_next_state <= 3'd5; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + builder_bankmachine0_next_state <= 3'd5; end end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - if (litedramcore_bankmachine0_cmd_ready) begin - litedramcore_bankmachine0_next_state <= 3'd7; + if (main_litedramcore_bankmachine0_trccon_ready) begin + if (main_litedramcore_bankmachine0_cmd_ready) begin + builder_bankmachine0_next_state <= 3'd7; end end end 3'd4: begin - if ((~litedramcore_bankmachine0_refresh_req)) begin - litedramcore_bankmachine0_next_state <= 1'd0; + if ((~main_litedramcore_bankmachine0_refresh_req)) begin + builder_bankmachine0_next_state <= 1'd0; + end + end + 3'd5: begin + builder_bankmachine0_next_state <= 3'd6; + end + 3'd6: begin + builder_bankmachine0_next_state <= 2'd3; + end + 3'd7: begin + builder_bankmachine0_next_state <= 4'd8; + end + 4'd8: begin + builder_bankmachine0_next_state <= 1'd0; + end + default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + builder_bankmachine0_next_state <= 3'd4; + end else begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if ((main_litedramcore_bankmachine0_cmd_ready & main_litedramcore_bankmachine0_auto_precharge)) begin + builder_bankmachine0_next_state <= 2'd2; + end + end else begin + builder_bankmachine0_next_state <= 1'd1; + end + end else begin + builder_bankmachine0_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; end end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end 3'd5: begin - litedramcore_bankmachine0_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine0_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine0_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine0_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - litedramcore_bankmachine0_next_state <= 3'd4; + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin - litedramcore_bankmachine0_next_state <= 2'd2; + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end else begin end end else begin - litedramcore_bankmachine0_next_state <= 1'd1; end end else begin - litedramcore_bankmachine0_next_state <= 2'd3; end end end @@ -4888,8 +5349,38 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -4907,14 +5398,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin end else begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; end end else begin end @@ -4926,8 +5417,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -4945,13 +5436,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -4964,8 +5455,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -4983,13 +5474,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin - litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin + main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready; end else begin end end else begin @@ -5002,8 +5493,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5021,14 +5512,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin end else begin - litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; + main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready; end end else begin end @@ -5040,8 +5531,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_refresh_gnt <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5049,8 +5540,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine0_twtpcon_ready) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd1; + if (main_litedramcore_bankmachine0_twtpcon_ready) begin + main_litedramcore_bankmachine0_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -5066,15 +5557,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_row_open <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_row_open <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_open <= 1'd1; + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_row_open <= 1'd1; end end 3'd4: begin @@ -5092,18 +5583,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_valid <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; end end 3'd4: begin @@ -5117,12 +5608,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; end else begin end end else begin @@ -5133,18 +5624,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_row_close <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_row_close <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - litedramcore_bankmachine0_row_close <= 1'd1; + main_litedramcore_bankmachine0_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine0_row_close <= 1'd1; + main_litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine0_row_close <= 1'd1; + main_litedramcore_bankmachine0_row_close <= 1'd1; end 3'd5: begin end @@ -5159,15 +5650,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -5185,8 +5676,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5204,12 +5695,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -5220,18 +5711,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -5248,41 +5739,139 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine0_state) +assign main_litedramcore_bankmachine1_sink_valid = main_litedramcore_bankmachine1_req_valid; +assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_sink_ready; +assign main_litedramcore_bankmachine1_sink_payload_we = main_litedramcore_bankmachine1_req_we; +assign main_litedramcore_bankmachine1_sink_payload_addr = main_litedramcore_bankmachine1_req_addr; +assign main_litedramcore_bankmachine1_sink_sink_valid = main_litedramcore_bankmachine1_source_valid; +assign main_litedramcore_bankmachine1_source_ready = main_litedramcore_bankmachine1_sink_sink_ready; +assign main_litedramcore_bankmachine1_sink_sink_first = main_litedramcore_bankmachine1_source_first; +assign main_litedramcore_bankmachine1_sink_sink_last = main_litedramcore_bankmachine1_source_last; +assign main_litedramcore_bankmachine1_sink_sink_payload_we = main_litedramcore_bankmachine1_source_payload_we; +assign main_litedramcore_bankmachine1_sink_sink_payload_addr = main_litedramcore_bankmachine1_source_payload_addr; +assign main_litedramcore_bankmachine1_source_source_ready = (main_litedramcore_bankmachine1_req_wdata_ready | main_litedramcore_bankmachine1_req_rdata_valid); +assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_source_valid | main_litedramcore_bankmachine1_source_source_valid); +assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_source_source_payload_addr[22:7]); +assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; +always @(*) begin + main_litedramcore_bankmachine1_cmd_payload_a <= 16'd0; + if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin + main_litedramcore_bankmachine1_cmd_payload_a <= main_litedramcore_bankmachine1_source_source_payload_addr[22:7]; + end else begin + main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write); +assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); +assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); +always @(*) begin + main_litedramcore_bankmachine1_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine1_source_valid & main_litedramcore_bankmachine1_source_source_valid)) begin + if ((main_litedramcore_bankmachine1_source_payload_addr[22:7] != main_litedramcore_bankmachine1_source_source_payload_addr[22:7])) begin + main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine1_syncfifo1_din = {main_litedramcore_bankmachine1_fifo_in_last, main_litedramcore_bankmachine1_fifo_in_first, main_litedramcore_bankmachine1_fifo_in_payload_addr, main_litedramcore_bankmachine1_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout; +assign main_litedramcore_bankmachine1_sink_ready = main_litedramcore_bankmachine1_syncfifo1_writable; +assign main_litedramcore_bankmachine1_syncfifo1_we = main_litedramcore_bankmachine1_sink_valid; +assign main_litedramcore_bankmachine1_fifo_in_first = main_litedramcore_bankmachine1_sink_first; +assign main_litedramcore_bankmachine1_fifo_in_last = main_litedramcore_bankmachine1_sink_last; +assign main_litedramcore_bankmachine1_fifo_in_payload_we = main_litedramcore_bankmachine1_sink_payload_we; +assign main_litedramcore_bankmachine1_fifo_in_payload_addr = main_litedramcore_bankmachine1_sink_payload_addr; +assign main_litedramcore_bankmachine1_source_valid = main_litedramcore_bankmachine1_syncfifo1_readable; +assign main_litedramcore_bankmachine1_source_first = main_litedramcore_bankmachine1_fifo_out_first; +assign main_litedramcore_bankmachine1_source_last = main_litedramcore_bankmachine1_fifo_out_last; +assign main_litedramcore_bankmachine1_source_payload_we = main_litedramcore_bankmachine1_fifo_out_payload_we; +assign main_litedramcore_bankmachine1_source_payload_addr = main_litedramcore_bankmachine1_fifo_out_payload_addr; +assign main_litedramcore_bankmachine1_syncfifo1_re = main_litedramcore_bankmachine1_source_ready; +always @(*) begin + main_litedramcore_bankmachine1_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine1_replace) begin + main_litedramcore_bankmachine1_wrport_adr <= (main_litedramcore_bankmachine1_produce - 1'd1); + end else begin + main_litedramcore_bankmachine1_wrport_adr <= main_litedramcore_bankmachine1_produce; + end +end +assign main_litedramcore_bankmachine1_wrport_dat_w = main_litedramcore_bankmachine1_syncfifo1_din; +assign main_litedramcore_bankmachine1_wrport_we = (main_litedramcore_bankmachine1_syncfifo1_we & (main_litedramcore_bankmachine1_syncfifo1_writable | main_litedramcore_bankmachine1_replace)); +assign main_litedramcore_bankmachine1_do_read = (main_litedramcore_bankmachine1_syncfifo1_readable & main_litedramcore_bankmachine1_syncfifo1_re); +assign main_litedramcore_bankmachine1_rdport_adr = main_litedramcore_bankmachine1_consume; +assign main_litedramcore_bankmachine1_syncfifo1_dout = main_litedramcore_bankmachine1_rdport_dat_r; +assign main_litedramcore_bankmachine1_syncfifo1_writable = (main_litedramcore_bankmachine1_level != 5'd16); +assign main_litedramcore_bankmachine1_syncfifo1_readable = (main_litedramcore_bankmachine1_level != 1'd0); +assign main_litedramcore_bankmachine1_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine1_pipe_valid_source_valid) | main_litedramcore_bankmachine1_pipe_valid_source_ready); +assign main_litedramcore_bankmachine1_pipe_valid_sink_valid = main_litedramcore_bankmachine1_sink_sink_valid; +assign main_litedramcore_bankmachine1_sink_sink_ready = main_litedramcore_bankmachine1_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine1_pipe_valid_sink_first = main_litedramcore_bankmachine1_sink_sink_first; +assign main_litedramcore_bankmachine1_pipe_valid_sink_last = main_litedramcore_bankmachine1_sink_sink_last; +assign main_litedramcore_bankmachine1_pipe_valid_sink_payload_we = main_litedramcore_bankmachine1_sink_sink_payload_we; +assign main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine1_sink_sink_payload_addr; +assign main_litedramcore_bankmachine1_source_source_valid = main_litedramcore_bankmachine1_pipe_valid_source_valid; +assign main_litedramcore_bankmachine1_pipe_valid_source_ready = main_litedramcore_bankmachine1_source_source_ready; +assign main_litedramcore_bankmachine1_source_source_first = main_litedramcore_bankmachine1_pipe_valid_source_first; +assign main_litedramcore_bankmachine1_source_source_last = main_litedramcore_bankmachine1_pipe_valid_source_last; +assign main_litedramcore_bankmachine1_source_source_payload_we = main_litedramcore_bankmachine1_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine1_source_source_payload_addr = main_litedramcore_bankmachine1_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine1_next_state <= 4'd0; + builder_bankmachine1_next_state <= builder_bankmachine1_state; + case (builder_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + if (main_litedramcore_bankmachine1_cmd_ready) begin + builder_bankmachine1_next_state <= 3'd5; + end end end 2'd2: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + builder_bankmachine1_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + if (main_litedramcore_bankmachine1_cmd_ready) begin + builder_bankmachine1_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine1_refresh_req)) begin + builder_bankmachine1_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine1_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine1_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine1_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine1_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin + builder_bankmachine1_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end else begin + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if ((main_litedramcore_bankmachine1_cmd_ready & main_litedramcore_bankmachine1_auto_precharge)) begin + builder_bankmachine1_next_state <= 2'd2; end end else begin + builder_bankmachine1_next_state <= 1'd1; end end else begin + builder_bankmachine1_next_state <= 2'd3; end end end @@ -5290,22 +5879,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5316,142 +5898,56 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin + main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end -assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid; -assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready; -assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we; -assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr; -assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid; -assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready; -assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first; -assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last; -assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we; -assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr; -assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); -assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid); -assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[22:7]); -assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1; -always @(*) begin - litedramcore_bankmachine1_cmd_payload_a <= 16'd0; - if (litedramcore_bankmachine1_row_col_n_addr_sel) begin - litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_source_source_payload_addr[22:7]; - end else begin - litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write); -assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); -assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); -always @(*) begin - litedramcore_bankmachine1_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin - if ((litedramcore_bankmachine1_source_payload_addr[22:7] != litedramcore_bankmachine1_source_source_payload_addr[22:7])) begin - litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we}; -assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; -assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; -assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; -assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; -assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable; -assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid; -assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first; -assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last; -assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we; -assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr; -assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable; -assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first; -assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last; -assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we; -assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr; -assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready; -always @(*) begin - litedramcore_bankmachine1_wrport_adr <= 4'd0; - if (litedramcore_bankmachine1_replace) begin - litedramcore_bankmachine1_wrport_adr <= (litedramcore_bankmachine1_produce - 1'd1); - end else begin - litedramcore_bankmachine1_wrport_adr <= litedramcore_bankmachine1_produce; - end -end -assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din; -assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace)); -assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re); -assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume; -assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r; -assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 5'd16); -assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0); -assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready); -assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid; -assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready; -assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first; -assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last; -assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we; -assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr; -assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid; -assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready; -assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first; -assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last; -assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we; -assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine1_next_state <= 4'd0; - litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state; - case (litedramcore_bankmachine1_state) +always @(*) begin + main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - if (litedramcore_bankmachine1_cmd_ready) begin - litedramcore_bankmachine1_next_state <= 3'd5; - end - end end 2'd2: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - if (litedramcore_bankmachine1_cmd_ready) begin - litedramcore_bankmachine1_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~litedramcore_bankmachine1_refresh_req)) begin - litedramcore_bankmachine1_next_state <= 1'd0; - end end 3'd5: begin - litedramcore_bankmachine1_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine1_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine1_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine1_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - litedramcore_bankmachine1_next_state <= 3'd4; + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin - litedramcore_bankmachine1_next_state <= 2'd2; + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready; end end else begin - litedramcore_bankmachine1_next_state <= 1'd1; end end else begin - litedramcore_bankmachine1_next_state <= 2'd3; end end end @@ -5459,8 +5955,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -5468,8 +5964,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine1_twtpcon_ready) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd1; + if (main_litedramcore_bankmachine1_twtpcon_ready) begin + main_litedramcore_bankmachine1_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -5485,15 +5981,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_row_open <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_row_open <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_open <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_row_open <= 1'd1; end end 3'd4: begin @@ -5511,18 +6007,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_valid <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; end end 3'd4: begin @@ -5536,12 +6032,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; end else begin end end else begin @@ -5552,18 +6048,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_row_close <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_row_close <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - litedramcore_bankmachine1_row_close <= 1'd1; + main_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine1_row_close <= 1'd1; + main_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine1_row_close <= 1'd1; + main_litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -5578,15 +6074,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -5604,8 +6100,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -5623,12 +6119,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -5639,18 +6135,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -5668,11 +6164,11 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -5690,13 +6186,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -5709,22 +6205,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5739,8 +6235,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -5758,14 +6254,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin end else begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; end end else begin end @@ -5777,8 +6273,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -5796,13 +6292,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin + main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -5814,38 +6310,139 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine1_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine1_state) +assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid; +assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready; +assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we; +assign main_litedramcore_bankmachine2_sink_payload_addr = main_litedramcore_bankmachine2_req_addr; +assign main_litedramcore_bankmachine2_sink_sink_valid = main_litedramcore_bankmachine2_source_valid; +assign main_litedramcore_bankmachine2_source_ready = main_litedramcore_bankmachine2_sink_sink_ready; +assign main_litedramcore_bankmachine2_sink_sink_first = main_litedramcore_bankmachine2_source_first; +assign main_litedramcore_bankmachine2_sink_sink_last = main_litedramcore_bankmachine2_source_last; +assign main_litedramcore_bankmachine2_sink_sink_payload_we = main_litedramcore_bankmachine2_source_payload_we; +assign main_litedramcore_bankmachine2_sink_sink_payload_addr = main_litedramcore_bankmachine2_source_payload_addr; +assign main_litedramcore_bankmachine2_source_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid); +assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_source_valid | main_litedramcore_bankmachine2_source_source_valid); +assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_source_source_payload_addr[22:7]); +assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; +always @(*) begin + main_litedramcore_bankmachine2_cmd_payload_a <= 16'd0; + if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin + main_litedramcore_bankmachine2_cmd_payload_a <= main_litedramcore_bankmachine2_source_source_payload_addr[22:7]; + end else begin + main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write); +assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); +assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); +always @(*) begin + main_litedramcore_bankmachine2_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine2_source_valid & main_litedramcore_bankmachine2_source_source_valid)) begin + if ((main_litedramcore_bankmachine2_source_payload_addr[22:7] != main_litedramcore_bankmachine2_source_source_payload_addr[22:7])) begin + main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine2_syncfifo2_din = {main_litedramcore_bankmachine2_fifo_in_last, main_litedramcore_bankmachine2_fifo_in_first, main_litedramcore_bankmachine2_fifo_in_payload_addr, main_litedramcore_bankmachine2_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; +assign main_litedramcore_bankmachine2_sink_ready = main_litedramcore_bankmachine2_syncfifo2_writable; +assign main_litedramcore_bankmachine2_syncfifo2_we = main_litedramcore_bankmachine2_sink_valid; +assign main_litedramcore_bankmachine2_fifo_in_first = main_litedramcore_bankmachine2_sink_first; +assign main_litedramcore_bankmachine2_fifo_in_last = main_litedramcore_bankmachine2_sink_last; +assign main_litedramcore_bankmachine2_fifo_in_payload_we = main_litedramcore_bankmachine2_sink_payload_we; +assign main_litedramcore_bankmachine2_fifo_in_payload_addr = main_litedramcore_bankmachine2_sink_payload_addr; +assign main_litedramcore_bankmachine2_source_valid = main_litedramcore_bankmachine2_syncfifo2_readable; +assign main_litedramcore_bankmachine2_source_first = main_litedramcore_bankmachine2_fifo_out_first; +assign main_litedramcore_bankmachine2_source_last = main_litedramcore_bankmachine2_fifo_out_last; +assign main_litedramcore_bankmachine2_source_payload_we = main_litedramcore_bankmachine2_fifo_out_payload_we; +assign main_litedramcore_bankmachine2_source_payload_addr = main_litedramcore_bankmachine2_fifo_out_payload_addr; +assign main_litedramcore_bankmachine2_syncfifo2_re = main_litedramcore_bankmachine2_source_ready; +always @(*) begin + main_litedramcore_bankmachine2_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine2_replace) begin + main_litedramcore_bankmachine2_wrport_adr <= (main_litedramcore_bankmachine2_produce - 1'd1); + end else begin + main_litedramcore_bankmachine2_wrport_adr <= main_litedramcore_bankmachine2_produce; + end +end +assign main_litedramcore_bankmachine2_wrport_dat_w = main_litedramcore_bankmachine2_syncfifo2_din; +assign main_litedramcore_bankmachine2_wrport_we = (main_litedramcore_bankmachine2_syncfifo2_we & (main_litedramcore_bankmachine2_syncfifo2_writable | main_litedramcore_bankmachine2_replace)); +assign main_litedramcore_bankmachine2_do_read = (main_litedramcore_bankmachine2_syncfifo2_readable & main_litedramcore_bankmachine2_syncfifo2_re); +assign main_litedramcore_bankmachine2_rdport_adr = main_litedramcore_bankmachine2_consume; +assign main_litedramcore_bankmachine2_syncfifo2_dout = main_litedramcore_bankmachine2_rdport_dat_r; +assign main_litedramcore_bankmachine2_syncfifo2_writable = (main_litedramcore_bankmachine2_level != 5'd16); +assign main_litedramcore_bankmachine2_syncfifo2_readable = (main_litedramcore_bankmachine2_level != 1'd0); +assign main_litedramcore_bankmachine2_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine2_pipe_valid_source_valid) | main_litedramcore_bankmachine2_pipe_valid_source_ready); +assign main_litedramcore_bankmachine2_pipe_valid_sink_valid = main_litedramcore_bankmachine2_sink_sink_valid; +assign main_litedramcore_bankmachine2_sink_sink_ready = main_litedramcore_bankmachine2_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine2_pipe_valid_sink_first = main_litedramcore_bankmachine2_sink_sink_first; +assign main_litedramcore_bankmachine2_pipe_valid_sink_last = main_litedramcore_bankmachine2_sink_sink_last; +assign main_litedramcore_bankmachine2_pipe_valid_sink_payload_we = main_litedramcore_bankmachine2_sink_sink_payload_we; +assign main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine2_sink_sink_payload_addr; +assign main_litedramcore_bankmachine2_source_source_valid = main_litedramcore_bankmachine2_pipe_valid_source_valid; +assign main_litedramcore_bankmachine2_pipe_valid_source_ready = main_litedramcore_bankmachine2_source_source_ready; +assign main_litedramcore_bankmachine2_source_source_first = main_litedramcore_bankmachine2_pipe_valid_source_first; +assign main_litedramcore_bankmachine2_source_source_last = main_litedramcore_bankmachine2_pipe_valid_source_last; +assign main_litedramcore_bankmachine2_source_source_payload_we = main_litedramcore_bankmachine2_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine2_source_source_payload_addr = main_litedramcore_bankmachine2_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine2_next_state <= 4'd0; + builder_bankmachine2_next_state <= builder_bankmachine2_state; + case (builder_bankmachine2_state) 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + if (main_litedramcore_bankmachine2_cmd_ready) begin + builder_bankmachine2_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + builder_bankmachine2_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + if (main_litedramcore_bankmachine2_cmd_ready) begin + builder_bankmachine2_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine2_refresh_req)) begin + builder_bankmachine2_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine2_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine2_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine2_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine2_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin + builder_bankmachine2_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; - end else begin + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if ((main_litedramcore_bankmachine2_cmd_ready & main_litedramcore_bankmachine2_auto_precharge)) begin + builder_bankmachine2_next_state <= 2'd2; end end else begin + builder_bankmachine2_next_state <= 1'd1; end end else begin + builder_bankmachine2_next_state <= 2'd3; end end end @@ -5853,13 +6450,16 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine2_row_open <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_row_open <= 1'd1; + end end 3'd4: begin end @@ -5872,157 +6472,44 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - end else begin - litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end -assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid; -assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready; -assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we; -assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr; -assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid; -assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready; -assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first; -assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last; -assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we; -assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr; -assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); -assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid); -assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[22:7]); -assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2; -always @(*) begin - litedramcore_bankmachine2_cmd_payload_a <= 16'd0; - if (litedramcore_bankmachine2_row_col_n_addr_sel) begin - litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_source_source_payload_addr[22:7]; - end else begin - litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write); -assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); -assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); -always @(*) begin - litedramcore_bankmachine2_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin - if ((litedramcore_bankmachine2_source_payload_addr[22:7] != litedramcore_bankmachine2_source_source_payload_addr[22:7])) begin - litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we}; -assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; -assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; -assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; -assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; -assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable; -assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid; -assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first; -assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last; -assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we; -assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr; -assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable; -assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first; -assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last; -assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we; -assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr; -assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready; -always @(*) begin - litedramcore_bankmachine2_wrport_adr <= 4'd0; - if (litedramcore_bankmachine2_replace) begin - litedramcore_bankmachine2_wrport_adr <= (litedramcore_bankmachine2_produce - 1'd1); - end else begin - litedramcore_bankmachine2_wrport_adr <= litedramcore_bankmachine2_produce; - end -end -assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din; -assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace)); -assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re); -assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume; -assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r; -assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 5'd16); -assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0); -assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready); -assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid; -assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready; -assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first; -assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last; -assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we; -assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr; -assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid; -assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready; -assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first; -assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last; -assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we; -assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine2_next_state <= 4'd0; - litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state; - case (litedramcore_bankmachine2_state) +always @(*) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - if (litedramcore_bankmachine2_cmd_ready) begin - litedramcore_bankmachine2_next_state <= 3'd5; - end + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; end end 2'd2: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - if (litedramcore_bankmachine2_cmd_ready) begin - litedramcore_bankmachine2_next_state <= 3'd7; - end + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; end end 3'd4: begin - if ((~litedramcore_bankmachine2_refresh_req)) begin - litedramcore_bankmachine2_next_state <= 1'd0; - end end 3'd5: begin - litedramcore_bankmachine2_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine2_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine2_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine2_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - litedramcore_bankmachine2_next_state <= 3'd4; + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin - litedramcore_bankmachine2_next_state <= 2'd2; - end + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; end else begin - litedramcore_bankmachine2_next_state <= 1'd1; end end else begin - litedramcore_bankmachine2_next_state <= 2'd3; end end end @@ -6030,15 +6517,41 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_row_close <= 1'd0; + case (builder_bankmachine2_state) + 1'd1: begin + main_litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd2: begin + main_litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + main_litedramcore_bankmachine2_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -6056,8 +6569,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6075,12 +6588,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -6091,18 +6604,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -6120,11 +6633,11 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -6142,13 +6655,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -6161,22 +6674,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6191,8 +6704,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6210,14 +6723,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin end else begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6229,8 +6742,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6248,13 +6761,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin + main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -6267,8 +6780,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6286,13 +6799,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin - litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin + main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready; end else begin end end else begin @@ -6305,8 +6818,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6324,14 +6837,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin end else begin - litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; + main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready; end end else begin end @@ -6343,8 +6856,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6352,8 +6865,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine2_twtpcon_ready) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd1; + if (main_litedramcore_bankmachine2_twtpcon_ready) begin + main_litedramcore_bankmachine2_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -6368,67 +6881,139 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine2_row_open <= 1'd0; - case (litedramcore_bankmachine2_state) +assign main_litedramcore_bankmachine3_sink_valid = main_litedramcore_bankmachine3_req_valid; +assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_sink_ready; +assign main_litedramcore_bankmachine3_sink_payload_we = main_litedramcore_bankmachine3_req_we; +assign main_litedramcore_bankmachine3_sink_payload_addr = main_litedramcore_bankmachine3_req_addr; +assign main_litedramcore_bankmachine3_sink_sink_valid = main_litedramcore_bankmachine3_source_valid; +assign main_litedramcore_bankmachine3_source_ready = main_litedramcore_bankmachine3_sink_sink_ready; +assign main_litedramcore_bankmachine3_sink_sink_first = main_litedramcore_bankmachine3_source_first; +assign main_litedramcore_bankmachine3_sink_sink_last = main_litedramcore_bankmachine3_source_last; +assign main_litedramcore_bankmachine3_sink_sink_payload_we = main_litedramcore_bankmachine3_source_payload_we; +assign main_litedramcore_bankmachine3_sink_sink_payload_addr = main_litedramcore_bankmachine3_source_payload_addr; +assign main_litedramcore_bankmachine3_source_source_ready = (main_litedramcore_bankmachine3_req_wdata_ready | main_litedramcore_bankmachine3_req_rdata_valid); +assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_source_valid | main_litedramcore_bankmachine3_source_source_valid); +assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_source_source_payload_addr[22:7]); +assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; +always @(*) begin + main_litedramcore_bankmachine3_cmd_payload_a <= 16'd0; + if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin + main_litedramcore_bankmachine3_cmd_payload_a <= main_litedramcore_bankmachine3_source_source_payload_addr[22:7]; + end else begin + main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write); +assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); +assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); +always @(*) begin + main_litedramcore_bankmachine3_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine3_source_valid & main_litedramcore_bankmachine3_source_source_valid)) begin + if ((main_litedramcore_bankmachine3_source_payload_addr[22:7] != main_litedramcore_bankmachine3_source_source_payload_addr[22:7])) begin + main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine3_syncfifo3_din = {main_litedramcore_bankmachine3_fifo_in_last, main_litedramcore_bankmachine3_fifo_in_first, main_litedramcore_bankmachine3_fifo_in_payload_addr, main_litedramcore_bankmachine3_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout; +assign main_litedramcore_bankmachine3_sink_ready = main_litedramcore_bankmachine3_syncfifo3_writable; +assign main_litedramcore_bankmachine3_syncfifo3_we = main_litedramcore_bankmachine3_sink_valid; +assign main_litedramcore_bankmachine3_fifo_in_first = main_litedramcore_bankmachine3_sink_first; +assign main_litedramcore_bankmachine3_fifo_in_last = main_litedramcore_bankmachine3_sink_last; +assign main_litedramcore_bankmachine3_fifo_in_payload_we = main_litedramcore_bankmachine3_sink_payload_we; +assign main_litedramcore_bankmachine3_fifo_in_payload_addr = main_litedramcore_bankmachine3_sink_payload_addr; +assign main_litedramcore_bankmachine3_source_valid = main_litedramcore_bankmachine3_syncfifo3_readable; +assign main_litedramcore_bankmachine3_source_first = main_litedramcore_bankmachine3_fifo_out_first; +assign main_litedramcore_bankmachine3_source_last = main_litedramcore_bankmachine3_fifo_out_last; +assign main_litedramcore_bankmachine3_source_payload_we = main_litedramcore_bankmachine3_fifo_out_payload_we; +assign main_litedramcore_bankmachine3_source_payload_addr = main_litedramcore_bankmachine3_fifo_out_payload_addr; +assign main_litedramcore_bankmachine3_syncfifo3_re = main_litedramcore_bankmachine3_source_ready; +always @(*) begin + main_litedramcore_bankmachine3_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine3_replace) begin + main_litedramcore_bankmachine3_wrport_adr <= (main_litedramcore_bankmachine3_produce - 1'd1); + end else begin + main_litedramcore_bankmachine3_wrport_adr <= main_litedramcore_bankmachine3_produce; + end +end +assign main_litedramcore_bankmachine3_wrport_dat_w = main_litedramcore_bankmachine3_syncfifo3_din; +assign main_litedramcore_bankmachine3_wrport_we = (main_litedramcore_bankmachine3_syncfifo3_we & (main_litedramcore_bankmachine3_syncfifo3_writable | main_litedramcore_bankmachine3_replace)); +assign main_litedramcore_bankmachine3_do_read = (main_litedramcore_bankmachine3_syncfifo3_readable & main_litedramcore_bankmachine3_syncfifo3_re); +assign main_litedramcore_bankmachine3_rdport_adr = main_litedramcore_bankmachine3_consume; +assign main_litedramcore_bankmachine3_syncfifo3_dout = main_litedramcore_bankmachine3_rdport_dat_r; +assign main_litedramcore_bankmachine3_syncfifo3_writable = (main_litedramcore_bankmachine3_level != 5'd16); +assign main_litedramcore_bankmachine3_syncfifo3_readable = (main_litedramcore_bankmachine3_level != 1'd0); +assign main_litedramcore_bankmachine3_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine3_pipe_valid_source_valid) | main_litedramcore_bankmachine3_pipe_valid_source_ready); +assign main_litedramcore_bankmachine3_pipe_valid_sink_valid = main_litedramcore_bankmachine3_sink_sink_valid; +assign main_litedramcore_bankmachine3_sink_sink_ready = main_litedramcore_bankmachine3_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine3_pipe_valid_sink_first = main_litedramcore_bankmachine3_sink_sink_first; +assign main_litedramcore_bankmachine3_pipe_valid_sink_last = main_litedramcore_bankmachine3_sink_sink_last; +assign main_litedramcore_bankmachine3_pipe_valid_sink_payload_we = main_litedramcore_bankmachine3_sink_sink_payload_we; +assign main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine3_sink_sink_payload_addr; +assign main_litedramcore_bankmachine3_source_source_valid = main_litedramcore_bankmachine3_pipe_valid_source_valid; +assign main_litedramcore_bankmachine3_pipe_valid_source_ready = main_litedramcore_bankmachine3_source_source_ready; +assign main_litedramcore_bankmachine3_source_source_first = main_litedramcore_bankmachine3_pipe_valid_source_first; +assign main_litedramcore_bankmachine3_source_source_last = main_litedramcore_bankmachine3_pipe_valid_source_last; +assign main_litedramcore_bankmachine3_source_source_payload_we = main_litedramcore_bankmachine3_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine3_source_source_payload_addr = main_litedramcore_bankmachine3_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine3_next_state <= 4'd0; + builder_bankmachine3_next_state <= builder_bankmachine3_state; + case (builder_bankmachine3_state) 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + if (main_litedramcore_bankmachine3_cmd_ready) begin + builder_bankmachine3_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + builder_bankmachine3_next_state <= 3'd5; + end end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + if (main_litedramcore_bankmachine3_cmd_ready) begin + builder_bankmachine3_next_state <= 3'd7; + end end end 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_valid <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; + if ((~main_litedramcore_bankmachine3_refresh_req)) begin + builder_bankmachine3_next_state <= 1'd0; end end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end 3'd5: begin + builder_bankmachine3_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine3_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine3_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine3_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin + builder_bankmachine3_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin + builder_bankmachine3_next_state <= 2'd2; + end end else begin + builder_bankmachine3_next_state <= 1'd1; end end else begin + builder_bankmachine3_next_state <= 2'd3; end end end @@ -6436,173 +7021,34 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_row_close <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid; -assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready; -assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we; -assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr; -assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid; -assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready; -assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first; -assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last; -assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we; -assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr; -assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); -assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid); -assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[22:7]); -assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3; -always @(*) begin - litedramcore_bankmachine3_cmd_payload_a <= 16'd0; - if (litedramcore_bankmachine3_row_col_n_addr_sel) begin - litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_source_source_payload_addr[22:7]; - end else begin - litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write); -assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); -assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); -always @(*) begin - litedramcore_bankmachine3_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin - if ((litedramcore_bankmachine3_source_payload_addr[22:7] != litedramcore_bankmachine3_source_source_payload_addr[22:7])) begin - litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we}; -assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; -assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; -assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; -assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; -assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable; -assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid; -assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first; -assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last; -assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we; -assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr; -assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable; -assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first; -assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last; -assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we; -assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr; -assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready; -always @(*) begin - litedramcore_bankmachine3_wrport_adr <= 4'd0; - if (litedramcore_bankmachine3_replace) begin - litedramcore_bankmachine3_wrport_adr <= (litedramcore_bankmachine3_produce - 1'd1); - end else begin - litedramcore_bankmachine3_wrport_adr <= litedramcore_bankmachine3_produce; - end -end -assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din; -assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace)); -assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re); -assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume; -assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r; -assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 5'd16); -assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0); -assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready); -assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid; -assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready; -assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first; -assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last; -assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we; -assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr; -assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid; -assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready; -assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first; -assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last; -assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we; -assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine3_next_state <= 4'd0; - litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - if (litedramcore_bankmachine3_cmd_ready) begin - litedramcore_bankmachine3_next_state <= 3'd5; - end - end end 2'd2: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - if (litedramcore_bankmachine3_cmd_ready) begin - litedramcore_bankmachine3_next_state <= 3'd7; - end + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin - if ((~litedramcore_bankmachine3_refresh_req)) begin - litedramcore_bankmachine3_next_state <= 1'd0; - end end 3'd5: begin - litedramcore_bankmachine3_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine3_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine3_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine3_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - litedramcore_bankmachine3_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin - litedramcore_bankmachine3_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine3_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine3_next_state <= 2'd3; - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -6620,12 +7066,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -6636,18 +7082,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -6665,11 +7111,11 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -6687,13 +7133,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -6706,22 +7152,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6736,8 +7182,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -6755,14 +7201,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin end else begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6774,8 +7220,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -6793,13 +7239,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin + main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -6812,8 +7258,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -6831,13 +7277,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin - litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin + main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready; end else begin end end else begin @@ -6850,8 +7296,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -6869,14 +7315,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin end else begin - litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; + main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready; end end else begin end @@ -6888,8 +7334,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -6897,8 +7343,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine3_twtpcon_ready) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd1; + if (main_litedramcore_bankmachine3_twtpcon_ready) begin + main_litedramcore_bankmachine3_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -6914,15 +7360,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_row_open <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_row_open <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_open <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_open <= 1'd1; end end 3'd4: begin @@ -6940,18 +7386,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_valid <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; end end 3'd4: begin @@ -6965,12 +7411,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; end else begin end end else begin @@ -6981,18 +7427,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_row_close <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_row_close <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - litedramcore_bankmachine3_row_close <= 1'd1; + main_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine3_row_close <= 1'd1; + main_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine3_row_close <= 1'd1; + main_litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -7006,165 +7452,180 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine3_state) +assign main_litedramcore_bankmachine4_sink_valid = main_litedramcore_bankmachine4_req_valid; +assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_sink_ready; +assign main_litedramcore_bankmachine4_sink_payload_we = main_litedramcore_bankmachine4_req_we; +assign main_litedramcore_bankmachine4_sink_payload_addr = main_litedramcore_bankmachine4_req_addr; +assign main_litedramcore_bankmachine4_sink_sink_valid = main_litedramcore_bankmachine4_source_valid; +assign main_litedramcore_bankmachine4_source_ready = main_litedramcore_bankmachine4_sink_sink_ready; +assign main_litedramcore_bankmachine4_sink_sink_first = main_litedramcore_bankmachine4_source_first; +assign main_litedramcore_bankmachine4_sink_sink_last = main_litedramcore_bankmachine4_source_last; +assign main_litedramcore_bankmachine4_sink_sink_payload_we = main_litedramcore_bankmachine4_source_payload_we; +assign main_litedramcore_bankmachine4_sink_sink_payload_addr = main_litedramcore_bankmachine4_source_payload_addr; +assign main_litedramcore_bankmachine4_source_source_ready = (main_litedramcore_bankmachine4_req_wdata_ready | main_litedramcore_bankmachine4_req_rdata_valid); +assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_source_valid | main_litedramcore_bankmachine4_source_source_valid); +assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_source_source_payload_addr[22:7]); +assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; +always @(*) begin + main_litedramcore_bankmachine4_cmd_payload_a <= 16'd0; + if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin + main_litedramcore_bankmachine4_cmd_payload_a <= main_litedramcore_bankmachine4_source_source_payload_addr[22:7]; + end else begin + main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write); +assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); +assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); +always @(*) begin + main_litedramcore_bankmachine4_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine4_source_valid & main_litedramcore_bankmachine4_source_source_valid)) begin + if ((main_litedramcore_bankmachine4_source_payload_addr[22:7] != main_litedramcore_bankmachine4_source_source_payload_addr[22:7])) begin + main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine4_syncfifo4_din = {main_litedramcore_bankmachine4_fifo_in_last, main_litedramcore_bankmachine4_fifo_in_first, main_litedramcore_bankmachine4_fifo_in_payload_addr, main_litedramcore_bankmachine4_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout; +assign main_litedramcore_bankmachine4_sink_ready = main_litedramcore_bankmachine4_syncfifo4_writable; +assign main_litedramcore_bankmachine4_syncfifo4_we = main_litedramcore_bankmachine4_sink_valid; +assign main_litedramcore_bankmachine4_fifo_in_first = main_litedramcore_bankmachine4_sink_first; +assign main_litedramcore_bankmachine4_fifo_in_last = main_litedramcore_bankmachine4_sink_last; +assign main_litedramcore_bankmachine4_fifo_in_payload_we = main_litedramcore_bankmachine4_sink_payload_we; +assign main_litedramcore_bankmachine4_fifo_in_payload_addr = main_litedramcore_bankmachine4_sink_payload_addr; +assign main_litedramcore_bankmachine4_source_valid = main_litedramcore_bankmachine4_syncfifo4_readable; +assign main_litedramcore_bankmachine4_source_first = main_litedramcore_bankmachine4_fifo_out_first; +assign main_litedramcore_bankmachine4_source_last = main_litedramcore_bankmachine4_fifo_out_last; +assign main_litedramcore_bankmachine4_source_payload_we = main_litedramcore_bankmachine4_fifo_out_payload_we; +assign main_litedramcore_bankmachine4_source_payload_addr = main_litedramcore_bankmachine4_fifo_out_payload_addr; +assign main_litedramcore_bankmachine4_syncfifo4_re = main_litedramcore_bankmachine4_source_ready; +always @(*) begin + main_litedramcore_bankmachine4_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine4_replace) begin + main_litedramcore_bankmachine4_wrport_adr <= (main_litedramcore_bankmachine4_produce - 1'd1); + end else begin + main_litedramcore_bankmachine4_wrport_adr <= main_litedramcore_bankmachine4_produce; + end +end +assign main_litedramcore_bankmachine4_wrport_dat_w = main_litedramcore_bankmachine4_syncfifo4_din; +assign main_litedramcore_bankmachine4_wrport_we = (main_litedramcore_bankmachine4_syncfifo4_we & (main_litedramcore_bankmachine4_syncfifo4_writable | main_litedramcore_bankmachine4_replace)); +assign main_litedramcore_bankmachine4_do_read = (main_litedramcore_bankmachine4_syncfifo4_readable & main_litedramcore_bankmachine4_syncfifo4_re); +assign main_litedramcore_bankmachine4_rdport_adr = main_litedramcore_bankmachine4_consume; +assign main_litedramcore_bankmachine4_syncfifo4_dout = main_litedramcore_bankmachine4_rdport_dat_r; +assign main_litedramcore_bankmachine4_syncfifo4_writable = (main_litedramcore_bankmachine4_level != 5'd16); +assign main_litedramcore_bankmachine4_syncfifo4_readable = (main_litedramcore_bankmachine4_level != 1'd0); +assign main_litedramcore_bankmachine4_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine4_pipe_valid_source_valid) | main_litedramcore_bankmachine4_pipe_valid_source_ready); +assign main_litedramcore_bankmachine4_pipe_valid_sink_valid = main_litedramcore_bankmachine4_sink_sink_valid; +assign main_litedramcore_bankmachine4_sink_sink_ready = main_litedramcore_bankmachine4_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine4_pipe_valid_sink_first = main_litedramcore_bankmachine4_sink_sink_first; +assign main_litedramcore_bankmachine4_pipe_valid_sink_last = main_litedramcore_bankmachine4_sink_sink_last; +assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_we = main_litedramcore_bankmachine4_sink_sink_payload_we; +assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine4_sink_sink_payload_addr; +assign main_litedramcore_bankmachine4_source_source_valid = main_litedramcore_bankmachine4_pipe_valid_source_valid; +assign main_litedramcore_bankmachine4_pipe_valid_source_ready = main_litedramcore_bankmachine4_source_source_ready; +assign main_litedramcore_bankmachine4_source_source_first = main_litedramcore_bankmachine4_pipe_valid_source_first; +assign main_litedramcore_bankmachine4_source_source_last = main_litedramcore_bankmachine4_pipe_valid_source_last; +assign main_litedramcore_bankmachine4_source_source_payload_we = main_litedramcore_bankmachine4_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine4_source_source_payload_addr = main_litedramcore_bankmachine4_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine4_next_state <= 4'd0; + builder_bankmachine4_next_state <= builder_bankmachine4_state; + case (builder_bankmachine4_state) 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + if (main_litedramcore_bankmachine4_cmd_ready) begin + builder_bankmachine4_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + builder_bankmachine4_next_state <= 3'd5; + end end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + if (main_litedramcore_bankmachine4_cmd_ready) begin + builder_bankmachine4_next_state <= 3'd7; + end end end 3'd4: begin + if ((~main_litedramcore_bankmachine4_refresh_req)) begin + builder_bankmachine4_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine4_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine4_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine4_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine4_next_state <= 1'd0; end default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + builder_bankmachine4_next_state <= 3'd4; + end else begin + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if ((main_litedramcore_bankmachine4_cmd_ready & main_litedramcore_bankmachine4_auto_precharge)) begin + builder_bankmachine4_next_state <= 2'd2; + end + end else begin + builder_bankmachine4_next_state <= 1'd1; + end + end else begin + builder_bankmachine4_next_state <= 2'd3; + end + end + end end endcase end -assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid; -assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready; -assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we; -assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr; -assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid; -assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready; -assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first; -assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last; -assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we; -assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr; -assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); -assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid); -assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[22:7]); -assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4; -always @(*) begin - litedramcore_bankmachine4_cmd_payload_a <= 16'd0; - if (litedramcore_bankmachine4_row_col_n_addr_sel) begin - litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_source_source_payload_addr[22:7]; - end else begin - litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write); -assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); -assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); -always @(*) begin - litedramcore_bankmachine4_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin - if ((litedramcore_bankmachine4_source_payload_addr[22:7] != litedramcore_bankmachine4_source_source_payload_addr[22:7])) begin - litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we}; -assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; -assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; -assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; -assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; -assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable; -assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid; -assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first; -assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last; -assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we; -assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr; -assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable; -assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first; -assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last; -assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we; -assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr; -assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready; -always @(*) begin - litedramcore_bankmachine4_wrport_adr <= 4'd0; - if (litedramcore_bankmachine4_replace) begin - litedramcore_bankmachine4_wrport_adr <= (litedramcore_bankmachine4_produce - 1'd1); - end else begin - litedramcore_bankmachine4_wrport_adr <= litedramcore_bankmachine4_produce; - end -end -assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din; -assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace)); -assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re); -assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume; -assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r; -assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 5'd16); -assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0); -assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready); -assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid; -assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready; -assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first; -assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last; -assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we; -assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr; -assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid; -assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready; -assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first; -assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last; -assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we; -assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine4_next_state <= 4'd0; - litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state; - case (litedramcore_bankmachine4_state) +always @(*) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - if (litedramcore_bankmachine4_cmd_ready) begin - litedramcore_bankmachine4_next_state <= 3'd5; - end + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end end 2'd2: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - if (litedramcore_bankmachine4_cmd_ready) begin - litedramcore_bankmachine4_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~litedramcore_bankmachine4_refresh_req)) begin - litedramcore_bankmachine4_next_state <= 1'd0; - end end 3'd5: begin - litedramcore_bankmachine4_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine4_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine4_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine4_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - litedramcore_bankmachine4_next_state <= 3'd4; + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin - litedramcore_bankmachine4_next_state <= 2'd2; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin end end else begin - litedramcore_bankmachine4_next_state <= 1'd1; end end else begin - litedramcore_bankmachine4_next_state <= 2'd3; end end end @@ -7172,8 +7633,38 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine4_state) + 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7191,14 +7682,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin end else begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; end end else begin end @@ -7210,8 +7701,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7229,13 +7720,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin + main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -7248,8 +7739,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7267,13 +7758,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin - litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin + main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready; end else begin end end else begin @@ -7286,8 +7777,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7305,14 +7796,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin end else begin - litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; + main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready; end end else begin end @@ -7324,8 +7815,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7333,8 +7824,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine4_twtpcon_ready) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd1; + if (main_litedramcore_bankmachine4_twtpcon_ready) begin + main_litedramcore_bankmachine4_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -7350,15 +7841,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_row_open <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_row_open <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_open <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_row_open <= 1'd1; end end 3'd4: begin @@ -7376,18 +7867,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_valid <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_valid <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; end end 3'd4: begin @@ -7401,12 +7892,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; end else begin end end else begin @@ -7417,18 +7908,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_row_close <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_row_close <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - litedramcore_bankmachine4_row_close <= 1'd1; + main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine4_row_close <= 1'd1; + main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine4_row_close <= 1'd1; + main_litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -7443,15 +7934,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -7469,8 +7960,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7488,12 +7979,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -7504,18 +7995,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -7532,41 +8023,139 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine4_state) +assign main_litedramcore_bankmachine5_sink_valid = main_litedramcore_bankmachine5_req_valid; +assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_sink_ready; +assign main_litedramcore_bankmachine5_sink_payload_we = main_litedramcore_bankmachine5_req_we; +assign main_litedramcore_bankmachine5_sink_payload_addr = main_litedramcore_bankmachine5_req_addr; +assign main_litedramcore_bankmachine5_sink_sink_valid = main_litedramcore_bankmachine5_source_valid; +assign main_litedramcore_bankmachine5_source_ready = main_litedramcore_bankmachine5_sink_sink_ready; +assign main_litedramcore_bankmachine5_sink_sink_first = main_litedramcore_bankmachine5_source_first; +assign main_litedramcore_bankmachine5_sink_sink_last = main_litedramcore_bankmachine5_source_last; +assign main_litedramcore_bankmachine5_sink_sink_payload_we = main_litedramcore_bankmachine5_source_payload_we; +assign main_litedramcore_bankmachine5_sink_sink_payload_addr = main_litedramcore_bankmachine5_source_payload_addr; +assign main_litedramcore_bankmachine5_source_source_ready = (main_litedramcore_bankmachine5_req_wdata_ready | main_litedramcore_bankmachine5_req_rdata_valid); +assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_source_valid | main_litedramcore_bankmachine5_source_source_valid); +assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_source_source_payload_addr[22:7]); +assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5; +always @(*) begin + main_litedramcore_bankmachine5_cmd_payload_a <= 16'd0; + if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin + main_litedramcore_bankmachine5_cmd_payload_a <= main_litedramcore_bankmachine5_source_source_payload_addr[22:7]; + end else begin + main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write); +assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); +assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); +always @(*) begin + main_litedramcore_bankmachine5_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine5_source_valid & main_litedramcore_bankmachine5_source_source_valid)) begin + if ((main_litedramcore_bankmachine5_source_payload_addr[22:7] != main_litedramcore_bankmachine5_source_source_payload_addr[22:7])) begin + main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine5_syncfifo5_din = {main_litedramcore_bankmachine5_fifo_in_last, main_litedramcore_bankmachine5_fifo_in_first, main_litedramcore_bankmachine5_fifo_in_payload_addr, main_litedramcore_bankmachine5_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout; +assign main_litedramcore_bankmachine5_sink_ready = main_litedramcore_bankmachine5_syncfifo5_writable; +assign main_litedramcore_bankmachine5_syncfifo5_we = main_litedramcore_bankmachine5_sink_valid; +assign main_litedramcore_bankmachine5_fifo_in_first = main_litedramcore_bankmachine5_sink_first; +assign main_litedramcore_bankmachine5_fifo_in_last = main_litedramcore_bankmachine5_sink_last; +assign main_litedramcore_bankmachine5_fifo_in_payload_we = main_litedramcore_bankmachine5_sink_payload_we; +assign main_litedramcore_bankmachine5_fifo_in_payload_addr = main_litedramcore_bankmachine5_sink_payload_addr; +assign main_litedramcore_bankmachine5_source_valid = main_litedramcore_bankmachine5_syncfifo5_readable; +assign main_litedramcore_bankmachine5_source_first = main_litedramcore_bankmachine5_fifo_out_first; +assign main_litedramcore_bankmachine5_source_last = main_litedramcore_bankmachine5_fifo_out_last; +assign main_litedramcore_bankmachine5_source_payload_we = main_litedramcore_bankmachine5_fifo_out_payload_we; +assign main_litedramcore_bankmachine5_source_payload_addr = main_litedramcore_bankmachine5_fifo_out_payload_addr; +assign main_litedramcore_bankmachine5_syncfifo5_re = main_litedramcore_bankmachine5_source_ready; +always @(*) begin + main_litedramcore_bankmachine5_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine5_replace) begin + main_litedramcore_bankmachine5_wrport_adr <= (main_litedramcore_bankmachine5_produce - 1'd1); + end else begin + main_litedramcore_bankmachine5_wrport_adr <= main_litedramcore_bankmachine5_produce; + end +end +assign main_litedramcore_bankmachine5_wrport_dat_w = main_litedramcore_bankmachine5_syncfifo5_din; +assign main_litedramcore_bankmachine5_wrport_we = (main_litedramcore_bankmachine5_syncfifo5_we & (main_litedramcore_bankmachine5_syncfifo5_writable | main_litedramcore_bankmachine5_replace)); +assign main_litedramcore_bankmachine5_do_read = (main_litedramcore_bankmachine5_syncfifo5_readable & main_litedramcore_bankmachine5_syncfifo5_re); +assign main_litedramcore_bankmachine5_rdport_adr = main_litedramcore_bankmachine5_consume; +assign main_litedramcore_bankmachine5_syncfifo5_dout = main_litedramcore_bankmachine5_rdport_dat_r; +assign main_litedramcore_bankmachine5_syncfifo5_writable = (main_litedramcore_bankmachine5_level != 5'd16); +assign main_litedramcore_bankmachine5_syncfifo5_readable = (main_litedramcore_bankmachine5_level != 1'd0); +assign main_litedramcore_bankmachine5_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine5_pipe_valid_source_valid) | main_litedramcore_bankmachine5_pipe_valid_source_ready); +assign main_litedramcore_bankmachine5_pipe_valid_sink_valid = main_litedramcore_bankmachine5_sink_sink_valid; +assign main_litedramcore_bankmachine5_sink_sink_ready = main_litedramcore_bankmachine5_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine5_pipe_valid_sink_first = main_litedramcore_bankmachine5_sink_sink_first; +assign main_litedramcore_bankmachine5_pipe_valid_sink_last = main_litedramcore_bankmachine5_sink_sink_last; +assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_we = main_litedramcore_bankmachine5_sink_sink_payload_we; +assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine5_sink_sink_payload_addr; +assign main_litedramcore_bankmachine5_source_source_valid = main_litedramcore_bankmachine5_pipe_valid_source_valid; +assign main_litedramcore_bankmachine5_pipe_valid_source_ready = main_litedramcore_bankmachine5_source_source_ready; +assign main_litedramcore_bankmachine5_source_source_first = main_litedramcore_bankmachine5_pipe_valid_source_first; +assign main_litedramcore_bankmachine5_source_source_last = main_litedramcore_bankmachine5_pipe_valid_source_last; +assign main_litedramcore_bankmachine5_source_source_payload_we = main_litedramcore_bankmachine5_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine5_source_source_payload_addr = main_litedramcore_bankmachine5_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine5_next_state <= 4'd0; + builder_bankmachine5_next_state <= builder_bankmachine5_state; + case (builder_bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + if (main_litedramcore_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd5; + end end end 2'd2: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + builder_bankmachine5_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + if (main_litedramcore_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine5_refresh_req)) begin + builder_bankmachine5_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine5_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine5_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine5_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine5_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin + builder_bankmachine5_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end else begin + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin + builder_bankmachine5_next_state <= 2'd2; end end else begin + builder_bankmachine5_next_state <= 1'd1; end end else begin + builder_bankmachine5_next_state <= 2'd3; end end end @@ -7574,22 +8163,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7600,142 +8182,56 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin + main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end -assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid; -assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready; -assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we; -assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr; -assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid; -assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready; -assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first; -assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last; -assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we; -assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr; -assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); -assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid); -assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[22:7]); -assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5; -always @(*) begin - litedramcore_bankmachine5_cmd_payload_a <= 16'd0; - if (litedramcore_bankmachine5_row_col_n_addr_sel) begin - litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_source_source_payload_addr[22:7]; - end else begin - litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write); -assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); -assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); -always @(*) begin - litedramcore_bankmachine5_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin - if ((litedramcore_bankmachine5_source_payload_addr[22:7] != litedramcore_bankmachine5_source_source_payload_addr[22:7])) begin - litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we}; -assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; -assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; -assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; -assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; -assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable; -assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid; -assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first; -assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last; -assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we; -assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr; -assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable; -assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first; -assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last; -assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we; -assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr; -assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready; -always @(*) begin - litedramcore_bankmachine5_wrport_adr <= 4'd0; - if (litedramcore_bankmachine5_replace) begin - litedramcore_bankmachine5_wrport_adr <= (litedramcore_bankmachine5_produce - 1'd1); - end else begin - litedramcore_bankmachine5_wrport_adr <= litedramcore_bankmachine5_produce; - end -end -assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din; -assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace)); -assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re); -assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume; -assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r; -assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 5'd16); -assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0); -assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready); -assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid; -assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready; -assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first; -assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last; -assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we; -assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr; -assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid; -assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready; -assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first; -assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last; -assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we; -assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine5_next_state <= 4'd0; - litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state; - case (litedramcore_bankmachine5_state) +always @(*) begin + main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - if (litedramcore_bankmachine5_cmd_ready) begin - litedramcore_bankmachine5_next_state <= 3'd5; - end - end end 2'd2: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - if (litedramcore_bankmachine5_cmd_ready) begin - litedramcore_bankmachine5_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~litedramcore_bankmachine5_refresh_req)) begin - litedramcore_bankmachine5_next_state <= 1'd0; - end end 3'd5: begin - litedramcore_bankmachine5_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine5_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine5_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine5_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - litedramcore_bankmachine5_next_state <= 3'd4; + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin - litedramcore_bankmachine5_next_state <= 2'd2; + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin + end else begin + main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready; end end else begin - litedramcore_bankmachine5_next_state <= 1'd1; end end else begin - litedramcore_bankmachine5_next_state <= 2'd3; end end end @@ -7743,8 +8239,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -7752,8 +8248,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine5_twtpcon_ready) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd1; + if (main_litedramcore_bankmachine5_twtpcon_ready) begin + main_litedramcore_bankmachine5_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -7769,15 +8265,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_row_open <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_row_open <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_open <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_row_open <= 1'd1; end end 3'd4: begin @@ -7795,18 +8291,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_valid <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; end end 3'd4: begin @@ -7820,12 +8316,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; end else begin end end else begin @@ -7836,18 +8332,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_row_close <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_row_close <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - litedramcore_bankmachine5_row_close <= 1'd1; + main_litedramcore_bankmachine5_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine5_row_close <= 1'd1; + main_litedramcore_bankmachine5_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine5_row_close <= 1'd1; + main_litedramcore_bankmachine5_row_close <= 1'd1; end 3'd5: begin end @@ -7862,15 +8358,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -7888,8 +8384,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -7907,12 +8403,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -7923,18 +8419,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -7952,11 +8448,11 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -7974,13 +8470,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -7993,22 +8489,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8023,8 +8519,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -8042,14 +8538,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin end else begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; end end else begin end @@ -8061,8 +8557,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -8080,13 +8576,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin + main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -8098,38 +8594,139 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine5_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine5_state) +assign main_litedramcore_bankmachine6_sink_valid = main_litedramcore_bankmachine6_req_valid; +assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_sink_ready; +assign main_litedramcore_bankmachine6_sink_payload_we = main_litedramcore_bankmachine6_req_we; +assign main_litedramcore_bankmachine6_sink_payload_addr = main_litedramcore_bankmachine6_req_addr; +assign main_litedramcore_bankmachine6_sink_sink_valid = main_litedramcore_bankmachine6_source_valid; +assign main_litedramcore_bankmachine6_source_ready = main_litedramcore_bankmachine6_sink_sink_ready; +assign main_litedramcore_bankmachine6_sink_sink_first = main_litedramcore_bankmachine6_source_first; +assign main_litedramcore_bankmachine6_sink_sink_last = main_litedramcore_bankmachine6_source_last; +assign main_litedramcore_bankmachine6_sink_sink_payload_we = main_litedramcore_bankmachine6_source_payload_we; +assign main_litedramcore_bankmachine6_sink_sink_payload_addr = main_litedramcore_bankmachine6_source_payload_addr; +assign main_litedramcore_bankmachine6_source_source_ready = (main_litedramcore_bankmachine6_req_wdata_ready | main_litedramcore_bankmachine6_req_rdata_valid); +assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_source_valid | main_litedramcore_bankmachine6_source_source_valid); +assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_source_source_payload_addr[22:7]); +assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; +always @(*) begin + main_litedramcore_bankmachine6_cmd_payload_a <= 16'd0; + if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin + main_litedramcore_bankmachine6_cmd_payload_a <= main_litedramcore_bankmachine6_source_source_payload_addr[22:7]; + end else begin + main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write); +assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); +assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); +always @(*) begin + main_litedramcore_bankmachine6_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine6_source_valid & main_litedramcore_bankmachine6_source_source_valid)) begin + if ((main_litedramcore_bankmachine6_source_payload_addr[22:7] != main_litedramcore_bankmachine6_source_source_payload_addr[22:7])) begin + main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine6_syncfifo6_din = {main_litedramcore_bankmachine6_fifo_in_last, main_litedramcore_bankmachine6_fifo_in_first, main_litedramcore_bankmachine6_fifo_in_payload_addr, main_litedramcore_bankmachine6_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout; +assign main_litedramcore_bankmachine6_sink_ready = main_litedramcore_bankmachine6_syncfifo6_writable; +assign main_litedramcore_bankmachine6_syncfifo6_we = main_litedramcore_bankmachine6_sink_valid; +assign main_litedramcore_bankmachine6_fifo_in_first = main_litedramcore_bankmachine6_sink_first; +assign main_litedramcore_bankmachine6_fifo_in_last = main_litedramcore_bankmachine6_sink_last; +assign main_litedramcore_bankmachine6_fifo_in_payload_we = main_litedramcore_bankmachine6_sink_payload_we; +assign main_litedramcore_bankmachine6_fifo_in_payload_addr = main_litedramcore_bankmachine6_sink_payload_addr; +assign main_litedramcore_bankmachine6_source_valid = main_litedramcore_bankmachine6_syncfifo6_readable; +assign main_litedramcore_bankmachine6_source_first = main_litedramcore_bankmachine6_fifo_out_first; +assign main_litedramcore_bankmachine6_source_last = main_litedramcore_bankmachine6_fifo_out_last; +assign main_litedramcore_bankmachine6_source_payload_we = main_litedramcore_bankmachine6_fifo_out_payload_we; +assign main_litedramcore_bankmachine6_source_payload_addr = main_litedramcore_bankmachine6_fifo_out_payload_addr; +assign main_litedramcore_bankmachine6_syncfifo6_re = main_litedramcore_bankmachine6_source_ready; +always @(*) begin + main_litedramcore_bankmachine6_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine6_replace) begin + main_litedramcore_bankmachine6_wrport_adr <= (main_litedramcore_bankmachine6_produce - 1'd1); + end else begin + main_litedramcore_bankmachine6_wrport_adr <= main_litedramcore_bankmachine6_produce; + end +end +assign main_litedramcore_bankmachine6_wrport_dat_w = main_litedramcore_bankmachine6_syncfifo6_din; +assign main_litedramcore_bankmachine6_wrport_we = (main_litedramcore_bankmachine6_syncfifo6_we & (main_litedramcore_bankmachine6_syncfifo6_writable | main_litedramcore_bankmachine6_replace)); +assign main_litedramcore_bankmachine6_do_read = (main_litedramcore_bankmachine6_syncfifo6_readable & main_litedramcore_bankmachine6_syncfifo6_re); +assign main_litedramcore_bankmachine6_rdport_adr = main_litedramcore_bankmachine6_consume; +assign main_litedramcore_bankmachine6_syncfifo6_dout = main_litedramcore_bankmachine6_rdport_dat_r; +assign main_litedramcore_bankmachine6_syncfifo6_writable = (main_litedramcore_bankmachine6_level != 5'd16); +assign main_litedramcore_bankmachine6_syncfifo6_readable = (main_litedramcore_bankmachine6_level != 1'd0); +assign main_litedramcore_bankmachine6_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine6_pipe_valid_source_valid) | main_litedramcore_bankmachine6_pipe_valid_source_ready); +assign main_litedramcore_bankmachine6_pipe_valid_sink_valid = main_litedramcore_bankmachine6_sink_sink_valid; +assign main_litedramcore_bankmachine6_sink_sink_ready = main_litedramcore_bankmachine6_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine6_pipe_valid_sink_first = main_litedramcore_bankmachine6_sink_sink_first; +assign main_litedramcore_bankmachine6_pipe_valid_sink_last = main_litedramcore_bankmachine6_sink_sink_last; +assign main_litedramcore_bankmachine6_pipe_valid_sink_payload_we = main_litedramcore_bankmachine6_sink_sink_payload_we; +assign main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine6_sink_sink_payload_addr; +assign main_litedramcore_bankmachine6_source_source_valid = main_litedramcore_bankmachine6_pipe_valid_source_valid; +assign main_litedramcore_bankmachine6_pipe_valid_source_ready = main_litedramcore_bankmachine6_source_source_ready; +assign main_litedramcore_bankmachine6_source_source_first = main_litedramcore_bankmachine6_pipe_valid_source_first; +assign main_litedramcore_bankmachine6_source_source_last = main_litedramcore_bankmachine6_pipe_valid_source_last; +assign main_litedramcore_bankmachine6_source_source_payload_we = main_litedramcore_bankmachine6_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine6_source_source_payload_addr = main_litedramcore_bankmachine6_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine6_next_state <= 4'd0; + builder_bankmachine6_next_state <= builder_bankmachine6_state; + case (builder_bankmachine6_state) 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + if (main_litedramcore_bankmachine6_cmd_ready) begin + builder_bankmachine6_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + builder_bankmachine6_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + if (main_litedramcore_bankmachine6_cmd_ready) begin + builder_bankmachine6_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine6_refresh_req)) begin + builder_bankmachine6_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine6_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine6_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine6_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine6_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin + builder_bankmachine6_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin - litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; - end else begin + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if ((main_litedramcore_bankmachine6_cmd_ready & main_litedramcore_bankmachine6_auto_precharge)) begin + builder_bankmachine6_next_state <= 2'd2; end end else begin + builder_bankmachine6_next_state <= 1'd1; end end else begin + builder_bankmachine6_next_state <= 2'd3; end end end @@ -8137,13 +8734,16 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine6_row_open <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_open <= 1'd1; + end end 3'd4: begin end @@ -8156,157 +8756,44 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin - end else begin - litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end -assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid; -assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready; -assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we; -assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr; -assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid; -assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready; -assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first; -assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last; -assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we; -assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr; -assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); -assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid); -assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[22:7]); -assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6; -always @(*) begin - litedramcore_bankmachine6_cmd_payload_a <= 16'd0; - if (litedramcore_bankmachine6_row_col_n_addr_sel) begin - litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_source_source_payload_addr[22:7]; - end else begin - litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write); -assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); -assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); -always @(*) begin - litedramcore_bankmachine6_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin - if ((litedramcore_bankmachine6_source_payload_addr[22:7] != litedramcore_bankmachine6_source_source_payload_addr[22:7])) begin - litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we}; -assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; -assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; -assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; -assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; -assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable; -assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid; -assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first; -assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last; -assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we; -assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr; -assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable; -assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first; -assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last; -assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we; -assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr; -assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready; -always @(*) begin - litedramcore_bankmachine6_wrport_adr <= 4'd0; - if (litedramcore_bankmachine6_replace) begin - litedramcore_bankmachine6_wrport_adr <= (litedramcore_bankmachine6_produce - 1'd1); - end else begin - litedramcore_bankmachine6_wrport_adr <= litedramcore_bankmachine6_produce; - end -end -assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din; -assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace)); -assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re); -assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume; -assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r; -assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 5'd16); -assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0); -assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready); -assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid; -assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready; -assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first; -assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last; -assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we; -assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr; -assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid; -assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready; -assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first; -assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last; -assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we; -assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine6_next_state <= 4'd0; - litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state; - case (litedramcore_bankmachine6_state) +always @(*) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - if (litedramcore_bankmachine6_cmd_ready) begin - litedramcore_bankmachine6_next_state <= 3'd5; - end + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; end end 2'd2: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - if (litedramcore_bankmachine6_cmd_ready) begin - litedramcore_bankmachine6_next_state <= 3'd7; - end + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; end end 3'd4: begin - if ((~litedramcore_bankmachine6_refresh_req)) begin - litedramcore_bankmachine6_next_state <= 1'd0; - end end 3'd5: begin - litedramcore_bankmachine6_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine6_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine6_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine6_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - litedramcore_bankmachine6_next_state <= 3'd4; + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin - litedramcore_bankmachine6_next_state <= 2'd2; - end + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; end else begin - litedramcore_bankmachine6_next_state <= 1'd1; end end else begin - litedramcore_bankmachine6_next_state <= 2'd3; end end end @@ -8314,15 +8801,41 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_row_close <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd2: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -8340,8 +8853,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8359,12 +8872,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -8375,18 +8888,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -8404,11 +8917,11 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -8426,13 +8939,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -8445,22 +8958,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8475,8 +8988,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8494,14 +9007,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin end else begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; end end else begin end @@ -8513,8 +9026,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8532,13 +9045,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin + main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -8551,8 +9064,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8570,13 +9083,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin - litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin + main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready; end else begin end end else begin @@ -8589,8 +9102,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8608,14 +9121,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin end else begin - litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; + main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready; end end else begin end @@ -8627,8 +9140,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8636,36 +9149,10 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine6_twtpcon_ready) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_row_open <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_open <= 1'd1; + if (main_litedramcore_bankmachine6_twtpcon_ready) begin + main_litedramcore_bankmachine6_refresh_gnt <= 1'd1; end end - 3'd4: begin - end 3'd5: begin end 3'd6: begin @@ -8678,41 +9165,139 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine6_cmd_valid <= 1'd0; - case (litedramcore_bankmachine6_state) +assign main_litedramcore_bankmachine7_sink_valid = main_litedramcore_bankmachine7_req_valid; +assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_sink_ready; +assign main_litedramcore_bankmachine7_sink_payload_we = main_litedramcore_bankmachine7_req_we; +assign main_litedramcore_bankmachine7_sink_payload_addr = main_litedramcore_bankmachine7_req_addr; +assign main_litedramcore_bankmachine7_sink_sink_valid = main_litedramcore_bankmachine7_source_valid; +assign main_litedramcore_bankmachine7_source_ready = main_litedramcore_bankmachine7_sink_sink_ready; +assign main_litedramcore_bankmachine7_sink_sink_first = main_litedramcore_bankmachine7_source_first; +assign main_litedramcore_bankmachine7_sink_sink_last = main_litedramcore_bankmachine7_source_last; +assign main_litedramcore_bankmachine7_sink_sink_payload_we = main_litedramcore_bankmachine7_source_payload_we; +assign main_litedramcore_bankmachine7_sink_sink_payload_addr = main_litedramcore_bankmachine7_source_payload_addr; +assign main_litedramcore_bankmachine7_source_source_ready = (main_litedramcore_bankmachine7_req_wdata_ready | main_litedramcore_bankmachine7_req_rdata_valid); +assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_source_valid | main_litedramcore_bankmachine7_source_source_valid); +assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_source_source_payload_addr[22:7]); +assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7; +always @(*) begin + main_litedramcore_bankmachine7_cmd_payload_a <= 16'd0; + if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin + main_litedramcore_bankmachine7_cmd_payload_a <= main_litedramcore_bankmachine7_source_source_payload_addr[22:7]; + end else begin + main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write); +assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); +assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); +always @(*) begin + main_litedramcore_bankmachine7_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine7_source_valid & main_litedramcore_bankmachine7_source_source_valid)) begin + if ((main_litedramcore_bankmachine7_source_payload_addr[22:7] != main_litedramcore_bankmachine7_source_source_payload_addr[22:7])) begin + main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine7_syncfifo7_din = {main_litedramcore_bankmachine7_fifo_in_last, main_litedramcore_bankmachine7_fifo_in_first, main_litedramcore_bankmachine7_fifo_in_payload_addr, main_litedramcore_bankmachine7_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout; +assign main_litedramcore_bankmachine7_sink_ready = main_litedramcore_bankmachine7_syncfifo7_writable; +assign main_litedramcore_bankmachine7_syncfifo7_we = main_litedramcore_bankmachine7_sink_valid; +assign main_litedramcore_bankmachine7_fifo_in_first = main_litedramcore_bankmachine7_sink_first; +assign main_litedramcore_bankmachine7_fifo_in_last = main_litedramcore_bankmachine7_sink_last; +assign main_litedramcore_bankmachine7_fifo_in_payload_we = main_litedramcore_bankmachine7_sink_payload_we; +assign main_litedramcore_bankmachine7_fifo_in_payload_addr = main_litedramcore_bankmachine7_sink_payload_addr; +assign main_litedramcore_bankmachine7_source_valid = main_litedramcore_bankmachine7_syncfifo7_readable; +assign main_litedramcore_bankmachine7_source_first = main_litedramcore_bankmachine7_fifo_out_first; +assign main_litedramcore_bankmachine7_source_last = main_litedramcore_bankmachine7_fifo_out_last; +assign main_litedramcore_bankmachine7_source_payload_we = main_litedramcore_bankmachine7_fifo_out_payload_we; +assign main_litedramcore_bankmachine7_source_payload_addr = main_litedramcore_bankmachine7_fifo_out_payload_addr; +assign main_litedramcore_bankmachine7_syncfifo7_re = main_litedramcore_bankmachine7_source_ready; +always @(*) begin + main_litedramcore_bankmachine7_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine7_replace) begin + main_litedramcore_bankmachine7_wrport_adr <= (main_litedramcore_bankmachine7_produce - 1'd1); + end else begin + main_litedramcore_bankmachine7_wrport_adr <= main_litedramcore_bankmachine7_produce; + end +end +assign main_litedramcore_bankmachine7_wrport_dat_w = main_litedramcore_bankmachine7_syncfifo7_din; +assign main_litedramcore_bankmachine7_wrport_we = (main_litedramcore_bankmachine7_syncfifo7_we & (main_litedramcore_bankmachine7_syncfifo7_writable | main_litedramcore_bankmachine7_replace)); +assign main_litedramcore_bankmachine7_do_read = (main_litedramcore_bankmachine7_syncfifo7_readable & main_litedramcore_bankmachine7_syncfifo7_re); +assign main_litedramcore_bankmachine7_rdport_adr = main_litedramcore_bankmachine7_consume; +assign main_litedramcore_bankmachine7_syncfifo7_dout = main_litedramcore_bankmachine7_rdport_dat_r; +assign main_litedramcore_bankmachine7_syncfifo7_writable = (main_litedramcore_bankmachine7_level != 5'd16); +assign main_litedramcore_bankmachine7_syncfifo7_readable = (main_litedramcore_bankmachine7_level != 1'd0); +assign main_litedramcore_bankmachine7_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine7_pipe_valid_source_valid) | main_litedramcore_bankmachine7_pipe_valid_source_ready); +assign main_litedramcore_bankmachine7_pipe_valid_sink_valid = main_litedramcore_bankmachine7_sink_sink_valid; +assign main_litedramcore_bankmachine7_sink_sink_ready = main_litedramcore_bankmachine7_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine7_pipe_valid_sink_first = main_litedramcore_bankmachine7_sink_sink_first; +assign main_litedramcore_bankmachine7_pipe_valid_sink_last = main_litedramcore_bankmachine7_sink_sink_last; +assign main_litedramcore_bankmachine7_pipe_valid_sink_payload_we = main_litedramcore_bankmachine7_sink_sink_payload_we; +assign main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine7_sink_sink_payload_addr; +assign main_litedramcore_bankmachine7_source_source_valid = main_litedramcore_bankmachine7_pipe_valid_source_valid; +assign main_litedramcore_bankmachine7_pipe_valid_source_ready = main_litedramcore_bankmachine7_source_source_ready; +assign main_litedramcore_bankmachine7_source_source_first = main_litedramcore_bankmachine7_pipe_valid_source_first; +assign main_litedramcore_bankmachine7_source_source_last = main_litedramcore_bankmachine7_pipe_valid_source_last; +assign main_litedramcore_bankmachine7_source_source_payload_we = main_litedramcore_bankmachine7_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine7_source_source_payload_addr = main_litedramcore_bankmachine7_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine7_next_state <= 4'd0; + builder_bankmachine7_next_state <= builder_bankmachine7_state; + case (builder_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + if (main_litedramcore_bankmachine7_cmd_ready) begin + builder_bankmachine7_next_state <= 3'd5; + end end end 2'd2: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + builder_bankmachine7_next_state <= 3'd5; + end end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + if (main_litedramcore_bankmachine7_cmd_ready) begin + builder_bankmachine7_next_state <= 3'd7; + end end end 3'd4: begin + if ((~main_litedramcore_bankmachine7_refresh_req)) begin + builder_bankmachine7_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine7_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine7_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine7_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine7_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin + builder_bankmachine7_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if ((main_litedramcore_bankmachine7_cmd_ready & main_litedramcore_bankmachine7_auto_precharge)) begin + builder_bankmachine7_next_state <= 2'd2; + end end else begin + builder_bankmachine7_next_state <= 1'd1; end end else begin + builder_bankmachine7_next_state <= 2'd3; end end end @@ -8720,173 +9305,34 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_row_close <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid; -assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready; -assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we; -assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr; -assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid; -assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready; -assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first; -assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last; -assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we; -assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr; -assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); -assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid); -assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[22:7]); -assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7; -always @(*) begin - litedramcore_bankmachine7_cmd_payload_a <= 16'd0; - if (litedramcore_bankmachine7_row_col_n_addr_sel) begin - litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_source_source_payload_addr[22:7]; - end else begin - litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write); -assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); -assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); -always @(*) begin - litedramcore_bankmachine7_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin - if ((litedramcore_bankmachine7_source_payload_addr[22:7] != litedramcore_bankmachine7_source_source_payload_addr[22:7])) begin - litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we}; -assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; -assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; -assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; -assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; -assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable; -assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid; -assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first; -assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last; -assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we; -assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr; -assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable; -assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first; -assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last; -assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we; -assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr; -assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready; -always @(*) begin - litedramcore_bankmachine7_wrport_adr <= 4'd0; - if (litedramcore_bankmachine7_replace) begin - litedramcore_bankmachine7_wrport_adr <= (litedramcore_bankmachine7_produce - 1'd1); - end else begin - litedramcore_bankmachine7_wrport_adr <= litedramcore_bankmachine7_produce; - end -end -assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din; -assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace)); -assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re); -assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume; -assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r; -assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 5'd16); -assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0); -assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready); -assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid; -assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready; -assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first; -assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last; -assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we; -assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr; -assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid; -assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready; -assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first; -assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last; -assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we; -assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine7_next_state <= 4'd0; - litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - if (litedramcore_bankmachine7_cmd_ready) begin - litedramcore_bankmachine7_next_state <= 3'd5; - end - end end 2'd2: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - if (litedramcore_bankmachine7_cmd_ready) begin - litedramcore_bankmachine7_next_state <= 3'd7; - end + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin - if ((~litedramcore_bankmachine7_refresh_req)) begin - litedramcore_bankmachine7_next_state <= 1'd0; - end end 3'd5: begin - litedramcore_bankmachine7_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine7_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine7_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine7_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - litedramcore_bankmachine7_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin - litedramcore_bankmachine7_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine7_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine7_next_state <= 2'd3; - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -8904,12 +9350,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -8920,18 +9366,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -8949,11 +9395,11 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -8971,13 +9417,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -8990,22 +9436,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9020,8 +9466,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -9039,14 +9485,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin end else begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9058,8 +9504,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -9077,13 +9523,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -9096,8 +9542,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -9115,13 +9561,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin - litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin + main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready; end else begin end end else begin @@ -9134,8 +9580,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -9153,14 +9599,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin end else begin - litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; + main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready; end end else begin end @@ -9172,8 +9618,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -9181,8 +9627,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine7_twtpcon_ready) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd1; + if (main_litedramcore_bankmachine7_twtpcon_ready) begin + main_litedramcore_bankmachine7_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -9198,15 +9644,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_row_open <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_row_open <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_open <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_row_open <= 1'd1; end end 3'd4: begin @@ -9224,18 +9670,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_valid <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; end end 3'd4: begin @@ -9249,12 +9695,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; end else begin end end else begin @@ -9265,18 +9711,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_row_close <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_row_close <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - litedramcore_bankmachine7_row_close <= 1'd1; + main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine7_row_close <= 1'd1; + main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine7_row_close <= 1'd1; + main_litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -9290,292 +9736,263 @@ always @(*) begin end endcase end +assign main_litedramcore_nphases = (main_a7ddrphy_rdphase_storage - 1'd1); +assign main_litedramcore_rdphase = (main_a7ddrphy_wrphase_storage - 1'd1); +assign main_litedramcore_trrdcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))); +assign main_litedramcore_tfawcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))); +assign main_litedramcore_ras_allowed = (main_litedramcore_trrdcon_ready & main_litedramcore_tfawcon_ready); +assign main_litedramcore_tccdcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_cmd_payload_is_write | main_litedramcore_choose_req_cmd_payload_is_read)); +assign main_litedramcore_cas_allowed = main_litedramcore_tccdcon_ready; +assign main_litedramcore_twtrcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); +assign main_litedramcore_read_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_read) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_read)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_read)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_read)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_read)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_read)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_read)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_read)); +assign main_litedramcore_write_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_write) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_write)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_write)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_write)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_write)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_write)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_write)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_write)); +assign main_litedramcore_max_time0 = (main_litedramcore_time0 == 1'd0); +assign main_litedramcore_max_time1 = (main_litedramcore_time1 == 1'd0); +assign main_litedramcore_bankmachine0_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine1_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine2_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine3_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine4_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine5_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine6_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine7_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_go_to_refresh = (((((((main_litedramcore_bankmachine0_refresh_gnt & main_litedramcore_bankmachine1_refresh_gnt) & main_litedramcore_bankmachine2_refresh_gnt) & main_litedramcore_bankmachine3_refresh_gnt) & main_litedramcore_bankmachine4_refresh_gnt) & main_litedramcore_bankmachine5_refresh_gnt) & main_litedramcore_bankmachine6_refresh_gnt) & main_litedramcore_bankmachine7_refresh_gnt); +assign main_litedramcore_interface_rdata = {main_litedramcore_dfi_p3_rddata, main_litedramcore_dfi_p2_rddata, main_litedramcore_dfi_p1_rddata, main_litedramcore_dfi_p0_rddata}; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); always @(*) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -assign litedramcore_rdcmdphase = (a7ddrphy_rdphase_storage - 1'd1); -assign litedramcore_wrcmdphase = (a7ddrphy_wrphase_storage - 1'd1); -assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); -assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); -assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready); -assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read)); -assign litedramcore_cas_allowed = litedramcore_tccdcon_ready; -assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); -assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read)); -assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write)); -assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0); -assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0); -assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid; -assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt); -assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata}; -assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; -assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; -assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; -assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; -assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); -assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); -assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); -assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); -always @(*) begin - litedramcore_choose_cmd_valids <= 8'd0; - litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids <= 8'd0; + main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); end -assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; -assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0; -assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1; -assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2; -assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; -assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; -assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; +assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids; +assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_self0; +assign main_litedramcore_choose_cmd_cmd_payload_a = builder_rhs_self1; +assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_self2; +assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_self3; +assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_self4; +assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_self5; always @(*) begin - litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; + main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_self0; end end always @(*) begin - litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; + main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_self1; end end always @(*) begin - litedramcore_choose_cmd_cmd_payload_we <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; + main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_self2; end end always @(*) begin - litedramcore_bankmachine0_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin - litedramcore_bankmachine0_cmd_ready <= 1'd1; + main_litedramcore_bankmachine0_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin + main_litedramcore_bankmachine0_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin - litedramcore_bankmachine0_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin + main_litedramcore_bankmachine0_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine1_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin - litedramcore_bankmachine1_cmd_ready <= 1'd1; + main_litedramcore_bankmachine1_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin + main_litedramcore_bankmachine1_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin - litedramcore_bankmachine1_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin + main_litedramcore_bankmachine1_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine2_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin - litedramcore_bankmachine2_cmd_ready <= 1'd1; + main_litedramcore_bankmachine2_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin + main_litedramcore_bankmachine2_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin - litedramcore_bankmachine2_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin + main_litedramcore_bankmachine2_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine3_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin - litedramcore_bankmachine3_cmd_ready <= 1'd1; + main_litedramcore_bankmachine3_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin + main_litedramcore_bankmachine3_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin - litedramcore_bankmachine3_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin + main_litedramcore_bankmachine3_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine4_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin - litedramcore_bankmachine4_cmd_ready <= 1'd1; + main_litedramcore_bankmachine4_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin + main_litedramcore_bankmachine4_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin - litedramcore_bankmachine4_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin + main_litedramcore_bankmachine4_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine5_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin - litedramcore_bankmachine5_cmd_ready <= 1'd1; + main_litedramcore_bankmachine5_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin + main_litedramcore_bankmachine5_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin - litedramcore_bankmachine5_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin + main_litedramcore_bankmachine5_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine6_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin - litedramcore_bankmachine6_cmd_ready <= 1'd1; + main_litedramcore_bankmachine6_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin + main_litedramcore_bankmachine6_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin - litedramcore_bankmachine6_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin + main_litedramcore_bankmachine6_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine7_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin - litedramcore_bankmachine7_cmd_ready <= 1'd1; + main_litedramcore_bankmachine7_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin + main_litedramcore_bankmachine7_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin - litedramcore_bankmachine7_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin + main_litedramcore_bankmachine7_cmd_ready <= 1'd1; end end -assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid)); +assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid)); always @(*) begin - litedramcore_choose_req_valids <= 8'd0; - litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids <= 8'd0; + main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); end -assign litedramcore_choose_req_request = litedramcore_choose_req_valids; -assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6; -assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7; -assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8; -assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9; -assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; -assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; +assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids; +assign main_litedramcore_choose_req_cmd_valid = builder_rhs_self6; +assign main_litedramcore_choose_req_cmd_payload_a = builder_rhs_self7; +assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_self8; +assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_self9; +assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_self10; +assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_self11; always @(*) begin - litedramcore_choose_req_cmd_payload_cas <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; + main_litedramcore_choose_req_cmd_payload_cas <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_cas <= builder_t_self3; end end always @(*) begin - litedramcore_choose_req_cmd_payload_ras <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; + main_litedramcore_choose_req_cmd_payload_ras <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_ras <= builder_t_self4; end end always @(*) begin - litedramcore_choose_req_cmd_payload_we <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; + main_litedramcore_choose_req_cmd_payload_we <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_we <= builder_t_self5; end end -assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); -assign litedramcore_dfi_p0_reset_n = 1'd1; -assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}}; -assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}}; -assign litedramcore_dfi_p1_reset_n = 1'd1; -assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}}; -assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}}; -assign litedramcore_dfi_p2_reset_n = 1'd1; -assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}}; -assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}}; -assign litedramcore_dfi_p3_reset_n = 1'd1; -assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}}; -assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}}; -assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]); +assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid)); +assign main_litedramcore_dfi_p0_reset_n = 1'd1; +assign main_litedramcore_dfi_p0_cke = {1{main_litedramcore_steerer4}}; +assign main_litedramcore_dfi_p0_odt = {1{main_litedramcore_steerer5}}; +assign main_litedramcore_dfi_p1_reset_n = 1'd1; +assign main_litedramcore_dfi_p1_cke = {1{main_litedramcore_steerer6}}; +assign main_litedramcore_dfi_p1_odt = {1{main_litedramcore_steerer7}}; +assign main_litedramcore_dfi_p2_reset_n = 1'd1; +assign main_litedramcore_dfi_p2_cke = {1{main_litedramcore_steerer8}}; +assign main_litedramcore_dfi_p2_odt = {1{main_litedramcore_steerer9}}; +assign main_litedramcore_dfi_p3_reset_n = 1'd1; +assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer10}}; +assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer11}}; +assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]); always @(*) begin - litedramcore_multiplexer_next_state <= 4'd0; - litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state; - case (litedramcore_multiplexer_state) + builder_multiplexer_next_state <= 4'd0; + builder_multiplexer_next_state <= builder_multiplexer_state; + case (builder_multiplexer_state) 1'd1: begin - if (litedramcore_read_available) begin - if (((~litedramcore_write_available) | litedramcore_max_time1)) begin - litedramcore_multiplexer_next_state <= 2'd3; + if (main_litedramcore_read_available) begin + if (((~main_litedramcore_write_available) | main_litedramcore_max_time1)) begin + builder_multiplexer_next_state <= 2'd3; end end - if (litedramcore_go_to_refresh) begin - litedramcore_multiplexer_next_state <= 2'd2; + if (main_litedramcore_go_to_refresh) begin + builder_multiplexer_next_state <= 2'd2; end end 2'd2: begin - if (litedramcore_cmd_last) begin - litedramcore_multiplexer_next_state <= 1'd0; + if (main_litedramcore_cmd_last) begin + builder_multiplexer_next_state <= 1'd0; end end 2'd3: begin - if (litedramcore_twtrcon_ready) begin - litedramcore_multiplexer_next_state <= 1'd0; + if (main_litedramcore_twtrcon_ready) begin + builder_multiplexer_next_state <= 1'd0; end end 3'd4: begin - litedramcore_multiplexer_next_state <= 3'd5; + builder_multiplexer_next_state <= 3'd5; end 3'd5: begin - litedramcore_multiplexer_next_state <= 3'd6; + builder_multiplexer_next_state <= 3'd6; end 3'd6: begin - litedramcore_multiplexer_next_state <= 3'd7; + builder_multiplexer_next_state <= 3'd7; end 3'd7: begin - litedramcore_multiplexer_next_state <= 4'd8; + builder_multiplexer_next_state <= 4'd8; end 4'd8: begin - litedramcore_multiplexer_next_state <= 4'd9; + builder_multiplexer_next_state <= 4'd9; end 4'd9: begin - litedramcore_multiplexer_next_state <= 4'd10; + builder_multiplexer_next_state <= 4'd10; end 4'd10: begin - litedramcore_multiplexer_next_state <= 1'd1; + builder_multiplexer_next_state <= 1'd1; end default: begin - if (litedramcore_write_available) begin - if (((~litedramcore_read_available) | litedramcore_max_time0)) begin - litedramcore_multiplexer_next_state <= 3'd4; + if (main_litedramcore_write_available) begin + if (((~main_litedramcore_read_available) | main_litedramcore_max_time0)) begin + builder_multiplexer_next_state <= 3'd4; end end - if (litedramcore_go_to_refresh) begin - litedramcore_multiplexer_next_state <= 2'd2; + if (main_litedramcore_go_to_refresh) begin + builder_multiplexer_next_state <= 2'd2; end end endcase end always @(*) begin - litedramcore_steerer_sel0 <= 2'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_req_cmd_ready <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_steerer_sel0 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 1'd0)) begin - litedramcore_steerer_sel0 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 1'd0)) begin - litedramcore_steerer_sel0 <= 1'd1; + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; end end 2'd2: begin - litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end @@ -9594,23 +10011,21 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel0 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 1'd0)) begin - litedramcore_steerer_sel0 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 1'd0)) begin - litedramcore_steerer_sel0 <= 1'd1; + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; end end endcase end always @(*) begin - litedramcore_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_en1 <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin + main_litedramcore_en1 <= 1'd1; end 2'd2: begin - litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -9633,18 +10048,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_steerer_sel1 <= 2'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_steerer0 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_steerer_sel1 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 1'd1)) begin - litedramcore_steerer_sel1 <= 2'd2; + main_litedramcore_steerer0 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 1'd0)) begin + main_litedramcore_steerer0 <= 2'd2; end - if ((litedramcore_wrcmdphase == 1'd1)) begin - litedramcore_steerer_sel1 <= 1'd1; + if ((main_litedramcore_rdphase == 1'd0)) begin + main_litedramcore_steerer0 <= 1'd1; end end 2'd2: begin + main_litedramcore_steerer0 <= 2'd3; end 2'd3: begin end @@ -9663,29 +10079,23 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel1 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 1'd1)) begin - litedramcore_steerer_sel1 <= 2'd2; + main_litedramcore_steerer0 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 1'd0)) begin + main_litedramcore_steerer0 <= 2'd2; end - if ((litedramcore_rdcmdphase == 1'd1)) begin - litedramcore_steerer_sel1 <= 1'd1; + if ((main_litedramcore_nphases == 1'd0)) begin + main_litedramcore_steerer0 <= 1'd1; end end endcase end always @(*) begin - litedramcore_steerer_sel2 <= 2'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_cmd_ready <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_steerer_sel2 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 2'd2)) begin - litedramcore_steerer_sel2 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 2'd2)) begin - litedramcore_steerer_sel2 <= 1'd1; - end end 2'd2: begin + main_litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -9704,23 +10114,19 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel2 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 2'd2)) begin - litedramcore_steerer_sel2 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 2'd2)) begin - litedramcore_steerer_sel2 <= 1'd1; - end end endcase end always @(*) begin - litedramcore_choose_cmd_want_activates <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_steerer1 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + main_litedramcore_steerer1 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin + main_litedramcore_steerer1 <= 2'd2; + end + if ((main_litedramcore_rdphase == 1'd1)) begin + main_litedramcore_steerer1 <= 1'd1; end end 2'd2: begin @@ -9742,23 +10148,26 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + main_litedramcore_steerer1 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin + main_litedramcore_steerer1 <= 2'd2; + end + if ((main_litedramcore_nphases == 1'd1)) begin + main_litedramcore_steerer1 <= 1'd1; end end endcase end always @(*) begin - litedramcore_steerer_sel3 <= 2'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_steerer2 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_steerer_sel3 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 2'd3)) begin - litedramcore_steerer_sel3 <= 2'd2; + main_litedramcore_steerer2 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 2'd2)) begin + main_litedramcore_steerer2 <= 2'd2; end - if ((litedramcore_wrcmdphase == 2'd3)) begin - litedramcore_steerer_sel3 <= 1'd1; + if ((main_litedramcore_rdphase == 2'd2)) begin + main_litedramcore_steerer2 <= 1'd1; end end 2'd2: begin @@ -9780,20 +10189,24 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel3 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 2'd3)) begin - litedramcore_steerer_sel3 <= 2'd2; + main_litedramcore_steerer2 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 2'd2)) begin + main_litedramcore_steerer2 <= 2'd2; end - if ((litedramcore_rdcmdphase == 2'd3)) begin - litedramcore_steerer_sel3 <= 1'd1; + if ((main_litedramcore_nphases == 2'd2)) begin + main_litedramcore_steerer2 <= 1'd1; end end endcase end always @(*) begin - litedramcore_en0 <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_cmd_want_activates <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; + end end 2'd2: begin end @@ -9814,17 +10227,23 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_en0 <= 1'd1; + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; + end end endcase end always @(*) begin - litedramcore_choose_cmd_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_steerer3 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + main_litedramcore_steerer3 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin + main_litedramcore_steerer3 <= 2'd2; + end + if ((main_litedramcore_rdphase == 2'd3)) begin + main_litedramcore_steerer3 <= 1'd1; end end 2'd2: begin @@ -9846,16 +10265,19 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + main_litedramcore_steerer3 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin + main_litedramcore_steerer3 <= 2'd2; + end + if ((main_litedramcore_nphases == 2'd3)) begin + main_litedramcore_steerer3 <= 1'd1; end end endcase end always @(*) begin - litedramcore_choose_req_want_reads <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_en0 <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin end 2'd2: begin @@ -9877,15 +10299,18 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_choose_req_want_reads <= 1'd1; + main_litedramcore_en0 <= 1'd1; end endcase end always @(*) begin - litedramcore_choose_req_want_writes <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_cmd_cmd_ready <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_choose_req_want_writes <= 1'd1; + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); + end end 2'd2: begin end @@ -9906,14 +10331,17 @@ always @(*) begin 4'd10: begin end default: begin + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); + end end endcase end always @(*) begin - litedramcore_en1 <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_req_want_reads <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_en1 <= 1'd1; end 2'd2: begin end @@ -9934,18 +10362,15 @@ always @(*) begin 4'd10: begin end default: begin + main_litedramcore_choose_req_want_reads <= 1'd1; end endcase end always @(*) begin - litedramcore_choose_req_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_req_want_writes <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end + main_litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -9966,2016 +10391,2008 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end end endcase end -assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock)); -assign litedramcore_interface_bank0_addr = rhs_array_muxed12; -assign litedramcore_interface_bank0_we = rhs_array_muxed13; -assign litedramcore_interface_bank0_valid = rhs_array_muxed14; -assign litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock)); -assign litedramcore_interface_bank1_addr = rhs_array_muxed15; -assign litedramcore_interface_bank1_we = rhs_array_muxed16; -assign litedramcore_interface_bank1_valid = rhs_array_muxed17; -assign litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock)); -assign litedramcore_interface_bank2_addr = rhs_array_muxed18; -assign litedramcore_interface_bank2_we = rhs_array_muxed19; -assign litedramcore_interface_bank2_valid = rhs_array_muxed20; -assign litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock)); -assign litedramcore_interface_bank3_addr = rhs_array_muxed21; -assign litedramcore_interface_bank3_we = rhs_array_muxed22; -assign litedramcore_interface_bank3_valid = rhs_array_muxed23; -assign litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock)); -assign litedramcore_interface_bank4_addr = rhs_array_muxed24; -assign litedramcore_interface_bank4_we = rhs_array_muxed25; -assign litedramcore_interface_bank4_valid = rhs_array_muxed26; -assign litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock)); -assign litedramcore_interface_bank5_addr = rhs_array_muxed27; -assign litedramcore_interface_bank5_we = rhs_array_muxed28; -assign litedramcore_interface_bank5_valid = rhs_array_muxed29; -assign litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock)); -assign litedramcore_interface_bank6_addr = rhs_array_muxed30; -assign litedramcore_interface_bank6_we = rhs_array_muxed31; -assign litedramcore_interface_bank6_valid = rhs_array_muxed32; -assign litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock)); -assign litedramcore_interface_bank7_addr = rhs_array_muxed33; -assign litedramcore_interface_bank7_we = rhs_array_muxed34; -assign litedramcore_interface_bank7_valid = rhs_array_muxed35; -assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready)); -assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1; -assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8; -always @(*) begin - litedramcore_interface_wdata <= 128'd0; - case ({litedramcore_new_master_wdata_ready1}) +assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock)); +assign main_litedramcore_interface_bank0_addr = builder_rhs_self12; +assign main_litedramcore_interface_bank0_we = builder_rhs_self13; +assign main_litedramcore_interface_bank0_valid = builder_rhs_self14; +assign builder_roundrobin1_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin1_ce = ((~main_litedramcore_interface_bank1_valid) & (~main_litedramcore_interface_bank1_lock)); +assign main_litedramcore_interface_bank1_addr = builder_rhs_self15; +assign main_litedramcore_interface_bank1_we = builder_rhs_self16; +assign main_litedramcore_interface_bank1_valid = builder_rhs_self17; +assign builder_roundrobin2_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin2_ce = ((~main_litedramcore_interface_bank2_valid) & (~main_litedramcore_interface_bank2_lock)); +assign main_litedramcore_interface_bank2_addr = builder_rhs_self18; +assign main_litedramcore_interface_bank2_we = builder_rhs_self19; +assign main_litedramcore_interface_bank2_valid = builder_rhs_self20; +assign builder_roundrobin3_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin3_ce = ((~main_litedramcore_interface_bank3_valid) & (~main_litedramcore_interface_bank3_lock)); +assign main_litedramcore_interface_bank3_addr = builder_rhs_self21; +assign main_litedramcore_interface_bank3_we = builder_rhs_self22; +assign main_litedramcore_interface_bank3_valid = builder_rhs_self23; +assign builder_roundrobin4_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin4_ce = ((~main_litedramcore_interface_bank4_valid) & (~main_litedramcore_interface_bank4_lock)); +assign main_litedramcore_interface_bank4_addr = builder_rhs_self24; +assign main_litedramcore_interface_bank4_we = builder_rhs_self25; +assign main_litedramcore_interface_bank4_valid = builder_rhs_self26; +assign builder_roundrobin5_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin5_ce = ((~main_litedramcore_interface_bank5_valid) & (~main_litedramcore_interface_bank5_lock)); +assign main_litedramcore_interface_bank5_addr = builder_rhs_self27; +assign main_litedramcore_interface_bank5_we = builder_rhs_self28; +assign main_litedramcore_interface_bank5_valid = builder_rhs_self29; +assign builder_roundrobin6_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin6_ce = ((~main_litedramcore_interface_bank6_valid) & (~main_litedramcore_interface_bank6_lock)); +assign main_litedramcore_interface_bank6_addr = builder_rhs_self30; +assign main_litedramcore_interface_bank6_we = builder_rhs_self31; +assign main_litedramcore_interface_bank6_valid = builder_rhs_self32; +assign builder_roundrobin7_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin7_ce = ((~main_litedramcore_interface_bank7_valid) & (~main_litedramcore_interface_bank7_lock)); +assign main_litedramcore_interface_bank7_addr = builder_rhs_self33; +assign main_litedramcore_interface_bank7_we = builder_rhs_self34; +assign main_litedramcore_interface_bank7_valid = builder_rhs_self35; +assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready)); +assign main_user_port_wdata_ready = builder_new_master_wdata_ready1; +assign main_user_port_rdata_valid = builder_new_master_rdata_valid8; +always @(*) begin + main_litedramcore_interface_wdata <= 128'd0; + case ({builder_new_master_wdata_ready1}) 1'd1: begin - litedramcore_interface_wdata <= user_port_wdata_payload_data; + main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data; end default: begin - litedramcore_interface_wdata <= 1'd0; + main_litedramcore_interface_wdata <= 1'd0; end endcase end always @(*) begin - litedramcore_interface_wdata_we <= 16'd0; - case ({litedramcore_new_master_wdata_ready1}) + main_litedramcore_interface_wdata_we <= 16'd0; + case ({builder_new_master_wdata_ready1}) 1'd1: begin - litedramcore_interface_wdata_we <= user_port_wdata_payload_we; + main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we; end default: begin - litedramcore_interface_wdata_we <= 1'd0; + main_litedramcore_interface_wdata_we <= 1'd0; end endcase end -assign user_port_rdata_payload_data = litedramcore_interface_rdata; -assign litedramcore_roundrobin0_grant = 1'd0; -assign litedramcore_roundrobin1_grant = 1'd0; -assign litedramcore_roundrobin2_grant = 1'd0; -assign litedramcore_roundrobin3_grant = 1'd0; -assign litedramcore_roundrobin4_grant = 1'd0; -assign litedramcore_roundrobin5_grant = 1'd0; -assign litedramcore_roundrobin6_grant = 1'd0; -assign litedramcore_roundrobin7_grant = 1'd0; -always @(*) begin - litedramcore_next_state <= 2'd0; - litedramcore_next_state <= litedramcore_state; - case (litedramcore_state) +assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata; +assign builder_roundrobin0_grant = 1'd0; +assign builder_roundrobin1_grant = 1'd0; +assign builder_roundrobin2_grant = 1'd0; +assign builder_roundrobin3_grant = 1'd0; +assign builder_roundrobin4_grant = 1'd0; +assign builder_roundrobin5_grant = 1'd0; +assign builder_roundrobin6_grant = 1'd0; +assign builder_roundrobin7_grant = 1'd0; +always @(*) begin + builder_next_state <= 2'd0; + builder_next_state <= builder_state; + case (builder_state) 1'd1: begin - litedramcore_next_state <= 2'd2; + builder_next_state <= 2'd2; end 2'd2: begin - litedramcore_next_state <= 1'd0; + builder_next_state <= 1'd0; end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_next_state <= 1'd1; + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_next_state <= 1'd1; end end endcase end always @(*) begin - litedramcore_adr_next_value1 <= 14'd0; - case (litedramcore_state) + builder_interface0_dat_r <= 32'd0; + case (builder_state) 1'd1: begin - litedramcore_adr_next_value1 <= 1'd0; end 2'd2: begin + builder_interface0_dat_r <= builder_interface1_dat_r; end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value1 <= litedramcore_wishbone_adr; - end end endcase end always @(*) begin - litedramcore_adr_next_value_ce1 <= 1'd0; - case (litedramcore_state) + builder_interface1_dat_w_next_value0 <= 32'd0; + case (builder_state) 1'd1: begin - litedramcore_adr_next_value_ce1 <= 1'd1; end 2'd2: begin end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value_ce1 <= 1'd1; - end + builder_interface1_dat_w_next_value0 <= builder_interface0_dat_w; end endcase end always @(*) begin - litedramcore_wishbone_dat_r <= 32'd0; - case (litedramcore_state) + builder_interface1_dat_w_next_value_ce0 <= 1'd0; + case (builder_state) 1'd1: begin end 2'd2: begin - litedramcore_wishbone_dat_r <= litedramcore_dat_r; end default: begin + builder_interface1_dat_w_next_value_ce0 <= 1'd1; end endcase end always @(*) begin - litedramcore_we_next_value2 <= 1'd0; - case (litedramcore_state) + builder_interface1_adr_next_value1 <= 14'd0; + case (builder_state) 1'd1: begin - litedramcore_we_next_value2 <= 1'd0; + builder_interface1_adr_next_value1 <= 1'd0; end 2'd2: begin end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_adr_next_value1 <= builder_interface0_adr[29:0]; end end endcase end always @(*) begin - litedramcore_we_next_value_ce2 <= 1'd0; - case (litedramcore_state) + builder_interface0_ack <= 1'd0; + case (builder_state) 1'd1: begin - litedramcore_we_next_value_ce2 <= 1'd1; end 2'd2: begin + builder_interface0_ack <= 1'd1; end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value_ce2 <= 1'd1; - end end endcase end always @(*) begin - litedramcore_wishbone_ack <= 1'd0; - case (litedramcore_state) + builder_interface1_adr_next_value_ce1 <= 1'd0; + case (builder_state) 1'd1: begin + builder_interface1_adr_next_value_ce1 <= 1'd1; end 2'd2: begin - litedramcore_wishbone_ack <= 1'd1; end default: begin + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_adr_next_value_ce1 <= 1'd1; + end end endcase end always @(*) begin - litedramcore_dat_w_next_value0 <= 32'd0; - case (litedramcore_state) + builder_interface1_we_next_value2 <= 1'd0; + case (builder_state) 1'd1: begin + builder_interface1_we_next_value2 <= 1'd0; end 2'd2: begin end default: begin - litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w; + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_we_next_value2 <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); + end end endcase end always @(*) begin - litedramcore_dat_w_next_value_ce0 <= 1'd0; - case (litedramcore_state) + builder_interface1_we_next_value_ce2 <= 1'd0; + case (builder_state) 1'd1: begin + builder_interface1_we_next_value_ce2 <= 1'd1; end 2'd2: begin end default: begin - litedramcore_dat_w_next_value_ce0 <= 1'd1; + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_we_next_value_ce2 <= 1'd1; + end end endcase end -assign litedramcore_wishbone_adr = wb_bus_adr; -assign litedramcore_wishbone_dat_w = wb_bus_dat_w; -assign wb_bus_dat_r = litedramcore_wishbone_dat_r; -assign litedramcore_wishbone_sel = wb_bus_sel; -assign litedramcore_wishbone_cyc = wb_bus_cyc; -assign litedramcore_wishbone_stb = wb_bus_stb; -assign wb_bus_ack = litedramcore_wishbone_ack; -assign litedramcore_wishbone_we = wb_bus_we; -assign litedramcore_wishbone_cti = wb_bus_cti; -assign litedramcore_wishbone_bte = wb_bus_bte; -assign wb_bus_err = litedramcore_wishbone_err; -assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); -assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; +assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); +assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_done0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_we <= (~interface0_bank_bus_we); + builder_csrbank0_init_done0_re <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we; end end always @(*) begin - csrbank0_init_done0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_re <= interface0_bank_bus_we; + builder_csrbank0_init_done0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we); end end -assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; +assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_error0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_we <= (~interface0_bank_bus_we); + builder_csrbank0_init_error0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we); end end always @(*) begin - csrbank0_init_error0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_re <= interface0_bank_bus_we; + builder_csrbank0_init_error0_re <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; end end -assign csrbank0_init_done0_w = init_done_storage; -assign csrbank0_init_error0_w = init_error_storage; -assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); -assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0]; +assign builder_csrbank0_init_done0_w = main_init_done_storage; +assign builder_csrbank0_init_error0_w = main_init_error_storage; +assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1); +assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - csrbank1_rst0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_rst0_we <= (~interface1_bank_bus_we); + builder_csrbank1_rst0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - csrbank1_rst0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_rst0_re <= interface1_bank_bus_we; + builder_csrbank1_rst0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; end end -assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; +assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_dly_sel0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dly_sel0_re <= interface1_bank_bus_we; + builder_csrbank1_dly_sel0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - csrbank1_dly_sel0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dly_sel0_we <= (~interface1_bank_bus_we); + builder_csrbank1_dly_sel0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we); end end -assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; +assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0]; always @(*) begin - csrbank1_half_sys8x_taps0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we); + builder_csrbank1_half_sys8x_taps0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - csrbank1_half_sys8x_taps0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we; + builder_csrbank1_half_sys8x_taps0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we); end end -assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0]; +assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - csrbank1_wlevel_en0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_wlevel_en0_re <= interface1_bank_bus_we; + builder_csrbank1_wlevel_en0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - csrbank1_wlevel_en0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we); + builder_csrbank1_wlevel_en0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we; end end -assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_wlevel_strobe_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we; + main_a7ddrphy_wlevel_strobe_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we; end end always @(*) begin - a7ddrphy_wlevel_strobe_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we); + main_a7ddrphy_wlevel_strobe_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we); end end -assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; end end always @(*) begin - a7ddrphy_rdly_dq_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we); end end -assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_inc_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_inc_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; end end always @(*) begin - a7ddrphy_rdly_dq_inc_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_inc_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we); end end -assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end end -assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_bitslip_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - a7ddrphy_rdly_dq_bitslip_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end end -assign a7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end end -assign a7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_wdly_dq_bitslip_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we); + main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - a7ddrphy_wdly_dq_bitslip_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we; + main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end end -assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0]; +assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_rdphase0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - csrbank1_rdphase0_re <= interface1_bank_bus_we; + builder_csrbank1_rdphase0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - csrbank1_rdphase0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - csrbank1_rdphase0_we <= (~interface1_bank_bus_we); + builder_csrbank1_rdphase0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we); end end -assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0]; +assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_wrphase0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - csrbank1_wrphase0_we <= (~interface1_bank_bus_we); + builder_csrbank1_wrphase0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - csrbank1_wrphase0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - csrbank1_wrphase0_re <= interface1_bank_bus_we; + builder_csrbank1_wrphase0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; end end -assign csrbank1_rst0_w = a7ddrphy_rst_storage; -assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; -assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0]; -assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage; -assign csrbank1_rdphase0_w = a7ddrphy_rdphase_storage[1:0]; -assign csrbank1_wrphase0_w = a7ddrphy_wrphase_storage[1:0]; -assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); -assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; +assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage; +assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0]; +assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0]; +assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage; +assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0]; +assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0]; +assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2); +assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0]; always @(*) begin - csrbank2_dfii_control0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_control0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_control0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_control0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; +assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi0_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi0_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we; end end -assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; +assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector0_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we); + main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - litedramcore_phaseinjector0_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we; + main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[15:0]; +assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[15:0]; always @(*) begin - csrbank2_dfii_pi0_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi0_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi0_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi0_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi0_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin + builder_csrbank2_dfii_pi0_rddata_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi0_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin + builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; +assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi1_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi1_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we); end end -assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; +assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector1_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we; + main_litedramcore_phaseinjector1_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin + main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we; end end always @(*) begin - litedramcore_phaseinjector1_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we); + main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin + main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[15:0]; +assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[15:0]; always @(*) begin - csrbank2_dfii_pi1_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi1_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi1_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi1_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi1_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi1_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi1_rddata_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0]; +assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi2_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi2_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we); end end -assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; +assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector2_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we); + main_litedramcore_phaseinjector2_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we; end end always @(*) begin - litedramcore_phaseinjector2_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we; + main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[15:0]; +assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[15:0]; always @(*) begin - csrbank2_dfii_pi2_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi2_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi2_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi2_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi2_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin - csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi2_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin - csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi2_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin - csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi2_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin - csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank2_dfii_pi2_rddata_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0]; +assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi3_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin - csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi3_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin - csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we; end end -assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; +assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector3_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin - litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we; + main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - litedramcore_phaseinjector3_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin - litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we); + main_litedramcore_phaseinjector3_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[15:0]; +assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[15:0]; always @(*) begin - csrbank2_dfii_pi3_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin - csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi3_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin - csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi3_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin - csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi3_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin - csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi3_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin - csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi3_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin - csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi3_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin - csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi3_rddata_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi3_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin - csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we); end end -assign litedramcore_sel = litedramcore_storage[0]; -assign litedramcore_cke = litedramcore_storage[1]; -assign litedramcore_odt = litedramcore_storage[2]; -assign litedramcore_reset_n = litedramcore_storage[3]; -assign csrbank2_dfii_control0_w = litedramcore_storage[3:0]; -assign litedramcore_phaseinjector0_csrfield_cs = litedramcore_phaseinjector0_command_storage[0]; -assign litedramcore_phaseinjector0_csrfield_we = litedramcore_phaseinjector0_command_storage[1]; -assign litedramcore_phaseinjector0_csrfield_cas = litedramcore_phaseinjector0_command_storage[2]; -assign litedramcore_phaseinjector0_csrfield_ras = litedramcore_phaseinjector0_command_storage[3]; -assign litedramcore_phaseinjector0_csrfield_wren = litedramcore_phaseinjector0_command_storage[4]; -assign litedramcore_phaseinjector0_csrfield_rden = litedramcore_phaseinjector0_command_storage[5]; -assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; -assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[15:0]; -assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0]; -assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0]; -assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_rddata_status[31:0]; -assign litedramcore_phaseinjector0_rddata_we = csrbank2_dfii_pi0_rddata_we; -assign litedramcore_phaseinjector1_csrfield_cs = litedramcore_phaseinjector1_command_storage[0]; -assign litedramcore_phaseinjector1_csrfield_we = litedramcore_phaseinjector1_command_storage[1]; -assign litedramcore_phaseinjector1_csrfield_cas = litedramcore_phaseinjector1_command_storage[2]; -assign litedramcore_phaseinjector1_csrfield_ras = litedramcore_phaseinjector1_command_storage[3]; -assign litedramcore_phaseinjector1_csrfield_wren = litedramcore_phaseinjector1_command_storage[4]; -assign litedramcore_phaseinjector1_csrfield_rden = litedramcore_phaseinjector1_command_storage[5]; -assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0]; -assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[15:0]; -assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0]; -assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0]; -assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_rddata_status[31:0]; -assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata_we; -assign litedramcore_phaseinjector2_csrfield_cs = litedramcore_phaseinjector2_command_storage[0]; -assign litedramcore_phaseinjector2_csrfield_we = litedramcore_phaseinjector2_command_storage[1]; -assign litedramcore_phaseinjector2_csrfield_cas = litedramcore_phaseinjector2_command_storage[2]; -assign litedramcore_phaseinjector2_csrfield_ras = litedramcore_phaseinjector2_command_storage[3]; -assign litedramcore_phaseinjector2_csrfield_wren = litedramcore_phaseinjector2_command_storage[4]; -assign litedramcore_phaseinjector2_csrfield_rden = litedramcore_phaseinjector2_command_storage[5]; -assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0]; -assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[15:0]; -assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0]; -assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0]; -assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_rddata_status[31:0]; -assign litedramcore_phaseinjector2_rddata_we = csrbank2_dfii_pi2_rddata_we; -assign litedramcore_phaseinjector3_csrfield_cs = litedramcore_phaseinjector3_command_storage[0]; -assign litedramcore_phaseinjector3_csrfield_we = litedramcore_phaseinjector3_command_storage[1]; -assign litedramcore_phaseinjector3_csrfield_cas = litedramcore_phaseinjector3_command_storage[2]; -assign litedramcore_phaseinjector3_csrfield_ras = litedramcore_phaseinjector3_command_storage[3]; -assign litedramcore_phaseinjector3_csrfield_wren = litedramcore_phaseinjector3_command_storage[4]; -assign litedramcore_phaseinjector3_csrfield_rden = litedramcore_phaseinjector3_command_storage[5]; -assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0]; -assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[15:0]; -assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0]; -assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0]; -assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_rddata_status[31:0]; -assign litedramcore_phaseinjector3_rddata_we = csrbank2_dfii_pi3_rddata_we; -assign csr_interconnect_adr = litedramcore_adr; -assign csr_interconnect_we = litedramcore_we; -assign csr_interconnect_dat_w = litedramcore_dat_w; -assign litedramcore_dat_r = csr_interconnect_dat_r; -assign interface0_bank_bus_adr = csr_interconnect_adr; -assign interface1_bank_bus_adr = csr_interconnect_adr; -assign interface2_bank_bus_adr = csr_interconnect_adr; -assign interface0_bank_bus_we = csr_interconnect_we; -assign interface1_bank_bus_we = csr_interconnect_we; -assign interface2_bank_bus_we = csr_interconnect_we; -assign interface0_bank_bus_dat_w = csr_interconnect_dat_w; -assign interface1_bank_bus_dat_w = csr_interconnect_dat_w; -assign interface2_bank_bus_dat_w = csr_interconnect_dat_w; -assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); -always @(*) begin - rhs_array_muxed0 <= 1'd0; - case (litedramcore_choose_cmd_grant) +assign main_litedramcore_sel = main_litedramcore_storage[0]; +assign main_litedramcore_cke = main_litedramcore_storage[1]; +assign main_litedramcore_odt = main_litedramcore_storage[2]; +assign main_litedramcore_reset_n = main_litedramcore_storage[3]; +assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0]; +assign main_litedramcore_phaseinjector0_csrfield_cs = main_litedramcore_phaseinjector0_command_storage[0]; +assign main_litedramcore_phaseinjector0_csrfield_we = main_litedramcore_phaseinjector0_command_storage[1]; +assign main_litedramcore_phaseinjector0_csrfield_cas = main_litedramcore_phaseinjector0_command_storage[2]; +assign main_litedramcore_phaseinjector0_csrfield_ras = main_litedramcore_phaseinjector0_command_storage[3]; +assign main_litedramcore_phaseinjector0_csrfield_wren = main_litedramcore_phaseinjector0_command_storage[4]; +assign main_litedramcore_phaseinjector0_csrfield_rden = main_litedramcore_phaseinjector0_command_storage[5]; +assign main_litedramcore_phaseinjector0_csrfield_cs_top = main_litedramcore_phaseinjector0_command_storage[6]; +assign main_litedramcore_phaseinjector0_csrfield_cs_bottom = main_litedramcore_phaseinjector0_command_storage[7]; +assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[7:0]; +assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[15:0]; +assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0]; +assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we; +assign main_litedramcore_phaseinjector1_csrfield_cs = main_litedramcore_phaseinjector1_command_storage[0]; +assign main_litedramcore_phaseinjector1_csrfield_we = main_litedramcore_phaseinjector1_command_storage[1]; +assign main_litedramcore_phaseinjector1_csrfield_cas = main_litedramcore_phaseinjector1_command_storage[2]; +assign main_litedramcore_phaseinjector1_csrfield_ras = main_litedramcore_phaseinjector1_command_storage[3]; +assign main_litedramcore_phaseinjector1_csrfield_wren = main_litedramcore_phaseinjector1_command_storage[4]; +assign main_litedramcore_phaseinjector1_csrfield_rden = main_litedramcore_phaseinjector1_command_storage[5]; +assign main_litedramcore_phaseinjector1_csrfield_cs_top = main_litedramcore_phaseinjector1_command_storage[6]; +assign main_litedramcore_phaseinjector1_csrfield_cs_bottom = main_litedramcore_phaseinjector1_command_storage[7]; +assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[7:0]; +assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[15:0]; +assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0]; +assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we; +assign main_litedramcore_phaseinjector2_csrfield_cs = main_litedramcore_phaseinjector2_command_storage[0]; +assign main_litedramcore_phaseinjector2_csrfield_we = main_litedramcore_phaseinjector2_command_storage[1]; +assign main_litedramcore_phaseinjector2_csrfield_cas = main_litedramcore_phaseinjector2_command_storage[2]; +assign main_litedramcore_phaseinjector2_csrfield_ras = main_litedramcore_phaseinjector2_command_storage[3]; +assign main_litedramcore_phaseinjector2_csrfield_wren = main_litedramcore_phaseinjector2_command_storage[4]; +assign main_litedramcore_phaseinjector2_csrfield_rden = main_litedramcore_phaseinjector2_command_storage[5]; +assign main_litedramcore_phaseinjector2_csrfield_cs_top = main_litedramcore_phaseinjector2_command_storage[6]; +assign main_litedramcore_phaseinjector2_csrfield_cs_bottom = main_litedramcore_phaseinjector2_command_storage[7]; +assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[7:0]; +assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[15:0]; +assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0]; +assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we; +assign main_litedramcore_phaseinjector3_csrfield_cs = main_litedramcore_phaseinjector3_command_storage[0]; +assign main_litedramcore_phaseinjector3_csrfield_we = main_litedramcore_phaseinjector3_command_storage[1]; +assign main_litedramcore_phaseinjector3_csrfield_cas = main_litedramcore_phaseinjector3_command_storage[2]; +assign main_litedramcore_phaseinjector3_csrfield_ras = main_litedramcore_phaseinjector3_command_storage[3]; +assign main_litedramcore_phaseinjector3_csrfield_wren = main_litedramcore_phaseinjector3_command_storage[4]; +assign main_litedramcore_phaseinjector3_csrfield_rden = main_litedramcore_phaseinjector3_command_storage[5]; +assign main_litedramcore_phaseinjector3_csrfield_cs_top = main_litedramcore_phaseinjector3_command_storage[6]; +assign main_litedramcore_phaseinjector3_csrfield_cs_bottom = main_litedramcore_phaseinjector3_command_storage[7]; +assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[7:0]; +assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[15:0]; +assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0]; +assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we; +assign builder_adr = builder_interface1_adr; +assign builder_we = builder_interface1_we; +assign builder_dat_w = builder_interface1_dat_w; +assign builder_interface1_dat_r = builder_dat_r; +assign builder_interface0_bank_bus_adr = builder_adr; +assign builder_interface1_bank_bus_adr = builder_adr; +assign builder_interface2_bank_bus_adr = builder_adr; +assign builder_interface0_bank_bus_we = builder_we; +assign builder_interface1_bank_bus_we = builder_we; +assign builder_interface2_bank_bus_we = builder_we; +assign builder_interface0_bank_bus_dat_w = builder_dat_w; +assign builder_interface1_bank_bus_dat_w = builder_dat_w; +assign builder_interface2_bank_bus_dat_w = builder_dat_w; +assign builder_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); +always @(*) begin + builder_rhs_self0 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[0]; end 1'd1: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[1]; end 2'd2: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[2]; end 2'd3: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[3]; end 3'd4: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[4]; end 3'd5: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[5]; end 3'd6: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[6]; end default: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[7]; end endcase end always @(*) begin - rhs_array_muxed1 <= 16'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self1 <= 16'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine6_cmd_payload_a; end default: begin - rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase end always @(*) begin - rhs_array_muxed2 <= 3'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self2 <= 3'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine6_cmd_payload_ba; end default: begin - rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase end always @(*) begin - rhs_array_muxed3 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self3 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase end always @(*) begin - rhs_array_muxed4 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self4 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase end always @(*) begin - rhs_array_muxed5 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self5 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase end always @(*) begin - t_array_muxed0 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_t_self0 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine6_cmd_payload_cas; end default: begin - t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase end always @(*) begin - t_array_muxed1 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_t_self1 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine6_cmd_payload_ras; end default: begin - t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase end always @(*) begin - t_array_muxed2 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_t_self2 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine6_cmd_payload_we; end default: begin - t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed6 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self6 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[0]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[0]; end 1'd1: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[1]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[1]; end 2'd2: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[2]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[2]; end 2'd3: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[3]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[3]; end 3'd4: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[4]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[4]; end 3'd5: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[5]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[5]; end 3'd6: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[6]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[6]; end default: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[7]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[7]; end endcase end always @(*) begin - rhs_array_muxed7 <= 16'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self7 <= 16'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine6_cmd_payload_a; end default: begin - rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase end always @(*) begin - rhs_array_muxed8 <= 3'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self8 <= 3'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine6_cmd_payload_ba; end default: begin - rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase end always @(*) begin - rhs_array_muxed9 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self9 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase end always @(*) begin - rhs_array_muxed10 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self10 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase end always @(*) begin - rhs_array_muxed11 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self11 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase end always @(*) begin - t_array_muxed3 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_t_self3 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine6_cmd_payload_cas; end default: begin - t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase end always @(*) begin - t_array_muxed4 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_t_self4 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine6_cmd_payload_ras; end default: begin - t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase end always @(*) begin - t_array_muxed5 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_t_self5 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine6_cmd_payload_we; end default: begin - t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed12 <= 23'd0; - case (litedramcore_roundrobin0_grant) + builder_rhs_self12 <= 23'd0; + case (builder_roundrobin0_grant) default: begin - rhs_array_muxed12 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self12 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed13 <= 1'd0; - case (litedramcore_roundrobin0_grant) + builder_rhs_self13 <= 1'd0; + case (builder_roundrobin0_grant) default: begin - rhs_array_muxed13 <= user_port_cmd_payload_we; + builder_rhs_self13 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed14 <= 1'd0; - case (litedramcore_roundrobin0_grant) + builder_rhs_self14 <= 1'd0; + case (builder_roundrobin0_grant) default: begin - rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed15 <= 23'd0; - case (litedramcore_roundrobin1_grant) + builder_rhs_self15 <= 23'd0; + case (builder_roundrobin1_grant) default: begin - rhs_array_muxed15 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self15 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed16 <= 1'd0; - case (litedramcore_roundrobin1_grant) + builder_rhs_self16 <= 1'd0; + case (builder_roundrobin1_grant) default: begin - rhs_array_muxed16 <= user_port_cmd_payload_we; + builder_rhs_self16 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed17 <= 1'd0; - case (litedramcore_roundrobin1_grant) + builder_rhs_self17 <= 1'd0; + case (builder_roundrobin1_grant) default: begin - rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed18 <= 23'd0; - case (litedramcore_roundrobin2_grant) + builder_rhs_self18 <= 23'd0; + case (builder_roundrobin2_grant) default: begin - rhs_array_muxed18 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self18 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed19 <= 1'd0; - case (litedramcore_roundrobin2_grant) + builder_rhs_self19 <= 1'd0; + case (builder_roundrobin2_grant) default: begin - rhs_array_muxed19 <= user_port_cmd_payload_we; + builder_rhs_self19 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed20 <= 1'd0; - case (litedramcore_roundrobin2_grant) + builder_rhs_self20 <= 1'd0; + case (builder_roundrobin2_grant) default: begin - rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed21 <= 23'd0; - case (litedramcore_roundrobin3_grant) + builder_rhs_self21 <= 23'd0; + case (builder_roundrobin3_grant) default: begin - rhs_array_muxed21 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self21 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed22 <= 1'd0; - case (litedramcore_roundrobin3_grant) + builder_rhs_self22 <= 1'd0; + case (builder_roundrobin3_grant) default: begin - rhs_array_muxed22 <= user_port_cmd_payload_we; + builder_rhs_self22 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed23 <= 1'd0; - case (litedramcore_roundrobin3_grant) + builder_rhs_self23 <= 1'd0; + case (builder_roundrobin3_grant) default: begin - rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed24 <= 23'd0; - case (litedramcore_roundrobin4_grant) + builder_rhs_self24 <= 23'd0; + case (builder_roundrobin4_grant) default: begin - rhs_array_muxed24 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self24 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed25 <= 1'd0; - case (litedramcore_roundrobin4_grant) + builder_rhs_self25 <= 1'd0; + case (builder_roundrobin4_grant) default: begin - rhs_array_muxed25 <= user_port_cmd_payload_we; + builder_rhs_self25 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed26 <= 1'd0; - case (litedramcore_roundrobin4_grant) + builder_rhs_self26 <= 1'd0; + case (builder_roundrobin4_grant) default: begin - rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed27 <= 23'd0; - case (litedramcore_roundrobin5_grant) + builder_rhs_self27 <= 23'd0; + case (builder_roundrobin5_grant) default: begin - rhs_array_muxed27 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self27 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed28 <= 1'd0; - case (litedramcore_roundrobin5_grant) + builder_rhs_self28 <= 1'd0; + case (builder_roundrobin5_grant) default: begin - rhs_array_muxed28 <= user_port_cmd_payload_we; + builder_rhs_self28 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed29 <= 1'd0; - case (litedramcore_roundrobin5_grant) + builder_rhs_self29 <= 1'd0; + case (builder_roundrobin5_grant) default: begin - rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed30 <= 23'd0; - case (litedramcore_roundrobin6_grant) + builder_rhs_self30 <= 23'd0; + case (builder_roundrobin6_grant) default: begin - rhs_array_muxed30 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self30 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed31 <= 1'd0; - case (litedramcore_roundrobin6_grant) + builder_rhs_self31 <= 1'd0; + case (builder_roundrobin6_grant) default: begin - rhs_array_muxed31 <= user_port_cmd_payload_we; + builder_rhs_self31 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed32 <= 1'd0; - case (litedramcore_roundrobin6_grant) + builder_rhs_self32 <= 1'd0; + case (builder_roundrobin6_grant) default: begin - rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed33 <= 23'd0; - case (litedramcore_roundrobin7_grant) + builder_rhs_self33 <= 23'd0; + case (builder_roundrobin7_grant) default: begin - rhs_array_muxed33 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self33 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed34 <= 1'd0; - case (litedramcore_roundrobin7_grant) + builder_rhs_self34 <= 1'd0; + case (builder_roundrobin7_grant) default: begin - rhs_array_muxed34 <= user_port_cmd_payload_we; + builder_rhs_self34 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed35 <= 1'd0; - case (litedramcore_roundrobin7_grant) + builder_rhs_self35 <= 1'd0; + case (builder_roundrobin7_grant) default: begin - rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - array_muxed0 <= 3'd0; - case (litedramcore_steerer_sel0) + builder_self0 <= 3'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed0 <= litedramcore_nop_ba[2:0]; + builder_self0 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed0 <= litedramcore_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed1 <= 16'd0; - case (litedramcore_steerer_sel0) + builder_self1 <= 16'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed1 <= litedramcore_nop_a; + builder_self1 <= main_litedramcore_nop_a; end 1'd1: begin - array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a; + builder_self1 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed1 <= litedramcore_choose_req_cmd_payload_a; + builder_self1 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed1 <= litedramcore_cmd_payload_a; + builder_self1 <= main_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed2 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self2 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed2 <= 1'd0; + builder_self2 <= 1'd0; end 1'd1: begin - array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + builder_self2 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + builder_self2 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + builder_self2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed3 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self3 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed3 <= 1'd0; + builder_self3 <= 1'd0; end 1'd1: begin - array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + builder_self3 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + builder_self3 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + builder_self3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed4 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self4 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed4 <= 1'd0; + builder_self4 <= 1'd0; end 1'd1: begin - array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + builder_self4 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + builder_self4 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + builder_self4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed5 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self5 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed5 <= 1'd0; + builder_self5 <= 1'd0; end 1'd1: begin - array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + builder_self5 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + builder_self5 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + builder_self5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed6 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self6 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed6 <= 1'd0; + builder_self6 <= 1'd0; end 1'd1: begin - array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + builder_self6 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + builder_self6 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + builder_self6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase end always @(*) begin - array_muxed7 <= 3'd0; - case (litedramcore_steerer_sel1) + builder_self7 <= 3'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed7 <= litedramcore_nop_ba[2:0]; + builder_self7 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed7 <= litedramcore_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed8 <= 16'd0; - case (litedramcore_steerer_sel1) + builder_self8 <= 16'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed8 <= litedramcore_nop_a; + builder_self8 <= main_litedramcore_nop_a; end 1'd1: begin - array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a; + builder_self8 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed8 <= litedramcore_choose_req_cmd_payload_a; + builder_self8 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed8 <= litedramcore_cmd_payload_a; + builder_self8 <= main_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed9 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self9 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed9 <= 1'd0; + builder_self9 <= 1'd0; end 1'd1: begin - array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + builder_self9 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + builder_self9 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + builder_self9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed10 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self10 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed10 <= 1'd0; + builder_self10 <= 1'd0; end 1'd1: begin - array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + builder_self10 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + builder_self10 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + builder_self10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed11 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self11 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed11 <= 1'd0; + builder_self11 <= 1'd0; end 1'd1: begin - array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + builder_self11 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + builder_self11 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + builder_self11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed12 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self12 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed12 <= 1'd0; + builder_self12 <= 1'd0; end 1'd1: begin - array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + builder_self12 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + builder_self12 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + builder_self12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed13 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self13 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed13 <= 1'd0; + builder_self13 <= 1'd0; end 1'd1: begin - array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + builder_self13 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + builder_self13 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + builder_self13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase end always @(*) begin - array_muxed14 <= 3'd0; - case (litedramcore_steerer_sel2) + builder_self14 <= 3'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed14 <= litedramcore_nop_ba[2:0]; + builder_self14 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed14 <= litedramcore_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed15 <= 16'd0; - case (litedramcore_steerer_sel2) + builder_self15 <= 16'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed15 <= litedramcore_nop_a; + builder_self15 <= main_litedramcore_nop_a; end 1'd1: begin - array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a; + builder_self15 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed15 <= litedramcore_choose_req_cmd_payload_a; + builder_self15 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed15 <= litedramcore_cmd_payload_a; + builder_self15 <= main_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed16 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self16 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed16 <= 1'd0; + builder_self16 <= 1'd0; end 1'd1: begin - array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + builder_self16 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + builder_self16 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + builder_self16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed17 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self17 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed17 <= 1'd0; + builder_self17 <= 1'd0; end 1'd1: begin - array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + builder_self17 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + builder_self17 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + builder_self17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed18 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self18 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed18 <= 1'd0; + builder_self18 <= 1'd0; end 1'd1: begin - array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + builder_self18 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + builder_self18 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + builder_self18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed19 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self19 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed19 <= 1'd0; + builder_self19 <= 1'd0; end 1'd1: begin - array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + builder_self19 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + builder_self19 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + builder_self19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed20 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self20 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed20 <= 1'd0; + builder_self20 <= 1'd0; end 1'd1: begin - array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + builder_self20 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + builder_self20 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + builder_self20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase end always @(*) begin - array_muxed21 <= 3'd0; - case (litedramcore_steerer_sel3) + builder_self21 <= 3'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed21 <= litedramcore_nop_ba[2:0]; + builder_self21 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed21 <= litedramcore_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed22 <= 16'd0; - case (litedramcore_steerer_sel3) + builder_self22 <= 16'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed22 <= litedramcore_nop_a; + builder_self22 <= main_litedramcore_nop_a; end 1'd1: begin - array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a; + builder_self22 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed22 <= litedramcore_choose_req_cmd_payload_a; + builder_self22 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed22 <= litedramcore_cmd_payload_a; + builder_self22 <= main_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed23 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self23 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed23 <= 1'd0; + builder_self23 <= 1'd0; end 1'd1: begin - array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + builder_self23 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + builder_self23 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + builder_self23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed24 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self24 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed24 <= 1'd0; + builder_self24 <= 1'd0; end 1'd1: begin - array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + builder_self24 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + builder_self24 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + builder_self24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed25 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self25 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed25 <= 1'd0; + builder_self25 <= 1'd0; end 1'd1: begin - array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + builder_self25 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + builder_self25 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + builder_self25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed26 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self26 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed26 <= 1'd0; + builder_self26 <= 1'd0; end 1'd1: begin - array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + builder_self26 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + builder_self26 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + builder_self26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed27 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self27 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed27 <= 1'd0; + builder_self27 <= 1'd0; end 1'd1: begin - array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + builder_self27 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + builder_self27 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + builder_self27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase end -assign xilinxasyncresetsynchronizerimpl0 = (~locked); -assign xilinxasyncresetsynchronizerimpl1 = (~locked); -assign xilinxasyncresetsynchronizerimpl2 = (~locked); -assign xilinxasyncresetsynchronizerimpl3 = (~locked); +assign builder_xilinxasyncresetsynchronizerimpl0_async_reset = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl1_async_reset = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl2_async_reset = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl3_async_reset = (~main_locked); //------------------------------------------------------------------------------ @@ -11983,1044 +12400,1044 @@ assign xilinxasyncresetsynchronizerimpl3 = (~locked); //------------------------------------------------------------------------------ always @(posedge iodelay_clk) begin - if ((reset_counter != 1'd0)) begin - reset_counter <= (reset_counter - 1'd1); + if ((main_reset_counter != 1'd0)) begin + main_reset_counter <= (main_reset_counter - 1'd1); end else begin - ic_reset <= 1'd0; + main_ic_reset <= 1'd0; end if (iodelay_rst) begin - reset_counter <= 4'd15; - ic_reset <= 1'd1; + main_reset_counter <= 4'd15; + main_ic_reset <= 1'd1; end end always @(posedge sys_clk) begin - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline; - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; - a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1); + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline; + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; + main_a7ddrphy_dqspattern_o1 <= main_a7ddrphy_dqspattern_o0; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value0 <= (main_a7ddrphy_bitslip0_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value0 <= 3'd7; end - a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1); + main_a7ddrphy_bitslip0_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip0_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value0 <= (main_a7ddrphy_bitslip1_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value0 <= 3'd7; end - a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1); + main_a7ddrphy_bitslip1_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip1_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value1 <= (main_a7ddrphy_bitslip0_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value1 <= 3'd7; end - a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1); + main_a7ddrphy_bitslip0_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[2], main_a7ddrphy_dfi_p3_wrdata_mask[0], main_a7ddrphy_dfi_p2_wrdata_mask[2], main_a7ddrphy_dfi_p2_wrdata_mask[0], main_a7ddrphy_dfi_p1_wrdata_mask[2], main_a7ddrphy_dfi_p1_wrdata_mask[0], main_a7ddrphy_dfi_p0_wrdata_mask[2], main_a7ddrphy_dfi_p0_wrdata_mask[0]}, main_a7ddrphy_bitslip0_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value1 <= (main_a7ddrphy_bitslip1_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value1 <= 3'd7; end - a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]}; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1); + main_a7ddrphy_bitslip1_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[3], main_a7ddrphy_dfi_p3_wrdata_mask[1], main_a7ddrphy_dfi_p2_wrdata_mask[3], main_a7ddrphy_dfi_p2_wrdata_mask[1], main_a7ddrphy_dfi_p1_wrdata_mask[3], main_a7ddrphy_dfi_p1_wrdata_mask[1], main_a7ddrphy_dfi_p0_wrdata_mask[3], main_a7ddrphy_dfi_p0_wrdata_mask[1]}, main_a7ddrphy_bitslip1_r1[15:8]}; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dq_oe_delay_tappeddelayline; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value2 <= (main_a7ddrphy_bitslip0_value2 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value2 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value2 <= 3'd7; end - a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1); + main_a7ddrphy_bitslip0_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[16], main_a7ddrphy_dfi_p3_wrdata[0], main_a7ddrphy_dfi_p2_wrdata[16], main_a7ddrphy_dfi_p2_wrdata[0], main_a7ddrphy_dfi_p1_wrdata[16], main_a7ddrphy_dfi_p1_wrdata[0], main_a7ddrphy_dfi_p0_wrdata[16], main_a7ddrphy_dfi_p0_wrdata[0]}, main_a7ddrphy_bitslip0_r2[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value3 <= (main_a7ddrphy_bitslip0_value3 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value3 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value3 <= 3'd7; end - a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1); + main_a7ddrphy_bitslip0_r3 <= {main_a7ddrphy_bitslip03, main_a7ddrphy_bitslip0_r3[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value2 <= (main_a7ddrphy_bitslip1_value2 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value2 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value2 <= 3'd7; end - a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1); + main_a7ddrphy_bitslip1_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[17], main_a7ddrphy_dfi_p3_wrdata[1], main_a7ddrphy_dfi_p2_wrdata[17], main_a7ddrphy_dfi_p2_wrdata[1], main_a7ddrphy_dfi_p1_wrdata[17], main_a7ddrphy_dfi_p1_wrdata[1], main_a7ddrphy_dfi_p0_wrdata[17], main_a7ddrphy_dfi_p0_wrdata[1]}, main_a7ddrphy_bitslip1_r2[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value3 <= (main_a7ddrphy_bitslip1_value3 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value3 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value3 <= 3'd7; end - a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1); + main_a7ddrphy_bitslip1_r3 <= {main_a7ddrphy_bitslip13, main_a7ddrphy_bitslip1_r3[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip2_value0 <= (main_a7ddrphy_bitslip2_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip2_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip2_value0 <= 3'd7; end - a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1); + main_a7ddrphy_bitslip2_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[18], main_a7ddrphy_dfi_p3_wrdata[2], main_a7ddrphy_dfi_p2_wrdata[18], main_a7ddrphy_dfi_p2_wrdata[2], main_a7ddrphy_dfi_p1_wrdata[18], main_a7ddrphy_dfi_p1_wrdata[2], main_a7ddrphy_dfi_p0_wrdata[18], main_a7ddrphy_dfi_p0_wrdata[2]}, main_a7ddrphy_bitslip2_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip2_value1 <= (main_a7ddrphy_bitslip2_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip2_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip2_value1 <= 3'd7; end - a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1); + main_a7ddrphy_bitslip2_r1 <= {main_a7ddrphy_bitslip21, main_a7ddrphy_bitslip2_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip3_value0 <= (main_a7ddrphy_bitslip3_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip3_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip3_value0 <= 3'd7; end - a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1); + main_a7ddrphy_bitslip3_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[19], main_a7ddrphy_dfi_p3_wrdata[3], main_a7ddrphy_dfi_p2_wrdata[19], main_a7ddrphy_dfi_p2_wrdata[3], main_a7ddrphy_dfi_p1_wrdata[19], main_a7ddrphy_dfi_p1_wrdata[3], main_a7ddrphy_dfi_p0_wrdata[19], main_a7ddrphy_dfi_p0_wrdata[3]}, main_a7ddrphy_bitslip3_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip3_value1 <= (main_a7ddrphy_bitslip3_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip3_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip3_value1 <= 3'd7; end - a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1); + main_a7ddrphy_bitslip3_r1 <= {main_a7ddrphy_bitslip31, main_a7ddrphy_bitslip3_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip4_value0 <= (main_a7ddrphy_bitslip4_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip4_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip4_value0 <= 3'd7; end - a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1); + main_a7ddrphy_bitslip4_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[20], main_a7ddrphy_dfi_p3_wrdata[4], main_a7ddrphy_dfi_p2_wrdata[20], main_a7ddrphy_dfi_p2_wrdata[4], main_a7ddrphy_dfi_p1_wrdata[20], main_a7ddrphy_dfi_p1_wrdata[4], main_a7ddrphy_dfi_p0_wrdata[20], main_a7ddrphy_dfi_p0_wrdata[4]}, main_a7ddrphy_bitslip4_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip4_value1 <= (main_a7ddrphy_bitslip4_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip4_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip4_value1 <= 3'd7; end - a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1); + main_a7ddrphy_bitslip4_r1 <= {main_a7ddrphy_bitslip41, main_a7ddrphy_bitslip4_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip5_value0 <= (main_a7ddrphy_bitslip5_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip5_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip5_value0 <= 3'd7; end - a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1); + main_a7ddrphy_bitslip5_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[21], main_a7ddrphy_dfi_p3_wrdata[5], main_a7ddrphy_dfi_p2_wrdata[21], main_a7ddrphy_dfi_p2_wrdata[5], main_a7ddrphy_dfi_p1_wrdata[21], main_a7ddrphy_dfi_p1_wrdata[5], main_a7ddrphy_dfi_p0_wrdata[21], main_a7ddrphy_dfi_p0_wrdata[5]}, main_a7ddrphy_bitslip5_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip5_value1 <= (main_a7ddrphy_bitslip5_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip5_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip5_value1 <= 3'd7; end - a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1); + main_a7ddrphy_bitslip5_r1 <= {main_a7ddrphy_bitslip51, main_a7ddrphy_bitslip5_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip6_value0 <= (main_a7ddrphy_bitslip6_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip6_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip6_value0 <= 3'd7; end - a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1); + main_a7ddrphy_bitslip6_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[22], main_a7ddrphy_dfi_p3_wrdata[6], main_a7ddrphy_dfi_p2_wrdata[22], main_a7ddrphy_dfi_p2_wrdata[6], main_a7ddrphy_dfi_p1_wrdata[22], main_a7ddrphy_dfi_p1_wrdata[6], main_a7ddrphy_dfi_p0_wrdata[22], main_a7ddrphy_dfi_p0_wrdata[6]}, main_a7ddrphy_bitslip6_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip6_value1 <= (main_a7ddrphy_bitslip6_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip6_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip6_value1 <= 3'd7; end - a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1); + main_a7ddrphy_bitslip6_r1 <= {main_a7ddrphy_bitslip61, main_a7ddrphy_bitslip6_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip7_value0 <= (main_a7ddrphy_bitslip7_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip7_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip7_value0 <= 3'd7; end - a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1); + main_a7ddrphy_bitslip7_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[23], main_a7ddrphy_dfi_p3_wrdata[7], main_a7ddrphy_dfi_p2_wrdata[23], main_a7ddrphy_dfi_p2_wrdata[7], main_a7ddrphy_dfi_p1_wrdata[23], main_a7ddrphy_dfi_p1_wrdata[7], main_a7ddrphy_dfi_p0_wrdata[23], main_a7ddrphy_dfi_p0_wrdata[7]}, main_a7ddrphy_bitslip7_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip7_value1 <= (main_a7ddrphy_bitslip7_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip7_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip7_value1 <= 3'd7; end - a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1); + main_a7ddrphy_bitslip7_r1 <= {main_a7ddrphy_bitslip71, main_a7ddrphy_bitslip7_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip8_value0 <= (main_a7ddrphy_bitslip8_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip8_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip8_value0 <= 3'd7; end - a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1); + main_a7ddrphy_bitslip8_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[24], main_a7ddrphy_dfi_p3_wrdata[8], main_a7ddrphy_dfi_p2_wrdata[24], main_a7ddrphy_dfi_p2_wrdata[8], main_a7ddrphy_dfi_p1_wrdata[24], main_a7ddrphy_dfi_p1_wrdata[8], main_a7ddrphy_dfi_p0_wrdata[24], main_a7ddrphy_dfi_p0_wrdata[8]}, main_a7ddrphy_bitslip8_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip8_value1 <= (main_a7ddrphy_bitslip8_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip8_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip8_value1 <= 3'd7; end - a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1); + main_a7ddrphy_bitslip8_r1 <= {main_a7ddrphy_bitslip81, main_a7ddrphy_bitslip8_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip9_value0 <= (main_a7ddrphy_bitslip9_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip9_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip9_value0 <= 3'd7; end - a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1); + main_a7ddrphy_bitslip9_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[25], main_a7ddrphy_dfi_p3_wrdata[9], main_a7ddrphy_dfi_p2_wrdata[25], main_a7ddrphy_dfi_p2_wrdata[9], main_a7ddrphy_dfi_p1_wrdata[25], main_a7ddrphy_dfi_p1_wrdata[9], main_a7ddrphy_dfi_p0_wrdata[25], main_a7ddrphy_dfi_p0_wrdata[9]}, main_a7ddrphy_bitslip9_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip9_value1 <= (main_a7ddrphy_bitslip9_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip9_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip9_value1 <= 3'd7; end - a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1); + main_a7ddrphy_bitslip9_r1 <= {main_a7ddrphy_bitslip91, main_a7ddrphy_bitslip9_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip10_value0 <= (main_a7ddrphy_bitslip10_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip10_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip10_value0 <= 3'd7; end - a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1); + main_a7ddrphy_bitslip10_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[26], main_a7ddrphy_dfi_p3_wrdata[10], main_a7ddrphy_dfi_p2_wrdata[26], main_a7ddrphy_dfi_p2_wrdata[10], main_a7ddrphy_dfi_p1_wrdata[26], main_a7ddrphy_dfi_p1_wrdata[10], main_a7ddrphy_dfi_p0_wrdata[26], main_a7ddrphy_dfi_p0_wrdata[10]}, main_a7ddrphy_bitslip10_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip10_value1 <= (main_a7ddrphy_bitslip10_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip10_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip10_value1 <= 3'd7; end - a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1); + main_a7ddrphy_bitslip10_r1 <= {main_a7ddrphy_bitslip101, main_a7ddrphy_bitslip10_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip11_value0 <= (main_a7ddrphy_bitslip11_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip11_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip11_value0 <= 3'd7; end - a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1); + main_a7ddrphy_bitslip11_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[27], main_a7ddrphy_dfi_p3_wrdata[11], main_a7ddrphy_dfi_p2_wrdata[27], main_a7ddrphy_dfi_p2_wrdata[11], main_a7ddrphy_dfi_p1_wrdata[27], main_a7ddrphy_dfi_p1_wrdata[11], main_a7ddrphy_dfi_p0_wrdata[27], main_a7ddrphy_dfi_p0_wrdata[11]}, main_a7ddrphy_bitslip11_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip11_value1 <= (main_a7ddrphy_bitslip11_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip11_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip11_value1 <= 3'd7; end - a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1); + main_a7ddrphy_bitslip11_r1 <= {main_a7ddrphy_bitslip111, main_a7ddrphy_bitslip11_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip12_value0 <= (main_a7ddrphy_bitslip12_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip12_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip12_value0 <= 3'd7; end - a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1); + main_a7ddrphy_bitslip12_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[28], main_a7ddrphy_dfi_p3_wrdata[12], main_a7ddrphy_dfi_p2_wrdata[28], main_a7ddrphy_dfi_p2_wrdata[12], main_a7ddrphy_dfi_p1_wrdata[28], main_a7ddrphy_dfi_p1_wrdata[12], main_a7ddrphy_dfi_p0_wrdata[28], main_a7ddrphy_dfi_p0_wrdata[12]}, main_a7ddrphy_bitslip12_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip12_value1 <= (main_a7ddrphy_bitslip12_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip12_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip12_value1 <= 3'd7; end - a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1); + main_a7ddrphy_bitslip12_r1 <= {main_a7ddrphy_bitslip121, main_a7ddrphy_bitslip12_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip13_value0 <= (main_a7ddrphy_bitslip13_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip13_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip13_value0 <= 3'd7; end - a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1); + main_a7ddrphy_bitslip13_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[29], main_a7ddrphy_dfi_p3_wrdata[13], main_a7ddrphy_dfi_p2_wrdata[29], main_a7ddrphy_dfi_p2_wrdata[13], main_a7ddrphy_dfi_p1_wrdata[29], main_a7ddrphy_dfi_p1_wrdata[13], main_a7ddrphy_dfi_p0_wrdata[29], main_a7ddrphy_dfi_p0_wrdata[13]}, main_a7ddrphy_bitslip13_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip13_value1 <= (main_a7ddrphy_bitslip13_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip13_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip13_value1 <= 3'd7; end - a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1); + main_a7ddrphy_bitslip13_r1 <= {main_a7ddrphy_bitslip131, main_a7ddrphy_bitslip13_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip14_value0 <= (main_a7ddrphy_bitslip14_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip14_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip14_value0 <= 3'd7; end - a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1); + main_a7ddrphy_bitslip14_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[30], main_a7ddrphy_dfi_p3_wrdata[14], main_a7ddrphy_dfi_p2_wrdata[30], main_a7ddrphy_dfi_p2_wrdata[14], main_a7ddrphy_dfi_p1_wrdata[30], main_a7ddrphy_dfi_p1_wrdata[14], main_a7ddrphy_dfi_p0_wrdata[30], main_a7ddrphy_dfi_p0_wrdata[14]}, main_a7ddrphy_bitslip14_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip14_value1 <= (main_a7ddrphy_bitslip14_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip14_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip14_value1 <= 3'd7; end - a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1); + main_a7ddrphy_bitslip14_r1 <= {main_a7ddrphy_bitslip141, main_a7ddrphy_bitslip14_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip15_value0 <= (main_a7ddrphy_bitslip15_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip15_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip15_value0 <= 3'd7; end - a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1); + main_a7ddrphy_bitslip15_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[31], main_a7ddrphy_dfi_p3_wrdata[15], main_a7ddrphy_dfi_p2_wrdata[31], main_a7ddrphy_dfi_p2_wrdata[15], main_a7ddrphy_dfi_p1_wrdata[31], main_a7ddrphy_dfi_p1_wrdata[15], main_a7ddrphy_dfi_p0_wrdata[31], main_a7ddrphy_dfi_p0_wrdata[15]}, main_a7ddrphy_bitslip15_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip15_value1 <= (main_a7ddrphy_bitslip15_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip15_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip15_value1 <= 3'd7; end - a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]}; - a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en); - a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0; - a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1; - a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2; - a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3; - a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4; - a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5; - a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6; - a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en); - a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0; - a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1; - if (litedramcore_csr_dfi_p0_rddata_valid) begin - litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata; + main_a7ddrphy_bitslip15_r1 <= {main_a7ddrphy_bitslip151, main_a7ddrphy_bitslip15_r1[15:8]}; + main_a7ddrphy_rddata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_rddata_en | main_a7ddrphy_dfi_p1_rddata_en) | main_a7ddrphy_dfi_p2_rddata_en) | main_a7ddrphy_dfi_p3_rddata_en); + main_a7ddrphy_rddata_en_tappeddelayline1 <= main_a7ddrphy_rddata_en_tappeddelayline0; + main_a7ddrphy_rddata_en_tappeddelayline2 <= main_a7ddrphy_rddata_en_tappeddelayline1; + main_a7ddrphy_rddata_en_tappeddelayline3 <= main_a7ddrphy_rddata_en_tappeddelayline2; + main_a7ddrphy_rddata_en_tappeddelayline4 <= main_a7ddrphy_rddata_en_tappeddelayline3; + main_a7ddrphy_rddata_en_tappeddelayline5 <= main_a7ddrphy_rddata_en_tappeddelayline4; + main_a7ddrphy_rddata_en_tappeddelayline6 <= main_a7ddrphy_rddata_en_tappeddelayline5; + main_a7ddrphy_rddata_en_tappeddelayline7 <= main_a7ddrphy_rddata_en_tappeddelayline6; + main_a7ddrphy_wrdata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_wrdata_en | main_a7ddrphy_dfi_p1_wrdata_en) | main_a7ddrphy_dfi_p2_wrdata_en) | main_a7ddrphy_dfi_p3_wrdata_en); + main_a7ddrphy_wrdata_en_tappeddelayline1 <= main_a7ddrphy_wrdata_en_tappeddelayline0; + main_a7ddrphy_wrdata_en_tappeddelayline2 <= main_a7ddrphy_wrdata_en_tappeddelayline1; + if (main_litedramcore_csr_dfi_p0_rddata_valid) begin + main_litedramcore_phaseinjector0_rddata_status <= main_litedramcore_csr_dfi_p0_rddata; end - if (litedramcore_csr_dfi_p1_rddata_valid) begin - litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata; + if (main_litedramcore_csr_dfi_p1_rddata_valid) begin + main_litedramcore_phaseinjector1_rddata_status <= main_litedramcore_csr_dfi_p1_rddata; end - if (litedramcore_csr_dfi_p2_rddata_valid) begin - litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata; + if (main_litedramcore_csr_dfi_p2_rddata_valid) begin + main_litedramcore_phaseinjector2_rddata_status <= main_litedramcore_csr_dfi_p2_rddata; end - if (litedramcore_csr_dfi_p3_rddata_valid) begin - litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata; + if (main_litedramcore_csr_dfi_p3_rddata_valid) begin + main_litedramcore_phaseinjector3_rddata_status <= main_litedramcore_csr_dfi_p3_rddata; end - if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin - litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); + if ((main_litedramcore_timer_wait & (~main_litedramcore_timer_done0))) begin + main_litedramcore_timer_count1 <= (main_litedramcore_timer_count1 - 1'd1); end else begin - litedramcore_timer_count1 <= 10'd781; + main_litedramcore_timer_count1 <= 10'd781; end - litedramcore_postponer_req_o <= 1'd0; - if (litedramcore_postponer_req_i) begin - litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); - if ((litedramcore_postponer_count == 1'd0)) begin - litedramcore_postponer_count <= 1'd0; - litedramcore_postponer_req_o <= 1'd1; + main_litedramcore_postponer_req_o <= 1'd0; + if (main_litedramcore_postponer_req_i) begin + main_litedramcore_postponer_count <= (main_litedramcore_postponer_count - 1'd1); + if ((main_litedramcore_postponer_count == 1'd0)) begin + main_litedramcore_postponer_count <= 1'd0; + main_litedramcore_postponer_req_o <= 1'd1; end end - if (litedramcore_sequencer_start0) begin - litedramcore_sequencer_count <= 1'd0; + if (main_litedramcore_sequencer_start0) begin + main_litedramcore_sequencer_count <= 1'd0; end else begin - if (litedramcore_sequencer_done1) begin - if ((litedramcore_sequencer_count != 1'd0)) begin - litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); - end - end - end - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_sequencer_done1 <= 1'd0; - if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_sequencer_counter == 2'd3)) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd1; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd0; - end - if ((litedramcore_sequencer_counter == 7'd73)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_sequencer_done1 <= 1'd1; - end - if ((litedramcore_sequencer_counter == 7'd73)) begin - litedramcore_sequencer_counter <= 1'd0; + if (main_litedramcore_sequencer_done1) begin + if ((main_litedramcore_sequencer_count != 1'd0)) begin + main_litedramcore_sequencer_count <= (main_litedramcore_sequencer_count - 1'd1); + end + end + end + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd0; + if ((main_litedramcore_sequencer_start1 & (main_litedramcore_sequencer_trigger == 1'd0))) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_sequencer_trigger == 2'd3)) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd1; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd0; + end + if ((main_litedramcore_sequencer_trigger == 7'd73)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd1; + end + if ((main_litedramcore_sequencer_trigger == 7'd73)) begin + main_litedramcore_sequencer_trigger <= 1'd0; end else begin - if ((litedramcore_sequencer_counter != 1'd0)) begin - litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1); + if ((main_litedramcore_sequencer_trigger != 1'd0)) begin + main_litedramcore_sequencer_trigger <= (main_litedramcore_sequencer_trigger + 1'd1); end else begin - if (litedramcore_sequencer_start1) begin - litedramcore_sequencer_counter <= 1'd1; + if (main_litedramcore_sequencer_start1) begin + main_litedramcore_sequencer_trigger <= 1'd1; end end end - if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin - litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); + if ((main_litedramcore_zqcs_timer_wait & (~main_litedramcore_zqcs_timer_done0))) begin + main_litedramcore_zqcs_timer_count1 <= (main_litedramcore_zqcs_timer_count1 - 1'd1); end else begin - litedramcore_zqcs_timer_count1 <= 27'd99999999; - end - litedramcore_zqcs_executer_done <= 1'd0; - if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 2'd3)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 5'd19)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_zqcs_executer_done <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 5'd19)) begin - litedramcore_zqcs_executer_counter <= 1'd0; + main_litedramcore_zqcs_timer_count1 <= 27'd99999999; + end + main_litedramcore_zqcs_executer_done <= 1'd0; + if ((main_litedramcore_zqcs_executer_start & (main_litedramcore_zqcs_executer_trigger == 1'd0))) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_trigger == 2'd3)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_trigger == 5'd19)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_zqcs_executer_done <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_trigger == 5'd19)) begin + main_litedramcore_zqcs_executer_trigger <= 1'd0; end else begin - if ((litedramcore_zqcs_executer_counter != 1'd0)) begin - litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1); + if ((main_litedramcore_zqcs_executer_trigger != 1'd0)) begin + main_litedramcore_zqcs_executer_trigger <= (main_litedramcore_zqcs_executer_trigger + 1'd1); end else begin - if (litedramcore_zqcs_executer_start) begin - litedramcore_zqcs_executer_counter <= 1'd1; + if (main_litedramcore_zqcs_executer_start) begin + main_litedramcore_zqcs_executer_trigger <= 1'd1; end end end - litedramcore_refresher_state <= litedramcore_refresher_next_state; - if (litedramcore_bankmachine0_row_close) begin - litedramcore_bankmachine0_row_opened <= 1'd0; + builder_refresher_state <= builder_refresher_next_state; + if (main_litedramcore_bankmachine0_row_close) begin + main_litedramcore_bankmachine0_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine0_row_open) begin - litedramcore_bankmachine0_row_opened <= 1'd1; - litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[22:7]; + if (main_litedramcore_bankmachine0_row_open) begin + main_litedramcore_bankmachine0_row_opened <= 1'd1; + main_litedramcore_bankmachine0_row <= main_litedramcore_bankmachine0_source_source_payload_addr[22:7]; end end - if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin - litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1); + if (((main_litedramcore_bankmachine0_syncfifo0_we & main_litedramcore_bankmachine0_syncfifo0_writable) & (~main_litedramcore_bankmachine0_replace))) begin + main_litedramcore_bankmachine0_produce <= (main_litedramcore_bankmachine0_produce + 1'd1); end - if (litedramcore_bankmachine0_do_read) begin - litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1); + if (main_litedramcore_bankmachine0_do_read) begin + main_litedramcore_bankmachine0_consume <= (main_litedramcore_bankmachine0_consume + 1'd1); end - if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin - if ((~litedramcore_bankmachine0_do_read)) begin - litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1); + if (((main_litedramcore_bankmachine0_syncfifo0_we & main_litedramcore_bankmachine0_syncfifo0_writable) & (~main_litedramcore_bankmachine0_replace))) begin + if ((~main_litedramcore_bankmachine0_do_read)) begin + main_litedramcore_bankmachine0_level <= (main_litedramcore_bankmachine0_level + 1'd1); end end else begin - if (litedramcore_bankmachine0_do_read) begin - litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1); + if (main_litedramcore_bankmachine0_do_read) begin + main_litedramcore_bankmachine0_level <= (main_litedramcore_bankmachine0_level - 1'd1); end end - if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin - litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid; - litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first; - litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last; - litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we; - litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine0_pipe_valid_source_valid) | main_litedramcore_bankmachine0_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine0_pipe_valid_source_valid <= main_litedramcore_bankmachine0_pipe_valid_sink_valid; + main_litedramcore_bankmachine0_pipe_valid_source_first <= main_litedramcore_bankmachine0_pipe_valid_sink_first; + main_litedramcore_bankmachine0_pipe_valid_source_last <= main_litedramcore_bankmachine0_pipe_valid_sink_last; + main_litedramcore_bankmachine0_pipe_valid_source_payload_we <= main_litedramcore_bankmachine0_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine0_twtpcon_valid) begin - litedramcore_bankmachine0_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine0_twtpcon_valid) begin + main_litedramcore_bankmachine0_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine0_twtpcon_ready)) begin - litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_twtpcon_ready)) begin + main_litedramcore_bankmachine0_twtpcon_count <= (main_litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine0_trccon_valid) begin - litedramcore_bankmachine0_trccon_count <= 3'd6; + if (main_litedramcore_bankmachine0_trccon_valid) begin + main_litedramcore_bankmachine0_trccon_count <= 3'd6; if (1'd0) begin - litedramcore_bankmachine0_trccon_ready <= 1'd1; + main_litedramcore_bankmachine0_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine0_trccon_ready <= 1'd0; + main_litedramcore_bankmachine0_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine0_trccon_ready)) begin - litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); - if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin - litedramcore_bankmachine0_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_trccon_ready)) begin + main_litedramcore_bankmachine0_trccon_count <= (main_litedramcore_bankmachine0_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine0_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine0_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine0_trascon_valid) begin - litedramcore_bankmachine0_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine0_trascon_valid) begin + main_litedramcore_bankmachine0_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine0_trascon_ready <= 1'd1; + main_litedramcore_bankmachine0_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine0_trascon_ready <= 1'd0; + main_litedramcore_bankmachine0_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); - if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin - litedramcore_bankmachine0_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_trascon_count <= (main_litedramcore_bankmachine0_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine0_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine0_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state; - if (litedramcore_bankmachine1_row_close) begin - litedramcore_bankmachine1_row_opened <= 1'd0; + builder_bankmachine0_state <= builder_bankmachine0_next_state; + if (main_litedramcore_bankmachine1_row_close) begin + main_litedramcore_bankmachine1_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine1_row_open) begin - litedramcore_bankmachine1_row_opened <= 1'd1; - litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[22:7]; + if (main_litedramcore_bankmachine1_row_open) begin + main_litedramcore_bankmachine1_row_opened <= 1'd1; + main_litedramcore_bankmachine1_row <= main_litedramcore_bankmachine1_source_source_payload_addr[22:7]; end end - if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin - litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1); + if (((main_litedramcore_bankmachine1_syncfifo1_we & main_litedramcore_bankmachine1_syncfifo1_writable) & (~main_litedramcore_bankmachine1_replace))) begin + main_litedramcore_bankmachine1_produce <= (main_litedramcore_bankmachine1_produce + 1'd1); end - if (litedramcore_bankmachine1_do_read) begin - litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1); + if (main_litedramcore_bankmachine1_do_read) begin + main_litedramcore_bankmachine1_consume <= (main_litedramcore_bankmachine1_consume + 1'd1); end - if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin - if ((~litedramcore_bankmachine1_do_read)) begin - litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1); + if (((main_litedramcore_bankmachine1_syncfifo1_we & main_litedramcore_bankmachine1_syncfifo1_writable) & (~main_litedramcore_bankmachine1_replace))) begin + if ((~main_litedramcore_bankmachine1_do_read)) begin + main_litedramcore_bankmachine1_level <= (main_litedramcore_bankmachine1_level + 1'd1); end end else begin - if (litedramcore_bankmachine1_do_read) begin - litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1); + if (main_litedramcore_bankmachine1_do_read) begin + main_litedramcore_bankmachine1_level <= (main_litedramcore_bankmachine1_level - 1'd1); end end - if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin - litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid; - litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first; - litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last; - litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we; - litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine1_pipe_valid_source_valid) | main_litedramcore_bankmachine1_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine1_pipe_valid_source_valid <= main_litedramcore_bankmachine1_pipe_valid_sink_valid; + main_litedramcore_bankmachine1_pipe_valid_source_first <= main_litedramcore_bankmachine1_pipe_valid_sink_first; + main_litedramcore_bankmachine1_pipe_valid_source_last <= main_litedramcore_bankmachine1_pipe_valid_sink_last; + main_litedramcore_bankmachine1_pipe_valid_source_payload_we <= main_litedramcore_bankmachine1_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine1_twtpcon_valid) begin - litedramcore_bankmachine1_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine1_twtpcon_valid) begin + main_litedramcore_bankmachine1_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine1_twtpcon_ready)) begin - litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_twtpcon_ready)) begin + main_litedramcore_bankmachine1_twtpcon_count <= (main_litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine1_trccon_valid) begin - litedramcore_bankmachine1_trccon_count <= 3'd6; + if (main_litedramcore_bankmachine1_trccon_valid) begin + main_litedramcore_bankmachine1_trccon_count <= 3'd6; if (1'd0) begin - litedramcore_bankmachine1_trccon_ready <= 1'd1; + main_litedramcore_bankmachine1_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine1_trccon_ready <= 1'd0; + main_litedramcore_bankmachine1_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine1_trccon_ready)) begin - litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); - if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin - litedramcore_bankmachine1_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_trccon_ready)) begin + main_litedramcore_bankmachine1_trccon_count <= (main_litedramcore_bankmachine1_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine1_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine1_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine1_trascon_valid) begin - litedramcore_bankmachine1_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine1_trascon_valid) begin + main_litedramcore_bankmachine1_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine1_trascon_ready <= 1'd1; + main_litedramcore_bankmachine1_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine1_trascon_ready <= 1'd0; + main_litedramcore_bankmachine1_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); - if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin - litedramcore_bankmachine1_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_trascon_count <= (main_litedramcore_bankmachine1_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine1_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine1_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state; - if (litedramcore_bankmachine2_row_close) begin - litedramcore_bankmachine2_row_opened <= 1'd0; + builder_bankmachine1_state <= builder_bankmachine1_next_state; + if (main_litedramcore_bankmachine2_row_close) begin + main_litedramcore_bankmachine2_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine2_row_open) begin - litedramcore_bankmachine2_row_opened <= 1'd1; - litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[22:7]; + if (main_litedramcore_bankmachine2_row_open) begin + main_litedramcore_bankmachine2_row_opened <= 1'd1; + main_litedramcore_bankmachine2_row <= main_litedramcore_bankmachine2_source_source_payload_addr[22:7]; end end - if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin - litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1); + if (((main_litedramcore_bankmachine2_syncfifo2_we & main_litedramcore_bankmachine2_syncfifo2_writable) & (~main_litedramcore_bankmachine2_replace))) begin + main_litedramcore_bankmachine2_produce <= (main_litedramcore_bankmachine2_produce + 1'd1); end - if (litedramcore_bankmachine2_do_read) begin - litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1); + if (main_litedramcore_bankmachine2_do_read) begin + main_litedramcore_bankmachine2_consume <= (main_litedramcore_bankmachine2_consume + 1'd1); end - if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin - if ((~litedramcore_bankmachine2_do_read)) begin - litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1); + if (((main_litedramcore_bankmachine2_syncfifo2_we & main_litedramcore_bankmachine2_syncfifo2_writable) & (~main_litedramcore_bankmachine2_replace))) begin + if ((~main_litedramcore_bankmachine2_do_read)) begin + main_litedramcore_bankmachine2_level <= (main_litedramcore_bankmachine2_level + 1'd1); end end else begin - if (litedramcore_bankmachine2_do_read) begin - litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1); + if (main_litedramcore_bankmachine2_do_read) begin + main_litedramcore_bankmachine2_level <= (main_litedramcore_bankmachine2_level - 1'd1); end end - if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin - litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid; - litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first; - litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last; - litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we; - litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine2_pipe_valid_source_valid) | main_litedramcore_bankmachine2_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine2_pipe_valid_source_valid <= main_litedramcore_bankmachine2_pipe_valid_sink_valid; + main_litedramcore_bankmachine2_pipe_valid_source_first <= main_litedramcore_bankmachine2_pipe_valid_sink_first; + main_litedramcore_bankmachine2_pipe_valid_source_last <= main_litedramcore_bankmachine2_pipe_valid_sink_last; + main_litedramcore_bankmachine2_pipe_valid_source_payload_we <= main_litedramcore_bankmachine2_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine2_twtpcon_valid) begin - litedramcore_bankmachine2_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine2_twtpcon_valid) begin + main_litedramcore_bankmachine2_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine2_twtpcon_ready)) begin - litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_twtpcon_ready)) begin + main_litedramcore_bankmachine2_twtpcon_count <= (main_litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine2_trccon_valid) begin - litedramcore_bankmachine2_trccon_count <= 3'd6; + if (main_litedramcore_bankmachine2_trccon_valid) begin + main_litedramcore_bankmachine2_trccon_count <= 3'd6; if (1'd0) begin - litedramcore_bankmachine2_trccon_ready <= 1'd1; + main_litedramcore_bankmachine2_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine2_trccon_ready <= 1'd0; + main_litedramcore_bankmachine2_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine2_trccon_ready)) begin - litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); - if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin - litedramcore_bankmachine2_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_trccon_ready)) begin + main_litedramcore_bankmachine2_trccon_count <= (main_litedramcore_bankmachine2_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine2_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine2_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine2_trascon_valid) begin - litedramcore_bankmachine2_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine2_trascon_valid) begin + main_litedramcore_bankmachine2_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine2_trascon_ready <= 1'd1; + main_litedramcore_bankmachine2_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine2_trascon_ready <= 1'd0; + main_litedramcore_bankmachine2_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); - if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin - litedramcore_bankmachine2_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_trascon_count <= (main_litedramcore_bankmachine2_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine2_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine2_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state; - if (litedramcore_bankmachine3_row_close) begin - litedramcore_bankmachine3_row_opened <= 1'd0; + builder_bankmachine2_state <= builder_bankmachine2_next_state; + if (main_litedramcore_bankmachine3_row_close) begin + main_litedramcore_bankmachine3_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine3_row_open) begin - litedramcore_bankmachine3_row_opened <= 1'd1; - litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[22:7]; + if (main_litedramcore_bankmachine3_row_open) begin + main_litedramcore_bankmachine3_row_opened <= 1'd1; + main_litedramcore_bankmachine3_row <= main_litedramcore_bankmachine3_source_source_payload_addr[22:7]; end end - if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin - litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1); + if (((main_litedramcore_bankmachine3_syncfifo3_we & main_litedramcore_bankmachine3_syncfifo3_writable) & (~main_litedramcore_bankmachine3_replace))) begin + main_litedramcore_bankmachine3_produce <= (main_litedramcore_bankmachine3_produce + 1'd1); end - if (litedramcore_bankmachine3_do_read) begin - litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1); + if (main_litedramcore_bankmachine3_do_read) begin + main_litedramcore_bankmachine3_consume <= (main_litedramcore_bankmachine3_consume + 1'd1); end - if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin - if ((~litedramcore_bankmachine3_do_read)) begin - litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1); + if (((main_litedramcore_bankmachine3_syncfifo3_we & main_litedramcore_bankmachine3_syncfifo3_writable) & (~main_litedramcore_bankmachine3_replace))) begin + if ((~main_litedramcore_bankmachine3_do_read)) begin + main_litedramcore_bankmachine3_level <= (main_litedramcore_bankmachine3_level + 1'd1); end end else begin - if (litedramcore_bankmachine3_do_read) begin - litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1); + if (main_litedramcore_bankmachine3_do_read) begin + main_litedramcore_bankmachine3_level <= (main_litedramcore_bankmachine3_level - 1'd1); end end - if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin - litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid; - litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first; - litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last; - litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we; - litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine3_pipe_valid_source_valid) | main_litedramcore_bankmachine3_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine3_pipe_valid_source_valid <= main_litedramcore_bankmachine3_pipe_valid_sink_valid; + main_litedramcore_bankmachine3_pipe_valid_source_first <= main_litedramcore_bankmachine3_pipe_valid_sink_first; + main_litedramcore_bankmachine3_pipe_valid_source_last <= main_litedramcore_bankmachine3_pipe_valid_sink_last; + main_litedramcore_bankmachine3_pipe_valid_source_payload_we <= main_litedramcore_bankmachine3_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine3_twtpcon_valid) begin - litedramcore_bankmachine3_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine3_twtpcon_valid) begin + main_litedramcore_bankmachine3_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine3_twtpcon_ready)) begin - litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_twtpcon_ready)) begin + main_litedramcore_bankmachine3_twtpcon_count <= (main_litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine3_trccon_valid) begin - litedramcore_bankmachine3_trccon_count <= 3'd6; + if (main_litedramcore_bankmachine3_trccon_valid) begin + main_litedramcore_bankmachine3_trccon_count <= 3'd6; if (1'd0) begin - litedramcore_bankmachine3_trccon_ready <= 1'd1; + main_litedramcore_bankmachine3_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine3_trccon_ready <= 1'd0; + main_litedramcore_bankmachine3_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine3_trccon_ready)) begin - litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); - if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin - litedramcore_bankmachine3_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_trccon_ready)) begin + main_litedramcore_bankmachine3_trccon_count <= (main_litedramcore_bankmachine3_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine3_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine3_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine3_trascon_valid) begin - litedramcore_bankmachine3_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine3_trascon_valid) begin + main_litedramcore_bankmachine3_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine3_trascon_ready <= 1'd1; + main_litedramcore_bankmachine3_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine3_trascon_ready <= 1'd0; + main_litedramcore_bankmachine3_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); - if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin - litedramcore_bankmachine3_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_trascon_count <= (main_litedramcore_bankmachine3_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine3_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine3_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state; - if (litedramcore_bankmachine4_row_close) begin - litedramcore_bankmachine4_row_opened <= 1'd0; + builder_bankmachine3_state <= builder_bankmachine3_next_state; + if (main_litedramcore_bankmachine4_row_close) begin + main_litedramcore_bankmachine4_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine4_row_open) begin - litedramcore_bankmachine4_row_opened <= 1'd1; - litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[22:7]; + if (main_litedramcore_bankmachine4_row_open) begin + main_litedramcore_bankmachine4_row_opened <= 1'd1; + main_litedramcore_bankmachine4_row <= main_litedramcore_bankmachine4_source_source_payload_addr[22:7]; end end - if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin - litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1); + if (((main_litedramcore_bankmachine4_syncfifo4_we & main_litedramcore_bankmachine4_syncfifo4_writable) & (~main_litedramcore_bankmachine4_replace))) begin + main_litedramcore_bankmachine4_produce <= (main_litedramcore_bankmachine4_produce + 1'd1); end - if (litedramcore_bankmachine4_do_read) begin - litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1); + if (main_litedramcore_bankmachine4_do_read) begin + main_litedramcore_bankmachine4_consume <= (main_litedramcore_bankmachine4_consume + 1'd1); end - if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin - if ((~litedramcore_bankmachine4_do_read)) begin - litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1); + if (((main_litedramcore_bankmachine4_syncfifo4_we & main_litedramcore_bankmachine4_syncfifo4_writable) & (~main_litedramcore_bankmachine4_replace))) begin + if ((~main_litedramcore_bankmachine4_do_read)) begin + main_litedramcore_bankmachine4_level <= (main_litedramcore_bankmachine4_level + 1'd1); end end else begin - if (litedramcore_bankmachine4_do_read) begin - litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1); + if (main_litedramcore_bankmachine4_do_read) begin + main_litedramcore_bankmachine4_level <= (main_litedramcore_bankmachine4_level - 1'd1); end end - if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin - litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid; - litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first; - litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last; - litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we; - litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine4_pipe_valid_source_valid) | main_litedramcore_bankmachine4_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine4_pipe_valid_source_valid <= main_litedramcore_bankmachine4_pipe_valid_sink_valid; + main_litedramcore_bankmachine4_pipe_valid_source_first <= main_litedramcore_bankmachine4_pipe_valid_sink_first; + main_litedramcore_bankmachine4_pipe_valid_source_last <= main_litedramcore_bankmachine4_pipe_valid_sink_last; + main_litedramcore_bankmachine4_pipe_valid_source_payload_we <= main_litedramcore_bankmachine4_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine4_twtpcon_valid) begin - litedramcore_bankmachine4_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine4_twtpcon_valid) begin + main_litedramcore_bankmachine4_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine4_twtpcon_ready)) begin - litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_twtpcon_ready)) begin + main_litedramcore_bankmachine4_twtpcon_count <= (main_litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine4_trccon_valid) begin - litedramcore_bankmachine4_trccon_count <= 3'd6; + if (main_litedramcore_bankmachine4_trccon_valid) begin + main_litedramcore_bankmachine4_trccon_count <= 3'd6; if (1'd0) begin - litedramcore_bankmachine4_trccon_ready <= 1'd1; + main_litedramcore_bankmachine4_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine4_trccon_ready <= 1'd0; + main_litedramcore_bankmachine4_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine4_trccon_ready)) begin - litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); - if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin - litedramcore_bankmachine4_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_trccon_ready)) begin + main_litedramcore_bankmachine4_trccon_count <= (main_litedramcore_bankmachine4_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine4_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine4_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine4_trascon_valid) begin - litedramcore_bankmachine4_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine4_trascon_valid) begin + main_litedramcore_bankmachine4_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine4_trascon_ready <= 1'd1; + main_litedramcore_bankmachine4_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine4_trascon_ready <= 1'd0; + main_litedramcore_bankmachine4_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); - if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin - litedramcore_bankmachine4_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_trascon_count <= (main_litedramcore_bankmachine4_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine4_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine4_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state; - if (litedramcore_bankmachine5_row_close) begin - litedramcore_bankmachine5_row_opened <= 1'd0; + builder_bankmachine4_state <= builder_bankmachine4_next_state; + if (main_litedramcore_bankmachine5_row_close) begin + main_litedramcore_bankmachine5_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine5_row_open) begin - litedramcore_bankmachine5_row_opened <= 1'd1; - litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[22:7]; + if (main_litedramcore_bankmachine5_row_open) begin + main_litedramcore_bankmachine5_row_opened <= 1'd1; + main_litedramcore_bankmachine5_row <= main_litedramcore_bankmachine5_source_source_payload_addr[22:7]; end end - if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin - litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1); + if (((main_litedramcore_bankmachine5_syncfifo5_we & main_litedramcore_bankmachine5_syncfifo5_writable) & (~main_litedramcore_bankmachine5_replace))) begin + main_litedramcore_bankmachine5_produce <= (main_litedramcore_bankmachine5_produce + 1'd1); end - if (litedramcore_bankmachine5_do_read) begin - litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1); + if (main_litedramcore_bankmachine5_do_read) begin + main_litedramcore_bankmachine5_consume <= (main_litedramcore_bankmachine5_consume + 1'd1); end - if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin - if ((~litedramcore_bankmachine5_do_read)) begin - litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1); + if (((main_litedramcore_bankmachine5_syncfifo5_we & main_litedramcore_bankmachine5_syncfifo5_writable) & (~main_litedramcore_bankmachine5_replace))) begin + if ((~main_litedramcore_bankmachine5_do_read)) begin + main_litedramcore_bankmachine5_level <= (main_litedramcore_bankmachine5_level + 1'd1); end end else begin - if (litedramcore_bankmachine5_do_read) begin - litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1); + if (main_litedramcore_bankmachine5_do_read) begin + main_litedramcore_bankmachine5_level <= (main_litedramcore_bankmachine5_level - 1'd1); end end - if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin - litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid; - litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first; - litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last; - litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we; - litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine5_pipe_valid_source_valid) | main_litedramcore_bankmachine5_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine5_pipe_valid_source_valid <= main_litedramcore_bankmachine5_pipe_valid_sink_valid; + main_litedramcore_bankmachine5_pipe_valid_source_first <= main_litedramcore_bankmachine5_pipe_valid_sink_first; + main_litedramcore_bankmachine5_pipe_valid_source_last <= main_litedramcore_bankmachine5_pipe_valid_sink_last; + main_litedramcore_bankmachine5_pipe_valid_source_payload_we <= main_litedramcore_bankmachine5_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine5_twtpcon_valid) begin - litedramcore_bankmachine5_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine5_twtpcon_valid) begin + main_litedramcore_bankmachine5_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine5_twtpcon_ready)) begin - litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_twtpcon_ready)) begin + main_litedramcore_bankmachine5_twtpcon_count <= (main_litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine5_trccon_valid) begin - litedramcore_bankmachine5_trccon_count <= 3'd6; + if (main_litedramcore_bankmachine5_trccon_valid) begin + main_litedramcore_bankmachine5_trccon_count <= 3'd6; if (1'd0) begin - litedramcore_bankmachine5_trccon_ready <= 1'd1; + main_litedramcore_bankmachine5_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine5_trccon_ready <= 1'd0; + main_litedramcore_bankmachine5_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine5_trccon_ready)) begin - litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); - if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin - litedramcore_bankmachine5_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_trccon_ready)) begin + main_litedramcore_bankmachine5_trccon_count <= (main_litedramcore_bankmachine5_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine5_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine5_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine5_trascon_valid) begin - litedramcore_bankmachine5_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine5_trascon_valid) begin + main_litedramcore_bankmachine5_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine5_trascon_ready <= 1'd1; + main_litedramcore_bankmachine5_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine5_trascon_ready <= 1'd0; + main_litedramcore_bankmachine5_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); - if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin - litedramcore_bankmachine5_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_trascon_count <= (main_litedramcore_bankmachine5_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine5_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine5_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state; - if (litedramcore_bankmachine6_row_close) begin - litedramcore_bankmachine6_row_opened <= 1'd0; + builder_bankmachine5_state <= builder_bankmachine5_next_state; + if (main_litedramcore_bankmachine6_row_close) begin + main_litedramcore_bankmachine6_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine6_row_open) begin - litedramcore_bankmachine6_row_opened <= 1'd1; - litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[22:7]; + if (main_litedramcore_bankmachine6_row_open) begin + main_litedramcore_bankmachine6_row_opened <= 1'd1; + main_litedramcore_bankmachine6_row <= main_litedramcore_bankmachine6_source_source_payload_addr[22:7]; end end - if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin - litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1); + if (((main_litedramcore_bankmachine6_syncfifo6_we & main_litedramcore_bankmachine6_syncfifo6_writable) & (~main_litedramcore_bankmachine6_replace))) begin + main_litedramcore_bankmachine6_produce <= (main_litedramcore_bankmachine6_produce + 1'd1); end - if (litedramcore_bankmachine6_do_read) begin - litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1); + if (main_litedramcore_bankmachine6_do_read) begin + main_litedramcore_bankmachine6_consume <= (main_litedramcore_bankmachine6_consume + 1'd1); end - if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin - if ((~litedramcore_bankmachine6_do_read)) begin - litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1); + if (((main_litedramcore_bankmachine6_syncfifo6_we & main_litedramcore_bankmachine6_syncfifo6_writable) & (~main_litedramcore_bankmachine6_replace))) begin + if ((~main_litedramcore_bankmachine6_do_read)) begin + main_litedramcore_bankmachine6_level <= (main_litedramcore_bankmachine6_level + 1'd1); end end else begin - if (litedramcore_bankmachine6_do_read) begin - litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1); + if (main_litedramcore_bankmachine6_do_read) begin + main_litedramcore_bankmachine6_level <= (main_litedramcore_bankmachine6_level - 1'd1); end end - if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin - litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid; - litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first; - litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last; - litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we; - litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine6_pipe_valid_source_valid) | main_litedramcore_bankmachine6_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine6_pipe_valid_source_valid <= main_litedramcore_bankmachine6_pipe_valid_sink_valid; + main_litedramcore_bankmachine6_pipe_valid_source_first <= main_litedramcore_bankmachine6_pipe_valid_sink_first; + main_litedramcore_bankmachine6_pipe_valid_source_last <= main_litedramcore_bankmachine6_pipe_valid_sink_last; + main_litedramcore_bankmachine6_pipe_valid_source_payload_we <= main_litedramcore_bankmachine6_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine6_twtpcon_valid) begin - litedramcore_bankmachine6_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine6_twtpcon_valid) begin + main_litedramcore_bankmachine6_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine6_twtpcon_ready)) begin - litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_twtpcon_ready)) begin + main_litedramcore_bankmachine6_twtpcon_count <= (main_litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine6_trccon_valid) begin - litedramcore_bankmachine6_trccon_count <= 3'd6; + if (main_litedramcore_bankmachine6_trccon_valid) begin + main_litedramcore_bankmachine6_trccon_count <= 3'd6; if (1'd0) begin - litedramcore_bankmachine6_trccon_ready <= 1'd1; + main_litedramcore_bankmachine6_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine6_trccon_ready <= 1'd0; + main_litedramcore_bankmachine6_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine6_trccon_ready)) begin - litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); - if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin - litedramcore_bankmachine6_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_trccon_ready)) begin + main_litedramcore_bankmachine6_trccon_count <= (main_litedramcore_bankmachine6_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine6_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine6_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine6_trascon_valid) begin - litedramcore_bankmachine6_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine6_trascon_valid) begin + main_litedramcore_bankmachine6_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine6_trascon_ready <= 1'd1; + main_litedramcore_bankmachine6_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine6_trascon_ready <= 1'd0; + main_litedramcore_bankmachine6_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); - if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin - litedramcore_bankmachine6_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_trascon_count <= (main_litedramcore_bankmachine6_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine6_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine6_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state; - if (litedramcore_bankmachine7_row_close) begin - litedramcore_bankmachine7_row_opened <= 1'd0; + builder_bankmachine6_state <= builder_bankmachine6_next_state; + if (main_litedramcore_bankmachine7_row_close) begin + main_litedramcore_bankmachine7_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine7_row_open) begin - litedramcore_bankmachine7_row_opened <= 1'd1; - litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[22:7]; + if (main_litedramcore_bankmachine7_row_open) begin + main_litedramcore_bankmachine7_row_opened <= 1'd1; + main_litedramcore_bankmachine7_row <= main_litedramcore_bankmachine7_source_source_payload_addr[22:7]; end end - if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin - litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1); + if (((main_litedramcore_bankmachine7_syncfifo7_we & main_litedramcore_bankmachine7_syncfifo7_writable) & (~main_litedramcore_bankmachine7_replace))) begin + main_litedramcore_bankmachine7_produce <= (main_litedramcore_bankmachine7_produce + 1'd1); end - if (litedramcore_bankmachine7_do_read) begin - litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1); + if (main_litedramcore_bankmachine7_do_read) begin + main_litedramcore_bankmachine7_consume <= (main_litedramcore_bankmachine7_consume + 1'd1); end - if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin - if ((~litedramcore_bankmachine7_do_read)) begin - litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1); + if (((main_litedramcore_bankmachine7_syncfifo7_we & main_litedramcore_bankmachine7_syncfifo7_writable) & (~main_litedramcore_bankmachine7_replace))) begin + if ((~main_litedramcore_bankmachine7_do_read)) begin + main_litedramcore_bankmachine7_level <= (main_litedramcore_bankmachine7_level + 1'd1); end end else begin - if (litedramcore_bankmachine7_do_read) begin - litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1); + if (main_litedramcore_bankmachine7_do_read) begin + main_litedramcore_bankmachine7_level <= (main_litedramcore_bankmachine7_level - 1'd1); end end - if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin - litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid; - litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first; - litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last; - litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we; - litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine7_pipe_valid_source_valid) | main_litedramcore_bankmachine7_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine7_pipe_valid_source_valid <= main_litedramcore_bankmachine7_pipe_valid_sink_valid; + main_litedramcore_bankmachine7_pipe_valid_source_first <= main_litedramcore_bankmachine7_pipe_valid_sink_first; + main_litedramcore_bankmachine7_pipe_valid_source_last <= main_litedramcore_bankmachine7_pipe_valid_sink_last; + main_litedramcore_bankmachine7_pipe_valid_source_payload_we <= main_litedramcore_bankmachine7_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine7_twtpcon_valid) begin - litedramcore_bankmachine7_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine7_twtpcon_valid) begin + main_litedramcore_bankmachine7_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine7_twtpcon_ready)) begin - litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_twtpcon_ready)) begin + main_litedramcore_bankmachine7_twtpcon_count <= (main_litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine7_trccon_valid) begin - litedramcore_bankmachine7_trccon_count <= 3'd6; + if (main_litedramcore_bankmachine7_trccon_valid) begin + main_litedramcore_bankmachine7_trccon_count <= 3'd6; if (1'd0) begin - litedramcore_bankmachine7_trccon_ready <= 1'd1; + main_litedramcore_bankmachine7_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine7_trccon_ready <= 1'd0; + main_litedramcore_bankmachine7_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine7_trccon_ready)) begin - litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); - if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin - litedramcore_bankmachine7_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_trccon_ready)) begin + main_litedramcore_bankmachine7_trccon_count <= (main_litedramcore_bankmachine7_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine7_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine7_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine7_trascon_valid) begin - litedramcore_bankmachine7_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine7_trascon_valid) begin + main_litedramcore_bankmachine7_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine7_trascon_ready <= 1'd1; + main_litedramcore_bankmachine7_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine7_trascon_ready <= 1'd0; + main_litedramcore_bankmachine7_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); - if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin - litedramcore_bankmachine7_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_trascon_count <= (main_litedramcore_bankmachine7_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine7_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine7_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state; - if ((~litedramcore_en0)) begin - litedramcore_time0 <= 5'd31; + builder_bankmachine7_state <= builder_bankmachine7_next_state; + if ((~main_litedramcore_en0)) begin + main_litedramcore_time0 <= 5'd31; end else begin - if ((~litedramcore_max_time0)) begin - litedramcore_time0 <= (litedramcore_time0 - 1'd1); + if ((~main_litedramcore_max_time0)) begin + main_litedramcore_time0 <= (main_litedramcore_time0 - 1'd1); end end - if ((~litedramcore_en1)) begin - litedramcore_time1 <= 4'd15; + if ((~main_litedramcore_en1)) begin + main_litedramcore_time1 <= 4'd15; end else begin - if ((~litedramcore_max_time1)) begin - litedramcore_time1 <= (litedramcore_time1 - 1'd1); + if ((~main_litedramcore_max_time1)) begin + main_litedramcore_time1 <= (main_litedramcore_time1 - 1'd1); end end - if (litedramcore_choose_cmd_ce) begin - case (litedramcore_choose_cmd_grant) + if (main_litedramcore_choose_cmd_ce) begin + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end end end @@ -13030,26 +13447,26 @@ always @(posedge sys_clk) begin end end 1'd1: begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end end end @@ -13059,26 +13476,26 @@ always @(posedge sys_clk) begin end end 2'd2: begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end end end @@ -13088,26 +13505,26 @@ always @(posedge sys_clk) begin end end 2'd3: begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end end end @@ -13117,26 +13534,26 @@ always @(posedge sys_clk) begin end end 3'd4: begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end end end @@ -13146,26 +13563,26 @@ always @(posedge sys_clk) begin end end 3'd5: begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end end end @@ -13175,26 +13592,26 @@ always @(posedge sys_clk) begin end end 3'd6: begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end end end @@ -13204,26 +13621,26 @@ always @(posedge sys_clk) begin end end 3'd7: begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end end end @@ -13234,29 +13651,29 @@ always @(posedge sys_clk) begin end endcase end - if (litedramcore_choose_req_ce) begin - case (litedramcore_choose_req_grant) + if (main_litedramcore_choose_req_ce) begin + case (main_litedramcore_choose_req_grant) 1'd0: begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end end end @@ -13266,26 +13683,26 @@ always @(posedge sys_clk) begin end end 1'd1: begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end end end @@ -13295,26 +13712,26 @@ always @(posedge sys_clk) begin end end 2'd2: begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end end end @@ -13324,26 +13741,26 @@ always @(posedge sys_clk) begin end end 2'd3: begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end end end @@ -13353,26 +13770,26 @@ always @(posedge sys_clk) begin end end 3'd4: begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end end end @@ -13382,26 +13799,26 @@ always @(posedge sys_clk) begin end end 3'd5: begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end end end @@ -13411,26 +13828,26 @@ always @(posedge sys_clk) begin end end 3'd6: begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end end end @@ -13440,26 +13857,26 @@ always @(posedge sys_clk) begin end end 3'd7: begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end end end @@ -13470,644 +13887,644 @@ always @(posedge sys_clk) begin end endcase end - litedramcore_dfi_p0_cs_n <= 1'd0; - litedramcore_dfi_p0_bank <= array_muxed0; - litedramcore_dfi_p0_address <= array_muxed1; - litedramcore_dfi_p0_cas_n <= (~array_muxed2); - litedramcore_dfi_p0_ras_n <= (~array_muxed3); - litedramcore_dfi_p0_we_n <= (~array_muxed4); - litedramcore_dfi_p0_rddata_en <= array_muxed5; - litedramcore_dfi_p0_wrdata_en <= array_muxed6; - litedramcore_dfi_p1_cs_n <= 1'd0; - litedramcore_dfi_p1_bank <= array_muxed7; - litedramcore_dfi_p1_address <= array_muxed8; - litedramcore_dfi_p1_cas_n <= (~array_muxed9); - litedramcore_dfi_p1_ras_n <= (~array_muxed10); - litedramcore_dfi_p1_we_n <= (~array_muxed11); - litedramcore_dfi_p1_rddata_en <= array_muxed12; - litedramcore_dfi_p1_wrdata_en <= array_muxed13; - litedramcore_dfi_p2_cs_n <= 1'd0; - litedramcore_dfi_p2_bank <= array_muxed14; - litedramcore_dfi_p2_address <= array_muxed15; - litedramcore_dfi_p2_cas_n <= (~array_muxed16); - litedramcore_dfi_p2_ras_n <= (~array_muxed17); - litedramcore_dfi_p2_we_n <= (~array_muxed18); - litedramcore_dfi_p2_rddata_en <= array_muxed19; - litedramcore_dfi_p2_wrdata_en <= array_muxed20; - litedramcore_dfi_p3_cs_n <= 1'd0; - litedramcore_dfi_p3_bank <= array_muxed21; - litedramcore_dfi_p3_address <= array_muxed22; - litedramcore_dfi_p3_cas_n <= (~array_muxed23); - litedramcore_dfi_p3_ras_n <= (~array_muxed24); - litedramcore_dfi_p3_we_n <= (~array_muxed25); - litedramcore_dfi_p3_rddata_en <= array_muxed26; - litedramcore_dfi_p3_wrdata_en <= array_muxed27; - if (litedramcore_trrdcon_valid) begin - litedramcore_trrdcon_count <= 1'd1; + main_litedramcore_dfi_p0_cs_n <= 1'd0; + main_litedramcore_dfi_p0_bank <= builder_self0; + main_litedramcore_dfi_p0_address <= builder_self1; + main_litedramcore_dfi_p0_cas_n <= (~builder_self2); + main_litedramcore_dfi_p0_ras_n <= (~builder_self3); + main_litedramcore_dfi_p0_we_n <= (~builder_self4); + main_litedramcore_dfi_p0_rddata_en <= builder_self5; + main_litedramcore_dfi_p0_wrdata_en <= builder_self6; + main_litedramcore_dfi_p1_cs_n <= 1'd0; + main_litedramcore_dfi_p1_bank <= builder_self7; + main_litedramcore_dfi_p1_address <= builder_self8; + main_litedramcore_dfi_p1_cas_n <= (~builder_self9); + main_litedramcore_dfi_p1_ras_n <= (~builder_self10); + main_litedramcore_dfi_p1_we_n <= (~builder_self11); + main_litedramcore_dfi_p1_rddata_en <= builder_self12; + main_litedramcore_dfi_p1_wrdata_en <= builder_self13; + main_litedramcore_dfi_p2_cs_n <= 1'd0; + main_litedramcore_dfi_p2_bank <= builder_self14; + main_litedramcore_dfi_p2_address <= builder_self15; + main_litedramcore_dfi_p2_cas_n <= (~builder_self16); + main_litedramcore_dfi_p2_ras_n <= (~builder_self17); + main_litedramcore_dfi_p2_we_n <= (~builder_self18); + main_litedramcore_dfi_p2_rddata_en <= builder_self19; + main_litedramcore_dfi_p2_wrdata_en <= builder_self20; + main_litedramcore_dfi_p3_cs_n <= 1'd0; + main_litedramcore_dfi_p3_bank <= builder_self21; + main_litedramcore_dfi_p3_address <= builder_self22; + main_litedramcore_dfi_p3_cas_n <= (~builder_self23); + main_litedramcore_dfi_p3_ras_n <= (~builder_self24); + main_litedramcore_dfi_p3_we_n <= (~builder_self25); + main_litedramcore_dfi_p3_rddata_en <= builder_self26; + main_litedramcore_dfi_p3_wrdata_en <= builder_self27; + if (main_litedramcore_trrdcon_valid) begin + main_litedramcore_trrdcon_count <= 1'd1; if (1'd0) begin - litedramcore_trrdcon_ready <= 1'd1; + main_litedramcore_trrdcon_ready <= 1'd1; end else begin - litedramcore_trrdcon_ready <= 1'd0; + main_litedramcore_trrdcon_ready <= 1'd0; end end else begin - if ((~litedramcore_trrdcon_ready)) begin - litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); - if ((litedramcore_trrdcon_count == 1'd1)) begin - litedramcore_trrdcon_ready <= 1'd1; + if ((~main_litedramcore_trrdcon_ready)) begin + main_litedramcore_trrdcon_count <= (main_litedramcore_trrdcon_count - 1'd1); + if ((main_litedramcore_trrdcon_count == 1'd1)) begin + main_litedramcore_trrdcon_ready <= 1'd1; end end end - litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; - if ((litedramcore_tfawcon_count < 3'd4)) begin - if ((litedramcore_tfawcon_count == 2'd3)) begin - litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); + main_litedramcore_tfawcon_window <= {main_litedramcore_tfawcon_window, main_litedramcore_tfawcon_valid}; + if ((main_litedramcore_tfawcon_count < 3'd4)) begin + if ((main_litedramcore_tfawcon_count == 2'd3)) begin + main_litedramcore_tfawcon_ready <= (~main_litedramcore_tfawcon_valid); end else begin - litedramcore_tfawcon_ready <= 1'd1; + main_litedramcore_tfawcon_ready <= 1'd1; end end - if (litedramcore_tccdcon_valid) begin - litedramcore_tccdcon_count <= 1'd0; + if (main_litedramcore_tccdcon_valid) begin + main_litedramcore_tccdcon_count <= 1'd0; if (1'd1) begin - litedramcore_tccdcon_ready <= 1'd1; + main_litedramcore_tccdcon_ready <= 1'd1; end else begin - litedramcore_tccdcon_ready <= 1'd0; + main_litedramcore_tccdcon_ready <= 1'd0; end end else begin - if ((~litedramcore_tccdcon_ready)) begin - litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); - if ((litedramcore_tccdcon_count == 1'd1)) begin - litedramcore_tccdcon_ready <= 1'd1; + if ((~main_litedramcore_tccdcon_ready)) begin + main_litedramcore_tccdcon_count <= (main_litedramcore_tccdcon_count - 1'd1); + if ((main_litedramcore_tccdcon_count == 1'd1)) begin + main_litedramcore_tccdcon_ready <= 1'd1; end end end - if (litedramcore_twtrcon_valid) begin - litedramcore_twtrcon_count <= 3'd4; + if (main_litedramcore_twtrcon_valid) begin + main_litedramcore_twtrcon_count <= 3'd4; if (1'd0) begin - litedramcore_twtrcon_ready <= 1'd1; + main_litedramcore_twtrcon_ready <= 1'd1; end else begin - litedramcore_twtrcon_ready <= 1'd0; + main_litedramcore_twtrcon_ready <= 1'd0; end end else begin - if ((~litedramcore_twtrcon_ready)) begin - litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); - if ((litedramcore_twtrcon_count == 1'd1)) begin - litedramcore_twtrcon_ready <= 1'd1; - end - end - end - litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state; - litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); - litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0; - litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); - litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0; - litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1; - litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2; - litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3; - litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4; - litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5; - litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6; - litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7; - litedramcore_state <= litedramcore_next_state; - if (litedramcore_dat_w_next_value_ce0) begin - litedramcore_dat_w <= litedramcore_dat_w_next_value0; - end - if (litedramcore_adr_next_value_ce1) begin - litedramcore_adr <= litedramcore_adr_next_value1; - end - if (litedramcore_we_next_value_ce2) begin - litedramcore_we <= litedramcore_we_next_value2; - end - interface0_bank_bus_dat_r <= 1'd0; - if (csrbank0_sel) begin - case (interface0_bank_bus_adr[8:0]) + if ((~main_litedramcore_twtrcon_ready)) begin + main_litedramcore_twtrcon_count <= (main_litedramcore_twtrcon_count - 1'd1); + if ((main_litedramcore_twtrcon_count == 1'd1)) begin + main_litedramcore_twtrcon_ready <= 1'd1; + end + end + end + builder_multiplexer_state <= builder_multiplexer_next_state; + builder_new_master_wdata_ready0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_wdata_ready)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_wdata_ready)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_wdata_ready)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_wdata_ready)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_wdata_ready)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_wdata_ready)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_wdata_ready)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_wdata_ready)); + builder_new_master_wdata_ready1 <= builder_new_master_wdata_ready0; + builder_new_master_rdata_valid0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_rdata_valid)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_rdata_valid)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_rdata_valid)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_rdata_valid)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_rdata_valid)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_rdata_valid)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_rdata_valid)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_rdata_valid)); + builder_new_master_rdata_valid1 <= builder_new_master_rdata_valid0; + builder_new_master_rdata_valid2 <= builder_new_master_rdata_valid1; + builder_new_master_rdata_valid3 <= builder_new_master_rdata_valid2; + builder_new_master_rdata_valid4 <= builder_new_master_rdata_valid3; + builder_new_master_rdata_valid5 <= builder_new_master_rdata_valid4; + builder_new_master_rdata_valid6 <= builder_new_master_rdata_valid5; + builder_new_master_rdata_valid7 <= builder_new_master_rdata_valid6; + builder_new_master_rdata_valid8 <= builder_new_master_rdata_valid7; + builder_state <= builder_next_state; + if (builder_interface1_dat_w_next_value_ce0) begin + builder_interface1_dat_w <= builder_interface1_dat_w_next_value0; + end + if (builder_interface1_adr_next_value_ce1) begin + builder_interface1_adr <= builder_interface1_adr_next_value1; + end + if (builder_interface1_we_next_value_ce2) begin + builder_interface1_we <= builder_interface1_we_next_value2; + end + builder_interface0_bank_bus_dat_r <= 1'd0; + if (builder_csrbank0_sel) begin + case (builder_interface0_bank_bus_adr[8:0]) 1'd0: begin - interface0_bank_bus_dat_r <= csrbank0_init_done0_w; + builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_done0_w; end 1'd1: begin - interface0_bank_bus_dat_r <= csrbank0_init_error0_w; + builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_error0_w; end endcase end - if (csrbank0_init_done0_re) begin - init_done_storage <= csrbank0_init_done0_r; + if (builder_csrbank0_init_done0_re) begin + main_init_done_storage <= builder_csrbank0_init_done0_r; end - init_done_re <= csrbank0_init_done0_re; - if (csrbank0_init_error0_re) begin - init_error_storage <= csrbank0_init_error0_r; + main_init_done_re <= builder_csrbank0_init_done0_re; + if (builder_csrbank0_init_error0_re) begin + main_init_error_storage <= builder_csrbank0_init_error0_r; end - init_error_re <= csrbank0_init_error0_re; - interface1_bank_bus_dat_r <= 1'd0; - if (csrbank1_sel) begin - case (interface1_bank_bus_adr[8:0]) + main_init_error_re <= builder_csrbank0_init_error0_re; + builder_interface1_bank_bus_dat_r <= 1'd0; + if (builder_csrbank1_sel) begin + case (builder_interface1_bank_bus_adr[8:0]) 1'd0: begin - interface1_bank_bus_dat_r <= csrbank1_rst0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rst0_w; end 1'd1: begin - interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_dly_sel0_w; end 2'd2: begin - interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_half_sys8x_taps0_w; end 2'd3: begin - interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_wlevel_en0_w; end 3'd4: begin - interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wlevel_strobe_w; end 3'd5: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_rst_w; end 3'd6: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_inc_w; end 3'd7: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_rst_w; end 4'd8: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_w; end 4'd9: begin - interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_rst_w; end 4'd10: begin - interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_w; end 4'd11: begin - interface1_bank_bus_dat_r <= csrbank1_rdphase0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rdphase0_w; end 4'd12: begin - interface1_bank_bus_dat_r <= csrbank1_wrphase0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_wrphase0_w; end endcase end - if (csrbank1_rst0_re) begin - a7ddrphy_rst_storage <= csrbank1_rst0_r; + if (builder_csrbank1_rst0_re) begin + main_a7ddrphy_rst_storage <= builder_csrbank1_rst0_r; end - a7ddrphy_rst_re <= csrbank1_rst0_re; - if (csrbank1_dly_sel0_re) begin - a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r; + main_a7ddrphy_rst_re <= builder_csrbank1_rst0_re; + if (builder_csrbank1_dly_sel0_re) begin + main_a7ddrphy_dly_sel_storage[1:0] <= builder_csrbank1_dly_sel0_r; end - a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; - if (csrbank1_half_sys8x_taps0_re) begin - a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r; + main_a7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re; + if (builder_csrbank1_half_sys8x_taps0_re) begin + main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r; end - a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re; - if (csrbank1_wlevel_en0_re) begin - a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r; + main_a7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re; + if (builder_csrbank1_wlevel_en0_re) begin + main_a7ddrphy_wlevel_en_storage <= builder_csrbank1_wlevel_en0_r; end - a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re; - if (csrbank1_rdphase0_re) begin - a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r; + main_a7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re; + if (builder_csrbank1_rdphase0_re) begin + main_a7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r; end - a7ddrphy_rdphase_re <= csrbank1_rdphase0_re; - if (csrbank1_wrphase0_re) begin - a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r; + main_a7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re; + if (builder_csrbank1_wrphase0_re) begin + main_a7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r; end - a7ddrphy_wrphase_re <= csrbank1_wrphase0_re; - interface2_bank_bus_dat_r <= 1'd0; - if (csrbank2_sel) begin - case (interface2_bank_bus_adr[8:0]) + main_a7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re; + builder_interface2_bank_bus_dat_r <= 1'd0; + if (builder_csrbank2_sel) begin + case (builder_interface2_bank_bus_adr[8:0]) 1'd0: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_control0_w; end 1'd1: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_command0_w; end 2'd2: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w; end 3'd4: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w; end 3'd5: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w; end 3'd6: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata_w; end 3'd7: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w; end 4'd8: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w; end 4'd9: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w; end 4'd10: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w; end 4'd11: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w; end 4'd12: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata_w; end 4'd13: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w; end 4'd14: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w; end 4'd15: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w; end 5'd16: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w; end 5'd17: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w; end 5'd18: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata_w; end 5'd19: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w; end 5'd20: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w; end 5'd21: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w; end 5'd22: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w; end 5'd23: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w; end 5'd24: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata_w; end endcase end - if (csrbank2_dfii_control0_re) begin - litedramcore_storage[3:0] <= csrbank2_dfii_control0_r; + if (builder_csrbank2_dfii_control0_re) begin + main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r; end - litedramcore_re <= csrbank2_dfii_control0_re; - if (csrbank2_dfii_pi0_command0_re) begin - litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; + main_litedramcore_re <= builder_csrbank2_dfii_control0_re; + if (builder_csrbank2_dfii_pi0_command0_re) begin + main_litedramcore_phaseinjector0_command_storage[7:0] <= builder_csrbank2_dfii_pi0_command0_r; end - litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; - if (csrbank2_dfii_pi0_address0_re) begin - litedramcore_phaseinjector0_address_storage[15:0] <= csrbank2_dfii_pi0_address0_r; + main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re; + if (builder_csrbank2_dfii_pi0_address0_re) begin + main_litedramcore_phaseinjector0_address_storage[15:0] <= builder_csrbank2_dfii_pi0_address0_r; end - litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; - if (csrbank2_dfii_pi0_baddress0_re) begin - litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; + main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re; + if (builder_csrbank2_dfii_pi0_baddress0_re) begin + main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r; end - litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; - if (csrbank2_dfii_pi0_wrdata0_re) begin - litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; + main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re; + if (builder_csrbank2_dfii_pi0_wrdata0_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r; end - litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; - litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re; - if (csrbank2_dfii_pi1_command0_re) begin - litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; + main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re; + main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re; + if (builder_csrbank2_dfii_pi1_command0_re) begin + main_litedramcore_phaseinjector1_command_storage[7:0] <= builder_csrbank2_dfii_pi1_command0_r; end - litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; - if (csrbank2_dfii_pi1_address0_re) begin - litedramcore_phaseinjector1_address_storage[15:0] <= csrbank2_dfii_pi1_address0_r; + main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re; + if (builder_csrbank2_dfii_pi1_address0_re) begin + main_litedramcore_phaseinjector1_address_storage[15:0] <= builder_csrbank2_dfii_pi1_address0_r; end - litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; - if (csrbank2_dfii_pi1_baddress0_re) begin - litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; + main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re; + if (builder_csrbank2_dfii_pi1_baddress0_re) begin + main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r; end - litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; - if (csrbank2_dfii_pi1_wrdata0_re) begin - litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; + main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re; + if (builder_csrbank2_dfii_pi1_wrdata0_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r; end - litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; - litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re; - if (csrbank2_dfii_pi2_command0_re) begin - litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; + main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re; + main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re; + if (builder_csrbank2_dfii_pi2_command0_re) begin + main_litedramcore_phaseinjector2_command_storage[7:0] <= builder_csrbank2_dfii_pi2_command0_r; end - litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; - if (csrbank2_dfii_pi2_address0_re) begin - litedramcore_phaseinjector2_address_storage[15:0] <= csrbank2_dfii_pi2_address0_r; + main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re; + if (builder_csrbank2_dfii_pi2_address0_re) begin + main_litedramcore_phaseinjector2_address_storage[15:0] <= builder_csrbank2_dfii_pi2_address0_r; end - litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; - if (csrbank2_dfii_pi2_baddress0_re) begin - litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; + main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re; + if (builder_csrbank2_dfii_pi2_baddress0_re) begin + main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r; end - litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; - if (csrbank2_dfii_pi2_wrdata0_re) begin - litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r; + main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re; + if (builder_csrbank2_dfii_pi2_wrdata0_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r; end - litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; - litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re; - if (csrbank2_dfii_pi3_command0_re) begin - litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; + main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re; + main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re; + if (builder_csrbank2_dfii_pi3_command0_re) begin + main_litedramcore_phaseinjector3_command_storage[7:0] <= builder_csrbank2_dfii_pi3_command0_r; end - litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; - if (csrbank2_dfii_pi3_address0_re) begin - litedramcore_phaseinjector3_address_storage[15:0] <= csrbank2_dfii_pi3_address0_r; + main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re; + if (builder_csrbank2_dfii_pi3_address0_re) begin + main_litedramcore_phaseinjector3_address_storage[15:0] <= builder_csrbank2_dfii_pi3_address0_r; end - litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; - if (csrbank2_dfii_pi3_baddress0_re) begin - litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; + main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re; + if (builder_csrbank2_dfii_pi3_baddress0_re) begin + main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r; end - litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; - if (csrbank2_dfii_pi3_wrdata0_re) begin - litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r; + main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re; + if (builder_csrbank2_dfii_pi3_wrdata0_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r; end - litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; - litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re; + main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re; + main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re; if (sys_rst) begin - a7ddrphy_rst_storage <= 1'd0; - a7ddrphy_rst_re <= 1'd0; - a7ddrphy_dly_sel_storage <= 2'd0; - a7ddrphy_dly_sel_re <= 1'd0; - a7ddrphy_half_sys8x_taps_storage <= 5'd8; - a7ddrphy_half_sys8x_taps_re <= 1'd0; - a7ddrphy_wlevel_en_storage <= 1'd0; - a7ddrphy_wlevel_en_re <= 1'd0; - a7ddrphy_rdphase_storage <= 2'd2; - a7ddrphy_rdphase_re <= 1'd0; - a7ddrphy_wrphase_storage <= 2'd3; - a7ddrphy_wrphase_re <= 1'd0; - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; - a7ddrphy_dqspattern_o1 <= 8'd0; - a7ddrphy_bitslip0_value0 <= 3'd7; - a7ddrphy_bitslip1_value0 <= 3'd7; - a7ddrphy_bitslip0_value1 <= 3'd7; - a7ddrphy_bitslip1_value1 <= 3'd7; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; - a7ddrphy_bitslip0_value2 <= 3'd7; - a7ddrphy_bitslip0_value3 <= 3'd7; - a7ddrphy_bitslip1_value2 <= 3'd7; - a7ddrphy_bitslip1_value3 <= 3'd7; - a7ddrphy_bitslip2_value0 <= 3'd7; - a7ddrphy_bitslip2_value1 <= 3'd7; - a7ddrphy_bitslip3_value0 <= 3'd7; - a7ddrphy_bitslip3_value1 <= 3'd7; - a7ddrphy_bitslip4_value0 <= 3'd7; - a7ddrphy_bitslip4_value1 <= 3'd7; - a7ddrphy_bitslip5_value0 <= 3'd7; - a7ddrphy_bitslip5_value1 <= 3'd7; - a7ddrphy_bitslip6_value0 <= 3'd7; - a7ddrphy_bitslip6_value1 <= 3'd7; - a7ddrphy_bitslip7_value0 <= 3'd7; - a7ddrphy_bitslip7_value1 <= 3'd7; - a7ddrphy_bitslip8_value0 <= 3'd7; - a7ddrphy_bitslip8_value1 <= 3'd7; - a7ddrphy_bitslip9_value0 <= 3'd7; - a7ddrphy_bitslip9_value1 <= 3'd7; - a7ddrphy_bitslip10_value0 <= 3'd7; - a7ddrphy_bitslip10_value1 <= 3'd7; - a7ddrphy_bitslip11_value0 <= 3'd7; - a7ddrphy_bitslip11_value1 <= 3'd7; - a7ddrphy_bitslip12_value0 <= 3'd7; - a7ddrphy_bitslip12_value1 <= 3'd7; - a7ddrphy_bitslip13_value0 <= 3'd7; - a7ddrphy_bitslip13_value1 <= 3'd7; - a7ddrphy_bitslip14_value0 <= 3'd7; - a7ddrphy_bitslip14_value1 <= 3'd7; - a7ddrphy_bitslip15_value0 <= 3'd7; - a7ddrphy_bitslip15_value1 <= 3'd7; - a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; - a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; - a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; - a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; - litedramcore_storage <= 4'd1; - litedramcore_re <= 1'd0; - litedramcore_phaseinjector0_command_storage <= 6'd0; - litedramcore_phaseinjector0_command_re <= 1'd0; - litedramcore_phaseinjector0_address_re <= 1'd0; - litedramcore_phaseinjector0_baddress_re <= 1'd0; - litedramcore_phaseinjector0_wrdata_re <= 1'd0; - litedramcore_phaseinjector0_rddata_status <= 32'd0; - litedramcore_phaseinjector0_rddata_re <= 1'd0; - litedramcore_phaseinjector1_command_storage <= 6'd0; - litedramcore_phaseinjector1_command_re <= 1'd0; - litedramcore_phaseinjector1_address_re <= 1'd0; - litedramcore_phaseinjector1_baddress_re <= 1'd0; - litedramcore_phaseinjector1_wrdata_re <= 1'd0; - litedramcore_phaseinjector1_rddata_status <= 32'd0; - litedramcore_phaseinjector1_rddata_re <= 1'd0; - litedramcore_phaseinjector2_command_storage <= 6'd0; - litedramcore_phaseinjector2_command_re <= 1'd0; - litedramcore_phaseinjector2_address_re <= 1'd0; - litedramcore_phaseinjector2_baddress_re <= 1'd0; - litedramcore_phaseinjector2_wrdata_re <= 1'd0; - litedramcore_phaseinjector2_rddata_status <= 32'd0; - litedramcore_phaseinjector2_rddata_re <= 1'd0; - litedramcore_phaseinjector3_command_storage <= 6'd0; - litedramcore_phaseinjector3_command_re <= 1'd0; - litedramcore_phaseinjector3_address_re <= 1'd0; - litedramcore_phaseinjector3_baddress_re <= 1'd0; - litedramcore_phaseinjector3_wrdata_re <= 1'd0; - litedramcore_phaseinjector3_rddata_status <= 32'd0; - litedramcore_phaseinjector3_rddata_re <= 1'd0; - litedramcore_dfi_p0_address <= 16'd0; - litedramcore_dfi_p0_bank <= 3'd0; - litedramcore_dfi_p0_cas_n <= 1'd1; - litedramcore_dfi_p0_cs_n <= 1'd1; - litedramcore_dfi_p0_ras_n <= 1'd1; - litedramcore_dfi_p0_we_n <= 1'd1; - litedramcore_dfi_p0_wrdata_en <= 1'd0; - litedramcore_dfi_p0_rddata_en <= 1'd0; - litedramcore_dfi_p1_address <= 16'd0; - litedramcore_dfi_p1_bank <= 3'd0; - litedramcore_dfi_p1_cas_n <= 1'd1; - litedramcore_dfi_p1_cs_n <= 1'd1; - litedramcore_dfi_p1_ras_n <= 1'd1; - litedramcore_dfi_p1_we_n <= 1'd1; - litedramcore_dfi_p1_wrdata_en <= 1'd0; - litedramcore_dfi_p1_rddata_en <= 1'd0; - litedramcore_dfi_p2_address <= 16'd0; - litedramcore_dfi_p2_bank <= 3'd0; - litedramcore_dfi_p2_cas_n <= 1'd1; - litedramcore_dfi_p2_cs_n <= 1'd1; - litedramcore_dfi_p2_ras_n <= 1'd1; - litedramcore_dfi_p2_we_n <= 1'd1; - litedramcore_dfi_p2_wrdata_en <= 1'd0; - litedramcore_dfi_p2_rddata_en <= 1'd0; - litedramcore_dfi_p3_address <= 16'd0; - litedramcore_dfi_p3_bank <= 3'd0; - litedramcore_dfi_p3_cas_n <= 1'd1; - litedramcore_dfi_p3_cs_n <= 1'd1; - litedramcore_dfi_p3_ras_n <= 1'd1; - litedramcore_dfi_p3_we_n <= 1'd1; - litedramcore_dfi_p3_wrdata_en <= 1'd0; - litedramcore_dfi_p3_rddata_en <= 1'd0; - litedramcore_cmd_payload_a <= 16'd0; - litedramcore_cmd_payload_ba <= 3'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_timer_count1 <= 10'd781; - litedramcore_postponer_req_o <= 1'd0; - litedramcore_postponer_count <= 1'd0; - litedramcore_sequencer_done1 <= 1'd0; - litedramcore_sequencer_counter <= 7'd0; - litedramcore_sequencer_count <= 1'd0; - litedramcore_zqcs_timer_count1 <= 27'd99999999; - litedramcore_zqcs_executer_done <= 1'd0; - litedramcore_zqcs_executer_counter <= 5'd0; - litedramcore_bankmachine0_level <= 5'd0; - litedramcore_bankmachine0_produce <= 4'd0; - litedramcore_bankmachine0_consume <= 4'd0; - litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 23'd0; - litedramcore_bankmachine0_row <= 16'd0; - litedramcore_bankmachine0_row_opened <= 1'd0; - litedramcore_bankmachine0_twtpcon_ready <= 1'd0; - litedramcore_bankmachine0_twtpcon_count <= 3'd0; - litedramcore_bankmachine0_trccon_ready <= 1'd0; - litedramcore_bankmachine0_trccon_count <= 3'd0; - litedramcore_bankmachine0_trascon_ready <= 1'd0; - litedramcore_bankmachine0_trascon_count <= 3'd0; - litedramcore_bankmachine1_level <= 5'd0; - litedramcore_bankmachine1_produce <= 4'd0; - litedramcore_bankmachine1_consume <= 4'd0; - litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 23'd0; - litedramcore_bankmachine1_row <= 16'd0; - litedramcore_bankmachine1_row_opened <= 1'd0; - litedramcore_bankmachine1_twtpcon_ready <= 1'd0; - litedramcore_bankmachine1_twtpcon_count <= 3'd0; - litedramcore_bankmachine1_trccon_ready <= 1'd0; - litedramcore_bankmachine1_trccon_count <= 3'd0; - litedramcore_bankmachine1_trascon_ready <= 1'd0; - litedramcore_bankmachine1_trascon_count <= 3'd0; - litedramcore_bankmachine2_level <= 5'd0; - litedramcore_bankmachine2_produce <= 4'd0; - litedramcore_bankmachine2_consume <= 4'd0; - litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 23'd0; - litedramcore_bankmachine2_row <= 16'd0; - litedramcore_bankmachine2_row_opened <= 1'd0; - litedramcore_bankmachine2_twtpcon_ready <= 1'd0; - litedramcore_bankmachine2_twtpcon_count <= 3'd0; - litedramcore_bankmachine2_trccon_ready <= 1'd0; - litedramcore_bankmachine2_trccon_count <= 3'd0; - litedramcore_bankmachine2_trascon_ready <= 1'd0; - litedramcore_bankmachine2_trascon_count <= 3'd0; - litedramcore_bankmachine3_level <= 5'd0; - litedramcore_bankmachine3_produce <= 4'd0; - litedramcore_bankmachine3_consume <= 4'd0; - litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 23'd0; - litedramcore_bankmachine3_row <= 16'd0; - litedramcore_bankmachine3_row_opened <= 1'd0; - litedramcore_bankmachine3_twtpcon_ready <= 1'd0; - litedramcore_bankmachine3_twtpcon_count <= 3'd0; - litedramcore_bankmachine3_trccon_ready <= 1'd0; - litedramcore_bankmachine3_trccon_count <= 3'd0; - litedramcore_bankmachine3_trascon_ready <= 1'd0; - litedramcore_bankmachine3_trascon_count <= 3'd0; - litedramcore_bankmachine4_level <= 5'd0; - litedramcore_bankmachine4_produce <= 4'd0; - litedramcore_bankmachine4_consume <= 4'd0; - litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 23'd0; - litedramcore_bankmachine4_row <= 16'd0; - litedramcore_bankmachine4_row_opened <= 1'd0; - litedramcore_bankmachine4_twtpcon_ready <= 1'd0; - litedramcore_bankmachine4_twtpcon_count <= 3'd0; - litedramcore_bankmachine4_trccon_ready <= 1'd0; - litedramcore_bankmachine4_trccon_count <= 3'd0; - litedramcore_bankmachine4_trascon_ready <= 1'd0; - litedramcore_bankmachine4_trascon_count <= 3'd0; - litedramcore_bankmachine5_level <= 5'd0; - litedramcore_bankmachine5_produce <= 4'd0; - litedramcore_bankmachine5_consume <= 4'd0; - litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 23'd0; - litedramcore_bankmachine5_row <= 16'd0; - litedramcore_bankmachine5_row_opened <= 1'd0; - litedramcore_bankmachine5_twtpcon_ready <= 1'd0; - litedramcore_bankmachine5_twtpcon_count <= 3'd0; - litedramcore_bankmachine5_trccon_ready <= 1'd0; - litedramcore_bankmachine5_trccon_count <= 3'd0; - litedramcore_bankmachine5_trascon_ready <= 1'd0; - litedramcore_bankmachine5_trascon_count <= 3'd0; - litedramcore_bankmachine6_level <= 5'd0; - litedramcore_bankmachine6_produce <= 4'd0; - litedramcore_bankmachine6_consume <= 4'd0; - litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 23'd0; - litedramcore_bankmachine6_row <= 16'd0; - litedramcore_bankmachine6_row_opened <= 1'd0; - litedramcore_bankmachine6_twtpcon_ready <= 1'd0; - litedramcore_bankmachine6_twtpcon_count <= 3'd0; - litedramcore_bankmachine6_trccon_ready <= 1'd0; - litedramcore_bankmachine6_trccon_count <= 3'd0; - litedramcore_bankmachine6_trascon_ready <= 1'd0; - litedramcore_bankmachine6_trascon_count <= 3'd0; - litedramcore_bankmachine7_level <= 5'd0; - litedramcore_bankmachine7_produce <= 4'd0; - litedramcore_bankmachine7_consume <= 4'd0; - litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 23'd0; - litedramcore_bankmachine7_row <= 16'd0; - litedramcore_bankmachine7_row_opened <= 1'd0; - litedramcore_bankmachine7_twtpcon_ready <= 1'd0; - litedramcore_bankmachine7_twtpcon_count <= 3'd0; - litedramcore_bankmachine7_trccon_ready <= 1'd0; - litedramcore_bankmachine7_trccon_count <= 3'd0; - litedramcore_bankmachine7_trascon_ready <= 1'd0; - litedramcore_bankmachine7_trascon_count <= 3'd0; - litedramcore_choose_cmd_grant <= 3'd0; - litedramcore_choose_req_grant <= 3'd0; - litedramcore_trrdcon_ready <= 1'd0; - litedramcore_trrdcon_count <= 1'd0; - litedramcore_tfawcon_ready <= 1'd1; - litedramcore_tfawcon_window <= 5'd0; - litedramcore_tccdcon_ready <= 1'd0; - litedramcore_tccdcon_count <= 1'd0; - litedramcore_twtrcon_ready <= 1'd0; - litedramcore_twtrcon_count <= 3'd0; - litedramcore_time0 <= 5'd0; - litedramcore_time1 <= 4'd0; - init_done_storage <= 1'd0; - init_done_re <= 1'd0; - init_error_storage <= 1'd0; - init_error_re <= 1'd0; - litedramcore_we <= 1'd0; - litedramcore_refresher_state <= 2'd0; - litedramcore_bankmachine0_state <= 4'd0; - litedramcore_bankmachine1_state <= 4'd0; - litedramcore_bankmachine2_state <= 4'd0; - litedramcore_bankmachine3_state <= 4'd0; - litedramcore_bankmachine4_state <= 4'd0; - litedramcore_bankmachine5_state <= 4'd0; - litedramcore_bankmachine6_state <= 4'd0; - litedramcore_bankmachine7_state <= 4'd0; - litedramcore_multiplexer_state <= 4'd0; - litedramcore_new_master_wdata_ready0 <= 1'd0; - litedramcore_new_master_wdata_ready1 <= 1'd0; - litedramcore_new_master_rdata_valid0 <= 1'd0; - litedramcore_new_master_rdata_valid1 <= 1'd0; - litedramcore_new_master_rdata_valid2 <= 1'd0; - litedramcore_new_master_rdata_valid3 <= 1'd0; - litedramcore_new_master_rdata_valid4 <= 1'd0; - litedramcore_new_master_rdata_valid5 <= 1'd0; - litedramcore_new_master_rdata_valid6 <= 1'd0; - litedramcore_new_master_rdata_valid7 <= 1'd0; - litedramcore_new_master_rdata_valid8 <= 1'd0; - litedramcore_state <= 2'd0; + main_a7ddrphy_rst_storage <= 1'd0; + main_a7ddrphy_rst_re <= 1'd0; + main_a7ddrphy_dly_sel_storage <= 2'd0; + main_a7ddrphy_dly_sel_re <= 1'd0; + main_a7ddrphy_half_sys8x_taps_storage <= 5'd8; + main_a7ddrphy_half_sys8x_taps_re <= 1'd0; + main_a7ddrphy_wlevel_en_storage <= 1'd0; + main_a7ddrphy_wlevel_en_re <= 1'd0; + main_a7ddrphy_rdphase_storage <= 2'd2; + main_a7ddrphy_rdphase_re <= 1'd0; + main_a7ddrphy_wrphase_storage <= 2'd3; + main_a7ddrphy_wrphase_re <= 1'd0; + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + main_a7ddrphy_dqspattern_o1 <= 8'd0; + main_a7ddrphy_bitslip0_value0 <= 3'd7; + main_a7ddrphy_bitslip1_value0 <= 3'd7; + main_a7ddrphy_bitslip0_value1 <= 3'd7; + main_a7ddrphy_bitslip1_value1 <= 3'd7; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + main_a7ddrphy_bitslip0_value2 <= 3'd7; + main_a7ddrphy_bitslip0_value3 <= 3'd7; + main_a7ddrphy_bitslip1_value2 <= 3'd7; + main_a7ddrphy_bitslip1_value3 <= 3'd7; + main_a7ddrphy_bitslip2_value0 <= 3'd7; + main_a7ddrphy_bitslip2_value1 <= 3'd7; + main_a7ddrphy_bitslip3_value0 <= 3'd7; + main_a7ddrphy_bitslip3_value1 <= 3'd7; + main_a7ddrphy_bitslip4_value0 <= 3'd7; + main_a7ddrphy_bitslip4_value1 <= 3'd7; + main_a7ddrphy_bitslip5_value0 <= 3'd7; + main_a7ddrphy_bitslip5_value1 <= 3'd7; + main_a7ddrphy_bitslip6_value0 <= 3'd7; + main_a7ddrphy_bitslip6_value1 <= 3'd7; + main_a7ddrphy_bitslip7_value0 <= 3'd7; + main_a7ddrphy_bitslip7_value1 <= 3'd7; + main_a7ddrphy_bitslip8_value0 <= 3'd7; + main_a7ddrphy_bitslip8_value1 <= 3'd7; + main_a7ddrphy_bitslip9_value0 <= 3'd7; + main_a7ddrphy_bitslip9_value1 <= 3'd7; + main_a7ddrphy_bitslip10_value0 <= 3'd7; + main_a7ddrphy_bitslip10_value1 <= 3'd7; + main_a7ddrphy_bitslip11_value0 <= 3'd7; + main_a7ddrphy_bitslip11_value1 <= 3'd7; + main_a7ddrphy_bitslip12_value0 <= 3'd7; + main_a7ddrphy_bitslip12_value1 <= 3'd7; + main_a7ddrphy_bitslip13_value0 <= 3'd7; + main_a7ddrphy_bitslip13_value1 <= 3'd7; + main_a7ddrphy_bitslip14_value0 <= 3'd7; + main_a7ddrphy_bitslip14_value1 <= 3'd7; + main_a7ddrphy_bitslip15_value0 <= 3'd7; + main_a7ddrphy_bitslip15_value1 <= 3'd7; + main_a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; + main_a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; + main_a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; + main_a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; + main_litedramcore_storage <= 4'd1; + main_litedramcore_re <= 1'd0; + main_litedramcore_phaseinjector0_command_storage <= 8'd0; + main_litedramcore_phaseinjector0_command_re <= 1'd0; + main_litedramcore_phaseinjector0_address_re <= 1'd0; + main_litedramcore_phaseinjector0_baddress_re <= 1'd0; + main_litedramcore_phaseinjector0_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector0_rddata_status <= 32'd0; + main_litedramcore_phaseinjector0_rddata_re <= 1'd0; + main_litedramcore_phaseinjector1_command_storage <= 8'd0; + main_litedramcore_phaseinjector1_command_re <= 1'd0; + main_litedramcore_phaseinjector1_address_re <= 1'd0; + main_litedramcore_phaseinjector1_baddress_re <= 1'd0; + main_litedramcore_phaseinjector1_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector1_rddata_status <= 32'd0; + main_litedramcore_phaseinjector1_rddata_re <= 1'd0; + main_litedramcore_phaseinjector2_command_storage <= 8'd0; + main_litedramcore_phaseinjector2_command_re <= 1'd0; + main_litedramcore_phaseinjector2_address_re <= 1'd0; + main_litedramcore_phaseinjector2_baddress_re <= 1'd0; + main_litedramcore_phaseinjector2_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector2_rddata_status <= 32'd0; + main_litedramcore_phaseinjector2_rddata_re <= 1'd0; + main_litedramcore_phaseinjector3_command_storage <= 8'd0; + main_litedramcore_phaseinjector3_command_re <= 1'd0; + main_litedramcore_phaseinjector3_address_re <= 1'd0; + main_litedramcore_phaseinjector3_baddress_re <= 1'd0; + main_litedramcore_phaseinjector3_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector3_rddata_status <= 32'd0; + main_litedramcore_phaseinjector3_rddata_re <= 1'd0; + main_litedramcore_dfi_p0_address <= 16'd0; + main_litedramcore_dfi_p0_bank <= 3'd0; + main_litedramcore_dfi_p0_cas_n <= 1'd1; + main_litedramcore_dfi_p0_cs_n <= 1'd1; + main_litedramcore_dfi_p0_ras_n <= 1'd1; + main_litedramcore_dfi_p0_we_n <= 1'd1; + main_litedramcore_dfi_p0_wrdata_en <= 1'd0; + main_litedramcore_dfi_p0_rddata_en <= 1'd0; + main_litedramcore_dfi_p1_address <= 16'd0; + main_litedramcore_dfi_p1_bank <= 3'd0; + main_litedramcore_dfi_p1_cas_n <= 1'd1; + main_litedramcore_dfi_p1_cs_n <= 1'd1; + main_litedramcore_dfi_p1_ras_n <= 1'd1; + main_litedramcore_dfi_p1_we_n <= 1'd1; + main_litedramcore_dfi_p1_wrdata_en <= 1'd0; + main_litedramcore_dfi_p1_rddata_en <= 1'd0; + main_litedramcore_dfi_p2_address <= 16'd0; + main_litedramcore_dfi_p2_bank <= 3'd0; + main_litedramcore_dfi_p2_cas_n <= 1'd1; + main_litedramcore_dfi_p2_cs_n <= 1'd1; + main_litedramcore_dfi_p2_ras_n <= 1'd1; + main_litedramcore_dfi_p2_we_n <= 1'd1; + main_litedramcore_dfi_p2_wrdata_en <= 1'd0; + main_litedramcore_dfi_p2_rddata_en <= 1'd0; + main_litedramcore_dfi_p3_address <= 16'd0; + main_litedramcore_dfi_p3_bank <= 3'd0; + main_litedramcore_dfi_p3_cas_n <= 1'd1; + main_litedramcore_dfi_p3_cs_n <= 1'd1; + main_litedramcore_dfi_p3_ras_n <= 1'd1; + main_litedramcore_dfi_p3_we_n <= 1'd1; + main_litedramcore_dfi_p3_wrdata_en <= 1'd0; + main_litedramcore_dfi_p3_rddata_en <= 1'd0; + main_litedramcore_cmd_payload_a <= 16'd0; + main_litedramcore_cmd_payload_ba <= 3'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_timer_count1 <= 10'd781; + main_litedramcore_postponer_req_o <= 1'd0; + main_litedramcore_postponer_count <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd0; + main_litedramcore_sequencer_trigger <= 7'd0; + main_litedramcore_sequencer_count <= 1'd0; + main_litedramcore_zqcs_timer_count1 <= 27'd99999999; + main_litedramcore_zqcs_executer_done <= 1'd0; + main_litedramcore_zqcs_executer_trigger <= 5'd0; + main_litedramcore_bankmachine0_level <= 5'd0; + main_litedramcore_bankmachine0_produce <= 4'd0; + main_litedramcore_bankmachine0_consume <= 4'd0; + main_litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 23'd0; + main_litedramcore_bankmachine0_row <= 16'd0; + main_litedramcore_bankmachine0_row_opened <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine0_trccon_ready <= 1'd0; + main_litedramcore_bankmachine0_trccon_count <= 3'd0; + main_litedramcore_bankmachine0_trascon_ready <= 1'd0; + main_litedramcore_bankmachine0_trascon_count <= 3'd0; + main_litedramcore_bankmachine1_level <= 5'd0; + main_litedramcore_bankmachine1_produce <= 4'd0; + main_litedramcore_bankmachine1_consume <= 4'd0; + main_litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 23'd0; + main_litedramcore_bankmachine1_row <= 16'd0; + main_litedramcore_bankmachine1_row_opened <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine1_trccon_ready <= 1'd0; + main_litedramcore_bankmachine1_trccon_count <= 3'd0; + main_litedramcore_bankmachine1_trascon_ready <= 1'd0; + main_litedramcore_bankmachine1_trascon_count <= 3'd0; + main_litedramcore_bankmachine2_level <= 5'd0; + main_litedramcore_bankmachine2_produce <= 4'd0; + main_litedramcore_bankmachine2_consume <= 4'd0; + main_litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 23'd0; + main_litedramcore_bankmachine2_row <= 16'd0; + main_litedramcore_bankmachine2_row_opened <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine2_trccon_ready <= 1'd0; + main_litedramcore_bankmachine2_trccon_count <= 3'd0; + main_litedramcore_bankmachine2_trascon_ready <= 1'd0; + main_litedramcore_bankmachine2_trascon_count <= 3'd0; + main_litedramcore_bankmachine3_level <= 5'd0; + main_litedramcore_bankmachine3_produce <= 4'd0; + main_litedramcore_bankmachine3_consume <= 4'd0; + main_litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 23'd0; + main_litedramcore_bankmachine3_row <= 16'd0; + main_litedramcore_bankmachine3_row_opened <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine3_trccon_ready <= 1'd0; + main_litedramcore_bankmachine3_trccon_count <= 3'd0; + main_litedramcore_bankmachine3_trascon_ready <= 1'd0; + main_litedramcore_bankmachine3_trascon_count <= 3'd0; + main_litedramcore_bankmachine4_level <= 5'd0; + main_litedramcore_bankmachine4_produce <= 4'd0; + main_litedramcore_bankmachine4_consume <= 4'd0; + main_litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 23'd0; + main_litedramcore_bankmachine4_row <= 16'd0; + main_litedramcore_bankmachine4_row_opened <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine4_trccon_ready <= 1'd0; + main_litedramcore_bankmachine4_trccon_count <= 3'd0; + main_litedramcore_bankmachine4_trascon_ready <= 1'd0; + main_litedramcore_bankmachine4_trascon_count <= 3'd0; + main_litedramcore_bankmachine5_level <= 5'd0; + main_litedramcore_bankmachine5_produce <= 4'd0; + main_litedramcore_bankmachine5_consume <= 4'd0; + main_litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 23'd0; + main_litedramcore_bankmachine5_row <= 16'd0; + main_litedramcore_bankmachine5_row_opened <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine5_trccon_ready <= 1'd0; + main_litedramcore_bankmachine5_trccon_count <= 3'd0; + main_litedramcore_bankmachine5_trascon_ready <= 1'd0; + main_litedramcore_bankmachine5_trascon_count <= 3'd0; + main_litedramcore_bankmachine6_level <= 5'd0; + main_litedramcore_bankmachine6_produce <= 4'd0; + main_litedramcore_bankmachine6_consume <= 4'd0; + main_litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 23'd0; + main_litedramcore_bankmachine6_row <= 16'd0; + main_litedramcore_bankmachine6_row_opened <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine6_trccon_ready <= 1'd0; + main_litedramcore_bankmachine6_trccon_count <= 3'd0; + main_litedramcore_bankmachine6_trascon_ready <= 1'd0; + main_litedramcore_bankmachine6_trascon_count <= 3'd0; + main_litedramcore_bankmachine7_level <= 5'd0; + main_litedramcore_bankmachine7_produce <= 4'd0; + main_litedramcore_bankmachine7_consume <= 4'd0; + main_litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 23'd0; + main_litedramcore_bankmachine7_row <= 16'd0; + main_litedramcore_bankmachine7_row_opened <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine7_trccon_ready <= 1'd0; + main_litedramcore_bankmachine7_trccon_count <= 3'd0; + main_litedramcore_bankmachine7_trascon_ready <= 1'd0; + main_litedramcore_bankmachine7_trascon_count <= 3'd0; + main_litedramcore_choose_cmd_grant <= 3'd0; + main_litedramcore_choose_req_grant <= 3'd0; + main_litedramcore_trrdcon_ready <= 1'd0; + main_litedramcore_trrdcon_count <= 1'd0; + main_litedramcore_tfawcon_ready <= 1'd1; + main_litedramcore_tfawcon_window <= 5'd0; + main_litedramcore_tccdcon_ready <= 1'd0; + main_litedramcore_tccdcon_count <= 1'd0; + main_litedramcore_twtrcon_ready <= 1'd0; + main_litedramcore_twtrcon_count <= 3'd0; + main_litedramcore_time0 <= 5'd0; + main_litedramcore_time1 <= 4'd0; + main_init_done_storage <= 1'd0; + main_init_done_re <= 1'd0; + main_init_error_storage <= 1'd0; + main_init_error_re <= 1'd0; + builder_interface1_we <= 1'd0; + builder_refresher_state <= 2'd0; + builder_bankmachine0_state <= 4'd0; + builder_bankmachine1_state <= 4'd0; + builder_bankmachine2_state <= 4'd0; + builder_bankmachine3_state <= 4'd0; + builder_bankmachine4_state <= 4'd0; + builder_bankmachine5_state <= 4'd0; + builder_bankmachine6_state <= 4'd0; + builder_bankmachine7_state <= 4'd0; + builder_multiplexer_state <= 4'd0; + builder_new_master_wdata_ready0 <= 1'd0; + builder_new_master_wdata_ready1 <= 1'd0; + builder_new_master_rdata_valid0 <= 1'd0; + builder_new_master_rdata_valid1 <= 1'd0; + builder_new_master_rdata_valid2 <= 1'd0; + builder_new_master_rdata_valid3 <= 1'd0; + builder_new_master_rdata_valid4 <= 1'd0; + builder_new_master_rdata_valid5 <= 1'd0; + builder_new_master_rdata_valid6 <= 1'd0; + builder_new_master_rdata_valid7 <= 1'd0; + builder_new_master_rdata_valid8 <= 1'd0; + builder_state <= 2'd0; end end @@ -14116,1955 +14533,2682 @@ end // Specialized Logic //------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +// Instance BUFG of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG( - .I(clkout0), - .O(clkout_buf0) + // Inputs. + .I (main_clkout0), + + // Outputs. + .O (main_clkout_buf0) ); +//------------------------------------------------------------------------------ +// Instance BUFG_1 of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG_1( - .I(clkout1), - .O(clkout_buf1) + // Inputs. + .I (main_clkout1), + + // Outputs. + .O (main_clkout_buf1) ); +//------------------------------------------------------------------------------ +// Instance BUFG_2 of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG_2( - .I(clkout2), - .O(clkout_buf2) + // Inputs. + .I (main_clkout2), + + // Outputs. + .O (main_clkout_buf2) ); +//------------------------------------------------------------------------------ +// Instance BUFG_3 of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG_3( - .I(clkout3), - .O(clkout_buf3) + // Inputs. + .I (main_clkout3), + + // Outputs. + .O (main_clkout_buf3) ); +//------------------------------------------------------------------------------ +// Instance IDELAYCTRL of IDELAYCTRL Module. +//------------------------------------------------------------------------------ IDELAYCTRL IDELAYCTRL( - .REFCLK(iodelay_clk), - .RST(ic_reset) + // Inputs. + .REFCLK (iodelay_clk), + .RST (main_ic_reset) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(1'd0), - .D2(1'd1), - .D3(1'd0), - .D4(1'd1), - .D5(1'd0), - .D6(1'd1), - .D7(1'd0), - .D8(1'd1), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(a7ddrphy_sd_clk_se_nodelay) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (1'd0), + .D2 (1'd1), + .D3 (1'd0), + .D4 (1'd1), + .D5 (1'd0), + .D6 (1'd1), + .D7 (1'd0), + .D8 (1'd1), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_a7ddrphy_sd_clk_se_nodelay) ); +//------------------------------------------------------------------------------ +// Instance OBUFDS of OBUFDS Module. +//------------------------------------------------------------------------------ OBUFDS OBUFDS( - .I(a7ddrphy_sd_clk_se_nodelay), - .O(ddram_clk_p), - .OB(ddram_clk_n) + // Inputs. + .I (main_a7ddrphy_sd_clk_se_nodelay), + + // Outputs. + .O (ddram_clk_p), + .OB (ddram_clk_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_1 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_1 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_reset_n), - .D2(a7ddrphy_dfi_p0_reset_n), - .D3(a7ddrphy_dfi_p1_reset_n), - .D4(a7ddrphy_dfi_p1_reset_n), - .D5(a7ddrphy_dfi_p2_reset_n), - .D6(a7ddrphy_dfi_p2_reset_n), - .D7(a7ddrphy_dfi_p3_reset_n), - .D8(a7ddrphy_dfi_p3_reset_n), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_reset_n) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_reset_n), + .D2 (main_a7ddrphy_dfi_p0_reset_n), + .D3 (main_a7ddrphy_dfi_p1_reset_n), + .D4 (main_a7ddrphy_dfi_p1_reset_n), + .D5 (main_a7ddrphy_dfi_p2_reset_n), + .D6 (main_a7ddrphy_dfi_p2_reset_n), + .D7 (main_a7ddrphy_dfi_p3_reset_n), + .D8 (main_a7ddrphy_dfi_p3_reset_n), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_reset_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_2 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_2 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_cs_n), - .D2(a7ddrphy_dfi_p0_cs_n), - .D3(a7ddrphy_dfi_p1_cs_n), - .D4(a7ddrphy_dfi_p1_cs_n), - .D5(a7ddrphy_dfi_p2_cs_n), - .D6(a7ddrphy_dfi_p2_cs_n), - .D7(a7ddrphy_dfi_p3_cs_n), - .D8(a7ddrphy_dfi_p3_cs_n), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_cs_n) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_cs_n), + .D2 (main_a7ddrphy_dfi_p0_cs_n), + .D3 (main_a7ddrphy_dfi_p1_cs_n), + .D4 (main_a7ddrphy_dfi_p1_cs_n), + .D5 (main_a7ddrphy_dfi_p2_cs_n), + .D6 (main_a7ddrphy_dfi_p2_cs_n), + .D7 (main_a7ddrphy_dfi_p3_cs_n), + .D8 (main_a7ddrphy_dfi_p3_cs_n), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_cs_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_3 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_3 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[0]), - .D2(a7ddrphy_dfi_p0_address[0]), - .D3(a7ddrphy_dfi_p1_address[0]), - .D4(a7ddrphy_dfi_p1_address[0]), - .D5(a7ddrphy_dfi_p2_address[0]), - .D6(a7ddrphy_dfi_p2_address[0]), - .D7(a7ddrphy_dfi_p3_address[0]), - .D8(a7ddrphy_dfi_p3_address[0]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[0]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[0]), + .D2 (main_a7ddrphy_dfi_p0_address[0]), + .D3 (main_a7ddrphy_dfi_p1_address[0]), + .D4 (main_a7ddrphy_dfi_p1_address[0]), + .D5 (main_a7ddrphy_dfi_p2_address[0]), + .D6 (main_a7ddrphy_dfi_p2_address[0]), + .D7 (main_a7ddrphy_dfi_p3_address[0]), + .D8 (main_a7ddrphy_dfi_p3_address[0]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[0]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_4 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_4 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[1]), - .D2(a7ddrphy_dfi_p0_address[1]), - .D3(a7ddrphy_dfi_p1_address[1]), - .D4(a7ddrphy_dfi_p1_address[1]), - .D5(a7ddrphy_dfi_p2_address[1]), - .D6(a7ddrphy_dfi_p2_address[1]), - .D7(a7ddrphy_dfi_p3_address[1]), - .D8(a7ddrphy_dfi_p3_address[1]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[1]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[1]), + .D2 (main_a7ddrphy_dfi_p0_address[1]), + .D3 (main_a7ddrphy_dfi_p1_address[1]), + .D4 (main_a7ddrphy_dfi_p1_address[1]), + .D5 (main_a7ddrphy_dfi_p2_address[1]), + .D6 (main_a7ddrphy_dfi_p2_address[1]), + .D7 (main_a7ddrphy_dfi_p3_address[1]), + .D8 (main_a7ddrphy_dfi_p3_address[1]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[1]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_5 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_5 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[2]), - .D2(a7ddrphy_dfi_p0_address[2]), - .D3(a7ddrphy_dfi_p1_address[2]), - .D4(a7ddrphy_dfi_p1_address[2]), - .D5(a7ddrphy_dfi_p2_address[2]), - .D6(a7ddrphy_dfi_p2_address[2]), - .D7(a7ddrphy_dfi_p3_address[2]), - .D8(a7ddrphy_dfi_p3_address[2]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[2]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[2]), + .D2 (main_a7ddrphy_dfi_p0_address[2]), + .D3 (main_a7ddrphy_dfi_p1_address[2]), + .D4 (main_a7ddrphy_dfi_p1_address[2]), + .D5 (main_a7ddrphy_dfi_p2_address[2]), + .D6 (main_a7ddrphy_dfi_p2_address[2]), + .D7 (main_a7ddrphy_dfi_p3_address[2]), + .D8 (main_a7ddrphy_dfi_p3_address[2]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[2]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_6 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_6 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[3]), - .D2(a7ddrphy_dfi_p0_address[3]), - .D3(a7ddrphy_dfi_p1_address[3]), - .D4(a7ddrphy_dfi_p1_address[3]), - .D5(a7ddrphy_dfi_p2_address[3]), - .D6(a7ddrphy_dfi_p2_address[3]), - .D7(a7ddrphy_dfi_p3_address[3]), - .D8(a7ddrphy_dfi_p3_address[3]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[3]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[3]), + .D2 (main_a7ddrphy_dfi_p0_address[3]), + .D3 (main_a7ddrphy_dfi_p1_address[3]), + .D4 (main_a7ddrphy_dfi_p1_address[3]), + .D5 (main_a7ddrphy_dfi_p2_address[3]), + .D6 (main_a7ddrphy_dfi_p2_address[3]), + .D7 (main_a7ddrphy_dfi_p3_address[3]), + .D8 (main_a7ddrphy_dfi_p3_address[3]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[3]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_7 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_7 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[4]), - .D2(a7ddrphy_dfi_p0_address[4]), - .D3(a7ddrphy_dfi_p1_address[4]), - .D4(a7ddrphy_dfi_p1_address[4]), - .D5(a7ddrphy_dfi_p2_address[4]), - .D6(a7ddrphy_dfi_p2_address[4]), - .D7(a7ddrphy_dfi_p3_address[4]), - .D8(a7ddrphy_dfi_p3_address[4]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[4]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[4]), + .D2 (main_a7ddrphy_dfi_p0_address[4]), + .D3 (main_a7ddrphy_dfi_p1_address[4]), + .D4 (main_a7ddrphy_dfi_p1_address[4]), + .D5 (main_a7ddrphy_dfi_p2_address[4]), + .D6 (main_a7ddrphy_dfi_p2_address[4]), + .D7 (main_a7ddrphy_dfi_p3_address[4]), + .D8 (main_a7ddrphy_dfi_p3_address[4]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[4]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_8 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_8 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[5]), - .D2(a7ddrphy_dfi_p0_address[5]), - .D3(a7ddrphy_dfi_p1_address[5]), - .D4(a7ddrphy_dfi_p1_address[5]), - .D5(a7ddrphy_dfi_p2_address[5]), - .D6(a7ddrphy_dfi_p2_address[5]), - .D7(a7ddrphy_dfi_p3_address[5]), - .D8(a7ddrphy_dfi_p3_address[5]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[5]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[5]), + .D2 (main_a7ddrphy_dfi_p0_address[5]), + .D3 (main_a7ddrphy_dfi_p1_address[5]), + .D4 (main_a7ddrphy_dfi_p1_address[5]), + .D5 (main_a7ddrphy_dfi_p2_address[5]), + .D6 (main_a7ddrphy_dfi_p2_address[5]), + .D7 (main_a7ddrphy_dfi_p3_address[5]), + .D8 (main_a7ddrphy_dfi_p3_address[5]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[5]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_9 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_9 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[6]), - .D2(a7ddrphy_dfi_p0_address[6]), - .D3(a7ddrphy_dfi_p1_address[6]), - .D4(a7ddrphy_dfi_p1_address[6]), - .D5(a7ddrphy_dfi_p2_address[6]), - .D6(a7ddrphy_dfi_p2_address[6]), - .D7(a7ddrphy_dfi_p3_address[6]), - .D8(a7ddrphy_dfi_p3_address[6]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[6]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[6]), + .D2 (main_a7ddrphy_dfi_p0_address[6]), + .D3 (main_a7ddrphy_dfi_p1_address[6]), + .D4 (main_a7ddrphy_dfi_p1_address[6]), + .D5 (main_a7ddrphy_dfi_p2_address[6]), + .D6 (main_a7ddrphy_dfi_p2_address[6]), + .D7 (main_a7ddrphy_dfi_p3_address[6]), + .D8 (main_a7ddrphy_dfi_p3_address[6]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[6]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_10 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_10 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[7]), - .D2(a7ddrphy_dfi_p0_address[7]), - .D3(a7ddrphy_dfi_p1_address[7]), - .D4(a7ddrphy_dfi_p1_address[7]), - .D5(a7ddrphy_dfi_p2_address[7]), - .D6(a7ddrphy_dfi_p2_address[7]), - .D7(a7ddrphy_dfi_p3_address[7]), - .D8(a7ddrphy_dfi_p3_address[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[7]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[7]), + .D2 (main_a7ddrphy_dfi_p0_address[7]), + .D3 (main_a7ddrphy_dfi_p1_address[7]), + .D4 (main_a7ddrphy_dfi_p1_address[7]), + .D5 (main_a7ddrphy_dfi_p2_address[7]), + .D6 (main_a7ddrphy_dfi_p2_address[7]), + .D7 (main_a7ddrphy_dfi_p3_address[7]), + .D8 (main_a7ddrphy_dfi_p3_address[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[7]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_11 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_11 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[8]), - .D2(a7ddrphy_dfi_p0_address[8]), - .D3(a7ddrphy_dfi_p1_address[8]), - .D4(a7ddrphy_dfi_p1_address[8]), - .D5(a7ddrphy_dfi_p2_address[8]), - .D6(a7ddrphy_dfi_p2_address[8]), - .D7(a7ddrphy_dfi_p3_address[8]), - .D8(a7ddrphy_dfi_p3_address[8]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[8]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[8]), + .D2 (main_a7ddrphy_dfi_p0_address[8]), + .D3 (main_a7ddrphy_dfi_p1_address[8]), + .D4 (main_a7ddrphy_dfi_p1_address[8]), + .D5 (main_a7ddrphy_dfi_p2_address[8]), + .D6 (main_a7ddrphy_dfi_p2_address[8]), + .D7 (main_a7ddrphy_dfi_p3_address[8]), + .D8 (main_a7ddrphy_dfi_p3_address[8]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[8]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_12 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_12 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[9]), - .D2(a7ddrphy_dfi_p0_address[9]), - .D3(a7ddrphy_dfi_p1_address[9]), - .D4(a7ddrphy_dfi_p1_address[9]), - .D5(a7ddrphy_dfi_p2_address[9]), - .D6(a7ddrphy_dfi_p2_address[9]), - .D7(a7ddrphy_dfi_p3_address[9]), - .D8(a7ddrphy_dfi_p3_address[9]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[9]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[9]), + .D2 (main_a7ddrphy_dfi_p0_address[9]), + .D3 (main_a7ddrphy_dfi_p1_address[9]), + .D4 (main_a7ddrphy_dfi_p1_address[9]), + .D5 (main_a7ddrphy_dfi_p2_address[9]), + .D6 (main_a7ddrphy_dfi_p2_address[9]), + .D7 (main_a7ddrphy_dfi_p3_address[9]), + .D8 (main_a7ddrphy_dfi_p3_address[9]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[9]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_13 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_13 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[10]), - .D2(a7ddrphy_dfi_p0_address[10]), - .D3(a7ddrphy_dfi_p1_address[10]), - .D4(a7ddrphy_dfi_p1_address[10]), - .D5(a7ddrphy_dfi_p2_address[10]), - .D6(a7ddrphy_dfi_p2_address[10]), - .D7(a7ddrphy_dfi_p3_address[10]), - .D8(a7ddrphy_dfi_p3_address[10]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[10]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[10]), + .D2 (main_a7ddrphy_dfi_p0_address[10]), + .D3 (main_a7ddrphy_dfi_p1_address[10]), + .D4 (main_a7ddrphy_dfi_p1_address[10]), + .D5 (main_a7ddrphy_dfi_p2_address[10]), + .D6 (main_a7ddrphy_dfi_p2_address[10]), + .D7 (main_a7ddrphy_dfi_p3_address[10]), + .D8 (main_a7ddrphy_dfi_p3_address[10]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[10]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_14 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_14 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[11]), - .D2(a7ddrphy_dfi_p0_address[11]), - .D3(a7ddrphy_dfi_p1_address[11]), - .D4(a7ddrphy_dfi_p1_address[11]), - .D5(a7ddrphy_dfi_p2_address[11]), - .D6(a7ddrphy_dfi_p2_address[11]), - .D7(a7ddrphy_dfi_p3_address[11]), - .D8(a7ddrphy_dfi_p3_address[11]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[11]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[11]), + .D2 (main_a7ddrphy_dfi_p0_address[11]), + .D3 (main_a7ddrphy_dfi_p1_address[11]), + .D4 (main_a7ddrphy_dfi_p1_address[11]), + .D5 (main_a7ddrphy_dfi_p2_address[11]), + .D6 (main_a7ddrphy_dfi_p2_address[11]), + .D7 (main_a7ddrphy_dfi_p3_address[11]), + .D8 (main_a7ddrphy_dfi_p3_address[11]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[11]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_15 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_15 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[12]), - .D2(a7ddrphy_dfi_p0_address[12]), - .D3(a7ddrphy_dfi_p1_address[12]), - .D4(a7ddrphy_dfi_p1_address[12]), - .D5(a7ddrphy_dfi_p2_address[12]), - .D6(a7ddrphy_dfi_p2_address[12]), - .D7(a7ddrphy_dfi_p3_address[12]), - .D8(a7ddrphy_dfi_p3_address[12]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[12]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[12]), + .D2 (main_a7ddrphy_dfi_p0_address[12]), + .D3 (main_a7ddrphy_dfi_p1_address[12]), + .D4 (main_a7ddrphy_dfi_p1_address[12]), + .D5 (main_a7ddrphy_dfi_p2_address[12]), + .D6 (main_a7ddrphy_dfi_p2_address[12]), + .D7 (main_a7ddrphy_dfi_p3_address[12]), + .D8 (main_a7ddrphy_dfi_p3_address[12]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[12]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_16 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_16 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[13]), - .D2(a7ddrphy_dfi_p0_address[13]), - .D3(a7ddrphy_dfi_p1_address[13]), - .D4(a7ddrphy_dfi_p1_address[13]), - .D5(a7ddrphy_dfi_p2_address[13]), - .D6(a7ddrphy_dfi_p2_address[13]), - .D7(a7ddrphy_dfi_p3_address[13]), - .D8(a7ddrphy_dfi_p3_address[13]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[13]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[13]), + .D2 (main_a7ddrphy_dfi_p0_address[13]), + .D3 (main_a7ddrphy_dfi_p1_address[13]), + .D4 (main_a7ddrphy_dfi_p1_address[13]), + .D5 (main_a7ddrphy_dfi_p2_address[13]), + .D6 (main_a7ddrphy_dfi_p2_address[13]), + .D7 (main_a7ddrphy_dfi_p3_address[13]), + .D8 (main_a7ddrphy_dfi_p3_address[13]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[13]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_17 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_17 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[14]), - .D2(a7ddrphy_dfi_p0_address[14]), - .D3(a7ddrphy_dfi_p1_address[14]), - .D4(a7ddrphy_dfi_p1_address[14]), - .D5(a7ddrphy_dfi_p2_address[14]), - .D6(a7ddrphy_dfi_p2_address[14]), - .D7(a7ddrphy_dfi_p3_address[14]), - .D8(a7ddrphy_dfi_p3_address[14]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[14]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[14]), + .D2 (main_a7ddrphy_dfi_p0_address[14]), + .D3 (main_a7ddrphy_dfi_p1_address[14]), + .D4 (main_a7ddrphy_dfi_p1_address[14]), + .D5 (main_a7ddrphy_dfi_p2_address[14]), + .D6 (main_a7ddrphy_dfi_p2_address[14]), + .D7 (main_a7ddrphy_dfi_p3_address[14]), + .D8 (main_a7ddrphy_dfi_p3_address[14]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[14]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_18 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_18 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[15]), - .D2(a7ddrphy_dfi_p0_address[15]), - .D3(a7ddrphy_dfi_p1_address[15]), - .D4(a7ddrphy_dfi_p1_address[15]), - .D5(a7ddrphy_dfi_p2_address[15]), - .D6(a7ddrphy_dfi_p2_address[15]), - .D7(a7ddrphy_dfi_p3_address[15]), - .D8(a7ddrphy_dfi_p3_address[15]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[15]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[15]), + .D2 (main_a7ddrphy_dfi_p0_address[15]), + .D3 (main_a7ddrphy_dfi_p1_address[15]), + .D4 (main_a7ddrphy_dfi_p1_address[15]), + .D5 (main_a7ddrphy_dfi_p2_address[15]), + .D6 (main_a7ddrphy_dfi_p2_address[15]), + .D7 (main_a7ddrphy_dfi_p3_address[15]), + .D8 (main_a7ddrphy_dfi_p3_address[15]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[15]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_19 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_19 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_bank[0]), - .D2(a7ddrphy_dfi_p0_bank[0]), - .D3(a7ddrphy_dfi_p1_bank[0]), - .D4(a7ddrphy_dfi_p1_bank[0]), - .D5(a7ddrphy_dfi_p2_bank[0]), - .D6(a7ddrphy_dfi_p2_bank[0]), - .D7(a7ddrphy_dfi_p3_bank[0]), - .D8(a7ddrphy_dfi_p3_bank[0]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(a7ddrphy_pads_ba[0]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_bank[0]), + .D2 (main_a7ddrphy_dfi_p0_bank[0]), + .D3 (main_a7ddrphy_dfi_p1_bank[0]), + .D4 (main_a7ddrphy_dfi_p1_bank[0]), + .D5 (main_a7ddrphy_dfi_p2_bank[0]), + .D6 (main_a7ddrphy_dfi_p2_bank[0]), + .D7 (main_a7ddrphy_dfi_p3_bank[0]), + .D8 (main_a7ddrphy_dfi_p3_bank[0]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_a7ddrphy_pads_ba[0]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_20 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_20 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_bank[1]), - .D2(a7ddrphy_dfi_p0_bank[1]), - .D3(a7ddrphy_dfi_p1_bank[1]), - .D4(a7ddrphy_dfi_p1_bank[1]), - .D5(a7ddrphy_dfi_p2_bank[1]), - .D6(a7ddrphy_dfi_p2_bank[1]), - .D7(a7ddrphy_dfi_p3_bank[1]), - .D8(a7ddrphy_dfi_p3_bank[1]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(a7ddrphy_pads_ba[1]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_bank[1]), + .D2 (main_a7ddrphy_dfi_p0_bank[1]), + .D3 (main_a7ddrphy_dfi_p1_bank[1]), + .D4 (main_a7ddrphy_dfi_p1_bank[1]), + .D5 (main_a7ddrphy_dfi_p2_bank[1]), + .D6 (main_a7ddrphy_dfi_p2_bank[1]), + .D7 (main_a7ddrphy_dfi_p3_bank[1]), + .D8 (main_a7ddrphy_dfi_p3_bank[1]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_a7ddrphy_pads_ba[1]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_21 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_21 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_bank[2]), - .D2(a7ddrphy_dfi_p0_bank[2]), - .D3(a7ddrphy_dfi_p1_bank[2]), - .D4(a7ddrphy_dfi_p1_bank[2]), - .D5(a7ddrphy_dfi_p2_bank[2]), - .D6(a7ddrphy_dfi_p2_bank[2]), - .D7(a7ddrphy_dfi_p3_bank[2]), - .D8(a7ddrphy_dfi_p3_bank[2]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(a7ddrphy_pads_ba[2]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_bank[2]), + .D2 (main_a7ddrphy_dfi_p0_bank[2]), + .D3 (main_a7ddrphy_dfi_p1_bank[2]), + .D4 (main_a7ddrphy_dfi_p1_bank[2]), + .D5 (main_a7ddrphy_dfi_p2_bank[2]), + .D6 (main_a7ddrphy_dfi_p2_bank[2]), + .D7 (main_a7ddrphy_dfi_p3_bank[2]), + .D8 (main_a7ddrphy_dfi_p3_bank[2]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_a7ddrphy_pads_ba[2]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_22 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_22 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_ras_n), - .D2(a7ddrphy_dfi_p0_ras_n), - .D3(a7ddrphy_dfi_p1_ras_n), - .D4(a7ddrphy_dfi_p1_ras_n), - .D5(a7ddrphy_dfi_p2_ras_n), - .D6(a7ddrphy_dfi_p2_ras_n), - .D7(a7ddrphy_dfi_p3_ras_n), - .D8(a7ddrphy_dfi_p3_ras_n), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_ras_n) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_ras_n), + .D2 (main_a7ddrphy_dfi_p0_ras_n), + .D3 (main_a7ddrphy_dfi_p1_ras_n), + .D4 (main_a7ddrphy_dfi_p1_ras_n), + .D5 (main_a7ddrphy_dfi_p2_ras_n), + .D6 (main_a7ddrphy_dfi_p2_ras_n), + .D7 (main_a7ddrphy_dfi_p3_ras_n), + .D8 (main_a7ddrphy_dfi_p3_ras_n), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_ras_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_23 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_23 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_cas_n), - .D2(a7ddrphy_dfi_p0_cas_n), - .D3(a7ddrphy_dfi_p1_cas_n), - .D4(a7ddrphy_dfi_p1_cas_n), - .D5(a7ddrphy_dfi_p2_cas_n), - .D6(a7ddrphy_dfi_p2_cas_n), - .D7(a7ddrphy_dfi_p3_cas_n), - .D8(a7ddrphy_dfi_p3_cas_n), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_cas_n) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_cas_n), + .D2 (main_a7ddrphy_dfi_p0_cas_n), + .D3 (main_a7ddrphy_dfi_p1_cas_n), + .D4 (main_a7ddrphy_dfi_p1_cas_n), + .D5 (main_a7ddrphy_dfi_p2_cas_n), + .D6 (main_a7ddrphy_dfi_p2_cas_n), + .D7 (main_a7ddrphy_dfi_p3_cas_n), + .D8 (main_a7ddrphy_dfi_p3_cas_n), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_cas_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_24 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_24 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_we_n), - .D2(a7ddrphy_dfi_p0_we_n), - .D3(a7ddrphy_dfi_p1_we_n), - .D4(a7ddrphy_dfi_p1_we_n), - .D5(a7ddrphy_dfi_p2_we_n), - .D6(a7ddrphy_dfi_p2_we_n), - .D7(a7ddrphy_dfi_p3_we_n), - .D8(a7ddrphy_dfi_p3_we_n), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_we_n) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_we_n), + .D2 (main_a7ddrphy_dfi_p0_we_n), + .D3 (main_a7ddrphy_dfi_p1_we_n), + .D4 (main_a7ddrphy_dfi_p1_we_n), + .D5 (main_a7ddrphy_dfi_p2_we_n), + .D6 (main_a7ddrphy_dfi_p2_we_n), + .D7 (main_a7ddrphy_dfi_p3_we_n), + .D8 (main_a7ddrphy_dfi_p3_we_n), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_we_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_25 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_25 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_cke), - .D2(a7ddrphy_dfi_p0_cke), - .D3(a7ddrphy_dfi_p1_cke), - .D4(a7ddrphy_dfi_p1_cke), - .D5(a7ddrphy_dfi_p2_cke), - .D6(a7ddrphy_dfi_p2_cke), - .D7(a7ddrphy_dfi_p3_cke), - .D8(a7ddrphy_dfi_p3_cke), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_cke) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_cke), + .D2 (main_a7ddrphy_dfi_p0_cke), + .D3 (main_a7ddrphy_dfi_p1_cke), + .D4 (main_a7ddrphy_dfi_p1_cke), + .D5 (main_a7ddrphy_dfi_p2_cke), + .D6 (main_a7ddrphy_dfi_p2_cke), + .D7 (main_a7ddrphy_dfi_p3_cke), + .D8 (main_a7ddrphy_dfi_p3_cke), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_cke) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_26 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_26 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_odt), - .D2(a7ddrphy_dfi_p0_odt), - .D3(a7ddrphy_dfi_p1_odt), - .D4(a7ddrphy_dfi_p1_odt), - .D5(a7ddrphy_dfi_p2_odt), - .D6(a7ddrphy_dfi_p2_odt), - .D7(a7ddrphy_dfi_p3_odt), - .D8(a7ddrphy_dfi_p3_odt), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_odt) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_odt), + .D2 (main_a7ddrphy_dfi_p0_odt), + .D3 (main_a7ddrphy_dfi_p1_odt), + .D4 (main_a7ddrphy_dfi_p1_odt), + .D5 (main_a7ddrphy_dfi_p2_odt), + .D6 (main_a7ddrphy_dfi_p2_odt), + .D7 (main_a7ddrphy_dfi_p3_odt), + .D8 (main_a7ddrphy_dfi_p3_odt), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_odt) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_27 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_27 ( - .CLK(sys4x_dqs_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip00[0]), - .D2(a7ddrphy_bitslip00[1]), - .D3(a7ddrphy_bitslip00[2]), - .D4(a7ddrphy_bitslip00[3]), - .D5(a7ddrphy_bitslip00[4]), - .D6(a7ddrphy_bitslip00[5]), - .D7(a7ddrphy_bitslip00[6]), - .D8(a7ddrphy_bitslip00[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OFB(a7ddrphy0), - .OQ(a7ddrphy_dqs_o_no_delay0), - .TQ(a7ddrphy_dqs_t0) + // Inputs. + .CLK (sys4x_dqs_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip00[0]), + .D2 (main_a7ddrphy_bitslip00[1]), + .D3 (main_a7ddrphy_bitslip00[2]), + .D4 (main_a7ddrphy_bitslip00[3]), + .D5 (main_a7ddrphy_bitslip00[4]), + .D6 (main_a7ddrphy_bitslip00[5]), + .D7 (main_a7ddrphy_bitslip00[6]), + .D8 (main_a7ddrphy_bitslip00[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OFB (main_a7ddrphy0), + .OQ (main_a7ddrphy_dqs_o_no_delay0), + .TQ (main_a7ddrphy_dqs_t0) ); +//------------------------------------------------------------------------------ +// Instance IOBUFDS of IOBUFDS Module. +//------------------------------------------------------------------------------ IOBUFDS IOBUFDS( - .I(a7ddrphy_dqs_o_no_delay0), - .T(a7ddrphy_dqs_t0), - .IO(ddram_dqs_p[0]), - .IOB(ddram_dqs_n[0]) + // Inputs. + .I (main_a7ddrphy_dqs_o_no_delay0), + .T (main_a7ddrphy_dqs_t0), + + // InOuts. + .IO (ddram_dqs_p[0]), + .IOB (ddram_dqs_n[0]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_28 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_28 ( - .CLK(sys4x_dqs_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip10[0]), - .D2(a7ddrphy_bitslip10[1]), - .D3(a7ddrphy_bitslip10[2]), - .D4(a7ddrphy_bitslip10[3]), - .D5(a7ddrphy_bitslip10[4]), - .D6(a7ddrphy_bitslip10[5]), - .D7(a7ddrphy_bitslip10[6]), - .D8(a7ddrphy_bitslip10[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OFB(a7ddrphy1), - .OQ(a7ddrphy_dqs_o_no_delay1), - .TQ(a7ddrphy_dqs_t1) + // Inputs. + .CLK (sys4x_dqs_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip10[0]), + .D2 (main_a7ddrphy_bitslip10[1]), + .D3 (main_a7ddrphy_bitslip10[2]), + .D4 (main_a7ddrphy_bitslip10[3]), + .D5 (main_a7ddrphy_bitslip10[4]), + .D6 (main_a7ddrphy_bitslip10[5]), + .D7 (main_a7ddrphy_bitslip10[6]), + .D8 (main_a7ddrphy_bitslip10[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OFB (main_a7ddrphy1), + .OQ (main_a7ddrphy_dqs_o_no_delay1), + .TQ (main_a7ddrphy_dqs_t1) ); +//------------------------------------------------------------------------------ +// Instance IOBUFDS_1 of IOBUFDS Module. +//------------------------------------------------------------------------------ IOBUFDS IOBUFDS_1( - .I(a7ddrphy_dqs_o_no_delay1), - .T(a7ddrphy_dqs_t1), - .IO(ddram_dqs_p[1]), - .IOB(ddram_dqs_n[1]) + // Inputs. + .I (main_a7ddrphy_dqs_o_no_delay1), + .T (main_a7ddrphy_dqs_t1), + + // InOuts. + .IO (ddram_dqs_p[1]), + .IOB (ddram_dqs_n[1]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_29 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_29 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip01[0]), - .D2(a7ddrphy_bitslip01[1]), - .D3(a7ddrphy_bitslip01[2]), - .D4(a7ddrphy_bitslip01[3]), - .D5(a7ddrphy_bitslip01[4]), - .D6(a7ddrphy_bitslip01[5]), - .D7(a7ddrphy_bitslip01[6]), - .D8(a7ddrphy_bitslip01[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_dm[0]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip01[0]), + .D2 (main_a7ddrphy_bitslip01[1]), + .D3 (main_a7ddrphy_bitslip01[2]), + .D4 (main_a7ddrphy_bitslip01[3]), + .D5 (main_a7ddrphy_bitslip01[4]), + .D6 (main_a7ddrphy_bitslip01[5]), + .D7 (main_a7ddrphy_bitslip01[6]), + .D8 (main_a7ddrphy_bitslip01[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_dm[0]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_30 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_30 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip11[0]), - .D2(a7ddrphy_bitslip11[1]), - .D3(a7ddrphy_bitslip11[2]), - .D4(a7ddrphy_bitslip11[3]), - .D5(a7ddrphy_bitslip11[4]), - .D6(a7ddrphy_bitslip11[5]), - .D7(a7ddrphy_bitslip11[6]), - .D8(a7ddrphy_bitslip11[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_dm[1]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip11[0]), + .D2 (main_a7ddrphy_bitslip11[1]), + .D3 (main_a7ddrphy_bitslip11[2]), + .D4 (main_a7ddrphy_bitslip11[3]), + .D5 (main_a7ddrphy_bitslip11[4]), + .D6 (main_a7ddrphy_bitslip11[5]), + .D7 (main_a7ddrphy_bitslip11[6]), + .D8 (main_a7ddrphy_bitslip11[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_dm[1]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_31 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_31 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip02[0]), - .D2(a7ddrphy_bitslip02[1]), - .D3(a7ddrphy_bitslip02[2]), - .D4(a7ddrphy_bitslip02[3]), - .D5(a7ddrphy_bitslip02[4]), - .D6(a7ddrphy_bitslip02[5]), - .D7(a7ddrphy_bitslip02[6]), - .D8(a7ddrphy_bitslip02[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay0), - .TQ(a7ddrphy_dq_t0) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip02[0]), + .D2 (main_a7ddrphy_bitslip02[1]), + .D3 (main_a7ddrphy_bitslip02[2]), + .D4 (main_a7ddrphy_bitslip02[3]), + .D5 (main_a7ddrphy_bitslip02[4]), + .D6 (main_a7ddrphy_bitslip02[5]), + .D7 (main_a7ddrphy_bitslip02[6]), + .D8 (main_a7ddrphy_bitslip02[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay0), + .TQ (main_a7ddrphy_dq_t0) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed0), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip03[7]), - .Q2(a7ddrphy_bitslip03[6]), - .Q3(a7ddrphy_bitslip03[5]), - .Q4(a7ddrphy_bitslip03[4]), - .Q5(a7ddrphy_bitslip03[3]), - .Q6(a7ddrphy_bitslip03[2]), - .Q7(a7ddrphy_bitslip03[1]), - .Q8(a7ddrphy_bitslip03[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed0), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip03[7]), + .Q2 (main_a7ddrphy_bitslip03[6]), + .Q3 (main_a7ddrphy_bitslip03[5]), + .Q4 (main_a7ddrphy_bitslip03[4]), + .Q5 (main_a7ddrphy_bitslip03[3]), + .Q6 (main_a7ddrphy_bitslip03[2]), + .Q7 (main_a7ddrphy_bitslip03[1]), + .Q8 (main_a7ddrphy_bitslip03[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay0), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed0) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay0), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed0) ); +//------------------------------------------------------------------------------ +// Instance IOBUF of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF( - .I(a7ddrphy_dq_o_nodelay0), - .T(a7ddrphy_dq_t0), - .IO(ddram_dq[0]), - .O(a7ddrphy_dq_i_nodelay0) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay0), + .T (main_a7ddrphy_dq_t0), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay0), + + // InOuts. + .IO (ddram_dq[0]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_32 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_32 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip12[0]), - .D2(a7ddrphy_bitslip12[1]), - .D3(a7ddrphy_bitslip12[2]), - .D4(a7ddrphy_bitslip12[3]), - .D5(a7ddrphy_bitslip12[4]), - .D6(a7ddrphy_bitslip12[5]), - .D7(a7ddrphy_bitslip12[6]), - .D8(a7ddrphy_bitslip12[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay1), - .TQ(a7ddrphy_dq_t1) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip12[0]), + .D2 (main_a7ddrphy_bitslip12[1]), + .D3 (main_a7ddrphy_bitslip12[2]), + .D4 (main_a7ddrphy_bitslip12[3]), + .D5 (main_a7ddrphy_bitslip12[4]), + .D6 (main_a7ddrphy_bitslip12[5]), + .D7 (main_a7ddrphy_bitslip12[6]), + .D8 (main_a7ddrphy_bitslip12[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay1), + .TQ (main_a7ddrphy_dq_t1) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_1 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_1 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip13[7]), - .Q2(a7ddrphy_bitslip13[6]), - .Q3(a7ddrphy_bitslip13[5]), - .Q4(a7ddrphy_bitslip13[4]), - .Q5(a7ddrphy_bitslip13[3]), - .Q6(a7ddrphy_bitslip13[2]), - .Q7(a7ddrphy_bitslip13[1]), - .Q8(a7ddrphy_bitslip13[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip13[7]), + .Q2 (main_a7ddrphy_bitslip13[6]), + .Q3 (main_a7ddrphy_bitslip13[5]), + .Q4 (main_a7ddrphy_bitslip13[4]), + .Q5 (main_a7ddrphy_bitslip13[3]), + .Q6 (main_a7ddrphy_bitslip13[2]), + .Q7 (main_a7ddrphy_bitslip13[1]), + .Q8 (main_a7ddrphy_bitslip13[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_1 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_1 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay1), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed1) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay1), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed1) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_1 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_1( - .I(a7ddrphy_dq_o_nodelay1), - .T(a7ddrphy_dq_t1), - .IO(ddram_dq[1]), - .O(a7ddrphy_dq_i_nodelay1) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay1), + .T (main_a7ddrphy_dq_t1), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay1), + + // InOuts. + .IO (ddram_dq[1]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_33 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_33 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip20[0]), - .D2(a7ddrphy_bitslip20[1]), - .D3(a7ddrphy_bitslip20[2]), - .D4(a7ddrphy_bitslip20[3]), - .D5(a7ddrphy_bitslip20[4]), - .D6(a7ddrphy_bitslip20[5]), - .D7(a7ddrphy_bitslip20[6]), - .D8(a7ddrphy_bitslip20[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay2), - .TQ(a7ddrphy_dq_t2) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip20[0]), + .D2 (main_a7ddrphy_bitslip20[1]), + .D3 (main_a7ddrphy_bitslip20[2]), + .D4 (main_a7ddrphy_bitslip20[3]), + .D5 (main_a7ddrphy_bitslip20[4]), + .D6 (main_a7ddrphy_bitslip20[5]), + .D7 (main_a7ddrphy_bitslip20[6]), + .D8 (main_a7ddrphy_bitslip20[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay2), + .TQ (main_a7ddrphy_dq_t2) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_2 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_2 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed2), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip21[7]), - .Q2(a7ddrphy_bitslip21[6]), - .Q3(a7ddrphy_bitslip21[5]), - .Q4(a7ddrphy_bitslip21[4]), - .Q5(a7ddrphy_bitslip21[3]), - .Q6(a7ddrphy_bitslip21[2]), - .Q7(a7ddrphy_bitslip21[1]), - .Q8(a7ddrphy_bitslip21[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed2), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip21[7]), + .Q2 (main_a7ddrphy_bitslip21[6]), + .Q3 (main_a7ddrphy_bitslip21[5]), + .Q4 (main_a7ddrphy_bitslip21[4]), + .Q5 (main_a7ddrphy_bitslip21[3]), + .Q6 (main_a7ddrphy_bitslip21[2]), + .Q7 (main_a7ddrphy_bitslip21[1]), + .Q8 (main_a7ddrphy_bitslip21[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_2 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_2 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay2), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed2) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay2), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed2) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_2 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_2( - .I(a7ddrphy_dq_o_nodelay2), - .T(a7ddrphy_dq_t2), - .IO(ddram_dq[2]), - .O(a7ddrphy_dq_i_nodelay2) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay2), + .T (main_a7ddrphy_dq_t2), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay2), + + // InOuts. + .IO (ddram_dq[2]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_34 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_34 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip30[0]), - .D2(a7ddrphy_bitslip30[1]), - .D3(a7ddrphy_bitslip30[2]), - .D4(a7ddrphy_bitslip30[3]), - .D5(a7ddrphy_bitslip30[4]), - .D6(a7ddrphy_bitslip30[5]), - .D7(a7ddrphy_bitslip30[6]), - .D8(a7ddrphy_bitslip30[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay3), - .TQ(a7ddrphy_dq_t3) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip30[0]), + .D2 (main_a7ddrphy_bitslip30[1]), + .D3 (main_a7ddrphy_bitslip30[2]), + .D4 (main_a7ddrphy_bitslip30[3]), + .D5 (main_a7ddrphy_bitslip30[4]), + .D6 (main_a7ddrphy_bitslip30[5]), + .D7 (main_a7ddrphy_bitslip30[6]), + .D8 (main_a7ddrphy_bitslip30[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay3), + .TQ (main_a7ddrphy_dq_t3) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_3 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_3 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed3), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip31[7]), - .Q2(a7ddrphy_bitslip31[6]), - .Q3(a7ddrphy_bitslip31[5]), - .Q4(a7ddrphy_bitslip31[4]), - .Q5(a7ddrphy_bitslip31[3]), - .Q6(a7ddrphy_bitslip31[2]), - .Q7(a7ddrphy_bitslip31[1]), - .Q8(a7ddrphy_bitslip31[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed3), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip31[7]), + .Q2 (main_a7ddrphy_bitslip31[6]), + .Q3 (main_a7ddrphy_bitslip31[5]), + .Q4 (main_a7ddrphy_bitslip31[4]), + .Q5 (main_a7ddrphy_bitslip31[3]), + .Q6 (main_a7ddrphy_bitslip31[2]), + .Q7 (main_a7ddrphy_bitslip31[1]), + .Q8 (main_a7ddrphy_bitslip31[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_3 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_3 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay3), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed3) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay3), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed3) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_3 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_3( - .I(a7ddrphy_dq_o_nodelay3), - .T(a7ddrphy_dq_t3), - .IO(ddram_dq[3]), - .O(a7ddrphy_dq_i_nodelay3) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay3), + .T (main_a7ddrphy_dq_t3), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay3), + + // InOuts. + .IO (ddram_dq[3]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_35 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_35 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip40[0]), - .D2(a7ddrphy_bitslip40[1]), - .D3(a7ddrphy_bitslip40[2]), - .D4(a7ddrphy_bitslip40[3]), - .D5(a7ddrphy_bitslip40[4]), - .D6(a7ddrphy_bitslip40[5]), - .D7(a7ddrphy_bitslip40[6]), - .D8(a7ddrphy_bitslip40[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay4), - .TQ(a7ddrphy_dq_t4) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip40[0]), + .D2 (main_a7ddrphy_bitslip40[1]), + .D3 (main_a7ddrphy_bitslip40[2]), + .D4 (main_a7ddrphy_bitslip40[3]), + .D5 (main_a7ddrphy_bitslip40[4]), + .D6 (main_a7ddrphy_bitslip40[5]), + .D7 (main_a7ddrphy_bitslip40[6]), + .D8 (main_a7ddrphy_bitslip40[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay4), + .TQ (main_a7ddrphy_dq_t4) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_4 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_4 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed4), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip41[7]), - .Q2(a7ddrphy_bitslip41[6]), - .Q3(a7ddrphy_bitslip41[5]), - .Q4(a7ddrphy_bitslip41[4]), - .Q5(a7ddrphy_bitslip41[3]), - .Q6(a7ddrphy_bitslip41[2]), - .Q7(a7ddrphy_bitslip41[1]), - .Q8(a7ddrphy_bitslip41[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed4), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip41[7]), + .Q2 (main_a7ddrphy_bitslip41[6]), + .Q3 (main_a7ddrphy_bitslip41[5]), + .Q4 (main_a7ddrphy_bitslip41[4]), + .Q5 (main_a7ddrphy_bitslip41[3]), + .Q6 (main_a7ddrphy_bitslip41[2]), + .Q7 (main_a7ddrphy_bitslip41[1]), + .Q8 (main_a7ddrphy_bitslip41[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_4 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_4 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay4), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed4) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay4), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed4) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_4 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_4( - .I(a7ddrphy_dq_o_nodelay4), - .T(a7ddrphy_dq_t4), - .IO(ddram_dq[4]), - .O(a7ddrphy_dq_i_nodelay4) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay4), + .T (main_a7ddrphy_dq_t4), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay4), + + // InOuts. + .IO (ddram_dq[4]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_36 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_36 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip50[0]), - .D2(a7ddrphy_bitslip50[1]), - .D3(a7ddrphy_bitslip50[2]), - .D4(a7ddrphy_bitslip50[3]), - .D5(a7ddrphy_bitslip50[4]), - .D6(a7ddrphy_bitslip50[5]), - .D7(a7ddrphy_bitslip50[6]), - .D8(a7ddrphy_bitslip50[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay5), - .TQ(a7ddrphy_dq_t5) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip50[0]), + .D2 (main_a7ddrphy_bitslip50[1]), + .D3 (main_a7ddrphy_bitslip50[2]), + .D4 (main_a7ddrphy_bitslip50[3]), + .D5 (main_a7ddrphy_bitslip50[4]), + .D6 (main_a7ddrphy_bitslip50[5]), + .D7 (main_a7ddrphy_bitslip50[6]), + .D8 (main_a7ddrphy_bitslip50[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay5), + .TQ (main_a7ddrphy_dq_t5) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_5 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_5 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed5), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip51[7]), - .Q2(a7ddrphy_bitslip51[6]), - .Q3(a7ddrphy_bitslip51[5]), - .Q4(a7ddrphy_bitslip51[4]), - .Q5(a7ddrphy_bitslip51[3]), - .Q6(a7ddrphy_bitslip51[2]), - .Q7(a7ddrphy_bitslip51[1]), - .Q8(a7ddrphy_bitslip51[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed5), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip51[7]), + .Q2 (main_a7ddrphy_bitslip51[6]), + .Q3 (main_a7ddrphy_bitslip51[5]), + .Q4 (main_a7ddrphy_bitslip51[4]), + .Q5 (main_a7ddrphy_bitslip51[3]), + .Q6 (main_a7ddrphy_bitslip51[2]), + .Q7 (main_a7ddrphy_bitslip51[1]), + .Q8 (main_a7ddrphy_bitslip51[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_5 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_5 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay5), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed5) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay5), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed5) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_5 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_5( - .I(a7ddrphy_dq_o_nodelay5), - .T(a7ddrphy_dq_t5), - .IO(ddram_dq[5]), - .O(a7ddrphy_dq_i_nodelay5) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay5), + .T (main_a7ddrphy_dq_t5), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay5), + + // InOuts. + .IO (ddram_dq[5]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_37 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_37 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip60[0]), - .D2(a7ddrphy_bitslip60[1]), - .D3(a7ddrphy_bitslip60[2]), - .D4(a7ddrphy_bitslip60[3]), - .D5(a7ddrphy_bitslip60[4]), - .D6(a7ddrphy_bitslip60[5]), - .D7(a7ddrphy_bitslip60[6]), - .D8(a7ddrphy_bitslip60[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay6), - .TQ(a7ddrphy_dq_t6) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip60[0]), + .D2 (main_a7ddrphy_bitslip60[1]), + .D3 (main_a7ddrphy_bitslip60[2]), + .D4 (main_a7ddrphy_bitslip60[3]), + .D5 (main_a7ddrphy_bitslip60[4]), + .D6 (main_a7ddrphy_bitslip60[5]), + .D7 (main_a7ddrphy_bitslip60[6]), + .D8 (main_a7ddrphy_bitslip60[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay6), + .TQ (main_a7ddrphy_dq_t6) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_6 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_6 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed6), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip61[7]), - .Q2(a7ddrphy_bitslip61[6]), - .Q3(a7ddrphy_bitslip61[5]), - .Q4(a7ddrphy_bitslip61[4]), - .Q5(a7ddrphy_bitslip61[3]), - .Q6(a7ddrphy_bitslip61[2]), - .Q7(a7ddrphy_bitslip61[1]), - .Q8(a7ddrphy_bitslip61[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed6), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip61[7]), + .Q2 (main_a7ddrphy_bitslip61[6]), + .Q3 (main_a7ddrphy_bitslip61[5]), + .Q4 (main_a7ddrphy_bitslip61[4]), + .Q5 (main_a7ddrphy_bitslip61[3]), + .Q6 (main_a7ddrphy_bitslip61[2]), + .Q7 (main_a7ddrphy_bitslip61[1]), + .Q8 (main_a7ddrphy_bitslip61[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_6 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_6 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay6), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed6) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay6), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed6) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_6 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_6( - .I(a7ddrphy_dq_o_nodelay6), - .T(a7ddrphy_dq_t6), - .IO(ddram_dq[6]), - .O(a7ddrphy_dq_i_nodelay6) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay6), + .T (main_a7ddrphy_dq_t6), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay6), + + // InOuts. + .IO (ddram_dq[6]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_38 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_38 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip70[0]), - .D2(a7ddrphy_bitslip70[1]), - .D3(a7ddrphy_bitslip70[2]), - .D4(a7ddrphy_bitslip70[3]), - .D5(a7ddrphy_bitslip70[4]), - .D6(a7ddrphy_bitslip70[5]), - .D7(a7ddrphy_bitslip70[6]), - .D8(a7ddrphy_bitslip70[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay7), - .TQ(a7ddrphy_dq_t7) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip70[0]), + .D2 (main_a7ddrphy_bitslip70[1]), + .D3 (main_a7ddrphy_bitslip70[2]), + .D4 (main_a7ddrphy_bitslip70[3]), + .D5 (main_a7ddrphy_bitslip70[4]), + .D6 (main_a7ddrphy_bitslip70[5]), + .D7 (main_a7ddrphy_bitslip70[6]), + .D8 (main_a7ddrphy_bitslip70[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay7), + .TQ (main_a7ddrphy_dq_t7) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_7 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_7 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed7), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip71[7]), - .Q2(a7ddrphy_bitslip71[6]), - .Q3(a7ddrphy_bitslip71[5]), - .Q4(a7ddrphy_bitslip71[4]), - .Q5(a7ddrphy_bitslip71[3]), - .Q6(a7ddrphy_bitslip71[2]), - .Q7(a7ddrphy_bitslip71[1]), - .Q8(a7ddrphy_bitslip71[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed7), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip71[7]), + .Q2 (main_a7ddrphy_bitslip71[6]), + .Q3 (main_a7ddrphy_bitslip71[5]), + .Q4 (main_a7ddrphy_bitslip71[4]), + .Q5 (main_a7ddrphy_bitslip71[3]), + .Q6 (main_a7ddrphy_bitslip71[2]), + .Q7 (main_a7ddrphy_bitslip71[1]), + .Q8 (main_a7ddrphy_bitslip71[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_7 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_7 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay7), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed7) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay7), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed7) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_7 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_7( - .I(a7ddrphy_dq_o_nodelay7), - .T(a7ddrphy_dq_t7), - .IO(ddram_dq[7]), - .O(a7ddrphy_dq_i_nodelay7) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay7), + .T (main_a7ddrphy_dq_t7), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay7), + + // InOuts. + .IO (ddram_dq[7]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_39 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_39 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip80[0]), - .D2(a7ddrphy_bitslip80[1]), - .D3(a7ddrphy_bitslip80[2]), - .D4(a7ddrphy_bitslip80[3]), - .D5(a7ddrphy_bitslip80[4]), - .D6(a7ddrphy_bitslip80[5]), - .D7(a7ddrphy_bitslip80[6]), - .D8(a7ddrphy_bitslip80[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay8), - .TQ(a7ddrphy_dq_t8) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip80[0]), + .D2 (main_a7ddrphy_bitslip80[1]), + .D3 (main_a7ddrphy_bitslip80[2]), + .D4 (main_a7ddrphy_bitslip80[3]), + .D5 (main_a7ddrphy_bitslip80[4]), + .D6 (main_a7ddrphy_bitslip80[5]), + .D7 (main_a7ddrphy_bitslip80[6]), + .D8 (main_a7ddrphy_bitslip80[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay8), + .TQ (main_a7ddrphy_dq_t8) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_8 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_8 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed8), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip81[7]), - .Q2(a7ddrphy_bitslip81[6]), - .Q3(a7ddrphy_bitslip81[5]), - .Q4(a7ddrphy_bitslip81[4]), - .Q5(a7ddrphy_bitslip81[3]), - .Q6(a7ddrphy_bitslip81[2]), - .Q7(a7ddrphy_bitslip81[1]), - .Q8(a7ddrphy_bitslip81[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed8), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip81[7]), + .Q2 (main_a7ddrphy_bitslip81[6]), + .Q3 (main_a7ddrphy_bitslip81[5]), + .Q4 (main_a7ddrphy_bitslip81[4]), + .Q5 (main_a7ddrphy_bitslip81[3]), + .Q6 (main_a7ddrphy_bitslip81[2]), + .Q7 (main_a7ddrphy_bitslip81[1]), + .Q8 (main_a7ddrphy_bitslip81[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_8 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_8 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay8), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed8) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay8), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed8) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_8 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_8( - .I(a7ddrphy_dq_o_nodelay8), - .T(a7ddrphy_dq_t8), - .IO(ddram_dq[8]), - .O(a7ddrphy_dq_i_nodelay8) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay8), + .T (main_a7ddrphy_dq_t8), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay8), + + // InOuts. + .IO (ddram_dq[8]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_40 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_40 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip90[0]), - .D2(a7ddrphy_bitslip90[1]), - .D3(a7ddrphy_bitslip90[2]), - .D4(a7ddrphy_bitslip90[3]), - .D5(a7ddrphy_bitslip90[4]), - .D6(a7ddrphy_bitslip90[5]), - .D7(a7ddrphy_bitslip90[6]), - .D8(a7ddrphy_bitslip90[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay9), - .TQ(a7ddrphy_dq_t9) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip90[0]), + .D2 (main_a7ddrphy_bitslip90[1]), + .D3 (main_a7ddrphy_bitslip90[2]), + .D4 (main_a7ddrphy_bitslip90[3]), + .D5 (main_a7ddrphy_bitslip90[4]), + .D6 (main_a7ddrphy_bitslip90[5]), + .D7 (main_a7ddrphy_bitslip90[6]), + .D8 (main_a7ddrphy_bitslip90[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay9), + .TQ (main_a7ddrphy_dq_t9) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_9 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_9 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed9), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip91[7]), - .Q2(a7ddrphy_bitslip91[6]), - .Q3(a7ddrphy_bitslip91[5]), - .Q4(a7ddrphy_bitslip91[4]), - .Q5(a7ddrphy_bitslip91[3]), - .Q6(a7ddrphy_bitslip91[2]), - .Q7(a7ddrphy_bitslip91[1]), - .Q8(a7ddrphy_bitslip91[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed9), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip91[7]), + .Q2 (main_a7ddrphy_bitslip91[6]), + .Q3 (main_a7ddrphy_bitslip91[5]), + .Q4 (main_a7ddrphy_bitslip91[4]), + .Q5 (main_a7ddrphy_bitslip91[3]), + .Q6 (main_a7ddrphy_bitslip91[2]), + .Q7 (main_a7ddrphy_bitslip91[1]), + .Q8 (main_a7ddrphy_bitslip91[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_9 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_9 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay9), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed9) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay9), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed9) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_9 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_9( - .I(a7ddrphy_dq_o_nodelay9), - .T(a7ddrphy_dq_t9), - .IO(ddram_dq[9]), - .O(a7ddrphy_dq_i_nodelay9) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay9), + .T (main_a7ddrphy_dq_t9), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay9), + + // InOuts. + .IO (ddram_dq[9]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_41 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_41 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip100[0]), - .D2(a7ddrphy_bitslip100[1]), - .D3(a7ddrphy_bitslip100[2]), - .D4(a7ddrphy_bitslip100[3]), - .D5(a7ddrphy_bitslip100[4]), - .D6(a7ddrphy_bitslip100[5]), - .D7(a7ddrphy_bitslip100[6]), - .D8(a7ddrphy_bitslip100[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay10), - .TQ(a7ddrphy_dq_t10) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip100[0]), + .D2 (main_a7ddrphy_bitslip100[1]), + .D3 (main_a7ddrphy_bitslip100[2]), + .D4 (main_a7ddrphy_bitslip100[3]), + .D5 (main_a7ddrphy_bitslip100[4]), + .D6 (main_a7ddrphy_bitslip100[5]), + .D7 (main_a7ddrphy_bitslip100[6]), + .D8 (main_a7ddrphy_bitslip100[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay10), + .TQ (main_a7ddrphy_dq_t10) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_10 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_10 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed10), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip101[7]), - .Q2(a7ddrphy_bitslip101[6]), - .Q3(a7ddrphy_bitslip101[5]), - .Q4(a7ddrphy_bitslip101[4]), - .Q5(a7ddrphy_bitslip101[3]), - .Q6(a7ddrphy_bitslip101[2]), - .Q7(a7ddrphy_bitslip101[1]), - .Q8(a7ddrphy_bitslip101[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed10), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip101[7]), + .Q2 (main_a7ddrphy_bitslip101[6]), + .Q3 (main_a7ddrphy_bitslip101[5]), + .Q4 (main_a7ddrphy_bitslip101[4]), + .Q5 (main_a7ddrphy_bitslip101[3]), + .Q6 (main_a7ddrphy_bitslip101[2]), + .Q7 (main_a7ddrphy_bitslip101[1]), + .Q8 (main_a7ddrphy_bitslip101[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_10 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_10 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay10), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed10) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay10), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed10) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_10 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_10( - .I(a7ddrphy_dq_o_nodelay10), - .T(a7ddrphy_dq_t10), - .IO(ddram_dq[10]), - .O(a7ddrphy_dq_i_nodelay10) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay10), + .T (main_a7ddrphy_dq_t10), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay10), + + // InOuts. + .IO (ddram_dq[10]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_42 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_42 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip110[0]), - .D2(a7ddrphy_bitslip110[1]), - .D3(a7ddrphy_bitslip110[2]), - .D4(a7ddrphy_bitslip110[3]), - .D5(a7ddrphy_bitslip110[4]), - .D6(a7ddrphy_bitslip110[5]), - .D7(a7ddrphy_bitslip110[6]), - .D8(a7ddrphy_bitslip110[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay11), - .TQ(a7ddrphy_dq_t11) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip110[0]), + .D2 (main_a7ddrphy_bitslip110[1]), + .D3 (main_a7ddrphy_bitslip110[2]), + .D4 (main_a7ddrphy_bitslip110[3]), + .D5 (main_a7ddrphy_bitslip110[4]), + .D6 (main_a7ddrphy_bitslip110[5]), + .D7 (main_a7ddrphy_bitslip110[6]), + .D8 (main_a7ddrphy_bitslip110[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay11), + .TQ (main_a7ddrphy_dq_t11) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_11 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_11 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed11), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip111[7]), - .Q2(a7ddrphy_bitslip111[6]), - .Q3(a7ddrphy_bitslip111[5]), - .Q4(a7ddrphy_bitslip111[4]), - .Q5(a7ddrphy_bitslip111[3]), - .Q6(a7ddrphy_bitslip111[2]), - .Q7(a7ddrphy_bitslip111[1]), - .Q8(a7ddrphy_bitslip111[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed11), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip111[7]), + .Q2 (main_a7ddrphy_bitslip111[6]), + .Q3 (main_a7ddrphy_bitslip111[5]), + .Q4 (main_a7ddrphy_bitslip111[4]), + .Q5 (main_a7ddrphy_bitslip111[3]), + .Q6 (main_a7ddrphy_bitslip111[2]), + .Q7 (main_a7ddrphy_bitslip111[1]), + .Q8 (main_a7ddrphy_bitslip111[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_11 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_11 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay11), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed11) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay11), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed11) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_11 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_11( - .I(a7ddrphy_dq_o_nodelay11), - .T(a7ddrphy_dq_t11), - .IO(ddram_dq[11]), - .O(a7ddrphy_dq_i_nodelay11) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay11), + .T (main_a7ddrphy_dq_t11), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay11), + + // InOuts. + .IO (ddram_dq[11]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_43 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_43 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip120[0]), - .D2(a7ddrphy_bitslip120[1]), - .D3(a7ddrphy_bitslip120[2]), - .D4(a7ddrphy_bitslip120[3]), - .D5(a7ddrphy_bitslip120[4]), - .D6(a7ddrphy_bitslip120[5]), - .D7(a7ddrphy_bitslip120[6]), - .D8(a7ddrphy_bitslip120[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay12), - .TQ(a7ddrphy_dq_t12) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip120[0]), + .D2 (main_a7ddrphy_bitslip120[1]), + .D3 (main_a7ddrphy_bitslip120[2]), + .D4 (main_a7ddrphy_bitslip120[3]), + .D5 (main_a7ddrphy_bitslip120[4]), + .D6 (main_a7ddrphy_bitslip120[5]), + .D7 (main_a7ddrphy_bitslip120[6]), + .D8 (main_a7ddrphy_bitslip120[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay12), + .TQ (main_a7ddrphy_dq_t12) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_12 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_12 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed12), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip121[7]), - .Q2(a7ddrphy_bitslip121[6]), - .Q3(a7ddrphy_bitslip121[5]), - .Q4(a7ddrphy_bitslip121[4]), - .Q5(a7ddrphy_bitslip121[3]), - .Q6(a7ddrphy_bitslip121[2]), - .Q7(a7ddrphy_bitslip121[1]), - .Q8(a7ddrphy_bitslip121[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed12), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip121[7]), + .Q2 (main_a7ddrphy_bitslip121[6]), + .Q3 (main_a7ddrphy_bitslip121[5]), + .Q4 (main_a7ddrphy_bitslip121[4]), + .Q5 (main_a7ddrphy_bitslip121[3]), + .Q6 (main_a7ddrphy_bitslip121[2]), + .Q7 (main_a7ddrphy_bitslip121[1]), + .Q8 (main_a7ddrphy_bitslip121[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_12 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_12 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay12), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed12) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay12), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed12) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_12 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_12( - .I(a7ddrphy_dq_o_nodelay12), - .T(a7ddrphy_dq_t12), - .IO(ddram_dq[12]), - .O(a7ddrphy_dq_i_nodelay12) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay12), + .T (main_a7ddrphy_dq_t12), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay12), + + // InOuts. + .IO (ddram_dq[12]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_44 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_44 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip130[0]), - .D2(a7ddrphy_bitslip130[1]), - .D3(a7ddrphy_bitslip130[2]), - .D4(a7ddrphy_bitslip130[3]), - .D5(a7ddrphy_bitslip130[4]), - .D6(a7ddrphy_bitslip130[5]), - .D7(a7ddrphy_bitslip130[6]), - .D8(a7ddrphy_bitslip130[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay13), - .TQ(a7ddrphy_dq_t13) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip130[0]), + .D2 (main_a7ddrphy_bitslip130[1]), + .D3 (main_a7ddrphy_bitslip130[2]), + .D4 (main_a7ddrphy_bitslip130[3]), + .D5 (main_a7ddrphy_bitslip130[4]), + .D6 (main_a7ddrphy_bitslip130[5]), + .D7 (main_a7ddrphy_bitslip130[6]), + .D8 (main_a7ddrphy_bitslip130[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay13), + .TQ (main_a7ddrphy_dq_t13) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_13 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_13 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed13), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip131[7]), - .Q2(a7ddrphy_bitslip131[6]), - .Q3(a7ddrphy_bitslip131[5]), - .Q4(a7ddrphy_bitslip131[4]), - .Q5(a7ddrphy_bitslip131[3]), - .Q6(a7ddrphy_bitslip131[2]), - .Q7(a7ddrphy_bitslip131[1]), - .Q8(a7ddrphy_bitslip131[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed13), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip131[7]), + .Q2 (main_a7ddrphy_bitslip131[6]), + .Q3 (main_a7ddrphy_bitslip131[5]), + .Q4 (main_a7ddrphy_bitslip131[4]), + .Q5 (main_a7ddrphy_bitslip131[3]), + .Q6 (main_a7ddrphy_bitslip131[2]), + .Q7 (main_a7ddrphy_bitslip131[1]), + .Q8 (main_a7ddrphy_bitslip131[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_13 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_13 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay13), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed13) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay13), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed13) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_13 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_13( - .I(a7ddrphy_dq_o_nodelay13), - .T(a7ddrphy_dq_t13), - .IO(ddram_dq[13]), - .O(a7ddrphy_dq_i_nodelay13) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay13), + .T (main_a7ddrphy_dq_t13), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay13), + + // InOuts. + .IO (ddram_dq[13]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_45 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_45 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip140[0]), - .D2(a7ddrphy_bitslip140[1]), - .D3(a7ddrphy_bitslip140[2]), - .D4(a7ddrphy_bitslip140[3]), - .D5(a7ddrphy_bitslip140[4]), - .D6(a7ddrphy_bitslip140[5]), - .D7(a7ddrphy_bitslip140[6]), - .D8(a7ddrphy_bitslip140[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay14), - .TQ(a7ddrphy_dq_t14) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip140[0]), + .D2 (main_a7ddrphy_bitslip140[1]), + .D3 (main_a7ddrphy_bitslip140[2]), + .D4 (main_a7ddrphy_bitslip140[3]), + .D5 (main_a7ddrphy_bitslip140[4]), + .D6 (main_a7ddrphy_bitslip140[5]), + .D7 (main_a7ddrphy_bitslip140[6]), + .D8 (main_a7ddrphy_bitslip140[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay14), + .TQ (main_a7ddrphy_dq_t14) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_14 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_14 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed14), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip141[7]), - .Q2(a7ddrphy_bitslip141[6]), - .Q3(a7ddrphy_bitslip141[5]), - .Q4(a7ddrphy_bitslip141[4]), - .Q5(a7ddrphy_bitslip141[3]), - .Q6(a7ddrphy_bitslip141[2]), - .Q7(a7ddrphy_bitslip141[1]), - .Q8(a7ddrphy_bitslip141[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed14), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip141[7]), + .Q2 (main_a7ddrphy_bitslip141[6]), + .Q3 (main_a7ddrphy_bitslip141[5]), + .Q4 (main_a7ddrphy_bitslip141[4]), + .Q5 (main_a7ddrphy_bitslip141[3]), + .Q6 (main_a7ddrphy_bitslip141[2]), + .Q7 (main_a7ddrphy_bitslip141[1]), + .Q8 (main_a7ddrphy_bitslip141[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_14 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_14 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay14), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed14) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay14), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed14) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_14 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_14( - .I(a7ddrphy_dq_o_nodelay14), - .T(a7ddrphy_dq_t14), - .IO(ddram_dq[14]), - .O(a7ddrphy_dq_i_nodelay14) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay14), + .T (main_a7ddrphy_dq_t14), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay14), + + // InOuts. + .IO (ddram_dq[14]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_46 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_46 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip150[0]), - .D2(a7ddrphy_bitslip150[1]), - .D3(a7ddrphy_bitslip150[2]), - .D4(a7ddrphy_bitslip150[3]), - .D5(a7ddrphy_bitslip150[4]), - .D6(a7ddrphy_bitslip150[5]), - .D7(a7ddrphy_bitslip150[6]), - .D8(a7ddrphy_bitslip150[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay15), - .TQ(a7ddrphy_dq_t15) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip150[0]), + .D2 (main_a7ddrphy_bitslip150[1]), + .D3 (main_a7ddrphy_bitslip150[2]), + .D4 (main_a7ddrphy_bitslip150[3]), + .D5 (main_a7ddrphy_bitslip150[4]), + .D6 (main_a7ddrphy_bitslip150[5]), + .D7 (main_a7ddrphy_bitslip150[6]), + .D8 (main_a7ddrphy_bitslip150[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay15), + .TQ (main_a7ddrphy_dq_t15) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_15 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_15 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed15), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip151[7]), - .Q2(a7ddrphy_bitslip151[6]), - .Q3(a7ddrphy_bitslip151[5]), - .Q4(a7ddrphy_bitslip151[4]), - .Q5(a7ddrphy_bitslip151[3]), - .Q6(a7ddrphy_bitslip151[2]), - .Q7(a7ddrphy_bitslip151[1]), - .Q8(a7ddrphy_bitslip151[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed15), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip151[7]), + .Q2 (main_a7ddrphy_bitslip151[6]), + .Q3 (main_a7ddrphy_bitslip151[5]), + .Q4 (main_a7ddrphy_bitslip151[4]), + .Q5 (main_a7ddrphy_bitslip151[3]), + .Q6 (main_a7ddrphy_bitslip151[2]), + .Q7 (main_a7ddrphy_bitslip151[1]), + .Q8 (main_a7ddrphy_bitslip151[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_15 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_15 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay15), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed15) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay15), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed15) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_15 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_15( - .I(a7ddrphy_dq_o_nodelay15), - .T(a7ddrphy_dq_t15), - .IO(ddram_dq[15]), - .O(a7ddrphy_dq_i_nodelay15) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay15), + .T (main_a7ddrphy_dq_t15), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay15), + + // InOuts. + .IO (ddram_dq[15]) ); //------------------------------------------------------------------------------ @@ -16075,14 +17219,14 @@ IOBUF IOBUF_15( reg [25:0] storage[0:15]; reg [25:0] storage_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine0_wrport_we) - storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w; - storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr]; + if (main_litedramcore_bankmachine0_wrport_we) + storage[main_litedramcore_bankmachine0_wrport_adr] <= main_litedramcore_bankmachine0_wrport_dat_w; + storage_dat0 <= storage[main_litedramcore_bankmachine0_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0; -assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr]; +assign main_litedramcore_bankmachine0_wrport_dat_r = storage_dat0; +assign main_litedramcore_bankmachine0_rdport_dat_r = storage[main_litedramcore_bankmachine0_rdport_adr]; //------------------------------------------------------------------------------ @@ -16093,14 +17237,14 @@ assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine reg [25:0] storage_1[0:15]; reg [25:0] storage_1_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine1_wrport_we) - storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w; - storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr]; + if (main_litedramcore_bankmachine1_wrport_we) + storage_1[main_litedramcore_bankmachine1_wrport_adr] <= main_litedramcore_bankmachine1_wrport_dat_w; + storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0; -assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr]; +assign main_litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0; +assign main_litedramcore_bankmachine1_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_rdport_adr]; //------------------------------------------------------------------------------ @@ -16111,14 +17255,14 @@ assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachi reg [25:0] storage_2[0:15]; reg [25:0] storage_2_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine2_wrport_we) - storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w; - storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr]; + if (main_litedramcore_bankmachine2_wrport_we) + storage_2[main_litedramcore_bankmachine2_wrport_adr] <= main_litedramcore_bankmachine2_wrport_dat_w; + storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0; -assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr]; +assign main_litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0; +assign main_litedramcore_bankmachine2_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_rdport_adr]; //------------------------------------------------------------------------------ @@ -16129,14 +17273,14 @@ assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachi reg [25:0] storage_3[0:15]; reg [25:0] storage_3_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine3_wrport_we) - storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w; - storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr]; + if (main_litedramcore_bankmachine3_wrport_we) + storage_3[main_litedramcore_bankmachine3_wrport_adr] <= main_litedramcore_bankmachine3_wrport_dat_w; + storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0; -assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr]; +assign main_litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0; +assign main_litedramcore_bankmachine3_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_rdport_adr]; //------------------------------------------------------------------------------ @@ -16147,14 +17291,14 @@ assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachi reg [25:0] storage_4[0:15]; reg [25:0] storage_4_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine4_wrport_we) - storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w; - storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr]; + if (main_litedramcore_bankmachine4_wrport_we) + storage_4[main_litedramcore_bankmachine4_wrport_adr] <= main_litedramcore_bankmachine4_wrport_dat_w; + storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0; -assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr]; +assign main_litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0; +assign main_litedramcore_bankmachine4_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_rdport_adr]; //------------------------------------------------------------------------------ @@ -16165,14 +17309,14 @@ assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachi reg [25:0] storage_5[0:15]; reg [25:0] storage_5_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine5_wrport_we) - storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w; - storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr]; + if (main_litedramcore_bankmachine5_wrport_we) + storage_5[main_litedramcore_bankmachine5_wrport_adr] <= main_litedramcore_bankmachine5_wrport_dat_w; + storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0; -assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr]; +assign main_litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0; +assign main_litedramcore_bankmachine5_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_rdport_adr]; //------------------------------------------------------------------------------ @@ -16183,14 +17327,14 @@ assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachi reg [25:0] storage_6[0:15]; reg [25:0] storage_6_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine6_wrport_we) - storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w; - storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr]; + if (main_litedramcore_bankmachine6_wrport_we) + storage_6[main_litedramcore_bankmachine6_wrport_adr] <= main_litedramcore_bankmachine6_wrport_dat_w; + storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0; -assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr]; +assign main_litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0; +assign main_litedramcore_bankmachine6_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_rdport_adr]; //------------------------------------------------------------------------------ @@ -16201,197 +17345,308 @@ assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachi reg [25:0] storage_7[0:15]; reg [25:0] storage_7_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine7_wrport_we) - storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w; - storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr]; + if (main_litedramcore_bankmachine7_wrport_we) + storage_7[main_litedramcore_bankmachine7_wrport_adr] <= main_litedramcore_bankmachine7_wrport_dat_w; + storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0; -assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr]; +assign main_litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0; +assign main_litedramcore_bankmachine7_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_rdport_adr]; +//------------------------------------------------------------------------------ +// Instance FDCE of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(reset), - .Q(litedramcore_reset0) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (main_reset), + + // Outputs. + .Q (builder_reset0) ); +//------------------------------------------------------------------------------ +// Instance FDCE_1 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_1( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset0), - .Q(litedramcore_reset1) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset0), + + // Outputs. + .Q (builder_reset1) ); +//------------------------------------------------------------------------------ +// Instance FDCE_2 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_2( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset1), - .Q(litedramcore_reset2) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset1), + + // Outputs. + .Q (builder_reset2) ); +//------------------------------------------------------------------------------ +// Instance FDCE_3 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_3( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset2), - .Q(litedramcore_reset3) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset2), + + // Outputs. + .Q (builder_reset3) ); +//------------------------------------------------------------------------------ +// Instance FDCE_4 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_4( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset3), - .Q(litedramcore_reset4) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset3), + + // Outputs. + .Q (builder_reset4) ); +//------------------------------------------------------------------------------ +// Instance FDCE_5 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_5( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset4), - .Q(litedramcore_reset5) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset4), + + // Outputs. + .Q (builder_reset5) ); +//------------------------------------------------------------------------------ +// Instance FDCE_6 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_6( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset5), - .Q(litedramcore_reset6) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset5), + + // Outputs. + .Q (builder_reset6) ); +//------------------------------------------------------------------------------ +// Instance FDCE_7 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_7( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset6), - .Q(litedramcore_reset7) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset6), + + // Outputs. + .Q (builder_reset7) ); +//------------------------------------------------------------------------------ +// Instance PLLE2_ADV of PLLE2_ADV Module. +//------------------------------------------------------------------------------ PLLE2_ADV #( - .CLKFBOUT_MULT(4'd8), - .CLKIN1_PERIOD(5.0), - .CLKOUT0_DIVIDE(4'd8), - .CLKOUT0_PHASE(1'd0), - .CLKOUT1_DIVIDE(5'd16), - .CLKOUT1_PHASE(1'd0), - .CLKOUT2_DIVIDE(3'd4), - .CLKOUT2_PHASE(1'd0), - .CLKOUT3_DIVIDE(3'd4), - .CLKOUT3_PHASE(7'd90), - .DIVCLK_DIVIDE(1'd1), - .REF_JITTER1(0.01), - .STARTUP_WAIT("FALSE") + // Parameters. + .CLKFBOUT_MULT (4'd8), + .CLKIN1_PERIOD (5.0), + .CLKOUT0_DIVIDE (4'd8), + .CLKOUT0_PHASE (1'd0), + .CLKOUT1_DIVIDE (5'd16), + .CLKOUT1_PHASE (1'd0), + .CLKOUT2_DIVIDE (3'd4), + .CLKOUT2_PHASE (1'd0), + .CLKOUT3_DIVIDE (3'd4), + .CLKOUT3_PHASE (7'd90), + .DIVCLK_DIVIDE (1'd1), + .REF_JITTER1 (0.01), + .STARTUP_WAIT ("FALSE") ) PLLE2_ADV ( - .CLKFBIN(litedramcore_pll_fb), - .CLKIN1(clkin), - .PWRDWN(power_down), - .RST(litedramcore_reset7), - .CLKFBOUT(litedramcore_pll_fb), - .CLKOUT0(clkout0), - .CLKOUT1(clkout1), - .CLKOUT2(clkout2), - .CLKOUT3(clkout3), - .LOCKED(locked) + // Inputs. + .CLKFBIN (builder_pll_fb), + .CLKIN1 (main_clkin), + .PWRDWN (main_power_down), + .RST (builder_reset7), + + // Outputs. + .CLKFBOUT (builder_pll_fb), + .CLKOUT0 (main_clkout0), + .CLKOUT1 (main_clkout1), + .CLKOUT2 (main_clkout2), + .CLKOUT3 (main_clkout3), + .LOCKED (main_locked) ); (* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE ( - .C(iodelay_clk), - .CE(1'd1), - .D(1'd0), - .PRE(xilinxasyncresetsynchronizerimpl0), - .Q(xilinxasyncresetsynchronizerimpl0_rst_meta) + // Inputs. + .C (iodelay_clk), + .CE (1'd1), + .D (1'd0), + .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl0_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_1 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_1 ( - .C(iodelay_clk), - .CE(1'd1), - .D(xilinxasyncresetsynchronizerimpl0_rst_meta), - .PRE(xilinxasyncresetsynchronizerimpl0), - .Q(iodelay_rst) + // Inputs. + .C (iodelay_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl0_rst_meta), + .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + + // Outputs. + .Q (iodelay_rst) ); (* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_2 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_2 ( - .C(sys_clk), - .CE(1'd1), - .D(1'd0), - .PRE(xilinxasyncresetsynchronizerimpl1), - .Q(xilinxasyncresetsynchronizerimpl1_rst_meta) + // Inputs. + .C (sys_clk), + .CE (1'd1), + .D (1'd0), + .PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl1_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_3 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_3 ( - .C(sys_clk), - .CE(1'd1), - .D(xilinxasyncresetsynchronizerimpl1_rst_meta), - .PRE(xilinxasyncresetsynchronizerimpl1), - .Q(sys_rst) + // Inputs. + .C (sys_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl1_rst_meta), + .PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset), + + // Outputs. + .Q (sys_rst) ); (* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_4 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_4 ( - .C(sys4x_clk), - .CE(1'd1), - .D(1'd0), - .PRE(xilinxasyncresetsynchronizerimpl2), - .Q(xilinxasyncresetsynchronizerimpl2_rst_meta) + // Inputs. + .C (sys4x_clk), + .CE (1'd1), + .D (1'd0), + .PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl2_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_5 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_5 ( - .C(sys4x_clk), - .CE(1'd1), - .D(xilinxasyncresetsynchronizerimpl2_rst_meta), - .PRE(xilinxasyncresetsynchronizerimpl2), - .Q(xilinxasyncresetsynchronizerimpl2_expr) + // Inputs. + .C (sys4x_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl2_rst_meta), + .PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl2_expr) ); (* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_6 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_6 ( - .C(sys4x_dqs_clk), - .CE(1'd1), - .D(1'd0), - .PRE(xilinxasyncresetsynchronizerimpl3), - .Q(xilinxasyncresetsynchronizerimpl3_rst_meta) + // Inputs. + .C (sys4x_dqs_clk), + .CE (1'd1), + .D (1'd0), + .PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl3_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_7 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_7 ( - .C(sys4x_dqs_clk), - .CE(1'd1), - .D(xilinxasyncresetsynchronizerimpl3_rst_meta), - .PRE(xilinxasyncresetsynchronizerimpl3), - .Q(xilinxasyncresetsynchronizerimpl3_expr) + // Inputs. + .C (sys4x_dqs_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl3_rst_meta), + .PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl3_expr) ); endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2022-10-28 19:01:23. +// Auto-Generated by LiteX on 2024-04-01 10:12:09. //------------------------------------------------------------------------------ diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init index 61e54f3..0573632 100644 --- a/litedram/generated/arty/litedram_core.init +++ b/litedram/generated/arty/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ff00782107c6 3d80000060215f00 798c07c6618c0000 -618c10e0658cff00 +618c10d4658cff00 4e8004217d8903a6 4e8004207c6903a6 0000000000000000 @@ -510,677 +510,687 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -392000003d40c000 -794a0020614a6004 -7d2057aa7c0004ac +3920000039406004 +7c0004ac654ac000 +600000007d2057aa 6000000060000000 6000000060000000 -4e80002060000000 +000000004e800020 0000000000000000 -3c4c000100000000 -7c0802a63842adc4 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203a46464f204853 7479622078257830 00000000000a7365 -2d2d2d2d2d2d2d2d +3033633733313738 0000000000000000 4d4152446574694c 6620746c69756220 @@ -1944,6 +1928,8 @@ ebe1fff8e8010010 52445320676e697a 3025783040204d41 000a2e2e2e786c38 +000000540000002a +6000000000000024 0000000042756c25 4b756c252e756c25 0000000000004269 diff --git a/litedram/generated/arty/litedram_core.v b/litedram/generated/arty/litedram_core.v index ea758b2..21cfb28 100644 --- a/litedram/generated/arty/litedram_core.v +++ b/litedram/generated/arty/litedram_core.v @@ -8,10 +8,11 @@ // // Filename : litedram_core.v // Device : -// LiteX sha1 : -------- -// Date : 2022-10-28 19:01:18 +// LiteX sha1 : 87137c30 +// Date : 2024-04-01 10:12:05 //------------------------------------------------------------------------------ +`timescale 1ns / 1ps //------------------------------------------------------------------------------ // Module @@ -19,4868 +20,5285 @@ module litedram_core ( input wire clk, - input wire rst, - output wire pll_locked, output wire [13:0] ddram_a, output wire [2:0] ddram_ba, - output wire ddram_ras_n, output wire ddram_cas_n, - output wire ddram_we_n, + output wire ddram_cke, + output wire ddram_clk_n, + output wire ddram_clk_p, output wire ddram_cs_n, output wire [1:0] ddram_dm, inout wire [15:0] ddram_dq, - inout wire [1:0] ddram_dqs_p, inout wire [1:0] ddram_dqs_n, - output wire ddram_clk_p, - output wire ddram_clk_n, - output wire ddram_cke, + inout wire [1:0] ddram_dqs_p, output wire ddram_odt, + output wire ddram_ras_n, output wire ddram_reset_n, + output wire ddram_we_n, output wire init_done, output wire init_error, - input wire [29:0] wb_ctrl_adr, - input wire [31:0] wb_ctrl_dat_w, - output wire [31:0] wb_ctrl_dat_r, - input wire [3:0] wb_ctrl_sel, - input wire wb_ctrl_cyc, - input wire wb_ctrl_stb, - output wire wb_ctrl_ack, - input wire wb_ctrl_we, - input wire [2:0] wb_ctrl_cti, - input wire [1:0] wb_ctrl_bte, - output wire wb_ctrl_err, + output wire pll_locked, + input wire rst, output wire user_clk, - output wire user_rst, - input wire user_port_native_0_cmd_valid, + input wire [23:0] user_port_native_0_cmd_addr, output wire user_port_native_0_cmd_ready, + input wire user_port_native_0_cmd_valid, input wire user_port_native_0_cmd_we, - input wire [23:0] user_port_native_0_cmd_addr, - input wire user_port_native_0_wdata_valid, + output wire [127:0] user_port_native_0_rdata_data, + input wire user_port_native_0_rdata_ready, + output wire user_port_native_0_rdata_valid, + input wire [127:0] user_port_native_0_wdata_data, output wire user_port_native_0_wdata_ready, + input wire user_port_native_0_wdata_valid, input wire [15:0] user_port_native_0_wdata_we, - input wire [127:0] user_port_native_0_wdata_data, - output wire user_port_native_0_rdata_valid, - input wire user_port_native_0_rdata_ready, - output wire [127:0] user_port_native_0_rdata_data + output wire user_rst, + output wire wb_ctrl_ack, + input wire [29:0] wb_ctrl_adr, + input wire [1:0] wb_ctrl_bte, + input wire [2:0] wb_ctrl_cti, + input wire wb_ctrl_cyc, + output wire [31:0] wb_ctrl_dat_r, + input wire [31:0] wb_ctrl_dat_w, + output wire wb_ctrl_err, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_stb, + input wire wb_ctrl_we ); +//------------------------------------------------------------------------------ +// Hierarchy +//------------------------------------------------------------------------------ + +/* +LiteDRAMCore +└─── bus (SoCBusHandler) +│ └─── _interconnect (InterconnectPointToPoint) +└─── csr (SoCCSRHandler) +└─── irq (SoCIRQHandler) +└─── cpu (CPUNone) +└─── crg (LiteDRAMS7DDRPHYCRG) +│ └─── pll (S7PLL) +│ │ └─── [BUFG] +│ │ └─── [BUFG] +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [BUFG] +│ │ └─── [BUFG] +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [PLLE2_ADV] +│ └─── idelayctrl (S7IDELAYCTRL) +│ │ └─── [IDELAYCTRL] +└─── ddrphy (A7DDRPHY) +│ └─── tappeddelayline_0* (TappedDelayLine) +│ └─── dqspattern_0* (DQSPattern) +│ └─── bitslip_0* (BitSlip) +│ └─── bitslip_1* (BitSlip) +│ └─── bitslip_2* (BitSlip) +│ └─── bitslip_3* (BitSlip) +│ └─── tappeddelayline_1* (TappedDelayLine) +│ └─── bitslip_4* (BitSlip) +│ └─── bitslip_5* (BitSlip) +│ └─── bitslip_6* (BitSlip) +│ └─── bitslip_7* (BitSlip) +│ └─── bitslip_8* (BitSlip) +│ └─── bitslip_9* (BitSlip) +│ └─── bitslip_10* (BitSlip) +│ └─── bitslip_11* (BitSlip) +│ └─── bitslip_12* (BitSlip) +│ └─── bitslip_13* (BitSlip) +│ └─── bitslip_14* (BitSlip) +│ └─── bitslip_15* (BitSlip) +│ └─── bitslip_16* (BitSlip) +│ └─── bitslip_17* (BitSlip) +│ └─── bitslip_18* (BitSlip) +│ └─── bitslip_19* (BitSlip) +│ └─── bitslip_20* (BitSlip) +│ └─── bitslip_21* (BitSlip) +│ └─── bitslip_22* (BitSlip) +│ └─── bitslip_23* (BitSlip) +│ └─── bitslip_24* (BitSlip) +│ └─── bitslip_25* (BitSlip) +│ └─── bitslip_26* (BitSlip) +│ └─── bitslip_27* (BitSlip) +│ └─── bitslip_28* (BitSlip) +│ └─── bitslip_29* (BitSlip) +│ └─── bitslip_30* (BitSlip) +│ └─── bitslip_31* (BitSlip) +│ └─── bitslip_32* (BitSlip) +│ └─── bitslip_33* (BitSlip) +│ └─── bitslip_34* (BitSlip) +│ └─── bitslip_35* (BitSlip) +│ └─── tappeddelayline_2* (TappedDelayLine) +│ └─── tappeddelayline_3* (TappedDelayLine) +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [ISERDESE2] +│ └─── [IOBUFDS] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUFDS] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [IDELAYE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [OBUFDS] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +└─── sdram (LiteDRAMCore) +│ └─── dfii (DFIInjector) +│ │ └─── pi0 (PhaseInjector) +│ │ └─── pi1 (PhaseInjector) +│ │ └─── pi2 (PhaseInjector) +│ │ └─── pi3 (PhaseInjector) +│ └─── controller (LiteDRAMController) +│ │ └─── refresher (Refresher) +│ │ │ └─── timer (RefreshTimer) +│ │ │ └─── postponer (RefreshPostponer) +│ │ │ └─── sequencer (RefreshSequencer) +│ │ │ │ └─── refreshexecuter_0* (RefreshExecuter) +│ │ │ └─── zqcs_timer (RefreshTimer) +│ │ │ └─── zqs_executer (ZQCSExecuter) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_0* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_1* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_2* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_3* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_4* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_5* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_6* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_7* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── multiplexer (Multiplexer) +│ │ │ └─── choose_cmd (_CommandChooser) +│ │ │ │ └─── roundrobin_0* (RoundRobin) +│ │ │ └─── choose_req (_CommandChooser) +│ │ │ │ └─── roundrobin_0* (RoundRobin) +│ │ │ └─── _steerer_0* (_Steerer) +│ │ │ └─── trrdcon (tXXDController) +│ │ │ └─── tfawcon (tFAWController) +│ │ │ └─── tccdcon (tXXDController) +│ │ │ └─── twtrcon (tXXDController) +│ │ │ └─── fsm (FSM) +│ └─── crossbar (LiteDRAMCrossbar) +│ │ └─── roundrobin_0* (RoundRobin) +│ │ └─── roundrobin_1* (RoundRobin) +│ │ └─── roundrobin_2* (RoundRobin) +│ │ └─── roundrobin_3* (RoundRobin) +│ │ └─── roundrobin_4* (RoundRobin) +│ │ └─── roundrobin_5* (RoundRobin) +│ │ └─── roundrobin_6* (RoundRobin) +│ │ └─── roundrobin_7* (RoundRobin) +└─── ddrctrl (LiteDRAMCoreControl) +└─── csr_bridge (Wishbone2CSR) +│ └─── fsm (FSM) +└─── csr_bankarray (CSRBankArray) +│ └─── csrbank_0* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ └─── csrbank_1* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstorage_4* (CSRStorage) +│ │ └─── csrstorage_5* (CSRStorage) +│ └─── csrbank_2* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstorage_4* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstorage_5* (CSRStorage) +│ │ └─── csrstorage_6* (CSRStorage) +│ │ └─── csrstorage_7* (CSRStorage) +│ │ └─── csrstorage_8* (CSRStorage) +│ │ └─── csrstatus_1* (CSRStatus) +│ │ └─── csrstorage_9* (CSRStorage) +│ │ └─── csrstorage_10* (CSRStorage) +│ │ └─── csrstorage_11* (CSRStorage) +│ │ └─── csrstorage_12* (CSRStorage) +│ │ └─── csrstatus_2* (CSRStatus) +│ │ └─── csrstorage_13* (CSRStorage) +│ │ └─── csrstorage_14* (CSRStorage) +│ │ └─── csrstorage_15* (CSRStorage) +│ │ └─── csrstorage_16* (CSRStorage) +│ │ └─── csrstatus_3* (CSRStatus) +└─── csr_interconnect (InterconnectShared) +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +* : Generated name. +[]: BlackBox. +*/ + //------------------------------------------------------------------------------ // Signals //------------------------------------------------------------------------------ -reg rst_1 = 1'd0; -wire sys_clk; -wire sys_rst; -wire sys4x_clk; -wire sys4x_dqs_clk; +wire [13:0] builder_adr; +reg [3:0] builder_bankmachine0_next_state = 4'd0; +reg [3:0] builder_bankmachine0_state = 4'd0; +reg [3:0] builder_bankmachine1_next_state = 4'd0; +reg [3:0] builder_bankmachine1_state = 4'd0; +reg [3:0] builder_bankmachine2_next_state = 4'd0; +reg [3:0] builder_bankmachine2_state = 4'd0; +reg [3:0] builder_bankmachine3_next_state = 4'd0; +reg [3:0] builder_bankmachine3_state = 4'd0; +reg [3:0] builder_bankmachine4_next_state = 4'd0; +reg [3:0] builder_bankmachine4_state = 4'd0; +reg [3:0] builder_bankmachine5_next_state = 4'd0; +reg [3:0] builder_bankmachine5_state = 4'd0; +reg [3:0] builder_bankmachine6_next_state = 4'd0; +reg [3:0] builder_bankmachine6_state = 4'd0; +reg [3:0] builder_bankmachine7_next_state = 4'd0; +reg [3:0] builder_bankmachine7_state = 4'd0; +wire builder_csrbank0_init_done0_r; +reg builder_csrbank0_init_done0_re = 1'd0; +wire builder_csrbank0_init_done0_w; +reg builder_csrbank0_init_done0_we = 1'd0; +wire builder_csrbank0_init_error0_r; +reg builder_csrbank0_init_error0_re = 1'd0; +wire builder_csrbank0_init_error0_w; +reg builder_csrbank0_init_error0_we = 1'd0; +wire builder_csrbank0_sel; +wire [1:0] builder_csrbank1_dly_sel0_r; +reg builder_csrbank1_dly_sel0_re = 1'd0; +wire [1:0] builder_csrbank1_dly_sel0_w; +reg builder_csrbank1_dly_sel0_we = 1'd0; +wire [4:0] builder_csrbank1_half_sys8x_taps0_r; +reg builder_csrbank1_half_sys8x_taps0_re = 1'd0; +wire [4:0] builder_csrbank1_half_sys8x_taps0_w; +reg builder_csrbank1_half_sys8x_taps0_we = 1'd0; +wire [1:0] builder_csrbank1_rdphase0_r; +reg builder_csrbank1_rdphase0_re = 1'd0; +wire [1:0] builder_csrbank1_rdphase0_w; +reg builder_csrbank1_rdphase0_we = 1'd0; +wire builder_csrbank1_rst0_r; +reg builder_csrbank1_rst0_re = 1'd0; +wire builder_csrbank1_rst0_w; +reg builder_csrbank1_rst0_we = 1'd0; +wire builder_csrbank1_sel; +wire builder_csrbank1_wlevel_en0_r; +reg builder_csrbank1_wlevel_en0_re = 1'd0; +wire builder_csrbank1_wlevel_en0_w; +reg builder_csrbank1_wlevel_en0_we = 1'd0; +wire [1:0] builder_csrbank1_wrphase0_r; +reg builder_csrbank1_wrphase0_re = 1'd0; +wire [1:0] builder_csrbank1_wrphase0_w; +reg builder_csrbank1_wrphase0_we = 1'd0; +wire [3:0] builder_csrbank2_dfii_control0_r; +reg builder_csrbank2_dfii_control0_re = 1'd0; +wire [3:0] builder_csrbank2_dfii_control0_w; +reg builder_csrbank2_dfii_control0_we = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi0_address0_r; +reg builder_csrbank2_dfii_pi0_address0_re = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi0_address0_w; +reg builder_csrbank2_dfii_pi0_address0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r; +reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w; +reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_command0_r; +reg builder_csrbank2_dfii_pi0_command0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_command0_w; +reg builder_csrbank2_dfii_pi0_command0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_rddata_r; +reg builder_csrbank2_dfii_pi0_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_rddata_w; +reg builder_csrbank2_dfii_pi0_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_r; +reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_w; +reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi1_address0_r; +reg builder_csrbank2_dfii_pi1_address0_re = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi1_address0_w; +reg builder_csrbank2_dfii_pi1_address0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r; +reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w; +reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_command0_r; +reg builder_csrbank2_dfii_pi1_command0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_command0_w; +reg builder_csrbank2_dfii_pi1_command0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_rddata_r; +reg builder_csrbank2_dfii_pi1_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_rddata_w; +reg builder_csrbank2_dfii_pi1_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_r; +reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_w; +reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi2_address0_r; +reg builder_csrbank2_dfii_pi2_address0_re = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi2_address0_w; +reg builder_csrbank2_dfii_pi2_address0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r; +reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w; +reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_command0_r; +reg builder_csrbank2_dfii_pi2_command0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_command0_w; +reg builder_csrbank2_dfii_pi2_command0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_rddata_r; +reg builder_csrbank2_dfii_pi2_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_rddata_w; +reg builder_csrbank2_dfii_pi2_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_r; +reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_w; +reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi3_address0_r; +reg builder_csrbank2_dfii_pi3_address0_re = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi3_address0_w; +reg builder_csrbank2_dfii_pi3_address0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r; +reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w; +reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_command0_r; +reg builder_csrbank2_dfii_pi3_command0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_command0_w; +reg builder_csrbank2_dfii_pi3_command0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_rddata_r; +reg builder_csrbank2_dfii_pi3_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_rddata_w; +reg builder_csrbank2_dfii_pi3_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_r; +reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_w; +reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0; +wire builder_csrbank2_sel; +wire [31:0] builder_dat_r; +wire [31:0] builder_dat_w; +reg builder_interface0_ack = 1'd0; +wire [29:0] builder_interface0_adr; +wire [13:0] builder_interface0_bank_bus_adr; +reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface0_bank_bus_dat_w; +wire builder_interface0_bank_bus_we; +wire [1:0] builder_interface0_bte; +wire [2:0] builder_interface0_cti; +wire builder_interface0_cyc; +reg [31:0] builder_interface0_dat_r = 32'd0; +wire [31:0] builder_interface0_dat_w; +reg builder_interface0_err = 1'd0; +wire [3:0] builder_interface0_sel; +wire builder_interface0_stb; +wire builder_interface0_we; +reg [13:0] builder_interface1_adr = 14'd0; +reg [13:0] builder_interface1_adr_next_value1 = 14'd0; +reg builder_interface1_adr_next_value_ce1 = 1'd0; +wire [13:0] builder_interface1_bank_bus_adr; +reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface1_bank_bus_dat_w; +wire builder_interface1_bank_bus_we; +wire [31:0] builder_interface1_dat_r; +reg [31:0] builder_interface1_dat_w = 32'd0; +reg [31:0] builder_interface1_dat_w_next_value0 = 32'd0; +reg builder_interface1_dat_w_next_value_ce0 = 1'd0; +reg builder_interface1_we = 1'd0; +reg builder_interface1_we_next_value2 = 1'd0; +reg builder_interface1_we_next_value_ce2 = 1'd0; +wire [13:0] builder_interface2_bank_bus_adr; +reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface2_bank_bus_dat_w; +wire builder_interface2_bank_bus_we; +reg builder_locked0 = 1'd0; +reg builder_locked1 = 1'd0; +reg builder_locked2 = 1'd0; +reg builder_locked3 = 1'd0; +reg builder_locked4 = 1'd0; +reg builder_locked5 = 1'd0; +reg builder_locked6 = 1'd0; +reg builder_locked7 = 1'd0; +reg [3:0] builder_multiplexer_next_state = 4'd0; +reg [3:0] builder_multiplexer_state = 4'd0; +reg builder_new_master_rdata_valid0 = 1'd0; +reg builder_new_master_rdata_valid1 = 1'd0; +reg builder_new_master_rdata_valid2 = 1'd0; +reg builder_new_master_rdata_valid3 = 1'd0; +reg builder_new_master_rdata_valid4 = 1'd0; +reg builder_new_master_rdata_valid5 = 1'd0; +reg builder_new_master_rdata_valid6 = 1'd0; +reg builder_new_master_rdata_valid7 = 1'd0; +reg builder_new_master_rdata_valid8 = 1'd0; +reg builder_new_master_wdata_ready0 = 1'd0; +reg builder_new_master_wdata_ready1 = 1'd0; +reg [1:0] builder_next_state = 2'd0; +wire builder_pll_fb; +reg [1:0] builder_refresher_next_state = 2'd0; +reg [1:0] builder_refresher_state = 2'd0; +wire builder_reset0; +wire builder_reset1; +wire builder_reset2; +wire builder_reset3; +wire builder_reset4; +wire builder_reset5; +wire builder_reset6; +wire builder_reset7; +reg builder_rhs_self0 = 1'd0; +reg [13:0] builder_rhs_self1 = 14'd0; +reg builder_rhs_self10 = 1'd0; +reg builder_rhs_self11 = 1'd0; +reg [20:0] builder_rhs_self12 = 21'd0; +reg builder_rhs_self13 = 1'd0; +reg builder_rhs_self14 = 1'd0; +reg [20:0] builder_rhs_self15 = 21'd0; +reg builder_rhs_self16 = 1'd0; +reg builder_rhs_self17 = 1'd0; +reg [20:0] builder_rhs_self18 = 21'd0; +reg builder_rhs_self19 = 1'd0; +reg [2:0] builder_rhs_self2 = 3'd0; +reg builder_rhs_self20 = 1'd0; +reg [20:0] builder_rhs_self21 = 21'd0; +reg builder_rhs_self22 = 1'd0; +reg builder_rhs_self23 = 1'd0; +reg [20:0] builder_rhs_self24 = 21'd0; +reg builder_rhs_self25 = 1'd0; +reg builder_rhs_self26 = 1'd0; +reg [20:0] builder_rhs_self27 = 21'd0; +reg builder_rhs_self28 = 1'd0; +reg builder_rhs_self29 = 1'd0; +reg builder_rhs_self3 = 1'd0; +reg [20:0] builder_rhs_self30 = 21'd0; +reg builder_rhs_self31 = 1'd0; +reg builder_rhs_self32 = 1'd0; +reg [20:0] builder_rhs_self33 = 21'd0; +reg builder_rhs_self34 = 1'd0; +reg builder_rhs_self35 = 1'd0; +reg builder_rhs_self4 = 1'd0; +reg builder_rhs_self5 = 1'd0; +reg builder_rhs_self6 = 1'd0; +reg [13:0] builder_rhs_self7 = 14'd0; +reg [2:0] builder_rhs_self8 = 3'd0; +reg builder_rhs_self9 = 1'd0; +wire builder_roundrobin0_ce; +wire builder_roundrobin0_grant; +wire builder_roundrobin0_request; +wire builder_roundrobin1_ce; +wire builder_roundrobin1_grant; +wire builder_roundrobin1_request; +wire builder_roundrobin2_ce; +wire builder_roundrobin2_grant; +wire builder_roundrobin2_request; +wire builder_roundrobin3_ce; +wire builder_roundrobin3_grant; +wire builder_roundrobin3_request; +wire builder_roundrobin4_ce; +wire builder_roundrobin4_grant; +wire builder_roundrobin4_request; +wire builder_roundrobin5_ce; +wire builder_roundrobin5_grant; +wire builder_roundrobin5_request; +wire builder_roundrobin6_ce; +wire builder_roundrobin6_grant; +wire builder_roundrobin6_request; +wire builder_roundrobin7_ce; +wire builder_roundrobin7_grant; +wire builder_roundrobin7_request; +reg [2:0] builder_self0 = 3'd0; +reg [13:0] builder_self1 = 14'd0; +reg builder_self10 = 1'd0; +reg builder_self11 = 1'd0; +reg builder_self12 = 1'd0; +reg builder_self13 = 1'd0; +reg [2:0] builder_self14 = 3'd0; +reg [13:0] builder_self15 = 14'd0; +reg builder_self16 = 1'd0; +reg builder_self17 = 1'd0; +reg builder_self18 = 1'd0; +reg builder_self19 = 1'd0; +reg builder_self2 = 1'd0; +reg builder_self20 = 1'd0; +reg [2:0] builder_self21 = 3'd0; +reg [13:0] builder_self22 = 14'd0; +reg builder_self23 = 1'd0; +reg builder_self24 = 1'd0; +reg builder_self25 = 1'd0; +reg builder_self26 = 1'd0; +reg builder_self27 = 1'd0; +reg builder_self3 = 1'd0; +reg builder_self4 = 1'd0; +reg builder_self5 = 1'd0; +reg builder_self6 = 1'd0; +reg [2:0] builder_self7 = 3'd0; +reg [13:0] builder_self8 = 14'd0; +reg builder_self9 = 1'd0; +reg [1:0] builder_state = 2'd0; +reg builder_t_self0 = 1'd0; +reg builder_t_self1 = 1'd0; +reg builder_t_self2 = 1'd0; +reg builder_t_self3 = 1'd0; +reg builder_t_self4 = 1'd0; +reg builder_t_self5 = 1'd0; +wire builder_we; +wire builder_xilinxasyncresetsynchronizerimpl0_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl1_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl2_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl2_expr; +wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl3_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl3_expr; +wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta; wire iodelay_clk; wire iodelay_rst; -wire reset; -reg power_down = 1'd0; -wire locked; -wire clkin; -wire clkout0; -wire clkout_buf0; -wire clkout1; -wire clkout_buf1; -wire clkout2; -wire clkout_buf2; -wire clkout3; -wire clkout_buf3; -reg [3:0] reset_counter = 4'd15; -reg ic_reset = 1'd1; -reg a7ddrphy_rst_storage = 1'd0; -reg a7ddrphy_rst_re = 1'd0; -reg [1:0] a7ddrphy_dly_sel_storage = 2'd0; -reg a7ddrphy_dly_sel_re = 1'd0; -reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8; -reg a7ddrphy_half_sys8x_taps_re = 1'd0; -reg a7ddrphy_wlevel_en_storage = 1'd0; -reg a7ddrphy_wlevel_en_re = 1'd0; -reg a7ddrphy_wlevel_strobe_re = 1'd0; -wire a7ddrphy_wlevel_strobe_r; -reg a7ddrphy_wlevel_strobe_we = 1'd0; -reg a7ddrphy_wlevel_strobe_w = 1'd0; -reg a7ddrphy_rdly_dq_rst_re = 1'd0; -wire a7ddrphy_rdly_dq_rst_r; -reg a7ddrphy_rdly_dq_rst_we = 1'd0; -reg a7ddrphy_rdly_dq_rst_w = 1'd0; -reg a7ddrphy_rdly_dq_inc_re = 1'd0; -wire a7ddrphy_rdly_dq_inc_r; -reg a7ddrphy_rdly_dq_inc_we = 1'd0; -reg a7ddrphy_rdly_dq_inc_w = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; -wire a7ddrphy_rdly_dq_bitslip_rst_r; -reg a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_re = 1'd0; -wire a7ddrphy_rdly_dq_bitslip_r; -reg a7ddrphy_rdly_dq_bitslip_we = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_w = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; -wire a7ddrphy_wdly_dq_bitslip_rst_r; -reg a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_re = 1'd0; -wire a7ddrphy_wdly_dq_bitslip_r; -reg a7ddrphy_wdly_dq_bitslip_we = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_w = 1'd0; -reg [1:0] a7ddrphy_rdphase_storage = 2'd2; -reg a7ddrphy_rdphase_re = 1'd0; -reg [1:0] a7ddrphy_wrphase_storage = 2'd3; -reg a7ddrphy_wrphase_re = 1'd0; -wire [13:0] a7ddrphy_dfi_p0_address; -wire [2:0] a7ddrphy_dfi_p0_bank; -wire a7ddrphy_dfi_p0_cas_n; -wire a7ddrphy_dfi_p0_cs_n; -wire a7ddrphy_dfi_p0_ras_n; -wire a7ddrphy_dfi_p0_we_n; -wire a7ddrphy_dfi_p0_cke; -wire a7ddrphy_dfi_p0_odt; -wire a7ddrphy_dfi_p0_reset_n; -wire a7ddrphy_dfi_p0_act_n; -wire [31:0] a7ddrphy_dfi_p0_wrdata; -wire a7ddrphy_dfi_p0_wrdata_en; -wire [3:0] a7ddrphy_dfi_p0_wrdata_mask; -wire a7ddrphy_dfi_p0_rddata_en; -reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0; -wire a7ddrphy_dfi_p0_rddata_valid; -wire [13:0] a7ddrphy_dfi_p1_address; -wire [2:0] a7ddrphy_dfi_p1_bank; -wire a7ddrphy_dfi_p1_cas_n; -wire a7ddrphy_dfi_p1_cs_n; -wire a7ddrphy_dfi_p1_ras_n; -wire a7ddrphy_dfi_p1_we_n; -wire a7ddrphy_dfi_p1_cke; -wire a7ddrphy_dfi_p1_odt; -wire a7ddrphy_dfi_p1_reset_n; -wire a7ddrphy_dfi_p1_act_n; -wire [31:0] a7ddrphy_dfi_p1_wrdata; -wire a7ddrphy_dfi_p1_wrdata_en; -wire [3:0] a7ddrphy_dfi_p1_wrdata_mask; -wire a7ddrphy_dfi_p1_rddata_en; -reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0; -wire a7ddrphy_dfi_p1_rddata_valid; -wire [13:0] a7ddrphy_dfi_p2_address; -wire [2:0] a7ddrphy_dfi_p2_bank; -wire a7ddrphy_dfi_p2_cas_n; -wire a7ddrphy_dfi_p2_cs_n; -wire a7ddrphy_dfi_p2_ras_n; -wire a7ddrphy_dfi_p2_we_n; -wire a7ddrphy_dfi_p2_cke; -wire a7ddrphy_dfi_p2_odt; -wire a7ddrphy_dfi_p2_reset_n; -wire a7ddrphy_dfi_p2_act_n; -wire [31:0] a7ddrphy_dfi_p2_wrdata; -wire a7ddrphy_dfi_p2_wrdata_en; -wire [3:0] a7ddrphy_dfi_p2_wrdata_mask; -wire a7ddrphy_dfi_p2_rddata_en; -reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0; -wire a7ddrphy_dfi_p2_rddata_valid; -wire [13:0] a7ddrphy_dfi_p3_address; -wire [2:0] a7ddrphy_dfi_p3_bank; -wire a7ddrphy_dfi_p3_cas_n; -wire a7ddrphy_dfi_p3_cs_n; -wire a7ddrphy_dfi_p3_ras_n; -wire a7ddrphy_dfi_p3_we_n; -wire a7ddrphy_dfi_p3_cke; -wire a7ddrphy_dfi_p3_odt; -wire a7ddrphy_dfi_p3_reset_n; -wire a7ddrphy_dfi_p3_act_n; -wire [31:0] a7ddrphy_dfi_p3_wrdata; -wire a7ddrphy_dfi_p3_wrdata_en; -wire [3:0] a7ddrphy_dfi_p3_wrdata_mask; -wire a7ddrphy_dfi_p3_rddata_en; -reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0; -wire a7ddrphy_dfi_p3_rddata_valid; -wire a7ddrphy_sd_clk_se_nodelay; -wire [2:0] a7ddrphy_pads_ba; -reg a7ddrphy_dqs_oe = 1'd0; -wire a7ddrphy_dqs_preamble; -wire a7ddrphy_dqs_postamble; -wire a7ddrphy_dqs_oe_delay_tappeddelayline; -reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -reg a7ddrphy_dqspattern0 = 1'd0; -reg a7ddrphy_dqspattern1 = 1'd0; -reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0; -reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0; -wire a7ddrphy_dqs_o_no_delay0; -wire a7ddrphy_dqs_t0; -reg [7:0] a7ddrphy_bitslip00 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r0 = 16'd0; -wire a7ddrphy0; -wire a7ddrphy_dqs_o_no_delay1; -wire a7ddrphy_dqs_t1; -reg [7:0] a7ddrphy_bitslip10 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r0 = 16'd0; -wire a7ddrphy1; -reg [7:0] a7ddrphy_bitslip01 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r1 = 16'd0; -reg [7:0] a7ddrphy_bitslip11 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r1 = 16'd0; -wire a7ddrphy_dq_oe; -wire a7ddrphy_dq_oe_delay_tappeddelayline; -reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -wire a7ddrphy_dq_o_nodelay0; -wire a7ddrphy_dq_i_nodelay0; -wire a7ddrphy_dq_i_delayed0; -wire a7ddrphy_dq_t0; -reg [7:0] a7ddrphy_bitslip02 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value2 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r2 = 16'd0; -wire [7:0] a7ddrphy_bitslip03; -reg [7:0] a7ddrphy_bitslip04 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value3 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r3 = 16'd0; -wire a7ddrphy_dq_o_nodelay1; -wire a7ddrphy_dq_i_nodelay1; -wire a7ddrphy_dq_i_delayed1; -wire a7ddrphy_dq_t1; -reg [7:0] a7ddrphy_bitslip12 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value2 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r2 = 16'd0; -wire [7:0] a7ddrphy_bitslip13; -reg [7:0] a7ddrphy_bitslip14 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value3 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r3 = 16'd0; -wire a7ddrphy_dq_o_nodelay2; -wire a7ddrphy_dq_i_nodelay2; -wire a7ddrphy_dq_i_delayed2; -wire a7ddrphy_dq_t2; -reg [7:0] a7ddrphy_bitslip20 = 8'd0; -reg [2:0] a7ddrphy_bitslip2_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip2_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip21; -reg [7:0] a7ddrphy_bitslip22 = 8'd0; -reg [2:0] a7ddrphy_bitslip2_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip2_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay3; -wire a7ddrphy_dq_i_nodelay3; -wire a7ddrphy_dq_i_delayed3; -wire a7ddrphy_dq_t3; -reg [7:0] a7ddrphy_bitslip30 = 8'd0; -reg [2:0] a7ddrphy_bitslip3_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip3_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip31; -reg [7:0] a7ddrphy_bitslip32 = 8'd0; -reg [2:0] a7ddrphy_bitslip3_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip3_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay4; -wire a7ddrphy_dq_i_nodelay4; -wire a7ddrphy_dq_i_delayed4; -wire a7ddrphy_dq_t4; -reg [7:0] a7ddrphy_bitslip40 = 8'd0; -reg [2:0] a7ddrphy_bitslip4_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip4_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip41; -reg [7:0] a7ddrphy_bitslip42 = 8'd0; -reg [2:0] a7ddrphy_bitslip4_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip4_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay5; -wire a7ddrphy_dq_i_nodelay5; -wire a7ddrphy_dq_i_delayed5; -wire a7ddrphy_dq_t5; -reg [7:0] a7ddrphy_bitslip50 = 8'd0; -reg [2:0] a7ddrphy_bitslip5_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip5_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip51; -reg [7:0] a7ddrphy_bitslip52 = 8'd0; -reg [2:0] a7ddrphy_bitslip5_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip5_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay6; -wire a7ddrphy_dq_i_nodelay6; -wire a7ddrphy_dq_i_delayed6; -wire a7ddrphy_dq_t6; -reg [7:0] a7ddrphy_bitslip60 = 8'd0; -reg [2:0] a7ddrphy_bitslip6_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip6_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip61; -reg [7:0] a7ddrphy_bitslip62 = 8'd0; -reg [2:0] a7ddrphy_bitslip6_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip6_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay7; -wire a7ddrphy_dq_i_nodelay7; -wire a7ddrphy_dq_i_delayed7; -wire a7ddrphy_dq_t7; -reg [7:0] a7ddrphy_bitslip70 = 8'd0; -reg [2:0] a7ddrphy_bitslip7_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip7_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip71; -reg [7:0] a7ddrphy_bitslip72 = 8'd0; -reg [2:0] a7ddrphy_bitslip7_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip7_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay8; -wire a7ddrphy_dq_i_nodelay8; -wire a7ddrphy_dq_i_delayed8; -wire a7ddrphy_dq_t8; -reg [7:0] a7ddrphy_bitslip80 = 8'd0; -reg [2:0] a7ddrphy_bitslip8_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip8_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip81; -reg [7:0] a7ddrphy_bitslip82 = 8'd0; -reg [2:0] a7ddrphy_bitslip8_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip8_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay9; -wire a7ddrphy_dq_i_nodelay9; -wire a7ddrphy_dq_i_delayed9; -wire a7ddrphy_dq_t9; -reg [7:0] a7ddrphy_bitslip90 = 8'd0; -reg [2:0] a7ddrphy_bitslip9_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip9_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip91; -reg [7:0] a7ddrphy_bitslip92 = 8'd0; -reg [2:0] a7ddrphy_bitslip9_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip9_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay10; -wire a7ddrphy_dq_i_nodelay10; -wire a7ddrphy_dq_i_delayed10; -wire a7ddrphy_dq_t10; -reg [7:0] a7ddrphy_bitslip100 = 8'd0; -reg [2:0] a7ddrphy_bitslip10_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip10_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip101; -reg [7:0] a7ddrphy_bitslip102 = 8'd0; -reg [2:0] a7ddrphy_bitslip10_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip10_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay11; -wire a7ddrphy_dq_i_nodelay11; -wire a7ddrphy_dq_i_delayed11; -wire a7ddrphy_dq_t11; -reg [7:0] a7ddrphy_bitslip110 = 8'd0; -reg [2:0] a7ddrphy_bitslip11_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip11_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip111; -reg [7:0] a7ddrphy_bitslip112 = 8'd0; -reg [2:0] a7ddrphy_bitslip11_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip11_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay12; -wire a7ddrphy_dq_i_nodelay12; -wire a7ddrphy_dq_i_delayed12; -wire a7ddrphy_dq_t12; -reg [7:0] a7ddrphy_bitslip120 = 8'd0; -reg [2:0] a7ddrphy_bitslip12_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip12_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip121; -reg [7:0] a7ddrphy_bitslip122 = 8'd0; -reg [2:0] a7ddrphy_bitslip12_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip12_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay13; -wire a7ddrphy_dq_i_nodelay13; -wire a7ddrphy_dq_i_delayed13; -wire a7ddrphy_dq_t13; -reg [7:0] a7ddrphy_bitslip130 = 8'd0; -reg [2:0] a7ddrphy_bitslip13_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip13_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip131; -reg [7:0] a7ddrphy_bitslip132 = 8'd0; -reg [2:0] a7ddrphy_bitslip13_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip13_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay14; -wire a7ddrphy_dq_i_nodelay14; -wire a7ddrphy_dq_i_delayed14; -wire a7ddrphy_dq_t14; -reg [7:0] a7ddrphy_bitslip140 = 8'd0; -reg [2:0] a7ddrphy_bitslip14_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip14_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip141; -reg [7:0] a7ddrphy_bitslip142 = 8'd0; -reg [2:0] a7ddrphy_bitslip14_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip14_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay15; -wire a7ddrphy_dq_i_nodelay15; -wire a7ddrphy_dq_i_delayed15; -wire a7ddrphy_dq_t15; -reg [7:0] a7ddrphy_bitslip150 = 8'd0; -reg [2:0] a7ddrphy_bitslip15_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip15_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip151; -reg [7:0] a7ddrphy_bitslip152 = 8'd0; -reg [2:0] a7ddrphy_bitslip15_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip15_r1 = 16'd0; -reg a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; -reg a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; -reg a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; -reg a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; -wire [13:0] litedramcore_slave_p0_address; -wire [2:0] litedramcore_slave_p0_bank; -wire litedramcore_slave_p0_cas_n; -wire litedramcore_slave_p0_cs_n; -wire litedramcore_slave_p0_ras_n; -wire litedramcore_slave_p0_we_n; -wire litedramcore_slave_p0_cke; -wire litedramcore_slave_p0_odt; -wire litedramcore_slave_p0_reset_n; -wire litedramcore_slave_p0_act_n; -wire [31:0] litedramcore_slave_p0_wrdata; -wire litedramcore_slave_p0_wrdata_en; -wire [3:0] litedramcore_slave_p0_wrdata_mask; -wire litedramcore_slave_p0_rddata_en; -reg [31:0] litedramcore_slave_p0_rddata = 32'd0; -reg litedramcore_slave_p0_rddata_valid = 1'd0; -wire [13:0] litedramcore_slave_p1_address; -wire [2:0] litedramcore_slave_p1_bank; -wire litedramcore_slave_p1_cas_n; -wire litedramcore_slave_p1_cs_n; -wire litedramcore_slave_p1_ras_n; -wire litedramcore_slave_p1_we_n; -wire litedramcore_slave_p1_cke; -wire litedramcore_slave_p1_odt; -wire litedramcore_slave_p1_reset_n; -wire litedramcore_slave_p1_act_n; -wire [31:0] litedramcore_slave_p1_wrdata; -wire litedramcore_slave_p1_wrdata_en; -wire [3:0] litedramcore_slave_p1_wrdata_mask; -wire litedramcore_slave_p1_rddata_en; -reg [31:0] litedramcore_slave_p1_rddata = 32'd0; -reg litedramcore_slave_p1_rddata_valid = 1'd0; -wire [13:0] litedramcore_slave_p2_address; -wire [2:0] litedramcore_slave_p2_bank; -wire litedramcore_slave_p2_cas_n; -wire litedramcore_slave_p2_cs_n; -wire litedramcore_slave_p2_ras_n; -wire litedramcore_slave_p2_we_n; -wire litedramcore_slave_p2_cke; -wire litedramcore_slave_p2_odt; -wire litedramcore_slave_p2_reset_n; -wire litedramcore_slave_p2_act_n; -wire [31:0] litedramcore_slave_p2_wrdata; -wire litedramcore_slave_p2_wrdata_en; -wire [3:0] litedramcore_slave_p2_wrdata_mask; -wire litedramcore_slave_p2_rddata_en; -reg [31:0] litedramcore_slave_p2_rddata = 32'd0; -reg litedramcore_slave_p2_rddata_valid = 1'd0; -wire [13:0] litedramcore_slave_p3_address; -wire [2:0] litedramcore_slave_p3_bank; -wire litedramcore_slave_p3_cas_n; -wire litedramcore_slave_p3_cs_n; -wire litedramcore_slave_p3_ras_n; -wire litedramcore_slave_p3_we_n; -wire litedramcore_slave_p3_cke; -wire litedramcore_slave_p3_odt; -wire litedramcore_slave_p3_reset_n; -wire litedramcore_slave_p3_act_n; -wire [31:0] litedramcore_slave_p3_wrdata; -wire litedramcore_slave_p3_wrdata_en; -wire [3:0] litedramcore_slave_p3_wrdata_mask; -wire litedramcore_slave_p3_rddata_en; -reg [31:0] litedramcore_slave_p3_rddata = 32'd0; -reg litedramcore_slave_p3_rddata_valid = 1'd0; -reg [13:0] litedramcore_master_p0_address = 14'd0; -reg [2:0] litedramcore_master_p0_bank = 3'd0; -reg litedramcore_master_p0_cas_n = 1'd1; -reg litedramcore_master_p0_cs_n = 1'd1; -reg litedramcore_master_p0_ras_n = 1'd1; -reg litedramcore_master_p0_we_n = 1'd1; -reg litedramcore_master_p0_cke = 1'd0; -reg litedramcore_master_p0_odt = 1'd0; -reg litedramcore_master_p0_reset_n = 1'd0; -reg litedramcore_master_p0_act_n = 1'd1; -reg [31:0] litedramcore_master_p0_wrdata = 32'd0; -reg litedramcore_master_p0_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0; -reg litedramcore_master_p0_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p0_rddata; -wire litedramcore_master_p0_rddata_valid; -reg [13:0] litedramcore_master_p1_address = 14'd0; -reg [2:0] litedramcore_master_p1_bank = 3'd0; -reg litedramcore_master_p1_cas_n = 1'd1; -reg litedramcore_master_p1_cs_n = 1'd1; -reg litedramcore_master_p1_ras_n = 1'd1; -reg litedramcore_master_p1_we_n = 1'd1; -reg litedramcore_master_p1_cke = 1'd0; -reg litedramcore_master_p1_odt = 1'd0; -reg litedramcore_master_p1_reset_n = 1'd0; -reg litedramcore_master_p1_act_n = 1'd1; -reg [31:0] litedramcore_master_p1_wrdata = 32'd0; -reg litedramcore_master_p1_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0; -reg litedramcore_master_p1_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p1_rddata; -wire litedramcore_master_p1_rddata_valid; -reg [13:0] litedramcore_master_p2_address = 14'd0; -reg [2:0] litedramcore_master_p2_bank = 3'd0; -reg litedramcore_master_p2_cas_n = 1'd1; -reg litedramcore_master_p2_cs_n = 1'd1; -reg litedramcore_master_p2_ras_n = 1'd1; -reg litedramcore_master_p2_we_n = 1'd1; -reg litedramcore_master_p2_cke = 1'd0; -reg litedramcore_master_p2_odt = 1'd0; -reg litedramcore_master_p2_reset_n = 1'd0; -reg litedramcore_master_p2_act_n = 1'd1; -reg [31:0] litedramcore_master_p2_wrdata = 32'd0; -reg litedramcore_master_p2_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0; -reg litedramcore_master_p2_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p2_rddata; -wire litedramcore_master_p2_rddata_valid; -reg [13:0] litedramcore_master_p3_address = 14'd0; -reg [2:0] litedramcore_master_p3_bank = 3'd0; -reg litedramcore_master_p3_cas_n = 1'd1; -reg litedramcore_master_p3_cs_n = 1'd1; -reg litedramcore_master_p3_ras_n = 1'd1; -reg litedramcore_master_p3_we_n = 1'd1; -reg litedramcore_master_p3_cke = 1'd0; -reg litedramcore_master_p3_odt = 1'd0; -reg litedramcore_master_p3_reset_n = 1'd0; -reg litedramcore_master_p3_act_n = 1'd1; -reg [31:0] litedramcore_master_p3_wrdata = 32'd0; -reg litedramcore_master_p3_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0; -reg litedramcore_master_p3_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p3_rddata; -wire litedramcore_master_p3_rddata_valid; -wire [13:0] litedramcore_csr_dfi_p0_address; -wire [2:0] litedramcore_csr_dfi_p0_bank; -reg litedramcore_csr_dfi_p0_cas_n = 1'd1; -reg litedramcore_csr_dfi_p0_cs_n = 1'd1; -reg litedramcore_csr_dfi_p0_ras_n = 1'd1; -reg litedramcore_csr_dfi_p0_we_n = 1'd1; -wire litedramcore_csr_dfi_p0_cke; -wire litedramcore_csr_dfi_p0_odt; -wire litedramcore_csr_dfi_p0_reset_n; -reg litedramcore_csr_dfi_p0_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p0_wrdata; -wire litedramcore_csr_dfi_p0_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask; -wire litedramcore_csr_dfi_p0_rddata_en; -reg [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0; -reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0; -wire [13:0] litedramcore_csr_dfi_p1_address; -wire [2:0] litedramcore_csr_dfi_p1_bank; -reg litedramcore_csr_dfi_p1_cas_n = 1'd1; -reg litedramcore_csr_dfi_p1_cs_n = 1'd1; -reg litedramcore_csr_dfi_p1_ras_n = 1'd1; -reg litedramcore_csr_dfi_p1_we_n = 1'd1; -wire litedramcore_csr_dfi_p1_cke; -wire litedramcore_csr_dfi_p1_odt; -wire litedramcore_csr_dfi_p1_reset_n; -reg litedramcore_csr_dfi_p1_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p1_wrdata; -wire litedramcore_csr_dfi_p1_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask; -wire litedramcore_csr_dfi_p1_rddata_en; -reg [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0; -reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0; -wire [13:0] litedramcore_csr_dfi_p2_address; -wire [2:0] litedramcore_csr_dfi_p2_bank; -reg litedramcore_csr_dfi_p2_cas_n = 1'd1; -reg litedramcore_csr_dfi_p2_cs_n = 1'd1; -reg litedramcore_csr_dfi_p2_ras_n = 1'd1; -reg litedramcore_csr_dfi_p2_we_n = 1'd1; -wire litedramcore_csr_dfi_p2_cke; -wire litedramcore_csr_dfi_p2_odt; -wire litedramcore_csr_dfi_p2_reset_n; -reg litedramcore_csr_dfi_p2_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p2_wrdata; -wire litedramcore_csr_dfi_p2_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask; -wire litedramcore_csr_dfi_p2_rddata_en; -reg [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0; -reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0; -wire [13:0] litedramcore_csr_dfi_p3_address; -wire [2:0] litedramcore_csr_dfi_p3_bank; -reg litedramcore_csr_dfi_p3_cas_n = 1'd1; -reg litedramcore_csr_dfi_p3_cs_n = 1'd1; -reg litedramcore_csr_dfi_p3_ras_n = 1'd1; -reg litedramcore_csr_dfi_p3_we_n = 1'd1; -wire litedramcore_csr_dfi_p3_cke; -wire litedramcore_csr_dfi_p3_odt; -wire litedramcore_csr_dfi_p3_reset_n; -reg litedramcore_csr_dfi_p3_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p3_wrdata; -wire litedramcore_csr_dfi_p3_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask; -wire litedramcore_csr_dfi_p3_rddata_en; -reg [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0; -reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0; -reg [13:0] litedramcore_ext_dfi_p0_address = 14'd0; -reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0; -reg litedramcore_ext_dfi_p0_cas_n = 1'd1; -reg litedramcore_ext_dfi_p0_cs_n = 1'd1; -reg litedramcore_ext_dfi_p0_ras_n = 1'd1; -reg litedramcore_ext_dfi_p0_we_n = 1'd1; -reg litedramcore_ext_dfi_p0_cke = 1'd0; -reg litedramcore_ext_dfi_p0_odt = 1'd0; -reg litedramcore_ext_dfi_p0_reset_n = 1'd0; -reg litedramcore_ext_dfi_p0_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0; -reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p0_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0; -reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0; -reg [13:0] litedramcore_ext_dfi_p1_address = 14'd0; -reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0; -reg litedramcore_ext_dfi_p1_cas_n = 1'd1; -reg litedramcore_ext_dfi_p1_cs_n = 1'd1; -reg litedramcore_ext_dfi_p1_ras_n = 1'd1; -reg litedramcore_ext_dfi_p1_we_n = 1'd1; -reg litedramcore_ext_dfi_p1_cke = 1'd0; -reg litedramcore_ext_dfi_p1_odt = 1'd0; -reg litedramcore_ext_dfi_p1_reset_n = 1'd0; -reg litedramcore_ext_dfi_p1_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0; -reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p1_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0; -reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0; -reg [13:0] litedramcore_ext_dfi_p2_address = 14'd0; -reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0; -reg litedramcore_ext_dfi_p2_cas_n = 1'd1; -reg litedramcore_ext_dfi_p2_cs_n = 1'd1; -reg litedramcore_ext_dfi_p2_ras_n = 1'd1; -reg litedramcore_ext_dfi_p2_we_n = 1'd1; -reg litedramcore_ext_dfi_p2_cke = 1'd0; -reg litedramcore_ext_dfi_p2_odt = 1'd0; -reg litedramcore_ext_dfi_p2_reset_n = 1'd0; -reg litedramcore_ext_dfi_p2_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0; -reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p2_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0; -reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0; -reg [13:0] litedramcore_ext_dfi_p3_address = 14'd0; -reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0; -reg litedramcore_ext_dfi_p3_cas_n = 1'd1; -reg litedramcore_ext_dfi_p3_cs_n = 1'd1; -reg litedramcore_ext_dfi_p3_ras_n = 1'd1; -reg litedramcore_ext_dfi_p3_we_n = 1'd1; -reg litedramcore_ext_dfi_p3_cke = 1'd0; -reg litedramcore_ext_dfi_p3_odt = 1'd0; -reg litedramcore_ext_dfi_p3_reset_n = 1'd0; -reg litedramcore_ext_dfi_p3_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0; -reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p3_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0; -reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0; -reg litedramcore_ext_dfi_sel = 1'd0; -wire litedramcore_sel; -wire litedramcore_cke; -wire litedramcore_odt; -wire litedramcore_reset_n; -reg [3:0] litedramcore_storage = 4'd1; -reg litedramcore_re = 1'd0; -wire litedramcore_phaseinjector0_csrfield_cs; -wire litedramcore_phaseinjector0_csrfield_we; -wire litedramcore_phaseinjector0_csrfield_cas; -wire litedramcore_phaseinjector0_csrfield_ras; -wire litedramcore_phaseinjector0_csrfield_wren; -wire litedramcore_phaseinjector0_csrfield_rden; -reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; -reg litedramcore_phaseinjector0_command_re = 1'd0; -reg litedramcore_phaseinjector0_command_issue_re = 1'd0; -wire litedramcore_phaseinjector0_command_issue_r; -reg litedramcore_phaseinjector0_command_issue_we = 1'd0; -reg litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [13:0] litedramcore_phaseinjector0_address_storage = 14'd0; -reg litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0; -wire litedramcore_phaseinjector0_rddata_we; -reg litedramcore_phaseinjector0_rddata_re = 1'd0; -wire litedramcore_phaseinjector1_csrfield_cs; -wire litedramcore_phaseinjector1_csrfield_we; -wire litedramcore_phaseinjector1_csrfield_cas; -wire litedramcore_phaseinjector1_csrfield_ras; -wire litedramcore_phaseinjector1_csrfield_wren; -wire litedramcore_phaseinjector1_csrfield_rden; -reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0; -reg litedramcore_phaseinjector1_command_re = 1'd0; -reg litedramcore_phaseinjector1_command_issue_re = 1'd0; -wire litedramcore_phaseinjector1_command_issue_r; -reg litedramcore_phaseinjector1_command_issue_we = 1'd0; -reg litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [13:0] litedramcore_phaseinjector1_address_storage = 14'd0; -reg litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0; -wire litedramcore_phaseinjector1_rddata_we; -reg litedramcore_phaseinjector1_rddata_re = 1'd0; -wire litedramcore_phaseinjector2_csrfield_cs; -wire litedramcore_phaseinjector2_csrfield_we; -wire litedramcore_phaseinjector2_csrfield_cas; -wire litedramcore_phaseinjector2_csrfield_ras; -wire litedramcore_phaseinjector2_csrfield_wren; -wire litedramcore_phaseinjector2_csrfield_rden; -reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0; -reg litedramcore_phaseinjector2_command_re = 1'd0; -reg litedramcore_phaseinjector2_command_issue_re = 1'd0; -wire litedramcore_phaseinjector2_command_issue_r; -reg litedramcore_phaseinjector2_command_issue_we = 1'd0; -reg litedramcore_phaseinjector2_command_issue_w = 1'd0; -reg [13:0] litedramcore_phaseinjector2_address_storage = 14'd0; -reg litedramcore_phaseinjector2_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0; -reg litedramcore_phaseinjector2_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector2_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0; -wire litedramcore_phaseinjector2_rddata_we; -reg litedramcore_phaseinjector2_rddata_re = 1'd0; -wire litedramcore_phaseinjector3_csrfield_cs; -wire litedramcore_phaseinjector3_csrfield_we; -wire litedramcore_phaseinjector3_csrfield_cas; -wire litedramcore_phaseinjector3_csrfield_ras; -wire litedramcore_phaseinjector3_csrfield_wren; -wire litedramcore_phaseinjector3_csrfield_rden; -reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0; -reg litedramcore_phaseinjector3_command_re = 1'd0; -reg litedramcore_phaseinjector3_command_issue_re = 1'd0; -wire litedramcore_phaseinjector3_command_issue_r; -reg litedramcore_phaseinjector3_command_issue_we = 1'd0; -reg litedramcore_phaseinjector3_command_issue_w = 1'd0; -reg [13:0] litedramcore_phaseinjector3_address_storage = 14'd0; -reg litedramcore_phaseinjector3_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0; -reg litedramcore_phaseinjector3_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector3_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0; -wire litedramcore_phaseinjector3_rddata_we; -reg litedramcore_phaseinjector3_rddata_re = 1'd0; -wire litedramcore_interface_bank0_valid; -wire litedramcore_interface_bank0_ready; -wire litedramcore_interface_bank0_we; -wire [20:0] litedramcore_interface_bank0_addr; -wire litedramcore_interface_bank0_lock; -wire litedramcore_interface_bank0_wdata_ready; -wire litedramcore_interface_bank0_rdata_valid; -wire litedramcore_interface_bank1_valid; -wire litedramcore_interface_bank1_ready; -wire litedramcore_interface_bank1_we; -wire [20:0] litedramcore_interface_bank1_addr; -wire litedramcore_interface_bank1_lock; -wire litedramcore_interface_bank1_wdata_ready; -wire litedramcore_interface_bank1_rdata_valid; -wire litedramcore_interface_bank2_valid; -wire litedramcore_interface_bank2_ready; -wire litedramcore_interface_bank2_we; -wire [20:0] litedramcore_interface_bank2_addr; -wire litedramcore_interface_bank2_lock; -wire litedramcore_interface_bank2_wdata_ready; -wire litedramcore_interface_bank2_rdata_valid; -wire litedramcore_interface_bank3_valid; -wire litedramcore_interface_bank3_ready; -wire litedramcore_interface_bank3_we; -wire [20:0] litedramcore_interface_bank3_addr; -wire litedramcore_interface_bank3_lock; -wire litedramcore_interface_bank3_wdata_ready; -wire litedramcore_interface_bank3_rdata_valid; -wire litedramcore_interface_bank4_valid; -wire litedramcore_interface_bank4_ready; -wire litedramcore_interface_bank4_we; -wire [20:0] litedramcore_interface_bank4_addr; -wire litedramcore_interface_bank4_lock; -wire litedramcore_interface_bank4_wdata_ready; -wire litedramcore_interface_bank4_rdata_valid; -wire litedramcore_interface_bank5_valid; -wire litedramcore_interface_bank5_ready; -wire litedramcore_interface_bank5_we; -wire [20:0] litedramcore_interface_bank5_addr; -wire litedramcore_interface_bank5_lock; -wire litedramcore_interface_bank5_wdata_ready; -wire litedramcore_interface_bank5_rdata_valid; -wire litedramcore_interface_bank6_valid; -wire litedramcore_interface_bank6_ready; -wire litedramcore_interface_bank6_we; -wire [20:0] litedramcore_interface_bank6_addr; -wire litedramcore_interface_bank6_lock; -wire litedramcore_interface_bank6_wdata_ready; -wire litedramcore_interface_bank6_rdata_valid; -wire litedramcore_interface_bank7_valid; -wire litedramcore_interface_bank7_ready; -wire litedramcore_interface_bank7_we; -wire [20:0] litedramcore_interface_bank7_addr; -wire litedramcore_interface_bank7_lock; -wire litedramcore_interface_bank7_wdata_ready; -wire litedramcore_interface_bank7_rdata_valid; -reg [127:0] litedramcore_interface_wdata = 128'd0; -reg [15:0] litedramcore_interface_wdata_we = 16'd0; -wire [127:0] litedramcore_interface_rdata; -reg [13:0] litedramcore_dfi_p0_address = 14'd0; -reg [2:0] litedramcore_dfi_p0_bank = 3'd0; -reg litedramcore_dfi_p0_cas_n = 1'd1; -reg litedramcore_dfi_p0_cs_n = 1'd1; -reg litedramcore_dfi_p0_ras_n = 1'd1; -reg litedramcore_dfi_p0_we_n = 1'd1; -wire litedramcore_dfi_p0_cke; -wire litedramcore_dfi_p0_odt; -wire litedramcore_dfi_p0_reset_n; -reg litedramcore_dfi_p0_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p0_wrdata; -reg litedramcore_dfi_p0_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p0_wrdata_mask; -reg litedramcore_dfi_p0_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p0_rddata; -wire litedramcore_dfi_p0_rddata_valid; -reg [13:0] litedramcore_dfi_p1_address = 14'd0; -reg [2:0] litedramcore_dfi_p1_bank = 3'd0; -reg litedramcore_dfi_p1_cas_n = 1'd1; -reg litedramcore_dfi_p1_cs_n = 1'd1; -reg litedramcore_dfi_p1_ras_n = 1'd1; -reg litedramcore_dfi_p1_we_n = 1'd1; -wire litedramcore_dfi_p1_cke; -wire litedramcore_dfi_p1_odt; -wire litedramcore_dfi_p1_reset_n; -reg litedramcore_dfi_p1_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p1_wrdata; -reg litedramcore_dfi_p1_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p1_wrdata_mask; -reg litedramcore_dfi_p1_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p1_rddata; -wire litedramcore_dfi_p1_rddata_valid; -reg [13:0] litedramcore_dfi_p2_address = 14'd0; -reg [2:0] litedramcore_dfi_p2_bank = 3'd0; -reg litedramcore_dfi_p2_cas_n = 1'd1; -reg litedramcore_dfi_p2_cs_n = 1'd1; -reg litedramcore_dfi_p2_ras_n = 1'd1; -reg litedramcore_dfi_p2_we_n = 1'd1; -wire litedramcore_dfi_p2_cke; -wire litedramcore_dfi_p2_odt; -wire litedramcore_dfi_p2_reset_n; -reg litedramcore_dfi_p2_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p2_wrdata; -reg litedramcore_dfi_p2_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p2_wrdata_mask; -reg litedramcore_dfi_p2_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p2_rddata; -wire litedramcore_dfi_p2_rddata_valid; -reg [13:0] litedramcore_dfi_p3_address = 14'd0; -reg [2:0] litedramcore_dfi_p3_bank = 3'd0; -reg litedramcore_dfi_p3_cas_n = 1'd1; -reg litedramcore_dfi_p3_cs_n = 1'd1; -reg litedramcore_dfi_p3_ras_n = 1'd1; -reg litedramcore_dfi_p3_we_n = 1'd1; -wire litedramcore_dfi_p3_cke; -wire litedramcore_dfi_p3_odt; -wire litedramcore_dfi_p3_reset_n; -reg litedramcore_dfi_p3_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p3_wrdata; -reg litedramcore_dfi_p3_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p3_wrdata_mask; -reg litedramcore_dfi_p3_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p3_rddata; -wire litedramcore_dfi_p3_rddata_valid; -reg litedramcore_cmd_valid = 1'd0; -reg litedramcore_cmd_ready = 1'd0; -reg litedramcore_cmd_last = 1'd0; -reg [13:0] litedramcore_cmd_payload_a = 14'd0; -reg [2:0] litedramcore_cmd_payload_ba = 3'd0; -reg litedramcore_cmd_payload_cas = 1'd0; -reg litedramcore_cmd_payload_ras = 1'd0; -reg litedramcore_cmd_payload_we = 1'd0; -reg litedramcore_cmd_payload_is_read = 1'd0; -reg litedramcore_cmd_payload_is_write = 1'd0; -wire litedramcore_wants_refresh; -wire litedramcore_wants_zqcs; -wire litedramcore_timer_wait; -wire litedramcore_timer_done0; -wire [9:0] litedramcore_timer_count0; -wire litedramcore_timer_done1; -reg [9:0] litedramcore_timer_count1 = 10'd781; -wire litedramcore_postponer_req_i; -reg litedramcore_postponer_req_o = 1'd0; -reg litedramcore_postponer_count = 1'd0; -reg litedramcore_sequencer_start0 = 1'd0; -wire litedramcore_sequencer_done0; -wire litedramcore_sequencer_start1; -reg litedramcore_sequencer_done1 = 1'd0; -reg [5:0] litedramcore_sequencer_counter = 6'd0; -reg litedramcore_sequencer_count = 1'd0; -wire litedramcore_zqcs_timer_wait; -wire litedramcore_zqcs_timer_done0; -wire [26:0] litedramcore_zqcs_timer_count0; -wire litedramcore_zqcs_timer_done1; -reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999; -reg litedramcore_zqcs_executer_start = 1'd0; -reg litedramcore_zqcs_executer_done = 1'd0; -reg [4:0] litedramcore_zqcs_executer_counter = 5'd0; -wire litedramcore_bankmachine0_req_valid; -wire litedramcore_bankmachine0_req_ready; -wire litedramcore_bankmachine0_req_we; -wire [20:0] litedramcore_bankmachine0_req_addr; -wire litedramcore_bankmachine0_req_lock; -reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine0_refresh_req; -reg litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg litedramcore_bankmachine0_cmd_valid = 1'd0; -reg litedramcore_bankmachine0_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine0_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; -reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine0_auto_precharge = 1'd0; -wire litedramcore_bankmachine0_sink_valid; -wire litedramcore_bankmachine0_sink_ready; -reg litedramcore_bankmachine0_sink_first = 1'd0; -reg litedramcore_bankmachine0_sink_last = 1'd0; -wire litedramcore_bankmachine0_sink_payload_we; -wire [20:0] litedramcore_bankmachine0_sink_payload_addr; -wire litedramcore_bankmachine0_source_valid; -wire litedramcore_bankmachine0_source_ready; -wire litedramcore_bankmachine0_source_first; -wire litedramcore_bankmachine0_source_last; -wire litedramcore_bankmachine0_source_payload_we; -wire [20:0] litedramcore_bankmachine0_source_payload_addr; -wire litedramcore_bankmachine0_syncfifo0_we; -wire litedramcore_bankmachine0_syncfifo0_writable; -wire litedramcore_bankmachine0_syncfifo0_re; -wire litedramcore_bankmachine0_syncfifo0_readable; -wire [23:0] litedramcore_bankmachine0_syncfifo0_din; -wire [23:0] litedramcore_bankmachine0_syncfifo0_dout; -reg [4:0] litedramcore_bankmachine0_level = 5'd0; -reg litedramcore_bankmachine0_replace = 1'd0; -reg [3:0] litedramcore_bankmachine0_produce = 4'd0; -reg [3:0] litedramcore_bankmachine0_consume = 4'd0; -reg [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine0_wrport_dat_r; -wire litedramcore_bankmachine0_wrport_we; -wire [23:0] litedramcore_bankmachine0_wrport_dat_w; -wire litedramcore_bankmachine0_do_read; -wire [3:0] litedramcore_bankmachine0_rdport_adr; -wire [23:0] litedramcore_bankmachine0_rdport_dat_r; -wire litedramcore_bankmachine0_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine0_fifo_in_payload_addr; -wire litedramcore_bankmachine0_fifo_in_first; -wire litedramcore_bankmachine0_fifo_in_last; -wire litedramcore_bankmachine0_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine0_fifo_out_payload_addr; -wire litedramcore_bankmachine0_fifo_out_first; -wire litedramcore_bankmachine0_fifo_out_last; -wire litedramcore_bankmachine0_sink_sink_valid; -wire litedramcore_bankmachine0_sink_sink_ready; -wire litedramcore_bankmachine0_sink_sink_first; -wire litedramcore_bankmachine0_sink_sink_last; -wire litedramcore_bankmachine0_sink_sink_payload_we; -wire [20:0] litedramcore_bankmachine0_sink_sink_payload_addr; -wire litedramcore_bankmachine0_source_source_valid; -wire litedramcore_bankmachine0_source_source_ready; -wire litedramcore_bankmachine0_source_source_first; -wire litedramcore_bankmachine0_source_source_last; -wire litedramcore_bankmachine0_source_source_payload_we; -wire [20:0] litedramcore_bankmachine0_source_source_payload_addr; -wire litedramcore_bankmachine0_pipe_valid_sink_valid; -wire litedramcore_bankmachine0_pipe_valid_sink_ready; -wire litedramcore_bankmachine0_pipe_valid_sink_first; -wire litedramcore_bankmachine0_pipe_valid_sink_last; -wire litedramcore_bankmachine0_pipe_valid_sink_payload_we; -wire [20:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine0_pipe_valid_source_ready; -reg litedramcore_bankmachine0_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine0_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine0_row = 14'd0; -reg litedramcore_bankmachine0_row_opened = 1'd0; -wire litedramcore_bankmachine0_row_hit; -reg litedramcore_bankmachine0_row_open = 1'd0; -reg litedramcore_bankmachine0_row_close = 1'd0; -reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine0_twtpcon_valid; +wire main_a7ddrphy0; +wire main_a7ddrphy1; +reg [7:0] main_a7ddrphy_bitslip00 = 8'd0; +reg [7:0] main_a7ddrphy_bitslip01 = 8'd0; +reg [7:0] main_a7ddrphy_bitslip02 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip03; +reg [7:0] main_a7ddrphy_bitslip04 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip10 = 8'd0; +reg [7:0] main_a7ddrphy_bitslip100 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip101; +reg [7:0] main_a7ddrphy_bitslip102 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip11 = 8'd0; +reg [7:0] main_a7ddrphy_bitslip110 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip111; +reg [7:0] main_a7ddrphy_bitslip112 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip12 = 8'd0; +reg [7:0] main_a7ddrphy_bitslip120 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip121; +reg [7:0] main_a7ddrphy_bitslip122 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7; +wire [7:0] main_a7ddrphy_bitslip13; +reg [7:0] main_a7ddrphy_bitslip130 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip131; +reg [7:0] main_a7ddrphy_bitslip132 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip14 = 8'd0; +reg [7:0] main_a7ddrphy_bitslip140 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip141; +reg [7:0] main_a7ddrphy_bitslip142 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip150 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip151; +reg [7:0] main_a7ddrphy_bitslip152 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip20 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip21; +reg [7:0] main_a7ddrphy_bitslip22 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip30 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip31; +reg [7:0] main_a7ddrphy_bitslip32 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip40 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip41; +reg [7:0] main_a7ddrphy_bitslip42 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip50 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip51; +reg [7:0] main_a7ddrphy_bitslip52 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip60 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip61; +reg [7:0] main_a7ddrphy_bitslip62 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip70 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip71; +reg [7:0] main_a7ddrphy_bitslip72 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip80 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip81; +reg [7:0] main_a7ddrphy_bitslip82 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip90 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip91; +reg [7:0] main_a7ddrphy_bitslip92 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7; +wire main_a7ddrphy_dfi_p0_act_n; +wire [13:0] main_a7ddrphy_dfi_p0_address; +wire [2:0] main_a7ddrphy_dfi_p0_bank; +wire main_a7ddrphy_dfi_p0_cas_n; +wire main_a7ddrphy_dfi_p0_cke; +wire main_a7ddrphy_dfi_p0_cs_n; +wire main_a7ddrphy_dfi_p0_odt; +wire main_a7ddrphy_dfi_p0_ras_n; +reg [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0; +wire main_a7ddrphy_dfi_p0_rddata_en; +wire main_a7ddrphy_dfi_p0_rddata_valid; +wire main_a7ddrphy_dfi_p0_reset_n; +wire main_a7ddrphy_dfi_p0_we_n; +wire [31:0] main_a7ddrphy_dfi_p0_wrdata; +wire main_a7ddrphy_dfi_p0_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p0_wrdata_mask; +wire main_a7ddrphy_dfi_p1_act_n; +wire [13:0] main_a7ddrphy_dfi_p1_address; +wire [2:0] main_a7ddrphy_dfi_p1_bank; +wire main_a7ddrphy_dfi_p1_cas_n; +wire main_a7ddrphy_dfi_p1_cke; +wire main_a7ddrphy_dfi_p1_cs_n; +wire main_a7ddrphy_dfi_p1_odt; +wire main_a7ddrphy_dfi_p1_ras_n; +reg [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0; +wire main_a7ddrphy_dfi_p1_rddata_en; +wire main_a7ddrphy_dfi_p1_rddata_valid; +wire main_a7ddrphy_dfi_p1_reset_n; +wire main_a7ddrphy_dfi_p1_we_n; +wire [31:0] main_a7ddrphy_dfi_p1_wrdata; +wire main_a7ddrphy_dfi_p1_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p1_wrdata_mask; +wire main_a7ddrphy_dfi_p2_act_n; +wire [13:0] main_a7ddrphy_dfi_p2_address; +wire [2:0] main_a7ddrphy_dfi_p2_bank; +wire main_a7ddrphy_dfi_p2_cas_n; +wire main_a7ddrphy_dfi_p2_cke; +wire main_a7ddrphy_dfi_p2_cs_n; +wire main_a7ddrphy_dfi_p2_odt; +wire main_a7ddrphy_dfi_p2_ras_n; +reg [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0; +wire main_a7ddrphy_dfi_p2_rddata_en; +wire main_a7ddrphy_dfi_p2_rddata_valid; +wire main_a7ddrphy_dfi_p2_reset_n; +wire main_a7ddrphy_dfi_p2_we_n; +wire [31:0] main_a7ddrphy_dfi_p2_wrdata; +wire main_a7ddrphy_dfi_p2_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p2_wrdata_mask; +wire main_a7ddrphy_dfi_p3_act_n; +wire [13:0] main_a7ddrphy_dfi_p3_address; +wire [2:0] main_a7ddrphy_dfi_p3_bank; +wire main_a7ddrphy_dfi_p3_cas_n; +wire main_a7ddrphy_dfi_p3_cke; +wire main_a7ddrphy_dfi_p3_cs_n; +wire main_a7ddrphy_dfi_p3_odt; +wire main_a7ddrphy_dfi_p3_ras_n; +reg [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0; +wire main_a7ddrphy_dfi_p3_rddata_en; +wire main_a7ddrphy_dfi_p3_rddata_valid; +wire main_a7ddrphy_dfi_p3_reset_n; +wire main_a7ddrphy_dfi_p3_we_n; +wire [31:0] main_a7ddrphy_dfi_p3_wrdata; +wire main_a7ddrphy_dfi_p3_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p3_wrdata_mask; +reg main_a7ddrphy_dly_sel_re = 1'd0; +reg [1:0] main_a7ddrphy_dly_sel_storage = 2'd0; +wire main_a7ddrphy_dq_i_delayed0; +wire main_a7ddrphy_dq_i_delayed1; +wire main_a7ddrphy_dq_i_delayed10; +wire main_a7ddrphy_dq_i_delayed11; +wire main_a7ddrphy_dq_i_delayed12; +wire main_a7ddrphy_dq_i_delayed13; +wire main_a7ddrphy_dq_i_delayed14; +wire main_a7ddrphy_dq_i_delayed15; +wire main_a7ddrphy_dq_i_delayed2; +wire main_a7ddrphy_dq_i_delayed3; +wire main_a7ddrphy_dq_i_delayed4; +wire main_a7ddrphy_dq_i_delayed5; +wire main_a7ddrphy_dq_i_delayed6; +wire main_a7ddrphy_dq_i_delayed7; +wire main_a7ddrphy_dq_i_delayed8; +wire main_a7ddrphy_dq_i_delayed9; +wire main_a7ddrphy_dq_i_nodelay0; +wire main_a7ddrphy_dq_i_nodelay1; +wire main_a7ddrphy_dq_i_nodelay10; +wire main_a7ddrphy_dq_i_nodelay11; +wire main_a7ddrphy_dq_i_nodelay12; +wire main_a7ddrphy_dq_i_nodelay13; +wire main_a7ddrphy_dq_i_nodelay14; +wire main_a7ddrphy_dq_i_nodelay15; +wire main_a7ddrphy_dq_i_nodelay2; +wire main_a7ddrphy_dq_i_nodelay3; +wire main_a7ddrphy_dq_i_nodelay4; +wire main_a7ddrphy_dq_i_nodelay5; +wire main_a7ddrphy_dq_i_nodelay6; +wire main_a7ddrphy_dq_i_nodelay7; +wire main_a7ddrphy_dq_i_nodelay8; +wire main_a7ddrphy_dq_i_nodelay9; +wire main_a7ddrphy_dq_o_nodelay0; +wire main_a7ddrphy_dq_o_nodelay1; +wire main_a7ddrphy_dq_o_nodelay10; +wire main_a7ddrphy_dq_o_nodelay11; +wire main_a7ddrphy_dq_o_nodelay12; +wire main_a7ddrphy_dq_o_nodelay13; +wire main_a7ddrphy_dq_o_nodelay14; +wire main_a7ddrphy_dq_o_nodelay15; +wire main_a7ddrphy_dq_o_nodelay2; +wire main_a7ddrphy_dq_o_nodelay3; +wire main_a7ddrphy_dq_o_nodelay4; +wire main_a7ddrphy_dq_o_nodelay5; +wire main_a7ddrphy_dq_o_nodelay6; +wire main_a7ddrphy_dq_o_nodelay7; +wire main_a7ddrphy_dq_o_nodelay8; +wire main_a7ddrphy_dq_o_nodelay9; +wire main_a7ddrphy_dq_oe; +wire main_a7ddrphy_dq_oe_delay_tappeddelayline; +reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +wire main_a7ddrphy_dq_t0; +wire main_a7ddrphy_dq_t1; +wire main_a7ddrphy_dq_t10; +wire main_a7ddrphy_dq_t11; +wire main_a7ddrphy_dq_t12; +wire main_a7ddrphy_dq_t13; +wire main_a7ddrphy_dq_t14; +wire main_a7ddrphy_dq_t15; +wire main_a7ddrphy_dq_t2; +wire main_a7ddrphy_dq_t3; +wire main_a7ddrphy_dq_t4; +wire main_a7ddrphy_dq_t5; +wire main_a7ddrphy_dq_t6; +wire main_a7ddrphy_dq_t7; +wire main_a7ddrphy_dq_t8; +wire main_a7ddrphy_dq_t9; +wire main_a7ddrphy_dqs_o_no_delay0; +wire main_a7ddrphy_dqs_o_no_delay1; +reg main_a7ddrphy_dqs_oe = 1'd0; +wire main_a7ddrphy_dqs_oe_delay_tappeddelayline; +reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +wire main_a7ddrphy_dqs_postamble; +wire main_a7ddrphy_dqs_preamble; +wire main_a7ddrphy_dqs_t0; +wire main_a7ddrphy_dqs_t1; +reg main_a7ddrphy_dqspattern0 = 1'd0; +reg main_a7ddrphy_dqspattern1 = 1'd0; +reg [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0; +reg [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0; +reg main_a7ddrphy_half_sys8x_taps_re = 1'd0; +reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8; +wire [2:0] main_a7ddrphy_pads_ba; +reg main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; +wire main_a7ddrphy_rdly_dq_bitslip_r; +reg main_a7ddrphy_rdly_dq_bitslip_re = 1'd0; +wire main_a7ddrphy_rdly_dq_bitslip_rst_r; +reg main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_w = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_we = 1'd0; +wire main_a7ddrphy_rdly_dq_inc_r; +reg main_a7ddrphy_rdly_dq_inc_re = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_w = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_we = 1'd0; +wire main_a7ddrphy_rdly_dq_rst_r; +reg main_a7ddrphy_rdly_dq_rst_re = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_w = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_we = 1'd0; +reg main_a7ddrphy_rdphase_re = 1'd0; +reg [1:0] main_a7ddrphy_rdphase_storage = 2'd2; +reg main_a7ddrphy_rst_re = 1'd0; +reg main_a7ddrphy_rst_storage = 1'd0; +wire main_a7ddrphy_sd_clk_se_nodelay; +wire main_a7ddrphy_wdly_dq_bitslip_r; +reg main_a7ddrphy_wdly_dq_bitslip_re = 1'd0; +wire main_a7ddrphy_wdly_dq_bitslip_rst_r; +reg main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_w = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_we = 1'd0; +reg main_a7ddrphy_wlevel_en_re = 1'd0; +reg main_a7ddrphy_wlevel_en_storage = 1'd0; +wire main_a7ddrphy_wlevel_strobe_r; +reg main_a7ddrphy_wlevel_strobe_re = 1'd0; +reg main_a7ddrphy_wlevel_strobe_w = 1'd0; +reg main_a7ddrphy_wlevel_strobe_we = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +reg main_a7ddrphy_wrphase_re = 1'd0; +reg [1:0] main_a7ddrphy_wrphase_storage = 2'd3; +wire main_clkin; +wire main_clkout0; +wire main_clkout1; +wire main_clkout2; +wire main_clkout3; +wire main_clkout_buf0; +wire main_clkout_buf1; +wire main_clkout_buf2; +wire main_clkout_buf3; +reg main_ic_reset = 1'd1; +reg main_init_done_re = 1'd0; +reg main_init_done_storage = 1'd0; +reg main_init_error_re = 1'd0; +reg main_init_error_storage = 1'd0; +reg main_litedramcore_bankmachine0_auto_precharge = 1'd0; +reg [13:0] main_litedramcore_bankmachine0_cmd_payload_a = 14'd0; +wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba; +reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine0_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine0_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine0_consume = 4'd0; +wire main_litedramcore_bankmachine0_do_read; +wire main_litedramcore_bankmachine0_fifo_in_first; +wire main_litedramcore_bankmachine0_fifo_in_last; +wire [20:0] main_litedramcore_bankmachine0_fifo_in_payload_addr; +wire main_litedramcore_bankmachine0_fifo_in_payload_we; +wire main_litedramcore_bankmachine0_fifo_out_first; +wire main_litedramcore_bankmachine0_fifo_out_last; +wire [20:0] main_litedramcore_bankmachine0_fifo_out_payload_addr; +wire main_litedramcore_bankmachine0_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine0_level = 5'd0; +wire main_litedramcore_bankmachine0_pipe_valid_sink_first; +wire main_litedramcore_bankmachine0_pipe_valid_sink_last; +wire [20:0] main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine0_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine0_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine0_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine0_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine0_pipe_valid_source_last = 1'd0; +reg [20:0] main_litedramcore_bankmachine0_pipe_valid_source_payload_addr = 21'd0; +reg main_litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine0_pipe_valid_source_ready; +reg main_litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine0_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine0_rdport_adr; +wire [23:0] main_litedramcore_bankmachine0_rdport_dat_r; +reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine0_refresh_req; +reg main_litedramcore_bankmachine0_replace = 1'd0; +wire [20:0] main_litedramcore_bankmachine0_req_addr; +wire main_litedramcore_bankmachine0_req_lock; +reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine0_req_ready; +wire main_litedramcore_bankmachine0_req_valid; +reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine0_req_we; +reg [13:0] main_litedramcore_bankmachine0_row = 14'd0; +reg main_litedramcore_bankmachine0_row_close = 1'd0; +reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine0_row_hit; +reg main_litedramcore_bankmachine0_row_open = 1'd0; +reg main_litedramcore_bankmachine0_row_opened = 1'd0; +reg main_litedramcore_bankmachine0_sink_first = 1'd0; +reg main_litedramcore_bankmachine0_sink_last = 1'd0; +wire [20:0] main_litedramcore_bankmachine0_sink_payload_addr; +wire main_litedramcore_bankmachine0_sink_payload_we; +wire main_litedramcore_bankmachine0_sink_ready; +wire main_litedramcore_bankmachine0_sink_sink_first; +wire main_litedramcore_bankmachine0_sink_sink_last; +wire [20:0] main_litedramcore_bankmachine0_sink_sink_payload_addr; +wire main_litedramcore_bankmachine0_sink_sink_payload_we; +wire main_litedramcore_bankmachine0_sink_sink_ready; +wire main_litedramcore_bankmachine0_sink_sink_valid; +wire main_litedramcore_bankmachine0_sink_valid; +wire main_litedramcore_bankmachine0_source_first; +wire main_litedramcore_bankmachine0_source_last; +wire [20:0] main_litedramcore_bankmachine0_source_payload_addr; +wire main_litedramcore_bankmachine0_source_payload_we; +wire main_litedramcore_bankmachine0_source_ready; +wire main_litedramcore_bankmachine0_source_source_first; +wire main_litedramcore_bankmachine0_source_source_last; +wire [20:0] main_litedramcore_bankmachine0_source_source_payload_addr; +wire main_litedramcore_bankmachine0_source_source_payload_we; +wire main_litedramcore_bankmachine0_source_source_ready; +wire main_litedramcore_bankmachine0_source_source_valid; +wire main_litedramcore_bankmachine0_source_valid; +wire [23:0] main_litedramcore_bankmachine0_syncfifo0_din; +wire [23:0] main_litedramcore_bankmachine0_syncfifo0_dout; +wire main_litedramcore_bankmachine0_syncfifo0_re; +wire main_litedramcore_bankmachine0_syncfifo0_readable; +wire main_litedramcore_bankmachine0_syncfifo0_we; +wire main_litedramcore_bankmachine0_syncfifo0_writable; +reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; -wire litedramcore_bankmachine0_trccon_valid; +reg main_litedramcore_bankmachine0_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine0_trascon_valid; +reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0; -wire litedramcore_bankmachine0_trascon_valid; +reg main_litedramcore_bankmachine0_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine0_trccon_valid; +reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine0_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0; -wire litedramcore_bankmachine1_req_valid; -wire litedramcore_bankmachine1_req_ready; -wire litedramcore_bankmachine1_req_we; -wire [20:0] litedramcore_bankmachine1_req_addr; -wire litedramcore_bankmachine1_req_lock; -reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine1_refresh_req; -reg litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg litedramcore_bankmachine1_cmd_valid = 1'd0; -reg litedramcore_bankmachine1_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine1_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; -reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine1_auto_precharge = 1'd0; -wire litedramcore_bankmachine1_sink_valid; -wire litedramcore_bankmachine1_sink_ready; -reg litedramcore_bankmachine1_sink_first = 1'd0; -reg litedramcore_bankmachine1_sink_last = 1'd0; -wire litedramcore_bankmachine1_sink_payload_we; -wire [20:0] litedramcore_bankmachine1_sink_payload_addr; -wire litedramcore_bankmachine1_source_valid; -wire litedramcore_bankmachine1_source_ready; -wire litedramcore_bankmachine1_source_first; -wire litedramcore_bankmachine1_source_last; -wire litedramcore_bankmachine1_source_payload_we; -wire [20:0] litedramcore_bankmachine1_source_payload_addr; -wire litedramcore_bankmachine1_syncfifo1_we; -wire litedramcore_bankmachine1_syncfifo1_writable; -wire litedramcore_bankmachine1_syncfifo1_re; -wire litedramcore_bankmachine1_syncfifo1_readable; -wire [23:0] litedramcore_bankmachine1_syncfifo1_din; -wire [23:0] litedramcore_bankmachine1_syncfifo1_dout; -reg [4:0] litedramcore_bankmachine1_level = 5'd0; -reg litedramcore_bankmachine1_replace = 1'd0; -reg [3:0] litedramcore_bankmachine1_produce = 4'd0; -reg [3:0] litedramcore_bankmachine1_consume = 4'd0; -reg [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine1_wrport_dat_r; -wire litedramcore_bankmachine1_wrport_we; -wire [23:0] litedramcore_bankmachine1_wrport_dat_w; -wire litedramcore_bankmachine1_do_read; -wire [3:0] litedramcore_bankmachine1_rdport_adr; -wire [23:0] litedramcore_bankmachine1_rdport_dat_r; -wire litedramcore_bankmachine1_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine1_fifo_in_payload_addr; -wire litedramcore_bankmachine1_fifo_in_first; -wire litedramcore_bankmachine1_fifo_in_last; -wire litedramcore_bankmachine1_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine1_fifo_out_payload_addr; -wire litedramcore_bankmachine1_fifo_out_first; -wire litedramcore_bankmachine1_fifo_out_last; -wire litedramcore_bankmachine1_sink_sink_valid; -wire litedramcore_bankmachine1_sink_sink_ready; -wire litedramcore_bankmachine1_sink_sink_first; -wire litedramcore_bankmachine1_sink_sink_last; -wire litedramcore_bankmachine1_sink_sink_payload_we; -wire [20:0] litedramcore_bankmachine1_sink_sink_payload_addr; -wire litedramcore_bankmachine1_source_source_valid; -wire litedramcore_bankmachine1_source_source_ready; -wire litedramcore_bankmachine1_source_source_first; -wire litedramcore_bankmachine1_source_source_last; -wire litedramcore_bankmachine1_source_source_payload_we; -wire [20:0] litedramcore_bankmachine1_source_source_payload_addr; -wire litedramcore_bankmachine1_pipe_valid_sink_valid; -wire litedramcore_bankmachine1_pipe_valid_sink_ready; -wire litedramcore_bankmachine1_pipe_valid_sink_first; -wire litedramcore_bankmachine1_pipe_valid_sink_last; -wire litedramcore_bankmachine1_pipe_valid_sink_payload_we; -wire [20:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine1_pipe_valid_source_ready; -reg litedramcore_bankmachine1_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine1_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine1_row = 14'd0; -reg litedramcore_bankmachine1_row_opened = 1'd0; -wire litedramcore_bankmachine1_row_hit; -reg litedramcore_bankmachine1_row_open = 1'd0; -reg litedramcore_bankmachine1_row_close = 1'd0; -reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine1_twtpcon_valid; +reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine0_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine0_wrport_adr = 4'd0; +wire [23:0] main_litedramcore_bankmachine0_wrport_dat_r; +wire [23:0] main_litedramcore_bankmachine0_wrport_dat_w; +wire main_litedramcore_bankmachine0_wrport_we; +reg main_litedramcore_bankmachine1_auto_precharge = 1'd0; +reg [13:0] main_litedramcore_bankmachine1_cmd_payload_a = 14'd0; +wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba; +reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine1_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine1_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine1_consume = 4'd0; +wire main_litedramcore_bankmachine1_do_read; +wire main_litedramcore_bankmachine1_fifo_in_first; +wire main_litedramcore_bankmachine1_fifo_in_last; +wire [20:0] main_litedramcore_bankmachine1_fifo_in_payload_addr; +wire main_litedramcore_bankmachine1_fifo_in_payload_we; +wire main_litedramcore_bankmachine1_fifo_out_first; +wire main_litedramcore_bankmachine1_fifo_out_last; +wire [20:0] main_litedramcore_bankmachine1_fifo_out_payload_addr; +wire main_litedramcore_bankmachine1_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine1_level = 5'd0; +wire main_litedramcore_bankmachine1_pipe_valid_sink_first; +wire main_litedramcore_bankmachine1_pipe_valid_sink_last; +wire [20:0] main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine1_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine1_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine1_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine1_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine1_pipe_valid_source_last = 1'd0; +reg [20:0] main_litedramcore_bankmachine1_pipe_valid_source_payload_addr = 21'd0; +reg main_litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine1_pipe_valid_source_ready; +reg main_litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine1_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine1_rdport_adr; +wire [23:0] main_litedramcore_bankmachine1_rdport_dat_r; +reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine1_refresh_req; +reg main_litedramcore_bankmachine1_replace = 1'd0; +wire [20:0] main_litedramcore_bankmachine1_req_addr; +wire main_litedramcore_bankmachine1_req_lock; +reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine1_req_ready; +wire main_litedramcore_bankmachine1_req_valid; +reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine1_req_we; +reg [13:0] main_litedramcore_bankmachine1_row = 14'd0; +reg main_litedramcore_bankmachine1_row_close = 1'd0; +reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine1_row_hit; +reg main_litedramcore_bankmachine1_row_open = 1'd0; +reg main_litedramcore_bankmachine1_row_opened = 1'd0; +reg main_litedramcore_bankmachine1_sink_first = 1'd0; +reg main_litedramcore_bankmachine1_sink_last = 1'd0; +wire [20:0] main_litedramcore_bankmachine1_sink_payload_addr; +wire main_litedramcore_bankmachine1_sink_payload_we; +wire main_litedramcore_bankmachine1_sink_ready; +wire main_litedramcore_bankmachine1_sink_sink_first; +wire main_litedramcore_bankmachine1_sink_sink_last; +wire [20:0] main_litedramcore_bankmachine1_sink_sink_payload_addr; +wire main_litedramcore_bankmachine1_sink_sink_payload_we; +wire main_litedramcore_bankmachine1_sink_sink_ready; +wire main_litedramcore_bankmachine1_sink_sink_valid; +wire main_litedramcore_bankmachine1_sink_valid; +wire main_litedramcore_bankmachine1_source_first; +wire main_litedramcore_bankmachine1_source_last; +wire [20:0] main_litedramcore_bankmachine1_source_payload_addr; +wire main_litedramcore_bankmachine1_source_payload_we; +wire main_litedramcore_bankmachine1_source_ready; +wire main_litedramcore_bankmachine1_source_source_first; +wire main_litedramcore_bankmachine1_source_source_last; +wire [20:0] main_litedramcore_bankmachine1_source_source_payload_addr; +wire main_litedramcore_bankmachine1_source_source_payload_we; +wire main_litedramcore_bankmachine1_source_source_ready; +wire main_litedramcore_bankmachine1_source_source_valid; +wire main_litedramcore_bankmachine1_source_valid; +wire [23:0] main_litedramcore_bankmachine1_syncfifo1_din; +wire [23:0] main_litedramcore_bankmachine1_syncfifo1_dout; +wire main_litedramcore_bankmachine1_syncfifo1_re; +wire main_litedramcore_bankmachine1_syncfifo1_readable; +wire main_litedramcore_bankmachine1_syncfifo1_we; +wire main_litedramcore_bankmachine1_syncfifo1_writable; +reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; -wire litedramcore_bankmachine1_trccon_valid; +reg main_litedramcore_bankmachine1_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine1_trascon_valid; +reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0; -wire litedramcore_bankmachine1_trascon_valid; +reg main_litedramcore_bankmachine1_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine1_trccon_valid; +reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine1_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0; -wire litedramcore_bankmachine2_req_valid; -wire litedramcore_bankmachine2_req_ready; -wire litedramcore_bankmachine2_req_we; -wire [20:0] litedramcore_bankmachine2_req_addr; -wire litedramcore_bankmachine2_req_lock; -reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine2_refresh_req; -reg litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg litedramcore_bankmachine2_cmd_valid = 1'd0; -reg litedramcore_bankmachine2_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine2_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; -reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine2_auto_precharge = 1'd0; -wire litedramcore_bankmachine2_sink_valid; -wire litedramcore_bankmachine2_sink_ready; -reg litedramcore_bankmachine2_sink_first = 1'd0; -reg litedramcore_bankmachine2_sink_last = 1'd0; -wire litedramcore_bankmachine2_sink_payload_we; -wire [20:0] litedramcore_bankmachine2_sink_payload_addr; -wire litedramcore_bankmachine2_source_valid; -wire litedramcore_bankmachine2_source_ready; -wire litedramcore_bankmachine2_source_first; -wire litedramcore_bankmachine2_source_last; -wire litedramcore_bankmachine2_source_payload_we; -wire [20:0] litedramcore_bankmachine2_source_payload_addr; -wire litedramcore_bankmachine2_syncfifo2_we; -wire litedramcore_bankmachine2_syncfifo2_writable; -wire litedramcore_bankmachine2_syncfifo2_re; -wire litedramcore_bankmachine2_syncfifo2_readable; -wire [23:0] litedramcore_bankmachine2_syncfifo2_din; -wire [23:0] litedramcore_bankmachine2_syncfifo2_dout; -reg [4:0] litedramcore_bankmachine2_level = 5'd0; -reg litedramcore_bankmachine2_replace = 1'd0; -reg [3:0] litedramcore_bankmachine2_produce = 4'd0; -reg [3:0] litedramcore_bankmachine2_consume = 4'd0; -reg [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine2_wrport_dat_r; -wire litedramcore_bankmachine2_wrport_we; -wire [23:0] litedramcore_bankmachine2_wrport_dat_w; -wire litedramcore_bankmachine2_do_read; -wire [3:0] litedramcore_bankmachine2_rdport_adr; -wire [23:0] litedramcore_bankmachine2_rdport_dat_r; -wire litedramcore_bankmachine2_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine2_fifo_in_payload_addr; -wire litedramcore_bankmachine2_fifo_in_first; -wire litedramcore_bankmachine2_fifo_in_last; -wire litedramcore_bankmachine2_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine2_fifo_out_payload_addr; -wire litedramcore_bankmachine2_fifo_out_first; -wire litedramcore_bankmachine2_fifo_out_last; -wire litedramcore_bankmachine2_sink_sink_valid; -wire litedramcore_bankmachine2_sink_sink_ready; -wire litedramcore_bankmachine2_sink_sink_first; -wire litedramcore_bankmachine2_sink_sink_last; -wire litedramcore_bankmachine2_sink_sink_payload_we; -wire [20:0] litedramcore_bankmachine2_sink_sink_payload_addr; -wire litedramcore_bankmachine2_source_source_valid; -wire litedramcore_bankmachine2_source_source_ready; -wire litedramcore_bankmachine2_source_source_first; -wire litedramcore_bankmachine2_source_source_last; -wire litedramcore_bankmachine2_source_source_payload_we; -wire [20:0] litedramcore_bankmachine2_source_source_payload_addr; -wire litedramcore_bankmachine2_pipe_valid_sink_valid; -wire litedramcore_bankmachine2_pipe_valid_sink_ready; -wire litedramcore_bankmachine2_pipe_valid_sink_first; -wire litedramcore_bankmachine2_pipe_valid_sink_last; -wire litedramcore_bankmachine2_pipe_valid_sink_payload_we; -wire [20:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine2_pipe_valid_source_ready; -reg litedramcore_bankmachine2_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine2_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine2_row = 14'd0; -reg litedramcore_bankmachine2_row_opened = 1'd0; -wire litedramcore_bankmachine2_row_hit; -reg litedramcore_bankmachine2_row_open = 1'd0; -reg litedramcore_bankmachine2_row_close = 1'd0; -reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine2_twtpcon_valid; +reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine1_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine1_wrport_adr = 4'd0; +wire [23:0] main_litedramcore_bankmachine1_wrport_dat_r; +wire [23:0] main_litedramcore_bankmachine1_wrport_dat_w; +wire main_litedramcore_bankmachine1_wrport_we; +reg main_litedramcore_bankmachine2_auto_precharge = 1'd0; +reg [13:0] main_litedramcore_bankmachine2_cmd_payload_a = 14'd0; +wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba; +reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine2_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine2_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine2_consume = 4'd0; +wire main_litedramcore_bankmachine2_do_read; +wire main_litedramcore_bankmachine2_fifo_in_first; +wire main_litedramcore_bankmachine2_fifo_in_last; +wire [20:0] main_litedramcore_bankmachine2_fifo_in_payload_addr; +wire main_litedramcore_bankmachine2_fifo_in_payload_we; +wire main_litedramcore_bankmachine2_fifo_out_first; +wire main_litedramcore_bankmachine2_fifo_out_last; +wire [20:0] main_litedramcore_bankmachine2_fifo_out_payload_addr; +wire main_litedramcore_bankmachine2_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine2_level = 5'd0; +wire main_litedramcore_bankmachine2_pipe_valid_sink_first; +wire main_litedramcore_bankmachine2_pipe_valid_sink_last; +wire [20:0] main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine2_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine2_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine2_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine2_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine2_pipe_valid_source_last = 1'd0; +reg [20:0] main_litedramcore_bankmachine2_pipe_valid_source_payload_addr = 21'd0; +reg main_litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine2_pipe_valid_source_ready; +reg main_litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine2_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine2_rdport_adr; +wire [23:0] main_litedramcore_bankmachine2_rdport_dat_r; +reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine2_refresh_req; +reg main_litedramcore_bankmachine2_replace = 1'd0; +wire [20:0] main_litedramcore_bankmachine2_req_addr; +wire main_litedramcore_bankmachine2_req_lock; +reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine2_req_ready; +wire main_litedramcore_bankmachine2_req_valid; +reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine2_req_we; +reg [13:0] main_litedramcore_bankmachine2_row = 14'd0; +reg main_litedramcore_bankmachine2_row_close = 1'd0; +reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine2_row_hit; +reg main_litedramcore_bankmachine2_row_open = 1'd0; +reg main_litedramcore_bankmachine2_row_opened = 1'd0; +reg main_litedramcore_bankmachine2_sink_first = 1'd0; +reg main_litedramcore_bankmachine2_sink_last = 1'd0; +wire [20:0] main_litedramcore_bankmachine2_sink_payload_addr; +wire main_litedramcore_bankmachine2_sink_payload_we; +wire main_litedramcore_bankmachine2_sink_ready; +wire main_litedramcore_bankmachine2_sink_sink_first; +wire main_litedramcore_bankmachine2_sink_sink_last; +wire [20:0] main_litedramcore_bankmachine2_sink_sink_payload_addr; +wire main_litedramcore_bankmachine2_sink_sink_payload_we; +wire main_litedramcore_bankmachine2_sink_sink_ready; +wire main_litedramcore_bankmachine2_sink_sink_valid; +wire main_litedramcore_bankmachine2_sink_valid; +wire main_litedramcore_bankmachine2_source_first; +wire main_litedramcore_bankmachine2_source_last; +wire [20:0] main_litedramcore_bankmachine2_source_payload_addr; +wire main_litedramcore_bankmachine2_source_payload_we; +wire main_litedramcore_bankmachine2_source_ready; +wire main_litedramcore_bankmachine2_source_source_first; +wire main_litedramcore_bankmachine2_source_source_last; +wire [20:0] main_litedramcore_bankmachine2_source_source_payload_addr; +wire main_litedramcore_bankmachine2_source_source_payload_we; +wire main_litedramcore_bankmachine2_source_source_ready; +wire main_litedramcore_bankmachine2_source_source_valid; +wire main_litedramcore_bankmachine2_source_valid; +wire [23:0] main_litedramcore_bankmachine2_syncfifo2_din; +wire [23:0] main_litedramcore_bankmachine2_syncfifo2_dout; +wire main_litedramcore_bankmachine2_syncfifo2_re; +wire main_litedramcore_bankmachine2_syncfifo2_readable; +wire main_litedramcore_bankmachine2_syncfifo2_we; +wire main_litedramcore_bankmachine2_syncfifo2_writable; +reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; -wire litedramcore_bankmachine2_trccon_valid; +reg main_litedramcore_bankmachine2_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine2_trascon_valid; +reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0; -wire litedramcore_bankmachine2_trascon_valid; +reg main_litedramcore_bankmachine2_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine2_trccon_valid; +reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine2_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0; -wire litedramcore_bankmachine3_req_valid; -wire litedramcore_bankmachine3_req_ready; -wire litedramcore_bankmachine3_req_we; -wire [20:0] litedramcore_bankmachine3_req_addr; -wire litedramcore_bankmachine3_req_lock; -reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine3_refresh_req; -reg litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg litedramcore_bankmachine3_cmd_valid = 1'd0; -reg litedramcore_bankmachine3_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine3_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; -reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine3_auto_precharge = 1'd0; -wire litedramcore_bankmachine3_sink_valid; -wire litedramcore_bankmachine3_sink_ready; -reg litedramcore_bankmachine3_sink_first = 1'd0; -reg litedramcore_bankmachine3_sink_last = 1'd0; -wire litedramcore_bankmachine3_sink_payload_we; -wire [20:0] litedramcore_bankmachine3_sink_payload_addr; -wire litedramcore_bankmachine3_source_valid; -wire litedramcore_bankmachine3_source_ready; -wire litedramcore_bankmachine3_source_first; -wire litedramcore_bankmachine3_source_last; -wire litedramcore_bankmachine3_source_payload_we; -wire [20:0] litedramcore_bankmachine3_source_payload_addr; -wire litedramcore_bankmachine3_syncfifo3_we; -wire litedramcore_bankmachine3_syncfifo3_writable; -wire litedramcore_bankmachine3_syncfifo3_re; -wire litedramcore_bankmachine3_syncfifo3_readable; -wire [23:0] litedramcore_bankmachine3_syncfifo3_din; -wire [23:0] litedramcore_bankmachine3_syncfifo3_dout; -reg [4:0] litedramcore_bankmachine3_level = 5'd0; -reg litedramcore_bankmachine3_replace = 1'd0; -reg [3:0] litedramcore_bankmachine3_produce = 4'd0; -reg [3:0] litedramcore_bankmachine3_consume = 4'd0; -reg [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine3_wrport_dat_r; -wire litedramcore_bankmachine3_wrport_we; -wire [23:0] litedramcore_bankmachine3_wrport_dat_w; -wire litedramcore_bankmachine3_do_read; -wire [3:0] litedramcore_bankmachine3_rdport_adr; -wire [23:0] litedramcore_bankmachine3_rdport_dat_r; -wire litedramcore_bankmachine3_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine3_fifo_in_payload_addr; -wire litedramcore_bankmachine3_fifo_in_first; -wire litedramcore_bankmachine3_fifo_in_last; -wire litedramcore_bankmachine3_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine3_fifo_out_payload_addr; -wire litedramcore_bankmachine3_fifo_out_first; -wire litedramcore_bankmachine3_fifo_out_last; -wire litedramcore_bankmachine3_sink_sink_valid; -wire litedramcore_bankmachine3_sink_sink_ready; -wire litedramcore_bankmachine3_sink_sink_first; -wire litedramcore_bankmachine3_sink_sink_last; -wire litedramcore_bankmachine3_sink_sink_payload_we; -wire [20:0] litedramcore_bankmachine3_sink_sink_payload_addr; -wire litedramcore_bankmachine3_source_source_valid; -wire litedramcore_bankmachine3_source_source_ready; -wire litedramcore_bankmachine3_source_source_first; -wire litedramcore_bankmachine3_source_source_last; -wire litedramcore_bankmachine3_source_source_payload_we; -wire [20:0] litedramcore_bankmachine3_source_source_payload_addr; -wire litedramcore_bankmachine3_pipe_valid_sink_valid; -wire litedramcore_bankmachine3_pipe_valid_sink_ready; -wire litedramcore_bankmachine3_pipe_valid_sink_first; -wire litedramcore_bankmachine3_pipe_valid_sink_last; -wire litedramcore_bankmachine3_pipe_valid_sink_payload_we; -wire [20:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine3_pipe_valid_source_ready; -reg litedramcore_bankmachine3_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine3_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine3_row = 14'd0; -reg litedramcore_bankmachine3_row_opened = 1'd0; -wire litedramcore_bankmachine3_row_hit; -reg litedramcore_bankmachine3_row_open = 1'd0; -reg litedramcore_bankmachine3_row_close = 1'd0; -reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine3_twtpcon_valid; +reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine2_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine2_wrport_adr = 4'd0; +wire [23:0] main_litedramcore_bankmachine2_wrport_dat_r; +wire [23:0] main_litedramcore_bankmachine2_wrport_dat_w; +wire main_litedramcore_bankmachine2_wrport_we; +reg main_litedramcore_bankmachine3_auto_precharge = 1'd0; +reg [13:0] main_litedramcore_bankmachine3_cmd_payload_a = 14'd0; +wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba; +reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine3_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine3_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine3_consume = 4'd0; +wire main_litedramcore_bankmachine3_do_read; +wire main_litedramcore_bankmachine3_fifo_in_first; +wire main_litedramcore_bankmachine3_fifo_in_last; +wire [20:0] main_litedramcore_bankmachine3_fifo_in_payload_addr; +wire main_litedramcore_bankmachine3_fifo_in_payload_we; +wire main_litedramcore_bankmachine3_fifo_out_first; +wire main_litedramcore_bankmachine3_fifo_out_last; +wire [20:0] main_litedramcore_bankmachine3_fifo_out_payload_addr; +wire main_litedramcore_bankmachine3_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine3_level = 5'd0; +wire main_litedramcore_bankmachine3_pipe_valid_sink_first; +wire main_litedramcore_bankmachine3_pipe_valid_sink_last; +wire [20:0] main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine3_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine3_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine3_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine3_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine3_pipe_valid_source_last = 1'd0; +reg [20:0] main_litedramcore_bankmachine3_pipe_valid_source_payload_addr = 21'd0; +reg main_litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine3_pipe_valid_source_ready; +reg main_litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine3_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine3_rdport_adr; +wire [23:0] main_litedramcore_bankmachine3_rdport_dat_r; +reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine3_refresh_req; +reg main_litedramcore_bankmachine3_replace = 1'd0; +wire [20:0] main_litedramcore_bankmachine3_req_addr; +wire main_litedramcore_bankmachine3_req_lock; +reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine3_req_ready; +wire main_litedramcore_bankmachine3_req_valid; +reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine3_req_we; +reg [13:0] main_litedramcore_bankmachine3_row = 14'd0; +reg main_litedramcore_bankmachine3_row_close = 1'd0; +reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine3_row_hit; +reg main_litedramcore_bankmachine3_row_open = 1'd0; +reg main_litedramcore_bankmachine3_row_opened = 1'd0; +reg main_litedramcore_bankmachine3_sink_first = 1'd0; +reg main_litedramcore_bankmachine3_sink_last = 1'd0; +wire [20:0] main_litedramcore_bankmachine3_sink_payload_addr; +wire main_litedramcore_bankmachine3_sink_payload_we; +wire main_litedramcore_bankmachine3_sink_ready; +wire main_litedramcore_bankmachine3_sink_sink_first; +wire main_litedramcore_bankmachine3_sink_sink_last; +wire [20:0] main_litedramcore_bankmachine3_sink_sink_payload_addr; +wire main_litedramcore_bankmachine3_sink_sink_payload_we; +wire main_litedramcore_bankmachine3_sink_sink_ready; +wire main_litedramcore_bankmachine3_sink_sink_valid; +wire main_litedramcore_bankmachine3_sink_valid; +wire main_litedramcore_bankmachine3_source_first; +wire main_litedramcore_bankmachine3_source_last; +wire [20:0] main_litedramcore_bankmachine3_source_payload_addr; +wire main_litedramcore_bankmachine3_source_payload_we; +wire main_litedramcore_bankmachine3_source_ready; +wire main_litedramcore_bankmachine3_source_source_first; +wire main_litedramcore_bankmachine3_source_source_last; +wire [20:0] main_litedramcore_bankmachine3_source_source_payload_addr; +wire main_litedramcore_bankmachine3_source_source_payload_we; +wire main_litedramcore_bankmachine3_source_source_ready; +wire main_litedramcore_bankmachine3_source_source_valid; +wire main_litedramcore_bankmachine3_source_valid; +wire [23:0] main_litedramcore_bankmachine3_syncfifo3_din; +wire [23:0] main_litedramcore_bankmachine3_syncfifo3_dout; +wire main_litedramcore_bankmachine3_syncfifo3_re; +wire main_litedramcore_bankmachine3_syncfifo3_readable; +wire main_litedramcore_bankmachine3_syncfifo3_we; +wire main_litedramcore_bankmachine3_syncfifo3_writable; +reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; -wire litedramcore_bankmachine3_trccon_valid; +reg main_litedramcore_bankmachine3_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine3_trascon_valid; +reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0; -wire litedramcore_bankmachine3_trascon_valid; +reg main_litedramcore_bankmachine3_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine3_trccon_valid; +reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine3_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0; -wire litedramcore_bankmachine4_req_valid; -wire litedramcore_bankmachine4_req_ready; -wire litedramcore_bankmachine4_req_we; -wire [20:0] litedramcore_bankmachine4_req_addr; -wire litedramcore_bankmachine4_req_lock; -reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine4_refresh_req; -reg litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg litedramcore_bankmachine4_cmd_valid = 1'd0; -reg litedramcore_bankmachine4_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine4_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; -reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine4_auto_precharge = 1'd0; -wire litedramcore_bankmachine4_sink_valid; -wire litedramcore_bankmachine4_sink_ready; -reg litedramcore_bankmachine4_sink_first = 1'd0; -reg litedramcore_bankmachine4_sink_last = 1'd0; -wire litedramcore_bankmachine4_sink_payload_we; -wire [20:0] litedramcore_bankmachine4_sink_payload_addr; -wire litedramcore_bankmachine4_source_valid; -wire litedramcore_bankmachine4_source_ready; -wire litedramcore_bankmachine4_source_first; -wire litedramcore_bankmachine4_source_last; -wire litedramcore_bankmachine4_source_payload_we; -wire [20:0] litedramcore_bankmachine4_source_payload_addr; -wire litedramcore_bankmachine4_syncfifo4_we; -wire litedramcore_bankmachine4_syncfifo4_writable; -wire litedramcore_bankmachine4_syncfifo4_re; -wire litedramcore_bankmachine4_syncfifo4_readable; -wire [23:0] litedramcore_bankmachine4_syncfifo4_din; -wire [23:0] litedramcore_bankmachine4_syncfifo4_dout; -reg [4:0] litedramcore_bankmachine4_level = 5'd0; -reg litedramcore_bankmachine4_replace = 1'd0; -reg [3:0] litedramcore_bankmachine4_produce = 4'd0; -reg [3:0] litedramcore_bankmachine4_consume = 4'd0; -reg [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine4_wrport_dat_r; -wire litedramcore_bankmachine4_wrport_we; -wire [23:0] litedramcore_bankmachine4_wrport_dat_w; -wire litedramcore_bankmachine4_do_read; -wire [3:0] litedramcore_bankmachine4_rdport_adr; -wire [23:0] litedramcore_bankmachine4_rdport_dat_r; -wire litedramcore_bankmachine4_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine4_fifo_in_payload_addr; -wire litedramcore_bankmachine4_fifo_in_first; -wire litedramcore_bankmachine4_fifo_in_last; -wire litedramcore_bankmachine4_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine4_fifo_out_payload_addr; -wire litedramcore_bankmachine4_fifo_out_first; -wire litedramcore_bankmachine4_fifo_out_last; -wire litedramcore_bankmachine4_sink_sink_valid; -wire litedramcore_bankmachine4_sink_sink_ready; -wire litedramcore_bankmachine4_sink_sink_first; -wire litedramcore_bankmachine4_sink_sink_last; -wire litedramcore_bankmachine4_sink_sink_payload_we; -wire [20:0] litedramcore_bankmachine4_sink_sink_payload_addr; -wire litedramcore_bankmachine4_source_source_valid; -wire litedramcore_bankmachine4_source_source_ready; -wire litedramcore_bankmachine4_source_source_first; -wire litedramcore_bankmachine4_source_source_last; -wire litedramcore_bankmachine4_source_source_payload_we; -wire [20:0] litedramcore_bankmachine4_source_source_payload_addr; -wire litedramcore_bankmachine4_pipe_valid_sink_valid; -wire litedramcore_bankmachine4_pipe_valid_sink_ready; -wire litedramcore_bankmachine4_pipe_valid_sink_first; -wire litedramcore_bankmachine4_pipe_valid_sink_last; -wire litedramcore_bankmachine4_pipe_valid_sink_payload_we; -wire [20:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine4_pipe_valid_source_ready; -reg litedramcore_bankmachine4_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine4_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine4_row = 14'd0; -reg litedramcore_bankmachine4_row_opened = 1'd0; -wire litedramcore_bankmachine4_row_hit; -reg litedramcore_bankmachine4_row_open = 1'd0; -reg litedramcore_bankmachine4_row_close = 1'd0; -reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine4_twtpcon_valid; +reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine3_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine3_wrport_adr = 4'd0; +wire [23:0] main_litedramcore_bankmachine3_wrport_dat_r; +wire [23:0] main_litedramcore_bankmachine3_wrport_dat_w; +wire main_litedramcore_bankmachine3_wrport_we; +reg main_litedramcore_bankmachine4_auto_precharge = 1'd0; +reg [13:0] main_litedramcore_bankmachine4_cmd_payload_a = 14'd0; +wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba; +reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine4_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine4_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine4_consume = 4'd0; +wire main_litedramcore_bankmachine4_do_read; +wire main_litedramcore_bankmachine4_fifo_in_first; +wire main_litedramcore_bankmachine4_fifo_in_last; +wire [20:0] main_litedramcore_bankmachine4_fifo_in_payload_addr; +wire main_litedramcore_bankmachine4_fifo_in_payload_we; +wire main_litedramcore_bankmachine4_fifo_out_first; +wire main_litedramcore_bankmachine4_fifo_out_last; +wire [20:0] main_litedramcore_bankmachine4_fifo_out_payload_addr; +wire main_litedramcore_bankmachine4_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine4_level = 5'd0; +wire main_litedramcore_bankmachine4_pipe_valid_sink_first; +wire main_litedramcore_bankmachine4_pipe_valid_sink_last; +wire [20:0] main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine4_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine4_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine4_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine4_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine4_pipe_valid_source_last = 1'd0; +reg [20:0] main_litedramcore_bankmachine4_pipe_valid_source_payload_addr = 21'd0; +reg main_litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine4_pipe_valid_source_ready; +reg main_litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine4_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine4_rdport_adr; +wire [23:0] main_litedramcore_bankmachine4_rdport_dat_r; +reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine4_refresh_req; +reg main_litedramcore_bankmachine4_replace = 1'd0; +wire [20:0] main_litedramcore_bankmachine4_req_addr; +wire main_litedramcore_bankmachine4_req_lock; +reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine4_req_ready; +wire main_litedramcore_bankmachine4_req_valid; +reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine4_req_we; +reg [13:0] main_litedramcore_bankmachine4_row = 14'd0; +reg main_litedramcore_bankmachine4_row_close = 1'd0; +reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine4_row_hit; +reg main_litedramcore_bankmachine4_row_open = 1'd0; +reg main_litedramcore_bankmachine4_row_opened = 1'd0; +reg main_litedramcore_bankmachine4_sink_first = 1'd0; +reg main_litedramcore_bankmachine4_sink_last = 1'd0; +wire [20:0] main_litedramcore_bankmachine4_sink_payload_addr; +wire main_litedramcore_bankmachine4_sink_payload_we; +wire main_litedramcore_bankmachine4_sink_ready; +wire main_litedramcore_bankmachine4_sink_sink_first; +wire main_litedramcore_bankmachine4_sink_sink_last; +wire [20:0] main_litedramcore_bankmachine4_sink_sink_payload_addr; +wire main_litedramcore_bankmachine4_sink_sink_payload_we; +wire main_litedramcore_bankmachine4_sink_sink_ready; +wire main_litedramcore_bankmachine4_sink_sink_valid; +wire main_litedramcore_bankmachine4_sink_valid; +wire main_litedramcore_bankmachine4_source_first; +wire main_litedramcore_bankmachine4_source_last; +wire [20:0] main_litedramcore_bankmachine4_source_payload_addr; +wire main_litedramcore_bankmachine4_source_payload_we; +wire main_litedramcore_bankmachine4_source_ready; +wire main_litedramcore_bankmachine4_source_source_first; +wire main_litedramcore_bankmachine4_source_source_last; +wire [20:0] main_litedramcore_bankmachine4_source_source_payload_addr; +wire main_litedramcore_bankmachine4_source_source_payload_we; +wire main_litedramcore_bankmachine4_source_source_ready; +wire main_litedramcore_bankmachine4_source_source_valid; +wire main_litedramcore_bankmachine4_source_valid; +wire [23:0] main_litedramcore_bankmachine4_syncfifo4_din; +wire [23:0] main_litedramcore_bankmachine4_syncfifo4_dout; +wire main_litedramcore_bankmachine4_syncfifo4_re; +wire main_litedramcore_bankmachine4_syncfifo4_readable; +wire main_litedramcore_bankmachine4_syncfifo4_we; +wire main_litedramcore_bankmachine4_syncfifo4_writable; +reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; -wire litedramcore_bankmachine4_trccon_valid; +reg main_litedramcore_bankmachine4_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine4_trascon_valid; +reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0; -wire litedramcore_bankmachine4_trascon_valid; +reg main_litedramcore_bankmachine4_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine4_trccon_valid; +reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine4_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0; -wire litedramcore_bankmachine5_req_valid; -wire litedramcore_bankmachine5_req_ready; -wire litedramcore_bankmachine5_req_we; -wire [20:0] litedramcore_bankmachine5_req_addr; -wire litedramcore_bankmachine5_req_lock; -reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine5_refresh_req; -reg litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg litedramcore_bankmachine5_cmd_valid = 1'd0; -reg litedramcore_bankmachine5_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine5_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; -reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine5_auto_precharge = 1'd0; -wire litedramcore_bankmachine5_sink_valid; -wire litedramcore_bankmachine5_sink_ready; -reg litedramcore_bankmachine5_sink_first = 1'd0; -reg litedramcore_bankmachine5_sink_last = 1'd0; -wire litedramcore_bankmachine5_sink_payload_we; -wire [20:0] litedramcore_bankmachine5_sink_payload_addr; -wire litedramcore_bankmachine5_source_valid; -wire litedramcore_bankmachine5_source_ready; -wire litedramcore_bankmachine5_source_first; -wire litedramcore_bankmachine5_source_last; -wire litedramcore_bankmachine5_source_payload_we; -wire [20:0] litedramcore_bankmachine5_source_payload_addr; -wire litedramcore_bankmachine5_syncfifo5_we; -wire litedramcore_bankmachine5_syncfifo5_writable; -wire litedramcore_bankmachine5_syncfifo5_re; -wire litedramcore_bankmachine5_syncfifo5_readable; -wire [23:0] litedramcore_bankmachine5_syncfifo5_din; -wire [23:0] litedramcore_bankmachine5_syncfifo5_dout; -reg [4:0] litedramcore_bankmachine5_level = 5'd0; -reg litedramcore_bankmachine5_replace = 1'd0; -reg [3:0] litedramcore_bankmachine5_produce = 4'd0; -reg [3:0] litedramcore_bankmachine5_consume = 4'd0; -reg [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine5_wrport_dat_r; -wire litedramcore_bankmachine5_wrport_we; -wire [23:0] litedramcore_bankmachine5_wrport_dat_w; -wire litedramcore_bankmachine5_do_read; -wire [3:0] litedramcore_bankmachine5_rdport_adr; -wire [23:0] litedramcore_bankmachine5_rdport_dat_r; -wire litedramcore_bankmachine5_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine5_fifo_in_payload_addr; -wire litedramcore_bankmachine5_fifo_in_first; -wire litedramcore_bankmachine5_fifo_in_last; -wire litedramcore_bankmachine5_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine5_fifo_out_payload_addr; -wire litedramcore_bankmachine5_fifo_out_first; -wire litedramcore_bankmachine5_fifo_out_last; -wire litedramcore_bankmachine5_sink_sink_valid; -wire litedramcore_bankmachine5_sink_sink_ready; -wire litedramcore_bankmachine5_sink_sink_first; -wire litedramcore_bankmachine5_sink_sink_last; -wire litedramcore_bankmachine5_sink_sink_payload_we; -wire [20:0] litedramcore_bankmachine5_sink_sink_payload_addr; -wire litedramcore_bankmachine5_source_source_valid; -wire litedramcore_bankmachine5_source_source_ready; -wire litedramcore_bankmachine5_source_source_first; -wire litedramcore_bankmachine5_source_source_last; -wire litedramcore_bankmachine5_source_source_payload_we; -wire [20:0] litedramcore_bankmachine5_source_source_payload_addr; -wire litedramcore_bankmachine5_pipe_valid_sink_valid; -wire litedramcore_bankmachine5_pipe_valid_sink_ready; -wire litedramcore_bankmachine5_pipe_valid_sink_first; -wire litedramcore_bankmachine5_pipe_valid_sink_last; -wire litedramcore_bankmachine5_pipe_valid_sink_payload_we; -wire [20:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine5_pipe_valid_source_ready; -reg litedramcore_bankmachine5_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine5_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine5_row = 14'd0; -reg litedramcore_bankmachine5_row_opened = 1'd0; -wire litedramcore_bankmachine5_row_hit; -reg litedramcore_bankmachine5_row_open = 1'd0; -reg litedramcore_bankmachine5_row_close = 1'd0; -reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine5_twtpcon_valid; +reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine4_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine4_wrport_adr = 4'd0; +wire [23:0] main_litedramcore_bankmachine4_wrport_dat_r; +wire [23:0] main_litedramcore_bankmachine4_wrport_dat_w; +wire main_litedramcore_bankmachine4_wrport_we; +reg main_litedramcore_bankmachine5_auto_precharge = 1'd0; +reg [13:0] main_litedramcore_bankmachine5_cmd_payload_a = 14'd0; +wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba; +reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine5_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine5_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine5_consume = 4'd0; +wire main_litedramcore_bankmachine5_do_read; +wire main_litedramcore_bankmachine5_fifo_in_first; +wire main_litedramcore_bankmachine5_fifo_in_last; +wire [20:0] main_litedramcore_bankmachine5_fifo_in_payload_addr; +wire main_litedramcore_bankmachine5_fifo_in_payload_we; +wire main_litedramcore_bankmachine5_fifo_out_first; +wire main_litedramcore_bankmachine5_fifo_out_last; +wire [20:0] main_litedramcore_bankmachine5_fifo_out_payload_addr; +wire main_litedramcore_bankmachine5_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine5_level = 5'd0; +wire main_litedramcore_bankmachine5_pipe_valid_sink_first; +wire main_litedramcore_bankmachine5_pipe_valid_sink_last; +wire [20:0] main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine5_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine5_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine5_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine5_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine5_pipe_valid_source_last = 1'd0; +reg [20:0] main_litedramcore_bankmachine5_pipe_valid_source_payload_addr = 21'd0; +reg main_litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine5_pipe_valid_source_ready; +reg main_litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine5_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine5_rdport_adr; +wire [23:0] main_litedramcore_bankmachine5_rdport_dat_r; +reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine5_refresh_req; +reg main_litedramcore_bankmachine5_replace = 1'd0; +wire [20:0] main_litedramcore_bankmachine5_req_addr; +wire main_litedramcore_bankmachine5_req_lock; +reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine5_req_ready; +wire main_litedramcore_bankmachine5_req_valid; +reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine5_req_we; +reg [13:0] main_litedramcore_bankmachine5_row = 14'd0; +reg main_litedramcore_bankmachine5_row_close = 1'd0; +reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine5_row_hit; +reg main_litedramcore_bankmachine5_row_open = 1'd0; +reg main_litedramcore_bankmachine5_row_opened = 1'd0; +reg main_litedramcore_bankmachine5_sink_first = 1'd0; +reg main_litedramcore_bankmachine5_sink_last = 1'd0; +wire [20:0] main_litedramcore_bankmachine5_sink_payload_addr; +wire main_litedramcore_bankmachine5_sink_payload_we; +wire main_litedramcore_bankmachine5_sink_ready; +wire main_litedramcore_bankmachine5_sink_sink_first; +wire main_litedramcore_bankmachine5_sink_sink_last; +wire [20:0] main_litedramcore_bankmachine5_sink_sink_payload_addr; +wire main_litedramcore_bankmachine5_sink_sink_payload_we; +wire main_litedramcore_bankmachine5_sink_sink_ready; +wire main_litedramcore_bankmachine5_sink_sink_valid; +wire main_litedramcore_bankmachine5_sink_valid; +wire main_litedramcore_bankmachine5_source_first; +wire main_litedramcore_bankmachine5_source_last; +wire [20:0] main_litedramcore_bankmachine5_source_payload_addr; +wire main_litedramcore_bankmachine5_source_payload_we; +wire main_litedramcore_bankmachine5_source_ready; +wire main_litedramcore_bankmachine5_source_source_first; +wire main_litedramcore_bankmachine5_source_source_last; +wire [20:0] main_litedramcore_bankmachine5_source_source_payload_addr; +wire main_litedramcore_bankmachine5_source_source_payload_we; +wire main_litedramcore_bankmachine5_source_source_ready; +wire main_litedramcore_bankmachine5_source_source_valid; +wire main_litedramcore_bankmachine5_source_valid; +wire [23:0] main_litedramcore_bankmachine5_syncfifo5_din; +wire [23:0] main_litedramcore_bankmachine5_syncfifo5_dout; +wire main_litedramcore_bankmachine5_syncfifo5_re; +wire main_litedramcore_bankmachine5_syncfifo5_readable; +wire main_litedramcore_bankmachine5_syncfifo5_we; +wire main_litedramcore_bankmachine5_syncfifo5_writable; +reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; -wire litedramcore_bankmachine5_trccon_valid; +reg main_litedramcore_bankmachine5_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine5_trascon_valid; +reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0; -wire litedramcore_bankmachine5_trascon_valid; +reg main_litedramcore_bankmachine5_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine5_trccon_valid; +reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine5_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0; -wire litedramcore_bankmachine6_req_valid; -wire litedramcore_bankmachine6_req_ready; -wire litedramcore_bankmachine6_req_we; -wire [20:0] litedramcore_bankmachine6_req_addr; -wire litedramcore_bankmachine6_req_lock; -reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine6_refresh_req; -reg litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg litedramcore_bankmachine6_cmd_valid = 1'd0; -reg litedramcore_bankmachine6_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine6_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; -reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine6_auto_precharge = 1'd0; -wire litedramcore_bankmachine6_sink_valid; -wire litedramcore_bankmachine6_sink_ready; -reg litedramcore_bankmachine6_sink_first = 1'd0; -reg litedramcore_bankmachine6_sink_last = 1'd0; -wire litedramcore_bankmachine6_sink_payload_we; -wire [20:0] litedramcore_bankmachine6_sink_payload_addr; -wire litedramcore_bankmachine6_source_valid; -wire litedramcore_bankmachine6_source_ready; -wire litedramcore_bankmachine6_source_first; -wire litedramcore_bankmachine6_source_last; -wire litedramcore_bankmachine6_source_payload_we; -wire [20:0] litedramcore_bankmachine6_source_payload_addr; -wire litedramcore_bankmachine6_syncfifo6_we; -wire litedramcore_bankmachine6_syncfifo6_writable; -wire litedramcore_bankmachine6_syncfifo6_re; -wire litedramcore_bankmachine6_syncfifo6_readable; -wire [23:0] litedramcore_bankmachine6_syncfifo6_din; -wire [23:0] litedramcore_bankmachine6_syncfifo6_dout; -reg [4:0] litedramcore_bankmachine6_level = 5'd0; -reg litedramcore_bankmachine6_replace = 1'd0; -reg [3:0] litedramcore_bankmachine6_produce = 4'd0; -reg [3:0] litedramcore_bankmachine6_consume = 4'd0; -reg [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine6_wrport_dat_r; -wire litedramcore_bankmachine6_wrport_we; -wire [23:0] litedramcore_bankmachine6_wrport_dat_w; -wire litedramcore_bankmachine6_do_read; -wire [3:0] litedramcore_bankmachine6_rdport_adr; -wire [23:0] litedramcore_bankmachine6_rdport_dat_r; -wire litedramcore_bankmachine6_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine6_fifo_in_payload_addr; -wire litedramcore_bankmachine6_fifo_in_first; -wire litedramcore_bankmachine6_fifo_in_last; -wire litedramcore_bankmachine6_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine6_fifo_out_payload_addr; -wire litedramcore_bankmachine6_fifo_out_first; -wire litedramcore_bankmachine6_fifo_out_last; -wire litedramcore_bankmachine6_sink_sink_valid; -wire litedramcore_bankmachine6_sink_sink_ready; -wire litedramcore_bankmachine6_sink_sink_first; -wire litedramcore_bankmachine6_sink_sink_last; -wire litedramcore_bankmachine6_sink_sink_payload_we; -wire [20:0] litedramcore_bankmachine6_sink_sink_payload_addr; -wire litedramcore_bankmachine6_source_source_valid; -wire litedramcore_bankmachine6_source_source_ready; -wire litedramcore_bankmachine6_source_source_first; -wire litedramcore_bankmachine6_source_source_last; -wire litedramcore_bankmachine6_source_source_payload_we; -wire [20:0] litedramcore_bankmachine6_source_source_payload_addr; -wire litedramcore_bankmachine6_pipe_valid_sink_valid; -wire litedramcore_bankmachine6_pipe_valid_sink_ready; -wire litedramcore_bankmachine6_pipe_valid_sink_first; -wire litedramcore_bankmachine6_pipe_valid_sink_last; -wire litedramcore_bankmachine6_pipe_valid_sink_payload_we; -wire [20:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine6_pipe_valid_source_ready; -reg litedramcore_bankmachine6_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine6_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine6_row = 14'd0; -reg litedramcore_bankmachine6_row_opened = 1'd0; -wire litedramcore_bankmachine6_row_hit; -reg litedramcore_bankmachine6_row_open = 1'd0; -reg litedramcore_bankmachine6_row_close = 1'd0; -reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine6_twtpcon_valid; +reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine5_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine5_wrport_adr = 4'd0; +wire [23:0] main_litedramcore_bankmachine5_wrport_dat_r; +wire [23:0] main_litedramcore_bankmachine5_wrport_dat_w; +wire main_litedramcore_bankmachine5_wrport_we; +reg main_litedramcore_bankmachine6_auto_precharge = 1'd0; +reg [13:0] main_litedramcore_bankmachine6_cmd_payload_a = 14'd0; +wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba; +reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine6_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine6_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine6_consume = 4'd0; +wire main_litedramcore_bankmachine6_do_read; +wire main_litedramcore_bankmachine6_fifo_in_first; +wire main_litedramcore_bankmachine6_fifo_in_last; +wire [20:0] main_litedramcore_bankmachine6_fifo_in_payload_addr; +wire main_litedramcore_bankmachine6_fifo_in_payload_we; +wire main_litedramcore_bankmachine6_fifo_out_first; +wire main_litedramcore_bankmachine6_fifo_out_last; +wire [20:0] main_litedramcore_bankmachine6_fifo_out_payload_addr; +wire main_litedramcore_bankmachine6_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine6_level = 5'd0; +wire main_litedramcore_bankmachine6_pipe_valid_sink_first; +wire main_litedramcore_bankmachine6_pipe_valid_sink_last; +wire [20:0] main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine6_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine6_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine6_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine6_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine6_pipe_valid_source_last = 1'd0; +reg [20:0] main_litedramcore_bankmachine6_pipe_valid_source_payload_addr = 21'd0; +reg main_litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine6_pipe_valid_source_ready; +reg main_litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine6_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine6_rdport_adr; +wire [23:0] main_litedramcore_bankmachine6_rdport_dat_r; +reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine6_refresh_req; +reg main_litedramcore_bankmachine6_replace = 1'd0; +wire [20:0] main_litedramcore_bankmachine6_req_addr; +wire main_litedramcore_bankmachine6_req_lock; +reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine6_req_ready; +wire main_litedramcore_bankmachine6_req_valid; +reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine6_req_we; +reg [13:0] main_litedramcore_bankmachine6_row = 14'd0; +reg main_litedramcore_bankmachine6_row_close = 1'd0; +reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine6_row_hit; +reg main_litedramcore_bankmachine6_row_open = 1'd0; +reg main_litedramcore_bankmachine6_row_opened = 1'd0; +reg main_litedramcore_bankmachine6_sink_first = 1'd0; +reg main_litedramcore_bankmachine6_sink_last = 1'd0; +wire [20:0] main_litedramcore_bankmachine6_sink_payload_addr; +wire main_litedramcore_bankmachine6_sink_payload_we; +wire main_litedramcore_bankmachine6_sink_ready; +wire main_litedramcore_bankmachine6_sink_sink_first; +wire main_litedramcore_bankmachine6_sink_sink_last; +wire [20:0] main_litedramcore_bankmachine6_sink_sink_payload_addr; +wire main_litedramcore_bankmachine6_sink_sink_payload_we; +wire main_litedramcore_bankmachine6_sink_sink_ready; +wire main_litedramcore_bankmachine6_sink_sink_valid; +wire main_litedramcore_bankmachine6_sink_valid; +wire main_litedramcore_bankmachine6_source_first; +wire main_litedramcore_bankmachine6_source_last; +wire [20:0] main_litedramcore_bankmachine6_source_payload_addr; +wire main_litedramcore_bankmachine6_source_payload_we; +wire main_litedramcore_bankmachine6_source_ready; +wire main_litedramcore_bankmachine6_source_source_first; +wire main_litedramcore_bankmachine6_source_source_last; +wire [20:0] main_litedramcore_bankmachine6_source_source_payload_addr; +wire main_litedramcore_bankmachine6_source_source_payload_we; +wire main_litedramcore_bankmachine6_source_source_ready; +wire main_litedramcore_bankmachine6_source_source_valid; +wire main_litedramcore_bankmachine6_source_valid; +wire [23:0] main_litedramcore_bankmachine6_syncfifo6_din; +wire [23:0] main_litedramcore_bankmachine6_syncfifo6_dout; +wire main_litedramcore_bankmachine6_syncfifo6_re; +wire main_litedramcore_bankmachine6_syncfifo6_readable; +wire main_litedramcore_bankmachine6_syncfifo6_we; +wire main_litedramcore_bankmachine6_syncfifo6_writable; +reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; -wire litedramcore_bankmachine6_trccon_valid; +reg main_litedramcore_bankmachine6_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine6_trascon_valid; +reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0; -wire litedramcore_bankmachine6_trascon_valid; +reg main_litedramcore_bankmachine6_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine6_trccon_valid; +reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine6_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0; -wire litedramcore_bankmachine7_req_valid; -wire litedramcore_bankmachine7_req_ready; -wire litedramcore_bankmachine7_req_we; -wire [20:0] litedramcore_bankmachine7_req_addr; -wire litedramcore_bankmachine7_req_lock; -reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine7_refresh_req; -reg litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg litedramcore_bankmachine7_cmd_valid = 1'd0; -reg litedramcore_bankmachine7_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine7_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; -reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine7_auto_precharge = 1'd0; -wire litedramcore_bankmachine7_sink_valid; -wire litedramcore_bankmachine7_sink_ready; -reg litedramcore_bankmachine7_sink_first = 1'd0; -reg litedramcore_bankmachine7_sink_last = 1'd0; -wire litedramcore_bankmachine7_sink_payload_we; -wire [20:0] litedramcore_bankmachine7_sink_payload_addr; -wire litedramcore_bankmachine7_source_valid; -wire litedramcore_bankmachine7_source_ready; -wire litedramcore_bankmachine7_source_first; -wire litedramcore_bankmachine7_source_last; -wire litedramcore_bankmachine7_source_payload_we; -wire [20:0] litedramcore_bankmachine7_source_payload_addr; -wire litedramcore_bankmachine7_syncfifo7_we; -wire litedramcore_bankmachine7_syncfifo7_writable; -wire litedramcore_bankmachine7_syncfifo7_re; -wire litedramcore_bankmachine7_syncfifo7_readable; -wire [23:0] litedramcore_bankmachine7_syncfifo7_din; -wire [23:0] litedramcore_bankmachine7_syncfifo7_dout; -reg [4:0] litedramcore_bankmachine7_level = 5'd0; -reg litedramcore_bankmachine7_replace = 1'd0; -reg [3:0] litedramcore_bankmachine7_produce = 4'd0; -reg [3:0] litedramcore_bankmachine7_consume = 4'd0; -reg [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine7_wrport_dat_r; -wire litedramcore_bankmachine7_wrport_we; -wire [23:0] litedramcore_bankmachine7_wrport_dat_w; -wire litedramcore_bankmachine7_do_read; -wire [3:0] litedramcore_bankmachine7_rdport_adr; -wire [23:0] litedramcore_bankmachine7_rdport_dat_r; -wire litedramcore_bankmachine7_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine7_fifo_in_payload_addr; -wire litedramcore_bankmachine7_fifo_in_first; -wire litedramcore_bankmachine7_fifo_in_last; -wire litedramcore_bankmachine7_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine7_fifo_out_payload_addr; -wire litedramcore_bankmachine7_fifo_out_first; -wire litedramcore_bankmachine7_fifo_out_last; -wire litedramcore_bankmachine7_sink_sink_valid; -wire litedramcore_bankmachine7_sink_sink_ready; -wire litedramcore_bankmachine7_sink_sink_first; -wire litedramcore_bankmachine7_sink_sink_last; -wire litedramcore_bankmachine7_sink_sink_payload_we; -wire [20:0] litedramcore_bankmachine7_sink_sink_payload_addr; -wire litedramcore_bankmachine7_source_source_valid; -wire litedramcore_bankmachine7_source_source_ready; -wire litedramcore_bankmachine7_source_source_first; -wire litedramcore_bankmachine7_source_source_last; -wire litedramcore_bankmachine7_source_source_payload_we; -wire [20:0] litedramcore_bankmachine7_source_source_payload_addr; -wire litedramcore_bankmachine7_pipe_valid_sink_valid; -wire litedramcore_bankmachine7_pipe_valid_sink_ready; -wire litedramcore_bankmachine7_pipe_valid_sink_first; -wire litedramcore_bankmachine7_pipe_valid_sink_last; -wire litedramcore_bankmachine7_pipe_valid_sink_payload_we; -wire [20:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine7_pipe_valid_source_ready; -reg litedramcore_bankmachine7_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine7_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine7_row = 14'd0; -reg litedramcore_bankmachine7_row_opened = 1'd0; -wire litedramcore_bankmachine7_row_hit; -reg litedramcore_bankmachine7_row_open = 1'd0; -reg litedramcore_bankmachine7_row_close = 1'd0; -reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine7_twtpcon_valid; +reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine6_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine6_wrport_adr = 4'd0; +wire [23:0] main_litedramcore_bankmachine6_wrport_dat_r; +wire [23:0] main_litedramcore_bankmachine6_wrport_dat_w; +wire main_litedramcore_bankmachine6_wrport_we; +reg main_litedramcore_bankmachine7_auto_precharge = 1'd0; +reg [13:0] main_litedramcore_bankmachine7_cmd_payload_a = 14'd0; +wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba; +reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine7_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine7_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine7_consume = 4'd0; +wire main_litedramcore_bankmachine7_do_read; +wire main_litedramcore_bankmachine7_fifo_in_first; +wire main_litedramcore_bankmachine7_fifo_in_last; +wire [20:0] main_litedramcore_bankmachine7_fifo_in_payload_addr; +wire main_litedramcore_bankmachine7_fifo_in_payload_we; +wire main_litedramcore_bankmachine7_fifo_out_first; +wire main_litedramcore_bankmachine7_fifo_out_last; +wire [20:0] main_litedramcore_bankmachine7_fifo_out_payload_addr; +wire main_litedramcore_bankmachine7_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine7_level = 5'd0; +wire main_litedramcore_bankmachine7_pipe_valid_sink_first; +wire main_litedramcore_bankmachine7_pipe_valid_sink_last; +wire [20:0] main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine7_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine7_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine7_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine7_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine7_pipe_valid_source_last = 1'd0; +reg [20:0] main_litedramcore_bankmachine7_pipe_valid_source_payload_addr = 21'd0; +reg main_litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine7_pipe_valid_source_ready; +reg main_litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine7_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine7_rdport_adr; +wire [23:0] main_litedramcore_bankmachine7_rdport_dat_r; +reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine7_refresh_req; +reg main_litedramcore_bankmachine7_replace = 1'd0; +wire [20:0] main_litedramcore_bankmachine7_req_addr; +wire main_litedramcore_bankmachine7_req_lock; +reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine7_req_ready; +wire main_litedramcore_bankmachine7_req_valid; +reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine7_req_we; +reg [13:0] main_litedramcore_bankmachine7_row = 14'd0; +reg main_litedramcore_bankmachine7_row_close = 1'd0; +reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine7_row_hit; +reg main_litedramcore_bankmachine7_row_open = 1'd0; +reg main_litedramcore_bankmachine7_row_opened = 1'd0; +reg main_litedramcore_bankmachine7_sink_first = 1'd0; +reg main_litedramcore_bankmachine7_sink_last = 1'd0; +wire [20:0] main_litedramcore_bankmachine7_sink_payload_addr; +wire main_litedramcore_bankmachine7_sink_payload_we; +wire main_litedramcore_bankmachine7_sink_ready; +wire main_litedramcore_bankmachine7_sink_sink_first; +wire main_litedramcore_bankmachine7_sink_sink_last; +wire [20:0] main_litedramcore_bankmachine7_sink_sink_payload_addr; +wire main_litedramcore_bankmachine7_sink_sink_payload_we; +wire main_litedramcore_bankmachine7_sink_sink_ready; +wire main_litedramcore_bankmachine7_sink_sink_valid; +wire main_litedramcore_bankmachine7_sink_valid; +wire main_litedramcore_bankmachine7_source_first; +wire main_litedramcore_bankmachine7_source_last; +wire [20:0] main_litedramcore_bankmachine7_source_payload_addr; +wire main_litedramcore_bankmachine7_source_payload_we; +wire main_litedramcore_bankmachine7_source_ready; +wire main_litedramcore_bankmachine7_source_source_first; +wire main_litedramcore_bankmachine7_source_source_last; +wire [20:0] main_litedramcore_bankmachine7_source_source_payload_addr; +wire main_litedramcore_bankmachine7_source_source_payload_we; +wire main_litedramcore_bankmachine7_source_source_ready; +wire main_litedramcore_bankmachine7_source_source_valid; +wire main_litedramcore_bankmachine7_source_valid; +wire [23:0] main_litedramcore_bankmachine7_syncfifo7_din; +wire [23:0] main_litedramcore_bankmachine7_syncfifo7_dout; +wire main_litedramcore_bankmachine7_syncfifo7_re; +wire main_litedramcore_bankmachine7_syncfifo7_readable; +wire main_litedramcore_bankmachine7_syncfifo7_we; +wire main_litedramcore_bankmachine7_syncfifo7_writable; +reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; -wire litedramcore_bankmachine7_trccon_valid; +reg main_litedramcore_bankmachine7_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine7_trascon_valid; +reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0; -wire litedramcore_bankmachine7_trascon_valid; +reg main_litedramcore_bankmachine7_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine7_trccon_valid; +reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine7_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0; -wire litedramcore_ras_allowed; -wire litedramcore_cas_allowed; -wire [1:0] litedramcore_rdcmdphase; -wire [1:0] litedramcore_wrcmdphase; -reg litedramcore_choose_cmd_want_reads = 1'd0; -reg litedramcore_choose_cmd_want_writes = 1'd0; -reg litedramcore_choose_cmd_want_cmds = 1'd0; -reg litedramcore_choose_cmd_want_activates = 1'd0; -wire litedramcore_choose_cmd_cmd_valid; -reg litedramcore_choose_cmd_cmd_ready = 1'd0; -wire [13:0] litedramcore_choose_cmd_cmd_payload_a; -wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; -reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; -wire litedramcore_choose_cmd_cmd_payload_is_cmd; -wire litedramcore_choose_cmd_cmd_payload_is_read; -wire litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] litedramcore_choose_cmd_valids = 8'd0; -wire [7:0] litedramcore_choose_cmd_request; -reg [2:0] litedramcore_choose_cmd_grant = 3'd0; -wire litedramcore_choose_cmd_ce; -reg litedramcore_choose_req_want_reads = 1'd0; -reg litedramcore_choose_req_want_writes = 1'd0; -reg litedramcore_choose_req_want_cmds = 1'd0; -reg litedramcore_choose_req_want_activates = 1'd0; -wire litedramcore_choose_req_cmd_valid; -reg litedramcore_choose_req_cmd_ready = 1'd0; -wire [13:0] litedramcore_choose_req_cmd_payload_a; -wire [2:0] litedramcore_choose_req_cmd_payload_ba; -reg litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg litedramcore_choose_req_cmd_payload_we = 1'd0; -wire litedramcore_choose_req_cmd_payload_is_cmd; -wire litedramcore_choose_req_cmd_payload_is_read; -wire litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] litedramcore_choose_req_valids = 8'd0; -wire [7:0] litedramcore_choose_req_request; -reg [2:0] litedramcore_choose_req_grant = 3'd0; -wire litedramcore_choose_req_ce; -reg [13:0] litedramcore_nop_a = 14'd0; -reg [2:0] litedramcore_nop_ba = 3'd0; -reg [1:0] litedramcore_steerer_sel0 = 2'd0; -reg [1:0] litedramcore_steerer_sel1 = 2'd0; -reg [1:0] litedramcore_steerer_sel2 = 2'd0; -reg [1:0] litedramcore_steerer_sel3 = 2'd0; -reg litedramcore_steerer0 = 1'd1; -reg litedramcore_steerer1 = 1'd1; -reg litedramcore_steerer2 = 1'd1; -reg litedramcore_steerer3 = 1'd1; -reg litedramcore_steerer4 = 1'd1; -reg litedramcore_steerer5 = 1'd1; -reg litedramcore_steerer6 = 1'd1; -reg litedramcore_steerer7 = 1'd1; -wire litedramcore_trrdcon_valid; +reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine7_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine7_wrport_adr = 4'd0; +wire [23:0] main_litedramcore_bankmachine7_wrport_dat_r; +wire [23:0] main_litedramcore_bankmachine7_wrport_dat_w; +wire main_litedramcore_bankmachine7_wrport_we; +wire main_litedramcore_cas_allowed; +wire main_litedramcore_choose_cmd_ce; +wire [13:0] main_litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba; +reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +wire main_litedramcore_choose_cmd_cmd_payload_is_cmd; +wire main_litedramcore_choose_cmd_cmd_payload_is_read; +wire main_litedramcore_choose_cmd_cmd_payload_is_write; +reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0; +reg main_litedramcore_choose_cmd_cmd_ready = 1'd0; +wire main_litedramcore_choose_cmd_cmd_valid; +reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0; +wire [7:0] main_litedramcore_choose_cmd_request; +reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0; +reg main_litedramcore_choose_cmd_want_activates = 1'd0; +reg main_litedramcore_choose_cmd_want_cmds = 1'd0; +reg main_litedramcore_choose_cmd_want_reads = 1'd0; +reg main_litedramcore_choose_cmd_want_writes = 1'd0; +wire main_litedramcore_choose_req_ce; +wire [13:0] main_litedramcore_choose_req_cmd_payload_a; +wire [2:0] main_litedramcore_choose_req_cmd_payload_ba; +reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0; +wire main_litedramcore_choose_req_cmd_payload_is_cmd; +wire main_litedramcore_choose_req_cmd_payload_is_read; +wire main_litedramcore_choose_req_cmd_payload_is_write; +reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_we = 1'd0; +reg main_litedramcore_choose_req_cmd_ready = 1'd0; +wire main_litedramcore_choose_req_cmd_valid; +reg [2:0] main_litedramcore_choose_req_grant = 3'd0; +wire [7:0] main_litedramcore_choose_req_request; +reg [7:0] main_litedramcore_choose_req_valids = 8'd0; +reg main_litedramcore_choose_req_want_activates = 1'd0; +reg main_litedramcore_choose_req_want_cmds = 1'd0; +reg main_litedramcore_choose_req_want_reads = 1'd0; +reg main_litedramcore_choose_req_want_writes = 1'd0; +wire main_litedramcore_cke; +reg main_litedramcore_cmd_last = 1'd0; +reg [13:0] main_litedramcore_cmd_payload_a = 14'd0; +reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0; +reg main_litedramcore_cmd_payload_cas = 1'd0; +reg main_litedramcore_cmd_payload_is_read = 1'd0; +reg main_litedramcore_cmd_payload_is_write = 1'd0; +reg main_litedramcore_cmd_payload_ras = 1'd0; +reg main_litedramcore_cmd_payload_we = 1'd0; +reg main_litedramcore_cmd_ready = 1'd0; +reg main_litedramcore_cmd_valid = 1'd0; +reg main_litedramcore_csr_dfi_p0_act_n = 1'd1; +wire [13:0] main_litedramcore_csr_dfi_p0_address; +wire [2:0] main_litedramcore_csr_dfi_p0_bank; +reg main_litedramcore_csr_dfi_p0_cas_n = 1'd1; +reg main_litedramcore_csr_dfi_p0_cke = 1'd0; +reg main_litedramcore_csr_dfi_p0_cs_n = 1'd1; +reg main_litedramcore_csr_dfi_p0_odt = 1'd0; +reg main_litedramcore_csr_dfi_p0_ras_n = 1'd1; +reg [31:0] main_litedramcore_csr_dfi_p0_rddata = 32'd0; +wire main_litedramcore_csr_dfi_p0_rddata_en; +reg main_litedramcore_csr_dfi_p0_rddata_valid = 1'd0; +wire main_litedramcore_csr_dfi_p0_reset_n; +reg main_litedramcore_csr_dfi_p0_we_n = 1'd1; +wire [31:0] main_litedramcore_csr_dfi_p0_wrdata; +wire main_litedramcore_csr_dfi_p0_wrdata_en; +wire [3:0] main_litedramcore_csr_dfi_p0_wrdata_mask; +reg main_litedramcore_csr_dfi_p1_act_n = 1'd1; +wire [13:0] main_litedramcore_csr_dfi_p1_address; +wire [2:0] main_litedramcore_csr_dfi_p1_bank; +reg main_litedramcore_csr_dfi_p1_cas_n = 1'd1; +reg main_litedramcore_csr_dfi_p1_cke = 1'd0; +reg main_litedramcore_csr_dfi_p1_cs_n = 1'd1; +reg main_litedramcore_csr_dfi_p1_odt = 1'd0; +reg main_litedramcore_csr_dfi_p1_ras_n = 1'd1; +reg [31:0] main_litedramcore_csr_dfi_p1_rddata = 32'd0; +wire main_litedramcore_csr_dfi_p1_rddata_en; +reg main_litedramcore_csr_dfi_p1_rddata_valid = 1'd0; +wire main_litedramcore_csr_dfi_p1_reset_n; +reg main_litedramcore_csr_dfi_p1_we_n = 1'd1; +wire [31:0] main_litedramcore_csr_dfi_p1_wrdata; +wire main_litedramcore_csr_dfi_p1_wrdata_en; +wire [3:0] main_litedramcore_csr_dfi_p1_wrdata_mask; +reg main_litedramcore_csr_dfi_p2_act_n = 1'd1; +wire [13:0] main_litedramcore_csr_dfi_p2_address; +wire [2:0] main_litedramcore_csr_dfi_p2_bank; +reg main_litedramcore_csr_dfi_p2_cas_n = 1'd1; +reg main_litedramcore_csr_dfi_p2_cke = 1'd0; +reg main_litedramcore_csr_dfi_p2_cs_n = 1'd1; +reg main_litedramcore_csr_dfi_p2_odt = 1'd0; +reg main_litedramcore_csr_dfi_p2_ras_n = 1'd1; +reg [31:0] main_litedramcore_csr_dfi_p2_rddata = 32'd0; +wire main_litedramcore_csr_dfi_p2_rddata_en; +reg main_litedramcore_csr_dfi_p2_rddata_valid = 1'd0; +wire main_litedramcore_csr_dfi_p2_reset_n; +reg main_litedramcore_csr_dfi_p2_we_n = 1'd1; +wire [31:0] main_litedramcore_csr_dfi_p2_wrdata; +wire main_litedramcore_csr_dfi_p2_wrdata_en; +wire [3:0] main_litedramcore_csr_dfi_p2_wrdata_mask; +reg main_litedramcore_csr_dfi_p3_act_n = 1'd1; +wire [13:0] main_litedramcore_csr_dfi_p3_address; +wire [2:0] main_litedramcore_csr_dfi_p3_bank; +reg main_litedramcore_csr_dfi_p3_cas_n = 1'd1; +reg main_litedramcore_csr_dfi_p3_cke = 1'd0; +reg main_litedramcore_csr_dfi_p3_cs_n = 1'd1; +reg main_litedramcore_csr_dfi_p3_odt = 1'd0; +reg main_litedramcore_csr_dfi_p3_ras_n = 1'd1; +reg [31:0] main_litedramcore_csr_dfi_p3_rddata = 32'd0; +wire main_litedramcore_csr_dfi_p3_rddata_en; +reg main_litedramcore_csr_dfi_p3_rddata_valid = 1'd0; +wire main_litedramcore_csr_dfi_p3_reset_n; +reg main_litedramcore_csr_dfi_p3_we_n = 1'd1; +wire [31:0] main_litedramcore_csr_dfi_p3_wrdata; +wire main_litedramcore_csr_dfi_p3_wrdata_en; +wire [3:0] main_litedramcore_csr_dfi_p3_wrdata_mask; +reg main_litedramcore_dfi_p0_act_n = 1'd1; +reg [13:0] main_litedramcore_dfi_p0_address = 14'd0; +reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0; +reg main_litedramcore_dfi_p0_cas_n = 1'd1; +wire main_litedramcore_dfi_p0_cke; +reg main_litedramcore_dfi_p0_cs_n = 1'd1; +wire main_litedramcore_dfi_p0_odt; +reg main_litedramcore_dfi_p0_ras_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p0_rddata; +reg main_litedramcore_dfi_p0_rddata_en = 1'd0; +wire main_litedramcore_dfi_p0_rddata_valid; +wire main_litedramcore_dfi_p0_reset_n; +reg main_litedramcore_dfi_p0_we_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p0_wrdata; +reg main_litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p0_wrdata_mask; +reg main_litedramcore_dfi_p1_act_n = 1'd1; +reg [13:0] main_litedramcore_dfi_p1_address = 14'd0; +reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0; +reg main_litedramcore_dfi_p1_cas_n = 1'd1; +wire main_litedramcore_dfi_p1_cke; +reg main_litedramcore_dfi_p1_cs_n = 1'd1; +wire main_litedramcore_dfi_p1_odt; +reg main_litedramcore_dfi_p1_ras_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p1_rddata; +reg main_litedramcore_dfi_p1_rddata_en = 1'd0; +wire main_litedramcore_dfi_p1_rddata_valid; +wire main_litedramcore_dfi_p1_reset_n; +reg main_litedramcore_dfi_p1_we_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p1_wrdata; +reg main_litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p1_wrdata_mask; +reg main_litedramcore_dfi_p2_act_n = 1'd1; +reg [13:0] main_litedramcore_dfi_p2_address = 14'd0; +reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0; +reg main_litedramcore_dfi_p2_cas_n = 1'd1; +wire main_litedramcore_dfi_p2_cke; +reg main_litedramcore_dfi_p2_cs_n = 1'd1; +wire main_litedramcore_dfi_p2_odt; +reg main_litedramcore_dfi_p2_ras_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p2_rddata; +reg main_litedramcore_dfi_p2_rddata_en = 1'd0; +wire main_litedramcore_dfi_p2_rddata_valid; +wire main_litedramcore_dfi_p2_reset_n; +reg main_litedramcore_dfi_p2_we_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p2_wrdata; +reg main_litedramcore_dfi_p2_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p2_wrdata_mask; +reg main_litedramcore_dfi_p3_act_n = 1'd1; +reg [13:0] main_litedramcore_dfi_p3_address = 14'd0; +reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0; +reg main_litedramcore_dfi_p3_cas_n = 1'd1; +wire main_litedramcore_dfi_p3_cke; +reg main_litedramcore_dfi_p3_cs_n = 1'd1; +wire main_litedramcore_dfi_p3_odt; +reg main_litedramcore_dfi_p3_ras_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p3_rddata; +reg main_litedramcore_dfi_p3_rddata_en = 1'd0; +wire main_litedramcore_dfi_p3_rddata_valid; +wire main_litedramcore_dfi_p3_reset_n; +reg main_litedramcore_dfi_p3_we_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p3_wrdata; +reg main_litedramcore_dfi_p3_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p3_wrdata_mask; +reg main_litedramcore_en0 = 1'd0; +reg main_litedramcore_en1 = 1'd0; +reg main_litedramcore_ext_dfi_p0_act_n = 1'd1; +reg [13:0] main_litedramcore_ext_dfi_p0_address = 14'd0; +reg [2:0] main_litedramcore_ext_dfi_p0_bank = 3'd0; +reg main_litedramcore_ext_dfi_p0_cas_n = 1'd1; +reg main_litedramcore_ext_dfi_p0_cke = 1'd0; +reg main_litedramcore_ext_dfi_p0_cs_n = 1'd1; +reg main_litedramcore_ext_dfi_p0_odt = 1'd0; +reg main_litedramcore_ext_dfi_p0_ras_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p0_rddata = 32'd0; +reg main_litedramcore_ext_dfi_p0_rddata_en = 1'd0; +reg main_litedramcore_ext_dfi_p0_rddata_valid = 1'd0; +reg main_litedramcore_ext_dfi_p0_reset_n = 1'd0; +reg main_litedramcore_ext_dfi_p0_we_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p0_wrdata = 32'd0; +reg main_litedramcore_ext_dfi_p0_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_ext_dfi_p0_wrdata_mask = 4'd0; +reg main_litedramcore_ext_dfi_p1_act_n = 1'd1; +reg [13:0] main_litedramcore_ext_dfi_p1_address = 14'd0; +reg [2:0] main_litedramcore_ext_dfi_p1_bank = 3'd0; +reg main_litedramcore_ext_dfi_p1_cas_n = 1'd1; +reg main_litedramcore_ext_dfi_p1_cke = 1'd0; +reg main_litedramcore_ext_dfi_p1_cs_n = 1'd1; +reg main_litedramcore_ext_dfi_p1_odt = 1'd0; +reg main_litedramcore_ext_dfi_p1_ras_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p1_rddata = 32'd0; +reg main_litedramcore_ext_dfi_p1_rddata_en = 1'd0; +reg main_litedramcore_ext_dfi_p1_rddata_valid = 1'd0; +reg main_litedramcore_ext_dfi_p1_reset_n = 1'd0; +reg main_litedramcore_ext_dfi_p1_we_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p1_wrdata = 32'd0; +reg main_litedramcore_ext_dfi_p1_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_ext_dfi_p1_wrdata_mask = 4'd0; +reg main_litedramcore_ext_dfi_p2_act_n = 1'd1; +reg [13:0] main_litedramcore_ext_dfi_p2_address = 14'd0; +reg [2:0] main_litedramcore_ext_dfi_p2_bank = 3'd0; +reg main_litedramcore_ext_dfi_p2_cas_n = 1'd1; +reg main_litedramcore_ext_dfi_p2_cke = 1'd0; +reg main_litedramcore_ext_dfi_p2_cs_n = 1'd1; +reg main_litedramcore_ext_dfi_p2_odt = 1'd0; +reg main_litedramcore_ext_dfi_p2_ras_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p2_rddata = 32'd0; +reg main_litedramcore_ext_dfi_p2_rddata_en = 1'd0; +reg main_litedramcore_ext_dfi_p2_rddata_valid = 1'd0; +reg main_litedramcore_ext_dfi_p2_reset_n = 1'd0; +reg main_litedramcore_ext_dfi_p2_we_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p2_wrdata = 32'd0; +reg main_litedramcore_ext_dfi_p2_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_ext_dfi_p2_wrdata_mask = 4'd0; +reg main_litedramcore_ext_dfi_p3_act_n = 1'd1; +reg [13:0] main_litedramcore_ext_dfi_p3_address = 14'd0; +reg [2:0] main_litedramcore_ext_dfi_p3_bank = 3'd0; +reg main_litedramcore_ext_dfi_p3_cas_n = 1'd1; +reg main_litedramcore_ext_dfi_p3_cke = 1'd0; +reg main_litedramcore_ext_dfi_p3_cs_n = 1'd1; +reg main_litedramcore_ext_dfi_p3_odt = 1'd0; +reg main_litedramcore_ext_dfi_p3_ras_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p3_rddata = 32'd0; +reg main_litedramcore_ext_dfi_p3_rddata_en = 1'd0; +reg main_litedramcore_ext_dfi_p3_rddata_valid = 1'd0; +reg main_litedramcore_ext_dfi_p3_reset_n = 1'd0; +reg main_litedramcore_ext_dfi_p3_we_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p3_wrdata = 32'd0; +reg main_litedramcore_ext_dfi_p3_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_ext_dfi_p3_wrdata_mask = 4'd0; +reg main_litedramcore_ext_dfi_sel = 1'd0; +wire main_litedramcore_go_to_refresh; +wire [20:0] main_litedramcore_interface_bank0_addr; +wire main_litedramcore_interface_bank0_lock; +wire main_litedramcore_interface_bank0_rdata_valid; +wire main_litedramcore_interface_bank0_ready; +wire main_litedramcore_interface_bank0_valid; +wire main_litedramcore_interface_bank0_wdata_ready; +wire main_litedramcore_interface_bank0_we; +wire [20:0] main_litedramcore_interface_bank1_addr; +wire main_litedramcore_interface_bank1_lock; +wire main_litedramcore_interface_bank1_rdata_valid; +wire main_litedramcore_interface_bank1_ready; +wire main_litedramcore_interface_bank1_valid; +wire main_litedramcore_interface_bank1_wdata_ready; +wire main_litedramcore_interface_bank1_we; +wire [20:0] main_litedramcore_interface_bank2_addr; +wire main_litedramcore_interface_bank2_lock; +wire main_litedramcore_interface_bank2_rdata_valid; +wire main_litedramcore_interface_bank2_ready; +wire main_litedramcore_interface_bank2_valid; +wire main_litedramcore_interface_bank2_wdata_ready; +wire main_litedramcore_interface_bank2_we; +wire [20:0] main_litedramcore_interface_bank3_addr; +wire main_litedramcore_interface_bank3_lock; +wire main_litedramcore_interface_bank3_rdata_valid; +wire main_litedramcore_interface_bank3_ready; +wire main_litedramcore_interface_bank3_valid; +wire main_litedramcore_interface_bank3_wdata_ready; +wire main_litedramcore_interface_bank3_we; +wire [20:0] main_litedramcore_interface_bank4_addr; +wire main_litedramcore_interface_bank4_lock; +wire main_litedramcore_interface_bank4_rdata_valid; +wire main_litedramcore_interface_bank4_ready; +wire main_litedramcore_interface_bank4_valid; +wire main_litedramcore_interface_bank4_wdata_ready; +wire main_litedramcore_interface_bank4_we; +wire [20:0] main_litedramcore_interface_bank5_addr; +wire main_litedramcore_interface_bank5_lock; +wire main_litedramcore_interface_bank5_rdata_valid; +wire main_litedramcore_interface_bank5_ready; +wire main_litedramcore_interface_bank5_valid; +wire main_litedramcore_interface_bank5_wdata_ready; +wire main_litedramcore_interface_bank5_we; +wire [20:0] main_litedramcore_interface_bank6_addr; +wire main_litedramcore_interface_bank6_lock; +wire main_litedramcore_interface_bank6_rdata_valid; +wire main_litedramcore_interface_bank6_ready; +wire main_litedramcore_interface_bank6_valid; +wire main_litedramcore_interface_bank6_wdata_ready; +wire main_litedramcore_interface_bank6_we; +wire [20:0] main_litedramcore_interface_bank7_addr; +wire main_litedramcore_interface_bank7_lock; +wire main_litedramcore_interface_bank7_rdata_valid; +wire main_litedramcore_interface_bank7_ready; +wire main_litedramcore_interface_bank7_valid; +wire main_litedramcore_interface_bank7_wdata_ready; +wire main_litedramcore_interface_bank7_we; +wire [127:0] main_litedramcore_interface_rdata; +reg [127:0] main_litedramcore_interface_wdata = 128'd0; +reg [15:0] main_litedramcore_interface_wdata_we = 16'd0; +reg main_litedramcore_master_p0_act_n = 1'd1; +reg [13:0] main_litedramcore_master_p0_address = 14'd0; +reg [2:0] main_litedramcore_master_p0_bank = 3'd0; +reg main_litedramcore_master_p0_cas_n = 1'd1; +reg main_litedramcore_master_p0_cke = 1'd0; +reg main_litedramcore_master_p0_cs_n = 1'd1; +reg main_litedramcore_master_p0_odt = 1'd0; +reg main_litedramcore_master_p0_ras_n = 1'd1; +wire [31:0] main_litedramcore_master_p0_rddata; +reg main_litedramcore_master_p0_rddata_en = 1'd0; +wire main_litedramcore_master_p0_rddata_valid; +reg main_litedramcore_master_p0_reset_n = 1'd0; +reg main_litedramcore_master_p0_we_n = 1'd1; +reg [31:0] main_litedramcore_master_p0_wrdata = 32'd0; +reg main_litedramcore_master_p0_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0; +reg main_litedramcore_master_p1_act_n = 1'd1; +reg [13:0] main_litedramcore_master_p1_address = 14'd0; +reg [2:0] main_litedramcore_master_p1_bank = 3'd0; +reg main_litedramcore_master_p1_cas_n = 1'd1; +reg main_litedramcore_master_p1_cke = 1'd0; +reg main_litedramcore_master_p1_cs_n = 1'd1; +reg main_litedramcore_master_p1_odt = 1'd0; +reg main_litedramcore_master_p1_ras_n = 1'd1; +wire [31:0] main_litedramcore_master_p1_rddata; +reg main_litedramcore_master_p1_rddata_en = 1'd0; +wire main_litedramcore_master_p1_rddata_valid; +reg main_litedramcore_master_p1_reset_n = 1'd0; +reg main_litedramcore_master_p1_we_n = 1'd1; +reg [31:0] main_litedramcore_master_p1_wrdata = 32'd0; +reg main_litedramcore_master_p1_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0; +reg main_litedramcore_master_p2_act_n = 1'd1; +reg [13:0] main_litedramcore_master_p2_address = 14'd0; +reg [2:0] main_litedramcore_master_p2_bank = 3'd0; +reg main_litedramcore_master_p2_cas_n = 1'd1; +reg main_litedramcore_master_p2_cke = 1'd0; +reg main_litedramcore_master_p2_cs_n = 1'd1; +reg main_litedramcore_master_p2_odt = 1'd0; +reg main_litedramcore_master_p2_ras_n = 1'd1; +wire [31:0] main_litedramcore_master_p2_rddata; +reg main_litedramcore_master_p2_rddata_en = 1'd0; +wire main_litedramcore_master_p2_rddata_valid; +reg main_litedramcore_master_p2_reset_n = 1'd0; +reg main_litedramcore_master_p2_we_n = 1'd1; +reg [31:0] main_litedramcore_master_p2_wrdata = 32'd0; +reg main_litedramcore_master_p2_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0; +reg main_litedramcore_master_p3_act_n = 1'd1; +reg [13:0] main_litedramcore_master_p3_address = 14'd0; +reg [2:0] main_litedramcore_master_p3_bank = 3'd0; +reg main_litedramcore_master_p3_cas_n = 1'd1; +reg main_litedramcore_master_p3_cke = 1'd0; +reg main_litedramcore_master_p3_cs_n = 1'd1; +reg main_litedramcore_master_p3_odt = 1'd0; +reg main_litedramcore_master_p3_ras_n = 1'd1; +wire [31:0] main_litedramcore_master_p3_rddata; +reg main_litedramcore_master_p3_rddata_en = 1'd0; +wire main_litedramcore_master_p3_rddata_valid; +reg main_litedramcore_master_p3_reset_n = 1'd0; +reg main_litedramcore_master_p3_we_n = 1'd1; +reg [31:0] main_litedramcore_master_p3_wrdata = 32'd0; +reg main_litedramcore_master_p3_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0; +wire main_litedramcore_max_time0; +wire main_litedramcore_max_time1; +reg [13:0] main_litedramcore_nop_a = 14'd0; +reg [2:0] main_litedramcore_nop_ba = 3'd0; +wire [1:0] main_litedramcore_nphases; +wire main_litedramcore_odt; +reg main_litedramcore_phaseinjector0_address_re = 1'd0; +reg [13:0] main_litedramcore_phaseinjector0_address_storage = 14'd0; +reg main_litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0; +wire main_litedramcore_phaseinjector0_command_issue_r; +reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector0_command_re = 1'd0; +reg [7:0] main_litedramcore_phaseinjector0_command_storage = 8'd0; +wire main_litedramcore_phaseinjector0_csrfield_cas; +wire main_litedramcore_phaseinjector0_csrfield_cs; +wire main_litedramcore_phaseinjector0_csrfield_cs_bottom; +wire main_litedramcore_phaseinjector0_csrfield_cs_top; +wire main_litedramcore_phaseinjector0_csrfield_ras; +wire main_litedramcore_phaseinjector0_csrfield_rden; +wire main_litedramcore_phaseinjector0_csrfield_we; +wire main_litedramcore_phaseinjector0_csrfield_wren; +reg main_litedramcore_phaseinjector0_rddata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector0_rddata_we; +reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector1_address_re = 1'd0; +reg [13:0] main_litedramcore_phaseinjector1_address_storage = 14'd0; +reg main_litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0; +wire main_litedramcore_phaseinjector1_command_issue_r; +reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector1_command_re = 1'd0; +reg [7:0] main_litedramcore_phaseinjector1_command_storage = 8'd0; +wire main_litedramcore_phaseinjector1_csrfield_cas; +wire main_litedramcore_phaseinjector1_csrfield_cs; +wire main_litedramcore_phaseinjector1_csrfield_cs_bottom; +wire main_litedramcore_phaseinjector1_csrfield_cs_top; +wire main_litedramcore_phaseinjector1_csrfield_ras; +wire main_litedramcore_phaseinjector1_csrfield_rden; +wire main_litedramcore_phaseinjector1_csrfield_we; +wire main_litedramcore_phaseinjector1_csrfield_wren; +reg main_litedramcore_phaseinjector1_rddata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector1_rddata_we; +reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector2_address_re = 1'd0; +reg [13:0] main_litedramcore_phaseinjector2_address_storage = 14'd0; +reg main_litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0; +wire main_litedramcore_phaseinjector2_command_issue_r; +reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector2_command_re = 1'd0; +reg [7:0] main_litedramcore_phaseinjector2_command_storage = 8'd0; +wire main_litedramcore_phaseinjector2_csrfield_cas; +wire main_litedramcore_phaseinjector2_csrfield_cs; +wire main_litedramcore_phaseinjector2_csrfield_cs_bottom; +wire main_litedramcore_phaseinjector2_csrfield_cs_top; +wire main_litedramcore_phaseinjector2_csrfield_ras; +wire main_litedramcore_phaseinjector2_csrfield_rden; +wire main_litedramcore_phaseinjector2_csrfield_we; +wire main_litedramcore_phaseinjector2_csrfield_wren; +reg main_litedramcore_phaseinjector2_rddata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector2_rddata_we; +reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector3_address_re = 1'd0; +reg [13:0] main_litedramcore_phaseinjector3_address_storage = 14'd0; +reg main_litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0; +wire main_litedramcore_phaseinjector3_command_issue_r; +reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector3_command_re = 1'd0; +reg [7:0] main_litedramcore_phaseinjector3_command_storage = 8'd0; +wire main_litedramcore_phaseinjector3_csrfield_cas; +wire main_litedramcore_phaseinjector3_csrfield_cs; +wire main_litedramcore_phaseinjector3_csrfield_cs_bottom; +wire main_litedramcore_phaseinjector3_csrfield_cs_top; +wire main_litedramcore_phaseinjector3_csrfield_ras; +wire main_litedramcore_phaseinjector3_csrfield_rden; +wire main_litedramcore_phaseinjector3_csrfield_we; +wire main_litedramcore_phaseinjector3_csrfield_wren; +reg main_litedramcore_phaseinjector3_rddata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector3_rddata_we; +reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0; +reg main_litedramcore_postponer_count = 1'd0; +wire main_litedramcore_postponer_req_i; +reg main_litedramcore_postponer_req_o = 1'd0; +wire main_litedramcore_ras_allowed; +wire [1:0] main_litedramcore_rdphase; +reg main_litedramcore_re = 1'd0; +wire main_litedramcore_read_available; +wire main_litedramcore_reset_n; +wire main_litedramcore_sel; +reg main_litedramcore_sequencer_count = 1'd0; +wire main_litedramcore_sequencer_done0; +reg main_litedramcore_sequencer_done1 = 1'd0; +reg main_litedramcore_sequencer_start0 = 1'd0; +wire main_litedramcore_sequencer_start1; +reg [5:0] main_litedramcore_sequencer_trigger = 6'd0; +wire main_litedramcore_slave_p0_act_n; +wire [13:0] main_litedramcore_slave_p0_address; +wire [2:0] main_litedramcore_slave_p0_bank; +wire main_litedramcore_slave_p0_cas_n; +wire main_litedramcore_slave_p0_cke; +wire main_litedramcore_slave_p0_cs_n; +wire main_litedramcore_slave_p0_odt; +wire main_litedramcore_slave_p0_ras_n; +reg [31:0] main_litedramcore_slave_p0_rddata = 32'd0; +wire main_litedramcore_slave_p0_rddata_en; +reg main_litedramcore_slave_p0_rddata_valid = 1'd0; +wire main_litedramcore_slave_p0_reset_n; +wire main_litedramcore_slave_p0_we_n; +wire [31:0] main_litedramcore_slave_p0_wrdata; +wire main_litedramcore_slave_p0_wrdata_en; +wire [3:0] main_litedramcore_slave_p0_wrdata_mask; +wire main_litedramcore_slave_p1_act_n; +wire [13:0] main_litedramcore_slave_p1_address; +wire [2:0] main_litedramcore_slave_p1_bank; +wire main_litedramcore_slave_p1_cas_n; +wire main_litedramcore_slave_p1_cke; +wire main_litedramcore_slave_p1_cs_n; +wire main_litedramcore_slave_p1_odt; +wire main_litedramcore_slave_p1_ras_n; +reg [31:0] main_litedramcore_slave_p1_rddata = 32'd0; +wire main_litedramcore_slave_p1_rddata_en; +reg main_litedramcore_slave_p1_rddata_valid = 1'd0; +wire main_litedramcore_slave_p1_reset_n; +wire main_litedramcore_slave_p1_we_n; +wire [31:0] main_litedramcore_slave_p1_wrdata; +wire main_litedramcore_slave_p1_wrdata_en; +wire [3:0] main_litedramcore_slave_p1_wrdata_mask; +wire main_litedramcore_slave_p2_act_n; +wire [13:0] main_litedramcore_slave_p2_address; +wire [2:0] main_litedramcore_slave_p2_bank; +wire main_litedramcore_slave_p2_cas_n; +wire main_litedramcore_slave_p2_cke; +wire main_litedramcore_slave_p2_cs_n; +wire main_litedramcore_slave_p2_odt; +wire main_litedramcore_slave_p2_ras_n; +reg [31:0] main_litedramcore_slave_p2_rddata = 32'd0; +wire main_litedramcore_slave_p2_rddata_en; +reg main_litedramcore_slave_p2_rddata_valid = 1'd0; +wire main_litedramcore_slave_p2_reset_n; +wire main_litedramcore_slave_p2_we_n; +wire [31:0] main_litedramcore_slave_p2_wrdata; +wire main_litedramcore_slave_p2_wrdata_en; +wire [3:0] main_litedramcore_slave_p2_wrdata_mask; +wire main_litedramcore_slave_p3_act_n; +wire [13:0] main_litedramcore_slave_p3_address; +wire [2:0] main_litedramcore_slave_p3_bank; +wire main_litedramcore_slave_p3_cas_n; +wire main_litedramcore_slave_p3_cke; +wire main_litedramcore_slave_p3_cs_n; +wire main_litedramcore_slave_p3_odt; +wire main_litedramcore_slave_p3_ras_n; +reg [31:0] main_litedramcore_slave_p3_rddata = 32'd0; +wire main_litedramcore_slave_p3_rddata_en; +reg main_litedramcore_slave_p3_rddata_valid = 1'd0; +wire main_litedramcore_slave_p3_reset_n; +wire main_litedramcore_slave_p3_we_n; +wire [31:0] main_litedramcore_slave_p3_wrdata; +wire main_litedramcore_slave_p3_wrdata_en; +wire [3:0] main_litedramcore_slave_p3_wrdata_mask; +reg [1:0] main_litedramcore_steerer0 = 2'd0; +reg [1:0] main_litedramcore_steerer1 = 2'd0; +reg main_litedramcore_steerer10 = 1'd1; +reg main_litedramcore_steerer11 = 1'd1; +reg [1:0] main_litedramcore_steerer2 = 2'd0; +reg [1:0] main_litedramcore_steerer3 = 2'd0; +reg main_litedramcore_steerer4 = 1'd1; +reg main_litedramcore_steerer5 = 1'd1; +reg main_litedramcore_steerer6 = 1'd1; +reg main_litedramcore_steerer7 = 1'd1; +reg main_litedramcore_steerer8 = 1'd1; +reg main_litedramcore_steerer9 = 1'd1; +reg [3:0] main_litedramcore_storage = 4'd1; +reg main_litedramcore_tccdcon_count = 1'd0; (* dont_touch = "true" *) -reg litedramcore_trrdcon_ready = 1'd0; -reg litedramcore_trrdcon_count = 1'd0; -wire litedramcore_tfawcon_valid; +reg main_litedramcore_tccdcon_ready = 1'd0; +wire main_litedramcore_tccdcon_valid; +wire [2:0] main_litedramcore_tfawcon_count; (* dont_touch = "true" *) -reg litedramcore_tfawcon_ready = 1'd1; -wire [2:0] litedramcore_tfawcon_count; -reg [4:0] litedramcore_tfawcon_window = 5'd0; -wire litedramcore_tccdcon_valid; +reg main_litedramcore_tfawcon_ready = 1'd1; +wire main_litedramcore_tfawcon_valid; +reg [4:0] main_litedramcore_tfawcon_window = 5'd0; +reg [4:0] main_litedramcore_time0 = 5'd0; +reg [3:0] main_litedramcore_time1 = 4'd0; +wire [9:0] main_litedramcore_timer_count0; +reg [9:0] main_litedramcore_timer_count1 = 10'd781; +wire main_litedramcore_timer_done0; +wire main_litedramcore_timer_done1; +wire main_litedramcore_timer_wait; +reg main_litedramcore_trrdcon_count = 1'd0; (* dont_touch = "true" *) -reg litedramcore_tccdcon_ready = 1'd0; -reg litedramcore_tccdcon_count = 1'd0; -wire litedramcore_twtrcon_valid; +reg main_litedramcore_trrdcon_ready = 1'd0; +wire main_litedramcore_trrdcon_valid; +reg [2:0] main_litedramcore_twtrcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_twtrcon_ready = 1'd0; -reg [2:0] litedramcore_twtrcon_count = 3'd0; -wire litedramcore_read_available; -wire litedramcore_write_available; -reg litedramcore_en0 = 1'd0; -wire litedramcore_max_time0; -reg [4:0] litedramcore_time0 = 5'd0; -reg litedramcore_en1 = 1'd0; -wire litedramcore_max_time1; -reg [3:0] litedramcore_time1 = 4'd0; -wire litedramcore_go_to_refresh; -reg init_done_storage = 1'd0; -reg init_done_re = 1'd0; -reg init_error_storage = 1'd0; -reg init_error_re = 1'd0; -wire [29:0] wb_bus_adr; -wire [31:0] wb_bus_dat_w; -wire [31:0] wb_bus_dat_r; -wire [3:0] wb_bus_sel; -wire wb_bus_cyc; -wire wb_bus_stb; -wire wb_bus_ack; -wire wb_bus_we; -wire [2:0] wb_bus_cti; -wire [1:0] wb_bus_bte; -wire wb_bus_err; -wire user_enable; -wire user_port_cmd_valid; -wire user_port_cmd_ready; -wire user_port_cmd_payload_we; -wire [23:0] user_port_cmd_payload_addr; -wire user_port_wdata_valid; -wire user_port_wdata_ready; -wire [127:0] user_port_wdata_payload_data; -wire [15:0] user_port_wdata_payload_we; -wire user_port_rdata_valid; -wire user_port_rdata_ready; -wire [127:0] user_port_rdata_payload_data; -reg [13:0] litedramcore_adr = 14'd0; -reg litedramcore_we = 1'd0; -reg [31:0] litedramcore_dat_w = 32'd0; -wire [31:0] litedramcore_dat_r; -wire [29:0] litedramcore_wishbone_adr; -wire [31:0] litedramcore_wishbone_dat_w; -reg [31:0] litedramcore_wishbone_dat_r = 32'd0; -wire [3:0] litedramcore_wishbone_sel; -wire litedramcore_wishbone_cyc; -wire litedramcore_wishbone_stb; -reg litedramcore_wishbone_ack = 1'd0; -wire litedramcore_wishbone_we; -wire [2:0] litedramcore_wishbone_cti; -wire [1:0] litedramcore_wishbone_bte; -reg litedramcore_wishbone_err = 1'd0; -wire [13:0] interface0_bank_bus_adr; -wire interface0_bank_bus_we; -wire [31:0] interface0_bank_bus_dat_w; -reg [31:0] interface0_bank_bus_dat_r = 32'd0; -reg csrbank0_init_done0_re = 1'd0; -wire csrbank0_init_done0_r; -reg csrbank0_init_done0_we = 1'd0; -wire csrbank0_init_done0_w; -reg csrbank0_init_error0_re = 1'd0; -wire csrbank0_init_error0_r; -reg csrbank0_init_error0_we = 1'd0; -wire csrbank0_init_error0_w; -wire csrbank0_sel; -wire [13:0] interface1_bank_bus_adr; -wire interface1_bank_bus_we; -wire [31:0] interface1_bank_bus_dat_w; -reg [31:0] interface1_bank_bus_dat_r = 32'd0; -reg csrbank1_rst0_re = 1'd0; -wire csrbank1_rst0_r; -reg csrbank1_rst0_we = 1'd0; -wire csrbank1_rst0_w; -reg csrbank1_dly_sel0_re = 1'd0; -wire [1:0] csrbank1_dly_sel0_r; -reg csrbank1_dly_sel0_we = 1'd0; -wire [1:0] csrbank1_dly_sel0_w; -reg csrbank1_half_sys8x_taps0_re = 1'd0; -wire [4:0] csrbank1_half_sys8x_taps0_r; -reg csrbank1_half_sys8x_taps0_we = 1'd0; -wire [4:0] csrbank1_half_sys8x_taps0_w; -reg csrbank1_wlevel_en0_re = 1'd0; -wire csrbank1_wlevel_en0_r; -reg csrbank1_wlevel_en0_we = 1'd0; -wire csrbank1_wlevel_en0_w; -reg csrbank1_rdphase0_re = 1'd0; -wire [1:0] csrbank1_rdphase0_r; -reg csrbank1_rdphase0_we = 1'd0; -wire [1:0] csrbank1_rdphase0_w; -reg csrbank1_wrphase0_re = 1'd0; -wire [1:0] csrbank1_wrphase0_r; -reg csrbank1_wrphase0_we = 1'd0; -wire [1:0] csrbank1_wrphase0_w; -wire csrbank1_sel; -wire [13:0] interface2_bank_bus_adr; -wire interface2_bank_bus_we; -wire [31:0] interface2_bank_bus_dat_w; -reg [31:0] interface2_bank_bus_dat_r = 32'd0; -reg csrbank2_dfii_control0_re = 1'd0; -wire [3:0] csrbank2_dfii_control0_r; -reg csrbank2_dfii_control0_we = 1'd0; -wire [3:0] csrbank2_dfii_control0_w; -reg csrbank2_dfii_pi0_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi0_command0_r; -reg csrbank2_dfii_pi0_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi0_command0_w; -reg csrbank2_dfii_pi0_address0_re = 1'd0; -wire [13:0] csrbank2_dfii_pi0_address0_r; -reg csrbank2_dfii_pi0_address0_we = 1'd0; -wire [13:0] csrbank2_dfii_pi0_address0_w; -reg csrbank2_dfii_pi0_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi0_baddress0_r; -reg csrbank2_dfii_pi0_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi0_baddress0_w; -reg csrbank2_dfii_pi0_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata0_r; -reg csrbank2_dfii_pi0_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata0_w; -reg csrbank2_dfii_pi0_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata_r; -reg csrbank2_dfii_pi0_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata_w; -reg csrbank2_dfii_pi1_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi1_command0_r; -reg csrbank2_dfii_pi1_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi1_command0_w; -reg csrbank2_dfii_pi1_address0_re = 1'd0; -wire [13:0] csrbank2_dfii_pi1_address0_r; -reg csrbank2_dfii_pi1_address0_we = 1'd0; -wire [13:0] csrbank2_dfii_pi1_address0_w; -reg csrbank2_dfii_pi1_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi1_baddress0_r; -reg csrbank2_dfii_pi1_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi1_baddress0_w; -reg csrbank2_dfii_pi1_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata0_r; -reg csrbank2_dfii_pi1_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata0_w; -reg csrbank2_dfii_pi1_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata_r; -reg csrbank2_dfii_pi1_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata_w; -reg csrbank2_dfii_pi2_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi2_command0_r; -reg csrbank2_dfii_pi2_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi2_command0_w; -reg csrbank2_dfii_pi2_address0_re = 1'd0; -wire [13:0] csrbank2_dfii_pi2_address0_r; -reg csrbank2_dfii_pi2_address0_we = 1'd0; -wire [13:0] csrbank2_dfii_pi2_address0_w; -reg csrbank2_dfii_pi2_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi2_baddress0_r; -reg csrbank2_dfii_pi2_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi2_baddress0_w; -reg csrbank2_dfii_pi2_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi2_wrdata0_r; -reg csrbank2_dfii_pi2_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi2_wrdata0_w; -reg csrbank2_dfii_pi2_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi2_rddata_r; -reg csrbank2_dfii_pi2_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi2_rddata_w; -reg csrbank2_dfii_pi3_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi3_command0_r; -reg csrbank2_dfii_pi3_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi3_command0_w; -reg csrbank2_dfii_pi3_address0_re = 1'd0; -wire [13:0] csrbank2_dfii_pi3_address0_r; -reg csrbank2_dfii_pi3_address0_we = 1'd0; -wire [13:0] csrbank2_dfii_pi3_address0_w; -reg csrbank2_dfii_pi3_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi3_baddress0_r; -reg csrbank2_dfii_pi3_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi3_baddress0_w; -reg csrbank2_dfii_pi3_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi3_wrdata0_r; -reg csrbank2_dfii_pi3_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi3_wrdata0_w; -reg csrbank2_dfii_pi3_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi3_rddata_r; -reg csrbank2_dfii_pi3_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi3_rddata_w; -wire csrbank2_sel; -wire [13:0] csr_interconnect_adr; -wire csr_interconnect_we; -wire [31:0] csr_interconnect_dat_w; -wire [31:0] csr_interconnect_dat_r; -wire litedramcore_reset0; -wire litedramcore_reset1; -wire litedramcore_reset2; -wire litedramcore_reset3; -wire litedramcore_reset4; -wire litedramcore_reset5; -wire litedramcore_reset6; -wire litedramcore_reset7; -wire litedramcore_pll_fb; -reg [1:0] litedramcore_refresher_state = 2'd0; -reg [1:0] litedramcore_refresher_next_state = 2'd0; -reg [3:0] litedramcore_bankmachine0_state = 4'd0; -reg [3:0] litedramcore_bankmachine0_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine1_state = 4'd0; -reg [3:0] litedramcore_bankmachine1_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine2_state = 4'd0; -reg [3:0] litedramcore_bankmachine2_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine3_state = 4'd0; -reg [3:0] litedramcore_bankmachine3_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine4_state = 4'd0; -reg [3:0] litedramcore_bankmachine4_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine5_state = 4'd0; -reg [3:0] litedramcore_bankmachine5_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine6_state = 4'd0; -reg [3:0] litedramcore_bankmachine6_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine7_state = 4'd0; -reg [3:0] litedramcore_bankmachine7_next_state = 4'd0; -reg [3:0] litedramcore_multiplexer_state = 4'd0; -reg [3:0] litedramcore_multiplexer_next_state = 4'd0; -wire litedramcore_roundrobin0_request; -wire litedramcore_roundrobin0_grant; -wire litedramcore_roundrobin0_ce; -wire litedramcore_roundrobin1_request; -wire litedramcore_roundrobin1_grant; -wire litedramcore_roundrobin1_ce; -wire litedramcore_roundrobin2_request; -wire litedramcore_roundrobin2_grant; -wire litedramcore_roundrobin2_ce; -wire litedramcore_roundrobin3_request; -wire litedramcore_roundrobin3_grant; -wire litedramcore_roundrobin3_ce; -wire litedramcore_roundrobin4_request; -wire litedramcore_roundrobin4_grant; -wire litedramcore_roundrobin4_ce; -wire litedramcore_roundrobin5_request; -wire litedramcore_roundrobin5_grant; -wire litedramcore_roundrobin5_ce; -wire litedramcore_roundrobin6_request; -wire litedramcore_roundrobin6_grant; -wire litedramcore_roundrobin6_ce; -wire litedramcore_roundrobin7_request; -wire litedramcore_roundrobin7_grant; -wire litedramcore_roundrobin7_ce; -reg litedramcore_locked0 = 1'd0; -reg litedramcore_locked1 = 1'd0; -reg litedramcore_locked2 = 1'd0; -reg litedramcore_locked3 = 1'd0; -reg litedramcore_locked4 = 1'd0; -reg litedramcore_locked5 = 1'd0; -reg litedramcore_locked6 = 1'd0; -reg litedramcore_locked7 = 1'd0; -reg litedramcore_new_master_wdata_ready0 = 1'd0; -reg litedramcore_new_master_wdata_ready1 = 1'd0; -reg litedramcore_new_master_rdata_valid0 = 1'd0; -reg litedramcore_new_master_rdata_valid1 = 1'd0; -reg litedramcore_new_master_rdata_valid2 = 1'd0; -reg litedramcore_new_master_rdata_valid3 = 1'd0; -reg litedramcore_new_master_rdata_valid4 = 1'd0; -reg litedramcore_new_master_rdata_valid5 = 1'd0; -reg litedramcore_new_master_rdata_valid6 = 1'd0; -reg litedramcore_new_master_rdata_valid7 = 1'd0; -reg litedramcore_new_master_rdata_valid8 = 1'd0; -reg [1:0] litedramcore_state = 2'd0; -reg [1:0] litedramcore_next_state = 2'd0; -reg [31:0] litedramcore_dat_w_next_value0 = 32'd0; -reg litedramcore_dat_w_next_value_ce0 = 1'd0; -reg [13:0] litedramcore_adr_next_value1 = 14'd0; -reg litedramcore_adr_next_value_ce1 = 1'd0; -reg litedramcore_we_next_value2 = 1'd0; -reg litedramcore_we_next_value_ce2 = 1'd0; -reg rhs_array_muxed0 = 1'd0; -reg [13:0] rhs_array_muxed1 = 14'd0; -reg [2:0] rhs_array_muxed2 = 3'd0; -reg rhs_array_muxed3 = 1'd0; -reg rhs_array_muxed4 = 1'd0; -reg rhs_array_muxed5 = 1'd0; -reg t_array_muxed0 = 1'd0; -reg t_array_muxed1 = 1'd0; -reg t_array_muxed2 = 1'd0; -reg rhs_array_muxed6 = 1'd0; -reg [13:0] rhs_array_muxed7 = 14'd0; -reg [2:0] rhs_array_muxed8 = 3'd0; -reg rhs_array_muxed9 = 1'd0; -reg rhs_array_muxed10 = 1'd0; -reg rhs_array_muxed11 = 1'd0; -reg t_array_muxed3 = 1'd0; -reg t_array_muxed4 = 1'd0; -reg t_array_muxed5 = 1'd0; -reg [20:0] rhs_array_muxed12 = 21'd0; -reg rhs_array_muxed13 = 1'd0; -reg rhs_array_muxed14 = 1'd0; -reg [20:0] rhs_array_muxed15 = 21'd0; -reg rhs_array_muxed16 = 1'd0; -reg rhs_array_muxed17 = 1'd0; -reg [20:0] rhs_array_muxed18 = 21'd0; -reg rhs_array_muxed19 = 1'd0; -reg rhs_array_muxed20 = 1'd0; -reg [20:0] rhs_array_muxed21 = 21'd0; -reg rhs_array_muxed22 = 1'd0; -reg rhs_array_muxed23 = 1'd0; -reg [20:0] rhs_array_muxed24 = 21'd0; -reg rhs_array_muxed25 = 1'd0; -reg rhs_array_muxed26 = 1'd0; -reg [20:0] rhs_array_muxed27 = 21'd0; -reg rhs_array_muxed28 = 1'd0; -reg rhs_array_muxed29 = 1'd0; -reg [20:0] rhs_array_muxed30 = 21'd0; -reg rhs_array_muxed31 = 1'd0; -reg rhs_array_muxed32 = 1'd0; -reg [20:0] rhs_array_muxed33 = 21'd0; -reg rhs_array_muxed34 = 1'd0; -reg rhs_array_muxed35 = 1'd0; -reg [2:0] array_muxed0 = 3'd0; -reg [13:0] array_muxed1 = 14'd0; -reg array_muxed2 = 1'd0; -reg array_muxed3 = 1'd0; -reg array_muxed4 = 1'd0; -reg array_muxed5 = 1'd0; -reg array_muxed6 = 1'd0; -reg [2:0] array_muxed7 = 3'd0; -reg [13:0] array_muxed8 = 14'd0; -reg array_muxed9 = 1'd0; -reg array_muxed10 = 1'd0; -reg array_muxed11 = 1'd0; -reg array_muxed12 = 1'd0; -reg array_muxed13 = 1'd0; -reg [2:0] array_muxed14 = 3'd0; -reg [13:0] array_muxed15 = 14'd0; -reg array_muxed16 = 1'd0; -reg array_muxed17 = 1'd0; -reg array_muxed18 = 1'd0; -reg array_muxed19 = 1'd0; -reg array_muxed20 = 1'd0; -reg [2:0] array_muxed21 = 3'd0; -reg [13:0] array_muxed22 = 14'd0; -reg array_muxed23 = 1'd0; -reg array_muxed24 = 1'd0; -reg array_muxed25 = 1'd0; -reg array_muxed26 = 1'd0; -reg array_muxed27 = 1'd0; -wire xilinxasyncresetsynchronizerimpl0; -wire xilinxasyncresetsynchronizerimpl0_rst_meta; -wire xilinxasyncresetsynchronizerimpl1; -wire xilinxasyncresetsynchronizerimpl1_rst_meta; -wire xilinxasyncresetsynchronizerimpl2; -wire xilinxasyncresetsynchronizerimpl2_rst_meta; -wire xilinxasyncresetsynchronizerimpl2_expr; -wire xilinxasyncresetsynchronizerimpl3; -wire xilinxasyncresetsynchronizerimpl3_rst_meta; -wire xilinxasyncresetsynchronizerimpl3_expr; +reg main_litedramcore_twtrcon_ready = 1'd0; +wire main_litedramcore_twtrcon_valid; +wire main_litedramcore_wants_refresh; +wire main_litedramcore_wants_zqcs; +wire main_litedramcore_write_available; +reg main_litedramcore_zqcs_executer_done = 1'd0; +reg main_litedramcore_zqcs_executer_start = 1'd0; +reg [4:0] main_litedramcore_zqcs_executer_trigger = 5'd0; +wire [26:0] main_litedramcore_zqcs_timer_count0; +reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999; +wire main_litedramcore_zqcs_timer_done0; +wire main_litedramcore_zqcs_timer_done1; +wire main_litedramcore_zqcs_timer_wait; +wire main_locked; +reg main_power_down = 1'd0; +wire main_reset; +reg [3:0] main_reset_counter = 4'd15; +reg main_rst = 1'd0; +wire main_user_enable; +wire [23:0] main_user_port_cmd_payload_addr; +wire main_user_port_cmd_payload_we; +wire main_user_port_cmd_ready; +wire main_user_port_cmd_valid; +wire [127:0] main_user_port_rdata_payload_data; +wire main_user_port_rdata_ready; +wire main_user_port_rdata_valid; +wire [127:0] main_user_port_wdata_payload_data; +wire [15:0] main_user_port_wdata_payload_we; +wire main_user_port_wdata_ready; +wire main_user_port_wdata_valid; +wire main_wb_bus_ack; +wire [29:0] main_wb_bus_adr; +wire [1:0] main_wb_bus_bte; +wire [2:0] main_wb_bus_cti; +wire main_wb_bus_cyc; +wire [31:0] main_wb_bus_dat_r; +wire [31:0] main_wb_bus_dat_w; +wire main_wb_bus_err; +wire [3:0] main_wb_bus_sel; +wire main_wb_bus_stb; +wire main_wb_bus_we; +wire sys4x_clk; +wire sys4x_dqs_clk; +wire sys_clk; +wire sys_rst; //------------------------------------------------------------------------------ // Combinatorial Logic //------------------------------------------------------------------------------ -assign init_done = init_done_storage; -assign init_error = init_error_storage; -assign wb_bus_adr = wb_ctrl_adr; -assign wb_bus_dat_w = wb_ctrl_dat_w; -assign wb_ctrl_dat_r = wb_bus_dat_r; -assign wb_bus_sel = wb_ctrl_sel; -assign wb_bus_cyc = wb_ctrl_cyc; -assign wb_bus_stb = wb_ctrl_stb; -assign wb_ctrl_ack = wb_bus_ack; -assign wb_bus_we = wb_ctrl_we; -assign wb_bus_cti = wb_ctrl_cti; -assign wb_bus_bte = wb_ctrl_bte; -assign wb_ctrl_err = wb_bus_err; +assign init_done = main_init_done_storage; +assign init_error = main_init_error_storage; +assign main_wb_bus_adr = wb_ctrl_adr; +assign main_wb_bus_dat_w = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = main_wb_bus_dat_r; +assign main_wb_bus_sel = wb_ctrl_sel; +assign main_wb_bus_cyc = wb_ctrl_cyc; +assign main_wb_bus_stb = wb_ctrl_stb; +assign wb_ctrl_ack = main_wb_bus_ack; +assign main_wb_bus_we = wb_ctrl_we; +assign main_wb_bus_cti = wb_ctrl_cti; +assign main_wb_bus_bte = wb_ctrl_bte; +assign wb_ctrl_err = main_wb_bus_err; assign user_clk = sys_clk; assign user_rst = sys_rst; -assign user_enable = 1'd1; -assign user_port_cmd_valid = (user_port_native_0_cmd_valid & user_enable); -assign user_port_native_0_cmd_ready = (user_port_cmd_ready & user_enable); -assign user_port_cmd_payload_we = user_port_native_0_cmd_we; -assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr; -assign user_port_wdata_valid = (user_port_native_0_wdata_valid & user_enable); -assign user_port_native_0_wdata_ready = (user_port_wdata_ready & user_enable); -assign user_port_wdata_payload_we = user_port_native_0_wdata_we; -assign user_port_wdata_payload_data = user_port_native_0_wdata_data; -assign user_port_native_0_rdata_valid = (user_port_rdata_valid & user_enable); -assign user_port_rdata_ready = (user_port_native_0_rdata_ready & user_enable); -assign user_port_native_0_rdata_data = user_port_rdata_payload_data; -assign reset = (rst | rst_1); -assign pll_locked = locked; -assign clkin = clk; -assign iodelay_clk = clkout_buf0; -assign sys_clk = clkout_buf1; -assign sys4x_clk = clkout_buf2; -assign sys4x_dqs_clk = clkout_buf3; -assign ddram_ba = a7ddrphy_pads_ba; -assign a7ddrphy_dqs_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dqs_oe) | a7ddrphy_dqs_postamble); -assign a7ddrphy_dq_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dq_oe) | a7ddrphy_dqs_postamble); -always @(*) begin - a7ddrphy_dfi_p0_rddata <= 32'd0; - a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0]; - a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1]; - a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0]; - a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1]; - a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0]; - a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1]; - a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0]; - a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1]; - a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0]; - a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1]; - a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0]; - a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1]; - a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0]; - a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1]; - a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0]; - a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1]; - a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0]; - a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1]; - a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0]; - a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1]; - a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0]; - a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1]; - a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0]; - a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1]; - a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0]; - a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1]; - a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0]; - a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1]; - a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0]; - a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1]; - a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0]; - a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1]; -end -always @(*) begin - a7ddrphy_dfi_p1_rddata <= 32'd0; - a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2]; - a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3]; - a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2]; - a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3]; - a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2]; - a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3]; - a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2]; - a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3]; - a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2]; - a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3]; - a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2]; - a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3]; - a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2]; - a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3]; - a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2]; - a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3]; - a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2]; - a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3]; - a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2]; - a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3]; - a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2]; - a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3]; - a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2]; - a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3]; - a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2]; - a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3]; - a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2]; - a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3]; - a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2]; - a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3]; - a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2]; - a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3]; -end -always @(*) begin - a7ddrphy_dfi_p2_rddata <= 32'd0; - a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4]; - a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5]; - a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4]; - a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5]; - a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4]; - a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5]; - a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4]; - a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5]; - a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4]; - a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5]; - a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4]; - a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5]; - a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4]; - a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5]; - a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4]; - a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5]; - a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4]; - a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5]; - a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4]; - a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5]; - a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4]; - a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5]; - a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4]; - a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5]; - a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4]; - a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5]; - a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4]; - a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5]; - a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4]; - a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5]; - a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4]; - a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5]; -end -always @(*) begin - a7ddrphy_dfi_p3_rddata <= 32'd0; - a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6]; - a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7]; - a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6]; - a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7]; - a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6]; - a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7]; - a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6]; - a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7]; - a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6]; - a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7]; - a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6]; - a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7]; - a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6]; - a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7]; - a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6]; - a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7]; - a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6]; - a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7]; - a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6]; - a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7]; - a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6]; - a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7]; - a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6]; - a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7]; - a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6]; - a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7]; - a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6]; - a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7]; - a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6]; - a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7]; - a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6]; - a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7]; -end -assign a7ddrphy_dfi_p0_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); -assign a7ddrphy_dfi_p1_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); -assign a7ddrphy_dfi_p2_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); -assign a7ddrphy_dfi_p3_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); -assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en_tappeddelayline1; -always @(*) begin - a7ddrphy_dqs_oe <= 1'd0; - if (a7ddrphy_wlevel_en_storage) begin - a7ddrphy_dqs_oe <= 1'd1; - end else begin - a7ddrphy_dqs_oe <= a7ddrphy_dq_oe; - end -end -assign a7ddrphy_dqs_preamble = (a7ddrphy_wrdata_en_tappeddelayline0 & (~a7ddrphy_wrdata_en_tappeddelayline1)); -assign a7ddrphy_dqs_postamble = (a7ddrphy_wrdata_en_tappeddelayline2 & (~a7ddrphy_wrdata_en_tappeddelayline1)); -always @(*) begin - a7ddrphy_dqspattern_o0 <= 8'd0; - a7ddrphy_dqspattern_o0 <= 7'd85; - if (a7ddrphy_dqspattern0) begin - a7ddrphy_dqspattern_o0 <= 5'd21; - end - if (a7ddrphy_dqspattern1) begin - a7ddrphy_dqspattern_o0 <= 7'd84; - end - if (a7ddrphy_wlevel_en_storage) begin - a7ddrphy_dqspattern_o0 <= 1'd0; - if (a7ddrphy_wlevel_strobe_re) begin - a7ddrphy_dqspattern_o0 <= 1'd1; - end - end -end -always @(*) begin - a7ddrphy_bitslip00 <= 8'd0; - case (a7ddrphy_bitslip0_value0) +assign main_user_enable = 1'd1; +assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable); +assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable); +assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we; +assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr; +assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable); +assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable); +assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we; +assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data; +assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable); +assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable); +assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data; +assign builder_interface0_adr = main_wb_bus_adr; +assign builder_interface0_dat_w = main_wb_bus_dat_w; +assign main_wb_bus_dat_r = builder_interface0_dat_r; +assign builder_interface0_sel = main_wb_bus_sel; +assign builder_interface0_cyc = main_wb_bus_cyc; +assign builder_interface0_stb = main_wb_bus_stb; +assign main_wb_bus_ack = builder_interface0_ack; +assign builder_interface0_we = main_wb_bus_we; +assign builder_interface0_cti = main_wb_bus_cti; +assign builder_interface0_bte = main_wb_bus_bte; +assign main_wb_bus_err = builder_interface0_err; +assign main_reset = (rst | main_rst); +assign pll_locked = main_locked; +assign main_clkin = clk; +assign iodelay_clk = main_clkout_buf0; +assign sys_clk = main_clkout_buf1; +assign sys4x_clk = main_clkout_buf2; +assign sys4x_dqs_clk = main_clkout_buf3; +assign ddram_ba = main_a7ddrphy_pads_ba; +assign main_a7ddrphy_dqs_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_oe) | main_a7ddrphy_dqs_postamble); +assign main_a7ddrphy_dq_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dq_oe) | main_a7ddrphy_dqs_postamble); +always @(*) begin + main_a7ddrphy_dfi_p0_rddata <= 32'd0; + main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip04[0]; + main_a7ddrphy_dfi_p0_rddata[16] <= main_a7ddrphy_bitslip04[1]; + main_a7ddrphy_dfi_p0_rddata[1] <= main_a7ddrphy_bitslip14[0]; + main_a7ddrphy_dfi_p0_rddata[17] <= main_a7ddrphy_bitslip14[1]; + main_a7ddrphy_dfi_p0_rddata[2] <= main_a7ddrphy_bitslip22[0]; + main_a7ddrphy_dfi_p0_rddata[18] <= main_a7ddrphy_bitslip22[1]; + main_a7ddrphy_dfi_p0_rddata[3] <= main_a7ddrphy_bitslip32[0]; + main_a7ddrphy_dfi_p0_rddata[19] <= main_a7ddrphy_bitslip32[1]; + main_a7ddrphy_dfi_p0_rddata[4] <= main_a7ddrphy_bitslip42[0]; + main_a7ddrphy_dfi_p0_rddata[20] <= main_a7ddrphy_bitslip42[1]; + main_a7ddrphy_dfi_p0_rddata[5] <= main_a7ddrphy_bitslip52[0]; + main_a7ddrphy_dfi_p0_rddata[21] <= main_a7ddrphy_bitslip52[1]; + main_a7ddrphy_dfi_p0_rddata[6] <= main_a7ddrphy_bitslip62[0]; + main_a7ddrphy_dfi_p0_rddata[22] <= main_a7ddrphy_bitslip62[1]; + main_a7ddrphy_dfi_p0_rddata[7] <= main_a7ddrphy_bitslip72[0]; + main_a7ddrphy_dfi_p0_rddata[23] <= main_a7ddrphy_bitslip72[1]; + main_a7ddrphy_dfi_p0_rddata[8] <= main_a7ddrphy_bitslip82[0]; + main_a7ddrphy_dfi_p0_rddata[24] <= main_a7ddrphy_bitslip82[1]; + main_a7ddrphy_dfi_p0_rddata[9] <= main_a7ddrphy_bitslip92[0]; + main_a7ddrphy_dfi_p0_rddata[25] <= main_a7ddrphy_bitslip92[1]; + main_a7ddrphy_dfi_p0_rddata[10] <= main_a7ddrphy_bitslip102[0]; + main_a7ddrphy_dfi_p0_rddata[26] <= main_a7ddrphy_bitslip102[1]; + main_a7ddrphy_dfi_p0_rddata[11] <= main_a7ddrphy_bitslip112[0]; + main_a7ddrphy_dfi_p0_rddata[27] <= main_a7ddrphy_bitslip112[1]; + main_a7ddrphy_dfi_p0_rddata[12] <= main_a7ddrphy_bitslip122[0]; + main_a7ddrphy_dfi_p0_rddata[28] <= main_a7ddrphy_bitslip122[1]; + main_a7ddrphy_dfi_p0_rddata[13] <= main_a7ddrphy_bitslip132[0]; + main_a7ddrphy_dfi_p0_rddata[29] <= main_a7ddrphy_bitslip132[1]; + main_a7ddrphy_dfi_p0_rddata[14] <= main_a7ddrphy_bitslip142[0]; + main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip142[1]; + main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip152[0]; + main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip152[1]; +end +always @(*) begin + main_a7ddrphy_dfi_p1_rddata <= 32'd0; + main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip04[2]; + main_a7ddrphy_dfi_p1_rddata[16] <= main_a7ddrphy_bitslip04[3]; + main_a7ddrphy_dfi_p1_rddata[1] <= main_a7ddrphy_bitslip14[2]; + main_a7ddrphy_dfi_p1_rddata[17] <= main_a7ddrphy_bitslip14[3]; + main_a7ddrphy_dfi_p1_rddata[2] <= main_a7ddrphy_bitslip22[2]; + main_a7ddrphy_dfi_p1_rddata[18] <= main_a7ddrphy_bitslip22[3]; + main_a7ddrphy_dfi_p1_rddata[3] <= main_a7ddrphy_bitslip32[2]; + main_a7ddrphy_dfi_p1_rddata[19] <= main_a7ddrphy_bitslip32[3]; + main_a7ddrphy_dfi_p1_rddata[4] <= main_a7ddrphy_bitslip42[2]; + main_a7ddrphy_dfi_p1_rddata[20] <= main_a7ddrphy_bitslip42[3]; + main_a7ddrphy_dfi_p1_rddata[5] <= main_a7ddrphy_bitslip52[2]; + main_a7ddrphy_dfi_p1_rddata[21] <= main_a7ddrphy_bitslip52[3]; + main_a7ddrphy_dfi_p1_rddata[6] <= main_a7ddrphy_bitslip62[2]; + main_a7ddrphy_dfi_p1_rddata[22] <= main_a7ddrphy_bitslip62[3]; + main_a7ddrphy_dfi_p1_rddata[7] <= main_a7ddrphy_bitslip72[2]; + main_a7ddrphy_dfi_p1_rddata[23] <= main_a7ddrphy_bitslip72[3]; + main_a7ddrphy_dfi_p1_rddata[8] <= main_a7ddrphy_bitslip82[2]; + main_a7ddrphy_dfi_p1_rddata[24] <= main_a7ddrphy_bitslip82[3]; + main_a7ddrphy_dfi_p1_rddata[9] <= main_a7ddrphy_bitslip92[2]; + main_a7ddrphy_dfi_p1_rddata[25] <= main_a7ddrphy_bitslip92[3]; + main_a7ddrphy_dfi_p1_rddata[10] <= main_a7ddrphy_bitslip102[2]; + main_a7ddrphy_dfi_p1_rddata[26] <= main_a7ddrphy_bitslip102[3]; + main_a7ddrphy_dfi_p1_rddata[11] <= main_a7ddrphy_bitslip112[2]; + main_a7ddrphy_dfi_p1_rddata[27] <= main_a7ddrphy_bitslip112[3]; + main_a7ddrphy_dfi_p1_rddata[12] <= main_a7ddrphy_bitslip122[2]; + main_a7ddrphy_dfi_p1_rddata[28] <= main_a7ddrphy_bitslip122[3]; + main_a7ddrphy_dfi_p1_rddata[13] <= main_a7ddrphy_bitslip132[2]; + main_a7ddrphy_dfi_p1_rddata[29] <= main_a7ddrphy_bitslip132[3]; + main_a7ddrphy_dfi_p1_rddata[14] <= main_a7ddrphy_bitslip142[2]; + main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip142[3]; + main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip152[2]; + main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip152[3]; +end +always @(*) begin + main_a7ddrphy_dfi_p2_rddata <= 32'd0; + main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip04[4]; + main_a7ddrphy_dfi_p2_rddata[16] <= main_a7ddrphy_bitslip04[5]; + main_a7ddrphy_dfi_p2_rddata[1] <= main_a7ddrphy_bitslip14[4]; + main_a7ddrphy_dfi_p2_rddata[17] <= main_a7ddrphy_bitslip14[5]; + main_a7ddrphy_dfi_p2_rddata[2] <= main_a7ddrphy_bitslip22[4]; + main_a7ddrphy_dfi_p2_rddata[18] <= main_a7ddrphy_bitslip22[5]; + main_a7ddrphy_dfi_p2_rddata[3] <= main_a7ddrphy_bitslip32[4]; + main_a7ddrphy_dfi_p2_rddata[19] <= main_a7ddrphy_bitslip32[5]; + main_a7ddrphy_dfi_p2_rddata[4] <= main_a7ddrphy_bitslip42[4]; + main_a7ddrphy_dfi_p2_rddata[20] <= main_a7ddrphy_bitslip42[5]; + main_a7ddrphy_dfi_p2_rddata[5] <= main_a7ddrphy_bitslip52[4]; + main_a7ddrphy_dfi_p2_rddata[21] <= main_a7ddrphy_bitslip52[5]; + main_a7ddrphy_dfi_p2_rddata[6] <= main_a7ddrphy_bitslip62[4]; + main_a7ddrphy_dfi_p2_rddata[22] <= main_a7ddrphy_bitslip62[5]; + main_a7ddrphy_dfi_p2_rddata[7] <= main_a7ddrphy_bitslip72[4]; + main_a7ddrphy_dfi_p2_rddata[23] <= main_a7ddrphy_bitslip72[5]; + main_a7ddrphy_dfi_p2_rddata[8] <= main_a7ddrphy_bitslip82[4]; + main_a7ddrphy_dfi_p2_rddata[24] <= main_a7ddrphy_bitslip82[5]; + main_a7ddrphy_dfi_p2_rddata[9] <= main_a7ddrphy_bitslip92[4]; + main_a7ddrphy_dfi_p2_rddata[25] <= main_a7ddrphy_bitslip92[5]; + main_a7ddrphy_dfi_p2_rddata[10] <= main_a7ddrphy_bitslip102[4]; + main_a7ddrphy_dfi_p2_rddata[26] <= main_a7ddrphy_bitslip102[5]; + main_a7ddrphy_dfi_p2_rddata[11] <= main_a7ddrphy_bitslip112[4]; + main_a7ddrphy_dfi_p2_rddata[27] <= main_a7ddrphy_bitslip112[5]; + main_a7ddrphy_dfi_p2_rddata[12] <= main_a7ddrphy_bitslip122[4]; + main_a7ddrphy_dfi_p2_rddata[28] <= main_a7ddrphy_bitslip122[5]; + main_a7ddrphy_dfi_p2_rddata[13] <= main_a7ddrphy_bitslip132[4]; + main_a7ddrphy_dfi_p2_rddata[29] <= main_a7ddrphy_bitslip132[5]; + main_a7ddrphy_dfi_p2_rddata[14] <= main_a7ddrphy_bitslip142[4]; + main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip142[5]; + main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip152[4]; + main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip152[5]; +end +always @(*) begin + main_a7ddrphy_dfi_p3_rddata <= 32'd0; + main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip04[6]; + main_a7ddrphy_dfi_p3_rddata[16] <= main_a7ddrphy_bitslip04[7]; + main_a7ddrphy_dfi_p3_rddata[1] <= main_a7ddrphy_bitslip14[6]; + main_a7ddrphy_dfi_p3_rddata[17] <= main_a7ddrphy_bitslip14[7]; + main_a7ddrphy_dfi_p3_rddata[2] <= main_a7ddrphy_bitslip22[6]; + main_a7ddrphy_dfi_p3_rddata[18] <= main_a7ddrphy_bitslip22[7]; + main_a7ddrphy_dfi_p3_rddata[3] <= main_a7ddrphy_bitslip32[6]; + main_a7ddrphy_dfi_p3_rddata[19] <= main_a7ddrphy_bitslip32[7]; + main_a7ddrphy_dfi_p3_rddata[4] <= main_a7ddrphy_bitslip42[6]; + main_a7ddrphy_dfi_p3_rddata[20] <= main_a7ddrphy_bitslip42[7]; + main_a7ddrphy_dfi_p3_rddata[5] <= main_a7ddrphy_bitslip52[6]; + main_a7ddrphy_dfi_p3_rddata[21] <= main_a7ddrphy_bitslip52[7]; + main_a7ddrphy_dfi_p3_rddata[6] <= main_a7ddrphy_bitslip62[6]; + main_a7ddrphy_dfi_p3_rddata[22] <= main_a7ddrphy_bitslip62[7]; + main_a7ddrphy_dfi_p3_rddata[7] <= main_a7ddrphy_bitslip72[6]; + main_a7ddrphy_dfi_p3_rddata[23] <= main_a7ddrphy_bitslip72[7]; + main_a7ddrphy_dfi_p3_rddata[8] <= main_a7ddrphy_bitslip82[6]; + main_a7ddrphy_dfi_p3_rddata[24] <= main_a7ddrphy_bitslip82[7]; + main_a7ddrphy_dfi_p3_rddata[9] <= main_a7ddrphy_bitslip92[6]; + main_a7ddrphy_dfi_p3_rddata[25] <= main_a7ddrphy_bitslip92[7]; + main_a7ddrphy_dfi_p3_rddata[10] <= main_a7ddrphy_bitslip102[6]; + main_a7ddrphy_dfi_p3_rddata[26] <= main_a7ddrphy_bitslip102[7]; + main_a7ddrphy_dfi_p3_rddata[11] <= main_a7ddrphy_bitslip112[6]; + main_a7ddrphy_dfi_p3_rddata[27] <= main_a7ddrphy_bitslip112[7]; + main_a7ddrphy_dfi_p3_rddata[12] <= main_a7ddrphy_bitslip122[6]; + main_a7ddrphy_dfi_p3_rddata[28] <= main_a7ddrphy_bitslip122[7]; + main_a7ddrphy_dfi_p3_rddata[13] <= main_a7ddrphy_bitslip132[6]; + main_a7ddrphy_dfi_p3_rddata[29] <= main_a7ddrphy_bitslip132[7]; + main_a7ddrphy_dfi_p3_rddata[14] <= main_a7ddrphy_bitslip142[6]; + main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip142[7]; + main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip152[6]; + main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip152[7]; +end +assign main_a7ddrphy_dfi_p0_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dfi_p1_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dfi_p2_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dfi_p3_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dq_oe = main_a7ddrphy_wrdata_en_tappeddelayline1; +always @(*) begin + main_a7ddrphy_dqs_oe <= 1'd0; + if (main_a7ddrphy_wlevel_en_storage) begin + main_a7ddrphy_dqs_oe <= 1'd1; + end else begin + main_a7ddrphy_dqs_oe <= main_a7ddrphy_dq_oe; + end +end +assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_wrdata_en_tappeddelayline0 & (~main_a7ddrphy_wrdata_en_tappeddelayline1)); +assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_wrdata_en_tappeddelayline2 & (~main_a7ddrphy_wrdata_en_tappeddelayline1)); +always @(*) begin + main_a7ddrphy_dqspattern_o0 <= 8'd0; + main_a7ddrphy_dqspattern_o0 <= 7'd85; + if (main_a7ddrphy_dqspattern0) begin + main_a7ddrphy_dqspattern_o0 <= 5'd21; + end + if (main_a7ddrphy_dqspattern1) begin + main_a7ddrphy_dqspattern_o0 <= 7'd84; + end + if (main_a7ddrphy_wlevel_en_storage) begin + main_a7ddrphy_dqspattern_o0 <= 1'd0; + if (main_a7ddrphy_wlevel_strobe_re) begin + main_a7ddrphy_dqspattern_o0 <= 1'd1; + end + end +end +always @(*) begin + main_a7ddrphy_bitslip00 <= 8'd0; + case (main_a7ddrphy_bitslip0_value0) 1'd0: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip10 <= 8'd0; - case (a7ddrphy_bitslip1_value0) + main_a7ddrphy_bitslip10 <= 8'd0; + case (main_a7ddrphy_bitslip1_value0) 1'd0: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip01 <= 8'd0; - case (a7ddrphy_bitslip0_value1) + main_a7ddrphy_bitslip01 <= 8'd0; + case (main_a7ddrphy_bitslip0_value1) 1'd0: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip11 <= 8'd0; - case (a7ddrphy_bitslip1_value1) + main_a7ddrphy_bitslip11 <= 8'd0; + case (main_a7ddrphy_bitslip1_value1) 1'd0: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip02 <= 8'd0; - case (a7ddrphy_bitslip0_value2) + main_a7ddrphy_bitslip02 <= 8'd0; + case (main_a7ddrphy_bitslip0_value2) 1'd0: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[8:1]; end 1'd1: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[9:2]; end 2'd2: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[10:3]; end 2'd3: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[11:4]; end 3'd4: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[12:5]; end 3'd5: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[13:6]; end 3'd6: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[14:7]; end 3'd7: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip04 <= 8'd0; - case (a7ddrphy_bitslip0_value3) + main_a7ddrphy_bitslip04 <= 8'd0; + case (main_a7ddrphy_bitslip0_value3) 1'd0: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[8:1]; end 1'd1: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[9:2]; end 2'd2: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[10:3]; end 2'd3: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[11:4]; end 3'd4: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[12:5]; end 3'd5: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[13:6]; end 3'd6: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[14:7]; end 3'd7: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip12 <= 8'd0; - case (a7ddrphy_bitslip1_value2) + main_a7ddrphy_bitslip12 <= 8'd0; + case (main_a7ddrphy_bitslip1_value2) 1'd0: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[8:1]; end 1'd1: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[9:2]; end 2'd2: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[10:3]; end 2'd3: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[11:4]; end 3'd4: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[12:5]; end 3'd5: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[13:6]; end 3'd6: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[14:7]; end 3'd7: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip14 <= 8'd0; - case (a7ddrphy_bitslip1_value3) + main_a7ddrphy_bitslip14 <= 8'd0; + case (main_a7ddrphy_bitslip1_value3) 1'd0: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[8:1]; end 1'd1: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[9:2]; end 2'd2: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[10:3]; end 2'd3: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[11:4]; end 3'd4: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[12:5]; end 3'd5: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[13:6]; end 3'd6: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[14:7]; end 3'd7: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip20 <= 8'd0; - case (a7ddrphy_bitslip2_value0) + main_a7ddrphy_bitslip20 <= 8'd0; + case (main_a7ddrphy_bitslip2_value0) 1'd0: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip22 <= 8'd0; - case (a7ddrphy_bitslip2_value1) + main_a7ddrphy_bitslip22 <= 8'd0; + case (main_a7ddrphy_bitslip2_value1) 1'd0: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip30 <= 8'd0; - case (a7ddrphy_bitslip3_value0) + main_a7ddrphy_bitslip30 <= 8'd0; + case (main_a7ddrphy_bitslip3_value0) 1'd0: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip32 <= 8'd0; - case (a7ddrphy_bitslip3_value1) + main_a7ddrphy_bitslip32 <= 8'd0; + case (main_a7ddrphy_bitslip3_value1) 1'd0: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip40 <= 8'd0; - case (a7ddrphy_bitslip4_value0) + main_a7ddrphy_bitslip40 <= 8'd0; + case (main_a7ddrphy_bitslip4_value0) 1'd0: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip42 <= 8'd0; - case (a7ddrphy_bitslip4_value1) + main_a7ddrphy_bitslip42 <= 8'd0; + case (main_a7ddrphy_bitslip4_value1) 1'd0: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip50 <= 8'd0; - case (a7ddrphy_bitslip5_value0) + main_a7ddrphy_bitslip50 <= 8'd0; + case (main_a7ddrphy_bitslip5_value0) 1'd0: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip52 <= 8'd0; - case (a7ddrphy_bitslip5_value1) + main_a7ddrphy_bitslip52 <= 8'd0; + case (main_a7ddrphy_bitslip5_value1) 1'd0: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip60 <= 8'd0; - case (a7ddrphy_bitslip6_value0) + main_a7ddrphy_bitslip60 <= 8'd0; + case (main_a7ddrphy_bitslip6_value0) 1'd0: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip62 <= 8'd0; - case (a7ddrphy_bitslip6_value1) + main_a7ddrphy_bitslip62 <= 8'd0; + case (main_a7ddrphy_bitslip6_value1) 1'd0: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip70 <= 8'd0; - case (a7ddrphy_bitslip7_value0) + main_a7ddrphy_bitslip70 <= 8'd0; + case (main_a7ddrphy_bitslip7_value0) 1'd0: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip72 <= 8'd0; - case (a7ddrphy_bitslip7_value1) + main_a7ddrphy_bitslip72 <= 8'd0; + case (main_a7ddrphy_bitslip7_value1) 1'd0: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip80 <= 8'd0; - case (a7ddrphy_bitslip8_value0) + main_a7ddrphy_bitslip80 <= 8'd0; + case (main_a7ddrphy_bitslip8_value0) 1'd0: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip82 <= 8'd0; - case (a7ddrphy_bitslip8_value1) + main_a7ddrphy_bitslip82 <= 8'd0; + case (main_a7ddrphy_bitslip8_value1) 1'd0: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip90 <= 8'd0; - case (a7ddrphy_bitslip9_value0) + main_a7ddrphy_bitslip90 <= 8'd0; + case (main_a7ddrphy_bitslip9_value0) 1'd0: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip92 <= 8'd0; - case (a7ddrphy_bitslip9_value1) + main_a7ddrphy_bitslip92 <= 8'd0; + case (main_a7ddrphy_bitslip9_value1) 1'd0: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip100 <= 8'd0; - case (a7ddrphy_bitslip10_value0) + main_a7ddrphy_bitslip100 <= 8'd0; + case (main_a7ddrphy_bitslip10_value0) 1'd0: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip102 <= 8'd0; - case (a7ddrphy_bitslip10_value1) + main_a7ddrphy_bitslip102 <= 8'd0; + case (main_a7ddrphy_bitslip10_value1) 1'd0: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip110 <= 8'd0; - case (a7ddrphy_bitslip11_value0) + main_a7ddrphy_bitslip110 <= 8'd0; + case (main_a7ddrphy_bitslip11_value0) 1'd0: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip112 <= 8'd0; - case (a7ddrphy_bitslip11_value1) + main_a7ddrphy_bitslip112 <= 8'd0; + case (main_a7ddrphy_bitslip11_value1) 1'd0: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip120 <= 8'd0; - case (a7ddrphy_bitslip12_value0) + main_a7ddrphy_bitslip120 <= 8'd0; + case (main_a7ddrphy_bitslip12_value0) 1'd0: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip122 <= 8'd0; - case (a7ddrphy_bitslip12_value1) + main_a7ddrphy_bitslip122 <= 8'd0; + case (main_a7ddrphy_bitslip12_value1) 1'd0: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip130 <= 8'd0; - case (a7ddrphy_bitslip13_value0) + main_a7ddrphy_bitslip130 <= 8'd0; + case (main_a7ddrphy_bitslip13_value0) 1'd0: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip132 <= 8'd0; - case (a7ddrphy_bitslip13_value1) + main_a7ddrphy_bitslip132 <= 8'd0; + case (main_a7ddrphy_bitslip13_value1) 1'd0: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip140 <= 8'd0; - case (a7ddrphy_bitslip14_value0) + main_a7ddrphy_bitslip140 <= 8'd0; + case (main_a7ddrphy_bitslip14_value0) 1'd0: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip142 <= 8'd0; - case (a7ddrphy_bitslip14_value1) + main_a7ddrphy_bitslip142 <= 8'd0; + case (main_a7ddrphy_bitslip14_value1) 1'd0: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip150 <= 8'd0; - case (a7ddrphy_bitslip15_value0) + main_a7ddrphy_bitslip150 <= 8'd0; + case (main_a7ddrphy_bitslip15_value0) 1'd0: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip152 <= 8'd0; - case (a7ddrphy_bitslip15_value1) + main_a7ddrphy_bitslip152 <= 8'd0; + case (main_a7ddrphy_bitslip15_value1) 1'd0: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8]; - end - endcase -end -assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address; -assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank; -assign a7ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n; -assign a7ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n; -assign a7ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n; -assign a7ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n; -assign a7ddrphy_dfi_p0_cke = litedramcore_master_p0_cke; -assign a7ddrphy_dfi_p0_odt = litedramcore_master_p0_odt; -assign a7ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n; -assign a7ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n; -assign a7ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata; -assign a7ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en; -assign a7ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask; -assign a7ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en; -assign litedramcore_master_p0_rddata = a7ddrphy_dfi_p0_rddata; -assign litedramcore_master_p0_rddata_valid = a7ddrphy_dfi_p0_rddata_valid; -assign a7ddrphy_dfi_p1_address = litedramcore_master_p1_address; -assign a7ddrphy_dfi_p1_bank = litedramcore_master_p1_bank; -assign a7ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n; -assign a7ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n; -assign a7ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n; -assign a7ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n; -assign a7ddrphy_dfi_p1_cke = litedramcore_master_p1_cke; -assign a7ddrphy_dfi_p1_odt = litedramcore_master_p1_odt; -assign a7ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n; -assign a7ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n; -assign a7ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata; -assign a7ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en; -assign a7ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask; -assign a7ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en; -assign litedramcore_master_p1_rddata = a7ddrphy_dfi_p1_rddata; -assign litedramcore_master_p1_rddata_valid = a7ddrphy_dfi_p1_rddata_valid; -assign a7ddrphy_dfi_p2_address = litedramcore_master_p2_address; -assign a7ddrphy_dfi_p2_bank = litedramcore_master_p2_bank; -assign a7ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n; -assign a7ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n; -assign a7ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n; -assign a7ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n; -assign a7ddrphy_dfi_p2_cke = litedramcore_master_p2_cke; -assign a7ddrphy_dfi_p2_odt = litedramcore_master_p2_odt; -assign a7ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n; -assign a7ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n; -assign a7ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata; -assign a7ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en; -assign a7ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask; -assign a7ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en; -assign litedramcore_master_p2_rddata = a7ddrphy_dfi_p2_rddata; -assign litedramcore_master_p2_rddata_valid = a7ddrphy_dfi_p2_rddata_valid; -assign a7ddrphy_dfi_p3_address = litedramcore_master_p3_address; -assign a7ddrphy_dfi_p3_bank = litedramcore_master_p3_bank; -assign a7ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n; -assign a7ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n; -assign a7ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n; -assign a7ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n; -assign a7ddrphy_dfi_p3_cke = litedramcore_master_p3_cke; -assign a7ddrphy_dfi_p3_odt = litedramcore_master_p3_odt; -assign a7ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n; -assign a7ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n; -assign a7ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata; -assign a7ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en; -assign a7ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask; -assign a7ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en; -assign litedramcore_master_p3_rddata = a7ddrphy_dfi_p3_rddata; -assign litedramcore_master_p3_rddata_valid = a7ddrphy_dfi_p3_rddata_valid; -assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address; -assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank; -assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n; -assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n; -assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n; -assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n; -assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke; -assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt; -assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n; -assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n; -assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata; -assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en; -assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask; -assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en; -assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata; -assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid; -assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address; -assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank; -assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n; -assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n; -assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n; -assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n; -assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke; -assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt; -assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n; -assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n; -assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata; -assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en; -assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask; -assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en; -assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata; -assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid; -assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address; -assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank; -assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n; -assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n; -assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n; -assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n; -assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke; -assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt; -assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n; -assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n; -assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata; -assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en; -assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask; -assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en; -assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata; -assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid; -assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address; -assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank; -assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n; -assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n; -assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n; -assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n; -assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke; -assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt; -assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n; -assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n; -assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata; -assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en; -assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask; -assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en; -assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata; -assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; -always @(*) begin - litedramcore_csr_dfi_p0_rddata <= 32'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata; - end -end -always @(*) begin - litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; - end -end -always @(*) begin - litedramcore_csr_dfi_p1_rddata <= 32'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata; - end -end -always @(*) begin - litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[15:8]; + end + endcase +end +assign main_a7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address; +assign main_a7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank; +assign main_a7ddrphy_dfi_p0_cas_n = main_litedramcore_master_p0_cas_n; +assign main_a7ddrphy_dfi_p0_cs_n = main_litedramcore_master_p0_cs_n; +assign main_a7ddrphy_dfi_p0_ras_n = main_litedramcore_master_p0_ras_n; +assign main_a7ddrphy_dfi_p0_we_n = main_litedramcore_master_p0_we_n; +assign main_a7ddrphy_dfi_p0_cke = main_litedramcore_master_p0_cke; +assign main_a7ddrphy_dfi_p0_odt = main_litedramcore_master_p0_odt; +assign main_a7ddrphy_dfi_p0_reset_n = main_litedramcore_master_p0_reset_n; +assign main_a7ddrphy_dfi_p0_act_n = main_litedramcore_master_p0_act_n; +assign main_a7ddrphy_dfi_p0_wrdata = main_litedramcore_master_p0_wrdata; +assign main_a7ddrphy_dfi_p0_wrdata_en = main_litedramcore_master_p0_wrdata_en; +assign main_a7ddrphy_dfi_p0_wrdata_mask = main_litedramcore_master_p0_wrdata_mask; +assign main_a7ddrphy_dfi_p0_rddata_en = main_litedramcore_master_p0_rddata_en; +assign main_litedramcore_master_p0_rddata = main_a7ddrphy_dfi_p0_rddata; +assign main_litedramcore_master_p0_rddata_valid = main_a7ddrphy_dfi_p0_rddata_valid; +assign main_a7ddrphy_dfi_p1_address = main_litedramcore_master_p1_address; +assign main_a7ddrphy_dfi_p1_bank = main_litedramcore_master_p1_bank; +assign main_a7ddrphy_dfi_p1_cas_n = main_litedramcore_master_p1_cas_n; +assign main_a7ddrphy_dfi_p1_cs_n = main_litedramcore_master_p1_cs_n; +assign main_a7ddrphy_dfi_p1_ras_n = main_litedramcore_master_p1_ras_n; +assign main_a7ddrphy_dfi_p1_we_n = main_litedramcore_master_p1_we_n; +assign main_a7ddrphy_dfi_p1_cke = main_litedramcore_master_p1_cke; +assign main_a7ddrphy_dfi_p1_odt = main_litedramcore_master_p1_odt; +assign main_a7ddrphy_dfi_p1_reset_n = main_litedramcore_master_p1_reset_n; +assign main_a7ddrphy_dfi_p1_act_n = main_litedramcore_master_p1_act_n; +assign main_a7ddrphy_dfi_p1_wrdata = main_litedramcore_master_p1_wrdata; +assign main_a7ddrphy_dfi_p1_wrdata_en = main_litedramcore_master_p1_wrdata_en; +assign main_a7ddrphy_dfi_p1_wrdata_mask = main_litedramcore_master_p1_wrdata_mask; +assign main_a7ddrphy_dfi_p1_rddata_en = main_litedramcore_master_p1_rddata_en; +assign main_litedramcore_master_p1_rddata = main_a7ddrphy_dfi_p1_rddata; +assign main_litedramcore_master_p1_rddata_valid = main_a7ddrphy_dfi_p1_rddata_valid; +assign main_a7ddrphy_dfi_p2_address = main_litedramcore_master_p2_address; +assign main_a7ddrphy_dfi_p2_bank = main_litedramcore_master_p2_bank; +assign main_a7ddrphy_dfi_p2_cas_n = main_litedramcore_master_p2_cas_n; +assign main_a7ddrphy_dfi_p2_cs_n = main_litedramcore_master_p2_cs_n; +assign main_a7ddrphy_dfi_p2_ras_n = main_litedramcore_master_p2_ras_n; +assign main_a7ddrphy_dfi_p2_we_n = main_litedramcore_master_p2_we_n; +assign main_a7ddrphy_dfi_p2_cke = main_litedramcore_master_p2_cke; +assign main_a7ddrphy_dfi_p2_odt = main_litedramcore_master_p2_odt; +assign main_a7ddrphy_dfi_p2_reset_n = main_litedramcore_master_p2_reset_n; +assign main_a7ddrphy_dfi_p2_act_n = main_litedramcore_master_p2_act_n; +assign main_a7ddrphy_dfi_p2_wrdata = main_litedramcore_master_p2_wrdata; +assign main_a7ddrphy_dfi_p2_wrdata_en = main_litedramcore_master_p2_wrdata_en; +assign main_a7ddrphy_dfi_p2_wrdata_mask = main_litedramcore_master_p2_wrdata_mask; +assign main_a7ddrphy_dfi_p2_rddata_en = main_litedramcore_master_p2_rddata_en; +assign main_litedramcore_master_p2_rddata = main_a7ddrphy_dfi_p2_rddata; +assign main_litedramcore_master_p2_rddata_valid = main_a7ddrphy_dfi_p2_rddata_valid; +assign main_a7ddrphy_dfi_p3_address = main_litedramcore_master_p3_address; +assign main_a7ddrphy_dfi_p3_bank = main_litedramcore_master_p3_bank; +assign main_a7ddrphy_dfi_p3_cas_n = main_litedramcore_master_p3_cas_n; +assign main_a7ddrphy_dfi_p3_cs_n = main_litedramcore_master_p3_cs_n; +assign main_a7ddrphy_dfi_p3_ras_n = main_litedramcore_master_p3_ras_n; +assign main_a7ddrphy_dfi_p3_we_n = main_litedramcore_master_p3_we_n; +assign main_a7ddrphy_dfi_p3_cke = main_litedramcore_master_p3_cke; +assign main_a7ddrphy_dfi_p3_odt = main_litedramcore_master_p3_odt; +assign main_a7ddrphy_dfi_p3_reset_n = main_litedramcore_master_p3_reset_n; +assign main_a7ddrphy_dfi_p3_act_n = main_litedramcore_master_p3_act_n; +assign main_a7ddrphy_dfi_p3_wrdata = main_litedramcore_master_p3_wrdata; +assign main_a7ddrphy_dfi_p3_wrdata_en = main_litedramcore_master_p3_wrdata_en; +assign main_a7ddrphy_dfi_p3_wrdata_mask = main_litedramcore_master_p3_wrdata_mask; +assign main_a7ddrphy_dfi_p3_rddata_en = main_litedramcore_master_p3_rddata_en; +assign main_litedramcore_master_p3_rddata = main_a7ddrphy_dfi_p3_rddata; +assign main_litedramcore_master_p3_rddata_valid = main_a7ddrphy_dfi_p3_rddata_valid; +assign main_litedramcore_slave_p0_address = main_litedramcore_dfi_p0_address; +assign main_litedramcore_slave_p0_bank = main_litedramcore_dfi_p0_bank; +assign main_litedramcore_slave_p0_cas_n = main_litedramcore_dfi_p0_cas_n; +assign main_litedramcore_slave_p0_cs_n = main_litedramcore_dfi_p0_cs_n; +assign main_litedramcore_slave_p0_ras_n = main_litedramcore_dfi_p0_ras_n; +assign main_litedramcore_slave_p0_we_n = main_litedramcore_dfi_p0_we_n; +assign main_litedramcore_slave_p0_cke = main_litedramcore_dfi_p0_cke; +assign main_litedramcore_slave_p0_odt = main_litedramcore_dfi_p0_odt; +assign main_litedramcore_slave_p0_reset_n = main_litedramcore_dfi_p0_reset_n; +assign main_litedramcore_slave_p0_act_n = main_litedramcore_dfi_p0_act_n; +assign main_litedramcore_slave_p0_wrdata = main_litedramcore_dfi_p0_wrdata; +assign main_litedramcore_slave_p0_wrdata_en = main_litedramcore_dfi_p0_wrdata_en; +assign main_litedramcore_slave_p0_wrdata_mask = main_litedramcore_dfi_p0_wrdata_mask; +assign main_litedramcore_slave_p0_rddata_en = main_litedramcore_dfi_p0_rddata_en; +assign main_litedramcore_dfi_p0_rddata = main_litedramcore_slave_p0_rddata; +assign main_litedramcore_dfi_p0_rddata_valid = main_litedramcore_slave_p0_rddata_valid; +assign main_litedramcore_slave_p1_address = main_litedramcore_dfi_p1_address; +assign main_litedramcore_slave_p1_bank = main_litedramcore_dfi_p1_bank; +assign main_litedramcore_slave_p1_cas_n = main_litedramcore_dfi_p1_cas_n; +assign main_litedramcore_slave_p1_cs_n = main_litedramcore_dfi_p1_cs_n; +assign main_litedramcore_slave_p1_ras_n = main_litedramcore_dfi_p1_ras_n; +assign main_litedramcore_slave_p1_we_n = main_litedramcore_dfi_p1_we_n; +assign main_litedramcore_slave_p1_cke = main_litedramcore_dfi_p1_cke; +assign main_litedramcore_slave_p1_odt = main_litedramcore_dfi_p1_odt; +assign main_litedramcore_slave_p1_reset_n = main_litedramcore_dfi_p1_reset_n; +assign main_litedramcore_slave_p1_act_n = main_litedramcore_dfi_p1_act_n; +assign main_litedramcore_slave_p1_wrdata = main_litedramcore_dfi_p1_wrdata; +assign main_litedramcore_slave_p1_wrdata_en = main_litedramcore_dfi_p1_wrdata_en; +assign main_litedramcore_slave_p1_wrdata_mask = main_litedramcore_dfi_p1_wrdata_mask; +assign main_litedramcore_slave_p1_rddata_en = main_litedramcore_dfi_p1_rddata_en; +assign main_litedramcore_dfi_p1_rddata = main_litedramcore_slave_p1_rddata; +assign main_litedramcore_dfi_p1_rddata_valid = main_litedramcore_slave_p1_rddata_valid; +assign main_litedramcore_slave_p2_address = main_litedramcore_dfi_p2_address; +assign main_litedramcore_slave_p2_bank = main_litedramcore_dfi_p2_bank; +assign main_litedramcore_slave_p2_cas_n = main_litedramcore_dfi_p2_cas_n; +assign main_litedramcore_slave_p2_cs_n = main_litedramcore_dfi_p2_cs_n; +assign main_litedramcore_slave_p2_ras_n = main_litedramcore_dfi_p2_ras_n; +assign main_litedramcore_slave_p2_we_n = main_litedramcore_dfi_p2_we_n; +assign main_litedramcore_slave_p2_cke = main_litedramcore_dfi_p2_cke; +assign main_litedramcore_slave_p2_odt = main_litedramcore_dfi_p2_odt; +assign main_litedramcore_slave_p2_reset_n = main_litedramcore_dfi_p2_reset_n; +assign main_litedramcore_slave_p2_act_n = main_litedramcore_dfi_p2_act_n; +assign main_litedramcore_slave_p2_wrdata = main_litedramcore_dfi_p2_wrdata; +assign main_litedramcore_slave_p2_wrdata_en = main_litedramcore_dfi_p2_wrdata_en; +assign main_litedramcore_slave_p2_wrdata_mask = main_litedramcore_dfi_p2_wrdata_mask; +assign main_litedramcore_slave_p2_rddata_en = main_litedramcore_dfi_p2_rddata_en; +assign main_litedramcore_dfi_p2_rddata = main_litedramcore_slave_p2_rddata; +assign main_litedramcore_dfi_p2_rddata_valid = main_litedramcore_slave_p2_rddata_valid; +assign main_litedramcore_slave_p3_address = main_litedramcore_dfi_p3_address; +assign main_litedramcore_slave_p3_bank = main_litedramcore_dfi_p3_bank; +assign main_litedramcore_slave_p3_cas_n = main_litedramcore_dfi_p3_cas_n; +assign main_litedramcore_slave_p3_cs_n = main_litedramcore_dfi_p3_cs_n; +assign main_litedramcore_slave_p3_ras_n = main_litedramcore_dfi_p3_ras_n; +assign main_litedramcore_slave_p3_we_n = main_litedramcore_dfi_p3_we_n; +assign main_litedramcore_slave_p3_cke = main_litedramcore_dfi_p3_cke; +assign main_litedramcore_slave_p3_odt = main_litedramcore_dfi_p3_odt; +assign main_litedramcore_slave_p3_reset_n = main_litedramcore_dfi_p3_reset_n; +assign main_litedramcore_slave_p3_act_n = main_litedramcore_dfi_p3_act_n; +assign main_litedramcore_slave_p3_wrdata = main_litedramcore_dfi_p3_wrdata; +assign main_litedramcore_slave_p3_wrdata_en = main_litedramcore_dfi_p3_wrdata_en; +assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_mask; +assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en; +assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata; +assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid; +always @(*) begin + main_litedramcore_csr_dfi_p0_rddata <= 32'd0; + if (main_litedramcore_sel) begin + end else begin + main_litedramcore_csr_dfi_p0_rddata <= main_litedramcore_master_p0_rddata; end end always @(*) begin - litedramcore_csr_dfi_p2_rddata <= 32'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata; + main_litedramcore_csr_dfi_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end end always @(*) begin - litedramcore_csr_dfi_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p1_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + main_litedramcore_csr_dfi_p1_rddata <= main_litedramcore_master_p1_rddata; end end always @(*) begin - litedramcore_csr_dfi_p3_rddata <= 32'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata; + main_litedramcore_csr_dfi_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end end always @(*) begin - litedramcore_csr_dfi_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p2_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + main_litedramcore_csr_dfi_p2_rddata <= main_litedramcore_master_p2_rddata; end end always @(*) begin - litedramcore_ext_dfi_p0_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata; - end else begin - end + main_litedramcore_csr_dfi_p2_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + end else begin + main_litedramcore_csr_dfi_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; + end +end +always @(*) begin + main_litedramcore_csr_dfi_p3_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin + main_litedramcore_csr_dfi_p3_rddata <= main_litedramcore_master_p3_rddata; end end always @(*) begin - litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + main_litedramcore_csr_dfi_p3_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + end else begin + main_litedramcore_csr_dfi_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; + end +end +always @(*) begin + main_litedramcore_ext_dfi_p0_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p0_rddata <= main_litedramcore_master_p0_rddata; end else begin end end else begin end end always @(*) begin - litedramcore_ext_dfi_p1_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata; + main_litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end else begin end end else begin end end always @(*) begin - litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + main_litedramcore_ext_dfi_p1_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p1_rddata <= main_litedramcore_master_p1_rddata; end else begin end end else begin end end always @(*) begin - litedramcore_ext_dfi_p2_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata; + main_litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end else begin end end else begin end end always @(*) begin - litedramcore_ext_dfi_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + main_litedramcore_ext_dfi_p2_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p2_rddata <= main_litedramcore_master_p2_rddata; end else begin end end else begin end end always @(*) begin - litedramcore_slave_p0_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p2_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end else begin - litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; end end else begin end end always @(*) begin - litedramcore_slave_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p0_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata; end end else begin end end always @(*) begin - litedramcore_ext_dfi_p3_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata; + main_litedramcore_slave_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin + main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end end else begin end end always @(*) begin - litedramcore_ext_dfi_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + main_litedramcore_ext_dfi_p3_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p3_rddata <= main_litedramcore_master_p3_rddata; end else begin end end else begin end end always @(*) begin - litedramcore_slave_p1_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p3_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end else begin - litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; end end else begin end end always @(*) begin - litedramcore_slave_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p1_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata; end end else begin end end always @(*) begin - litedramcore_slave_p2_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p1_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; + main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end end else begin end end always @(*) begin - litedramcore_slave_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p2_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata; end end else begin end end always @(*) begin - litedramcore_slave_p3_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p2_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; + main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end end else begin end end always @(*) begin - litedramcore_slave_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p3_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata; end end else begin end end always @(*) begin - litedramcore_master_p0_address <= 14'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address; + main_litedramcore_slave_p3_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_master_p0_address <= litedramcore_slave_p0_address; + main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end end else begin - litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address; end end always @(*) begin - litedramcore_master_p0_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank; + main_litedramcore_master_p0_address <= 14'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_address <= main_litedramcore_ext_dfi_p0_address; end else begin - litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; + main_litedramcore_master_p0_address <= main_litedramcore_slave_p0_address; end end else begin - litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank; + main_litedramcore_master_p0_address <= main_litedramcore_csr_dfi_p0_address; end end always @(*) begin - litedramcore_master_p0_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n; + main_litedramcore_master_p0_bank <= 3'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_bank <= main_litedramcore_ext_dfi_p0_bank; end else begin - litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; + main_litedramcore_master_p0_bank <= main_litedramcore_slave_p0_bank; end end else begin - litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n; + main_litedramcore_master_p0_bank <= main_litedramcore_csr_dfi_p0_bank; end end always @(*) begin - litedramcore_master_p0_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n; + main_litedramcore_master_p0_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_cas_n <= main_litedramcore_ext_dfi_p0_cas_n; end else begin - litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; + main_litedramcore_master_p0_cas_n <= main_litedramcore_slave_p0_cas_n; end end else begin - litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n; + main_litedramcore_master_p0_cas_n <= main_litedramcore_csr_dfi_p0_cas_n; end end always @(*) begin - litedramcore_master_p0_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n; + main_litedramcore_master_p0_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_cs_n <= main_litedramcore_ext_dfi_p0_cs_n; end else begin - litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; + main_litedramcore_master_p0_cs_n <= main_litedramcore_slave_p0_cs_n; + if (1'd0) begin + main_litedramcore_master_p0_cs_n <= {2{main_litedramcore_slave_p0_cs_n}}; + end end end else begin - litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n; + main_litedramcore_master_p0_cs_n <= main_litedramcore_csr_dfi_p0_cs_n; end end always @(*) begin - litedramcore_master_p0_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n; + main_litedramcore_master_p0_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_ras_n <= main_litedramcore_ext_dfi_p0_ras_n; end else begin - litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + main_litedramcore_master_p0_ras_n <= main_litedramcore_slave_p0_ras_n; end end else begin - litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n; + main_litedramcore_master_p0_ras_n <= main_litedramcore_csr_dfi_p0_ras_n; end end always @(*) begin - litedramcore_master_p0_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke; + main_litedramcore_master_p0_we_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_we_n <= main_litedramcore_ext_dfi_p0_we_n; end else begin - litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; + main_litedramcore_master_p0_we_n <= main_litedramcore_slave_p0_we_n; end end else begin - litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke; + main_litedramcore_master_p0_we_n <= main_litedramcore_csr_dfi_p0_we_n; end end always @(*) begin - litedramcore_master_p0_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt; + main_litedramcore_master_p0_cke <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_cke <= main_litedramcore_ext_dfi_p0_cke; end else begin - litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; + main_litedramcore_master_p0_cke <= main_litedramcore_slave_p0_cke; end end else begin - litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt; + main_litedramcore_master_p0_cke <= main_litedramcore_csr_dfi_p0_cke; end end always @(*) begin - litedramcore_master_p0_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n; + main_litedramcore_master_p0_odt <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_odt <= main_litedramcore_ext_dfi_p0_odt; end else begin - litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; + main_litedramcore_master_p0_odt <= main_litedramcore_slave_p0_odt; end end else begin - litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n; + main_litedramcore_master_p0_odt <= main_litedramcore_csr_dfi_p0_odt; end end always @(*) begin - litedramcore_master_p0_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n; + main_litedramcore_master_p0_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_reset_n <= main_litedramcore_ext_dfi_p0_reset_n; end else begin - litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; + main_litedramcore_master_p0_reset_n <= main_litedramcore_slave_p0_reset_n; end end else begin - litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n; + main_litedramcore_master_p0_reset_n <= main_litedramcore_csr_dfi_p0_reset_n; end end always @(*) begin - litedramcore_master_p0_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata; + main_litedramcore_master_p0_act_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_act_n <= main_litedramcore_ext_dfi_p0_act_n; end else begin - litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; + main_litedramcore_master_p0_act_n <= main_litedramcore_slave_p0_act_n; end end else begin - litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata; + main_litedramcore_master_p0_act_n <= main_litedramcore_csr_dfi_p0_act_n; end end always @(*) begin - litedramcore_master_p0_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en; + main_litedramcore_master_p0_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_wrdata <= main_litedramcore_ext_dfi_p0_wrdata; end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; + main_litedramcore_master_p0_wrdata <= main_litedramcore_slave_p0_wrdata; end end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en; + main_litedramcore_master_p0_wrdata <= main_litedramcore_csr_dfi_p0_wrdata; end end always @(*) begin - litedramcore_master_p0_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask; + main_litedramcore_master_p0_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_wrdata_en <= main_litedramcore_ext_dfi_p0_wrdata_en; end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; + main_litedramcore_master_p0_wrdata_en <= main_litedramcore_slave_p0_wrdata_en; end end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask; + main_litedramcore_master_p0_wrdata_en <= main_litedramcore_csr_dfi_p0_wrdata_en; end end always @(*) begin - litedramcore_master_p0_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en; + main_litedramcore_master_p0_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_ext_dfi_p0_wrdata_mask; end else begin - litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_slave_p0_wrdata_mask; end end else begin - litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en; + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_csr_dfi_p0_wrdata_mask; end end always @(*) begin - litedramcore_master_p1_address <= 14'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address; + main_litedramcore_master_p0_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_rddata_en <= main_litedramcore_ext_dfi_p0_rddata_en; end else begin - litedramcore_master_p1_address <= litedramcore_slave_p1_address; + main_litedramcore_master_p0_rddata_en <= main_litedramcore_slave_p0_rddata_en; end end else begin - litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address; + main_litedramcore_master_p0_rddata_en <= main_litedramcore_csr_dfi_p0_rddata_en; end end always @(*) begin - litedramcore_master_p1_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank; + main_litedramcore_master_p1_address <= 14'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_address <= main_litedramcore_ext_dfi_p1_address; end else begin - litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; + main_litedramcore_master_p1_address <= main_litedramcore_slave_p1_address; end end else begin - litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank; + main_litedramcore_master_p1_address <= main_litedramcore_csr_dfi_p1_address; end end always @(*) begin - litedramcore_master_p1_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n; + main_litedramcore_master_p1_bank <= 3'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_bank <= main_litedramcore_ext_dfi_p1_bank; end else begin - litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; + main_litedramcore_master_p1_bank <= main_litedramcore_slave_p1_bank; end end else begin - litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n; + main_litedramcore_master_p1_bank <= main_litedramcore_csr_dfi_p1_bank; end end always @(*) begin - litedramcore_master_p1_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n; + main_litedramcore_master_p1_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_cas_n <= main_litedramcore_ext_dfi_p1_cas_n; end else begin - litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; + main_litedramcore_master_p1_cas_n <= main_litedramcore_slave_p1_cas_n; end end else begin - litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n; + main_litedramcore_master_p1_cas_n <= main_litedramcore_csr_dfi_p1_cas_n; end end always @(*) begin - litedramcore_master_p1_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n; + main_litedramcore_master_p1_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_cs_n <= main_litedramcore_ext_dfi_p1_cs_n; end else begin - litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; + main_litedramcore_master_p1_cs_n <= main_litedramcore_slave_p1_cs_n; + if (1'd0) begin + main_litedramcore_master_p1_cs_n <= {2{main_litedramcore_slave_p1_cs_n}}; + end end end else begin - litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n; + main_litedramcore_master_p1_cs_n <= main_litedramcore_csr_dfi_p1_cs_n; end end always @(*) begin - litedramcore_master_p1_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n; + main_litedramcore_master_p1_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_ras_n <= main_litedramcore_ext_dfi_p1_ras_n; end else begin - litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; + main_litedramcore_master_p1_ras_n <= main_litedramcore_slave_p1_ras_n; end end else begin - litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n; + main_litedramcore_master_p1_ras_n <= main_litedramcore_csr_dfi_p1_ras_n; end end always @(*) begin - litedramcore_master_p1_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke; + main_litedramcore_master_p1_we_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_we_n <= main_litedramcore_ext_dfi_p1_we_n; end else begin - litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; + main_litedramcore_master_p1_we_n <= main_litedramcore_slave_p1_we_n; end end else begin - litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke; + main_litedramcore_master_p1_we_n <= main_litedramcore_csr_dfi_p1_we_n; end end always @(*) begin - litedramcore_master_p1_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt; + main_litedramcore_master_p1_cke <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_cke <= main_litedramcore_ext_dfi_p1_cke; end else begin - litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; + main_litedramcore_master_p1_cke <= main_litedramcore_slave_p1_cke; end end else begin - litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt; + main_litedramcore_master_p1_cke <= main_litedramcore_csr_dfi_p1_cke; end end always @(*) begin - litedramcore_master_p1_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n; + main_litedramcore_master_p1_odt <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_odt <= main_litedramcore_ext_dfi_p1_odt; end else begin - litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; + main_litedramcore_master_p1_odt <= main_litedramcore_slave_p1_odt; end end else begin - litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n; + main_litedramcore_master_p1_odt <= main_litedramcore_csr_dfi_p1_odt; end end always @(*) begin - litedramcore_master_p1_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n; + main_litedramcore_master_p1_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_reset_n <= main_litedramcore_ext_dfi_p1_reset_n; end else begin - litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; + main_litedramcore_master_p1_reset_n <= main_litedramcore_slave_p1_reset_n; end end else begin - litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n; + main_litedramcore_master_p1_reset_n <= main_litedramcore_csr_dfi_p1_reset_n; end end always @(*) begin - litedramcore_master_p1_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata; + main_litedramcore_master_p1_act_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_act_n <= main_litedramcore_ext_dfi_p1_act_n; end else begin - litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; + main_litedramcore_master_p1_act_n <= main_litedramcore_slave_p1_act_n; end end else begin - litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata; + main_litedramcore_master_p1_act_n <= main_litedramcore_csr_dfi_p1_act_n; end end always @(*) begin - litedramcore_master_p1_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en; + main_litedramcore_master_p1_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_wrdata <= main_litedramcore_ext_dfi_p1_wrdata; end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; + main_litedramcore_master_p1_wrdata <= main_litedramcore_slave_p1_wrdata; end end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en; + main_litedramcore_master_p1_wrdata <= main_litedramcore_csr_dfi_p1_wrdata; end end always @(*) begin - litedramcore_master_p1_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask; + main_litedramcore_master_p1_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_wrdata_en <= main_litedramcore_ext_dfi_p1_wrdata_en; end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; + main_litedramcore_master_p1_wrdata_en <= main_litedramcore_slave_p1_wrdata_en; end end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask; + main_litedramcore_master_p1_wrdata_en <= main_litedramcore_csr_dfi_p1_wrdata_en; end end always @(*) begin - litedramcore_master_p1_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en; + main_litedramcore_master_p1_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_ext_dfi_p1_wrdata_mask; end else begin - litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; + main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_slave_p1_wrdata_mask; end end else begin - litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en; + main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_csr_dfi_p1_wrdata_mask; end end always @(*) begin - litedramcore_master_p2_address <= 14'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address; + main_litedramcore_master_p1_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_rddata_en <= main_litedramcore_ext_dfi_p1_rddata_en; end else begin - litedramcore_master_p2_address <= litedramcore_slave_p2_address; + main_litedramcore_master_p1_rddata_en <= main_litedramcore_slave_p1_rddata_en; end end else begin - litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address; + main_litedramcore_master_p1_rddata_en <= main_litedramcore_csr_dfi_p1_rddata_en; end end always @(*) begin - litedramcore_master_p2_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank; + main_litedramcore_master_p2_address <= 14'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_address <= main_litedramcore_ext_dfi_p2_address; end else begin - litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; + main_litedramcore_master_p2_address <= main_litedramcore_slave_p2_address; end end else begin - litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank; + main_litedramcore_master_p2_address <= main_litedramcore_csr_dfi_p2_address; end end always @(*) begin - litedramcore_master_p2_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n; + main_litedramcore_master_p2_bank <= 3'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_bank <= main_litedramcore_ext_dfi_p2_bank; end else begin - litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; + main_litedramcore_master_p2_bank <= main_litedramcore_slave_p2_bank; end end else begin - litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n; + main_litedramcore_master_p2_bank <= main_litedramcore_csr_dfi_p2_bank; end end always @(*) begin - litedramcore_master_p2_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n; + main_litedramcore_master_p2_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_cas_n <= main_litedramcore_ext_dfi_p2_cas_n; end else begin - litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; + main_litedramcore_master_p2_cas_n <= main_litedramcore_slave_p2_cas_n; end end else begin - litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n; + main_litedramcore_master_p2_cas_n <= main_litedramcore_csr_dfi_p2_cas_n; end end always @(*) begin - litedramcore_master_p2_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n; + main_litedramcore_master_p2_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_cs_n <= main_litedramcore_ext_dfi_p2_cs_n; end else begin - litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; + main_litedramcore_master_p2_cs_n <= main_litedramcore_slave_p2_cs_n; + if (1'd0) begin + main_litedramcore_master_p2_cs_n <= {2{main_litedramcore_slave_p2_cs_n}}; + end end end else begin - litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n; + main_litedramcore_master_p2_cs_n <= main_litedramcore_csr_dfi_p2_cs_n; end end always @(*) begin - litedramcore_master_p2_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n; + main_litedramcore_master_p2_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_ras_n <= main_litedramcore_ext_dfi_p2_ras_n; end else begin - litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; + main_litedramcore_master_p2_ras_n <= main_litedramcore_slave_p2_ras_n; end end else begin - litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n; + main_litedramcore_master_p2_ras_n <= main_litedramcore_csr_dfi_p2_ras_n; end end always @(*) begin - litedramcore_master_p2_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke; + main_litedramcore_master_p2_we_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_we_n <= main_litedramcore_ext_dfi_p2_we_n; end else begin - litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; + main_litedramcore_master_p2_we_n <= main_litedramcore_slave_p2_we_n; end end else begin - litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke; + main_litedramcore_master_p2_we_n <= main_litedramcore_csr_dfi_p2_we_n; end end always @(*) begin - litedramcore_master_p2_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt; + main_litedramcore_master_p2_cke <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_cke <= main_litedramcore_ext_dfi_p2_cke; end else begin - litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; + main_litedramcore_master_p2_cke <= main_litedramcore_slave_p2_cke; end end else begin - litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt; + main_litedramcore_master_p2_cke <= main_litedramcore_csr_dfi_p2_cke; end end always @(*) begin - litedramcore_master_p2_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n; + main_litedramcore_master_p2_odt <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_odt <= main_litedramcore_ext_dfi_p2_odt; end else begin - litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; + main_litedramcore_master_p2_odt <= main_litedramcore_slave_p2_odt; end end else begin - litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n; + main_litedramcore_master_p2_odt <= main_litedramcore_csr_dfi_p2_odt; end end always @(*) begin - litedramcore_master_p2_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n; + main_litedramcore_master_p2_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_reset_n <= main_litedramcore_ext_dfi_p2_reset_n; end else begin - litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; + main_litedramcore_master_p2_reset_n <= main_litedramcore_slave_p2_reset_n; end end else begin - litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n; + main_litedramcore_master_p2_reset_n <= main_litedramcore_csr_dfi_p2_reset_n; end end always @(*) begin - litedramcore_master_p2_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata; + main_litedramcore_master_p2_act_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_act_n <= main_litedramcore_ext_dfi_p2_act_n; end else begin - litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; + main_litedramcore_master_p2_act_n <= main_litedramcore_slave_p2_act_n; end end else begin - litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata; + main_litedramcore_master_p2_act_n <= main_litedramcore_csr_dfi_p2_act_n; end end always @(*) begin - litedramcore_master_p2_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en; + main_litedramcore_master_p2_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_wrdata <= main_litedramcore_ext_dfi_p2_wrdata; end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; + main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata; end end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en; + main_litedramcore_master_p2_wrdata <= main_litedramcore_csr_dfi_p2_wrdata; end end always @(*) begin - litedramcore_master_p2_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask; + main_litedramcore_master_p2_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_wrdata_en <= main_litedramcore_ext_dfi_p2_wrdata_en; end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; + main_litedramcore_master_p2_wrdata_en <= main_litedramcore_slave_p2_wrdata_en; end end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask; + main_litedramcore_master_p2_wrdata_en <= main_litedramcore_csr_dfi_p2_wrdata_en; end end always @(*) begin - litedramcore_master_p2_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en; + main_litedramcore_master_p2_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_ext_dfi_p2_wrdata_mask; end else begin - litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; + main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_slave_p2_wrdata_mask; end end else begin - litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en; + main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_csr_dfi_p2_wrdata_mask; end end always @(*) begin - litedramcore_master_p3_address <= 14'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address; + main_litedramcore_master_p2_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_rddata_en <= main_litedramcore_ext_dfi_p2_rddata_en; end else begin - litedramcore_master_p3_address <= litedramcore_slave_p3_address; + main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en; end end else begin - litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address; + main_litedramcore_master_p2_rddata_en <= main_litedramcore_csr_dfi_p2_rddata_en; end end always @(*) begin - litedramcore_master_p3_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank; + main_litedramcore_master_p3_address <= 14'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_address <= main_litedramcore_ext_dfi_p3_address; end else begin - litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; + main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address; end end else begin - litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank; + main_litedramcore_master_p3_address <= main_litedramcore_csr_dfi_p3_address; end end always @(*) begin - litedramcore_master_p3_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n; + main_litedramcore_master_p3_bank <= 3'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_bank <= main_litedramcore_ext_dfi_p3_bank; end else begin - litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; + main_litedramcore_master_p3_bank <= main_litedramcore_slave_p3_bank; end end else begin - litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n; + main_litedramcore_master_p3_bank <= main_litedramcore_csr_dfi_p3_bank; end end always @(*) begin - litedramcore_master_p3_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n; + main_litedramcore_master_p3_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_cas_n <= main_litedramcore_ext_dfi_p3_cas_n; end else begin - litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; + main_litedramcore_master_p3_cas_n <= main_litedramcore_slave_p3_cas_n; end end else begin - litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n; + main_litedramcore_master_p3_cas_n <= main_litedramcore_csr_dfi_p3_cas_n; end end always @(*) begin - litedramcore_master_p3_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n; + main_litedramcore_master_p3_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_cs_n <= main_litedramcore_ext_dfi_p3_cs_n; end else begin - litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; + main_litedramcore_master_p3_cs_n <= main_litedramcore_slave_p3_cs_n; + if (1'd0) begin + main_litedramcore_master_p3_cs_n <= {2{main_litedramcore_slave_p3_cs_n}}; + end end end else begin - litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n; + main_litedramcore_master_p3_cs_n <= main_litedramcore_csr_dfi_p3_cs_n; end end always @(*) begin - litedramcore_master_p3_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n; + main_litedramcore_master_p3_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_ras_n <= main_litedramcore_ext_dfi_p3_ras_n; end else begin - litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; + main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n; end end else begin - litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n; + main_litedramcore_master_p3_ras_n <= main_litedramcore_csr_dfi_p3_ras_n; end end always @(*) begin - litedramcore_master_p3_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke; + main_litedramcore_master_p3_we_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_we_n <= main_litedramcore_ext_dfi_p3_we_n; end else begin - litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; + main_litedramcore_master_p3_we_n <= main_litedramcore_slave_p3_we_n; end end else begin - litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke; + main_litedramcore_master_p3_we_n <= main_litedramcore_csr_dfi_p3_we_n; end end always @(*) begin - litedramcore_master_p3_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt; + main_litedramcore_master_p3_cke <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_cke <= main_litedramcore_ext_dfi_p3_cke; end else begin - litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; + main_litedramcore_master_p3_cke <= main_litedramcore_slave_p3_cke; end end else begin - litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt; + main_litedramcore_master_p3_cke <= main_litedramcore_csr_dfi_p3_cke; end end always @(*) begin - litedramcore_master_p3_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n; + main_litedramcore_master_p3_odt <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_odt <= main_litedramcore_ext_dfi_p3_odt; end else begin - litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; + main_litedramcore_master_p3_odt <= main_litedramcore_slave_p3_odt; end end else begin - litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n; + main_litedramcore_master_p3_odt <= main_litedramcore_csr_dfi_p3_odt; end end always @(*) begin - litedramcore_master_p3_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n; + main_litedramcore_master_p3_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_reset_n <= main_litedramcore_ext_dfi_p3_reset_n; end else begin - litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; + main_litedramcore_master_p3_reset_n <= main_litedramcore_slave_p3_reset_n; end end else begin - litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n; + main_litedramcore_master_p3_reset_n <= main_litedramcore_csr_dfi_p3_reset_n; end end always @(*) begin - litedramcore_master_p3_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata; + main_litedramcore_master_p3_act_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_act_n <= main_litedramcore_ext_dfi_p3_act_n; end else begin - litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; + main_litedramcore_master_p3_act_n <= main_litedramcore_slave_p3_act_n; end end else begin - litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata; + main_litedramcore_master_p3_act_n <= main_litedramcore_csr_dfi_p3_act_n; end end always @(*) begin - litedramcore_master_p3_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en; + main_litedramcore_master_p3_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_wrdata <= main_litedramcore_ext_dfi_p3_wrdata; end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; + main_litedramcore_master_p3_wrdata <= main_litedramcore_slave_p3_wrdata; end end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en; + main_litedramcore_master_p3_wrdata <= main_litedramcore_csr_dfi_p3_wrdata; end end always @(*) begin - litedramcore_master_p3_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask; + main_litedramcore_master_p3_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_wrdata_en <= main_litedramcore_ext_dfi_p3_wrdata_en; end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; + main_litedramcore_master_p3_wrdata_en <= main_litedramcore_slave_p3_wrdata_en; end end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask; + main_litedramcore_master_p3_wrdata_en <= main_litedramcore_csr_dfi_p3_wrdata_en; end end always @(*) begin - litedramcore_master_p3_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en; + main_litedramcore_master_p3_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_ext_dfi_p3_wrdata_mask; end else begin - litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; + main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_slave_p3_wrdata_mask; end end else begin - litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en; + main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_csr_dfi_p3_wrdata_mask; end end -assign litedramcore_csr_dfi_p0_cke = litedramcore_cke; -assign litedramcore_csr_dfi_p1_cke = litedramcore_cke; -assign litedramcore_csr_dfi_p2_cke = litedramcore_cke; -assign litedramcore_csr_dfi_p3_cke = litedramcore_cke; -assign litedramcore_csr_dfi_p0_odt = litedramcore_odt; -assign litedramcore_csr_dfi_p1_odt = litedramcore_odt; -assign litedramcore_csr_dfi_p2_odt = litedramcore_odt; -assign litedramcore_csr_dfi_p3_odt = litedramcore_odt; -assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n; -assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n; -assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n; -assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n; always @(*) begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we); + main_litedramcore_master_p3_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_rddata_en <= main_litedramcore_ext_dfi_p3_rddata_en; + end else begin + main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en; + end end else begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; + main_litedramcore_master_p3_rddata_en <= main_litedramcore_csr_dfi_p3_rddata_en; end end always @(*) begin - litedramcore_csr_dfi_p0_cas_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas); + main_litedramcore_csr_dfi_p0_cke <= 1'd0; + main_litedramcore_csr_dfi_p0_cke <= main_litedramcore_cke; +end +always @(*) begin + main_litedramcore_csr_dfi_p1_cke <= 1'd0; + main_litedramcore_csr_dfi_p1_cke <= main_litedramcore_cke; +end +always @(*) begin + main_litedramcore_csr_dfi_p2_cke <= 1'd0; + main_litedramcore_csr_dfi_p2_cke <= main_litedramcore_cke; +end +always @(*) begin + main_litedramcore_csr_dfi_p3_cke <= 1'd0; + main_litedramcore_csr_dfi_p3_cke <= main_litedramcore_cke; +end +always @(*) begin + main_litedramcore_csr_dfi_p0_odt <= 1'd0; + main_litedramcore_csr_dfi_p0_odt <= main_litedramcore_odt; +end +always @(*) begin + main_litedramcore_csr_dfi_p1_odt <= 1'd0; + main_litedramcore_csr_dfi_p1_odt <= main_litedramcore_odt; +end +always @(*) begin + main_litedramcore_csr_dfi_p2_odt <= 1'd0; + main_litedramcore_csr_dfi_p2_odt <= main_litedramcore_odt; +end +always @(*) begin + main_litedramcore_csr_dfi_p3_odt <= 1'd0; + main_litedramcore_csr_dfi_p3_odt <= main_litedramcore_odt; +end +assign main_litedramcore_csr_dfi_p0_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_csr_dfi_p1_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_csr_dfi_p2_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_csr_dfi_p3_reset_n = main_litedramcore_reset_n; +always @(*) begin + main_litedramcore_csr_dfi_p0_we_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_csr_dfi_p0_we_n <= (~main_litedramcore_phaseinjector0_csrfield_we); end else begin - litedramcore_csr_dfi_p0_cas_n <= 1'd1; + main_litedramcore_csr_dfi_p0_we_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p0_cs_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}}; + main_litedramcore_csr_dfi_p0_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_csr_dfi_p0_cas_n <= (~main_litedramcore_phaseinjector0_csrfield_cas); end else begin - litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; + main_litedramcore_csr_dfi_p0_cas_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p0_ras_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras); + main_litedramcore_csr_dfi_p0_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + if (main_litedramcore_phaseinjector0_csrfield_cs_top) begin + main_litedramcore_csr_dfi_p0_cs_n <= 2'd2; + end else begin + if (main_litedramcore_phaseinjector0_csrfield_cs_bottom) begin + main_litedramcore_csr_dfi_p0_cs_n <= 1'd1; + end else begin + main_litedramcore_csr_dfi_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_csrfield_cs)}}; + end + end end else begin - litedramcore_csr_dfi_p0_ras_n <= 1'd1; + main_litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; end end -assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage; -assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage; -assign litedramcore_csr_dfi_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_wren); -assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_rden); -assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; -assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we); + main_litedramcore_csr_dfi_p0_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_csr_dfi_p0_ras_n <= (~main_litedramcore_phaseinjector0_csrfield_ras); end else begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; + main_litedramcore_csr_dfi_p0_ras_n <= 1'd1; end end +assign main_litedramcore_csr_dfi_p0_address = main_litedramcore_phaseinjector0_address_storage; +assign main_litedramcore_csr_dfi_p0_bank = main_litedramcore_phaseinjector0_baddress_storage; +assign main_litedramcore_csr_dfi_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_wren); +assign main_litedramcore_csr_dfi_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_rden); +assign main_litedramcore_csr_dfi_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage; +assign main_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p1_cas_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas); + main_litedramcore_csr_dfi_p1_we_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_csr_dfi_p1_we_n <= (~main_litedramcore_phaseinjector1_csrfield_we); end else begin - litedramcore_csr_dfi_p1_cas_n <= 1'd1; + main_litedramcore_csr_dfi_p1_we_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p1_cs_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}}; + main_litedramcore_csr_dfi_p1_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_csr_dfi_p1_cas_n <= (~main_litedramcore_phaseinjector1_csrfield_cas); end else begin - litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; + main_litedramcore_csr_dfi_p1_cas_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p1_ras_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras); + main_litedramcore_csr_dfi_p1_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + if (main_litedramcore_phaseinjector1_csrfield_cs_top) begin + main_litedramcore_csr_dfi_p1_cs_n <= 2'd2; + end else begin + if (main_litedramcore_phaseinjector1_csrfield_cs_bottom) begin + main_litedramcore_csr_dfi_p1_cs_n <= 1'd1; + end else begin + main_litedramcore_csr_dfi_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_csrfield_cs)}}; + end + end end else begin - litedramcore_csr_dfi_p1_ras_n <= 1'd1; + main_litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; end end -assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage; -assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage; -assign litedramcore_csr_dfi_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_wren); -assign litedramcore_csr_dfi_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_rden); -assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; -assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p2_we_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we); + main_litedramcore_csr_dfi_p1_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_csr_dfi_p1_ras_n <= (~main_litedramcore_phaseinjector1_csrfield_ras); end else begin - litedramcore_csr_dfi_p2_we_n <= 1'd1; + main_litedramcore_csr_dfi_p1_ras_n <= 1'd1; end end +assign main_litedramcore_csr_dfi_p1_address = main_litedramcore_phaseinjector1_address_storage; +assign main_litedramcore_csr_dfi_p1_bank = main_litedramcore_phaseinjector1_baddress_storage; +assign main_litedramcore_csr_dfi_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_wren); +assign main_litedramcore_csr_dfi_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_rden); +assign main_litedramcore_csr_dfi_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage; +assign main_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p2_cas_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas); + main_litedramcore_csr_dfi_p2_we_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_csr_dfi_p2_we_n <= (~main_litedramcore_phaseinjector2_csrfield_we); end else begin - litedramcore_csr_dfi_p2_cas_n <= 1'd1; + main_litedramcore_csr_dfi_p2_we_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p2_cs_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}}; + main_litedramcore_csr_dfi_p2_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_csr_dfi_p2_cas_n <= (~main_litedramcore_phaseinjector2_csrfield_cas); end else begin - litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; + main_litedramcore_csr_dfi_p2_cas_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p2_ras_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras); + main_litedramcore_csr_dfi_p2_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + if (main_litedramcore_phaseinjector2_csrfield_cs_top) begin + main_litedramcore_csr_dfi_p2_cs_n <= 2'd2; + end else begin + if (main_litedramcore_phaseinjector2_csrfield_cs_bottom) begin + main_litedramcore_csr_dfi_p2_cs_n <= 1'd1; + end else begin + main_litedramcore_csr_dfi_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_csrfield_cs)}}; + end + end end else begin - litedramcore_csr_dfi_p2_ras_n <= 1'd1; + main_litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; end end -assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage; -assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage; -assign litedramcore_csr_dfi_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_wren); -assign litedramcore_csr_dfi_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_rden); -assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage; -assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p3_we_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we); + main_litedramcore_csr_dfi_p2_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_csr_dfi_p2_ras_n <= (~main_litedramcore_phaseinjector2_csrfield_ras); end else begin - litedramcore_csr_dfi_p3_we_n <= 1'd1; + main_litedramcore_csr_dfi_p2_ras_n <= 1'd1; end end +assign main_litedramcore_csr_dfi_p2_address = main_litedramcore_phaseinjector2_address_storage; +assign main_litedramcore_csr_dfi_p2_bank = main_litedramcore_phaseinjector2_baddress_storage; +assign main_litedramcore_csr_dfi_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_wren); +assign main_litedramcore_csr_dfi_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_rden); +assign main_litedramcore_csr_dfi_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage; +assign main_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p3_cas_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas); + main_litedramcore_csr_dfi_p3_we_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_csr_dfi_p3_we_n <= (~main_litedramcore_phaseinjector3_csrfield_we); end else begin - litedramcore_csr_dfi_p3_cas_n <= 1'd1; + main_litedramcore_csr_dfi_p3_we_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p3_cs_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}}; + main_litedramcore_csr_dfi_p3_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_csr_dfi_p3_cas_n <= (~main_litedramcore_phaseinjector3_csrfield_cas); end else begin - litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; + main_litedramcore_csr_dfi_p3_cas_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p3_ras_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras); + main_litedramcore_csr_dfi_p3_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + if (main_litedramcore_phaseinjector3_csrfield_cs_top) begin + main_litedramcore_csr_dfi_p3_cs_n <= 2'd2; + end else begin + if (main_litedramcore_phaseinjector3_csrfield_cs_bottom) begin + main_litedramcore_csr_dfi_p3_cs_n <= 1'd1; + end else begin + main_litedramcore_csr_dfi_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_csrfield_cs)}}; + end + end end else begin - litedramcore_csr_dfi_p3_ras_n <= 1'd1; + main_litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; end end -assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage; -assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage; -assign litedramcore_csr_dfi_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_wren); -assign litedramcore_csr_dfi_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_rden); -assign litedramcore_csr_dfi_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage; -assign litedramcore_csr_dfi_p3_wrdata_mask = 1'd0; -assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid; -assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready; -assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we; -assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr; -assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock; -assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready; -assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid; -assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid; -assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready; -assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we; -assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr; -assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock; -assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready; -assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid; -assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid; -assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready; -assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we; -assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr; -assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock; -assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready; -assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid; -assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid; -assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready; -assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we; -assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr; -assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock; -assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready; -assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid; -assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid; -assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready; -assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we; -assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr; -assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock; -assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready; -assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid; -assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid; -assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready; -assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we; -assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr; -assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock; -assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready; -assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid; -assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid; -assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready; -assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we; -assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr; -assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock; -assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready; -assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid; -assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid; -assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready; -assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we; -assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr; -assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock; -assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready; -assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid; -assign litedramcore_timer_wait = (~litedramcore_timer_done0); -assign litedramcore_postponer_req_i = litedramcore_timer_done0; -assign litedramcore_wants_refresh = litedramcore_postponer_req_o; -assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0; -assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done); -assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0); -assign litedramcore_timer_done0 = litedramcore_timer_done1; -assign litedramcore_timer_count0 = litedramcore_timer_count1; -assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0)); -assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0)); -assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0); -assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1; -assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1; -always @(*) begin - litedramcore_refresher_next_state <= 2'd0; - litedramcore_refresher_next_state <= litedramcore_refresher_state; - case (litedramcore_refresher_state) - 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_refresher_next_state <= 2'd2; - end - end - 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - litedramcore_refresher_next_state <= 2'd3; +always @(*) begin + main_litedramcore_csr_dfi_p3_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_csr_dfi_p3_ras_n <= (~main_litedramcore_phaseinjector3_csrfield_ras); + end else begin + main_litedramcore_csr_dfi_p3_ras_n <= 1'd1; + end +end +assign main_litedramcore_csr_dfi_p3_address = main_litedramcore_phaseinjector3_address_storage; +assign main_litedramcore_csr_dfi_p3_bank = main_litedramcore_phaseinjector3_baddress_storage; +assign main_litedramcore_csr_dfi_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_wren); +assign main_litedramcore_csr_dfi_p3_rddata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_rden); +assign main_litedramcore_csr_dfi_p3_wrdata = main_litedramcore_phaseinjector3_wrdata_storage; +assign main_litedramcore_csr_dfi_p3_wrdata_mask = 1'd0; +assign main_litedramcore_bankmachine0_req_valid = main_litedramcore_interface_bank0_valid; +assign main_litedramcore_interface_bank0_ready = main_litedramcore_bankmachine0_req_ready; +assign main_litedramcore_bankmachine0_req_we = main_litedramcore_interface_bank0_we; +assign main_litedramcore_bankmachine0_req_addr = main_litedramcore_interface_bank0_addr; +assign main_litedramcore_interface_bank0_lock = main_litedramcore_bankmachine0_req_lock; +assign main_litedramcore_interface_bank0_wdata_ready = main_litedramcore_bankmachine0_req_wdata_ready; +assign main_litedramcore_interface_bank0_rdata_valid = main_litedramcore_bankmachine0_req_rdata_valid; +assign main_litedramcore_bankmachine1_req_valid = main_litedramcore_interface_bank1_valid; +assign main_litedramcore_interface_bank1_ready = main_litedramcore_bankmachine1_req_ready; +assign main_litedramcore_bankmachine1_req_we = main_litedramcore_interface_bank1_we; +assign main_litedramcore_bankmachine1_req_addr = main_litedramcore_interface_bank1_addr; +assign main_litedramcore_interface_bank1_lock = main_litedramcore_bankmachine1_req_lock; +assign main_litedramcore_interface_bank1_wdata_ready = main_litedramcore_bankmachine1_req_wdata_ready; +assign main_litedramcore_interface_bank1_rdata_valid = main_litedramcore_bankmachine1_req_rdata_valid; +assign main_litedramcore_bankmachine2_req_valid = main_litedramcore_interface_bank2_valid; +assign main_litedramcore_interface_bank2_ready = main_litedramcore_bankmachine2_req_ready; +assign main_litedramcore_bankmachine2_req_we = main_litedramcore_interface_bank2_we; +assign main_litedramcore_bankmachine2_req_addr = main_litedramcore_interface_bank2_addr; +assign main_litedramcore_interface_bank2_lock = main_litedramcore_bankmachine2_req_lock; +assign main_litedramcore_interface_bank2_wdata_ready = main_litedramcore_bankmachine2_req_wdata_ready; +assign main_litedramcore_interface_bank2_rdata_valid = main_litedramcore_bankmachine2_req_rdata_valid; +assign main_litedramcore_bankmachine3_req_valid = main_litedramcore_interface_bank3_valid; +assign main_litedramcore_interface_bank3_ready = main_litedramcore_bankmachine3_req_ready; +assign main_litedramcore_bankmachine3_req_we = main_litedramcore_interface_bank3_we; +assign main_litedramcore_bankmachine3_req_addr = main_litedramcore_interface_bank3_addr; +assign main_litedramcore_interface_bank3_lock = main_litedramcore_bankmachine3_req_lock; +assign main_litedramcore_interface_bank3_wdata_ready = main_litedramcore_bankmachine3_req_wdata_ready; +assign main_litedramcore_interface_bank3_rdata_valid = main_litedramcore_bankmachine3_req_rdata_valid; +assign main_litedramcore_bankmachine4_req_valid = main_litedramcore_interface_bank4_valid; +assign main_litedramcore_interface_bank4_ready = main_litedramcore_bankmachine4_req_ready; +assign main_litedramcore_bankmachine4_req_we = main_litedramcore_interface_bank4_we; +assign main_litedramcore_bankmachine4_req_addr = main_litedramcore_interface_bank4_addr; +assign main_litedramcore_interface_bank4_lock = main_litedramcore_bankmachine4_req_lock; +assign main_litedramcore_interface_bank4_wdata_ready = main_litedramcore_bankmachine4_req_wdata_ready; +assign main_litedramcore_interface_bank4_rdata_valid = main_litedramcore_bankmachine4_req_rdata_valid; +assign main_litedramcore_bankmachine5_req_valid = main_litedramcore_interface_bank5_valid; +assign main_litedramcore_interface_bank5_ready = main_litedramcore_bankmachine5_req_ready; +assign main_litedramcore_bankmachine5_req_we = main_litedramcore_interface_bank5_we; +assign main_litedramcore_bankmachine5_req_addr = main_litedramcore_interface_bank5_addr; +assign main_litedramcore_interface_bank5_lock = main_litedramcore_bankmachine5_req_lock; +assign main_litedramcore_interface_bank5_wdata_ready = main_litedramcore_bankmachine5_req_wdata_ready; +assign main_litedramcore_interface_bank5_rdata_valid = main_litedramcore_bankmachine5_req_rdata_valid; +assign main_litedramcore_bankmachine6_req_valid = main_litedramcore_interface_bank6_valid; +assign main_litedramcore_interface_bank6_ready = main_litedramcore_bankmachine6_req_ready; +assign main_litedramcore_bankmachine6_req_we = main_litedramcore_interface_bank6_we; +assign main_litedramcore_bankmachine6_req_addr = main_litedramcore_interface_bank6_addr; +assign main_litedramcore_interface_bank6_lock = main_litedramcore_bankmachine6_req_lock; +assign main_litedramcore_interface_bank6_wdata_ready = main_litedramcore_bankmachine6_req_wdata_ready; +assign main_litedramcore_interface_bank6_rdata_valid = main_litedramcore_bankmachine6_req_rdata_valid; +assign main_litedramcore_bankmachine7_req_valid = main_litedramcore_interface_bank7_valid; +assign main_litedramcore_interface_bank7_ready = main_litedramcore_bankmachine7_req_ready; +assign main_litedramcore_bankmachine7_req_we = main_litedramcore_interface_bank7_we; +assign main_litedramcore_bankmachine7_req_addr = main_litedramcore_interface_bank7_addr; +assign main_litedramcore_interface_bank7_lock = main_litedramcore_bankmachine7_req_lock; +assign main_litedramcore_interface_bank7_wdata_ready = main_litedramcore_bankmachine7_req_wdata_ready; +assign main_litedramcore_interface_bank7_rdata_valid = main_litedramcore_bankmachine7_req_rdata_valid; +assign main_litedramcore_timer_wait = (~main_litedramcore_timer_done0); +assign main_litedramcore_postponer_req_i = main_litedramcore_timer_done0; +assign main_litedramcore_wants_refresh = main_litedramcore_postponer_req_o; +assign main_litedramcore_wants_zqcs = main_litedramcore_zqcs_timer_done0; +assign main_litedramcore_zqcs_timer_wait = (~main_litedramcore_zqcs_executer_done); +assign main_litedramcore_timer_done1 = (main_litedramcore_timer_count1 == 1'd0); +assign main_litedramcore_timer_done0 = main_litedramcore_timer_done1; +assign main_litedramcore_timer_count0 = main_litedramcore_timer_count1; +assign main_litedramcore_sequencer_start1 = (main_litedramcore_sequencer_start0 | (main_litedramcore_sequencer_count != 1'd0)); +assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & (main_litedramcore_sequencer_count == 1'd0)); +assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0); +assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1; +assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1; +always @(*) begin + builder_refresher_next_state <= 2'd0; + builder_refresher_next_state <= builder_refresher_state; + case (builder_refresher_state) + 1'd1: begin + if (main_litedramcore_cmd_ready) begin + builder_refresher_next_state <= 2'd2; + end + end + 2'd2: begin + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + builder_refresher_next_state <= 2'd3; end else begin - litedramcore_refresher_next_state <= 1'd0; + builder_refresher_next_state <= 1'd0; end end end 2'd3: begin - if (litedramcore_zqcs_executer_done) begin - litedramcore_refresher_next_state <= 1'd0; + if (main_litedramcore_zqcs_executer_done) begin + builder_refresher_next_state <= 1'd0; end end default: begin if (1'd1) begin - if (litedramcore_wants_refresh) begin - litedramcore_refresher_next_state <= 1'd1; + if (main_litedramcore_wants_refresh) begin + builder_refresher_next_state <= 1'd1; end end end endcase end always @(*) begin - litedramcore_zqcs_executer_start <= 1'd0; - case (litedramcore_refresher_state) + main_litedramcore_cmd_valid <= 1'd0; + case (builder_refresher_state) 1'd1: begin + main_litedramcore_cmd_valid <= 1'd1; end 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - litedramcore_zqcs_executer_start <= 1'd1; + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin end else begin + main_litedramcore_cmd_valid <= 1'd0; end end end 2'd3: begin + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_valid <= 1'd0; + end end default: begin end endcase end always @(*) begin - litedramcore_cmd_last <= 1'd0; - case (litedramcore_refresher_state) + main_litedramcore_zqcs_executer_start <= 1'd0; + case (builder_refresher_state) 1'd1: begin end 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + main_litedramcore_zqcs_executer_start <= 1'd1; end else begin - litedramcore_cmd_last <= 1'd1; end end end 2'd3: begin - if (litedramcore_zqcs_executer_done) begin - litedramcore_cmd_last <= 1'd1; - end end default: begin end endcase end always @(*) begin - litedramcore_sequencer_start0 <= 1'd0; - case (litedramcore_refresher_state) + main_litedramcore_cmd_last <= 1'd0; + case (builder_refresher_state) 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_sequencer_start0 <= 1'd1; - end end 2'd2: begin + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + end else begin + main_litedramcore_cmd_last <= 1'd1; + end + end end 2'd3: begin + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_last <= 1'd1; + end end default: begin end endcase end always @(*) begin - litedramcore_cmd_valid <= 1'd0; - case (litedramcore_refresher_state) + main_litedramcore_sequencer_start0 <= 1'd0; + case (builder_refresher_state) 1'd1: begin - litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_cmd_ready) begin + main_litedramcore_sequencer_start0 <= 1'd1; + end end 2'd2: begin - litedramcore_cmd_valid <= 1'd1; - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - end else begin - litedramcore_cmd_valid <= 1'd0; - end - end end 2'd3: begin - litedramcore_cmd_valid <= 1'd1; - if (litedramcore_zqcs_executer_done) begin - litedramcore_cmd_valid <= 1'd0; - end - end - default: begin - end - endcase -end -assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid; -assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready; -assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we; -assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr; -assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid; -assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready; -assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first; -assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last; -assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we; -assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr; -assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); -assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid); -assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[20:7]); -assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0; -always @(*) begin - litedramcore_bankmachine0_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine0_row_col_n_addr_sel) begin - litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_source_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write); -assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); -assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); -always @(*) begin - litedramcore_bankmachine0_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin - if ((litedramcore_bankmachine0_source_payload_addr[20:7] != litedramcore_bankmachine0_source_source_payload_addr[20:7])) begin - litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we}; -assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; -assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; -assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; -assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; -assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable; -assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid; -assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first; -assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last; -assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we; -assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr; -assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable; -assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first; -assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last; -assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we; -assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr; -assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready; -always @(*) begin - litedramcore_bankmachine0_wrport_adr <= 4'd0; - if (litedramcore_bankmachine0_replace) begin - litedramcore_bankmachine0_wrport_adr <= (litedramcore_bankmachine0_produce - 1'd1); - end else begin - litedramcore_bankmachine0_wrport_adr <= litedramcore_bankmachine0_produce; - end -end -assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din; -assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace)); -assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re); -assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume; -assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r; -assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 5'd16); -assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0); -assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready); -assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid; -assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready; -assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first; -assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last; -assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we; -assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr; -assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid; -assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready; -assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first; -assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last; -assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we; -assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine0_next_state <= 4'd0; - litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - if (litedramcore_bankmachine0_cmd_ready) begin - litedramcore_bankmachine0_next_state <= 3'd5; + end + default: begin + end + endcase +end +assign main_litedramcore_bankmachine0_sink_valid = main_litedramcore_bankmachine0_req_valid; +assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_sink_ready; +assign main_litedramcore_bankmachine0_sink_payload_we = main_litedramcore_bankmachine0_req_we; +assign main_litedramcore_bankmachine0_sink_payload_addr = main_litedramcore_bankmachine0_req_addr; +assign main_litedramcore_bankmachine0_sink_sink_valid = main_litedramcore_bankmachine0_source_valid; +assign main_litedramcore_bankmachine0_source_ready = main_litedramcore_bankmachine0_sink_sink_ready; +assign main_litedramcore_bankmachine0_sink_sink_first = main_litedramcore_bankmachine0_source_first; +assign main_litedramcore_bankmachine0_sink_sink_last = main_litedramcore_bankmachine0_source_last; +assign main_litedramcore_bankmachine0_sink_sink_payload_we = main_litedramcore_bankmachine0_source_payload_we; +assign main_litedramcore_bankmachine0_sink_sink_payload_addr = main_litedramcore_bankmachine0_source_payload_addr; +assign main_litedramcore_bankmachine0_source_source_ready = (main_litedramcore_bankmachine0_req_wdata_ready | main_litedramcore_bankmachine0_req_rdata_valid); +assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_source_valid | main_litedramcore_bankmachine0_source_source_valid); +assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_source_source_payload_addr[20:7]); +assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0; +always @(*) begin + main_litedramcore_bankmachine0_cmd_payload_a <= 14'd0; + if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin + main_litedramcore_bankmachine0_cmd_payload_a <= main_litedramcore_bankmachine0_source_source_payload_addr[20:7]; + end else begin + main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write); +assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); +assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); +always @(*) begin + main_litedramcore_bankmachine0_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine0_source_valid & main_litedramcore_bankmachine0_source_source_valid)) begin + if ((main_litedramcore_bankmachine0_source_payload_addr[20:7] != main_litedramcore_bankmachine0_source_source_payload_addr[20:7])) begin + main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine0_syncfifo0_din = {main_litedramcore_bankmachine0_fifo_in_last, main_litedramcore_bankmachine0_fifo_in_first, main_litedramcore_bankmachine0_fifo_in_payload_addr, main_litedramcore_bankmachine0_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout; +assign main_litedramcore_bankmachine0_sink_ready = main_litedramcore_bankmachine0_syncfifo0_writable; +assign main_litedramcore_bankmachine0_syncfifo0_we = main_litedramcore_bankmachine0_sink_valid; +assign main_litedramcore_bankmachine0_fifo_in_first = main_litedramcore_bankmachine0_sink_first; +assign main_litedramcore_bankmachine0_fifo_in_last = main_litedramcore_bankmachine0_sink_last; +assign main_litedramcore_bankmachine0_fifo_in_payload_we = main_litedramcore_bankmachine0_sink_payload_we; +assign main_litedramcore_bankmachine0_fifo_in_payload_addr = main_litedramcore_bankmachine0_sink_payload_addr; +assign main_litedramcore_bankmachine0_source_valid = main_litedramcore_bankmachine0_syncfifo0_readable; +assign main_litedramcore_bankmachine0_source_first = main_litedramcore_bankmachine0_fifo_out_first; +assign main_litedramcore_bankmachine0_source_last = main_litedramcore_bankmachine0_fifo_out_last; +assign main_litedramcore_bankmachine0_source_payload_we = main_litedramcore_bankmachine0_fifo_out_payload_we; +assign main_litedramcore_bankmachine0_source_payload_addr = main_litedramcore_bankmachine0_fifo_out_payload_addr; +assign main_litedramcore_bankmachine0_syncfifo0_re = main_litedramcore_bankmachine0_source_ready; +always @(*) begin + main_litedramcore_bankmachine0_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine0_replace) begin + main_litedramcore_bankmachine0_wrport_adr <= (main_litedramcore_bankmachine0_produce - 1'd1); + end else begin + main_litedramcore_bankmachine0_wrport_adr <= main_litedramcore_bankmachine0_produce; + end +end +assign main_litedramcore_bankmachine0_wrport_dat_w = main_litedramcore_bankmachine0_syncfifo0_din; +assign main_litedramcore_bankmachine0_wrport_we = (main_litedramcore_bankmachine0_syncfifo0_we & (main_litedramcore_bankmachine0_syncfifo0_writable | main_litedramcore_bankmachine0_replace)); +assign main_litedramcore_bankmachine0_do_read = (main_litedramcore_bankmachine0_syncfifo0_readable & main_litedramcore_bankmachine0_syncfifo0_re); +assign main_litedramcore_bankmachine0_rdport_adr = main_litedramcore_bankmachine0_consume; +assign main_litedramcore_bankmachine0_syncfifo0_dout = main_litedramcore_bankmachine0_rdport_dat_r; +assign main_litedramcore_bankmachine0_syncfifo0_writable = (main_litedramcore_bankmachine0_level != 5'd16); +assign main_litedramcore_bankmachine0_syncfifo0_readable = (main_litedramcore_bankmachine0_level != 1'd0); +assign main_litedramcore_bankmachine0_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine0_pipe_valid_source_valid) | main_litedramcore_bankmachine0_pipe_valid_source_ready); +assign main_litedramcore_bankmachine0_pipe_valid_sink_valid = main_litedramcore_bankmachine0_sink_sink_valid; +assign main_litedramcore_bankmachine0_sink_sink_ready = main_litedramcore_bankmachine0_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine0_pipe_valid_sink_first = main_litedramcore_bankmachine0_sink_sink_first; +assign main_litedramcore_bankmachine0_pipe_valid_sink_last = main_litedramcore_bankmachine0_sink_sink_last; +assign main_litedramcore_bankmachine0_pipe_valid_sink_payload_we = main_litedramcore_bankmachine0_sink_sink_payload_we; +assign main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine0_sink_sink_payload_addr; +assign main_litedramcore_bankmachine0_source_source_valid = main_litedramcore_bankmachine0_pipe_valid_source_valid; +assign main_litedramcore_bankmachine0_pipe_valid_source_ready = main_litedramcore_bankmachine0_source_source_ready; +assign main_litedramcore_bankmachine0_source_source_first = main_litedramcore_bankmachine0_pipe_valid_source_first; +assign main_litedramcore_bankmachine0_source_source_last = main_litedramcore_bankmachine0_pipe_valid_source_last; +assign main_litedramcore_bankmachine0_source_source_payload_we = main_litedramcore_bankmachine0_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine0_source_source_payload_addr = main_litedramcore_bankmachine0_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine0_next_state <= 4'd0; + builder_bankmachine0_next_state <= builder_bankmachine0_state; + case (builder_bankmachine0_state) + 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + if (main_litedramcore_bankmachine0_cmd_ready) begin + builder_bankmachine0_next_state <= 3'd5; end end end 2'd2: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_next_state <= 3'd5; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + builder_bankmachine0_next_state <= 3'd5; end end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - if (litedramcore_bankmachine0_cmd_ready) begin - litedramcore_bankmachine0_next_state <= 3'd7; + if (main_litedramcore_bankmachine0_trccon_ready) begin + if (main_litedramcore_bankmachine0_cmd_ready) begin + builder_bankmachine0_next_state <= 3'd7; end end end 3'd4: begin - if ((~litedramcore_bankmachine0_refresh_req)) begin - litedramcore_bankmachine0_next_state <= 1'd0; + if ((~main_litedramcore_bankmachine0_refresh_req)) begin + builder_bankmachine0_next_state <= 1'd0; end end 3'd5: begin - litedramcore_bankmachine0_next_state <= 3'd6; + builder_bankmachine0_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine0_next_state <= 2'd3; + builder_bankmachine0_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine0_next_state <= 4'd8; + builder_bankmachine0_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine0_next_state <= 1'd0; + builder_bankmachine0_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - litedramcore_bankmachine0_next_state <= 3'd4; + if (main_litedramcore_bankmachine0_refresh_req) begin + builder_bankmachine0_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin - litedramcore_bankmachine0_next_state <= 2'd2; + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if ((main_litedramcore_bankmachine0_cmd_ready & main_litedramcore_bankmachine0_auto_precharge)) begin + builder_bankmachine0_next_state <= 2'd2; end end else begin - litedramcore_bankmachine0_next_state <= 1'd1; + builder_bankmachine0_next_state <= 1'd1; end end else begin - litedramcore_bankmachine0_next_state <= 2'd3; + builder_bankmachine0_next_state <= 2'd3; end end end @@ -4888,8 +5306,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -4907,14 +5325,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; end else begin - litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; end end else begin end @@ -4926,8 +5344,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -4935,9 +5353,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine0_twtpcon_ready) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -4948,20 +5363,32 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin + main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine0_row_open <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_open <= 1'd1; - end end 3'd4: begin end @@ -4974,25 +5401,37 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin + end else begin + main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine0_cmd_valid <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_refresh_gnt <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine0_twtpcon_ready) begin + main_litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -5003,34 +5442,22 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine0_row_close <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_row_open <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - litedramcore_bankmachine0_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_row_open <= 1'd1; + end end 3'd4: begin - litedramcore_bankmachine0_row_close <= 1'd1; end 3'd5: begin end @@ -5045,15 +5472,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; end end 3'd4: begin @@ -5067,19 +5497,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_row_close <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin + main_litedramcore_bankmachine0_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + main_litedramcore_bankmachine0_row_close <= 1'd1; end 3'd5: begin end @@ -5090,34 +5535,19 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -5135,12 +5565,9 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -5157,15 +5584,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end else begin - end + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -5176,22 +5600,21 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5206,9 +5629,12 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -5225,14 +5651,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; end else begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; end end else begin end @@ -5244,15 +5670,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5263,27 +5696,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine0_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5301,14 +5719,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin - litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin end else begin + main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; end end else begin end @@ -5319,139 +5737,139 @@ always @(*) begin end endcase end -assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid; -assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready; -assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we; -assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr; -assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid; -assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready; -assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first; -assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last; -assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we; -assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr; -assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); -assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid); -assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[20:7]); -assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1; -always @(*) begin - litedramcore_bankmachine1_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine1_row_col_n_addr_sel) begin - litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_source_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write); -assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); -assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); -always @(*) begin - litedramcore_bankmachine1_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin - if ((litedramcore_bankmachine1_source_payload_addr[20:7] != litedramcore_bankmachine1_source_source_payload_addr[20:7])) begin - litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we}; -assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; -assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; -assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; -assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; -assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable; -assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid; -assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first; -assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last; -assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we; -assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr; -assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable; -assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first; -assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last; -assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we; -assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr; -assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready; -always @(*) begin - litedramcore_bankmachine1_wrport_adr <= 4'd0; - if (litedramcore_bankmachine1_replace) begin - litedramcore_bankmachine1_wrport_adr <= (litedramcore_bankmachine1_produce - 1'd1); - end else begin - litedramcore_bankmachine1_wrport_adr <= litedramcore_bankmachine1_produce; - end -end -assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din; -assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace)); -assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re); -assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume; -assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r; -assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 5'd16); -assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0); -assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready); -assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid; -assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready; -assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first; -assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last; -assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we; -assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr; -assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid; -assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready; -assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first; -assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last; -assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we; -assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine1_next_state <= 4'd0; - litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - if (litedramcore_bankmachine1_cmd_ready) begin - litedramcore_bankmachine1_next_state <= 3'd5; +assign main_litedramcore_bankmachine1_sink_valid = main_litedramcore_bankmachine1_req_valid; +assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_sink_ready; +assign main_litedramcore_bankmachine1_sink_payload_we = main_litedramcore_bankmachine1_req_we; +assign main_litedramcore_bankmachine1_sink_payload_addr = main_litedramcore_bankmachine1_req_addr; +assign main_litedramcore_bankmachine1_sink_sink_valid = main_litedramcore_bankmachine1_source_valid; +assign main_litedramcore_bankmachine1_source_ready = main_litedramcore_bankmachine1_sink_sink_ready; +assign main_litedramcore_bankmachine1_sink_sink_first = main_litedramcore_bankmachine1_source_first; +assign main_litedramcore_bankmachine1_sink_sink_last = main_litedramcore_bankmachine1_source_last; +assign main_litedramcore_bankmachine1_sink_sink_payload_we = main_litedramcore_bankmachine1_source_payload_we; +assign main_litedramcore_bankmachine1_sink_sink_payload_addr = main_litedramcore_bankmachine1_source_payload_addr; +assign main_litedramcore_bankmachine1_source_source_ready = (main_litedramcore_bankmachine1_req_wdata_ready | main_litedramcore_bankmachine1_req_rdata_valid); +assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_source_valid | main_litedramcore_bankmachine1_source_source_valid); +assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_source_source_payload_addr[20:7]); +assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; +always @(*) begin + main_litedramcore_bankmachine1_cmd_payload_a <= 14'd0; + if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin + main_litedramcore_bankmachine1_cmd_payload_a <= main_litedramcore_bankmachine1_source_source_payload_addr[20:7]; + end else begin + main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write); +assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); +assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); +always @(*) begin + main_litedramcore_bankmachine1_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine1_source_valid & main_litedramcore_bankmachine1_source_source_valid)) begin + if ((main_litedramcore_bankmachine1_source_payload_addr[20:7] != main_litedramcore_bankmachine1_source_source_payload_addr[20:7])) begin + main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine1_syncfifo1_din = {main_litedramcore_bankmachine1_fifo_in_last, main_litedramcore_bankmachine1_fifo_in_first, main_litedramcore_bankmachine1_fifo_in_payload_addr, main_litedramcore_bankmachine1_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout; +assign main_litedramcore_bankmachine1_sink_ready = main_litedramcore_bankmachine1_syncfifo1_writable; +assign main_litedramcore_bankmachine1_syncfifo1_we = main_litedramcore_bankmachine1_sink_valid; +assign main_litedramcore_bankmachine1_fifo_in_first = main_litedramcore_bankmachine1_sink_first; +assign main_litedramcore_bankmachine1_fifo_in_last = main_litedramcore_bankmachine1_sink_last; +assign main_litedramcore_bankmachine1_fifo_in_payload_we = main_litedramcore_bankmachine1_sink_payload_we; +assign main_litedramcore_bankmachine1_fifo_in_payload_addr = main_litedramcore_bankmachine1_sink_payload_addr; +assign main_litedramcore_bankmachine1_source_valid = main_litedramcore_bankmachine1_syncfifo1_readable; +assign main_litedramcore_bankmachine1_source_first = main_litedramcore_bankmachine1_fifo_out_first; +assign main_litedramcore_bankmachine1_source_last = main_litedramcore_bankmachine1_fifo_out_last; +assign main_litedramcore_bankmachine1_source_payload_we = main_litedramcore_bankmachine1_fifo_out_payload_we; +assign main_litedramcore_bankmachine1_source_payload_addr = main_litedramcore_bankmachine1_fifo_out_payload_addr; +assign main_litedramcore_bankmachine1_syncfifo1_re = main_litedramcore_bankmachine1_source_ready; +always @(*) begin + main_litedramcore_bankmachine1_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine1_replace) begin + main_litedramcore_bankmachine1_wrport_adr <= (main_litedramcore_bankmachine1_produce - 1'd1); + end else begin + main_litedramcore_bankmachine1_wrport_adr <= main_litedramcore_bankmachine1_produce; + end +end +assign main_litedramcore_bankmachine1_wrport_dat_w = main_litedramcore_bankmachine1_syncfifo1_din; +assign main_litedramcore_bankmachine1_wrport_we = (main_litedramcore_bankmachine1_syncfifo1_we & (main_litedramcore_bankmachine1_syncfifo1_writable | main_litedramcore_bankmachine1_replace)); +assign main_litedramcore_bankmachine1_do_read = (main_litedramcore_bankmachine1_syncfifo1_readable & main_litedramcore_bankmachine1_syncfifo1_re); +assign main_litedramcore_bankmachine1_rdport_adr = main_litedramcore_bankmachine1_consume; +assign main_litedramcore_bankmachine1_syncfifo1_dout = main_litedramcore_bankmachine1_rdport_dat_r; +assign main_litedramcore_bankmachine1_syncfifo1_writable = (main_litedramcore_bankmachine1_level != 5'd16); +assign main_litedramcore_bankmachine1_syncfifo1_readable = (main_litedramcore_bankmachine1_level != 1'd0); +assign main_litedramcore_bankmachine1_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine1_pipe_valid_source_valid) | main_litedramcore_bankmachine1_pipe_valid_source_ready); +assign main_litedramcore_bankmachine1_pipe_valid_sink_valid = main_litedramcore_bankmachine1_sink_sink_valid; +assign main_litedramcore_bankmachine1_sink_sink_ready = main_litedramcore_bankmachine1_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine1_pipe_valid_sink_first = main_litedramcore_bankmachine1_sink_sink_first; +assign main_litedramcore_bankmachine1_pipe_valid_sink_last = main_litedramcore_bankmachine1_sink_sink_last; +assign main_litedramcore_bankmachine1_pipe_valid_sink_payload_we = main_litedramcore_bankmachine1_sink_sink_payload_we; +assign main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine1_sink_sink_payload_addr; +assign main_litedramcore_bankmachine1_source_source_valid = main_litedramcore_bankmachine1_pipe_valid_source_valid; +assign main_litedramcore_bankmachine1_pipe_valid_source_ready = main_litedramcore_bankmachine1_source_source_ready; +assign main_litedramcore_bankmachine1_source_source_first = main_litedramcore_bankmachine1_pipe_valid_source_first; +assign main_litedramcore_bankmachine1_source_source_last = main_litedramcore_bankmachine1_pipe_valid_source_last; +assign main_litedramcore_bankmachine1_source_source_payload_we = main_litedramcore_bankmachine1_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine1_source_source_payload_addr = main_litedramcore_bankmachine1_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine1_next_state <= 4'd0; + builder_bankmachine1_next_state <= builder_bankmachine1_state; + case (builder_bankmachine1_state) + 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + if (main_litedramcore_bankmachine1_cmd_ready) begin + builder_bankmachine1_next_state <= 3'd5; end end end 2'd2: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_next_state <= 3'd5; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + builder_bankmachine1_next_state <= 3'd5; end end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - if (litedramcore_bankmachine1_cmd_ready) begin - litedramcore_bankmachine1_next_state <= 3'd7; + if (main_litedramcore_bankmachine1_trccon_ready) begin + if (main_litedramcore_bankmachine1_cmd_ready) begin + builder_bankmachine1_next_state <= 3'd7; end end end 3'd4: begin - if ((~litedramcore_bankmachine1_refresh_req)) begin - litedramcore_bankmachine1_next_state <= 1'd0; + if ((~main_litedramcore_bankmachine1_refresh_req)) begin + builder_bankmachine1_next_state <= 1'd0; end end 3'd5: begin - litedramcore_bankmachine1_next_state <= 3'd6; + builder_bankmachine1_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine1_next_state <= 2'd3; + builder_bankmachine1_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine1_next_state <= 4'd8; + builder_bankmachine1_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine1_next_state <= 1'd0; + builder_bankmachine1_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - litedramcore_bankmachine1_next_state <= 3'd4; + if (main_litedramcore_bankmachine1_refresh_req) begin + builder_bankmachine1_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin - litedramcore_bankmachine1_next_state <= 2'd2; + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if ((main_litedramcore_bankmachine1_cmd_ready & main_litedramcore_bankmachine1_auto_precharge)) begin + builder_bankmachine1_next_state <= 2'd2; end end else begin - litedramcore_bankmachine1_next_state <= 1'd1; + builder_bankmachine1_next_state <= 1'd1; end end else begin - litedramcore_bankmachine1_next_state <= 2'd3; + builder_bankmachine1_next_state <= 2'd3; end end end @@ -5459,18 +5877,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine1_twtpcon_ready) begin + main_litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -5485,13 +5903,16 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_row_open <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_row_open <= 1'd1; + end end 3'd4: begin end @@ -5504,34 +5925,22 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; end end 3'd4: begin @@ -5545,22 +5954,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_row_close <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end + main_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + main_litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -5571,41 +5992,22 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5620,8 +6022,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -5639,15 +6041,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - end else begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; - end + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -5658,13 +6057,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -5677,28 +6082,16 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine1_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -5715,13 +6108,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -5734,15 +6127,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5753,27 +6153,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - end else begin - litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -5781,9 +6166,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine1_twtpcon_ready) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -5794,20 +6176,32 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine1_row_open <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_open <= 1'd1; - end end 3'd4: begin end @@ -5820,23 +6214,32 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin + main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine1_cmd_valid <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -5849,12 +6252,15 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin + main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready; + end else begin + end end else begin end end else begin @@ -5865,18 +6271,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_row_close <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - litedramcore_bankmachine1_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -5887,142 +6290,157 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase end -assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid; -assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready; -assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we; -assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr; -assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid; -assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready; -assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first; -assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last; -assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we; -assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr; -assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); -assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid); -assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[20:7]); -assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2; -always @(*) begin - litedramcore_bankmachine2_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine2_row_col_n_addr_sel) begin - litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_source_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write); -assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); -assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); -always @(*) begin - litedramcore_bankmachine2_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin - if ((litedramcore_bankmachine2_source_payload_addr[20:7] != litedramcore_bankmachine2_source_source_payload_addr[20:7])) begin - litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we}; -assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; -assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; -assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; -assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; -assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable; -assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid; -assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first; -assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last; -assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we; -assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr; -assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable; -assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first; -assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last; -assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we; -assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr; -assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready; -always @(*) begin - litedramcore_bankmachine2_wrport_adr <= 4'd0; - if (litedramcore_bankmachine2_replace) begin - litedramcore_bankmachine2_wrport_adr <= (litedramcore_bankmachine2_produce - 1'd1); - end else begin - litedramcore_bankmachine2_wrport_adr <= litedramcore_bankmachine2_produce; - end -end -assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din; -assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace)); -assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re); -assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume; -assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r; -assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 5'd16); -assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0); -assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready); -assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid; -assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready; -assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first; -assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last; -assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we; -assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr; -assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid; -assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready; -assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first; -assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last; -assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we; -assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine2_next_state <= 4'd0; - litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - if (litedramcore_bankmachine2_cmd_ready) begin - litedramcore_bankmachine2_next_state <= 3'd5; +assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid; +assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready; +assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we; +assign main_litedramcore_bankmachine2_sink_payload_addr = main_litedramcore_bankmachine2_req_addr; +assign main_litedramcore_bankmachine2_sink_sink_valid = main_litedramcore_bankmachine2_source_valid; +assign main_litedramcore_bankmachine2_source_ready = main_litedramcore_bankmachine2_sink_sink_ready; +assign main_litedramcore_bankmachine2_sink_sink_first = main_litedramcore_bankmachine2_source_first; +assign main_litedramcore_bankmachine2_sink_sink_last = main_litedramcore_bankmachine2_source_last; +assign main_litedramcore_bankmachine2_sink_sink_payload_we = main_litedramcore_bankmachine2_source_payload_we; +assign main_litedramcore_bankmachine2_sink_sink_payload_addr = main_litedramcore_bankmachine2_source_payload_addr; +assign main_litedramcore_bankmachine2_source_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid); +assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_source_valid | main_litedramcore_bankmachine2_source_source_valid); +assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_source_source_payload_addr[20:7]); +assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; +always @(*) begin + main_litedramcore_bankmachine2_cmd_payload_a <= 14'd0; + if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin + main_litedramcore_bankmachine2_cmd_payload_a <= main_litedramcore_bankmachine2_source_source_payload_addr[20:7]; + end else begin + main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write); +assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); +assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); +always @(*) begin + main_litedramcore_bankmachine2_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine2_source_valid & main_litedramcore_bankmachine2_source_source_valid)) begin + if ((main_litedramcore_bankmachine2_source_payload_addr[20:7] != main_litedramcore_bankmachine2_source_source_payload_addr[20:7])) begin + main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine2_syncfifo2_din = {main_litedramcore_bankmachine2_fifo_in_last, main_litedramcore_bankmachine2_fifo_in_first, main_litedramcore_bankmachine2_fifo_in_payload_addr, main_litedramcore_bankmachine2_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; +assign main_litedramcore_bankmachine2_sink_ready = main_litedramcore_bankmachine2_syncfifo2_writable; +assign main_litedramcore_bankmachine2_syncfifo2_we = main_litedramcore_bankmachine2_sink_valid; +assign main_litedramcore_bankmachine2_fifo_in_first = main_litedramcore_bankmachine2_sink_first; +assign main_litedramcore_bankmachine2_fifo_in_last = main_litedramcore_bankmachine2_sink_last; +assign main_litedramcore_bankmachine2_fifo_in_payload_we = main_litedramcore_bankmachine2_sink_payload_we; +assign main_litedramcore_bankmachine2_fifo_in_payload_addr = main_litedramcore_bankmachine2_sink_payload_addr; +assign main_litedramcore_bankmachine2_source_valid = main_litedramcore_bankmachine2_syncfifo2_readable; +assign main_litedramcore_bankmachine2_source_first = main_litedramcore_bankmachine2_fifo_out_first; +assign main_litedramcore_bankmachine2_source_last = main_litedramcore_bankmachine2_fifo_out_last; +assign main_litedramcore_bankmachine2_source_payload_we = main_litedramcore_bankmachine2_fifo_out_payload_we; +assign main_litedramcore_bankmachine2_source_payload_addr = main_litedramcore_bankmachine2_fifo_out_payload_addr; +assign main_litedramcore_bankmachine2_syncfifo2_re = main_litedramcore_bankmachine2_source_ready; +always @(*) begin + main_litedramcore_bankmachine2_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine2_replace) begin + main_litedramcore_bankmachine2_wrport_adr <= (main_litedramcore_bankmachine2_produce - 1'd1); + end else begin + main_litedramcore_bankmachine2_wrport_adr <= main_litedramcore_bankmachine2_produce; + end +end +assign main_litedramcore_bankmachine2_wrport_dat_w = main_litedramcore_bankmachine2_syncfifo2_din; +assign main_litedramcore_bankmachine2_wrport_we = (main_litedramcore_bankmachine2_syncfifo2_we & (main_litedramcore_bankmachine2_syncfifo2_writable | main_litedramcore_bankmachine2_replace)); +assign main_litedramcore_bankmachine2_do_read = (main_litedramcore_bankmachine2_syncfifo2_readable & main_litedramcore_bankmachine2_syncfifo2_re); +assign main_litedramcore_bankmachine2_rdport_adr = main_litedramcore_bankmachine2_consume; +assign main_litedramcore_bankmachine2_syncfifo2_dout = main_litedramcore_bankmachine2_rdport_dat_r; +assign main_litedramcore_bankmachine2_syncfifo2_writable = (main_litedramcore_bankmachine2_level != 5'd16); +assign main_litedramcore_bankmachine2_syncfifo2_readable = (main_litedramcore_bankmachine2_level != 1'd0); +assign main_litedramcore_bankmachine2_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine2_pipe_valid_source_valid) | main_litedramcore_bankmachine2_pipe_valid_source_ready); +assign main_litedramcore_bankmachine2_pipe_valid_sink_valid = main_litedramcore_bankmachine2_sink_sink_valid; +assign main_litedramcore_bankmachine2_sink_sink_ready = main_litedramcore_bankmachine2_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine2_pipe_valid_sink_first = main_litedramcore_bankmachine2_sink_sink_first; +assign main_litedramcore_bankmachine2_pipe_valid_sink_last = main_litedramcore_bankmachine2_sink_sink_last; +assign main_litedramcore_bankmachine2_pipe_valid_sink_payload_we = main_litedramcore_bankmachine2_sink_sink_payload_we; +assign main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine2_sink_sink_payload_addr; +assign main_litedramcore_bankmachine2_source_source_valid = main_litedramcore_bankmachine2_pipe_valid_source_valid; +assign main_litedramcore_bankmachine2_pipe_valid_source_ready = main_litedramcore_bankmachine2_source_source_ready; +assign main_litedramcore_bankmachine2_source_source_first = main_litedramcore_bankmachine2_pipe_valid_source_first; +assign main_litedramcore_bankmachine2_source_source_last = main_litedramcore_bankmachine2_pipe_valid_source_last; +assign main_litedramcore_bankmachine2_source_source_payload_we = main_litedramcore_bankmachine2_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine2_source_source_payload_addr = main_litedramcore_bankmachine2_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine2_next_state <= 4'd0; + builder_bankmachine2_next_state <= builder_bankmachine2_state; + case (builder_bankmachine2_state) + 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + if (main_litedramcore_bankmachine2_cmd_ready) begin + builder_bankmachine2_next_state <= 3'd5; end end end 2'd2: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_next_state <= 3'd5; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + builder_bankmachine2_next_state <= 3'd5; end end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - if (litedramcore_bankmachine2_cmd_ready) begin - litedramcore_bankmachine2_next_state <= 3'd7; + if (main_litedramcore_bankmachine2_trccon_ready) begin + if (main_litedramcore_bankmachine2_cmd_ready) begin + builder_bankmachine2_next_state <= 3'd7; end end end 3'd4: begin - if ((~litedramcore_bankmachine2_refresh_req)) begin - litedramcore_bankmachine2_next_state <= 1'd0; + if ((~main_litedramcore_bankmachine2_refresh_req)) begin + builder_bankmachine2_next_state <= 1'd0; end end 3'd5: begin - litedramcore_bankmachine2_next_state <= 3'd6; + builder_bankmachine2_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine2_next_state <= 2'd3; + builder_bankmachine2_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine2_next_state <= 4'd8; + builder_bankmachine2_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine2_next_state <= 1'd0; + builder_bankmachine2_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - litedramcore_bankmachine2_next_state <= 3'd4; + if (main_litedramcore_bankmachine2_refresh_req) begin + builder_bankmachine2_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin - litedramcore_bankmachine2_next_state <= 2'd2; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if ((main_litedramcore_bankmachine2_cmd_ready & main_litedramcore_bankmachine2_auto_precharge)) begin + builder_bankmachine2_next_state <= 2'd2; end end else begin - litedramcore_bankmachine2_next_state <= 1'd1; + builder_bankmachine2_next_state <= 1'd1; end end else begin - litedramcore_bankmachine2_next_state <= 2'd3; + builder_bankmachine2_next_state <= 2'd3; end end end @@ -6030,8 +6448,34 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6049,12 +6493,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -6065,18 +6509,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -6094,11 +6538,11 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -6116,13 +6560,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -6135,22 +6579,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6165,8 +6609,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6184,14 +6628,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin end else begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6203,8 +6647,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6222,13 +6666,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin + main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -6241,8 +6685,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6260,13 +6704,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin - litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin + main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready; end else begin end end else begin @@ -6279,8 +6723,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6298,14 +6742,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin end else begin - litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; + main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready; end end else begin end @@ -6317,8 +6761,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6326,8 +6770,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine2_twtpcon_ready) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd1; + if (main_litedramcore_bankmachine2_twtpcon_ready) begin + main_litedramcore_bankmachine2_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -6343,15 +6787,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_row_open <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_row_open <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_row_open <= 1'd1; end end 3'd4: begin @@ -6369,18 +6813,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_valid <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_valid <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; end end 3'd4: begin @@ -6394,12 +6838,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; end else begin end end else begin @@ -6410,18 +6854,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_row_close <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_row_close <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - litedramcore_bankmachine2_row_close <= 1'd1; + main_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine2_row_close <= 1'd1; + main_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine2_row_close <= 1'd1; + main_litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -6435,165 +6879,209 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine2_state) +assign main_litedramcore_bankmachine3_sink_valid = main_litedramcore_bankmachine3_req_valid; +assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_sink_ready; +assign main_litedramcore_bankmachine3_sink_payload_we = main_litedramcore_bankmachine3_req_we; +assign main_litedramcore_bankmachine3_sink_payload_addr = main_litedramcore_bankmachine3_req_addr; +assign main_litedramcore_bankmachine3_sink_sink_valid = main_litedramcore_bankmachine3_source_valid; +assign main_litedramcore_bankmachine3_source_ready = main_litedramcore_bankmachine3_sink_sink_ready; +assign main_litedramcore_bankmachine3_sink_sink_first = main_litedramcore_bankmachine3_source_first; +assign main_litedramcore_bankmachine3_sink_sink_last = main_litedramcore_bankmachine3_source_last; +assign main_litedramcore_bankmachine3_sink_sink_payload_we = main_litedramcore_bankmachine3_source_payload_we; +assign main_litedramcore_bankmachine3_sink_sink_payload_addr = main_litedramcore_bankmachine3_source_payload_addr; +assign main_litedramcore_bankmachine3_source_source_ready = (main_litedramcore_bankmachine3_req_wdata_ready | main_litedramcore_bankmachine3_req_rdata_valid); +assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_source_valid | main_litedramcore_bankmachine3_source_source_valid); +assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_source_source_payload_addr[20:7]); +assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; +always @(*) begin + main_litedramcore_bankmachine3_cmd_payload_a <= 14'd0; + if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin + main_litedramcore_bankmachine3_cmd_payload_a <= main_litedramcore_bankmachine3_source_source_payload_addr[20:7]; + end else begin + main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write); +assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); +assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); +always @(*) begin + main_litedramcore_bankmachine3_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine3_source_valid & main_litedramcore_bankmachine3_source_source_valid)) begin + if ((main_litedramcore_bankmachine3_source_payload_addr[20:7] != main_litedramcore_bankmachine3_source_source_payload_addr[20:7])) begin + main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine3_syncfifo3_din = {main_litedramcore_bankmachine3_fifo_in_last, main_litedramcore_bankmachine3_fifo_in_first, main_litedramcore_bankmachine3_fifo_in_payload_addr, main_litedramcore_bankmachine3_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout; +assign main_litedramcore_bankmachine3_sink_ready = main_litedramcore_bankmachine3_syncfifo3_writable; +assign main_litedramcore_bankmachine3_syncfifo3_we = main_litedramcore_bankmachine3_sink_valid; +assign main_litedramcore_bankmachine3_fifo_in_first = main_litedramcore_bankmachine3_sink_first; +assign main_litedramcore_bankmachine3_fifo_in_last = main_litedramcore_bankmachine3_sink_last; +assign main_litedramcore_bankmachine3_fifo_in_payload_we = main_litedramcore_bankmachine3_sink_payload_we; +assign main_litedramcore_bankmachine3_fifo_in_payload_addr = main_litedramcore_bankmachine3_sink_payload_addr; +assign main_litedramcore_bankmachine3_source_valid = main_litedramcore_bankmachine3_syncfifo3_readable; +assign main_litedramcore_bankmachine3_source_first = main_litedramcore_bankmachine3_fifo_out_first; +assign main_litedramcore_bankmachine3_source_last = main_litedramcore_bankmachine3_fifo_out_last; +assign main_litedramcore_bankmachine3_source_payload_we = main_litedramcore_bankmachine3_fifo_out_payload_we; +assign main_litedramcore_bankmachine3_source_payload_addr = main_litedramcore_bankmachine3_fifo_out_payload_addr; +assign main_litedramcore_bankmachine3_syncfifo3_re = main_litedramcore_bankmachine3_source_ready; +always @(*) begin + main_litedramcore_bankmachine3_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine3_replace) begin + main_litedramcore_bankmachine3_wrport_adr <= (main_litedramcore_bankmachine3_produce - 1'd1); + end else begin + main_litedramcore_bankmachine3_wrport_adr <= main_litedramcore_bankmachine3_produce; + end +end +assign main_litedramcore_bankmachine3_wrport_dat_w = main_litedramcore_bankmachine3_syncfifo3_din; +assign main_litedramcore_bankmachine3_wrport_we = (main_litedramcore_bankmachine3_syncfifo3_we & (main_litedramcore_bankmachine3_syncfifo3_writable | main_litedramcore_bankmachine3_replace)); +assign main_litedramcore_bankmachine3_do_read = (main_litedramcore_bankmachine3_syncfifo3_readable & main_litedramcore_bankmachine3_syncfifo3_re); +assign main_litedramcore_bankmachine3_rdport_adr = main_litedramcore_bankmachine3_consume; +assign main_litedramcore_bankmachine3_syncfifo3_dout = main_litedramcore_bankmachine3_rdport_dat_r; +assign main_litedramcore_bankmachine3_syncfifo3_writable = (main_litedramcore_bankmachine3_level != 5'd16); +assign main_litedramcore_bankmachine3_syncfifo3_readable = (main_litedramcore_bankmachine3_level != 1'd0); +assign main_litedramcore_bankmachine3_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine3_pipe_valid_source_valid) | main_litedramcore_bankmachine3_pipe_valid_source_ready); +assign main_litedramcore_bankmachine3_pipe_valid_sink_valid = main_litedramcore_bankmachine3_sink_sink_valid; +assign main_litedramcore_bankmachine3_sink_sink_ready = main_litedramcore_bankmachine3_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine3_pipe_valid_sink_first = main_litedramcore_bankmachine3_sink_sink_first; +assign main_litedramcore_bankmachine3_pipe_valid_sink_last = main_litedramcore_bankmachine3_sink_sink_last; +assign main_litedramcore_bankmachine3_pipe_valid_sink_payload_we = main_litedramcore_bankmachine3_sink_sink_payload_we; +assign main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine3_sink_sink_payload_addr; +assign main_litedramcore_bankmachine3_source_source_valid = main_litedramcore_bankmachine3_pipe_valid_source_valid; +assign main_litedramcore_bankmachine3_pipe_valid_source_ready = main_litedramcore_bankmachine3_source_source_ready; +assign main_litedramcore_bankmachine3_source_source_first = main_litedramcore_bankmachine3_pipe_valid_source_first; +assign main_litedramcore_bankmachine3_source_source_last = main_litedramcore_bankmachine3_pipe_valid_source_last; +assign main_litedramcore_bankmachine3_source_source_payload_we = main_litedramcore_bankmachine3_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine3_source_source_payload_addr = main_litedramcore_bankmachine3_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine3_next_state <= 4'd0; + builder_bankmachine3_next_state <= builder_bankmachine3_state; + case (builder_bankmachine3_state) 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + if (main_litedramcore_bankmachine3_cmd_ready) begin + builder_bankmachine3_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + builder_bankmachine3_next_state <= 3'd5; + end end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + if (main_litedramcore_bankmachine3_cmd_ready) begin + builder_bankmachine3_next_state <= 3'd7; + end end end 3'd4: begin + if ((~main_litedramcore_bankmachine3_refresh_req)) begin + builder_bankmachine3_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine3_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine3_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine3_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine3_next_state <= 1'd0; end default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + builder_bankmachine3_next_state <= 3'd4; + end else begin + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin + builder_bankmachine3_next_state <= 2'd2; + end + end else begin + builder_bankmachine3_next_state <= 1'd1; + end + end else begin + builder_bankmachine3_next_state <= 2'd3; + end + end + end end endcase end -assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid; -assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready; -assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we; -assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr; -assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid; -assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready; -assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first; -assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last; -assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we; -assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr; -assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); -assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid); -assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[20:7]); -assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3; -always @(*) begin - litedramcore_bankmachine3_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine3_row_col_n_addr_sel) begin - litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_source_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write); -assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); -assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); -always @(*) begin - litedramcore_bankmachine3_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin - if ((litedramcore_bankmachine3_source_payload_addr[20:7] != litedramcore_bankmachine3_source_source_payload_addr[20:7])) begin - litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we}; -assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; -assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; -assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; -assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; -assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable; -assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid; -assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first; -assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last; -assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we; -assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr; -assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable; -assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first; -assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last; -assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we; -assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr; -assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready; -always @(*) begin - litedramcore_bankmachine3_wrport_adr <= 4'd0; - if (litedramcore_bankmachine3_replace) begin - litedramcore_bankmachine3_wrport_adr <= (litedramcore_bankmachine3_produce - 1'd1); - end else begin - litedramcore_bankmachine3_wrport_adr <= litedramcore_bankmachine3_produce; - end -end -assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din; -assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace)); -assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re); -assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume; -assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r; -assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 5'd16); -assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0); -assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready); -assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid; -assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready; -assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first; -assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last; -assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we; -assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr; -assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid; -assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready; -assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first; -assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last; -assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we; -assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine3_next_state <= 4'd0; - litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - if (litedramcore_bankmachine3_cmd_ready) begin - litedramcore_bankmachine3_next_state <= 3'd5; - end +always @(*) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (builder_bankmachine3_state) + 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; end end 2'd2: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - if (litedramcore_bankmachine3_cmd_ready) begin - litedramcore_bankmachine3_next_state <= 3'd7; - end + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; end end 3'd4: begin - if ((~litedramcore_bankmachine3_refresh_req)) begin - litedramcore_bankmachine3_next_state <= 1'd0; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (builder_bankmachine3_state) + 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; end end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end 3'd5: begin - litedramcore_bankmachine3_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine3_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine3_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine3_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - litedramcore_bankmachine3_next_state <= 3'd4; + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin - litedramcore_bankmachine3_next_state <= 2'd2; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end else begin end end else begin - litedramcore_bankmachine3_next_state <= 1'd1; end end else begin - litedramcore_bankmachine3_next_state <= 2'd3; end end end @@ -6601,22 +7089,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6631,8 +7119,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -6650,14 +7138,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin end else begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6669,8 +7157,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -6688,13 +7176,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin + main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -6707,8 +7195,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -6726,13 +7214,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin - litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin + main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready; end else begin end end else begin @@ -6745,8 +7233,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -6764,14 +7252,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin end else begin - litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; + main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready; end end else begin end @@ -6783,8 +7271,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -6792,8 +7280,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine3_twtpcon_ready) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd1; + if (main_litedramcore_bankmachine3_twtpcon_ready) begin + main_litedramcore_bankmachine3_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -6809,15 +7297,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_row_open <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_row_open <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_open <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_open <= 1'd1; end end 3'd4: begin @@ -6835,18 +7323,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_valid <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; end end 3'd4: begin @@ -6860,12 +7348,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; end else begin end end else begin @@ -6876,18 +7364,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_row_close <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_row_close <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - litedramcore_bankmachine3_row_close <= 1'd1; + main_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine3_row_close <= 1'd1; + main_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine3_row_close <= 1'd1; + main_litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -6902,15 +7390,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -6928,8 +7416,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -6947,12 +7435,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -6962,42 +7450,149 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine3_state) +assign main_litedramcore_bankmachine4_sink_valid = main_litedramcore_bankmachine4_req_valid; +assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_sink_ready; +assign main_litedramcore_bankmachine4_sink_payload_we = main_litedramcore_bankmachine4_req_we; +assign main_litedramcore_bankmachine4_sink_payload_addr = main_litedramcore_bankmachine4_req_addr; +assign main_litedramcore_bankmachine4_sink_sink_valid = main_litedramcore_bankmachine4_source_valid; +assign main_litedramcore_bankmachine4_source_ready = main_litedramcore_bankmachine4_sink_sink_ready; +assign main_litedramcore_bankmachine4_sink_sink_first = main_litedramcore_bankmachine4_source_first; +assign main_litedramcore_bankmachine4_sink_sink_last = main_litedramcore_bankmachine4_source_last; +assign main_litedramcore_bankmachine4_sink_sink_payload_we = main_litedramcore_bankmachine4_source_payload_we; +assign main_litedramcore_bankmachine4_sink_sink_payload_addr = main_litedramcore_bankmachine4_source_payload_addr; +assign main_litedramcore_bankmachine4_source_source_ready = (main_litedramcore_bankmachine4_req_wdata_ready | main_litedramcore_bankmachine4_req_rdata_valid); +assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_source_valid | main_litedramcore_bankmachine4_source_source_valid); +assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_source_source_payload_addr[20:7]); +assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; +always @(*) begin + main_litedramcore_bankmachine4_cmd_payload_a <= 14'd0; + if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin + main_litedramcore_bankmachine4_cmd_payload_a <= main_litedramcore_bankmachine4_source_source_payload_addr[20:7]; + end else begin + main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write); +assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); +assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); +always @(*) begin + main_litedramcore_bankmachine4_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine4_source_valid & main_litedramcore_bankmachine4_source_source_valid)) begin + if ((main_litedramcore_bankmachine4_source_payload_addr[20:7] != main_litedramcore_bankmachine4_source_source_payload_addr[20:7])) begin + main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine4_syncfifo4_din = {main_litedramcore_bankmachine4_fifo_in_last, main_litedramcore_bankmachine4_fifo_in_first, main_litedramcore_bankmachine4_fifo_in_payload_addr, main_litedramcore_bankmachine4_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout; +assign main_litedramcore_bankmachine4_sink_ready = main_litedramcore_bankmachine4_syncfifo4_writable; +assign main_litedramcore_bankmachine4_syncfifo4_we = main_litedramcore_bankmachine4_sink_valid; +assign main_litedramcore_bankmachine4_fifo_in_first = main_litedramcore_bankmachine4_sink_first; +assign main_litedramcore_bankmachine4_fifo_in_last = main_litedramcore_bankmachine4_sink_last; +assign main_litedramcore_bankmachine4_fifo_in_payload_we = main_litedramcore_bankmachine4_sink_payload_we; +assign main_litedramcore_bankmachine4_fifo_in_payload_addr = main_litedramcore_bankmachine4_sink_payload_addr; +assign main_litedramcore_bankmachine4_source_valid = main_litedramcore_bankmachine4_syncfifo4_readable; +assign main_litedramcore_bankmachine4_source_first = main_litedramcore_bankmachine4_fifo_out_first; +assign main_litedramcore_bankmachine4_source_last = main_litedramcore_bankmachine4_fifo_out_last; +assign main_litedramcore_bankmachine4_source_payload_we = main_litedramcore_bankmachine4_fifo_out_payload_we; +assign main_litedramcore_bankmachine4_source_payload_addr = main_litedramcore_bankmachine4_fifo_out_payload_addr; +assign main_litedramcore_bankmachine4_syncfifo4_re = main_litedramcore_bankmachine4_source_ready; +always @(*) begin + main_litedramcore_bankmachine4_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine4_replace) begin + main_litedramcore_bankmachine4_wrport_adr <= (main_litedramcore_bankmachine4_produce - 1'd1); + end else begin + main_litedramcore_bankmachine4_wrport_adr <= main_litedramcore_bankmachine4_produce; + end +end +assign main_litedramcore_bankmachine4_wrport_dat_w = main_litedramcore_bankmachine4_syncfifo4_din; +assign main_litedramcore_bankmachine4_wrport_we = (main_litedramcore_bankmachine4_syncfifo4_we & (main_litedramcore_bankmachine4_syncfifo4_writable | main_litedramcore_bankmachine4_replace)); +assign main_litedramcore_bankmachine4_do_read = (main_litedramcore_bankmachine4_syncfifo4_readable & main_litedramcore_bankmachine4_syncfifo4_re); +assign main_litedramcore_bankmachine4_rdport_adr = main_litedramcore_bankmachine4_consume; +assign main_litedramcore_bankmachine4_syncfifo4_dout = main_litedramcore_bankmachine4_rdport_dat_r; +assign main_litedramcore_bankmachine4_syncfifo4_writable = (main_litedramcore_bankmachine4_level != 5'd16); +assign main_litedramcore_bankmachine4_syncfifo4_readable = (main_litedramcore_bankmachine4_level != 1'd0); +assign main_litedramcore_bankmachine4_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine4_pipe_valid_source_valid) | main_litedramcore_bankmachine4_pipe_valid_source_ready); +assign main_litedramcore_bankmachine4_pipe_valid_sink_valid = main_litedramcore_bankmachine4_sink_sink_valid; +assign main_litedramcore_bankmachine4_sink_sink_ready = main_litedramcore_bankmachine4_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine4_pipe_valid_sink_first = main_litedramcore_bankmachine4_sink_sink_first; +assign main_litedramcore_bankmachine4_pipe_valid_sink_last = main_litedramcore_bankmachine4_sink_sink_last; +assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_we = main_litedramcore_bankmachine4_sink_sink_payload_we; +assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine4_sink_sink_payload_addr; +assign main_litedramcore_bankmachine4_source_source_valid = main_litedramcore_bankmachine4_pipe_valid_source_valid; +assign main_litedramcore_bankmachine4_pipe_valid_source_ready = main_litedramcore_bankmachine4_source_source_ready; +assign main_litedramcore_bankmachine4_source_source_first = main_litedramcore_bankmachine4_pipe_valid_source_first; +assign main_litedramcore_bankmachine4_source_source_last = main_litedramcore_bankmachine4_pipe_valid_source_last; +assign main_litedramcore_bankmachine4_source_source_payload_we = main_litedramcore_bankmachine4_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine4_source_source_payload_addr = main_litedramcore_bankmachine4_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine4_next_state <= 4'd0; + builder_bankmachine4_next_state <= builder_bankmachine4_state; + case (builder_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + if (main_litedramcore_bankmachine4_cmd_ready) begin + builder_bankmachine4_next_state <= 3'd5; + end end end 2'd2: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + builder_bankmachine4_next_state <= 3'd5; + end end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + if (main_litedramcore_bankmachine4_cmd_ready) begin + builder_bankmachine4_next_state <= 3'd7; + end end end 3'd4: begin + if ((~main_litedramcore_bankmachine4_refresh_req)) begin + builder_bankmachine4_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine4_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine4_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine4_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine4_next_state <= 1'd0; end default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + builder_bankmachine4_next_state <= 3'd4; + end else begin + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if ((main_litedramcore_bankmachine4_cmd_ready & main_litedramcore_bankmachine4_auto_precharge)) begin + builder_bankmachine4_next_state <= 2'd2; + end + end else begin + builder_bankmachine4_next_state <= 1'd1; + end + end else begin + builder_bankmachine4_next_state <= 2'd3; + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -7014,13 +7609,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin + main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -7032,139 +7627,38 @@ always @(*) begin end endcase end -assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid; -assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready; -assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we; -assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr; -assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid; -assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready; -assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first; -assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last; -assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we; -assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr; -assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); -assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid); -assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[20:7]); -assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4; -always @(*) begin - litedramcore_bankmachine4_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine4_row_col_n_addr_sel) begin - litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_source_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write); -assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); -assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); -always @(*) begin - litedramcore_bankmachine4_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin - if ((litedramcore_bankmachine4_source_payload_addr[20:7] != litedramcore_bankmachine4_source_source_payload_addr[20:7])) begin - litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we}; -assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; -assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; -assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; -assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; -assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable; -assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid; -assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first; -assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last; -assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we; -assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr; -assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable; -assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first; -assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last; -assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we; -assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr; -assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready; -always @(*) begin - litedramcore_bankmachine4_wrport_adr <= 4'd0; - if (litedramcore_bankmachine4_replace) begin - litedramcore_bankmachine4_wrport_adr <= (litedramcore_bankmachine4_produce - 1'd1); - end else begin - litedramcore_bankmachine4_wrport_adr <= litedramcore_bankmachine4_produce; - end -end -assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din; -assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace)); -assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re); -assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume; -assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r; -assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 5'd16); -assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0); -assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready); -assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid; -assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready; -assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first; -assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last; -assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we; -assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr; -assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid; -assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready; -assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first; -assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last; -assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we; -assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine4_next_state <= 4'd0; - litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - if (litedramcore_bankmachine4_cmd_ready) begin - litedramcore_bankmachine4_next_state <= 3'd5; - end - end +always @(*) begin + main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (builder_bankmachine4_state) + 1'd1: begin end 2'd2: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - if (litedramcore_bankmachine4_cmd_ready) begin - litedramcore_bankmachine4_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~litedramcore_bankmachine4_refresh_req)) begin - litedramcore_bankmachine4_next_state <= 1'd0; - end end 3'd5: begin - litedramcore_bankmachine4_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine4_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine4_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine4_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - litedramcore_bankmachine4_next_state <= 3'd4; + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin - litedramcore_bankmachine4_next_state <= 2'd2; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin + main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready; + end else begin end end else begin - litedramcore_bankmachine4_next_state <= 1'd1; end end else begin - litedramcore_bankmachine4_next_state <= 2'd3; end end end @@ -7172,8 +7666,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7191,14 +7685,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin end else begin - litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; + main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready; end end else begin end @@ -7210,8 +7704,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7219,8 +7713,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine4_twtpcon_ready) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd1; + if (main_litedramcore_bankmachine4_twtpcon_ready) begin + main_litedramcore_bankmachine4_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -7236,15 +7730,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_row_open <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_row_open <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_open <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_row_open <= 1'd1; end end 3'd4: begin @@ -7262,18 +7756,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_valid <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_valid <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; end end 3'd4: begin @@ -7287,12 +7781,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; end else begin end end else begin @@ -7303,18 +7797,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_row_close <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_row_close <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - litedramcore_bankmachine4_row_close <= 1'd1; + main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine4_row_close <= 1'd1; + main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine4_row_close <= 1'd1; + main_litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -7329,15 +7823,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -7355,8 +7849,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7374,12 +7868,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -7390,18 +7884,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -7419,11 +7913,11 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -7441,13 +7935,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -7460,22 +7954,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7490,8 +7984,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7509,14 +8003,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin end else begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; end end else begin end @@ -7527,38 +8021,139 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine4_state) +assign main_litedramcore_bankmachine5_sink_valid = main_litedramcore_bankmachine5_req_valid; +assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_sink_ready; +assign main_litedramcore_bankmachine5_sink_payload_we = main_litedramcore_bankmachine5_req_we; +assign main_litedramcore_bankmachine5_sink_payload_addr = main_litedramcore_bankmachine5_req_addr; +assign main_litedramcore_bankmachine5_sink_sink_valid = main_litedramcore_bankmachine5_source_valid; +assign main_litedramcore_bankmachine5_source_ready = main_litedramcore_bankmachine5_sink_sink_ready; +assign main_litedramcore_bankmachine5_sink_sink_first = main_litedramcore_bankmachine5_source_first; +assign main_litedramcore_bankmachine5_sink_sink_last = main_litedramcore_bankmachine5_source_last; +assign main_litedramcore_bankmachine5_sink_sink_payload_we = main_litedramcore_bankmachine5_source_payload_we; +assign main_litedramcore_bankmachine5_sink_sink_payload_addr = main_litedramcore_bankmachine5_source_payload_addr; +assign main_litedramcore_bankmachine5_source_source_ready = (main_litedramcore_bankmachine5_req_wdata_ready | main_litedramcore_bankmachine5_req_rdata_valid); +assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_source_valid | main_litedramcore_bankmachine5_source_source_valid); +assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_source_source_payload_addr[20:7]); +assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5; +always @(*) begin + main_litedramcore_bankmachine5_cmd_payload_a <= 14'd0; + if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin + main_litedramcore_bankmachine5_cmd_payload_a <= main_litedramcore_bankmachine5_source_source_payload_addr[20:7]; + end else begin + main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write); +assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); +assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); +always @(*) begin + main_litedramcore_bankmachine5_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine5_source_valid & main_litedramcore_bankmachine5_source_source_valid)) begin + if ((main_litedramcore_bankmachine5_source_payload_addr[20:7] != main_litedramcore_bankmachine5_source_source_payload_addr[20:7])) begin + main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine5_syncfifo5_din = {main_litedramcore_bankmachine5_fifo_in_last, main_litedramcore_bankmachine5_fifo_in_first, main_litedramcore_bankmachine5_fifo_in_payload_addr, main_litedramcore_bankmachine5_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout; +assign main_litedramcore_bankmachine5_sink_ready = main_litedramcore_bankmachine5_syncfifo5_writable; +assign main_litedramcore_bankmachine5_syncfifo5_we = main_litedramcore_bankmachine5_sink_valid; +assign main_litedramcore_bankmachine5_fifo_in_first = main_litedramcore_bankmachine5_sink_first; +assign main_litedramcore_bankmachine5_fifo_in_last = main_litedramcore_bankmachine5_sink_last; +assign main_litedramcore_bankmachine5_fifo_in_payload_we = main_litedramcore_bankmachine5_sink_payload_we; +assign main_litedramcore_bankmachine5_fifo_in_payload_addr = main_litedramcore_bankmachine5_sink_payload_addr; +assign main_litedramcore_bankmachine5_source_valid = main_litedramcore_bankmachine5_syncfifo5_readable; +assign main_litedramcore_bankmachine5_source_first = main_litedramcore_bankmachine5_fifo_out_first; +assign main_litedramcore_bankmachine5_source_last = main_litedramcore_bankmachine5_fifo_out_last; +assign main_litedramcore_bankmachine5_source_payload_we = main_litedramcore_bankmachine5_fifo_out_payload_we; +assign main_litedramcore_bankmachine5_source_payload_addr = main_litedramcore_bankmachine5_fifo_out_payload_addr; +assign main_litedramcore_bankmachine5_syncfifo5_re = main_litedramcore_bankmachine5_source_ready; +always @(*) begin + main_litedramcore_bankmachine5_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine5_replace) begin + main_litedramcore_bankmachine5_wrport_adr <= (main_litedramcore_bankmachine5_produce - 1'd1); + end else begin + main_litedramcore_bankmachine5_wrport_adr <= main_litedramcore_bankmachine5_produce; + end +end +assign main_litedramcore_bankmachine5_wrport_dat_w = main_litedramcore_bankmachine5_syncfifo5_din; +assign main_litedramcore_bankmachine5_wrport_we = (main_litedramcore_bankmachine5_syncfifo5_we & (main_litedramcore_bankmachine5_syncfifo5_writable | main_litedramcore_bankmachine5_replace)); +assign main_litedramcore_bankmachine5_do_read = (main_litedramcore_bankmachine5_syncfifo5_readable & main_litedramcore_bankmachine5_syncfifo5_re); +assign main_litedramcore_bankmachine5_rdport_adr = main_litedramcore_bankmachine5_consume; +assign main_litedramcore_bankmachine5_syncfifo5_dout = main_litedramcore_bankmachine5_rdport_dat_r; +assign main_litedramcore_bankmachine5_syncfifo5_writable = (main_litedramcore_bankmachine5_level != 5'd16); +assign main_litedramcore_bankmachine5_syncfifo5_readable = (main_litedramcore_bankmachine5_level != 1'd0); +assign main_litedramcore_bankmachine5_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine5_pipe_valid_source_valid) | main_litedramcore_bankmachine5_pipe_valid_source_ready); +assign main_litedramcore_bankmachine5_pipe_valid_sink_valid = main_litedramcore_bankmachine5_sink_sink_valid; +assign main_litedramcore_bankmachine5_sink_sink_ready = main_litedramcore_bankmachine5_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine5_pipe_valid_sink_first = main_litedramcore_bankmachine5_sink_sink_first; +assign main_litedramcore_bankmachine5_pipe_valid_sink_last = main_litedramcore_bankmachine5_sink_sink_last; +assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_we = main_litedramcore_bankmachine5_sink_sink_payload_we; +assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine5_sink_sink_payload_addr; +assign main_litedramcore_bankmachine5_source_source_valid = main_litedramcore_bankmachine5_pipe_valid_source_valid; +assign main_litedramcore_bankmachine5_pipe_valid_source_ready = main_litedramcore_bankmachine5_source_source_ready; +assign main_litedramcore_bankmachine5_source_source_first = main_litedramcore_bankmachine5_pipe_valid_source_first; +assign main_litedramcore_bankmachine5_source_source_last = main_litedramcore_bankmachine5_pipe_valid_source_last; +assign main_litedramcore_bankmachine5_source_source_payload_we = main_litedramcore_bankmachine5_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine5_source_source_payload_addr = main_litedramcore_bankmachine5_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine5_next_state <= 4'd0; + builder_bankmachine5_next_state <= builder_bankmachine5_state; + case (builder_bankmachine5_state) 1'd1: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + if (main_litedramcore_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + builder_bankmachine5_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + if (main_litedramcore_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine5_refresh_req)) begin + builder_bankmachine5_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine5_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine5_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine5_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine5_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin + builder_bankmachine5_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; - end else begin + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin + builder_bankmachine5_next_state <= 2'd2; end end else begin + builder_bankmachine5_next_state <= 1'd1; end end else begin + builder_bankmachine5_next_state <= 2'd3; end end end @@ -7566,8 +8161,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -7575,6 +8170,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine5_twtpcon_ready) begin + main_litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -7585,157 +8183,70 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin - litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine5_row_open <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_row_open <= 1'd1; end end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end endcase end -assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid; -assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready; -assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we; -assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr; -assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid; -assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready; -assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first; -assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last; -assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we; -assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr; -assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); -assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid); -assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[20:7]); -assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5; -always @(*) begin - litedramcore_bankmachine5_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine5_row_col_n_addr_sel) begin - litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_source_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write); -assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); -assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); -always @(*) begin - litedramcore_bankmachine5_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin - if ((litedramcore_bankmachine5_source_payload_addr[20:7] != litedramcore_bankmachine5_source_source_payload_addr[20:7])) begin - litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we}; -assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; -assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; -assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; -assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; -assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable; -assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid; -assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first; -assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last; -assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we; -assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr; -assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable; -assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first; -assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last; -assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we; -assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr; -assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready; -always @(*) begin - litedramcore_bankmachine5_wrport_adr <= 4'd0; - if (litedramcore_bankmachine5_replace) begin - litedramcore_bankmachine5_wrport_adr <= (litedramcore_bankmachine5_produce - 1'd1); - end else begin - litedramcore_bankmachine5_wrport_adr <= litedramcore_bankmachine5_produce; - end -end -assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din; -assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace)); -assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re); -assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume; -assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r; -assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 5'd16); -assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0); -assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready); -assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid; -assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready; -assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first; -assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last; -assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we; -assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr; -assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid; -assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready; -assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first; -assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last; -assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we; -assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine5_next_state <= 4'd0; - litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - if (litedramcore_bankmachine5_cmd_ready) begin - litedramcore_bankmachine5_next_state <= 3'd5; - end +always @(*) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; end end 2'd2: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - if (litedramcore_bankmachine5_cmd_ready) begin - litedramcore_bankmachine5_next_state <= 3'd7; - end + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; end end 3'd4: begin - if ((~litedramcore_bankmachine5_refresh_req)) begin - litedramcore_bankmachine5_next_state <= 1'd0; - end end 3'd5: begin - litedramcore_bankmachine5_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine5_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine5_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine5_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - litedramcore_bankmachine5_next_state <= 3'd4; + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin - litedramcore_bankmachine5_next_state <= 2'd2; - end + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; end else begin - litedramcore_bankmachine5_next_state <= 1'd1; end end else begin - litedramcore_bankmachine5_next_state <= 2'd3; end end end @@ -7743,15 +8254,41 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_row_close <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + main_litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd2: begin + main_litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + main_litedramcore_bankmachine5_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -7769,8 +8306,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -7788,12 +8325,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -7804,18 +8341,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -7833,11 +8370,11 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -7855,13 +8392,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -7874,22 +8411,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7904,8 +8441,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -7923,14 +8460,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin end else begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; end end else begin end @@ -7942,8 +8479,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -7961,13 +8498,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin + main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -7980,8 +8517,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -7999,13 +8536,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin - litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin + main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready; end else begin end end else begin @@ -8018,8 +8555,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -8037,14 +8574,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin end else begin - litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; + main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready; end end else begin end @@ -8055,42 +8592,155 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine5_state) +assign main_litedramcore_bankmachine6_sink_valid = main_litedramcore_bankmachine6_req_valid; +assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_sink_ready; +assign main_litedramcore_bankmachine6_sink_payload_we = main_litedramcore_bankmachine6_req_we; +assign main_litedramcore_bankmachine6_sink_payload_addr = main_litedramcore_bankmachine6_req_addr; +assign main_litedramcore_bankmachine6_sink_sink_valid = main_litedramcore_bankmachine6_source_valid; +assign main_litedramcore_bankmachine6_source_ready = main_litedramcore_bankmachine6_sink_sink_ready; +assign main_litedramcore_bankmachine6_sink_sink_first = main_litedramcore_bankmachine6_source_first; +assign main_litedramcore_bankmachine6_sink_sink_last = main_litedramcore_bankmachine6_source_last; +assign main_litedramcore_bankmachine6_sink_sink_payload_we = main_litedramcore_bankmachine6_source_payload_we; +assign main_litedramcore_bankmachine6_sink_sink_payload_addr = main_litedramcore_bankmachine6_source_payload_addr; +assign main_litedramcore_bankmachine6_source_source_ready = (main_litedramcore_bankmachine6_req_wdata_ready | main_litedramcore_bankmachine6_req_rdata_valid); +assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_source_valid | main_litedramcore_bankmachine6_source_source_valid); +assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_source_source_payload_addr[20:7]); +assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; +always @(*) begin + main_litedramcore_bankmachine6_cmd_payload_a <= 14'd0; + if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin + main_litedramcore_bankmachine6_cmd_payload_a <= main_litedramcore_bankmachine6_source_source_payload_addr[20:7]; + end else begin + main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write); +assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); +assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); +always @(*) begin + main_litedramcore_bankmachine6_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine6_source_valid & main_litedramcore_bankmachine6_source_source_valid)) begin + if ((main_litedramcore_bankmachine6_source_payload_addr[20:7] != main_litedramcore_bankmachine6_source_source_payload_addr[20:7])) begin + main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine6_syncfifo6_din = {main_litedramcore_bankmachine6_fifo_in_last, main_litedramcore_bankmachine6_fifo_in_first, main_litedramcore_bankmachine6_fifo_in_payload_addr, main_litedramcore_bankmachine6_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout; +assign main_litedramcore_bankmachine6_sink_ready = main_litedramcore_bankmachine6_syncfifo6_writable; +assign main_litedramcore_bankmachine6_syncfifo6_we = main_litedramcore_bankmachine6_sink_valid; +assign main_litedramcore_bankmachine6_fifo_in_first = main_litedramcore_bankmachine6_sink_first; +assign main_litedramcore_bankmachine6_fifo_in_last = main_litedramcore_bankmachine6_sink_last; +assign main_litedramcore_bankmachine6_fifo_in_payload_we = main_litedramcore_bankmachine6_sink_payload_we; +assign main_litedramcore_bankmachine6_fifo_in_payload_addr = main_litedramcore_bankmachine6_sink_payload_addr; +assign main_litedramcore_bankmachine6_source_valid = main_litedramcore_bankmachine6_syncfifo6_readable; +assign main_litedramcore_bankmachine6_source_first = main_litedramcore_bankmachine6_fifo_out_first; +assign main_litedramcore_bankmachine6_source_last = main_litedramcore_bankmachine6_fifo_out_last; +assign main_litedramcore_bankmachine6_source_payload_we = main_litedramcore_bankmachine6_fifo_out_payload_we; +assign main_litedramcore_bankmachine6_source_payload_addr = main_litedramcore_bankmachine6_fifo_out_payload_addr; +assign main_litedramcore_bankmachine6_syncfifo6_re = main_litedramcore_bankmachine6_source_ready; +always @(*) begin + main_litedramcore_bankmachine6_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine6_replace) begin + main_litedramcore_bankmachine6_wrport_adr <= (main_litedramcore_bankmachine6_produce - 1'd1); + end else begin + main_litedramcore_bankmachine6_wrport_adr <= main_litedramcore_bankmachine6_produce; + end +end +assign main_litedramcore_bankmachine6_wrport_dat_w = main_litedramcore_bankmachine6_syncfifo6_din; +assign main_litedramcore_bankmachine6_wrport_we = (main_litedramcore_bankmachine6_syncfifo6_we & (main_litedramcore_bankmachine6_syncfifo6_writable | main_litedramcore_bankmachine6_replace)); +assign main_litedramcore_bankmachine6_do_read = (main_litedramcore_bankmachine6_syncfifo6_readable & main_litedramcore_bankmachine6_syncfifo6_re); +assign main_litedramcore_bankmachine6_rdport_adr = main_litedramcore_bankmachine6_consume; +assign main_litedramcore_bankmachine6_syncfifo6_dout = main_litedramcore_bankmachine6_rdport_dat_r; +assign main_litedramcore_bankmachine6_syncfifo6_writable = (main_litedramcore_bankmachine6_level != 5'd16); +assign main_litedramcore_bankmachine6_syncfifo6_readable = (main_litedramcore_bankmachine6_level != 1'd0); +assign main_litedramcore_bankmachine6_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine6_pipe_valid_source_valid) | main_litedramcore_bankmachine6_pipe_valid_source_ready); +assign main_litedramcore_bankmachine6_pipe_valid_sink_valid = main_litedramcore_bankmachine6_sink_sink_valid; +assign main_litedramcore_bankmachine6_sink_sink_ready = main_litedramcore_bankmachine6_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine6_pipe_valid_sink_first = main_litedramcore_bankmachine6_sink_sink_first; +assign main_litedramcore_bankmachine6_pipe_valid_sink_last = main_litedramcore_bankmachine6_sink_sink_last; +assign main_litedramcore_bankmachine6_pipe_valid_sink_payload_we = main_litedramcore_bankmachine6_sink_sink_payload_we; +assign main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine6_sink_sink_payload_addr; +assign main_litedramcore_bankmachine6_source_source_valid = main_litedramcore_bankmachine6_pipe_valid_source_valid; +assign main_litedramcore_bankmachine6_pipe_valid_source_ready = main_litedramcore_bankmachine6_source_source_ready; +assign main_litedramcore_bankmachine6_source_source_first = main_litedramcore_bankmachine6_pipe_valid_source_first; +assign main_litedramcore_bankmachine6_source_source_last = main_litedramcore_bankmachine6_pipe_valid_source_last; +assign main_litedramcore_bankmachine6_source_source_payload_we = main_litedramcore_bankmachine6_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine6_source_source_payload_addr = main_litedramcore_bankmachine6_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine6_next_state <= 4'd0; + builder_bankmachine6_next_state <= builder_bankmachine6_state; + case (builder_bankmachine6_state) 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + if (main_litedramcore_bankmachine6_cmd_ready) begin + builder_bankmachine6_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + builder_bankmachine6_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + if (main_litedramcore_bankmachine6_cmd_ready) begin + builder_bankmachine6_next_state <= 3'd7; + end + end end 3'd4: begin - if (litedramcore_bankmachine5_twtpcon_ready) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd1; + if ((~main_litedramcore_bankmachine6_refresh_req)) begin + builder_bankmachine6_next_state <= 1'd0; end end 3'd5: begin + builder_bankmachine6_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine6_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine6_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine6_next_state <= 1'd0; end default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + builder_bankmachine6_next_state <= 3'd4; + end else begin + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if ((main_litedramcore_bankmachine6_cmd_ready & main_litedramcore_bankmachine6_auto_precharge)) begin + builder_bankmachine6_next_state <= 2'd2; + end + end else begin + builder_bankmachine6_next_state <= 1'd1; + end + end else begin + builder_bankmachine6_next_state <= 2'd3; + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine5_row_open <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_open <= 1'd1; + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -8108,19 +8758,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_valid <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -8133,12 +8777,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -8149,18 +8793,21 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_row_close <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - litedramcore_bankmachine5_row_close <= 1'd1; + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 2'd2: begin - litedramcore_bankmachine5_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 3'd4: begin - litedramcore_bankmachine5_row_close <= 1'd1; end 3'd5: begin end @@ -8174,139 +8821,41 @@ always @(*) begin end endcase end -assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid; -assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready; -assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we; -assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr; -assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid; -assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready; -assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first; -assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last; -assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we; -assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr; -assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); -assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid); -assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[20:7]); -assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6; -always @(*) begin - litedramcore_bankmachine6_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine6_row_col_n_addr_sel) begin - litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_source_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write); -assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); -assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); -always @(*) begin - litedramcore_bankmachine6_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin - if ((litedramcore_bankmachine6_source_payload_addr[20:7] != litedramcore_bankmachine6_source_source_payload_addr[20:7])) begin - litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we}; -assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; -assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; -assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; -assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; -assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable; -assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid; -assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first; -assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last; -assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we; -assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr; -assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable; -assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first; -assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last; -assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we; -assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr; -assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready; -always @(*) begin - litedramcore_bankmachine6_wrport_adr <= 4'd0; - if (litedramcore_bankmachine6_replace) begin - litedramcore_bankmachine6_wrport_adr <= (litedramcore_bankmachine6_produce - 1'd1); - end else begin - litedramcore_bankmachine6_wrport_adr <= litedramcore_bankmachine6_produce; - end -end -assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din; -assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace)); -assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re); -assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume; -assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r; -assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 5'd16); -assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0); -assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready); -assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid; -assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready; -assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first; -assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last; -assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we; -assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr; -assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid; -assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready; -assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first; -assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last; -assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we; -assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine6_next_state <= 4'd0; - litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - if (litedramcore_bankmachine6_cmd_ready) begin - litedramcore_bankmachine6_next_state <= 3'd5; - end +always @(*) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; end end 2'd2: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - if (litedramcore_bankmachine6_cmd_ready) begin - litedramcore_bankmachine6_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~litedramcore_bankmachine6_refresh_req)) begin - litedramcore_bankmachine6_next_state <= 1'd0; - end end 3'd5: begin - litedramcore_bankmachine6_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine6_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine6_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine6_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - litedramcore_bankmachine6_next_state <= 3'd4; + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin - litedramcore_bankmachine6_next_state <= 2'd2; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end else begin end end else begin - litedramcore_bankmachine6_next_state <= 1'd1; end end else begin - litedramcore_bankmachine6_next_state <= 2'd3; end end end @@ -8314,56 +8863,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8378,12 +8893,9 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -8400,14 +8912,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin end else begin + main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; end end else begin end @@ -8419,38 +8931,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8468,14 +8950,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin + main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; end else begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; end end else begin end @@ -8487,8 +8969,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8506,13 +8988,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin + main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready; end else begin end end else begin @@ -8525,8 +9007,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8544,14 +9026,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin - litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin end else begin + main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready; end end else begin end @@ -8563,8 +9045,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8572,6 +9054,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine6_twtpcon_ready) begin + main_litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -8582,37 +9067,22 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin - end else begin - litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_row_open <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_open <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine6_twtpcon_ready) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -8627,15 +9097,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_row_open <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_valid <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_open <= 1'd1; + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; end end 3'd4: begin @@ -8649,25 +9122,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine6_cmd_valid <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_row_close <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end + main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 3'd4: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -8678,57 +9160,161 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end -always @(*) begin - litedramcore_bankmachine6_row_close <= 1'd0; - case (litedramcore_bankmachine6_state) +assign main_litedramcore_bankmachine7_sink_valid = main_litedramcore_bankmachine7_req_valid; +assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_sink_ready; +assign main_litedramcore_bankmachine7_sink_payload_we = main_litedramcore_bankmachine7_req_we; +assign main_litedramcore_bankmachine7_sink_payload_addr = main_litedramcore_bankmachine7_req_addr; +assign main_litedramcore_bankmachine7_sink_sink_valid = main_litedramcore_bankmachine7_source_valid; +assign main_litedramcore_bankmachine7_source_ready = main_litedramcore_bankmachine7_sink_sink_ready; +assign main_litedramcore_bankmachine7_sink_sink_first = main_litedramcore_bankmachine7_source_first; +assign main_litedramcore_bankmachine7_sink_sink_last = main_litedramcore_bankmachine7_source_last; +assign main_litedramcore_bankmachine7_sink_sink_payload_we = main_litedramcore_bankmachine7_source_payload_we; +assign main_litedramcore_bankmachine7_sink_sink_payload_addr = main_litedramcore_bankmachine7_source_payload_addr; +assign main_litedramcore_bankmachine7_source_source_ready = (main_litedramcore_bankmachine7_req_wdata_ready | main_litedramcore_bankmachine7_req_rdata_valid); +assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_source_valid | main_litedramcore_bankmachine7_source_source_valid); +assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_source_source_payload_addr[20:7]); +assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7; +always @(*) begin + main_litedramcore_bankmachine7_cmd_payload_a <= 14'd0; + if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin + main_litedramcore_bankmachine7_cmd_payload_a <= main_litedramcore_bankmachine7_source_source_payload_addr[20:7]; + end else begin + main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write); +assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); +assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); +always @(*) begin + main_litedramcore_bankmachine7_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine7_source_valid & main_litedramcore_bankmachine7_source_source_valid)) begin + if ((main_litedramcore_bankmachine7_source_payload_addr[20:7] != main_litedramcore_bankmachine7_source_source_payload_addr[20:7])) begin + main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine7_syncfifo7_din = {main_litedramcore_bankmachine7_fifo_in_last, main_litedramcore_bankmachine7_fifo_in_first, main_litedramcore_bankmachine7_fifo_in_payload_addr, main_litedramcore_bankmachine7_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout; +assign main_litedramcore_bankmachine7_sink_ready = main_litedramcore_bankmachine7_syncfifo7_writable; +assign main_litedramcore_bankmachine7_syncfifo7_we = main_litedramcore_bankmachine7_sink_valid; +assign main_litedramcore_bankmachine7_fifo_in_first = main_litedramcore_bankmachine7_sink_first; +assign main_litedramcore_bankmachine7_fifo_in_last = main_litedramcore_bankmachine7_sink_last; +assign main_litedramcore_bankmachine7_fifo_in_payload_we = main_litedramcore_bankmachine7_sink_payload_we; +assign main_litedramcore_bankmachine7_fifo_in_payload_addr = main_litedramcore_bankmachine7_sink_payload_addr; +assign main_litedramcore_bankmachine7_source_valid = main_litedramcore_bankmachine7_syncfifo7_readable; +assign main_litedramcore_bankmachine7_source_first = main_litedramcore_bankmachine7_fifo_out_first; +assign main_litedramcore_bankmachine7_source_last = main_litedramcore_bankmachine7_fifo_out_last; +assign main_litedramcore_bankmachine7_source_payload_we = main_litedramcore_bankmachine7_fifo_out_payload_we; +assign main_litedramcore_bankmachine7_source_payload_addr = main_litedramcore_bankmachine7_fifo_out_payload_addr; +assign main_litedramcore_bankmachine7_syncfifo7_re = main_litedramcore_bankmachine7_source_ready; +always @(*) begin + main_litedramcore_bankmachine7_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine7_replace) begin + main_litedramcore_bankmachine7_wrport_adr <= (main_litedramcore_bankmachine7_produce - 1'd1); + end else begin + main_litedramcore_bankmachine7_wrport_adr <= main_litedramcore_bankmachine7_produce; + end +end +assign main_litedramcore_bankmachine7_wrport_dat_w = main_litedramcore_bankmachine7_syncfifo7_din; +assign main_litedramcore_bankmachine7_wrport_we = (main_litedramcore_bankmachine7_syncfifo7_we & (main_litedramcore_bankmachine7_syncfifo7_writable | main_litedramcore_bankmachine7_replace)); +assign main_litedramcore_bankmachine7_do_read = (main_litedramcore_bankmachine7_syncfifo7_readable & main_litedramcore_bankmachine7_syncfifo7_re); +assign main_litedramcore_bankmachine7_rdport_adr = main_litedramcore_bankmachine7_consume; +assign main_litedramcore_bankmachine7_syncfifo7_dout = main_litedramcore_bankmachine7_rdport_dat_r; +assign main_litedramcore_bankmachine7_syncfifo7_writable = (main_litedramcore_bankmachine7_level != 5'd16); +assign main_litedramcore_bankmachine7_syncfifo7_readable = (main_litedramcore_bankmachine7_level != 1'd0); +assign main_litedramcore_bankmachine7_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine7_pipe_valid_source_valid) | main_litedramcore_bankmachine7_pipe_valid_source_ready); +assign main_litedramcore_bankmachine7_pipe_valid_sink_valid = main_litedramcore_bankmachine7_sink_sink_valid; +assign main_litedramcore_bankmachine7_sink_sink_ready = main_litedramcore_bankmachine7_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine7_pipe_valid_sink_first = main_litedramcore_bankmachine7_sink_sink_first; +assign main_litedramcore_bankmachine7_pipe_valid_sink_last = main_litedramcore_bankmachine7_sink_sink_last; +assign main_litedramcore_bankmachine7_pipe_valid_sink_payload_we = main_litedramcore_bankmachine7_sink_sink_payload_we; +assign main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine7_sink_sink_payload_addr; +assign main_litedramcore_bankmachine7_source_source_valid = main_litedramcore_bankmachine7_pipe_valid_source_valid; +assign main_litedramcore_bankmachine7_pipe_valid_source_ready = main_litedramcore_bankmachine7_source_source_ready; +assign main_litedramcore_bankmachine7_source_source_first = main_litedramcore_bankmachine7_pipe_valid_source_first; +assign main_litedramcore_bankmachine7_source_source_last = main_litedramcore_bankmachine7_pipe_valid_source_last; +assign main_litedramcore_bankmachine7_source_source_payload_we = main_litedramcore_bankmachine7_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine7_source_source_payload_addr = main_litedramcore_bankmachine7_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine7_next_state <= 4'd0; + builder_bankmachine7_next_state <= builder_bankmachine7_state; + case (builder_bankmachine7_state) 1'd1: begin - litedramcore_bankmachine6_row_close <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + if (main_litedramcore_bankmachine7_cmd_ready) begin + builder_bankmachine7_next_state <= 3'd5; + end + end end 2'd2: begin - litedramcore_bankmachine6_row_close <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + builder_bankmachine7_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + if (main_litedramcore_bankmachine7_cmd_ready) begin + builder_bankmachine7_next_state <= 3'd7; + end + end end 3'd4: begin - litedramcore_bankmachine6_row_close <= 1'd1; + if ((~main_litedramcore_bankmachine7_refresh_req)) begin + builder_bankmachine7_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine7_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine7_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine7_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine7_next_state <= 1'd0; end default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + builder_bankmachine7_next_state <= 3'd4; + end else begin + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if ((main_litedramcore_bankmachine7_cmd_ready & main_litedramcore_bankmachine7_auto_precharge)) begin + builder_bankmachine7_next_state <= 2'd2; + end + end else begin + builder_bankmachine7_next_state <= 1'd1; + end + end else begin + builder_bankmachine7_next_state <= 2'd3; + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -8745,139 +9331,41 @@ always @(*) begin end endcase end -assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid; -assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready; -assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we; -assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr; -assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid; -assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready; -assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first; -assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last; -assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we; -assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr; -assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); -assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid); -assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[20:7]); -assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7; -always @(*) begin - litedramcore_bankmachine7_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine7_row_col_n_addr_sel) begin - litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_source_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write); -assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); -assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); -always @(*) begin - litedramcore_bankmachine7_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin - if ((litedramcore_bankmachine7_source_payload_addr[20:7] != litedramcore_bankmachine7_source_source_payload_addr[20:7])) begin - litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we}; -assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; -assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; -assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; -assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; -assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable; -assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid; -assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first; -assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last; -assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we; -assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr; -assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable; -assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first; -assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last; -assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we; -assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr; -assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready; -always @(*) begin - litedramcore_bankmachine7_wrport_adr <= 4'd0; - if (litedramcore_bankmachine7_replace) begin - litedramcore_bankmachine7_wrport_adr <= (litedramcore_bankmachine7_produce - 1'd1); - end else begin - litedramcore_bankmachine7_wrport_adr <= litedramcore_bankmachine7_produce; - end -end -assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din; -assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace)); -assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re); -assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume; -assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r; -assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 5'd16); -assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0); -assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready); -assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid; -assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready; -assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first; -assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last; -assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we; -assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr; -assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid; -assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready; -assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first; -assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last; -assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we; -assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine7_next_state <= 4'd0; - litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - if (litedramcore_bankmachine7_cmd_ready) begin - litedramcore_bankmachine7_next_state <= 3'd5; - end +always @(*) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end end 2'd2: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - if (litedramcore_bankmachine7_cmd_ready) begin - litedramcore_bankmachine7_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~litedramcore_bankmachine7_refresh_req)) begin - litedramcore_bankmachine7_next_state <= 1'd0; - end end 3'd5: begin - litedramcore_bankmachine7_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine7_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine7_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine7_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - litedramcore_bankmachine7_next_state <= 3'd4; + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin - litedramcore_bankmachine7_next_state <= 2'd2; + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin end end else begin - litedramcore_bankmachine7_next_state <= 1'd1; end end else begin - litedramcore_bankmachine7_next_state <= 2'd3; end end end @@ -8885,22 +9373,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8915,8 +9403,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -8934,14 +9422,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin end else begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; end end else begin end @@ -8953,8 +9441,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -8972,13 +9460,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -8991,8 +9479,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -9010,13 +9498,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin - litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin + main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready; end else begin end end else begin @@ -9029,8 +9517,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -9048,14 +9536,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin end else begin - litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; + main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready; end end else begin end @@ -9067,8 +9555,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -9076,8 +9564,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine7_twtpcon_ready) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd1; + if (main_litedramcore_bankmachine7_twtpcon_ready) begin + main_litedramcore_bankmachine7_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -9093,15 +9581,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_row_open <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_row_open <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_open <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_row_open <= 1'd1; end end 3'd4: begin @@ -9119,18 +9607,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_valid <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; end end 3'd4: begin @@ -9144,12 +9632,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; end else begin end end else begin @@ -9160,67 +9648,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_row_close <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_row_close <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -9231,34 +9670,19 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -9276,12 +9700,9 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -9298,15 +9719,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end else begin - end + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -9316,266 +9734,266 @@ always @(*) begin end endcase end -assign litedramcore_rdcmdphase = (a7ddrphy_rdphase_storage - 1'd1); -assign litedramcore_wrcmdphase = (a7ddrphy_wrphase_storage - 1'd1); -assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); -assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); -assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready); -assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read)); -assign litedramcore_cas_allowed = litedramcore_tccdcon_ready; -assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); -assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read)); -assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write)); -assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0); -assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0); -assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid; -assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt); -assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata}; -assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; -assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; -assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; -assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; -assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); -assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); -assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); -assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); +assign main_litedramcore_nphases = (main_a7ddrphy_rdphase_storage - 1'd1); +assign main_litedramcore_rdphase = (main_a7ddrphy_wrphase_storage - 1'd1); +assign main_litedramcore_trrdcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))); +assign main_litedramcore_tfawcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))); +assign main_litedramcore_ras_allowed = (main_litedramcore_trrdcon_ready & main_litedramcore_tfawcon_ready); +assign main_litedramcore_tccdcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_cmd_payload_is_write | main_litedramcore_choose_req_cmd_payload_is_read)); +assign main_litedramcore_cas_allowed = main_litedramcore_tccdcon_ready; +assign main_litedramcore_twtrcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); +assign main_litedramcore_read_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_read) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_read)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_read)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_read)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_read)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_read)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_read)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_read)); +assign main_litedramcore_write_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_write) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_write)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_write)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_write)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_write)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_write)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_write)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_write)); +assign main_litedramcore_max_time0 = (main_litedramcore_time0 == 1'd0); +assign main_litedramcore_max_time1 = (main_litedramcore_time1 == 1'd0); +assign main_litedramcore_bankmachine0_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine1_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine2_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine3_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine4_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine5_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine6_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine7_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_go_to_refresh = (((((((main_litedramcore_bankmachine0_refresh_gnt & main_litedramcore_bankmachine1_refresh_gnt) & main_litedramcore_bankmachine2_refresh_gnt) & main_litedramcore_bankmachine3_refresh_gnt) & main_litedramcore_bankmachine4_refresh_gnt) & main_litedramcore_bankmachine5_refresh_gnt) & main_litedramcore_bankmachine6_refresh_gnt) & main_litedramcore_bankmachine7_refresh_gnt); +assign main_litedramcore_interface_rdata = {main_litedramcore_dfi_p3_rddata, main_litedramcore_dfi_p2_rddata, main_litedramcore_dfi_p1_rddata, main_litedramcore_dfi_p0_rddata}; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); always @(*) begin - litedramcore_choose_cmd_valids <= 8'd0; - litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids <= 8'd0; + main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); end -assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; -assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0; -assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1; -assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2; -assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; -assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; -assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; +assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids; +assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_self0; +assign main_litedramcore_choose_cmd_cmd_payload_a = builder_rhs_self1; +assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_self2; +assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_self3; +assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_self4; +assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_self5; always @(*) begin - litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; + main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_self0; end end always @(*) begin - litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; + main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_self1; end end always @(*) begin - litedramcore_choose_cmd_cmd_payload_we <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; + main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_self2; end end always @(*) begin - litedramcore_bankmachine0_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin - litedramcore_bankmachine0_cmd_ready <= 1'd1; + main_litedramcore_bankmachine0_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin + main_litedramcore_bankmachine0_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin - litedramcore_bankmachine0_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin + main_litedramcore_bankmachine0_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine1_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin - litedramcore_bankmachine1_cmd_ready <= 1'd1; + main_litedramcore_bankmachine1_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin + main_litedramcore_bankmachine1_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin - litedramcore_bankmachine1_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin + main_litedramcore_bankmachine1_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine2_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin - litedramcore_bankmachine2_cmd_ready <= 1'd1; + main_litedramcore_bankmachine2_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin + main_litedramcore_bankmachine2_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin - litedramcore_bankmachine2_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin + main_litedramcore_bankmachine2_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine3_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin - litedramcore_bankmachine3_cmd_ready <= 1'd1; + main_litedramcore_bankmachine3_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin + main_litedramcore_bankmachine3_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin - litedramcore_bankmachine3_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin + main_litedramcore_bankmachine3_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine4_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin - litedramcore_bankmachine4_cmd_ready <= 1'd1; + main_litedramcore_bankmachine4_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin + main_litedramcore_bankmachine4_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin - litedramcore_bankmachine4_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin + main_litedramcore_bankmachine4_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine5_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin - litedramcore_bankmachine5_cmd_ready <= 1'd1; + main_litedramcore_bankmachine5_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin + main_litedramcore_bankmachine5_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin - litedramcore_bankmachine5_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin + main_litedramcore_bankmachine5_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine6_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin - litedramcore_bankmachine6_cmd_ready <= 1'd1; + main_litedramcore_bankmachine6_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin + main_litedramcore_bankmachine6_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin - litedramcore_bankmachine6_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin + main_litedramcore_bankmachine6_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine7_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin - litedramcore_bankmachine7_cmd_ready <= 1'd1; + main_litedramcore_bankmachine7_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin + main_litedramcore_bankmachine7_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin - litedramcore_bankmachine7_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin + main_litedramcore_bankmachine7_cmd_ready <= 1'd1; end end -assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid)); +assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid)); always @(*) begin - litedramcore_choose_req_valids <= 8'd0; - litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids <= 8'd0; + main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); end -assign litedramcore_choose_req_request = litedramcore_choose_req_valids; -assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6; -assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7; -assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8; -assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9; -assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; -assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; +assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids; +assign main_litedramcore_choose_req_cmd_valid = builder_rhs_self6; +assign main_litedramcore_choose_req_cmd_payload_a = builder_rhs_self7; +assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_self8; +assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_self9; +assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_self10; +assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_self11; always @(*) begin - litedramcore_choose_req_cmd_payload_cas <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; + main_litedramcore_choose_req_cmd_payload_cas <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_cas <= builder_t_self3; end end always @(*) begin - litedramcore_choose_req_cmd_payload_ras <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; + main_litedramcore_choose_req_cmd_payload_ras <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_ras <= builder_t_self4; end end always @(*) begin - litedramcore_choose_req_cmd_payload_we <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; + main_litedramcore_choose_req_cmd_payload_we <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_we <= builder_t_self5; end end -assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); -assign litedramcore_dfi_p0_reset_n = 1'd1; -assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}}; -assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}}; -assign litedramcore_dfi_p1_reset_n = 1'd1; -assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}}; -assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}}; -assign litedramcore_dfi_p2_reset_n = 1'd1; -assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}}; -assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}}; -assign litedramcore_dfi_p3_reset_n = 1'd1; -assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}}; -assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}}; -assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]); +assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid)); +assign main_litedramcore_dfi_p0_reset_n = 1'd1; +assign main_litedramcore_dfi_p0_cke = {1{main_litedramcore_steerer4}}; +assign main_litedramcore_dfi_p0_odt = {1{main_litedramcore_steerer5}}; +assign main_litedramcore_dfi_p1_reset_n = 1'd1; +assign main_litedramcore_dfi_p1_cke = {1{main_litedramcore_steerer6}}; +assign main_litedramcore_dfi_p1_odt = {1{main_litedramcore_steerer7}}; +assign main_litedramcore_dfi_p2_reset_n = 1'd1; +assign main_litedramcore_dfi_p2_cke = {1{main_litedramcore_steerer8}}; +assign main_litedramcore_dfi_p2_odt = {1{main_litedramcore_steerer9}}; +assign main_litedramcore_dfi_p3_reset_n = 1'd1; +assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer10}}; +assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer11}}; +assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]); always @(*) begin - litedramcore_multiplexer_next_state <= 4'd0; - litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state; - case (litedramcore_multiplexer_state) + builder_multiplexer_next_state <= 4'd0; + builder_multiplexer_next_state <= builder_multiplexer_state; + case (builder_multiplexer_state) 1'd1: begin - if (litedramcore_read_available) begin - if (((~litedramcore_write_available) | litedramcore_max_time1)) begin - litedramcore_multiplexer_next_state <= 2'd3; + if (main_litedramcore_read_available) begin + if (((~main_litedramcore_write_available) | main_litedramcore_max_time1)) begin + builder_multiplexer_next_state <= 2'd3; end end - if (litedramcore_go_to_refresh) begin - litedramcore_multiplexer_next_state <= 2'd2; + if (main_litedramcore_go_to_refresh) begin + builder_multiplexer_next_state <= 2'd2; end end 2'd2: begin - if (litedramcore_cmd_last) begin - litedramcore_multiplexer_next_state <= 1'd0; + if (main_litedramcore_cmd_last) begin + builder_multiplexer_next_state <= 1'd0; end end 2'd3: begin - if (litedramcore_twtrcon_ready) begin - litedramcore_multiplexer_next_state <= 1'd0; + if (main_litedramcore_twtrcon_ready) begin + builder_multiplexer_next_state <= 1'd0; end end 3'd4: begin - litedramcore_multiplexer_next_state <= 3'd5; + builder_multiplexer_next_state <= 3'd5; end 3'd5: begin - litedramcore_multiplexer_next_state <= 3'd6; + builder_multiplexer_next_state <= 3'd6; end 3'd6: begin - litedramcore_multiplexer_next_state <= 3'd7; + builder_multiplexer_next_state <= 3'd7; end 3'd7: begin - litedramcore_multiplexer_next_state <= 4'd8; + builder_multiplexer_next_state <= 4'd8; end 4'd8: begin - litedramcore_multiplexer_next_state <= 4'd9; + builder_multiplexer_next_state <= 4'd9; end 4'd9: begin - litedramcore_multiplexer_next_state <= 4'd10; + builder_multiplexer_next_state <= 4'd10; end 4'd10: begin - litedramcore_multiplexer_next_state <= 1'd1; + builder_multiplexer_next_state <= 1'd1; end default: begin - if (litedramcore_write_available) begin - if (((~litedramcore_read_available) | litedramcore_max_time0)) begin - litedramcore_multiplexer_next_state <= 3'd4; + if (main_litedramcore_write_available) begin + if (((~main_litedramcore_read_available) | main_litedramcore_max_time0)) begin + builder_multiplexer_next_state <= 3'd4; end end - if (litedramcore_go_to_refresh) begin - litedramcore_multiplexer_next_state <= 2'd2; + if (main_litedramcore_go_to_refresh) begin + builder_multiplexer_next_state <= 2'd2; end end endcase end always @(*) begin - litedramcore_steerer_sel0 <= 2'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_steerer0 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_steerer_sel0 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 1'd0)) begin - litedramcore_steerer_sel0 <= 2'd2; + main_litedramcore_steerer0 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 1'd0)) begin + main_litedramcore_steerer0 <= 2'd2; end - if ((litedramcore_wrcmdphase == 1'd0)) begin - litedramcore_steerer_sel0 <= 1'd1; + if ((main_litedramcore_rdphase == 1'd0)) begin + main_litedramcore_steerer0 <= 1'd1; end end 2'd2: begin - litedramcore_steerer_sel0 <= 2'd3; + main_litedramcore_steerer0 <= 2'd3; end 2'd3: begin end @@ -9594,23 +10012,23 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel0 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 1'd0)) begin - litedramcore_steerer_sel0 <= 2'd2; + main_litedramcore_steerer0 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 1'd0)) begin + main_litedramcore_steerer0 <= 2'd2; end - if ((litedramcore_rdcmdphase == 1'd0)) begin - litedramcore_steerer_sel0 <= 1'd1; + if ((main_litedramcore_nphases == 1'd0)) begin + main_litedramcore_steerer0 <= 1'd1; end end endcase end always @(*) begin - litedramcore_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_cmd_ready <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin end 2'd2: begin - litedramcore_cmd_ready <= 1'd1; + main_litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -9633,15 +10051,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_steerer_sel1 <= 2'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_steerer1 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_steerer_sel1 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 1'd1)) begin - litedramcore_steerer_sel1 <= 2'd2; + main_litedramcore_steerer1 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin + main_litedramcore_steerer1 <= 2'd2; end - if ((litedramcore_wrcmdphase == 1'd1)) begin - litedramcore_steerer_sel1 <= 1'd1; + if ((main_litedramcore_rdphase == 1'd1)) begin + main_litedramcore_steerer1 <= 1'd1; end end 2'd2: begin @@ -9663,26 +10081,26 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel1 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 1'd1)) begin - litedramcore_steerer_sel1 <= 2'd2; + main_litedramcore_steerer1 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin + main_litedramcore_steerer1 <= 2'd2; end - if ((litedramcore_rdcmdphase == 1'd1)) begin - litedramcore_steerer_sel1 <= 1'd1; + if ((main_litedramcore_nphases == 1'd1)) begin + main_litedramcore_steerer1 <= 1'd1; end end endcase end always @(*) begin - litedramcore_steerer_sel2 <= 2'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_steerer2 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_steerer_sel2 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 2'd2)) begin - litedramcore_steerer_sel2 <= 2'd2; + main_litedramcore_steerer2 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 2'd2)) begin + main_litedramcore_steerer2 <= 2'd2; end - if ((litedramcore_wrcmdphase == 2'd2)) begin - litedramcore_steerer_sel2 <= 1'd1; + if ((main_litedramcore_rdphase == 2'd2)) begin + main_litedramcore_steerer2 <= 1'd1; end end 2'd2: begin @@ -9704,23 +10122,23 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel2 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 2'd2)) begin - litedramcore_steerer_sel2 <= 2'd2; + main_litedramcore_steerer2 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 2'd2)) begin + main_litedramcore_steerer2 <= 2'd2; end - if ((litedramcore_rdcmdphase == 2'd2)) begin - litedramcore_steerer_sel2 <= 1'd1; + if ((main_litedramcore_nphases == 2'd2)) begin + main_litedramcore_steerer2 <= 1'd1; end end endcase end always @(*) begin - litedramcore_choose_cmd_want_activates <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_cmd_want_activates <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin if (1'd0) begin end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; end end 2'd2: begin @@ -9744,21 +10162,21 @@ always @(*) begin default: begin if (1'd0) begin end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; end end endcase end always @(*) begin - litedramcore_steerer_sel3 <= 2'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_steerer3 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_steerer_sel3 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 2'd3)) begin - litedramcore_steerer_sel3 <= 2'd2; + main_litedramcore_steerer3 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin + main_litedramcore_steerer3 <= 2'd2; end - if ((litedramcore_wrcmdphase == 2'd3)) begin - litedramcore_steerer_sel3 <= 1'd1; + if ((main_litedramcore_rdphase == 2'd3)) begin + main_litedramcore_steerer3 <= 1'd1; end end 2'd2: begin @@ -9780,19 +10198,19 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel3 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 2'd3)) begin - litedramcore_steerer_sel3 <= 2'd2; + main_litedramcore_steerer3 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin + main_litedramcore_steerer3 <= 2'd2; end - if ((litedramcore_rdcmdphase == 2'd3)) begin - litedramcore_steerer_sel3 <= 1'd1; + if ((main_litedramcore_nphases == 2'd3)) begin + main_litedramcore_steerer3 <= 1'd1; end end endcase end always @(*) begin - litedramcore_en0 <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_en0 <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin end 2'd2: begin @@ -9814,17 +10232,17 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_en0 <= 1'd1; + main_litedramcore_en0 <= 1'd1; end endcase end always @(*) begin - litedramcore_choose_cmd_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_cmd_cmd_ready <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin if (1'd0) begin end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); end end 2'd2: begin @@ -9848,14 +10266,14 @@ always @(*) begin default: begin if (1'd0) begin end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); end end endcase end always @(*) begin - litedramcore_choose_req_want_reads <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_req_want_reads <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin end 2'd2: begin @@ -9877,15 +10295,15 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_choose_req_want_reads <= 1'd1; + main_litedramcore_choose_req_want_reads <= 1'd1; end endcase end always @(*) begin - litedramcore_choose_req_want_writes <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_req_want_writes <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_choose_req_want_writes <= 1'd1; + main_litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -9910,14 +10328,10 @@ always @(*) begin endcase end always @(*) begin - litedramcore_choose_req_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_en1 <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end + main_litedramcore_en1 <= 1'd1; end 2'd2: begin end @@ -9938,19 +10352,18 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end end endcase end always @(*) begin - litedramcore_en1 <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_req_cmd_ready <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_en1 <= 1'd1; + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; + end end 2'd2: begin end @@ -9971,2011 +10384,2013 @@ always @(*) begin 4'd10: begin end default: begin + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; + end end endcase end -assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock)); -assign litedramcore_interface_bank0_addr = rhs_array_muxed12; -assign litedramcore_interface_bank0_we = rhs_array_muxed13; -assign litedramcore_interface_bank0_valid = rhs_array_muxed14; -assign litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock)); -assign litedramcore_interface_bank1_addr = rhs_array_muxed15; -assign litedramcore_interface_bank1_we = rhs_array_muxed16; -assign litedramcore_interface_bank1_valid = rhs_array_muxed17; -assign litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock)); -assign litedramcore_interface_bank2_addr = rhs_array_muxed18; -assign litedramcore_interface_bank2_we = rhs_array_muxed19; -assign litedramcore_interface_bank2_valid = rhs_array_muxed20; -assign litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock)); -assign litedramcore_interface_bank3_addr = rhs_array_muxed21; -assign litedramcore_interface_bank3_we = rhs_array_muxed22; -assign litedramcore_interface_bank3_valid = rhs_array_muxed23; -assign litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock)); -assign litedramcore_interface_bank4_addr = rhs_array_muxed24; -assign litedramcore_interface_bank4_we = rhs_array_muxed25; -assign litedramcore_interface_bank4_valid = rhs_array_muxed26; -assign litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock)); -assign litedramcore_interface_bank5_addr = rhs_array_muxed27; -assign litedramcore_interface_bank5_we = rhs_array_muxed28; -assign litedramcore_interface_bank5_valid = rhs_array_muxed29; -assign litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock)); -assign litedramcore_interface_bank6_addr = rhs_array_muxed30; -assign litedramcore_interface_bank6_we = rhs_array_muxed31; -assign litedramcore_interface_bank6_valid = rhs_array_muxed32; -assign litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock)); -assign litedramcore_interface_bank7_addr = rhs_array_muxed33; -assign litedramcore_interface_bank7_we = rhs_array_muxed34; -assign litedramcore_interface_bank7_valid = rhs_array_muxed35; -assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready)); -assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1; -assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8; -always @(*) begin - litedramcore_interface_wdata <= 128'd0; - case ({litedramcore_new_master_wdata_ready1}) +assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock)); +assign main_litedramcore_interface_bank0_addr = builder_rhs_self12; +assign main_litedramcore_interface_bank0_we = builder_rhs_self13; +assign main_litedramcore_interface_bank0_valid = builder_rhs_self14; +assign builder_roundrobin1_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin1_ce = ((~main_litedramcore_interface_bank1_valid) & (~main_litedramcore_interface_bank1_lock)); +assign main_litedramcore_interface_bank1_addr = builder_rhs_self15; +assign main_litedramcore_interface_bank1_we = builder_rhs_self16; +assign main_litedramcore_interface_bank1_valid = builder_rhs_self17; +assign builder_roundrobin2_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin2_ce = ((~main_litedramcore_interface_bank2_valid) & (~main_litedramcore_interface_bank2_lock)); +assign main_litedramcore_interface_bank2_addr = builder_rhs_self18; +assign main_litedramcore_interface_bank2_we = builder_rhs_self19; +assign main_litedramcore_interface_bank2_valid = builder_rhs_self20; +assign builder_roundrobin3_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin3_ce = ((~main_litedramcore_interface_bank3_valid) & (~main_litedramcore_interface_bank3_lock)); +assign main_litedramcore_interface_bank3_addr = builder_rhs_self21; +assign main_litedramcore_interface_bank3_we = builder_rhs_self22; +assign main_litedramcore_interface_bank3_valid = builder_rhs_self23; +assign builder_roundrobin4_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin4_ce = ((~main_litedramcore_interface_bank4_valid) & (~main_litedramcore_interface_bank4_lock)); +assign main_litedramcore_interface_bank4_addr = builder_rhs_self24; +assign main_litedramcore_interface_bank4_we = builder_rhs_self25; +assign main_litedramcore_interface_bank4_valid = builder_rhs_self26; +assign builder_roundrobin5_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin5_ce = ((~main_litedramcore_interface_bank5_valid) & (~main_litedramcore_interface_bank5_lock)); +assign main_litedramcore_interface_bank5_addr = builder_rhs_self27; +assign main_litedramcore_interface_bank5_we = builder_rhs_self28; +assign main_litedramcore_interface_bank5_valid = builder_rhs_self29; +assign builder_roundrobin6_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin6_ce = ((~main_litedramcore_interface_bank6_valid) & (~main_litedramcore_interface_bank6_lock)); +assign main_litedramcore_interface_bank6_addr = builder_rhs_self30; +assign main_litedramcore_interface_bank6_we = builder_rhs_self31; +assign main_litedramcore_interface_bank6_valid = builder_rhs_self32; +assign builder_roundrobin7_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin7_ce = ((~main_litedramcore_interface_bank7_valid) & (~main_litedramcore_interface_bank7_lock)); +assign main_litedramcore_interface_bank7_addr = builder_rhs_self33; +assign main_litedramcore_interface_bank7_we = builder_rhs_self34; +assign main_litedramcore_interface_bank7_valid = builder_rhs_self35; +assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready)); +assign main_user_port_wdata_ready = builder_new_master_wdata_ready1; +assign main_user_port_rdata_valid = builder_new_master_rdata_valid8; +always @(*) begin + main_litedramcore_interface_wdata <= 128'd0; + case ({builder_new_master_wdata_ready1}) 1'd1: begin - litedramcore_interface_wdata <= user_port_wdata_payload_data; + main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data; end default: begin - litedramcore_interface_wdata <= 1'd0; + main_litedramcore_interface_wdata <= 1'd0; end endcase end always @(*) begin - litedramcore_interface_wdata_we <= 16'd0; - case ({litedramcore_new_master_wdata_ready1}) + main_litedramcore_interface_wdata_we <= 16'd0; + case ({builder_new_master_wdata_ready1}) 1'd1: begin - litedramcore_interface_wdata_we <= user_port_wdata_payload_we; + main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we; end default: begin - litedramcore_interface_wdata_we <= 1'd0; + main_litedramcore_interface_wdata_we <= 1'd0; end endcase end -assign user_port_rdata_payload_data = litedramcore_interface_rdata; -assign litedramcore_roundrobin0_grant = 1'd0; -assign litedramcore_roundrobin1_grant = 1'd0; -assign litedramcore_roundrobin2_grant = 1'd0; -assign litedramcore_roundrobin3_grant = 1'd0; -assign litedramcore_roundrobin4_grant = 1'd0; -assign litedramcore_roundrobin5_grant = 1'd0; -assign litedramcore_roundrobin6_grant = 1'd0; -assign litedramcore_roundrobin7_grant = 1'd0; -always @(*) begin - litedramcore_next_state <= 2'd0; - litedramcore_next_state <= litedramcore_state; - case (litedramcore_state) +assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata; +assign builder_roundrobin0_grant = 1'd0; +assign builder_roundrobin1_grant = 1'd0; +assign builder_roundrobin2_grant = 1'd0; +assign builder_roundrobin3_grant = 1'd0; +assign builder_roundrobin4_grant = 1'd0; +assign builder_roundrobin5_grant = 1'd0; +assign builder_roundrobin6_grant = 1'd0; +assign builder_roundrobin7_grant = 1'd0; +always @(*) begin + builder_next_state <= 2'd0; + builder_next_state <= builder_state; + case (builder_state) 1'd1: begin - litedramcore_next_state <= 2'd2; + builder_next_state <= 2'd2; end 2'd2: begin - litedramcore_next_state <= 1'd0; + builder_next_state <= 1'd0; end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_next_state <= 1'd1; + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_next_state <= 1'd1; end end endcase end always @(*) begin - litedramcore_we_next_value2 <= 1'd0; - case (litedramcore_state) + builder_interface1_adr_next_value1 <= 14'd0; + case (builder_state) 1'd1: begin - litedramcore_we_next_value2 <= 1'd0; + builder_interface1_adr_next_value1 <= 1'd0; end 2'd2: begin end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_adr_next_value1 <= builder_interface0_adr[29:0]; end end endcase end always @(*) begin - litedramcore_we_next_value_ce2 <= 1'd0; - case (litedramcore_state) + builder_interface0_ack <= 1'd0; + case (builder_state) 1'd1: begin - litedramcore_we_next_value_ce2 <= 1'd1; end 2'd2: begin + builder_interface0_ack <= 1'd1; end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value_ce2 <= 1'd1; - end end endcase end always @(*) begin - litedramcore_wishbone_ack <= 1'd0; - case (litedramcore_state) + builder_interface1_adr_next_value_ce1 <= 1'd0; + case (builder_state) 1'd1: begin + builder_interface1_adr_next_value_ce1 <= 1'd1; end 2'd2: begin - litedramcore_wishbone_ack <= 1'd1; end default: begin + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_adr_next_value_ce1 <= 1'd1; + end end endcase end always @(*) begin - litedramcore_wishbone_dat_r <= 32'd0; - case (litedramcore_state) + builder_interface1_we_next_value2 <= 1'd0; + case (builder_state) 1'd1: begin + builder_interface1_we_next_value2 <= 1'd0; end 2'd2: begin - litedramcore_wishbone_dat_r <= litedramcore_dat_r; end default: begin + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_we_next_value2 <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); + end end endcase end always @(*) begin - litedramcore_dat_w_next_value0 <= 32'd0; - case (litedramcore_state) + builder_interface1_we_next_value_ce2 <= 1'd0; + case (builder_state) 1'd1: begin + builder_interface1_we_next_value_ce2 <= 1'd1; end 2'd2: begin end default: begin - litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w; + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_we_next_value_ce2 <= 1'd1; + end end endcase end always @(*) begin - litedramcore_dat_w_next_value_ce0 <= 1'd0; - case (litedramcore_state) + builder_interface0_dat_r <= 32'd0; + case (builder_state) 1'd1: begin end 2'd2: begin + builder_interface0_dat_r <= builder_interface1_dat_r; end default: begin - litedramcore_dat_w_next_value_ce0 <= 1'd1; end endcase end always @(*) begin - litedramcore_adr_next_value1 <= 14'd0; - case (litedramcore_state) + builder_interface1_dat_w_next_value0 <= 32'd0; + case (builder_state) 1'd1: begin - litedramcore_adr_next_value1 <= 1'd0; end 2'd2: begin end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value1 <= litedramcore_wishbone_adr; - end + builder_interface1_dat_w_next_value0 <= builder_interface0_dat_w; end endcase end always @(*) begin - litedramcore_adr_next_value_ce1 <= 1'd0; - case (litedramcore_state) + builder_interface1_dat_w_next_value_ce0 <= 1'd0; + case (builder_state) 1'd1: begin - litedramcore_adr_next_value_ce1 <= 1'd1; end 2'd2: begin end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value_ce1 <= 1'd1; - end + builder_interface1_dat_w_next_value_ce0 <= 1'd1; end endcase end -assign litedramcore_wishbone_adr = wb_bus_adr; -assign litedramcore_wishbone_dat_w = wb_bus_dat_w; -assign wb_bus_dat_r = litedramcore_wishbone_dat_r; -assign litedramcore_wishbone_sel = wb_bus_sel; -assign litedramcore_wishbone_cyc = wb_bus_cyc; -assign litedramcore_wishbone_stb = wb_bus_stb; -assign wb_bus_ack = litedramcore_wishbone_ack; -assign litedramcore_wishbone_we = wb_bus_we; -assign litedramcore_wishbone_cti = wb_bus_cti; -assign litedramcore_wishbone_bte = wb_bus_bte; -assign wb_bus_err = litedramcore_wishbone_err; -assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); -assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; +assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); +assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_done0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_we <= (~interface0_bank_bus_we); + builder_csrbank0_init_done0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we); end end always @(*) begin - csrbank0_init_done0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_re <= interface0_bank_bus_we; + builder_csrbank0_init_done0_re <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we; end end -assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; +assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_error0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_re <= interface0_bank_bus_we; + builder_csrbank0_init_error0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we); end end always @(*) begin - csrbank0_init_error0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_we <= (~interface0_bank_bus_we); + builder_csrbank0_init_error0_re <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; end end -assign csrbank0_init_done0_w = init_done_storage; -assign csrbank0_init_error0_w = init_error_storage; -assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); -assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0]; +assign builder_csrbank0_init_done0_w = main_init_done_storage; +assign builder_csrbank0_init_error0_w = main_init_error_storage; +assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1); +assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - csrbank1_rst0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_rst0_re <= interface1_bank_bus_we; + builder_csrbank1_rst0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - csrbank1_rst0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_rst0_we <= (~interface1_bank_bus_we); + builder_csrbank1_rst0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; end end -assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; +assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_dly_sel0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dly_sel0_we <= (~interface1_bank_bus_we); + builder_csrbank1_dly_sel0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - csrbank1_dly_sel0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dly_sel0_re <= interface1_bank_bus_we; + builder_csrbank1_dly_sel0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we); end end -assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; +assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0]; always @(*) begin - csrbank1_half_sys8x_taps0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we); + builder_csrbank1_half_sys8x_taps0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - csrbank1_half_sys8x_taps0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we; + builder_csrbank1_half_sys8x_taps0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; end end -assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0]; +assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - csrbank1_wlevel_en0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_wlevel_en0_re <= interface1_bank_bus_we; + builder_csrbank1_wlevel_en0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - csrbank1_wlevel_en0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we); + builder_csrbank1_wlevel_en0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we); end end -assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_wlevel_strobe_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we; + main_a7ddrphy_wlevel_strobe_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we; end end always @(*) begin - a7ddrphy_wlevel_strobe_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we); + main_a7ddrphy_wlevel_strobe_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we); end end -assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; end end always @(*) begin - a7ddrphy_rdly_dq_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we); end end -assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_inc_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_inc_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; end end always @(*) begin - a7ddrphy_rdly_dq_inc_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_inc_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we); end end -assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end end -assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_bitslip_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - a7ddrphy_rdly_dq_bitslip_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end end -assign a7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end end -assign a7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_wdly_dq_bitslip_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we); + main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - a7ddrphy_wdly_dq_bitslip_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we; + main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end end -assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0]; +assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_rdphase0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - csrbank1_rdphase0_we <= (~interface1_bank_bus_we); + builder_csrbank1_rdphase0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - csrbank1_rdphase0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - csrbank1_rdphase0_re <= interface1_bank_bus_we; + builder_csrbank1_rdphase0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we); end end -assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0]; +assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_wrphase0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - csrbank1_wrphase0_re <= interface1_bank_bus_we; + builder_csrbank1_wrphase0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - csrbank1_wrphase0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - csrbank1_wrphase0_we <= (~interface1_bank_bus_we); + builder_csrbank1_wrphase0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; end end -assign csrbank1_rst0_w = a7ddrphy_rst_storage; -assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; -assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0]; -assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage; -assign csrbank1_rdphase0_w = a7ddrphy_rdphase_storage[1:0]; -assign csrbank1_wrphase0_w = a7ddrphy_wrphase_storage[1:0]; -assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); -assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; +assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage; +assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0]; +assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0]; +assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage; +assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0]; +assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0]; +assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2); +assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0]; always @(*) begin - csrbank2_dfii_control0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_control0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_control0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_control0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; +assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi0_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi0_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we; end end -assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; +assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector0_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we; + main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - litedramcore_phaseinjector0_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we); + main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[13:0]; +assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[13:0]; always @(*) begin - csrbank2_dfii_pi0_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi0_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi0_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi0_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi0_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin + builder_csrbank2_dfii_pi0_rddata_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi0_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin + builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; +assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi1_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi1_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we; end end -assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; +assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector1_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we); + main_litedramcore_phaseinjector1_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin + main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we; end end always @(*) begin - litedramcore_phaseinjector1_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we; + main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin + main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[13:0]; +assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[13:0]; always @(*) begin - csrbank2_dfii_pi1_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi1_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi1_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi1_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi1_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi1_rddata_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi1_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0]; +assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi2_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi2_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we); end end -assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; +assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector2_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we); + main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - litedramcore_phaseinjector2_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we; + main_litedramcore_phaseinjector2_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[13:0]; +assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[13:0]; always @(*) begin - csrbank2_dfii_pi2_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi2_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi2_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi2_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi2_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin - csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi2_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin - csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi2_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin - csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi2_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin - csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank2_dfii_pi2_rddata_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0]; +assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi3_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin - csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi3_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin - csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we); end end -assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; +assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector3_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin - litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we; + main_litedramcore_phaseinjector3_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we; end end always @(*) begin - litedramcore_phaseinjector3_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin - litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we); + main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[13:0]; +assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[13:0]; always @(*) begin - csrbank2_dfii_pi3_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin - csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi3_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin - csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi3_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin - csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi3_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin - csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi3_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin - csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi3_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin - csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi3_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin - csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi3_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin - csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi3_rddata_re <= builder_interface2_bank_bus_we; end end -assign litedramcore_sel = litedramcore_storage[0]; -assign litedramcore_cke = litedramcore_storage[1]; -assign litedramcore_odt = litedramcore_storage[2]; -assign litedramcore_reset_n = litedramcore_storage[3]; -assign csrbank2_dfii_control0_w = litedramcore_storage[3:0]; -assign litedramcore_phaseinjector0_csrfield_cs = litedramcore_phaseinjector0_command_storage[0]; -assign litedramcore_phaseinjector0_csrfield_we = litedramcore_phaseinjector0_command_storage[1]; -assign litedramcore_phaseinjector0_csrfield_cas = litedramcore_phaseinjector0_command_storage[2]; -assign litedramcore_phaseinjector0_csrfield_ras = litedramcore_phaseinjector0_command_storage[3]; -assign litedramcore_phaseinjector0_csrfield_wren = litedramcore_phaseinjector0_command_storage[4]; -assign litedramcore_phaseinjector0_csrfield_rden = litedramcore_phaseinjector0_command_storage[5]; -assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; -assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0]; -assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0]; -assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0]; -assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_rddata_status[31:0]; -assign litedramcore_phaseinjector0_rddata_we = csrbank2_dfii_pi0_rddata_we; -assign litedramcore_phaseinjector1_csrfield_cs = litedramcore_phaseinjector1_command_storage[0]; -assign litedramcore_phaseinjector1_csrfield_we = litedramcore_phaseinjector1_command_storage[1]; -assign litedramcore_phaseinjector1_csrfield_cas = litedramcore_phaseinjector1_command_storage[2]; -assign litedramcore_phaseinjector1_csrfield_ras = litedramcore_phaseinjector1_command_storage[3]; -assign litedramcore_phaseinjector1_csrfield_wren = litedramcore_phaseinjector1_command_storage[4]; -assign litedramcore_phaseinjector1_csrfield_rden = litedramcore_phaseinjector1_command_storage[5]; -assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0]; -assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[13:0]; -assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0]; -assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0]; -assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_rddata_status[31:0]; -assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata_we; -assign litedramcore_phaseinjector2_csrfield_cs = litedramcore_phaseinjector2_command_storage[0]; -assign litedramcore_phaseinjector2_csrfield_we = litedramcore_phaseinjector2_command_storage[1]; -assign litedramcore_phaseinjector2_csrfield_cas = litedramcore_phaseinjector2_command_storage[2]; -assign litedramcore_phaseinjector2_csrfield_ras = litedramcore_phaseinjector2_command_storage[3]; -assign litedramcore_phaseinjector2_csrfield_wren = litedramcore_phaseinjector2_command_storage[4]; -assign litedramcore_phaseinjector2_csrfield_rden = litedramcore_phaseinjector2_command_storage[5]; -assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0]; -assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[13:0]; -assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0]; -assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0]; -assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_rddata_status[31:0]; -assign litedramcore_phaseinjector2_rddata_we = csrbank2_dfii_pi2_rddata_we; -assign litedramcore_phaseinjector3_csrfield_cs = litedramcore_phaseinjector3_command_storage[0]; -assign litedramcore_phaseinjector3_csrfield_we = litedramcore_phaseinjector3_command_storage[1]; -assign litedramcore_phaseinjector3_csrfield_cas = litedramcore_phaseinjector3_command_storage[2]; -assign litedramcore_phaseinjector3_csrfield_ras = litedramcore_phaseinjector3_command_storage[3]; -assign litedramcore_phaseinjector3_csrfield_wren = litedramcore_phaseinjector3_command_storage[4]; -assign litedramcore_phaseinjector3_csrfield_rden = litedramcore_phaseinjector3_command_storage[5]; -assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0]; -assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[13:0]; -assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0]; -assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0]; -assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_rddata_status[31:0]; -assign litedramcore_phaseinjector3_rddata_we = csrbank2_dfii_pi3_rddata_we; -assign csr_interconnect_adr = litedramcore_adr; -assign csr_interconnect_we = litedramcore_we; -assign csr_interconnect_dat_w = litedramcore_dat_w; -assign litedramcore_dat_r = csr_interconnect_dat_r; -assign interface0_bank_bus_adr = csr_interconnect_adr; -assign interface1_bank_bus_adr = csr_interconnect_adr; -assign interface2_bank_bus_adr = csr_interconnect_adr; -assign interface0_bank_bus_we = csr_interconnect_we; -assign interface1_bank_bus_we = csr_interconnect_we; -assign interface2_bank_bus_we = csr_interconnect_we; -assign interface0_bank_bus_dat_w = csr_interconnect_dat_w; -assign interface1_bank_bus_dat_w = csr_interconnect_dat_w; -assign interface2_bank_bus_dat_w = csr_interconnect_dat_w; -assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); -always @(*) begin - rhs_array_muxed0 <= 1'd0; - case (litedramcore_choose_cmd_grant) +assign main_litedramcore_sel = main_litedramcore_storage[0]; +assign main_litedramcore_cke = main_litedramcore_storage[1]; +assign main_litedramcore_odt = main_litedramcore_storage[2]; +assign main_litedramcore_reset_n = main_litedramcore_storage[3]; +assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0]; +assign main_litedramcore_phaseinjector0_csrfield_cs = main_litedramcore_phaseinjector0_command_storage[0]; +assign main_litedramcore_phaseinjector0_csrfield_we = main_litedramcore_phaseinjector0_command_storage[1]; +assign main_litedramcore_phaseinjector0_csrfield_cas = main_litedramcore_phaseinjector0_command_storage[2]; +assign main_litedramcore_phaseinjector0_csrfield_ras = main_litedramcore_phaseinjector0_command_storage[3]; +assign main_litedramcore_phaseinjector0_csrfield_wren = main_litedramcore_phaseinjector0_command_storage[4]; +assign main_litedramcore_phaseinjector0_csrfield_rden = main_litedramcore_phaseinjector0_command_storage[5]; +assign main_litedramcore_phaseinjector0_csrfield_cs_top = main_litedramcore_phaseinjector0_command_storage[6]; +assign main_litedramcore_phaseinjector0_csrfield_cs_bottom = main_litedramcore_phaseinjector0_command_storage[7]; +assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[7:0]; +assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[13:0]; +assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0]; +assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we; +assign main_litedramcore_phaseinjector1_csrfield_cs = main_litedramcore_phaseinjector1_command_storage[0]; +assign main_litedramcore_phaseinjector1_csrfield_we = main_litedramcore_phaseinjector1_command_storage[1]; +assign main_litedramcore_phaseinjector1_csrfield_cas = main_litedramcore_phaseinjector1_command_storage[2]; +assign main_litedramcore_phaseinjector1_csrfield_ras = main_litedramcore_phaseinjector1_command_storage[3]; +assign main_litedramcore_phaseinjector1_csrfield_wren = main_litedramcore_phaseinjector1_command_storage[4]; +assign main_litedramcore_phaseinjector1_csrfield_rden = main_litedramcore_phaseinjector1_command_storage[5]; +assign main_litedramcore_phaseinjector1_csrfield_cs_top = main_litedramcore_phaseinjector1_command_storage[6]; +assign main_litedramcore_phaseinjector1_csrfield_cs_bottom = main_litedramcore_phaseinjector1_command_storage[7]; +assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[7:0]; +assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[13:0]; +assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0]; +assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we; +assign main_litedramcore_phaseinjector2_csrfield_cs = main_litedramcore_phaseinjector2_command_storage[0]; +assign main_litedramcore_phaseinjector2_csrfield_we = main_litedramcore_phaseinjector2_command_storage[1]; +assign main_litedramcore_phaseinjector2_csrfield_cas = main_litedramcore_phaseinjector2_command_storage[2]; +assign main_litedramcore_phaseinjector2_csrfield_ras = main_litedramcore_phaseinjector2_command_storage[3]; +assign main_litedramcore_phaseinjector2_csrfield_wren = main_litedramcore_phaseinjector2_command_storage[4]; +assign main_litedramcore_phaseinjector2_csrfield_rden = main_litedramcore_phaseinjector2_command_storage[5]; +assign main_litedramcore_phaseinjector2_csrfield_cs_top = main_litedramcore_phaseinjector2_command_storage[6]; +assign main_litedramcore_phaseinjector2_csrfield_cs_bottom = main_litedramcore_phaseinjector2_command_storage[7]; +assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[7:0]; +assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[13:0]; +assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0]; +assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we; +assign main_litedramcore_phaseinjector3_csrfield_cs = main_litedramcore_phaseinjector3_command_storage[0]; +assign main_litedramcore_phaseinjector3_csrfield_we = main_litedramcore_phaseinjector3_command_storage[1]; +assign main_litedramcore_phaseinjector3_csrfield_cas = main_litedramcore_phaseinjector3_command_storage[2]; +assign main_litedramcore_phaseinjector3_csrfield_ras = main_litedramcore_phaseinjector3_command_storage[3]; +assign main_litedramcore_phaseinjector3_csrfield_wren = main_litedramcore_phaseinjector3_command_storage[4]; +assign main_litedramcore_phaseinjector3_csrfield_rden = main_litedramcore_phaseinjector3_command_storage[5]; +assign main_litedramcore_phaseinjector3_csrfield_cs_top = main_litedramcore_phaseinjector3_command_storage[6]; +assign main_litedramcore_phaseinjector3_csrfield_cs_bottom = main_litedramcore_phaseinjector3_command_storage[7]; +assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[7:0]; +assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[13:0]; +assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0]; +assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we; +assign builder_adr = builder_interface1_adr; +assign builder_we = builder_interface1_we; +assign builder_dat_w = builder_interface1_dat_w; +assign builder_interface1_dat_r = builder_dat_r; +assign builder_interface0_bank_bus_adr = builder_adr; +assign builder_interface1_bank_bus_adr = builder_adr; +assign builder_interface2_bank_bus_adr = builder_adr; +assign builder_interface0_bank_bus_we = builder_we; +assign builder_interface1_bank_bus_we = builder_we; +assign builder_interface2_bank_bus_we = builder_we; +assign builder_interface0_bank_bus_dat_w = builder_dat_w; +assign builder_interface1_bank_bus_dat_w = builder_dat_w; +assign builder_interface2_bank_bus_dat_w = builder_dat_w; +assign builder_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); +always @(*) begin + builder_rhs_self0 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[0]; end 1'd1: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[1]; end 2'd2: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[2]; end 2'd3: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[3]; end 3'd4: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[4]; end 3'd5: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[5]; end 3'd6: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[6]; end default: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[7]; end endcase end always @(*) begin - rhs_array_muxed1 <= 14'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self1 <= 14'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine6_cmd_payload_a; end default: begin - rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase end always @(*) begin - rhs_array_muxed2 <= 3'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self2 <= 3'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine6_cmd_payload_ba; end default: begin - rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase end always @(*) begin - rhs_array_muxed3 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self3 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase end always @(*) begin - rhs_array_muxed4 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self4 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase end always @(*) begin - rhs_array_muxed5 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self5 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase end always @(*) begin - t_array_muxed0 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_t_self0 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine6_cmd_payload_cas; end default: begin - t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase end always @(*) begin - t_array_muxed1 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_t_self1 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine6_cmd_payload_ras; end default: begin - t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase end always @(*) begin - t_array_muxed2 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_t_self2 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine6_cmd_payload_we; end default: begin - t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed6 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self6 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[0]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[0]; end 1'd1: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[1]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[1]; end 2'd2: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[2]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[2]; end 2'd3: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[3]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[3]; end 3'd4: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[4]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[4]; end 3'd5: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[5]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[5]; end 3'd6: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[6]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[6]; end default: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[7]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[7]; end endcase end always @(*) begin - rhs_array_muxed7 <= 14'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self7 <= 14'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine6_cmd_payload_a; end default: begin - rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase end always @(*) begin - rhs_array_muxed8 <= 3'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self8 <= 3'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine6_cmd_payload_ba; end default: begin - rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase end always @(*) begin - rhs_array_muxed9 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self9 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase end always @(*) begin - rhs_array_muxed10 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self10 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase end always @(*) begin - rhs_array_muxed11 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self11 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase end always @(*) begin - t_array_muxed3 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_t_self3 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine6_cmd_payload_cas; end default: begin - t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase end always @(*) begin - t_array_muxed4 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_t_self4 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine6_cmd_payload_ras; end default: begin - t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase end always @(*) begin - t_array_muxed5 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_t_self5 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine6_cmd_payload_we; end default: begin - t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed12 <= 21'd0; - case (litedramcore_roundrobin0_grant) + builder_rhs_self12 <= 21'd0; + case (builder_roundrobin0_grant) default: begin - rhs_array_muxed12 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self12 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed13 <= 1'd0; - case (litedramcore_roundrobin0_grant) + builder_rhs_self13 <= 1'd0; + case (builder_roundrobin0_grant) default: begin - rhs_array_muxed13 <= user_port_cmd_payload_we; + builder_rhs_self13 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed14 <= 1'd0; - case (litedramcore_roundrobin0_grant) + builder_rhs_self14 <= 1'd0; + case (builder_roundrobin0_grant) default: begin - rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed15 <= 21'd0; - case (litedramcore_roundrobin1_grant) + builder_rhs_self15 <= 21'd0; + case (builder_roundrobin1_grant) default: begin - rhs_array_muxed15 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self15 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed16 <= 1'd0; - case (litedramcore_roundrobin1_grant) + builder_rhs_self16 <= 1'd0; + case (builder_roundrobin1_grant) default: begin - rhs_array_muxed16 <= user_port_cmd_payload_we; + builder_rhs_self16 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed17 <= 1'd0; - case (litedramcore_roundrobin1_grant) + builder_rhs_self17 <= 1'd0; + case (builder_roundrobin1_grant) default: begin - rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed18 <= 21'd0; - case (litedramcore_roundrobin2_grant) + builder_rhs_self18 <= 21'd0; + case (builder_roundrobin2_grant) default: begin - rhs_array_muxed18 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self18 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed19 <= 1'd0; - case (litedramcore_roundrobin2_grant) + builder_rhs_self19 <= 1'd0; + case (builder_roundrobin2_grant) default: begin - rhs_array_muxed19 <= user_port_cmd_payload_we; + builder_rhs_self19 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed20 <= 1'd0; - case (litedramcore_roundrobin2_grant) + builder_rhs_self20 <= 1'd0; + case (builder_roundrobin2_grant) default: begin - rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed21 <= 21'd0; - case (litedramcore_roundrobin3_grant) + builder_rhs_self21 <= 21'd0; + case (builder_roundrobin3_grant) default: begin - rhs_array_muxed21 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self21 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed22 <= 1'd0; - case (litedramcore_roundrobin3_grant) + builder_rhs_self22 <= 1'd0; + case (builder_roundrobin3_grant) default: begin - rhs_array_muxed22 <= user_port_cmd_payload_we; + builder_rhs_self22 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed23 <= 1'd0; - case (litedramcore_roundrobin3_grant) + builder_rhs_self23 <= 1'd0; + case (builder_roundrobin3_grant) default: begin - rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed24 <= 21'd0; - case (litedramcore_roundrobin4_grant) + builder_rhs_self24 <= 21'd0; + case (builder_roundrobin4_grant) default: begin - rhs_array_muxed24 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self24 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed25 <= 1'd0; - case (litedramcore_roundrobin4_grant) + builder_rhs_self25 <= 1'd0; + case (builder_roundrobin4_grant) default: begin - rhs_array_muxed25 <= user_port_cmd_payload_we; + builder_rhs_self25 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed26 <= 1'd0; - case (litedramcore_roundrobin4_grant) + builder_rhs_self26 <= 1'd0; + case (builder_roundrobin4_grant) default: begin - rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed27 <= 21'd0; - case (litedramcore_roundrobin5_grant) + builder_rhs_self27 <= 21'd0; + case (builder_roundrobin5_grant) default: begin - rhs_array_muxed27 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self27 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed28 <= 1'd0; - case (litedramcore_roundrobin5_grant) + builder_rhs_self28 <= 1'd0; + case (builder_roundrobin5_grant) default: begin - rhs_array_muxed28 <= user_port_cmd_payload_we; + builder_rhs_self28 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed29 <= 1'd0; - case (litedramcore_roundrobin5_grant) + builder_rhs_self29 <= 1'd0; + case (builder_roundrobin5_grant) default: begin - rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed30 <= 21'd0; - case (litedramcore_roundrobin6_grant) + builder_rhs_self30 <= 21'd0; + case (builder_roundrobin6_grant) default: begin - rhs_array_muxed30 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self30 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed31 <= 1'd0; - case (litedramcore_roundrobin6_grant) + builder_rhs_self31 <= 1'd0; + case (builder_roundrobin6_grant) default: begin - rhs_array_muxed31 <= user_port_cmd_payload_we; + builder_rhs_self31 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed32 <= 1'd0; - case (litedramcore_roundrobin6_grant) + builder_rhs_self32 <= 1'd0; + case (builder_roundrobin6_grant) default: begin - rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed33 <= 21'd0; - case (litedramcore_roundrobin7_grant) + builder_rhs_self33 <= 21'd0; + case (builder_roundrobin7_grant) default: begin - rhs_array_muxed33 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self33 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed34 <= 1'd0; - case (litedramcore_roundrobin7_grant) + builder_rhs_self34 <= 1'd0; + case (builder_roundrobin7_grant) default: begin - rhs_array_muxed34 <= user_port_cmd_payload_we; + builder_rhs_self34 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed35 <= 1'd0; - case (litedramcore_roundrobin7_grant) + builder_rhs_self35 <= 1'd0; + case (builder_roundrobin7_grant) default: begin - rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - array_muxed0 <= 3'd0; - case (litedramcore_steerer_sel0) + builder_self0 <= 3'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed0 <= litedramcore_nop_ba[2:0]; + builder_self0 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed0 <= litedramcore_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed1 <= 14'd0; - case (litedramcore_steerer_sel0) + builder_self1 <= 14'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed1 <= litedramcore_nop_a; + builder_self1 <= main_litedramcore_nop_a; end 1'd1: begin - array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a; + builder_self1 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed1 <= litedramcore_choose_req_cmd_payload_a; + builder_self1 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed1 <= litedramcore_cmd_payload_a; + builder_self1 <= main_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed2 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self2 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed2 <= 1'd0; + builder_self2 <= 1'd0; end 1'd1: begin - array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + builder_self2 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + builder_self2 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + builder_self2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed3 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self3 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed3 <= 1'd0; + builder_self3 <= 1'd0; end 1'd1: begin - array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + builder_self3 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + builder_self3 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + builder_self3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed4 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self4 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed4 <= 1'd0; + builder_self4 <= 1'd0; end 1'd1: begin - array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + builder_self4 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + builder_self4 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + builder_self4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed5 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self5 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed5 <= 1'd0; + builder_self5 <= 1'd0; end 1'd1: begin - array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + builder_self5 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + builder_self5 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + builder_self5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed6 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self6 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed6 <= 1'd0; + builder_self6 <= 1'd0; end 1'd1: begin - array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + builder_self6 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + builder_self6 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + builder_self6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase end always @(*) begin - array_muxed7 <= 3'd0; - case (litedramcore_steerer_sel1) + builder_self7 <= 3'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed7 <= litedramcore_nop_ba[2:0]; + builder_self7 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed7 <= litedramcore_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed8 <= 14'd0; - case (litedramcore_steerer_sel1) + builder_self8 <= 14'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed8 <= litedramcore_nop_a; + builder_self8 <= main_litedramcore_nop_a; end 1'd1: begin - array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a; + builder_self8 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed8 <= litedramcore_choose_req_cmd_payload_a; + builder_self8 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed8 <= litedramcore_cmd_payload_a; + builder_self8 <= main_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed9 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self9 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed9 <= 1'd0; + builder_self9 <= 1'd0; end 1'd1: begin - array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + builder_self9 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + builder_self9 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + builder_self9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed10 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self10 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed10 <= 1'd0; + builder_self10 <= 1'd0; end 1'd1: begin - array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + builder_self10 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + builder_self10 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + builder_self10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed11 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self11 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed11 <= 1'd0; + builder_self11 <= 1'd0; end 1'd1: begin - array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + builder_self11 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + builder_self11 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + builder_self11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed12 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self12 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed12 <= 1'd0; + builder_self12 <= 1'd0; end 1'd1: begin - array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + builder_self12 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + builder_self12 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + builder_self12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed13 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self13 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed13 <= 1'd0; + builder_self13 <= 1'd0; end 1'd1: begin - array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + builder_self13 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + builder_self13 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + builder_self13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase end always @(*) begin - array_muxed14 <= 3'd0; - case (litedramcore_steerer_sel2) + builder_self14 <= 3'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed14 <= litedramcore_nop_ba[2:0]; + builder_self14 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed14 <= litedramcore_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed15 <= 14'd0; - case (litedramcore_steerer_sel2) + builder_self15 <= 14'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed15 <= litedramcore_nop_a; + builder_self15 <= main_litedramcore_nop_a; end 1'd1: begin - array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a; + builder_self15 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed15 <= litedramcore_choose_req_cmd_payload_a; + builder_self15 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed15 <= litedramcore_cmd_payload_a; + builder_self15 <= main_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed16 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self16 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed16 <= 1'd0; + builder_self16 <= 1'd0; end 1'd1: begin - array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + builder_self16 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + builder_self16 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + builder_self16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed17 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self17 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed17 <= 1'd0; + builder_self17 <= 1'd0; end 1'd1: begin - array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + builder_self17 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + builder_self17 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + builder_self17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed18 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self18 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed18 <= 1'd0; + builder_self18 <= 1'd0; end 1'd1: begin - array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + builder_self18 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + builder_self18 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + builder_self18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed19 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self19 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed19 <= 1'd0; + builder_self19 <= 1'd0; end 1'd1: begin - array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + builder_self19 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + builder_self19 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + builder_self19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed20 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self20 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed20 <= 1'd0; + builder_self20 <= 1'd0; end 1'd1: begin - array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + builder_self20 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + builder_self20 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + builder_self20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase end always @(*) begin - array_muxed21 <= 3'd0; - case (litedramcore_steerer_sel3) + builder_self21 <= 3'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed21 <= litedramcore_nop_ba[2:0]; + builder_self21 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed21 <= litedramcore_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed22 <= 14'd0; - case (litedramcore_steerer_sel3) + builder_self22 <= 14'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed22 <= litedramcore_nop_a; + builder_self22 <= main_litedramcore_nop_a; end 1'd1: begin - array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a; + builder_self22 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed22 <= litedramcore_choose_req_cmd_payload_a; + builder_self22 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed22 <= litedramcore_cmd_payload_a; + builder_self22 <= main_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed23 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self23 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed23 <= 1'd0; + builder_self23 <= 1'd0; end 1'd1: begin - array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + builder_self23 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + builder_self23 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + builder_self23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed24 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self24 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed24 <= 1'd0; + builder_self24 <= 1'd0; end 1'd1: begin - array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + builder_self24 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + builder_self24 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + builder_self24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed25 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self25 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed25 <= 1'd0; + builder_self25 <= 1'd0; end 1'd1: begin - array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + builder_self25 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + builder_self25 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + builder_self25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed26 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self26 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed26 <= 1'd0; + builder_self26 <= 1'd0; end 1'd1: begin - array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + builder_self26 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + builder_self26 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + builder_self26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed27 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self27 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed27 <= 1'd0; + builder_self27 <= 1'd0; end 1'd1: begin - array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + builder_self27 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + builder_self27 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + builder_self27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase end -assign xilinxasyncresetsynchronizerimpl0 = (~locked); -assign xilinxasyncresetsynchronizerimpl1 = (~locked); -assign xilinxasyncresetsynchronizerimpl2 = (~locked); -assign xilinxasyncresetsynchronizerimpl3 = (~locked); +assign builder_xilinxasyncresetsynchronizerimpl0_async_reset = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl1_async_reset = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl2_async_reset = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl3_async_reset = (~main_locked); //------------------------------------------------------------------------------ @@ -11983,1044 +12398,1044 @@ assign xilinxasyncresetsynchronizerimpl3 = (~locked); //------------------------------------------------------------------------------ always @(posedge iodelay_clk) begin - if ((reset_counter != 1'd0)) begin - reset_counter <= (reset_counter - 1'd1); + if ((main_reset_counter != 1'd0)) begin + main_reset_counter <= (main_reset_counter - 1'd1); end else begin - ic_reset <= 1'd0; + main_ic_reset <= 1'd0; end if (iodelay_rst) begin - reset_counter <= 4'd15; - ic_reset <= 1'd1; + main_reset_counter <= 4'd15; + main_ic_reset <= 1'd1; end end always @(posedge sys_clk) begin - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline; - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; - a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1); + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline; + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; + main_a7ddrphy_dqspattern_o1 <= main_a7ddrphy_dqspattern_o0; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value0 <= (main_a7ddrphy_bitslip0_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value0 <= 3'd7; end - a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1); + main_a7ddrphy_bitslip0_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip0_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value0 <= (main_a7ddrphy_bitslip1_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value0 <= 3'd7; end - a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1); + main_a7ddrphy_bitslip1_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip1_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value1 <= (main_a7ddrphy_bitslip0_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value1 <= 3'd7; end - a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1); + main_a7ddrphy_bitslip0_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[2], main_a7ddrphy_dfi_p3_wrdata_mask[0], main_a7ddrphy_dfi_p2_wrdata_mask[2], main_a7ddrphy_dfi_p2_wrdata_mask[0], main_a7ddrphy_dfi_p1_wrdata_mask[2], main_a7ddrphy_dfi_p1_wrdata_mask[0], main_a7ddrphy_dfi_p0_wrdata_mask[2], main_a7ddrphy_dfi_p0_wrdata_mask[0]}, main_a7ddrphy_bitslip0_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value1 <= (main_a7ddrphy_bitslip1_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value1 <= 3'd7; end - a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]}; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1); + main_a7ddrphy_bitslip1_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[3], main_a7ddrphy_dfi_p3_wrdata_mask[1], main_a7ddrphy_dfi_p2_wrdata_mask[3], main_a7ddrphy_dfi_p2_wrdata_mask[1], main_a7ddrphy_dfi_p1_wrdata_mask[3], main_a7ddrphy_dfi_p1_wrdata_mask[1], main_a7ddrphy_dfi_p0_wrdata_mask[3], main_a7ddrphy_dfi_p0_wrdata_mask[1]}, main_a7ddrphy_bitslip1_r1[15:8]}; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dq_oe_delay_tappeddelayline; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value2 <= (main_a7ddrphy_bitslip0_value2 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value2 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value2 <= 3'd7; end - a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1); + main_a7ddrphy_bitslip0_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[16], main_a7ddrphy_dfi_p3_wrdata[0], main_a7ddrphy_dfi_p2_wrdata[16], main_a7ddrphy_dfi_p2_wrdata[0], main_a7ddrphy_dfi_p1_wrdata[16], main_a7ddrphy_dfi_p1_wrdata[0], main_a7ddrphy_dfi_p0_wrdata[16], main_a7ddrphy_dfi_p0_wrdata[0]}, main_a7ddrphy_bitslip0_r2[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value3 <= (main_a7ddrphy_bitslip0_value3 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value3 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value3 <= 3'd7; end - a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1); + main_a7ddrphy_bitslip0_r3 <= {main_a7ddrphy_bitslip03, main_a7ddrphy_bitslip0_r3[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value2 <= (main_a7ddrphy_bitslip1_value2 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value2 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value2 <= 3'd7; end - a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1); + main_a7ddrphy_bitslip1_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[17], main_a7ddrphy_dfi_p3_wrdata[1], main_a7ddrphy_dfi_p2_wrdata[17], main_a7ddrphy_dfi_p2_wrdata[1], main_a7ddrphy_dfi_p1_wrdata[17], main_a7ddrphy_dfi_p1_wrdata[1], main_a7ddrphy_dfi_p0_wrdata[17], main_a7ddrphy_dfi_p0_wrdata[1]}, main_a7ddrphy_bitslip1_r2[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value3 <= (main_a7ddrphy_bitslip1_value3 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value3 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value3 <= 3'd7; end - a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1); + main_a7ddrphy_bitslip1_r3 <= {main_a7ddrphy_bitslip13, main_a7ddrphy_bitslip1_r3[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip2_value0 <= (main_a7ddrphy_bitslip2_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip2_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip2_value0 <= 3'd7; end - a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1); + main_a7ddrphy_bitslip2_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[18], main_a7ddrphy_dfi_p3_wrdata[2], main_a7ddrphy_dfi_p2_wrdata[18], main_a7ddrphy_dfi_p2_wrdata[2], main_a7ddrphy_dfi_p1_wrdata[18], main_a7ddrphy_dfi_p1_wrdata[2], main_a7ddrphy_dfi_p0_wrdata[18], main_a7ddrphy_dfi_p0_wrdata[2]}, main_a7ddrphy_bitslip2_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip2_value1 <= (main_a7ddrphy_bitslip2_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip2_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip2_value1 <= 3'd7; end - a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1); + main_a7ddrphy_bitslip2_r1 <= {main_a7ddrphy_bitslip21, main_a7ddrphy_bitslip2_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip3_value0 <= (main_a7ddrphy_bitslip3_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip3_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip3_value0 <= 3'd7; end - a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1); + main_a7ddrphy_bitslip3_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[19], main_a7ddrphy_dfi_p3_wrdata[3], main_a7ddrphy_dfi_p2_wrdata[19], main_a7ddrphy_dfi_p2_wrdata[3], main_a7ddrphy_dfi_p1_wrdata[19], main_a7ddrphy_dfi_p1_wrdata[3], main_a7ddrphy_dfi_p0_wrdata[19], main_a7ddrphy_dfi_p0_wrdata[3]}, main_a7ddrphy_bitslip3_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip3_value1 <= (main_a7ddrphy_bitslip3_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip3_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip3_value1 <= 3'd7; end - a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1); + main_a7ddrphy_bitslip3_r1 <= {main_a7ddrphy_bitslip31, main_a7ddrphy_bitslip3_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip4_value0 <= (main_a7ddrphy_bitslip4_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip4_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip4_value0 <= 3'd7; end - a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1); + main_a7ddrphy_bitslip4_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[20], main_a7ddrphy_dfi_p3_wrdata[4], main_a7ddrphy_dfi_p2_wrdata[20], main_a7ddrphy_dfi_p2_wrdata[4], main_a7ddrphy_dfi_p1_wrdata[20], main_a7ddrphy_dfi_p1_wrdata[4], main_a7ddrphy_dfi_p0_wrdata[20], main_a7ddrphy_dfi_p0_wrdata[4]}, main_a7ddrphy_bitslip4_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip4_value1 <= (main_a7ddrphy_bitslip4_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip4_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip4_value1 <= 3'd7; end - a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1); + main_a7ddrphy_bitslip4_r1 <= {main_a7ddrphy_bitslip41, main_a7ddrphy_bitslip4_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip5_value0 <= (main_a7ddrphy_bitslip5_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip5_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip5_value0 <= 3'd7; end - a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1); + main_a7ddrphy_bitslip5_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[21], main_a7ddrphy_dfi_p3_wrdata[5], main_a7ddrphy_dfi_p2_wrdata[21], main_a7ddrphy_dfi_p2_wrdata[5], main_a7ddrphy_dfi_p1_wrdata[21], main_a7ddrphy_dfi_p1_wrdata[5], main_a7ddrphy_dfi_p0_wrdata[21], main_a7ddrphy_dfi_p0_wrdata[5]}, main_a7ddrphy_bitslip5_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip5_value1 <= (main_a7ddrphy_bitslip5_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip5_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip5_value1 <= 3'd7; end - a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1); + main_a7ddrphy_bitslip5_r1 <= {main_a7ddrphy_bitslip51, main_a7ddrphy_bitslip5_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip6_value0 <= (main_a7ddrphy_bitslip6_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip6_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip6_value0 <= 3'd7; end - a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1); + main_a7ddrphy_bitslip6_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[22], main_a7ddrphy_dfi_p3_wrdata[6], main_a7ddrphy_dfi_p2_wrdata[22], main_a7ddrphy_dfi_p2_wrdata[6], main_a7ddrphy_dfi_p1_wrdata[22], main_a7ddrphy_dfi_p1_wrdata[6], main_a7ddrphy_dfi_p0_wrdata[22], main_a7ddrphy_dfi_p0_wrdata[6]}, main_a7ddrphy_bitslip6_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip6_value1 <= (main_a7ddrphy_bitslip6_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip6_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip6_value1 <= 3'd7; end - a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1); + main_a7ddrphy_bitslip6_r1 <= {main_a7ddrphy_bitslip61, main_a7ddrphy_bitslip6_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip7_value0 <= (main_a7ddrphy_bitslip7_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip7_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip7_value0 <= 3'd7; end - a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1); + main_a7ddrphy_bitslip7_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[23], main_a7ddrphy_dfi_p3_wrdata[7], main_a7ddrphy_dfi_p2_wrdata[23], main_a7ddrphy_dfi_p2_wrdata[7], main_a7ddrphy_dfi_p1_wrdata[23], main_a7ddrphy_dfi_p1_wrdata[7], main_a7ddrphy_dfi_p0_wrdata[23], main_a7ddrphy_dfi_p0_wrdata[7]}, main_a7ddrphy_bitslip7_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip7_value1 <= (main_a7ddrphy_bitslip7_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip7_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip7_value1 <= 3'd7; end - a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1); + main_a7ddrphy_bitslip7_r1 <= {main_a7ddrphy_bitslip71, main_a7ddrphy_bitslip7_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip8_value0 <= (main_a7ddrphy_bitslip8_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip8_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip8_value0 <= 3'd7; end - a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1); + main_a7ddrphy_bitslip8_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[24], main_a7ddrphy_dfi_p3_wrdata[8], main_a7ddrphy_dfi_p2_wrdata[24], main_a7ddrphy_dfi_p2_wrdata[8], main_a7ddrphy_dfi_p1_wrdata[24], main_a7ddrphy_dfi_p1_wrdata[8], main_a7ddrphy_dfi_p0_wrdata[24], main_a7ddrphy_dfi_p0_wrdata[8]}, main_a7ddrphy_bitslip8_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip8_value1 <= (main_a7ddrphy_bitslip8_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip8_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip8_value1 <= 3'd7; end - a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1); + main_a7ddrphy_bitslip8_r1 <= {main_a7ddrphy_bitslip81, main_a7ddrphy_bitslip8_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip9_value0 <= (main_a7ddrphy_bitslip9_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip9_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip9_value0 <= 3'd7; end - a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1); + main_a7ddrphy_bitslip9_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[25], main_a7ddrphy_dfi_p3_wrdata[9], main_a7ddrphy_dfi_p2_wrdata[25], main_a7ddrphy_dfi_p2_wrdata[9], main_a7ddrphy_dfi_p1_wrdata[25], main_a7ddrphy_dfi_p1_wrdata[9], main_a7ddrphy_dfi_p0_wrdata[25], main_a7ddrphy_dfi_p0_wrdata[9]}, main_a7ddrphy_bitslip9_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip9_value1 <= (main_a7ddrphy_bitslip9_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip9_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip9_value1 <= 3'd7; end - a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1); + main_a7ddrphy_bitslip9_r1 <= {main_a7ddrphy_bitslip91, main_a7ddrphy_bitslip9_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip10_value0 <= (main_a7ddrphy_bitslip10_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip10_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip10_value0 <= 3'd7; end - a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1); + main_a7ddrphy_bitslip10_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[26], main_a7ddrphy_dfi_p3_wrdata[10], main_a7ddrphy_dfi_p2_wrdata[26], main_a7ddrphy_dfi_p2_wrdata[10], main_a7ddrphy_dfi_p1_wrdata[26], main_a7ddrphy_dfi_p1_wrdata[10], main_a7ddrphy_dfi_p0_wrdata[26], main_a7ddrphy_dfi_p0_wrdata[10]}, main_a7ddrphy_bitslip10_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip10_value1 <= (main_a7ddrphy_bitslip10_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip10_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip10_value1 <= 3'd7; end - a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1); + main_a7ddrphy_bitslip10_r1 <= {main_a7ddrphy_bitslip101, main_a7ddrphy_bitslip10_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip11_value0 <= (main_a7ddrphy_bitslip11_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip11_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip11_value0 <= 3'd7; end - a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1); + main_a7ddrphy_bitslip11_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[27], main_a7ddrphy_dfi_p3_wrdata[11], main_a7ddrphy_dfi_p2_wrdata[27], main_a7ddrphy_dfi_p2_wrdata[11], main_a7ddrphy_dfi_p1_wrdata[27], main_a7ddrphy_dfi_p1_wrdata[11], main_a7ddrphy_dfi_p0_wrdata[27], main_a7ddrphy_dfi_p0_wrdata[11]}, main_a7ddrphy_bitslip11_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip11_value1 <= (main_a7ddrphy_bitslip11_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip11_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip11_value1 <= 3'd7; end - a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1); + main_a7ddrphy_bitslip11_r1 <= {main_a7ddrphy_bitslip111, main_a7ddrphy_bitslip11_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip12_value0 <= (main_a7ddrphy_bitslip12_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip12_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip12_value0 <= 3'd7; end - a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1); + main_a7ddrphy_bitslip12_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[28], main_a7ddrphy_dfi_p3_wrdata[12], main_a7ddrphy_dfi_p2_wrdata[28], main_a7ddrphy_dfi_p2_wrdata[12], main_a7ddrphy_dfi_p1_wrdata[28], main_a7ddrphy_dfi_p1_wrdata[12], main_a7ddrphy_dfi_p0_wrdata[28], main_a7ddrphy_dfi_p0_wrdata[12]}, main_a7ddrphy_bitslip12_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip12_value1 <= (main_a7ddrphy_bitslip12_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip12_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip12_value1 <= 3'd7; end - a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1); + main_a7ddrphy_bitslip12_r1 <= {main_a7ddrphy_bitslip121, main_a7ddrphy_bitslip12_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip13_value0 <= (main_a7ddrphy_bitslip13_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip13_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip13_value0 <= 3'd7; end - a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1); + main_a7ddrphy_bitslip13_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[29], main_a7ddrphy_dfi_p3_wrdata[13], main_a7ddrphy_dfi_p2_wrdata[29], main_a7ddrphy_dfi_p2_wrdata[13], main_a7ddrphy_dfi_p1_wrdata[29], main_a7ddrphy_dfi_p1_wrdata[13], main_a7ddrphy_dfi_p0_wrdata[29], main_a7ddrphy_dfi_p0_wrdata[13]}, main_a7ddrphy_bitslip13_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip13_value1 <= (main_a7ddrphy_bitslip13_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip13_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip13_value1 <= 3'd7; end - a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1); + main_a7ddrphy_bitslip13_r1 <= {main_a7ddrphy_bitslip131, main_a7ddrphy_bitslip13_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip14_value0 <= (main_a7ddrphy_bitslip14_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip14_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip14_value0 <= 3'd7; end - a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1); + main_a7ddrphy_bitslip14_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[30], main_a7ddrphy_dfi_p3_wrdata[14], main_a7ddrphy_dfi_p2_wrdata[30], main_a7ddrphy_dfi_p2_wrdata[14], main_a7ddrphy_dfi_p1_wrdata[30], main_a7ddrphy_dfi_p1_wrdata[14], main_a7ddrphy_dfi_p0_wrdata[30], main_a7ddrphy_dfi_p0_wrdata[14]}, main_a7ddrphy_bitslip14_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip14_value1 <= (main_a7ddrphy_bitslip14_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip14_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip14_value1 <= 3'd7; end - a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1); + main_a7ddrphy_bitslip14_r1 <= {main_a7ddrphy_bitslip141, main_a7ddrphy_bitslip14_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip15_value0 <= (main_a7ddrphy_bitslip15_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip15_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip15_value0 <= 3'd7; end - a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1); + main_a7ddrphy_bitslip15_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[31], main_a7ddrphy_dfi_p3_wrdata[15], main_a7ddrphy_dfi_p2_wrdata[31], main_a7ddrphy_dfi_p2_wrdata[15], main_a7ddrphy_dfi_p1_wrdata[31], main_a7ddrphy_dfi_p1_wrdata[15], main_a7ddrphy_dfi_p0_wrdata[31], main_a7ddrphy_dfi_p0_wrdata[15]}, main_a7ddrphy_bitslip15_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip15_value1 <= (main_a7ddrphy_bitslip15_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip15_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip15_value1 <= 3'd7; end - a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]}; - a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en); - a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0; - a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1; - a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2; - a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3; - a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4; - a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5; - a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6; - a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en); - a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0; - a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1; - if (litedramcore_csr_dfi_p0_rddata_valid) begin - litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata; + main_a7ddrphy_bitslip15_r1 <= {main_a7ddrphy_bitslip151, main_a7ddrphy_bitslip15_r1[15:8]}; + main_a7ddrphy_rddata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_rddata_en | main_a7ddrphy_dfi_p1_rddata_en) | main_a7ddrphy_dfi_p2_rddata_en) | main_a7ddrphy_dfi_p3_rddata_en); + main_a7ddrphy_rddata_en_tappeddelayline1 <= main_a7ddrphy_rddata_en_tappeddelayline0; + main_a7ddrphy_rddata_en_tappeddelayline2 <= main_a7ddrphy_rddata_en_tappeddelayline1; + main_a7ddrphy_rddata_en_tappeddelayline3 <= main_a7ddrphy_rddata_en_tappeddelayline2; + main_a7ddrphy_rddata_en_tappeddelayline4 <= main_a7ddrphy_rddata_en_tappeddelayline3; + main_a7ddrphy_rddata_en_tappeddelayline5 <= main_a7ddrphy_rddata_en_tappeddelayline4; + main_a7ddrphy_rddata_en_tappeddelayline6 <= main_a7ddrphy_rddata_en_tappeddelayline5; + main_a7ddrphy_rddata_en_tappeddelayline7 <= main_a7ddrphy_rddata_en_tappeddelayline6; + main_a7ddrphy_wrdata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_wrdata_en | main_a7ddrphy_dfi_p1_wrdata_en) | main_a7ddrphy_dfi_p2_wrdata_en) | main_a7ddrphy_dfi_p3_wrdata_en); + main_a7ddrphy_wrdata_en_tappeddelayline1 <= main_a7ddrphy_wrdata_en_tappeddelayline0; + main_a7ddrphy_wrdata_en_tappeddelayline2 <= main_a7ddrphy_wrdata_en_tappeddelayline1; + if (main_litedramcore_csr_dfi_p0_rddata_valid) begin + main_litedramcore_phaseinjector0_rddata_status <= main_litedramcore_csr_dfi_p0_rddata; end - if (litedramcore_csr_dfi_p1_rddata_valid) begin - litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata; + if (main_litedramcore_csr_dfi_p1_rddata_valid) begin + main_litedramcore_phaseinjector1_rddata_status <= main_litedramcore_csr_dfi_p1_rddata; end - if (litedramcore_csr_dfi_p2_rddata_valid) begin - litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata; + if (main_litedramcore_csr_dfi_p2_rddata_valid) begin + main_litedramcore_phaseinjector2_rddata_status <= main_litedramcore_csr_dfi_p2_rddata; end - if (litedramcore_csr_dfi_p3_rddata_valid) begin - litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata; - end - if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin - litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); + if (main_litedramcore_csr_dfi_p3_rddata_valid) begin + main_litedramcore_phaseinjector3_rddata_status <= main_litedramcore_csr_dfi_p3_rddata; + end + if ((main_litedramcore_timer_wait & (~main_litedramcore_timer_done0))) begin + main_litedramcore_timer_count1 <= (main_litedramcore_timer_count1 - 1'd1); end else begin - litedramcore_timer_count1 <= 10'd781; + main_litedramcore_timer_count1 <= 10'd781; end - litedramcore_postponer_req_o <= 1'd0; - if (litedramcore_postponer_req_i) begin - litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); - if ((litedramcore_postponer_count == 1'd0)) begin - litedramcore_postponer_count <= 1'd0; - litedramcore_postponer_req_o <= 1'd1; - end + main_litedramcore_postponer_req_o <= 1'd0; + if (main_litedramcore_postponer_req_i) begin + main_litedramcore_postponer_count <= (main_litedramcore_postponer_count - 1'd1); + if ((main_litedramcore_postponer_count == 1'd0)) begin + main_litedramcore_postponer_count <= 1'd0; + main_litedramcore_postponer_req_o <= 1'd1; + end end - if (litedramcore_sequencer_start0) begin - litedramcore_sequencer_count <= 1'd0; - end else begin - if (litedramcore_sequencer_done1) begin - if ((litedramcore_sequencer_count != 1'd0)) begin - litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); - end - end - end - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_sequencer_done1 <= 1'd0; - if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_sequencer_counter == 2'd3)) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd1; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd0; - end - if ((litedramcore_sequencer_counter == 6'd35)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_sequencer_done1 <= 1'd1; - end - if ((litedramcore_sequencer_counter == 6'd35)) begin - litedramcore_sequencer_counter <= 1'd0; - end else begin - if ((litedramcore_sequencer_counter != 1'd0)) begin - litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1); + if (main_litedramcore_sequencer_start0) begin + main_litedramcore_sequencer_count <= 1'd0; + end else begin + if (main_litedramcore_sequencer_done1) begin + if ((main_litedramcore_sequencer_count != 1'd0)) begin + main_litedramcore_sequencer_count <= (main_litedramcore_sequencer_count - 1'd1); + end + end + end + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd0; + if ((main_litedramcore_sequencer_start1 & (main_litedramcore_sequencer_trigger == 1'd0))) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_sequencer_trigger == 2'd3)) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd1; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd0; + end + if ((main_litedramcore_sequencer_trigger == 6'd35)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd1; + end + if ((main_litedramcore_sequencer_trigger == 6'd35)) begin + main_litedramcore_sequencer_trigger <= 1'd0; + end else begin + if ((main_litedramcore_sequencer_trigger != 1'd0)) begin + main_litedramcore_sequencer_trigger <= (main_litedramcore_sequencer_trigger + 1'd1); end else begin - if (litedramcore_sequencer_start1) begin - litedramcore_sequencer_counter <= 1'd1; + if (main_litedramcore_sequencer_start1) begin + main_litedramcore_sequencer_trigger <= 1'd1; end end end - if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin - litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); + if ((main_litedramcore_zqcs_timer_wait & (~main_litedramcore_zqcs_timer_done0))) begin + main_litedramcore_zqcs_timer_count1 <= (main_litedramcore_zqcs_timer_count1 - 1'd1); end else begin - litedramcore_zqcs_timer_count1 <= 27'd99999999; - end - litedramcore_zqcs_executer_done <= 1'd0; - if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 2'd3)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 5'd19)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_zqcs_executer_done <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 5'd19)) begin - litedramcore_zqcs_executer_counter <= 1'd0; + main_litedramcore_zqcs_timer_count1 <= 27'd99999999; + end + main_litedramcore_zqcs_executer_done <= 1'd0; + if ((main_litedramcore_zqcs_executer_start & (main_litedramcore_zqcs_executer_trigger == 1'd0))) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_trigger == 2'd3)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_trigger == 5'd19)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_zqcs_executer_done <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_trigger == 5'd19)) begin + main_litedramcore_zqcs_executer_trigger <= 1'd0; end else begin - if ((litedramcore_zqcs_executer_counter != 1'd0)) begin - litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1); + if ((main_litedramcore_zqcs_executer_trigger != 1'd0)) begin + main_litedramcore_zqcs_executer_trigger <= (main_litedramcore_zqcs_executer_trigger + 1'd1); end else begin - if (litedramcore_zqcs_executer_start) begin - litedramcore_zqcs_executer_counter <= 1'd1; + if (main_litedramcore_zqcs_executer_start) begin + main_litedramcore_zqcs_executer_trigger <= 1'd1; end end end - litedramcore_refresher_state <= litedramcore_refresher_next_state; - if (litedramcore_bankmachine0_row_close) begin - litedramcore_bankmachine0_row_opened <= 1'd0; + builder_refresher_state <= builder_refresher_next_state; + if (main_litedramcore_bankmachine0_row_close) begin + main_litedramcore_bankmachine0_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine0_row_open) begin - litedramcore_bankmachine0_row_opened <= 1'd1; - litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[20:7]; + if (main_litedramcore_bankmachine0_row_open) begin + main_litedramcore_bankmachine0_row_opened <= 1'd1; + main_litedramcore_bankmachine0_row <= main_litedramcore_bankmachine0_source_source_payload_addr[20:7]; end end - if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin - litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1); + if (((main_litedramcore_bankmachine0_syncfifo0_we & main_litedramcore_bankmachine0_syncfifo0_writable) & (~main_litedramcore_bankmachine0_replace))) begin + main_litedramcore_bankmachine0_produce <= (main_litedramcore_bankmachine0_produce + 1'd1); end - if (litedramcore_bankmachine0_do_read) begin - litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1); + if (main_litedramcore_bankmachine0_do_read) begin + main_litedramcore_bankmachine0_consume <= (main_litedramcore_bankmachine0_consume + 1'd1); end - if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin - if ((~litedramcore_bankmachine0_do_read)) begin - litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1); + if (((main_litedramcore_bankmachine0_syncfifo0_we & main_litedramcore_bankmachine0_syncfifo0_writable) & (~main_litedramcore_bankmachine0_replace))) begin + if ((~main_litedramcore_bankmachine0_do_read)) begin + main_litedramcore_bankmachine0_level <= (main_litedramcore_bankmachine0_level + 1'd1); end end else begin - if (litedramcore_bankmachine0_do_read) begin - litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1); + if (main_litedramcore_bankmachine0_do_read) begin + main_litedramcore_bankmachine0_level <= (main_litedramcore_bankmachine0_level - 1'd1); end end - if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin - litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid; - litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first; - litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last; - litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we; - litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine0_pipe_valid_source_valid) | main_litedramcore_bankmachine0_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine0_pipe_valid_source_valid <= main_litedramcore_bankmachine0_pipe_valid_sink_valid; + main_litedramcore_bankmachine0_pipe_valid_source_first <= main_litedramcore_bankmachine0_pipe_valid_sink_first; + main_litedramcore_bankmachine0_pipe_valid_source_last <= main_litedramcore_bankmachine0_pipe_valid_sink_last; + main_litedramcore_bankmachine0_pipe_valid_source_payload_we <= main_litedramcore_bankmachine0_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine0_twtpcon_valid) begin - litedramcore_bankmachine0_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine0_twtpcon_valid) begin + main_litedramcore_bankmachine0_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine0_twtpcon_ready)) begin - litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_twtpcon_ready)) begin + main_litedramcore_bankmachine0_twtpcon_count <= (main_litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine0_trccon_valid) begin - litedramcore_bankmachine0_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine0_trccon_valid) begin + main_litedramcore_bankmachine0_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine0_trccon_ready <= 1'd1; + main_litedramcore_bankmachine0_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine0_trccon_ready <= 1'd0; + main_litedramcore_bankmachine0_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine0_trccon_ready)) begin - litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); - if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin - litedramcore_bankmachine0_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_trccon_ready)) begin + main_litedramcore_bankmachine0_trccon_count <= (main_litedramcore_bankmachine0_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine0_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine0_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine0_trascon_valid) begin - litedramcore_bankmachine0_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine0_trascon_valid) begin + main_litedramcore_bankmachine0_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine0_trascon_ready <= 1'd1; + main_litedramcore_bankmachine0_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine0_trascon_ready <= 1'd0; + main_litedramcore_bankmachine0_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); - if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin - litedramcore_bankmachine0_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_trascon_count <= (main_litedramcore_bankmachine0_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine0_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine0_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state; - if (litedramcore_bankmachine1_row_close) begin - litedramcore_bankmachine1_row_opened <= 1'd0; + builder_bankmachine0_state <= builder_bankmachine0_next_state; + if (main_litedramcore_bankmachine1_row_close) begin + main_litedramcore_bankmachine1_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine1_row_open) begin - litedramcore_bankmachine1_row_opened <= 1'd1; - litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[20:7]; + if (main_litedramcore_bankmachine1_row_open) begin + main_litedramcore_bankmachine1_row_opened <= 1'd1; + main_litedramcore_bankmachine1_row <= main_litedramcore_bankmachine1_source_source_payload_addr[20:7]; end end - if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin - litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1); + if (((main_litedramcore_bankmachine1_syncfifo1_we & main_litedramcore_bankmachine1_syncfifo1_writable) & (~main_litedramcore_bankmachine1_replace))) begin + main_litedramcore_bankmachine1_produce <= (main_litedramcore_bankmachine1_produce + 1'd1); end - if (litedramcore_bankmachine1_do_read) begin - litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1); + if (main_litedramcore_bankmachine1_do_read) begin + main_litedramcore_bankmachine1_consume <= (main_litedramcore_bankmachine1_consume + 1'd1); end - if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin - if ((~litedramcore_bankmachine1_do_read)) begin - litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1); + if (((main_litedramcore_bankmachine1_syncfifo1_we & main_litedramcore_bankmachine1_syncfifo1_writable) & (~main_litedramcore_bankmachine1_replace))) begin + if ((~main_litedramcore_bankmachine1_do_read)) begin + main_litedramcore_bankmachine1_level <= (main_litedramcore_bankmachine1_level + 1'd1); end end else begin - if (litedramcore_bankmachine1_do_read) begin - litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1); + if (main_litedramcore_bankmachine1_do_read) begin + main_litedramcore_bankmachine1_level <= (main_litedramcore_bankmachine1_level - 1'd1); end end - if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin - litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid; - litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first; - litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last; - litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we; - litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine1_pipe_valid_source_valid) | main_litedramcore_bankmachine1_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine1_pipe_valid_source_valid <= main_litedramcore_bankmachine1_pipe_valid_sink_valid; + main_litedramcore_bankmachine1_pipe_valid_source_first <= main_litedramcore_bankmachine1_pipe_valid_sink_first; + main_litedramcore_bankmachine1_pipe_valid_source_last <= main_litedramcore_bankmachine1_pipe_valid_sink_last; + main_litedramcore_bankmachine1_pipe_valid_source_payload_we <= main_litedramcore_bankmachine1_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine1_twtpcon_valid) begin - litedramcore_bankmachine1_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine1_twtpcon_valid) begin + main_litedramcore_bankmachine1_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine1_twtpcon_ready)) begin - litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_twtpcon_ready)) begin + main_litedramcore_bankmachine1_twtpcon_count <= (main_litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine1_trccon_valid) begin - litedramcore_bankmachine1_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine1_trccon_valid) begin + main_litedramcore_bankmachine1_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine1_trccon_ready <= 1'd1; + main_litedramcore_bankmachine1_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine1_trccon_ready <= 1'd0; + main_litedramcore_bankmachine1_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine1_trccon_ready)) begin - litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); - if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin - litedramcore_bankmachine1_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_trccon_ready)) begin + main_litedramcore_bankmachine1_trccon_count <= (main_litedramcore_bankmachine1_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine1_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine1_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine1_trascon_valid) begin - litedramcore_bankmachine1_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine1_trascon_valid) begin + main_litedramcore_bankmachine1_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine1_trascon_ready <= 1'd1; + main_litedramcore_bankmachine1_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine1_trascon_ready <= 1'd0; + main_litedramcore_bankmachine1_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); - if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin - litedramcore_bankmachine1_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_trascon_count <= (main_litedramcore_bankmachine1_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine1_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine1_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state; - if (litedramcore_bankmachine2_row_close) begin - litedramcore_bankmachine2_row_opened <= 1'd0; + builder_bankmachine1_state <= builder_bankmachine1_next_state; + if (main_litedramcore_bankmachine2_row_close) begin + main_litedramcore_bankmachine2_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine2_row_open) begin - litedramcore_bankmachine2_row_opened <= 1'd1; - litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[20:7]; + if (main_litedramcore_bankmachine2_row_open) begin + main_litedramcore_bankmachine2_row_opened <= 1'd1; + main_litedramcore_bankmachine2_row <= main_litedramcore_bankmachine2_source_source_payload_addr[20:7]; end end - if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin - litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1); + if (((main_litedramcore_bankmachine2_syncfifo2_we & main_litedramcore_bankmachine2_syncfifo2_writable) & (~main_litedramcore_bankmachine2_replace))) begin + main_litedramcore_bankmachine2_produce <= (main_litedramcore_bankmachine2_produce + 1'd1); end - if (litedramcore_bankmachine2_do_read) begin - litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1); + if (main_litedramcore_bankmachine2_do_read) begin + main_litedramcore_bankmachine2_consume <= (main_litedramcore_bankmachine2_consume + 1'd1); end - if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin - if ((~litedramcore_bankmachine2_do_read)) begin - litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1); + if (((main_litedramcore_bankmachine2_syncfifo2_we & main_litedramcore_bankmachine2_syncfifo2_writable) & (~main_litedramcore_bankmachine2_replace))) begin + if ((~main_litedramcore_bankmachine2_do_read)) begin + main_litedramcore_bankmachine2_level <= (main_litedramcore_bankmachine2_level + 1'd1); end end else begin - if (litedramcore_bankmachine2_do_read) begin - litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1); + if (main_litedramcore_bankmachine2_do_read) begin + main_litedramcore_bankmachine2_level <= (main_litedramcore_bankmachine2_level - 1'd1); end end - if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin - litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid; - litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first; - litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last; - litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we; - litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine2_pipe_valid_source_valid) | main_litedramcore_bankmachine2_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine2_pipe_valid_source_valid <= main_litedramcore_bankmachine2_pipe_valid_sink_valid; + main_litedramcore_bankmachine2_pipe_valid_source_first <= main_litedramcore_bankmachine2_pipe_valid_sink_first; + main_litedramcore_bankmachine2_pipe_valid_source_last <= main_litedramcore_bankmachine2_pipe_valid_sink_last; + main_litedramcore_bankmachine2_pipe_valid_source_payload_we <= main_litedramcore_bankmachine2_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine2_twtpcon_valid) begin - litedramcore_bankmachine2_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine2_twtpcon_valid) begin + main_litedramcore_bankmachine2_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine2_twtpcon_ready)) begin - litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_twtpcon_ready)) begin + main_litedramcore_bankmachine2_twtpcon_count <= (main_litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine2_trccon_valid) begin - litedramcore_bankmachine2_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine2_trccon_valid) begin + main_litedramcore_bankmachine2_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine2_trccon_ready <= 1'd1; + main_litedramcore_bankmachine2_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine2_trccon_ready <= 1'd0; + main_litedramcore_bankmachine2_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine2_trccon_ready)) begin - litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); - if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin - litedramcore_bankmachine2_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_trccon_ready)) begin + main_litedramcore_bankmachine2_trccon_count <= (main_litedramcore_bankmachine2_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine2_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine2_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine2_trascon_valid) begin - litedramcore_bankmachine2_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine2_trascon_valid) begin + main_litedramcore_bankmachine2_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine2_trascon_ready <= 1'd1; + main_litedramcore_bankmachine2_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine2_trascon_ready <= 1'd0; + main_litedramcore_bankmachine2_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); - if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin - litedramcore_bankmachine2_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_trascon_count <= (main_litedramcore_bankmachine2_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine2_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine2_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state; - if (litedramcore_bankmachine3_row_close) begin - litedramcore_bankmachine3_row_opened <= 1'd0; + builder_bankmachine2_state <= builder_bankmachine2_next_state; + if (main_litedramcore_bankmachine3_row_close) begin + main_litedramcore_bankmachine3_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine3_row_open) begin - litedramcore_bankmachine3_row_opened <= 1'd1; - litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[20:7]; + if (main_litedramcore_bankmachine3_row_open) begin + main_litedramcore_bankmachine3_row_opened <= 1'd1; + main_litedramcore_bankmachine3_row <= main_litedramcore_bankmachine3_source_source_payload_addr[20:7]; end end - if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin - litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1); + if (((main_litedramcore_bankmachine3_syncfifo3_we & main_litedramcore_bankmachine3_syncfifo3_writable) & (~main_litedramcore_bankmachine3_replace))) begin + main_litedramcore_bankmachine3_produce <= (main_litedramcore_bankmachine3_produce + 1'd1); end - if (litedramcore_bankmachine3_do_read) begin - litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1); + if (main_litedramcore_bankmachine3_do_read) begin + main_litedramcore_bankmachine3_consume <= (main_litedramcore_bankmachine3_consume + 1'd1); end - if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin - if ((~litedramcore_bankmachine3_do_read)) begin - litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1); + if (((main_litedramcore_bankmachine3_syncfifo3_we & main_litedramcore_bankmachine3_syncfifo3_writable) & (~main_litedramcore_bankmachine3_replace))) begin + if ((~main_litedramcore_bankmachine3_do_read)) begin + main_litedramcore_bankmachine3_level <= (main_litedramcore_bankmachine3_level + 1'd1); end end else begin - if (litedramcore_bankmachine3_do_read) begin - litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1); + if (main_litedramcore_bankmachine3_do_read) begin + main_litedramcore_bankmachine3_level <= (main_litedramcore_bankmachine3_level - 1'd1); end end - if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin - litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid; - litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first; - litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last; - litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we; - litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine3_pipe_valid_source_valid) | main_litedramcore_bankmachine3_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine3_pipe_valid_source_valid <= main_litedramcore_bankmachine3_pipe_valid_sink_valid; + main_litedramcore_bankmachine3_pipe_valid_source_first <= main_litedramcore_bankmachine3_pipe_valid_sink_first; + main_litedramcore_bankmachine3_pipe_valid_source_last <= main_litedramcore_bankmachine3_pipe_valid_sink_last; + main_litedramcore_bankmachine3_pipe_valid_source_payload_we <= main_litedramcore_bankmachine3_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine3_twtpcon_valid) begin - litedramcore_bankmachine3_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine3_twtpcon_valid) begin + main_litedramcore_bankmachine3_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine3_twtpcon_ready)) begin - litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_twtpcon_ready)) begin + main_litedramcore_bankmachine3_twtpcon_count <= (main_litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine3_trccon_valid) begin - litedramcore_bankmachine3_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine3_trccon_valid) begin + main_litedramcore_bankmachine3_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine3_trccon_ready <= 1'd1; + main_litedramcore_bankmachine3_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine3_trccon_ready <= 1'd0; + main_litedramcore_bankmachine3_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine3_trccon_ready)) begin - litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); - if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin - litedramcore_bankmachine3_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_trccon_ready)) begin + main_litedramcore_bankmachine3_trccon_count <= (main_litedramcore_bankmachine3_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine3_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine3_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine3_trascon_valid) begin - litedramcore_bankmachine3_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine3_trascon_valid) begin + main_litedramcore_bankmachine3_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine3_trascon_ready <= 1'd1; + main_litedramcore_bankmachine3_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine3_trascon_ready <= 1'd0; + main_litedramcore_bankmachine3_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); - if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin - litedramcore_bankmachine3_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_trascon_count <= (main_litedramcore_bankmachine3_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine3_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine3_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state; - if (litedramcore_bankmachine4_row_close) begin - litedramcore_bankmachine4_row_opened <= 1'd0; + builder_bankmachine3_state <= builder_bankmachine3_next_state; + if (main_litedramcore_bankmachine4_row_close) begin + main_litedramcore_bankmachine4_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine4_row_open) begin - litedramcore_bankmachine4_row_opened <= 1'd1; - litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[20:7]; + if (main_litedramcore_bankmachine4_row_open) begin + main_litedramcore_bankmachine4_row_opened <= 1'd1; + main_litedramcore_bankmachine4_row <= main_litedramcore_bankmachine4_source_source_payload_addr[20:7]; end end - if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin - litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1); + if (((main_litedramcore_bankmachine4_syncfifo4_we & main_litedramcore_bankmachine4_syncfifo4_writable) & (~main_litedramcore_bankmachine4_replace))) begin + main_litedramcore_bankmachine4_produce <= (main_litedramcore_bankmachine4_produce + 1'd1); end - if (litedramcore_bankmachine4_do_read) begin - litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1); + if (main_litedramcore_bankmachine4_do_read) begin + main_litedramcore_bankmachine4_consume <= (main_litedramcore_bankmachine4_consume + 1'd1); end - if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin - if ((~litedramcore_bankmachine4_do_read)) begin - litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1); + if (((main_litedramcore_bankmachine4_syncfifo4_we & main_litedramcore_bankmachine4_syncfifo4_writable) & (~main_litedramcore_bankmachine4_replace))) begin + if ((~main_litedramcore_bankmachine4_do_read)) begin + main_litedramcore_bankmachine4_level <= (main_litedramcore_bankmachine4_level + 1'd1); end end else begin - if (litedramcore_bankmachine4_do_read) begin - litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1); + if (main_litedramcore_bankmachine4_do_read) begin + main_litedramcore_bankmachine4_level <= (main_litedramcore_bankmachine4_level - 1'd1); end end - if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin - litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid; - litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first; - litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last; - litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we; - litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine4_pipe_valid_source_valid) | main_litedramcore_bankmachine4_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine4_pipe_valid_source_valid <= main_litedramcore_bankmachine4_pipe_valid_sink_valid; + main_litedramcore_bankmachine4_pipe_valid_source_first <= main_litedramcore_bankmachine4_pipe_valid_sink_first; + main_litedramcore_bankmachine4_pipe_valid_source_last <= main_litedramcore_bankmachine4_pipe_valid_sink_last; + main_litedramcore_bankmachine4_pipe_valid_source_payload_we <= main_litedramcore_bankmachine4_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine4_twtpcon_valid) begin - litedramcore_bankmachine4_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine4_twtpcon_valid) begin + main_litedramcore_bankmachine4_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine4_twtpcon_ready)) begin - litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_twtpcon_ready)) begin + main_litedramcore_bankmachine4_twtpcon_count <= (main_litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine4_trccon_valid) begin - litedramcore_bankmachine4_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine4_trccon_valid) begin + main_litedramcore_bankmachine4_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine4_trccon_ready <= 1'd1; + main_litedramcore_bankmachine4_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine4_trccon_ready <= 1'd0; + main_litedramcore_bankmachine4_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine4_trccon_ready)) begin - litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); - if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin - litedramcore_bankmachine4_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_trccon_ready)) begin + main_litedramcore_bankmachine4_trccon_count <= (main_litedramcore_bankmachine4_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine4_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine4_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine4_trascon_valid) begin - litedramcore_bankmachine4_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine4_trascon_valid) begin + main_litedramcore_bankmachine4_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine4_trascon_ready <= 1'd1; + main_litedramcore_bankmachine4_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine4_trascon_ready <= 1'd0; + main_litedramcore_bankmachine4_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); - if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin - litedramcore_bankmachine4_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_trascon_count <= (main_litedramcore_bankmachine4_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine4_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine4_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state; - if (litedramcore_bankmachine5_row_close) begin - litedramcore_bankmachine5_row_opened <= 1'd0; + builder_bankmachine4_state <= builder_bankmachine4_next_state; + if (main_litedramcore_bankmachine5_row_close) begin + main_litedramcore_bankmachine5_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine5_row_open) begin - litedramcore_bankmachine5_row_opened <= 1'd1; - litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[20:7]; + if (main_litedramcore_bankmachine5_row_open) begin + main_litedramcore_bankmachine5_row_opened <= 1'd1; + main_litedramcore_bankmachine5_row <= main_litedramcore_bankmachine5_source_source_payload_addr[20:7]; end end - if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin - litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1); + if (((main_litedramcore_bankmachine5_syncfifo5_we & main_litedramcore_bankmachine5_syncfifo5_writable) & (~main_litedramcore_bankmachine5_replace))) begin + main_litedramcore_bankmachine5_produce <= (main_litedramcore_bankmachine5_produce + 1'd1); end - if (litedramcore_bankmachine5_do_read) begin - litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1); + if (main_litedramcore_bankmachine5_do_read) begin + main_litedramcore_bankmachine5_consume <= (main_litedramcore_bankmachine5_consume + 1'd1); end - if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin - if ((~litedramcore_bankmachine5_do_read)) begin - litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1); + if (((main_litedramcore_bankmachine5_syncfifo5_we & main_litedramcore_bankmachine5_syncfifo5_writable) & (~main_litedramcore_bankmachine5_replace))) begin + if ((~main_litedramcore_bankmachine5_do_read)) begin + main_litedramcore_bankmachine5_level <= (main_litedramcore_bankmachine5_level + 1'd1); end end else begin - if (litedramcore_bankmachine5_do_read) begin - litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1); + if (main_litedramcore_bankmachine5_do_read) begin + main_litedramcore_bankmachine5_level <= (main_litedramcore_bankmachine5_level - 1'd1); end end - if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin - litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid; - litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first; - litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last; - litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we; - litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine5_pipe_valid_source_valid) | main_litedramcore_bankmachine5_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine5_pipe_valid_source_valid <= main_litedramcore_bankmachine5_pipe_valid_sink_valid; + main_litedramcore_bankmachine5_pipe_valid_source_first <= main_litedramcore_bankmachine5_pipe_valid_sink_first; + main_litedramcore_bankmachine5_pipe_valid_source_last <= main_litedramcore_bankmachine5_pipe_valid_sink_last; + main_litedramcore_bankmachine5_pipe_valid_source_payload_we <= main_litedramcore_bankmachine5_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine5_twtpcon_valid) begin - litedramcore_bankmachine5_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine5_twtpcon_valid) begin + main_litedramcore_bankmachine5_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine5_twtpcon_ready)) begin - litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_twtpcon_ready)) begin + main_litedramcore_bankmachine5_twtpcon_count <= (main_litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine5_trccon_valid) begin - litedramcore_bankmachine5_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine5_trccon_valid) begin + main_litedramcore_bankmachine5_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine5_trccon_ready <= 1'd1; + main_litedramcore_bankmachine5_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine5_trccon_ready <= 1'd0; + main_litedramcore_bankmachine5_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine5_trccon_ready)) begin - litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); - if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin - litedramcore_bankmachine5_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_trccon_ready)) begin + main_litedramcore_bankmachine5_trccon_count <= (main_litedramcore_bankmachine5_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine5_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine5_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine5_trascon_valid) begin - litedramcore_bankmachine5_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine5_trascon_valid) begin + main_litedramcore_bankmachine5_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine5_trascon_ready <= 1'd1; + main_litedramcore_bankmachine5_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine5_trascon_ready <= 1'd0; + main_litedramcore_bankmachine5_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); - if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin - litedramcore_bankmachine5_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_trascon_count <= (main_litedramcore_bankmachine5_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine5_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine5_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state; - if (litedramcore_bankmachine6_row_close) begin - litedramcore_bankmachine6_row_opened <= 1'd0; + builder_bankmachine5_state <= builder_bankmachine5_next_state; + if (main_litedramcore_bankmachine6_row_close) begin + main_litedramcore_bankmachine6_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine6_row_open) begin - litedramcore_bankmachine6_row_opened <= 1'd1; - litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[20:7]; + if (main_litedramcore_bankmachine6_row_open) begin + main_litedramcore_bankmachine6_row_opened <= 1'd1; + main_litedramcore_bankmachine6_row <= main_litedramcore_bankmachine6_source_source_payload_addr[20:7]; end end - if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin - litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1); + if (((main_litedramcore_bankmachine6_syncfifo6_we & main_litedramcore_bankmachine6_syncfifo6_writable) & (~main_litedramcore_bankmachine6_replace))) begin + main_litedramcore_bankmachine6_produce <= (main_litedramcore_bankmachine6_produce + 1'd1); end - if (litedramcore_bankmachine6_do_read) begin - litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1); + if (main_litedramcore_bankmachine6_do_read) begin + main_litedramcore_bankmachine6_consume <= (main_litedramcore_bankmachine6_consume + 1'd1); end - if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin - if ((~litedramcore_bankmachine6_do_read)) begin - litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1); + if (((main_litedramcore_bankmachine6_syncfifo6_we & main_litedramcore_bankmachine6_syncfifo6_writable) & (~main_litedramcore_bankmachine6_replace))) begin + if ((~main_litedramcore_bankmachine6_do_read)) begin + main_litedramcore_bankmachine6_level <= (main_litedramcore_bankmachine6_level + 1'd1); end end else begin - if (litedramcore_bankmachine6_do_read) begin - litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1); + if (main_litedramcore_bankmachine6_do_read) begin + main_litedramcore_bankmachine6_level <= (main_litedramcore_bankmachine6_level - 1'd1); end end - if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin - litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid; - litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first; - litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last; - litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we; - litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine6_pipe_valid_source_valid) | main_litedramcore_bankmachine6_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine6_pipe_valid_source_valid <= main_litedramcore_bankmachine6_pipe_valid_sink_valid; + main_litedramcore_bankmachine6_pipe_valid_source_first <= main_litedramcore_bankmachine6_pipe_valid_sink_first; + main_litedramcore_bankmachine6_pipe_valid_source_last <= main_litedramcore_bankmachine6_pipe_valid_sink_last; + main_litedramcore_bankmachine6_pipe_valid_source_payload_we <= main_litedramcore_bankmachine6_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine6_twtpcon_valid) begin - litedramcore_bankmachine6_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine6_twtpcon_valid) begin + main_litedramcore_bankmachine6_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine6_twtpcon_ready)) begin - litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_twtpcon_ready)) begin + main_litedramcore_bankmachine6_twtpcon_count <= (main_litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine6_trccon_valid) begin - litedramcore_bankmachine6_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine6_trccon_valid) begin + main_litedramcore_bankmachine6_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine6_trccon_ready <= 1'd1; + main_litedramcore_bankmachine6_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine6_trccon_ready <= 1'd0; + main_litedramcore_bankmachine6_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine6_trccon_ready)) begin - litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); - if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin - litedramcore_bankmachine6_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_trccon_ready)) begin + main_litedramcore_bankmachine6_trccon_count <= (main_litedramcore_bankmachine6_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine6_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine6_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine6_trascon_valid) begin - litedramcore_bankmachine6_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine6_trascon_valid) begin + main_litedramcore_bankmachine6_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine6_trascon_ready <= 1'd1; + main_litedramcore_bankmachine6_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine6_trascon_ready <= 1'd0; + main_litedramcore_bankmachine6_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); - if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin - litedramcore_bankmachine6_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_trascon_count <= (main_litedramcore_bankmachine6_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine6_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine6_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state; - if (litedramcore_bankmachine7_row_close) begin - litedramcore_bankmachine7_row_opened <= 1'd0; + builder_bankmachine6_state <= builder_bankmachine6_next_state; + if (main_litedramcore_bankmachine7_row_close) begin + main_litedramcore_bankmachine7_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine7_row_open) begin - litedramcore_bankmachine7_row_opened <= 1'd1; - litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[20:7]; + if (main_litedramcore_bankmachine7_row_open) begin + main_litedramcore_bankmachine7_row_opened <= 1'd1; + main_litedramcore_bankmachine7_row <= main_litedramcore_bankmachine7_source_source_payload_addr[20:7]; end end - if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin - litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1); + if (((main_litedramcore_bankmachine7_syncfifo7_we & main_litedramcore_bankmachine7_syncfifo7_writable) & (~main_litedramcore_bankmachine7_replace))) begin + main_litedramcore_bankmachine7_produce <= (main_litedramcore_bankmachine7_produce + 1'd1); end - if (litedramcore_bankmachine7_do_read) begin - litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1); + if (main_litedramcore_bankmachine7_do_read) begin + main_litedramcore_bankmachine7_consume <= (main_litedramcore_bankmachine7_consume + 1'd1); end - if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin - if ((~litedramcore_bankmachine7_do_read)) begin - litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1); + if (((main_litedramcore_bankmachine7_syncfifo7_we & main_litedramcore_bankmachine7_syncfifo7_writable) & (~main_litedramcore_bankmachine7_replace))) begin + if ((~main_litedramcore_bankmachine7_do_read)) begin + main_litedramcore_bankmachine7_level <= (main_litedramcore_bankmachine7_level + 1'd1); end end else begin - if (litedramcore_bankmachine7_do_read) begin - litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1); + if (main_litedramcore_bankmachine7_do_read) begin + main_litedramcore_bankmachine7_level <= (main_litedramcore_bankmachine7_level - 1'd1); end end - if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin - litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid; - litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first; - litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last; - litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we; - litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine7_pipe_valid_source_valid) | main_litedramcore_bankmachine7_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine7_pipe_valid_source_valid <= main_litedramcore_bankmachine7_pipe_valid_sink_valid; + main_litedramcore_bankmachine7_pipe_valid_source_first <= main_litedramcore_bankmachine7_pipe_valid_sink_first; + main_litedramcore_bankmachine7_pipe_valid_source_last <= main_litedramcore_bankmachine7_pipe_valid_sink_last; + main_litedramcore_bankmachine7_pipe_valid_source_payload_we <= main_litedramcore_bankmachine7_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine7_twtpcon_valid) begin - litedramcore_bankmachine7_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine7_twtpcon_valid) begin + main_litedramcore_bankmachine7_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine7_twtpcon_ready)) begin - litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_twtpcon_ready)) begin + main_litedramcore_bankmachine7_twtpcon_count <= (main_litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine7_trccon_valid) begin - litedramcore_bankmachine7_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine7_trccon_valid) begin + main_litedramcore_bankmachine7_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine7_trccon_ready <= 1'd1; + main_litedramcore_bankmachine7_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine7_trccon_ready <= 1'd0; + main_litedramcore_bankmachine7_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine7_trccon_ready)) begin - litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); - if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin - litedramcore_bankmachine7_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_trccon_ready)) begin + main_litedramcore_bankmachine7_trccon_count <= (main_litedramcore_bankmachine7_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine7_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine7_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine7_trascon_valid) begin - litedramcore_bankmachine7_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine7_trascon_valid) begin + main_litedramcore_bankmachine7_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine7_trascon_ready <= 1'd1; + main_litedramcore_bankmachine7_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine7_trascon_ready <= 1'd0; + main_litedramcore_bankmachine7_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); - if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin - litedramcore_bankmachine7_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_trascon_count <= (main_litedramcore_bankmachine7_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine7_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine7_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state; - if ((~litedramcore_en0)) begin - litedramcore_time0 <= 5'd31; + builder_bankmachine7_state <= builder_bankmachine7_next_state; + if ((~main_litedramcore_en0)) begin + main_litedramcore_time0 <= 5'd31; end else begin - if ((~litedramcore_max_time0)) begin - litedramcore_time0 <= (litedramcore_time0 - 1'd1); + if ((~main_litedramcore_max_time0)) begin + main_litedramcore_time0 <= (main_litedramcore_time0 - 1'd1); end end - if ((~litedramcore_en1)) begin - litedramcore_time1 <= 4'd15; + if ((~main_litedramcore_en1)) begin + main_litedramcore_time1 <= 4'd15; end else begin - if ((~litedramcore_max_time1)) begin - litedramcore_time1 <= (litedramcore_time1 - 1'd1); + if ((~main_litedramcore_max_time1)) begin + main_litedramcore_time1 <= (main_litedramcore_time1 - 1'd1); end end - if (litedramcore_choose_cmd_ce) begin - case (litedramcore_choose_cmd_grant) + if (main_litedramcore_choose_cmd_ce) begin + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end end end @@ -13030,26 +13445,26 @@ always @(posedge sys_clk) begin end end 1'd1: begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end end end @@ -13059,26 +13474,26 @@ always @(posedge sys_clk) begin end end 2'd2: begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end end end @@ -13088,26 +13503,26 @@ always @(posedge sys_clk) begin end end 2'd3: begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end end end @@ -13117,26 +13532,26 @@ always @(posedge sys_clk) begin end end 3'd4: begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end end end @@ -13146,26 +13561,26 @@ always @(posedge sys_clk) begin end end 3'd5: begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end end end @@ -13175,26 +13590,26 @@ always @(posedge sys_clk) begin end end 3'd6: begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end end end @@ -13204,26 +13619,26 @@ always @(posedge sys_clk) begin end end 3'd7: begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end end end @@ -13234,29 +13649,29 @@ always @(posedge sys_clk) begin end endcase end - if (litedramcore_choose_req_ce) begin - case (litedramcore_choose_req_grant) + if (main_litedramcore_choose_req_ce) begin + case (main_litedramcore_choose_req_grant) 1'd0: begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end end end @@ -13266,26 +13681,26 @@ always @(posedge sys_clk) begin end end 1'd1: begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end end end @@ -13295,26 +13710,26 @@ always @(posedge sys_clk) begin end end 2'd2: begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end end end @@ -13324,26 +13739,26 @@ always @(posedge sys_clk) begin end end 2'd3: begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end end end @@ -13353,26 +13768,26 @@ always @(posedge sys_clk) begin end end 3'd4: begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end end end @@ -13382,26 +13797,26 @@ always @(posedge sys_clk) begin end end 3'd5: begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end end end @@ -13411,26 +13826,26 @@ always @(posedge sys_clk) begin end end 3'd6: begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end end end @@ -13440,26 +13855,26 @@ always @(posedge sys_clk) begin end end 3'd7: begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end end end @@ -13470,644 +13885,644 @@ always @(posedge sys_clk) begin end endcase end - litedramcore_dfi_p0_cs_n <= 1'd0; - litedramcore_dfi_p0_bank <= array_muxed0; - litedramcore_dfi_p0_address <= array_muxed1; - litedramcore_dfi_p0_cas_n <= (~array_muxed2); - litedramcore_dfi_p0_ras_n <= (~array_muxed3); - litedramcore_dfi_p0_we_n <= (~array_muxed4); - litedramcore_dfi_p0_rddata_en <= array_muxed5; - litedramcore_dfi_p0_wrdata_en <= array_muxed6; - litedramcore_dfi_p1_cs_n <= 1'd0; - litedramcore_dfi_p1_bank <= array_muxed7; - litedramcore_dfi_p1_address <= array_muxed8; - litedramcore_dfi_p1_cas_n <= (~array_muxed9); - litedramcore_dfi_p1_ras_n <= (~array_muxed10); - litedramcore_dfi_p1_we_n <= (~array_muxed11); - litedramcore_dfi_p1_rddata_en <= array_muxed12; - litedramcore_dfi_p1_wrdata_en <= array_muxed13; - litedramcore_dfi_p2_cs_n <= 1'd0; - litedramcore_dfi_p2_bank <= array_muxed14; - litedramcore_dfi_p2_address <= array_muxed15; - litedramcore_dfi_p2_cas_n <= (~array_muxed16); - litedramcore_dfi_p2_ras_n <= (~array_muxed17); - litedramcore_dfi_p2_we_n <= (~array_muxed18); - litedramcore_dfi_p2_rddata_en <= array_muxed19; - litedramcore_dfi_p2_wrdata_en <= array_muxed20; - litedramcore_dfi_p3_cs_n <= 1'd0; - litedramcore_dfi_p3_bank <= array_muxed21; - litedramcore_dfi_p3_address <= array_muxed22; - litedramcore_dfi_p3_cas_n <= (~array_muxed23); - litedramcore_dfi_p3_ras_n <= (~array_muxed24); - litedramcore_dfi_p3_we_n <= (~array_muxed25); - litedramcore_dfi_p3_rddata_en <= array_muxed26; - litedramcore_dfi_p3_wrdata_en <= array_muxed27; - if (litedramcore_trrdcon_valid) begin - litedramcore_trrdcon_count <= 1'd1; + main_litedramcore_dfi_p0_cs_n <= 1'd0; + main_litedramcore_dfi_p0_bank <= builder_self0; + main_litedramcore_dfi_p0_address <= builder_self1; + main_litedramcore_dfi_p0_cas_n <= (~builder_self2); + main_litedramcore_dfi_p0_ras_n <= (~builder_self3); + main_litedramcore_dfi_p0_we_n <= (~builder_self4); + main_litedramcore_dfi_p0_rddata_en <= builder_self5; + main_litedramcore_dfi_p0_wrdata_en <= builder_self6; + main_litedramcore_dfi_p1_cs_n <= 1'd0; + main_litedramcore_dfi_p1_bank <= builder_self7; + main_litedramcore_dfi_p1_address <= builder_self8; + main_litedramcore_dfi_p1_cas_n <= (~builder_self9); + main_litedramcore_dfi_p1_ras_n <= (~builder_self10); + main_litedramcore_dfi_p1_we_n <= (~builder_self11); + main_litedramcore_dfi_p1_rddata_en <= builder_self12; + main_litedramcore_dfi_p1_wrdata_en <= builder_self13; + main_litedramcore_dfi_p2_cs_n <= 1'd0; + main_litedramcore_dfi_p2_bank <= builder_self14; + main_litedramcore_dfi_p2_address <= builder_self15; + main_litedramcore_dfi_p2_cas_n <= (~builder_self16); + main_litedramcore_dfi_p2_ras_n <= (~builder_self17); + main_litedramcore_dfi_p2_we_n <= (~builder_self18); + main_litedramcore_dfi_p2_rddata_en <= builder_self19; + main_litedramcore_dfi_p2_wrdata_en <= builder_self20; + main_litedramcore_dfi_p3_cs_n <= 1'd0; + main_litedramcore_dfi_p3_bank <= builder_self21; + main_litedramcore_dfi_p3_address <= builder_self22; + main_litedramcore_dfi_p3_cas_n <= (~builder_self23); + main_litedramcore_dfi_p3_ras_n <= (~builder_self24); + main_litedramcore_dfi_p3_we_n <= (~builder_self25); + main_litedramcore_dfi_p3_rddata_en <= builder_self26; + main_litedramcore_dfi_p3_wrdata_en <= builder_self27; + if (main_litedramcore_trrdcon_valid) begin + main_litedramcore_trrdcon_count <= 1'd1; if (1'd0) begin - litedramcore_trrdcon_ready <= 1'd1; + main_litedramcore_trrdcon_ready <= 1'd1; end else begin - litedramcore_trrdcon_ready <= 1'd0; + main_litedramcore_trrdcon_ready <= 1'd0; end end else begin - if ((~litedramcore_trrdcon_ready)) begin - litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); - if ((litedramcore_trrdcon_count == 1'd1)) begin - litedramcore_trrdcon_ready <= 1'd1; + if ((~main_litedramcore_trrdcon_ready)) begin + main_litedramcore_trrdcon_count <= (main_litedramcore_trrdcon_count - 1'd1); + if ((main_litedramcore_trrdcon_count == 1'd1)) begin + main_litedramcore_trrdcon_ready <= 1'd1; end end end - litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; - if ((litedramcore_tfawcon_count < 3'd4)) begin - if ((litedramcore_tfawcon_count == 2'd3)) begin - litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); + main_litedramcore_tfawcon_window <= {main_litedramcore_tfawcon_window, main_litedramcore_tfawcon_valid}; + if ((main_litedramcore_tfawcon_count < 3'd4)) begin + if ((main_litedramcore_tfawcon_count == 2'd3)) begin + main_litedramcore_tfawcon_ready <= (~main_litedramcore_tfawcon_valid); end else begin - litedramcore_tfawcon_ready <= 1'd1; + main_litedramcore_tfawcon_ready <= 1'd1; end end - if (litedramcore_tccdcon_valid) begin - litedramcore_tccdcon_count <= 1'd0; + if (main_litedramcore_tccdcon_valid) begin + main_litedramcore_tccdcon_count <= 1'd0; if (1'd1) begin - litedramcore_tccdcon_ready <= 1'd1; + main_litedramcore_tccdcon_ready <= 1'd1; end else begin - litedramcore_tccdcon_ready <= 1'd0; + main_litedramcore_tccdcon_ready <= 1'd0; end end else begin - if ((~litedramcore_tccdcon_ready)) begin - litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); - if ((litedramcore_tccdcon_count == 1'd1)) begin - litedramcore_tccdcon_ready <= 1'd1; + if ((~main_litedramcore_tccdcon_ready)) begin + main_litedramcore_tccdcon_count <= (main_litedramcore_tccdcon_count - 1'd1); + if ((main_litedramcore_tccdcon_count == 1'd1)) begin + main_litedramcore_tccdcon_ready <= 1'd1; end end end - if (litedramcore_twtrcon_valid) begin - litedramcore_twtrcon_count <= 3'd4; + if (main_litedramcore_twtrcon_valid) begin + main_litedramcore_twtrcon_count <= 3'd4; if (1'd0) begin - litedramcore_twtrcon_ready <= 1'd1; + main_litedramcore_twtrcon_ready <= 1'd1; end else begin - litedramcore_twtrcon_ready <= 1'd0; + main_litedramcore_twtrcon_ready <= 1'd0; end end else begin - if ((~litedramcore_twtrcon_ready)) begin - litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); - if ((litedramcore_twtrcon_count == 1'd1)) begin - litedramcore_twtrcon_ready <= 1'd1; - end - end - end - litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state; - litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); - litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0; - litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); - litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0; - litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1; - litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2; - litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3; - litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4; - litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5; - litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6; - litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7; - litedramcore_state <= litedramcore_next_state; - if (litedramcore_dat_w_next_value_ce0) begin - litedramcore_dat_w <= litedramcore_dat_w_next_value0; - end - if (litedramcore_adr_next_value_ce1) begin - litedramcore_adr <= litedramcore_adr_next_value1; - end - if (litedramcore_we_next_value_ce2) begin - litedramcore_we <= litedramcore_we_next_value2; - end - interface0_bank_bus_dat_r <= 1'd0; - if (csrbank0_sel) begin - case (interface0_bank_bus_adr[8:0]) + if ((~main_litedramcore_twtrcon_ready)) begin + main_litedramcore_twtrcon_count <= (main_litedramcore_twtrcon_count - 1'd1); + if ((main_litedramcore_twtrcon_count == 1'd1)) begin + main_litedramcore_twtrcon_ready <= 1'd1; + end + end + end + builder_multiplexer_state <= builder_multiplexer_next_state; + builder_new_master_wdata_ready0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_wdata_ready)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_wdata_ready)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_wdata_ready)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_wdata_ready)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_wdata_ready)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_wdata_ready)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_wdata_ready)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_wdata_ready)); + builder_new_master_wdata_ready1 <= builder_new_master_wdata_ready0; + builder_new_master_rdata_valid0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_rdata_valid)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_rdata_valid)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_rdata_valid)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_rdata_valid)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_rdata_valid)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_rdata_valid)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_rdata_valid)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_rdata_valid)); + builder_new_master_rdata_valid1 <= builder_new_master_rdata_valid0; + builder_new_master_rdata_valid2 <= builder_new_master_rdata_valid1; + builder_new_master_rdata_valid3 <= builder_new_master_rdata_valid2; + builder_new_master_rdata_valid4 <= builder_new_master_rdata_valid3; + builder_new_master_rdata_valid5 <= builder_new_master_rdata_valid4; + builder_new_master_rdata_valid6 <= builder_new_master_rdata_valid5; + builder_new_master_rdata_valid7 <= builder_new_master_rdata_valid6; + builder_new_master_rdata_valid8 <= builder_new_master_rdata_valid7; + builder_state <= builder_next_state; + if (builder_interface1_dat_w_next_value_ce0) begin + builder_interface1_dat_w <= builder_interface1_dat_w_next_value0; + end + if (builder_interface1_adr_next_value_ce1) begin + builder_interface1_adr <= builder_interface1_adr_next_value1; + end + if (builder_interface1_we_next_value_ce2) begin + builder_interface1_we <= builder_interface1_we_next_value2; + end + builder_interface0_bank_bus_dat_r <= 1'd0; + if (builder_csrbank0_sel) begin + case (builder_interface0_bank_bus_adr[8:0]) 1'd0: begin - interface0_bank_bus_dat_r <= csrbank0_init_done0_w; + builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_done0_w; end 1'd1: begin - interface0_bank_bus_dat_r <= csrbank0_init_error0_w; + builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_error0_w; end endcase end - if (csrbank0_init_done0_re) begin - init_done_storage <= csrbank0_init_done0_r; + if (builder_csrbank0_init_done0_re) begin + main_init_done_storage <= builder_csrbank0_init_done0_r; end - init_done_re <= csrbank0_init_done0_re; - if (csrbank0_init_error0_re) begin - init_error_storage <= csrbank0_init_error0_r; + main_init_done_re <= builder_csrbank0_init_done0_re; + if (builder_csrbank0_init_error0_re) begin + main_init_error_storage <= builder_csrbank0_init_error0_r; end - init_error_re <= csrbank0_init_error0_re; - interface1_bank_bus_dat_r <= 1'd0; - if (csrbank1_sel) begin - case (interface1_bank_bus_adr[8:0]) + main_init_error_re <= builder_csrbank0_init_error0_re; + builder_interface1_bank_bus_dat_r <= 1'd0; + if (builder_csrbank1_sel) begin + case (builder_interface1_bank_bus_adr[8:0]) 1'd0: begin - interface1_bank_bus_dat_r <= csrbank1_rst0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rst0_w; end 1'd1: begin - interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_dly_sel0_w; end 2'd2: begin - interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_half_sys8x_taps0_w; end 2'd3: begin - interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_wlevel_en0_w; end 3'd4: begin - interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wlevel_strobe_w; end 3'd5: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_rst_w; end 3'd6: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_inc_w; end 3'd7: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_rst_w; end 4'd8: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_w; end 4'd9: begin - interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_rst_w; end 4'd10: begin - interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_w; end 4'd11: begin - interface1_bank_bus_dat_r <= csrbank1_rdphase0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rdphase0_w; end 4'd12: begin - interface1_bank_bus_dat_r <= csrbank1_wrphase0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_wrphase0_w; end endcase end - if (csrbank1_rst0_re) begin - a7ddrphy_rst_storage <= csrbank1_rst0_r; + if (builder_csrbank1_rst0_re) begin + main_a7ddrphy_rst_storage <= builder_csrbank1_rst0_r; end - a7ddrphy_rst_re <= csrbank1_rst0_re; - if (csrbank1_dly_sel0_re) begin - a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r; + main_a7ddrphy_rst_re <= builder_csrbank1_rst0_re; + if (builder_csrbank1_dly_sel0_re) begin + main_a7ddrphy_dly_sel_storage[1:0] <= builder_csrbank1_dly_sel0_r; end - a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; - if (csrbank1_half_sys8x_taps0_re) begin - a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r; + main_a7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re; + if (builder_csrbank1_half_sys8x_taps0_re) begin + main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r; end - a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re; - if (csrbank1_wlevel_en0_re) begin - a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r; + main_a7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re; + if (builder_csrbank1_wlevel_en0_re) begin + main_a7ddrphy_wlevel_en_storage <= builder_csrbank1_wlevel_en0_r; end - a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re; - if (csrbank1_rdphase0_re) begin - a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r; + main_a7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re; + if (builder_csrbank1_rdphase0_re) begin + main_a7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r; end - a7ddrphy_rdphase_re <= csrbank1_rdphase0_re; - if (csrbank1_wrphase0_re) begin - a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r; + main_a7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re; + if (builder_csrbank1_wrphase0_re) begin + main_a7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r; end - a7ddrphy_wrphase_re <= csrbank1_wrphase0_re; - interface2_bank_bus_dat_r <= 1'd0; - if (csrbank2_sel) begin - case (interface2_bank_bus_adr[8:0]) + main_a7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re; + builder_interface2_bank_bus_dat_r <= 1'd0; + if (builder_csrbank2_sel) begin + case (builder_interface2_bank_bus_adr[8:0]) 1'd0: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_control0_w; end 1'd1: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_command0_w; end 2'd2: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w; end 3'd4: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w; end 3'd5: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w; end 3'd6: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata_w; end 3'd7: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w; end 4'd8: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w; end 4'd9: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w; end 4'd10: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w; end 4'd11: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w; end 4'd12: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata_w; end 4'd13: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w; end 4'd14: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w; end 4'd15: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w; end 5'd16: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w; end 5'd17: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w; end 5'd18: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata_w; end 5'd19: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w; end 5'd20: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w; end 5'd21: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w; end 5'd22: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w; end 5'd23: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w; end 5'd24: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata_w; end endcase end - if (csrbank2_dfii_control0_re) begin - litedramcore_storage[3:0] <= csrbank2_dfii_control0_r; + if (builder_csrbank2_dfii_control0_re) begin + main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r; end - litedramcore_re <= csrbank2_dfii_control0_re; - if (csrbank2_dfii_pi0_command0_re) begin - litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; + main_litedramcore_re <= builder_csrbank2_dfii_control0_re; + if (builder_csrbank2_dfii_pi0_command0_re) begin + main_litedramcore_phaseinjector0_command_storage[7:0] <= builder_csrbank2_dfii_pi0_command0_r; end - litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; - if (csrbank2_dfii_pi0_address0_re) begin - litedramcore_phaseinjector0_address_storage[13:0] <= csrbank2_dfii_pi0_address0_r; + main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re; + if (builder_csrbank2_dfii_pi0_address0_re) begin + main_litedramcore_phaseinjector0_address_storage[13:0] <= builder_csrbank2_dfii_pi0_address0_r; end - litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; - if (csrbank2_dfii_pi0_baddress0_re) begin - litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; + main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re; + if (builder_csrbank2_dfii_pi0_baddress0_re) begin + main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r; end - litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; - if (csrbank2_dfii_pi0_wrdata0_re) begin - litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; + main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re; + if (builder_csrbank2_dfii_pi0_wrdata0_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r; end - litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; - litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re; - if (csrbank2_dfii_pi1_command0_re) begin - litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; + main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re; + main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re; + if (builder_csrbank2_dfii_pi1_command0_re) begin + main_litedramcore_phaseinjector1_command_storage[7:0] <= builder_csrbank2_dfii_pi1_command0_r; end - litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; - if (csrbank2_dfii_pi1_address0_re) begin - litedramcore_phaseinjector1_address_storage[13:0] <= csrbank2_dfii_pi1_address0_r; + main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re; + if (builder_csrbank2_dfii_pi1_address0_re) begin + main_litedramcore_phaseinjector1_address_storage[13:0] <= builder_csrbank2_dfii_pi1_address0_r; end - litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; - if (csrbank2_dfii_pi1_baddress0_re) begin - litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; + main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re; + if (builder_csrbank2_dfii_pi1_baddress0_re) begin + main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r; end - litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; - if (csrbank2_dfii_pi1_wrdata0_re) begin - litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; + main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re; + if (builder_csrbank2_dfii_pi1_wrdata0_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r; end - litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; - litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re; - if (csrbank2_dfii_pi2_command0_re) begin - litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; + main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re; + main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re; + if (builder_csrbank2_dfii_pi2_command0_re) begin + main_litedramcore_phaseinjector2_command_storage[7:0] <= builder_csrbank2_dfii_pi2_command0_r; end - litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; - if (csrbank2_dfii_pi2_address0_re) begin - litedramcore_phaseinjector2_address_storage[13:0] <= csrbank2_dfii_pi2_address0_r; + main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re; + if (builder_csrbank2_dfii_pi2_address0_re) begin + main_litedramcore_phaseinjector2_address_storage[13:0] <= builder_csrbank2_dfii_pi2_address0_r; end - litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; - if (csrbank2_dfii_pi2_baddress0_re) begin - litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; + main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re; + if (builder_csrbank2_dfii_pi2_baddress0_re) begin + main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r; end - litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; - if (csrbank2_dfii_pi2_wrdata0_re) begin - litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r; + main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re; + if (builder_csrbank2_dfii_pi2_wrdata0_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r; end - litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; - litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re; - if (csrbank2_dfii_pi3_command0_re) begin - litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; + main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re; + main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re; + if (builder_csrbank2_dfii_pi3_command0_re) begin + main_litedramcore_phaseinjector3_command_storage[7:0] <= builder_csrbank2_dfii_pi3_command0_r; end - litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; - if (csrbank2_dfii_pi3_address0_re) begin - litedramcore_phaseinjector3_address_storage[13:0] <= csrbank2_dfii_pi3_address0_r; + main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re; + if (builder_csrbank2_dfii_pi3_address0_re) begin + main_litedramcore_phaseinjector3_address_storage[13:0] <= builder_csrbank2_dfii_pi3_address0_r; end - litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; - if (csrbank2_dfii_pi3_baddress0_re) begin - litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; + main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re; + if (builder_csrbank2_dfii_pi3_baddress0_re) begin + main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r; end - litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; - if (csrbank2_dfii_pi3_wrdata0_re) begin - litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r; + main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re; + if (builder_csrbank2_dfii_pi3_wrdata0_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r; end - litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; - litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re; + main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re; + main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re; if (sys_rst) begin - a7ddrphy_rst_storage <= 1'd0; - a7ddrphy_rst_re <= 1'd0; - a7ddrphy_dly_sel_storage <= 2'd0; - a7ddrphy_dly_sel_re <= 1'd0; - a7ddrphy_half_sys8x_taps_storage <= 5'd8; - a7ddrphy_half_sys8x_taps_re <= 1'd0; - a7ddrphy_wlevel_en_storage <= 1'd0; - a7ddrphy_wlevel_en_re <= 1'd0; - a7ddrphy_rdphase_storage <= 2'd2; - a7ddrphy_rdphase_re <= 1'd0; - a7ddrphy_wrphase_storage <= 2'd3; - a7ddrphy_wrphase_re <= 1'd0; - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; - a7ddrphy_dqspattern_o1 <= 8'd0; - a7ddrphy_bitslip0_value0 <= 3'd7; - a7ddrphy_bitslip1_value0 <= 3'd7; - a7ddrphy_bitslip0_value1 <= 3'd7; - a7ddrphy_bitslip1_value1 <= 3'd7; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; - a7ddrphy_bitslip0_value2 <= 3'd7; - a7ddrphy_bitslip0_value3 <= 3'd7; - a7ddrphy_bitslip1_value2 <= 3'd7; - a7ddrphy_bitslip1_value3 <= 3'd7; - a7ddrphy_bitslip2_value0 <= 3'd7; - a7ddrphy_bitslip2_value1 <= 3'd7; - a7ddrphy_bitslip3_value0 <= 3'd7; - a7ddrphy_bitslip3_value1 <= 3'd7; - a7ddrphy_bitslip4_value0 <= 3'd7; - a7ddrphy_bitslip4_value1 <= 3'd7; - a7ddrphy_bitslip5_value0 <= 3'd7; - a7ddrphy_bitslip5_value1 <= 3'd7; - a7ddrphy_bitslip6_value0 <= 3'd7; - a7ddrphy_bitslip6_value1 <= 3'd7; - a7ddrphy_bitslip7_value0 <= 3'd7; - a7ddrphy_bitslip7_value1 <= 3'd7; - a7ddrphy_bitslip8_value0 <= 3'd7; - a7ddrphy_bitslip8_value1 <= 3'd7; - a7ddrphy_bitslip9_value0 <= 3'd7; - a7ddrphy_bitslip9_value1 <= 3'd7; - a7ddrphy_bitslip10_value0 <= 3'd7; - a7ddrphy_bitslip10_value1 <= 3'd7; - a7ddrphy_bitslip11_value0 <= 3'd7; - a7ddrphy_bitslip11_value1 <= 3'd7; - a7ddrphy_bitslip12_value0 <= 3'd7; - a7ddrphy_bitslip12_value1 <= 3'd7; - a7ddrphy_bitslip13_value0 <= 3'd7; - a7ddrphy_bitslip13_value1 <= 3'd7; - a7ddrphy_bitslip14_value0 <= 3'd7; - a7ddrphy_bitslip14_value1 <= 3'd7; - a7ddrphy_bitslip15_value0 <= 3'd7; - a7ddrphy_bitslip15_value1 <= 3'd7; - a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; - a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; - a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; - a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; - litedramcore_storage <= 4'd1; - litedramcore_re <= 1'd0; - litedramcore_phaseinjector0_command_storage <= 6'd0; - litedramcore_phaseinjector0_command_re <= 1'd0; - litedramcore_phaseinjector0_address_re <= 1'd0; - litedramcore_phaseinjector0_baddress_re <= 1'd0; - litedramcore_phaseinjector0_wrdata_re <= 1'd0; - litedramcore_phaseinjector0_rddata_status <= 32'd0; - litedramcore_phaseinjector0_rddata_re <= 1'd0; - litedramcore_phaseinjector1_command_storage <= 6'd0; - litedramcore_phaseinjector1_command_re <= 1'd0; - litedramcore_phaseinjector1_address_re <= 1'd0; - litedramcore_phaseinjector1_baddress_re <= 1'd0; - litedramcore_phaseinjector1_wrdata_re <= 1'd0; - litedramcore_phaseinjector1_rddata_status <= 32'd0; - litedramcore_phaseinjector1_rddata_re <= 1'd0; - litedramcore_phaseinjector2_command_storage <= 6'd0; - litedramcore_phaseinjector2_command_re <= 1'd0; - litedramcore_phaseinjector2_address_re <= 1'd0; - litedramcore_phaseinjector2_baddress_re <= 1'd0; - litedramcore_phaseinjector2_wrdata_re <= 1'd0; - litedramcore_phaseinjector2_rddata_status <= 32'd0; - litedramcore_phaseinjector2_rddata_re <= 1'd0; - litedramcore_phaseinjector3_command_storage <= 6'd0; - litedramcore_phaseinjector3_command_re <= 1'd0; - litedramcore_phaseinjector3_address_re <= 1'd0; - litedramcore_phaseinjector3_baddress_re <= 1'd0; - litedramcore_phaseinjector3_wrdata_re <= 1'd0; - litedramcore_phaseinjector3_rddata_status <= 32'd0; - litedramcore_phaseinjector3_rddata_re <= 1'd0; - litedramcore_dfi_p0_address <= 14'd0; - litedramcore_dfi_p0_bank <= 3'd0; - litedramcore_dfi_p0_cas_n <= 1'd1; - litedramcore_dfi_p0_cs_n <= 1'd1; - litedramcore_dfi_p0_ras_n <= 1'd1; - litedramcore_dfi_p0_we_n <= 1'd1; - litedramcore_dfi_p0_wrdata_en <= 1'd0; - litedramcore_dfi_p0_rddata_en <= 1'd0; - litedramcore_dfi_p1_address <= 14'd0; - litedramcore_dfi_p1_bank <= 3'd0; - litedramcore_dfi_p1_cas_n <= 1'd1; - litedramcore_dfi_p1_cs_n <= 1'd1; - litedramcore_dfi_p1_ras_n <= 1'd1; - litedramcore_dfi_p1_we_n <= 1'd1; - litedramcore_dfi_p1_wrdata_en <= 1'd0; - litedramcore_dfi_p1_rddata_en <= 1'd0; - litedramcore_dfi_p2_address <= 14'd0; - litedramcore_dfi_p2_bank <= 3'd0; - litedramcore_dfi_p2_cas_n <= 1'd1; - litedramcore_dfi_p2_cs_n <= 1'd1; - litedramcore_dfi_p2_ras_n <= 1'd1; - litedramcore_dfi_p2_we_n <= 1'd1; - litedramcore_dfi_p2_wrdata_en <= 1'd0; - litedramcore_dfi_p2_rddata_en <= 1'd0; - litedramcore_dfi_p3_address <= 14'd0; - litedramcore_dfi_p3_bank <= 3'd0; - litedramcore_dfi_p3_cas_n <= 1'd1; - litedramcore_dfi_p3_cs_n <= 1'd1; - litedramcore_dfi_p3_ras_n <= 1'd1; - litedramcore_dfi_p3_we_n <= 1'd1; - litedramcore_dfi_p3_wrdata_en <= 1'd0; - litedramcore_dfi_p3_rddata_en <= 1'd0; - litedramcore_cmd_payload_a <= 14'd0; - litedramcore_cmd_payload_ba <= 3'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_timer_count1 <= 10'd781; - litedramcore_postponer_req_o <= 1'd0; - litedramcore_postponer_count <= 1'd0; - litedramcore_sequencer_done1 <= 1'd0; - litedramcore_sequencer_counter <= 6'd0; - litedramcore_sequencer_count <= 1'd0; - litedramcore_zqcs_timer_count1 <= 27'd99999999; - litedramcore_zqcs_executer_done <= 1'd0; - litedramcore_zqcs_executer_counter <= 5'd0; - litedramcore_bankmachine0_level <= 5'd0; - litedramcore_bankmachine0_produce <= 4'd0; - litedramcore_bankmachine0_consume <= 4'd0; - litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 21'd0; - litedramcore_bankmachine0_row <= 14'd0; - litedramcore_bankmachine0_row_opened <= 1'd0; - litedramcore_bankmachine0_twtpcon_ready <= 1'd0; - litedramcore_bankmachine0_twtpcon_count <= 3'd0; - litedramcore_bankmachine0_trccon_ready <= 1'd0; - litedramcore_bankmachine0_trccon_count <= 3'd0; - litedramcore_bankmachine0_trascon_ready <= 1'd0; - litedramcore_bankmachine0_trascon_count <= 3'd0; - litedramcore_bankmachine1_level <= 5'd0; - litedramcore_bankmachine1_produce <= 4'd0; - litedramcore_bankmachine1_consume <= 4'd0; - litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 21'd0; - litedramcore_bankmachine1_row <= 14'd0; - litedramcore_bankmachine1_row_opened <= 1'd0; - litedramcore_bankmachine1_twtpcon_ready <= 1'd0; - litedramcore_bankmachine1_twtpcon_count <= 3'd0; - litedramcore_bankmachine1_trccon_ready <= 1'd0; - litedramcore_bankmachine1_trccon_count <= 3'd0; - litedramcore_bankmachine1_trascon_ready <= 1'd0; - litedramcore_bankmachine1_trascon_count <= 3'd0; - litedramcore_bankmachine2_level <= 5'd0; - litedramcore_bankmachine2_produce <= 4'd0; - litedramcore_bankmachine2_consume <= 4'd0; - litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 21'd0; - litedramcore_bankmachine2_row <= 14'd0; - litedramcore_bankmachine2_row_opened <= 1'd0; - litedramcore_bankmachine2_twtpcon_ready <= 1'd0; - litedramcore_bankmachine2_twtpcon_count <= 3'd0; - litedramcore_bankmachine2_trccon_ready <= 1'd0; - litedramcore_bankmachine2_trccon_count <= 3'd0; - litedramcore_bankmachine2_trascon_ready <= 1'd0; - litedramcore_bankmachine2_trascon_count <= 3'd0; - litedramcore_bankmachine3_level <= 5'd0; - litedramcore_bankmachine3_produce <= 4'd0; - litedramcore_bankmachine3_consume <= 4'd0; - litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 21'd0; - litedramcore_bankmachine3_row <= 14'd0; - litedramcore_bankmachine3_row_opened <= 1'd0; - litedramcore_bankmachine3_twtpcon_ready <= 1'd0; - litedramcore_bankmachine3_twtpcon_count <= 3'd0; - litedramcore_bankmachine3_trccon_ready <= 1'd0; - litedramcore_bankmachine3_trccon_count <= 3'd0; - litedramcore_bankmachine3_trascon_ready <= 1'd0; - litedramcore_bankmachine3_trascon_count <= 3'd0; - litedramcore_bankmachine4_level <= 5'd0; - litedramcore_bankmachine4_produce <= 4'd0; - litedramcore_bankmachine4_consume <= 4'd0; - litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 21'd0; - litedramcore_bankmachine4_row <= 14'd0; - litedramcore_bankmachine4_row_opened <= 1'd0; - litedramcore_bankmachine4_twtpcon_ready <= 1'd0; - litedramcore_bankmachine4_twtpcon_count <= 3'd0; - litedramcore_bankmachine4_trccon_ready <= 1'd0; - litedramcore_bankmachine4_trccon_count <= 3'd0; - litedramcore_bankmachine4_trascon_ready <= 1'd0; - litedramcore_bankmachine4_trascon_count <= 3'd0; - litedramcore_bankmachine5_level <= 5'd0; - litedramcore_bankmachine5_produce <= 4'd0; - litedramcore_bankmachine5_consume <= 4'd0; - litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 21'd0; - litedramcore_bankmachine5_row <= 14'd0; - litedramcore_bankmachine5_row_opened <= 1'd0; - litedramcore_bankmachine5_twtpcon_ready <= 1'd0; - litedramcore_bankmachine5_twtpcon_count <= 3'd0; - litedramcore_bankmachine5_trccon_ready <= 1'd0; - litedramcore_bankmachine5_trccon_count <= 3'd0; - litedramcore_bankmachine5_trascon_ready <= 1'd0; - litedramcore_bankmachine5_trascon_count <= 3'd0; - litedramcore_bankmachine6_level <= 5'd0; - litedramcore_bankmachine6_produce <= 4'd0; - litedramcore_bankmachine6_consume <= 4'd0; - litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 21'd0; - litedramcore_bankmachine6_row <= 14'd0; - litedramcore_bankmachine6_row_opened <= 1'd0; - litedramcore_bankmachine6_twtpcon_ready <= 1'd0; - litedramcore_bankmachine6_twtpcon_count <= 3'd0; - litedramcore_bankmachine6_trccon_ready <= 1'd0; - litedramcore_bankmachine6_trccon_count <= 3'd0; - litedramcore_bankmachine6_trascon_ready <= 1'd0; - litedramcore_bankmachine6_trascon_count <= 3'd0; - litedramcore_bankmachine7_level <= 5'd0; - litedramcore_bankmachine7_produce <= 4'd0; - litedramcore_bankmachine7_consume <= 4'd0; - litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 21'd0; - litedramcore_bankmachine7_row <= 14'd0; - litedramcore_bankmachine7_row_opened <= 1'd0; - litedramcore_bankmachine7_twtpcon_ready <= 1'd0; - litedramcore_bankmachine7_twtpcon_count <= 3'd0; - litedramcore_bankmachine7_trccon_ready <= 1'd0; - litedramcore_bankmachine7_trccon_count <= 3'd0; - litedramcore_bankmachine7_trascon_ready <= 1'd0; - litedramcore_bankmachine7_trascon_count <= 3'd0; - litedramcore_choose_cmd_grant <= 3'd0; - litedramcore_choose_req_grant <= 3'd0; - litedramcore_trrdcon_ready <= 1'd0; - litedramcore_trrdcon_count <= 1'd0; - litedramcore_tfawcon_ready <= 1'd1; - litedramcore_tfawcon_window <= 5'd0; - litedramcore_tccdcon_ready <= 1'd0; - litedramcore_tccdcon_count <= 1'd0; - litedramcore_twtrcon_ready <= 1'd0; - litedramcore_twtrcon_count <= 3'd0; - litedramcore_time0 <= 5'd0; - litedramcore_time1 <= 4'd0; - init_done_storage <= 1'd0; - init_done_re <= 1'd0; - init_error_storage <= 1'd0; - init_error_re <= 1'd0; - litedramcore_we <= 1'd0; - litedramcore_refresher_state <= 2'd0; - litedramcore_bankmachine0_state <= 4'd0; - litedramcore_bankmachine1_state <= 4'd0; - litedramcore_bankmachine2_state <= 4'd0; - litedramcore_bankmachine3_state <= 4'd0; - litedramcore_bankmachine4_state <= 4'd0; - litedramcore_bankmachine5_state <= 4'd0; - litedramcore_bankmachine6_state <= 4'd0; - litedramcore_bankmachine7_state <= 4'd0; - litedramcore_multiplexer_state <= 4'd0; - litedramcore_new_master_wdata_ready0 <= 1'd0; - litedramcore_new_master_wdata_ready1 <= 1'd0; - litedramcore_new_master_rdata_valid0 <= 1'd0; - litedramcore_new_master_rdata_valid1 <= 1'd0; - litedramcore_new_master_rdata_valid2 <= 1'd0; - litedramcore_new_master_rdata_valid3 <= 1'd0; - litedramcore_new_master_rdata_valid4 <= 1'd0; - litedramcore_new_master_rdata_valid5 <= 1'd0; - litedramcore_new_master_rdata_valid6 <= 1'd0; - litedramcore_new_master_rdata_valid7 <= 1'd0; - litedramcore_new_master_rdata_valid8 <= 1'd0; - litedramcore_state <= 2'd0; + main_a7ddrphy_rst_storage <= 1'd0; + main_a7ddrphy_rst_re <= 1'd0; + main_a7ddrphy_dly_sel_storage <= 2'd0; + main_a7ddrphy_dly_sel_re <= 1'd0; + main_a7ddrphy_half_sys8x_taps_storage <= 5'd8; + main_a7ddrphy_half_sys8x_taps_re <= 1'd0; + main_a7ddrphy_wlevel_en_storage <= 1'd0; + main_a7ddrphy_wlevel_en_re <= 1'd0; + main_a7ddrphy_rdphase_storage <= 2'd2; + main_a7ddrphy_rdphase_re <= 1'd0; + main_a7ddrphy_wrphase_storage <= 2'd3; + main_a7ddrphy_wrphase_re <= 1'd0; + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + main_a7ddrphy_dqspattern_o1 <= 8'd0; + main_a7ddrphy_bitslip0_value0 <= 3'd7; + main_a7ddrphy_bitslip1_value0 <= 3'd7; + main_a7ddrphy_bitslip0_value1 <= 3'd7; + main_a7ddrphy_bitslip1_value1 <= 3'd7; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + main_a7ddrphy_bitslip0_value2 <= 3'd7; + main_a7ddrphy_bitslip0_value3 <= 3'd7; + main_a7ddrphy_bitslip1_value2 <= 3'd7; + main_a7ddrphy_bitslip1_value3 <= 3'd7; + main_a7ddrphy_bitslip2_value0 <= 3'd7; + main_a7ddrphy_bitslip2_value1 <= 3'd7; + main_a7ddrphy_bitslip3_value0 <= 3'd7; + main_a7ddrphy_bitslip3_value1 <= 3'd7; + main_a7ddrphy_bitslip4_value0 <= 3'd7; + main_a7ddrphy_bitslip4_value1 <= 3'd7; + main_a7ddrphy_bitslip5_value0 <= 3'd7; + main_a7ddrphy_bitslip5_value1 <= 3'd7; + main_a7ddrphy_bitslip6_value0 <= 3'd7; + main_a7ddrphy_bitslip6_value1 <= 3'd7; + main_a7ddrphy_bitslip7_value0 <= 3'd7; + main_a7ddrphy_bitslip7_value1 <= 3'd7; + main_a7ddrphy_bitslip8_value0 <= 3'd7; + main_a7ddrphy_bitslip8_value1 <= 3'd7; + main_a7ddrphy_bitslip9_value0 <= 3'd7; + main_a7ddrphy_bitslip9_value1 <= 3'd7; + main_a7ddrphy_bitslip10_value0 <= 3'd7; + main_a7ddrphy_bitslip10_value1 <= 3'd7; + main_a7ddrphy_bitslip11_value0 <= 3'd7; + main_a7ddrphy_bitslip11_value1 <= 3'd7; + main_a7ddrphy_bitslip12_value0 <= 3'd7; + main_a7ddrphy_bitslip12_value1 <= 3'd7; + main_a7ddrphy_bitslip13_value0 <= 3'd7; + main_a7ddrphy_bitslip13_value1 <= 3'd7; + main_a7ddrphy_bitslip14_value0 <= 3'd7; + main_a7ddrphy_bitslip14_value1 <= 3'd7; + main_a7ddrphy_bitslip15_value0 <= 3'd7; + main_a7ddrphy_bitslip15_value1 <= 3'd7; + main_a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; + main_a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; + main_a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; + main_a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; + main_litedramcore_storage <= 4'd1; + main_litedramcore_re <= 1'd0; + main_litedramcore_phaseinjector0_command_storage <= 8'd0; + main_litedramcore_phaseinjector0_command_re <= 1'd0; + main_litedramcore_phaseinjector0_address_re <= 1'd0; + main_litedramcore_phaseinjector0_baddress_re <= 1'd0; + main_litedramcore_phaseinjector0_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector0_rddata_status <= 32'd0; + main_litedramcore_phaseinjector0_rddata_re <= 1'd0; + main_litedramcore_phaseinjector1_command_storage <= 8'd0; + main_litedramcore_phaseinjector1_command_re <= 1'd0; + main_litedramcore_phaseinjector1_address_re <= 1'd0; + main_litedramcore_phaseinjector1_baddress_re <= 1'd0; + main_litedramcore_phaseinjector1_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector1_rddata_status <= 32'd0; + main_litedramcore_phaseinjector1_rddata_re <= 1'd0; + main_litedramcore_phaseinjector2_command_storage <= 8'd0; + main_litedramcore_phaseinjector2_command_re <= 1'd0; + main_litedramcore_phaseinjector2_address_re <= 1'd0; + main_litedramcore_phaseinjector2_baddress_re <= 1'd0; + main_litedramcore_phaseinjector2_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector2_rddata_status <= 32'd0; + main_litedramcore_phaseinjector2_rddata_re <= 1'd0; + main_litedramcore_phaseinjector3_command_storage <= 8'd0; + main_litedramcore_phaseinjector3_command_re <= 1'd0; + main_litedramcore_phaseinjector3_address_re <= 1'd0; + main_litedramcore_phaseinjector3_baddress_re <= 1'd0; + main_litedramcore_phaseinjector3_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector3_rddata_status <= 32'd0; + main_litedramcore_phaseinjector3_rddata_re <= 1'd0; + main_litedramcore_dfi_p0_address <= 14'd0; + main_litedramcore_dfi_p0_bank <= 3'd0; + main_litedramcore_dfi_p0_cas_n <= 1'd1; + main_litedramcore_dfi_p0_cs_n <= 1'd1; + main_litedramcore_dfi_p0_ras_n <= 1'd1; + main_litedramcore_dfi_p0_we_n <= 1'd1; + main_litedramcore_dfi_p0_wrdata_en <= 1'd0; + main_litedramcore_dfi_p0_rddata_en <= 1'd0; + main_litedramcore_dfi_p1_address <= 14'd0; + main_litedramcore_dfi_p1_bank <= 3'd0; + main_litedramcore_dfi_p1_cas_n <= 1'd1; + main_litedramcore_dfi_p1_cs_n <= 1'd1; + main_litedramcore_dfi_p1_ras_n <= 1'd1; + main_litedramcore_dfi_p1_we_n <= 1'd1; + main_litedramcore_dfi_p1_wrdata_en <= 1'd0; + main_litedramcore_dfi_p1_rddata_en <= 1'd0; + main_litedramcore_dfi_p2_address <= 14'd0; + main_litedramcore_dfi_p2_bank <= 3'd0; + main_litedramcore_dfi_p2_cas_n <= 1'd1; + main_litedramcore_dfi_p2_cs_n <= 1'd1; + main_litedramcore_dfi_p2_ras_n <= 1'd1; + main_litedramcore_dfi_p2_we_n <= 1'd1; + main_litedramcore_dfi_p2_wrdata_en <= 1'd0; + main_litedramcore_dfi_p2_rddata_en <= 1'd0; + main_litedramcore_dfi_p3_address <= 14'd0; + main_litedramcore_dfi_p3_bank <= 3'd0; + main_litedramcore_dfi_p3_cas_n <= 1'd1; + main_litedramcore_dfi_p3_cs_n <= 1'd1; + main_litedramcore_dfi_p3_ras_n <= 1'd1; + main_litedramcore_dfi_p3_we_n <= 1'd1; + main_litedramcore_dfi_p3_wrdata_en <= 1'd0; + main_litedramcore_dfi_p3_rddata_en <= 1'd0; + main_litedramcore_cmd_payload_a <= 14'd0; + main_litedramcore_cmd_payload_ba <= 3'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_timer_count1 <= 10'd781; + main_litedramcore_postponer_req_o <= 1'd0; + main_litedramcore_postponer_count <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd0; + main_litedramcore_sequencer_trigger <= 6'd0; + main_litedramcore_sequencer_count <= 1'd0; + main_litedramcore_zqcs_timer_count1 <= 27'd99999999; + main_litedramcore_zqcs_executer_done <= 1'd0; + main_litedramcore_zqcs_executer_trigger <= 5'd0; + main_litedramcore_bankmachine0_level <= 5'd0; + main_litedramcore_bankmachine0_produce <= 4'd0; + main_litedramcore_bankmachine0_consume <= 4'd0; + main_litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 21'd0; + main_litedramcore_bankmachine0_row <= 14'd0; + main_litedramcore_bankmachine0_row_opened <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine0_trccon_ready <= 1'd0; + main_litedramcore_bankmachine0_trccon_count <= 3'd0; + main_litedramcore_bankmachine0_trascon_ready <= 1'd0; + main_litedramcore_bankmachine0_trascon_count <= 3'd0; + main_litedramcore_bankmachine1_level <= 5'd0; + main_litedramcore_bankmachine1_produce <= 4'd0; + main_litedramcore_bankmachine1_consume <= 4'd0; + main_litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 21'd0; + main_litedramcore_bankmachine1_row <= 14'd0; + main_litedramcore_bankmachine1_row_opened <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine1_trccon_ready <= 1'd0; + main_litedramcore_bankmachine1_trccon_count <= 3'd0; + main_litedramcore_bankmachine1_trascon_ready <= 1'd0; + main_litedramcore_bankmachine1_trascon_count <= 3'd0; + main_litedramcore_bankmachine2_level <= 5'd0; + main_litedramcore_bankmachine2_produce <= 4'd0; + main_litedramcore_bankmachine2_consume <= 4'd0; + main_litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 21'd0; + main_litedramcore_bankmachine2_row <= 14'd0; + main_litedramcore_bankmachine2_row_opened <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine2_trccon_ready <= 1'd0; + main_litedramcore_bankmachine2_trccon_count <= 3'd0; + main_litedramcore_bankmachine2_trascon_ready <= 1'd0; + main_litedramcore_bankmachine2_trascon_count <= 3'd0; + main_litedramcore_bankmachine3_level <= 5'd0; + main_litedramcore_bankmachine3_produce <= 4'd0; + main_litedramcore_bankmachine3_consume <= 4'd0; + main_litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 21'd0; + main_litedramcore_bankmachine3_row <= 14'd0; + main_litedramcore_bankmachine3_row_opened <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine3_trccon_ready <= 1'd0; + main_litedramcore_bankmachine3_trccon_count <= 3'd0; + main_litedramcore_bankmachine3_trascon_ready <= 1'd0; + main_litedramcore_bankmachine3_trascon_count <= 3'd0; + main_litedramcore_bankmachine4_level <= 5'd0; + main_litedramcore_bankmachine4_produce <= 4'd0; + main_litedramcore_bankmachine4_consume <= 4'd0; + main_litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 21'd0; + main_litedramcore_bankmachine4_row <= 14'd0; + main_litedramcore_bankmachine4_row_opened <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine4_trccon_ready <= 1'd0; + main_litedramcore_bankmachine4_trccon_count <= 3'd0; + main_litedramcore_bankmachine4_trascon_ready <= 1'd0; + main_litedramcore_bankmachine4_trascon_count <= 3'd0; + main_litedramcore_bankmachine5_level <= 5'd0; + main_litedramcore_bankmachine5_produce <= 4'd0; + main_litedramcore_bankmachine5_consume <= 4'd0; + main_litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 21'd0; + main_litedramcore_bankmachine5_row <= 14'd0; + main_litedramcore_bankmachine5_row_opened <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine5_trccon_ready <= 1'd0; + main_litedramcore_bankmachine5_trccon_count <= 3'd0; + main_litedramcore_bankmachine5_trascon_ready <= 1'd0; + main_litedramcore_bankmachine5_trascon_count <= 3'd0; + main_litedramcore_bankmachine6_level <= 5'd0; + main_litedramcore_bankmachine6_produce <= 4'd0; + main_litedramcore_bankmachine6_consume <= 4'd0; + main_litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 21'd0; + main_litedramcore_bankmachine6_row <= 14'd0; + main_litedramcore_bankmachine6_row_opened <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine6_trccon_ready <= 1'd0; + main_litedramcore_bankmachine6_trccon_count <= 3'd0; + main_litedramcore_bankmachine6_trascon_ready <= 1'd0; + main_litedramcore_bankmachine6_trascon_count <= 3'd0; + main_litedramcore_bankmachine7_level <= 5'd0; + main_litedramcore_bankmachine7_produce <= 4'd0; + main_litedramcore_bankmachine7_consume <= 4'd0; + main_litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 21'd0; + main_litedramcore_bankmachine7_row <= 14'd0; + main_litedramcore_bankmachine7_row_opened <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine7_trccon_ready <= 1'd0; + main_litedramcore_bankmachine7_trccon_count <= 3'd0; + main_litedramcore_bankmachine7_trascon_ready <= 1'd0; + main_litedramcore_bankmachine7_trascon_count <= 3'd0; + main_litedramcore_choose_cmd_grant <= 3'd0; + main_litedramcore_choose_req_grant <= 3'd0; + main_litedramcore_trrdcon_ready <= 1'd0; + main_litedramcore_trrdcon_count <= 1'd0; + main_litedramcore_tfawcon_ready <= 1'd1; + main_litedramcore_tfawcon_window <= 5'd0; + main_litedramcore_tccdcon_ready <= 1'd0; + main_litedramcore_tccdcon_count <= 1'd0; + main_litedramcore_twtrcon_ready <= 1'd0; + main_litedramcore_twtrcon_count <= 3'd0; + main_litedramcore_time0 <= 5'd0; + main_litedramcore_time1 <= 4'd0; + main_init_done_storage <= 1'd0; + main_init_done_re <= 1'd0; + main_init_error_storage <= 1'd0; + main_init_error_re <= 1'd0; + builder_interface1_we <= 1'd0; + builder_refresher_state <= 2'd0; + builder_bankmachine0_state <= 4'd0; + builder_bankmachine1_state <= 4'd0; + builder_bankmachine2_state <= 4'd0; + builder_bankmachine3_state <= 4'd0; + builder_bankmachine4_state <= 4'd0; + builder_bankmachine5_state <= 4'd0; + builder_bankmachine6_state <= 4'd0; + builder_bankmachine7_state <= 4'd0; + builder_multiplexer_state <= 4'd0; + builder_new_master_wdata_ready0 <= 1'd0; + builder_new_master_wdata_ready1 <= 1'd0; + builder_new_master_rdata_valid0 <= 1'd0; + builder_new_master_rdata_valid1 <= 1'd0; + builder_new_master_rdata_valid2 <= 1'd0; + builder_new_master_rdata_valid3 <= 1'd0; + builder_new_master_rdata_valid4 <= 1'd0; + builder_new_master_rdata_valid5 <= 1'd0; + builder_new_master_rdata_valid6 <= 1'd0; + builder_new_master_rdata_valid7 <= 1'd0; + builder_new_master_rdata_valid8 <= 1'd0; + builder_state <= 2'd0; end end @@ -14116,1911 +14531,2624 @@ end // Specialized Logic //------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +// Instance BUFG of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG( - .I(clkout0), - .O(clkout_buf0) + // Inputs. + .I (main_clkout0), + + // Outputs. + .O (main_clkout_buf0) ); +//------------------------------------------------------------------------------ +// Instance BUFG_1 of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG_1( - .I(clkout1), - .O(clkout_buf1) + // Inputs. + .I (main_clkout1), + + // Outputs. + .O (main_clkout_buf1) ); +//------------------------------------------------------------------------------ +// Instance BUFG_2 of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG_2( - .I(clkout2), - .O(clkout_buf2) + // Inputs. + .I (main_clkout2), + + // Outputs. + .O (main_clkout_buf2) ); +//------------------------------------------------------------------------------ +// Instance BUFG_3 of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG_3( - .I(clkout3), - .O(clkout_buf3) + // Inputs. + .I (main_clkout3), + + // Outputs. + .O (main_clkout_buf3) ); +//------------------------------------------------------------------------------ +// Instance IDELAYCTRL of IDELAYCTRL Module. +//------------------------------------------------------------------------------ IDELAYCTRL IDELAYCTRL( - .REFCLK(iodelay_clk), - .RST(ic_reset) + // Inputs. + .REFCLK (iodelay_clk), + .RST (main_ic_reset) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(1'd0), - .D2(1'd1), - .D3(1'd0), - .D4(1'd1), - .D5(1'd0), - .D6(1'd1), - .D7(1'd0), - .D8(1'd1), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(a7ddrphy_sd_clk_se_nodelay) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (1'd0), + .D2 (1'd1), + .D3 (1'd0), + .D4 (1'd1), + .D5 (1'd0), + .D6 (1'd1), + .D7 (1'd0), + .D8 (1'd1), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_a7ddrphy_sd_clk_se_nodelay) ); +//------------------------------------------------------------------------------ +// Instance OBUFDS of OBUFDS Module. +//------------------------------------------------------------------------------ OBUFDS OBUFDS( - .I(a7ddrphy_sd_clk_se_nodelay), - .O(ddram_clk_p), - .OB(ddram_clk_n) + // Inputs. + .I (main_a7ddrphy_sd_clk_se_nodelay), + + // Outputs. + .O (ddram_clk_p), + .OB (ddram_clk_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_1 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_1 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_reset_n), - .D2(a7ddrphy_dfi_p0_reset_n), - .D3(a7ddrphy_dfi_p1_reset_n), - .D4(a7ddrphy_dfi_p1_reset_n), - .D5(a7ddrphy_dfi_p2_reset_n), - .D6(a7ddrphy_dfi_p2_reset_n), - .D7(a7ddrphy_dfi_p3_reset_n), - .D8(a7ddrphy_dfi_p3_reset_n), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_reset_n) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_reset_n), + .D2 (main_a7ddrphy_dfi_p0_reset_n), + .D3 (main_a7ddrphy_dfi_p1_reset_n), + .D4 (main_a7ddrphy_dfi_p1_reset_n), + .D5 (main_a7ddrphy_dfi_p2_reset_n), + .D6 (main_a7ddrphy_dfi_p2_reset_n), + .D7 (main_a7ddrphy_dfi_p3_reset_n), + .D8 (main_a7ddrphy_dfi_p3_reset_n), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_reset_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_2 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_2 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_cs_n), - .D2(a7ddrphy_dfi_p0_cs_n), - .D3(a7ddrphy_dfi_p1_cs_n), - .D4(a7ddrphy_dfi_p1_cs_n), - .D5(a7ddrphy_dfi_p2_cs_n), - .D6(a7ddrphy_dfi_p2_cs_n), - .D7(a7ddrphy_dfi_p3_cs_n), - .D8(a7ddrphy_dfi_p3_cs_n), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_cs_n) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_cs_n), + .D2 (main_a7ddrphy_dfi_p0_cs_n), + .D3 (main_a7ddrphy_dfi_p1_cs_n), + .D4 (main_a7ddrphy_dfi_p1_cs_n), + .D5 (main_a7ddrphy_dfi_p2_cs_n), + .D6 (main_a7ddrphy_dfi_p2_cs_n), + .D7 (main_a7ddrphy_dfi_p3_cs_n), + .D8 (main_a7ddrphy_dfi_p3_cs_n), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_cs_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_3 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_3 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[0]), - .D2(a7ddrphy_dfi_p0_address[0]), - .D3(a7ddrphy_dfi_p1_address[0]), - .D4(a7ddrphy_dfi_p1_address[0]), - .D5(a7ddrphy_dfi_p2_address[0]), - .D6(a7ddrphy_dfi_p2_address[0]), - .D7(a7ddrphy_dfi_p3_address[0]), - .D8(a7ddrphy_dfi_p3_address[0]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[0]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[0]), + .D2 (main_a7ddrphy_dfi_p0_address[0]), + .D3 (main_a7ddrphy_dfi_p1_address[0]), + .D4 (main_a7ddrphy_dfi_p1_address[0]), + .D5 (main_a7ddrphy_dfi_p2_address[0]), + .D6 (main_a7ddrphy_dfi_p2_address[0]), + .D7 (main_a7ddrphy_dfi_p3_address[0]), + .D8 (main_a7ddrphy_dfi_p3_address[0]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[0]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_4 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_4 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[1]), - .D2(a7ddrphy_dfi_p0_address[1]), - .D3(a7ddrphy_dfi_p1_address[1]), - .D4(a7ddrphy_dfi_p1_address[1]), - .D5(a7ddrphy_dfi_p2_address[1]), - .D6(a7ddrphy_dfi_p2_address[1]), - .D7(a7ddrphy_dfi_p3_address[1]), - .D8(a7ddrphy_dfi_p3_address[1]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[1]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[1]), + .D2 (main_a7ddrphy_dfi_p0_address[1]), + .D3 (main_a7ddrphy_dfi_p1_address[1]), + .D4 (main_a7ddrphy_dfi_p1_address[1]), + .D5 (main_a7ddrphy_dfi_p2_address[1]), + .D6 (main_a7ddrphy_dfi_p2_address[1]), + .D7 (main_a7ddrphy_dfi_p3_address[1]), + .D8 (main_a7ddrphy_dfi_p3_address[1]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[1]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_5 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_5 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[2]), - .D2(a7ddrphy_dfi_p0_address[2]), - .D3(a7ddrphy_dfi_p1_address[2]), - .D4(a7ddrphy_dfi_p1_address[2]), - .D5(a7ddrphy_dfi_p2_address[2]), - .D6(a7ddrphy_dfi_p2_address[2]), - .D7(a7ddrphy_dfi_p3_address[2]), - .D8(a7ddrphy_dfi_p3_address[2]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[2]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[2]), + .D2 (main_a7ddrphy_dfi_p0_address[2]), + .D3 (main_a7ddrphy_dfi_p1_address[2]), + .D4 (main_a7ddrphy_dfi_p1_address[2]), + .D5 (main_a7ddrphy_dfi_p2_address[2]), + .D6 (main_a7ddrphy_dfi_p2_address[2]), + .D7 (main_a7ddrphy_dfi_p3_address[2]), + .D8 (main_a7ddrphy_dfi_p3_address[2]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[2]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_6 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_6 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[3]), - .D2(a7ddrphy_dfi_p0_address[3]), - .D3(a7ddrphy_dfi_p1_address[3]), - .D4(a7ddrphy_dfi_p1_address[3]), - .D5(a7ddrphy_dfi_p2_address[3]), - .D6(a7ddrphy_dfi_p2_address[3]), - .D7(a7ddrphy_dfi_p3_address[3]), - .D8(a7ddrphy_dfi_p3_address[3]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[3]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[3]), + .D2 (main_a7ddrphy_dfi_p0_address[3]), + .D3 (main_a7ddrphy_dfi_p1_address[3]), + .D4 (main_a7ddrphy_dfi_p1_address[3]), + .D5 (main_a7ddrphy_dfi_p2_address[3]), + .D6 (main_a7ddrphy_dfi_p2_address[3]), + .D7 (main_a7ddrphy_dfi_p3_address[3]), + .D8 (main_a7ddrphy_dfi_p3_address[3]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[3]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_7 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_7 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[4]), - .D2(a7ddrphy_dfi_p0_address[4]), - .D3(a7ddrphy_dfi_p1_address[4]), - .D4(a7ddrphy_dfi_p1_address[4]), - .D5(a7ddrphy_dfi_p2_address[4]), - .D6(a7ddrphy_dfi_p2_address[4]), - .D7(a7ddrphy_dfi_p3_address[4]), - .D8(a7ddrphy_dfi_p3_address[4]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[4]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[4]), + .D2 (main_a7ddrphy_dfi_p0_address[4]), + .D3 (main_a7ddrphy_dfi_p1_address[4]), + .D4 (main_a7ddrphy_dfi_p1_address[4]), + .D5 (main_a7ddrphy_dfi_p2_address[4]), + .D6 (main_a7ddrphy_dfi_p2_address[4]), + .D7 (main_a7ddrphy_dfi_p3_address[4]), + .D8 (main_a7ddrphy_dfi_p3_address[4]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[4]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_8 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_8 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[5]), - .D2(a7ddrphy_dfi_p0_address[5]), - .D3(a7ddrphy_dfi_p1_address[5]), - .D4(a7ddrphy_dfi_p1_address[5]), - .D5(a7ddrphy_dfi_p2_address[5]), - .D6(a7ddrphy_dfi_p2_address[5]), - .D7(a7ddrphy_dfi_p3_address[5]), - .D8(a7ddrphy_dfi_p3_address[5]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[5]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[5]), + .D2 (main_a7ddrphy_dfi_p0_address[5]), + .D3 (main_a7ddrphy_dfi_p1_address[5]), + .D4 (main_a7ddrphy_dfi_p1_address[5]), + .D5 (main_a7ddrphy_dfi_p2_address[5]), + .D6 (main_a7ddrphy_dfi_p2_address[5]), + .D7 (main_a7ddrphy_dfi_p3_address[5]), + .D8 (main_a7ddrphy_dfi_p3_address[5]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[5]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_9 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_9 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[6]), - .D2(a7ddrphy_dfi_p0_address[6]), - .D3(a7ddrphy_dfi_p1_address[6]), - .D4(a7ddrphy_dfi_p1_address[6]), - .D5(a7ddrphy_dfi_p2_address[6]), - .D6(a7ddrphy_dfi_p2_address[6]), - .D7(a7ddrphy_dfi_p3_address[6]), - .D8(a7ddrphy_dfi_p3_address[6]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[6]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[6]), + .D2 (main_a7ddrphy_dfi_p0_address[6]), + .D3 (main_a7ddrphy_dfi_p1_address[6]), + .D4 (main_a7ddrphy_dfi_p1_address[6]), + .D5 (main_a7ddrphy_dfi_p2_address[6]), + .D6 (main_a7ddrphy_dfi_p2_address[6]), + .D7 (main_a7ddrphy_dfi_p3_address[6]), + .D8 (main_a7ddrphy_dfi_p3_address[6]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[6]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_10 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_10 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[7]), - .D2(a7ddrphy_dfi_p0_address[7]), - .D3(a7ddrphy_dfi_p1_address[7]), - .D4(a7ddrphy_dfi_p1_address[7]), - .D5(a7ddrphy_dfi_p2_address[7]), - .D6(a7ddrphy_dfi_p2_address[7]), - .D7(a7ddrphy_dfi_p3_address[7]), - .D8(a7ddrphy_dfi_p3_address[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[7]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[7]), + .D2 (main_a7ddrphy_dfi_p0_address[7]), + .D3 (main_a7ddrphy_dfi_p1_address[7]), + .D4 (main_a7ddrphy_dfi_p1_address[7]), + .D5 (main_a7ddrphy_dfi_p2_address[7]), + .D6 (main_a7ddrphy_dfi_p2_address[7]), + .D7 (main_a7ddrphy_dfi_p3_address[7]), + .D8 (main_a7ddrphy_dfi_p3_address[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[7]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_11 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_11 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[8]), - .D2(a7ddrphy_dfi_p0_address[8]), - .D3(a7ddrphy_dfi_p1_address[8]), - .D4(a7ddrphy_dfi_p1_address[8]), - .D5(a7ddrphy_dfi_p2_address[8]), - .D6(a7ddrphy_dfi_p2_address[8]), - .D7(a7ddrphy_dfi_p3_address[8]), - .D8(a7ddrphy_dfi_p3_address[8]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[8]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[8]), + .D2 (main_a7ddrphy_dfi_p0_address[8]), + .D3 (main_a7ddrphy_dfi_p1_address[8]), + .D4 (main_a7ddrphy_dfi_p1_address[8]), + .D5 (main_a7ddrphy_dfi_p2_address[8]), + .D6 (main_a7ddrphy_dfi_p2_address[8]), + .D7 (main_a7ddrphy_dfi_p3_address[8]), + .D8 (main_a7ddrphy_dfi_p3_address[8]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[8]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_12 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_12 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[9]), - .D2(a7ddrphy_dfi_p0_address[9]), - .D3(a7ddrphy_dfi_p1_address[9]), - .D4(a7ddrphy_dfi_p1_address[9]), - .D5(a7ddrphy_dfi_p2_address[9]), - .D6(a7ddrphy_dfi_p2_address[9]), - .D7(a7ddrphy_dfi_p3_address[9]), - .D8(a7ddrphy_dfi_p3_address[9]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[9]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[9]), + .D2 (main_a7ddrphy_dfi_p0_address[9]), + .D3 (main_a7ddrphy_dfi_p1_address[9]), + .D4 (main_a7ddrphy_dfi_p1_address[9]), + .D5 (main_a7ddrphy_dfi_p2_address[9]), + .D6 (main_a7ddrphy_dfi_p2_address[9]), + .D7 (main_a7ddrphy_dfi_p3_address[9]), + .D8 (main_a7ddrphy_dfi_p3_address[9]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[9]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_13 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_13 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[10]), - .D2(a7ddrphy_dfi_p0_address[10]), - .D3(a7ddrphy_dfi_p1_address[10]), - .D4(a7ddrphy_dfi_p1_address[10]), - .D5(a7ddrphy_dfi_p2_address[10]), - .D6(a7ddrphy_dfi_p2_address[10]), - .D7(a7ddrphy_dfi_p3_address[10]), - .D8(a7ddrphy_dfi_p3_address[10]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[10]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[10]), + .D2 (main_a7ddrphy_dfi_p0_address[10]), + .D3 (main_a7ddrphy_dfi_p1_address[10]), + .D4 (main_a7ddrphy_dfi_p1_address[10]), + .D5 (main_a7ddrphy_dfi_p2_address[10]), + .D6 (main_a7ddrphy_dfi_p2_address[10]), + .D7 (main_a7ddrphy_dfi_p3_address[10]), + .D8 (main_a7ddrphy_dfi_p3_address[10]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[10]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_14 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_14 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[11]), - .D2(a7ddrphy_dfi_p0_address[11]), - .D3(a7ddrphy_dfi_p1_address[11]), - .D4(a7ddrphy_dfi_p1_address[11]), - .D5(a7ddrphy_dfi_p2_address[11]), - .D6(a7ddrphy_dfi_p2_address[11]), - .D7(a7ddrphy_dfi_p3_address[11]), - .D8(a7ddrphy_dfi_p3_address[11]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[11]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[11]), + .D2 (main_a7ddrphy_dfi_p0_address[11]), + .D3 (main_a7ddrphy_dfi_p1_address[11]), + .D4 (main_a7ddrphy_dfi_p1_address[11]), + .D5 (main_a7ddrphy_dfi_p2_address[11]), + .D6 (main_a7ddrphy_dfi_p2_address[11]), + .D7 (main_a7ddrphy_dfi_p3_address[11]), + .D8 (main_a7ddrphy_dfi_p3_address[11]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[11]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_15 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_15 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[12]), - .D2(a7ddrphy_dfi_p0_address[12]), - .D3(a7ddrphy_dfi_p1_address[12]), - .D4(a7ddrphy_dfi_p1_address[12]), - .D5(a7ddrphy_dfi_p2_address[12]), - .D6(a7ddrphy_dfi_p2_address[12]), - .D7(a7ddrphy_dfi_p3_address[12]), - .D8(a7ddrphy_dfi_p3_address[12]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[12]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[12]), + .D2 (main_a7ddrphy_dfi_p0_address[12]), + .D3 (main_a7ddrphy_dfi_p1_address[12]), + .D4 (main_a7ddrphy_dfi_p1_address[12]), + .D5 (main_a7ddrphy_dfi_p2_address[12]), + .D6 (main_a7ddrphy_dfi_p2_address[12]), + .D7 (main_a7ddrphy_dfi_p3_address[12]), + .D8 (main_a7ddrphy_dfi_p3_address[12]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[12]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_16 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_16 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[13]), - .D2(a7ddrphy_dfi_p0_address[13]), - .D3(a7ddrphy_dfi_p1_address[13]), - .D4(a7ddrphy_dfi_p1_address[13]), - .D5(a7ddrphy_dfi_p2_address[13]), - .D6(a7ddrphy_dfi_p2_address[13]), - .D7(a7ddrphy_dfi_p3_address[13]), - .D8(a7ddrphy_dfi_p3_address[13]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[13]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[13]), + .D2 (main_a7ddrphy_dfi_p0_address[13]), + .D3 (main_a7ddrphy_dfi_p1_address[13]), + .D4 (main_a7ddrphy_dfi_p1_address[13]), + .D5 (main_a7ddrphy_dfi_p2_address[13]), + .D6 (main_a7ddrphy_dfi_p2_address[13]), + .D7 (main_a7ddrphy_dfi_p3_address[13]), + .D8 (main_a7ddrphy_dfi_p3_address[13]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[13]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_17 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_17 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_bank[0]), - .D2(a7ddrphy_dfi_p0_bank[0]), - .D3(a7ddrphy_dfi_p1_bank[0]), - .D4(a7ddrphy_dfi_p1_bank[0]), - .D5(a7ddrphy_dfi_p2_bank[0]), - .D6(a7ddrphy_dfi_p2_bank[0]), - .D7(a7ddrphy_dfi_p3_bank[0]), - .D8(a7ddrphy_dfi_p3_bank[0]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(a7ddrphy_pads_ba[0]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_bank[0]), + .D2 (main_a7ddrphy_dfi_p0_bank[0]), + .D3 (main_a7ddrphy_dfi_p1_bank[0]), + .D4 (main_a7ddrphy_dfi_p1_bank[0]), + .D5 (main_a7ddrphy_dfi_p2_bank[0]), + .D6 (main_a7ddrphy_dfi_p2_bank[0]), + .D7 (main_a7ddrphy_dfi_p3_bank[0]), + .D8 (main_a7ddrphy_dfi_p3_bank[0]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_a7ddrphy_pads_ba[0]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_18 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_18 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_bank[1]), - .D2(a7ddrphy_dfi_p0_bank[1]), - .D3(a7ddrphy_dfi_p1_bank[1]), - .D4(a7ddrphy_dfi_p1_bank[1]), - .D5(a7ddrphy_dfi_p2_bank[1]), - .D6(a7ddrphy_dfi_p2_bank[1]), - .D7(a7ddrphy_dfi_p3_bank[1]), - .D8(a7ddrphy_dfi_p3_bank[1]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(a7ddrphy_pads_ba[1]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_bank[1]), + .D2 (main_a7ddrphy_dfi_p0_bank[1]), + .D3 (main_a7ddrphy_dfi_p1_bank[1]), + .D4 (main_a7ddrphy_dfi_p1_bank[1]), + .D5 (main_a7ddrphy_dfi_p2_bank[1]), + .D6 (main_a7ddrphy_dfi_p2_bank[1]), + .D7 (main_a7ddrphy_dfi_p3_bank[1]), + .D8 (main_a7ddrphy_dfi_p3_bank[1]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_a7ddrphy_pads_ba[1]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_19 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_19 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_bank[2]), - .D2(a7ddrphy_dfi_p0_bank[2]), - .D3(a7ddrphy_dfi_p1_bank[2]), - .D4(a7ddrphy_dfi_p1_bank[2]), - .D5(a7ddrphy_dfi_p2_bank[2]), - .D6(a7ddrphy_dfi_p2_bank[2]), - .D7(a7ddrphy_dfi_p3_bank[2]), - .D8(a7ddrphy_dfi_p3_bank[2]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(a7ddrphy_pads_ba[2]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_bank[2]), + .D2 (main_a7ddrphy_dfi_p0_bank[2]), + .D3 (main_a7ddrphy_dfi_p1_bank[2]), + .D4 (main_a7ddrphy_dfi_p1_bank[2]), + .D5 (main_a7ddrphy_dfi_p2_bank[2]), + .D6 (main_a7ddrphy_dfi_p2_bank[2]), + .D7 (main_a7ddrphy_dfi_p3_bank[2]), + .D8 (main_a7ddrphy_dfi_p3_bank[2]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_a7ddrphy_pads_ba[2]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_20 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_20 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_ras_n), - .D2(a7ddrphy_dfi_p0_ras_n), - .D3(a7ddrphy_dfi_p1_ras_n), - .D4(a7ddrphy_dfi_p1_ras_n), - .D5(a7ddrphy_dfi_p2_ras_n), - .D6(a7ddrphy_dfi_p2_ras_n), - .D7(a7ddrphy_dfi_p3_ras_n), - .D8(a7ddrphy_dfi_p3_ras_n), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_ras_n) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_ras_n), + .D2 (main_a7ddrphy_dfi_p0_ras_n), + .D3 (main_a7ddrphy_dfi_p1_ras_n), + .D4 (main_a7ddrphy_dfi_p1_ras_n), + .D5 (main_a7ddrphy_dfi_p2_ras_n), + .D6 (main_a7ddrphy_dfi_p2_ras_n), + .D7 (main_a7ddrphy_dfi_p3_ras_n), + .D8 (main_a7ddrphy_dfi_p3_ras_n), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_ras_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_21 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_21 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_cas_n), - .D2(a7ddrphy_dfi_p0_cas_n), - .D3(a7ddrphy_dfi_p1_cas_n), - .D4(a7ddrphy_dfi_p1_cas_n), - .D5(a7ddrphy_dfi_p2_cas_n), - .D6(a7ddrphy_dfi_p2_cas_n), - .D7(a7ddrphy_dfi_p3_cas_n), - .D8(a7ddrphy_dfi_p3_cas_n), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_cas_n) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_cas_n), + .D2 (main_a7ddrphy_dfi_p0_cas_n), + .D3 (main_a7ddrphy_dfi_p1_cas_n), + .D4 (main_a7ddrphy_dfi_p1_cas_n), + .D5 (main_a7ddrphy_dfi_p2_cas_n), + .D6 (main_a7ddrphy_dfi_p2_cas_n), + .D7 (main_a7ddrphy_dfi_p3_cas_n), + .D8 (main_a7ddrphy_dfi_p3_cas_n), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_cas_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_22 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_22 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_we_n), - .D2(a7ddrphy_dfi_p0_we_n), - .D3(a7ddrphy_dfi_p1_we_n), - .D4(a7ddrphy_dfi_p1_we_n), - .D5(a7ddrphy_dfi_p2_we_n), - .D6(a7ddrphy_dfi_p2_we_n), - .D7(a7ddrphy_dfi_p3_we_n), - .D8(a7ddrphy_dfi_p3_we_n), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_we_n) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_we_n), + .D2 (main_a7ddrphy_dfi_p0_we_n), + .D3 (main_a7ddrphy_dfi_p1_we_n), + .D4 (main_a7ddrphy_dfi_p1_we_n), + .D5 (main_a7ddrphy_dfi_p2_we_n), + .D6 (main_a7ddrphy_dfi_p2_we_n), + .D7 (main_a7ddrphy_dfi_p3_we_n), + .D8 (main_a7ddrphy_dfi_p3_we_n), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_we_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_23 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_23 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_cke), - .D2(a7ddrphy_dfi_p0_cke), - .D3(a7ddrphy_dfi_p1_cke), - .D4(a7ddrphy_dfi_p1_cke), - .D5(a7ddrphy_dfi_p2_cke), - .D6(a7ddrphy_dfi_p2_cke), - .D7(a7ddrphy_dfi_p3_cke), - .D8(a7ddrphy_dfi_p3_cke), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_cke) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_cke), + .D2 (main_a7ddrphy_dfi_p0_cke), + .D3 (main_a7ddrphy_dfi_p1_cke), + .D4 (main_a7ddrphy_dfi_p1_cke), + .D5 (main_a7ddrphy_dfi_p2_cke), + .D6 (main_a7ddrphy_dfi_p2_cke), + .D7 (main_a7ddrphy_dfi_p3_cke), + .D8 (main_a7ddrphy_dfi_p3_cke), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_cke) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_24 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_24 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_odt), - .D2(a7ddrphy_dfi_p0_odt), - .D3(a7ddrphy_dfi_p1_odt), - .D4(a7ddrphy_dfi_p1_odt), - .D5(a7ddrphy_dfi_p2_odt), - .D6(a7ddrphy_dfi_p2_odt), - .D7(a7ddrphy_dfi_p3_odt), - .D8(a7ddrphy_dfi_p3_odt), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_odt) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_odt), + .D2 (main_a7ddrphy_dfi_p0_odt), + .D3 (main_a7ddrphy_dfi_p1_odt), + .D4 (main_a7ddrphy_dfi_p1_odt), + .D5 (main_a7ddrphy_dfi_p2_odt), + .D6 (main_a7ddrphy_dfi_p2_odt), + .D7 (main_a7ddrphy_dfi_p3_odt), + .D8 (main_a7ddrphy_dfi_p3_odt), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_odt) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_25 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_25 ( - .CLK(sys4x_dqs_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip00[0]), - .D2(a7ddrphy_bitslip00[1]), - .D3(a7ddrphy_bitslip00[2]), - .D4(a7ddrphy_bitslip00[3]), - .D5(a7ddrphy_bitslip00[4]), - .D6(a7ddrphy_bitslip00[5]), - .D7(a7ddrphy_bitslip00[6]), - .D8(a7ddrphy_bitslip00[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OFB(a7ddrphy0), - .OQ(a7ddrphy_dqs_o_no_delay0), - .TQ(a7ddrphy_dqs_t0) + // Inputs. + .CLK (sys4x_dqs_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip00[0]), + .D2 (main_a7ddrphy_bitslip00[1]), + .D3 (main_a7ddrphy_bitslip00[2]), + .D4 (main_a7ddrphy_bitslip00[3]), + .D5 (main_a7ddrphy_bitslip00[4]), + .D6 (main_a7ddrphy_bitslip00[5]), + .D7 (main_a7ddrphy_bitslip00[6]), + .D8 (main_a7ddrphy_bitslip00[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OFB (main_a7ddrphy0), + .OQ (main_a7ddrphy_dqs_o_no_delay0), + .TQ (main_a7ddrphy_dqs_t0) ); +//------------------------------------------------------------------------------ +// Instance IOBUFDS of IOBUFDS Module. +//------------------------------------------------------------------------------ IOBUFDS IOBUFDS( - .I(a7ddrphy_dqs_o_no_delay0), - .T(a7ddrphy_dqs_t0), - .IO(ddram_dqs_p[0]), - .IOB(ddram_dqs_n[0]) + // Inputs. + .I (main_a7ddrphy_dqs_o_no_delay0), + .T (main_a7ddrphy_dqs_t0), + + // InOuts. + .IO (ddram_dqs_p[0]), + .IOB (ddram_dqs_n[0]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_26 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_26 ( - .CLK(sys4x_dqs_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip10[0]), - .D2(a7ddrphy_bitslip10[1]), - .D3(a7ddrphy_bitslip10[2]), - .D4(a7ddrphy_bitslip10[3]), - .D5(a7ddrphy_bitslip10[4]), - .D6(a7ddrphy_bitslip10[5]), - .D7(a7ddrphy_bitslip10[6]), - .D8(a7ddrphy_bitslip10[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OFB(a7ddrphy1), - .OQ(a7ddrphy_dqs_o_no_delay1), - .TQ(a7ddrphy_dqs_t1) + // Inputs. + .CLK (sys4x_dqs_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip10[0]), + .D2 (main_a7ddrphy_bitslip10[1]), + .D3 (main_a7ddrphy_bitslip10[2]), + .D4 (main_a7ddrphy_bitslip10[3]), + .D5 (main_a7ddrphy_bitslip10[4]), + .D6 (main_a7ddrphy_bitslip10[5]), + .D7 (main_a7ddrphy_bitslip10[6]), + .D8 (main_a7ddrphy_bitslip10[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OFB (main_a7ddrphy1), + .OQ (main_a7ddrphy_dqs_o_no_delay1), + .TQ (main_a7ddrphy_dqs_t1) ); +//------------------------------------------------------------------------------ +// Instance IOBUFDS_1 of IOBUFDS Module. +//------------------------------------------------------------------------------ IOBUFDS IOBUFDS_1( - .I(a7ddrphy_dqs_o_no_delay1), - .T(a7ddrphy_dqs_t1), - .IO(ddram_dqs_p[1]), - .IOB(ddram_dqs_n[1]) + // Inputs. + .I (main_a7ddrphy_dqs_o_no_delay1), + .T (main_a7ddrphy_dqs_t1), + + // InOuts. + .IO (ddram_dqs_p[1]), + .IOB (ddram_dqs_n[1]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_27 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_27 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip01[0]), - .D2(a7ddrphy_bitslip01[1]), - .D3(a7ddrphy_bitslip01[2]), - .D4(a7ddrphy_bitslip01[3]), - .D5(a7ddrphy_bitslip01[4]), - .D6(a7ddrphy_bitslip01[5]), - .D7(a7ddrphy_bitslip01[6]), - .D8(a7ddrphy_bitslip01[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_dm[0]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip01[0]), + .D2 (main_a7ddrphy_bitslip01[1]), + .D3 (main_a7ddrphy_bitslip01[2]), + .D4 (main_a7ddrphy_bitslip01[3]), + .D5 (main_a7ddrphy_bitslip01[4]), + .D6 (main_a7ddrphy_bitslip01[5]), + .D7 (main_a7ddrphy_bitslip01[6]), + .D8 (main_a7ddrphy_bitslip01[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_dm[0]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_28 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_28 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip11[0]), - .D2(a7ddrphy_bitslip11[1]), - .D3(a7ddrphy_bitslip11[2]), - .D4(a7ddrphy_bitslip11[3]), - .D5(a7ddrphy_bitslip11[4]), - .D6(a7ddrphy_bitslip11[5]), - .D7(a7ddrphy_bitslip11[6]), - .D8(a7ddrphy_bitslip11[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_dm[1]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip11[0]), + .D2 (main_a7ddrphy_bitslip11[1]), + .D3 (main_a7ddrphy_bitslip11[2]), + .D4 (main_a7ddrphy_bitslip11[3]), + .D5 (main_a7ddrphy_bitslip11[4]), + .D6 (main_a7ddrphy_bitslip11[5]), + .D7 (main_a7ddrphy_bitslip11[6]), + .D8 (main_a7ddrphy_bitslip11[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_dm[1]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_29 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_29 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip02[0]), - .D2(a7ddrphy_bitslip02[1]), - .D3(a7ddrphy_bitslip02[2]), - .D4(a7ddrphy_bitslip02[3]), - .D5(a7ddrphy_bitslip02[4]), - .D6(a7ddrphy_bitslip02[5]), - .D7(a7ddrphy_bitslip02[6]), - .D8(a7ddrphy_bitslip02[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay0), - .TQ(a7ddrphy_dq_t0) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip02[0]), + .D2 (main_a7ddrphy_bitslip02[1]), + .D3 (main_a7ddrphy_bitslip02[2]), + .D4 (main_a7ddrphy_bitslip02[3]), + .D5 (main_a7ddrphy_bitslip02[4]), + .D6 (main_a7ddrphy_bitslip02[5]), + .D7 (main_a7ddrphy_bitslip02[6]), + .D8 (main_a7ddrphy_bitslip02[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay0), + .TQ (main_a7ddrphy_dq_t0) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed0), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip03[7]), - .Q2(a7ddrphy_bitslip03[6]), - .Q3(a7ddrphy_bitslip03[5]), - .Q4(a7ddrphy_bitslip03[4]), - .Q5(a7ddrphy_bitslip03[3]), - .Q6(a7ddrphy_bitslip03[2]), - .Q7(a7ddrphy_bitslip03[1]), - .Q8(a7ddrphy_bitslip03[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed0), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip03[7]), + .Q2 (main_a7ddrphy_bitslip03[6]), + .Q3 (main_a7ddrphy_bitslip03[5]), + .Q4 (main_a7ddrphy_bitslip03[4]), + .Q5 (main_a7ddrphy_bitslip03[3]), + .Q6 (main_a7ddrphy_bitslip03[2]), + .Q7 (main_a7ddrphy_bitslip03[1]), + .Q8 (main_a7ddrphy_bitslip03[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay0), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed0) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay0), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed0) ); +//------------------------------------------------------------------------------ +// Instance IOBUF of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF( - .I(a7ddrphy_dq_o_nodelay0), - .T(a7ddrphy_dq_t0), - .IO(ddram_dq[0]), - .O(a7ddrphy_dq_i_nodelay0) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay0), + .T (main_a7ddrphy_dq_t0), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay0), + + // InOuts. + .IO (ddram_dq[0]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_30 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_30 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip12[0]), - .D2(a7ddrphy_bitslip12[1]), - .D3(a7ddrphy_bitslip12[2]), - .D4(a7ddrphy_bitslip12[3]), - .D5(a7ddrphy_bitslip12[4]), - .D6(a7ddrphy_bitslip12[5]), - .D7(a7ddrphy_bitslip12[6]), - .D8(a7ddrphy_bitslip12[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay1), - .TQ(a7ddrphy_dq_t1) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip12[0]), + .D2 (main_a7ddrphy_bitslip12[1]), + .D3 (main_a7ddrphy_bitslip12[2]), + .D4 (main_a7ddrphy_bitslip12[3]), + .D5 (main_a7ddrphy_bitslip12[4]), + .D6 (main_a7ddrphy_bitslip12[5]), + .D7 (main_a7ddrphy_bitslip12[6]), + .D8 (main_a7ddrphy_bitslip12[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay1), + .TQ (main_a7ddrphy_dq_t1) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_1 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_1 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip13[7]), - .Q2(a7ddrphy_bitslip13[6]), - .Q3(a7ddrphy_bitslip13[5]), - .Q4(a7ddrphy_bitslip13[4]), - .Q5(a7ddrphy_bitslip13[3]), - .Q6(a7ddrphy_bitslip13[2]), - .Q7(a7ddrphy_bitslip13[1]), - .Q8(a7ddrphy_bitslip13[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip13[7]), + .Q2 (main_a7ddrphy_bitslip13[6]), + .Q3 (main_a7ddrphy_bitslip13[5]), + .Q4 (main_a7ddrphy_bitslip13[4]), + .Q5 (main_a7ddrphy_bitslip13[3]), + .Q6 (main_a7ddrphy_bitslip13[2]), + .Q7 (main_a7ddrphy_bitslip13[1]), + .Q8 (main_a7ddrphy_bitslip13[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_1 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_1 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay1), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed1) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay1), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed1) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_1 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_1( - .I(a7ddrphy_dq_o_nodelay1), - .T(a7ddrphy_dq_t1), - .IO(ddram_dq[1]), - .O(a7ddrphy_dq_i_nodelay1) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay1), + .T (main_a7ddrphy_dq_t1), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay1), + + // InOuts. + .IO (ddram_dq[1]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_31 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_31 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip20[0]), - .D2(a7ddrphy_bitslip20[1]), - .D3(a7ddrphy_bitslip20[2]), - .D4(a7ddrphy_bitslip20[3]), - .D5(a7ddrphy_bitslip20[4]), - .D6(a7ddrphy_bitslip20[5]), - .D7(a7ddrphy_bitslip20[6]), - .D8(a7ddrphy_bitslip20[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay2), - .TQ(a7ddrphy_dq_t2) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip20[0]), + .D2 (main_a7ddrphy_bitslip20[1]), + .D3 (main_a7ddrphy_bitslip20[2]), + .D4 (main_a7ddrphy_bitslip20[3]), + .D5 (main_a7ddrphy_bitslip20[4]), + .D6 (main_a7ddrphy_bitslip20[5]), + .D7 (main_a7ddrphy_bitslip20[6]), + .D8 (main_a7ddrphy_bitslip20[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay2), + .TQ (main_a7ddrphy_dq_t2) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_2 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_2 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed2), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip21[7]), - .Q2(a7ddrphy_bitslip21[6]), - .Q3(a7ddrphy_bitslip21[5]), - .Q4(a7ddrphy_bitslip21[4]), - .Q5(a7ddrphy_bitslip21[3]), - .Q6(a7ddrphy_bitslip21[2]), - .Q7(a7ddrphy_bitslip21[1]), - .Q8(a7ddrphy_bitslip21[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed2), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip21[7]), + .Q2 (main_a7ddrphy_bitslip21[6]), + .Q3 (main_a7ddrphy_bitslip21[5]), + .Q4 (main_a7ddrphy_bitslip21[4]), + .Q5 (main_a7ddrphy_bitslip21[3]), + .Q6 (main_a7ddrphy_bitslip21[2]), + .Q7 (main_a7ddrphy_bitslip21[1]), + .Q8 (main_a7ddrphy_bitslip21[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_2 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_2 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay2), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed2) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay2), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed2) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_2 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_2( - .I(a7ddrphy_dq_o_nodelay2), - .T(a7ddrphy_dq_t2), - .IO(ddram_dq[2]), - .O(a7ddrphy_dq_i_nodelay2) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay2), + .T (main_a7ddrphy_dq_t2), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay2), + + // InOuts. + .IO (ddram_dq[2]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_32 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_32 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip30[0]), - .D2(a7ddrphy_bitslip30[1]), - .D3(a7ddrphy_bitslip30[2]), - .D4(a7ddrphy_bitslip30[3]), - .D5(a7ddrphy_bitslip30[4]), - .D6(a7ddrphy_bitslip30[5]), - .D7(a7ddrphy_bitslip30[6]), - .D8(a7ddrphy_bitslip30[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay3), - .TQ(a7ddrphy_dq_t3) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip30[0]), + .D2 (main_a7ddrphy_bitslip30[1]), + .D3 (main_a7ddrphy_bitslip30[2]), + .D4 (main_a7ddrphy_bitslip30[3]), + .D5 (main_a7ddrphy_bitslip30[4]), + .D6 (main_a7ddrphy_bitslip30[5]), + .D7 (main_a7ddrphy_bitslip30[6]), + .D8 (main_a7ddrphy_bitslip30[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay3), + .TQ (main_a7ddrphy_dq_t3) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_3 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_3 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed3), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip31[7]), - .Q2(a7ddrphy_bitslip31[6]), - .Q3(a7ddrphy_bitslip31[5]), - .Q4(a7ddrphy_bitslip31[4]), - .Q5(a7ddrphy_bitslip31[3]), - .Q6(a7ddrphy_bitslip31[2]), - .Q7(a7ddrphy_bitslip31[1]), - .Q8(a7ddrphy_bitslip31[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed3), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip31[7]), + .Q2 (main_a7ddrphy_bitslip31[6]), + .Q3 (main_a7ddrphy_bitslip31[5]), + .Q4 (main_a7ddrphy_bitslip31[4]), + .Q5 (main_a7ddrphy_bitslip31[3]), + .Q6 (main_a7ddrphy_bitslip31[2]), + .Q7 (main_a7ddrphy_bitslip31[1]), + .Q8 (main_a7ddrphy_bitslip31[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_3 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_3 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay3), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed3) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay3), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed3) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_3 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_3( - .I(a7ddrphy_dq_o_nodelay3), - .T(a7ddrphy_dq_t3), - .IO(ddram_dq[3]), - .O(a7ddrphy_dq_i_nodelay3) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay3), + .T (main_a7ddrphy_dq_t3), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay3), + + // InOuts. + .IO (ddram_dq[3]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_33 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_33 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip40[0]), - .D2(a7ddrphy_bitslip40[1]), - .D3(a7ddrphy_bitslip40[2]), - .D4(a7ddrphy_bitslip40[3]), - .D5(a7ddrphy_bitslip40[4]), - .D6(a7ddrphy_bitslip40[5]), - .D7(a7ddrphy_bitslip40[6]), - .D8(a7ddrphy_bitslip40[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay4), - .TQ(a7ddrphy_dq_t4) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip40[0]), + .D2 (main_a7ddrphy_bitslip40[1]), + .D3 (main_a7ddrphy_bitslip40[2]), + .D4 (main_a7ddrphy_bitslip40[3]), + .D5 (main_a7ddrphy_bitslip40[4]), + .D6 (main_a7ddrphy_bitslip40[5]), + .D7 (main_a7ddrphy_bitslip40[6]), + .D8 (main_a7ddrphy_bitslip40[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay4), + .TQ (main_a7ddrphy_dq_t4) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_4 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_4 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed4), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip41[7]), - .Q2(a7ddrphy_bitslip41[6]), - .Q3(a7ddrphy_bitslip41[5]), - .Q4(a7ddrphy_bitslip41[4]), - .Q5(a7ddrphy_bitslip41[3]), - .Q6(a7ddrphy_bitslip41[2]), - .Q7(a7ddrphy_bitslip41[1]), - .Q8(a7ddrphy_bitslip41[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed4), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip41[7]), + .Q2 (main_a7ddrphy_bitslip41[6]), + .Q3 (main_a7ddrphy_bitslip41[5]), + .Q4 (main_a7ddrphy_bitslip41[4]), + .Q5 (main_a7ddrphy_bitslip41[3]), + .Q6 (main_a7ddrphy_bitslip41[2]), + .Q7 (main_a7ddrphy_bitslip41[1]), + .Q8 (main_a7ddrphy_bitslip41[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_4 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_4 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay4), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed4) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay4), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed4) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_4 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_4( - .I(a7ddrphy_dq_o_nodelay4), - .T(a7ddrphy_dq_t4), - .IO(ddram_dq[4]), - .O(a7ddrphy_dq_i_nodelay4) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay4), + .T (main_a7ddrphy_dq_t4), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay4), + + // InOuts. + .IO (ddram_dq[4]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_34 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_34 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip50[0]), - .D2(a7ddrphy_bitslip50[1]), - .D3(a7ddrphy_bitslip50[2]), - .D4(a7ddrphy_bitslip50[3]), - .D5(a7ddrphy_bitslip50[4]), - .D6(a7ddrphy_bitslip50[5]), - .D7(a7ddrphy_bitslip50[6]), - .D8(a7ddrphy_bitslip50[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay5), - .TQ(a7ddrphy_dq_t5) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip50[0]), + .D2 (main_a7ddrphy_bitslip50[1]), + .D3 (main_a7ddrphy_bitslip50[2]), + .D4 (main_a7ddrphy_bitslip50[3]), + .D5 (main_a7ddrphy_bitslip50[4]), + .D6 (main_a7ddrphy_bitslip50[5]), + .D7 (main_a7ddrphy_bitslip50[6]), + .D8 (main_a7ddrphy_bitslip50[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay5), + .TQ (main_a7ddrphy_dq_t5) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_5 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_5 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed5), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip51[7]), - .Q2(a7ddrphy_bitslip51[6]), - .Q3(a7ddrphy_bitslip51[5]), - .Q4(a7ddrphy_bitslip51[4]), - .Q5(a7ddrphy_bitslip51[3]), - .Q6(a7ddrphy_bitslip51[2]), - .Q7(a7ddrphy_bitslip51[1]), - .Q8(a7ddrphy_bitslip51[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed5), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip51[7]), + .Q2 (main_a7ddrphy_bitslip51[6]), + .Q3 (main_a7ddrphy_bitslip51[5]), + .Q4 (main_a7ddrphy_bitslip51[4]), + .Q5 (main_a7ddrphy_bitslip51[3]), + .Q6 (main_a7ddrphy_bitslip51[2]), + .Q7 (main_a7ddrphy_bitslip51[1]), + .Q8 (main_a7ddrphy_bitslip51[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_5 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_5 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay5), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed5) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay5), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed5) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_5 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_5( - .I(a7ddrphy_dq_o_nodelay5), - .T(a7ddrphy_dq_t5), - .IO(ddram_dq[5]), - .O(a7ddrphy_dq_i_nodelay5) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay5), + .T (main_a7ddrphy_dq_t5), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay5), + + // InOuts. + .IO (ddram_dq[5]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_35 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_35 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip60[0]), - .D2(a7ddrphy_bitslip60[1]), - .D3(a7ddrphy_bitslip60[2]), - .D4(a7ddrphy_bitslip60[3]), - .D5(a7ddrphy_bitslip60[4]), - .D6(a7ddrphy_bitslip60[5]), - .D7(a7ddrphy_bitslip60[6]), - .D8(a7ddrphy_bitslip60[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay6), - .TQ(a7ddrphy_dq_t6) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip60[0]), + .D2 (main_a7ddrphy_bitslip60[1]), + .D3 (main_a7ddrphy_bitslip60[2]), + .D4 (main_a7ddrphy_bitslip60[3]), + .D5 (main_a7ddrphy_bitslip60[4]), + .D6 (main_a7ddrphy_bitslip60[5]), + .D7 (main_a7ddrphy_bitslip60[6]), + .D8 (main_a7ddrphy_bitslip60[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay6), + .TQ (main_a7ddrphy_dq_t6) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_6 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_6 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed6), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip61[7]), - .Q2(a7ddrphy_bitslip61[6]), - .Q3(a7ddrphy_bitslip61[5]), - .Q4(a7ddrphy_bitslip61[4]), - .Q5(a7ddrphy_bitslip61[3]), - .Q6(a7ddrphy_bitslip61[2]), - .Q7(a7ddrphy_bitslip61[1]), - .Q8(a7ddrphy_bitslip61[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed6), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip61[7]), + .Q2 (main_a7ddrphy_bitslip61[6]), + .Q3 (main_a7ddrphy_bitslip61[5]), + .Q4 (main_a7ddrphy_bitslip61[4]), + .Q5 (main_a7ddrphy_bitslip61[3]), + .Q6 (main_a7ddrphy_bitslip61[2]), + .Q7 (main_a7ddrphy_bitslip61[1]), + .Q8 (main_a7ddrphy_bitslip61[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_6 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_6 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay6), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed6) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay6), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed6) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_6 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_6( - .I(a7ddrphy_dq_o_nodelay6), - .T(a7ddrphy_dq_t6), - .IO(ddram_dq[6]), - .O(a7ddrphy_dq_i_nodelay6) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay6), + .T (main_a7ddrphy_dq_t6), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay6), + + // InOuts. + .IO (ddram_dq[6]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_36 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_36 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip70[0]), - .D2(a7ddrphy_bitslip70[1]), - .D3(a7ddrphy_bitslip70[2]), - .D4(a7ddrphy_bitslip70[3]), - .D5(a7ddrphy_bitslip70[4]), - .D6(a7ddrphy_bitslip70[5]), - .D7(a7ddrphy_bitslip70[6]), - .D8(a7ddrphy_bitslip70[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay7), - .TQ(a7ddrphy_dq_t7) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip70[0]), + .D2 (main_a7ddrphy_bitslip70[1]), + .D3 (main_a7ddrphy_bitslip70[2]), + .D4 (main_a7ddrphy_bitslip70[3]), + .D5 (main_a7ddrphy_bitslip70[4]), + .D6 (main_a7ddrphy_bitslip70[5]), + .D7 (main_a7ddrphy_bitslip70[6]), + .D8 (main_a7ddrphy_bitslip70[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay7), + .TQ (main_a7ddrphy_dq_t7) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_7 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_7 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed7), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip71[7]), - .Q2(a7ddrphy_bitslip71[6]), - .Q3(a7ddrphy_bitslip71[5]), - .Q4(a7ddrphy_bitslip71[4]), - .Q5(a7ddrphy_bitslip71[3]), - .Q6(a7ddrphy_bitslip71[2]), - .Q7(a7ddrphy_bitslip71[1]), - .Q8(a7ddrphy_bitslip71[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed7), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip71[7]), + .Q2 (main_a7ddrphy_bitslip71[6]), + .Q3 (main_a7ddrphy_bitslip71[5]), + .Q4 (main_a7ddrphy_bitslip71[4]), + .Q5 (main_a7ddrphy_bitslip71[3]), + .Q6 (main_a7ddrphy_bitslip71[2]), + .Q7 (main_a7ddrphy_bitslip71[1]), + .Q8 (main_a7ddrphy_bitslip71[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_7 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_7 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay7), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed7) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay7), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed7) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_7 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_7( - .I(a7ddrphy_dq_o_nodelay7), - .T(a7ddrphy_dq_t7), - .IO(ddram_dq[7]), - .O(a7ddrphy_dq_i_nodelay7) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay7), + .T (main_a7ddrphy_dq_t7), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay7), + + // InOuts. + .IO (ddram_dq[7]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_37 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_37 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip80[0]), - .D2(a7ddrphy_bitslip80[1]), - .D3(a7ddrphy_bitslip80[2]), - .D4(a7ddrphy_bitslip80[3]), - .D5(a7ddrphy_bitslip80[4]), - .D6(a7ddrphy_bitslip80[5]), - .D7(a7ddrphy_bitslip80[6]), - .D8(a7ddrphy_bitslip80[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay8), - .TQ(a7ddrphy_dq_t8) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip80[0]), + .D2 (main_a7ddrphy_bitslip80[1]), + .D3 (main_a7ddrphy_bitslip80[2]), + .D4 (main_a7ddrphy_bitslip80[3]), + .D5 (main_a7ddrphy_bitslip80[4]), + .D6 (main_a7ddrphy_bitslip80[5]), + .D7 (main_a7ddrphy_bitslip80[6]), + .D8 (main_a7ddrphy_bitslip80[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay8), + .TQ (main_a7ddrphy_dq_t8) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_8 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_8 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed8), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip81[7]), - .Q2(a7ddrphy_bitslip81[6]), - .Q3(a7ddrphy_bitslip81[5]), - .Q4(a7ddrphy_bitslip81[4]), - .Q5(a7ddrphy_bitslip81[3]), - .Q6(a7ddrphy_bitslip81[2]), - .Q7(a7ddrphy_bitslip81[1]), - .Q8(a7ddrphy_bitslip81[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed8), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip81[7]), + .Q2 (main_a7ddrphy_bitslip81[6]), + .Q3 (main_a7ddrphy_bitslip81[5]), + .Q4 (main_a7ddrphy_bitslip81[4]), + .Q5 (main_a7ddrphy_bitslip81[3]), + .Q6 (main_a7ddrphy_bitslip81[2]), + .Q7 (main_a7ddrphy_bitslip81[1]), + .Q8 (main_a7ddrphy_bitslip81[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_8 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_8 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay8), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed8) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay8), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed8) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_8 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_8( - .I(a7ddrphy_dq_o_nodelay8), - .T(a7ddrphy_dq_t8), - .IO(ddram_dq[8]), - .O(a7ddrphy_dq_i_nodelay8) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay8), + .T (main_a7ddrphy_dq_t8), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay8), + + // InOuts. + .IO (ddram_dq[8]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_38 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_38 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip90[0]), - .D2(a7ddrphy_bitslip90[1]), - .D3(a7ddrphy_bitslip90[2]), - .D4(a7ddrphy_bitslip90[3]), - .D5(a7ddrphy_bitslip90[4]), - .D6(a7ddrphy_bitslip90[5]), - .D7(a7ddrphy_bitslip90[6]), - .D8(a7ddrphy_bitslip90[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay9), - .TQ(a7ddrphy_dq_t9) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip90[0]), + .D2 (main_a7ddrphy_bitslip90[1]), + .D3 (main_a7ddrphy_bitslip90[2]), + .D4 (main_a7ddrphy_bitslip90[3]), + .D5 (main_a7ddrphy_bitslip90[4]), + .D6 (main_a7ddrphy_bitslip90[5]), + .D7 (main_a7ddrphy_bitslip90[6]), + .D8 (main_a7ddrphy_bitslip90[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay9), + .TQ (main_a7ddrphy_dq_t9) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_9 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_9 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed9), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip91[7]), - .Q2(a7ddrphy_bitslip91[6]), - .Q3(a7ddrphy_bitslip91[5]), - .Q4(a7ddrphy_bitslip91[4]), - .Q5(a7ddrphy_bitslip91[3]), - .Q6(a7ddrphy_bitslip91[2]), - .Q7(a7ddrphy_bitslip91[1]), - .Q8(a7ddrphy_bitslip91[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed9), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip91[7]), + .Q2 (main_a7ddrphy_bitslip91[6]), + .Q3 (main_a7ddrphy_bitslip91[5]), + .Q4 (main_a7ddrphy_bitslip91[4]), + .Q5 (main_a7ddrphy_bitslip91[3]), + .Q6 (main_a7ddrphy_bitslip91[2]), + .Q7 (main_a7ddrphy_bitslip91[1]), + .Q8 (main_a7ddrphy_bitslip91[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_9 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_9 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay9), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed9) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay9), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed9) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_9 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_9( - .I(a7ddrphy_dq_o_nodelay9), - .T(a7ddrphy_dq_t9), - .IO(ddram_dq[9]), - .O(a7ddrphy_dq_i_nodelay9) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay9), + .T (main_a7ddrphy_dq_t9), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay9), + + // InOuts. + .IO (ddram_dq[9]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_39 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_39 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip100[0]), - .D2(a7ddrphy_bitslip100[1]), - .D3(a7ddrphy_bitslip100[2]), - .D4(a7ddrphy_bitslip100[3]), - .D5(a7ddrphy_bitslip100[4]), - .D6(a7ddrphy_bitslip100[5]), - .D7(a7ddrphy_bitslip100[6]), - .D8(a7ddrphy_bitslip100[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay10), - .TQ(a7ddrphy_dq_t10) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip100[0]), + .D2 (main_a7ddrphy_bitslip100[1]), + .D3 (main_a7ddrphy_bitslip100[2]), + .D4 (main_a7ddrphy_bitslip100[3]), + .D5 (main_a7ddrphy_bitslip100[4]), + .D6 (main_a7ddrphy_bitslip100[5]), + .D7 (main_a7ddrphy_bitslip100[6]), + .D8 (main_a7ddrphy_bitslip100[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay10), + .TQ (main_a7ddrphy_dq_t10) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_10 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_10 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed10), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip101[7]), - .Q2(a7ddrphy_bitslip101[6]), - .Q3(a7ddrphy_bitslip101[5]), - .Q4(a7ddrphy_bitslip101[4]), - .Q5(a7ddrphy_bitslip101[3]), - .Q6(a7ddrphy_bitslip101[2]), - .Q7(a7ddrphy_bitslip101[1]), - .Q8(a7ddrphy_bitslip101[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed10), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip101[7]), + .Q2 (main_a7ddrphy_bitslip101[6]), + .Q3 (main_a7ddrphy_bitslip101[5]), + .Q4 (main_a7ddrphy_bitslip101[4]), + .Q5 (main_a7ddrphy_bitslip101[3]), + .Q6 (main_a7ddrphy_bitslip101[2]), + .Q7 (main_a7ddrphy_bitslip101[1]), + .Q8 (main_a7ddrphy_bitslip101[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_10 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_10 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay10), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed10) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay10), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed10) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_10 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_10( - .I(a7ddrphy_dq_o_nodelay10), - .T(a7ddrphy_dq_t10), - .IO(ddram_dq[10]), - .O(a7ddrphy_dq_i_nodelay10) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay10), + .T (main_a7ddrphy_dq_t10), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay10), + + // InOuts. + .IO (ddram_dq[10]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_40 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_40 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip110[0]), - .D2(a7ddrphy_bitslip110[1]), - .D3(a7ddrphy_bitslip110[2]), - .D4(a7ddrphy_bitslip110[3]), - .D5(a7ddrphy_bitslip110[4]), - .D6(a7ddrphy_bitslip110[5]), - .D7(a7ddrphy_bitslip110[6]), - .D8(a7ddrphy_bitslip110[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay11), - .TQ(a7ddrphy_dq_t11) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip110[0]), + .D2 (main_a7ddrphy_bitslip110[1]), + .D3 (main_a7ddrphy_bitslip110[2]), + .D4 (main_a7ddrphy_bitslip110[3]), + .D5 (main_a7ddrphy_bitslip110[4]), + .D6 (main_a7ddrphy_bitslip110[5]), + .D7 (main_a7ddrphy_bitslip110[6]), + .D8 (main_a7ddrphy_bitslip110[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay11), + .TQ (main_a7ddrphy_dq_t11) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_11 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_11 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed11), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip111[7]), - .Q2(a7ddrphy_bitslip111[6]), - .Q3(a7ddrphy_bitslip111[5]), - .Q4(a7ddrphy_bitslip111[4]), - .Q5(a7ddrphy_bitslip111[3]), - .Q6(a7ddrphy_bitslip111[2]), - .Q7(a7ddrphy_bitslip111[1]), - .Q8(a7ddrphy_bitslip111[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed11), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip111[7]), + .Q2 (main_a7ddrphy_bitslip111[6]), + .Q3 (main_a7ddrphy_bitslip111[5]), + .Q4 (main_a7ddrphy_bitslip111[4]), + .Q5 (main_a7ddrphy_bitslip111[3]), + .Q6 (main_a7ddrphy_bitslip111[2]), + .Q7 (main_a7ddrphy_bitslip111[1]), + .Q8 (main_a7ddrphy_bitslip111[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_11 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_11 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay11), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed11) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay11), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed11) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_11 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_11( - .I(a7ddrphy_dq_o_nodelay11), - .T(a7ddrphy_dq_t11), - .IO(ddram_dq[11]), - .O(a7ddrphy_dq_i_nodelay11) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay11), + .T (main_a7ddrphy_dq_t11), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay11), + + // InOuts. + .IO (ddram_dq[11]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_41 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_41 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip120[0]), - .D2(a7ddrphy_bitslip120[1]), - .D3(a7ddrphy_bitslip120[2]), - .D4(a7ddrphy_bitslip120[3]), - .D5(a7ddrphy_bitslip120[4]), - .D6(a7ddrphy_bitslip120[5]), - .D7(a7ddrphy_bitslip120[6]), - .D8(a7ddrphy_bitslip120[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay12), - .TQ(a7ddrphy_dq_t12) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip120[0]), + .D2 (main_a7ddrphy_bitslip120[1]), + .D3 (main_a7ddrphy_bitslip120[2]), + .D4 (main_a7ddrphy_bitslip120[3]), + .D5 (main_a7ddrphy_bitslip120[4]), + .D6 (main_a7ddrphy_bitslip120[5]), + .D7 (main_a7ddrphy_bitslip120[6]), + .D8 (main_a7ddrphy_bitslip120[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay12), + .TQ (main_a7ddrphy_dq_t12) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_12 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_12 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed12), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip121[7]), - .Q2(a7ddrphy_bitslip121[6]), - .Q3(a7ddrphy_bitslip121[5]), - .Q4(a7ddrphy_bitslip121[4]), - .Q5(a7ddrphy_bitslip121[3]), - .Q6(a7ddrphy_bitslip121[2]), - .Q7(a7ddrphy_bitslip121[1]), - .Q8(a7ddrphy_bitslip121[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed12), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip121[7]), + .Q2 (main_a7ddrphy_bitslip121[6]), + .Q3 (main_a7ddrphy_bitslip121[5]), + .Q4 (main_a7ddrphy_bitslip121[4]), + .Q5 (main_a7ddrphy_bitslip121[3]), + .Q6 (main_a7ddrphy_bitslip121[2]), + .Q7 (main_a7ddrphy_bitslip121[1]), + .Q8 (main_a7ddrphy_bitslip121[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_12 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_12 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay12), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed12) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay12), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed12) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_12 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_12( - .I(a7ddrphy_dq_o_nodelay12), - .T(a7ddrphy_dq_t12), - .IO(ddram_dq[12]), - .O(a7ddrphy_dq_i_nodelay12) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay12), + .T (main_a7ddrphy_dq_t12), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay12), + + // InOuts. + .IO (ddram_dq[12]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_42 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_42 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip130[0]), - .D2(a7ddrphy_bitslip130[1]), - .D3(a7ddrphy_bitslip130[2]), - .D4(a7ddrphy_bitslip130[3]), - .D5(a7ddrphy_bitslip130[4]), - .D6(a7ddrphy_bitslip130[5]), - .D7(a7ddrphy_bitslip130[6]), - .D8(a7ddrphy_bitslip130[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay13), - .TQ(a7ddrphy_dq_t13) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip130[0]), + .D2 (main_a7ddrphy_bitslip130[1]), + .D3 (main_a7ddrphy_bitslip130[2]), + .D4 (main_a7ddrphy_bitslip130[3]), + .D5 (main_a7ddrphy_bitslip130[4]), + .D6 (main_a7ddrphy_bitslip130[5]), + .D7 (main_a7ddrphy_bitslip130[6]), + .D8 (main_a7ddrphy_bitslip130[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay13), + .TQ (main_a7ddrphy_dq_t13) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_13 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_13 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed13), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip131[7]), - .Q2(a7ddrphy_bitslip131[6]), - .Q3(a7ddrphy_bitslip131[5]), - .Q4(a7ddrphy_bitslip131[4]), - .Q5(a7ddrphy_bitslip131[3]), - .Q6(a7ddrphy_bitslip131[2]), - .Q7(a7ddrphy_bitslip131[1]), - .Q8(a7ddrphy_bitslip131[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed13), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip131[7]), + .Q2 (main_a7ddrphy_bitslip131[6]), + .Q3 (main_a7ddrphy_bitslip131[5]), + .Q4 (main_a7ddrphy_bitslip131[4]), + .Q5 (main_a7ddrphy_bitslip131[3]), + .Q6 (main_a7ddrphy_bitslip131[2]), + .Q7 (main_a7ddrphy_bitslip131[1]), + .Q8 (main_a7ddrphy_bitslip131[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_13 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_13 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay13), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed13) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay13), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed13) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_13 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_13( - .I(a7ddrphy_dq_o_nodelay13), - .T(a7ddrphy_dq_t13), - .IO(ddram_dq[13]), - .O(a7ddrphy_dq_i_nodelay13) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay13), + .T (main_a7ddrphy_dq_t13), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay13), + + // InOuts. + .IO (ddram_dq[13]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_43 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_43 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip140[0]), - .D2(a7ddrphy_bitslip140[1]), - .D3(a7ddrphy_bitslip140[2]), - .D4(a7ddrphy_bitslip140[3]), - .D5(a7ddrphy_bitslip140[4]), - .D6(a7ddrphy_bitslip140[5]), - .D7(a7ddrphy_bitslip140[6]), - .D8(a7ddrphy_bitslip140[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay14), - .TQ(a7ddrphy_dq_t14) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip140[0]), + .D2 (main_a7ddrphy_bitslip140[1]), + .D3 (main_a7ddrphy_bitslip140[2]), + .D4 (main_a7ddrphy_bitslip140[3]), + .D5 (main_a7ddrphy_bitslip140[4]), + .D6 (main_a7ddrphy_bitslip140[5]), + .D7 (main_a7ddrphy_bitslip140[6]), + .D8 (main_a7ddrphy_bitslip140[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay14), + .TQ (main_a7ddrphy_dq_t14) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_14 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_14 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed14), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip141[7]), - .Q2(a7ddrphy_bitslip141[6]), - .Q3(a7ddrphy_bitslip141[5]), - .Q4(a7ddrphy_bitslip141[4]), - .Q5(a7ddrphy_bitslip141[3]), - .Q6(a7ddrphy_bitslip141[2]), - .Q7(a7ddrphy_bitslip141[1]), - .Q8(a7ddrphy_bitslip141[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed14), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip141[7]), + .Q2 (main_a7ddrphy_bitslip141[6]), + .Q3 (main_a7ddrphy_bitslip141[5]), + .Q4 (main_a7ddrphy_bitslip141[4]), + .Q5 (main_a7ddrphy_bitslip141[3]), + .Q6 (main_a7ddrphy_bitslip141[2]), + .Q7 (main_a7ddrphy_bitslip141[1]), + .Q8 (main_a7ddrphy_bitslip141[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_14 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_14 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay14), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed14) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay14), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed14) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_14 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_14( - .I(a7ddrphy_dq_o_nodelay14), - .T(a7ddrphy_dq_t14), - .IO(ddram_dq[14]), - .O(a7ddrphy_dq_i_nodelay14) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay14), + .T (main_a7ddrphy_dq_t14), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay14), + + // InOuts. + .IO (ddram_dq[14]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_44 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_44 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip150[0]), - .D2(a7ddrphy_bitslip150[1]), - .D3(a7ddrphy_bitslip150[2]), - .D4(a7ddrphy_bitslip150[3]), - .D5(a7ddrphy_bitslip150[4]), - .D6(a7ddrphy_bitslip150[5]), - .D7(a7ddrphy_bitslip150[6]), - .D8(a7ddrphy_bitslip150[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay15), - .TQ(a7ddrphy_dq_t15) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip150[0]), + .D2 (main_a7ddrphy_bitslip150[1]), + .D3 (main_a7ddrphy_bitslip150[2]), + .D4 (main_a7ddrphy_bitslip150[3]), + .D5 (main_a7ddrphy_bitslip150[4]), + .D6 (main_a7ddrphy_bitslip150[5]), + .D7 (main_a7ddrphy_bitslip150[6]), + .D8 (main_a7ddrphy_bitslip150[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay15), + .TQ (main_a7ddrphy_dq_t15) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_15 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_15 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed15), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip151[7]), - .Q2(a7ddrphy_bitslip151[6]), - .Q3(a7ddrphy_bitslip151[5]), - .Q4(a7ddrphy_bitslip151[4]), - .Q5(a7ddrphy_bitslip151[3]), - .Q6(a7ddrphy_bitslip151[2]), - .Q7(a7ddrphy_bitslip151[1]), - .Q8(a7ddrphy_bitslip151[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed15), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip151[7]), + .Q2 (main_a7ddrphy_bitslip151[6]), + .Q3 (main_a7ddrphy_bitslip151[5]), + .Q4 (main_a7ddrphy_bitslip151[4]), + .Q5 (main_a7ddrphy_bitslip151[3]), + .Q6 (main_a7ddrphy_bitslip151[2]), + .Q7 (main_a7ddrphy_bitslip151[1]), + .Q8 (main_a7ddrphy_bitslip151[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_15 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_15 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay15), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed15) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay15), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed15) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_15 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_15( - .I(a7ddrphy_dq_o_nodelay15), - .T(a7ddrphy_dq_t15), - .IO(ddram_dq[15]), - .O(a7ddrphy_dq_i_nodelay15) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay15), + .T (main_a7ddrphy_dq_t15), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay15), + + // InOuts. + .IO (ddram_dq[15]) ); //------------------------------------------------------------------------------ @@ -16031,14 +17159,14 @@ IOBUF IOBUF_15( reg [23:0] storage[0:15]; reg [23:0] storage_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine0_wrport_we) - storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w; - storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr]; + if (main_litedramcore_bankmachine0_wrport_we) + storage[main_litedramcore_bankmachine0_wrport_adr] <= main_litedramcore_bankmachine0_wrport_dat_w; + storage_dat0 <= storage[main_litedramcore_bankmachine0_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0; -assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr]; +assign main_litedramcore_bankmachine0_wrport_dat_r = storage_dat0; +assign main_litedramcore_bankmachine0_rdport_dat_r = storage[main_litedramcore_bankmachine0_rdport_adr]; //------------------------------------------------------------------------------ @@ -16049,14 +17177,14 @@ assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine reg [23:0] storage_1[0:15]; reg [23:0] storage_1_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine1_wrport_we) - storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w; - storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr]; + if (main_litedramcore_bankmachine1_wrport_we) + storage_1[main_litedramcore_bankmachine1_wrport_adr] <= main_litedramcore_bankmachine1_wrport_dat_w; + storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0; -assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr]; +assign main_litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0; +assign main_litedramcore_bankmachine1_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_rdport_adr]; //------------------------------------------------------------------------------ @@ -16067,14 +17195,14 @@ assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachi reg [23:0] storage_2[0:15]; reg [23:0] storage_2_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine2_wrport_we) - storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w; - storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr]; + if (main_litedramcore_bankmachine2_wrport_we) + storage_2[main_litedramcore_bankmachine2_wrport_adr] <= main_litedramcore_bankmachine2_wrport_dat_w; + storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0; -assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr]; +assign main_litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0; +assign main_litedramcore_bankmachine2_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_rdport_adr]; //------------------------------------------------------------------------------ @@ -16085,14 +17213,14 @@ assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachi reg [23:0] storage_3[0:15]; reg [23:0] storage_3_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine3_wrport_we) - storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w; - storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr]; + if (main_litedramcore_bankmachine3_wrport_we) + storage_3[main_litedramcore_bankmachine3_wrport_adr] <= main_litedramcore_bankmachine3_wrport_dat_w; + storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0; -assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr]; +assign main_litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0; +assign main_litedramcore_bankmachine3_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_rdport_adr]; //------------------------------------------------------------------------------ @@ -16103,14 +17231,14 @@ assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachi reg [23:0] storage_4[0:15]; reg [23:0] storage_4_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine4_wrport_we) - storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w; - storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr]; + if (main_litedramcore_bankmachine4_wrport_we) + storage_4[main_litedramcore_bankmachine4_wrport_adr] <= main_litedramcore_bankmachine4_wrport_dat_w; + storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0; -assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr]; +assign main_litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0; +assign main_litedramcore_bankmachine4_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_rdport_adr]; //------------------------------------------------------------------------------ @@ -16121,14 +17249,14 @@ assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachi reg [23:0] storage_5[0:15]; reg [23:0] storage_5_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine5_wrport_we) - storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w; - storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr]; + if (main_litedramcore_bankmachine5_wrport_we) + storage_5[main_litedramcore_bankmachine5_wrport_adr] <= main_litedramcore_bankmachine5_wrport_dat_w; + storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0; -assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr]; +assign main_litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0; +assign main_litedramcore_bankmachine5_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_rdport_adr]; //------------------------------------------------------------------------------ @@ -16139,14 +17267,14 @@ assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachi reg [23:0] storage_6[0:15]; reg [23:0] storage_6_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine6_wrport_we) - storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w; - storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr]; + if (main_litedramcore_bankmachine6_wrport_we) + storage_6[main_litedramcore_bankmachine6_wrport_adr] <= main_litedramcore_bankmachine6_wrport_dat_w; + storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0; -assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr]; +assign main_litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0; +assign main_litedramcore_bankmachine6_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_rdport_adr]; //------------------------------------------------------------------------------ @@ -16157,197 +17285,308 @@ assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachi reg [23:0] storage_7[0:15]; reg [23:0] storage_7_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine7_wrport_we) - storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w; - storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr]; + if (main_litedramcore_bankmachine7_wrport_we) + storage_7[main_litedramcore_bankmachine7_wrport_adr] <= main_litedramcore_bankmachine7_wrport_dat_w; + storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0; -assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr]; +assign main_litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0; +assign main_litedramcore_bankmachine7_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_rdport_adr]; +//------------------------------------------------------------------------------ +// Instance FDCE of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(reset), - .Q(litedramcore_reset0) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (main_reset), + + // Outputs. + .Q (builder_reset0) ); +//------------------------------------------------------------------------------ +// Instance FDCE_1 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_1( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset0), - .Q(litedramcore_reset1) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset0), + + // Outputs. + .Q (builder_reset1) ); +//------------------------------------------------------------------------------ +// Instance FDCE_2 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_2( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset1), - .Q(litedramcore_reset2) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset1), + + // Outputs. + .Q (builder_reset2) ); +//------------------------------------------------------------------------------ +// Instance FDCE_3 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_3( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset2), - .Q(litedramcore_reset3) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset2), + + // Outputs. + .Q (builder_reset3) ); +//------------------------------------------------------------------------------ +// Instance FDCE_4 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_4( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset3), - .Q(litedramcore_reset4) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset3), + + // Outputs. + .Q (builder_reset4) ); +//------------------------------------------------------------------------------ +// Instance FDCE_5 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_5( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset4), - .Q(litedramcore_reset5) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset4), + + // Outputs. + .Q (builder_reset5) ); +//------------------------------------------------------------------------------ +// Instance FDCE_6 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_6( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset5), - .Q(litedramcore_reset6) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset5), + + // Outputs. + .Q (builder_reset6) ); +//------------------------------------------------------------------------------ +// Instance FDCE_7 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_7( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset6), - .Q(litedramcore_reset7) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset6), + + // Outputs. + .Q (builder_reset7) ); +//------------------------------------------------------------------------------ +// Instance PLLE2_ADV of PLLE2_ADV Module. +//------------------------------------------------------------------------------ PLLE2_ADV #( - .CLKFBOUT_MULT(5'd16), - .CLKIN1_PERIOD(10.0), - .CLKOUT0_DIVIDE(4'd8), - .CLKOUT0_PHASE(1'd0), - .CLKOUT1_DIVIDE(5'd16), - .CLKOUT1_PHASE(1'd0), - .CLKOUT2_DIVIDE(3'd4), - .CLKOUT2_PHASE(1'd0), - .CLKOUT3_DIVIDE(3'd4), - .CLKOUT3_PHASE(7'd90), - .DIVCLK_DIVIDE(1'd1), - .REF_JITTER1(0.01), - .STARTUP_WAIT("FALSE") + // Parameters. + .CLKFBOUT_MULT (5'd16), + .CLKIN1_PERIOD (10.0), + .CLKOUT0_DIVIDE (4'd8), + .CLKOUT0_PHASE (1'd0), + .CLKOUT1_DIVIDE (5'd16), + .CLKOUT1_PHASE (1'd0), + .CLKOUT2_DIVIDE (3'd4), + .CLKOUT2_PHASE (1'd0), + .CLKOUT3_DIVIDE (3'd4), + .CLKOUT3_PHASE (7'd90), + .DIVCLK_DIVIDE (1'd1), + .REF_JITTER1 (0.01), + .STARTUP_WAIT ("FALSE") ) PLLE2_ADV ( - .CLKFBIN(litedramcore_pll_fb), - .CLKIN1(clkin), - .PWRDWN(power_down), - .RST(litedramcore_reset7), - .CLKFBOUT(litedramcore_pll_fb), - .CLKOUT0(clkout0), - .CLKOUT1(clkout1), - .CLKOUT2(clkout2), - .CLKOUT3(clkout3), - .LOCKED(locked) + // Inputs. + .CLKFBIN (builder_pll_fb), + .CLKIN1 (main_clkin), + .PWRDWN (main_power_down), + .RST (builder_reset7), + + // Outputs. + .CLKFBOUT (builder_pll_fb), + .CLKOUT0 (main_clkout0), + .CLKOUT1 (main_clkout1), + .CLKOUT2 (main_clkout2), + .CLKOUT3 (main_clkout3), + .LOCKED (main_locked) ); (* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE ( - .C(iodelay_clk), - .CE(1'd1), - .D(1'd0), - .PRE(xilinxasyncresetsynchronizerimpl0), - .Q(xilinxasyncresetsynchronizerimpl0_rst_meta) + // Inputs. + .C (iodelay_clk), + .CE (1'd1), + .D (1'd0), + .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl0_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_1 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_1 ( - .C(iodelay_clk), - .CE(1'd1), - .D(xilinxasyncresetsynchronizerimpl0_rst_meta), - .PRE(xilinxasyncresetsynchronizerimpl0), - .Q(iodelay_rst) + // Inputs. + .C (iodelay_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl0_rst_meta), + .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + + // Outputs. + .Q (iodelay_rst) ); (* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_2 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_2 ( - .C(sys_clk), - .CE(1'd1), - .D(1'd0), - .PRE(xilinxasyncresetsynchronizerimpl1), - .Q(xilinxasyncresetsynchronizerimpl1_rst_meta) + // Inputs. + .C (sys_clk), + .CE (1'd1), + .D (1'd0), + .PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl1_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_3 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_3 ( - .C(sys_clk), - .CE(1'd1), - .D(xilinxasyncresetsynchronizerimpl1_rst_meta), - .PRE(xilinxasyncresetsynchronizerimpl1), - .Q(sys_rst) + // Inputs. + .C (sys_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl1_rst_meta), + .PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset), + + // Outputs. + .Q (sys_rst) ); (* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_4 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_4 ( - .C(sys4x_clk), - .CE(1'd1), - .D(1'd0), - .PRE(xilinxasyncresetsynchronizerimpl2), - .Q(xilinxasyncresetsynchronizerimpl2_rst_meta) + // Inputs. + .C (sys4x_clk), + .CE (1'd1), + .D (1'd0), + .PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl2_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_5 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_5 ( - .C(sys4x_clk), - .CE(1'd1), - .D(xilinxasyncresetsynchronizerimpl2_rst_meta), - .PRE(xilinxasyncresetsynchronizerimpl2), - .Q(xilinxasyncresetsynchronizerimpl2_expr) + // Inputs. + .C (sys4x_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl2_rst_meta), + .PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl2_expr) ); (* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_6 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_6 ( - .C(sys4x_dqs_clk), - .CE(1'd1), - .D(1'd0), - .PRE(xilinxasyncresetsynchronizerimpl3), - .Q(xilinxasyncresetsynchronizerimpl3_rst_meta) + // Inputs. + .C (sys4x_dqs_clk), + .CE (1'd1), + .D (1'd0), + .PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl3_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_7 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_7 ( - .C(sys4x_dqs_clk), - .CE(1'd1), - .D(xilinxasyncresetsynchronizerimpl3_rst_meta), - .PRE(xilinxasyncresetsynchronizerimpl3), - .Q(xilinxasyncresetsynchronizerimpl3_expr) + // Inputs. + .C (sys4x_dqs_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl3_rst_meta), + .PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl3_expr) ); endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2022-10-28 19:01:19. +// Auto-Generated by LiteX on 2024-04-01 10:12:06. //------------------------------------------------------------------------------ diff --git a/litedram/generated/ecpix-5/litedram-initmem.vhdl b/litedram/generated/ecpix-5/litedram-initmem.vhdl new file mode 100644 index 0000000..231249e --- /dev/null +++ b/litedram/generated/ecpix-5/litedram-initmem.vhdl @@ -0,0 +1,123 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; + +library work; +use work.wishbone_types.all; +use work.utils.all; + +entity dram_init_mem is + generic ( + EXTRA_PAYLOAD_FILE : string := ""; + EXTRA_PAYLOAD_SIZE : integer := 0 + ); + port ( + clk : in std_ulogic; + wb_in : in wb_io_master_out; + wb_out : out wb_io_slave_out + ); +end entity dram_init_mem; + +architecture rtl of dram_init_mem is + + constant INIT_RAM_SIZE : integer := 24576; + constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8); + constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE; + constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1); + constant INIT_RAM_FILE : string := "litedram_core.init"; + + type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); + + -- XXX FIXME: Have a single init function called twice with + -- an offset as argument + procedure init_load_payload(ram: inout ram_t; filename: string) is + file payload_file : text open read_mode is filename; + variable ram_line : line; + variable temp_word : std_logic_vector(63 downto 0); + begin + for i in 0 to RND_PAYLOAD_SIZE-1 loop + exit when endfile(payload_file); + readline(payload_file, ram_line); + hread(ram_line, temp_word); + ram((INIT_RAM_SIZE/4) + i*2) := temp_word(31 downto 0); + ram((INIT_RAM_SIZE/4) + i*2+1) := temp_word(63 downto 32); + end loop; + assert endfile(payload_file) report "Payload too big !" severity failure; + end procedure; + + impure function init_load_ram(name : string) return ram_t is + file ram_file : text open read_mode is name; + variable temp_word : std_logic_vector(63 downto 0); + variable temp_ram : ram_t := (others => (others => '0')); + variable ram_line : line; + begin + report "Payload size:" & integer'image(EXTRA_PAYLOAD_SIZE) & + " rounded to:" & integer'image(RND_PAYLOAD_SIZE); + report "Total RAM size:" & integer'image(TOTAL_RAM_SIZE) & + " bytes using " & integer'image(INIT_RAM_ABITS) & + " address bits"; + for i in 0 to (INIT_RAM_SIZE/8)-1 loop + exit when endfile(ram_file); + readline(ram_file, ram_line); + hread(ram_line, temp_word); + temp_ram(i*2) := temp_word(31 downto 0); + temp_ram(i*2+1) := temp_word(63 downto 32); + end loop; + if RND_PAYLOAD_SIZE /= 0 then + init_load_payload(temp_ram, EXTRA_PAYLOAD_FILE); + end if; + return temp_ram; + end function; + + impure function init_zero return ram_t is + variable temp_ram : ram_t := (others => (others => '0')); + begin + return temp_ram; + end function; + + impure function initialize_ram(filename: string) return ram_t is + begin + report "Opening file " & filename; + if filename'length = 0 then + return init_zero; + else + return init_load_ram(filename); + end if; + end function; + signal init_ram : ram_t := initialize_ram(INIT_RAM_FILE); + + attribute ram_style : string; + attribute ram_style of init_ram: signal is "block"; + + signal obuf : std_ulogic_vector(31 downto 0); + signal oack : std_ulogic; +begin + + init_ram_0: process(clk) + variable adr : integer; + begin + if rising_edge(clk) then + oack <= '0'; + if (wb_in.cyc and wb_in.stb) = '1' then + adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS - 3 downto 0)))); + if wb_in.we = '0' then + obuf <= init_ram(adr); + else + for i in 0 to 3 loop + if wb_in.sel(i) = '1' then + init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <= + wb_in.dat(((i + 1) * 8) - 1 downto i * 8); + end if; + end loop; + end if; + oack <= '1'; + end if; + wb_out.ack <= oack; + wb_out.dat <= obuf; + end if; + end process; + + wb_out.stall <= '0'; + +end architecture rtl; diff --git a/litedram/generated/ecpix-5/litedram_core.init b/litedram/generated/ecpix-5/litedram_core.init new file mode 100644 index 0000000..ecf50a2 --- /dev/null +++ b/litedram/generated/ecpix-5/litedram_core.init @@ -0,0 +1,2002 @@ +4800002408000048 +01006b69a600607d +a602487d05009f42 +a64b5a7d14004a39 +2402004ca64b7b7d +602100003c200000 +6421ff00782107c6 +3d80000060215f00 +798c07c6618c0000 +618c114c658cff00 +4e8004217d8903a6 +4e8004207c6903a6 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 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----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : litedram_core.v +// Device : LFE5UM5G-85F-8BG554I +// LiteX sha1 : 87137c30 +// Date : 2024-04-01 18:06:24 +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ps + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module litedram_core ( + input wire clk, + output wire [14:0] ddram_a, + output wire [2:0] ddram_ba, + output wire ddram_cas_n, + output wire ddram_cke, + input wire ddram_clk_n, + output wire ddram_clk_p, + output wire ddram_cs_n, + output wire [1:0] ddram_dm, + input wire [15:0] ddram_dq, + input wire [1:0] ddram_dqs_n, + input wire [1:0] ddram_dqs_p, + output wire ddram_odt, + output wire ddram_ras_n, + output wire ddram_reset_n, + output wire ddram_we_n, + output wire init_done, + output wire init_error, + output wire pll_locked, + input wire rst, + output wire user_clk, + input wire [24:0] user_port_native_0_cmd_addr, + output wire user_port_native_0_cmd_ready, + input wire user_port_native_0_cmd_valid, + input wire user_port_native_0_cmd_we, + output wire [127:0] user_port_native_0_rdata_data, + input wire user_port_native_0_rdata_ready, + output wire user_port_native_0_rdata_valid, + input wire [127:0] user_port_native_0_wdata_data, + output wire user_port_native_0_wdata_ready, + input wire user_port_native_0_wdata_valid, + input wire [15:0] user_port_native_0_wdata_we, + output wire user_rst, + output wire wb_ctrl_ack, + input wire [29:0] wb_ctrl_adr, + input wire [1:0] wb_ctrl_bte, + input wire [2:0] wb_ctrl_cti, + input wire wb_ctrl_cyc, + output wire [31:0] wb_ctrl_dat_r, + input wire [31:0] wb_ctrl_dat_w, + output wire wb_ctrl_err, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_stb, + input wire wb_ctrl_we +); + + +//------------------------------------------------------------------------------ +// Hierarchy +//------------------------------------------------------------------------------ + +/* +LiteDRAMCore +└─── bus (SoCBusHandler) +│ └─── _interconnect (InterconnectPointToPoint) +└─── csr (SoCCSRHandler) +└─── irq (SoCIRQHandler) +└─── cpu (CPUNone) +└─── crg (LiteDRAMECP5DDRPHYCRG) +│ └─── pll (ECP5PLL) +│ │ └─── [EHXPLLL] +│ └─── [CLKDIVF] +│ └─── [ECLKBRIDGECS] +│ └─── [ECLKSYNCB] +└─── ddrphy (ECP5DDRPHY) +│ └─── init (ECP5DDRPHYInit) +│ │ └─── [DDRDLLA] +│ └─── bitslip_0* (BitSlip) +│ └─── bitslip_1* (BitSlip) +│ └─── bitslip_2* (BitSlip) +│ └─── bitslip_3* (BitSlip) +│ └─── bitslip_4* (BitSlip) +│ └─── bitslip_5* (BitSlip) +│ └─── bitslip_6* (BitSlip) +│ └─── bitslip_7* (BitSlip) +│ └─── bitslip_8* (BitSlip) +│ └─── bitslip_9* (BitSlip) +│ └─── bitslip_10* (BitSlip) +│ └─── bitslip_11* (BitSlip) +│ └─── bitslip_12* (BitSlip) +│ └─── bitslip_13* (BitSlip) +│ └─── bitslip_14* (BitSlip) +│ └─── bitslip_15* (BitSlip) +│ └─── tappeddelayline_0* (TappedDelayLine) +│ └─── tappeddelayline_1* (TappedDelayLine) +│ └─── [DELAYG] +│ └─── [TSHX2DQA] +│ └─── [ODDRX2F] +│ └─── [TSHX2DQA] +│ └─── [DELAYG] +│ └─── [ODDRX2F] +│ └─── [ODDRX2F] +│ └─── [DELAYG] +│ └─── [ODDRX2F] +│ └─── [ODDRX2DQSB] +│ └─── [TSHX2DQA] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [TSHX2DQA] +│ └─── [DELAYG] +│ └─── [ODDRX2F] +│ └─── [ODDRX2F] +│ └─── [TSHX2DQA] +│ └─── [DELAYG] +│ └─── [ODDRX2DQA] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [TSHX2DQA] +│ └─── [ODDRX2DQA] +│ └─── [ODDRX2DQA] +│ └─── [ODDRX2F] +│ └─── [ODDRX2F] +│ └─── [ODDRX2DQA] +│ └─── [ODDRX2DQA] +│ └─── [DELAYG] +│ └─── [DQSBUFM] +│ └─── [DELAYG] +│ └─── [TSHX2DQA] +│ └─── [ODDRX2F] +│ └─── [ODDRX2DQA] +│ └─── [ODDRX2F] +│ └─── [IDDRX2DQA] +│ └─── [ODDRX2DQA] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [IDDRX2DQA] +│ └─── [IDDRX2DQA] +│ └─── [DELAYG] +│ └─── [TSHX2DQSA] +│ └─── [IDDRX2DQA] +│ └─── [IDDRX2DQA] +│ └─── [ODDRX2DQA] +│ └─── [ODDRX2F] +│ └─── [DELAYG] +│ └─── [IDDRX2DQA] +│ └─── [DELAYG] +│ └─── [IDDRX2DQA] +│ └─── [DELAYG] +│ └─── [ODDRX2F] +│ └─── [DELAYG] +│ └─── [DQSBUFM] +│ └─── [DELAYG] +│ └─── [TSHX2DQSA] +│ └─── [ODDRX2F] +│ └─── [DELAYG] +│ └─── [IDDRX2DQA] +│ └─── [DELAYG] +│ └─── [ODDRX2DQA] +│ └─── [TSHX2DQA] +│ └─── [IDDRX2DQA] +│ └─── [DELAYG] +│ └─── [TSHX2DQA] +│ └─── [DELAYG] +│ └─── [TSHX2DQA] +│ └─── [DELAYG] +│ └─── [ODDRX2F] +│ └─── [DELAYG] +│ └─── [ODDRX2F] +│ └─── [DELAYG] +│ └─── [TSHX2DQA] +│ └─── [DELAYG] +│ └─── [TSHX2DQA] +│ └─── [DELAYG] +│ └─── [ODDRX2DQA] +│ └─── [ODDRX2F] +│ └─── [TSHX2DQA] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [ODDRX2DQA] +│ └─── [ODDRX2F] +│ └─── [TSHX2DQA] +│ └─── [ODDRX2DQA] +│ └─── [ODDRX2F] +│ └─── [ODDRX2DQA] +│ └─── [ODDRX2DQA] +│ └─── [TSHX2DQA] +│ └─── [ODDRX2DQA] +│ └─── [ODDRX2DQA] +│ └─── [ODDRX2DQA] +│ └─── [ODDRX2F] +│ └─── [ODDRX2F] +│ └─── [DELAYG] +│ └─── [IDDRX2DQA] +│ └─── [IDDRX2DQA] +│ └─── [IDDRX2DQA] +│ └─── [IDDRX2DQA] +│ └─── [ODDRX2F] +│ └─── [ODDRX2F] +│ └─── [IDDRX2DQA] +│ └─── [ODDRX2DQA] +│ └─── [DELAYG] +│ └─── [ODDRX2F] +│ └─── [ODDRX2F] +│ └─── [DELAYG] +│ └─── [ODDRX2F] +│ └─── [DELAYG] +│ └─── [IDDRX2DQA] +│ └─── [DELAYG] +│ └─── [IDDRX2DQA] +│ └─── [ODDRX2DQSB] +│ └─── [ODDRX2F] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [TSHX2DQA] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [DELAYG] +└─── sdram (LiteDRAMCore) +│ └─── dfii (DFIInjector) +│ │ └─── pi0 (PhaseInjector) +│ │ └─── pi1 (PhaseInjector) +│ └─── controller (LiteDRAMController) +│ │ └─── refresher (Refresher) +│ │ │ └─── timer (RefreshTimer) +│ │ │ └─── postponer (RefreshPostponer) +│ │ │ └─── sequencer (RefreshSequencer) +│ │ │ │ └─── refreshexecuter_0* (RefreshExecuter) +│ │ │ └─── zqcs_timer (RefreshTimer) +│ │ │ └─── zqs_executer (ZQCSExecuter) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_0* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_1* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_2* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_3* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_4* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_5* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_6* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_7* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── multiplexer (Multiplexer) +│ │ │ └─── choose_cmd (_CommandChooser) +│ │ │ │ └─── roundrobin_0* (RoundRobin) +│ │ │ └─── choose_req (_CommandChooser) +│ │ │ │ └─── roundrobin_0* (RoundRobin) +│ │ │ └─── _steerer_0* (_Steerer) +│ │ │ └─── trrdcon (tXXDController) +│ │ │ └─── tfawcon (tFAWController) +│ │ │ └─── tccdcon (tXXDController) +│ │ │ └─── twtrcon (tXXDController) +│ │ │ └─── fsm (FSM) +│ └─── crossbar (LiteDRAMCrossbar) +│ │ └─── roundrobin_0* (RoundRobin) +│ │ └─── roundrobin_1* (RoundRobin) +│ │ └─── roundrobin_2* (RoundRobin) +│ │ └─── roundrobin_3* (RoundRobin) +│ │ └─── roundrobin_4* (RoundRobin) +│ │ └─── roundrobin_5* (RoundRobin) +│ │ └─── roundrobin_6* (RoundRobin) +│ │ └─── roundrobin_7* (RoundRobin) +└─── ddrctrl (LiteDRAMCoreControl) +└─── csr_bridge (Wishbone2CSR) +│ └─── fsm (FSM) +└─── csr_bankarray (CSRBankArray) +│ └─── csrbank_0* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ └─── csrbank_1* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ └─── csrbank_2* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstorage_4* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstorage_5* (CSRStorage) +│ │ └─── csrstorage_6* (CSRStorage) +│ │ └─── csrstorage_7* (CSRStorage) +│ │ └─── csrstorage_8* (CSRStorage) +│ │ └─── csrstatus_1* (CSRStatus) +└─── csr_interconnect (InterconnectShared) +└─── [FD1S3BX] +└─── [FD1S3BX] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +└─── [FD1S3BX] +└─── [FD1S3BX] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +└─── [FD1S3BX] +└─── [TRELLIS_IO] +└─── [FD1S3BX] +└─── [TRELLIS_IO] +└─── [FD1S3BX] +└─── [TRELLIS_IO] +└─── [FD1S3BX] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +* : Generated name. +[]: BlackBox. +*/ + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +wire [13:0] adr; +wire crg_clkin; +wire crg_clkout0; +wire crg_clkout1; +wire crg_locked; +reg [15:0] crg_por_count = 16'd65535; +wire crg_por_done; +wire crg_reset0; +wire crg_reset1; +reg crg_rst = 1'd0; +reg crg_stdby = 1'd0; +wire crg_stop; +wire crg_sys2x_clk_ecsout; +wire csrbank0_init_done0_r; +reg csrbank0_init_done0_re = 1'd0; +wire csrbank0_init_done0_w; +reg csrbank0_init_done0_we = 1'd0; +wire csrbank0_init_error0_r; +reg csrbank0_init_error0_re = 1'd0; +wire csrbank0_init_error0_w; +reg csrbank0_init_error0_we = 1'd0; +wire csrbank0_sel; +wire [1:0] csrbank1_burstdet_seen_r; +reg csrbank1_burstdet_seen_re = 1'd0; +wire [1:0] csrbank1_burstdet_seen_w; +reg csrbank1_burstdet_seen_we = 1'd0; +wire [1:0] csrbank1_dly_sel0_r; +reg csrbank1_dly_sel0_re = 1'd0; +wire [1:0] csrbank1_dly_sel0_w; +reg csrbank1_dly_sel0_we = 1'd0; +wire csrbank1_sel; +wire [3:0] csrbank2_dfii_control0_r; +reg csrbank2_dfii_control0_re = 1'd0; +wire [3:0] csrbank2_dfii_control0_w; +reg csrbank2_dfii_control0_we = 1'd0; +wire [14:0] csrbank2_dfii_pi0_address0_r; +reg csrbank2_dfii_pi0_address0_re = 1'd0; +wire [14:0] csrbank2_dfii_pi0_address0_w; +reg csrbank2_dfii_pi0_address0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi0_baddress0_r; +reg csrbank2_dfii_pi0_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi0_baddress0_w; +reg csrbank2_dfii_pi0_baddress0_we = 1'd0; +wire [7:0] csrbank2_dfii_pi0_command0_r; +reg csrbank2_dfii_pi0_command0_re = 1'd0; +wire [7:0] csrbank2_dfii_pi0_command0_w; +reg csrbank2_dfii_pi0_command0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata0_r; +reg csrbank2_dfii_pi0_rddata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata0_w; +reg csrbank2_dfii_pi0_rddata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata1_r; +reg csrbank2_dfii_pi0_rddata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata1_w; +reg csrbank2_dfii_pi0_rddata1_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata0_r; +reg csrbank2_dfii_pi0_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata0_w; +reg csrbank2_dfii_pi0_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata1_r; +reg csrbank2_dfii_pi0_wrdata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata1_w; +reg csrbank2_dfii_pi0_wrdata1_we = 1'd0; +wire [14:0] csrbank2_dfii_pi1_address0_r; +reg csrbank2_dfii_pi1_address0_re = 1'd0; +wire [14:0] csrbank2_dfii_pi1_address0_w; +reg csrbank2_dfii_pi1_address0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi1_baddress0_r; +reg csrbank2_dfii_pi1_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi1_baddress0_w; +reg csrbank2_dfii_pi1_baddress0_we = 1'd0; +wire [7:0] csrbank2_dfii_pi1_command0_r; +reg csrbank2_dfii_pi1_command0_re = 1'd0; +wire [7:0] csrbank2_dfii_pi1_command0_w; +reg csrbank2_dfii_pi1_command0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata0_r; +reg csrbank2_dfii_pi1_rddata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata0_w; +reg csrbank2_dfii_pi1_rddata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata1_r; +reg csrbank2_dfii_pi1_rddata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata1_w; +reg csrbank2_dfii_pi1_rddata1_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata0_r; +reg csrbank2_dfii_pi1_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata0_w; +reg csrbank2_dfii_pi1_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata1_r; +reg csrbank2_dfii_pi1_wrdata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata1_w; +reg csrbank2_dfii_pi1_wrdata1_we = 1'd0; +wire csrbank2_sel; +wire [31:0] dat_r; +wire [31:0] dat_w; +wire [3:0] ddrphy_bitslip0_i; +reg [3:0] ddrphy_bitslip0_o = 4'd0; +reg [7:0] ddrphy_bitslip0_r = 8'd0; +reg [1:0] ddrphy_bitslip0_value = 2'd0; +wire [3:0] ddrphy_bitslip10_i; +reg [3:0] ddrphy_bitslip10_o = 4'd0; +reg [7:0] ddrphy_bitslip10_r = 8'd0; +reg [1:0] ddrphy_bitslip10_value = 2'd0; +wire [3:0] ddrphy_bitslip11_i; +reg [3:0] ddrphy_bitslip11_o = 4'd0; +reg [7:0] ddrphy_bitslip11_r = 8'd0; +reg [1:0] ddrphy_bitslip11_value = 2'd0; +wire [3:0] ddrphy_bitslip12_i; +reg [3:0] ddrphy_bitslip12_o = 4'd0; +reg [7:0] ddrphy_bitslip12_r = 8'd0; +reg [1:0] ddrphy_bitslip12_value = 2'd0; +wire [3:0] ddrphy_bitslip13_i; +reg [3:0] ddrphy_bitslip13_o = 4'd0; +reg [7:0] ddrphy_bitslip13_r = 8'd0; +reg [1:0] ddrphy_bitslip13_value = 2'd0; +wire [3:0] ddrphy_bitslip14_i; +reg [3:0] ddrphy_bitslip14_o = 4'd0; +reg [7:0] ddrphy_bitslip14_r = 8'd0; +reg [1:0] ddrphy_bitslip14_value = 2'd0; +wire [3:0] ddrphy_bitslip15_i; +reg [3:0] ddrphy_bitslip15_o = 4'd0; +reg [7:0] ddrphy_bitslip15_r = 8'd0; +reg [1:0] ddrphy_bitslip15_value = 2'd0; +wire [3:0] ddrphy_bitslip1_i; +reg [3:0] ddrphy_bitslip1_o = 4'd0; +reg [7:0] ddrphy_bitslip1_r = 8'd0; +reg [1:0] ddrphy_bitslip1_value = 2'd0; +wire [3:0] ddrphy_bitslip2_i; +reg [3:0] ddrphy_bitslip2_o = 4'd0; +reg [7:0] ddrphy_bitslip2_r = 8'd0; +reg [1:0] ddrphy_bitslip2_value = 2'd0; +wire [3:0] ddrphy_bitslip3_i; +reg [3:0] ddrphy_bitslip3_o = 4'd0; +reg [7:0] ddrphy_bitslip3_r = 8'd0; +reg [1:0] ddrphy_bitslip3_value = 2'd0; +wire [3:0] ddrphy_bitslip4_i; +reg [3:0] ddrphy_bitslip4_o = 4'd0; +reg [7:0] ddrphy_bitslip4_r = 8'd0; +reg [1:0] ddrphy_bitslip4_value = 2'd0; +wire [3:0] ddrphy_bitslip5_i; +reg [3:0] ddrphy_bitslip5_o = 4'd0; +reg [7:0] ddrphy_bitslip5_r = 8'd0; +reg [1:0] ddrphy_bitslip5_value = 2'd0; +wire [3:0] ddrphy_bitslip6_i; +reg [3:0] ddrphy_bitslip6_o = 4'd0; +reg [7:0] ddrphy_bitslip6_r = 8'd0; +reg [1:0] ddrphy_bitslip6_value = 2'd0; +wire [3:0] ddrphy_bitslip7_i; +reg [3:0] ddrphy_bitslip7_o = 4'd0; +reg [7:0] ddrphy_bitslip7_r = 8'd0; +reg [1:0] ddrphy_bitslip7_value = 2'd0; +wire [3:0] ddrphy_bitslip8_i; +reg [3:0] ddrphy_bitslip8_o = 4'd0; +reg [7:0] ddrphy_bitslip8_r = 8'd0; +reg [1:0] ddrphy_bitslip8_value = 2'd0; +wire [3:0] ddrphy_bitslip9_i; +reg [3:0] ddrphy_bitslip9_o = 4'd0; +reg [7:0] ddrphy_bitslip9_r = 8'd0; +reg [1:0] ddrphy_bitslip9_value = 2'd0; +wire ddrphy_bl8_chunk; +wire ddrphy_burstdet0; +wire ddrphy_burstdet1; +wire ddrphy_burstdet_clr_r; +reg ddrphy_burstdet_clr_re = 1'd0; +reg ddrphy_burstdet_clr_w = 1'd0; +reg ddrphy_burstdet_clr_we = 1'd0; +reg ddrphy_burstdet_d0 = 1'd0; +reg ddrphy_burstdet_d1 = 1'd0; +reg ddrphy_burstdet_seen_re = 1'd0; +reg [1:0] ddrphy_burstdet_seen_status = 2'd0; +wire ddrphy_burstdet_seen_we; +wire [1:0] ddrphy_datavalid; +wire ddrphy_delay0; +wire ddrphy_delay1; +wire ddrphy_dfi_p0_act_n; +wire [14:0] ddrphy_dfi_p0_address; +wire [2:0] ddrphy_dfi_p0_bank; +wire ddrphy_dfi_p0_cas_n; +wire ddrphy_dfi_p0_cke; +wire ddrphy_dfi_p0_cs_n; +wire ddrphy_dfi_p0_odt; +wire ddrphy_dfi_p0_ras_n; +reg [63:0] ddrphy_dfi_p0_rddata = 64'd0; +wire ddrphy_dfi_p0_rddata_en; +wire ddrphy_dfi_p0_rddata_valid; +wire ddrphy_dfi_p0_reset_n; +wire ddrphy_dfi_p0_we_n; +wire [63:0] ddrphy_dfi_p0_wrdata; +wire ddrphy_dfi_p0_wrdata_en; +wire [7:0] ddrphy_dfi_p0_wrdata_mask; +wire ddrphy_dfi_p1_act_n; +wire [14:0] ddrphy_dfi_p1_address; +wire [2:0] ddrphy_dfi_p1_bank; +wire ddrphy_dfi_p1_cas_n; +wire ddrphy_dfi_p1_cke; +wire ddrphy_dfi_p1_cs_n; +wire ddrphy_dfi_p1_odt; +wire ddrphy_dfi_p1_ras_n; +reg [63:0] ddrphy_dfi_p1_rddata = 64'd0; +wire ddrphy_dfi_p1_rddata_en; +wire ddrphy_dfi_p1_rddata_valid; +wire ddrphy_dfi_p1_reset_n; +wire ddrphy_dfi_p1_we_n; +wire [63:0] ddrphy_dfi_p1_wrdata; +wire ddrphy_dfi_p1_wrdata_en; +wire [7:0] ddrphy_dfi_p1_wrdata_mask; +reg ddrphy_dly_sel_re = 1'd0; +reg [1:0] ddrphy_dly_sel_storage = 2'd0; +reg [7:0] ddrphy_dm_o_data0 = 8'd0; +reg [7:0] ddrphy_dm_o_data1 = 8'd0; +reg [7:0] ddrphy_dm_o_data_d0 = 8'd0; +reg [7:0] ddrphy_dm_o_data_d1 = 8'd0; +reg [3:0] ddrphy_dm_o_data_muxed0 = 4'd0; +reg [3:0] ddrphy_dm_o_data_muxed1 = 4'd0; +wire ddrphy_dq_i0; +wire ddrphy_dq_i1; +wire ddrphy_dq_i10; +wire ddrphy_dq_i11; +wire ddrphy_dq_i12; +wire ddrphy_dq_i13; +wire ddrphy_dq_i14; +wire ddrphy_dq_i15; +wire ddrphy_dq_i2; +wire ddrphy_dq_i3; +wire ddrphy_dq_i4; +wire ddrphy_dq_i5; +wire ddrphy_dq_i6; +wire ddrphy_dq_i7; +wire ddrphy_dq_i8; +wire ddrphy_dq_i9; +reg [3:0] ddrphy_dq_i_bitslip_o_d0 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d1 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d10 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d11 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d12 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d13 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d14 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d15 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d2 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d3 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d4 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d5 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d6 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d7 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d8 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d9 = 4'd0; +wire [7:0] ddrphy_dq_i_data0; +wire [7:0] ddrphy_dq_i_data1; +wire [7:0] ddrphy_dq_i_data10; +wire [7:0] ddrphy_dq_i_data11; +wire [7:0] ddrphy_dq_i_data12; +wire [7:0] ddrphy_dq_i_data13; +wire [7:0] ddrphy_dq_i_data14; +wire [7:0] ddrphy_dq_i_data15; +wire [7:0] ddrphy_dq_i_data2; +wire [7:0] ddrphy_dq_i_data3; +wire [7:0] ddrphy_dq_i_data4; +wire [7:0] ddrphy_dq_i_data5; +wire [7:0] ddrphy_dq_i_data6; +wire [7:0] ddrphy_dq_i_data7; +wire [7:0] ddrphy_dq_i_data8; +wire [7:0] ddrphy_dq_i_data9; +wire ddrphy_dq_i_delayed0; +wire ddrphy_dq_i_delayed1; +wire ddrphy_dq_i_delayed10; +wire ddrphy_dq_i_delayed11; +wire ddrphy_dq_i_delayed12; +wire ddrphy_dq_i_delayed13; +wire ddrphy_dq_i_delayed14; +wire ddrphy_dq_i_delayed15; +wire ddrphy_dq_i_delayed2; +wire ddrphy_dq_i_delayed3; +wire ddrphy_dq_i_delayed4; +wire ddrphy_dq_i_delayed5; +wire ddrphy_dq_i_delayed6; +wire ddrphy_dq_i_delayed7; +wire ddrphy_dq_i_delayed8; +wire ddrphy_dq_i_delayed9; +wire ddrphy_dq_o0; +wire ddrphy_dq_o1; +wire ddrphy_dq_o10; +wire ddrphy_dq_o11; +wire ddrphy_dq_o12; +wire ddrphy_dq_o13; +wire ddrphy_dq_o14; +wire ddrphy_dq_o15; +wire ddrphy_dq_o2; +wire ddrphy_dq_o3; +wire ddrphy_dq_o4; +wire ddrphy_dq_o5; +wire ddrphy_dq_o6; +wire ddrphy_dq_o7; +wire ddrphy_dq_o8; +wire ddrphy_dq_o9; +reg [7:0] ddrphy_dq_o_data0 = 8'd0; +reg [7:0] ddrphy_dq_o_data1 = 8'd0; +reg [7:0] ddrphy_dq_o_data10 = 8'd0; +reg [7:0] ddrphy_dq_o_data11 = 8'd0; +reg [7:0] ddrphy_dq_o_data12 = 8'd0; +reg [7:0] ddrphy_dq_o_data13 = 8'd0; +reg [7:0] ddrphy_dq_o_data14 = 8'd0; +reg [7:0] ddrphy_dq_o_data15 = 8'd0; +reg [7:0] ddrphy_dq_o_data2 = 8'd0; +reg [7:0] ddrphy_dq_o_data3 = 8'd0; +reg [7:0] ddrphy_dq_o_data4 = 8'd0; +reg [7:0] ddrphy_dq_o_data5 = 8'd0; +reg [7:0] ddrphy_dq_o_data6 = 8'd0; +reg [7:0] ddrphy_dq_o_data7 = 8'd0; +reg [7:0] ddrphy_dq_o_data8 = 8'd0; +reg [7:0] ddrphy_dq_o_data9 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d0 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d1 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d10 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d11 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d12 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d13 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d14 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d15 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d2 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d3 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d4 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d5 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d6 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d7 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d8 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d9 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed0 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed1 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed10 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed11 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed12 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed13 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed14 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed15 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed2 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed3 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed4 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed5 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed6 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed7 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed8 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed9 = 4'd0; +wire ddrphy_dq_oe; +wire ddrphy_dq_oe_n0; +wire ddrphy_dq_oe_n1; +wire ddrphy_dq_oe_n10; +wire ddrphy_dq_oe_n11; +wire ddrphy_dq_oe_n12; +wire ddrphy_dq_oe_n13; +wire ddrphy_dq_oe_n14; +wire ddrphy_dq_oe_n15; +wire ddrphy_dq_oe_n2; +wire ddrphy_dq_oe_n3; +wire ddrphy_dq_oe_n4; +wire ddrphy_dq_oe_n5; +wire ddrphy_dq_oe_n6; +wire ddrphy_dq_oe_n7; +wire ddrphy_dq_oe_n8; +wire ddrphy_dq_oe_n9; +wire ddrphy_dqs0; +wire ddrphy_dqs1; +wire ddrphy_dqs_i0; +wire ddrphy_dqs_i1; +wire ddrphy_dqs_oe; +wire ddrphy_dqs_oe_n0; +wire ddrphy_dqs_oe_n1; +wire ddrphy_dqs_postamble; +wire ddrphy_dqs_preamble; +wire ddrphy_dqs_re; +wire ddrphy_dqsr900; +wire ddrphy_dqsr901; +wire ddrphy_dqsw0; +wire ddrphy_dqsw1; +wire ddrphy_dqsw2700; +wire ddrphy_dqsw2701; +reg ddrphy_freeze = 1'd0; +wire ddrphy_lock0; +wire ddrphy_lock1; +reg ddrphy_lock_d = 1'd0; +wire ddrphy_new_lock; +wire ddrphy_pad_oddrx2f0; +wire ddrphy_pad_oddrx2f1; +wire ddrphy_pad_oddrx2f10; +wire ddrphy_pad_oddrx2f11; +wire ddrphy_pad_oddrx2f12; +wire ddrphy_pad_oddrx2f13; +wire ddrphy_pad_oddrx2f14; +wire ddrphy_pad_oddrx2f15; +wire ddrphy_pad_oddrx2f16; +wire ddrphy_pad_oddrx2f17; +wire ddrphy_pad_oddrx2f18; +wire ddrphy_pad_oddrx2f19; +wire ddrphy_pad_oddrx2f2; +wire ddrphy_pad_oddrx2f20; +wire ddrphy_pad_oddrx2f21; +wire ddrphy_pad_oddrx2f22; +wire ddrphy_pad_oddrx2f23; +wire ddrphy_pad_oddrx2f24; +wire ddrphy_pad_oddrx2f25; +wire ddrphy_pad_oddrx2f3; +wire ddrphy_pad_oddrx2f4; +wire ddrphy_pad_oddrx2f5; +wire ddrphy_pad_oddrx2f6; +wire ddrphy_pad_oddrx2f7; +wire ddrphy_pad_oddrx2f8; +wire ddrphy_pad_oddrx2f9; +wire ddrphy_pause0; +reg ddrphy_pause1 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline10 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline11 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline12 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline7 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline8 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline9 = 1'd0; +reg [2:0] ddrphy_rdly0 = 3'd0; +reg [2:0] ddrphy_rdly1 = 3'd0; +wire ddrphy_rdly_dq_bitslip_r; +reg ddrphy_rdly_dq_bitslip_re = 1'd0; +wire ddrphy_rdly_dq_bitslip_rst_r; +reg ddrphy_rdly_dq_bitslip_rst_re = 1'd0; +reg ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +reg ddrphy_rdly_dq_bitslip_rst_we = 1'd0; +reg ddrphy_rdly_dq_bitslip_w = 1'd0; +reg ddrphy_rdly_dq_bitslip_we = 1'd0; +wire ddrphy_rdly_dq_inc_r; +reg ddrphy_rdly_dq_inc_re = 1'd0; +reg ddrphy_rdly_dq_inc_w = 1'd0; +reg ddrphy_rdly_dq_inc_we = 1'd0; +wire ddrphy_rdly_dq_rst_r; +reg ddrphy_rdly_dq_rst_re = 1'd0; +reg ddrphy_rdly_dq_rst_w = 1'd0; +reg ddrphy_rdly_dq_rst_we = 1'd0; +wire [2:0] ddrphy_rdpntr0; +wire [2:0] ddrphy_rdpntr1; +wire ddrphy_reset0; +reg ddrphy_reset1 = 1'd0; +wire ddrphy_stop0; +reg ddrphy_stop1 = 1'd0; +reg [6:0] ddrphy_trigger = 7'd0; +reg ddrphy_update = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline3 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline4 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline5 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline6 = 1'd0; +wire [2:0] ddrphy_wrpntr0; +wire [2:0] ddrphy_wrpntr1; +wire init_clk; +reg init_done_re = 1'd0; +reg init_done_storage = 1'd0; +reg init_error_re = 1'd0; +reg init_error_storage = 1'd0; +wire init_rst; +reg interface0_ack = 1'd0; +wire [29:0] interface0_adr; +wire [13:0] interface0_bank_bus_adr; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; +wire [31:0] interface0_bank_bus_dat_w; +wire interface0_bank_bus_we; +wire [1:0] interface0_bte; +wire [2:0] interface0_cti; +wire interface0_cyc; +reg [31:0] interface0_dat_r = 32'd0; +wire [31:0] interface0_dat_w; +reg interface0_err = 1'd0; +wire [3:0] interface0_sel; +wire interface0_stb; +wire interface0_we; +reg [13:0] interface1_adr = 14'd0; +reg [13:0] interface1_adr_next_value1 = 14'd0; +reg interface1_adr_next_value_ce1 = 1'd0; +wire [13:0] interface1_bank_bus_adr; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; +wire [31:0] interface1_bank_bus_dat_w; +wire interface1_bank_bus_we; +wire [31:0] interface1_dat_r; +reg [31:0] interface1_dat_w = 32'd0; +reg [31:0] interface1_dat_w_next_value0 = 32'd0; +reg interface1_dat_w_next_value_ce0 = 1'd0; +reg interface1_we = 1'd0; +reg interface1_we_next_value2 = 1'd0; +reg interface1_we_next_value_ce2 = 1'd0; +wire [13:0] interface2_bank_bus_adr; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; +wire [31:0] interface2_bank_bus_dat_w; +wire interface2_bank_bus_we; +wire latticeecp5asyncresetsynchronizerimpl0_expr; +wire latticeecp5asyncresetsynchronizerimpl0_rst1; +wire latticeecp5asyncresetsynchronizerimpl1_rst1; +wire latticeecp5asyncresetsynchronizerimpl2_rst1; +wire latticeecp5asyncresetsynchronizerimpl3_rst1; +reg litedramcore_bankmachine0_auto_precharge = 1'd0; +reg [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; +reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine0_cmd_ready = 1'd0; +reg litedramcore_bankmachine0_cmd_valid = 1'd0; +reg [3:0] litedramcore_bankmachine0_consume = 4'd0; +wire litedramcore_bankmachine0_do_read; +wire litedramcore_bankmachine0_fifo_in_first; +wire litedramcore_bankmachine0_fifo_in_last; +wire [21:0] litedramcore_bankmachine0_fifo_in_payload_addr; +wire litedramcore_bankmachine0_fifo_in_payload_we; +wire litedramcore_bankmachine0_fifo_out_first; +wire litedramcore_bankmachine0_fifo_out_last; +wire [21:0] litedramcore_bankmachine0_fifo_out_payload_addr; +wire litedramcore_bankmachine0_fifo_out_payload_we; +reg [4:0] litedramcore_bankmachine0_level = 5'd0; +reg [2:0] litedramcore_bankmachine0_next_state = 3'd0; +wire litedramcore_bankmachine0_pipe_valid_sink_first; +wire litedramcore_bankmachine0_pipe_valid_sink_last; +wire [21:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr; +wire litedramcore_bankmachine0_pipe_valid_sink_payload_we; +wire litedramcore_bankmachine0_pipe_valid_sink_ready; +wire litedramcore_bankmachine0_pipe_valid_sink_valid; +reg litedramcore_bankmachine0_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine0_pipe_valid_source_last = 1'd0; +reg [21:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 22'd0; +reg litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; +wire litedramcore_bankmachine0_pipe_valid_source_ready; +reg litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; +reg [3:0] litedramcore_bankmachine0_produce = 4'd0; +wire [3:0] litedramcore_bankmachine0_rdport_adr; +wire [24:0] litedramcore_bankmachine0_rdport_dat_r; +reg litedramcore_bankmachine0_refresh_gnt = 1'd0; +wire litedramcore_bankmachine0_refresh_req; +reg litedramcore_bankmachine0_replace = 1'd0; +wire [21:0] litedramcore_bankmachine0_req_addr; +wire litedramcore_bankmachine0_req_lock; +reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine0_req_ready; +wire litedramcore_bankmachine0_req_valid; +reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; +wire litedramcore_bankmachine0_req_we; +reg [14:0] litedramcore_bankmachine0_row = 15'd0; +reg litedramcore_bankmachine0_row_close = 1'd0; +reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine0_row_hit; +reg litedramcore_bankmachine0_row_open = 1'd0; +reg litedramcore_bankmachine0_row_opened = 1'd0; +reg litedramcore_bankmachine0_sink_first = 1'd0; +reg litedramcore_bankmachine0_sink_last = 1'd0; +wire [21:0] litedramcore_bankmachine0_sink_payload_addr; +wire litedramcore_bankmachine0_sink_payload_we; +wire litedramcore_bankmachine0_sink_ready; +wire litedramcore_bankmachine0_sink_sink_first; +wire litedramcore_bankmachine0_sink_sink_last; +wire [21:0] litedramcore_bankmachine0_sink_sink_payload_addr; +wire litedramcore_bankmachine0_sink_sink_payload_we; +wire litedramcore_bankmachine0_sink_sink_ready; +wire litedramcore_bankmachine0_sink_sink_valid; +wire litedramcore_bankmachine0_sink_valid; +wire litedramcore_bankmachine0_source_first; +wire litedramcore_bankmachine0_source_last; +wire [21:0] litedramcore_bankmachine0_source_payload_addr; +wire litedramcore_bankmachine0_source_payload_we; +wire litedramcore_bankmachine0_source_ready; +wire litedramcore_bankmachine0_source_source_first; +wire litedramcore_bankmachine0_source_source_last; +wire [21:0] litedramcore_bankmachine0_source_source_payload_addr; +wire litedramcore_bankmachine0_source_source_payload_we; +wire litedramcore_bankmachine0_source_source_ready; +wire litedramcore_bankmachine0_source_source_valid; +wire litedramcore_bankmachine0_source_valid; +reg [2:0] litedramcore_bankmachine0_state = 3'd0; +wire [24:0] litedramcore_bankmachine0_syncfifo0_din; +wire [24:0] litedramcore_bankmachine0_syncfifo0_dout; +wire litedramcore_bankmachine0_syncfifo0_re; +wire litedramcore_bankmachine0_syncfifo0_readable; +wire litedramcore_bankmachine0_syncfifo0_we; +wire litedramcore_bankmachine0_syncfifo0_writable; +reg [1:0] litedramcore_bankmachine0_trascon_count = 2'd0; +reg litedramcore_bankmachine0_trascon_ready = 1'd0; +wire litedramcore_bankmachine0_trascon_valid; +reg [1:0] litedramcore_bankmachine0_trccon_count = 2'd0; +reg litedramcore_bankmachine0_trccon_ready = 1'd0; +wire litedramcore_bankmachine0_trccon_valid; +reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; +reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; +wire litedramcore_bankmachine0_twtpcon_valid; +reg [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine0_wrport_dat_r; +wire [24:0] litedramcore_bankmachine0_wrport_dat_w; +wire litedramcore_bankmachine0_wrport_we; +reg litedramcore_bankmachine1_auto_precharge = 1'd0; +reg [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; +reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine1_cmd_ready = 1'd0; +reg litedramcore_bankmachine1_cmd_valid = 1'd0; +reg [3:0] litedramcore_bankmachine1_consume = 4'd0; +wire litedramcore_bankmachine1_do_read; +wire litedramcore_bankmachine1_fifo_in_first; +wire litedramcore_bankmachine1_fifo_in_last; +wire [21:0] litedramcore_bankmachine1_fifo_in_payload_addr; +wire litedramcore_bankmachine1_fifo_in_payload_we; +wire litedramcore_bankmachine1_fifo_out_first; +wire litedramcore_bankmachine1_fifo_out_last; +wire [21:0] litedramcore_bankmachine1_fifo_out_payload_addr; +wire litedramcore_bankmachine1_fifo_out_payload_we; +reg [4:0] litedramcore_bankmachine1_level = 5'd0; +reg [2:0] litedramcore_bankmachine1_next_state = 3'd0; +wire litedramcore_bankmachine1_pipe_valid_sink_first; +wire litedramcore_bankmachine1_pipe_valid_sink_last; +wire [21:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr; +wire litedramcore_bankmachine1_pipe_valid_sink_payload_we; +wire litedramcore_bankmachine1_pipe_valid_sink_ready; +wire litedramcore_bankmachine1_pipe_valid_sink_valid; +reg litedramcore_bankmachine1_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine1_pipe_valid_source_last = 1'd0; +reg [21:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 22'd0; +reg litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; +wire litedramcore_bankmachine1_pipe_valid_source_ready; +reg litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; +reg [3:0] litedramcore_bankmachine1_produce = 4'd0; +wire [3:0] litedramcore_bankmachine1_rdport_adr; +wire [24:0] litedramcore_bankmachine1_rdport_dat_r; +reg litedramcore_bankmachine1_refresh_gnt = 1'd0; +wire litedramcore_bankmachine1_refresh_req; +reg litedramcore_bankmachine1_replace = 1'd0; +wire [21:0] litedramcore_bankmachine1_req_addr; +wire litedramcore_bankmachine1_req_lock; +reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine1_req_ready; +wire litedramcore_bankmachine1_req_valid; +reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; +wire litedramcore_bankmachine1_req_we; +reg [14:0] litedramcore_bankmachine1_row = 15'd0; +reg litedramcore_bankmachine1_row_close = 1'd0; +reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine1_row_hit; +reg litedramcore_bankmachine1_row_open = 1'd0; +reg litedramcore_bankmachine1_row_opened = 1'd0; +reg litedramcore_bankmachine1_sink_first = 1'd0; +reg litedramcore_bankmachine1_sink_last = 1'd0; +wire [21:0] litedramcore_bankmachine1_sink_payload_addr; +wire litedramcore_bankmachine1_sink_payload_we; +wire litedramcore_bankmachine1_sink_ready; +wire litedramcore_bankmachine1_sink_sink_first; +wire litedramcore_bankmachine1_sink_sink_last; +wire [21:0] litedramcore_bankmachine1_sink_sink_payload_addr; +wire litedramcore_bankmachine1_sink_sink_payload_we; +wire litedramcore_bankmachine1_sink_sink_ready; +wire litedramcore_bankmachine1_sink_sink_valid; +wire litedramcore_bankmachine1_sink_valid; +wire litedramcore_bankmachine1_source_first; +wire litedramcore_bankmachine1_source_last; +wire [21:0] litedramcore_bankmachine1_source_payload_addr; +wire litedramcore_bankmachine1_source_payload_we; +wire litedramcore_bankmachine1_source_ready; +wire litedramcore_bankmachine1_source_source_first; +wire litedramcore_bankmachine1_source_source_last; +wire [21:0] litedramcore_bankmachine1_source_source_payload_addr; +wire litedramcore_bankmachine1_source_source_payload_we; +wire litedramcore_bankmachine1_source_source_ready; +wire litedramcore_bankmachine1_source_source_valid; +wire litedramcore_bankmachine1_source_valid; +reg [2:0] litedramcore_bankmachine1_state = 3'd0; +wire [24:0] litedramcore_bankmachine1_syncfifo1_din; +wire [24:0] litedramcore_bankmachine1_syncfifo1_dout; +wire litedramcore_bankmachine1_syncfifo1_re; +wire litedramcore_bankmachine1_syncfifo1_readable; +wire litedramcore_bankmachine1_syncfifo1_we; +wire litedramcore_bankmachine1_syncfifo1_writable; +reg [1:0] litedramcore_bankmachine1_trascon_count = 2'd0; +reg litedramcore_bankmachine1_trascon_ready = 1'd0; +wire litedramcore_bankmachine1_trascon_valid; +reg [1:0] litedramcore_bankmachine1_trccon_count = 2'd0; +reg litedramcore_bankmachine1_trccon_ready = 1'd0; +wire litedramcore_bankmachine1_trccon_valid; +reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; +reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; +wire litedramcore_bankmachine1_twtpcon_valid; +reg [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine1_wrport_dat_r; +wire [24:0] litedramcore_bankmachine1_wrport_dat_w; +wire litedramcore_bankmachine1_wrport_we; +reg litedramcore_bankmachine2_auto_precharge = 1'd0; +reg [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; +reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine2_cmd_ready = 1'd0; +reg litedramcore_bankmachine2_cmd_valid = 1'd0; +reg [3:0] litedramcore_bankmachine2_consume = 4'd0; +wire litedramcore_bankmachine2_do_read; +wire litedramcore_bankmachine2_fifo_in_first; +wire litedramcore_bankmachine2_fifo_in_last; +wire [21:0] litedramcore_bankmachine2_fifo_in_payload_addr; +wire litedramcore_bankmachine2_fifo_in_payload_we; +wire litedramcore_bankmachine2_fifo_out_first; +wire litedramcore_bankmachine2_fifo_out_last; +wire [21:0] litedramcore_bankmachine2_fifo_out_payload_addr; +wire litedramcore_bankmachine2_fifo_out_payload_we; +reg [4:0] litedramcore_bankmachine2_level = 5'd0; +reg [2:0] litedramcore_bankmachine2_next_state = 3'd0; +wire litedramcore_bankmachine2_pipe_valid_sink_first; +wire litedramcore_bankmachine2_pipe_valid_sink_last; +wire [21:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr; +wire litedramcore_bankmachine2_pipe_valid_sink_payload_we; +wire litedramcore_bankmachine2_pipe_valid_sink_ready; +wire litedramcore_bankmachine2_pipe_valid_sink_valid; +reg litedramcore_bankmachine2_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine2_pipe_valid_source_last = 1'd0; +reg [21:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 22'd0; +reg litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; +wire litedramcore_bankmachine2_pipe_valid_source_ready; +reg litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; +reg [3:0] litedramcore_bankmachine2_produce = 4'd0; +wire [3:0] litedramcore_bankmachine2_rdport_adr; +wire [24:0] litedramcore_bankmachine2_rdport_dat_r; +reg litedramcore_bankmachine2_refresh_gnt = 1'd0; +wire litedramcore_bankmachine2_refresh_req; +reg litedramcore_bankmachine2_replace = 1'd0; +wire [21:0] litedramcore_bankmachine2_req_addr; +wire litedramcore_bankmachine2_req_lock; +reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine2_req_ready; +wire litedramcore_bankmachine2_req_valid; +reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; +wire litedramcore_bankmachine2_req_we; +reg [14:0] litedramcore_bankmachine2_row = 15'd0; +reg litedramcore_bankmachine2_row_close = 1'd0; +reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine2_row_hit; +reg litedramcore_bankmachine2_row_open = 1'd0; +reg litedramcore_bankmachine2_row_opened = 1'd0; +reg litedramcore_bankmachine2_sink_first = 1'd0; +reg litedramcore_bankmachine2_sink_last = 1'd0; +wire [21:0] litedramcore_bankmachine2_sink_payload_addr; +wire litedramcore_bankmachine2_sink_payload_we; +wire litedramcore_bankmachine2_sink_ready; +wire litedramcore_bankmachine2_sink_sink_first; +wire litedramcore_bankmachine2_sink_sink_last; +wire [21:0] litedramcore_bankmachine2_sink_sink_payload_addr; +wire litedramcore_bankmachine2_sink_sink_payload_we; +wire litedramcore_bankmachine2_sink_sink_ready; +wire litedramcore_bankmachine2_sink_sink_valid; +wire litedramcore_bankmachine2_sink_valid; +wire litedramcore_bankmachine2_source_first; +wire litedramcore_bankmachine2_source_last; +wire [21:0] litedramcore_bankmachine2_source_payload_addr; +wire litedramcore_bankmachine2_source_payload_we; +wire litedramcore_bankmachine2_source_ready; +wire litedramcore_bankmachine2_source_source_first; +wire litedramcore_bankmachine2_source_source_last; +wire [21:0] litedramcore_bankmachine2_source_source_payload_addr; +wire litedramcore_bankmachine2_source_source_payload_we; +wire litedramcore_bankmachine2_source_source_ready; +wire litedramcore_bankmachine2_source_source_valid; +wire litedramcore_bankmachine2_source_valid; +reg [2:0] litedramcore_bankmachine2_state = 3'd0; +wire [24:0] litedramcore_bankmachine2_syncfifo2_din; +wire [24:0] litedramcore_bankmachine2_syncfifo2_dout; +wire litedramcore_bankmachine2_syncfifo2_re; +wire litedramcore_bankmachine2_syncfifo2_readable; +wire litedramcore_bankmachine2_syncfifo2_we; +wire litedramcore_bankmachine2_syncfifo2_writable; +reg [1:0] litedramcore_bankmachine2_trascon_count = 2'd0; +reg litedramcore_bankmachine2_trascon_ready = 1'd0; +wire litedramcore_bankmachine2_trascon_valid; +reg [1:0] litedramcore_bankmachine2_trccon_count = 2'd0; +reg litedramcore_bankmachine2_trccon_ready = 1'd0; +wire litedramcore_bankmachine2_trccon_valid; +reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; +reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; +wire litedramcore_bankmachine2_twtpcon_valid; +reg [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine2_wrport_dat_r; +wire [24:0] litedramcore_bankmachine2_wrport_dat_w; +wire litedramcore_bankmachine2_wrport_we; +reg litedramcore_bankmachine3_auto_precharge = 1'd0; +reg [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; +reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine3_cmd_ready = 1'd0; +reg litedramcore_bankmachine3_cmd_valid = 1'd0; +reg [3:0] litedramcore_bankmachine3_consume = 4'd0; +wire litedramcore_bankmachine3_do_read; +wire litedramcore_bankmachine3_fifo_in_first; +wire litedramcore_bankmachine3_fifo_in_last; +wire [21:0] litedramcore_bankmachine3_fifo_in_payload_addr; +wire litedramcore_bankmachine3_fifo_in_payload_we; +wire litedramcore_bankmachine3_fifo_out_first; +wire litedramcore_bankmachine3_fifo_out_last; +wire [21:0] litedramcore_bankmachine3_fifo_out_payload_addr; +wire litedramcore_bankmachine3_fifo_out_payload_we; +reg [4:0] litedramcore_bankmachine3_level = 5'd0; +reg [2:0] litedramcore_bankmachine3_next_state = 3'd0; +wire litedramcore_bankmachine3_pipe_valid_sink_first; +wire litedramcore_bankmachine3_pipe_valid_sink_last; +wire [21:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr; +wire litedramcore_bankmachine3_pipe_valid_sink_payload_we; +wire litedramcore_bankmachine3_pipe_valid_sink_ready; +wire litedramcore_bankmachine3_pipe_valid_sink_valid; +reg litedramcore_bankmachine3_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine3_pipe_valid_source_last = 1'd0; +reg [21:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 22'd0; +reg litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; +wire litedramcore_bankmachine3_pipe_valid_source_ready; +reg litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; +reg [3:0] litedramcore_bankmachine3_produce = 4'd0; +wire [3:0] litedramcore_bankmachine3_rdport_adr; +wire [24:0] litedramcore_bankmachine3_rdport_dat_r; +reg litedramcore_bankmachine3_refresh_gnt = 1'd0; +wire litedramcore_bankmachine3_refresh_req; +reg litedramcore_bankmachine3_replace = 1'd0; +wire [21:0] litedramcore_bankmachine3_req_addr; +wire litedramcore_bankmachine3_req_lock; +reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine3_req_ready; +wire litedramcore_bankmachine3_req_valid; +reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; +wire litedramcore_bankmachine3_req_we; +reg [14:0] litedramcore_bankmachine3_row = 15'd0; +reg litedramcore_bankmachine3_row_close = 1'd0; +reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine3_row_hit; +reg litedramcore_bankmachine3_row_open = 1'd0; +reg litedramcore_bankmachine3_row_opened = 1'd0; +reg litedramcore_bankmachine3_sink_first = 1'd0; +reg litedramcore_bankmachine3_sink_last = 1'd0; +wire [21:0] litedramcore_bankmachine3_sink_payload_addr; +wire litedramcore_bankmachine3_sink_payload_we; +wire litedramcore_bankmachine3_sink_ready; +wire litedramcore_bankmachine3_sink_sink_first; +wire litedramcore_bankmachine3_sink_sink_last; +wire [21:0] litedramcore_bankmachine3_sink_sink_payload_addr; +wire litedramcore_bankmachine3_sink_sink_payload_we; +wire litedramcore_bankmachine3_sink_sink_ready; +wire litedramcore_bankmachine3_sink_sink_valid; +wire litedramcore_bankmachine3_sink_valid; +wire litedramcore_bankmachine3_source_first; +wire litedramcore_bankmachine3_source_last; +wire [21:0] litedramcore_bankmachine3_source_payload_addr; +wire litedramcore_bankmachine3_source_payload_we; +wire litedramcore_bankmachine3_source_ready; +wire litedramcore_bankmachine3_source_source_first; +wire litedramcore_bankmachine3_source_source_last; +wire [21:0] litedramcore_bankmachine3_source_source_payload_addr; +wire litedramcore_bankmachine3_source_source_payload_we; +wire litedramcore_bankmachine3_source_source_ready; +wire litedramcore_bankmachine3_source_source_valid; +wire litedramcore_bankmachine3_source_valid; +reg [2:0] litedramcore_bankmachine3_state = 3'd0; +wire [24:0] litedramcore_bankmachine3_syncfifo3_din; +wire [24:0] litedramcore_bankmachine3_syncfifo3_dout; +wire litedramcore_bankmachine3_syncfifo3_re; +wire litedramcore_bankmachine3_syncfifo3_readable; +wire litedramcore_bankmachine3_syncfifo3_we; +wire litedramcore_bankmachine3_syncfifo3_writable; +reg [1:0] litedramcore_bankmachine3_trascon_count = 2'd0; +reg litedramcore_bankmachine3_trascon_ready = 1'd0; +wire litedramcore_bankmachine3_trascon_valid; +reg [1:0] litedramcore_bankmachine3_trccon_count = 2'd0; +reg litedramcore_bankmachine3_trccon_ready = 1'd0; +wire litedramcore_bankmachine3_trccon_valid; +reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; +reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; +wire litedramcore_bankmachine3_twtpcon_valid; +reg [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine3_wrport_dat_r; +wire [24:0] litedramcore_bankmachine3_wrport_dat_w; +wire litedramcore_bankmachine3_wrport_we; +reg litedramcore_bankmachine4_auto_precharge = 1'd0; +reg [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; +reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine4_cmd_ready = 1'd0; +reg litedramcore_bankmachine4_cmd_valid = 1'd0; +reg [3:0] litedramcore_bankmachine4_consume = 4'd0; +wire litedramcore_bankmachine4_do_read; +wire litedramcore_bankmachine4_fifo_in_first; +wire litedramcore_bankmachine4_fifo_in_last; +wire [21:0] litedramcore_bankmachine4_fifo_in_payload_addr; +wire litedramcore_bankmachine4_fifo_in_payload_we; +wire litedramcore_bankmachine4_fifo_out_first; +wire litedramcore_bankmachine4_fifo_out_last; +wire [21:0] litedramcore_bankmachine4_fifo_out_payload_addr; +wire litedramcore_bankmachine4_fifo_out_payload_we; +reg [4:0] litedramcore_bankmachine4_level = 5'd0; +reg [2:0] litedramcore_bankmachine4_next_state = 3'd0; +wire litedramcore_bankmachine4_pipe_valid_sink_first; +wire litedramcore_bankmachine4_pipe_valid_sink_last; +wire [21:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr; +wire litedramcore_bankmachine4_pipe_valid_sink_payload_we; +wire litedramcore_bankmachine4_pipe_valid_sink_ready; +wire litedramcore_bankmachine4_pipe_valid_sink_valid; +reg litedramcore_bankmachine4_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine4_pipe_valid_source_last = 1'd0; +reg [21:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 22'd0; +reg litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; +wire litedramcore_bankmachine4_pipe_valid_source_ready; +reg litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; +reg [3:0] litedramcore_bankmachine4_produce = 4'd0; +wire [3:0] litedramcore_bankmachine4_rdport_adr; +wire [24:0] litedramcore_bankmachine4_rdport_dat_r; +reg litedramcore_bankmachine4_refresh_gnt = 1'd0; +wire litedramcore_bankmachine4_refresh_req; +reg litedramcore_bankmachine4_replace = 1'd0; +wire [21:0] litedramcore_bankmachine4_req_addr; +wire litedramcore_bankmachine4_req_lock; +reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine4_req_ready; +wire litedramcore_bankmachine4_req_valid; +reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; +wire litedramcore_bankmachine4_req_we; +reg [14:0] litedramcore_bankmachine4_row = 15'd0; +reg litedramcore_bankmachine4_row_close = 1'd0; +reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine4_row_hit; +reg litedramcore_bankmachine4_row_open = 1'd0; +reg litedramcore_bankmachine4_row_opened = 1'd0; +reg litedramcore_bankmachine4_sink_first = 1'd0; +reg litedramcore_bankmachine4_sink_last = 1'd0; +wire [21:0] litedramcore_bankmachine4_sink_payload_addr; +wire litedramcore_bankmachine4_sink_payload_we; +wire litedramcore_bankmachine4_sink_ready; +wire litedramcore_bankmachine4_sink_sink_first; +wire litedramcore_bankmachine4_sink_sink_last; +wire [21:0] litedramcore_bankmachine4_sink_sink_payload_addr; +wire litedramcore_bankmachine4_sink_sink_payload_we; +wire litedramcore_bankmachine4_sink_sink_ready; +wire litedramcore_bankmachine4_sink_sink_valid; +wire litedramcore_bankmachine4_sink_valid; +wire litedramcore_bankmachine4_source_first; +wire litedramcore_bankmachine4_source_last; +wire [21:0] litedramcore_bankmachine4_source_payload_addr; +wire litedramcore_bankmachine4_source_payload_we; +wire litedramcore_bankmachine4_source_ready; +wire litedramcore_bankmachine4_source_source_first; +wire litedramcore_bankmachine4_source_source_last; +wire [21:0] litedramcore_bankmachine4_source_source_payload_addr; +wire litedramcore_bankmachine4_source_source_payload_we; +wire litedramcore_bankmachine4_source_source_ready; +wire litedramcore_bankmachine4_source_source_valid; +wire litedramcore_bankmachine4_source_valid; +reg [2:0] litedramcore_bankmachine4_state = 3'd0; +wire [24:0] litedramcore_bankmachine4_syncfifo4_din; +wire [24:0] litedramcore_bankmachine4_syncfifo4_dout; +wire litedramcore_bankmachine4_syncfifo4_re; +wire litedramcore_bankmachine4_syncfifo4_readable; +wire litedramcore_bankmachine4_syncfifo4_we; +wire litedramcore_bankmachine4_syncfifo4_writable; +reg [1:0] litedramcore_bankmachine4_trascon_count = 2'd0; +reg litedramcore_bankmachine4_trascon_ready = 1'd0; +wire litedramcore_bankmachine4_trascon_valid; +reg [1:0] litedramcore_bankmachine4_trccon_count = 2'd0; +reg litedramcore_bankmachine4_trccon_ready = 1'd0; +wire litedramcore_bankmachine4_trccon_valid; +reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; +reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; +wire litedramcore_bankmachine4_twtpcon_valid; +reg [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine4_wrport_dat_r; +wire [24:0] litedramcore_bankmachine4_wrport_dat_w; +wire litedramcore_bankmachine4_wrport_we; +reg litedramcore_bankmachine5_auto_precharge = 1'd0; +reg [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; +reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine5_cmd_ready = 1'd0; +reg litedramcore_bankmachine5_cmd_valid = 1'd0; +reg [3:0] litedramcore_bankmachine5_consume = 4'd0; +wire litedramcore_bankmachine5_do_read; +wire litedramcore_bankmachine5_fifo_in_first; +wire litedramcore_bankmachine5_fifo_in_last; +wire [21:0] litedramcore_bankmachine5_fifo_in_payload_addr; +wire litedramcore_bankmachine5_fifo_in_payload_we; +wire litedramcore_bankmachine5_fifo_out_first; +wire litedramcore_bankmachine5_fifo_out_last; +wire [21:0] litedramcore_bankmachine5_fifo_out_payload_addr; +wire litedramcore_bankmachine5_fifo_out_payload_we; +reg [4:0] litedramcore_bankmachine5_level = 5'd0; +reg [2:0] litedramcore_bankmachine5_next_state = 3'd0; +wire litedramcore_bankmachine5_pipe_valid_sink_first; +wire litedramcore_bankmachine5_pipe_valid_sink_last; +wire [21:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr; +wire litedramcore_bankmachine5_pipe_valid_sink_payload_we; +wire litedramcore_bankmachine5_pipe_valid_sink_ready; +wire litedramcore_bankmachine5_pipe_valid_sink_valid; +reg litedramcore_bankmachine5_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine5_pipe_valid_source_last = 1'd0; +reg [21:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 22'd0; +reg litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; +wire litedramcore_bankmachine5_pipe_valid_source_ready; +reg litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; +reg [3:0] litedramcore_bankmachine5_produce = 4'd0; +wire [3:0] litedramcore_bankmachine5_rdport_adr; +wire [24:0] litedramcore_bankmachine5_rdport_dat_r; +reg litedramcore_bankmachine5_refresh_gnt = 1'd0; +wire litedramcore_bankmachine5_refresh_req; +reg litedramcore_bankmachine5_replace = 1'd0; +wire [21:0] litedramcore_bankmachine5_req_addr; +wire litedramcore_bankmachine5_req_lock; +reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine5_req_ready; +wire litedramcore_bankmachine5_req_valid; +reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; +wire litedramcore_bankmachine5_req_we; +reg [14:0] litedramcore_bankmachine5_row = 15'd0; +reg litedramcore_bankmachine5_row_close = 1'd0; +reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine5_row_hit; +reg litedramcore_bankmachine5_row_open = 1'd0; +reg litedramcore_bankmachine5_row_opened = 1'd0; +reg litedramcore_bankmachine5_sink_first = 1'd0; +reg litedramcore_bankmachine5_sink_last = 1'd0; +wire [21:0] litedramcore_bankmachine5_sink_payload_addr; +wire litedramcore_bankmachine5_sink_payload_we; +wire litedramcore_bankmachine5_sink_ready; +wire litedramcore_bankmachine5_sink_sink_first; +wire litedramcore_bankmachine5_sink_sink_last; +wire [21:0] litedramcore_bankmachine5_sink_sink_payload_addr; +wire litedramcore_bankmachine5_sink_sink_payload_we; +wire litedramcore_bankmachine5_sink_sink_ready; +wire litedramcore_bankmachine5_sink_sink_valid; +wire litedramcore_bankmachine5_sink_valid; +wire litedramcore_bankmachine5_source_first; +wire litedramcore_bankmachine5_source_last; +wire [21:0] litedramcore_bankmachine5_source_payload_addr; +wire litedramcore_bankmachine5_source_payload_we; +wire litedramcore_bankmachine5_source_ready; +wire litedramcore_bankmachine5_source_source_first; +wire litedramcore_bankmachine5_source_source_last; +wire [21:0] litedramcore_bankmachine5_source_source_payload_addr; +wire litedramcore_bankmachine5_source_source_payload_we; +wire litedramcore_bankmachine5_source_source_ready; +wire litedramcore_bankmachine5_source_source_valid; +wire litedramcore_bankmachine5_source_valid; +reg [2:0] litedramcore_bankmachine5_state = 3'd0; +wire [24:0] litedramcore_bankmachine5_syncfifo5_din; +wire [24:0] litedramcore_bankmachine5_syncfifo5_dout; +wire litedramcore_bankmachine5_syncfifo5_re; +wire litedramcore_bankmachine5_syncfifo5_readable; +wire litedramcore_bankmachine5_syncfifo5_we; +wire litedramcore_bankmachine5_syncfifo5_writable; +reg [1:0] litedramcore_bankmachine5_trascon_count = 2'd0; +reg litedramcore_bankmachine5_trascon_ready = 1'd0; +wire litedramcore_bankmachine5_trascon_valid; +reg [1:0] litedramcore_bankmachine5_trccon_count = 2'd0; +reg litedramcore_bankmachine5_trccon_ready = 1'd0; +wire litedramcore_bankmachine5_trccon_valid; +reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; +reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; +wire litedramcore_bankmachine5_twtpcon_valid; +reg [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine5_wrport_dat_r; +wire [24:0] litedramcore_bankmachine5_wrport_dat_w; +wire litedramcore_bankmachine5_wrport_we; +reg litedramcore_bankmachine6_auto_precharge = 1'd0; +reg [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; +reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine6_cmd_ready = 1'd0; +reg litedramcore_bankmachine6_cmd_valid = 1'd0; +reg [3:0] litedramcore_bankmachine6_consume = 4'd0; +wire litedramcore_bankmachine6_do_read; +wire litedramcore_bankmachine6_fifo_in_first; +wire litedramcore_bankmachine6_fifo_in_last; +wire [21:0] litedramcore_bankmachine6_fifo_in_payload_addr; +wire litedramcore_bankmachine6_fifo_in_payload_we; +wire litedramcore_bankmachine6_fifo_out_first; +wire litedramcore_bankmachine6_fifo_out_last; +wire [21:0] litedramcore_bankmachine6_fifo_out_payload_addr; +wire litedramcore_bankmachine6_fifo_out_payload_we; +reg [4:0] litedramcore_bankmachine6_level = 5'd0; +reg [2:0] litedramcore_bankmachine6_next_state = 3'd0; +wire litedramcore_bankmachine6_pipe_valid_sink_first; +wire litedramcore_bankmachine6_pipe_valid_sink_last; +wire [21:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr; +wire litedramcore_bankmachine6_pipe_valid_sink_payload_we; +wire litedramcore_bankmachine6_pipe_valid_sink_ready; +wire litedramcore_bankmachine6_pipe_valid_sink_valid; +reg litedramcore_bankmachine6_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine6_pipe_valid_source_last = 1'd0; +reg [21:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 22'd0; +reg litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; +wire litedramcore_bankmachine6_pipe_valid_source_ready; +reg litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; +reg [3:0] litedramcore_bankmachine6_produce = 4'd0; +wire [3:0] litedramcore_bankmachine6_rdport_adr; +wire [24:0] litedramcore_bankmachine6_rdport_dat_r; +reg litedramcore_bankmachine6_refresh_gnt = 1'd0; +wire litedramcore_bankmachine6_refresh_req; +reg litedramcore_bankmachine6_replace = 1'd0; +wire [21:0] litedramcore_bankmachine6_req_addr; +wire litedramcore_bankmachine6_req_lock; +reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine6_req_ready; +wire litedramcore_bankmachine6_req_valid; +reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; +wire litedramcore_bankmachine6_req_we; +reg [14:0] litedramcore_bankmachine6_row = 15'd0; +reg litedramcore_bankmachine6_row_close = 1'd0; +reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine6_row_hit; +reg litedramcore_bankmachine6_row_open = 1'd0; +reg litedramcore_bankmachine6_row_opened = 1'd0; +reg litedramcore_bankmachine6_sink_first = 1'd0; +reg litedramcore_bankmachine6_sink_last = 1'd0; +wire [21:0] litedramcore_bankmachine6_sink_payload_addr; +wire litedramcore_bankmachine6_sink_payload_we; +wire litedramcore_bankmachine6_sink_ready; +wire litedramcore_bankmachine6_sink_sink_first; +wire litedramcore_bankmachine6_sink_sink_last; +wire [21:0] litedramcore_bankmachine6_sink_sink_payload_addr; +wire litedramcore_bankmachine6_sink_sink_payload_we; +wire litedramcore_bankmachine6_sink_sink_ready; +wire litedramcore_bankmachine6_sink_sink_valid; +wire litedramcore_bankmachine6_sink_valid; +wire litedramcore_bankmachine6_source_first; +wire litedramcore_bankmachine6_source_last; +wire [21:0] litedramcore_bankmachine6_source_payload_addr; +wire litedramcore_bankmachine6_source_payload_we; +wire litedramcore_bankmachine6_source_ready; +wire litedramcore_bankmachine6_source_source_first; +wire litedramcore_bankmachine6_source_source_last; +wire [21:0] litedramcore_bankmachine6_source_source_payload_addr; +wire litedramcore_bankmachine6_source_source_payload_we; +wire litedramcore_bankmachine6_source_source_ready; +wire litedramcore_bankmachine6_source_source_valid; +wire litedramcore_bankmachine6_source_valid; +reg [2:0] litedramcore_bankmachine6_state = 3'd0; +wire [24:0] litedramcore_bankmachine6_syncfifo6_din; +wire [24:0] litedramcore_bankmachine6_syncfifo6_dout; +wire litedramcore_bankmachine6_syncfifo6_re; +wire litedramcore_bankmachine6_syncfifo6_readable; +wire litedramcore_bankmachine6_syncfifo6_we; +wire litedramcore_bankmachine6_syncfifo6_writable; +reg [1:0] litedramcore_bankmachine6_trascon_count = 2'd0; +reg litedramcore_bankmachine6_trascon_ready = 1'd0; +wire litedramcore_bankmachine6_trascon_valid; +reg [1:0] litedramcore_bankmachine6_trccon_count = 2'd0; +reg litedramcore_bankmachine6_trccon_ready = 1'd0; +wire litedramcore_bankmachine6_trccon_valid; +reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; +reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; +wire litedramcore_bankmachine6_twtpcon_valid; +reg [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine6_wrport_dat_r; +wire [24:0] litedramcore_bankmachine6_wrport_dat_w; +wire litedramcore_bankmachine6_wrport_we; +reg litedramcore_bankmachine7_auto_precharge = 1'd0; +reg [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; +reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine7_cmd_ready = 1'd0; +reg litedramcore_bankmachine7_cmd_valid = 1'd0; +reg [3:0] litedramcore_bankmachine7_consume = 4'd0; +wire litedramcore_bankmachine7_do_read; +wire litedramcore_bankmachine7_fifo_in_first; +wire litedramcore_bankmachine7_fifo_in_last; +wire [21:0] litedramcore_bankmachine7_fifo_in_payload_addr; +wire litedramcore_bankmachine7_fifo_in_payload_we; +wire litedramcore_bankmachine7_fifo_out_first; +wire litedramcore_bankmachine7_fifo_out_last; +wire [21:0] litedramcore_bankmachine7_fifo_out_payload_addr; +wire litedramcore_bankmachine7_fifo_out_payload_we; +reg [4:0] litedramcore_bankmachine7_level = 5'd0; +reg [2:0] litedramcore_bankmachine7_next_state = 3'd0; +wire litedramcore_bankmachine7_pipe_valid_sink_first; +wire litedramcore_bankmachine7_pipe_valid_sink_last; +wire [21:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr; +wire litedramcore_bankmachine7_pipe_valid_sink_payload_we; +wire litedramcore_bankmachine7_pipe_valid_sink_ready; +wire litedramcore_bankmachine7_pipe_valid_sink_valid; +reg litedramcore_bankmachine7_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine7_pipe_valid_source_last = 1'd0; +reg [21:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 22'd0; +reg litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; +wire litedramcore_bankmachine7_pipe_valid_source_ready; +reg litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; +reg [3:0] litedramcore_bankmachine7_produce = 4'd0; +wire [3:0] litedramcore_bankmachine7_rdport_adr; +wire [24:0] litedramcore_bankmachine7_rdport_dat_r; +reg litedramcore_bankmachine7_refresh_gnt = 1'd0; +wire litedramcore_bankmachine7_refresh_req; +reg litedramcore_bankmachine7_replace = 1'd0; +wire [21:0] litedramcore_bankmachine7_req_addr; +wire litedramcore_bankmachine7_req_lock; +reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine7_req_ready; +wire litedramcore_bankmachine7_req_valid; +reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; +wire litedramcore_bankmachine7_req_we; +reg [14:0] litedramcore_bankmachine7_row = 15'd0; +reg litedramcore_bankmachine7_row_close = 1'd0; +reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine7_row_hit; +reg litedramcore_bankmachine7_row_open = 1'd0; +reg litedramcore_bankmachine7_row_opened = 1'd0; +reg litedramcore_bankmachine7_sink_first = 1'd0; +reg litedramcore_bankmachine7_sink_last = 1'd0; +wire [21:0] litedramcore_bankmachine7_sink_payload_addr; +wire litedramcore_bankmachine7_sink_payload_we; +wire litedramcore_bankmachine7_sink_ready; +wire litedramcore_bankmachine7_sink_sink_first; +wire litedramcore_bankmachine7_sink_sink_last; +wire [21:0] litedramcore_bankmachine7_sink_sink_payload_addr; +wire litedramcore_bankmachine7_sink_sink_payload_we; +wire litedramcore_bankmachine7_sink_sink_ready; +wire litedramcore_bankmachine7_sink_sink_valid; +wire litedramcore_bankmachine7_sink_valid; +wire litedramcore_bankmachine7_source_first; +wire litedramcore_bankmachine7_source_last; +wire [21:0] litedramcore_bankmachine7_source_payload_addr; +wire litedramcore_bankmachine7_source_payload_we; +wire litedramcore_bankmachine7_source_ready; +wire litedramcore_bankmachine7_source_source_first; +wire litedramcore_bankmachine7_source_source_last; +wire [21:0] litedramcore_bankmachine7_source_source_payload_addr; +wire litedramcore_bankmachine7_source_source_payload_we; +wire litedramcore_bankmachine7_source_source_ready; +wire litedramcore_bankmachine7_source_source_valid; +wire litedramcore_bankmachine7_source_valid; +reg [2:0] litedramcore_bankmachine7_state = 3'd0; +wire [24:0] litedramcore_bankmachine7_syncfifo7_din; +wire [24:0] litedramcore_bankmachine7_syncfifo7_dout; +wire litedramcore_bankmachine7_syncfifo7_re; +wire litedramcore_bankmachine7_syncfifo7_readable; +wire litedramcore_bankmachine7_syncfifo7_we; +wire litedramcore_bankmachine7_syncfifo7_writable; +reg [1:0] litedramcore_bankmachine7_trascon_count = 2'd0; +reg litedramcore_bankmachine7_trascon_ready = 1'd0; +wire litedramcore_bankmachine7_trascon_valid; +reg [1:0] litedramcore_bankmachine7_trccon_count = 2'd0; +reg litedramcore_bankmachine7_trccon_ready = 1'd0; +wire litedramcore_bankmachine7_trccon_valid; +reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; +reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; +wire litedramcore_bankmachine7_twtpcon_valid; +reg [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine7_wrport_dat_r; +wire [24:0] litedramcore_bankmachine7_wrport_dat_w; +wire litedramcore_bankmachine7_wrport_we; +wire litedramcore_cas_allowed; +wire litedramcore_choose_cmd_ce; +wire [14:0] litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; +reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +wire litedramcore_choose_cmd_cmd_payload_is_cmd; +wire litedramcore_choose_cmd_cmd_payload_is_read; +wire litedramcore_choose_cmd_cmd_payload_is_write; +reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; +reg litedramcore_choose_cmd_cmd_ready = 1'd0; +wire litedramcore_choose_cmd_cmd_valid; +reg [2:0] litedramcore_choose_cmd_grant = 3'd0; +wire [7:0] litedramcore_choose_cmd_request; +reg [7:0] litedramcore_choose_cmd_valids = 8'd0; +reg litedramcore_choose_cmd_want_activates = 1'd0; +reg litedramcore_choose_cmd_want_cmds = 1'd0; +reg litedramcore_choose_cmd_want_reads = 1'd0; +reg litedramcore_choose_cmd_want_writes = 1'd0; +wire litedramcore_choose_req_ce; +wire [14:0] litedramcore_choose_req_cmd_payload_a; +wire [2:0] litedramcore_choose_req_cmd_payload_ba; +reg litedramcore_choose_req_cmd_payload_cas = 1'd0; +wire litedramcore_choose_req_cmd_payload_is_cmd; +wire litedramcore_choose_req_cmd_payload_is_read; +wire litedramcore_choose_req_cmd_payload_is_write; +reg litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg litedramcore_choose_req_cmd_payload_we = 1'd0; +reg litedramcore_choose_req_cmd_ready = 1'd0; +wire litedramcore_choose_req_cmd_valid; +reg [2:0] litedramcore_choose_req_grant = 3'd0; +wire [7:0] litedramcore_choose_req_request; +reg [7:0] litedramcore_choose_req_valids = 8'd0; +reg litedramcore_choose_req_want_activates = 1'd0; +reg litedramcore_choose_req_want_cmds = 1'd0; +reg litedramcore_choose_req_want_reads = 1'd0; +reg litedramcore_choose_req_want_writes = 1'd0; +wire litedramcore_cke; +reg litedramcore_cmd_last = 1'd0; +reg [14:0] litedramcore_cmd_payload_a = 15'd0; +reg [2:0] litedramcore_cmd_payload_ba = 3'd0; +reg litedramcore_cmd_payload_cas = 1'd0; +reg litedramcore_cmd_payload_is_read = 1'd0; +reg litedramcore_cmd_payload_is_write = 1'd0; +reg litedramcore_cmd_payload_ras = 1'd0; +reg litedramcore_cmd_payload_we = 1'd0; +reg litedramcore_cmd_ready = 1'd0; +reg litedramcore_cmd_valid = 1'd0; +reg litedramcore_csr_dfi_p0_act_n = 1'd1; +wire [14:0] litedramcore_csr_dfi_p0_address; +wire [2:0] litedramcore_csr_dfi_p0_bank; +reg litedramcore_csr_dfi_p0_cas_n = 1'd1; +reg litedramcore_csr_dfi_p0_cke = 1'd0; +reg litedramcore_csr_dfi_p0_cs_n = 1'd1; +reg litedramcore_csr_dfi_p0_odt = 1'd0; +reg litedramcore_csr_dfi_p0_ras_n = 1'd1; +reg [63:0] litedramcore_csr_dfi_p0_rddata = 64'd0; +wire litedramcore_csr_dfi_p0_rddata_en; +reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0; +wire litedramcore_csr_dfi_p0_reset_n; +reg litedramcore_csr_dfi_p0_we_n = 1'd1; +wire [63:0] litedramcore_csr_dfi_p0_wrdata; +wire litedramcore_csr_dfi_p0_wrdata_en; +wire [7:0] litedramcore_csr_dfi_p0_wrdata_mask; +reg litedramcore_csr_dfi_p1_act_n = 1'd1; +wire [14:0] litedramcore_csr_dfi_p1_address; +wire [2:0] litedramcore_csr_dfi_p1_bank; +reg litedramcore_csr_dfi_p1_cas_n = 1'd1; +reg litedramcore_csr_dfi_p1_cke = 1'd0; +reg litedramcore_csr_dfi_p1_cs_n = 1'd1; +reg litedramcore_csr_dfi_p1_odt = 1'd0; +reg litedramcore_csr_dfi_p1_ras_n = 1'd1; +reg [63:0] litedramcore_csr_dfi_p1_rddata = 64'd0; +wire litedramcore_csr_dfi_p1_rddata_en; +reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0; +wire litedramcore_csr_dfi_p1_reset_n; +reg litedramcore_csr_dfi_p1_we_n = 1'd1; +wire [63:0] litedramcore_csr_dfi_p1_wrdata; +wire litedramcore_csr_dfi_p1_wrdata_en; +wire [7:0] litedramcore_csr_dfi_p1_wrdata_mask; +reg litedramcore_dfi_p0_act_n = 1'd1; +reg [14:0] litedramcore_dfi_p0_address = 15'd0; +reg [2:0] litedramcore_dfi_p0_bank = 3'd0; +reg litedramcore_dfi_p0_cas_n = 1'd1; +wire litedramcore_dfi_p0_cke; +reg litedramcore_dfi_p0_cs_n = 1'd1; +wire litedramcore_dfi_p0_odt; +reg litedramcore_dfi_p0_ras_n = 1'd1; +wire [63:0] litedramcore_dfi_p0_rddata; +reg litedramcore_dfi_p0_rddata_en = 1'd0; +wire litedramcore_dfi_p0_rddata_valid; +wire litedramcore_dfi_p0_reset_n; +reg litedramcore_dfi_p0_we_n = 1'd1; +wire [63:0] litedramcore_dfi_p0_wrdata; +reg litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [7:0] litedramcore_dfi_p0_wrdata_mask; +reg litedramcore_dfi_p1_act_n = 1'd1; +reg [14:0] litedramcore_dfi_p1_address = 15'd0; +reg [2:0] litedramcore_dfi_p1_bank = 3'd0; +reg litedramcore_dfi_p1_cas_n = 1'd1; +wire litedramcore_dfi_p1_cke; +reg litedramcore_dfi_p1_cs_n = 1'd1; +wire litedramcore_dfi_p1_odt; +reg litedramcore_dfi_p1_ras_n = 1'd1; +wire [63:0] litedramcore_dfi_p1_rddata; +reg litedramcore_dfi_p1_rddata_en = 1'd0; +wire litedramcore_dfi_p1_rddata_valid; +wire litedramcore_dfi_p1_reset_n; +reg litedramcore_dfi_p1_we_n = 1'd1; +wire [63:0] litedramcore_dfi_p1_wrdata; +reg litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [7:0] litedramcore_dfi_p1_wrdata_mask; +reg litedramcore_en0 = 1'd0; +reg litedramcore_en1 = 1'd0; +reg litedramcore_ext_dfi_p0_act_n = 1'd1; +reg [14:0] litedramcore_ext_dfi_p0_address = 15'd0; +reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0; +reg litedramcore_ext_dfi_p0_cas_n = 1'd1; +reg litedramcore_ext_dfi_p0_cke = 1'd0; +reg litedramcore_ext_dfi_p0_cs_n = 1'd1; +reg litedramcore_ext_dfi_p0_odt = 1'd0; +reg litedramcore_ext_dfi_p0_ras_n = 1'd1; +reg [63:0] litedramcore_ext_dfi_p0_rddata = 64'd0; +reg litedramcore_ext_dfi_p0_rddata_en = 1'd0; +reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0; +reg litedramcore_ext_dfi_p0_reset_n = 1'd0; +reg litedramcore_ext_dfi_p0_we_n = 1'd1; +reg [63:0] litedramcore_ext_dfi_p0_wrdata = 64'd0; +reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0; +reg [7:0] litedramcore_ext_dfi_p0_wrdata_mask = 8'd0; +reg litedramcore_ext_dfi_p1_act_n = 1'd1; +reg [14:0] litedramcore_ext_dfi_p1_address = 15'd0; +reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0; +reg litedramcore_ext_dfi_p1_cas_n = 1'd1; +reg litedramcore_ext_dfi_p1_cke = 1'd0; +reg litedramcore_ext_dfi_p1_cs_n = 1'd1; +reg litedramcore_ext_dfi_p1_odt = 1'd0; +reg litedramcore_ext_dfi_p1_ras_n = 1'd1; +reg [63:0] litedramcore_ext_dfi_p1_rddata = 64'd0; +reg litedramcore_ext_dfi_p1_rddata_en = 1'd0; +reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0; +reg litedramcore_ext_dfi_p1_reset_n = 1'd0; +reg litedramcore_ext_dfi_p1_we_n = 1'd1; +reg [63:0] litedramcore_ext_dfi_p1_wrdata = 64'd0; +reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0; +reg [7:0] litedramcore_ext_dfi_p1_wrdata_mask = 8'd0; +reg litedramcore_ext_dfi_sel = 1'd0; +wire litedramcore_go_to_refresh; +wire [21:0] litedramcore_interface_bank0_addr; +wire litedramcore_interface_bank0_lock; +wire litedramcore_interface_bank0_rdata_valid; +wire litedramcore_interface_bank0_ready; +wire litedramcore_interface_bank0_valid; +wire litedramcore_interface_bank0_wdata_ready; +wire litedramcore_interface_bank0_we; +wire [21:0] litedramcore_interface_bank1_addr; +wire litedramcore_interface_bank1_lock; +wire litedramcore_interface_bank1_rdata_valid; +wire litedramcore_interface_bank1_ready; +wire litedramcore_interface_bank1_valid; +wire litedramcore_interface_bank1_wdata_ready; +wire litedramcore_interface_bank1_we; +wire [21:0] litedramcore_interface_bank2_addr; +wire litedramcore_interface_bank2_lock; +wire litedramcore_interface_bank2_rdata_valid; +wire litedramcore_interface_bank2_ready; +wire litedramcore_interface_bank2_valid; +wire litedramcore_interface_bank2_wdata_ready; +wire litedramcore_interface_bank2_we; +wire [21:0] litedramcore_interface_bank3_addr; +wire litedramcore_interface_bank3_lock; +wire litedramcore_interface_bank3_rdata_valid; +wire litedramcore_interface_bank3_ready; +wire litedramcore_interface_bank3_valid; +wire litedramcore_interface_bank3_wdata_ready; +wire litedramcore_interface_bank3_we; +wire [21:0] litedramcore_interface_bank4_addr; +wire litedramcore_interface_bank4_lock; +wire litedramcore_interface_bank4_rdata_valid; +wire litedramcore_interface_bank4_ready; +wire litedramcore_interface_bank4_valid; +wire litedramcore_interface_bank4_wdata_ready; +wire litedramcore_interface_bank4_we; +wire [21:0] litedramcore_interface_bank5_addr; +wire litedramcore_interface_bank5_lock; +wire litedramcore_interface_bank5_rdata_valid; +wire litedramcore_interface_bank5_ready; +wire litedramcore_interface_bank5_valid; +wire litedramcore_interface_bank5_wdata_ready; +wire litedramcore_interface_bank5_we; +wire [21:0] litedramcore_interface_bank6_addr; +wire litedramcore_interface_bank6_lock; +wire litedramcore_interface_bank6_rdata_valid; +wire litedramcore_interface_bank6_ready; +wire litedramcore_interface_bank6_valid; +wire litedramcore_interface_bank6_wdata_ready; +wire litedramcore_interface_bank6_we; +wire [21:0] litedramcore_interface_bank7_addr; +wire litedramcore_interface_bank7_lock; +wire litedramcore_interface_bank7_rdata_valid; +wire litedramcore_interface_bank7_ready; +wire litedramcore_interface_bank7_valid; +wire litedramcore_interface_bank7_wdata_ready; +wire litedramcore_interface_bank7_we; +wire [127:0] litedramcore_interface_rdata; +reg [127:0] litedramcore_interface_wdata = 128'd0; +reg [15:0] litedramcore_interface_wdata_we = 16'd0; +reg litedramcore_locked0 = 1'd0; +reg litedramcore_locked1 = 1'd0; +reg litedramcore_locked2 = 1'd0; +reg litedramcore_locked3 = 1'd0; +reg litedramcore_locked4 = 1'd0; +reg litedramcore_locked5 = 1'd0; +reg litedramcore_locked6 = 1'd0; +reg litedramcore_locked7 = 1'd0; +reg litedramcore_master_p0_act_n = 1'd1; +reg [14:0] litedramcore_master_p0_address = 15'd0; +reg [2:0] litedramcore_master_p0_bank = 3'd0; +reg litedramcore_master_p0_cas_n = 1'd1; +reg litedramcore_master_p0_cke = 1'd0; +reg litedramcore_master_p0_cs_n = 1'd1; +reg litedramcore_master_p0_odt = 1'd0; +reg litedramcore_master_p0_ras_n = 1'd1; +wire [63:0] litedramcore_master_p0_rddata; +reg litedramcore_master_p0_rddata_en = 1'd0; +wire litedramcore_master_p0_rddata_valid; +reg litedramcore_master_p0_reset_n = 1'd0; +reg litedramcore_master_p0_we_n = 1'd1; +reg [63:0] litedramcore_master_p0_wrdata = 64'd0; +reg litedramcore_master_p0_wrdata_en = 1'd0; +reg [7:0] litedramcore_master_p0_wrdata_mask = 8'd0; +reg litedramcore_master_p1_act_n = 1'd1; +reg [14:0] litedramcore_master_p1_address = 15'd0; +reg [2:0] litedramcore_master_p1_bank = 3'd0; +reg litedramcore_master_p1_cas_n = 1'd1; +reg litedramcore_master_p1_cke = 1'd0; +reg litedramcore_master_p1_cs_n = 1'd1; +reg litedramcore_master_p1_odt = 1'd0; +reg litedramcore_master_p1_ras_n = 1'd1; +wire [63:0] litedramcore_master_p1_rddata; +reg litedramcore_master_p1_rddata_en = 1'd0; +wire litedramcore_master_p1_rddata_valid; +reg litedramcore_master_p1_reset_n = 1'd0; +reg litedramcore_master_p1_we_n = 1'd1; +reg [63:0] litedramcore_master_p1_wrdata = 64'd0; +reg litedramcore_master_p1_wrdata_en = 1'd0; +reg [7:0] litedramcore_master_p1_wrdata_mask = 8'd0; +wire litedramcore_max_time0; +wire litedramcore_max_time1; +reg [3:0] litedramcore_multiplexer_next_state = 4'd0; +reg [3:0] litedramcore_multiplexer_state = 4'd0; +reg litedramcore_new_master_rdata_valid0 = 1'd0; +reg litedramcore_new_master_rdata_valid1 = 1'd0; +reg litedramcore_new_master_rdata_valid10 = 1'd0; +reg litedramcore_new_master_rdata_valid11 = 1'd0; +reg litedramcore_new_master_rdata_valid12 = 1'd0; +reg litedramcore_new_master_rdata_valid13 = 1'd0; +reg litedramcore_new_master_rdata_valid2 = 1'd0; +reg litedramcore_new_master_rdata_valid3 = 1'd0; +reg litedramcore_new_master_rdata_valid4 = 1'd0; +reg litedramcore_new_master_rdata_valid5 = 1'd0; +reg litedramcore_new_master_rdata_valid6 = 1'd0; +reg litedramcore_new_master_rdata_valid7 = 1'd0; +reg litedramcore_new_master_rdata_valid8 = 1'd0; +reg litedramcore_new_master_rdata_valid9 = 1'd0; +reg litedramcore_new_master_wdata_ready0 = 1'd0; +reg litedramcore_new_master_wdata_ready1 = 1'd0; +reg litedramcore_new_master_wdata_ready2 = 1'd0; +reg litedramcore_new_master_wdata_ready3 = 1'd0; +reg [14:0] litedramcore_nop_a = 15'd0; +reg [2:0] litedramcore_nop_ba = 3'd0; +wire litedramcore_odt; +reg litedramcore_phaseinjector0_address_re = 1'd0; +reg [14:0] litedramcore_phaseinjector0_address_storage = 15'd0; +reg litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; +wire litedramcore_phaseinjector0_command_issue_r; +reg litedramcore_phaseinjector0_command_issue_re = 1'd0; +reg litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg litedramcore_phaseinjector0_command_re = 1'd0; +reg [7:0] litedramcore_phaseinjector0_command_storage = 8'd0; +wire litedramcore_phaseinjector0_csrfield_cas; +wire litedramcore_phaseinjector0_csrfield_cs; +wire litedramcore_phaseinjector0_csrfield_cs_bottom; +wire litedramcore_phaseinjector0_csrfield_cs_top; +wire litedramcore_phaseinjector0_csrfield_ras; +wire litedramcore_phaseinjector0_csrfield_rden; +wire litedramcore_phaseinjector0_csrfield_we; +wire litedramcore_phaseinjector0_csrfield_wren; +reg litedramcore_phaseinjector0_rddata_re = 1'd0; +reg [63:0] litedramcore_phaseinjector0_rddata_status = 64'd0; +wire litedramcore_phaseinjector0_rddata_we; +reg litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [63:0] litedramcore_phaseinjector0_wrdata_storage = 64'd0; +reg litedramcore_phaseinjector1_address_re = 1'd0; +reg [14:0] litedramcore_phaseinjector1_address_storage = 15'd0; +reg litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; +wire litedramcore_phaseinjector1_command_issue_r; +reg litedramcore_phaseinjector1_command_issue_re = 1'd0; +reg litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg litedramcore_phaseinjector1_command_re = 1'd0; +reg [7:0] litedramcore_phaseinjector1_command_storage = 8'd0; +wire litedramcore_phaseinjector1_csrfield_cas; +wire litedramcore_phaseinjector1_csrfield_cs; +wire litedramcore_phaseinjector1_csrfield_cs_bottom; +wire litedramcore_phaseinjector1_csrfield_cs_top; +wire litedramcore_phaseinjector1_csrfield_ras; +wire litedramcore_phaseinjector1_csrfield_rden; +wire litedramcore_phaseinjector1_csrfield_we; +wire litedramcore_phaseinjector1_csrfield_wren; +reg litedramcore_phaseinjector1_rddata_re = 1'd0; +reg [63:0] litedramcore_phaseinjector1_rddata_status = 64'd0; +wire litedramcore_phaseinjector1_rddata_we; +reg litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [63:0] litedramcore_phaseinjector1_wrdata_storage = 64'd0; +reg litedramcore_postponer_count = 1'd0; +wire litedramcore_postponer_req_i; +reg litedramcore_postponer_req_o = 1'd0; +wire litedramcore_ras_allowed; +reg litedramcore_re = 1'd0; +wire litedramcore_read_available; +reg [1:0] litedramcore_refresher_next_state = 2'd0; +reg [1:0] litedramcore_refresher_state = 2'd0; +wire litedramcore_reset_n; +wire litedramcore_roundrobin0_ce; +wire litedramcore_roundrobin0_grant; +wire litedramcore_roundrobin0_request; +wire litedramcore_roundrobin1_ce; +wire litedramcore_roundrobin1_grant; +wire litedramcore_roundrobin1_request; +wire litedramcore_roundrobin2_ce; +wire litedramcore_roundrobin2_grant; +wire litedramcore_roundrobin2_request; +wire litedramcore_roundrobin3_ce; +wire litedramcore_roundrobin3_grant; +wire litedramcore_roundrobin3_request; +wire litedramcore_roundrobin4_ce; +wire litedramcore_roundrobin4_grant; +wire litedramcore_roundrobin4_request; +wire litedramcore_roundrobin5_ce; +wire litedramcore_roundrobin5_grant; +wire litedramcore_roundrobin5_request; +wire litedramcore_roundrobin6_ce; +wire litedramcore_roundrobin6_grant; +wire litedramcore_roundrobin6_request; +wire litedramcore_roundrobin7_ce; +wire litedramcore_roundrobin7_grant; +wire litedramcore_roundrobin7_request; +wire litedramcore_sel; +reg litedramcore_sequencer_count = 1'd0; +wire litedramcore_sequencer_done0; +reg litedramcore_sequencer_done1 = 1'd0; +reg litedramcore_sequencer_start0 = 1'd0; +wire litedramcore_sequencer_start1; +reg [6:0] litedramcore_sequencer_trigger = 7'd0; +wire litedramcore_slave_p0_act_n; +wire [14:0] litedramcore_slave_p0_address; +wire [2:0] litedramcore_slave_p0_bank; +wire litedramcore_slave_p0_cas_n; +wire litedramcore_slave_p0_cke; +wire litedramcore_slave_p0_cs_n; +wire litedramcore_slave_p0_odt; +wire litedramcore_slave_p0_ras_n; +reg [63:0] litedramcore_slave_p0_rddata = 64'd0; +wire litedramcore_slave_p0_rddata_en; +reg litedramcore_slave_p0_rddata_valid = 1'd0; +wire litedramcore_slave_p0_reset_n; +wire litedramcore_slave_p0_we_n; +wire [63:0] litedramcore_slave_p0_wrdata; +wire litedramcore_slave_p0_wrdata_en; +wire [7:0] litedramcore_slave_p0_wrdata_mask; +wire litedramcore_slave_p1_act_n; +wire [14:0] litedramcore_slave_p1_address; +wire [2:0] litedramcore_slave_p1_bank; +wire litedramcore_slave_p1_cas_n; +wire litedramcore_slave_p1_cke; +wire litedramcore_slave_p1_cs_n; +wire litedramcore_slave_p1_odt; +wire litedramcore_slave_p1_ras_n; +reg [63:0] litedramcore_slave_p1_rddata = 64'd0; +wire litedramcore_slave_p1_rddata_en; +reg litedramcore_slave_p1_rddata_valid = 1'd0; +wire litedramcore_slave_p1_reset_n; +wire litedramcore_slave_p1_we_n; +wire [63:0] litedramcore_slave_p1_wrdata; +wire litedramcore_slave_p1_wrdata_en; +wire [7:0] litedramcore_slave_p1_wrdata_mask; +reg [1:0] litedramcore_steerer0 = 2'd0; +reg [1:0] litedramcore_steerer1 = 2'd0; +reg litedramcore_steerer2 = 1'd1; +reg litedramcore_steerer3 = 1'd1; +reg litedramcore_steerer4 = 1'd1; +reg litedramcore_steerer5 = 1'd1; +reg [3:0] litedramcore_storage = 4'd1; +reg litedramcore_tccdcon_count = 1'd0; +reg litedramcore_tccdcon_ready = 1'd0; +wire litedramcore_tccdcon_valid; +wire [1:0] litedramcore_tfawcon_count; +reg litedramcore_tfawcon_ready = 1'd1; +wire litedramcore_tfawcon_valid; +reg [2:0] litedramcore_tfawcon_window = 3'd0; +reg [4:0] litedramcore_time0 = 5'd0; +reg [3:0] litedramcore_time1 = 4'd0; +wire [8:0] litedramcore_timer_count0; +reg [8:0] litedramcore_timer_count1 = 9'd390; +wire litedramcore_timer_done0; +wire litedramcore_timer_done1; +wire litedramcore_timer_wait; +reg litedramcore_trrdcon_count = 1'd0; +reg litedramcore_trrdcon_ready = 1'd0; +wire litedramcore_trrdcon_valid; +reg [2:0] litedramcore_twtrcon_count = 3'd0; +reg litedramcore_twtrcon_ready = 1'd0; +wire litedramcore_twtrcon_valid; +wire litedramcore_wants_refresh; +wire litedramcore_wants_zqcs; +wire litedramcore_write_available; +reg litedramcore_zqcs_executer_done = 1'd0; +reg litedramcore_zqcs_executer_start = 1'd0; +reg [5:0] litedramcore_zqcs_executer_trigger = 6'd0; +wire [25:0] litedramcore_zqcs_timer_count0; +reg [25:0] litedramcore_zqcs_timer_count1 = 26'd49999999; +wire litedramcore_zqcs_timer_done0; +wire litedramcore_zqcs_timer_done1; +wire litedramcore_zqcs_timer_wait; +wire litedramecp5ddrphycrg_ecp5pll; +wire litedramecp5ddrphycrg_locked; +reg multiregimpl0 = 1'd0; +reg multiregimpl1 = 1'd0; +reg [1:0] next_state = 2'd0; +wire por_clk; +reg rhs_self0 = 1'd0; +reg [14:0] rhs_self1 = 15'd0; +reg rhs_self10 = 1'd0; +reg rhs_self11 = 1'd0; +reg [21:0] rhs_self12 = 22'd0; +reg rhs_self13 = 1'd0; +reg rhs_self14 = 1'd0; +reg [21:0] rhs_self15 = 22'd0; +reg rhs_self16 = 1'd0; +reg rhs_self17 = 1'd0; +reg [21:0] rhs_self18 = 22'd0; +reg rhs_self19 = 1'd0; +reg [2:0] rhs_self2 = 3'd0; +reg rhs_self20 = 1'd0; +reg [21:0] rhs_self21 = 22'd0; +reg rhs_self22 = 1'd0; +reg rhs_self23 = 1'd0; +reg [21:0] rhs_self24 = 22'd0; +reg rhs_self25 = 1'd0; +reg rhs_self26 = 1'd0; +reg [21:0] rhs_self27 = 22'd0; +reg rhs_self28 = 1'd0; +reg rhs_self29 = 1'd0; +reg rhs_self3 = 1'd0; +reg [21:0] rhs_self30 = 22'd0; +reg rhs_self31 = 1'd0; +reg rhs_self32 = 1'd0; +reg [21:0] rhs_self33 = 22'd0; +reg rhs_self34 = 1'd0; +reg rhs_self35 = 1'd0; +reg rhs_self4 = 1'd0; +reg rhs_self5 = 1'd0; +reg rhs_self6 = 1'd0; +reg [14:0] rhs_self7 = 15'd0; +reg [2:0] rhs_self8 = 3'd0; +reg rhs_self9 = 1'd0; +reg [2:0] self0 = 3'd0; +reg [14:0] self1 = 15'd0; +reg self10 = 1'd0; +reg self11 = 1'd0; +reg self12 = 1'd0; +reg self13 = 1'd0; +reg self2 = 1'd0; +reg self3 = 1'd0; +reg self4 = 1'd0; +reg self5 = 1'd0; +reg self6 = 1'd0; +reg [2:0] self7 = 3'd0; +reg [14:0] self8 = 15'd0; +reg self9 = 1'd0; +reg [1:0] state = 2'd0; +wire sys2x_clk; +wire sys2x_i_clk; +wire sys2x_rst; +wire sys_clk; +wire sys_rst; +reg t_self0 = 1'd0; +reg t_self1 = 1'd0; +reg t_self2 = 1'd0; +reg t_self3 = 1'd0; +reg t_self4 = 1'd0; +reg t_self5 = 1'd0; +wire user_enable; +wire [24:0] user_port_cmd_payload_addr; +wire user_port_cmd_payload_we; +wire user_port_cmd_ready; +wire user_port_cmd_valid; +wire [127:0] user_port_rdata_payload_data; +wire user_port_rdata_ready; +wire user_port_rdata_valid; +wire [127:0] user_port_wdata_payload_data; +wire [15:0] user_port_wdata_payload_we; +wire user_port_wdata_ready; +wire user_port_wdata_valid; +wire wb_bus_ack; +wire [29:0] wb_bus_adr; +wire [1:0] wb_bus_bte; +wire [2:0] wb_bus_cti; +wire wb_bus_cyc; +wire [31:0] wb_bus_dat_r; +wire [31:0] wb_bus_dat_w; +wire wb_bus_err; +wire [3:0] wb_bus_sel; +wire wb_bus_stb; +wire wb_bus_we; +wire we; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + +assign crg_stop = ddrphy_stop0; +assign crg_reset0 = ddrphy_reset0; +assign init_done = init_done_storage; +assign init_error = init_error_storage; +assign wb_bus_adr = wb_ctrl_adr; +assign wb_bus_dat_w = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = wb_bus_dat_r; +assign wb_bus_sel = wb_ctrl_sel; +assign wb_bus_cyc = wb_ctrl_cyc; +assign wb_bus_stb = wb_ctrl_stb; +assign wb_ctrl_ack = wb_bus_ack; +assign wb_bus_we = wb_ctrl_we; +assign wb_bus_cti = wb_ctrl_cti; +assign wb_bus_bte = wb_ctrl_bte; +assign wb_ctrl_err = wb_bus_err; +assign user_clk = sys_clk; +assign user_rst = sys_rst; +assign user_enable = 1'd1; +assign user_port_cmd_valid = (user_port_native_0_cmd_valid & user_enable); +assign user_port_native_0_cmd_ready = (user_port_cmd_ready & user_enable); +assign user_port_cmd_payload_we = user_port_native_0_cmd_we; +assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr; +assign user_port_wdata_valid = (user_port_native_0_wdata_valid & user_enable); +assign user_port_native_0_wdata_ready = (user_port_wdata_ready & user_enable); +assign user_port_wdata_payload_we = user_port_native_0_wdata_we; +assign user_port_wdata_payload_data = user_port_native_0_wdata_data; +assign user_port_native_0_rdata_valid = (user_port_rdata_valid & user_enable); +assign user_port_rdata_ready = (user_port_native_0_rdata_ready & user_enable); +assign user_port_native_0_rdata_data = user_port_rdata_payload_data; +assign interface0_adr = wb_bus_adr; +assign interface0_dat_w = wb_bus_dat_w; +assign wb_bus_dat_r = interface0_dat_r; +assign interface0_sel = wb_bus_sel; +assign interface0_cyc = wb_bus_cyc; +assign interface0_stb = wb_bus_stb; +assign wb_bus_ack = interface0_ack; +assign interface0_we = wb_bus_we; +assign interface0_cti = wb_bus_cti; +assign interface0_bte = wb_bus_bte; +assign wb_bus_err = interface0_err; +assign por_clk = clk; +assign crg_por_done = (crg_por_count == 1'd0); +assign crg_reset1 = (((~crg_por_done) | rst) | crg_rst); +assign pll_locked = crg_locked; +assign crg_clkin = clk; +assign sys2x_i_clk = crg_clkout0; +assign init_clk = crg_clkout1; +assign crg_locked = (litedramecp5ddrphycrg_locked & (~crg_reset1)); +always @(*) begin + ddrphy_dm_o_data0 <= 8'd0; + ddrphy_dm_o_data0[0] <= ddrphy_dfi_p0_wrdata_mask[0]; + ddrphy_dm_o_data0[1] <= ddrphy_dfi_p0_wrdata_mask[2]; + ddrphy_dm_o_data0[2] <= ddrphy_dfi_p0_wrdata_mask[4]; + ddrphy_dm_o_data0[3] <= ddrphy_dfi_p0_wrdata_mask[6]; + ddrphy_dm_o_data0[4] <= ddrphy_dfi_p1_wrdata_mask[0]; + ddrphy_dm_o_data0[5] <= ddrphy_dfi_p1_wrdata_mask[2]; + ddrphy_dm_o_data0[6] <= ddrphy_dfi_p1_wrdata_mask[4]; + ddrphy_dm_o_data0[7] <= ddrphy_dfi_p1_wrdata_mask[6]; +end +always @(*) begin + ddrphy_dq_o_data0 <= 8'd0; + ddrphy_dq_o_data0[0] <= ddrphy_dfi_p0_wrdata[0]; + ddrphy_dq_o_data0[1] <= ddrphy_dfi_p0_wrdata[16]; + ddrphy_dq_o_data0[2] <= ddrphy_dfi_p0_wrdata[32]; + ddrphy_dq_o_data0[3] <= ddrphy_dfi_p0_wrdata[48]; + ddrphy_dq_o_data0[4] <= ddrphy_dfi_p1_wrdata[0]; + ddrphy_dq_o_data0[5] <= ddrphy_dfi_p1_wrdata[16]; + ddrphy_dq_o_data0[6] <= ddrphy_dfi_p1_wrdata[32]; + ddrphy_dq_o_data0[7] <= ddrphy_dfi_p1_wrdata[48]; +end +assign ddrphy_dq_i_data0 = {ddrphy_bitslip0_o, ddrphy_dq_i_bitslip_o_d0}; +always @(*) begin + ddrphy_dfi_p0_rddata <= 64'd0; + ddrphy_dfi_p0_rddata[0] <= ddrphy_dq_i_data0[0]; + ddrphy_dfi_p0_rddata[16] <= ddrphy_dq_i_data0[1]; + ddrphy_dfi_p0_rddata[32] <= ddrphy_dq_i_data0[2]; + ddrphy_dfi_p0_rddata[48] <= ddrphy_dq_i_data0[3]; + ddrphy_dfi_p0_rddata[1] <= ddrphy_dq_i_data1[0]; + ddrphy_dfi_p0_rddata[17] <= ddrphy_dq_i_data1[1]; + ddrphy_dfi_p0_rddata[33] <= ddrphy_dq_i_data1[2]; + ddrphy_dfi_p0_rddata[49] <= ddrphy_dq_i_data1[3]; + ddrphy_dfi_p0_rddata[2] <= ddrphy_dq_i_data2[0]; + ddrphy_dfi_p0_rddata[18] <= ddrphy_dq_i_data2[1]; + ddrphy_dfi_p0_rddata[34] <= ddrphy_dq_i_data2[2]; + ddrphy_dfi_p0_rddata[50] <= ddrphy_dq_i_data2[3]; + ddrphy_dfi_p0_rddata[3] <= ddrphy_dq_i_data3[0]; + ddrphy_dfi_p0_rddata[19] <= ddrphy_dq_i_data3[1]; + ddrphy_dfi_p0_rddata[35] <= ddrphy_dq_i_data3[2]; + ddrphy_dfi_p0_rddata[51] <= ddrphy_dq_i_data3[3]; + ddrphy_dfi_p0_rddata[4] <= ddrphy_dq_i_data4[0]; + ddrphy_dfi_p0_rddata[20] <= ddrphy_dq_i_data4[1]; + ddrphy_dfi_p0_rddata[36] <= ddrphy_dq_i_data4[2]; + ddrphy_dfi_p0_rddata[52] <= ddrphy_dq_i_data4[3]; + ddrphy_dfi_p0_rddata[5] <= ddrphy_dq_i_data5[0]; + ddrphy_dfi_p0_rddata[21] <= ddrphy_dq_i_data5[1]; + ddrphy_dfi_p0_rddata[37] <= ddrphy_dq_i_data5[2]; + ddrphy_dfi_p0_rddata[53] <= ddrphy_dq_i_data5[3]; + ddrphy_dfi_p0_rddata[6] <= ddrphy_dq_i_data6[0]; + ddrphy_dfi_p0_rddata[22] <= ddrphy_dq_i_data6[1]; + ddrphy_dfi_p0_rddata[38] <= ddrphy_dq_i_data6[2]; + ddrphy_dfi_p0_rddata[54] <= ddrphy_dq_i_data6[3]; + ddrphy_dfi_p0_rddata[7] <= ddrphy_dq_i_data7[0]; + ddrphy_dfi_p0_rddata[23] <= ddrphy_dq_i_data7[1]; + ddrphy_dfi_p0_rddata[39] <= ddrphy_dq_i_data7[2]; + ddrphy_dfi_p0_rddata[55] <= ddrphy_dq_i_data7[3]; + ddrphy_dfi_p0_rddata[8] <= ddrphy_dq_i_data8[0]; + ddrphy_dfi_p0_rddata[24] <= ddrphy_dq_i_data8[1]; + ddrphy_dfi_p0_rddata[40] <= ddrphy_dq_i_data8[2]; + ddrphy_dfi_p0_rddata[56] <= ddrphy_dq_i_data8[3]; + ddrphy_dfi_p0_rddata[9] <= ddrphy_dq_i_data9[0]; + ddrphy_dfi_p0_rddata[25] <= ddrphy_dq_i_data9[1]; + ddrphy_dfi_p0_rddata[41] <= ddrphy_dq_i_data9[2]; + ddrphy_dfi_p0_rddata[57] <= ddrphy_dq_i_data9[3]; + ddrphy_dfi_p0_rddata[10] <= ddrphy_dq_i_data10[0]; + ddrphy_dfi_p0_rddata[26] <= ddrphy_dq_i_data10[1]; + ddrphy_dfi_p0_rddata[42] <= ddrphy_dq_i_data10[2]; + ddrphy_dfi_p0_rddata[58] <= ddrphy_dq_i_data10[3]; + ddrphy_dfi_p0_rddata[11] <= ddrphy_dq_i_data11[0]; + ddrphy_dfi_p0_rddata[27] <= ddrphy_dq_i_data11[1]; + ddrphy_dfi_p0_rddata[43] <= ddrphy_dq_i_data11[2]; + ddrphy_dfi_p0_rddata[59] <= ddrphy_dq_i_data11[3]; + ddrphy_dfi_p0_rddata[12] <= ddrphy_dq_i_data12[0]; + ddrphy_dfi_p0_rddata[28] <= ddrphy_dq_i_data12[1]; + ddrphy_dfi_p0_rddata[44] <= ddrphy_dq_i_data12[2]; + ddrphy_dfi_p0_rddata[60] <= ddrphy_dq_i_data12[3]; + ddrphy_dfi_p0_rddata[13] <= ddrphy_dq_i_data13[0]; + ddrphy_dfi_p0_rddata[29] <= ddrphy_dq_i_data13[1]; + ddrphy_dfi_p0_rddata[45] <= ddrphy_dq_i_data13[2]; + ddrphy_dfi_p0_rddata[61] <= ddrphy_dq_i_data13[3]; + ddrphy_dfi_p0_rddata[14] <= ddrphy_dq_i_data14[0]; + ddrphy_dfi_p0_rddata[30] <= ddrphy_dq_i_data14[1]; + ddrphy_dfi_p0_rddata[46] <= ddrphy_dq_i_data14[2]; + ddrphy_dfi_p0_rddata[62] <= ddrphy_dq_i_data14[3]; + ddrphy_dfi_p0_rddata[15] <= ddrphy_dq_i_data15[0]; + ddrphy_dfi_p0_rddata[31] <= ddrphy_dq_i_data15[1]; + ddrphy_dfi_p0_rddata[47] <= ddrphy_dq_i_data15[2]; + ddrphy_dfi_p0_rddata[63] <= ddrphy_dq_i_data15[3]; +end +always @(*) begin + ddrphy_dfi_p1_rddata <= 64'd0; + ddrphy_dfi_p1_rddata[0] <= ddrphy_dq_i_data0[4]; + ddrphy_dfi_p1_rddata[16] <= ddrphy_dq_i_data0[5]; + ddrphy_dfi_p1_rddata[32] <= ddrphy_dq_i_data0[6]; + ddrphy_dfi_p1_rddata[48] <= ddrphy_dq_i_data0[7]; + ddrphy_dfi_p1_rddata[1] <= ddrphy_dq_i_data1[4]; + ddrphy_dfi_p1_rddata[17] <= ddrphy_dq_i_data1[5]; + ddrphy_dfi_p1_rddata[33] <= ddrphy_dq_i_data1[6]; + ddrphy_dfi_p1_rddata[49] <= ddrphy_dq_i_data1[7]; + ddrphy_dfi_p1_rddata[2] <= ddrphy_dq_i_data2[4]; + ddrphy_dfi_p1_rddata[18] <= ddrphy_dq_i_data2[5]; + ddrphy_dfi_p1_rddata[34] <= ddrphy_dq_i_data2[6]; + ddrphy_dfi_p1_rddata[50] <= ddrphy_dq_i_data2[7]; + ddrphy_dfi_p1_rddata[3] <= ddrphy_dq_i_data3[4]; + ddrphy_dfi_p1_rddata[19] <= ddrphy_dq_i_data3[5]; + ddrphy_dfi_p1_rddata[35] <= ddrphy_dq_i_data3[6]; + ddrphy_dfi_p1_rddata[51] <= ddrphy_dq_i_data3[7]; + ddrphy_dfi_p1_rddata[4] <= ddrphy_dq_i_data4[4]; + ddrphy_dfi_p1_rddata[20] <= ddrphy_dq_i_data4[5]; + ddrphy_dfi_p1_rddata[36] <= ddrphy_dq_i_data4[6]; + ddrphy_dfi_p1_rddata[52] <= ddrphy_dq_i_data4[7]; + ddrphy_dfi_p1_rddata[5] <= ddrphy_dq_i_data5[4]; + ddrphy_dfi_p1_rddata[21] <= ddrphy_dq_i_data5[5]; + ddrphy_dfi_p1_rddata[37] <= ddrphy_dq_i_data5[6]; + ddrphy_dfi_p1_rddata[53] <= ddrphy_dq_i_data5[7]; + ddrphy_dfi_p1_rddata[6] <= ddrphy_dq_i_data6[4]; + ddrphy_dfi_p1_rddata[22] <= ddrphy_dq_i_data6[5]; + ddrphy_dfi_p1_rddata[38] <= ddrphy_dq_i_data6[6]; + ddrphy_dfi_p1_rddata[54] <= ddrphy_dq_i_data6[7]; + ddrphy_dfi_p1_rddata[7] <= ddrphy_dq_i_data7[4]; + ddrphy_dfi_p1_rddata[23] <= ddrphy_dq_i_data7[5]; + ddrphy_dfi_p1_rddata[39] <= ddrphy_dq_i_data7[6]; + ddrphy_dfi_p1_rddata[55] <= ddrphy_dq_i_data7[7]; + ddrphy_dfi_p1_rddata[8] <= ddrphy_dq_i_data8[4]; + ddrphy_dfi_p1_rddata[24] <= ddrphy_dq_i_data8[5]; + ddrphy_dfi_p1_rddata[40] <= ddrphy_dq_i_data8[6]; + ddrphy_dfi_p1_rddata[56] <= ddrphy_dq_i_data8[7]; + ddrphy_dfi_p1_rddata[9] <= ddrphy_dq_i_data9[4]; + ddrphy_dfi_p1_rddata[25] <= ddrphy_dq_i_data9[5]; + ddrphy_dfi_p1_rddata[41] <= ddrphy_dq_i_data9[6]; + ddrphy_dfi_p1_rddata[57] <= ddrphy_dq_i_data9[7]; + ddrphy_dfi_p1_rddata[10] <= ddrphy_dq_i_data10[4]; + ddrphy_dfi_p1_rddata[26] <= ddrphy_dq_i_data10[5]; + ddrphy_dfi_p1_rddata[42] <= ddrphy_dq_i_data10[6]; + ddrphy_dfi_p1_rddata[58] <= ddrphy_dq_i_data10[7]; + ddrphy_dfi_p1_rddata[11] <= ddrphy_dq_i_data11[4]; + ddrphy_dfi_p1_rddata[27] <= ddrphy_dq_i_data11[5]; + ddrphy_dfi_p1_rddata[43] <= ddrphy_dq_i_data11[6]; + ddrphy_dfi_p1_rddata[59] <= ddrphy_dq_i_data11[7]; + ddrphy_dfi_p1_rddata[12] <= ddrphy_dq_i_data12[4]; + ddrphy_dfi_p1_rddata[28] <= ddrphy_dq_i_data12[5]; + ddrphy_dfi_p1_rddata[44] <= ddrphy_dq_i_data12[6]; + ddrphy_dfi_p1_rddata[60] <= ddrphy_dq_i_data12[7]; + ddrphy_dfi_p1_rddata[13] <= ddrphy_dq_i_data13[4]; + ddrphy_dfi_p1_rddata[29] <= ddrphy_dq_i_data13[5]; + ddrphy_dfi_p1_rddata[45] <= ddrphy_dq_i_data13[6]; + ddrphy_dfi_p1_rddata[61] <= ddrphy_dq_i_data13[7]; + ddrphy_dfi_p1_rddata[14] <= ddrphy_dq_i_data14[4]; + ddrphy_dfi_p1_rddata[30] <= ddrphy_dq_i_data14[5]; + ddrphy_dfi_p1_rddata[46] <= ddrphy_dq_i_data14[6]; + ddrphy_dfi_p1_rddata[62] <= ddrphy_dq_i_data14[7]; + ddrphy_dfi_p1_rddata[15] <= ddrphy_dq_i_data15[4]; + ddrphy_dfi_p1_rddata[31] <= ddrphy_dq_i_data15[5]; + ddrphy_dfi_p1_rddata[47] <= ddrphy_dq_i_data15[6]; + ddrphy_dfi_p1_rddata[63] <= ddrphy_dq_i_data15[7]; +end +always @(*) begin + ddrphy_dq_o_data1 <= 8'd0; + ddrphy_dq_o_data1[0] <= ddrphy_dfi_p0_wrdata[1]; + ddrphy_dq_o_data1[1] <= ddrphy_dfi_p0_wrdata[17]; + ddrphy_dq_o_data1[2] <= ddrphy_dfi_p0_wrdata[33]; + ddrphy_dq_o_data1[3] <= ddrphy_dfi_p0_wrdata[49]; + ddrphy_dq_o_data1[4] <= ddrphy_dfi_p1_wrdata[1]; + ddrphy_dq_o_data1[5] <= ddrphy_dfi_p1_wrdata[17]; + ddrphy_dq_o_data1[6] <= ddrphy_dfi_p1_wrdata[33]; + ddrphy_dq_o_data1[7] <= ddrphy_dfi_p1_wrdata[49]; +end +assign ddrphy_dq_i_data1 = {ddrphy_bitslip1_o, ddrphy_dq_i_bitslip_o_d1}; +always @(*) begin + ddrphy_dq_o_data2 <= 8'd0; + ddrphy_dq_o_data2[0] <= ddrphy_dfi_p0_wrdata[2]; + ddrphy_dq_o_data2[1] <= ddrphy_dfi_p0_wrdata[18]; + ddrphy_dq_o_data2[2] <= ddrphy_dfi_p0_wrdata[34]; + ddrphy_dq_o_data2[3] <= ddrphy_dfi_p0_wrdata[50]; + ddrphy_dq_o_data2[4] <= ddrphy_dfi_p1_wrdata[2]; + ddrphy_dq_o_data2[5] <= ddrphy_dfi_p1_wrdata[18]; + ddrphy_dq_o_data2[6] <= ddrphy_dfi_p1_wrdata[34]; + ddrphy_dq_o_data2[7] <= ddrphy_dfi_p1_wrdata[50]; +end +assign ddrphy_dq_i_data2 = {ddrphy_bitslip2_o, ddrphy_dq_i_bitslip_o_d2}; +always @(*) begin + ddrphy_dq_o_data3 <= 8'd0; + ddrphy_dq_o_data3[0] <= ddrphy_dfi_p0_wrdata[3]; + ddrphy_dq_o_data3[1] <= ddrphy_dfi_p0_wrdata[19]; + ddrphy_dq_o_data3[2] <= ddrphy_dfi_p0_wrdata[35]; + ddrphy_dq_o_data3[3] <= ddrphy_dfi_p0_wrdata[51]; + ddrphy_dq_o_data3[4] <= ddrphy_dfi_p1_wrdata[3]; + ddrphy_dq_o_data3[5] <= ddrphy_dfi_p1_wrdata[19]; + ddrphy_dq_o_data3[6] <= ddrphy_dfi_p1_wrdata[35]; + ddrphy_dq_o_data3[7] <= ddrphy_dfi_p1_wrdata[51]; +end +assign ddrphy_dq_i_data3 = {ddrphy_bitslip3_o, ddrphy_dq_i_bitslip_o_d3}; +always @(*) begin + ddrphy_dq_o_data4 <= 8'd0; + ddrphy_dq_o_data4[0] <= ddrphy_dfi_p0_wrdata[4]; + ddrphy_dq_o_data4[1] <= ddrphy_dfi_p0_wrdata[20]; + ddrphy_dq_o_data4[2] <= ddrphy_dfi_p0_wrdata[36]; + ddrphy_dq_o_data4[3] <= ddrphy_dfi_p0_wrdata[52]; + ddrphy_dq_o_data4[4] <= ddrphy_dfi_p1_wrdata[4]; + ddrphy_dq_o_data4[5] <= ddrphy_dfi_p1_wrdata[20]; + ddrphy_dq_o_data4[6] <= ddrphy_dfi_p1_wrdata[36]; + ddrphy_dq_o_data4[7] <= ddrphy_dfi_p1_wrdata[52]; +end +assign ddrphy_dq_i_data4 = {ddrphy_bitslip4_o, ddrphy_dq_i_bitslip_o_d4}; +always @(*) begin + ddrphy_dq_o_data5 <= 8'd0; + ddrphy_dq_o_data5[0] <= ddrphy_dfi_p0_wrdata[5]; + ddrphy_dq_o_data5[1] <= ddrphy_dfi_p0_wrdata[21]; + ddrphy_dq_o_data5[2] <= ddrphy_dfi_p0_wrdata[37]; + ddrphy_dq_o_data5[3] <= ddrphy_dfi_p0_wrdata[53]; + ddrphy_dq_o_data5[4] <= ddrphy_dfi_p1_wrdata[5]; + ddrphy_dq_o_data5[5] <= ddrphy_dfi_p1_wrdata[21]; + ddrphy_dq_o_data5[6] <= ddrphy_dfi_p1_wrdata[37]; + ddrphy_dq_o_data5[7] <= ddrphy_dfi_p1_wrdata[53]; +end +assign ddrphy_dq_i_data5 = {ddrphy_bitslip5_o, ddrphy_dq_i_bitslip_o_d5}; +always @(*) begin + ddrphy_dq_o_data6 <= 8'd0; + ddrphy_dq_o_data6[0] <= ddrphy_dfi_p0_wrdata[6]; + ddrphy_dq_o_data6[1] <= ddrphy_dfi_p0_wrdata[22]; + ddrphy_dq_o_data6[2] <= ddrphy_dfi_p0_wrdata[38]; + ddrphy_dq_o_data6[3] <= ddrphy_dfi_p0_wrdata[54]; + ddrphy_dq_o_data6[4] <= ddrphy_dfi_p1_wrdata[6]; + ddrphy_dq_o_data6[5] <= ddrphy_dfi_p1_wrdata[22]; + ddrphy_dq_o_data6[6] <= ddrphy_dfi_p1_wrdata[38]; + ddrphy_dq_o_data6[7] <= ddrphy_dfi_p1_wrdata[54]; +end +assign ddrphy_dq_i_data6 = {ddrphy_bitslip6_o, ddrphy_dq_i_bitslip_o_d6}; +always @(*) begin + ddrphy_dq_o_data7 <= 8'd0; + ddrphy_dq_o_data7[0] <= ddrphy_dfi_p0_wrdata[7]; + ddrphy_dq_o_data7[1] <= ddrphy_dfi_p0_wrdata[23]; + ddrphy_dq_o_data7[2] <= ddrphy_dfi_p0_wrdata[39]; + ddrphy_dq_o_data7[3] <= ddrphy_dfi_p0_wrdata[55]; + ddrphy_dq_o_data7[4] <= ddrphy_dfi_p1_wrdata[7]; + ddrphy_dq_o_data7[5] <= ddrphy_dfi_p1_wrdata[23]; + ddrphy_dq_o_data7[6] <= ddrphy_dfi_p1_wrdata[39]; + ddrphy_dq_o_data7[7] <= ddrphy_dfi_p1_wrdata[55]; +end +assign ddrphy_dq_i_data7 = {ddrphy_bitslip7_o, ddrphy_dq_i_bitslip_o_d7}; +always @(*) begin + ddrphy_dm_o_data1 <= 8'd0; + ddrphy_dm_o_data1[0] <= ddrphy_dfi_p0_wrdata_mask[1]; + ddrphy_dm_o_data1[1] <= ddrphy_dfi_p0_wrdata_mask[3]; + ddrphy_dm_o_data1[2] <= ddrphy_dfi_p0_wrdata_mask[5]; + ddrphy_dm_o_data1[3] <= ddrphy_dfi_p0_wrdata_mask[7]; + ddrphy_dm_o_data1[4] <= ddrphy_dfi_p1_wrdata_mask[1]; + ddrphy_dm_o_data1[5] <= ddrphy_dfi_p1_wrdata_mask[3]; + ddrphy_dm_o_data1[6] <= ddrphy_dfi_p1_wrdata_mask[5]; + ddrphy_dm_o_data1[7] <= ddrphy_dfi_p1_wrdata_mask[7]; +end +always @(*) begin + ddrphy_dq_o_data8 <= 8'd0; + ddrphy_dq_o_data8[0] <= ddrphy_dfi_p0_wrdata[8]; + ddrphy_dq_o_data8[1] <= ddrphy_dfi_p0_wrdata[24]; + ddrphy_dq_o_data8[2] <= ddrphy_dfi_p0_wrdata[40]; + ddrphy_dq_o_data8[3] <= ddrphy_dfi_p0_wrdata[56]; + ddrphy_dq_o_data8[4] <= ddrphy_dfi_p1_wrdata[8]; + ddrphy_dq_o_data8[5] <= ddrphy_dfi_p1_wrdata[24]; + ddrphy_dq_o_data8[6] <= ddrphy_dfi_p1_wrdata[40]; + ddrphy_dq_o_data8[7] <= ddrphy_dfi_p1_wrdata[56]; +end +assign ddrphy_dq_i_data8 = {ddrphy_bitslip8_o, ddrphy_dq_i_bitslip_o_d8}; +always @(*) begin + ddrphy_dq_o_data9 <= 8'd0; + ddrphy_dq_o_data9[0] <= ddrphy_dfi_p0_wrdata[9]; + ddrphy_dq_o_data9[1] <= ddrphy_dfi_p0_wrdata[25]; + ddrphy_dq_o_data9[2] <= ddrphy_dfi_p0_wrdata[41]; + ddrphy_dq_o_data9[3] <= ddrphy_dfi_p0_wrdata[57]; + ddrphy_dq_o_data9[4] <= ddrphy_dfi_p1_wrdata[9]; + ddrphy_dq_o_data9[5] <= ddrphy_dfi_p1_wrdata[25]; + ddrphy_dq_o_data9[6] <= ddrphy_dfi_p1_wrdata[41]; + ddrphy_dq_o_data9[7] <= ddrphy_dfi_p1_wrdata[57]; +end +assign ddrphy_dq_i_data9 = {ddrphy_bitslip9_o, ddrphy_dq_i_bitslip_o_d9}; +always @(*) begin + ddrphy_dq_o_data10 <= 8'd0; + ddrphy_dq_o_data10[0] <= ddrphy_dfi_p0_wrdata[10]; + ddrphy_dq_o_data10[1] <= ddrphy_dfi_p0_wrdata[26]; + ddrphy_dq_o_data10[2] <= ddrphy_dfi_p0_wrdata[42]; + ddrphy_dq_o_data10[3] <= ddrphy_dfi_p0_wrdata[58]; + ddrphy_dq_o_data10[4] <= ddrphy_dfi_p1_wrdata[10]; + ddrphy_dq_o_data10[5] <= ddrphy_dfi_p1_wrdata[26]; + ddrphy_dq_o_data10[6] <= ddrphy_dfi_p1_wrdata[42]; + ddrphy_dq_o_data10[7] <= ddrphy_dfi_p1_wrdata[58]; +end +assign ddrphy_dq_i_data10 = {ddrphy_bitslip10_o, ddrphy_dq_i_bitslip_o_d10}; +always @(*) begin + ddrphy_dq_o_data11 <= 8'd0; + ddrphy_dq_o_data11[0] <= ddrphy_dfi_p0_wrdata[11]; + ddrphy_dq_o_data11[1] <= ddrphy_dfi_p0_wrdata[27]; + ddrphy_dq_o_data11[2] <= ddrphy_dfi_p0_wrdata[43]; + ddrphy_dq_o_data11[3] <= ddrphy_dfi_p0_wrdata[59]; + ddrphy_dq_o_data11[4] <= ddrphy_dfi_p1_wrdata[11]; + ddrphy_dq_o_data11[5] <= ddrphy_dfi_p1_wrdata[27]; + ddrphy_dq_o_data11[6] <= ddrphy_dfi_p1_wrdata[43]; + ddrphy_dq_o_data11[7] <= ddrphy_dfi_p1_wrdata[59]; +end +assign ddrphy_dq_i_data11 = {ddrphy_bitslip11_o, ddrphy_dq_i_bitslip_o_d11}; +always @(*) begin + ddrphy_dq_o_data12 <= 8'd0; + ddrphy_dq_o_data12[0] <= ddrphy_dfi_p0_wrdata[12]; + ddrphy_dq_o_data12[1] <= ddrphy_dfi_p0_wrdata[28]; + ddrphy_dq_o_data12[2] <= ddrphy_dfi_p0_wrdata[44]; + ddrphy_dq_o_data12[3] <= ddrphy_dfi_p0_wrdata[60]; + ddrphy_dq_o_data12[4] <= ddrphy_dfi_p1_wrdata[12]; + ddrphy_dq_o_data12[5] <= ddrphy_dfi_p1_wrdata[28]; + ddrphy_dq_o_data12[6] <= ddrphy_dfi_p1_wrdata[44]; + ddrphy_dq_o_data12[7] <= ddrphy_dfi_p1_wrdata[60]; +end +assign ddrphy_dq_i_data12 = {ddrphy_bitslip12_o, ddrphy_dq_i_bitslip_o_d12}; +always @(*) begin + ddrphy_dq_o_data13 <= 8'd0; + ddrphy_dq_o_data13[0] <= ddrphy_dfi_p0_wrdata[13]; + ddrphy_dq_o_data13[1] <= ddrphy_dfi_p0_wrdata[29]; + ddrphy_dq_o_data13[2] <= ddrphy_dfi_p0_wrdata[45]; + ddrphy_dq_o_data13[3] <= ddrphy_dfi_p0_wrdata[61]; + ddrphy_dq_o_data13[4] <= ddrphy_dfi_p1_wrdata[13]; + ddrphy_dq_o_data13[5] <= ddrphy_dfi_p1_wrdata[29]; + ddrphy_dq_o_data13[6] <= ddrphy_dfi_p1_wrdata[45]; + ddrphy_dq_o_data13[7] <= ddrphy_dfi_p1_wrdata[61]; +end +assign ddrphy_dq_i_data13 = {ddrphy_bitslip13_o, ddrphy_dq_i_bitslip_o_d13}; +always @(*) begin + ddrphy_dq_o_data14 <= 8'd0; + ddrphy_dq_o_data14[0] <= ddrphy_dfi_p0_wrdata[14]; + ddrphy_dq_o_data14[1] <= ddrphy_dfi_p0_wrdata[30]; + ddrphy_dq_o_data14[2] <= ddrphy_dfi_p0_wrdata[46]; + ddrphy_dq_o_data14[3] <= ddrphy_dfi_p0_wrdata[62]; + ddrphy_dq_o_data14[4] <= ddrphy_dfi_p1_wrdata[14]; + ddrphy_dq_o_data14[5] <= ddrphy_dfi_p1_wrdata[30]; + ddrphy_dq_o_data14[6] <= ddrphy_dfi_p1_wrdata[46]; + ddrphy_dq_o_data14[7] <= ddrphy_dfi_p1_wrdata[62]; +end +assign ddrphy_dq_i_data14 = {ddrphy_bitslip14_o, ddrphy_dq_i_bitslip_o_d14}; +always @(*) begin + ddrphy_dq_o_data15 <= 8'd0; + ddrphy_dq_o_data15[0] <= ddrphy_dfi_p0_wrdata[15]; + ddrphy_dq_o_data15[1] <= ddrphy_dfi_p0_wrdata[31]; + ddrphy_dq_o_data15[2] <= ddrphy_dfi_p0_wrdata[47]; + ddrphy_dq_o_data15[3] <= ddrphy_dfi_p0_wrdata[63]; + ddrphy_dq_o_data15[4] <= ddrphy_dfi_p1_wrdata[15]; + ddrphy_dq_o_data15[5] <= ddrphy_dfi_p1_wrdata[31]; + ddrphy_dq_o_data15[6] <= ddrphy_dfi_p1_wrdata[47]; + ddrphy_dq_o_data15[7] <= ddrphy_dfi_p1_wrdata[63]; +end +assign ddrphy_dq_i_data15 = {ddrphy_bitslip15_o, ddrphy_dq_i_bitslip_o_d15}; +assign ddrphy_dfi_p0_rddata_valid = ddrphy_rddata_en_tappeddelayline12; +assign ddrphy_dfi_p1_rddata_valid = ddrphy_rddata_en_tappeddelayline12; +assign ddrphy_dqs_re = (ddrphy_rddata_en_tappeddelayline3 | ddrphy_rddata_en_tappeddelayline4); +assign ddrphy_dq_oe = (ddrphy_wrdata_en_tappeddelayline3 | ddrphy_wrdata_en_tappeddelayline4); +assign ddrphy_bl8_chunk = ddrphy_wrdata_en_tappeddelayline3; +assign ddrphy_dqs_oe = ddrphy_dq_oe; +assign ddrphy_dqs_preamble = (ddrphy_wrdata_en_tappeddelayline2 & (~ddrphy_wrdata_en_tappeddelayline3)); +assign ddrphy_dqs_postamble = (ddrphy_wrdata_en_tappeddelayline5 & (~ddrphy_wrdata_en_tappeddelayline4)); +assign ddrphy_new_lock = (ddrphy_lock1 & (~ddrphy_lock_d)); +assign ddrphy_pause0 = ddrphy_pause1; +assign ddrphy_stop0 = ddrphy_stop1; +assign ddrphy_delay0 = ddrphy_delay1; +assign ddrphy_reset0 = ddrphy_reset1; +always @(*) begin + ddrphy_bitslip0_o <= 4'd0; + case (ddrphy_bitslip0_value) + 1'd0: begin + ddrphy_bitslip0_o <= ddrphy_bitslip0_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip0_o <= ddrphy_bitslip0_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip0_o <= ddrphy_bitslip0_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip0_o <= ddrphy_bitslip0_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip1_o <= 4'd0; + case (ddrphy_bitslip1_value) + 1'd0: begin + ddrphy_bitslip1_o <= ddrphy_bitslip1_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip1_o <= ddrphy_bitslip1_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip1_o <= ddrphy_bitslip1_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip1_o <= ddrphy_bitslip1_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip2_o <= 4'd0; + case (ddrphy_bitslip2_value) + 1'd0: begin + ddrphy_bitslip2_o <= ddrphy_bitslip2_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip2_o <= ddrphy_bitslip2_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip2_o <= ddrphy_bitslip2_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip2_o <= ddrphy_bitslip2_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip3_o <= 4'd0; + case (ddrphy_bitslip3_value) + 1'd0: begin + ddrphy_bitslip3_o <= ddrphy_bitslip3_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip3_o <= ddrphy_bitslip3_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip3_o <= ddrphy_bitslip3_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip3_o <= ddrphy_bitslip3_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip4_o <= 4'd0; + case (ddrphy_bitslip4_value) + 1'd0: begin + ddrphy_bitslip4_o <= ddrphy_bitslip4_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip4_o <= ddrphy_bitslip4_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip4_o <= ddrphy_bitslip4_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip4_o <= ddrphy_bitslip4_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip5_o <= 4'd0; + case (ddrphy_bitslip5_value) + 1'd0: begin + ddrphy_bitslip5_o <= ddrphy_bitslip5_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip5_o <= ddrphy_bitslip5_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip5_o <= ddrphy_bitslip5_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip5_o <= ddrphy_bitslip5_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip6_o <= 4'd0; + case (ddrphy_bitslip6_value) + 1'd0: begin + ddrphy_bitslip6_o <= ddrphy_bitslip6_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip6_o <= ddrphy_bitslip6_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip6_o <= ddrphy_bitslip6_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip6_o <= ddrphy_bitslip6_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip7_o <= 4'd0; + case (ddrphy_bitslip7_value) + 1'd0: begin + ddrphy_bitslip7_o <= ddrphy_bitslip7_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip7_o <= ddrphy_bitslip7_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip7_o <= ddrphy_bitslip7_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip7_o <= ddrphy_bitslip7_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip8_o <= 4'd0; + case (ddrphy_bitslip8_value) + 1'd0: begin + ddrphy_bitslip8_o <= ddrphy_bitslip8_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip8_o <= ddrphy_bitslip8_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip8_o <= ddrphy_bitslip8_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip8_o <= ddrphy_bitslip8_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip9_o <= 4'd0; + case (ddrphy_bitslip9_value) + 1'd0: begin + ddrphy_bitslip9_o <= ddrphy_bitslip9_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip9_o <= ddrphy_bitslip9_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip9_o <= ddrphy_bitslip9_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip9_o <= ddrphy_bitslip9_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip10_o <= 4'd0; + case (ddrphy_bitslip10_value) + 1'd0: begin + ddrphy_bitslip10_o <= ddrphy_bitslip10_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip10_o <= ddrphy_bitslip10_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip10_o <= ddrphy_bitslip10_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip10_o <= ddrphy_bitslip10_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip11_o <= 4'd0; + case (ddrphy_bitslip11_value) + 1'd0: begin + ddrphy_bitslip11_o <= ddrphy_bitslip11_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip11_o <= ddrphy_bitslip11_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip11_o <= ddrphy_bitslip11_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip11_o <= ddrphy_bitslip11_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip12_o <= 4'd0; + case (ddrphy_bitslip12_value) + 1'd0: begin + ddrphy_bitslip12_o <= ddrphy_bitslip12_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip12_o <= ddrphy_bitslip12_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip12_o <= ddrphy_bitslip12_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip12_o <= ddrphy_bitslip12_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip13_o <= 4'd0; + case (ddrphy_bitslip13_value) + 1'd0: begin + ddrphy_bitslip13_o <= ddrphy_bitslip13_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip13_o <= ddrphy_bitslip13_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip13_o <= ddrphy_bitslip13_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip13_o <= ddrphy_bitslip13_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip14_o <= 4'd0; + case (ddrphy_bitslip14_value) + 1'd0: begin + ddrphy_bitslip14_o <= ddrphy_bitslip14_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip14_o <= ddrphy_bitslip14_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip14_o <= ddrphy_bitslip14_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip14_o <= ddrphy_bitslip14_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip15_o <= 4'd0; + case (ddrphy_bitslip15_value) + 1'd0: begin + ddrphy_bitslip15_o <= ddrphy_bitslip15_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip15_o <= ddrphy_bitslip15_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip15_o <= ddrphy_bitslip15_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip15_o <= ddrphy_bitslip15_r[6:3]; + end + endcase +end +assign ddrphy_dfi_p0_address = litedramcore_master_p0_address; +assign ddrphy_dfi_p0_bank = litedramcore_master_p0_bank; +assign ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n; +assign ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n; +assign ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n; +assign ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n; +assign ddrphy_dfi_p0_cke = litedramcore_master_p0_cke; +assign ddrphy_dfi_p0_odt = litedramcore_master_p0_odt; +assign ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n; +assign ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n; +assign ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata; +assign ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en; +assign ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask; +assign ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en; +assign litedramcore_master_p0_rddata = ddrphy_dfi_p0_rddata; +assign litedramcore_master_p0_rddata_valid = ddrphy_dfi_p0_rddata_valid; +assign ddrphy_dfi_p1_address = litedramcore_master_p1_address; +assign ddrphy_dfi_p1_bank = litedramcore_master_p1_bank; +assign ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n; +assign ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n; +assign ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n; +assign ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n; +assign ddrphy_dfi_p1_cke = litedramcore_master_p1_cke; +assign ddrphy_dfi_p1_odt = litedramcore_master_p1_odt; +assign ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n; +assign ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n; +assign ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata; +assign ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en; +assign ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask; +assign ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en; +assign litedramcore_master_p1_rddata = ddrphy_dfi_p1_rddata; +assign litedramcore_master_p1_rddata_valid = ddrphy_dfi_p1_rddata_valid; +assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address; +assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank; +assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n; +assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n; +assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n; +assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n; +assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke; +assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt; +assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n; +assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n; +assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata; +assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en; +assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask; +assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en; +assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata; +assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid; +assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address; +assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank; +assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n; +assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n; +assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n; +assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n; +assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke; +assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt; +assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n; +assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n; +assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata; +assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en; +assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask; +assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en; +assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata; +assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid; +always @(*) begin + litedramcore_master_p0_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n; + end else begin + litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; + if (1'd0) begin + litedramcore_master_p0_cs_n <= {2{litedramcore_slave_p0_cs_n}}; + end + end + end else begin + litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n; + end +end +always @(*) begin + litedramcore_csr_dfi_p1_rddata <= 64'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata; + end +end +always @(*) begin + litedramcore_master_p0_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n; + end else begin + litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; + end + end else begin + litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n; + end +end +always @(*) begin + litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end +end +always @(*) begin + litedramcore_master_p0_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n; + end else begin + litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + end + end else begin + litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n; + end +end +always @(*) begin + litedramcore_master_p0_cke <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke; + end else begin + litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; + end + end else begin + litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke; + end +end +always @(*) begin + litedramcore_master_p0_odt <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt; + end else begin + litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; + end + end else begin + litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt; + end +end +always @(*) begin + litedramcore_master_p0_reset_n <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n; + end else begin + litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; + end + end else begin + litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n; + end +end +always @(*) begin + litedramcore_master_p0_act_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n; + end else begin + litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; + end + end else begin + litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n; + end +end +always @(*) begin + litedramcore_master_p0_wrdata <= 64'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata; + end else begin + litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; + end + end else begin + litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata; + end +end +always @(*) begin + litedramcore_master_p0_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en; + end else begin + litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; + end + end else begin + litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p0_wrdata_mask <= 8'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask; + end else begin + litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; + end + end else begin + litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p0_rddata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en; + end else begin + litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; + end + end else begin + litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en; + end +end +always @(*) begin + litedramcore_master_p1_address <= 15'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address; + end else begin + litedramcore_master_p1_address <= litedramcore_slave_p1_address; + end + end else begin + litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address; + end +end +always @(*) begin + litedramcore_master_p1_bank <= 3'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank; + end else begin + litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; + end + end else begin + litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank; + end +end +always @(*) begin + litedramcore_master_p1_cas_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n; + end else begin + litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; + end + end else begin + litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n; + end +end +always @(*) begin + litedramcore_master_p1_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n; + end else begin + litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; + if (1'd0) begin + litedramcore_master_p1_cs_n <= {2{litedramcore_slave_p1_cs_n}}; + end + end + end else begin + litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n; + end +end +always @(*) begin + litedramcore_master_p1_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n; + end else begin + litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; + end + end else begin + litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n; + end +end +always @(*) begin + litedramcore_master_p1_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n; + end else begin + litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; + end + end else begin + litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n; + end +end +always @(*) begin + litedramcore_master_p1_cke <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke; + end else begin + litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; + end + end else begin + litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke; + end +end +always @(*) begin + litedramcore_master_p1_odt <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt; + end else begin + litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; + end + end else begin + litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt; + end +end +always @(*) begin + litedramcore_ext_dfi_p0_rddata <= 64'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_master_p1_reset_n <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n; + end else begin + litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; + end + end else begin + litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n; + end +end +always @(*) begin + litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_master_p1_act_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n; + end else begin + litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; + end + end else begin + litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n; + end +end +always @(*) begin + litedramcore_master_p1_wrdata <= 64'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata; + end else begin + litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; + end + end else begin + litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata; + end +end +always @(*) begin + litedramcore_master_p1_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en; + end else begin + litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; + end + end else begin + litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p1_wrdata_mask <= 8'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask; + end else begin + litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; + end + end else begin + litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p1_rddata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en; + end else begin + litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; + end + end else begin + litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en; + end +end +always @(*) begin + litedramcore_ext_dfi_p1_rddata <= 64'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p0_rddata <= 64'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p0_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + end + end else begin + end +end +always @(*) begin + litedramcore_csr_dfi_p0_rddata <= 64'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata; + end +end +always @(*) begin + litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + end +end +always @(*) begin + litedramcore_slave_p1_rddata <= 64'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end + end else begin + end +end +always @(*) begin + litedramcore_master_p0_address <= 15'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address; + end else begin + litedramcore_master_p0_address <= litedramcore_slave_p0_address; + end + end else begin + litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address; + end +end +always @(*) begin + litedramcore_master_p0_bank <= 3'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank; + end else begin + litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; + end + end else begin + litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank; + end +end +always @(*) begin + litedramcore_master_p0_cas_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n; + end else begin + litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; + end + end else begin + litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n; + end +end +always @(*) begin + litedramcore_csr_dfi_p0_cke <= 1'd0; + litedramcore_csr_dfi_p0_cke <= litedramcore_cke; +end +always @(*) begin + litedramcore_csr_dfi_p1_cke <= 1'd0; + litedramcore_csr_dfi_p1_cke <= litedramcore_cke; +end +always @(*) begin + litedramcore_csr_dfi_p0_odt <= 1'd0; + litedramcore_csr_dfi_p0_odt <= litedramcore_odt; +end +always @(*) begin + litedramcore_csr_dfi_p1_odt <= 1'd0; + litedramcore_csr_dfi_p1_odt <= litedramcore_odt; +end +assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n; +assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n; +always @(*) begin + litedramcore_csr_dfi_p0_cas_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas); + end else begin + litedramcore_csr_dfi_p0_cas_n <= 1'd1; + end +end +always @(*) begin + litedramcore_csr_dfi_p0_cs_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + if (litedramcore_phaseinjector0_csrfield_cs_top) begin + litedramcore_csr_dfi_p0_cs_n <= 2'd2; + end else begin + if (litedramcore_phaseinjector0_csrfield_cs_bottom) begin + litedramcore_csr_dfi_p0_cs_n <= 1'd1; + end else begin + litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}}; + end + end + end else begin + litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; + end +end +always @(*) begin + litedramcore_csr_dfi_p0_ras_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras); + end else begin + litedramcore_csr_dfi_p0_ras_n <= 1'd1; + end +end +always @(*) begin + litedramcore_csr_dfi_p0_we_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we); + end else begin + litedramcore_csr_dfi_p0_we_n <= 1'd1; + end +end +assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage; +assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage; +assign litedramcore_csr_dfi_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_wren); +assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_rden); +assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; +assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; +always @(*) begin + litedramcore_csr_dfi_p1_cas_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas); + end else begin + litedramcore_csr_dfi_p1_cas_n <= 1'd1; + end +end +always @(*) begin + litedramcore_csr_dfi_p1_cs_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + if (litedramcore_phaseinjector1_csrfield_cs_top) begin + litedramcore_csr_dfi_p1_cs_n <= 2'd2; + end else begin + if (litedramcore_phaseinjector1_csrfield_cs_bottom) begin + litedramcore_csr_dfi_p1_cs_n <= 1'd1; + end else begin + litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}}; + end + end + end else begin + litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; + end +end +always @(*) begin + litedramcore_csr_dfi_p1_ras_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras); + end else begin + litedramcore_csr_dfi_p1_ras_n <= 1'd1; + end +end +always @(*) begin + litedramcore_csr_dfi_p1_we_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we); + end else begin + litedramcore_csr_dfi_p1_we_n <= 1'd1; + end +end +assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage; +assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage; +assign litedramcore_csr_dfi_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_wren); +assign litedramcore_csr_dfi_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_rden); +assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; +assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; +assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid; +assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready; +assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we; +assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr; +assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock; +assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready; +assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid; +assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid; +assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready; +assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we; +assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr; +assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock; +assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready; +assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid; +assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid; +assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready; +assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we; +assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr; +assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock; +assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready; +assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid; +assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid; +assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready; +assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we; +assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr; +assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock; +assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready; +assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid; +assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid; +assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready; +assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we; +assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr; +assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock; +assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready; +assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid; +assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid; +assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready; +assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we; +assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr; +assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock; +assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready; +assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid; +assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid; +assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready; +assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we; +assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr; +assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock; +assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready; +assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid; +assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid; +assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready; +assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we; +assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr; +assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock; +assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready; +assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid; +assign litedramcore_timer_wait = (~litedramcore_timer_done0); +assign litedramcore_postponer_req_i = litedramcore_timer_done0; +assign litedramcore_wants_refresh = litedramcore_postponer_req_o; +assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0; +assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done); +assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0); +assign litedramcore_timer_done0 = litedramcore_timer_done1; +assign litedramcore_timer_count0 = litedramcore_timer_count1; +assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0)); +assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0)); +assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0); +assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1; +assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1; +always @(*) begin + litedramcore_refresher_next_state <= 2'd0; + litedramcore_refresher_next_state <= litedramcore_refresher_state; + case (litedramcore_refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + litedramcore_refresher_next_state <= 2'd2; + end + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + litedramcore_refresher_next_state <= 2'd3; + end else begin + litedramcore_refresher_next_state <= 1'd0; + end + end + end + 2'd3: begin + if (litedramcore_zqcs_executer_done) begin + litedramcore_refresher_next_state <= 1'd0; + end + end + default: begin + if (1'd1) begin + if (litedramcore_wants_refresh) begin + litedramcore_refresher_next_state <= 1'd1; + end + end + end + endcase +end +always @(*) begin + litedramcore_sequencer_start0 <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + litedramcore_sequencer_start0 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_cmd_valid <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + litedramcore_cmd_valid <= 1'd1; + end + 2'd2: begin + litedramcore_cmd_valid <= 1'd1; + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + end else begin + litedramcore_cmd_valid <= 1'd0; + end + end + end + 2'd3: begin + litedramcore_cmd_valid <= 1'd1; + if (litedramcore_zqcs_executer_done) begin + litedramcore_cmd_valid <= 1'd0; + end + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_zqcs_executer_start <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + litedramcore_zqcs_executer_start <= 1'd1; + end else begin + end + end + end + 2'd3: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_cmd_last <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + end else begin + litedramcore_cmd_last <= 1'd1; + end + end + end + 2'd3: begin + if (litedramcore_zqcs_executer_done) begin + litedramcore_cmd_last <= 1'd1; + end + end + default: begin + end + endcase +end +assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid; +assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready; +assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we; +assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr; +assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid; +assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready; +assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first; +assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last; +assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we; +assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr; +assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); +assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid); +assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[21:7]); +assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0; +always @(*) begin + litedramcore_bankmachine0_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine0_row_col_n_addr_sel) begin + litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write); +assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); +assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); +always @(*) begin + litedramcore_bankmachine0_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin + if ((litedramcore_bankmachine0_source_payload_addr[21:7] != litedramcore_bankmachine0_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we}; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable; +assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid; +assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first; +assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last; +assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we; +assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr; +assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable; +assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first; +assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last; +assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we; +assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr; +assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready; +always @(*) begin + litedramcore_bankmachine0_wrport_adr <= 4'd0; + if (litedramcore_bankmachine0_replace) begin + litedramcore_bankmachine0_wrport_adr <= (litedramcore_bankmachine0_produce - 1'd1); + end else begin + litedramcore_bankmachine0_wrport_adr <= litedramcore_bankmachine0_produce; + end +end +assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din; +assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace)); +assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re); +assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume; +assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r; +assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 5'd16); +assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0); +assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready); +assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid; +assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready; +assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first; +assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last; +assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we; +assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr; +assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid; +assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready; +assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first; +assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last; +assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we; +assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine0_next_state <= 3'd0; + litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + if (litedramcore_bankmachine0_cmd_ready) begin + litedramcore_bankmachine0_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + if (litedramcore_bankmachine0_cmd_ready) begin + litedramcore_bankmachine0_next_state <= 3'd6; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine0_refresh_req)) begin + litedramcore_bankmachine0_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine0_next_state <= 2'd3; + end + 3'd6: begin + litedramcore_bankmachine0_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + litedramcore_bankmachine0_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin + litedramcore_bankmachine0_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine0_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine0_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + end else begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + end else begin + litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine0_twtpcon_ready) begin + litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_open <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_close <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid; +assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready; +assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we; +assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr; +assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid; +assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready; +assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first; +assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last; +assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we; +assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr; +assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); +assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid); +assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[21:7]); +assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1; +always @(*) begin + litedramcore_bankmachine1_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine1_row_col_n_addr_sel) begin + litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write); +assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); +assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); +always @(*) begin + litedramcore_bankmachine1_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin + if ((litedramcore_bankmachine1_source_payload_addr[21:7] != litedramcore_bankmachine1_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we}; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable; +assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid; +assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first; +assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last; +assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we; +assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr; +assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable; +assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first; +assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last; +assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we; +assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr; +assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready; +always @(*) begin + litedramcore_bankmachine1_wrport_adr <= 4'd0; + if (litedramcore_bankmachine1_replace) begin + litedramcore_bankmachine1_wrport_adr <= (litedramcore_bankmachine1_produce - 1'd1); + end else begin + litedramcore_bankmachine1_wrport_adr <= litedramcore_bankmachine1_produce; + end +end +assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din; +assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace)); +assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re); +assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume; +assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r; +assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 5'd16); +assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0); +assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready); +assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid; +assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready; +assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first; +assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last; +assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we; +assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr; +assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid; +assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready; +assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first; +assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last; +assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we; +assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine1_next_state <= 3'd0; + litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + if (litedramcore_bankmachine1_cmd_ready) begin + litedramcore_bankmachine1_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + if (litedramcore_bankmachine1_cmd_ready) begin + litedramcore_bankmachine1_next_state <= 3'd6; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine1_refresh_req)) begin + litedramcore_bankmachine1_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine1_next_state <= 2'd3; + end + 3'd6: begin + litedramcore_bankmachine1_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + litedramcore_bankmachine1_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin + litedramcore_bankmachine1_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine1_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine1_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine1_twtpcon_ready) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_open <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_close <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid; +assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready; +assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we; +assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr; +assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid; +assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready; +assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first; +assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last; +assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we; +assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr; +assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); +assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid); +assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[21:7]); +assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2; +always @(*) begin + litedramcore_bankmachine2_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine2_row_col_n_addr_sel) begin + litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write); +assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); +assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); +always @(*) begin + litedramcore_bankmachine2_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin + if ((litedramcore_bankmachine2_source_payload_addr[21:7] != litedramcore_bankmachine2_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we}; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable; +assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid; +assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first; +assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last; +assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we; +assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr; +assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable; +assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first; +assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last; +assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we; +assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr; +assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready; +always @(*) begin + litedramcore_bankmachine2_wrport_adr <= 4'd0; + if (litedramcore_bankmachine2_replace) begin + litedramcore_bankmachine2_wrport_adr <= (litedramcore_bankmachine2_produce - 1'd1); + end else begin + litedramcore_bankmachine2_wrport_adr <= litedramcore_bankmachine2_produce; + end +end +assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din; +assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace)); +assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re); +assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume; +assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r; +assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 5'd16); +assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0); +assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready); +assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid; +assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready; +assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first; +assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last; +assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we; +assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr; +assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid; +assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready; +assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first; +assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last; +assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we; +assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine2_next_state <= 3'd0; + litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + if (litedramcore_bankmachine2_cmd_ready) begin + litedramcore_bankmachine2_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + if (litedramcore_bankmachine2_cmd_ready) begin + litedramcore_bankmachine2_next_state <= 3'd6; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine2_refresh_req)) begin + litedramcore_bankmachine2_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine2_next_state <= 2'd3; + end + 3'd6: begin + litedramcore_bankmachine2_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + litedramcore_bankmachine2_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin + litedramcore_bankmachine2_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine2_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine2_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_close <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + end else begin + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + end else begin + litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine2_twtpcon_ready) begin + litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_open <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_valid <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid; +assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready; +assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we; +assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr; +assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid; +assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready; +assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first; +assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last; +assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we; +assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr; +assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); +assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid); +assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[21:7]); +assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3; +always @(*) begin + litedramcore_bankmachine3_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine3_row_col_n_addr_sel) begin + litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write); +assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); +assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); +always @(*) begin + litedramcore_bankmachine3_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin + if ((litedramcore_bankmachine3_source_payload_addr[21:7] != litedramcore_bankmachine3_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we}; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable; +assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid; +assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first; +assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last; +assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we; +assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr; +assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable; +assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first; +assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last; +assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we; +assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr; +assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready; +always @(*) begin + litedramcore_bankmachine3_wrport_adr <= 4'd0; + if (litedramcore_bankmachine3_replace) begin + litedramcore_bankmachine3_wrport_adr <= (litedramcore_bankmachine3_produce - 1'd1); + end else begin + litedramcore_bankmachine3_wrport_adr <= litedramcore_bankmachine3_produce; + end +end +assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din; +assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace)); +assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re); +assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume; +assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r; +assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 5'd16); +assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0); +assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready); +assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid; +assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready; +assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first; +assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last; +assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we; +assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr; +assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid; +assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready; +assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first; +assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last; +assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we; +assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine3_next_state <= 3'd0; + litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + if (litedramcore_bankmachine3_cmd_ready) begin + litedramcore_bankmachine3_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + if (litedramcore_bankmachine3_cmd_ready) begin + litedramcore_bankmachine3_next_state <= 3'd6; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine3_refresh_req)) begin + litedramcore_bankmachine3_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine3_next_state <= 2'd3; + end + 3'd6: begin + litedramcore_bankmachine3_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + litedramcore_bankmachine3_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin + litedramcore_bankmachine3_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine3_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine3_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + end else begin + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + end else begin + litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine3_twtpcon_ready) begin + litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_open <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_close <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + litedramcore_bankmachine3_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine3_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine3_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid; +assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready; +assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we; +assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr; +assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid; +assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready; +assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first; +assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last; +assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we; +assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr; +assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); +assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid); +assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[21:7]); +assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4; +always @(*) begin + litedramcore_bankmachine4_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine4_row_col_n_addr_sel) begin + litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write); +assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); +assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); +always @(*) begin + litedramcore_bankmachine4_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin + if ((litedramcore_bankmachine4_source_payload_addr[21:7] != litedramcore_bankmachine4_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we}; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable; +assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid; +assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first; +assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last; +assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we; +assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr; +assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable; +assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first; +assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last; +assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we; +assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr; +assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready; +always @(*) begin + litedramcore_bankmachine4_wrport_adr <= 4'd0; + if (litedramcore_bankmachine4_replace) begin + litedramcore_bankmachine4_wrport_adr <= (litedramcore_bankmachine4_produce - 1'd1); + end else begin + litedramcore_bankmachine4_wrport_adr <= litedramcore_bankmachine4_produce; + end +end +assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din; +assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace)); +assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re); +assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume; +assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r; +assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 5'd16); +assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0); +assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready); +assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid; +assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready; +assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first; +assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last; +assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we; +assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr; +assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid; +assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready; +assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first; +assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last; +assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we; +assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine4_next_state <= 3'd0; + litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + if (litedramcore_bankmachine4_cmd_ready) begin + litedramcore_bankmachine4_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + if (litedramcore_bankmachine4_cmd_ready) begin + litedramcore_bankmachine4_next_state <= 3'd6; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine4_refresh_req)) begin + litedramcore_bankmachine4_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine4_next_state <= 2'd3; + end + 3'd6: begin + litedramcore_bankmachine4_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + litedramcore_bankmachine4_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin + litedramcore_bankmachine4_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine4_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine4_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + end else begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + end else begin + litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine4_twtpcon_ready) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_open <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_valid <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_close <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine4_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid; +assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready; +assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we; +assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr; +assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid; +assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready; +assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first; +assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last; +assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we; +assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr; +assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); +assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid); +assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[21:7]); +assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5; +always @(*) begin + litedramcore_bankmachine5_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine5_row_col_n_addr_sel) begin + litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write); +assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); +assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); +always @(*) begin + litedramcore_bankmachine5_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin + if ((litedramcore_bankmachine5_source_payload_addr[21:7] != litedramcore_bankmachine5_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we}; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable; +assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid; +assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first; +assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last; +assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we; +assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr; +assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable; +assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first; +assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last; +assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we; +assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr; +assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready; +always @(*) begin + litedramcore_bankmachine5_wrport_adr <= 4'd0; + if (litedramcore_bankmachine5_replace) begin + litedramcore_bankmachine5_wrport_adr <= (litedramcore_bankmachine5_produce - 1'd1); + end else begin + litedramcore_bankmachine5_wrport_adr <= litedramcore_bankmachine5_produce; + end +end +assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din; +assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace)); +assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re); +assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume; +assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r; +assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 5'd16); +assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0); +assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready); +assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid; +assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready; +assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first; +assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last; +assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we; +assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr; +assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid; +assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready; +assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first; +assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last; +assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we; +assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine5_next_state <= 3'd0; + litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + if (litedramcore_bankmachine5_cmd_ready) begin + litedramcore_bankmachine5_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + if (litedramcore_bankmachine5_cmd_ready) begin + litedramcore_bankmachine5_next_state <= 3'd6; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine5_refresh_req)) begin + litedramcore_bankmachine5_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine5_next_state <= 2'd3; + end + 3'd6: begin + litedramcore_bankmachine5_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + litedramcore_bankmachine5_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin + litedramcore_bankmachine5_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine5_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine5_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + end else begin + litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine5_twtpcon_ready) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_open <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_close <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine5_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + end else begin + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid; +assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready; +assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we; +assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr; +assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid; +assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready; +assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first; +assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last; +assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we; +assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr; +assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); +assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid); +assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[21:7]); +assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6; +always @(*) begin + litedramcore_bankmachine6_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine6_row_col_n_addr_sel) begin + litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write); +assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); +assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); +always @(*) begin + litedramcore_bankmachine6_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin + if ((litedramcore_bankmachine6_source_payload_addr[21:7] != litedramcore_bankmachine6_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we}; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable; +assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid; +assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first; +assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last; +assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we; +assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr; +assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable; +assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first; +assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last; +assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we; +assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr; +assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready; +always @(*) begin + litedramcore_bankmachine6_wrport_adr <= 4'd0; + if (litedramcore_bankmachine6_replace) begin + litedramcore_bankmachine6_wrport_adr <= (litedramcore_bankmachine6_produce - 1'd1); + end else begin + litedramcore_bankmachine6_wrport_adr <= litedramcore_bankmachine6_produce; + end +end +assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din; +assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace)); +assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re); +assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume; +assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r; +assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 5'd16); +assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0); +assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready); +assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid; +assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready; +assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first; +assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last; +assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we; +assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr; +assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid; +assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready; +assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first; +assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last; +assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we; +assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine6_next_state <= 3'd0; + litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + if (litedramcore_bankmachine6_cmd_ready) begin + litedramcore_bankmachine6_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + if (litedramcore_bankmachine6_cmd_ready) begin + litedramcore_bankmachine6_next_state <= 3'd6; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine6_refresh_req)) begin + litedramcore_bankmachine6_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine6_next_state <= 2'd3; + end + 3'd6: begin + litedramcore_bankmachine6_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + litedramcore_bankmachine6_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin + litedramcore_bankmachine6_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine6_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine6_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_close <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_open <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + end else begin + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + end else begin + litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine6_twtpcon_ready) begin + litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_valid <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid; +assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready; +assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we; +assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr; +assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid; +assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready; +assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first; +assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last; +assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we; +assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr; +assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); +assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid); +assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[21:7]); +assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7; +always @(*) begin + litedramcore_bankmachine7_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine7_row_col_n_addr_sel) begin + litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write); +assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); +assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); +always @(*) begin + litedramcore_bankmachine7_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin + if ((litedramcore_bankmachine7_source_payload_addr[21:7] != litedramcore_bankmachine7_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we}; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable; +assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid; +assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first; +assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last; +assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we; +assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr; +assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable; +assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first; +assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last; +assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we; +assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr; +assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready; +always @(*) begin + litedramcore_bankmachine7_wrport_adr <= 4'd0; + if (litedramcore_bankmachine7_replace) begin + litedramcore_bankmachine7_wrport_adr <= (litedramcore_bankmachine7_produce - 1'd1); + end else begin + litedramcore_bankmachine7_wrport_adr <= litedramcore_bankmachine7_produce; + end +end +assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din; +assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace)); +assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re); +assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume; +assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r; +assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 5'd16); +assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0); +assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready); +assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid; +assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready; +assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first; +assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last; +assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we; +assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr; +assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid; +assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready; +assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first; +assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last; +assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we; +assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine7_next_state <= 3'd0; + litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + if (litedramcore_bankmachine7_cmd_ready) begin + litedramcore_bankmachine7_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + if (litedramcore_bankmachine7_cmd_ready) begin + litedramcore_bankmachine7_next_state <= 3'd6; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine7_refresh_req)) begin + litedramcore_bankmachine7_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine7_next_state <= 2'd3; + end + 3'd6: begin + litedramcore_bankmachine7_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + litedramcore_bankmachine7_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin + litedramcore_bankmachine7_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine7_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine7_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + end else begin + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + end else begin + litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine7_twtpcon_ready) begin + litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_open <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_close <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine7_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); +assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); +assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready); +assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read)); +assign litedramcore_cas_allowed = litedramcore_tccdcon_ready; +assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); +assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read)); +assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write)); +assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0); +assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0); +assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid; +assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt); +assign litedramcore_interface_rdata = {litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata}; +assign {litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; +assign {litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; +assign {litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); +assign {litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); +always @(*) begin + litedramcore_choose_cmd_valids <= 8'd0; + litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); +end +assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; +assign litedramcore_choose_cmd_cmd_valid = rhs_self0; +assign litedramcore_choose_cmd_cmd_payload_a = rhs_self1; +assign litedramcore_choose_cmd_cmd_payload_ba = rhs_self2; +assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_self3; +assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_self4; +assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_self5; +always @(*) begin + litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_cas <= t_self0; + end +end +always @(*) begin + litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_ras <= t_self1; + end +end +always @(*) begin + litedramcore_choose_cmd_cmd_payload_we <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_we <= t_self2; + end +end +always @(*) begin + litedramcore_bankmachine0_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin + litedramcore_bankmachine0_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin + litedramcore_bankmachine0_cmd_ready <= 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine1_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin + litedramcore_bankmachine1_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin + litedramcore_bankmachine1_cmd_ready <= 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine2_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin + litedramcore_bankmachine2_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin + litedramcore_bankmachine2_cmd_ready <= 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine3_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin + litedramcore_bankmachine3_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin + litedramcore_bankmachine3_cmd_ready <= 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine4_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin + litedramcore_bankmachine4_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin + litedramcore_bankmachine4_cmd_ready <= 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine5_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin + litedramcore_bankmachine5_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin + litedramcore_bankmachine5_cmd_ready <= 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine6_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin + litedramcore_bankmachine6_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin + litedramcore_bankmachine6_cmd_ready <= 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine7_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin + litedramcore_bankmachine7_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin + litedramcore_bankmachine7_cmd_ready <= 1'd1; + end +end +assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid)); +always @(*) begin + litedramcore_choose_req_valids <= 8'd0; + litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); +end +assign litedramcore_choose_req_request = litedramcore_choose_req_valids; +assign litedramcore_choose_req_cmd_valid = rhs_self6; +assign litedramcore_choose_req_cmd_payload_a = rhs_self7; +assign litedramcore_choose_req_cmd_payload_ba = rhs_self8; +assign litedramcore_choose_req_cmd_payload_is_read = rhs_self9; +assign litedramcore_choose_req_cmd_payload_is_write = rhs_self10; +assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_self11; +always @(*) begin + litedramcore_choose_req_cmd_payload_cas <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_cas <= t_self3; + end +end +always @(*) begin + litedramcore_choose_req_cmd_payload_ras <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_ras <= t_self4; + end +end +always @(*) begin + litedramcore_choose_req_cmd_payload_we <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_we <= t_self5; + end +end +assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); +assign litedramcore_dfi_p0_reset_n = 1'd1; +assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer2}}; +assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer3}}; +assign litedramcore_dfi_p1_reset_n = 1'd1; +assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer4}}; +assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer5}}; +assign litedramcore_tfawcon_count = ((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]); +always @(*) begin + litedramcore_multiplexer_next_state <= 4'd0; + litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (litedramcore_read_available) begin + if (((~litedramcore_write_available) | litedramcore_max_time1)) begin + litedramcore_multiplexer_next_state <= 2'd3; + end + end + if (litedramcore_go_to_refresh) begin + litedramcore_multiplexer_next_state <= 2'd2; + end + end + 2'd2: begin + if (litedramcore_cmd_last) begin + litedramcore_multiplexer_next_state <= 1'd0; + end + end + 2'd3: begin + if (litedramcore_twtrcon_ready) begin + litedramcore_multiplexer_next_state <= 1'd0; + end + end + 3'd4: begin + litedramcore_multiplexer_next_state <= 3'd5; + end + 3'd5: begin + litedramcore_multiplexer_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_multiplexer_next_state <= 3'd7; + end + 3'd7: begin + litedramcore_multiplexer_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_multiplexer_next_state <= 4'd9; + end + 4'd9: begin + litedramcore_multiplexer_next_state <= 4'd10; + end + 4'd10: begin + litedramcore_multiplexer_next_state <= 4'd11; + end + 4'd11: begin + litedramcore_multiplexer_next_state <= 4'd12; + end + 4'd12: begin + litedramcore_multiplexer_next_state <= 4'd13; + end + 4'd13: begin + litedramcore_multiplexer_next_state <= 4'd14; + end + 4'd14: begin + litedramcore_multiplexer_next_state <= 4'd15; + end + 4'd15: begin + litedramcore_multiplexer_next_state <= 1'd1; + end + default: begin + if (litedramcore_write_available) begin + if (((~litedramcore_read_available) | litedramcore_max_time0)) begin + litedramcore_multiplexer_next_state <= 3'd4; + end + end + if (litedramcore_go_to_refresh) begin + litedramcore_multiplexer_next_state <= 2'd2; + end + end + endcase +end +always @(*) begin + litedramcore_steerer0 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer0 <= 1'd0; + if (1'd0) begin + litedramcore_steerer0 <= 2'd2; + end + if (1'd1) begin + litedramcore_steerer0 <= 1'd1; + end + end + 2'd2: begin + litedramcore_steerer0 <= 2'd3; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + litedramcore_steerer0 <= 1'd0; + if (1'd1) begin + litedramcore_steerer0 <= 2'd2; + end + if (1'd0) begin + litedramcore_steerer0 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_steerer1 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer1 <= 1'd0; + if (1'd1) begin + litedramcore_steerer1 <= 2'd2; + end + if (1'd0) begin + litedramcore_steerer1 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + litedramcore_steerer1 <= 1'd0; + if (1'd0) begin + litedramcore_steerer1 <= 2'd2; + end + if (1'd1) begin + litedramcore_steerer1 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_choose_cmd_want_activates <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end + end + endcase +end +always @(*) begin + litedramcore_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + litedramcore_cmd_ready <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_choose_cmd_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end + end + endcase +end +always @(*) begin + litedramcore_choose_req_want_reads <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + litedramcore_choose_req_want_reads <= 1'd1; + end + endcase +end +always @(*) begin + litedramcore_choose_req_want_writes <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_choose_req_want_writes <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_en0 <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + litedramcore_en0 <= 1'd1; + end + endcase +end +always @(*) begin + litedramcore_choose_req_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end + end + endcase +end +always @(*) begin + litedramcore_en1 <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_en1 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + end + endcase +end +assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock)); +assign litedramcore_interface_bank0_addr = rhs_self12; +assign litedramcore_interface_bank0_we = rhs_self13; +assign litedramcore_interface_bank0_valid = rhs_self14; +assign litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock)); +assign litedramcore_interface_bank1_addr = rhs_self15; +assign litedramcore_interface_bank1_we = rhs_self16; +assign litedramcore_interface_bank1_valid = rhs_self17; +assign litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock)); +assign litedramcore_interface_bank2_addr = rhs_self18; +assign litedramcore_interface_bank2_we = rhs_self19; +assign litedramcore_interface_bank2_valid = rhs_self20; +assign litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock)); +assign litedramcore_interface_bank3_addr = rhs_self21; +assign litedramcore_interface_bank3_we = rhs_self22; +assign litedramcore_interface_bank3_valid = rhs_self23; +assign litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock)); +assign litedramcore_interface_bank4_addr = rhs_self24; +assign litedramcore_interface_bank4_we = rhs_self25; +assign litedramcore_interface_bank4_valid = rhs_self26; +assign litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock)); +assign litedramcore_interface_bank5_addr = rhs_self27; +assign litedramcore_interface_bank5_we = rhs_self28; +assign litedramcore_interface_bank5_valid = rhs_self29; +assign litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock)); +assign litedramcore_interface_bank6_addr = rhs_self30; +assign litedramcore_interface_bank6_we = rhs_self31; +assign litedramcore_interface_bank6_valid = rhs_self32; +assign litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)}; +assign litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock)); +assign litedramcore_interface_bank7_addr = rhs_self33; +assign litedramcore_interface_bank7_we = rhs_self34; +assign litedramcore_interface_bank7_valid = rhs_self35; +assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready)); +assign user_port_wdata_ready = litedramcore_new_master_wdata_ready3; +assign user_port_rdata_valid = litedramcore_new_master_rdata_valid13; +always @(*) begin + litedramcore_interface_wdata <= 128'd0; + case ({litedramcore_new_master_wdata_ready3}) + 1'd1: begin + litedramcore_interface_wdata <= user_port_wdata_payload_data; + end + default: begin + litedramcore_interface_wdata <= 1'd0; + end + endcase +end +always @(*) begin + litedramcore_interface_wdata_we <= 16'd0; + case ({litedramcore_new_master_wdata_ready3}) + 1'd1: begin + litedramcore_interface_wdata_we <= user_port_wdata_payload_we; + end + default: begin + litedramcore_interface_wdata_we <= 1'd0; + end + endcase +end +assign user_port_rdata_payload_data = litedramcore_interface_rdata; +assign litedramcore_roundrobin0_grant = 1'd0; +assign litedramcore_roundrobin1_grant = 1'd0; +assign litedramcore_roundrobin2_grant = 1'd0; +assign litedramcore_roundrobin3_grant = 1'd0; +assign litedramcore_roundrobin4_grant = 1'd0; +assign litedramcore_roundrobin5_grant = 1'd0; +assign litedramcore_roundrobin6_grant = 1'd0; +assign litedramcore_roundrobin7_grant = 1'd0; +always @(*) begin + next_state <= 2'd0; + next_state <= state; + case (state) + 1'd1: begin + next_state <= 2'd2; + end + 2'd2: begin + next_state <= 1'd0; + end + default: begin + if ((interface0_cyc & interface0_stb)) begin + next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + interface0_ack <= 1'd0; + case (state) + 1'd1: begin + end + 2'd2: begin + interface0_ack <= 1'd1; + end + default: begin + end + endcase +end +always @(*) begin + interface0_dat_r <= 32'd0; + case (state) + 1'd1: begin + end + 2'd2: begin + interface0_dat_r <= interface1_dat_r; + end + default: begin + end + endcase +end +always @(*) begin + interface1_dat_w_next_value0 <= 32'd0; + case (state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + interface1_dat_w_next_value0 <= interface0_dat_w; + end + endcase +end +always @(*) begin + interface1_dat_w_next_value_ce0 <= 1'd0; + case (state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + interface1_dat_w_next_value_ce0 <= 1'd1; + end + endcase +end +always @(*) begin + interface1_adr_next_value1 <= 14'd0; + case (state) + 1'd1: begin + interface1_adr_next_value1 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((interface0_cyc & interface0_stb)) begin + interface1_adr_next_value1 <= interface0_adr[29:0]; + end + end + endcase +end +always @(*) begin + interface1_adr_next_value_ce1 <= 1'd0; + case (state) + 1'd1: begin + interface1_adr_next_value_ce1 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((interface0_cyc & interface0_stb)) begin + interface1_adr_next_value_ce1 <= 1'd1; + end + end + endcase +end +always @(*) begin + interface1_we_next_value2 <= 1'd0; + case (state) + 1'd1: begin + interface1_we_next_value2 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((interface0_cyc & interface0_stb)) begin + interface1_we_next_value2 <= (interface0_we & (interface0_sel != 1'd0)); + end + end + endcase +end +always @(*) begin + interface1_we_next_value_ce2 <= 1'd0; + case (state) + 1'd1: begin + interface1_we_next_value_ce2 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((interface0_cyc & interface0_stb)) begin + interface1_we_next_value_ce2 <= 1'd1; + end + end + endcase +end +assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); +assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; +always @(*) begin + csrbank0_init_done0_re <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_init_done0_re <= interface0_bank_bus_we; + end +end +always @(*) begin + csrbank0_init_done0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_init_done0_we <= (~interface0_bank_bus_we); + end +end +assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; +always @(*) begin + csrbank0_init_error0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_init_error0_we <= (~interface0_bank_bus_we); + end +end +always @(*) begin + csrbank0_init_error0_re <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_init_error0_re <= interface0_bank_bus_we; + end +end +assign csrbank0_init_done0_w = init_done_storage; +assign csrbank0_init_error0_w = init_error_storage; +assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); +assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; +always @(*) begin + csrbank1_dly_sel0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_dly_sel0_we <= (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dly_sel0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_dly_sel0_re <= interface1_bank_bus_we; + end +end +assign ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + ddrphy_rdly_dq_rst_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we); + end +end +always @(*) begin + ddrphy_rdly_dq_rst_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we; + end +end +assign ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + ddrphy_rdly_dq_inc_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we); + end +end +always @(*) begin + ddrphy_rdly_dq_inc_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we; + end +end +assign ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + end +end +always @(*) begin + ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + end +end +assign ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + ddrphy_rdly_dq_bitslip_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we; + end +end +always @(*) begin + ddrphy_rdly_dq_bitslip_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we); + end +end +assign ddrphy_burstdet_clr_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + ddrphy_burstdet_clr_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + ddrphy_burstdet_clr_re <= interface1_bank_bus_we; + end +end +always @(*) begin + ddrphy_burstdet_clr_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + ddrphy_burstdet_clr_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_burstdet_seen_r = interface1_bank_bus_dat_w[1:0]; +always @(*) begin + csrbank1_burstdet_seen_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + csrbank1_burstdet_seen_re <= interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_burstdet_seen_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + csrbank1_burstdet_seen_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dly_sel0_w = ddrphy_dly_sel_storage[1:0]; +assign csrbank1_burstdet_seen_w = ddrphy_burstdet_seen_status[1:0]; +assign ddrphy_burstdet_seen_we = csrbank1_burstdet_seen_we; +assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); +assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank2_dfii_control0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_dfii_control0_re <= interface2_bank_bus_we; + end +end +always @(*) begin + csrbank2_dfii_control0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_dfii_control0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank2_dfii_pi0_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we); + end +end +always @(*) begin + csrbank2_dfii_pi0_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; + end +end +assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; +always @(*) begin + litedramcore_phaseinjector0_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we; + end +end +always @(*) begin + litedramcore_phaseinjector0_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0]; +always @(*) begin + csrbank2_dfii_pi0_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin + csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; + end +end +always @(*) begin + csrbank2_dfii_pi0_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin + csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; +always @(*) begin + csrbank2_dfii_pi0_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin + csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we; + end +end +always @(*) begin + csrbank2_dfii_pi0_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin + csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_dfii_pi0_wrdata1_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin + csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we); + end +end +always @(*) begin + csrbank2_dfii_pi0_wrdata1_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin + csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we; + end +end +assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_dfii_pi0_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin + csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; + end +end +always @(*) begin + csrbank2_dfii_pi0_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin + csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_dfii_pi0_rddata1_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin + csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we); + end +end +always @(*) begin + csrbank2_dfii_pi0_rddata1_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin + csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we; + end +end +assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_dfii_pi0_rddata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin + csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we); + end +end +always @(*) begin + csrbank2_dfii_pi0_rddata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin + csrbank2_dfii_pi0_rddata0_re <= interface2_bank_bus_we; + end +end +assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[7:0]; +always @(*) begin + csrbank2_dfii_pi1_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin + csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; + end +end +always @(*) begin + csrbank2_dfii_pi1_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin + csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we); + end +end +assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; +always @(*) begin + litedramcore_phaseinjector1_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin + litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we); + end +end +always @(*) begin + litedramcore_phaseinjector1_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin + litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we; + end +end +assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0]; +always @(*) begin + csrbank2_dfii_pi1_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin + csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we; + end +end +always @(*) begin + csrbank2_dfii_pi1_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin + csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; +always @(*) begin + csrbank2_dfii_pi1_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin + csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we); + end +end +always @(*) begin + csrbank2_dfii_pi1_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin + csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we; + end +end +assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_dfii_pi1_wrdata1_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin + csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we; + end +end +always @(*) begin + csrbank2_dfii_pi1_wrdata1_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin + csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_dfii_pi1_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin + csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we); + end +end +always @(*) begin + csrbank2_dfii_pi1_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin + csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; + end +end +assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_dfii_pi1_rddata1_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin + csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we); + end +end +always @(*) begin + csrbank2_dfii_pi1_rddata1_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin + csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we; + end +end +assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_dfii_pi1_rddata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin + csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we; + end +end +always @(*) begin + csrbank2_dfii_pi1_rddata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin + csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we); + end +end +assign litedramcore_sel = litedramcore_storage[0]; +assign litedramcore_cke = litedramcore_storage[1]; +assign litedramcore_odt = litedramcore_storage[2]; +assign litedramcore_reset_n = litedramcore_storage[3]; +assign csrbank2_dfii_control0_w = litedramcore_storage[3:0]; +assign litedramcore_phaseinjector0_csrfield_cs = litedramcore_phaseinjector0_command_storage[0]; +assign litedramcore_phaseinjector0_csrfield_we = litedramcore_phaseinjector0_command_storage[1]; +assign litedramcore_phaseinjector0_csrfield_cas = litedramcore_phaseinjector0_command_storage[2]; +assign litedramcore_phaseinjector0_csrfield_ras = litedramcore_phaseinjector0_command_storage[3]; +assign litedramcore_phaseinjector0_csrfield_wren = litedramcore_phaseinjector0_command_storage[4]; +assign litedramcore_phaseinjector0_csrfield_rden = litedramcore_phaseinjector0_command_storage[5]; +assign litedramcore_phaseinjector0_csrfield_cs_top = litedramcore_phaseinjector0_command_storage[6]; +assign litedramcore_phaseinjector0_csrfield_cs_bottom = litedramcore_phaseinjector0_command_storage[7]; +assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[7:0]; +assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0]; +assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0]; +assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[63:32]; +assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0]; +assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_rddata_status[63:32]; +assign csrbank2_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_rddata_status[31:0]; +assign litedramcore_phaseinjector0_rddata_we = csrbank2_dfii_pi0_rddata0_we; +assign litedramcore_phaseinjector1_csrfield_cs = litedramcore_phaseinjector1_command_storage[0]; +assign litedramcore_phaseinjector1_csrfield_we = litedramcore_phaseinjector1_command_storage[1]; +assign litedramcore_phaseinjector1_csrfield_cas = litedramcore_phaseinjector1_command_storage[2]; +assign litedramcore_phaseinjector1_csrfield_ras = litedramcore_phaseinjector1_command_storage[3]; +assign litedramcore_phaseinjector1_csrfield_wren = litedramcore_phaseinjector1_command_storage[4]; +assign litedramcore_phaseinjector1_csrfield_rden = litedramcore_phaseinjector1_command_storage[5]; +assign litedramcore_phaseinjector1_csrfield_cs_top = litedramcore_phaseinjector1_command_storage[6]; +assign litedramcore_phaseinjector1_csrfield_cs_bottom = litedramcore_phaseinjector1_command_storage[7]; +assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[7:0]; +assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[14:0]; +assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0]; +assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[63:32]; +assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0]; +assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_rddata_status[63:32]; +assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_rddata_status[31:0]; +assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata0_we; +assign adr = interface1_adr; +assign we = interface1_we; +assign dat_w = interface1_dat_w; +assign interface1_dat_r = dat_r; +assign interface0_bank_bus_adr = adr; +assign interface1_bank_bus_adr = adr; +assign interface2_bank_bus_adr = adr; +assign interface0_bank_bus_we = we; +assign interface1_bank_bus_we = we; +assign interface2_bank_bus_we = we; +assign interface0_bank_bus_dat_w = dat_w; +assign interface1_bank_bus_dat_w = dat_w; +assign interface2_bank_bus_dat_w = dat_w; +assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); +always @(*) begin + rhs_self0 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_self0 <= litedramcore_choose_cmd_valids[0]; + end + 1'd1: begin + rhs_self0 <= litedramcore_choose_cmd_valids[1]; + end + 2'd2: begin + rhs_self0 <= litedramcore_choose_cmd_valids[2]; + end + 2'd3: begin + rhs_self0 <= litedramcore_choose_cmd_valids[3]; + end + 3'd4: begin + rhs_self0 <= litedramcore_choose_cmd_valids[4]; + end + 3'd5: begin + rhs_self0 <= litedramcore_choose_cmd_valids[5]; + end + 3'd6: begin + rhs_self0 <= litedramcore_choose_cmd_valids[6]; + end + default: begin + rhs_self0 <= litedramcore_choose_cmd_valids[7]; + end + endcase +end +always @(*) begin + rhs_self1 <= 15'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_self1 <= litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_self1 <= litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_self1 <= litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_self1 <= litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_self1 <= litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_self1 <= litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_self1 <= litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + rhs_self1 <= litedramcore_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_self2 <= 3'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_self2 <= litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_self2 <= litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_self2 <= litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_self2 <= litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_self2 <= litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_self2 <= litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_self2 <= litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_self2 <= litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_self3 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_self3 <= litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_self3 <= litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_self3 <= litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_self3 <= litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_self3 <= litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_self3 <= litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_self3 <= litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_self3 <= litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_self4 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_self4 <= litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_self4 <= litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_self4 <= litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_self4 <= litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_self4 <= litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_self4 <= litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_self4 <= litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_self4 <= litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_self5 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_self5 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_self5 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_self5 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_self5 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_self5 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_self5 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_self5 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_self5 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_self0 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_self0 <= litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_self0 <= litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_self0 <= litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_self0 <= litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_self0 <= litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_self0 <= litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_self0 <= litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + t_self0 <= litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_self1 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_self1 <= litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_self1 <= litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_self1 <= litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_self1 <= litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_self1 <= litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_self1 <= litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_self1 <= litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + t_self1 <= litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_self2 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_self2 <= litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_self2 <= litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_self2 <= litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_self2 <= litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_self2 <= litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_self2 <= litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_self2 <= litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + t_self2 <= litedramcore_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self6 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_self6 <= litedramcore_choose_req_valids[0]; + end + 1'd1: begin + rhs_self6 <= litedramcore_choose_req_valids[1]; + end + 2'd2: begin + rhs_self6 <= litedramcore_choose_req_valids[2]; + end + 2'd3: begin + rhs_self6 <= litedramcore_choose_req_valids[3]; + end + 3'd4: begin + rhs_self6 <= litedramcore_choose_req_valids[4]; + end + 3'd5: begin + rhs_self6 <= litedramcore_choose_req_valids[5]; + end + 3'd6: begin + rhs_self6 <= litedramcore_choose_req_valids[6]; + end + default: begin + rhs_self6 <= litedramcore_choose_req_valids[7]; + end + endcase +end +always @(*) begin + rhs_self7 <= 15'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_self7 <= litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_self7 <= litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_self7 <= litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_self7 <= litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_self7 <= litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_self7 <= litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_self7 <= litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + rhs_self7 <= litedramcore_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_self8 <= 3'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_self8 <= litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_self8 <= litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_self8 <= litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_self8 <= litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_self8 <= litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_self8 <= litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_self8 <= litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_self8 <= litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_self9 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_self9 <= litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_self9 <= litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_self9 <= litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_self9 <= litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_self9 <= litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_self9 <= litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_self9 <= litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_self9 <= litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_self10 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_self10 <= litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_self10 <= litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_self10 <= litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_self10 <= litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_self10 <= litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_self10 <= litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_self10 <= litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_self10 <= litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_self11 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_self11 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_self11 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_self11 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_self11 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_self11 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_self11 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_self11 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_self11 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_self3 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_self3 <= litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_self3 <= litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_self3 <= litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_self3 <= litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_self3 <= litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_self3 <= litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_self3 <= litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + t_self3 <= litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_self4 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_self4 <= litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_self4 <= litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_self4 <= litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_self4 <= litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_self4 <= litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_self4 <= litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_self4 <= litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + t_self4 <= litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_self5 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_self5 <= litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_self5 <= litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_self5 <= litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_self5 <= litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_self5 <= litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_self5 <= litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_self5 <= litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + t_self5 <= litedramcore_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self12 <= 22'd0; + case (litedramcore_roundrobin0_grant) + default: begin + rhs_self12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_self13 <= 1'd0; + case (litedramcore_roundrobin0_grant) + default: begin + rhs_self13 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self14 <= 1'd0; + case (litedramcore_roundrobin0_grant) + default: begin + rhs_self14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_self15 <= 22'd0; + case (litedramcore_roundrobin1_grant) + default: begin + rhs_self15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_self16 <= 1'd0; + case (litedramcore_roundrobin1_grant) + default: begin + rhs_self16 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self17 <= 1'd0; + case (litedramcore_roundrobin1_grant) + default: begin + rhs_self17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_self18 <= 22'd0; + case (litedramcore_roundrobin2_grant) + default: begin + rhs_self18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_self19 <= 1'd0; + case (litedramcore_roundrobin2_grant) + default: begin + rhs_self19 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self20 <= 1'd0; + case (litedramcore_roundrobin2_grant) + default: begin + rhs_self20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_self21 <= 22'd0; + case (litedramcore_roundrobin3_grant) + default: begin + rhs_self21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_self22 <= 1'd0; + case (litedramcore_roundrobin3_grant) + default: begin + rhs_self22 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self23 <= 1'd0; + case (litedramcore_roundrobin3_grant) + default: begin + rhs_self23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_self24 <= 22'd0; + case (litedramcore_roundrobin4_grant) + default: begin + rhs_self24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_self25 <= 1'd0; + case (litedramcore_roundrobin4_grant) + default: begin + rhs_self25 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self26 <= 1'd0; + case (litedramcore_roundrobin4_grant) + default: begin + rhs_self26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_self27 <= 22'd0; + case (litedramcore_roundrobin5_grant) + default: begin + rhs_self27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_self28 <= 1'd0; + case (litedramcore_roundrobin5_grant) + default: begin + rhs_self28 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self29 <= 1'd0; + case (litedramcore_roundrobin5_grant) + default: begin + rhs_self29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_self30 <= 22'd0; + case (litedramcore_roundrobin6_grant) + default: begin + rhs_self30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_self31 <= 1'd0; + case (litedramcore_roundrobin6_grant) + default: begin + rhs_self31 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self32 <= 1'd0; + case (litedramcore_roundrobin6_grant) + default: begin + rhs_self32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_self33 <= 22'd0; + case (litedramcore_roundrobin7_grant) + default: begin + rhs_self33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_self34 <= 1'd0; + case (litedramcore_roundrobin7_grant) + default: begin + rhs_self34 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_self35 <= 1'd0; + case (litedramcore_roundrobin7_grant) + default: begin + rhs_self35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + self0 <= 3'd0; + case (litedramcore_steerer0) + 1'd0: begin + self0 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + self0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + self0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + self0 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + self1 <= 15'd0; + case (litedramcore_steerer0) + 1'd0: begin + self1 <= litedramcore_nop_a; + end + 1'd1: begin + self1 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + self1 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + self1 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + self2 <= 1'd0; + case (litedramcore_steerer0) + 1'd0: begin + self2 <= 1'd0; + end + 1'd1: begin + self2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + self2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + self2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + self3 <= 1'd0; + case (litedramcore_steerer0) + 1'd0: begin + self3 <= 1'd0; + end + 1'd1: begin + self3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + self3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + self3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + self4 <= 1'd0; + case (litedramcore_steerer0) + 1'd0: begin + self4 <= 1'd0; + end + 1'd1: begin + self4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + self4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + self4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + self5 <= 1'd0; + case (litedramcore_steerer0) + 1'd0: begin + self5 <= 1'd0; + end + 1'd1: begin + self5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + self5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + self5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + self6 <= 1'd0; + case (litedramcore_steerer0) + 1'd0: begin + self6 <= 1'd0; + end + 1'd1: begin + self6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + self6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + self6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + self7 <= 3'd0; + case (litedramcore_steerer1) + 1'd0: begin + self7 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + self7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + self7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + self7 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + self8 <= 15'd0; + case (litedramcore_steerer1) + 1'd0: begin + self8 <= litedramcore_nop_a; + end + 1'd1: begin + self8 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + self8 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + self8 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + self9 <= 1'd0; + case (litedramcore_steerer1) + 1'd0: begin + self9 <= 1'd0; + end + 1'd1: begin + self9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + self9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + self9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + self10 <= 1'd0; + case (litedramcore_steerer1) + 1'd0: begin + self10 <= 1'd0; + end + 1'd1: begin + self10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + self10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + self10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + self11 <= 1'd0; + case (litedramcore_steerer1) + 1'd0: begin + self11 <= 1'd0; + end + 1'd1: begin + self11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + self11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + self11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + self12 <= 1'd0; + case (litedramcore_steerer1) + 1'd0: begin + self12 <= 1'd0; + end + 1'd1: begin + self12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + self12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + self12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + self13 <= 1'd0; + case (litedramcore_steerer1) + 1'd0: begin + self13 <= 1'd0; + end + 1'd1: begin + self13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + self13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + self13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +assign ddrphy_lock1 = multiregimpl1; + + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + +always @(posedge init_clk) begin + ddrphy_lock_d <= ddrphy_lock1; + if ((ddrphy_trigger == 4'd8)) begin + ddrphy_freeze <= 1'd1; + end + if ((ddrphy_trigger == 5'd16)) begin + ddrphy_stop1 <= 1'd1; + end + if ((ddrphy_trigger == 5'd24)) begin + ddrphy_reset1 <= 1'd1; + end + if ((ddrphy_trigger == 6'd32)) begin + ddrphy_reset1 <= 1'd0; + end + if ((ddrphy_trigger == 6'd40)) begin + ddrphy_stop1 <= 1'd0; + end + if ((ddrphy_trigger == 6'd48)) begin + ddrphy_freeze <= 1'd0; + end + if ((ddrphy_trigger == 6'd56)) begin + ddrphy_pause1 <= 1'd1; + end + if ((ddrphy_trigger == 7'd64)) begin + ddrphy_update <= 1'd1; + end + if ((ddrphy_trigger == 7'd72)) begin + ddrphy_update <= 1'd0; + end + if ((ddrphy_trigger == 7'd80)) begin + ddrphy_pause1 <= 1'd0; + end + if ((ddrphy_trigger == 7'd80)) begin + ddrphy_trigger <= 1'd0; + end else begin + if ((ddrphy_trigger != 1'd0)) begin + ddrphy_trigger <= (ddrphy_trigger + 1'd1); + end else begin + if (ddrphy_new_lock) begin + ddrphy_trigger <= 1'd1; + end + end + end + if (init_rst) begin + ddrphy_update <= 1'd0; + ddrphy_stop1 <= 1'd0; + ddrphy_freeze <= 1'd0; + ddrphy_pause1 <= 1'd0; + ddrphy_reset1 <= 1'd0; + ddrphy_lock_d <= 1'd0; + ddrphy_trigger <= 7'd0; + end + multiregimpl0 <= ddrphy_lock0; + multiregimpl1 <= multiregimpl0; +end + +always @(posedge por_clk) begin + if ((~crg_por_done)) begin + crg_por_count <= (crg_por_count - 1'd1); + end +end + +always @(posedge sys_clk) begin + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_rst_re)) begin + ddrphy_rdly0 <= 1'd0; + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_inc_re)) begin + ddrphy_rdly0 <= (ddrphy_rdly0 + 1'd1); + end + ddrphy_burstdet_d0 <= ddrphy_burstdet0; + if (ddrphy_burstdet_clr_re) begin + ddrphy_burstdet_seen_status[0] <= 1'd0; + end + if ((ddrphy_burstdet0 & (~ddrphy_burstdet_d0))) begin + ddrphy_burstdet_seen_status[0] <= 1'd1; + end + ddrphy_dm_o_data_d0 <= ddrphy_dm_o_data0; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dm_o_data_muxed0 <= ddrphy_dm_o_data0[3:0]; + end + 1'd1: begin + ddrphy_dm_o_data_muxed0 <= ddrphy_dm_o_data_d0[7:4]; + end + endcase + ddrphy_dq_o_data_d0 <= ddrphy_dq_o_data0; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed0 <= ddrphy_dq_o_data0[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed0 <= ddrphy_dq_o_data_d0[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d0 <= ddrphy_bitslip0_o; + ddrphy_dq_o_data_d1 <= ddrphy_dq_o_data1; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed1 <= ddrphy_dq_o_data1[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed1 <= ddrphy_dq_o_data_d1[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d1 <= ddrphy_bitslip1_o; + ddrphy_dq_o_data_d2 <= ddrphy_dq_o_data2; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed2 <= ddrphy_dq_o_data2[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed2 <= ddrphy_dq_o_data_d2[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d2 <= ddrphy_bitslip2_o; + ddrphy_dq_o_data_d3 <= ddrphy_dq_o_data3; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed3 <= ddrphy_dq_o_data3[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed3 <= ddrphy_dq_o_data_d3[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d3 <= ddrphy_bitslip3_o; + ddrphy_dq_o_data_d4 <= ddrphy_dq_o_data4; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed4 <= ddrphy_dq_o_data4[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed4 <= ddrphy_dq_o_data_d4[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d4 <= ddrphy_bitslip4_o; + ddrphy_dq_o_data_d5 <= ddrphy_dq_o_data5; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed5 <= ddrphy_dq_o_data5[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed5 <= ddrphy_dq_o_data_d5[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d5 <= ddrphy_bitslip5_o; + ddrphy_dq_o_data_d6 <= ddrphy_dq_o_data6; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed6 <= ddrphy_dq_o_data6[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed6 <= ddrphy_dq_o_data_d6[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d6 <= ddrphy_bitslip6_o; + ddrphy_dq_o_data_d7 <= ddrphy_dq_o_data7; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed7 <= ddrphy_dq_o_data7[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed7 <= ddrphy_dq_o_data_d7[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d7 <= ddrphy_bitslip7_o; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_rst_re)) begin + ddrphy_rdly1 <= 1'd0; + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_inc_re)) begin + ddrphy_rdly1 <= (ddrphy_rdly1 + 1'd1); + end + ddrphy_burstdet_d1 <= ddrphy_burstdet1; + if (ddrphy_burstdet_clr_re) begin + ddrphy_burstdet_seen_status[1] <= 1'd0; + end + if ((ddrphy_burstdet1 & (~ddrphy_burstdet_d1))) begin + ddrphy_burstdet_seen_status[1] <= 1'd1; + end + ddrphy_dm_o_data_d1 <= ddrphy_dm_o_data1; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dm_o_data_muxed1 <= ddrphy_dm_o_data1[3:0]; + end + 1'd1: begin + ddrphy_dm_o_data_muxed1 <= ddrphy_dm_o_data_d1[7:4]; + end + endcase + ddrphy_dq_o_data_d8 <= ddrphy_dq_o_data8; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed8 <= ddrphy_dq_o_data8[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed8 <= ddrphy_dq_o_data_d8[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d8 <= ddrphy_bitslip8_o; + ddrphy_dq_o_data_d9 <= ddrphy_dq_o_data9; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed9 <= ddrphy_dq_o_data9[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed9 <= ddrphy_dq_o_data_d9[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d9 <= ddrphy_bitslip9_o; + ddrphy_dq_o_data_d10 <= ddrphy_dq_o_data10; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed10 <= ddrphy_dq_o_data10[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed10 <= ddrphy_dq_o_data_d10[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d10 <= ddrphy_bitslip10_o; + ddrphy_dq_o_data_d11 <= ddrphy_dq_o_data11; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed11 <= ddrphy_dq_o_data11[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed11 <= ddrphy_dq_o_data_d11[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d11 <= ddrphy_bitslip11_o; + ddrphy_dq_o_data_d12 <= ddrphy_dq_o_data12; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed12 <= ddrphy_dq_o_data12[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed12 <= ddrphy_dq_o_data_d12[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d12 <= ddrphy_bitslip12_o; + ddrphy_dq_o_data_d13 <= ddrphy_dq_o_data13; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed13 <= ddrphy_dq_o_data13[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed13 <= ddrphy_dq_o_data_d13[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d13 <= ddrphy_bitslip13_o; + ddrphy_dq_o_data_d14 <= ddrphy_dq_o_data14; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed14 <= ddrphy_dq_o_data14[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed14 <= ddrphy_dq_o_data_d14[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d14 <= ddrphy_bitslip14_o; + ddrphy_dq_o_data_d15 <= ddrphy_dq_o_data15; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed15 <= ddrphy_dq_o_data15[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed15 <= ddrphy_dq_o_data_d15[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d15 <= ddrphy_bitslip15_o; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip0_value <= (ddrphy_bitslip0_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip0_value <= 1'd0; + end + ddrphy_bitslip0_r <= {ddrphy_bitslip0_i, ddrphy_bitslip0_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip1_value <= (ddrphy_bitslip1_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip1_value <= 1'd0; + end + ddrphy_bitslip1_r <= {ddrphy_bitslip1_i, ddrphy_bitslip1_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip2_value <= (ddrphy_bitslip2_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip2_value <= 1'd0; + end + ddrphy_bitslip2_r <= {ddrphy_bitslip2_i, ddrphy_bitslip2_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip3_value <= (ddrphy_bitslip3_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip3_value <= 1'd0; + end + ddrphy_bitslip3_r <= {ddrphy_bitslip3_i, ddrphy_bitslip3_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip4_value <= (ddrphy_bitslip4_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip4_value <= 1'd0; + end + ddrphy_bitslip4_r <= {ddrphy_bitslip4_i, ddrphy_bitslip4_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip5_value <= (ddrphy_bitslip5_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip5_value <= 1'd0; + end + ddrphy_bitslip5_r <= {ddrphy_bitslip5_i, ddrphy_bitslip5_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip6_value <= (ddrphy_bitslip6_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip6_value <= 1'd0; + end + ddrphy_bitslip6_r <= {ddrphy_bitslip6_i, ddrphy_bitslip6_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip7_value <= (ddrphy_bitslip7_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip7_value <= 1'd0; + end + ddrphy_bitslip7_r <= {ddrphy_bitslip7_i, ddrphy_bitslip7_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip8_value <= (ddrphy_bitslip8_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip8_value <= 1'd0; + end + ddrphy_bitslip8_r <= {ddrphy_bitslip8_i, ddrphy_bitslip8_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip9_value <= (ddrphy_bitslip9_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip9_value <= 1'd0; + end + ddrphy_bitslip9_r <= {ddrphy_bitslip9_i, ddrphy_bitslip9_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip10_value <= (ddrphy_bitslip10_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip10_value <= 1'd0; + end + ddrphy_bitslip10_r <= {ddrphy_bitslip10_i, ddrphy_bitslip10_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip11_value <= (ddrphy_bitslip11_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip11_value <= 1'd0; + end + ddrphy_bitslip11_r <= {ddrphy_bitslip11_i, ddrphy_bitslip11_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip12_value <= (ddrphy_bitslip12_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip12_value <= 1'd0; + end + ddrphy_bitslip12_r <= {ddrphy_bitslip12_i, ddrphy_bitslip12_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip13_value <= (ddrphy_bitslip13_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip13_value <= 1'd0; + end + ddrphy_bitslip13_r <= {ddrphy_bitslip13_i, ddrphy_bitslip13_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip14_value <= (ddrphy_bitslip14_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip14_value <= 1'd0; + end + ddrphy_bitslip14_r <= {ddrphy_bitslip14_i, ddrphy_bitslip14_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip15_value <= (ddrphy_bitslip15_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip15_value <= 1'd0; + end + ddrphy_bitslip15_r <= {ddrphy_bitslip15_i, ddrphy_bitslip15_r[7:4]}; + ddrphy_rddata_en_tappeddelayline0 <= (ddrphy_dfi_p0_rddata_en | ddrphy_dfi_p1_rddata_en); + ddrphy_rddata_en_tappeddelayline1 <= ddrphy_rddata_en_tappeddelayline0; + ddrphy_rddata_en_tappeddelayline2 <= ddrphy_rddata_en_tappeddelayline1; + ddrphy_rddata_en_tappeddelayline3 <= ddrphy_rddata_en_tappeddelayline2; + ddrphy_rddata_en_tappeddelayline4 <= ddrphy_rddata_en_tappeddelayline3; + ddrphy_rddata_en_tappeddelayline5 <= ddrphy_rddata_en_tappeddelayline4; + ddrphy_rddata_en_tappeddelayline6 <= ddrphy_rddata_en_tappeddelayline5; + ddrphy_rddata_en_tappeddelayline7 <= ddrphy_rddata_en_tappeddelayline6; + ddrphy_rddata_en_tappeddelayline8 <= ddrphy_rddata_en_tappeddelayline7; + ddrphy_rddata_en_tappeddelayline9 <= ddrphy_rddata_en_tappeddelayline8; + ddrphy_rddata_en_tappeddelayline10 <= ddrphy_rddata_en_tappeddelayline9; + ddrphy_rddata_en_tappeddelayline11 <= ddrphy_rddata_en_tappeddelayline10; + ddrphy_rddata_en_tappeddelayline12 <= ddrphy_rddata_en_tappeddelayline11; + ddrphy_wrdata_en_tappeddelayline0 <= (ddrphy_dfi_p0_wrdata_en | ddrphy_dfi_p1_wrdata_en); + ddrphy_wrdata_en_tappeddelayline1 <= ddrphy_wrdata_en_tappeddelayline0; + ddrphy_wrdata_en_tappeddelayline2 <= ddrphy_wrdata_en_tappeddelayline1; + ddrphy_wrdata_en_tappeddelayline3 <= ddrphy_wrdata_en_tappeddelayline2; + ddrphy_wrdata_en_tappeddelayline4 <= ddrphy_wrdata_en_tappeddelayline3; + ddrphy_wrdata_en_tappeddelayline5 <= ddrphy_wrdata_en_tappeddelayline4; + ddrphy_wrdata_en_tappeddelayline6 <= ddrphy_wrdata_en_tappeddelayline5; + if (litedramcore_csr_dfi_p0_rddata_valid) begin + litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata; + end + if (litedramcore_csr_dfi_p1_rddata_valid) begin + litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata; + end + if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin + litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); + end else begin + litedramcore_timer_count1 <= 9'd390; + end + litedramcore_postponer_req_o <= 1'd0; + if (litedramcore_postponer_req_i) begin + litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); + if ((litedramcore_postponer_count == 1'd0)) begin + litedramcore_postponer_count <= 1'd0; + litedramcore_postponer_req_o <= 1'd1; + end + end + if (litedramcore_sequencer_start0) begin + litedramcore_sequencer_count <= 1'd0; + end else begin + if (litedramcore_sequencer_done1) begin + if ((litedramcore_sequencer_count != 1'd0)) begin + litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); + end + end + end + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_sequencer_done1 <= 1'd0; + if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_trigger == 1'd0))) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_sequencer_trigger == 2'd2)) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd1; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd0; + end + if ((litedramcore_sequencer_trigger == 7'd106)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_sequencer_done1 <= 1'd1; + end + if ((litedramcore_sequencer_trigger == 7'd106)) begin + litedramcore_sequencer_trigger <= 1'd0; + end else begin + if ((litedramcore_sequencer_trigger != 1'd0)) begin + litedramcore_sequencer_trigger <= (litedramcore_sequencer_trigger + 1'd1); + end else begin + if (litedramcore_sequencer_start1) begin + litedramcore_sequencer_trigger <= 1'd1; + end + end + end + if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin + litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); + end else begin + litedramcore_zqcs_timer_count1 <= 26'd49999999; + end + litedramcore_zqcs_executer_done <= 1'd0; + if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_trigger == 1'd0))) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_zqcs_executer_trigger == 2'd2)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_zqcs_executer_trigger == 6'd34)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_zqcs_executer_done <= 1'd1; + end + if ((litedramcore_zqcs_executer_trigger == 6'd34)) begin + litedramcore_zqcs_executer_trigger <= 1'd0; + end else begin + if ((litedramcore_zqcs_executer_trigger != 1'd0)) begin + litedramcore_zqcs_executer_trigger <= (litedramcore_zqcs_executer_trigger + 1'd1); + end else begin + if (litedramcore_zqcs_executer_start) begin + litedramcore_zqcs_executer_trigger <= 1'd1; + end + end + end + litedramcore_refresher_state <= litedramcore_refresher_next_state; + if (litedramcore_bankmachine0_row_close) begin + litedramcore_bankmachine0_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine0_row_open) begin + litedramcore_bankmachine0_row_opened <= 1'd1; + litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin + litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1); + end + if (litedramcore_bankmachine0_do_read) begin + litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1); + end + if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin + if ((~litedramcore_bankmachine0_do_read)) begin + litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine0_do_read) begin + litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1); + end + end + if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin + litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid; + litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first; + litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last; + litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we; + litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine0_twtpcon_valid) begin + litedramcore_bankmachine0_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_twtpcon_ready)) begin + litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine0_trccon_valid) begin + litedramcore_bankmachine0_trccon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine0_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_trccon_ready)) begin + litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); + if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin + litedramcore_bankmachine0_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine0_trascon_valid) begin + litedramcore_bankmachine0_trascon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine0_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); + if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin + litedramcore_bankmachine0_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state; + if (litedramcore_bankmachine1_row_close) begin + litedramcore_bankmachine1_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine1_row_open) begin + litedramcore_bankmachine1_row_opened <= 1'd1; + litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin + litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1); + end + if (litedramcore_bankmachine1_do_read) begin + litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1); + end + if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin + if ((~litedramcore_bankmachine1_do_read)) begin + litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine1_do_read) begin + litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1); + end + end + if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin + litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid; + litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first; + litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last; + litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we; + litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine1_twtpcon_valid) begin + litedramcore_bankmachine1_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_twtpcon_ready)) begin + litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine1_trccon_valid) begin + litedramcore_bankmachine1_trccon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine1_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_trccon_ready)) begin + litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); + if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin + litedramcore_bankmachine1_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine1_trascon_valid) begin + litedramcore_bankmachine1_trascon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine1_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); + if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin + litedramcore_bankmachine1_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state; + if (litedramcore_bankmachine2_row_close) begin + litedramcore_bankmachine2_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine2_row_open) begin + litedramcore_bankmachine2_row_opened <= 1'd1; + litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin + litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1); + end + if (litedramcore_bankmachine2_do_read) begin + litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1); + end + if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin + if ((~litedramcore_bankmachine2_do_read)) begin + litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine2_do_read) begin + litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1); + end + end + if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin + litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid; + litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first; + litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last; + litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we; + litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine2_twtpcon_valid) begin + litedramcore_bankmachine2_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_twtpcon_ready)) begin + litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine2_trccon_valid) begin + litedramcore_bankmachine2_trccon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine2_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_trccon_ready)) begin + litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); + if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin + litedramcore_bankmachine2_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine2_trascon_valid) begin + litedramcore_bankmachine2_trascon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine2_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); + if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin + litedramcore_bankmachine2_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state; + if (litedramcore_bankmachine3_row_close) begin + litedramcore_bankmachine3_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine3_row_open) begin + litedramcore_bankmachine3_row_opened <= 1'd1; + litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin + litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1); + end + if (litedramcore_bankmachine3_do_read) begin + litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1); + end + if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin + if ((~litedramcore_bankmachine3_do_read)) begin + litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine3_do_read) begin + litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1); + end + end + if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin + litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid; + litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first; + litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last; + litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we; + litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine3_twtpcon_valid) begin + litedramcore_bankmachine3_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_twtpcon_ready)) begin + litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine3_trccon_valid) begin + litedramcore_bankmachine3_trccon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine3_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_trccon_ready)) begin + litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); + if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin + litedramcore_bankmachine3_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine3_trascon_valid) begin + litedramcore_bankmachine3_trascon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine3_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); + if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin + litedramcore_bankmachine3_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state; + if (litedramcore_bankmachine4_row_close) begin + litedramcore_bankmachine4_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine4_row_open) begin + litedramcore_bankmachine4_row_opened <= 1'd1; + litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin + litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1); + end + if (litedramcore_bankmachine4_do_read) begin + litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1); + end + if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin + if ((~litedramcore_bankmachine4_do_read)) begin + litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine4_do_read) begin + litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1); + end + end + if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin + litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid; + litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first; + litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last; + litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we; + litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine4_twtpcon_valid) begin + litedramcore_bankmachine4_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_twtpcon_ready)) begin + litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine4_trccon_valid) begin + litedramcore_bankmachine4_trccon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine4_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_trccon_ready)) begin + litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); + if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin + litedramcore_bankmachine4_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine4_trascon_valid) begin + litedramcore_bankmachine4_trascon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine4_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); + if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin + litedramcore_bankmachine4_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state; + if (litedramcore_bankmachine5_row_close) begin + litedramcore_bankmachine5_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine5_row_open) begin + litedramcore_bankmachine5_row_opened <= 1'd1; + litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin + litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1); + end + if (litedramcore_bankmachine5_do_read) begin + litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1); + end + if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin + if ((~litedramcore_bankmachine5_do_read)) begin + litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine5_do_read) begin + litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1); + end + end + if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin + litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid; + litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first; + litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last; + litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we; + litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine5_twtpcon_valid) begin + litedramcore_bankmachine5_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_twtpcon_ready)) begin + litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine5_trccon_valid) begin + litedramcore_bankmachine5_trccon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine5_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_trccon_ready)) begin + litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); + if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin + litedramcore_bankmachine5_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine5_trascon_valid) begin + litedramcore_bankmachine5_trascon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine5_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); + if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin + litedramcore_bankmachine5_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state; + if (litedramcore_bankmachine6_row_close) begin + litedramcore_bankmachine6_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine6_row_open) begin + litedramcore_bankmachine6_row_opened <= 1'd1; + litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin + litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1); + end + if (litedramcore_bankmachine6_do_read) begin + litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1); + end + if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin + if ((~litedramcore_bankmachine6_do_read)) begin + litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine6_do_read) begin + litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1); + end + end + if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin + litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid; + litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first; + litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last; + litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we; + litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine6_twtpcon_valid) begin + litedramcore_bankmachine6_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_twtpcon_ready)) begin + litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine6_trccon_valid) begin + litedramcore_bankmachine6_trccon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine6_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_trccon_ready)) begin + litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); + if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin + litedramcore_bankmachine6_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine6_trascon_valid) begin + litedramcore_bankmachine6_trascon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine6_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); + if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin + litedramcore_bankmachine6_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state; + if (litedramcore_bankmachine7_row_close) begin + litedramcore_bankmachine7_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine7_row_open) begin + litedramcore_bankmachine7_row_opened <= 1'd1; + litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin + litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1); + end + if (litedramcore_bankmachine7_do_read) begin + litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1); + end + if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin + if ((~litedramcore_bankmachine7_do_read)) begin + litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine7_do_read) begin + litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1); + end + end + if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin + litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid; + litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first; + litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last; + litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we; + litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine7_twtpcon_valid) begin + litedramcore_bankmachine7_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_twtpcon_ready)) begin + litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine7_trccon_valid) begin + litedramcore_bankmachine7_trccon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine7_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_trccon_ready)) begin + litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); + if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin + litedramcore_bankmachine7_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine7_trascon_valid) begin + litedramcore_bankmachine7_trascon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine7_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); + if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin + litedramcore_bankmachine7_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state; + if ((~litedramcore_en0)) begin + litedramcore_time0 <= 5'd31; + end else begin + if ((~litedramcore_max_time0)) begin + litedramcore_time0 <= (litedramcore_time0 - 1'd1); + end + end + if ((~litedramcore_en1)) begin + litedramcore_time1 <= 4'd15; + end else begin + if ((~litedramcore_max_time1)) begin + litedramcore_time1 <= (litedramcore_time1 - 1'd1); + end + end + if (litedramcore_choose_cmd_ce) begin + case (litedramcore_choose_cmd_grant) + 1'd0: begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + if (litedramcore_choose_req_ce) begin + case (litedramcore_choose_req_grant) + 1'd0: begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + litedramcore_dfi_p0_cs_n <= 1'd0; + litedramcore_dfi_p0_bank <= self0; + litedramcore_dfi_p0_address <= self1; + litedramcore_dfi_p0_cas_n <= (~self2); + litedramcore_dfi_p0_ras_n <= (~self3); + litedramcore_dfi_p0_we_n <= (~self4); + litedramcore_dfi_p0_rddata_en <= self5; + litedramcore_dfi_p0_wrdata_en <= self6; + litedramcore_dfi_p1_cs_n <= 1'd0; + litedramcore_dfi_p1_bank <= self7; + litedramcore_dfi_p1_address <= self8; + litedramcore_dfi_p1_cas_n <= (~self9); + litedramcore_dfi_p1_ras_n <= (~self10); + litedramcore_dfi_p1_we_n <= (~self11); + litedramcore_dfi_p1_rddata_en <= self12; + litedramcore_dfi_p1_wrdata_en <= self13; + if (litedramcore_trrdcon_valid) begin + litedramcore_trrdcon_count <= 1'd1; + if (1'd0) begin + litedramcore_trrdcon_ready <= 1'd1; + end else begin + litedramcore_trrdcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_trrdcon_ready)) begin + litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); + if ((litedramcore_trrdcon_count == 1'd1)) begin + litedramcore_trrdcon_ready <= 1'd1; + end + end + end + litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; + if ((litedramcore_tfawcon_count < 3'd4)) begin + if ((litedramcore_tfawcon_count == 2'd3)) begin + litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); + end else begin + litedramcore_tfawcon_ready <= 1'd1; + end + end + if (litedramcore_tccdcon_valid) begin + litedramcore_tccdcon_count <= 1'd1; + if (1'd0) begin + litedramcore_tccdcon_ready <= 1'd1; + end else begin + litedramcore_tccdcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_tccdcon_ready)) begin + litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); + if ((litedramcore_tccdcon_count == 1'd1)) begin + litedramcore_tccdcon_ready <= 1'd1; + end + end + end + if (litedramcore_twtrcon_valid) begin + litedramcore_twtrcon_count <= 3'd6; + if (1'd0) begin + litedramcore_twtrcon_ready <= 1'd1; + end else begin + litedramcore_twtrcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_twtrcon_ready)) begin + litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); + if ((litedramcore_twtrcon_count == 1'd1)) begin + litedramcore_twtrcon_ready <= 1'd1; + end + end + end + litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state; + litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); + litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0; + litedramcore_new_master_wdata_ready2 <= litedramcore_new_master_wdata_ready1; + litedramcore_new_master_wdata_ready3 <= litedramcore_new_master_wdata_ready2; + litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); + litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0; + litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1; + litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2; + litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3; + litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4; + litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5; + litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6; + litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7; + litedramcore_new_master_rdata_valid9 <= litedramcore_new_master_rdata_valid8; + litedramcore_new_master_rdata_valid10 <= litedramcore_new_master_rdata_valid9; + litedramcore_new_master_rdata_valid11 <= litedramcore_new_master_rdata_valid10; + litedramcore_new_master_rdata_valid12 <= litedramcore_new_master_rdata_valid11; + litedramcore_new_master_rdata_valid13 <= litedramcore_new_master_rdata_valid12; + state <= next_state; + if (interface1_dat_w_next_value_ce0) begin + interface1_dat_w <= interface1_dat_w_next_value0; + end + if (interface1_adr_next_value_ce1) begin + interface1_adr <= interface1_adr_next_value1; + end + if (interface1_we_next_value_ce2) begin + interface1_we <= interface1_we_next_value2; + end + interface0_bank_bus_dat_r <= 1'd0; + if (csrbank0_sel) begin + case (interface0_bank_bus_adr[8:0]) + 1'd0: begin + interface0_bank_bus_dat_r <= csrbank0_init_done0_w; + end + 1'd1: begin + interface0_bank_bus_dat_r <= csrbank0_init_error0_w; + end + endcase + end + if (csrbank0_init_done0_re) begin + init_done_storage <= csrbank0_init_done0_r; + end + init_done_re <= csrbank0_init_done0_re; + if (csrbank0_init_error0_re) begin + init_error_storage <= csrbank0_init_error0_r; + end + init_error_re <= csrbank0_init_error0_re; + interface1_bank_bus_dat_r <= 1'd0; + if (csrbank1_sel) begin + case (interface1_bank_bus_adr[8:0]) + 1'd0: begin + interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w; + end + 1'd1: begin + interface1_bank_bus_dat_r <= ddrphy_rdly_dq_rst_w; + end + 2'd2: begin + interface1_bank_bus_dat_r <= ddrphy_rdly_dq_inc_w; + end + 2'd3: begin + interface1_bank_bus_dat_r <= ddrphy_rdly_dq_bitslip_rst_w; + end + 3'd4: begin + interface1_bank_bus_dat_r <= ddrphy_rdly_dq_bitslip_w; + end + 3'd5: begin + interface1_bank_bus_dat_r <= ddrphy_burstdet_clr_w; + end + 3'd6: begin + interface1_bank_bus_dat_r <= csrbank1_burstdet_seen_w; + end + endcase + end + if (csrbank1_dly_sel0_re) begin + ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r; + end + ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; + ddrphy_burstdet_seen_re <= csrbank1_burstdet_seen_re; + interface2_bank_bus_dat_r <= 1'd0; + if (csrbank2_sel) begin + case (interface2_bank_bus_adr[8:0]) + 1'd0: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; + end + 1'd1: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w; + end + 2'd2: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; + end + 2'd3: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; + end + 3'd4: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; + end + 3'd5: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w; + end + 3'd6: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; + end + 3'd7: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w; + end + 4'd8: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w; + end + 4'd9: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; + end + 4'd10: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; + end + 4'd11: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; + end + 4'd12: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; + end + 4'd13: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w; + end + 4'd14: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; + end + 4'd15: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w; + end + 5'd16: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w; + end + endcase + end + if (csrbank2_dfii_control0_re) begin + litedramcore_storage[3:0] <= csrbank2_dfii_control0_r; + end + litedramcore_re <= csrbank2_dfii_control0_re; + if (csrbank2_dfii_pi0_command0_re) begin + litedramcore_phaseinjector0_command_storage[7:0] <= csrbank2_dfii_pi0_command0_r; + end + litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; + if (csrbank2_dfii_pi0_address0_re) begin + litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r; + end + litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; + if (csrbank2_dfii_pi0_baddress0_re) begin + litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; + end + litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; + if (csrbank2_dfii_pi0_wrdata1_re) begin + litedramcore_phaseinjector0_wrdata_storage[63:32] <= csrbank2_dfii_pi0_wrdata1_r; + end + if (csrbank2_dfii_pi0_wrdata0_re) begin + litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; + end + litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; + litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata0_re; + if (csrbank2_dfii_pi1_command0_re) begin + litedramcore_phaseinjector1_command_storage[7:0] <= csrbank2_dfii_pi1_command0_r; + end + litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; + if (csrbank2_dfii_pi1_address0_re) begin + litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r; + end + litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; + if (csrbank2_dfii_pi1_baddress0_re) begin + litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; + end + litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; + if (csrbank2_dfii_pi1_wrdata1_re) begin + litedramcore_phaseinjector1_wrdata_storage[63:32] <= csrbank2_dfii_pi1_wrdata1_r; + end + if (csrbank2_dfii_pi1_wrdata0_re) begin + litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; + end + litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; + litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata0_re; + if (sys_rst) begin + ddrphy_dly_sel_storage <= 2'd0; + ddrphy_dly_sel_re <= 1'd0; + ddrphy_burstdet_seen_status <= 2'd0; + ddrphy_burstdet_seen_re <= 1'd0; + ddrphy_rdly0 <= 3'd0; + ddrphy_burstdet_d0 <= 1'd0; + ddrphy_dm_o_data_d0 <= 8'd0; + ddrphy_dm_o_data_muxed0 <= 4'd0; + ddrphy_dq_o_data_d0 <= 8'd0; + ddrphy_dq_o_data_muxed0 <= 4'd0; + ddrphy_bitslip0_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d0 <= 4'd0; + ddrphy_dq_o_data_d1 <= 8'd0; + ddrphy_dq_o_data_muxed1 <= 4'd0; + ddrphy_bitslip1_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d1 <= 4'd0; + ddrphy_dq_o_data_d2 <= 8'd0; + ddrphy_dq_o_data_muxed2 <= 4'd0; + ddrphy_bitslip2_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d2 <= 4'd0; + ddrphy_dq_o_data_d3 <= 8'd0; + ddrphy_dq_o_data_muxed3 <= 4'd0; + ddrphy_bitslip3_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d3 <= 4'd0; + ddrphy_dq_o_data_d4 <= 8'd0; + ddrphy_dq_o_data_muxed4 <= 4'd0; + ddrphy_bitslip4_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d4 <= 4'd0; + ddrphy_dq_o_data_d5 <= 8'd0; + ddrphy_dq_o_data_muxed5 <= 4'd0; + ddrphy_bitslip5_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d5 <= 4'd0; + ddrphy_dq_o_data_d6 <= 8'd0; + ddrphy_dq_o_data_muxed6 <= 4'd0; + ddrphy_bitslip6_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d6 <= 4'd0; + ddrphy_dq_o_data_d7 <= 8'd0; + ddrphy_dq_o_data_muxed7 <= 4'd0; + ddrphy_bitslip7_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d7 <= 4'd0; + ddrphy_rdly1 <= 3'd0; + ddrphy_burstdet_d1 <= 1'd0; + ddrphy_dm_o_data_d1 <= 8'd0; + ddrphy_dm_o_data_muxed1 <= 4'd0; + ddrphy_dq_o_data_d8 <= 8'd0; + ddrphy_dq_o_data_muxed8 <= 4'd0; + ddrphy_bitslip8_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d8 <= 4'd0; + ddrphy_dq_o_data_d9 <= 8'd0; + ddrphy_dq_o_data_muxed9 <= 4'd0; + ddrphy_bitslip9_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d9 <= 4'd0; + ddrphy_dq_o_data_d10 <= 8'd0; + ddrphy_dq_o_data_muxed10 <= 4'd0; + ddrphy_bitslip10_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d10 <= 4'd0; + ddrphy_dq_o_data_d11 <= 8'd0; + ddrphy_dq_o_data_muxed11 <= 4'd0; + ddrphy_bitslip11_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d11 <= 4'd0; + ddrphy_dq_o_data_d12 <= 8'd0; + ddrphy_dq_o_data_muxed12 <= 4'd0; + ddrphy_bitslip12_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d12 <= 4'd0; + ddrphy_dq_o_data_d13 <= 8'd0; + ddrphy_dq_o_data_muxed13 <= 4'd0; + ddrphy_bitslip13_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d13 <= 4'd0; + ddrphy_dq_o_data_d14 <= 8'd0; + ddrphy_dq_o_data_muxed14 <= 4'd0; + ddrphy_bitslip14_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d14 <= 4'd0; + ddrphy_dq_o_data_d15 <= 8'd0; + ddrphy_dq_o_data_muxed15 <= 4'd0; + ddrphy_bitslip15_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d15 <= 4'd0; + ddrphy_rddata_en_tappeddelayline0 <= 1'd0; + ddrphy_rddata_en_tappeddelayline1 <= 1'd0; + ddrphy_rddata_en_tappeddelayline2 <= 1'd0; + ddrphy_rddata_en_tappeddelayline3 <= 1'd0; + ddrphy_rddata_en_tappeddelayline4 <= 1'd0; + ddrphy_rddata_en_tappeddelayline5 <= 1'd0; + ddrphy_rddata_en_tappeddelayline6 <= 1'd0; + ddrphy_rddata_en_tappeddelayline7 <= 1'd0; + ddrphy_rddata_en_tappeddelayline8 <= 1'd0; + ddrphy_rddata_en_tappeddelayline9 <= 1'd0; + ddrphy_rddata_en_tappeddelayline10 <= 1'd0; + ddrphy_rddata_en_tappeddelayline11 <= 1'd0; + ddrphy_rddata_en_tappeddelayline12 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline3 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline4 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline5 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline6 <= 1'd0; + litedramcore_storage <= 4'd1; + litedramcore_re <= 1'd0; + litedramcore_phaseinjector0_command_storage <= 8'd0; + litedramcore_phaseinjector0_command_re <= 1'd0; + litedramcore_phaseinjector0_address_re <= 1'd0; + litedramcore_phaseinjector0_baddress_re <= 1'd0; + litedramcore_phaseinjector0_wrdata_re <= 1'd0; + litedramcore_phaseinjector0_rddata_status <= 64'd0; + litedramcore_phaseinjector0_rddata_re <= 1'd0; + litedramcore_phaseinjector1_command_storage <= 8'd0; + litedramcore_phaseinjector1_command_re <= 1'd0; + litedramcore_phaseinjector1_address_re <= 1'd0; + litedramcore_phaseinjector1_baddress_re <= 1'd0; + litedramcore_phaseinjector1_wrdata_re <= 1'd0; + litedramcore_phaseinjector1_rddata_status <= 64'd0; + litedramcore_phaseinjector1_rddata_re <= 1'd0; + litedramcore_dfi_p0_address <= 15'd0; + litedramcore_dfi_p0_bank <= 3'd0; + litedramcore_dfi_p0_cas_n <= 1'd1; + litedramcore_dfi_p0_cs_n <= 1'd1; + litedramcore_dfi_p0_ras_n <= 1'd1; + litedramcore_dfi_p0_we_n <= 1'd1; + litedramcore_dfi_p0_wrdata_en <= 1'd0; + litedramcore_dfi_p0_rddata_en <= 1'd0; + litedramcore_dfi_p1_address <= 15'd0; + litedramcore_dfi_p1_bank <= 3'd0; + litedramcore_dfi_p1_cas_n <= 1'd1; + litedramcore_dfi_p1_cs_n <= 1'd1; + litedramcore_dfi_p1_ras_n <= 1'd1; + litedramcore_dfi_p1_we_n <= 1'd1; + litedramcore_dfi_p1_wrdata_en <= 1'd0; + litedramcore_dfi_p1_rddata_en <= 1'd0; + litedramcore_cmd_payload_a <= 15'd0; + litedramcore_cmd_payload_ba <= 3'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_timer_count1 <= 9'd390; + litedramcore_postponer_req_o <= 1'd0; + litedramcore_postponer_count <= 1'd0; + litedramcore_sequencer_done1 <= 1'd0; + litedramcore_sequencer_trigger <= 7'd0; + litedramcore_sequencer_count <= 1'd0; + litedramcore_zqcs_timer_count1 <= 26'd49999999; + litedramcore_zqcs_executer_done <= 1'd0; + litedramcore_zqcs_executer_trigger <= 6'd0; + litedramcore_bankmachine0_level <= 5'd0; + litedramcore_bankmachine0_produce <= 4'd0; + litedramcore_bankmachine0_consume <= 4'd0; + litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine0_row <= 15'd0; + litedramcore_bankmachine0_row_opened <= 1'd0; + litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + litedramcore_bankmachine0_twtpcon_count <= 3'd0; + litedramcore_bankmachine0_trccon_ready <= 1'd0; + litedramcore_bankmachine0_trccon_count <= 2'd0; + litedramcore_bankmachine0_trascon_ready <= 1'd0; + litedramcore_bankmachine0_trascon_count <= 2'd0; + litedramcore_bankmachine1_level <= 5'd0; + litedramcore_bankmachine1_produce <= 4'd0; + litedramcore_bankmachine1_consume <= 4'd0; + litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine1_row <= 15'd0; + litedramcore_bankmachine1_row_opened <= 1'd0; + litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + litedramcore_bankmachine1_twtpcon_count <= 3'd0; + litedramcore_bankmachine1_trccon_ready <= 1'd0; + litedramcore_bankmachine1_trccon_count <= 2'd0; + litedramcore_bankmachine1_trascon_ready <= 1'd0; + litedramcore_bankmachine1_trascon_count <= 2'd0; + litedramcore_bankmachine2_level <= 5'd0; + litedramcore_bankmachine2_produce <= 4'd0; + litedramcore_bankmachine2_consume <= 4'd0; + litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine2_row <= 15'd0; + litedramcore_bankmachine2_row_opened <= 1'd0; + litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + litedramcore_bankmachine2_twtpcon_count <= 3'd0; + litedramcore_bankmachine2_trccon_ready <= 1'd0; + litedramcore_bankmachine2_trccon_count <= 2'd0; + litedramcore_bankmachine2_trascon_ready <= 1'd0; + litedramcore_bankmachine2_trascon_count <= 2'd0; + litedramcore_bankmachine3_level <= 5'd0; + litedramcore_bankmachine3_produce <= 4'd0; + litedramcore_bankmachine3_consume <= 4'd0; + litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine3_row <= 15'd0; + litedramcore_bankmachine3_row_opened <= 1'd0; + litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + litedramcore_bankmachine3_twtpcon_count <= 3'd0; + litedramcore_bankmachine3_trccon_ready <= 1'd0; + litedramcore_bankmachine3_trccon_count <= 2'd0; + litedramcore_bankmachine3_trascon_ready <= 1'd0; + litedramcore_bankmachine3_trascon_count <= 2'd0; + litedramcore_bankmachine4_level <= 5'd0; + litedramcore_bankmachine4_produce <= 4'd0; + litedramcore_bankmachine4_consume <= 4'd0; + litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine4_row <= 15'd0; + litedramcore_bankmachine4_row_opened <= 1'd0; + litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + litedramcore_bankmachine4_twtpcon_count <= 3'd0; + litedramcore_bankmachine4_trccon_ready <= 1'd0; + litedramcore_bankmachine4_trccon_count <= 2'd0; + litedramcore_bankmachine4_trascon_ready <= 1'd0; + litedramcore_bankmachine4_trascon_count <= 2'd0; + litedramcore_bankmachine5_level <= 5'd0; + litedramcore_bankmachine5_produce <= 4'd0; + litedramcore_bankmachine5_consume <= 4'd0; + litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine5_row <= 15'd0; + litedramcore_bankmachine5_row_opened <= 1'd0; + litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + litedramcore_bankmachine5_twtpcon_count <= 3'd0; + litedramcore_bankmachine5_trccon_ready <= 1'd0; + litedramcore_bankmachine5_trccon_count <= 2'd0; + litedramcore_bankmachine5_trascon_ready <= 1'd0; + litedramcore_bankmachine5_trascon_count <= 2'd0; + litedramcore_bankmachine6_level <= 5'd0; + litedramcore_bankmachine6_produce <= 4'd0; + litedramcore_bankmachine6_consume <= 4'd0; + litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine6_row <= 15'd0; + litedramcore_bankmachine6_row_opened <= 1'd0; + litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + litedramcore_bankmachine6_twtpcon_count <= 3'd0; + litedramcore_bankmachine6_trccon_ready <= 1'd0; + litedramcore_bankmachine6_trccon_count <= 2'd0; + litedramcore_bankmachine6_trascon_ready <= 1'd0; + litedramcore_bankmachine6_trascon_count <= 2'd0; + litedramcore_bankmachine7_level <= 5'd0; + litedramcore_bankmachine7_produce <= 4'd0; + litedramcore_bankmachine7_consume <= 4'd0; + litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine7_row <= 15'd0; + litedramcore_bankmachine7_row_opened <= 1'd0; + litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + litedramcore_bankmachine7_twtpcon_count <= 3'd0; + litedramcore_bankmachine7_trccon_ready <= 1'd0; + litedramcore_bankmachine7_trccon_count <= 2'd0; + litedramcore_bankmachine7_trascon_ready <= 1'd0; + litedramcore_bankmachine7_trascon_count <= 2'd0; + litedramcore_choose_cmd_grant <= 3'd0; + litedramcore_choose_req_grant <= 3'd0; + litedramcore_trrdcon_ready <= 1'd0; + litedramcore_trrdcon_count <= 1'd0; + litedramcore_tfawcon_ready <= 1'd1; + litedramcore_tfawcon_window <= 3'd0; + litedramcore_tccdcon_ready <= 1'd0; + litedramcore_tccdcon_count <= 1'd0; + litedramcore_twtrcon_ready <= 1'd0; + litedramcore_twtrcon_count <= 3'd0; + litedramcore_time0 <= 5'd0; + litedramcore_time1 <= 4'd0; + init_done_storage <= 1'd0; + init_done_re <= 1'd0; + init_error_storage <= 1'd0; + init_error_re <= 1'd0; + interface1_we <= 1'd0; + litedramcore_refresher_state <= 2'd0; + litedramcore_bankmachine0_state <= 3'd0; + litedramcore_bankmachine1_state <= 3'd0; + litedramcore_bankmachine2_state <= 3'd0; + litedramcore_bankmachine3_state <= 3'd0; + litedramcore_bankmachine4_state <= 3'd0; + litedramcore_bankmachine5_state <= 3'd0; + litedramcore_bankmachine6_state <= 3'd0; + litedramcore_bankmachine7_state <= 3'd0; + litedramcore_multiplexer_state <= 4'd0; + litedramcore_new_master_wdata_ready0 <= 1'd0; + litedramcore_new_master_wdata_ready1 <= 1'd0; + litedramcore_new_master_wdata_ready2 <= 1'd0; + litedramcore_new_master_wdata_ready3 <= 1'd0; + litedramcore_new_master_rdata_valid0 <= 1'd0; + litedramcore_new_master_rdata_valid1 <= 1'd0; + litedramcore_new_master_rdata_valid2 <= 1'd0; + litedramcore_new_master_rdata_valid3 <= 1'd0; + litedramcore_new_master_rdata_valid4 <= 1'd0; + litedramcore_new_master_rdata_valid5 <= 1'd0; + litedramcore_new_master_rdata_valid6 <= 1'd0; + litedramcore_new_master_rdata_valid7 <= 1'd0; + litedramcore_new_master_rdata_valid8 <= 1'd0; + litedramcore_new_master_rdata_valid9 <= 1'd0; + litedramcore_new_master_rdata_valid10 <= 1'd0; + litedramcore_new_master_rdata_valid11 <= 1'd0; + litedramcore_new_master_rdata_valid12 <= 1'd0; + litedramcore_new_master_rdata_valid13 <= 1'd0; + state <= 2'd0; + end +end + + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Instance ECLKBRIDGECS of ECLKBRIDGECS Module. +//------------------------------------------------------------------------------ +ECLKBRIDGECS ECLKBRIDGECS( + // Inputs. + .CLK0 (sys2x_i_clk), + .SEL (1'd0), + + // Outputs. + .ECSOUT (crg_sys2x_clk_ecsout) +); + +//------------------------------------------------------------------------------ +// Instance ECLKSYNCB of ECLKSYNCB Module. +//------------------------------------------------------------------------------ +ECLKSYNCB ECLKSYNCB( + // Inputs. + .ECLKI (crg_sys2x_clk_ecsout), + .STOP (crg_stop), + + // Outputs. + .ECLKO (sys2x_clk) +); + +//------------------------------------------------------------------------------ +// Instance CLKDIVF of CLKDIVF Module. +//------------------------------------------------------------------------------ +CLKDIVF #( + // Parameters. + .DIV ("2.0") +) CLKDIVF ( + // Inputs. + .ALIGNWD (1'd0), + .CLKI (sys2x_clk), + .RST (crg_reset0), + + // Outputs. + .CDIVX (sys_clk) +); + +//------------------------------------------------------------------------------ +// Instance DDRDLLA of DDRDLLA Module. +//------------------------------------------------------------------------------ +DDRDLLA DDRDLLA( + // Inputs. + .CLK (sys2x_clk), + .FREEZE (ddrphy_freeze), + .RST (init_rst), + .UDDCNTLN ((~ddrphy_update)), + + // Outputs. + .DDRDEL (ddrphy_delay1), + .LOCK (ddrphy_lock0) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F( + // Inputs. + .D0 (1'd0), + .D1 (1'd1), + .D2 (1'd0), + .D3 (1'd1), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f0) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG ( + // Inputs. + .A (ddrphy_pad_oddrx2f0), + + // Outputs. + .Z (ddram_clk_p) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_1 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_1( + // Inputs. + .D0 (ddrphy_dfi_p0_reset_n), + .D1 (ddrphy_dfi_p0_reset_n), + .D2 (ddrphy_dfi_p1_reset_n), + .D3 (ddrphy_dfi_p1_reset_n), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f1) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_1 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_1 ( + // Inputs. + .A (ddrphy_pad_oddrx2f1), + + // Outputs. + .Z (ddram_reset_n) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_2 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_2( + // Inputs. + .D0 (ddrphy_dfi_p0_cs_n), + .D1 (ddrphy_dfi_p0_cs_n), + .D2 (ddrphy_dfi_p1_cs_n), + .D3 (ddrphy_dfi_p1_cs_n), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f2) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_2 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_2 ( + // Inputs. + .A (ddrphy_pad_oddrx2f2), + + // Outputs. + .Z (ddram_cs_n) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_3 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_3( + // Inputs. + .D0 (ddrphy_dfi_p0_address[0]), + .D1 (ddrphy_dfi_p0_address[0]), + .D2 (ddrphy_dfi_p1_address[0]), + .D3 (ddrphy_dfi_p1_address[0]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f3) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_3 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_3 ( + // Inputs. + .A (ddrphy_pad_oddrx2f3), + + // Outputs. + .Z (ddram_a[0]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_4 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_4( + // Inputs. + .D0 (ddrphy_dfi_p0_address[1]), + .D1 (ddrphy_dfi_p0_address[1]), + .D2 (ddrphy_dfi_p1_address[1]), + .D3 (ddrphy_dfi_p1_address[1]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f4) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_4 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_4 ( + // Inputs. + .A (ddrphy_pad_oddrx2f4), + + // Outputs. + .Z (ddram_a[1]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_5 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_5( + // Inputs. + .D0 (ddrphy_dfi_p0_address[2]), + .D1 (ddrphy_dfi_p0_address[2]), + .D2 (ddrphy_dfi_p1_address[2]), + .D3 (ddrphy_dfi_p1_address[2]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f5) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_5 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_5 ( + // Inputs. + .A (ddrphy_pad_oddrx2f5), + + // Outputs. + .Z (ddram_a[2]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_6 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_6( + // Inputs. + .D0 (ddrphy_dfi_p0_address[3]), + .D1 (ddrphy_dfi_p0_address[3]), + .D2 (ddrphy_dfi_p1_address[3]), + .D3 (ddrphy_dfi_p1_address[3]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f6) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_6 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_6 ( + // Inputs. + .A (ddrphy_pad_oddrx2f6), + + // Outputs. + .Z (ddram_a[3]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_7 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_7( + // Inputs. + .D0 (ddrphy_dfi_p0_address[4]), + .D1 (ddrphy_dfi_p0_address[4]), + .D2 (ddrphy_dfi_p1_address[4]), + .D3 (ddrphy_dfi_p1_address[4]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f7) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_7 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_7 ( + // Inputs. + .A (ddrphy_pad_oddrx2f7), + + // Outputs. + .Z (ddram_a[4]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_8 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_8( + // Inputs. + .D0 (ddrphy_dfi_p0_address[5]), + .D1 (ddrphy_dfi_p0_address[5]), + .D2 (ddrphy_dfi_p1_address[5]), + .D3 (ddrphy_dfi_p1_address[5]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f8) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_8 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_8 ( + // Inputs. + .A (ddrphy_pad_oddrx2f8), + + // Outputs. + .Z (ddram_a[5]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_9 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_9( + // Inputs. + .D0 (ddrphy_dfi_p0_address[6]), + .D1 (ddrphy_dfi_p0_address[6]), + .D2 (ddrphy_dfi_p1_address[6]), + .D3 (ddrphy_dfi_p1_address[6]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f9) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_9 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_9 ( + // Inputs. + .A (ddrphy_pad_oddrx2f9), + + // Outputs. + .Z (ddram_a[6]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_10 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_10( + // Inputs. + .D0 (ddrphy_dfi_p0_address[7]), + .D1 (ddrphy_dfi_p0_address[7]), + .D2 (ddrphy_dfi_p1_address[7]), + .D3 (ddrphy_dfi_p1_address[7]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f10) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_10 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_10 ( + // Inputs. + .A (ddrphy_pad_oddrx2f10), + + // Outputs. + .Z (ddram_a[7]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_11 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_11( + // Inputs. + .D0 (ddrphy_dfi_p0_address[8]), + .D1 (ddrphy_dfi_p0_address[8]), + .D2 (ddrphy_dfi_p1_address[8]), + .D3 (ddrphy_dfi_p1_address[8]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f11) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_11 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_11 ( + // Inputs. + .A (ddrphy_pad_oddrx2f11), + + // Outputs. + .Z (ddram_a[8]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_12 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_12( + // Inputs. + .D0 (ddrphy_dfi_p0_address[9]), + .D1 (ddrphy_dfi_p0_address[9]), + .D2 (ddrphy_dfi_p1_address[9]), + .D3 (ddrphy_dfi_p1_address[9]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f12) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_12 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_12 ( + // Inputs. + .A (ddrphy_pad_oddrx2f12), + + // Outputs. + .Z (ddram_a[9]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_13 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_13( + // Inputs. + .D0 (ddrphy_dfi_p0_address[10]), + .D1 (ddrphy_dfi_p0_address[10]), + .D2 (ddrphy_dfi_p1_address[10]), + .D3 (ddrphy_dfi_p1_address[10]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f13) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_13 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_13 ( + // Inputs. + .A (ddrphy_pad_oddrx2f13), + + // Outputs. + .Z (ddram_a[10]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_14 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_14( + // Inputs. + .D0 (ddrphy_dfi_p0_address[11]), + .D1 (ddrphy_dfi_p0_address[11]), + .D2 (ddrphy_dfi_p1_address[11]), + .D3 (ddrphy_dfi_p1_address[11]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f14) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_14 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_14 ( + // Inputs. + .A (ddrphy_pad_oddrx2f14), + + // Outputs. + .Z (ddram_a[11]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_15 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_15( + // Inputs. + .D0 (ddrphy_dfi_p0_address[12]), + .D1 (ddrphy_dfi_p0_address[12]), + .D2 (ddrphy_dfi_p1_address[12]), + .D3 (ddrphy_dfi_p1_address[12]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f15) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_15 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_15 ( + // Inputs. + .A (ddrphy_pad_oddrx2f15), + + // Outputs. + .Z (ddram_a[12]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_16 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_16( + // Inputs. + .D0 (ddrphy_dfi_p0_address[13]), + .D1 (ddrphy_dfi_p0_address[13]), + .D2 (ddrphy_dfi_p1_address[13]), + .D3 (ddrphy_dfi_p1_address[13]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f16) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_16 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_16 ( + // Inputs. + .A (ddrphy_pad_oddrx2f16), + + // Outputs. + .Z (ddram_a[13]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_17 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_17( + // Inputs. + .D0 (ddrphy_dfi_p0_address[14]), + .D1 (ddrphy_dfi_p0_address[14]), + .D2 (ddrphy_dfi_p1_address[14]), + .D3 (ddrphy_dfi_p1_address[14]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f17) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_17 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_17 ( + // Inputs. + .A (ddrphy_pad_oddrx2f17), + + // Outputs. + .Z (ddram_a[14]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_18 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_18( + // Inputs. + .D0 (ddrphy_dfi_p0_bank[0]), + .D1 (ddrphy_dfi_p0_bank[0]), + .D2 (ddrphy_dfi_p1_bank[0]), + .D3 (ddrphy_dfi_p1_bank[0]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f18) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_18 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_18 ( + // Inputs. + .A (ddrphy_pad_oddrx2f18), + + // Outputs. + .Z (ddram_ba[0]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_19 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_19( + // Inputs. + .D0 (ddrphy_dfi_p0_bank[1]), + .D1 (ddrphy_dfi_p0_bank[1]), + .D2 (ddrphy_dfi_p1_bank[1]), + .D3 (ddrphy_dfi_p1_bank[1]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f19) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_19 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_19 ( + // Inputs. + .A (ddrphy_pad_oddrx2f19), + + // Outputs. + .Z (ddram_ba[1]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_20 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_20( + // Inputs. + .D0 (ddrphy_dfi_p0_bank[2]), + .D1 (ddrphy_dfi_p0_bank[2]), + .D2 (ddrphy_dfi_p1_bank[2]), + .D3 (ddrphy_dfi_p1_bank[2]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f20) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_20 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_20 ( + // Inputs. + .A (ddrphy_pad_oddrx2f20), + + // Outputs. + .Z (ddram_ba[2]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_21 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_21( + // Inputs. + .D0 (ddrphy_dfi_p0_ras_n), + .D1 (ddrphy_dfi_p0_ras_n), + .D2 (ddrphy_dfi_p1_ras_n), + .D3 (ddrphy_dfi_p1_ras_n), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f21) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_21 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_21 ( + // Inputs. + .A (ddrphy_pad_oddrx2f21), + + // Outputs. + .Z (ddram_ras_n) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_22 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_22( + // Inputs. + .D0 (ddrphy_dfi_p0_cas_n), + .D1 (ddrphy_dfi_p0_cas_n), + .D2 (ddrphy_dfi_p1_cas_n), + .D3 (ddrphy_dfi_p1_cas_n), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f22) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_22 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_22 ( + // Inputs. + .A (ddrphy_pad_oddrx2f22), + + // Outputs. + .Z (ddram_cas_n) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_23 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_23( + // Inputs. + .D0 (ddrphy_dfi_p0_we_n), + .D1 (ddrphy_dfi_p0_we_n), + .D2 (ddrphy_dfi_p1_we_n), + .D3 (ddrphy_dfi_p1_we_n), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f23) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_23 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_23 ( + // Inputs. + .A (ddrphy_pad_oddrx2f23), + + // Outputs. + .Z (ddram_we_n) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_24 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_24( + // Inputs. + .D0 (ddrphy_dfi_p0_cke), + .D1 (ddrphy_dfi_p0_cke), + .D2 (ddrphy_dfi_p1_cke), + .D3 (ddrphy_dfi_p1_cke), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f24) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_24 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_24 ( + // Inputs. + .A (ddrphy_pad_oddrx2f24), + + // Outputs. + .Z (ddram_cke) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2F_25 of ODDRX2F Module. +//------------------------------------------------------------------------------ +ODDRX2F ODDRX2F_25( + // Inputs. + .D0 (ddrphy_dfi_p0_odt), + .D1 (ddrphy_dfi_p0_odt), + .D2 (ddrphy_dfi_p1_odt), + .D3 (ddrphy_dfi_p1_odt), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f25) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_25 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_VALUE (1'd0) +) DELAYG_25 ( + // Inputs. + .A (ddrphy_pad_oddrx2f25), + + // Outputs. + .Z (ddram_odt) +); + +//------------------------------------------------------------------------------ +// Instance DQSBUFM of DQSBUFM Module. +//------------------------------------------------------------------------------ +DQSBUFM #( + // Parameters. + .DQS_LI_DEL_ADJ ("MINUS"), + .DQS_LI_DEL_VAL (1'd1), + .DQS_LO_DEL_ADJ ("MINUS"), + .DQS_LO_DEL_VAL (3'd4) +) DQSBUFM ( + // Inputs. + .DDRDEL (ddrphy_delay0), + .DQSI (ddrphy_dqs_i0), + .ECLK (sys2x_clk), + .PAUSE ((ddrphy_pause0 | ddrphy_dly_sel_storage[0])), + .RDDIRECTION (1'd1), + .RDLOADN (1'd0), + .RDMOVE (1'd0), + .READ0 (ddrphy_dqs_re), + .READ1 (ddrphy_dqs_re), + .READCLKSEL0 (ddrphy_rdly0[0]), + .READCLKSEL1 (ddrphy_rdly0[1]), + .READCLKSEL2 (ddrphy_rdly0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRDIRECTION (1'd1), + .WRLOADN (1'd0), + .WRMOVE (1'd0), + + // Outputs. + .BURSTDET (ddrphy_burstdet0), + .DATAVALID (ddrphy_datavalid[0]), + .DQSR90 (ddrphy_dqsr900), + .DQSW (ddrphy_dqsw0), + .DQSW270 (ddrphy_dqsw2700), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQSB of ODDRX2DQSB Module. +//------------------------------------------------------------------------------ +ODDRX2DQSB ODDRX2DQSB( + // Inputs. + .D0 (1'd0), + .D1 (1'd1), + .D2 (1'd0), + .D3 (1'd1), + .DQSW (ddrphy_dqsw0), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dqs0) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQSA of TSHX2DQSA Module. +//------------------------------------------------------------------------------ +TSHX2DQSA TSHX2DQSA( + // Inputs. + .DQSW (ddrphy_dqsw0), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~(ddrphy_dqs_oe | ddrphy_dqs_postamble))), + .T1 ((~(ddrphy_dqs_oe | ddrphy_dqs_preamble))), + + // Outputs. + .Q (ddrphy_dqs_oe_n0) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA( + // Inputs. + .D0 (ddrphy_dm_o_data_muxed0[0]), + .D1 (ddrphy_dm_o_data_muxed0[1]), + .D2 (ddrphy_dm_o_data_muxed0[2]), + .D3 (ddrphy_dm_o_data_muxed0[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddram_dm[0]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_1 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_1( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed0[0]), + .D1 (ddrphy_dq_o_data_muxed0[1]), + .D2 (ddrphy_dq_o_data_muxed0[2]), + .D3 (ddrphy_dq_o_data_muxed0[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o0) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_26 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_26 ( + // Inputs. + .A (ddrphy_dq_i0), + + // Outputs. + .Z (ddrphy_dq_i_delayed0) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA( + // Inputs. + .D (ddrphy_dq_i_delayed0), + .DQSR90 (ddrphy_dqsr900), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]), + + // Outputs. + .Q0 (ddrphy_bitslip0_i[0]), + .Q1 (ddrphy_bitslip0_i[1]), + .Q2 (ddrphy_bitslip0_i[2]), + .Q3 (ddrphy_bitslip0_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA( + // Inputs. + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n0) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_2 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_2( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed1[0]), + .D1 (ddrphy_dq_o_data_muxed1[1]), + .D2 (ddrphy_dq_o_data_muxed1[2]), + .D3 (ddrphy_dq_o_data_muxed1[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o1) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_27 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_27 ( + // Inputs. + .A (ddrphy_dq_i1), + + // Outputs. + .Z (ddrphy_dq_i_delayed1) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_1 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_1( + // Inputs. + .D (ddrphy_dq_i_delayed1), + .DQSR90 (ddrphy_dqsr900), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]), + + // Outputs. + .Q0 (ddrphy_bitslip1_i[0]), + .Q1 (ddrphy_bitslip1_i[1]), + .Q2 (ddrphy_bitslip1_i[2]), + .Q3 (ddrphy_bitslip1_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_1 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_1( + // Inputs. + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n1) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_3 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_3( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed2[0]), + .D1 (ddrphy_dq_o_data_muxed2[1]), + .D2 (ddrphy_dq_o_data_muxed2[2]), + .D3 (ddrphy_dq_o_data_muxed2[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o2) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_28 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_28 ( + // Inputs. + .A (ddrphy_dq_i2), + + // Outputs. + .Z (ddrphy_dq_i_delayed2) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_2 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_2( + // Inputs. + .D (ddrphy_dq_i_delayed2), + .DQSR90 (ddrphy_dqsr900), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]), + + // Outputs. + .Q0 (ddrphy_bitslip2_i[0]), + .Q1 (ddrphy_bitslip2_i[1]), + .Q2 (ddrphy_bitslip2_i[2]), + .Q3 (ddrphy_bitslip2_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_2 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_2( + // Inputs. + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n2) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_4 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_4( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed3[0]), + .D1 (ddrphy_dq_o_data_muxed3[1]), + .D2 (ddrphy_dq_o_data_muxed3[2]), + .D3 (ddrphy_dq_o_data_muxed3[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o3) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_29 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_29 ( + // Inputs. + .A (ddrphy_dq_i3), + + // Outputs. + .Z (ddrphy_dq_i_delayed3) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_3 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_3( + // Inputs. + .D (ddrphy_dq_i_delayed3), + .DQSR90 (ddrphy_dqsr900), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]), + + // Outputs. + .Q0 (ddrphy_bitslip3_i[0]), + .Q1 (ddrphy_bitslip3_i[1]), + .Q2 (ddrphy_bitslip3_i[2]), + .Q3 (ddrphy_bitslip3_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_3 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_3( + // Inputs. + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n3) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_5 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_5( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed4[0]), + .D1 (ddrphy_dq_o_data_muxed4[1]), + .D2 (ddrphy_dq_o_data_muxed4[2]), + .D3 (ddrphy_dq_o_data_muxed4[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o4) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_30 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_30 ( + // Inputs. + .A (ddrphy_dq_i4), + + // Outputs. + .Z (ddrphy_dq_i_delayed4) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_4 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_4( + // Inputs. + .D (ddrphy_dq_i_delayed4), + .DQSR90 (ddrphy_dqsr900), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]), + + // Outputs. + .Q0 (ddrphy_bitslip4_i[0]), + .Q1 (ddrphy_bitslip4_i[1]), + .Q2 (ddrphy_bitslip4_i[2]), + .Q3 (ddrphy_bitslip4_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_4 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_4( + // Inputs. + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n4) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_6 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_6( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed5[0]), + .D1 (ddrphy_dq_o_data_muxed5[1]), + .D2 (ddrphy_dq_o_data_muxed5[2]), + .D3 (ddrphy_dq_o_data_muxed5[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o5) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_31 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_31 ( + // Inputs. + .A (ddrphy_dq_i5), + + // Outputs. + .Z (ddrphy_dq_i_delayed5) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_5 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_5( + // Inputs. + .D (ddrphy_dq_i_delayed5), + .DQSR90 (ddrphy_dqsr900), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]), + + // Outputs. + .Q0 (ddrphy_bitslip5_i[0]), + .Q1 (ddrphy_bitslip5_i[1]), + .Q2 (ddrphy_bitslip5_i[2]), + .Q3 (ddrphy_bitslip5_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_5 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_5( + // Inputs. + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n5) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_7 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_7( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed6[0]), + .D1 (ddrphy_dq_o_data_muxed6[1]), + .D2 (ddrphy_dq_o_data_muxed6[2]), + .D3 (ddrphy_dq_o_data_muxed6[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o6) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_32 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_32 ( + // Inputs. + .A (ddrphy_dq_i6), + + // Outputs. + .Z (ddrphy_dq_i_delayed6) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_6 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_6( + // Inputs. + .D (ddrphy_dq_i_delayed6), + .DQSR90 (ddrphy_dqsr900), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]), + + // Outputs. + .Q0 (ddrphy_bitslip6_i[0]), + .Q1 (ddrphy_bitslip6_i[1]), + .Q2 (ddrphy_bitslip6_i[2]), + .Q3 (ddrphy_bitslip6_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_6 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_6( + // Inputs. + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n6) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_8 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_8( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed7[0]), + .D1 (ddrphy_dq_o_data_muxed7[1]), + .D2 (ddrphy_dq_o_data_muxed7[2]), + .D3 (ddrphy_dq_o_data_muxed7[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o7) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_33 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_33 ( + // Inputs. + .A (ddrphy_dq_i7), + + // Outputs. + .Z (ddrphy_dq_i_delayed7) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_7 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_7( + // Inputs. + .D (ddrphy_dq_i_delayed7), + .DQSR90 (ddrphy_dqsr900), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]), + + // Outputs. + .Q0 (ddrphy_bitslip7_i[0]), + .Q1 (ddrphy_bitslip7_i[1]), + .Q2 (ddrphy_bitslip7_i[2]), + .Q3 (ddrphy_bitslip7_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_7 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_7( + // Inputs. + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n7) +); + +//------------------------------------------------------------------------------ +// Instance DQSBUFM_1 of DQSBUFM Module. +//------------------------------------------------------------------------------ +DQSBUFM #( + // Parameters. + .DQS_LI_DEL_ADJ ("MINUS"), + .DQS_LI_DEL_VAL (1'd1), + .DQS_LO_DEL_ADJ ("MINUS"), + .DQS_LO_DEL_VAL (3'd4) +) DQSBUFM_1 ( + // Inputs. + .DDRDEL (ddrphy_delay0), + .DQSI (ddrphy_dqs_i1), + .ECLK (sys2x_clk), + .PAUSE ((ddrphy_pause0 | ddrphy_dly_sel_storage[1])), + .RDDIRECTION (1'd1), + .RDLOADN (1'd0), + .RDMOVE (1'd0), + .READ0 (ddrphy_dqs_re), + .READ1 (ddrphy_dqs_re), + .READCLKSEL0 (ddrphy_rdly1[0]), + .READCLKSEL1 (ddrphy_rdly1[1]), + .READCLKSEL2 (ddrphy_rdly1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRDIRECTION (1'd1), + .WRLOADN (1'd0), + .WRMOVE (1'd0), + + // Outputs. + .BURSTDET (ddrphy_burstdet1), + .DATAVALID (ddrphy_datavalid[1]), + .DQSR90 (ddrphy_dqsr901), + .DQSW (ddrphy_dqsw1), + .DQSW270 (ddrphy_dqsw2701), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQSB_1 of ODDRX2DQSB Module. +//------------------------------------------------------------------------------ +ODDRX2DQSB ODDRX2DQSB_1( + // Inputs. + .D0 (1'd0), + .D1 (1'd1), + .D2 (1'd0), + .D3 (1'd1), + .DQSW (ddrphy_dqsw1), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dqs1) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQSA_1 of TSHX2DQSA Module. +//------------------------------------------------------------------------------ +TSHX2DQSA TSHX2DQSA_1( + // Inputs. + .DQSW (ddrphy_dqsw1), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~(ddrphy_dqs_oe | ddrphy_dqs_postamble))), + .T1 ((~(ddrphy_dqs_oe | ddrphy_dqs_preamble))), + + // Outputs. + .Q (ddrphy_dqs_oe_n1) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_9 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_9( + // Inputs. + .D0 (ddrphy_dm_o_data_muxed1[0]), + .D1 (ddrphy_dm_o_data_muxed1[1]), + .D2 (ddrphy_dm_o_data_muxed1[2]), + .D3 (ddrphy_dm_o_data_muxed1[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddram_dm[1]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_10 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_10( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed8[0]), + .D1 (ddrphy_dq_o_data_muxed8[1]), + .D2 (ddrphy_dq_o_data_muxed8[2]), + .D3 (ddrphy_dq_o_data_muxed8[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o8) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_34 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_34 ( + // Inputs. + .A (ddrphy_dq_i8), + + // Outputs. + .Z (ddrphy_dq_i_delayed8) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_8 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_8( + // Inputs. + .D (ddrphy_dq_i_delayed8), + .DQSR90 (ddrphy_dqsr901), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]), + + // Outputs. + .Q0 (ddrphy_bitslip8_i[0]), + .Q1 (ddrphy_bitslip8_i[1]), + .Q2 (ddrphy_bitslip8_i[2]), + .Q3 (ddrphy_bitslip8_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_8 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_8( + // Inputs. + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n8) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_11 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_11( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed9[0]), + .D1 (ddrphy_dq_o_data_muxed9[1]), + .D2 (ddrphy_dq_o_data_muxed9[2]), + .D3 (ddrphy_dq_o_data_muxed9[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o9) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_35 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_35 ( + // Inputs. + .A (ddrphy_dq_i9), + + // Outputs. + .Z (ddrphy_dq_i_delayed9) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_9 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_9( + // Inputs. + .D (ddrphy_dq_i_delayed9), + .DQSR90 (ddrphy_dqsr901), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]), + + // Outputs. + .Q0 (ddrphy_bitslip9_i[0]), + .Q1 (ddrphy_bitslip9_i[1]), + .Q2 (ddrphy_bitslip9_i[2]), + .Q3 (ddrphy_bitslip9_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_9 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_9( + // Inputs. + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n9) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_12 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_12( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed10[0]), + .D1 (ddrphy_dq_o_data_muxed10[1]), + .D2 (ddrphy_dq_o_data_muxed10[2]), + .D3 (ddrphy_dq_o_data_muxed10[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o10) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_36 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_36 ( + // Inputs. + .A (ddrphy_dq_i10), + + // Outputs. + .Z (ddrphy_dq_i_delayed10) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_10 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_10( + // Inputs. + .D (ddrphy_dq_i_delayed10), + .DQSR90 (ddrphy_dqsr901), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]), + + // Outputs. + .Q0 (ddrphy_bitslip10_i[0]), + .Q1 (ddrphy_bitslip10_i[1]), + .Q2 (ddrphy_bitslip10_i[2]), + .Q3 (ddrphy_bitslip10_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_10 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_10( + // Inputs. + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n10) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_13 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_13( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed11[0]), + .D1 (ddrphy_dq_o_data_muxed11[1]), + .D2 (ddrphy_dq_o_data_muxed11[2]), + .D3 (ddrphy_dq_o_data_muxed11[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o11) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_37 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_37 ( + // Inputs. + .A (ddrphy_dq_i11), + + // Outputs. + .Z (ddrphy_dq_i_delayed11) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_11 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_11( + // Inputs. + .D (ddrphy_dq_i_delayed11), + .DQSR90 (ddrphy_dqsr901), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]), + + // Outputs. + .Q0 (ddrphy_bitslip11_i[0]), + .Q1 (ddrphy_bitslip11_i[1]), + .Q2 (ddrphy_bitslip11_i[2]), + .Q3 (ddrphy_bitslip11_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_11 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_11( + // Inputs. + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n11) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_14 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_14( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed12[0]), + .D1 (ddrphy_dq_o_data_muxed12[1]), + .D2 (ddrphy_dq_o_data_muxed12[2]), + .D3 (ddrphy_dq_o_data_muxed12[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o12) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_38 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_38 ( + // Inputs. + .A (ddrphy_dq_i12), + + // Outputs. + .Z (ddrphy_dq_i_delayed12) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_12 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_12( + // Inputs. + .D (ddrphy_dq_i_delayed12), + .DQSR90 (ddrphy_dqsr901), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]), + + // Outputs. + .Q0 (ddrphy_bitslip12_i[0]), + .Q1 (ddrphy_bitslip12_i[1]), + .Q2 (ddrphy_bitslip12_i[2]), + .Q3 (ddrphy_bitslip12_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_12 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_12( + // Inputs. + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n12) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_15 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_15( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed13[0]), + .D1 (ddrphy_dq_o_data_muxed13[1]), + .D2 (ddrphy_dq_o_data_muxed13[2]), + .D3 (ddrphy_dq_o_data_muxed13[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o13) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_39 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_39 ( + // Inputs. + .A (ddrphy_dq_i13), + + // Outputs. + .Z (ddrphy_dq_i_delayed13) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_13 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_13( + // Inputs. + .D (ddrphy_dq_i_delayed13), + .DQSR90 (ddrphy_dqsr901), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]), + + // Outputs. + .Q0 (ddrphy_bitslip13_i[0]), + .Q1 (ddrphy_bitslip13_i[1]), + .Q2 (ddrphy_bitslip13_i[2]), + .Q3 (ddrphy_bitslip13_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_13 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_13( + // Inputs. + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n13) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_16 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_16( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed14[0]), + .D1 (ddrphy_dq_o_data_muxed14[1]), + .D2 (ddrphy_dq_o_data_muxed14[2]), + .D3 (ddrphy_dq_o_data_muxed14[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o14) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_40 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_40 ( + // Inputs. + .A (ddrphy_dq_i14), + + // Outputs. + .Z (ddrphy_dq_i_delayed14) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_14 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_14( + // Inputs. + .D (ddrphy_dq_i_delayed14), + .DQSR90 (ddrphy_dqsr901), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]), + + // Outputs. + .Q0 (ddrphy_bitslip14_i[0]), + .Q1 (ddrphy_bitslip14_i[1]), + .Q2 (ddrphy_bitslip14_i[2]), + .Q3 (ddrphy_bitslip14_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_14 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_14( + // Inputs. + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n14) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_17 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ +ODDRX2DQA ODDRX2DQA_17( + // Inputs. + .D0 (ddrphy_dq_o_data_muxed15[0]), + .D1 (ddrphy_dq_o_data_muxed15[1]), + .D2 (ddrphy_dq_o_data_muxed15[2]), + .D3 (ddrphy_dq_o_data_muxed15[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o15) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_41 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") +) DELAYG_41 ( + // Inputs. + .A (ddrphy_dq_i15), + + // Outputs. + .Z (ddrphy_dq_i_delayed15) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_15 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ +IDDRX2DQA IDDRX2DQA_15( + // Inputs. + .D (ddrphy_dq_i_delayed15), + .DQSR90 (ddrphy_dqsr901), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]), + + // Outputs. + .Q0 (ddrphy_bitslip15_i[0]), + .Q1 (ddrphy_bitslip15_i[1]), + .Q2 (ddrphy_bitslip15_i[2]), + .Q3 (ddrphy_bitslip15_i[3]) +); + +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_15 of TSHX2DQA Module. +//------------------------------------------------------------------------------ +TSHX2DQA TSHX2DQA_15( + // Inputs. + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n15) +); + +//------------------------------------------------------------------------------ +// Memory storage: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage[0:15]; +reg [24:0] storage_dat0; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine0_wrport_we) + storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w; + storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0; +assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_1: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_1[0:15]; +reg [24:0] storage_1_dat0; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine1_wrport_we) + storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w; + storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0; +assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_2: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_2[0:15]; +reg [24:0] storage_2_dat0; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine2_wrport_we) + storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w; + storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0; +assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_3: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_3[0:15]; +reg [24:0] storage_3_dat0; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine3_wrport_we) + storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w; + storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0; +assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_4: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_4[0:15]; +reg [24:0] storage_4_dat0; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine4_wrport_we) + storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w; + storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0; +assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_5: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_5[0:15]; +reg [24:0] storage_5_dat0; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine5_wrport_we) + storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w; + storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0; +assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_6: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_6[0:15]; +reg [24:0] storage_6_dat0; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine6_wrport_we) + storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w; + storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0; +assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_7: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_7[0:15]; +reg [24:0] storage_7_dat0; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine7_wrport_we) + storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w; + storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0; +assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr]; + + +(* FREQUENCY_PIN_CLKI = "100.0", FREQUENCY_PIN_CLKOP = "100.0", FREQUENCY_PIN_CLKOS = "50.0", ICP_CURRENT = "6", LPF_RESISTOR = "16", MFG_ENABLE_FILTEROPAMP = "1", MFG_GMCREF_SEL = "2" *) +//------------------------------------------------------------------------------ +// Instance EHXPLLL of EHXPLLL Module. +//------------------------------------------------------------------------------ +EHXPLLL #( + // Parameters. + .CLKFB_DIV (3'd4), + .CLKI_DIV (1'd1), + .CLKOP_CPHASE (2'd3), + .CLKOP_DIV (3'd4), + .CLKOP_ENABLE ("ENABLED"), + .CLKOP_FPHASE (1'd0), + .CLKOS2_CPHASE (1'd0), + .CLKOS2_DIV (1'd1), + .CLKOS2_ENABLE ("ENABLED"), + .CLKOS2_FPHASE (1'd0), + .CLKOS_CPHASE (3'd7), + .CLKOS_DIV (4'd8), + .CLKOS_ENABLE ("ENABLED"), + .CLKOS_FPHASE (1'd0), + .FEEDBK_PATH ("INT_OS2") +) EHXPLLL ( + // Inputs. + .CLKI (crg_clkin), + .RST (crg_reset1), + .STDBY (crg_stdby), + + // Outputs. + .CLKOP (crg_clkout0), + .CLKOS (crg_clkout1), + .CLKOS2 (litedramecp5ddrphycrg_ecp5pll), + .LOCK (litedramecp5ddrphycrg_locked) +); + +//------------------------------------------------------------------------------ +// Instance FD1S3BX of FD1S3BX Module. +//------------------------------------------------------------------------------ +FD1S3BX FD1S3BX( + // Inputs. + .CK (sys2x_i_clk), + .D (1'd0), + .PD ((~crg_locked)), + + // Outputs. + .Q (latticeecp5asyncresetsynchronizerimpl0_rst1) +); + +//------------------------------------------------------------------------------ +// Instance FD1S3BX_1 of FD1S3BX Module. +//------------------------------------------------------------------------------ +FD1S3BX FD1S3BX_1( + // Inputs. + .CK (sys2x_i_clk), + .D (latticeecp5asyncresetsynchronizerimpl0_rst1), + .PD ((~crg_locked)), + + // Outputs. + .Q (latticeecp5asyncresetsynchronizerimpl0_expr) +); + +//------------------------------------------------------------------------------ +// Instance FD1S3BX_2 of FD1S3BX Module. +//------------------------------------------------------------------------------ +FD1S3BX FD1S3BX_2( + // Inputs. + .CK (init_clk), + .D (1'd0), + .PD ((~crg_locked)), + + // Outputs. + .Q (latticeecp5asyncresetsynchronizerimpl1_rst1) +); + +//------------------------------------------------------------------------------ +// Instance FD1S3BX_3 of FD1S3BX Module. +//------------------------------------------------------------------------------ +FD1S3BX FD1S3BX_3( + // Inputs. + .CK (init_clk), + .D (latticeecp5asyncresetsynchronizerimpl1_rst1), + .PD ((~crg_locked)), + + // Outputs. + .Q (init_rst) +); + +//------------------------------------------------------------------------------ +// Instance FD1S3BX_4 of FD1S3BX Module. +//------------------------------------------------------------------------------ +FD1S3BX FD1S3BX_4( + // Inputs. + .CK (sys_clk), + .D (1'd0), + .PD (((~crg_locked) | crg_reset0)), + + // Outputs. + .Q (latticeecp5asyncresetsynchronizerimpl2_rst1) +); + +//------------------------------------------------------------------------------ +// Instance FD1S3BX_5 of FD1S3BX Module. +//------------------------------------------------------------------------------ +FD1S3BX FD1S3BX_5( + // Inputs. + .CK (sys_clk), + .D (latticeecp5asyncresetsynchronizerimpl2_rst1), + .PD (((~crg_locked) | crg_reset0)), + + // Outputs. + .Q (sys_rst) +); + +//------------------------------------------------------------------------------ +// Instance FD1S3BX_6 of FD1S3BX Module. +//------------------------------------------------------------------------------ +FD1S3BX FD1S3BX_6( + // Inputs. + .CK (sys2x_clk), + .D (1'd0), + .PD (((~crg_locked) | crg_reset0)), + + // Outputs. + .Q (latticeecp5asyncresetsynchronizerimpl3_rst1) +); + +//------------------------------------------------------------------------------ +// Instance FD1S3BX_7 of FD1S3BX Module. +//------------------------------------------------------------------------------ +FD1S3BX FD1S3BX_7( + // Inputs. + .CK (sys2x_clk), + .D (latticeecp5asyncresetsynchronizerimpl3_rst1), + .PD (((~crg_locked) | crg_reset0)), + + // Outputs. + .Q (sys2x_rst) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO ( + // Inputs. + .B (ddram_dqs_p[0]), + .I (ddrphy_dqs0), + .T ((~(~ddrphy_dqs_oe_n0))), + + // Outputs. + .O (ddrphy_dqs_i0) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_1 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_1 ( + // Inputs. + .B (ddram_dq[0]), + .I (ddrphy_dq_o0), + .T ((~(~ddrphy_dq_oe_n0))), + + // Outputs. + .O (ddrphy_dq_i0) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_2 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_2 ( + // Inputs. + .B (ddram_dq[1]), + .I (ddrphy_dq_o1), + .T ((~(~ddrphy_dq_oe_n1))), + + // Outputs. + .O (ddrphy_dq_i1) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_3 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_3 ( + // Inputs. + .B (ddram_dq[2]), + .I (ddrphy_dq_o2), + .T ((~(~ddrphy_dq_oe_n2))), + + // Outputs. + .O (ddrphy_dq_i2) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_4 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_4 ( + // Inputs. + .B (ddram_dq[3]), + .I (ddrphy_dq_o3), + .T ((~(~ddrphy_dq_oe_n3))), + + // Outputs. + .O (ddrphy_dq_i3) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_5 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_5 ( + // Inputs. + .B (ddram_dq[4]), + .I (ddrphy_dq_o4), + .T ((~(~ddrphy_dq_oe_n4))), + + // Outputs. + .O (ddrphy_dq_i4) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_6 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_6 ( + // Inputs. + .B (ddram_dq[5]), + .I (ddrphy_dq_o5), + .T ((~(~ddrphy_dq_oe_n5))), + + // Outputs. + .O (ddrphy_dq_i5) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_7 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_7 ( + // Inputs. + .B (ddram_dq[6]), + .I (ddrphy_dq_o6), + .T ((~(~ddrphy_dq_oe_n6))), + + // Outputs. + .O (ddrphy_dq_i6) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_8 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_8 ( + // Inputs. + .B (ddram_dq[7]), + .I (ddrphy_dq_o7), + .T ((~(~ddrphy_dq_oe_n7))), + + // Outputs. + .O (ddrphy_dq_i7) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_9 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_9 ( + // Inputs. + .B (ddram_dqs_p[1]), + .I (ddrphy_dqs1), + .T ((~(~ddrphy_dqs_oe_n1))), + + // Outputs. + .O (ddrphy_dqs_i1) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_10 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_10 ( + // Inputs. + .B (ddram_dq[8]), + .I (ddrphy_dq_o8), + .T ((~(~ddrphy_dq_oe_n8))), + + // Outputs. + .O (ddrphy_dq_i8) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_11 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_11 ( + // Inputs. + .B (ddram_dq[9]), + .I (ddrphy_dq_o9), + .T ((~(~ddrphy_dq_oe_n9))), + + // Outputs. + .O (ddrphy_dq_i9) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_12 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_12 ( + // Inputs. + .B (ddram_dq[10]), + .I (ddrphy_dq_o10), + .T ((~(~ddrphy_dq_oe_n10))), + + // Outputs. + .O (ddrphy_dq_i10) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_13 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_13 ( + // Inputs. + .B (ddram_dq[11]), + .I (ddrphy_dq_o11), + .T ((~(~ddrphy_dq_oe_n11))), + + // Outputs. + .O (ddrphy_dq_i11) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_14 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_14 ( + // Inputs. + .B (ddram_dq[12]), + .I (ddrphy_dq_o12), + .T ((~(~ddrphy_dq_oe_n12))), + + // Outputs. + .O (ddrphy_dq_i12) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_15 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_15 ( + // Inputs. + .B (ddram_dq[13]), + .I (ddrphy_dq_o13), + .T ((~(~ddrphy_dq_oe_n13))), + + // Outputs. + .O (ddrphy_dq_i13) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_16 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_16 ( + // Inputs. + .B (ddram_dq[14]), + .I (ddrphy_dq_o14), + .T ((~(~ddrphy_dq_oe_n14))), + + // Outputs. + .O (ddrphy_dq_i14) +); + +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_17 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ +TRELLIS_IO #( + // Parameters. + .DIR ("BIDIR") +) TRELLIS_IO_17 ( + // Inputs. + .B (ddram_dq[15]), + .I (ddrphy_dq_o15), + .T ((~(~ddrphy_dq_oe_n15))), + + // Outputs. + .O (ddrphy_dq_i15) +); + +endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2024-04-01 18:06:24. +//------------------------------------------------------------------------------ diff --git a/litedram/generated/genesys2/litedram_core.init b/litedram/generated/genesys2/litedram_core.init index a0de849..33ac9e8 100644 --- a/litedram/generated/genesys2/litedram_core.init +++ b/litedram/generated/genesys2/litedram_core.init @@ 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+600000004bfff795 +7f83e3787c6e1b78 +600000004bfff75d +408100487c2e1840 +7fbdf850e9210070 +394000007c637050 +3bbd000138e00020 +7c691a147d09f050 +2c2800007d08fa14 +3ba0000140820008 +3bbdffff2c3d0001 +714a000140820028 +e881006040820034 +386100607f85e378 +7c84f8507c9e2050 +4bfffde84bfff955 +3929000198e90000 +7c29184039400001 +f92100604082ffc0 +893a00014bffffcc +2c09006c3b200008 +7cda33784082fdbc +893a00014bfffdb4 +2c0900683b200002 +7cda33784082fda4 +4bfffd983b200001 +5529063e392affd0 +4181fd8828090009 +3b7b00017b690020 +994900207d214a14 +3b2000084bfffd74 +3a4000204bfffd6c +4bfffbd43b410041 +3bde0001993e0000 +fbc100607d054378 +000000004bfffa54 0000128001000000 f9e1ff78f9c1ff70 fa21ff88fa01ff80 @@ -2319,7 +2332,7 @@ ebe1fff8e8010010 203a46464f204853 7479622078257830 00000000000a7365 -2d2d2d2d2d2d2d2d +3033633733313738 0000000000000000 4d4152446574694c 6620746c69756220 @@ -2360,16 +2373,9 @@ ebe1fff8e8010010 20676e69746f6f42 415244206d6f7266 0000000a2e2e2e4d -7c203a64256d2020 -0000000000000000 -0000000000006425 -000000000000007c -203a79616c656420 -0000000000000a2d -203a79616c656420 -0000000a64323025 62202c64256d2020 007c203a64323025 +0000000000006425 000000000000207c 00007c203a64256d 203a7379616c6564 @@ -2387,6 +2393,13 @@ ebe1fff8e8010010 7764726168206f74 746e6f6320657261 0000000a2e6c6f72 +7c203a64256d2020 +0000000000000000 +000000000000007c +203a79616c656420 +0000000000000a2d +203a79616c656420 +0000000a64323025 7165204b43742020 746e656c61766975 25203a7370617420 @@ -2425,6 +2438,17 @@ ebe1fff8e8010010 52445320676e697a 3025783040204d41 000a2e2e2e786c38 +000000540000002a +6000000000000024 +676e697465736552 +6c65642074614420 +6f6d20666f207961 +0a642520656c7564 +0000000000000000 +676e697465736552 +70696c7374694220 +75646f6d20666f20 +00000a642520656c 0000000042756c25 4b756c252e756c25 0000000000004269 diff --git a/litedram/generated/genesys2/litedram_core.v b/litedram/generated/genesys2/litedram_core.v index 9f8030a..b6d2e37 100644 --- a/litedram/generated/genesys2/litedram_core.v +++ b/litedram/generated/genesys2/litedram_core.v @@ -8,10 +8,11 @@ // // Filename : litedram_core.v // Device : -// LiteX sha1 : -------- -// Date : 2022-10-28 19:01:21 +// LiteX sha1 : 87137c30 +// Date : 2024-04-01 10:12:08 //------------------------------------------------------------------------------ +`timescale 1ns / 1ps //------------------------------------------------------------------------------ // Module @@ -19,6355 +20,6945 @@ module litedram_core ( input wire clk, - input wire rst, - output wire pll_locked, output wire [14:0] ddram_a, output wire [2:0] ddram_ba, - output wire ddram_ras_n, output wire ddram_cas_n, - output wire ddram_we_n, + output wire ddram_cke, + output wire ddram_clk_n, + output wire ddram_clk_p, output wire ddram_cs_n, output wire [3:0] ddram_dm, inout wire [31:0] ddram_dq, - inout wire [3:0] ddram_dqs_p, inout wire [3:0] ddram_dqs_n, - output wire ddram_clk_p, - output wire ddram_clk_n, - output wire ddram_cke, + inout wire [3:0] ddram_dqs_p, output wire ddram_odt, + output wire ddram_ras_n, output wire ddram_reset_n, + output wire ddram_we_n, output wire init_done, output wire init_error, - input wire [29:0] wb_ctrl_adr, - input wire [31:0] wb_ctrl_dat_w, - output wire [31:0] wb_ctrl_dat_r, - input wire [3:0] wb_ctrl_sel, - input wire wb_ctrl_cyc, - input wire wb_ctrl_stb, - output wire wb_ctrl_ack, - input wire wb_ctrl_we, - input wire [2:0] wb_ctrl_cti, - input wire [1:0] wb_ctrl_bte, - output wire wb_ctrl_err, + output wire pll_locked, + input wire rst, output wire user_clk, - output wire user_rst, - input wire user_port_native_0_cmd_valid, + input wire [24:0] user_port_native_0_cmd_addr, output wire user_port_native_0_cmd_ready, + input wire user_port_native_0_cmd_valid, input wire user_port_native_0_cmd_we, - input wire [24:0] user_port_native_0_cmd_addr, - input wire user_port_native_0_wdata_valid, + output wire [255:0] user_port_native_0_rdata_data, + input wire user_port_native_0_rdata_ready, + output wire user_port_native_0_rdata_valid, + input wire [255:0] user_port_native_0_wdata_data, output wire user_port_native_0_wdata_ready, + input wire user_port_native_0_wdata_valid, input wire [31:0] user_port_native_0_wdata_we, - input wire [255:0] user_port_native_0_wdata_data, - output wire user_port_native_0_rdata_valid, - input wire user_port_native_0_rdata_ready, - output wire [255:0] user_port_native_0_rdata_data + output wire user_rst, + output wire wb_ctrl_ack, + input wire [29:0] wb_ctrl_adr, + input wire [1:0] wb_ctrl_bte, + input wire [2:0] wb_ctrl_cti, + input wire wb_ctrl_cyc, + output wire [31:0] wb_ctrl_dat_r, + input wire [31:0] wb_ctrl_dat_w, + output wire wb_ctrl_err, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_stb, + input wire wb_ctrl_we ); +//------------------------------------------------------------------------------ +// Hierarchy +//------------------------------------------------------------------------------ + +/* +LiteDRAMCore +└─── bus (SoCBusHandler) +│ └─── _interconnect (InterconnectPointToPoint) +└─── csr (SoCCSRHandler) +└─── irq (SoCIRQHandler) +└─── cpu (CPUNone) +└─── crg (LiteDRAMS7DDRPHYCRG) +│ └─── pll (S7PLL) +│ │ └─── [FDCE] +│ │ └─── [BUFG] +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [BUFG] +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [BUFG] +│ │ └─── [FDCE] +│ │ └─── [BUFG] +│ │ └─── [PLLE2_ADV] +│ └─── idelayctrl (S7IDELAYCTRL) +│ │ └─── [IDELAYCTRL] +└─── ddrphy (K7DDRPHY) +│ └─── tappeddelayline_0* (TappedDelayLine) +│ └─── dqspattern_0* (DQSPattern) +│ └─── bitslip_0* (BitSlip) +│ └─── bitslip_1* (BitSlip) +│ └─── bitslip_2* (BitSlip) +│ └─── bitslip_3* (BitSlip) +│ └─── bitslip_4* (BitSlip) +│ └─── bitslip_5* (BitSlip) +│ └─── bitslip_6* (BitSlip) +│ └─── bitslip_7* (BitSlip) +│ └─── tappeddelayline_1* (TappedDelayLine) +│ └─── bitslip_8* (BitSlip) +│ └─── bitslip_9* (BitSlip) +│ └─── bitslip_10* (BitSlip) +│ └─── bitslip_11* (BitSlip) +│ └─── bitslip_12* (BitSlip) +│ └─── bitslip_13* (BitSlip) +│ └─── bitslip_14* (BitSlip) +│ └─── bitslip_15* (BitSlip) +│ └─── bitslip_16* (BitSlip) +│ └─── bitslip_17* (BitSlip) +│ └─── bitslip_18* (BitSlip) +│ └─── bitslip_19* (BitSlip) +│ └─── bitslip_20* (BitSlip) +│ └─── bitslip_21* (BitSlip) +│ └─── bitslip_22* (BitSlip) +│ └─── bitslip_23* (BitSlip) +│ └─── bitslip_24* (BitSlip) +│ └─── bitslip_25* (BitSlip) +│ └─── bitslip_26* (BitSlip) +│ └─── bitslip_27* (BitSlip) +│ └─── bitslip_28* (BitSlip) +│ └─── bitslip_29* (BitSlip) +│ └─── bitslip_30* (BitSlip) +│ └─── bitslip_31* (BitSlip) +│ └─── bitslip_32* (BitSlip) +│ └─── bitslip_33* (BitSlip) +│ └─── bitslip_34* (BitSlip) +│ └─── bitslip_35* (BitSlip) +│ └─── bitslip_36* (BitSlip) +│ └─── bitslip_37* (BitSlip) +│ └─── bitslip_38* (BitSlip) +│ └─── bitslip_39* (BitSlip) +│ └─── bitslip_40* (BitSlip) +│ └─── bitslip_41* (BitSlip) +│ └─── bitslip_42* (BitSlip) +│ └─── bitslip_43* (BitSlip) +│ └─── bitslip_44* (BitSlip) +│ └─── bitslip_45* (BitSlip) +│ └─── bitslip_46* (BitSlip) +│ └─── bitslip_47* (BitSlip) +│ └─── bitslip_48* (BitSlip) +│ └─── bitslip_49* (BitSlip) +│ └─── bitslip_50* (BitSlip) +│ └─── bitslip_51* (BitSlip) +│ └─── bitslip_52* (BitSlip) +│ └─── bitslip_53* (BitSlip) +│ └─── bitslip_54* (BitSlip) +│ └─── bitslip_55* (BitSlip) +│ └─── bitslip_56* (BitSlip) +│ └─── bitslip_57* (BitSlip) +│ └─── bitslip_58* (BitSlip) +│ └─── bitslip_59* (BitSlip) +│ └─── bitslip_60* (BitSlip) +│ └─── bitslip_61* (BitSlip) +│ └─── bitslip_62* (BitSlip) +│ └─── bitslip_63* (BitSlip) +│ └─── bitslip_64* (BitSlip) +│ └─── bitslip_65* (BitSlip) +│ └─── bitslip_66* (BitSlip) +│ └─── bitslip_67* (BitSlip) +│ └─── bitslip_68* (BitSlip) +│ └─── bitslip_69* (BitSlip) +│ └─── bitslip_70* (BitSlip) +│ └─── bitslip_71* (BitSlip) +│ └─── tappeddelayline_2* (TappedDelayLine) +│ └─── tappeddelayline_3* (TappedDelayLine) +│ └─── [ODELAYE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [ODELAYE2] +│ └─── [OSERDESE2] +│ └─── [ODELAYE2] +│ └─── [ISERDESE2] +│ └─── [ODELAYE2] +│ └─── [IDELAYE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [ODELAYE2] +│ └─── [OSERDESE2] +│ └─── [ODELAYE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [ODELAYE2] +│ └─── [OSERDESE2] +│ └─── [ODELAYE2] +│ └─── [ODELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ODELAYE2] +│ └─── [ODELAYE2] +│ └─── [OSERDESE2] +│ └─── [ODELAYE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [ODELAYE2] +│ └─── [ISERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [ODELAYE2] +│ └─── [IDELAYE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [ODELAYE2] +│ └─── [ODELAYE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [ODELAYE2] +│ └─── [IOBUF] +│ └─── [ODELAYE2] +│ └─── [OSERDESE2] +│ └─── [ODELAYE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [ODELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ODELAYE2] +│ └─── [ODELAYE2] +│ └─── [ODELAYE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IOBUFDS] +│ └─── [IDELAYE2] +│ └─── [ISERDESE2] +│ └─── [ISERDESE2] +│ └─── [ODELAYE2] +│ └─── [ODELAYE2] +│ └─── [IDELAYE2] +│ └─── [IDELAYE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [IDELAYE2] +│ └─── [ISERDESE2] +│ └─── [IOBUF] +│ └─── [IOBUF] +│ └─── [ODELAYE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [ODELAYE2] +│ └─── [ODELAYE2] +│ └─── [ODELAYE2] +│ └─── [ODELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ODELAYE2] +│ └─── [ODELAYE2] +│ └─── [ISERDESE2] +│ └─── [IOBUF] +│ └─── [ISERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [ISERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [ODELAYE2] +│ └─── [IOBUF] +│ └─── [ODELAYE2] +│ └─── [IDELAYE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ODELAYE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [ODELAYE2] +│ └─── [IOBUF] +│ └─── [IOBUFDS] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ODELAYE2] +│ └─── [ODELAYE2] +│ └─── [OSERDESE2] +│ └─── [ODELAYE2] +│ └─── [ODELAYE2] +│ └─── [ODELAYE2] +│ └─── [ODELAYE2] +│ └─── [ISERDESE2] +│ └─── [OBUFDS] +│ └─── [ODELAYE2] +│ └─── [ODELAYE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [ODELAYE2] +│ └─── [IOBUF] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ODELAYE2] +│ └─── [ODELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ODELAYE2] +│ └─── [OSERDESE2] +│ └─── [ODELAYE2] +│ └─── [ISERDESE2] +│ └─── [ODELAYE2] +│ └─── [ISERDESE2] +│ └─── [ODELAYE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUFDS] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [ODELAYE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [ODELAYE2] +│ └─── [ODELAYE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [ODELAYE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ODELAYE2] +│ └─── [ODELAYE2] +│ └─── [OSERDESE2] +│ └─── [ODELAYE2] +│ └─── [ODELAYE2] +│ └─── [OSERDESE2] +│ └─── [ODELAYE2] +│ └─── [ISERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [ISERDESE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [ODELAYE2] +│ └─── [IOBUF] +│ └─── [IDELAYE2] +│ └─── [ODELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [ODELAYE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [ODELAYE2] +│ └─── [ODELAYE2] +│ └─── [ODELAYE2] +│ └─── [OSERDESE2] +│ └─── [IOBUFDS] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +└─── sdram (LiteDRAMCore) +│ └─── dfii (DFIInjector) +│ │ └─── pi0 (PhaseInjector) +│ │ └─── pi1 (PhaseInjector) +│ │ └─── pi2 (PhaseInjector) +│ │ └─── pi3 (PhaseInjector) +│ └─── controller (LiteDRAMController) +│ │ └─── refresher (Refresher) +│ │ │ └─── timer (RefreshTimer) +│ │ │ └─── postponer (RefreshPostponer) +│ │ │ └─── sequencer (RefreshSequencer) +│ │ │ │ └─── refreshexecuter_0* (RefreshExecuter) +│ │ │ └─── zqcs_timer (RefreshTimer) +│ │ │ └─── zqs_executer (ZQCSExecuter) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_0* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_1* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_2* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_3* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_4* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_5* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_6* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_7* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── multiplexer (Multiplexer) +│ │ │ └─── choose_cmd (_CommandChooser) +│ │ │ │ └─── roundrobin_0* (RoundRobin) +│ │ │ └─── choose_req (_CommandChooser) +│ │ │ │ └─── roundrobin_0* (RoundRobin) +│ │ │ └─── _steerer_0* (_Steerer) +│ │ │ └─── trrdcon (tXXDController) +│ │ │ └─── tfawcon (tFAWController) +│ │ │ └─── tccdcon (tXXDController) +│ │ │ └─── twtrcon (tXXDController) +│ │ │ └─── fsm (FSM) +│ └─── crossbar (LiteDRAMCrossbar) +│ │ └─── roundrobin_0* (RoundRobin) +│ │ └─── roundrobin_1* (RoundRobin) +│ │ └─── roundrobin_2* (RoundRobin) +│ │ └─── roundrobin_3* (RoundRobin) +│ │ └─── roundrobin_4* (RoundRobin) +│ │ └─── roundrobin_5* (RoundRobin) +│ │ └─── roundrobin_6* (RoundRobin) +│ │ └─── roundrobin_7* (RoundRobin) +└─── ddrctrl (LiteDRAMCoreControl) +└─── csr_bridge (Wishbone2CSR) +│ └─── fsm (FSM) +└─── csr_bankarray (CSRBankArray) +│ └─── csrbank_0* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ └─── csrbank_1* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstorage_4* (CSRStorage) +│ │ └─── csrstorage_5* (CSRStorage) +│ └─── csrbank_2* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstorage_4* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstorage_5* (CSRStorage) +│ │ └─── csrstorage_6* (CSRStorage) +│ │ └─── csrstorage_7* (CSRStorage) +│ │ └─── csrstorage_8* (CSRStorage) +│ │ └─── csrstatus_1* (CSRStatus) +│ │ └─── csrstorage_9* (CSRStorage) +│ │ └─── csrstorage_10* (CSRStorage) +│ │ └─── csrstorage_11* (CSRStorage) +│ │ └─── csrstorage_12* (CSRStorage) +│ │ └─── csrstatus_2* (CSRStatus) +│ │ └─── csrstorage_13* (CSRStorage) +│ │ └─── csrstorage_14* (CSRStorage) +│ │ └─── csrstorage_15* (CSRStorage) +│ │ └─── csrstorage_16* (CSRStorage) +│ │ └─── csrstatus_3* (CSRStatus) +└─── csr_interconnect (InterconnectShared) +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +* : Generated name. +[]: BlackBox. +*/ + //------------------------------------------------------------------------------ // Signals //------------------------------------------------------------------------------ -reg rst_1 = 1'd0; -wire sys_clk; -wire sys_rst; -wire sys4x_clk; -wire sys4x_dqs_clk; +wire [13:0] builder_adr; +reg [3:0] builder_bankmachine0_next_state = 4'd0; +reg [3:0] builder_bankmachine0_state = 4'd0; +reg [3:0] builder_bankmachine1_next_state = 4'd0; +reg [3:0] builder_bankmachine1_state = 4'd0; +reg [3:0] builder_bankmachine2_next_state = 4'd0; +reg [3:0] builder_bankmachine2_state = 4'd0; +reg [3:0] builder_bankmachine3_next_state = 4'd0; +reg [3:0] builder_bankmachine3_state = 4'd0; +reg [3:0] builder_bankmachine4_next_state = 4'd0; +reg [3:0] builder_bankmachine4_state = 4'd0; +reg [3:0] builder_bankmachine5_next_state = 4'd0; +reg [3:0] builder_bankmachine5_state = 4'd0; +reg [3:0] builder_bankmachine6_next_state = 4'd0; +reg [3:0] builder_bankmachine6_state = 4'd0; +reg [3:0] builder_bankmachine7_next_state = 4'd0; +reg [3:0] builder_bankmachine7_state = 4'd0; +wire builder_csrbank0_init_done0_r; +reg builder_csrbank0_init_done0_re = 1'd0; +wire builder_csrbank0_init_done0_w; +reg builder_csrbank0_init_done0_we = 1'd0; +wire builder_csrbank0_init_error0_r; +reg builder_csrbank0_init_error0_re = 1'd0; +wire builder_csrbank0_init_error0_w; +reg builder_csrbank0_init_error0_we = 1'd0; +wire builder_csrbank0_sel; +wire [3:0] builder_csrbank1_dly_sel0_r; +reg builder_csrbank1_dly_sel0_re = 1'd0; +wire [3:0] builder_csrbank1_dly_sel0_w; +reg builder_csrbank1_dly_sel0_we = 1'd0; +wire [4:0] builder_csrbank1_half_sys8x_taps0_r; +reg builder_csrbank1_half_sys8x_taps0_re = 1'd0; +wire [4:0] builder_csrbank1_half_sys8x_taps0_w; +reg builder_csrbank1_half_sys8x_taps0_we = 1'd0; +wire [1:0] builder_csrbank1_rdphase0_r; +reg builder_csrbank1_rdphase0_re = 1'd0; +wire [1:0] builder_csrbank1_rdphase0_w; +reg builder_csrbank1_rdphase0_we = 1'd0; +wire builder_csrbank1_rst0_r; +reg builder_csrbank1_rst0_re = 1'd0; +wire builder_csrbank1_rst0_w; +reg builder_csrbank1_rst0_we = 1'd0; +wire builder_csrbank1_sel; +wire builder_csrbank1_wlevel_en0_r; +reg builder_csrbank1_wlevel_en0_re = 1'd0; +wire builder_csrbank1_wlevel_en0_w; +reg builder_csrbank1_wlevel_en0_we = 1'd0; +wire [1:0] builder_csrbank1_wrphase0_r; +reg builder_csrbank1_wrphase0_re = 1'd0; +wire [1:0] builder_csrbank1_wrphase0_w; +reg builder_csrbank1_wrphase0_we = 1'd0; +wire [3:0] builder_csrbank2_dfii_control0_r; +reg builder_csrbank2_dfii_control0_re = 1'd0; +wire [3:0] builder_csrbank2_dfii_control0_w; +reg builder_csrbank2_dfii_control0_we = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi0_address0_r; +reg builder_csrbank2_dfii_pi0_address0_re = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi0_address0_w; +reg builder_csrbank2_dfii_pi0_address0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r; +reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w; +reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_command0_r; +reg builder_csrbank2_dfii_pi0_command0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_command0_w; +reg builder_csrbank2_dfii_pi0_command0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_rddata0_r; +reg builder_csrbank2_dfii_pi0_rddata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_rddata0_w; +reg builder_csrbank2_dfii_pi0_rddata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_rddata1_r; +reg builder_csrbank2_dfii_pi0_rddata1_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_rddata1_w; +reg builder_csrbank2_dfii_pi0_rddata1_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_r; +reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_w; +reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_wrdata1_r; +reg builder_csrbank2_dfii_pi0_wrdata1_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_wrdata1_w; +reg builder_csrbank2_dfii_pi0_wrdata1_we = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi1_address0_r; +reg builder_csrbank2_dfii_pi1_address0_re = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi1_address0_w; +reg builder_csrbank2_dfii_pi1_address0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r; +reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w; +reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_command0_r; +reg builder_csrbank2_dfii_pi1_command0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_command0_w; +reg builder_csrbank2_dfii_pi1_command0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_rddata0_r; +reg builder_csrbank2_dfii_pi1_rddata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_rddata0_w; +reg builder_csrbank2_dfii_pi1_rddata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_rddata1_r; +reg builder_csrbank2_dfii_pi1_rddata1_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_rddata1_w; +reg builder_csrbank2_dfii_pi1_rddata1_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_r; +reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_w; +reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_wrdata1_r; +reg builder_csrbank2_dfii_pi1_wrdata1_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_wrdata1_w; +reg builder_csrbank2_dfii_pi1_wrdata1_we = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi2_address0_r; +reg builder_csrbank2_dfii_pi2_address0_re = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi2_address0_w; +reg builder_csrbank2_dfii_pi2_address0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r; +reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w; +reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_command0_r; +reg builder_csrbank2_dfii_pi2_command0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_command0_w; +reg builder_csrbank2_dfii_pi2_command0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_rddata0_r; +reg builder_csrbank2_dfii_pi2_rddata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_rddata0_w; +reg builder_csrbank2_dfii_pi2_rddata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_rddata1_r; +reg builder_csrbank2_dfii_pi2_rddata1_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_rddata1_w; +reg builder_csrbank2_dfii_pi2_rddata1_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_r; +reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_w; +reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_wrdata1_r; +reg builder_csrbank2_dfii_pi2_wrdata1_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_wrdata1_w; +reg builder_csrbank2_dfii_pi2_wrdata1_we = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi3_address0_r; +reg builder_csrbank2_dfii_pi3_address0_re = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi3_address0_w; +reg builder_csrbank2_dfii_pi3_address0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r; +reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w; +reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_command0_r; +reg builder_csrbank2_dfii_pi3_command0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_command0_w; +reg builder_csrbank2_dfii_pi3_command0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_rddata0_r; +reg builder_csrbank2_dfii_pi3_rddata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_rddata0_w; +reg builder_csrbank2_dfii_pi3_rddata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_rddata1_r; +reg builder_csrbank2_dfii_pi3_rddata1_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_rddata1_w; +reg builder_csrbank2_dfii_pi3_rddata1_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_r; +reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_w; +reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_wrdata1_r; +reg builder_csrbank2_dfii_pi3_wrdata1_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_wrdata1_w; +reg builder_csrbank2_dfii_pi3_wrdata1_we = 1'd0; +wire builder_csrbank2_sel; +wire [31:0] builder_dat_r; +wire [31:0] builder_dat_w; +reg builder_interface0_ack = 1'd0; +wire [29:0] builder_interface0_adr; +wire [13:0] builder_interface0_bank_bus_adr; +reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface0_bank_bus_dat_w; +wire builder_interface0_bank_bus_we; +wire [1:0] builder_interface0_bte; +wire [2:0] builder_interface0_cti; +wire builder_interface0_cyc; +reg [31:0] builder_interface0_dat_r = 32'd0; +wire [31:0] builder_interface0_dat_w; +reg builder_interface0_err = 1'd0; +wire [3:0] builder_interface0_sel; +wire builder_interface0_stb; +wire builder_interface0_we; +reg [13:0] builder_interface1_adr = 14'd0; +reg [13:0] builder_interface1_adr_next_value1 = 14'd0; +reg builder_interface1_adr_next_value_ce1 = 1'd0; +wire [13:0] builder_interface1_bank_bus_adr; +reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface1_bank_bus_dat_w; +wire builder_interface1_bank_bus_we; +wire [31:0] builder_interface1_dat_r; +reg [31:0] builder_interface1_dat_w = 32'd0; +reg [31:0] builder_interface1_dat_w_next_value0 = 32'd0; +reg builder_interface1_dat_w_next_value_ce0 = 1'd0; +reg builder_interface1_we = 1'd0; +reg builder_interface1_we_next_value2 = 1'd0; +reg builder_interface1_we_next_value_ce2 = 1'd0; +wire [13:0] builder_interface2_bank_bus_adr; +reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface2_bank_bus_dat_w; +wire builder_interface2_bank_bus_we; +reg builder_locked0 = 1'd0; +reg builder_locked1 = 1'd0; +reg builder_locked2 = 1'd0; +reg builder_locked3 = 1'd0; +reg builder_locked4 = 1'd0; +reg builder_locked5 = 1'd0; +reg builder_locked6 = 1'd0; +reg builder_locked7 = 1'd0; +reg [3:0] builder_multiplexer_next_state = 4'd0; +reg [3:0] builder_multiplexer_state = 4'd0; +reg builder_new_master_rdata_valid0 = 1'd0; +reg builder_new_master_rdata_valid1 = 1'd0; +reg builder_new_master_rdata_valid2 = 1'd0; +reg builder_new_master_rdata_valid3 = 1'd0; +reg builder_new_master_rdata_valid4 = 1'd0; +reg builder_new_master_rdata_valid5 = 1'd0; +reg builder_new_master_rdata_valid6 = 1'd0; +reg builder_new_master_rdata_valid7 = 1'd0; +reg builder_new_master_rdata_valid8 = 1'd0; +reg builder_new_master_wdata_ready0 = 1'd0; +reg builder_new_master_wdata_ready1 = 1'd0; +reg [1:0] builder_next_state = 2'd0; +wire builder_pll_fb; +reg [1:0] builder_refresher_next_state = 2'd0; +reg [1:0] builder_refresher_state = 2'd0; +wire builder_reset0; +wire builder_reset1; +wire builder_reset2; +wire builder_reset3; +wire builder_reset4; +wire builder_reset5; +wire builder_reset6; +wire builder_reset7; +reg builder_rhs_self0 = 1'd0; +reg [14:0] builder_rhs_self1 = 15'd0; +reg builder_rhs_self10 = 1'd0; +reg builder_rhs_self11 = 1'd0; +reg [21:0] builder_rhs_self12 = 22'd0; +reg builder_rhs_self13 = 1'd0; +reg builder_rhs_self14 = 1'd0; +reg [21:0] builder_rhs_self15 = 22'd0; +reg builder_rhs_self16 = 1'd0; +reg builder_rhs_self17 = 1'd0; +reg [21:0] builder_rhs_self18 = 22'd0; +reg builder_rhs_self19 = 1'd0; +reg [2:0] builder_rhs_self2 = 3'd0; +reg builder_rhs_self20 = 1'd0; +reg [21:0] builder_rhs_self21 = 22'd0; +reg builder_rhs_self22 = 1'd0; +reg builder_rhs_self23 = 1'd0; +reg [21:0] builder_rhs_self24 = 22'd0; +reg builder_rhs_self25 = 1'd0; +reg builder_rhs_self26 = 1'd0; +reg [21:0] builder_rhs_self27 = 22'd0; +reg builder_rhs_self28 = 1'd0; +reg builder_rhs_self29 = 1'd0; +reg builder_rhs_self3 = 1'd0; +reg [21:0] builder_rhs_self30 = 22'd0; +reg builder_rhs_self31 = 1'd0; +reg builder_rhs_self32 = 1'd0; +reg [21:0] builder_rhs_self33 = 22'd0; +reg builder_rhs_self34 = 1'd0; +reg builder_rhs_self35 = 1'd0; +reg builder_rhs_self4 = 1'd0; +reg builder_rhs_self5 = 1'd0; +reg builder_rhs_self6 = 1'd0; +reg [14:0] builder_rhs_self7 = 15'd0; +reg [2:0] builder_rhs_self8 = 3'd0; +reg builder_rhs_self9 = 1'd0; +wire builder_roundrobin0_ce; +wire builder_roundrobin0_grant; +wire builder_roundrobin0_request; +wire builder_roundrobin1_ce; +wire builder_roundrobin1_grant; +wire builder_roundrobin1_request; +wire builder_roundrobin2_ce; +wire builder_roundrobin2_grant; +wire builder_roundrobin2_request; +wire builder_roundrobin3_ce; +wire builder_roundrobin3_grant; +wire builder_roundrobin3_request; +wire builder_roundrobin4_ce; +wire builder_roundrobin4_grant; +wire builder_roundrobin4_request; +wire builder_roundrobin5_ce; +wire builder_roundrobin5_grant; +wire builder_roundrobin5_request; +wire builder_roundrobin6_ce; +wire builder_roundrobin6_grant; +wire builder_roundrobin6_request; +wire builder_roundrobin7_ce; +wire builder_roundrobin7_grant; +wire builder_roundrobin7_request; +reg [2:0] builder_self0 = 3'd0; +reg [14:0] builder_self1 = 15'd0; +reg builder_self10 = 1'd0; +reg builder_self11 = 1'd0; +reg builder_self12 = 1'd0; +reg builder_self13 = 1'd0; +reg [2:0] builder_self14 = 3'd0; +reg [14:0] builder_self15 = 15'd0; +reg builder_self16 = 1'd0; +reg builder_self17 = 1'd0; +reg builder_self18 = 1'd0; +reg builder_self19 = 1'd0; +reg builder_self2 = 1'd0; +reg builder_self20 = 1'd0; +reg [2:0] builder_self21 = 3'd0; +reg [14:0] builder_self22 = 15'd0; +reg builder_self23 = 1'd0; +reg builder_self24 = 1'd0; +reg builder_self25 = 1'd0; +reg builder_self26 = 1'd0; +reg builder_self27 = 1'd0; +reg builder_self3 = 1'd0; +reg builder_self4 = 1'd0; +reg builder_self5 = 1'd0; +reg builder_self6 = 1'd0; +reg [2:0] builder_self7 = 3'd0; +reg [14:0] builder_self8 = 15'd0; +reg builder_self9 = 1'd0; +reg [1:0] builder_state = 2'd0; +reg builder_t_self0 = 1'd0; +reg builder_t_self1 = 1'd0; +reg builder_t_self2 = 1'd0; +reg builder_t_self3 = 1'd0; +reg builder_t_self4 = 1'd0; +reg builder_t_self5 = 1'd0; +wire builder_we; +wire builder_xilinxasyncresetsynchronizerimpl0_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl1_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl2_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl2_expr; +wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl3_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl3_expr; +wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta; wire iodelay_clk; wire iodelay_rst; -wire reset; -reg power_down = 1'd0; -wire locked; -wire clkin; -wire clkout0; -wire clkout_buf0; -wire clkout1; -wire clkout_buf1; -wire clkout2; -wire clkout_buf2; -wire clkout3; -wire clkout_buf3; -reg [3:0] reset_counter = 4'd15; -reg ic_reset = 1'd1; -reg k7ddrphy_rst_storage = 1'd0; -reg k7ddrphy_rst_re = 1'd0; -reg [3:0] k7ddrphy_dly_sel_storage = 4'd0; -reg k7ddrphy_dly_sel_re = 1'd0; -reg [4:0] k7ddrphy_half_sys8x_taps_storage = 5'd8; -reg k7ddrphy_half_sys8x_taps_re = 1'd0; -reg k7ddrphy_wlevel_en_storage = 1'd0; -reg k7ddrphy_wlevel_en_re = 1'd0; -reg k7ddrphy_wlevel_strobe_re = 1'd0; -wire k7ddrphy_wlevel_strobe_r; -reg k7ddrphy_wlevel_strobe_we = 1'd0; -reg k7ddrphy_wlevel_strobe_w = 1'd0; -reg k7ddrphy_cdly_rst_re = 1'd0; -wire k7ddrphy_cdly_rst_r; -reg k7ddrphy_cdly_rst_we = 1'd0; -reg k7ddrphy_cdly_rst_w = 1'd0; -reg k7ddrphy_cdly_inc_re = 1'd0; -wire k7ddrphy_cdly_inc_r; -reg k7ddrphy_cdly_inc_we = 1'd0; -reg k7ddrphy_cdly_inc_w = 1'd0; -reg k7ddrphy_rdly_dq_rst_re = 1'd0; -wire k7ddrphy_rdly_dq_rst_r; -reg k7ddrphy_rdly_dq_rst_we = 1'd0; -reg k7ddrphy_rdly_dq_rst_w = 1'd0; -reg k7ddrphy_rdly_dq_inc_re = 1'd0; -wire k7ddrphy_rdly_dq_inc_r; -reg k7ddrphy_rdly_dq_inc_we = 1'd0; -reg k7ddrphy_rdly_dq_inc_w = 1'd0; -reg k7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; -wire k7ddrphy_rdly_dq_bitslip_rst_r; -reg k7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; -reg k7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; -reg k7ddrphy_rdly_dq_bitslip_re = 1'd0; -wire k7ddrphy_rdly_dq_bitslip_r; -reg k7ddrphy_rdly_dq_bitslip_we = 1'd0; -reg k7ddrphy_rdly_dq_bitslip_w = 1'd0; -reg k7ddrphy_wdly_dq_rst_re = 1'd0; -wire k7ddrphy_wdly_dq_rst_r; -reg k7ddrphy_wdly_dq_rst_we = 1'd0; -reg k7ddrphy_wdly_dq_rst_w = 1'd0; -reg k7ddrphy_wdly_dq_inc_re = 1'd0; -wire k7ddrphy_wdly_dq_inc_r; -reg k7ddrphy_wdly_dq_inc_we = 1'd0; -reg k7ddrphy_wdly_dq_inc_w = 1'd0; -reg k7ddrphy_wdly_dqs_rst_re = 1'd0; -wire k7ddrphy_wdly_dqs_rst_r; -reg k7ddrphy_wdly_dqs_rst_we = 1'd0; -reg k7ddrphy_wdly_dqs_rst_w = 1'd0; -reg k7ddrphy_wdly_dqs_inc_re = 1'd0; -wire k7ddrphy_wdly_dqs_inc_r; -reg k7ddrphy_wdly_dqs_inc_we = 1'd0; -reg k7ddrphy_wdly_dqs_inc_w = 1'd0; -reg k7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; -wire k7ddrphy_wdly_dq_bitslip_rst_r; -reg k7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; -reg k7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; -reg k7ddrphy_wdly_dq_bitslip_re = 1'd0; -wire k7ddrphy_wdly_dq_bitslip_r; -reg k7ddrphy_wdly_dq_bitslip_we = 1'd0; -reg k7ddrphy_wdly_dq_bitslip_w = 1'd0; -reg [1:0] k7ddrphy_rdphase_storage = 2'd1; -reg k7ddrphy_rdphase_re = 1'd0; -reg [1:0] k7ddrphy_wrphase_storage = 2'd2; -reg k7ddrphy_wrphase_re = 1'd0; -wire [14:0] k7ddrphy_dfi_p0_address; -wire [2:0] k7ddrphy_dfi_p0_bank; -wire k7ddrphy_dfi_p0_cas_n; -wire k7ddrphy_dfi_p0_cs_n; -wire k7ddrphy_dfi_p0_ras_n; -wire k7ddrphy_dfi_p0_we_n; -wire k7ddrphy_dfi_p0_cke; -wire k7ddrphy_dfi_p0_odt; -wire k7ddrphy_dfi_p0_reset_n; -wire k7ddrphy_dfi_p0_act_n; -wire [63:0] k7ddrphy_dfi_p0_wrdata; -wire k7ddrphy_dfi_p0_wrdata_en; -wire [7:0] k7ddrphy_dfi_p0_wrdata_mask; -wire k7ddrphy_dfi_p0_rddata_en; -reg [63:0] k7ddrphy_dfi_p0_rddata = 64'd0; -wire k7ddrphy_dfi_p0_rddata_valid; -wire [14:0] k7ddrphy_dfi_p1_address; -wire [2:0] k7ddrphy_dfi_p1_bank; -wire k7ddrphy_dfi_p1_cas_n; -wire k7ddrphy_dfi_p1_cs_n; -wire k7ddrphy_dfi_p1_ras_n; -wire k7ddrphy_dfi_p1_we_n; -wire k7ddrphy_dfi_p1_cke; -wire k7ddrphy_dfi_p1_odt; -wire k7ddrphy_dfi_p1_reset_n; -wire k7ddrphy_dfi_p1_act_n; -wire [63:0] k7ddrphy_dfi_p1_wrdata; -wire k7ddrphy_dfi_p1_wrdata_en; -wire [7:0] k7ddrphy_dfi_p1_wrdata_mask; -wire k7ddrphy_dfi_p1_rddata_en; -reg [63:0] k7ddrphy_dfi_p1_rddata = 64'd0; -wire k7ddrphy_dfi_p1_rddata_valid; -wire [14:0] k7ddrphy_dfi_p2_address; -wire [2:0] k7ddrphy_dfi_p2_bank; -wire k7ddrphy_dfi_p2_cas_n; -wire k7ddrphy_dfi_p2_cs_n; -wire k7ddrphy_dfi_p2_ras_n; -wire k7ddrphy_dfi_p2_we_n; -wire k7ddrphy_dfi_p2_cke; -wire k7ddrphy_dfi_p2_odt; -wire k7ddrphy_dfi_p2_reset_n; -wire k7ddrphy_dfi_p2_act_n; -wire [63:0] k7ddrphy_dfi_p2_wrdata; -wire k7ddrphy_dfi_p2_wrdata_en; -wire [7:0] k7ddrphy_dfi_p2_wrdata_mask; -wire k7ddrphy_dfi_p2_rddata_en; -reg [63:0] k7ddrphy_dfi_p2_rddata = 64'd0; -wire k7ddrphy_dfi_p2_rddata_valid; -wire [14:0] k7ddrphy_dfi_p3_address; -wire [2:0] k7ddrphy_dfi_p3_bank; -wire k7ddrphy_dfi_p3_cas_n; -wire k7ddrphy_dfi_p3_cs_n; -wire k7ddrphy_dfi_p3_ras_n; -wire k7ddrphy_dfi_p3_we_n; -wire k7ddrphy_dfi_p3_cke; -wire k7ddrphy_dfi_p3_odt; -wire k7ddrphy_dfi_p3_reset_n; -wire k7ddrphy_dfi_p3_act_n; -wire [63:0] k7ddrphy_dfi_p3_wrdata; -wire k7ddrphy_dfi_p3_wrdata_en; -wire [7:0] k7ddrphy_dfi_p3_wrdata_mask; -wire k7ddrphy_dfi_p3_rddata_en; -reg [63:0] k7ddrphy_dfi_p3_rddata = 64'd0; -wire k7ddrphy_dfi_p3_rddata_valid; -wire k7ddrphy_sd_clk_se_nodelay; -wire k7ddrphy_sd_clk_se_delayed; -wire [2:0] k7ddrphy_pads_ba; -wire k7ddrphy_oq0; -wire k7ddrphy_oq1; -wire k7ddrphy_oq2; -wire k7ddrphy_oq3; -wire k7ddrphy_oq4; -wire k7ddrphy_oq5; -wire k7ddrphy_oq6; -wire k7ddrphy_oq7; -wire k7ddrphy_oq8; -wire k7ddrphy_oq9; -wire k7ddrphy_oq10; -wire k7ddrphy_oq11; -wire k7ddrphy_oq12; -wire k7ddrphy_oq13; -wire k7ddrphy_oq14; -wire k7ddrphy_oq15; -wire k7ddrphy_oq16; -wire k7ddrphy_oq17; -wire k7ddrphy_oq18; -wire k7ddrphy_oq19; -wire k7ddrphy_oq20; -wire k7ddrphy_oq21; -wire k7ddrphy_oq22; -wire k7ddrphy_oq23; -wire k7ddrphy_oq24; -reg k7ddrphy_dqs_oe = 1'd0; -wire k7ddrphy_dqs_preamble; -wire k7ddrphy_dqs_postamble; -wire k7ddrphy_dqs_oe_delay_tappeddelayline; -reg k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -reg k7ddrphy_dqspattern0 = 1'd0; -reg k7ddrphy_dqspattern1 = 1'd0; -reg [7:0] k7ddrphy_dqspattern_o = 8'd0; -wire k7ddrphy_dqs_o_no_delay0; -wire k7ddrphy_dqs_o_delayed0; -wire k7ddrphy_dqs_t0; -reg [7:0] k7ddrphy_bitslip00 = 8'd0; -reg [2:0] k7ddrphy_bitslip0_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip0_r0 = 16'd0; -wire k7ddrphy0; -wire k7ddrphy_dqs_o_no_delay1; -wire k7ddrphy_dqs_o_delayed1; -wire k7ddrphy_dqs_t1; -reg [7:0] k7ddrphy_bitslip10 = 8'd0; -reg [2:0] k7ddrphy_bitslip1_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip1_r0 = 16'd0; -wire k7ddrphy1; -wire k7ddrphy_dqs_o_no_delay2; -wire k7ddrphy_dqs_o_delayed2; -wire k7ddrphy_dqs_t2; -reg [7:0] k7ddrphy_bitslip20 = 8'd0; -reg [2:0] k7ddrphy_bitslip2_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip2_r0 = 16'd0; -wire k7ddrphy2; -wire k7ddrphy_dqs_o_no_delay3; -wire k7ddrphy_dqs_o_delayed3; -wire k7ddrphy_dqs_t3; -reg [7:0] k7ddrphy_bitslip30 = 8'd0; -reg [2:0] k7ddrphy_bitslip3_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip3_r0 = 16'd0; -wire k7ddrphy3; -wire k7ddrphy_dm_o_nodelay0; -reg [7:0] k7ddrphy_bitslip01 = 8'd0; -reg [2:0] k7ddrphy_bitslip0_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip0_r1 = 16'd0; -wire k7ddrphy_dm_o_nodelay1; -reg [7:0] k7ddrphy_bitslip11 = 8'd0; -reg [2:0] k7ddrphy_bitslip1_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip1_r1 = 16'd0; -wire k7ddrphy_dm_o_nodelay2; -reg [7:0] k7ddrphy_bitslip21 = 8'd0; -reg [2:0] k7ddrphy_bitslip2_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip2_r1 = 16'd0; -wire k7ddrphy_dm_o_nodelay3; -reg [7:0] k7ddrphy_bitslip31 = 8'd0; -reg [2:0] k7ddrphy_bitslip3_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip3_r1 = 16'd0; -wire k7ddrphy_dq_oe; -wire k7ddrphy_dq_oe_delay_tappeddelayline; -reg k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -wire k7ddrphy_dq_o_nodelay0; -wire k7ddrphy_dq_o_delayed0; -wire k7ddrphy_dq_i_nodelay0; -wire k7ddrphy_dq_i_delayed0; -wire k7ddrphy_dq_t0; -reg [7:0] k7ddrphy_bitslip02 = 8'd0; -reg [2:0] k7ddrphy_bitslip0_value2 = 3'd7; -reg [15:0] k7ddrphy_bitslip0_r2 = 16'd0; -wire [7:0] k7ddrphy_bitslip03; -reg [7:0] k7ddrphy_bitslip04 = 8'd0; -reg [2:0] k7ddrphy_bitslip0_value3 = 3'd7; -reg [15:0] k7ddrphy_bitslip0_r3 = 16'd0; -wire k7ddrphy_dq_o_nodelay1; -wire k7ddrphy_dq_o_delayed1; -wire k7ddrphy_dq_i_nodelay1; -wire k7ddrphy_dq_i_delayed1; -wire k7ddrphy_dq_t1; -reg [7:0] k7ddrphy_bitslip12 = 8'd0; -reg [2:0] k7ddrphy_bitslip1_value2 = 3'd7; -reg [15:0] k7ddrphy_bitslip1_r2 = 16'd0; -wire [7:0] k7ddrphy_bitslip13; -reg [7:0] k7ddrphy_bitslip14 = 8'd0; -reg [2:0] k7ddrphy_bitslip1_value3 = 3'd7; -reg [15:0] k7ddrphy_bitslip1_r3 = 16'd0; -wire k7ddrphy_dq_o_nodelay2; -wire k7ddrphy_dq_o_delayed2; -wire k7ddrphy_dq_i_nodelay2; -wire k7ddrphy_dq_i_delayed2; -wire k7ddrphy_dq_t2; -reg [7:0] k7ddrphy_bitslip22 = 8'd0; -reg [2:0] k7ddrphy_bitslip2_value2 = 3'd7; -reg [15:0] k7ddrphy_bitslip2_r2 = 16'd0; -wire [7:0] k7ddrphy_bitslip23; -reg [7:0] k7ddrphy_bitslip24 = 8'd0; -reg [2:0] k7ddrphy_bitslip2_value3 = 3'd7; -reg [15:0] k7ddrphy_bitslip2_r3 = 16'd0; -wire k7ddrphy_dq_o_nodelay3; -wire k7ddrphy_dq_o_delayed3; -wire k7ddrphy_dq_i_nodelay3; -wire k7ddrphy_dq_i_delayed3; -wire k7ddrphy_dq_t3; -reg [7:0] k7ddrphy_bitslip32 = 8'd0; -reg [2:0] k7ddrphy_bitslip3_value2 = 3'd7; -reg [15:0] k7ddrphy_bitslip3_r2 = 16'd0; -wire [7:0] k7ddrphy_bitslip33; -reg [7:0] k7ddrphy_bitslip34 = 8'd0; -reg [2:0] k7ddrphy_bitslip3_value3 = 3'd7; -reg [15:0] k7ddrphy_bitslip3_r3 = 16'd0; -wire k7ddrphy_dq_o_nodelay4; -wire k7ddrphy_dq_o_delayed4; -wire k7ddrphy_dq_i_nodelay4; -wire k7ddrphy_dq_i_delayed4; -wire k7ddrphy_dq_t4; -reg [7:0] k7ddrphy_bitslip40 = 8'd0; -reg [2:0] k7ddrphy_bitslip4_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip4_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip41; -reg [7:0] k7ddrphy_bitslip42 = 8'd0; -reg [2:0] k7ddrphy_bitslip4_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip4_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay5; -wire k7ddrphy_dq_o_delayed5; -wire k7ddrphy_dq_i_nodelay5; -wire k7ddrphy_dq_i_delayed5; -wire k7ddrphy_dq_t5; -reg [7:0] k7ddrphy_bitslip50 = 8'd0; -reg [2:0] k7ddrphy_bitslip5_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip5_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip51; -reg [7:0] k7ddrphy_bitslip52 = 8'd0; -reg [2:0] k7ddrphy_bitslip5_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip5_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay6; -wire k7ddrphy_dq_o_delayed6; -wire k7ddrphy_dq_i_nodelay6; -wire k7ddrphy_dq_i_delayed6; -wire k7ddrphy_dq_t6; -reg [7:0] k7ddrphy_bitslip60 = 8'd0; -reg [2:0] k7ddrphy_bitslip6_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip6_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip61; -reg [7:0] k7ddrphy_bitslip62 = 8'd0; -reg [2:0] k7ddrphy_bitslip6_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip6_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay7; -wire k7ddrphy_dq_o_delayed7; -wire k7ddrphy_dq_i_nodelay7; -wire k7ddrphy_dq_i_delayed7; -wire k7ddrphy_dq_t7; -reg [7:0] k7ddrphy_bitslip70 = 8'd0; -reg [2:0] k7ddrphy_bitslip7_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip7_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip71; -reg [7:0] k7ddrphy_bitslip72 = 8'd0; -reg [2:0] k7ddrphy_bitslip7_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip7_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay8; -wire k7ddrphy_dq_o_delayed8; -wire k7ddrphy_dq_i_nodelay8; -wire k7ddrphy_dq_i_delayed8; -wire k7ddrphy_dq_t8; -reg [7:0] k7ddrphy_bitslip80 = 8'd0; -reg [2:0] k7ddrphy_bitslip8_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip8_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip81; -reg [7:0] k7ddrphy_bitslip82 = 8'd0; -reg [2:0] k7ddrphy_bitslip8_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip8_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay9; -wire k7ddrphy_dq_o_delayed9; -wire k7ddrphy_dq_i_nodelay9; -wire k7ddrphy_dq_i_delayed9; -wire k7ddrphy_dq_t9; -reg [7:0] k7ddrphy_bitslip90 = 8'd0; -reg [2:0] k7ddrphy_bitslip9_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip9_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip91; -reg [7:0] k7ddrphy_bitslip92 = 8'd0; -reg [2:0] k7ddrphy_bitslip9_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip9_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay10; -wire k7ddrphy_dq_o_delayed10; -wire k7ddrphy_dq_i_nodelay10; -wire k7ddrphy_dq_i_delayed10; -wire k7ddrphy_dq_t10; -reg [7:0] k7ddrphy_bitslip100 = 8'd0; -reg [2:0] k7ddrphy_bitslip10_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip10_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip101; -reg [7:0] k7ddrphy_bitslip102 = 8'd0; -reg [2:0] k7ddrphy_bitslip10_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip10_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay11; -wire k7ddrphy_dq_o_delayed11; -wire k7ddrphy_dq_i_nodelay11; -wire k7ddrphy_dq_i_delayed11; -wire k7ddrphy_dq_t11; -reg [7:0] k7ddrphy_bitslip110 = 8'd0; -reg [2:0] k7ddrphy_bitslip11_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip11_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip111; -reg [7:0] k7ddrphy_bitslip112 = 8'd0; -reg [2:0] k7ddrphy_bitslip11_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip11_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay12; -wire k7ddrphy_dq_o_delayed12; -wire k7ddrphy_dq_i_nodelay12; -wire k7ddrphy_dq_i_delayed12; -wire k7ddrphy_dq_t12; -reg [7:0] k7ddrphy_bitslip120 = 8'd0; -reg [2:0] k7ddrphy_bitslip12_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip12_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip121; -reg [7:0] k7ddrphy_bitslip122 = 8'd0; -reg [2:0] k7ddrphy_bitslip12_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip12_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay13; -wire k7ddrphy_dq_o_delayed13; -wire k7ddrphy_dq_i_nodelay13; -wire k7ddrphy_dq_i_delayed13; -wire k7ddrphy_dq_t13; -reg [7:0] k7ddrphy_bitslip130 = 8'd0; -reg [2:0] k7ddrphy_bitslip13_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip13_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip131; -reg [7:0] k7ddrphy_bitslip132 = 8'd0; -reg [2:0] k7ddrphy_bitslip13_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip13_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay14; -wire k7ddrphy_dq_o_delayed14; -wire k7ddrphy_dq_i_nodelay14; -wire k7ddrphy_dq_i_delayed14; -wire k7ddrphy_dq_t14; -reg [7:0] k7ddrphy_bitslip140 = 8'd0; -reg [2:0] k7ddrphy_bitslip14_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip14_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip141; -reg [7:0] k7ddrphy_bitslip142 = 8'd0; -reg [2:0] k7ddrphy_bitslip14_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip14_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay15; -wire k7ddrphy_dq_o_delayed15; -wire k7ddrphy_dq_i_nodelay15; -wire k7ddrphy_dq_i_delayed15; -wire k7ddrphy_dq_t15; -reg [7:0] k7ddrphy_bitslip150 = 8'd0; -reg [2:0] k7ddrphy_bitslip15_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip15_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip151; -reg [7:0] k7ddrphy_bitslip152 = 8'd0; -reg [2:0] k7ddrphy_bitslip15_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip15_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay16; -wire k7ddrphy_dq_o_delayed16; -wire k7ddrphy_dq_i_nodelay16; -wire k7ddrphy_dq_i_delayed16; -wire k7ddrphy_dq_t16; -reg [7:0] k7ddrphy_bitslip160 = 8'd0; -reg [2:0] k7ddrphy_bitslip16_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip16_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip161; -reg [7:0] k7ddrphy_bitslip162 = 8'd0; -reg [2:0] k7ddrphy_bitslip16_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip16_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay17; -wire k7ddrphy_dq_o_delayed17; -wire k7ddrphy_dq_i_nodelay17; -wire k7ddrphy_dq_i_delayed17; -wire k7ddrphy_dq_t17; -reg [7:0] k7ddrphy_bitslip170 = 8'd0; -reg [2:0] k7ddrphy_bitslip17_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip17_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip171; -reg [7:0] k7ddrphy_bitslip172 = 8'd0; -reg [2:0] k7ddrphy_bitslip17_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip17_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay18; -wire k7ddrphy_dq_o_delayed18; -wire k7ddrphy_dq_i_nodelay18; -wire k7ddrphy_dq_i_delayed18; -wire k7ddrphy_dq_t18; -reg [7:0] k7ddrphy_bitslip180 = 8'd0; -reg [2:0] k7ddrphy_bitslip18_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip18_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip181; -reg [7:0] k7ddrphy_bitslip182 = 8'd0; -reg [2:0] k7ddrphy_bitslip18_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip18_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay19; -wire k7ddrphy_dq_o_delayed19; -wire k7ddrphy_dq_i_nodelay19; -wire k7ddrphy_dq_i_delayed19; -wire k7ddrphy_dq_t19; -reg [7:0] k7ddrphy_bitslip190 = 8'd0; -reg [2:0] k7ddrphy_bitslip19_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip19_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip191; -reg [7:0] k7ddrphy_bitslip192 = 8'd0; -reg [2:0] k7ddrphy_bitslip19_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip19_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay20; -wire k7ddrphy_dq_o_delayed20; -wire k7ddrphy_dq_i_nodelay20; -wire k7ddrphy_dq_i_delayed20; -wire k7ddrphy_dq_t20; -reg [7:0] k7ddrphy_bitslip200 = 8'd0; -reg [2:0] k7ddrphy_bitslip20_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip20_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip201; -reg [7:0] k7ddrphy_bitslip202 = 8'd0; -reg [2:0] k7ddrphy_bitslip20_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip20_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay21; -wire k7ddrphy_dq_o_delayed21; -wire k7ddrphy_dq_i_nodelay21; -wire k7ddrphy_dq_i_delayed21; -wire k7ddrphy_dq_t21; -reg [7:0] k7ddrphy_bitslip210 = 8'd0; -reg [2:0] k7ddrphy_bitslip21_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip21_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip211; -reg [7:0] k7ddrphy_bitslip212 = 8'd0; -reg [2:0] k7ddrphy_bitslip21_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip21_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay22; -wire k7ddrphy_dq_o_delayed22; -wire k7ddrphy_dq_i_nodelay22; -wire k7ddrphy_dq_i_delayed22; -wire k7ddrphy_dq_t22; -reg [7:0] k7ddrphy_bitslip220 = 8'd0; -reg [2:0] k7ddrphy_bitslip22_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip22_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip221; -reg [7:0] k7ddrphy_bitslip222 = 8'd0; -reg [2:0] k7ddrphy_bitslip22_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip22_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay23; -wire k7ddrphy_dq_o_delayed23; -wire k7ddrphy_dq_i_nodelay23; -wire k7ddrphy_dq_i_delayed23; -wire k7ddrphy_dq_t23; -reg [7:0] k7ddrphy_bitslip230 = 8'd0; -reg [2:0] k7ddrphy_bitslip23_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip23_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip231; -reg [7:0] k7ddrphy_bitslip232 = 8'd0; -reg [2:0] k7ddrphy_bitslip23_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip23_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay24; -wire k7ddrphy_dq_o_delayed24; -wire k7ddrphy_dq_i_nodelay24; -wire k7ddrphy_dq_i_delayed24; -wire k7ddrphy_dq_t24; -reg [7:0] k7ddrphy_bitslip240 = 8'd0; -reg [2:0] k7ddrphy_bitslip24_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip24_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip241; -reg [7:0] k7ddrphy_bitslip242 = 8'd0; -reg [2:0] k7ddrphy_bitslip24_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip24_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay25; -wire k7ddrphy_dq_o_delayed25; -wire k7ddrphy_dq_i_nodelay25; -wire k7ddrphy_dq_i_delayed25; -wire k7ddrphy_dq_t25; -reg [7:0] k7ddrphy_bitslip250 = 8'd0; -reg [2:0] k7ddrphy_bitslip25_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip25_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip251; -reg [7:0] k7ddrphy_bitslip252 = 8'd0; -reg [2:0] k7ddrphy_bitslip25_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip25_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay26; -wire k7ddrphy_dq_o_delayed26; -wire k7ddrphy_dq_i_nodelay26; -wire k7ddrphy_dq_i_delayed26; -wire k7ddrphy_dq_t26; -reg [7:0] k7ddrphy_bitslip260 = 8'd0; -reg [2:0] k7ddrphy_bitslip26_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip26_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip261; -reg [7:0] k7ddrphy_bitslip262 = 8'd0; -reg [2:0] k7ddrphy_bitslip26_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip26_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay27; -wire k7ddrphy_dq_o_delayed27; -wire k7ddrphy_dq_i_nodelay27; -wire k7ddrphy_dq_i_delayed27; -wire k7ddrphy_dq_t27; -reg [7:0] k7ddrphy_bitslip270 = 8'd0; -reg [2:0] k7ddrphy_bitslip27_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip27_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip271; -reg [7:0] k7ddrphy_bitslip272 = 8'd0; -reg [2:0] k7ddrphy_bitslip27_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip27_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay28; -wire k7ddrphy_dq_o_delayed28; -wire k7ddrphy_dq_i_nodelay28; -wire k7ddrphy_dq_i_delayed28; -wire k7ddrphy_dq_t28; -reg [7:0] k7ddrphy_bitslip280 = 8'd0; -reg [2:0] k7ddrphy_bitslip28_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip28_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip281; -reg [7:0] k7ddrphy_bitslip282 = 8'd0; -reg [2:0] k7ddrphy_bitslip28_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip28_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay29; -wire k7ddrphy_dq_o_delayed29; -wire k7ddrphy_dq_i_nodelay29; -wire k7ddrphy_dq_i_delayed29; -wire k7ddrphy_dq_t29; -reg [7:0] k7ddrphy_bitslip290 = 8'd0; -reg [2:0] k7ddrphy_bitslip29_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip29_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip291; -reg [7:0] k7ddrphy_bitslip292 = 8'd0; -reg [2:0] k7ddrphy_bitslip29_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip29_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay30; -wire k7ddrphy_dq_o_delayed30; -wire k7ddrphy_dq_i_nodelay30; -wire k7ddrphy_dq_i_delayed30; -wire k7ddrphy_dq_t30; -reg [7:0] k7ddrphy_bitslip300 = 8'd0; -reg [2:0] k7ddrphy_bitslip30_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip30_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip301; -reg [7:0] k7ddrphy_bitslip302 = 8'd0; -reg [2:0] k7ddrphy_bitslip30_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip30_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay31; -wire k7ddrphy_dq_o_delayed31; -wire k7ddrphy_dq_i_nodelay31; -wire k7ddrphy_dq_i_delayed31; -wire k7ddrphy_dq_t31; -reg [7:0] k7ddrphy_bitslip310 = 8'd0; -reg [2:0] k7ddrphy_bitslip31_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip31_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip311; -reg [7:0] k7ddrphy_bitslip312 = 8'd0; -reg [2:0] k7ddrphy_bitslip31_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip31_r1 = 16'd0; -reg k7ddrphy_rddata_en_tappeddelayline0 = 1'd0; -reg k7ddrphy_rddata_en_tappeddelayline1 = 1'd0; -reg k7ddrphy_rddata_en_tappeddelayline2 = 1'd0; -reg k7ddrphy_rddata_en_tappeddelayline3 = 1'd0; -reg k7ddrphy_rddata_en_tappeddelayline4 = 1'd0; -reg k7ddrphy_rddata_en_tappeddelayline5 = 1'd0; -reg k7ddrphy_rddata_en_tappeddelayline6 = 1'd0; -reg k7ddrphy_rddata_en_tappeddelayline7 = 1'd0; -reg k7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; -reg k7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; -reg k7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; -wire [14:0] litedramcore_slave_p0_address; -wire [2:0] litedramcore_slave_p0_bank; -wire litedramcore_slave_p0_cas_n; -wire litedramcore_slave_p0_cs_n; -wire litedramcore_slave_p0_ras_n; -wire litedramcore_slave_p0_we_n; -wire litedramcore_slave_p0_cke; -wire litedramcore_slave_p0_odt; -wire litedramcore_slave_p0_reset_n; -wire litedramcore_slave_p0_act_n; -wire [63:0] litedramcore_slave_p0_wrdata; -wire litedramcore_slave_p0_wrdata_en; -wire [7:0] litedramcore_slave_p0_wrdata_mask; -wire litedramcore_slave_p0_rddata_en; -reg [63:0] litedramcore_slave_p0_rddata = 64'd0; -reg litedramcore_slave_p0_rddata_valid = 1'd0; -wire [14:0] litedramcore_slave_p1_address; -wire [2:0] litedramcore_slave_p1_bank; -wire litedramcore_slave_p1_cas_n; -wire litedramcore_slave_p1_cs_n; -wire litedramcore_slave_p1_ras_n; -wire litedramcore_slave_p1_we_n; -wire litedramcore_slave_p1_cke; -wire litedramcore_slave_p1_odt; -wire litedramcore_slave_p1_reset_n; -wire litedramcore_slave_p1_act_n; -wire [63:0] litedramcore_slave_p1_wrdata; -wire litedramcore_slave_p1_wrdata_en; -wire [7:0] litedramcore_slave_p1_wrdata_mask; -wire litedramcore_slave_p1_rddata_en; -reg [63:0] litedramcore_slave_p1_rddata = 64'd0; -reg litedramcore_slave_p1_rddata_valid = 1'd0; -wire [14:0] litedramcore_slave_p2_address; -wire [2:0] litedramcore_slave_p2_bank; -wire litedramcore_slave_p2_cas_n; -wire litedramcore_slave_p2_cs_n; -wire litedramcore_slave_p2_ras_n; -wire litedramcore_slave_p2_we_n; -wire litedramcore_slave_p2_cke; -wire litedramcore_slave_p2_odt; -wire litedramcore_slave_p2_reset_n; -wire litedramcore_slave_p2_act_n; -wire [63:0] litedramcore_slave_p2_wrdata; -wire litedramcore_slave_p2_wrdata_en; -wire [7:0] litedramcore_slave_p2_wrdata_mask; -wire litedramcore_slave_p2_rddata_en; -reg [63:0] litedramcore_slave_p2_rddata = 64'd0; -reg litedramcore_slave_p2_rddata_valid = 1'd0; -wire [14:0] litedramcore_slave_p3_address; -wire [2:0] litedramcore_slave_p3_bank; -wire litedramcore_slave_p3_cas_n; -wire litedramcore_slave_p3_cs_n; -wire litedramcore_slave_p3_ras_n; -wire litedramcore_slave_p3_we_n; -wire litedramcore_slave_p3_cke; -wire litedramcore_slave_p3_odt; -wire litedramcore_slave_p3_reset_n; -wire litedramcore_slave_p3_act_n; -wire [63:0] litedramcore_slave_p3_wrdata; -wire litedramcore_slave_p3_wrdata_en; -wire [7:0] litedramcore_slave_p3_wrdata_mask; -wire litedramcore_slave_p3_rddata_en; -reg [63:0] litedramcore_slave_p3_rddata = 64'd0; -reg litedramcore_slave_p3_rddata_valid = 1'd0; -reg [14:0] litedramcore_master_p0_address = 15'd0; -reg [2:0] litedramcore_master_p0_bank = 3'd0; -reg litedramcore_master_p0_cas_n = 1'd1; -reg litedramcore_master_p0_cs_n = 1'd1; -reg litedramcore_master_p0_ras_n = 1'd1; -reg litedramcore_master_p0_we_n = 1'd1; -reg litedramcore_master_p0_cke = 1'd0; -reg litedramcore_master_p0_odt = 1'd0; -reg litedramcore_master_p0_reset_n = 1'd0; -reg litedramcore_master_p0_act_n = 1'd1; -reg [63:0] litedramcore_master_p0_wrdata = 64'd0; -reg litedramcore_master_p0_wrdata_en = 1'd0; -reg [7:0] litedramcore_master_p0_wrdata_mask = 8'd0; -reg litedramcore_master_p0_rddata_en = 1'd0; -wire [63:0] litedramcore_master_p0_rddata; -wire litedramcore_master_p0_rddata_valid; -reg [14:0] litedramcore_master_p1_address = 15'd0; -reg [2:0] litedramcore_master_p1_bank = 3'd0; -reg litedramcore_master_p1_cas_n = 1'd1; -reg litedramcore_master_p1_cs_n = 1'd1; -reg litedramcore_master_p1_ras_n = 1'd1; -reg litedramcore_master_p1_we_n = 1'd1; -reg litedramcore_master_p1_cke = 1'd0; -reg litedramcore_master_p1_odt = 1'd0; -reg litedramcore_master_p1_reset_n = 1'd0; -reg litedramcore_master_p1_act_n = 1'd1; -reg [63:0] litedramcore_master_p1_wrdata = 64'd0; -reg litedramcore_master_p1_wrdata_en = 1'd0; -reg [7:0] litedramcore_master_p1_wrdata_mask = 8'd0; -reg litedramcore_master_p1_rddata_en = 1'd0; -wire [63:0] litedramcore_master_p1_rddata; -wire litedramcore_master_p1_rddata_valid; -reg [14:0] litedramcore_master_p2_address = 15'd0; -reg [2:0] litedramcore_master_p2_bank = 3'd0; -reg litedramcore_master_p2_cas_n = 1'd1; -reg litedramcore_master_p2_cs_n = 1'd1; -reg litedramcore_master_p2_ras_n = 1'd1; -reg litedramcore_master_p2_we_n = 1'd1; -reg litedramcore_master_p2_cke = 1'd0; -reg litedramcore_master_p2_odt = 1'd0; -reg litedramcore_master_p2_reset_n = 1'd0; -reg litedramcore_master_p2_act_n = 1'd1; -reg [63:0] litedramcore_master_p2_wrdata = 64'd0; -reg litedramcore_master_p2_wrdata_en = 1'd0; -reg [7:0] litedramcore_master_p2_wrdata_mask = 8'd0; -reg litedramcore_master_p2_rddata_en = 1'd0; -wire [63:0] litedramcore_master_p2_rddata; -wire litedramcore_master_p2_rddata_valid; -reg [14:0] litedramcore_master_p3_address = 15'd0; -reg [2:0] litedramcore_master_p3_bank = 3'd0; -reg litedramcore_master_p3_cas_n = 1'd1; -reg litedramcore_master_p3_cs_n = 1'd1; -reg litedramcore_master_p3_ras_n = 1'd1; -reg litedramcore_master_p3_we_n = 1'd1; -reg litedramcore_master_p3_cke = 1'd0; -reg litedramcore_master_p3_odt = 1'd0; -reg litedramcore_master_p3_reset_n = 1'd0; -reg litedramcore_master_p3_act_n = 1'd1; -reg [63:0] litedramcore_master_p3_wrdata = 64'd0; -reg litedramcore_master_p3_wrdata_en = 1'd0; -reg [7:0] litedramcore_master_p3_wrdata_mask = 8'd0; -reg litedramcore_master_p3_rddata_en = 1'd0; -wire [63:0] litedramcore_master_p3_rddata; -wire litedramcore_master_p3_rddata_valid; -wire [14:0] litedramcore_csr_dfi_p0_address; -wire [2:0] litedramcore_csr_dfi_p0_bank; -reg litedramcore_csr_dfi_p0_cas_n = 1'd1; -reg litedramcore_csr_dfi_p0_cs_n = 1'd1; -reg litedramcore_csr_dfi_p0_ras_n = 1'd1; -reg litedramcore_csr_dfi_p0_we_n = 1'd1; -wire litedramcore_csr_dfi_p0_cke; -wire litedramcore_csr_dfi_p0_odt; -wire litedramcore_csr_dfi_p0_reset_n; -reg litedramcore_csr_dfi_p0_act_n = 1'd1; -wire [63:0] litedramcore_csr_dfi_p0_wrdata; -wire litedramcore_csr_dfi_p0_wrdata_en; -wire [7:0] litedramcore_csr_dfi_p0_wrdata_mask; -wire litedramcore_csr_dfi_p0_rddata_en; -reg [63:0] litedramcore_csr_dfi_p0_rddata = 64'd0; -reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0; -wire [14:0] litedramcore_csr_dfi_p1_address; -wire [2:0] litedramcore_csr_dfi_p1_bank; -reg litedramcore_csr_dfi_p1_cas_n = 1'd1; -reg litedramcore_csr_dfi_p1_cs_n = 1'd1; -reg litedramcore_csr_dfi_p1_ras_n = 1'd1; -reg litedramcore_csr_dfi_p1_we_n = 1'd1; -wire litedramcore_csr_dfi_p1_cke; -wire litedramcore_csr_dfi_p1_odt; -wire litedramcore_csr_dfi_p1_reset_n; -reg litedramcore_csr_dfi_p1_act_n = 1'd1; -wire [63:0] litedramcore_csr_dfi_p1_wrdata; -wire litedramcore_csr_dfi_p1_wrdata_en; -wire [7:0] litedramcore_csr_dfi_p1_wrdata_mask; -wire litedramcore_csr_dfi_p1_rddata_en; -reg [63:0] litedramcore_csr_dfi_p1_rddata = 64'd0; -reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0; -wire [14:0] litedramcore_csr_dfi_p2_address; -wire [2:0] litedramcore_csr_dfi_p2_bank; -reg litedramcore_csr_dfi_p2_cas_n = 1'd1; -reg litedramcore_csr_dfi_p2_cs_n = 1'd1; -reg litedramcore_csr_dfi_p2_ras_n = 1'd1; -reg litedramcore_csr_dfi_p2_we_n = 1'd1; -wire litedramcore_csr_dfi_p2_cke; -wire litedramcore_csr_dfi_p2_odt; -wire litedramcore_csr_dfi_p2_reset_n; -reg litedramcore_csr_dfi_p2_act_n = 1'd1; -wire [63:0] litedramcore_csr_dfi_p2_wrdata; -wire litedramcore_csr_dfi_p2_wrdata_en; -wire [7:0] litedramcore_csr_dfi_p2_wrdata_mask; -wire litedramcore_csr_dfi_p2_rddata_en; -reg [63:0] litedramcore_csr_dfi_p2_rddata = 64'd0; -reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0; -wire [14:0] litedramcore_csr_dfi_p3_address; -wire [2:0] litedramcore_csr_dfi_p3_bank; -reg litedramcore_csr_dfi_p3_cas_n = 1'd1; -reg litedramcore_csr_dfi_p3_cs_n = 1'd1; -reg litedramcore_csr_dfi_p3_ras_n = 1'd1; -reg litedramcore_csr_dfi_p3_we_n = 1'd1; -wire litedramcore_csr_dfi_p3_cke; -wire litedramcore_csr_dfi_p3_odt; -wire litedramcore_csr_dfi_p3_reset_n; -reg litedramcore_csr_dfi_p3_act_n = 1'd1; -wire [63:0] litedramcore_csr_dfi_p3_wrdata; -wire litedramcore_csr_dfi_p3_wrdata_en; -wire [7:0] litedramcore_csr_dfi_p3_wrdata_mask; -wire litedramcore_csr_dfi_p3_rddata_en; -reg [63:0] litedramcore_csr_dfi_p3_rddata = 64'd0; -reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0; -reg [14:0] litedramcore_ext_dfi_p0_address = 15'd0; -reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0; -reg litedramcore_ext_dfi_p0_cas_n = 1'd1; -reg litedramcore_ext_dfi_p0_cs_n = 1'd1; -reg litedramcore_ext_dfi_p0_ras_n = 1'd1; -reg litedramcore_ext_dfi_p0_we_n = 1'd1; -reg litedramcore_ext_dfi_p0_cke = 1'd0; -reg litedramcore_ext_dfi_p0_odt = 1'd0; -reg litedramcore_ext_dfi_p0_reset_n = 1'd0; -reg litedramcore_ext_dfi_p0_act_n = 1'd1; -reg [63:0] litedramcore_ext_dfi_p0_wrdata = 64'd0; -reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0; -reg [7:0] litedramcore_ext_dfi_p0_wrdata_mask = 8'd0; -reg litedramcore_ext_dfi_p0_rddata_en = 1'd0; -reg [63:0] litedramcore_ext_dfi_p0_rddata = 64'd0; -reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0; -reg [14:0] litedramcore_ext_dfi_p1_address = 15'd0; -reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0; -reg litedramcore_ext_dfi_p1_cas_n = 1'd1; -reg litedramcore_ext_dfi_p1_cs_n = 1'd1; -reg litedramcore_ext_dfi_p1_ras_n = 1'd1; -reg litedramcore_ext_dfi_p1_we_n = 1'd1; -reg litedramcore_ext_dfi_p1_cke = 1'd0; -reg litedramcore_ext_dfi_p1_odt = 1'd0; -reg litedramcore_ext_dfi_p1_reset_n = 1'd0; -reg litedramcore_ext_dfi_p1_act_n = 1'd1; -reg [63:0] litedramcore_ext_dfi_p1_wrdata = 64'd0; -reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0; -reg [7:0] litedramcore_ext_dfi_p1_wrdata_mask = 8'd0; -reg litedramcore_ext_dfi_p1_rddata_en = 1'd0; -reg [63:0] litedramcore_ext_dfi_p1_rddata = 64'd0; -reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0; -reg [14:0] litedramcore_ext_dfi_p2_address = 15'd0; -reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0; -reg litedramcore_ext_dfi_p2_cas_n = 1'd1; -reg litedramcore_ext_dfi_p2_cs_n = 1'd1; -reg litedramcore_ext_dfi_p2_ras_n = 1'd1; -reg litedramcore_ext_dfi_p2_we_n = 1'd1; -reg litedramcore_ext_dfi_p2_cke = 1'd0; -reg litedramcore_ext_dfi_p2_odt = 1'd0; -reg litedramcore_ext_dfi_p2_reset_n = 1'd0; -reg litedramcore_ext_dfi_p2_act_n = 1'd1; -reg [63:0] litedramcore_ext_dfi_p2_wrdata = 64'd0; -reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0; -reg [7:0] litedramcore_ext_dfi_p2_wrdata_mask = 8'd0; -reg litedramcore_ext_dfi_p2_rddata_en = 1'd0; -reg [63:0] litedramcore_ext_dfi_p2_rddata = 64'd0; -reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0; -reg [14:0] litedramcore_ext_dfi_p3_address = 15'd0; -reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0; -reg litedramcore_ext_dfi_p3_cas_n = 1'd1; -reg litedramcore_ext_dfi_p3_cs_n = 1'd1; -reg litedramcore_ext_dfi_p3_ras_n = 1'd1; -reg litedramcore_ext_dfi_p3_we_n = 1'd1; -reg litedramcore_ext_dfi_p3_cke = 1'd0; -reg litedramcore_ext_dfi_p3_odt = 1'd0; -reg litedramcore_ext_dfi_p3_reset_n = 1'd0; -reg litedramcore_ext_dfi_p3_act_n = 1'd1; -reg [63:0] litedramcore_ext_dfi_p3_wrdata = 64'd0; -reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0; -reg [7:0] litedramcore_ext_dfi_p3_wrdata_mask = 8'd0; -reg litedramcore_ext_dfi_p3_rddata_en = 1'd0; -reg [63:0] litedramcore_ext_dfi_p3_rddata = 64'd0; -reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0; -reg litedramcore_ext_dfi_sel = 1'd0; -wire litedramcore_sel; -wire litedramcore_cke; -wire litedramcore_odt; -wire litedramcore_reset_n; -reg [3:0] litedramcore_storage = 4'd1; -reg litedramcore_re = 1'd0; -wire litedramcore_phaseinjector0_csrfield_cs; -wire litedramcore_phaseinjector0_csrfield_we; -wire litedramcore_phaseinjector0_csrfield_cas; -wire litedramcore_phaseinjector0_csrfield_ras; -wire litedramcore_phaseinjector0_csrfield_wren; -wire litedramcore_phaseinjector0_csrfield_rden; -reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; -reg litedramcore_phaseinjector0_command_re = 1'd0; -reg litedramcore_phaseinjector0_command_issue_re = 1'd0; -wire litedramcore_phaseinjector0_command_issue_r; -reg litedramcore_phaseinjector0_command_issue_we = 1'd0; -reg litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [14:0] litedramcore_phaseinjector0_address_storage = 15'd0; -reg litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [63:0] litedramcore_phaseinjector0_wrdata_storage = 64'd0; -reg litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [63:0] litedramcore_phaseinjector0_rddata_status = 64'd0; -wire litedramcore_phaseinjector0_rddata_we; -reg litedramcore_phaseinjector0_rddata_re = 1'd0; -wire litedramcore_phaseinjector1_csrfield_cs; -wire litedramcore_phaseinjector1_csrfield_we; -wire litedramcore_phaseinjector1_csrfield_cas; -wire litedramcore_phaseinjector1_csrfield_ras; -wire litedramcore_phaseinjector1_csrfield_wren; -wire litedramcore_phaseinjector1_csrfield_rden; -reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0; -reg litedramcore_phaseinjector1_command_re = 1'd0; -reg litedramcore_phaseinjector1_command_issue_re = 1'd0; -wire litedramcore_phaseinjector1_command_issue_r; -reg litedramcore_phaseinjector1_command_issue_we = 1'd0; -reg litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [14:0] litedramcore_phaseinjector1_address_storage = 15'd0; -reg litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [63:0] litedramcore_phaseinjector1_wrdata_storage = 64'd0; -reg litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [63:0] litedramcore_phaseinjector1_rddata_status = 64'd0; -wire litedramcore_phaseinjector1_rddata_we; -reg litedramcore_phaseinjector1_rddata_re = 1'd0; -wire litedramcore_phaseinjector2_csrfield_cs; -wire litedramcore_phaseinjector2_csrfield_we; -wire litedramcore_phaseinjector2_csrfield_cas; -wire litedramcore_phaseinjector2_csrfield_ras; -wire litedramcore_phaseinjector2_csrfield_wren; -wire litedramcore_phaseinjector2_csrfield_rden; -reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0; -reg litedramcore_phaseinjector2_command_re = 1'd0; -reg litedramcore_phaseinjector2_command_issue_re = 1'd0; -wire litedramcore_phaseinjector2_command_issue_r; -reg litedramcore_phaseinjector2_command_issue_we = 1'd0; -reg litedramcore_phaseinjector2_command_issue_w = 1'd0; -reg [14:0] litedramcore_phaseinjector2_address_storage = 15'd0; -reg litedramcore_phaseinjector2_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0; -reg litedramcore_phaseinjector2_baddress_re = 1'd0; -reg [63:0] litedramcore_phaseinjector2_wrdata_storage = 64'd0; -reg litedramcore_phaseinjector2_wrdata_re = 1'd0; -reg [63:0] litedramcore_phaseinjector2_rddata_status = 64'd0; -wire litedramcore_phaseinjector2_rddata_we; -reg litedramcore_phaseinjector2_rddata_re = 1'd0; -wire litedramcore_phaseinjector3_csrfield_cs; -wire litedramcore_phaseinjector3_csrfield_we; -wire litedramcore_phaseinjector3_csrfield_cas; -wire litedramcore_phaseinjector3_csrfield_ras; -wire litedramcore_phaseinjector3_csrfield_wren; -wire litedramcore_phaseinjector3_csrfield_rden; -reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0; -reg litedramcore_phaseinjector3_command_re = 1'd0; -reg litedramcore_phaseinjector3_command_issue_re = 1'd0; -wire litedramcore_phaseinjector3_command_issue_r; -reg litedramcore_phaseinjector3_command_issue_we = 1'd0; -reg litedramcore_phaseinjector3_command_issue_w = 1'd0; -reg [14:0] litedramcore_phaseinjector3_address_storage = 15'd0; -reg litedramcore_phaseinjector3_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0; -reg litedramcore_phaseinjector3_baddress_re = 1'd0; -reg [63:0] litedramcore_phaseinjector3_wrdata_storage = 64'd0; -reg litedramcore_phaseinjector3_wrdata_re = 1'd0; -reg [63:0] litedramcore_phaseinjector3_rddata_status = 64'd0; -wire litedramcore_phaseinjector3_rddata_we; -reg litedramcore_phaseinjector3_rddata_re = 1'd0; -wire litedramcore_interface_bank0_valid; -wire litedramcore_interface_bank0_ready; -wire litedramcore_interface_bank0_we; -wire [21:0] litedramcore_interface_bank0_addr; -wire litedramcore_interface_bank0_lock; -wire litedramcore_interface_bank0_wdata_ready; -wire litedramcore_interface_bank0_rdata_valid; -wire litedramcore_interface_bank1_valid; -wire litedramcore_interface_bank1_ready; -wire litedramcore_interface_bank1_we; -wire [21:0] litedramcore_interface_bank1_addr; -wire litedramcore_interface_bank1_lock; -wire litedramcore_interface_bank1_wdata_ready; -wire litedramcore_interface_bank1_rdata_valid; -wire litedramcore_interface_bank2_valid; -wire litedramcore_interface_bank2_ready; -wire litedramcore_interface_bank2_we; -wire [21:0] litedramcore_interface_bank2_addr; -wire litedramcore_interface_bank2_lock; -wire litedramcore_interface_bank2_wdata_ready; -wire litedramcore_interface_bank2_rdata_valid; -wire litedramcore_interface_bank3_valid; -wire litedramcore_interface_bank3_ready; -wire litedramcore_interface_bank3_we; -wire [21:0] litedramcore_interface_bank3_addr; -wire litedramcore_interface_bank3_lock; -wire litedramcore_interface_bank3_wdata_ready; -wire litedramcore_interface_bank3_rdata_valid; -wire litedramcore_interface_bank4_valid; -wire litedramcore_interface_bank4_ready; -wire litedramcore_interface_bank4_we; -wire [21:0] litedramcore_interface_bank4_addr; -wire litedramcore_interface_bank4_lock; -wire litedramcore_interface_bank4_wdata_ready; -wire litedramcore_interface_bank4_rdata_valid; -wire litedramcore_interface_bank5_valid; -wire litedramcore_interface_bank5_ready; -wire litedramcore_interface_bank5_we; -wire [21:0] litedramcore_interface_bank5_addr; -wire litedramcore_interface_bank5_lock; -wire litedramcore_interface_bank5_wdata_ready; -wire litedramcore_interface_bank5_rdata_valid; -wire litedramcore_interface_bank6_valid; -wire litedramcore_interface_bank6_ready; -wire litedramcore_interface_bank6_we; -wire [21:0] litedramcore_interface_bank6_addr; -wire litedramcore_interface_bank6_lock; -wire litedramcore_interface_bank6_wdata_ready; -wire litedramcore_interface_bank6_rdata_valid; -wire litedramcore_interface_bank7_valid; -wire litedramcore_interface_bank7_ready; -wire litedramcore_interface_bank7_we; -wire [21:0] litedramcore_interface_bank7_addr; -wire litedramcore_interface_bank7_lock; -wire litedramcore_interface_bank7_wdata_ready; -wire litedramcore_interface_bank7_rdata_valid; -reg [255:0] litedramcore_interface_wdata = 256'd0; -reg [31:0] litedramcore_interface_wdata_we = 32'd0; -wire [255:0] litedramcore_interface_rdata; -reg [14:0] litedramcore_dfi_p0_address = 15'd0; -reg [2:0] litedramcore_dfi_p0_bank = 3'd0; -reg litedramcore_dfi_p0_cas_n = 1'd1; -reg litedramcore_dfi_p0_cs_n = 1'd1; -reg litedramcore_dfi_p0_ras_n = 1'd1; -reg litedramcore_dfi_p0_we_n = 1'd1; -wire litedramcore_dfi_p0_cke; -wire litedramcore_dfi_p0_odt; -wire litedramcore_dfi_p0_reset_n; -reg litedramcore_dfi_p0_act_n = 1'd1; -wire [63:0] litedramcore_dfi_p0_wrdata; -reg litedramcore_dfi_p0_wrdata_en = 1'd0; -wire [7:0] litedramcore_dfi_p0_wrdata_mask; -reg litedramcore_dfi_p0_rddata_en = 1'd0; -wire [63:0] litedramcore_dfi_p0_rddata; -wire litedramcore_dfi_p0_rddata_valid; -reg [14:0] litedramcore_dfi_p1_address = 15'd0; -reg [2:0] litedramcore_dfi_p1_bank = 3'd0; -reg litedramcore_dfi_p1_cas_n = 1'd1; -reg litedramcore_dfi_p1_cs_n = 1'd1; -reg litedramcore_dfi_p1_ras_n = 1'd1; -reg litedramcore_dfi_p1_we_n = 1'd1; -wire litedramcore_dfi_p1_cke; -wire litedramcore_dfi_p1_odt; -wire litedramcore_dfi_p1_reset_n; -reg litedramcore_dfi_p1_act_n = 1'd1; -wire [63:0] litedramcore_dfi_p1_wrdata; -reg litedramcore_dfi_p1_wrdata_en = 1'd0; -wire [7:0] litedramcore_dfi_p1_wrdata_mask; -reg litedramcore_dfi_p1_rddata_en = 1'd0; -wire [63:0] litedramcore_dfi_p1_rddata; -wire litedramcore_dfi_p1_rddata_valid; -reg [14:0] litedramcore_dfi_p2_address = 15'd0; -reg [2:0] litedramcore_dfi_p2_bank = 3'd0; -reg litedramcore_dfi_p2_cas_n = 1'd1; -reg litedramcore_dfi_p2_cs_n = 1'd1; -reg litedramcore_dfi_p2_ras_n = 1'd1; -reg litedramcore_dfi_p2_we_n = 1'd1; -wire litedramcore_dfi_p2_cke; -wire litedramcore_dfi_p2_odt; -wire litedramcore_dfi_p2_reset_n; -reg litedramcore_dfi_p2_act_n = 1'd1; -wire [63:0] litedramcore_dfi_p2_wrdata; -reg litedramcore_dfi_p2_wrdata_en = 1'd0; -wire [7:0] litedramcore_dfi_p2_wrdata_mask; -reg litedramcore_dfi_p2_rddata_en = 1'd0; -wire [63:0] litedramcore_dfi_p2_rddata; -wire litedramcore_dfi_p2_rddata_valid; -reg [14:0] litedramcore_dfi_p3_address = 15'd0; -reg [2:0] litedramcore_dfi_p3_bank = 3'd0; -reg litedramcore_dfi_p3_cas_n = 1'd1; -reg litedramcore_dfi_p3_cs_n = 1'd1; -reg litedramcore_dfi_p3_ras_n = 1'd1; -reg litedramcore_dfi_p3_we_n = 1'd1; -wire litedramcore_dfi_p3_cke; -wire litedramcore_dfi_p3_odt; -wire litedramcore_dfi_p3_reset_n; -reg litedramcore_dfi_p3_act_n = 1'd1; -wire [63:0] litedramcore_dfi_p3_wrdata; -reg litedramcore_dfi_p3_wrdata_en = 1'd0; -wire [7:0] litedramcore_dfi_p3_wrdata_mask; -reg litedramcore_dfi_p3_rddata_en = 1'd0; -wire [63:0] litedramcore_dfi_p3_rddata; -wire litedramcore_dfi_p3_rddata_valid; -reg litedramcore_cmd_valid = 1'd0; -reg litedramcore_cmd_ready = 1'd0; -reg litedramcore_cmd_last = 1'd0; -reg [14:0] litedramcore_cmd_payload_a = 15'd0; -reg [2:0] litedramcore_cmd_payload_ba = 3'd0; -reg litedramcore_cmd_payload_cas = 1'd0; -reg litedramcore_cmd_payload_ras = 1'd0; -reg litedramcore_cmd_payload_we = 1'd0; -reg litedramcore_cmd_payload_is_read = 1'd0; -reg litedramcore_cmd_payload_is_write = 1'd0; -wire litedramcore_wants_refresh; -wire litedramcore_wants_zqcs; -wire litedramcore_timer_wait; -wire litedramcore_timer_done0; -wire [9:0] litedramcore_timer_count0; -wire litedramcore_timer_done1; -reg [9:0] litedramcore_timer_count1 = 10'd781; -wire litedramcore_postponer_req_i; -reg litedramcore_postponer_req_o = 1'd0; -reg litedramcore_postponer_count = 1'd0; -reg litedramcore_sequencer_start0 = 1'd0; -wire litedramcore_sequencer_done0; -wire litedramcore_sequencer_start1; -reg litedramcore_sequencer_done1 = 1'd0; -reg [5:0] litedramcore_sequencer_counter = 6'd0; -reg litedramcore_sequencer_count = 1'd0; -wire litedramcore_zqcs_timer_wait; -wire litedramcore_zqcs_timer_done0; -wire [26:0] litedramcore_zqcs_timer_count0; -wire litedramcore_zqcs_timer_done1; -reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999; -reg litedramcore_zqcs_executer_start = 1'd0; -reg litedramcore_zqcs_executer_done = 1'd0; -reg [4:0] litedramcore_zqcs_executer_counter = 5'd0; -wire litedramcore_bankmachine0_req_valid; -wire litedramcore_bankmachine0_req_ready; -wire litedramcore_bankmachine0_req_we; -wire [21:0] litedramcore_bankmachine0_req_addr; -wire litedramcore_bankmachine0_req_lock; -reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine0_refresh_req; -reg litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg litedramcore_bankmachine0_cmd_valid = 1'd0; -reg litedramcore_bankmachine0_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; -reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine0_auto_precharge = 1'd0; -wire litedramcore_bankmachine0_sink_valid; -wire litedramcore_bankmachine0_sink_ready; -reg litedramcore_bankmachine0_sink_first = 1'd0; -reg litedramcore_bankmachine0_sink_last = 1'd0; -wire litedramcore_bankmachine0_sink_payload_we; -wire [21:0] litedramcore_bankmachine0_sink_payload_addr; -wire litedramcore_bankmachine0_source_valid; -wire litedramcore_bankmachine0_source_ready; -wire litedramcore_bankmachine0_source_first; -wire litedramcore_bankmachine0_source_last; -wire litedramcore_bankmachine0_source_payload_we; -wire [21:0] litedramcore_bankmachine0_source_payload_addr; -wire litedramcore_bankmachine0_syncfifo0_we; -wire litedramcore_bankmachine0_syncfifo0_writable; -wire litedramcore_bankmachine0_syncfifo0_re; -wire litedramcore_bankmachine0_syncfifo0_readable; -wire [24:0] litedramcore_bankmachine0_syncfifo0_din; -wire [24:0] litedramcore_bankmachine0_syncfifo0_dout; -reg [4:0] litedramcore_bankmachine0_level = 5'd0; -reg litedramcore_bankmachine0_replace = 1'd0; -reg [3:0] litedramcore_bankmachine0_produce = 4'd0; -reg [3:0] litedramcore_bankmachine0_consume = 4'd0; -reg [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine0_wrport_dat_r; -wire litedramcore_bankmachine0_wrport_we; -wire [24:0] litedramcore_bankmachine0_wrport_dat_w; -wire litedramcore_bankmachine0_do_read; -wire [3:0] litedramcore_bankmachine0_rdport_adr; -wire [24:0] litedramcore_bankmachine0_rdport_dat_r; -wire litedramcore_bankmachine0_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine0_fifo_in_payload_addr; -wire litedramcore_bankmachine0_fifo_in_first; -wire litedramcore_bankmachine0_fifo_in_last; -wire litedramcore_bankmachine0_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine0_fifo_out_payload_addr; -wire litedramcore_bankmachine0_fifo_out_first; -wire litedramcore_bankmachine0_fifo_out_last; -wire litedramcore_bankmachine0_sink_sink_valid; -wire litedramcore_bankmachine0_sink_sink_ready; -wire litedramcore_bankmachine0_sink_sink_first; -wire litedramcore_bankmachine0_sink_sink_last; -wire litedramcore_bankmachine0_sink_sink_payload_we; -wire [21:0] litedramcore_bankmachine0_sink_sink_payload_addr; -wire litedramcore_bankmachine0_source_source_valid; -wire litedramcore_bankmachine0_source_source_ready; -wire litedramcore_bankmachine0_source_source_first; -wire litedramcore_bankmachine0_source_source_last; -wire litedramcore_bankmachine0_source_source_payload_we; -wire [21:0] litedramcore_bankmachine0_source_source_payload_addr; -wire litedramcore_bankmachine0_pipe_valid_sink_valid; -wire litedramcore_bankmachine0_pipe_valid_sink_ready; -wire litedramcore_bankmachine0_pipe_valid_sink_first; -wire litedramcore_bankmachine0_pipe_valid_sink_last; -wire litedramcore_bankmachine0_pipe_valid_sink_payload_we; -wire [21:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine0_pipe_valid_source_ready; -reg litedramcore_bankmachine0_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine0_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine0_row = 15'd0; -reg litedramcore_bankmachine0_row_opened = 1'd0; -wire litedramcore_bankmachine0_row_hit; -reg litedramcore_bankmachine0_row_open = 1'd0; -reg litedramcore_bankmachine0_row_close = 1'd0; -reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine0_twtpcon_valid; +wire main_clkin; +wire main_clkout0; +wire main_clkout1; +wire main_clkout2; +wire main_clkout3; +wire main_clkout_buf0; +wire main_clkout_buf1; +wire main_clkout_buf2; +wire main_clkout_buf3; +reg main_ic_reset = 1'd1; +reg main_init_done_re = 1'd0; +reg main_init_done_storage = 1'd0; +reg main_init_error_re = 1'd0; +reg main_init_error_storage = 1'd0; +wire main_k7ddrphy0; +wire main_k7ddrphy1; +wire main_k7ddrphy2; +wire main_k7ddrphy3; +reg [7:0] main_k7ddrphy_bitslip00 = 8'd0; +reg [7:0] main_k7ddrphy_bitslip01 = 8'd0; +reg [7:0] main_k7ddrphy_bitslip02 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip03; +reg [7:0] main_k7ddrphy_bitslip04 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip0_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip0_r1 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip0_r2 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip0_r3 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip0_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip0_value1 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip0_value2 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip0_value3 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip10 = 8'd0; +reg [7:0] main_k7ddrphy_bitslip100 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip101; +reg [7:0] main_k7ddrphy_bitslip102 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip10_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip10_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip10_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip10_value1 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip11 = 8'd0; +reg [7:0] main_k7ddrphy_bitslip110 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip111; +reg [7:0] main_k7ddrphy_bitslip112 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip11_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip11_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip11_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip11_value1 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip12 = 8'd0; +reg [7:0] main_k7ddrphy_bitslip120 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip121; +reg [7:0] main_k7ddrphy_bitslip122 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip12_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip12_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip12_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip12_value1 = 3'd7; +wire [7:0] main_k7ddrphy_bitslip13; +reg [7:0] main_k7ddrphy_bitslip130 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip131; +reg [7:0] main_k7ddrphy_bitslip132 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip13_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip13_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip13_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip13_value1 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip14 = 8'd0; +reg [7:0] main_k7ddrphy_bitslip140 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip141; +reg [7:0] main_k7ddrphy_bitslip142 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip14_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip14_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip14_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip14_value1 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip150 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip151; +reg [7:0] main_k7ddrphy_bitslip152 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip15_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip15_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip15_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip15_value1 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip160 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip161; +reg [7:0] main_k7ddrphy_bitslip162 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip16_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip16_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip16_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip16_value1 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip170 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip171; +reg [7:0] main_k7ddrphy_bitslip172 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip17_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip17_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip17_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip17_value1 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip180 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip181; +reg [7:0] main_k7ddrphy_bitslip182 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip18_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip18_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip18_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip18_value1 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip190 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip191; +reg [7:0] main_k7ddrphy_bitslip192 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip19_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip19_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip19_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip19_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip1_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip1_r1 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip1_r2 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip1_r3 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip1_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip1_value1 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip1_value2 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip1_value3 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip20 = 8'd0; +reg [7:0] main_k7ddrphy_bitslip200 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip201; +reg [7:0] main_k7ddrphy_bitslip202 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip20_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip20_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip20_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip20_value1 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip21 = 8'd0; +reg [7:0] main_k7ddrphy_bitslip210 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip211; +reg [7:0] main_k7ddrphy_bitslip212 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip21_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip21_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip21_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip21_value1 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip22 = 8'd0; +reg [7:0] main_k7ddrphy_bitslip220 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip221; +reg [7:0] main_k7ddrphy_bitslip222 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip22_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip22_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip22_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip22_value1 = 3'd7; +wire [7:0] main_k7ddrphy_bitslip23; +reg [7:0] main_k7ddrphy_bitslip230 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip231; +reg [7:0] main_k7ddrphy_bitslip232 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip23_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip23_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip23_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip23_value1 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip24 = 8'd0; +reg [7:0] main_k7ddrphy_bitslip240 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip241; +reg [7:0] main_k7ddrphy_bitslip242 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip24_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip24_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip24_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip24_value1 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip250 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip251; +reg [7:0] main_k7ddrphy_bitslip252 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip25_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip25_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip25_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip25_value1 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip260 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip261; +reg [7:0] main_k7ddrphy_bitslip262 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip26_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip26_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip26_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip26_value1 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip270 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip271; +reg [7:0] main_k7ddrphy_bitslip272 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip27_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip27_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip27_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip27_value1 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip280 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip281; +reg [7:0] main_k7ddrphy_bitslip282 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip28_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip28_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip28_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip28_value1 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip290 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip291; +reg [7:0] main_k7ddrphy_bitslip292 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip29_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip29_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip29_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip29_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip2_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip2_r1 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip2_r2 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip2_r3 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip2_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip2_value1 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip2_value2 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip2_value3 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip30 = 8'd0; +reg [7:0] main_k7ddrphy_bitslip300 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip301; +reg [7:0] main_k7ddrphy_bitslip302 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip30_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip30_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip30_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip30_value1 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip31 = 8'd0; +reg [7:0] main_k7ddrphy_bitslip310 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip311; +reg [7:0] main_k7ddrphy_bitslip312 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip31_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip31_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip31_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip31_value1 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip32 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip33; +reg [7:0] main_k7ddrphy_bitslip34 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip3_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip3_r1 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip3_r2 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip3_r3 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip3_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip3_value1 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip3_value2 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip3_value3 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip40 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip41; +reg [7:0] main_k7ddrphy_bitslip42 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip4_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip4_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip4_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip4_value1 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip50 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip51; +reg [7:0] main_k7ddrphy_bitslip52 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip5_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip5_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip5_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip5_value1 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip60 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip61; +reg [7:0] main_k7ddrphy_bitslip62 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip6_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip6_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip6_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip6_value1 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip70 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip71; +reg [7:0] main_k7ddrphy_bitslip72 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip7_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip7_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip7_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip7_value1 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip80 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip81; +reg [7:0] main_k7ddrphy_bitslip82 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip8_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip8_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip8_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip8_value1 = 3'd7; +reg [7:0] main_k7ddrphy_bitslip90 = 8'd0; +wire [7:0] main_k7ddrphy_bitslip91; +reg [7:0] main_k7ddrphy_bitslip92 = 8'd0; +reg [15:0] main_k7ddrphy_bitslip9_r0 = 16'd0; +reg [15:0] main_k7ddrphy_bitslip9_r1 = 16'd0; +reg [2:0] main_k7ddrphy_bitslip9_value0 = 3'd7; +reg [2:0] main_k7ddrphy_bitslip9_value1 = 3'd7; +wire main_k7ddrphy_cdly_inc_r; +reg main_k7ddrphy_cdly_inc_re = 1'd0; +reg main_k7ddrphy_cdly_inc_w = 1'd0; +reg main_k7ddrphy_cdly_inc_we = 1'd0; +wire main_k7ddrphy_cdly_rst_r; +reg main_k7ddrphy_cdly_rst_re = 1'd0; +reg main_k7ddrphy_cdly_rst_w = 1'd0; +reg main_k7ddrphy_cdly_rst_we = 1'd0; +wire main_k7ddrphy_dfi_p0_act_n; +wire [14:0] main_k7ddrphy_dfi_p0_address; +wire [2:0] main_k7ddrphy_dfi_p0_bank; +wire main_k7ddrphy_dfi_p0_cas_n; +wire main_k7ddrphy_dfi_p0_cke; +wire main_k7ddrphy_dfi_p0_cs_n; +wire main_k7ddrphy_dfi_p0_odt; +wire main_k7ddrphy_dfi_p0_ras_n; +reg [63:0] main_k7ddrphy_dfi_p0_rddata = 64'd0; +wire main_k7ddrphy_dfi_p0_rddata_en; +wire main_k7ddrphy_dfi_p0_rddata_valid; +wire main_k7ddrphy_dfi_p0_reset_n; +wire main_k7ddrphy_dfi_p0_we_n; +wire [63:0] main_k7ddrphy_dfi_p0_wrdata; +wire main_k7ddrphy_dfi_p0_wrdata_en; +wire [7:0] main_k7ddrphy_dfi_p0_wrdata_mask; +wire main_k7ddrphy_dfi_p1_act_n; +wire [14:0] main_k7ddrphy_dfi_p1_address; +wire [2:0] main_k7ddrphy_dfi_p1_bank; +wire main_k7ddrphy_dfi_p1_cas_n; +wire main_k7ddrphy_dfi_p1_cke; +wire main_k7ddrphy_dfi_p1_cs_n; +wire main_k7ddrphy_dfi_p1_odt; +wire main_k7ddrphy_dfi_p1_ras_n; +reg [63:0] main_k7ddrphy_dfi_p1_rddata = 64'd0; +wire main_k7ddrphy_dfi_p1_rddata_en; +wire main_k7ddrphy_dfi_p1_rddata_valid; +wire main_k7ddrphy_dfi_p1_reset_n; +wire main_k7ddrphy_dfi_p1_we_n; +wire [63:0] main_k7ddrphy_dfi_p1_wrdata; +wire main_k7ddrphy_dfi_p1_wrdata_en; +wire [7:0] main_k7ddrphy_dfi_p1_wrdata_mask; +wire main_k7ddrphy_dfi_p2_act_n; +wire [14:0] main_k7ddrphy_dfi_p2_address; +wire [2:0] main_k7ddrphy_dfi_p2_bank; +wire main_k7ddrphy_dfi_p2_cas_n; +wire main_k7ddrphy_dfi_p2_cke; +wire main_k7ddrphy_dfi_p2_cs_n; +wire main_k7ddrphy_dfi_p2_odt; +wire main_k7ddrphy_dfi_p2_ras_n; +reg [63:0] main_k7ddrphy_dfi_p2_rddata = 64'd0; +wire main_k7ddrphy_dfi_p2_rddata_en; +wire main_k7ddrphy_dfi_p2_rddata_valid; +wire main_k7ddrphy_dfi_p2_reset_n; +wire main_k7ddrphy_dfi_p2_we_n; +wire [63:0] main_k7ddrphy_dfi_p2_wrdata; +wire main_k7ddrphy_dfi_p2_wrdata_en; +wire [7:0] main_k7ddrphy_dfi_p2_wrdata_mask; +wire main_k7ddrphy_dfi_p3_act_n; +wire [14:0] main_k7ddrphy_dfi_p3_address; +wire [2:0] main_k7ddrphy_dfi_p3_bank; +wire main_k7ddrphy_dfi_p3_cas_n; +wire main_k7ddrphy_dfi_p3_cke; +wire main_k7ddrphy_dfi_p3_cs_n; +wire main_k7ddrphy_dfi_p3_odt; +wire main_k7ddrphy_dfi_p3_ras_n; +reg [63:0] main_k7ddrphy_dfi_p3_rddata = 64'd0; +wire main_k7ddrphy_dfi_p3_rddata_en; +wire main_k7ddrphy_dfi_p3_rddata_valid; +wire main_k7ddrphy_dfi_p3_reset_n; +wire main_k7ddrphy_dfi_p3_we_n; +wire [63:0] main_k7ddrphy_dfi_p3_wrdata; +wire main_k7ddrphy_dfi_p3_wrdata_en; +wire [7:0] main_k7ddrphy_dfi_p3_wrdata_mask; +reg main_k7ddrphy_dly_sel_re = 1'd0; +reg [3:0] main_k7ddrphy_dly_sel_storage = 4'd0; +wire main_k7ddrphy_dm_o_nodelay0; +wire main_k7ddrphy_dm_o_nodelay1; +wire main_k7ddrphy_dm_o_nodelay2; +wire main_k7ddrphy_dm_o_nodelay3; +wire main_k7ddrphy_dq_i_delayed0; +wire main_k7ddrphy_dq_i_delayed1; +wire main_k7ddrphy_dq_i_delayed10; +wire main_k7ddrphy_dq_i_delayed11; +wire main_k7ddrphy_dq_i_delayed12; +wire main_k7ddrphy_dq_i_delayed13; +wire main_k7ddrphy_dq_i_delayed14; +wire main_k7ddrphy_dq_i_delayed15; +wire main_k7ddrphy_dq_i_delayed16; +wire main_k7ddrphy_dq_i_delayed17; +wire main_k7ddrphy_dq_i_delayed18; +wire main_k7ddrphy_dq_i_delayed19; +wire main_k7ddrphy_dq_i_delayed2; +wire main_k7ddrphy_dq_i_delayed20; +wire main_k7ddrphy_dq_i_delayed21; +wire main_k7ddrphy_dq_i_delayed22; +wire main_k7ddrphy_dq_i_delayed23; +wire main_k7ddrphy_dq_i_delayed24; +wire main_k7ddrphy_dq_i_delayed25; +wire main_k7ddrphy_dq_i_delayed26; +wire main_k7ddrphy_dq_i_delayed27; +wire main_k7ddrphy_dq_i_delayed28; +wire main_k7ddrphy_dq_i_delayed29; +wire main_k7ddrphy_dq_i_delayed3; +wire main_k7ddrphy_dq_i_delayed30; +wire main_k7ddrphy_dq_i_delayed31; +wire main_k7ddrphy_dq_i_delayed4; +wire main_k7ddrphy_dq_i_delayed5; +wire main_k7ddrphy_dq_i_delayed6; +wire main_k7ddrphy_dq_i_delayed7; +wire main_k7ddrphy_dq_i_delayed8; +wire main_k7ddrphy_dq_i_delayed9; +wire main_k7ddrphy_dq_i_nodelay0; +wire main_k7ddrphy_dq_i_nodelay1; +wire main_k7ddrphy_dq_i_nodelay10; +wire main_k7ddrphy_dq_i_nodelay11; +wire main_k7ddrphy_dq_i_nodelay12; +wire main_k7ddrphy_dq_i_nodelay13; +wire main_k7ddrphy_dq_i_nodelay14; +wire main_k7ddrphy_dq_i_nodelay15; +wire main_k7ddrphy_dq_i_nodelay16; +wire main_k7ddrphy_dq_i_nodelay17; +wire main_k7ddrphy_dq_i_nodelay18; +wire main_k7ddrphy_dq_i_nodelay19; +wire main_k7ddrphy_dq_i_nodelay2; +wire main_k7ddrphy_dq_i_nodelay20; +wire main_k7ddrphy_dq_i_nodelay21; +wire main_k7ddrphy_dq_i_nodelay22; +wire main_k7ddrphy_dq_i_nodelay23; +wire main_k7ddrphy_dq_i_nodelay24; +wire main_k7ddrphy_dq_i_nodelay25; +wire main_k7ddrphy_dq_i_nodelay26; +wire main_k7ddrphy_dq_i_nodelay27; +wire main_k7ddrphy_dq_i_nodelay28; +wire main_k7ddrphy_dq_i_nodelay29; +wire main_k7ddrphy_dq_i_nodelay3; +wire main_k7ddrphy_dq_i_nodelay30; +wire main_k7ddrphy_dq_i_nodelay31; +wire main_k7ddrphy_dq_i_nodelay4; +wire main_k7ddrphy_dq_i_nodelay5; +wire main_k7ddrphy_dq_i_nodelay6; +wire main_k7ddrphy_dq_i_nodelay7; +wire main_k7ddrphy_dq_i_nodelay8; +wire main_k7ddrphy_dq_i_nodelay9; +wire main_k7ddrphy_dq_o_delayed0; +wire main_k7ddrphy_dq_o_delayed1; +wire main_k7ddrphy_dq_o_delayed10; +wire main_k7ddrphy_dq_o_delayed11; +wire main_k7ddrphy_dq_o_delayed12; +wire main_k7ddrphy_dq_o_delayed13; +wire main_k7ddrphy_dq_o_delayed14; +wire main_k7ddrphy_dq_o_delayed15; +wire main_k7ddrphy_dq_o_delayed16; +wire main_k7ddrphy_dq_o_delayed17; +wire main_k7ddrphy_dq_o_delayed18; +wire main_k7ddrphy_dq_o_delayed19; +wire main_k7ddrphy_dq_o_delayed2; +wire main_k7ddrphy_dq_o_delayed20; +wire main_k7ddrphy_dq_o_delayed21; +wire main_k7ddrphy_dq_o_delayed22; +wire main_k7ddrphy_dq_o_delayed23; +wire main_k7ddrphy_dq_o_delayed24; +wire main_k7ddrphy_dq_o_delayed25; +wire main_k7ddrphy_dq_o_delayed26; +wire main_k7ddrphy_dq_o_delayed27; +wire main_k7ddrphy_dq_o_delayed28; +wire main_k7ddrphy_dq_o_delayed29; +wire main_k7ddrphy_dq_o_delayed3; +wire main_k7ddrphy_dq_o_delayed30; +wire main_k7ddrphy_dq_o_delayed31; +wire main_k7ddrphy_dq_o_delayed4; +wire main_k7ddrphy_dq_o_delayed5; +wire main_k7ddrphy_dq_o_delayed6; +wire main_k7ddrphy_dq_o_delayed7; +wire main_k7ddrphy_dq_o_delayed8; +wire main_k7ddrphy_dq_o_delayed9; +wire main_k7ddrphy_dq_o_nodelay0; +wire main_k7ddrphy_dq_o_nodelay1; +wire main_k7ddrphy_dq_o_nodelay10; +wire main_k7ddrphy_dq_o_nodelay11; +wire main_k7ddrphy_dq_o_nodelay12; +wire main_k7ddrphy_dq_o_nodelay13; +wire main_k7ddrphy_dq_o_nodelay14; +wire main_k7ddrphy_dq_o_nodelay15; +wire main_k7ddrphy_dq_o_nodelay16; +wire main_k7ddrphy_dq_o_nodelay17; +wire main_k7ddrphy_dq_o_nodelay18; +wire main_k7ddrphy_dq_o_nodelay19; +wire main_k7ddrphy_dq_o_nodelay2; +wire main_k7ddrphy_dq_o_nodelay20; +wire main_k7ddrphy_dq_o_nodelay21; +wire main_k7ddrphy_dq_o_nodelay22; +wire main_k7ddrphy_dq_o_nodelay23; +wire main_k7ddrphy_dq_o_nodelay24; +wire main_k7ddrphy_dq_o_nodelay25; +wire main_k7ddrphy_dq_o_nodelay26; +wire main_k7ddrphy_dq_o_nodelay27; +wire main_k7ddrphy_dq_o_nodelay28; +wire main_k7ddrphy_dq_o_nodelay29; +wire main_k7ddrphy_dq_o_nodelay3; +wire main_k7ddrphy_dq_o_nodelay30; +wire main_k7ddrphy_dq_o_nodelay31; +wire main_k7ddrphy_dq_o_nodelay4; +wire main_k7ddrphy_dq_o_nodelay5; +wire main_k7ddrphy_dq_o_nodelay6; +wire main_k7ddrphy_dq_o_nodelay7; +wire main_k7ddrphy_dq_o_nodelay8; +wire main_k7ddrphy_dq_o_nodelay9; +wire main_k7ddrphy_dq_oe; +wire main_k7ddrphy_dq_oe_delay_tappeddelayline; +reg main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +wire main_k7ddrphy_dq_t0; +wire main_k7ddrphy_dq_t1; +wire main_k7ddrphy_dq_t10; +wire main_k7ddrphy_dq_t11; +wire main_k7ddrphy_dq_t12; +wire main_k7ddrphy_dq_t13; +wire main_k7ddrphy_dq_t14; +wire main_k7ddrphy_dq_t15; +wire main_k7ddrphy_dq_t16; +wire main_k7ddrphy_dq_t17; +wire main_k7ddrphy_dq_t18; +wire main_k7ddrphy_dq_t19; +wire main_k7ddrphy_dq_t2; +wire main_k7ddrphy_dq_t20; +wire main_k7ddrphy_dq_t21; +wire main_k7ddrphy_dq_t22; +wire main_k7ddrphy_dq_t23; +wire main_k7ddrphy_dq_t24; +wire main_k7ddrphy_dq_t25; +wire main_k7ddrphy_dq_t26; +wire main_k7ddrphy_dq_t27; +wire main_k7ddrphy_dq_t28; +wire main_k7ddrphy_dq_t29; +wire main_k7ddrphy_dq_t3; +wire main_k7ddrphy_dq_t30; +wire main_k7ddrphy_dq_t31; +wire main_k7ddrphy_dq_t4; +wire main_k7ddrphy_dq_t5; +wire main_k7ddrphy_dq_t6; +wire main_k7ddrphy_dq_t7; +wire main_k7ddrphy_dq_t8; +wire main_k7ddrphy_dq_t9; +wire main_k7ddrphy_dqs_o_delayed0; +wire main_k7ddrphy_dqs_o_delayed1; +wire main_k7ddrphy_dqs_o_delayed2; +wire main_k7ddrphy_dqs_o_delayed3; +wire main_k7ddrphy_dqs_o_no_delay0; +wire main_k7ddrphy_dqs_o_no_delay1; +wire main_k7ddrphy_dqs_o_no_delay2; +wire main_k7ddrphy_dqs_o_no_delay3; +reg main_k7ddrphy_dqs_oe = 1'd0; +wire main_k7ddrphy_dqs_oe_delay_tappeddelayline; +reg main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +wire main_k7ddrphy_dqs_postamble; +wire main_k7ddrphy_dqs_preamble; +wire main_k7ddrphy_dqs_t0; +wire main_k7ddrphy_dqs_t1; +wire main_k7ddrphy_dqs_t2; +wire main_k7ddrphy_dqs_t3; +reg main_k7ddrphy_dqspattern0 = 1'd0; +reg main_k7ddrphy_dqspattern1 = 1'd0; +reg [7:0] main_k7ddrphy_dqspattern_o = 8'd0; +reg main_k7ddrphy_half_sys8x_taps_re = 1'd0; +reg [4:0] main_k7ddrphy_half_sys8x_taps_storage = 5'd8; +wire main_k7ddrphy_oq0; +wire main_k7ddrphy_oq1; +wire main_k7ddrphy_oq10; +wire main_k7ddrphy_oq11; +wire main_k7ddrphy_oq12; +wire main_k7ddrphy_oq13; +wire main_k7ddrphy_oq14; +wire main_k7ddrphy_oq15; +wire main_k7ddrphy_oq16; +wire main_k7ddrphy_oq17; +wire main_k7ddrphy_oq18; +wire main_k7ddrphy_oq19; +wire main_k7ddrphy_oq2; +wire main_k7ddrphy_oq20; +wire main_k7ddrphy_oq21; +wire main_k7ddrphy_oq22; +wire main_k7ddrphy_oq23; +wire main_k7ddrphy_oq24; +wire main_k7ddrphy_oq3; +wire main_k7ddrphy_oq4; +wire main_k7ddrphy_oq5; +wire main_k7ddrphy_oq6; +wire main_k7ddrphy_oq7; +wire main_k7ddrphy_oq8; +wire main_k7ddrphy_oq9; +wire [2:0] main_k7ddrphy_pads_ba; +reg main_k7ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg main_k7ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg main_k7ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg main_k7ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg main_k7ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg main_k7ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg main_k7ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg main_k7ddrphy_rddata_en_tappeddelayline7 = 1'd0; +wire main_k7ddrphy_rdly_dq_bitslip_r; +reg main_k7ddrphy_rdly_dq_bitslip_re = 1'd0; +wire main_k7ddrphy_rdly_dq_bitslip_rst_r; +reg main_k7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; +reg main_k7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +reg main_k7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; +reg main_k7ddrphy_rdly_dq_bitslip_w = 1'd0; +reg main_k7ddrphy_rdly_dq_bitslip_we = 1'd0; +wire main_k7ddrphy_rdly_dq_inc_r; +reg main_k7ddrphy_rdly_dq_inc_re = 1'd0; +reg main_k7ddrphy_rdly_dq_inc_w = 1'd0; +reg main_k7ddrphy_rdly_dq_inc_we = 1'd0; +wire main_k7ddrphy_rdly_dq_rst_r; +reg main_k7ddrphy_rdly_dq_rst_re = 1'd0; +reg main_k7ddrphy_rdly_dq_rst_w = 1'd0; +reg main_k7ddrphy_rdly_dq_rst_we = 1'd0; +reg main_k7ddrphy_rdphase_re = 1'd0; +reg [1:0] main_k7ddrphy_rdphase_storage = 2'd1; +reg main_k7ddrphy_rst_re = 1'd0; +reg main_k7ddrphy_rst_storage = 1'd0; +wire main_k7ddrphy_sd_clk_se_delayed; +wire main_k7ddrphy_sd_clk_se_nodelay; +wire main_k7ddrphy_wdly_dq_bitslip_r; +reg main_k7ddrphy_wdly_dq_bitslip_re = 1'd0; +wire main_k7ddrphy_wdly_dq_bitslip_rst_r; +reg main_k7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; +reg main_k7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; +reg main_k7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; +reg main_k7ddrphy_wdly_dq_bitslip_w = 1'd0; +reg main_k7ddrphy_wdly_dq_bitslip_we = 1'd0; +wire main_k7ddrphy_wdly_dq_inc_r; +reg main_k7ddrphy_wdly_dq_inc_re = 1'd0; +reg main_k7ddrphy_wdly_dq_inc_w = 1'd0; +reg main_k7ddrphy_wdly_dq_inc_we = 1'd0; +wire main_k7ddrphy_wdly_dq_rst_r; +reg main_k7ddrphy_wdly_dq_rst_re = 1'd0; +reg main_k7ddrphy_wdly_dq_rst_w = 1'd0; +reg main_k7ddrphy_wdly_dq_rst_we = 1'd0; +wire main_k7ddrphy_wdly_dqs_inc_r; +reg main_k7ddrphy_wdly_dqs_inc_re = 1'd0; +reg main_k7ddrphy_wdly_dqs_inc_w = 1'd0; +reg main_k7ddrphy_wdly_dqs_inc_we = 1'd0; +wire main_k7ddrphy_wdly_dqs_rst_r; +reg main_k7ddrphy_wdly_dqs_rst_re = 1'd0; +reg main_k7ddrphy_wdly_dqs_rst_w = 1'd0; +reg main_k7ddrphy_wdly_dqs_rst_we = 1'd0; +reg main_k7ddrphy_wlevel_en_re = 1'd0; +reg main_k7ddrphy_wlevel_en_storage = 1'd0; +wire main_k7ddrphy_wlevel_strobe_r; +reg main_k7ddrphy_wlevel_strobe_re = 1'd0; +reg main_k7ddrphy_wlevel_strobe_w = 1'd0; +reg main_k7ddrphy_wlevel_strobe_we = 1'd0; +reg main_k7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg main_k7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg main_k7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +reg main_k7ddrphy_wrphase_re = 1'd0; +reg [1:0] main_k7ddrphy_wrphase_storage = 2'd2; +reg main_litedramcore_bankmachine0_auto_precharge = 1'd0; +reg [14:0] main_litedramcore_bankmachine0_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba; +reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine0_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine0_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine0_consume = 4'd0; +wire main_litedramcore_bankmachine0_do_read; +wire main_litedramcore_bankmachine0_fifo_in_first; +wire main_litedramcore_bankmachine0_fifo_in_last; +wire [21:0] main_litedramcore_bankmachine0_fifo_in_payload_addr; +wire main_litedramcore_bankmachine0_fifo_in_payload_we; +wire main_litedramcore_bankmachine0_fifo_out_first; +wire main_litedramcore_bankmachine0_fifo_out_last; +wire [21:0] main_litedramcore_bankmachine0_fifo_out_payload_addr; +wire main_litedramcore_bankmachine0_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine0_level = 5'd0; +wire main_litedramcore_bankmachine0_pipe_valid_sink_first; +wire main_litedramcore_bankmachine0_pipe_valid_sink_last; +wire [21:0] main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine0_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine0_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine0_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine0_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine0_pipe_valid_source_last = 1'd0; +reg [21:0] main_litedramcore_bankmachine0_pipe_valid_source_payload_addr = 22'd0; +reg main_litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine0_pipe_valid_source_ready; +reg main_litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine0_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine0_rdport_adr; +wire [24:0] main_litedramcore_bankmachine0_rdport_dat_r; +reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine0_refresh_req; +reg main_litedramcore_bankmachine0_replace = 1'd0; +wire [21:0] main_litedramcore_bankmachine0_req_addr; +wire main_litedramcore_bankmachine0_req_lock; +reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine0_req_ready; +wire main_litedramcore_bankmachine0_req_valid; +reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine0_req_we; +reg [14:0] main_litedramcore_bankmachine0_row = 15'd0; +reg main_litedramcore_bankmachine0_row_close = 1'd0; +reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine0_row_hit; +reg main_litedramcore_bankmachine0_row_open = 1'd0; +reg main_litedramcore_bankmachine0_row_opened = 1'd0; +reg main_litedramcore_bankmachine0_sink_first = 1'd0; +reg main_litedramcore_bankmachine0_sink_last = 1'd0; +wire [21:0] main_litedramcore_bankmachine0_sink_payload_addr; +wire main_litedramcore_bankmachine0_sink_payload_we; +wire main_litedramcore_bankmachine0_sink_ready; +wire main_litedramcore_bankmachine0_sink_sink_first; +wire main_litedramcore_bankmachine0_sink_sink_last; +wire [21:0] main_litedramcore_bankmachine0_sink_sink_payload_addr; +wire main_litedramcore_bankmachine0_sink_sink_payload_we; +wire main_litedramcore_bankmachine0_sink_sink_ready; +wire main_litedramcore_bankmachine0_sink_sink_valid; +wire main_litedramcore_bankmachine0_sink_valid; +wire main_litedramcore_bankmachine0_source_first; +wire main_litedramcore_bankmachine0_source_last; +wire [21:0] main_litedramcore_bankmachine0_source_payload_addr; +wire main_litedramcore_bankmachine0_source_payload_we; +wire main_litedramcore_bankmachine0_source_ready; +wire main_litedramcore_bankmachine0_source_source_first; +wire main_litedramcore_bankmachine0_source_source_last; +wire [21:0] main_litedramcore_bankmachine0_source_source_payload_addr; +wire main_litedramcore_bankmachine0_source_source_payload_we; +wire main_litedramcore_bankmachine0_source_source_ready; +wire main_litedramcore_bankmachine0_source_source_valid; +wire main_litedramcore_bankmachine0_source_valid; +wire [24:0] main_litedramcore_bankmachine0_syncfifo0_din; +wire [24:0] main_litedramcore_bankmachine0_syncfifo0_dout; +wire main_litedramcore_bankmachine0_syncfifo0_re; +wire main_litedramcore_bankmachine0_syncfifo0_readable; +wire main_litedramcore_bankmachine0_syncfifo0_we; +wire main_litedramcore_bankmachine0_syncfifo0_writable; +reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; -wire litedramcore_bankmachine0_trccon_valid; +reg main_litedramcore_bankmachine0_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine0_trascon_valid; +reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0; -wire litedramcore_bankmachine0_trascon_valid; +reg main_litedramcore_bankmachine0_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine0_trccon_valid; +reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine0_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0; -wire litedramcore_bankmachine1_req_valid; -wire litedramcore_bankmachine1_req_ready; -wire litedramcore_bankmachine1_req_we; -wire [21:0] litedramcore_bankmachine1_req_addr; -wire litedramcore_bankmachine1_req_lock; -reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine1_refresh_req; -reg litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg litedramcore_bankmachine1_cmd_valid = 1'd0; -reg litedramcore_bankmachine1_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; -reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine1_auto_precharge = 1'd0; -wire litedramcore_bankmachine1_sink_valid; -wire litedramcore_bankmachine1_sink_ready; -reg litedramcore_bankmachine1_sink_first = 1'd0; -reg litedramcore_bankmachine1_sink_last = 1'd0; -wire litedramcore_bankmachine1_sink_payload_we; -wire [21:0] litedramcore_bankmachine1_sink_payload_addr; -wire litedramcore_bankmachine1_source_valid; -wire litedramcore_bankmachine1_source_ready; -wire litedramcore_bankmachine1_source_first; -wire litedramcore_bankmachine1_source_last; -wire litedramcore_bankmachine1_source_payload_we; -wire [21:0] litedramcore_bankmachine1_source_payload_addr; -wire litedramcore_bankmachine1_syncfifo1_we; -wire litedramcore_bankmachine1_syncfifo1_writable; -wire litedramcore_bankmachine1_syncfifo1_re; -wire litedramcore_bankmachine1_syncfifo1_readable; -wire [24:0] litedramcore_bankmachine1_syncfifo1_din; -wire [24:0] litedramcore_bankmachine1_syncfifo1_dout; -reg [4:0] litedramcore_bankmachine1_level = 5'd0; -reg litedramcore_bankmachine1_replace = 1'd0; -reg [3:0] litedramcore_bankmachine1_produce = 4'd0; -reg [3:0] litedramcore_bankmachine1_consume = 4'd0; -reg [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine1_wrport_dat_r; -wire litedramcore_bankmachine1_wrport_we; -wire [24:0] litedramcore_bankmachine1_wrport_dat_w; -wire litedramcore_bankmachine1_do_read; -wire [3:0] litedramcore_bankmachine1_rdport_adr; -wire [24:0] litedramcore_bankmachine1_rdport_dat_r; -wire litedramcore_bankmachine1_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine1_fifo_in_payload_addr; -wire litedramcore_bankmachine1_fifo_in_first; -wire litedramcore_bankmachine1_fifo_in_last; -wire litedramcore_bankmachine1_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine1_fifo_out_payload_addr; -wire litedramcore_bankmachine1_fifo_out_first; -wire litedramcore_bankmachine1_fifo_out_last; -wire litedramcore_bankmachine1_sink_sink_valid; -wire litedramcore_bankmachine1_sink_sink_ready; -wire litedramcore_bankmachine1_sink_sink_first; -wire litedramcore_bankmachine1_sink_sink_last; -wire litedramcore_bankmachine1_sink_sink_payload_we; -wire [21:0] litedramcore_bankmachine1_sink_sink_payload_addr; -wire litedramcore_bankmachine1_source_source_valid; -wire litedramcore_bankmachine1_source_source_ready; -wire litedramcore_bankmachine1_source_source_first; -wire litedramcore_bankmachine1_source_source_last; -wire litedramcore_bankmachine1_source_source_payload_we; -wire [21:0] litedramcore_bankmachine1_source_source_payload_addr; -wire litedramcore_bankmachine1_pipe_valid_sink_valid; -wire litedramcore_bankmachine1_pipe_valid_sink_ready; -wire litedramcore_bankmachine1_pipe_valid_sink_first; -wire litedramcore_bankmachine1_pipe_valid_sink_last; -wire litedramcore_bankmachine1_pipe_valid_sink_payload_we; -wire [21:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine1_pipe_valid_source_ready; -reg litedramcore_bankmachine1_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine1_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine1_row = 15'd0; -reg litedramcore_bankmachine1_row_opened = 1'd0; -wire litedramcore_bankmachine1_row_hit; -reg litedramcore_bankmachine1_row_open = 1'd0; -reg litedramcore_bankmachine1_row_close = 1'd0; -reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine1_twtpcon_valid; +reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine0_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine0_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine0_wrport_dat_r; +wire [24:0] main_litedramcore_bankmachine0_wrport_dat_w; +wire main_litedramcore_bankmachine0_wrport_we; +reg main_litedramcore_bankmachine1_auto_precharge = 1'd0; +reg [14:0] main_litedramcore_bankmachine1_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba; +reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine1_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine1_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine1_consume = 4'd0; +wire main_litedramcore_bankmachine1_do_read; +wire main_litedramcore_bankmachine1_fifo_in_first; +wire main_litedramcore_bankmachine1_fifo_in_last; +wire [21:0] main_litedramcore_bankmachine1_fifo_in_payload_addr; +wire main_litedramcore_bankmachine1_fifo_in_payload_we; +wire main_litedramcore_bankmachine1_fifo_out_first; +wire main_litedramcore_bankmachine1_fifo_out_last; +wire [21:0] main_litedramcore_bankmachine1_fifo_out_payload_addr; +wire main_litedramcore_bankmachine1_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine1_level = 5'd0; +wire main_litedramcore_bankmachine1_pipe_valid_sink_first; +wire main_litedramcore_bankmachine1_pipe_valid_sink_last; +wire [21:0] main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine1_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine1_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine1_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine1_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine1_pipe_valid_source_last = 1'd0; +reg [21:0] main_litedramcore_bankmachine1_pipe_valid_source_payload_addr = 22'd0; +reg main_litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine1_pipe_valid_source_ready; +reg main_litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine1_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine1_rdport_adr; +wire [24:0] main_litedramcore_bankmachine1_rdport_dat_r; +reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine1_refresh_req; +reg main_litedramcore_bankmachine1_replace = 1'd0; +wire [21:0] main_litedramcore_bankmachine1_req_addr; +wire main_litedramcore_bankmachine1_req_lock; +reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine1_req_ready; +wire main_litedramcore_bankmachine1_req_valid; +reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine1_req_we; +reg [14:0] main_litedramcore_bankmachine1_row = 15'd0; +reg main_litedramcore_bankmachine1_row_close = 1'd0; +reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine1_row_hit; +reg main_litedramcore_bankmachine1_row_open = 1'd0; +reg main_litedramcore_bankmachine1_row_opened = 1'd0; +reg main_litedramcore_bankmachine1_sink_first = 1'd0; +reg main_litedramcore_bankmachine1_sink_last = 1'd0; +wire [21:0] main_litedramcore_bankmachine1_sink_payload_addr; +wire main_litedramcore_bankmachine1_sink_payload_we; +wire main_litedramcore_bankmachine1_sink_ready; +wire main_litedramcore_bankmachine1_sink_sink_first; +wire main_litedramcore_bankmachine1_sink_sink_last; +wire [21:0] main_litedramcore_bankmachine1_sink_sink_payload_addr; +wire main_litedramcore_bankmachine1_sink_sink_payload_we; +wire main_litedramcore_bankmachine1_sink_sink_ready; +wire main_litedramcore_bankmachine1_sink_sink_valid; +wire main_litedramcore_bankmachine1_sink_valid; +wire main_litedramcore_bankmachine1_source_first; +wire main_litedramcore_bankmachine1_source_last; +wire [21:0] main_litedramcore_bankmachine1_source_payload_addr; +wire main_litedramcore_bankmachine1_source_payload_we; +wire main_litedramcore_bankmachine1_source_ready; +wire main_litedramcore_bankmachine1_source_source_first; +wire main_litedramcore_bankmachine1_source_source_last; +wire [21:0] main_litedramcore_bankmachine1_source_source_payload_addr; +wire main_litedramcore_bankmachine1_source_source_payload_we; +wire main_litedramcore_bankmachine1_source_source_ready; +wire main_litedramcore_bankmachine1_source_source_valid; +wire main_litedramcore_bankmachine1_source_valid; +wire [24:0] main_litedramcore_bankmachine1_syncfifo1_din; +wire [24:0] main_litedramcore_bankmachine1_syncfifo1_dout; +wire main_litedramcore_bankmachine1_syncfifo1_re; +wire main_litedramcore_bankmachine1_syncfifo1_readable; +wire main_litedramcore_bankmachine1_syncfifo1_we; +wire main_litedramcore_bankmachine1_syncfifo1_writable; +reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; -wire litedramcore_bankmachine1_trccon_valid; +reg main_litedramcore_bankmachine1_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine1_trascon_valid; +reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0; -wire litedramcore_bankmachine1_trascon_valid; +reg main_litedramcore_bankmachine1_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine1_trccon_valid; +reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine1_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0; -wire litedramcore_bankmachine2_req_valid; -wire litedramcore_bankmachine2_req_ready; -wire litedramcore_bankmachine2_req_we; -wire [21:0] litedramcore_bankmachine2_req_addr; -wire litedramcore_bankmachine2_req_lock; -reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine2_refresh_req; -reg litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg litedramcore_bankmachine2_cmd_valid = 1'd0; -reg litedramcore_bankmachine2_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; -reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine2_auto_precharge = 1'd0; -wire litedramcore_bankmachine2_sink_valid; -wire litedramcore_bankmachine2_sink_ready; -reg litedramcore_bankmachine2_sink_first = 1'd0; -reg litedramcore_bankmachine2_sink_last = 1'd0; -wire litedramcore_bankmachine2_sink_payload_we; -wire [21:0] litedramcore_bankmachine2_sink_payload_addr; -wire litedramcore_bankmachine2_source_valid; -wire litedramcore_bankmachine2_source_ready; -wire litedramcore_bankmachine2_source_first; -wire litedramcore_bankmachine2_source_last; -wire litedramcore_bankmachine2_source_payload_we; -wire [21:0] litedramcore_bankmachine2_source_payload_addr; -wire litedramcore_bankmachine2_syncfifo2_we; -wire litedramcore_bankmachine2_syncfifo2_writable; -wire litedramcore_bankmachine2_syncfifo2_re; -wire litedramcore_bankmachine2_syncfifo2_readable; -wire [24:0] litedramcore_bankmachine2_syncfifo2_din; -wire [24:0] litedramcore_bankmachine2_syncfifo2_dout; -reg [4:0] litedramcore_bankmachine2_level = 5'd0; -reg litedramcore_bankmachine2_replace = 1'd0; -reg [3:0] litedramcore_bankmachine2_produce = 4'd0; -reg [3:0] litedramcore_bankmachine2_consume = 4'd0; -reg [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine2_wrport_dat_r; -wire litedramcore_bankmachine2_wrport_we; -wire [24:0] litedramcore_bankmachine2_wrport_dat_w; -wire litedramcore_bankmachine2_do_read; -wire [3:0] litedramcore_bankmachine2_rdport_adr; -wire [24:0] litedramcore_bankmachine2_rdport_dat_r; -wire litedramcore_bankmachine2_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine2_fifo_in_payload_addr; -wire litedramcore_bankmachine2_fifo_in_first; -wire litedramcore_bankmachine2_fifo_in_last; -wire litedramcore_bankmachine2_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine2_fifo_out_payload_addr; -wire litedramcore_bankmachine2_fifo_out_first; -wire litedramcore_bankmachine2_fifo_out_last; -wire litedramcore_bankmachine2_sink_sink_valid; -wire litedramcore_bankmachine2_sink_sink_ready; -wire litedramcore_bankmachine2_sink_sink_first; -wire litedramcore_bankmachine2_sink_sink_last; -wire litedramcore_bankmachine2_sink_sink_payload_we; -wire [21:0] litedramcore_bankmachine2_sink_sink_payload_addr; -wire litedramcore_bankmachine2_source_source_valid; -wire litedramcore_bankmachine2_source_source_ready; -wire litedramcore_bankmachine2_source_source_first; -wire litedramcore_bankmachine2_source_source_last; -wire litedramcore_bankmachine2_source_source_payload_we; -wire [21:0] litedramcore_bankmachine2_source_source_payload_addr; -wire litedramcore_bankmachine2_pipe_valid_sink_valid; -wire litedramcore_bankmachine2_pipe_valid_sink_ready; -wire litedramcore_bankmachine2_pipe_valid_sink_first; -wire litedramcore_bankmachine2_pipe_valid_sink_last; -wire litedramcore_bankmachine2_pipe_valid_sink_payload_we; -wire [21:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine2_pipe_valid_source_ready; -reg litedramcore_bankmachine2_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine2_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine2_row = 15'd0; -reg litedramcore_bankmachine2_row_opened = 1'd0; -wire litedramcore_bankmachine2_row_hit; -reg litedramcore_bankmachine2_row_open = 1'd0; -reg litedramcore_bankmachine2_row_close = 1'd0; -reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine2_twtpcon_valid; +reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine1_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine1_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine1_wrport_dat_r; +wire [24:0] main_litedramcore_bankmachine1_wrport_dat_w; +wire main_litedramcore_bankmachine1_wrport_we; +reg main_litedramcore_bankmachine2_auto_precharge = 1'd0; +reg [14:0] main_litedramcore_bankmachine2_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba; +reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine2_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine2_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine2_consume = 4'd0; +wire main_litedramcore_bankmachine2_do_read; +wire main_litedramcore_bankmachine2_fifo_in_first; +wire main_litedramcore_bankmachine2_fifo_in_last; +wire [21:0] main_litedramcore_bankmachine2_fifo_in_payload_addr; +wire main_litedramcore_bankmachine2_fifo_in_payload_we; +wire main_litedramcore_bankmachine2_fifo_out_first; +wire main_litedramcore_bankmachine2_fifo_out_last; +wire [21:0] main_litedramcore_bankmachine2_fifo_out_payload_addr; +wire main_litedramcore_bankmachine2_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine2_level = 5'd0; +wire main_litedramcore_bankmachine2_pipe_valid_sink_first; +wire main_litedramcore_bankmachine2_pipe_valid_sink_last; +wire [21:0] main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine2_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine2_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine2_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine2_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine2_pipe_valid_source_last = 1'd0; +reg [21:0] main_litedramcore_bankmachine2_pipe_valid_source_payload_addr = 22'd0; +reg main_litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine2_pipe_valid_source_ready; +reg main_litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine2_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine2_rdport_adr; +wire [24:0] main_litedramcore_bankmachine2_rdport_dat_r; +reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine2_refresh_req; +reg main_litedramcore_bankmachine2_replace = 1'd0; +wire [21:0] main_litedramcore_bankmachine2_req_addr; +wire main_litedramcore_bankmachine2_req_lock; +reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine2_req_ready; +wire main_litedramcore_bankmachine2_req_valid; +reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine2_req_we; +reg [14:0] main_litedramcore_bankmachine2_row = 15'd0; +reg main_litedramcore_bankmachine2_row_close = 1'd0; +reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine2_row_hit; +reg main_litedramcore_bankmachine2_row_open = 1'd0; +reg main_litedramcore_bankmachine2_row_opened = 1'd0; +reg main_litedramcore_bankmachine2_sink_first = 1'd0; +reg main_litedramcore_bankmachine2_sink_last = 1'd0; +wire [21:0] main_litedramcore_bankmachine2_sink_payload_addr; +wire main_litedramcore_bankmachine2_sink_payload_we; +wire main_litedramcore_bankmachine2_sink_ready; +wire main_litedramcore_bankmachine2_sink_sink_first; +wire main_litedramcore_bankmachine2_sink_sink_last; +wire [21:0] main_litedramcore_bankmachine2_sink_sink_payload_addr; +wire main_litedramcore_bankmachine2_sink_sink_payload_we; +wire main_litedramcore_bankmachine2_sink_sink_ready; +wire main_litedramcore_bankmachine2_sink_sink_valid; +wire main_litedramcore_bankmachine2_sink_valid; +wire main_litedramcore_bankmachine2_source_first; +wire main_litedramcore_bankmachine2_source_last; +wire [21:0] main_litedramcore_bankmachine2_source_payload_addr; +wire main_litedramcore_bankmachine2_source_payload_we; +wire main_litedramcore_bankmachine2_source_ready; +wire main_litedramcore_bankmachine2_source_source_first; +wire main_litedramcore_bankmachine2_source_source_last; +wire [21:0] main_litedramcore_bankmachine2_source_source_payload_addr; +wire main_litedramcore_bankmachine2_source_source_payload_we; +wire main_litedramcore_bankmachine2_source_source_ready; +wire main_litedramcore_bankmachine2_source_source_valid; +wire main_litedramcore_bankmachine2_source_valid; +wire [24:0] main_litedramcore_bankmachine2_syncfifo2_din; +wire [24:0] main_litedramcore_bankmachine2_syncfifo2_dout; +wire main_litedramcore_bankmachine2_syncfifo2_re; +wire main_litedramcore_bankmachine2_syncfifo2_readable; +wire main_litedramcore_bankmachine2_syncfifo2_we; +wire main_litedramcore_bankmachine2_syncfifo2_writable; +reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; -wire litedramcore_bankmachine2_trccon_valid; +reg main_litedramcore_bankmachine2_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine2_trascon_valid; +reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0; -wire litedramcore_bankmachine2_trascon_valid; +reg main_litedramcore_bankmachine2_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine2_trccon_valid; +reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine2_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0; -wire litedramcore_bankmachine3_req_valid; -wire litedramcore_bankmachine3_req_ready; -wire litedramcore_bankmachine3_req_we; -wire [21:0] litedramcore_bankmachine3_req_addr; -wire litedramcore_bankmachine3_req_lock; -reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine3_refresh_req; -reg litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg litedramcore_bankmachine3_cmd_valid = 1'd0; -reg litedramcore_bankmachine3_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; -reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine3_auto_precharge = 1'd0; -wire litedramcore_bankmachine3_sink_valid; -wire litedramcore_bankmachine3_sink_ready; -reg litedramcore_bankmachine3_sink_first = 1'd0; -reg litedramcore_bankmachine3_sink_last = 1'd0; -wire litedramcore_bankmachine3_sink_payload_we; -wire [21:0] litedramcore_bankmachine3_sink_payload_addr; -wire litedramcore_bankmachine3_source_valid; -wire litedramcore_bankmachine3_source_ready; -wire litedramcore_bankmachine3_source_first; -wire litedramcore_bankmachine3_source_last; -wire litedramcore_bankmachine3_source_payload_we; -wire [21:0] litedramcore_bankmachine3_source_payload_addr; -wire litedramcore_bankmachine3_syncfifo3_we; -wire litedramcore_bankmachine3_syncfifo3_writable; -wire litedramcore_bankmachine3_syncfifo3_re; -wire litedramcore_bankmachine3_syncfifo3_readable; -wire [24:0] litedramcore_bankmachine3_syncfifo3_din; -wire [24:0] litedramcore_bankmachine3_syncfifo3_dout; -reg [4:0] litedramcore_bankmachine3_level = 5'd0; -reg litedramcore_bankmachine3_replace = 1'd0; -reg [3:0] litedramcore_bankmachine3_produce = 4'd0; -reg [3:0] litedramcore_bankmachine3_consume = 4'd0; -reg [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine3_wrport_dat_r; -wire litedramcore_bankmachine3_wrport_we; -wire [24:0] litedramcore_bankmachine3_wrport_dat_w; -wire litedramcore_bankmachine3_do_read; -wire [3:0] litedramcore_bankmachine3_rdport_adr; -wire [24:0] litedramcore_bankmachine3_rdport_dat_r; -wire litedramcore_bankmachine3_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine3_fifo_in_payload_addr; -wire litedramcore_bankmachine3_fifo_in_first; -wire litedramcore_bankmachine3_fifo_in_last; -wire litedramcore_bankmachine3_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine3_fifo_out_payload_addr; -wire litedramcore_bankmachine3_fifo_out_first; -wire litedramcore_bankmachine3_fifo_out_last; -wire litedramcore_bankmachine3_sink_sink_valid; -wire litedramcore_bankmachine3_sink_sink_ready; -wire litedramcore_bankmachine3_sink_sink_first; -wire litedramcore_bankmachine3_sink_sink_last; -wire litedramcore_bankmachine3_sink_sink_payload_we; -wire [21:0] litedramcore_bankmachine3_sink_sink_payload_addr; -wire litedramcore_bankmachine3_source_source_valid; -wire litedramcore_bankmachine3_source_source_ready; -wire litedramcore_bankmachine3_source_source_first; -wire litedramcore_bankmachine3_source_source_last; -wire litedramcore_bankmachine3_source_source_payload_we; -wire [21:0] litedramcore_bankmachine3_source_source_payload_addr; -wire litedramcore_bankmachine3_pipe_valid_sink_valid; -wire litedramcore_bankmachine3_pipe_valid_sink_ready; -wire litedramcore_bankmachine3_pipe_valid_sink_first; -wire litedramcore_bankmachine3_pipe_valid_sink_last; -wire litedramcore_bankmachine3_pipe_valid_sink_payload_we; -wire [21:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine3_pipe_valid_source_ready; -reg litedramcore_bankmachine3_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine3_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine3_row = 15'd0; -reg litedramcore_bankmachine3_row_opened = 1'd0; -wire litedramcore_bankmachine3_row_hit; -reg litedramcore_bankmachine3_row_open = 1'd0; -reg litedramcore_bankmachine3_row_close = 1'd0; -reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine3_twtpcon_valid; +reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine2_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine2_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine2_wrport_dat_r; +wire [24:0] main_litedramcore_bankmachine2_wrport_dat_w; +wire main_litedramcore_bankmachine2_wrport_we; +reg main_litedramcore_bankmachine3_auto_precharge = 1'd0; +reg [14:0] main_litedramcore_bankmachine3_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba; +reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine3_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine3_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine3_consume = 4'd0; +wire main_litedramcore_bankmachine3_do_read; +wire main_litedramcore_bankmachine3_fifo_in_first; +wire main_litedramcore_bankmachine3_fifo_in_last; +wire [21:0] main_litedramcore_bankmachine3_fifo_in_payload_addr; +wire main_litedramcore_bankmachine3_fifo_in_payload_we; +wire main_litedramcore_bankmachine3_fifo_out_first; +wire main_litedramcore_bankmachine3_fifo_out_last; +wire [21:0] main_litedramcore_bankmachine3_fifo_out_payload_addr; +wire main_litedramcore_bankmachine3_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine3_level = 5'd0; +wire main_litedramcore_bankmachine3_pipe_valid_sink_first; +wire main_litedramcore_bankmachine3_pipe_valid_sink_last; +wire [21:0] main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine3_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine3_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine3_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine3_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine3_pipe_valid_source_last = 1'd0; +reg [21:0] main_litedramcore_bankmachine3_pipe_valid_source_payload_addr = 22'd0; +reg main_litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine3_pipe_valid_source_ready; +reg main_litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine3_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine3_rdport_adr; +wire [24:0] main_litedramcore_bankmachine3_rdport_dat_r; +reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine3_refresh_req; +reg main_litedramcore_bankmachine3_replace = 1'd0; +wire [21:0] main_litedramcore_bankmachine3_req_addr; +wire main_litedramcore_bankmachine3_req_lock; +reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine3_req_ready; +wire main_litedramcore_bankmachine3_req_valid; +reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine3_req_we; +reg [14:0] main_litedramcore_bankmachine3_row = 15'd0; +reg main_litedramcore_bankmachine3_row_close = 1'd0; +reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine3_row_hit; +reg main_litedramcore_bankmachine3_row_open = 1'd0; +reg main_litedramcore_bankmachine3_row_opened = 1'd0; +reg main_litedramcore_bankmachine3_sink_first = 1'd0; +reg main_litedramcore_bankmachine3_sink_last = 1'd0; +wire [21:0] main_litedramcore_bankmachine3_sink_payload_addr; +wire main_litedramcore_bankmachine3_sink_payload_we; +wire main_litedramcore_bankmachine3_sink_ready; +wire main_litedramcore_bankmachine3_sink_sink_first; +wire main_litedramcore_bankmachine3_sink_sink_last; +wire [21:0] main_litedramcore_bankmachine3_sink_sink_payload_addr; +wire main_litedramcore_bankmachine3_sink_sink_payload_we; +wire main_litedramcore_bankmachine3_sink_sink_ready; +wire main_litedramcore_bankmachine3_sink_sink_valid; +wire main_litedramcore_bankmachine3_sink_valid; +wire main_litedramcore_bankmachine3_source_first; +wire main_litedramcore_bankmachine3_source_last; +wire [21:0] main_litedramcore_bankmachine3_source_payload_addr; +wire main_litedramcore_bankmachine3_source_payload_we; +wire main_litedramcore_bankmachine3_source_ready; +wire main_litedramcore_bankmachine3_source_source_first; +wire main_litedramcore_bankmachine3_source_source_last; +wire [21:0] main_litedramcore_bankmachine3_source_source_payload_addr; +wire main_litedramcore_bankmachine3_source_source_payload_we; +wire main_litedramcore_bankmachine3_source_source_ready; +wire main_litedramcore_bankmachine3_source_source_valid; +wire main_litedramcore_bankmachine3_source_valid; +wire [24:0] main_litedramcore_bankmachine3_syncfifo3_din; +wire [24:0] main_litedramcore_bankmachine3_syncfifo3_dout; +wire main_litedramcore_bankmachine3_syncfifo3_re; +wire main_litedramcore_bankmachine3_syncfifo3_readable; +wire main_litedramcore_bankmachine3_syncfifo3_we; +wire main_litedramcore_bankmachine3_syncfifo3_writable; +reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; -wire litedramcore_bankmachine3_trccon_valid; +reg main_litedramcore_bankmachine3_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine3_trascon_valid; +reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0; -wire litedramcore_bankmachine3_trascon_valid; +reg main_litedramcore_bankmachine3_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine3_trccon_valid; +reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine3_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0; -wire litedramcore_bankmachine4_req_valid; -wire litedramcore_bankmachine4_req_ready; -wire litedramcore_bankmachine4_req_we; -wire [21:0] litedramcore_bankmachine4_req_addr; -wire litedramcore_bankmachine4_req_lock; -reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine4_refresh_req; -reg litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg litedramcore_bankmachine4_cmd_valid = 1'd0; -reg litedramcore_bankmachine4_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; -reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine4_auto_precharge = 1'd0; -wire litedramcore_bankmachine4_sink_valid; -wire litedramcore_bankmachine4_sink_ready; -reg litedramcore_bankmachine4_sink_first = 1'd0; -reg litedramcore_bankmachine4_sink_last = 1'd0; -wire litedramcore_bankmachine4_sink_payload_we; -wire [21:0] litedramcore_bankmachine4_sink_payload_addr; -wire litedramcore_bankmachine4_source_valid; -wire litedramcore_bankmachine4_source_ready; -wire litedramcore_bankmachine4_source_first; -wire litedramcore_bankmachine4_source_last; -wire litedramcore_bankmachine4_source_payload_we; -wire [21:0] litedramcore_bankmachine4_source_payload_addr; -wire litedramcore_bankmachine4_syncfifo4_we; -wire litedramcore_bankmachine4_syncfifo4_writable; -wire litedramcore_bankmachine4_syncfifo4_re; -wire litedramcore_bankmachine4_syncfifo4_readable; -wire [24:0] litedramcore_bankmachine4_syncfifo4_din; -wire [24:0] litedramcore_bankmachine4_syncfifo4_dout; -reg [4:0] litedramcore_bankmachine4_level = 5'd0; -reg litedramcore_bankmachine4_replace = 1'd0; -reg [3:0] litedramcore_bankmachine4_produce = 4'd0; -reg [3:0] litedramcore_bankmachine4_consume = 4'd0; -reg [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine4_wrport_dat_r; -wire litedramcore_bankmachine4_wrport_we; -wire [24:0] litedramcore_bankmachine4_wrport_dat_w; -wire litedramcore_bankmachine4_do_read; -wire [3:0] litedramcore_bankmachine4_rdport_adr; -wire [24:0] litedramcore_bankmachine4_rdport_dat_r; -wire litedramcore_bankmachine4_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine4_fifo_in_payload_addr; -wire litedramcore_bankmachine4_fifo_in_first; -wire litedramcore_bankmachine4_fifo_in_last; -wire litedramcore_bankmachine4_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine4_fifo_out_payload_addr; -wire litedramcore_bankmachine4_fifo_out_first; -wire litedramcore_bankmachine4_fifo_out_last; -wire litedramcore_bankmachine4_sink_sink_valid; -wire litedramcore_bankmachine4_sink_sink_ready; -wire litedramcore_bankmachine4_sink_sink_first; -wire litedramcore_bankmachine4_sink_sink_last; -wire litedramcore_bankmachine4_sink_sink_payload_we; -wire [21:0] litedramcore_bankmachine4_sink_sink_payload_addr; -wire litedramcore_bankmachine4_source_source_valid; -wire litedramcore_bankmachine4_source_source_ready; -wire litedramcore_bankmachine4_source_source_first; -wire litedramcore_bankmachine4_source_source_last; -wire litedramcore_bankmachine4_source_source_payload_we; -wire [21:0] litedramcore_bankmachine4_source_source_payload_addr; -wire litedramcore_bankmachine4_pipe_valid_sink_valid; -wire litedramcore_bankmachine4_pipe_valid_sink_ready; -wire litedramcore_bankmachine4_pipe_valid_sink_first; -wire litedramcore_bankmachine4_pipe_valid_sink_last; -wire litedramcore_bankmachine4_pipe_valid_sink_payload_we; -wire [21:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine4_pipe_valid_source_ready; -reg litedramcore_bankmachine4_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine4_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine4_row = 15'd0; -reg litedramcore_bankmachine4_row_opened = 1'd0; -wire litedramcore_bankmachine4_row_hit; -reg litedramcore_bankmachine4_row_open = 1'd0; -reg litedramcore_bankmachine4_row_close = 1'd0; -reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine4_twtpcon_valid; +reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine3_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine3_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine3_wrport_dat_r; +wire [24:0] main_litedramcore_bankmachine3_wrport_dat_w; +wire main_litedramcore_bankmachine3_wrport_we; +reg main_litedramcore_bankmachine4_auto_precharge = 1'd0; +reg [14:0] main_litedramcore_bankmachine4_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba; +reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine4_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine4_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine4_consume = 4'd0; +wire main_litedramcore_bankmachine4_do_read; +wire main_litedramcore_bankmachine4_fifo_in_first; +wire main_litedramcore_bankmachine4_fifo_in_last; +wire [21:0] main_litedramcore_bankmachine4_fifo_in_payload_addr; +wire main_litedramcore_bankmachine4_fifo_in_payload_we; +wire main_litedramcore_bankmachine4_fifo_out_first; +wire main_litedramcore_bankmachine4_fifo_out_last; +wire [21:0] main_litedramcore_bankmachine4_fifo_out_payload_addr; +wire main_litedramcore_bankmachine4_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine4_level = 5'd0; +wire main_litedramcore_bankmachine4_pipe_valid_sink_first; +wire main_litedramcore_bankmachine4_pipe_valid_sink_last; +wire [21:0] main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine4_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine4_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine4_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine4_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine4_pipe_valid_source_last = 1'd0; +reg [21:0] main_litedramcore_bankmachine4_pipe_valid_source_payload_addr = 22'd0; +reg main_litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine4_pipe_valid_source_ready; +reg main_litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine4_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine4_rdport_adr; +wire [24:0] main_litedramcore_bankmachine4_rdport_dat_r; +reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine4_refresh_req; +reg main_litedramcore_bankmachine4_replace = 1'd0; +wire [21:0] main_litedramcore_bankmachine4_req_addr; +wire main_litedramcore_bankmachine4_req_lock; +reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine4_req_ready; +wire main_litedramcore_bankmachine4_req_valid; +reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine4_req_we; +reg [14:0] main_litedramcore_bankmachine4_row = 15'd0; +reg main_litedramcore_bankmachine4_row_close = 1'd0; +reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine4_row_hit; +reg main_litedramcore_bankmachine4_row_open = 1'd0; +reg main_litedramcore_bankmachine4_row_opened = 1'd0; +reg main_litedramcore_bankmachine4_sink_first = 1'd0; +reg main_litedramcore_bankmachine4_sink_last = 1'd0; +wire [21:0] main_litedramcore_bankmachine4_sink_payload_addr; +wire main_litedramcore_bankmachine4_sink_payload_we; +wire main_litedramcore_bankmachine4_sink_ready; +wire main_litedramcore_bankmachine4_sink_sink_first; +wire main_litedramcore_bankmachine4_sink_sink_last; +wire [21:0] main_litedramcore_bankmachine4_sink_sink_payload_addr; +wire main_litedramcore_bankmachine4_sink_sink_payload_we; +wire main_litedramcore_bankmachine4_sink_sink_ready; +wire main_litedramcore_bankmachine4_sink_sink_valid; +wire main_litedramcore_bankmachine4_sink_valid; +wire main_litedramcore_bankmachine4_source_first; +wire main_litedramcore_bankmachine4_source_last; +wire [21:0] main_litedramcore_bankmachine4_source_payload_addr; +wire main_litedramcore_bankmachine4_source_payload_we; +wire main_litedramcore_bankmachine4_source_ready; +wire main_litedramcore_bankmachine4_source_source_first; +wire main_litedramcore_bankmachine4_source_source_last; +wire [21:0] main_litedramcore_bankmachine4_source_source_payload_addr; +wire main_litedramcore_bankmachine4_source_source_payload_we; +wire main_litedramcore_bankmachine4_source_source_ready; +wire main_litedramcore_bankmachine4_source_source_valid; +wire main_litedramcore_bankmachine4_source_valid; +wire [24:0] main_litedramcore_bankmachine4_syncfifo4_din; +wire [24:0] main_litedramcore_bankmachine4_syncfifo4_dout; +wire main_litedramcore_bankmachine4_syncfifo4_re; +wire main_litedramcore_bankmachine4_syncfifo4_readable; +wire main_litedramcore_bankmachine4_syncfifo4_we; +wire main_litedramcore_bankmachine4_syncfifo4_writable; +reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; -wire litedramcore_bankmachine4_trccon_valid; +reg main_litedramcore_bankmachine4_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine4_trascon_valid; +reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0; -wire litedramcore_bankmachine4_trascon_valid; +reg main_litedramcore_bankmachine4_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine4_trccon_valid; +reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine4_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0; -wire litedramcore_bankmachine5_req_valid; -wire litedramcore_bankmachine5_req_ready; -wire litedramcore_bankmachine5_req_we; -wire [21:0] litedramcore_bankmachine5_req_addr; -wire litedramcore_bankmachine5_req_lock; -reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine5_refresh_req; -reg litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg litedramcore_bankmachine5_cmd_valid = 1'd0; -reg litedramcore_bankmachine5_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; -reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine5_auto_precharge = 1'd0; -wire litedramcore_bankmachine5_sink_valid; -wire litedramcore_bankmachine5_sink_ready; -reg litedramcore_bankmachine5_sink_first = 1'd0; -reg litedramcore_bankmachine5_sink_last = 1'd0; -wire litedramcore_bankmachine5_sink_payload_we; -wire [21:0] litedramcore_bankmachine5_sink_payload_addr; -wire litedramcore_bankmachine5_source_valid; -wire litedramcore_bankmachine5_source_ready; -wire litedramcore_bankmachine5_source_first; -wire litedramcore_bankmachine5_source_last; -wire litedramcore_bankmachine5_source_payload_we; -wire [21:0] litedramcore_bankmachine5_source_payload_addr; -wire litedramcore_bankmachine5_syncfifo5_we; -wire litedramcore_bankmachine5_syncfifo5_writable; -wire litedramcore_bankmachine5_syncfifo5_re; -wire litedramcore_bankmachine5_syncfifo5_readable; -wire [24:0] litedramcore_bankmachine5_syncfifo5_din; -wire [24:0] litedramcore_bankmachine5_syncfifo5_dout; -reg [4:0] litedramcore_bankmachine5_level = 5'd0; -reg litedramcore_bankmachine5_replace = 1'd0; -reg [3:0] litedramcore_bankmachine5_produce = 4'd0; -reg [3:0] litedramcore_bankmachine5_consume = 4'd0; -reg [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine5_wrport_dat_r; -wire litedramcore_bankmachine5_wrport_we; -wire [24:0] litedramcore_bankmachine5_wrport_dat_w; -wire litedramcore_bankmachine5_do_read; -wire [3:0] litedramcore_bankmachine5_rdport_adr; -wire [24:0] litedramcore_bankmachine5_rdport_dat_r; -wire litedramcore_bankmachine5_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine5_fifo_in_payload_addr; -wire litedramcore_bankmachine5_fifo_in_first; -wire litedramcore_bankmachine5_fifo_in_last; -wire litedramcore_bankmachine5_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine5_fifo_out_payload_addr; -wire litedramcore_bankmachine5_fifo_out_first; -wire litedramcore_bankmachine5_fifo_out_last; -wire litedramcore_bankmachine5_sink_sink_valid; -wire litedramcore_bankmachine5_sink_sink_ready; -wire litedramcore_bankmachine5_sink_sink_first; -wire litedramcore_bankmachine5_sink_sink_last; -wire litedramcore_bankmachine5_sink_sink_payload_we; -wire [21:0] litedramcore_bankmachine5_sink_sink_payload_addr; -wire litedramcore_bankmachine5_source_source_valid; -wire litedramcore_bankmachine5_source_source_ready; -wire litedramcore_bankmachine5_source_source_first; -wire litedramcore_bankmachine5_source_source_last; -wire litedramcore_bankmachine5_source_source_payload_we; -wire [21:0] litedramcore_bankmachine5_source_source_payload_addr; -wire litedramcore_bankmachine5_pipe_valid_sink_valid; -wire litedramcore_bankmachine5_pipe_valid_sink_ready; -wire litedramcore_bankmachine5_pipe_valid_sink_first; -wire litedramcore_bankmachine5_pipe_valid_sink_last; -wire litedramcore_bankmachine5_pipe_valid_sink_payload_we; -wire [21:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine5_pipe_valid_source_ready; -reg litedramcore_bankmachine5_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine5_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine5_row = 15'd0; -reg litedramcore_bankmachine5_row_opened = 1'd0; -wire litedramcore_bankmachine5_row_hit; -reg litedramcore_bankmachine5_row_open = 1'd0; -reg litedramcore_bankmachine5_row_close = 1'd0; -reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine5_twtpcon_valid; +reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine4_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine4_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine4_wrport_dat_r; +wire [24:0] main_litedramcore_bankmachine4_wrport_dat_w; +wire main_litedramcore_bankmachine4_wrport_we; +reg main_litedramcore_bankmachine5_auto_precharge = 1'd0; +reg [14:0] main_litedramcore_bankmachine5_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba; +reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine5_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine5_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine5_consume = 4'd0; +wire main_litedramcore_bankmachine5_do_read; +wire main_litedramcore_bankmachine5_fifo_in_first; +wire main_litedramcore_bankmachine5_fifo_in_last; +wire [21:0] main_litedramcore_bankmachine5_fifo_in_payload_addr; +wire main_litedramcore_bankmachine5_fifo_in_payload_we; +wire main_litedramcore_bankmachine5_fifo_out_first; +wire main_litedramcore_bankmachine5_fifo_out_last; +wire [21:0] main_litedramcore_bankmachine5_fifo_out_payload_addr; +wire main_litedramcore_bankmachine5_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine5_level = 5'd0; +wire main_litedramcore_bankmachine5_pipe_valid_sink_first; +wire main_litedramcore_bankmachine5_pipe_valid_sink_last; +wire [21:0] main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine5_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine5_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine5_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine5_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine5_pipe_valid_source_last = 1'd0; +reg [21:0] main_litedramcore_bankmachine5_pipe_valid_source_payload_addr = 22'd0; +reg main_litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine5_pipe_valid_source_ready; +reg main_litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine5_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine5_rdport_adr; +wire [24:0] main_litedramcore_bankmachine5_rdport_dat_r; +reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine5_refresh_req; +reg main_litedramcore_bankmachine5_replace = 1'd0; +wire [21:0] main_litedramcore_bankmachine5_req_addr; +wire main_litedramcore_bankmachine5_req_lock; +reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine5_req_ready; +wire main_litedramcore_bankmachine5_req_valid; +reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine5_req_we; +reg [14:0] main_litedramcore_bankmachine5_row = 15'd0; +reg main_litedramcore_bankmachine5_row_close = 1'd0; +reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine5_row_hit; +reg main_litedramcore_bankmachine5_row_open = 1'd0; +reg main_litedramcore_bankmachine5_row_opened = 1'd0; +reg main_litedramcore_bankmachine5_sink_first = 1'd0; +reg main_litedramcore_bankmachine5_sink_last = 1'd0; +wire [21:0] main_litedramcore_bankmachine5_sink_payload_addr; +wire main_litedramcore_bankmachine5_sink_payload_we; +wire main_litedramcore_bankmachine5_sink_ready; +wire main_litedramcore_bankmachine5_sink_sink_first; +wire main_litedramcore_bankmachine5_sink_sink_last; +wire [21:0] main_litedramcore_bankmachine5_sink_sink_payload_addr; +wire main_litedramcore_bankmachine5_sink_sink_payload_we; +wire main_litedramcore_bankmachine5_sink_sink_ready; +wire main_litedramcore_bankmachine5_sink_sink_valid; +wire main_litedramcore_bankmachine5_sink_valid; +wire main_litedramcore_bankmachine5_source_first; +wire main_litedramcore_bankmachine5_source_last; +wire [21:0] main_litedramcore_bankmachine5_source_payload_addr; +wire main_litedramcore_bankmachine5_source_payload_we; +wire main_litedramcore_bankmachine5_source_ready; +wire main_litedramcore_bankmachine5_source_source_first; +wire main_litedramcore_bankmachine5_source_source_last; +wire [21:0] main_litedramcore_bankmachine5_source_source_payload_addr; +wire main_litedramcore_bankmachine5_source_source_payload_we; +wire main_litedramcore_bankmachine5_source_source_ready; +wire main_litedramcore_bankmachine5_source_source_valid; +wire main_litedramcore_bankmachine5_source_valid; +wire [24:0] main_litedramcore_bankmachine5_syncfifo5_din; +wire [24:0] main_litedramcore_bankmachine5_syncfifo5_dout; +wire main_litedramcore_bankmachine5_syncfifo5_re; +wire main_litedramcore_bankmachine5_syncfifo5_readable; +wire main_litedramcore_bankmachine5_syncfifo5_we; +wire main_litedramcore_bankmachine5_syncfifo5_writable; +reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; -wire litedramcore_bankmachine5_trccon_valid; +reg main_litedramcore_bankmachine5_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine5_trascon_valid; +reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0; -wire litedramcore_bankmachine5_trascon_valid; +reg main_litedramcore_bankmachine5_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine5_trccon_valid; +reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine5_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0; -wire litedramcore_bankmachine6_req_valid; -wire litedramcore_bankmachine6_req_ready; -wire litedramcore_bankmachine6_req_we; -wire [21:0] litedramcore_bankmachine6_req_addr; -wire litedramcore_bankmachine6_req_lock; -reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine6_refresh_req; -reg litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg litedramcore_bankmachine6_cmd_valid = 1'd0; -reg litedramcore_bankmachine6_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; -reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine6_auto_precharge = 1'd0; -wire litedramcore_bankmachine6_sink_valid; -wire litedramcore_bankmachine6_sink_ready; -reg litedramcore_bankmachine6_sink_first = 1'd0; -reg litedramcore_bankmachine6_sink_last = 1'd0; -wire litedramcore_bankmachine6_sink_payload_we; -wire [21:0] litedramcore_bankmachine6_sink_payload_addr; -wire litedramcore_bankmachine6_source_valid; -wire litedramcore_bankmachine6_source_ready; -wire litedramcore_bankmachine6_source_first; -wire litedramcore_bankmachine6_source_last; -wire litedramcore_bankmachine6_source_payload_we; -wire [21:0] litedramcore_bankmachine6_source_payload_addr; -wire litedramcore_bankmachine6_syncfifo6_we; -wire litedramcore_bankmachine6_syncfifo6_writable; -wire litedramcore_bankmachine6_syncfifo6_re; -wire litedramcore_bankmachine6_syncfifo6_readable; -wire [24:0] litedramcore_bankmachine6_syncfifo6_din; -wire [24:0] litedramcore_bankmachine6_syncfifo6_dout; -reg [4:0] litedramcore_bankmachine6_level = 5'd0; -reg litedramcore_bankmachine6_replace = 1'd0; -reg [3:0] litedramcore_bankmachine6_produce = 4'd0; -reg [3:0] litedramcore_bankmachine6_consume = 4'd0; -reg [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine6_wrport_dat_r; -wire litedramcore_bankmachine6_wrport_we; -wire [24:0] litedramcore_bankmachine6_wrport_dat_w; -wire litedramcore_bankmachine6_do_read; -wire [3:0] litedramcore_bankmachine6_rdport_adr; -wire [24:0] litedramcore_bankmachine6_rdport_dat_r; -wire litedramcore_bankmachine6_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine6_fifo_in_payload_addr; -wire litedramcore_bankmachine6_fifo_in_first; -wire litedramcore_bankmachine6_fifo_in_last; -wire litedramcore_bankmachine6_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine6_fifo_out_payload_addr; -wire litedramcore_bankmachine6_fifo_out_first; -wire litedramcore_bankmachine6_fifo_out_last; -wire litedramcore_bankmachine6_sink_sink_valid; -wire litedramcore_bankmachine6_sink_sink_ready; -wire litedramcore_bankmachine6_sink_sink_first; -wire litedramcore_bankmachine6_sink_sink_last; -wire litedramcore_bankmachine6_sink_sink_payload_we; -wire [21:0] litedramcore_bankmachine6_sink_sink_payload_addr; -wire litedramcore_bankmachine6_source_source_valid; -wire litedramcore_bankmachine6_source_source_ready; -wire litedramcore_bankmachine6_source_source_first; -wire litedramcore_bankmachine6_source_source_last; -wire litedramcore_bankmachine6_source_source_payload_we; -wire [21:0] litedramcore_bankmachine6_source_source_payload_addr; -wire litedramcore_bankmachine6_pipe_valid_sink_valid; -wire litedramcore_bankmachine6_pipe_valid_sink_ready; -wire litedramcore_bankmachine6_pipe_valid_sink_first; -wire litedramcore_bankmachine6_pipe_valid_sink_last; -wire litedramcore_bankmachine6_pipe_valid_sink_payload_we; -wire [21:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine6_pipe_valid_source_ready; -reg litedramcore_bankmachine6_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine6_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine6_row = 15'd0; -reg litedramcore_bankmachine6_row_opened = 1'd0; -wire litedramcore_bankmachine6_row_hit; -reg litedramcore_bankmachine6_row_open = 1'd0; -reg litedramcore_bankmachine6_row_close = 1'd0; -reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine6_twtpcon_valid; +reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine5_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine5_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine5_wrport_dat_r; +wire [24:0] main_litedramcore_bankmachine5_wrport_dat_w; +wire main_litedramcore_bankmachine5_wrport_we; +reg main_litedramcore_bankmachine6_auto_precharge = 1'd0; +reg [14:0] main_litedramcore_bankmachine6_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba; +reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine6_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine6_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine6_consume = 4'd0; +wire main_litedramcore_bankmachine6_do_read; +wire main_litedramcore_bankmachine6_fifo_in_first; +wire main_litedramcore_bankmachine6_fifo_in_last; +wire [21:0] main_litedramcore_bankmachine6_fifo_in_payload_addr; +wire main_litedramcore_bankmachine6_fifo_in_payload_we; +wire main_litedramcore_bankmachine6_fifo_out_first; +wire main_litedramcore_bankmachine6_fifo_out_last; +wire [21:0] main_litedramcore_bankmachine6_fifo_out_payload_addr; +wire main_litedramcore_bankmachine6_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine6_level = 5'd0; +wire main_litedramcore_bankmachine6_pipe_valid_sink_first; +wire main_litedramcore_bankmachine6_pipe_valid_sink_last; +wire [21:0] main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine6_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine6_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine6_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine6_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine6_pipe_valid_source_last = 1'd0; +reg [21:0] main_litedramcore_bankmachine6_pipe_valid_source_payload_addr = 22'd0; +reg main_litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine6_pipe_valid_source_ready; +reg main_litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine6_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine6_rdport_adr; +wire [24:0] main_litedramcore_bankmachine6_rdport_dat_r; +reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine6_refresh_req; +reg main_litedramcore_bankmachine6_replace = 1'd0; +wire [21:0] main_litedramcore_bankmachine6_req_addr; +wire main_litedramcore_bankmachine6_req_lock; +reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine6_req_ready; +wire main_litedramcore_bankmachine6_req_valid; +reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine6_req_we; +reg [14:0] main_litedramcore_bankmachine6_row = 15'd0; +reg main_litedramcore_bankmachine6_row_close = 1'd0; +reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine6_row_hit; +reg main_litedramcore_bankmachine6_row_open = 1'd0; +reg main_litedramcore_bankmachine6_row_opened = 1'd0; +reg main_litedramcore_bankmachine6_sink_first = 1'd0; +reg main_litedramcore_bankmachine6_sink_last = 1'd0; +wire [21:0] main_litedramcore_bankmachine6_sink_payload_addr; +wire main_litedramcore_bankmachine6_sink_payload_we; +wire main_litedramcore_bankmachine6_sink_ready; +wire main_litedramcore_bankmachine6_sink_sink_first; +wire main_litedramcore_bankmachine6_sink_sink_last; +wire [21:0] main_litedramcore_bankmachine6_sink_sink_payload_addr; +wire main_litedramcore_bankmachine6_sink_sink_payload_we; +wire main_litedramcore_bankmachine6_sink_sink_ready; +wire main_litedramcore_bankmachine6_sink_sink_valid; +wire main_litedramcore_bankmachine6_sink_valid; +wire main_litedramcore_bankmachine6_source_first; +wire main_litedramcore_bankmachine6_source_last; +wire [21:0] main_litedramcore_bankmachine6_source_payload_addr; +wire main_litedramcore_bankmachine6_source_payload_we; +wire main_litedramcore_bankmachine6_source_ready; +wire main_litedramcore_bankmachine6_source_source_first; +wire main_litedramcore_bankmachine6_source_source_last; +wire [21:0] main_litedramcore_bankmachine6_source_source_payload_addr; +wire main_litedramcore_bankmachine6_source_source_payload_we; +wire main_litedramcore_bankmachine6_source_source_ready; +wire main_litedramcore_bankmachine6_source_source_valid; +wire main_litedramcore_bankmachine6_source_valid; +wire [24:0] main_litedramcore_bankmachine6_syncfifo6_din; +wire [24:0] main_litedramcore_bankmachine6_syncfifo6_dout; +wire main_litedramcore_bankmachine6_syncfifo6_re; +wire main_litedramcore_bankmachine6_syncfifo6_readable; +wire main_litedramcore_bankmachine6_syncfifo6_we; +wire main_litedramcore_bankmachine6_syncfifo6_writable; +reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; -wire litedramcore_bankmachine6_trccon_valid; +reg main_litedramcore_bankmachine6_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine6_trascon_valid; +reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0; -wire litedramcore_bankmachine6_trascon_valid; +reg main_litedramcore_bankmachine6_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine6_trccon_valid; +reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine6_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0; -wire litedramcore_bankmachine7_req_valid; -wire litedramcore_bankmachine7_req_ready; -wire litedramcore_bankmachine7_req_we; -wire [21:0] litedramcore_bankmachine7_req_addr; -wire litedramcore_bankmachine7_req_lock; -reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine7_refresh_req; -reg litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg litedramcore_bankmachine7_cmd_valid = 1'd0; -reg litedramcore_bankmachine7_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; -reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine7_auto_precharge = 1'd0; -wire litedramcore_bankmachine7_sink_valid; -wire litedramcore_bankmachine7_sink_ready; -reg litedramcore_bankmachine7_sink_first = 1'd0; -reg litedramcore_bankmachine7_sink_last = 1'd0; -wire litedramcore_bankmachine7_sink_payload_we; -wire [21:0] litedramcore_bankmachine7_sink_payload_addr; -wire litedramcore_bankmachine7_source_valid; -wire litedramcore_bankmachine7_source_ready; -wire litedramcore_bankmachine7_source_first; -wire litedramcore_bankmachine7_source_last; -wire litedramcore_bankmachine7_source_payload_we; -wire [21:0] litedramcore_bankmachine7_source_payload_addr; -wire litedramcore_bankmachine7_syncfifo7_we; -wire litedramcore_bankmachine7_syncfifo7_writable; -wire litedramcore_bankmachine7_syncfifo7_re; -wire litedramcore_bankmachine7_syncfifo7_readable; -wire [24:0] litedramcore_bankmachine7_syncfifo7_din; -wire [24:0] litedramcore_bankmachine7_syncfifo7_dout; -reg [4:0] litedramcore_bankmachine7_level = 5'd0; -reg litedramcore_bankmachine7_replace = 1'd0; -reg [3:0] litedramcore_bankmachine7_produce = 4'd0; -reg [3:0] litedramcore_bankmachine7_consume = 4'd0; -reg [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine7_wrport_dat_r; -wire litedramcore_bankmachine7_wrport_we; -wire [24:0] litedramcore_bankmachine7_wrport_dat_w; -wire litedramcore_bankmachine7_do_read; -wire [3:0] litedramcore_bankmachine7_rdport_adr; -wire [24:0] litedramcore_bankmachine7_rdport_dat_r; -wire litedramcore_bankmachine7_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine7_fifo_in_payload_addr; -wire litedramcore_bankmachine7_fifo_in_first; -wire litedramcore_bankmachine7_fifo_in_last; -wire litedramcore_bankmachine7_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine7_fifo_out_payload_addr; -wire litedramcore_bankmachine7_fifo_out_first; -wire litedramcore_bankmachine7_fifo_out_last; -wire litedramcore_bankmachine7_sink_sink_valid; -wire litedramcore_bankmachine7_sink_sink_ready; -wire litedramcore_bankmachine7_sink_sink_first; -wire litedramcore_bankmachine7_sink_sink_last; -wire litedramcore_bankmachine7_sink_sink_payload_we; -wire [21:0] litedramcore_bankmachine7_sink_sink_payload_addr; -wire litedramcore_bankmachine7_source_source_valid; -wire litedramcore_bankmachine7_source_source_ready; -wire litedramcore_bankmachine7_source_source_first; -wire litedramcore_bankmachine7_source_source_last; -wire litedramcore_bankmachine7_source_source_payload_we; -wire [21:0] litedramcore_bankmachine7_source_source_payload_addr; -wire litedramcore_bankmachine7_pipe_valid_sink_valid; -wire litedramcore_bankmachine7_pipe_valid_sink_ready; -wire litedramcore_bankmachine7_pipe_valid_sink_first; -wire litedramcore_bankmachine7_pipe_valid_sink_last; -wire litedramcore_bankmachine7_pipe_valid_sink_payload_we; -wire [21:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine7_pipe_valid_source_ready; -reg litedramcore_bankmachine7_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine7_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine7_row = 15'd0; -reg litedramcore_bankmachine7_row_opened = 1'd0; -wire litedramcore_bankmachine7_row_hit; -reg litedramcore_bankmachine7_row_open = 1'd0; -reg litedramcore_bankmachine7_row_close = 1'd0; -reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine7_twtpcon_valid; +reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine6_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine6_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine6_wrport_dat_r; +wire [24:0] main_litedramcore_bankmachine6_wrport_dat_w; +wire main_litedramcore_bankmachine6_wrport_we; +reg main_litedramcore_bankmachine7_auto_precharge = 1'd0; +reg [14:0] main_litedramcore_bankmachine7_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba; +reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine7_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine7_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine7_consume = 4'd0; +wire main_litedramcore_bankmachine7_do_read; +wire main_litedramcore_bankmachine7_fifo_in_first; +wire main_litedramcore_bankmachine7_fifo_in_last; +wire [21:0] main_litedramcore_bankmachine7_fifo_in_payload_addr; +wire main_litedramcore_bankmachine7_fifo_in_payload_we; +wire main_litedramcore_bankmachine7_fifo_out_first; +wire main_litedramcore_bankmachine7_fifo_out_last; +wire [21:0] main_litedramcore_bankmachine7_fifo_out_payload_addr; +wire main_litedramcore_bankmachine7_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine7_level = 5'd0; +wire main_litedramcore_bankmachine7_pipe_valid_sink_first; +wire main_litedramcore_bankmachine7_pipe_valid_sink_last; +wire [21:0] main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine7_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine7_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine7_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine7_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine7_pipe_valid_source_last = 1'd0; +reg [21:0] main_litedramcore_bankmachine7_pipe_valid_source_payload_addr = 22'd0; +reg main_litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine7_pipe_valid_source_ready; +reg main_litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine7_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine7_rdport_adr; +wire [24:0] main_litedramcore_bankmachine7_rdport_dat_r; +reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine7_refresh_req; +reg main_litedramcore_bankmachine7_replace = 1'd0; +wire [21:0] main_litedramcore_bankmachine7_req_addr; +wire main_litedramcore_bankmachine7_req_lock; +reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine7_req_ready; +wire main_litedramcore_bankmachine7_req_valid; +reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine7_req_we; +reg [14:0] main_litedramcore_bankmachine7_row = 15'd0; +reg main_litedramcore_bankmachine7_row_close = 1'd0; +reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine7_row_hit; +reg main_litedramcore_bankmachine7_row_open = 1'd0; +reg main_litedramcore_bankmachine7_row_opened = 1'd0; +reg main_litedramcore_bankmachine7_sink_first = 1'd0; +reg main_litedramcore_bankmachine7_sink_last = 1'd0; +wire [21:0] main_litedramcore_bankmachine7_sink_payload_addr; +wire main_litedramcore_bankmachine7_sink_payload_we; +wire main_litedramcore_bankmachine7_sink_ready; +wire main_litedramcore_bankmachine7_sink_sink_first; +wire main_litedramcore_bankmachine7_sink_sink_last; +wire [21:0] main_litedramcore_bankmachine7_sink_sink_payload_addr; +wire main_litedramcore_bankmachine7_sink_sink_payload_we; +wire main_litedramcore_bankmachine7_sink_sink_ready; +wire main_litedramcore_bankmachine7_sink_sink_valid; +wire main_litedramcore_bankmachine7_sink_valid; +wire main_litedramcore_bankmachine7_source_first; +wire main_litedramcore_bankmachine7_source_last; +wire [21:0] main_litedramcore_bankmachine7_source_payload_addr; +wire main_litedramcore_bankmachine7_source_payload_we; +wire main_litedramcore_bankmachine7_source_ready; +wire main_litedramcore_bankmachine7_source_source_first; +wire main_litedramcore_bankmachine7_source_source_last; +wire [21:0] main_litedramcore_bankmachine7_source_source_payload_addr; +wire main_litedramcore_bankmachine7_source_source_payload_we; +wire main_litedramcore_bankmachine7_source_source_ready; +wire main_litedramcore_bankmachine7_source_source_valid; +wire main_litedramcore_bankmachine7_source_valid; +wire [24:0] main_litedramcore_bankmachine7_syncfifo7_din; +wire [24:0] main_litedramcore_bankmachine7_syncfifo7_dout; +wire main_litedramcore_bankmachine7_syncfifo7_re; +wire main_litedramcore_bankmachine7_syncfifo7_readable; +wire main_litedramcore_bankmachine7_syncfifo7_we; +wire main_litedramcore_bankmachine7_syncfifo7_writable; +reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; -wire litedramcore_bankmachine7_trccon_valid; +reg main_litedramcore_bankmachine7_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine7_trascon_valid; +reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0; -wire litedramcore_bankmachine7_trascon_valid; +reg main_litedramcore_bankmachine7_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine7_trccon_valid; +reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine7_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0; -wire litedramcore_ras_allowed; -wire litedramcore_cas_allowed; -wire [1:0] litedramcore_rdcmdphase; -wire [1:0] litedramcore_wrcmdphase; -reg litedramcore_choose_cmd_want_reads = 1'd0; -reg litedramcore_choose_cmd_want_writes = 1'd0; -reg litedramcore_choose_cmd_want_cmds = 1'd0; -reg litedramcore_choose_cmd_want_activates = 1'd0; -wire litedramcore_choose_cmd_cmd_valid; -reg litedramcore_choose_cmd_cmd_ready = 1'd0; -wire [14:0] litedramcore_choose_cmd_cmd_payload_a; -wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; -reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; -wire litedramcore_choose_cmd_cmd_payload_is_cmd; -wire litedramcore_choose_cmd_cmd_payload_is_read; -wire litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] litedramcore_choose_cmd_valids = 8'd0; -wire [7:0] litedramcore_choose_cmd_request; -reg [2:0] litedramcore_choose_cmd_grant = 3'd0; -wire litedramcore_choose_cmd_ce; -reg litedramcore_choose_req_want_reads = 1'd0; -reg litedramcore_choose_req_want_writes = 1'd0; -reg litedramcore_choose_req_want_cmds = 1'd0; -reg litedramcore_choose_req_want_activates = 1'd0; -wire litedramcore_choose_req_cmd_valid; -reg litedramcore_choose_req_cmd_ready = 1'd0; -wire [14:0] litedramcore_choose_req_cmd_payload_a; -wire [2:0] litedramcore_choose_req_cmd_payload_ba; -reg litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg litedramcore_choose_req_cmd_payload_we = 1'd0; -wire litedramcore_choose_req_cmd_payload_is_cmd; -wire litedramcore_choose_req_cmd_payload_is_read; -wire litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] litedramcore_choose_req_valids = 8'd0; -wire [7:0] litedramcore_choose_req_request; -reg [2:0] litedramcore_choose_req_grant = 3'd0; -wire litedramcore_choose_req_ce; -reg [14:0] litedramcore_nop_a = 15'd0; -reg [2:0] litedramcore_nop_ba = 3'd0; -reg [1:0] litedramcore_steerer_sel0 = 2'd0; -reg [1:0] litedramcore_steerer_sel1 = 2'd0; -reg [1:0] litedramcore_steerer_sel2 = 2'd0; -reg [1:0] litedramcore_steerer_sel3 = 2'd0; -reg litedramcore_steerer0 = 1'd1; -reg litedramcore_steerer1 = 1'd1; -reg litedramcore_steerer2 = 1'd1; -reg litedramcore_steerer3 = 1'd1; -reg litedramcore_steerer4 = 1'd1; -reg litedramcore_steerer5 = 1'd1; -reg litedramcore_steerer6 = 1'd1; -reg litedramcore_steerer7 = 1'd1; -wire litedramcore_trrdcon_valid; +reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine7_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine7_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine7_wrport_dat_r; +wire [24:0] main_litedramcore_bankmachine7_wrport_dat_w; +wire main_litedramcore_bankmachine7_wrport_we; +wire main_litedramcore_cas_allowed; +wire main_litedramcore_choose_cmd_ce; +wire [14:0] main_litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba; +reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +wire main_litedramcore_choose_cmd_cmd_payload_is_cmd; +wire main_litedramcore_choose_cmd_cmd_payload_is_read; +wire main_litedramcore_choose_cmd_cmd_payload_is_write; +reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0; +reg main_litedramcore_choose_cmd_cmd_ready = 1'd0; +wire main_litedramcore_choose_cmd_cmd_valid; +reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0; +wire [7:0] main_litedramcore_choose_cmd_request; +reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0; +reg main_litedramcore_choose_cmd_want_activates = 1'd0; +reg main_litedramcore_choose_cmd_want_cmds = 1'd0; +reg main_litedramcore_choose_cmd_want_reads = 1'd0; +reg main_litedramcore_choose_cmd_want_writes = 1'd0; +wire main_litedramcore_choose_req_ce; +wire [14:0] main_litedramcore_choose_req_cmd_payload_a; +wire [2:0] main_litedramcore_choose_req_cmd_payload_ba; +reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0; +wire main_litedramcore_choose_req_cmd_payload_is_cmd; +wire main_litedramcore_choose_req_cmd_payload_is_read; +wire main_litedramcore_choose_req_cmd_payload_is_write; +reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_we = 1'd0; +reg main_litedramcore_choose_req_cmd_ready = 1'd0; +wire main_litedramcore_choose_req_cmd_valid; +reg [2:0] main_litedramcore_choose_req_grant = 3'd0; +wire [7:0] main_litedramcore_choose_req_request; +reg [7:0] main_litedramcore_choose_req_valids = 8'd0; +reg main_litedramcore_choose_req_want_activates = 1'd0; +reg main_litedramcore_choose_req_want_cmds = 1'd0; +reg main_litedramcore_choose_req_want_reads = 1'd0; +reg main_litedramcore_choose_req_want_writes = 1'd0; +wire main_litedramcore_cke; +reg main_litedramcore_cmd_last = 1'd0; +reg [14:0] main_litedramcore_cmd_payload_a = 15'd0; +reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0; +reg main_litedramcore_cmd_payload_cas = 1'd0; +reg main_litedramcore_cmd_payload_is_read = 1'd0; +reg main_litedramcore_cmd_payload_is_write = 1'd0; +reg main_litedramcore_cmd_payload_ras = 1'd0; +reg main_litedramcore_cmd_payload_we = 1'd0; +reg main_litedramcore_cmd_ready = 1'd0; +reg main_litedramcore_cmd_valid = 1'd0; +reg main_litedramcore_csr_dfi_p0_act_n = 1'd1; +wire [14:0] main_litedramcore_csr_dfi_p0_address; +wire [2:0] main_litedramcore_csr_dfi_p0_bank; +reg main_litedramcore_csr_dfi_p0_cas_n = 1'd1; +reg main_litedramcore_csr_dfi_p0_cke = 1'd0; +reg main_litedramcore_csr_dfi_p0_cs_n = 1'd1; +reg main_litedramcore_csr_dfi_p0_odt = 1'd0; +reg main_litedramcore_csr_dfi_p0_ras_n = 1'd1; +reg [63:0] main_litedramcore_csr_dfi_p0_rddata = 64'd0; +wire main_litedramcore_csr_dfi_p0_rddata_en; +reg main_litedramcore_csr_dfi_p0_rddata_valid = 1'd0; +wire main_litedramcore_csr_dfi_p0_reset_n; +reg main_litedramcore_csr_dfi_p0_we_n = 1'd1; +wire [63:0] main_litedramcore_csr_dfi_p0_wrdata; +wire main_litedramcore_csr_dfi_p0_wrdata_en; +wire [7:0] main_litedramcore_csr_dfi_p0_wrdata_mask; +reg main_litedramcore_csr_dfi_p1_act_n = 1'd1; +wire [14:0] main_litedramcore_csr_dfi_p1_address; +wire [2:0] main_litedramcore_csr_dfi_p1_bank; +reg main_litedramcore_csr_dfi_p1_cas_n = 1'd1; +reg main_litedramcore_csr_dfi_p1_cke = 1'd0; +reg main_litedramcore_csr_dfi_p1_cs_n = 1'd1; +reg main_litedramcore_csr_dfi_p1_odt = 1'd0; +reg main_litedramcore_csr_dfi_p1_ras_n = 1'd1; +reg [63:0] main_litedramcore_csr_dfi_p1_rddata = 64'd0; +wire main_litedramcore_csr_dfi_p1_rddata_en; +reg main_litedramcore_csr_dfi_p1_rddata_valid = 1'd0; +wire main_litedramcore_csr_dfi_p1_reset_n; +reg main_litedramcore_csr_dfi_p1_we_n = 1'd1; +wire [63:0] main_litedramcore_csr_dfi_p1_wrdata; +wire main_litedramcore_csr_dfi_p1_wrdata_en; +wire [7:0] main_litedramcore_csr_dfi_p1_wrdata_mask; +reg main_litedramcore_csr_dfi_p2_act_n = 1'd1; +wire [14:0] main_litedramcore_csr_dfi_p2_address; +wire [2:0] main_litedramcore_csr_dfi_p2_bank; +reg main_litedramcore_csr_dfi_p2_cas_n = 1'd1; +reg main_litedramcore_csr_dfi_p2_cke = 1'd0; +reg main_litedramcore_csr_dfi_p2_cs_n = 1'd1; +reg main_litedramcore_csr_dfi_p2_odt = 1'd0; +reg main_litedramcore_csr_dfi_p2_ras_n = 1'd1; +reg [63:0] main_litedramcore_csr_dfi_p2_rddata = 64'd0; +wire main_litedramcore_csr_dfi_p2_rddata_en; +reg main_litedramcore_csr_dfi_p2_rddata_valid = 1'd0; +wire main_litedramcore_csr_dfi_p2_reset_n; +reg main_litedramcore_csr_dfi_p2_we_n = 1'd1; +wire [63:0] main_litedramcore_csr_dfi_p2_wrdata; +wire main_litedramcore_csr_dfi_p2_wrdata_en; +wire [7:0] main_litedramcore_csr_dfi_p2_wrdata_mask; +reg main_litedramcore_csr_dfi_p3_act_n = 1'd1; +wire [14:0] main_litedramcore_csr_dfi_p3_address; +wire [2:0] main_litedramcore_csr_dfi_p3_bank; +reg main_litedramcore_csr_dfi_p3_cas_n = 1'd1; +reg main_litedramcore_csr_dfi_p3_cke = 1'd0; +reg main_litedramcore_csr_dfi_p3_cs_n = 1'd1; +reg main_litedramcore_csr_dfi_p3_odt = 1'd0; +reg main_litedramcore_csr_dfi_p3_ras_n = 1'd1; +reg [63:0] main_litedramcore_csr_dfi_p3_rddata = 64'd0; +wire main_litedramcore_csr_dfi_p3_rddata_en; +reg main_litedramcore_csr_dfi_p3_rddata_valid = 1'd0; +wire main_litedramcore_csr_dfi_p3_reset_n; +reg main_litedramcore_csr_dfi_p3_we_n = 1'd1; +wire [63:0] main_litedramcore_csr_dfi_p3_wrdata; +wire main_litedramcore_csr_dfi_p3_wrdata_en; +wire [7:0] main_litedramcore_csr_dfi_p3_wrdata_mask; +reg main_litedramcore_dfi_p0_act_n = 1'd1; +reg [14:0] main_litedramcore_dfi_p0_address = 15'd0; +reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0; +reg main_litedramcore_dfi_p0_cas_n = 1'd1; +wire main_litedramcore_dfi_p0_cke; +reg main_litedramcore_dfi_p0_cs_n = 1'd1; +wire main_litedramcore_dfi_p0_odt; +reg main_litedramcore_dfi_p0_ras_n = 1'd1; +wire [63:0] main_litedramcore_dfi_p0_rddata; +reg main_litedramcore_dfi_p0_rddata_en = 1'd0; +wire main_litedramcore_dfi_p0_rddata_valid; +wire main_litedramcore_dfi_p0_reset_n; +reg main_litedramcore_dfi_p0_we_n = 1'd1; +wire [63:0] main_litedramcore_dfi_p0_wrdata; +reg main_litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [7:0] main_litedramcore_dfi_p0_wrdata_mask; +reg main_litedramcore_dfi_p1_act_n = 1'd1; +reg [14:0] main_litedramcore_dfi_p1_address = 15'd0; +reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0; +reg main_litedramcore_dfi_p1_cas_n = 1'd1; +wire main_litedramcore_dfi_p1_cke; +reg main_litedramcore_dfi_p1_cs_n = 1'd1; +wire main_litedramcore_dfi_p1_odt; +reg main_litedramcore_dfi_p1_ras_n = 1'd1; +wire [63:0] main_litedramcore_dfi_p1_rddata; +reg main_litedramcore_dfi_p1_rddata_en = 1'd0; +wire main_litedramcore_dfi_p1_rddata_valid; +wire main_litedramcore_dfi_p1_reset_n; +reg main_litedramcore_dfi_p1_we_n = 1'd1; +wire [63:0] main_litedramcore_dfi_p1_wrdata; +reg main_litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [7:0] main_litedramcore_dfi_p1_wrdata_mask; +reg main_litedramcore_dfi_p2_act_n = 1'd1; +reg [14:0] main_litedramcore_dfi_p2_address = 15'd0; +reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0; +reg main_litedramcore_dfi_p2_cas_n = 1'd1; +wire main_litedramcore_dfi_p2_cke; +reg main_litedramcore_dfi_p2_cs_n = 1'd1; +wire main_litedramcore_dfi_p2_odt; +reg main_litedramcore_dfi_p2_ras_n = 1'd1; +wire [63:0] main_litedramcore_dfi_p2_rddata; +reg main_litedramcore_dfi_p2_rddata_en = 1'd0; +wire main_litedramcore_dfi_p2_rddata_valid; +wire main_litedramcore_dfi_p2_reset_n; +reg main_litedramcore_dfi_p2_we_n = 1'd1; +wire [63:0] main_litedramcore_dfi_p2_wrdata; +reg main_litedramcore_dfi_p2_wrdata_en = 1'd0; +wire [7:0] main_litedramcore_dfi_p2_wrdata_mask; +reg main_litedramcore_dfi_p3_act_n = 1'd1; +reg [14:0] main_litedramcore_dfi_p3_address = 15'd0; +reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0; +reg main_litedramcore_dfi_p3_cas_n = 1'd1; +wire main_litedramcore_dfi_p3_cke; +reg main_litedramcore_dfi_p3_cs_n = 1'd1; +wire main_litedramcore_dfi_p3_odt; +reg main_litedramcore_dfi_p3_ras_n = 1'd1; +wire [63:0] main_litedramcore_dfi_p3_rddata; +reg main_litedramcore_dfi_p3_rddata_en = 1'd0; +wire main_litedramcore_dfi_p3_rddata_valid; +wire main_litedramcore_dfi_p3_reset_n; +reg main_litedramcore_dfi_p3_we_n = 1'd1; +wire [63:0] main_litedramcore_dfi_p3_wrdata; +reg main_litedramcore_dfi_p3_wrdata_en = 1'd0; +wire [7:0] main_litedramcore_dfi_p3_wrdata_mask; +reg main_litedramcore_en0 = 1'd0; +reg main_litedramcore_en1 = 1'd0; +reg main_litedramcore_ext_dfi_p0_act_n = 1'd1; +reg [14:0] main_litedramcore_ext_dfi_p0_address = 15'd0; +reg [2:0] main_litedramcore_ext_dfi_p0_bank = 3'd0; +reg main_litedramcore_ext_dfi_p0_cas_n = 1'd1; +reg main_litedramcore_ext_dfi_p0_cke = 1'd0; +reg main_litedramcore_ext_dfi_p0_cs_n = 1'd1; +reg main_litedramcore_ext_dfi_p0_odt = 1'd0; +reg main_litedramcore_ext_dfi_p0_ras_n = 1'd1; +reg [63:0] main_litedramcore_ext_dfi_p0_rddata = 64'd0; +reg main_litedramcore_ext_dfi_p0_rddata_en = 1'd0; +reg main_litedramcore_ext_dfi_p0_rddata_valid = 1'd0; +reg main_litedramcore_ext_dfi_p0_reset_n = 1'd0; +reg main_litedramcore_ext_dfi_p0_we_n = 1'd1; +reg [63:0] main_litedramcore_ext_dfi_p0_wrdata = 64'd0; +reg main_litedramcore_ext_dfi_p0_wrdata_en = 1'd0; +reg [7:0] main_litedramcore_ext_dfi_p0_wrdata_mask = 8'd0; +reg main_litedramcore_ext_dfi_p1_act_n = 1'd1; +reg [14:0] main_litedramcore_ext_dfi_p1_address = 15'd0; +reg [2:0] main_litedramcore_ext_dfi_p1_bank = 3'd0; +reg main_litedramcore_ext_dfi_p1_cas_n = 1'd1; +reg main_litedramcore_ext_dfi_p1_cke = 1'd0; +reg main_litedramcore_ext_dfi_p1_cs_n = 1'd1; +reg main_litedramcore_ext_dfi_p1_odt = 1'd0; +reg main_litedramcore_ext_dfi_p1_ras_n = 1'd1; +reg [63:0] main_litedramcore_ext_dfi_p1_rddata = 64'd0; +reg main_litedramcore_ext_dfi_p1_rddata_en = 1'd0; +reg main_litedramcore_ext_dfi_p1_rddata_valid = 1'd0; +reg main_litedramcore_ext_dfi_p1_reset_n = 1'd0; +reg main_litedramcore_ext_dfi_p1_we_n = 1'd1; +reg [63:0] main_litedramcore_ext_dfi_p1_wrdata = 64'd0; +reg main_litedramcore_ext_dfi_p1_wrdata_en = 1'd0; +reg [7:0] main_litedramcore_ext_dfi_p1_wrdata_mask = 8'd0; +reg main_litedramcore_ext_dfi_p2_act_n = 1'd1; +reg [14:0] main_litedramcore_ext_dfi_p2_address = 15'd0; +reg [2:0] main_litedramcore_ext_dfi_p2_bank = 3'd0; +reg main_litedramcore_ext_dfi_p2_cas_n = 1'd1; +reg main_litedramcore_ext_dfi_p2_cke = 1'd0; +reg main_litedramcore_ext_dfi_p2_cs_n = 1'd1; +reg main_litedramcore_ext_dfi_p2_odt = 1'd0; +reg main_litedramcore_ext_dfi_p2_ras_n = 1'd1; +reg [63:0] main_litedramcore_ext_dfi_p2_rddata = 64'd0; +reg main_litedramcore_ext_dfi_p2_rddata_en = 1'd0; +reg main_litedramcore_ext_dfi_p2_rddata_valid = 1'd0; +reg main_litedramcore_ext_dfi_p2_reset_n = 1'd0; +reg main_litedramcore_ext_dfi_p2_we_n = 1'd1; +reg [63:0] main_litedramcore_ext_dfi_p2_wrdata = 64'd0; +reg main_litedramcore_ext_dfi_p2_wrdata_en = 1'd0; +reg [7:0] main_litedramcore_ext_dfi_p2_wrdata_mask = 8'd0; +reg main_litedramcore_ext_dfi_p3_act_n = 1'd1; +reg [14:0] main_litedramcore_ext_dfi_p3_address = 15'd0; +reg [2:0] main_litedramcore_ext_dfi_p3_bank = 3'd0; +reg main_litedramcore_ext_dfi_p3_cas_n = 1'd1; +reg main_litedramcore_ext_dfi_p3_cke = 1'd0; +reg main_litedramcore_ext_dfi_p3_cs_n = 1'd1; +reg main_litedramcore_ext_dfi_p3_odt = 1'd0; +reg main_litedramcore_ext_dfi_p3_ras_n = 1'd1; +reg [63:0] main_litedramcore_ext_dfi_p3_rddata = 64'd0; +reg main_litedramcore_ext_dfi_p3_rddata_en = 1'd0; +reg main_litedramcore_ext_dfi_p3_rddata_valid = 1'd0; +reg main_litedramcore_ext_dfi_p3_reset_n = 1'd0; +reg main_litedramcore_ext_dfi_p3_we_n = 1'd1; +reg [63:0] main_litedramcore_ext_dfi_p3_wrdata = 64'd0; +reg main_litedramcore_ext_dfi_p3_wrdata_en = 1'd0; +reg [7:0] main_litedramcore_ext_dfi_p3_wrdata_mask = 8'd0; +reg main_litedramcore_ext_dfi_sel = 1'd0; +wire main_litedramcore_go_to_refresh; +wire [21:0] main_litedramcore_interface_bank0_addr; +wire main_litedramcore_interface_bank0_lock; +wire main_litedramcore_interface_bank0_rdata_valid; +wire main_litedramcore_interface_bank0_ready; +wire main_litedramcore_interface_bank0_valid; +wire main_litedramcore_interface_bank0_wdata_ready; +wire main_litedramcore_interface_bank0_we; +wire [21:0] main_litedramcore_interface_bank1_addr; +wire main_litedramcore_interface_bank1_lock; +wire main_litedramcore_interface_bank1_rdata_valid; +wire main_litedramcore_interface_bank1_ready; +wire main_litedramcore_interface_bank1_valid; +wire main_litedramcore_interface_bank1_wdata_ready; +wire main_litedramcore_interface_bank1_we; +wire [21:0] main_litedramcore_interface_bank2_addr; +wire main_litedramcore_interface_bank2_lock; +wire main_litedramcore_interface_bank2_rdata_valid; +wire main_litedramcore_interface_bank2_ready; +wire main_litedramcore_interface_bank2_valid; +wire main_litedramcore_interface_bank2_wdata_ready; +wire main_litedramcore_interface_bank2_we; +wire [21:0] main_litedramcore_interface_bank3_addr; +wire main_litedramcore_interface_bank3_lock; +wire main_litedramcore_interface_bank3_rdata_valid; +wire main_litedramcore_interface_bank3_ready; +wire main_litedramcore_interface_bank3_valid; +wire main_litedramcore_interface_bank3_wdata_ready; +wire main_litedramcore_interface_bank3_we; +wire [21:0] main_litedramcore_interface_bank4_addr; +wire main_litedramcore_interface_bank4_lock; +wire main_litedramcore_interface_bank4_rdata_valid; +wire main_litedramcore_interface_bank4_ready; +wire main_litedramcore_interface_bank4_valid; +wire main_litedramcore_interface_bank4_wdata_ready; +wire main_litedramcore_interface_bank4_we; +wire [21:0] main_litedramcore_interface_bank5_addr; +wire main_litedramcore_interface_bank5_lock; +wire main_litedramcore_interface_bank5_rdata_valid; +wire main_litedramcore_interface_bank5_ready; +wire main_litedramcore_interface_bank5_valid; +wire main_litedramcore_interface_bank5_wdata_ready; +wire main_litedramcore_interface_bank5_we; +wire [21:0] main_litedramcore_interface_bank6_addr; +wire main_litedramcore_interface_bank6_lock; +wire main_litedramcore_interface_bank6_rdata_valid; +wire main_litedramcore_interface_bank6_ready; +wire main_litedramcore_interface_bank6_valid; +wire main_litedramcore_interface_bank6_wdata_ready; +wire main_litedramcore_interface_bank6_we; +wire [21:0] main_litedramcore_interface_bank7_addr; +wire main_litedramcore_interface_bank7_lock; +wire main_litedramcore_interface_bank7_rdata_valid; +wire main_litedramcore_interface_bank7_ready; +wire main_litedramcore_interface_bank7_valid; +wire main_litedramcore_interface_bank7_wdata_ready; +wire main_litedramcore_interface_bank7_we; +wire [255:0] main_litedramcore_interface_rdata; +reg [255:0] main_litedramcore_interface_wdata = 256'd0; +reg [31:0] main_litedramcore_interface_wdata_we = 32'd0; +reg main_litedramcore_master_p0_act_n = 1'd1; +reg [14:0] main_litedramcore_master_p0_address = 15'd0; +reg [2:0] main_litedramcore_master_p0_bank = 3'd0; +reg main_litedramcore_master_p0_cas_n = 1'd1; +reg main_litedramcore_master_p0_cke = 1'd0; +reg main_litedramcore_master_p0_cs_n = 1'd1; +reg main_litedramcore_master_p0_odt = 1'd0; +reg main_litedramcore_master_p0_ras_n = 1'd1; +wire [63:0] main_litedramcore_master_p0_rddata; +reg main_litedramcore_master_p0_rddata_en = 1'd0; +wire main_litedramcore_master_p0_rddata_valid; +reg main_litedramcore_master_p0_reset_n = 1'd0; +reg main_litedramcore_master_p0_we_n = 1'd1; +reg [63:0] main_litedramcore_master_p0_wrdata = 64'd0; +reg main_litedramcore_master_p0_wrdata_en = 1'd0; +reg [7:0] main_litedramcore_master_p0_wrdata_mask = 8'd0; +reg main_litedramcore_master_p1_act_n = 1'd1; +reg [14:0] main_litedramcore_master_p1_address = 15'd0; +reg [2:0] main_litedramcore_master_p1_bank = 3'd0; +reg main_litedramcore_master_p1_cas_n = 1'd1; +reg main_litedramcore_master_p1_cke = 1'd0; +reg main_litedramcore_master_p1_cs_n = 1'd1; +reg main_litedramcore_master_p1_odt = 1'd0; +reg main_litedramcore_master_p1_ras_n = 1'd1; +wire [63:0] main_litedramcore_master_p1_rddata; +reg main_litedramcore_master_p1_rddata_en = 1'd0; +wire main_litedramcore_master_p1_rddata_valid; +reg main_litedramcore_master_p1_reset_n = 1'd0; +reg main_litedramcore_master_p1_we_n = 1'd1; +reg [63:0] main_litedramcore_master_p1_wrdata = 64'd0; +reg main_litedramcore_master_p1_wrdata_en = 1'd0; +reg [7:0] main_litedramcore_master_p1_wrdata_mask = 8'd0; +reg main_litedramcore_master_p2_act_n = 1'd1; +reg [14:0] main_litedramcore_master_p2_address = 15'd0; +reg [2:0] main_litedramcore_master_p2_bank = 3'd0; +reg main_litedramcore_master_p2_cas_n = 1'd1; +reg main_litedramcore_master_p2_cke = 1'd0; +reg main_litedramcore_master_p2_cs_n = 1'd1; +reg main_litedramcore_master_p2_odt = 1'd0; +reg main_litedramcore_master_p2_ras_n = 1'd1; +wire [63:0] main_litedramcore_master_p2_rddata; +reg main_litedramcore_master_p2_rddata_en = 1'd0; +wire main_litedramcore_master_p2_rddata_valid; +reg main_litedramcore_master_p2_reset_n = 1'd0; +reg main_litedramcore_master_p2_we_n = 1'd1; +reg [63:0] main_litedramcore_master_p2_wrdata = 64'd0; +reg main_litedramcore_master_p2_wrdata_en = 1'd0; +reg [7:0] main_litedramcore_master_p2_wrdata_mask = 8'd0; +reg main_litedramcore_master_p3_act_n = 1'd1; +reg [14:0] main_litedramcore_master_p3_address = 15'd0; +reg [2:0] main_litedramcore_master_p3_bank = 3'd0; +reg main_litedramcore_master_p3_cas_n = 1'd1; +reg main_litedramcore_master_p3_cke = 1'd0; +reg main_litedramcore_master_p3_cs_n = 1'd1; +reg main_litedramcore_master_p3_odt = 1'd0; +reg main_litedramcore_master_p3_ras_n = 1'd1; +wire [63:0] main_litedramcore_master_p3_rddata; +reg main_litedramcore_master_p3_rddata_en = 1'd0; +wire main_litedramcore_master_p3_rddata_valid; +reg main_litedramcore_master_p3_reset_n = 1'd0; +reg main_litedramcore_master_p3_we_n = 1'd1; +reg [63:0] main_litedramcore_master_p3_wrdata = 64'd0; +reg main_litedramcore_master_p3_wrdata_en = 1'd0; +reg [7:0] main_litedramcore_master_p3_wrdata_mask = 8'd0; +wire main_litedramcore_max_time0; +wire main_litedramcore_max_time1; +reg [14:0] main_litedramcore_nop_a = 15'd0; +reg [2:0] main_litedramcore_nop_ba = 3'd0; +wire [1:0] main_litedramcore_nphases; +wire main_litedramcore_odt; +reg main_litedramcore_phaseinjector0_address_re = 1'd0; +reg [14:0] main_litedramcore_phaseinjector0_address_storage = 15'd0; +reg main_litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0; +wire main_litedramcore_phaseinjector0_command_issue_r; +reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector0_command_re = 1'd0; +reg [7:0] main_litedramcore_phaseinjector0_command_storage = 8'd0; +wire main_litedramcore_phaseinjector0_csrfield_cas; +wire main_litedramcore_phaseinjector0_csrfield_cs; +wire main_litedramcore_phaseinjector0_csrfield_cs_bottom; +wire main_litedramcore_phaseinjector0_csrfield_cs_top; +wire main_litedramcore_phaseinjector0_csrfield_ras; +wire main_litedramcore_phaseinjector0_csrfield_rden; +wire main_litedramcore_phaseinjector0_csrfield_we; +wire main_litedramcore_phaseinjector0_csrfield_wren; +reg main_litedramcore_phaseinjector0_rddata_re = 1'd0; +reg [63:0] main_litedramcore_phaseinjector0_rddata_status = 64'd0; +wire main_litedramcore_phaseinjector0_rddata_we; +reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [63:0] main_litedramcore_phaseinjector0_wrdata_storage = 64'd0; +reg main_litedramcore_phaseinjector1_address_re = 1'd0; +reg [14:0] main_litedramcore_phaseinjector1_address_storage = 15'd0; +reg main_litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0; +wire main_litedramcore_phaseinjector1_command_issue_r; +reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector1_command_re = 1'd0; +reg [7:0] main_litedramcore_phaseinjector1_command_storage = 8'd0; +wire main_litedramcore_phaseinjector1_csrfield_cas; +wire main_litedramcore_phaseinjector1_csrfield_cs; +wire main_litedramcore_phaseinjector1_csrfield_cs_bottom; +wire main_litedramcore_phaseinjector1_csrfield_cs_top; +wire main_litedramcore_phaseinjector1_csrfield_ras; +wire main_litedramcore_phaseinjector1_csrfield_rden; +wire main_litedramcore_phaseinjector1_csrfield_we; +wire main_litedramcore_phaseinjector1_csrfield_wren; +reg main_litedramcore_phaseinjector1_rddata_re = 1'd0; +reg [63:0] main_litedramcore_phaseinjector1_rddata_status = 64'd0; +wire main_litedramcore_phaseinjector1_rddata_we; +reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [63:0] main_litedramcore_phaseinjector1_wrdata_storage = 64'd0; +reg main_litedramcore_phaseinjector2_address_re = 1'd0; +reg [14:0] main_litedramcore_phaseinjector2_address_storage = 15'd0; +reg main_litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0; +wire main_litedramcore_phaseinjector2_command_issue_r; +reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector2_command_re = 1'd0; +reg [7:0] main_litedramcore_phaseinjector2_command_storage = 8'd0; +wire main_litedramcore_phaseinjector2_csrfield_cas; +wire main_litedramcore_phaseinjector2_csrfield_cs; +wire main_litedramcore_phaseinjector2_csrfield_cs_bottom; +wire main_litedramcore_phaseinjector2_csrfield_cs_top; +wire main_litedramcore_phaseinjector2_csrfield_ras; +wire main_litedramcore_phaseinjector2_csrfield_rden; +wire main_litedramcore_phaseinjector2_csrfield_we; +wire main_litedramcore_phaseinjector2_csrfield_wren; +reg main_litedramcore_phaseinjector2_rddata_re = 1'd0; +reg [63:0] main_litedramcore_phaseinjector2_rddata_status = 64'd0; +wire main_litedramcore_phaseinjector2_rddata_we; +reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [63:0] main_litedramcore_phaseinjector2_wrdata_storage = 64'd0; +reg main_litedramcore_phaseinjector3_address_re = 1'd0; +reg [14:0] main_litedramcore_phaseinjector3_address_storage = 15'd0; +reg main_litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0; +wire main_litedramcore_phaseinjector3_command_issue_r; +reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector3_command_re = 1'd0; +reg [7:0] main_litedramcore_phaseinjector3_command_storage = 8'd0; +wire main_litedramcore_phaseinjector3_csrfield_cas; +wire main_litedramcore_phaseinjector3_csrfield_cs; +wire main_litedramcore_phaseinjector3_csrfield_cs_bottom; +wire main_litedramcore_phaseinjector3_csrfield_cs_top; +wire main_litedramcore_phaseinjector3_csrfield_ras; +wire main_litedramcore_phaseinjector3_csrfield_rden; +wire main_litedramcore_phaseinjector3_csrfield_we; +wire main_litedramcore_phaseinjector3_csrfield_wren; +reg main_litedramcore_phaseinjector3_rddata_re = 1'd0; +reg [63:0] main_litedramcore_phaseinjector3_rddata_status = 64'd0; +wire main_litedramcore_phaseinjector3_rddata_we; +reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [63:0] main_litedramcore_phaseinjector3_wrdata_storage = 64'd0; +reg main_litedramcore_postponer_count = 1'd0; +wire main_litedramcore_postponer_req_i; +reg main_litedramcore_postponer_req_o = 1'd0; +wire main_litedramcore_ras_allowed; +wire [1:0] main_litedramcore_rdphase; +reg main_litedramcore_re = 1'd0; +wire main_litedramcore_read_available; +wire main_litedramcore_reset_n; +wire main_litedramcore_sel; +reg main_litedramcore_sequencer_count = 1'd0; +wire main_litedramcore_sequencer_done0; +reg main_litedramcore_sequencer_done1 = 1'd0; +reg main_litedramcore_sequencer_start0 = 1'd0; +wire main_litedramcore_sequencer_start1; +reg [5:0] main_litedramcore_sequencer_trigger = 6'd0; +wire main_litedramcore_slave_p0_act_n; +wire [14:0] main_litedramcore_slave_p0_address; +wire [2:0] main_litedramcore_slave_p0_bank; +wire main_litedramcore_slave_p0_cas_n; +wire main_litedramcore_slave_p0_cke; +wire main_litedramcore_slave_p0_cs_n; +wire main_litedramcore_slave_p0_odt; +wire main_litedramcore_slave_p0_ras_n; +reg [63:0] main_litedramcore_slave_p0_rddata = 64'd0; +wire main_litedramcore_slave_p0_rddata_en; +reg main_litedramcore_slave_p0_rddata_valid = 1'd0; +wire main_litedramcore_slave_p0_reset_n; +wire main_litedramcore_slave_p0_we_n; +wire [63:0] main_litedramcore_slave_p0_wrdata; +wire main_litedramcore_slave_p0_wrdata_en; +wire [7:0] main_litedramcore_slave_p0_wrdata_mask; +wire main_litedramcore_slave_p1_act_n; +wire [14:0] main_litedramcore_slave_p1_address; +wire [2:0] main_litedramcore_slave_p1_bank; +wire main_litedramcore_slave_p1_cas_n; +wire main_litedramcore_slave_p1_cke; +wire main_litedramcore_slave_p1_cs_n; +wire main_litedramcore_slave_p1_odt; +wire main_litedramcore_slave_p1_ras_n; +reg [63:0] main_litedramcore_slave_p1_rddata = 64'd0; +wire main_litedramcore_slave_p1_rddata_en; +reg main_litedramcore_slave_p1_rddata_valid = 1'd0; +wire main_litedramcore_slave_p1_reset_n; +wire main_litedramcore_slave_p1_we_n; +wire [63:0] main_litedramcore_slave_p1_wrdata; +wire main_litedramcore_slave_p1_wrdata_en; +wire [7:0] main_litedramcore_slave_p1_wrdata_mask; +wire main_litedramcore_slave_p2_act_n; +wire [14:0] main_litedramcore_slave_p2_address; +wire [2:0] main_litedramcore_slave_p2_bank; +wire main_litedramcore_slave_p2_cas_n; +wire main_litedramcore_slave_p2_cke; +wire main_litedramcore_slave_p2_cs_n; +wire main_litedramcore_slave_p2_odt; +wire main_litedramcore_slave_p2_ras_n; +reg [63:0] main_litedramcore_slave_p2_rddata = 64'd0; +wire main_litedramcore_slave_p2_rddata_en; +reg main_litedramcore_slave_p2_rddata_valid = 1'd0; +wire main_litedramcore_slave_p2_reset_n; +wire main_litedramcore_slave_p2_we_n; +wire [63:0] main_litedramcore_slave_p2_wrdata; +wire main_litedramcore_slave_p2_wrdata_en; +wire [7:0] main_litedramcore_slave_p2_wrdata_mask; +wire main_litedramcore_slave_p3_act_n; +wire [14:0] main_litedramcore_slave_p3_address; +wire [2:0] main_litedramcore_slave_p3_bank; +wire main_litedramcore_slave_p3_cas_n; +wire main_litedramcore_slave_p3_cke; +wire main_litedramcore_slave_p3_cs_n; +wire main_litedramcore_slave_p3_odt; +wire main_litedramcore_slave_p3_ras_n; +reg [63:0] main_litedramcore_slave_p3_rddata = 64'd0; +wire main_litedramcore_slave_p3_rddata_en; +reg main_litedramcore_slave_p3_rddata_valid = 1'd0; +wire main_litedramcore_slave_p3_reset_n; +wire main_litedramcore_slave_p3_we_n; +wire [63:0] main_litedramcore_slave_p3_wrdata; +wire main_litedramcore_slave_p3_wrdata_en; +wire [7:0] main_litedramcore_slave_p3_wrdata_mask; +reg [1:0] main_litedramcore_steerer0 = 2'd0; +reg [1:0] main_litedramcore_steerer1 = 2'd0; +reg main_litedramcore_steerer10 = 1'd1; +reg main_litedramcore_steerer11 = 1'd1; +reg [1:0] main_litedramcore_steerer2 = 2'd0; +reg [1:0] main_litedramcore_steerer3 = 2'd0; +reg main_litedramcore_steerer4 = 1'd1; +reg main_litedramcore_steerer5 = 1'd1; +reg main_litedramcore_steerer6 = 1'd1; +reg main_litedramcore_steerer7 = 1'd1; +reg main_litedramcore_steerer8 = 1'd1; +reg main_litedramcore_steerer9 = 1'd1; +reg [3:0] main_litedramcore_storage = 4'd1; +reg main_litedramcore_tccdcon_count = 1'd0; (* dont_touch = "true" *) -reg litedramcore_trrdcon_ready = 1'd0; -reg litedramcore_trrdcon_count = 1'd0; -wire litedramcore_tfawcon_valid; +reg main_litedramcore_tccdcon_ready = 1'd0; +wire main_litedramcore_tccdcon_valid; +wire [2:0] main_litedramcore_tfawcon_count; (* dont_touch = "true" *) -reg litedramcore_tfawcon_ready = 1'd1; -wire [2:0] litedramcore_tfawcon_count; -reg [4:0] litedramcore_tfawcon_window = 5'd0; -wire litedramcore_tccdcon_valid; +reg main_litedramcore_tfawcon_ready = 1'd1; +wire main_litedramcore_tfawcon_valid; +reg [4:0] main_litedramcore_tfawcon_window = 5'd0; +reg [4:0] main_litedramcore_time0 = 5'd0; +reg [3:0] main_litedramcore_time1 = 4'd0; +wire [9:0] main_litedramcore_timer_count0; +reg [9:0] main_litedramcore_timer_count1 = 10'd781; +wire main_litedramcore_timer_done0; +wire main_litedramcore_timer_done1; +wire main_litedramcore_timer_wait; +reg main_litedramcore_trrdcon_count = 1'd0; (* dont_touch = "true" *) -reg litedramcore_tccdcon_ready = 1'd0; -reg litedramcore_tccdcon_count = 1'd0; -wire litedramcore_twtrcon_valid; +reg main_litedramcore_trrdcon_ready = 1'd0; +wire main_litedramcore_trrdcon_valid; +reg [2:0] main_litedramcore_twtrcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_twtrcon_ready = 1'd0; -reg [2:0] litedramcore_twtrcon_count = 3'd0; -wire litedramcore_read_available; -wire litedramcore_write_available; -reg litedramcore_en0 = 1'd0; -wire litedramcore_max_time0; -reg [4:0] litedramcore_time0 = 5'd0; -reg litedramcore_en1 = 1'd0; -wire litedramcore_max_time1; -reg [3:0] litedramcore_time1 = 4'd0; -wire litedramcore_go_to_refresh; -reg init_done_storage = 1'd0; -reg init_done_re = 1'd0; -reg init_error_storage = 1'd0; -reg init_error_re = 1'd0; -wire [29:0] wb_bus_adr; -wire [31:0] wb_bus_dat_w; -wire [31:0] wb_bus_dat_r; -wire [3:0] wb_bus_sel; -wire wb_bus_cyc; -wire wb_bus_stb; -wire wb_bus_ack; -wire wb_bus_we; -wire [2:0] wb_bus_cti; -wire [1:0] wb_bus_bte; -wire wb_bus_err; -wire user_enable; -wire user_port_cmd_valid; -wire user_port_cmd_ready; -wire user_port_cmd_payload_we; -wire [24:0] user_port_cmd_payload_addr; -wire user_port_wdata_valid; -wire user_port_wdata_ready; -wire [255:0] user_port_wdata_payload_data; -wire [31:0] user_port_wdata_payload_we; -wire user_port_rdata_valid; -wire user_port_rdata_ready; -wire [255:0] user_port_rdata_payload_data; -reg [13:0] litedramcore_adr = 14'd0; -reg litedramcore_we = 1'd0; -reg [31:0] litedramcore_dat_w = 32'd0; -wire [31:0] litedramcore_dat_r; -wire [29:0] litedramcore_wishbone_adr; -wire [31:0] litedramcore_wishbone_dat_w; -reg [31:0] litedramcore_wishbone_dat_r = 32'd0; -wire [3:0] litedramcore_wishbone_sel; -wire litedramcore_wishbone_cyc; -wire litedramcore_wishbone_stb; -reg litedramcore_wishbone_ack = 1'd0; -wire litedramcore_wishbone_we; -wire [2:0] litedramcore_wishbone_cti; -wire [1:0] litedramcore_wishbone_bte; -reg litedramcore_wishbone_err = 1'd0; -wire [13:0] interface0_bank_bus_adr; -wire interface0_bank_bus_we; -wire [31:0] interface0_bank_bus_dat_w; -reg [31:0] interface0_bank_bus_dat_r = 32'd0; -reg csrbank0_init_done0_re = 1'd0; -wire csrbank0_init_done0_r; -reg csrbank0_init_done0_we = 1'd0; -wire csrbank0_init_done0_w; -reg csrbank0_init_error0_re = 1'd0; -wire csrbank0_init_error0_r; -reg csrbank0_init_error0_we = 1'd0; -wire csrbank0_init_error0_w; -wire csrbank0_sel; -wire [13:0] interface1_bank_bus_adr; -wire interface1_bank_bus_we; -wire [31:0] interface1_bank_bus_dat_w; -reg [31:0] interface1_bank_bus_dat_r = 32'd0; -reg csrbank1_rst0_re = 1'd0; -wire csrbank1_rst0_r; -reg csrbank1_rst0_we = 1'd0; -wire csrbank1_rst0_w; -reg csrbank1_dly_sel0_re = 1'd0; -wire [3:0] csrbank1_dly_sel0_r; -reg csrbank1_dly_sel0_we = 1'd0; -wire [3:0] csrbank1_dly_sel0_w; -reg csrbank1_half_sys8x_taps0_re = 1'd0; -wire [4:0] csrbank1_half_sys8x_taps0_r; -reg csrbank1_half_sys8x_taps0_we = 1'd0; -wire [4:0] csrbank1_half_sys8x_taps0_w; -reg csrbank1_wlevel_en0_re = 1'd0; -wire csrbank1_wlevel_en0_r; -reg csrbank1_wlevel_en0_we = 1'd0; -wire csrbank1_wlevel_en0_w; -reg csrbank1_rdphase0_re = 1'd0; -wire [1:0] csrbank1_rdphase0_r; -reg csrbank1_rdphase0_we = 1'd0; -wire [1:0] csrbank1_rdphase0_w; -reg csrbank1_wrphase0_re = 1'd0; -wire [1:0] csrbank1_wrphase0_r; -reg csrbank1_wrphase0_we = 1'd0; -wire [1:0] csrbank1_wrphase0_w; -wire csrbank1_sel; -wire [13:0] interface2_bank_bus_adr; -wire interface2_bank_bus_we; -wire [31:0] interface2_bank_bus_dat_w; -reg [31:0] interface2_bank_bus_dat_r = 32'd0; -reg csrbank2_dfii_control0_re = 1'd0; -wire [3:0] csrbank2_dfii_control0_r; -reg csrbank2_dfii_control0_we = 1'd0; -wire [3:0] csrbank2_dfii_control0_w; -reg csrbank2_dfii_pi0_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi0_command0_r; -reg csrbank2_dfii_pi0_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi0_command0_w; -reg csrbank2_dfii_pi0_address0_re = 1'd0; -wire [14:0] csrbank2_dfii_pi0_address0_r; -reg csrbank2_dfii_pi0_address0_we = 1'd0; -wire [14:0] csrbank2_dfii_pi0_address0_w; -reg csrbank2_dfii_pi0_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi0_baddress0_r; -reg csrbank2_dfii_pi0_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi0_baddress0_w; -reg csrbank2_dfii_pi0_wrdata1_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata1_r; -reg csrbank2_dfii_pi0_wrdata1_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata1_w; -reg csrbank2_dfii_pi0_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata0_r; -reg csrbank2_dfii_pi0_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata0_w; -reg csrbank2_dfii_pi0_rddata1_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata1_r; -reg csrbank2_dfii_pi0_rddata1_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata1_w; -reg csrbank2_dfii_pi0_rddata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata0_r; -reg csrbank2_dfii_pi0_rddata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata0_w; -reg csrbank2_dfii_pi1_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi1_command0_r; -reg csrbank2_dfii_pi1_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi1_command0_w; -reg csrbank2_dfii_pi1_address0_re = 1'd0; -wire [14:0] csrbank2_dfii_pi1_address0_r; -reg csrbank2_dfii_pi1_address0_we = 1'd0; -wire [14:0] csrbank2_dfii_pi1_address0_w; -reg csrbank2_dfii_pi1_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi1_baddress0_r; -reg csrbank2_dfii_pi1_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi1_baddress0_w; -reg csrbank2_dfii_pi1_wrdata1_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata1_r; -reg csrbank2_dfii_pi1_wrdata1_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata1_w; -reg csrbank2_dfii_pi1_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata0_r; -reg csrbank2_dfii_pi1_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata0_w; -reg csrbank2_dfii_pi1_rddata1_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata1_r; -reg csrbank2_dfii_pi1_rddata1_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata1_w; -reg csrbank2_dfii_pi1_rddata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata0_r; -reg csrbank2_dfii_pi1_rddata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata0_w; -reg csrbank2_dfii_pi2_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi2_command0_r; -reg csrbank2_dfii_pi2_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi2_command0_w; -reg csrbank2_dfii_pi2_address0_re = 1'd0; -wire [14:0] csrbank2_dfii_pi2_address0_r; -reg csrbank2_dfii_pi2_address0_we = 1'd0; -wire [14:0] csrbank2_dfii_pi2_address0_w; -reg csrbank2_dfii_pi2_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi2_baddress0_r; -reg csrbank2_dfii_pi2_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi2_baddress0_w; -reg csrbank2_dfii_pi2_wrdata1_re = 1'd0; -wire [31:0] csrbank2_dfii_pi2_wrdata1_r; -reg csrbank2_dfii_pi2_wrdata1_we = 1'd0; -wire [31:0] csrbank2_dfii_pi2_wrdata1_w; -reg csrbank2_dfii_pi2_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi2_wrdata0_r; -reg csrbank2_dfii_pi2_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi2_wrdata0_w; -reg csrbank2_dfii_pi2_rddata1_re = 1'd0; -wire [31:0] csrbank2_dfii_pi2_rddata1_r; -reg csrbank2_dfii_pi2_rddata1_we = 1'd0; -wire [31:0] csrbank2_dfii_pi2_rddata1_w; -reg csrbank2_dfii_pi2_rddata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi2_rddata0_r; -reg csrbank2_dfii_pi2_rddata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi2_rddata0_w; -reg csrbank2_dfii_pi3_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi3_command0_r; -reg csrbank2_dfii_pi3_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi3_command0_w; -reg csrbank2_dfii_pi3_address0_re = 1'd0; -wire [14:0] csrbank2_dfii_pi3_address0_r; -reg csrbank2_dfii_pi3_address0_we = 1'd0; -wire [14:0] csrbank2_dfii_pi3_address0_w; -reg csrbank2_dfii_pi3_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi3_baddress0_r; -reg csrbank2_dfii_pi3_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi3_baddress0_w; -reg csrbank2_dfii_pi3_wrdata1_re = 1'd0; -wire [31:0] csrbank2_dfii_pi3_wrdata1_r; -reg csrbank2_dfii_pi3_wrdata1_we = 1'd0; -wire [31:0] csrbank2_dfii_pi3_wrdata1_w; -reg csrbank2_dfii_pi3_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi3_wrdata0_r; -reg csrbank2_dfii_pi3_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi3_wrdata0_w; -reg csrbank2_dfii_pi3_rddata1_re = 1'd0; -wire [31:0] csrbank2_dfii_pi3_rddata1_r; -reg csrbank2_dfii_pi3_rddata1_we = 1'd0; -wire [31:0] csrbank2_dfii_pi3_rddata1_w; -reg csrbank2_dfii_pi3_rddata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi3_rddata0_r; -reg csrbank2_dfii_pi3_rddata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi3_rddata0_w; -wire csrbank2_sel; -wire [13:0] csr_interconnect_adr; -wire csr_interconnect_we; -wire [31:0] csr_interconnect_dat_w; -wire [31:0] csr_interconnect_dat_r; -wire litedramcore_reset0; -wire litedramcore_reset1; -wire litedramcore_reset2; -wire litedramcore_reset3; -wire litedramcore_reset4; -wire litedramcore_reset5; -wire litedramcore_reset6; -wire litedramcore_reset7; -wire litedramcore_pll_fb; -reg [1:0] litedramcore_refresher_state = 2'd0; -reg [1:0] litedramcore_refresher_next_state = 2'd0; -reg [3:0] litedramcore_bankmachine0_state = 4'd0; -reg [3:0] litedramcore_bankmachine0_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine1_state = 4'd0; -reg [3:0] litedramcore_bankmachine1_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine2_state = 4'd0; -reg [3:0] litedramcore_bankmachine2_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine3_state = 4'd0; -reg [3:0] litedramcore_bankmachine3_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine4_state = 4'd0; -reg [3:0] litedramcore_bankmachine4_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine5_state = 4'd0; -reg [3:0] litedramcore_bankmachine5_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine6_state = 4'd0; -reg [3:0] litedramcore_bankmachine6_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine7_state = 4'd0; -reg [3:0] litedramcore_bankmachine7_next_state = 4'd0; -reg [3:0] litedramcore_multiplexer_state = 4'd0; -reg [3:0] litedramcore_multiplexer_next_state = 4'd0; -wire litedramcore_roundrobin0_request; -wire litedramcore_roundrobin0_grant; -wire litedramcore_roundrobin0_ce; -wire litedramcore_roundrobin1_request; -wire litedramcore_roundrobin1_grant; -wire litedramcore_roundrobin1_ce; -wire litedramcore_roundrobin2_request; -wire litedramcore_roundrobin2_grant; -wire litedramcore_roundrobin2_ce; -wire litedramcore_roundrobin3_request; -wire litedramcore_roundrobin3_grant; -wire litedramcore_roundrobin3_ce; -wire litedramcore_roundrobin4_request; -wire litedramcore_roundrobin4_grant; -wire litedramcore_roundrobin4_ce; -wire litedramcore_roundrobin5_request; -wire litedramcore_roundrobin5_grant; -wire litedramcore_roundrobin5_ce; -wire litedramcore_roundrobin6_request; -wire litedramcore_roundrobin6_grant; -wire litedramcore_roundrobin6_ce; -wire litedramcore_roundrobin7_request; -wire litedramcore_roundrobin7_grant; -wire litedramcore_roundrobin7_ce; -reg litedramcore_locked0 = 1'd0; -reg litedramcore_locked1 = 1'd0; -reg litedramcore_locked2 = 1'd0; -reg litedramcore_locked3 = 1'd0; -reg litedramcore_locked4 = 1'd0; -reg litedramcore_locked5 = 1'd0; -reg litedramcore_locked6 = 1'd0; -reg litedramcore_locked7 = 1'd0; -reg litedramcore_new_master_wdata_ready0 = 1'd0; -reg litedramcore_new_master_wdata_ready1 = 1'd0; -reg litedramcore_new_master_rdata_valid0 = 1'd0; -reg litedramcore_new_master_rdata_valid1 = 1'd0; -reg litedramcore_new_master_rdata_valid2 = 1'd0; -reg litedramcore_new_master_rdata_valid3 = 1'd0; -reg litedramcore_new_master_rdata_valid4 = 1'd0; -reg litedramcore_new_master_rdata_valid5 = 1'd0; -reg litedramcore_new_master_rdata_valid6 = 1'd0; -reg litedramcore_new_master_rdata_valid7 = 1'd0; -reg litedramcore_new_master_rdata_valid8 = 1'd0; -reg [1:0] litedramcore_state = 2'd0; -reg [1:0] litedramcore_next_state = 2'd0; -reg [31:0] litedramcore_dat_w_next_value0 = 32'd0; -reg litedramcore_dat_w_next_value_ce0 = 1'd0; -reg [13:0] litedramcore_adr_next_value1 = 14'd0; -reg litedramcore_adr_next_value_ce1 = 1'd0; -reg litedramcore_we_next_value2 = 1'd0; -reg litedramcore_we_next_value_ce2 = 1'd0; -reg rhs_array_muxed0 = 1'd0; -reg [14:0] rhs_array_muxed1 = 15'd0; -reg [2:0] rhs_array_muxed2 = 3'd0; -reg rhs_array_muxed3 = 1'd0; -reg rhs_array_muxed4 = 1'd0; -reg rhs_array_muxed5 = 1'd0; -reg t_array_muxed0 = 1'd0; -reg t_array_muxed1 = 1'd0; -reg t_array_muxed2 = 1'd0; -reg rhs_array_muxed6 = 1'd0; -reg [14:0] rhs_array_muxed7 = 15'd0; -reg [2:0] rhs_array_muxed8 = 3'd0; -reg rhs_array_muxed9 = 1'd0; -reg rhs_array_muxed10 = 1'd0; -reg rhs_array_muxed11 = 1'd0; -reg t_array_muxed3 = 1'd0; -reg t_array_muxed4 = 1'd0; -reg t_array_muxed5 = 1'd0; -reg [21:0] rhs_array_muxed12 = 22'd0; -reg rhs_array_muxed13 = 1'd0; -reg rhs_array_muxed14 = 1'd0; -reg [21:0] rhs_array_muxed15 = 22'd0; -reg rhs_array_muxed16 = 1'd0; -reg rhs_array_muxed17 = 1'd0; -reg [21:0] rhs_array_muxed18 = 22'd0; -reg rhs_array_muxed19 = 1'd0; -reg rhs_array_muxed20 = 1'd0; -reg [21:0] rhs_array_muxed21 = 22'd0; -reg rhs_array_muxed22 = 1'd0; -reg rhs_array_muxed23 = 1'd0; -reg [21:0] rhs_array_muxed24 = 22'd0; -reg rhs_array_muxed25 = 1'd0; -reg rhs_array_muxed26 = 1'd0; -reg [21:0] rhs_array_muxed27 = 22'd0; -reg rhs_array_muxed28 = 1'd0; -reg rhs_array_muxed29 = 1'd0; -reg [21:0] rhs_array_muxed30 = 22'd0; -reg rhs_array_muxed31 = 1'd0; -reg rhs_array_muxed32 = 1'd0; -reg [21:0] rhs_array_muxed33 = 22'd0; -reg rhs_array_muxed34 = 1'd0; -reg rhs_array_muxed35 = 1'd0; -reg [2:0] array_muxed0 = 3'd0; -reg [14:0] array_muxed1 = 15'd0; -reg array_muxed2 = 1'd0; -reg array_muxed3 = 1'd0; -reg array_muxed4 = 1'd0; -reg array_muxed5 = 1'd0; -reg array_muxed6 = 1'd0; -reg [2:0] array_muxed7 = 3'd0; -reg [14:0] array_muxed8 = 15'd0; -reg array_muxed9 = 1'd0; -reg array_muxed10 = 1'd0; -reg array_muxed11 = 1'd0; -reg array_muxed12 = 1'd0; -reg array_muxed13 = 1'd0; -reg [2:0] array_muxed14 = 3'd0; -reg [14:0] array_muxed15 = 15'd0; -reg array_muxed16 = 1'd0; -reg array_muxed17 = 1'd0; -reg array_muxed18 = 1'd0; -reg array_muxed19 = 1'd0; -reg array_muxed20 = 1'd0; -reg [2:0] array_muxed21 = 3'd0; -reg [14:0] array_muxed22 = 15'd0; -reg array_muxed23 = 1'd0; -reg array_muxed24 = 1'd0; -reg array_muxed25 = 1'd0; -reg array_muxed26 = 1'd0; -reg array_muxed27 = 1'd0; -wire xilinxasyncresetsynchronizerimpl0; -wire xilinxasyncresetsynchronizerimpl0_rst_meta; -wire xilinxasyncresetsynchronizerimpl1; -wire xilinxasyncresetsynchronizerimpl1_rst_meta; -wire xilinxasyncresetsynchronizerimpl2; -wire xilinxasyncresetsynchronizerimpl2_rst_meta; -wire xilinxasyncresetsynchronizerimpl2_expr; -wire xilinxasyncresetsynchronizerimpl3; -wire xilinxasyncresetsynchronizerimpl3_rst_meta; -wire xilinxasyncresetsynchronizerimpl3_expr; +reg main_litedramcore_twtrcon_ready = 1'd0; +wire main_litedramcore_twtrcon_valid; +wire main_litedramcore_wants_refresh; +wire main_litedramcore_wants_zqcs; +wire main_litedramcore_write_available; +reg main_litedramcore_zqcs_executer_done = 1'd0; +reg main_litedramcore_zqcs_executer_start = 1'd0; +reg [4:0] main_litedramcore_zqcs_executer_trigger = 5'd0; +wire [26:0] main_litedramcore_zqcs_timer_count0; +reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999; +wire main_litedramcore_zqcs_timer_done0; +wire main_litedramcore_zqcs_timer_done1; +wire main_litedramcore_zqcs_timer_wait; +wire main_locked; +reg main_power_down = 1'd0; +wire main_reset; +reg [3:0] main_reset_counter = 4'd15; +reg main_rst = 1'd0; +wire main_user_enable; +wire [24:0] main_user_port_cmd_payload_addr; +wire main_user_port_cmd_payload_we; +wire main_user_port_cmd_ready; +wire main_user_port_cmd_valid; +wire [255:0] main_user_port_rdata_payload_data; +wire main_user_port_rdata_ready; +wire main_user_port_rdata_valid; +wire [255:0] main_user_port_wdata_payload_data; +wire [31:0] main_user_port_wdata_payload_we; +wire main_user_port_wdata_ready; +wire main_user_port_wdata_valid; +wire main_wb_bus_ack; +wire [29:0] main_wb_bus_adr; +wire [1:0] main_wb_bus_bte; +wire [2:0] main_wb_bus_cti; +wire main_wb_bus_cyc; +wire [31:0] main_wb_bus_dat_r; +wire [31:0] main_wb_bus_dat_w; +wire main_wb_bus_err; +wire [3:0] main_wb_bus_sel; +wire main_wb_bus_stb; +wire main_wb_bus_we; +wire sys4x_clk; +wire sys4x_dqs_clk; +wire sys_clk; +wire sys_rst; //------------------------------------------------------------------------------ // Combinatorial Logic //------------------------------------------------------------------------------ -assign init_done = init_done_storage; -assign init_error = init_error_storage; -assign wb_bus_adr = wb_ctrl_adr; -assign wb_bus_dat_w = wb_ctrl_dat_w; -assign wb_ctrl_dat_r = wb_bus_dat_r; -assign wb_bus_sel = wb_ctrl_sel; -assign wb_bus_cyc = wb_ctrl_cyc; -assign wb_bus_stb = wb_ctrl_stb; -assign wb_ctrl_ack = wb_bus_ack; -assign wb_bus_we = wb_ctrl_we; -assign wb_bus_cti = wb_ctrl_cti; -assign wb_bus_bte = wb_ctrl_bte; -assign wb_ctrl_err = wb_bus_err; +assign init_done = main_init_done_storage; +assign init_error = main_init_error_storage; +assign main_wb_bus_adr = wb_ctrl_adr; +assign main_wb_bus_dat_w = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = main_wb_bus_dat_r; +assign main_wb_bus_sel = wb_ctrl_sel; +assign main_wb_bus_cyc = wb_ctrl_cyc; +assign main_wb_bus_stb = wb_ctrl_stb; +assign wb_ctrl_ack = main_wb_bus_ack; +assign main_wb_bus_we = wb_ctrl_we; +assign main_wb_bus_cti = wb_ctrl_cti; +assign main_wb_bus_bte = wb_ctrl_bte; +assign wb_ctrl_err = main_wb_bus_err; assign user_clk = sys_clk; assign user_rst = sys_rst; -assign user_enable = 1'd1; -assign user_port_cmd_valid = (user_port_native_0_cmd_valid & user_enable); -assign user_port_native_0_cmd_ready = (user_port_cmd_ready & user_enable); -assign user_port_cmd_payload_we = user_port_native_0_cmd_we; -assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr; -assign user_port_wdata_valid = (user_port_native_0_wdata_valid & user_enable); -assign user_port_native_0_wdata_ready = (user_port_wdata_ready & user_enable); -assign user_port_wdata_payload_we = user_port_native_0_wdata_we; -assign user_port_wdata_payload_data = user_port_native_0_wdata_data; -assign user_port_native_0_rdata_valid = (user_port_rdata_valid & user_enable); -assign user_port_rdata_ready = (user_port_native_0_rdata_ready & user_enable); -assign user_port_native_0_rdata_data = user_port_rdata_payload_data; -assign reset = (rst | rst_1); -assign pll_locked = locked; -assign clkin = clk; -assign iodelay_clk = clkout_buf0; -assign sys_clk = clkout_buf1; -assign sys4x_clk = clkout_buf2; -assign sys4x_dqs_clk = clkout_buf3; -assign ddram_ba = k7ddrphy_pads_ba; -assign k7ddrphy_dqs_oe_delay_tappeddelayline = ((k7ddrphy_dqs_preamble | k7ddrphy_dqs_oe) | k7ddrphy_dqs_postamble); -assign k7ddrphy_dq_oe_delay_tappeddelayline = ((k7ddrphy_dqs_preamble | k7ddrphy_dq_oe) | k7ddrphy_dqs_postamble); -always @(*) begin - k7ddrphy_dfi_p0_rddata <= 64'd0; - k7ddrphy_dfi_p0_rddata[0] <= k7ddrphy_bitslip04[0]; - k7ddrphy_dfi_p0_rddata[32] <= k7ddrphy_bitslip04[1]; - k7ddrphy_dfi_p0_rddata[1] <= k7ddrphy_bitslip14[0]; - k7ddrphy_dfi_p0_rddata[33] <= k7ddrphy_bitslip14[1]; - k7ddrphy_dfi_p0_rddata[2] <= k7ddrphy_bitslip24[0]; - k7ddrphy_dfi_p0_rddata[34] <= k7ddrphy_bitslip24[1]; - k7ddrphy_dfi_p0_rddata[3] <= k7ddrphy_bitslip34[0]; - k7ddrphy_dfi_p0_rddata[35] <= k7ddrphy_bitslip34[1]; - k7ddrphy_dfi_p0_rddata[4] <= k7ddrphy_bitslip42[0]; - k7ddrphy_dfi_p0_rddata[36] <= k7ddrphy_bitslip42[1]; - k7ddrphy_dfi_p0_rddata[5] <= k7ddrphy_bitslip52[0]; - k7ddrphy_dfi_p0_rddata[37] <= k7ddrphy_bitslip52[1]; - k7ddrphy_dfi_p0_rddata[6] <= k7ddrphy_bitslip62[0]; - k7ddrphy_dfi_p0_rddata[38] <= k7ddrphy_bitslip62[1]; - k7ddrphy_dfi_p0_rddata[7] <= k7ddrphy_bitslip72[0]; - k7ddrphy_dfi_p0_rddata[39] <= k7ddrphy_bitslip72[1]; - k7ddrphy_dfi_p0_rddata[8] <= k7ddrphy_bitslip82[0]; - k7ddrphy_dfi_p0_rddata[40] <= k7ddrphy_bitslip82[1]; - k7ddrphy_dfi_p0_rddata[9] <= k7ddrphy_bitslip92[0]; - k7ddrphy_dfi_p0_rddata[41] <= k7ddrphy_bitslip92[1]; - k7ddrphy_dfi_p0_rddata[10] <= k7ddrphy_bitslip102[0]; - k7ddrphy_dfi_p0_rddata[42] <= k7ddrphy_bitslip102[1]; - k7ddrphy_dfi_p0_rddata[11] <= k7ddrphy_bitslip112[0]; - k7ddrphy_dfi_p0_rddata[43] <= k7ddrphy_bitslip112[1]; - k7ddrphy_dfi_p0_rddata[12] <= k7ddrphy_bitslip122[0]; - k7ddrphy_dfi_p0_rddata[44] <= k7ddrphy_bitslip122[1]; - k7ddrphy_dfi_p0_rddata[13] <= k7ddrphy_bitslip132[0]; - k7ddrphy_dfi_p0_rddata[45] <= k7ddrphy_bitslip132[1]; - k7ddrphy_dfi_p0_rddata[14] <= k7ddrphy_bitslip142[0]; - k7ddrphy_dfi_p0_rddata[46] <= k7ddrphy_bitslip142[1]; - k7ddrphy_dfi_p0_rddata[15] <= k7ddrphy_bitslip152[0]; - k7ddrphy_dfi_p0_rddata[47] <= k7ddrphy_bitslip152[1]; - k7ddrphy_dfi_p0_rddata[16] <= k7ddrphy_bitslip162[0]; - k7ddrphy_dfi_p0_rddata[48] <= k7ddrphy_bitslip162[1]; - k7ddrphy_dfi_p0_rddata[17] <= k7ddrphy_bitslip172[0]; - k7ddrphy_dfi_p0_rddata[49] <= k7ddrphy_bitslip172[1]; - k7ddrphy_dfi_p0_rddata[18] <= k7ddrphy_bitslip182[0]; - k7ddrphy_dfi_p0_rddata[50] <= k7ddrphy_bitslip182[1]; - k7ddrphy_dfi_p0_rddata[19] <= k7ddrphy_bitslip192[0]; - k7ddrphy_dfi_p0_rddata[51] <= k7ddrphy_bitslip192[1]; - k7ddrphy_dfi_p0_rddata[20] <= k7ddrphy_bitslip202[0]; - k7ddrphy_dfi_p0_rddata[52] <= k7ddrphy_bitslip202[1]; - k7ddrphy_dfi_p0_rddata[21] <= k7ddrphy_bitslip212[0]; - k7ddrphy_dfi_p0_rddata[53] <= k7ddrphy_bitslip212[1]; - k7ddrphy_dfi_p0_rddata[22] <= k7ddrphy_bitslip222[0]; - k7ddrphy_dfi_p0_rddata[54] <= k7ddrphy_bitslip222[1]; - k7ddrphy_dfi_p0_rddata[23] <= k7ddrphy_bitslip232[0]; - k7ddrphy_dfi_p0_rddata[55] <= k7ddrphy_bitslip232[1]; - k7ddrphy_dfi_p0_rddata[24] <= k7ddrphy_bitslip242[0]; - k7ddrphy_dfi_p0_rddata[56] <= k7ddrphy_bitslip242[1]; - k7ddrphy_dfi_p0_rddata[25] <= k7ddrphy_bitslip252[0]; - k7ddrphy_dfi_p0_rddata[57] <= k7ddrphy_bitslip252[1]; - k7ddrphy_dfi_p0_rddata[26] <= k7ddrphy_bitslip262[0]; - k7ddrphy_dfi_p0_rddata[58] <= k7ddrphy_bitslip262[1]; - k7ddrphy_dfi_p0_rddata[27] <= k7ddrphy_bitslip272[0]; - k7ddrphy_dfi_p0_rddata[59] <= k7ddrphy_bitslip272[1]; - k7ddrphy_dfi_p0_rddata[28] <= k7ddrphy_bitslip282[0]; - k7ddrphy_dfi_p0_rddata[60] <= k7ddrphy_bitslip282[1]; - k7ddrphy_dfi_p0_rddata[29] <= k7ddrphy_bitslip292[0]; - k7ddrphy_dfi_p0_rddata[61] <= k7ddrphy_bitslip292[1]; - k7ddrphy_dfi_p0_rddata[30] <= k7ddrphy_bitslip302[0]; - k7ddrphy_dfi_p0_rddata[62] <= k7ddrphy_bitslip302[1]; - k7ddrphy_dfi_p0_rddata[31] <= k7ddrphy_bitslip312[0]; - k7ddrphy_dfi_p0_rddata[63] <= k7ddrphy_bitslip312[1]; -end -always @(*) begin - k7ddrphy_dfi_p1_rddata <= 64'd0; - k7ddrphy_dfi_p1_rddata[0] <= k7ddrphy_bitslip04[2]; - k7ddrphy_dfi_p1_rddata[32] <= k7ddrphy_bitslip04[3]; - k7ddrphy_dfi_p1_rddata[1] <= k7ddrphy_bitslip14[2]; - k7ddrphy_dfi_p1_rddata[33] <= k7ddrphy_bitslip14[3]; - k7ddrphy_dfi_p1_rddata[2] <= k7ddrphy_bitslip24[2]; - k7ddrphy_dfi_p1_rddata[34] <= k7ddrphy_bitslip24[3]; - k7ddrphy_dfi_p1_rddata[3] <= k7ddrphy_bitslip34[2]; - k7ddrphy_dfi_p1_rddata[35] <= k7ddrphy_bitslip34[3]; - k7ddrphy_dfi_p1_rddata[4] <= k7ddrphy_bitslip42[2]; - k7ddrphy_dfi_p1_rddata[36] <= k7ddrphy_bitslip42[3]; - k7ddrphy_dfi_p1_rddata[5] <= k7ddrphy_bitslip52[2]; - k7ddrphy_dfi_p1_rddata[37] <= k7ddrphy_bitslip52[3]; - k7ddrphy_dfi_p1_rddata[6] <= k7ddrphy_bitslip62[2]; - k7ddrphy_dfi_p1_rddata[38] <= k7ddrphy_bitslip62[3]; - k7ddrphy_dfi_p1_rddata[7] <= k7ddrphy_bitslip72[2]; - k7ddrphy_dfi_p1_rddata[39] <= k7ddrphy_bitslip72[3]; - k7ddrphy_dfi_p1_rddata[8] <= k7ddrphy_bitslip82[2]; - k7ddrphy_dfi_p1_rddata[40] <= k7ddrphy_bitslip82[3]; - k7ddrphy_dfi_p1_rddata[9] <= k7ddrphy_bitslip92[2]; - k7ddrphy_dfi_p1_rddata[41] <= k7ddrphy_bitslip92[3]; - k7ddrphy_dfi_p1_rddata[10] <= k7ddrphy_bitslip102[2]; - k7ddrphy_dfi_p1_rddata[42] <= k7ddrphy_bitslip102[3]; - k7ddrphy_dfi_p1_rddata[11] <= k7ddrphy_bitslip112[2]; - k7ddrphy_dfi_p1_rddata[43] <= k7ddrphy_bitslip112[3]; - k7ddrphy_dfi_p1_rddata[12] <= k7ddrphy_bitslip122[2]; - k7ddrphy_dfi_p1_rddata[44] <= k7ddrphy_bitslip122[3]; - k7ddrphy_dfi_p1_rddata[13] <= k7ddrphy_bitslip132[2]; - k7ddrphy_dfi_p1_rddata[45] <= k7ddrphy_bitslip132[3]; - k7ddrphy_dfi_p1_rddata[14] <= k7ddrphy_bitslip142[2]; - k7ddrphy_dfi_p1_rddata[46] <= k7ddrphy_bitslip142[3]; - k7ddrphy_dfi_p1_rddata[15] <= k7ddrphy_bitslip152[2]; - k7ddrphy_dfi_p1_rddata[47] <= k7ddrphy_bitslip152[3]; - k7ddrphy_dfi_p1_rddata[16] <= k7ddrphy_bitslip162[2]; - k7ddrphy_dfi_p1_rddata[48] <= k7ddrphy_bitslip162[3]; - k7ddrphy_dfi_p1_rddata[17] <= k7ddrphy_bitslip172[2]; - k7ddrphy_dfi_p1_rddata[49] <= k7ddrphy_bitslip172[3]; - k7ddrphy_dfi_p1_rddata[18] <= k7ddrphy_bitslip182[2]; - k7ddrphy_dfi_p1_rddata[50] <= k7ddrphy_bitslip182[3]; - k7ddrphy_dfi_p1_rddata[19] <= k7ddrphy_bitslip192[2]; - k7ddrphy_dfi_p1_rddata[51] <= k7ddrphy_bitslip192[3]; - k7ddrphy_dfi_p1_rddata[20] <= k7ddrphy_bitslip202[2]; - k7ddrphy_dfi_p1_rddata[52] <= k7ddrphy_bitslip202[3]; - k7ddrphy_dfi_p1_rddata[21] <= k7ddrphy_bitslip212[2]; - k7ddrphy_dfi_p1_rddata[53] <= k7ddrphy_bitslip212[3]; - k7ddrphy_dfi_p1_rddata[22] <= k7ddrphy_bitslip222[2]; - k7ddrphy_dfi_p1_rddata[54] <= k7ddrphy_bitslip222[3]; - k7ddrphy_dfi_p1_rddata[23] <= k7ddrphy_bitslip232[2]; - k7ddrphy_dfi_p1_rddata[55] <= k7ddrphy_bitslip232[3]; - k7ddrphy_dfi_p1_rddata[24] <= k7ddrphy_bitslip242[2]; - k7ddrphy_dfi_p1_rddata[56] <= k7ddrphy_bitslip242[3]; - k7ddrphy_dfi_p1_rddata[25] <= k7ddrphy_bitslip252[2]; - k7ddrphy_dfi_p1_rddata[57] <= k7ddrphy_bitslip252[3]; - k7ddrphy_dfi_p1_rddata[26] <= k7ddrphy_bitslip262[2]; - k7ddrphy_dfi_p1_rddata[58] <= k7ddrphy_bitslip262[3]; - k7ddrphy_dfi_p1_rddata[27] <= k7ddrphy_bitslip272[2]; - k7ddrphy_dfi_p1_rddata[59] <= k7ddrphy_bitslip272[3]; - k7ddrphy_dfi_p1_rddata[28] <= k7ddrphy_bitslip282[2]; - k7ddrphy_dfi_p1_rddata[60] <= k7ddrphy_bitslip282[3]; - k7ddrphy_dfi_p1_rddata[29] <= k7ddrphy_bitslip292[2]; - k7ddrphy_dfi_p1_rddata[61] <= k7ddrphy_bitslip292[3]; - k7ddrphy_dfi_p1_rddata[30] <= k7ddrphy_bitslip302[2]; - k7ddrphy_dfi_p1_rddata[62] <= k7ddrphy_bitslip302[3]; - k7ddrphy_dfi_p1_rddata[31] <= k7ddrphy_bitslip312[2]; - k7ddrphy_dfi_p1_rddata[63] <= k7ddrphy_bitslip312[3]; -end -always @(*) begin - k7ddrphy_dfi_p2_rddata <= 64'd0; - k7ddrphy_dfi_p2_rddata[0] <= k7ddrphy_bitslip04[4]; - k7ddrphy_dfi_p2_rddata[32] <= k7ddrphy_bitslip04[5]; - k7ddrphy_dfi_p2_rddata[1] <= k7ddrphy_bitslip14[4]; - k7ddrphy_dfi_p2_rddata[33] <= k7ddrphy_bitslip14[5]; - k7ddrphy_dfi_p2_rddata[2] <= k7ddrphy_bitslip24[4]; - k7ddrphy_dfi_p2_rddata[34] <= k7ddrphy_bitslip24[5]; - k7ddrphy_dfi_p2_rddata[3] <= k7ddrphy_bitslip34[4]; - k7ddrphy_dfi_p2_rddata[35] <= k7ddrphy_bitslip34[5]; - k7ddrphy_dfi_p2_rddata[4] <= k7ddrphy_bitslip42[4]; - k7ddrphy_dfi_p2_rddata[36] <= k7ddrphy_bitslip42[5]; - k7ddrphy_dfi_p2_rddata[5] <= k7ddrphy_bitslip52[4]; - k7ddrphy_dfi_p2_rddata[37] <= k7ddrphy_bitslip52[5]; - k7ddrphy_dfi_p2_rddata[6] <= k7ddrphy_bitslip62[4]; - k7ddrphy_dfi_p2_rddata[38] <= k7ddrphy_bitslip62[5]; - k7ddrphy_dfi_p2_rddata[7] <= k7ddrphy_bitslip72[4]; - k7ddrphy_dfi_p2_rddata[39] <= k7ddrphy_bitslip72[5]; - k7ddrphy_dfi_p2_rddata[8] <= k7ddrphy_bitslip82[4]; - k7ddrphy_dfi_p2_rddata[40] <= k7ddrphy_bitslip82[5]; - k7ddrphy_dfi_p2_rddata[9] <= k7ddrphy_bitslip92[4]; - k7ddrphy_dfi_p2_rddata[41] <= k7ddrphy_bitslip92[5]; - k7ddrphy_dfi_p2_rddata[10] <= k7ddrphy_bitslip102[4]; - k7ddrphy_dfi_p2_rddata[42] <= k7ddrphy_bitslip102[5]; - k7ddrphy_dfi_p2_rddata[11] <= k7ddrphy_bitslip112[4]; - k7ddrphy_dfi_p2_rddata[43] <= k7ddrphy_bitslip112[5]; - k7ddrphy_dfi_p2_rddata[12] <= k7ddrphy_bitslip122[4]; - k7ddrphy_dfi_p2_rddata[44] <= k7ddrphy_bitslip122[5]; - k7ddrphy_dfi_p2_rddata[13] <= k7ddrphy_bitslip132[4]; - k7ddrphy_dfi_p2_rddata[45] <= k7ddrphy_bitslip132[5]; - k7ddrphy_dfi_p2_rddata[14] <= k7ddrphy_bitslip142[4]; - k7ddrphy_dfi_p2_rddata[46] <= k7ddrphy_bitslip142[5]; - k7ddrphy_dfi_p2_rddata[15] <= k7ddrphy_bitslip152[4]; - k7ddrphy_dfi_p2_rddata[47] <= k7ddrphy_bitslip152[5]; - k7ddrphy_dfi_p2_rddata[16] <= k7ddrphy_bitslip162[4]; - k7ddrphy_dfi_p2_rddata[48] <= k7ddrphy_bitslip162[5]; - k7ddrphy_dfi_p2_rddata[17] <= k7ddrphy_bitslip172[4]; - k7ddrphy_dfi_p2_rddata[49] <= k7ddrphy_bitslip172[5]; - k7ddrphy_dfi_p2_rddata[18] <= k7ddrphy_bitslip182[4]; - k7ddrphy_dfi_p2_rddata[50] <= k7ddrphy_bitslip182[5]; - k7ddrphy_dfi_p2_rddata[19] <= k7ddrphy_bitslip192[4]; - k7ddrphy_dfi_p2_rddata[51] <= k7ddrphy_bitslip192[5]; - k7ddrphy_dfi_p2_rddata[20] <= k7ddrphy_bitslip202[4]; - k7ddrphy_dfi_p2_rddata[52] <= k7ddrphy_bitslip202[5]; - k7ddrphy_dfi_p2_rddata[21] <= k7ddrphy_bitslip212[4]; - k7ddrphy_dfi_p2_rddata[53] <= k7ddrphy_bitslip212[5]; - k7ddrphy_dfi_p2_rddata[22] <= k7ddrphy_bitslip222[4]; - k7ddrphy_dfi_p2_rddata[54] <= k7ddrphy_bitslip222[5]; - k7ddrphy_dfi_p2_rddata[23] <= k7ddrphy_bitslip232[4]; - k7ddrphy_dfi_p2_rddata[55] <= k7ddrphy_bitslip232[5]; - k7ddrphy_dfi_p2_rddata[24] <= k7ddrphy_bitslip242[4]; - k7ddrphy_dfi_p2_rddata[56] <= k7ddrphy_bitslip242[5]; - k7ddrphy_dfi_p2_rddata[25] <= k7ddrphy_bitslip252[4]; - k7ddrphy_dfi_p2_rddata[57] <= k7ddrphy_bitslip252[5]; - k7ddrphy_dfi_p2_rddata[26] <= k7ddrphy_bitslip262[4]; - k7ddrphy_dfi_p2_rddata[58] <= k7ddrphy_bitslip262[5]; - k7ddrphy_dfi_p2_rddata[27] <= k7ddrphy_bitslip272[4]; - k7ddrphy_dfi_p2_rddata[59] <= k7ddrphy_bitslip272[5]; - k7ddrphy_dfi_p2_rddata[28] <= k7ddrphy_bitslip282[4]; - k7ddrphy_dfi_p2_rddata[60] <= k7ddrphy_bitslip282[5]; - k7ddrphy_dfi_p2_rddata[29] <= k7ddrphy_bitslip292[4]; - k7ddrphy_dfi_p2_rddata[61] <= k7ddrphy_bitslip292[5]; - k7ddrphy_dfi_p2_rddata[30] <= k7ddrphy_bitslip302[4]; - k7ddrphy_dfi_p2_rddata[62] <= k7ddrphy_bitslip302[5]; - k7ddrphy_dfi_p2_rddata[31] <= k7ddrphy_bitslip312[4]; - k7ddrphy_dfi_p2_rddata[63] <= k7ddrphy_bitslip312[5]; -end -always @(*) begin - k7ddrphy_dfi_p3_rddata <= 64'd0; - k7ddrphy_dfi_p3_rddata[0] <= k7ddrphy_bitslip04[6]; - k7ddrphy_dfi_p3_rddata[32] <= k7ddrphy_bitslip04[7]; - k7ddrphy_dfi_p3_rddata[1] <= k7ddrphy_bitslip14[6]; - k7ddrphy_dfi_p3_rddata[33] <= k7ddrphy_bitslip14[7]; - k7ddrphy_dfi_p3_rddata[2] <= k7ddrphy_bitslip24[6]; - k7ddrphy_dfi_p3_rddata[34] <= k7ddrphy_bitslip24[7]; - k7ddrphy_dfi_p3_rddata[3] <= k7ddrphy_bitslip34[6]; - k7ddrphy_dfi_p3_rddata[35] <= k7ddrphy_bitslip34[7]; - k7ddrphy_dfi_p3_rddata[4] <= k7ddrphy_bitslip42[6]; - k7ddrphy_dfi_p3_rddata[36] <= k7ddrphy_bitslip42[7]; - k7ddrphy_dfi_p3_rddata[5] <= k7ddrphy_bitslip52[6]; - k7ddrphy_dfi_p3_rddata[37] <= k7ddrphy_bitslip52[7]; - k7ddrphy_dfi_p3_rddata[6] <= k7ddrphy_bitslip62[6]; - k7ddrphy_dfi_p3_rddata[38] <= k7ddrphy_bitslip62[7]; - k7ddrphy_dfi_p3_rddata[7] <= k7ddrphy_bitslip72[6]; - k7ddrphy_dfi_p3_rddata[39] <= k7ddrphy_bitslip72[7]; - k7ddrphy_dfi_p3_rddata[8] <= k7ddrphy_bitslip82[6]; - k7ddrphy_dfi_p3_rddata[40] <= k7ddrphy_bitslip82[7]; - k7ddrphy_dfi_p3_rddata[9] <= k7ddrphy_bitslip92[6]; - k7ddrphy_dfi_p3_rddata[41] <= k7ddrphy_bitslip92[7]; - k7ddrphy_dfi_p3_rddata[10] <= k7ddrphy_bitslip102[6]; - k7ddrphy_dfi_p3_rddata[42] <= k7ddrphy_bitslip102[7]; - k7ddrphy_dfi_p3_rddata[11] <= k7ddrphy_bitslip112[6]; - k7ddrphy_dfi_p3_rddata[43] <= k7ddrphy_bitslip112[7]; - k7ddrphy_dfi_p3_rddata[12] <= k7ddrphy_bitslip122[6]; - k7ddrphy_dfi_p3_rddata[44] <= k7ddrphy_bitslip122[7]; - k7ddrphy_dfi_p3_rddata[13] <= k7ddrphy_bitslip132[6]; - k7ddrphy_dfi_p3_rddata[45] <= k7ddrphy_bitslip132[7]; - k7ddrphy_dfi_p3_rddata[14] <= k7ddrphy_bitslip142[6]; - k7ddrphy_dfi_p3_rddata[46] <= k7ddrphy_bitslip142[7]; - k7ddrphy_dfi_p3_rddata[15] <= k7ddrphy_bitslip152[6]; - k7ddrphy_dfi_p3_rddata[47] <= k7ddrphy_bitslip152[7]; - k7ddrphy_dfi_p3_rddata[16] <= k7ddrphy_bitslip162[6]; - k7ddrphy_dfi_p3_rddata[48] <= k7ddrphy_bitslip162[7]; - k7ddrphy_dfi_p3_rddata[17] <= k7ddrphy_bitslip172[6]; - k7ddrphy_dfi_p3_rddata[49] <= k7ddrphy_bitslip172[7]; - k7ddrphy_dfi_p3_rddata[18] <= k7ddrphy_bitslip182[6]; - k7ddrphy_dfi_p3_rddata[50] <= k7ddrphy_bitslip182[7]; - k7ddrphy_dfi_p3_rddata[19] <= k7ddrphy_bitslip192[6]; - k7ddrphy_dfi_p3_rddata[51] <= k7ddrphy_bitslip192[7]; - k7ddrphy_dfi_p3_rddata[20] <= k7ddrphy_bitslip202[6]; - k7ddrphy_dfi_p3_rddata[52] <= k7ddrphy_bitslip202[7]; - k7ddrphy_dfi_p3_rddata[21] <= k7ddrphy_bitslip212[6]; - k7ddrphy_dfi_p3_rddata[53] <= k7ddrphy_bitslip212[7]; - k7ddrphy_dfi_p3_rddata[22] <= k7ddrphy_bitslip222[6]; - k7ddrphy_dfi_p3_rddata[54] <= k7ddrphy_bitslip222[7]; - k7ddrphy_dfi_p3_rddata[23] <= k7ddrphy_bitslip232[6]; - k7ddrphy_dfi_p3_rddata[55] <= k7ddrphy_bitslip232[7]; - k7ddrphy_dfi_p3_rddata[24] <= k7ddrphy_bitslip242[6]; - k7ddrphy_dfi_p3_rddata[56] <= k7ddrphy_bitslip242[7]; - k7ddrphy_dfi_p3_rddata[25] <= k7ddrphy_bitslip252[6]; - k7ddrphy_dfi_p3_rddata[57] <= k7ddrphy_bitslip252[7]; - k7ddrphy_dfi_p3_rddata[26] <= k7ddrphy_bitslip262[6]; - k7ddrphy_dfi_p3_rddata[58] <= k7ddrphy_bitslip262[7]; - k7ddrphy_dfi_p3_rddata[27] <= k7ddrphy_bitslip272[6]; - k7ddrphy_dfi_p3_rddata[59] <= k7ddrphy_bitslip272[7]; - k7ddrphy_dfi_p3_rddata[28] <= k7ddrphy_bitslip282[6]; - k7ddrphy_dfi_p3_rddata[60] <= k7ddrphy_bitslip282[7]; - k7ddrphy_dfi_p3_rddata[29] <= k7ddrphy_bitslip292[6]; - k7ddrphy_dfi_p3_rddata[61] <= k7ddrphy_bitslip292[7]; - k7ddrphy_dfi_p3_rddata[30] <= k7ddrphy_bitslip302[6]; - k7ddrphy_dfi_p3_rddata[62] <= k7ddrphy_bitslip302[7]; - k7ddrphy_dfi_p3_rddata[31] <= k7ddrphy_bitslip312[6]; - k7ddrphy_dfi_p3_rddata[63] <= k7ddrphy_bitslip312[7]; -end -assign k7ddrphy_dfi_p0_rddata_valid = (k7ddrphy_rddata_en_tappeddelayline7 | k7ddrphy_wlevel_en_storage); -assign k7ddrphy_dfi_p1_rddata_valid = (k7ddrphy_rddata_en_tappeddelayline7 | k7ddrphy_wlevel_en_storage); -assign k7ddrphy_dfi_p2_rddata_valid = (k7ddrphy_rddata_en_tappeddelayline7 | k7ddrphy_wlevel_en_storage); -assign k7ddrphy_dfi_p3_rddata_valid = (k7ddrphy_rddata_en_tappeddelayline7 | k7ddrphy_wlevel_en_storage); -assign k7ddrphy_dq_oe = k7ddrphy_wrdata_en_tappeddelayline1; -always @(*) begin - k7ddrphy_dqs_oe <= 1'd0; - if (k7ddrphy_wlevel_en_storage) begin - k7ddrphy_dqs_oe <= 1'd1; +assign main_user_enable = 1'd1; +assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable); +assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable); +assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we; +assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr; +assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable); +assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable); +assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we; +assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data; +assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable); +assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable); +assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data; +assign builder_interface0_adr = main_wb_bus_adr; +assign builder_interface0_dat_w = main_wb_bus_dat_w; +assign main_wb_bus_dat_r = builder_interface0_dat_r; +assign builder_interface0_sel = main_wb_bus_sel; +assign builder_interface0_cyc = main_wb_bus_cyc; +assign builder_interface0_stb = main_wb_bus_stb; +assign main_wb_bus_ack = builder_interface0_ack; +assign builder_interface0_we = main_wb_bus_we; +assign builder_interface0_cti = main_wb_bus_cti; +assign builder_interface0_bte = main_wb_bus_bte; +assign main_wb_bus_err = builder_interface0_err; +assign main_reset = (rst | main_rst); +assign pll_locked = main_locked; +assign main_clkin = clk; +assign iodelay_clk = main_clkout_buf0; +assign sys_clk = main_clkout_buf1; +assign sys4x_clk = main_clkout_buf2; +assign sys4x_dqs_clk = main_clkout_buf3; +assign ddram_ba = main_k7ddrphy_pads_ba; +assign main_k7ddrphy_dqs_oe_delay_tappeddelayline = ((main_k7ddrphy_dqs_preamble | main_k7ddrphy_dqs_oe) | main_k7ddrphy_dqs_postamble); +assign main_k7ddrphy_dq_oe_delay_tappeddelayline = ((main_k7ddrphy_dqs_preamble | main_k7ddrphy_dq_oe) | main_k7ddrphy_dqs_postamble); +always @(*) begin + main_k7ddrphy_dfi_p0_rddata <= 64'd0; + main_k7ddrphy_dfi_p0_rddata[0] <= main_k7ddrphy_bitslip04[0]; + main_k7ddrphy_dfi_p0_rddata[32] <= main_k7ddrphy_bitslip04[1]; + main_k7ddrphy_dfi_p0_rddata[1] <= main_k7ddrphy_bitslip14[0]; + main_k7ddrphy_dfi_p0_rddata[33] <= main_k7ddrphy_bitslip14[1]; + main_k7ddrphy_dfi_p0_rddata[2] <= main_k7ddrphy_bitslip24[0]; + main_k7ddrphy_dfi_p0_rddata[34] <= main_k7ddrphy_bitslip24[1]; + main_k7ddrphy_dfi_p0_rddata[3] <= main_k7ddrphy_bitslip34[0]; + main_k7ddrphy_dfi_p0_rddata[35] <= main_k7ddrphy_bitslip34[1]; + main_k7ddrphy_dfi_p0_rddata[4] <= main_k7ddrphy_bitslip42[0]; + main_k7ddrphy_dfi_p0_rddata[36] <= main_k7ddrphy_bitslip42[1]; + main_k7ddrphy_dfi_p0_rddata[5] <= main_k7ddrphy_bitslip52[0]; + main_k7ddrphy_dfi_p0_rddata[37] <= main_k7ddrphy_bitslip52[1]; + main_k7ddrphy_dfi_p0_rddata[6] <= main_k7ddrphy_bitslip62[0]; + main_k7ddrphy_dfi_p0_rddata[38] <= main_k7ddrphy_bitslip62[1]; + main_k7ddrphy_dfi_p0_rddata[7] <= main_k7ddrphy_bitslip72[0]; + main_k7ddrphy_dfi_p0_rddata[39] <= main_k7ddrphy_bitslip72[1]; + main_k7ddrphy_dfi_p0_rddata[8] <= main_k7ddrphy_bitslip82[0]; + main_k7ddrphy_dfi_p0_rddata[40] <= main_k7ddrphy_bitslip82[1]; + main_k7ddrphy_dfi_p0_rddata[9] <= main_k7ddrphy_bitslip92[0]; + main_k7ddrphy_dfi_p0_rddata[41] <= main_k7ddrphy_bitslip92[1]; + main_k7ddrphy_dfi_p0_rddata[10] <= main_k7ddrphy_bitslip102[0]; + main_k7ddrphy_dfi_p0_rddata[42] <= main_k7ddrphy_bitslip102[1]; + main_k7ddrphy_dfi_p0_rddata[11] <= main_k7ddrphy_bitslip112[0]; + main_k7ddrphy_dfi_p0_rddata[43] <= main_k7ddrphy_bitslip112[1]; + main_k7ddrphy_dfi_p0_rddata[12] <= main_k7ddrphy_bitslip122[0]; + main_k7ddrphy_dfi_p0_rddata[44] <= main_k7ddrphy_bitslip122[1]; + main_k7ddrphy_dfi_p0_rddata[13] <= main_k7ddrphy_bitslip132[0]; + main_k7ddrphy_dfi_p0_rddata[45] <= main_k7ddrphy_bitslip132[1]; + main_k7ddrphy_dfi_p0_rddata[14] <= main_k7ddrphy_bitslip142[0]; + main_k7ddrphy_dfi_p0_rddata[46] <= main_k7ddrphy_bitslip142[1]; + main_k7ddrphy_dfi_p0_rddata[15] <= main_k7ddrphy_bitslip152[0]; + main_k7ddrphy_dfi_p0_rddata[47] <= main_k7ddrphy_bitslip152[1]; + main_k7ddrphy_dfi_p0_rddata[16] <= main_k7ddrphy_bitslip162[0]; + main_k7ddrphy_dfi_p0_rddata[48] <= main_k7ddrphy_bitslip162[1]; + main_k7ddrphy_dfi_p0_rddata[17] <= main_k7ddrphy_bitslip172[0]; + main_k7ddrphy_dfi_p0_rddata[49] <= main_k7ddrphy_bitslip172[1]; + main_k7ddrphy_dfi_p0_rddata[18] <= main_k7ddrphy_bitslip182[0]; + main_k7ddrphy_dfi_p0_rddata[50] <= main_k7ddrphy_bitslip182[1]; + main_k7ddrphy_dfi_p0_rddata[19] <= main_k7ddrphy_bitslip192[0]; + main_k7ddrphy_dfi_p0_rddata[51] <= main_k7ddrphy_bitslip192[1]; + main_k7ddrphy_dfi_p0_rddata[20] <= main_k7ddrphy_bitslip202[0]; + main_k7ddrphy_dfi_p0_rddata[52] <= main_k7ddrphy_bitslip202[1]; + main_k7ddrphy_dfi_p0_rddata[21] <= main_k7ddrphy_bitslip212[0]; + main_k7ddrphy_dfi_p0_rddata[53] <= main_k7ddrphy_bitslip212[1]; + main_k7ddrphy_dfi_p0_rddata[22] <= main_k7ddrphy_bitslip222[0]; + main_k7ddrphy_dfi_p0_rddata[54] <= main_k7ddrphy_bitslip222[1]; + main_k7ddrphy_dfi_p0_rddata[23] <= main_k7ddrphy_bitslip232[0]; + main_k7ddrphy_dfi_p0_rddata[55] <= main_k7ddrphy_bitslip232[1]; + main_k7ddrphy_dfi_p0_rddata[24] <= main_k7ddrphy_bitslip242[0]; + main_k7ddrphy_dfi_p0_rddata[56] <= main_k7ddrphy_bitslip242[1]; + main_k7ddrphy_dfi_p0_rddata[25] <= main_k7ddrphy_bitslip252[0]; + main_k7ddrphy_dfi_p0_rddata[57] <= main_k7ddrphy_bitslip252[1]; + main_k7ddrphy_dfi_p0_rddata[26] <= main_k7ddrphy_bitslip262[0]; + main_k7ddrphy_dfi_p0_rddata[58] <= main_k7ddrphy_bitslip262[1]; + main_k7ddrphy_dfi_p0_rddata[27] <= main_k7ddrphy_bitslip272[0]; + main_k7ddrphy_dfi_p0_rddata[59] <= main_k7ddrphy_bitslip272[1]; + main_k7ddrphy_dfi_p0_rddata[28] <= main_k7ddrphy_bitslip282[0]; + main_k7ddrphy_dfi_p0_rddata[60] <= main_k7ddrphy_bitslip282[1]; + main_k7ddrphy_dfi_p0_rddata[29] <= main_k7ddrphy_bitslip292[0]; + main_k7ddrphy_dfi_p0_rddata[61] <= main_k7ddrphy_bitslip292[1]; + main_k7ddrphy_dfi_p0_rddata[30] <= main_k7ddrphy_bitslip302[0]; + main_k7ddrphy_dfi_p0_rddata[62] <= main_k7ddrphy_bitslip302[1]; + main_k7ddrphy_dfi_p0_rddata[31] <= main_k7ddrphy_bitslip312[0]; + main_k7ddrphy_dfi_p0_rddata[63] <= main_k7ddrphy_bitslip312[1]; +end +always @(*) begin + main_k7ddrphy_dfi_p1_rddata <= 64'd0; + main_k7ddrphy_dfi_p1_rddata[0] <= main_k7ddrphy_bitslip04[2]; + main_k7ddrphy_dfi_p1_rddata[32] <= main_k7ddrphy_bitslip04[3]; + main_k7ddrphy_dfi_p1_rddata[1] <= main_k7ddrphy_bitslip14[2]; + main_k7ddrphy_dfi_p1_rddata[33] <= main_k7ddrphy_bitslip14[3]; + main_k7ddrphy_dfi_p1_rddata[2] <= main_k7ddrphy_bitslip24[2]; + main_k7ddrphy_dfi_p1_rddata[34] <= main_k7ddrphy_bitslip24[3]; + main_k7ddrphy_dfi_p1_rddata[3] <= main_k7ddrphy_bitslip34[2]; + main_k7ddrphy_dfi_p1_rddata[35] <= main_k7ddrphy_bitslip34[3]; + main_k7ddrphy_dfi_p1_rddata[4] <= main_k7ddrphy_bitslip42[2]; + main_k7ddrphy_dfi_p1_rddata[36] <= main_k7ddrphy_bitslip42[3]; + main_k7ddrphy_dfi_p1_rddata[5] <= main_k7ddrphy_bitslip52[2]; + main_k7ddrphy_dfi_p1_rddata[37] <= main_k7ddrphy_bitslip52[3]; + main_k7ddrphy_dfi_p1_rddata[6] <= main_k7ddrphy_bitslip62[2]; + main_k7ddrphy_dfi_p1_rddata[38] <= main_k7ddrphy_bitslip62[3]; + main_k7ddrphy_dfi_p1_rddata[7] <= main_k7ddrphy_bitslip72[2]; + main_k7ddrphy_dfi_p1_rddata[39] <= main_k7ddrphy_bitslip72[3]; + main_k7ddrphy_dfi_p1_rddata[8] <= main_k7ddrphy_bitslip82[2]; + main_k7ddrphy_dfi_p1_rddata[40] <= main_k7ddrphy_bitslip82[3]; + main_k7ddrphy_dfi_p1_rddata[9] <= main_k7ddrphy_bitslip92[2]; + main_k7ddrphy_dfi_p1_rddata[41] <= main_k7ddrphy_bitslip92[3]; + main_k7ddrphy_dfi_p1_rddata[10] <= main_k7ddrphy_bitslip102[2]; + main_k7ddrphy_dfi_p1_rddata[42] <= main_k7ddrphy_bitslip102[3]; + main_k7ddrphy_dfi_p1_rddata[11] <= main_k7ddrphy_bitslip112[2]; + main_k7ddrphy_dfi_p1_rddata[43] <= main_k7ddrphy_bitslip112[3]; + main_k7ddrphy_dfi_p1_rddata[12] <= main_k7ddrphy_bitslip122[2]; + main_k7ddrphy_dfi_p1_rddata[44] <= main_k7ddrphy_bitslip122[3]; + main_k7ddrphy_dfi_p1_rddata[13] <= main_k7ddrphy_bitslip132[2]; + main_k7ddrphy_dfi_p1_rddata[45] <= main_k7ddrphy_bitslip132[3]; + main_k7ddrphy_dfi_p1_rddata[14] <= main_k7ddrphy_bitslip142[2]; + main_k7ddrphy_dfi_p1_rddata[46] <= main_k7ddrphy_bitslip142[3]; + main_k7ddrphy_dfi_p1_rddata[15] <= main_k7ddrphy_bitslip152[2]; + main_k7ddrphy_dfi_p1_rddata[47] <= main_k7ddrphy_bitslip152[3]; + main_k7ddrphy_dfi_p1_rddata[16] <= main_k7ddrphy_bitslip162[2]; + main_k7ddrphy_dfi_p1_rddata[48] <= main_k7ddrphy_bitslip162[3]; + main_k7ddrphy_dfi_p1_rddata[17] <= main_k7ddrphy_bitslip172[2]; + main_k7ddrphy_dfi_p1_rddata[49] <= main_k7ddrphy_bitslip172[3]; + main_k7ddrphy_dfi_p1_rddata[18] <= main_k7ddrphy_bitslip182[2]; + main_k7ddrphy_dfi_p1_rddata[50] <= main_k7ddrphy_bitslip182[3]; + main_k7ddrphy_dfi_p1_rddata[19] <= main_k7ddrphy_bitslip192[2]; + main_k7ddrphy_dfi_p1_rddata[51] <= main_k7ddrphy_bitslip192[3]; + main_k7ddrphy_dfi_p1_rddata[20] <= main_k7ddrphy_bitslip202[2]; + main_k7ddrphy_dfi_p1_rddata[52] <= main_k7ddrphy_bitslip202[3]; + main_k7ddrphy_dfi_p1_rddata[21] <= main_k7ddrphy_bitslip212[2]; + main_k7ddrphy_dfi_p1_rddata[53] <= main_k7ddrphy_bitslip212[3]; + main_k7ddrphy_dfi_p1_rddata[22] <= main_k7ddrphy_bitslip222[2]; + main_k7ddrphy_dfi_p1_rddata[54] <= main_k7ddrphy_bitslip222[3]; + main_k7ddrphy_dfi_p1_rddata[23] <= main_k7ddrphy_bitslip232[2]; + main_k7ddrphy_dfi_p1_rddata[55] <= main_k7ddrphy_bitslip232[3]; + main_k7ddrphy_dfi_p1_rddata[24] <= main_k7ddrphy_bitslip242[2]; + main_k7ddrphy_dfi_p1_rddata[56] <= main_k7ddrphy_bitslip242[3]; + main_k7ddrphy_dfi_p1_rddata[25] <= main_k7ddrphy_bitslip252[2]; + main_k7ddrphy_dfi_p1_rddata[57] <= main_k7ddrphy_bitslip252[3]; + main_k7ddrphy_dfi_p1_rddata[26] <= main_k7ddrphy_bitslip262[2]; + main_k7ddrphy_dfi_p1_rddata[58] <= main_k7ddrphy_bitslip262[3]; + main_k7ddrphy_dfi_p1_rddata[27] <= main_k7ddrphy_bitslip272[2]; + main_k7ddrphy_dfi_p1_rddata[59] <= main_k7ddrphy_bitslip272[3]; + main_k7ddrphy_dfi_p1_rddata[28] <= main_k7ddrphy_bitslip282[2]; + main_k7ddrphy_dfi_p1_rddata[60] <= main_k7ddrphy_bitslip282[3]; + main_k7ddrphy_dfi_p1_rddata[29] <= main_k7ddrphy_bitslip292[2]; + main_k7ddrphy_dfi_p1_rddata[61] <= main_k7ddrphy_bitslip292[3]; + main_k7ddrphy_dfi_p1_rddata[30] <= main_k7ddrphy_bitslip302[2]; + main_k7ddrphy_dfi_p1_rddata[62] <= main_k7ddrphy_bitslip302[3]; + main_k7ddrphy_dfi_p1_rddata[31] <= main_k7ddrphy_bitslip312[2]; + main_k7ddrphy_dfi_p1_rddata[63] <= main_k7ddrphy_bitslip312[3]; +end +always @(*) begin + main_k7ddrphy_dfi_p2_rddata <= 64'd0; + main_k7ddrphy_dfi_p2_rddata[0] <= main_k7ddrphy_bitslip04[4]; + main_k7ddrphy_dfi_p2_rddata[32] <= main_k7ddrphy_bitslip04[5]; + main_k7ddrphy_dfi_p2_rddata[1] <= main_k7ddrphy_bitslip14[4]; + main_k7ddrphy_dfi_p2_rddata[33] <= main_k7ddrphy_bitslip14[5]; + main_k7ddrphy_dfi_p2_rddata[2] <= main_k7ddrphy_bitslip24[4]; + main_k7ddrphy_dfi_p2_rddata[34] <= main_k7ddrphy_bitslip24[5]; + main_k7ddrphy_dfi_p2_rddata[3] <= main_k7ddrphy_bitslip34[4]; + main_k7ddrphy_dfi_p2_rddata[35] <= main_k7ddrphy_bitslip34[5]; + main_k7ddrphy_dfi_p2_rddata[4] <= main_k7ddrphy_bitslip42[4]; + main_k7ddrphy_dfi_p2_rddata[36] <= main_k7ddrphy_bitslip42[5]; + main_k7ddrphy_dfi_p2_rddata[5] <= main_k7ddrphy_bitslip52[4]; + main_k7ddrphy_dfi_p2_rddata[37] <= main_k7ddrphy_bitslip52[5]; + main_k7ddrphy_dfi_p2_rddata[6] <= main_k7ddrphy_bitslip62[4]; + main_k7ddrphy_dfi_p2_rddata[38] <= main_k7ddrphy_bitslip62[5]; + main_k7ddrphy_dfi_p2_rddata[7] <= main_k7ddrphy_bitslip72[4]; + main_k7ddrphy_dfi_p2_rddata[39] <= main_k7ddrphy_bitslip72[5]; + main_k7ddrphy_dfi_p2_rddata[8] <= main_k7ddrphy_bitslip82[4]; + main_k7ddrphy_dfi_p2_rddata[40] <= main_k7ddrphy_bitslip82[5]; + main_k7ddrphy_dfi_p2_rddata[9] <= main_k7ddrphy_bitslip92[4]; + main_k7ddrphy_dfi_p2_rddata[41] <= main_k7ddrphy_bitslip92[5]; + main_k7ddrphy_dfi_p2_rddata[10] <= main_k7ddrphy_bitslip102[4]; + main_k7ddrphy_dfi_p2_rddata[42] <= main_k7ddrphy_bitslip102[5]; + main_k7ddrphy_dfi_p2_rddata[11] <= main_k7ddrphy_bitslip112[4]; + main_k7ddrphy_dfi_p2_rddata[43] <= main_k7ddrphy_bitslip112[5]; + main_k7ddrphy_dfi_p2_rddata[12] <= main_k7ddrphy_bitslip122[4]; + main_k7ddrphy_dfi_p2_rddata[44] <= main_k7ddrphy_bitslip122[5]; + main_k7ddrphy_dfi_p2_rddata[13] <= main_k7ddrphy_bitslip132[4]; + main_k7ddrphy_dfi_p2_rddata[45] <= main_k7ddrphy_bitslip132[5]; + main_k7ddrphy_dfi_p2_rddata[14] <= main_k7ddrphy_bitslip142[4]; + main_k7ddrphy_dfi_p2_rddata[46] <= main_k7ddrphy_bitslip142[5]; + main_k7ddrphy_dfi_p2_rddata[15] <= main_k7ddrphy_bitslip152[4]; + main_k7ddrphy_dfi_p2_rddata[47] <= main_k7ddrphy_bitslip152[5]; + main_k7ddrphy_dfi_p2_rddata[16] <= main_k7ddrphy_bitslip162[4]; + main_k7ddrphy_dfi_p2_rddata[48] <= main_k7ddrphy_bitslip162[5]; + main_k7ddrphy_dfi_p2_rddata[17] <= main_k7ddrphy_bitslip172[4]; + main_k7ddrphy_dfi_p2_rddata[49] <= main_k7ddrphy_bitslip172[5]; + main_k7ddrphy_dfi_p2_rddata[18] <= main_k7ddrphy_bitslip182[4]; + main_k7ddrphy_dfi_p2_rddata[50] <= main_k7ddrphy_bitslip182[5]; + main_k7ddrphy_dfi_p2_rddata[19] <= main_k7ddrphy_bitslip192[4]; + main_k7ddrphy_dfi_p2_rddata[51] <= main_k7ddrphy_bitslip192[5]; + main_k7ddrphy_dfi_p2_rddata[20] <= main_k7ddrphy_bitslip202[4]; + main_k7ddrphy_dfi_p2_rddata[52] <= main_k7ddrphy_bitslip202[5]; + main_k7ddrphy_dfi_p2_rddata[21] <= main_k7ddrphy_bitslip212[4]; + main_k7ddrphy_dfi_p2_rddata[53] <= main_k7ddrphy_bitslip212[5]; + main_k7ddrphy_dfi_p2_rddata[22] <= main_k7ddrphy_bitslip222[4]; + main_k7ddrphy_dfi_p2_rddata[54] <= main_k7ddrphy_bitslip222[5]; + main_k7ddrphy_dfi_p2_rddata[23] <= main_k7ddrphy_bitslip232[4]; + main_k7ddrphy_dfi_p2_rddata[55] <= main_k7ddrphy_bitslip232[5]; + main_k7ddrphy_dfi_p2_rddata[24] <= main_k7ddrphy_bitslip242[4]; + main_k7ddrphy_dfi_p2_rddata[56] <= main_k7ddrphy_bitslip242[5]; + main_k7ddrphy_dfi_p2_rddata[25] <= main_k7ddrphy_bitslip252[4]; + main_k7ddrphy_dfi_p2_rddata[57] <= main_k7ddrphy_bitslip252[5]; + main_k7ddrphy_dfi_p2_rddata[26] <= main_k7ddrphy_bitslip262[4]; + main_k7ddrphy_dfi_p2_rddata[58] <= main_k7ddrphy_bitslip262[5]; + main_k7ddrphy_dfi_p2_rddata[27] <= main_k7ddrphy_bitslip272[4]; + main_k7ddrphy_dfi_p2_rddata[59] <= main_k7ddrphy_bitslip272[5]; + main_k7ddrphy_dfi_p2_rddata[28] <= main_k7ddrphy_bitslip282[4]; + main_k7ddrphy_dfi_p2_rddata[60] <= main_k7ddrphy_bitslip282[5]; + main_k7ddrphy_dfi_p2_rddata[29] <= main_k7ddrphy_bitslip292[4]; + main_k7ddrphy_dfi_p2_rddata[61] <= main_k7ddrphy_bitslip292[5]; + main_k7ddrphy_dfi_p2_rddata[30] <= main_k7ddrphy_bitslip302[4]; + main_k7ddrphy_dfi_p2_rddata[62] <= main_k7ddrphy_bitslip302[5]; + main_k7ddrphy_dfi_p2_rddata[31] <= main_k7ddrphy_bitslip312[4]; + main_k7ddrphy_dfi_p2_rddata[63] <= main_k7ddrphy_bitslip312[5]; +end +always @(*) begin + main_k7ddrphy_dfi_p3_rddata <= 64'd0; + main_k7ddrphy_dfi_p3_rddata[0] <= main_k7ddrphy_bitslip04[6]; + main_k7ddrphy_dfi_p3_rddata[32] <= main_k7ddrphy_bitslip04[7]; + main_k7ddrphy_dfi_p3_rddata[1] <= main_k7ddrphy_bitslip14[6]; + main_k7ddrphy_dfi_p3_rddata[33] <= main_k7ddrphy_bitslip14[7]; + main_k7ddrphy_dfi_p3_rddata[2] <= main_k7ddrphy_bitslip24[6]; + main_k7ddrphy_dfi_p3_rddata[34] <= main_k7ddrphy_bitslip24[7]; + main_k7ddrphy_dfi_p3_rddata[3] <= main_k7ddrphy_bitslip34[6]; + main_k7ddrphy_dfi_p3_rddata[35] <= main_k7ddrphy_bitslip34[7]; + main_k7ddrphy_dfi_p3_rddata[4] <= main_k7ddrphy_bitslip42[6]; + main_k7ddrphy_dfi_p3_rddata[36] <= main_k7ddrphy_bitslip42[7]; + main_k7ddrphy_dfi_p3_rddata[5] <= main_k7ddrphy_bitslip52[6]; + main_k7ddrphy_dfi_p3_rddata[37] <= main_k7ddrphy_bitslip52[7]; + main_k7ddrphy_dfi_p3_rddata[6] <= main_k7ddrphy_bitslip62[6]; + main_k7ddrphy_dfi_p3_rddata[38] <= main_k7ddrphy_bitslip62[7]; + main_k7ddrphy_dfi_p3_rddata[7] <= main_k7ddrphy_bitslip72[6]; + main_k7ddrphy_dfi_p3_rddata[39] <= main_k7ddrphy_bitslip72[7]; + main_k7ddrphy_dfi_p3_rddata[8] <= main_k7ddrphy_bitslip82[6]; + main_k7ddrphy_dfi_p3_rddata[40] <= main_k7ddrphy_bitslip82[7]; + main_k7ddrphy_dfi_p3_rddata[9] <= main_k7ddrphy_bitslip92[6]; + main_k7ddrphy_dfi_p3_rddata[41] <= main_k7ddrphy_bitslip92[7]; + main_k7ddrphy_dfi_p3_rddata[10] <= main_k7ddrphy_bitslip102[6]; + main_k7ddrphy_dfi_p3_rddata[42] <= main_k7ddrphy_bitslip102[7]; + main_k7ddrphy_dfi_p3_rddata[11] <= main_k7ddrphy_bitslip112[6]; + main_k7ddrphy_dfi_p3_rddata[43] <= main_k7ddrphy_bitslip112[7]; + main_k7ddrphy_dfi_p3_rddata[12] <= main_k7ddrphy_bitslip122[6]; + main_k7ddrphy_dfi_p3_rddata[44] <= main_k7ddrphy_bitslip122[7]; + main_k7ddrphy_dfi_p3_rddata[13] <= main_k7ddrphy_bitslip132[6]; + main_k7ddrphy_dfi_p3_rddata[45] <= main_k7ddrphy_bitslip132[7]; + main_k7ddrphy_dfi_p3_rddata[14] <= main_k7ddrphy_bitslip142[6]; + main_k7ddrphy_dfi_p3_rddata[46] <= main_k7ddrphy_bitslip142[7]; + main_k7ddrphy_dfi_p3_rddata[15] <= main_k7ddrphy_bitslip152[6]; + main_k7ddrphy_dfi_p3_rddata[47] <= main_k7ddrphy_bitslip152[7]; + main_k7ddrphy_dfi_p3_rddata[16] <= main_k7ddrphy_bitslip162[6]; + main_k7ddrphy_dfi_p3_rddata[48] <= main_k7ddrphy_bitslip162[7]; + main_k7ddrphy_dfi_p3_rddata[17] <= main_k7ddrphy_bitslip172[6]; + main_k7ddrphy_dfi_p3_rddata[49] <= main_k7ddrphy_bitslip172[7]; + main_k7ddrphy_dfi_p3_rddata[18] <= main_k7ddrphy_bitslip182[6]; + main_k7ddrphy_dfi_p3_rddata[50] <= main_k7ddrphy_bitslip182[7]; + main_k7ddrphy_dfi_p3_rddata[19] <= main_k7ddrphy_bitslip192[6]; + main_k7ddrphy_dfi_p3_rddata[51] <= main_k7ddrphy_bitslip192[7]; + main_k7ddrphy_dfi_p3_rddata[20] <= main_k7ddrphy_bitslip202[6]; + main_k7ddrphy_dfi_p3_rddata[52] <= main_k7ddrphy_bitslip202[7]; + main_k7ddrphy_dfi_p3_rddata[21] <= main_k7ddrphy_bitslip212[6]; + main_k7ddrphy_dfi_p3_rddata[53] <= main_k7ddrphy_bitslip212[7]; + main_k7ddrphy_dfi_p3_rddata[22] <= main_k7ddrphy_bitslip222[6]; + main_k7ddrphy_dfi_p3_rddata[54] <= main_k7ddrphy_bitslip222[7]; + main_k7ddrphy_dfi_p3_rddata[23] <= main_k7ddrphy_bitslip232[6]; + main_k7ddrphy_dfi_p3_rddata[55] <= main_k7ddrphy_bitslip232[7]; + main_k7ddrphy_dfi_p3_rddata[24] <= main_k7ddrphy_bitslip242[6]; + main_k7ddrphy_dfi_p3_rddata[56] <= main_k7ddrphy_bitslip242[7]; + main_k7ddrphy_dfi_p3_rddata[25] <= main_k7ddrphy_bitslip252[6]; + main_k7ddrphy_dfi_p3_rddata[57] <= main_k7ddrphy_bitslip252[7]; + main_k7ddrphy_dfi_p3_rddata[26] <= main_k7ddrphy_bitslip262[6]; + main_k7ddrphy_dfi_p3_rddata[58] <= main_k7ddrphy_bitslip262[7]; + main_k7ddrphy_dfi_p3_rddata[27] <= main_k7ddrphy_bitslip272[6]; + main_k7ddrphy_dfi_p3_rddata[59] <= main_k7ddrphy_bitslip272[7]; + main_k7ddrphy_dfi_p3_rddata[28] <= main_k7ddrphy_bitslip282[6]; + main_k7ddrphy_dfi_p3_rddata[60] <= main_k7ddrphy_bitslip282[7]; + main_k7ddrphy_dfi_p3_rddata[29] <= main_k7ddrphy_bitslip292[6]; + main_k7ddrphy_dfi_p3_rddata[61] <= main_k7ddrphy_bitslip292[7]; + main_k7ddrphy_dfi_p3_rddata[30] <= main_k7ddrphy_bitslip302[6]; + main_k7ddrphy_dfi_p3_rddata[62] <= main_k7ddrphy_bitslip302[7]; + main_k7ddrphy_dfi_p3_rddata[31] <= main_k7ddrphy_bitslip312[6]; + main_k7ddrphy_dfi_p3_rddata[63] <= main_k7ddrphy_bitslip312[7]; +end +assign main_k7ddrphy_dfi_p0_rddata_valid = (main_k7ddrphy_rddata_en_tappeddelayline7 | main_k7ddrphy_wlevel_en_storage); +assign main_k7ddrphy_dfi_p1_rddata_valid = (main_k7ddrphy_rddata_en_tappeddelayline7 | main_k7ddrphy_wlevel_en_storage); +assign main_k7ddrphy_dfi_p2_rddata_valid = (main_k7ddrphy_rddata_en_tappeddelayline7 | main_k7ddrphy_wlevel_en_storage); +assign main_k7ddrphy_dfi_p3_rddata_valid = (main_k7ddrphy_rddata_en_tappeddelayline7 | main_k7ddrphy_wlevel_en_storage); +assign main_k7ddrphy_dq_oe = main_k7ddrphy_wrdata_en_tappeddelayline1; +always @(*) begin + main_k7ddrphy_dqs_oe <= 1'd0; + if (main_k7ddrphy_wlevel_en_storage) begin + main_k7ddrphy_dqs_oe <= 1'd1; end else begin - k7ddrphy_dqs_oe <= k7ddrphy_dq_oe; + main_k7ddrphy_dqs_oe <= main_k7ddrphy_dq_oe; end end -assign k7ddrphy_dqs_preamble = (k7ddrphy_wrdata_en_tappeddelayline0 & (~k7ddrphy_wrdata_en_tappeddelayline1)); -assign k7ddrphy_dqs_postamble = (k7ddrphy_wrdata_en_tappeddelayline2 & (~k7ddrphy_wrdata_en_tappeddelayline1)); +assign main_k7ddrphy_dqs_preamble = (main_k7ddrphy_wrdata_en_tappeddelayline0 & (~main_k7ddrphy_wrdata_en_tappeddelayline1)); +assign main_k7ddrphy_dqs_postamble = (main_k7ddrphy_wrdata_en_tappeddelayline2 & (~main_k7ddrphy_wrdata_en_tappeddelayline1)); always @(*) begin - k7ddrphy_dqspattern_o <= 8'd0; - k7ddrphy_dqspattern_o <= 7'd85; - if (k7ddrphy_dqspattern0) begin - k7ddrphy_dqspattern_o <= 5'd21; + main_k7ddrphy_dqspattern_o <= 8'd0; + main_k7ddrphy_dqspattern_o <= 7'd85; + if (main_k7ddrphy_dqspattern0) begin + main_k7ddrphy_dqspattern_o <= 5'd21; end - if (k7ddrphy_dqspattern1) begin - k7ddrphy_dqspattern_o <= 7'd84; + if (main_k7ddrphy_dqspattern1) begin + main_k7ddrphy_dqspattern_o <= 7'd84; end - if (k7ddrphy_wlevel_en_storage) begin - k7ddrphy_dqspattern_o <= 1'd0; - if (k7ddrphy_wlevel_strobe_re) begin - k7ddrphy_dqspattern_o <= 1'd1; + if (main_k7ddrphy_wlevel_en_storage) begin + main_k7ddrphy_dqspattern_o <= 1'd0; + if (main_k7ddrphy_wlevel_strobe_re) begin + main_k7ddrphy_dqspattern_o <= 1'd1; end end end always @(*) begin - k7ddrphy_bitslip00 <= 8'd0; - case (k7ddrphy_bitslip0_value0) + main_k7ddrphy_bitslip00 <= 8'd0; + case (main_k7ddrphy_bitslip0_value0) 1'd0: begin - k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[8:1]; + main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[9:2]; + main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[10:3]; + main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[11:4]; + main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[12:5]; + main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[13:6]; + main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[14:7]; + main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[15:8]; + main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip10 <= 8'd0; - case (k7ddrphy_bitslip1_value0) + main_k7ddrphy_bitslip10 <= 8'd0; + case (main_k7ddrphy_bitslip1_value0) 1'd0: begin - k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[8:1]; + main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[9:2]; + main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[10:3]; + main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[11:4]; + main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[12:5]; + main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[13:6]; + main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[14:7]; + main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[15:8]; + main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip20 <= 8'd0; - case (k7ddrphy_bitslip2_value0) + main_k7ddrphy_bitslip20 <= 8'd0; + case (main_k7ddrphy_bitslip2_value0) 1'd0: begin - k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[8:1]; + main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[9:2]; + main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[10:3]; + main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[11:4]; + main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[12:5]; + main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[13:6]; + main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[14:7]; + main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[15:8]; + main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip30 <= 8'd0; - case (k7ddrphy_bitslip3_value0) + main_k7ddrphy_bitslip30 <= 8'd0; + case (main_k7ddrphy_bitslip3_value0) 1'd0: begin - k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[8:1]; + main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[9:2]; + main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[10:3]; + main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[11:4]; + main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[12:5]; + main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[13:6]; + main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[14:7]; + main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[15:8]; + main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip01 <= 8'd0; - case (k7ddrphy_bitslip0_value1) + main_k7ddrphy_bitslip01 <= 8'd0; + case (main_k7ddrphy_bitslip0_value1) 1'd0: begin - k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[8:1]; + main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[9:2]; + main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[10:3]; + main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[11:4]; + main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[12:5]; + main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[13:6]; + main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[14:7]; + main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[15:8]; + main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip11 <= 8'd0; - case (k7ddrphy_bitslip1_value1) + main_k7ddrphy_bitslip11 <= 8'd0; + case (main_k7ddrphy_bitslip1_value1) 1'd0: begin - k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[8:1]; + main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[9:2]; + main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[10:3]; + main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[11:4]; + main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[12:5]; + main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[13:6]; + main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[14:7]; + main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[15:8]; + main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip21 <= 8'd0; - case (k7ddrphy_bitslip2_value1) + main_k7ddrphy_bitslip21 <= 8'd0; + case (main_k7ddrphy_bitslip2_value1) 1'd0: begin - k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[8:1]; + main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[9:2]; + main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[10:3]; + main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[11:4]; + main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[12:5]; + main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[13:6]; + main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[14:7]; + main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[15:8]; + main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip31 <= 8'd0; - case (k7ddrphy_bitslip3_value1) + main_k7ddrphy_bitslip31 <= 8'd0; + case (main_k7ddrphy_bitslip3_value1) 1'd0: begin - k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[8:1]; + main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[9:2]; + main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[10:3]; + main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[11:4]; + main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[12:5]; + main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[13:6]; + main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[14:7]; + main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[15:8]; + main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip02 <= 8'd0; - case (k7ddrphy_bitslip0_value2) + main_k7ddrphy_bitslip02 <= 8'd0; + case (main_k7ddrphy_bitslip0_value2) 1'd0: begin - k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[8:1]; + main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[8:1]; end 1'd1: begin - k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[9:2]; + main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[9:2]; end 2'd2: begin - k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[10:3]; + main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[10:3]; end 2'd3: begin - k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[11:4]; + main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[11:4]; end 3'd4: begin - k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[12:5]; + main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[12:5]; end 3'd5: begin - k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[13:6]; + main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[13:6]; end 3'd6: begin - k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[14:7]; + main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[14:7]; end 3'd7: begin - k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[15:8]; + main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip04 <= 8'd0; - case (k7ddrphy_bitslip0_value3) + main_k7ddrphy_bitslip04 <= 8'd0; + case (main_k7ddrphy_bitslip0_value3) 1'd0: begin - k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[8:1]; + main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[8:1]; end 1'd1: begin - k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[9:2]; + main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[9:2]; end 2'd2: begin - k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[10:3]; + main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[10:3]; end 2'd3: begin - k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[11:4]; + main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[11:4]; end 3'd4: begin - k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[12:5]; + main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[12:5]; end 3'd5: begin - k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[13:6]; + main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[13:6]; end 3'd6: begin - k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[14:7]; + main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[14:7]; end 3'd7: begin - k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[15:8]; + main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip12 <= 8'd0; - case (k7ddrphy_bitslip1_value2) + main_k7ddrphy_bitslip12 <= 8'd0; + case (main_k7ddrphy_bitslip1_value2) 1'd0: begin - k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[8:1]; + main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[8:1]; end 1'd1: begin - k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[9:2]; + main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[9:2]; end 2'd2: begin - k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[10:3]; + main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[10:3]; end 2'd3: begin - k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[11:4]; + main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[11:4]; end 3'd4: begin - k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[12:5]; + main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[12:5]; end 3'd5: begin - k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[13:6]; + main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[13:6]; end 3'd6: begin - k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[14:7]; + main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[14:7]; end 3'd7: begin - k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[15:8]; + main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip14 <= 8'd0; - case (k7ddrphy_bitslip1_value3) + main_k7ddrphy_bitslip14 <= 8'd0; + case (main_k7ddrphy_bitslip1_value3) 1'd0: begin - k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[8:1]; + main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[8:1]; end 1'd1: begin - k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[9:2]; + main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[9:2]; end 2'd2: begin - k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[10:3]; + main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[10:3]; end 2'd3: begin - k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[11:4]; + main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[11:4]; end 3'd4: begin - k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[12:5]; + main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[12:5]; end 3'd5: begin - k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[13:6]; + main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[13:6]; end 3'd6: begin - k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[14:7]; + main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[14:7]; end 3'd7: begin - k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[15:8]; + main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip22 <= 8'd0; - case (k7ddrphy_bitslip2_value2) + main_k7ddrphy_bitslip22 <= 8'd0; + case (main_k7ddrphy_bitslip2_value2) 1'd0: begin - k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[8:1]; + main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[8:1]; end 1'd1: begin - k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[9:2]; + main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[9:2]; end 2'd2: begin - k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[10:3]; + main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[10:3]; end 2'd3: begin - k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[11:4]; + main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[11:4]; end 3'd4: begin - k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[12:5]; + main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[12:5]; end 3'd5: begin - k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[13:6]; + main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[13:6]; end 3'd6: begin - k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[14:7]; + main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[14:7]; end 3'd7: begin - k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[15:8]; + main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip24 <= 8'd0; - case (k7ddrphy_bitslip2_value3) + main_k7ddrphy_bitslip24 <= 8'd0; + case (main_k7ddrphy_bitslip2_value3) 1'd0: begin - k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[8:1]; + main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[8:1]; end 1'd1: begin - k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[9:2]; + main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[9:2]; end 2'd2: begin - k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[10:3]; + main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[10:3]; end 2'd3: begin - k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[11:4]; + main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[11:4]; end 3'd4: begin - k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[12:5]; + main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[12:5]; end 3'd5: begin - k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[13:6]; + main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[13:6]; end 3'd6: begin - k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[14:7]; + main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[14:7]; end 3'd7: begin - k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[15:8]; + main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip32 <= 8'd0; - case (k7ddrphy_bitslip3_value2) + main_k7ddrphy_bitslip32 <= 8'd0; + case (main_k7ddrphy_bitslip3_value2) 1'd0: begin - k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[8:1]; + main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[8:1]; end 1'd1: begin - k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[9:2]; + main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[9:2]; end 2'd2: begin - k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[10:3]; + main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[10:3]; end 2'd3: begin - k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[11:4]; + main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[11:4]; end 3'd4: begin - k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[12:5]; + main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[12:5]; end 3'd5: begin - k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[13:6]; + main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[13:6]; end 3'd6: begin - k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[14:7]; + main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[14:7]; end 3'd7: begin - k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[15:8]; + main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip34 <= 8'd0; - case (k7ddrphy_bitslip3_value3) + main_k7ddrphy_bitslip34 <= 8'd0; + case (main_k7ddrphy_bitslip3_value3) 1'd0: begin - k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[8:1]; + main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[8:1]; end 1'd1: begin - k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[9:2]; + main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[9:2]; end 2'd2: begin - k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[10:3]; + main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[10:3]; end 2'd3: begin - k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[11:4]; + main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[11:4]; end 3'd4: begin - k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[12:5]; + main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[12:5]; end 3'd5: begin - k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[13:6]; + main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[13:6]; end 3'd6: begin - k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[14:7]; + main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[14:7]; end 3'd7: begin - k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[15:8]; + main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip40 <= 8'd0; - case (k7ddrphy_bitslip4_value0) + main_k7ddrphy_bitslip40 <= 8'd0; + case (main_k7ddrphy_bitslip4_value0) 1'd0: begin - k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[8:1]; + main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[9:2]; + main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[10:3]; + main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[11:4]; + main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[12:5]; + main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[13:6]; + main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[14:7]; + main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[15:8]; + main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip42 <= 8'd0; - case (k7ddrphy_bitslip4_value1) + main_k7ddrphy_bitslip42 <= 8'd0; + case (main_k7ddrphy_bitslip4_value1) 1'd0: begin - k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[8:1]; + main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[9:2]; + main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[10:3]; + main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[11:4]; + main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[12:5]; + main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[13:6]; + main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[14:7]; + main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[15:8]; + main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip50 <= 8'd0; - case (k7ddrphy_bitslip5_value0) + main_k7ddrphy_bitslip50 <= 8'd0; + case (main_k7ddrphy_bitslip5_value0) 1'd0: begin - k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[8:1]; + main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[9:2]; + main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[10:3]; + main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[11:4]; + main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[12:5]; + main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[13:6]; + main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[14:7]; + main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[15:8]; + main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip52 <= 8'd0; - case (k7ddrphy_bitslip5_value1) + main_k7ddrphy_bitslip52 <= 8'd0; + case (main_k7ddrphy_bitslip5_value1) 1'd0: begin - k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[8:1]; + main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[9:2]; + main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[10:3]; + main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[11:4]; + main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[12:5]; + main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[13:6]; + main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[14:7]; + main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[15:8]; + main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip60 <= 8'd0; - case (k7ddrphy_bitslip6_value0) + main_k7ddrphy_bitslip60 <= 8'd0; + case (main_k7ddrphy_bitslip6_value0) 1'd0: begin - k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[8:1]; + main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[9:2]; + main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[10:3]; + main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[11:4]; + main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[12:5]; + main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[13:6]; + main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[14:7]; + main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[15:8]; + main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip62 <= 8'd0; - case (k7ddrphy_bitslip6_value1) + main_k7ddrphy_bitslip62 <= 8'd0; + case (main_k7ddrphy_bitslip6_value1) 1'd0: begin - k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[8:1]; + main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[9:2]; + main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[10:3]; + main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[11:4]; + main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[12:5]; + main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[13:6]; + main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[14:7]; + main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[15:8]; + main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip70 <= 8'd0; - case (k7ddrphy_bitslip7_value0) + main_k7ddrphy_bitslip70 <= 8'd0; + case (main_k7ddrphy_bitslip7_value0) 1'd0: begin - k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[8:1]; + main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[9:2]; + main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[10:3]; + main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[11:4]; + main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[12:5]; + main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[13:6]; + main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[14:7]; + main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[15:8]; + main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip72 <= 8'd0; - case (k7ddrphy_bitslip7_value1) + main_k7ddrphy_bitslip72 <= 8'd0; + case (main_k7ddrphy_bitslip7_value1) 1'd0: begin - k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[8:1]; + main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[9:2]; + main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[10:3]; + main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[11:4]; + main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[12:5]; + main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[13:6]; + main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[14:7]; + main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[15:8]; + main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip80 <= 8'd0; - case (k7ddrphy_bitslip8_value0) + main_k7ddrphy_bitslip80 <= 8'd0; + case (main_k7ddrphy_bitslip8_value0) 1'd0: begin - k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[8:1]; + main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[9:2]; + main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[10:3]; + main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[11:4]; + main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[12:5]; + main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[13:6]; + main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[14:7]; + main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[15:8]; + main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip82 <= 8'd0; - case (k7ddrphy_bitslip8_value1) + main_k7ddrphy_bitslip82 <= 8'd0; + case (main_k7ddrphy_bitslip8_value1) 1'd0: begin - k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[8:1]; + main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[9:2]; + main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[10:3]; + main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[11:4]; + main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[12:5]; + main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[13:6]; + main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[14:7]; + main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[15:8]; + main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip90 <= 8'd0; - case (k7ddrphy_bitslip9_value0) + main_k7ddrphy_bitslip90 <= 8'd0; + case (main_k7ddrphy_bitslip9_value0) 1'd0: begin - k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[8:1]; + main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[9:2]; + main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[10:3]; + main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[11:4]; + main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[12:5]; + main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[13:6]; + main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[14:7]; + main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[15:8]; + main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip92 <= 8'd0; - case (k7ddrphy_bitslip9_value1) + main_k7ddrphy_bitslip92 <= 8'd0; + case (main_k7ddrphy_bitslip9_value1) 1'd0: begin - k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[8:1]; + main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[9:2]; + main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[10:3]; + main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[11:4]; + main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[12:5]; + main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[13:6]; + main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[14:7]; + main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[15:8]; + main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip100 <= 8'd0; - case (k7ddrphy_bitslip10_value0) + main_k7ddrphy_bitslip100 <= 8'd0; + case (main_k7ddrphy_bitslip10_value0) 1'd0: begin - k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[8:1]; + main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[9:2]; + main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[10:3]; + main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[11:4]; + main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[12:5]; + main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[13:6]; + main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[14:7]; + main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[15:8]; + main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip102 <= 8'd0; - case (k7ddrphy_bitslip10_value1) + main_k7ddrphy_bitslip102 <= 8'd0; + case (main_k7ddrphy_bitslip10_value1) 1'd0: begin - k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[8:1]; + main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[9:2]; + main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[10:3]; + main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[11:4]; + main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[12:5]; + main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[13:6]; + main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[14:7]; + main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[15:8]; + main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip110 <= 8'd0; - case (k7ddrphy_bitslip11_value0) + main_k7ddrphy_bitslip110 <= 8'd0; + case (main_k7ddrphy_bitslip11_value0) 1'd0: begin - k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[8:1]; + main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[9:2]; + main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[10:3]; + main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[11:4]; + main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[12:5]; + main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[13:6]; + main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[14:7]; + main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[15:8]; + main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip112 <= 8'd0; - case (k7ddrphy_bitslip11_value1) + main_k7ddrphy_bitslip112 <= 8'd0; + case (main_k7ddrphy_bitslip11_value1) 1'd0: begin - k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[8:1]; + main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[9:2]; + main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[10:3]; + main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[11:4]; + main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[12:5]; + main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[13:6]; + main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[14:7]; + main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[15:8]; + main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip120 <= 8'd0; - case (k7ddrphy_bitslip12_value0) + main_k7ddrphy_bitslip120 <= 8'd0; + case (main_k7ddrphy_bitslip12_value0) 1'd0: begin - k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[8:1]; + main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[9:2]; + main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[10:3]; + main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[11:4]; + main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[12:5]; + main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[13:6]; + main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[14:7]; + main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[15:8]; + main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip122 <= 8'd0; - case (k7ddrphy_bitslip12_value1) + main_k7ddrphy_bitslip122 <= 8'd0; + case (main_k7ddrphy_bitslip12_value1) 1'd0: begin - k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[8:1]; + main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[9:2]; + main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[10:3]; + main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[11:4]; + main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[12:5]; + main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[13:6]; + main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[14:7]; + main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[15:8]; + main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip130 <= 8'd0; - case (k7ddrphy_bitslip13_value0) + main_k7ddrphy_bitslip130 <= 8'd0; + case (main_k7ddrphy_bitslip13_value0) 1'd0: begin - k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[8:1]; + main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[9:2]; + main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[10:3]; + main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[11:4]; + main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[12:5]; + main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[13:6]; + main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[14:7]; + main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[15:8]; + main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip132 <= 8'd0; - case (k7ddrphy_bitslip13_value1) + main_k7ddrphy_bitslip132 <= 8'd0; + case (main_k7ddrphy_bitslip13_value1) 1'd0: begin - k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[8:1]; + main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[9:2]; + main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[10:3]; + main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[11:4]; + main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[12:5]; + main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[13:6]; + main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[14:7]; + main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[15:8]; + main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip140 <= 8'd0; - case (k7ddrphy_bitslip14_value0) + main_k7ddrphy_bitslip140 <= 8'd0; + case (main_k7ddrphy_bitslip14_value0) 1'd0: begin - k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[8:1]; + main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[9:2]; + main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[10:3]; + main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[11:4]; + main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[12:5]; + main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[13:6]; + main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[14:7]; + main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[15:8]; + main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip142 <= 8'd0; - case (k7ddrphy_bitslip14_value1) + main_k7ddrphy_bitslip142 <= 8'd0; + case (main_k7ddrphy_bitslip14_value1) 1'd0: begin - k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[8:1]; + main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[9:2]; + main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[10:3]; + main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[11:4]; + main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[12:5]; + main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[13:6]; + main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[14:7]; + main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[15:8]; + main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip150 <= 8'd0; - case (k7ddrphy_bitslip15_value0) + main_k7ddrphy_bitslip150 <= 8'd0; + case (main_k7ddrphy_bitslip15_value0) 1'd0: begin - k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[8:1]; + main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[9:2]; + main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[10:3]; + main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[11:4]; + main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[12:5]; + main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[13:6]; + main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[14:7]; + main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[15:8]; + main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip152 <= 8'd0; - case (k7ddrphy_bitslip15_value1) + main_k7ddrphy_bitslip152 <= 8'd0; + case (main_k7ddrphy_bitslip15_value1) 1'd0: begin - k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[8:1]; + main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[9:2]; + main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[10:3]; + main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[11:4]; + main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[12:5]; + main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[13:6]; + main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[14:7]; + main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[15:8]; + main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip160 <= 8'd0; - case (k7ddrphy_bitslip16_value0) + main_k7ddrphy_bitslip160 <= 8'd0; + case (main_k7ddrphy_bitslip16_value0) 1'd0: begin - k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[8:1]; + main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[9:2]; + main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[10:3]; + main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[11:4]; + main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[12:5]; + main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[13:6]; + main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[14:7]; + main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[15:8]; + main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip162 <= 8'd0; - case (k7ddrphy_bitslip16_value1) + main_k7ddrphy_bitslip162 <= 8'd0; + case (main_k7ddrphy_bitslip16_value1) 1'd0: begin - k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[8:1]; + main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[9:2]; + main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[10:3]; + main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[11:4]; + main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[12:5]; + main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[13:6]; + main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[14:7]; + main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[15:8]; + main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip170 <= 8'd0; - case (k7ddrphy_bitslip17_value0) + main_k7ddrphy_bitslip170 <= 8'd0; + case (main_k7ddrphy_bitslip17_value0) 1'd0: begin - k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[8:1]; + main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[9:2]; + main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[10:3]; + main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[11:4]; + main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[12:5]; + main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[13:6]; + main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[14:7]; + main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[15:8]; + main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip172 <= 8'd0; - case (k7ddrphy_bitslip17_value1) + main_k7ddrphy_bitslip172 <= 8'd0; + case (main_k7ddrphy_bitslip17_value1) 1'd0: begin - k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[8:1]; + main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[9:2]; + main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[10:3]; + main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[11:4]; + main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[12:5]; + main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[13:6]; + main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[14:7]; + main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[15:8]; + main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip180 <= 8'd0; - case (k7ddrphy_bitslip18_value0) + main_k7ddrphy_bitslip180 <= 8'd0; + case (main_k7ddrphy_bitslip18_value0) 1'd0: begin - k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[8:1]; + main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[9:2]; + main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[10:3]; + main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[11:4]; + main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[12:5]; + main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[13:6]; + main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[14:7]; + main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[15:8]; + main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip182 <= 8'd0; - case (k7ddrphy_bitslip18_value1) + main_k7ddrphy_bitslip182 <= 8'd0; + case (main_k7ddrphy_bitslip18_value1) 1'd0: begin - k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[8:1]; + main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[9:2]; + main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[10:3]; + main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[11:4]; + main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[12:5]; + main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[13:6]; + main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[14:7]; + main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[15:8]; + main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip190 <= 8'd0; - case (k7ddrphy_bitslip19_value0) + main_k7ddrphy_bitslip190 <= 8'd0; + case (main_k7ddrphy_bitslip19_value0) 1'd0: begin - k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[8:1]; + main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[9:2]; + main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[10:3]; + main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[11:4]; + main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[12:5]; + main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[13:6]; + main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[14:7]; + main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[15:8]; + main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip192 <= 8'd0; - case (k7ddrphy_bitslip19_value1) + main_k7ddrphy_bitslip192 <= 8'd0; + case (main_k7ddrphy_bitslip19_value1) 1'd0: begin - k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[8:1]; + main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[9:2]; + main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[10:3]; + main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[11:4]; + main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[12:5]; + main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[13:6]; + main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[14:7]; + main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[15:8]; + main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip200 <= 8'd0; - case (k7ddrphy_bitslip20_value0) + main_k7ddrphy_bitslip200 <= 8'd0; + case (main_k7ddrphy_bitslip20_value0) 1'd0: begin - k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[8:1]; + main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[9:2]; + main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[10:3]; + main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[11:4]; + main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[12:5]; + main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[13:6]; + main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[14:7]; + main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[15:8]; + main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip202 <= 8'd0; - case (k7ddrphy_bitslip20_value1) + main_k7ddrphy_bitslip202 <= 8'd0; + case (main_k7ddrphy_bitslip20_value1) 1'd0: begin - k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[8:1]; + main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[9:2]; + main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[10:3]; + main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[11:4]; + main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[12:5]; + main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[13:6]; + main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[14:7]; + main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[15:8]; + main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip210 <= 8'd0; - case (k7ddrphy_bitslip21_value0) + main_k7ddrphy_bitslip210 <= 8'd0; + case (main_k7ddrphy_bitslip21_value0) 1'd0: begin - k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[8:1]; + main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[9:2]; + main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[10:3]; + main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[11:4]; + main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[12:5]; + main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[13:6]; + main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[14:7]; + main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[15:8]; + main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip212 <= 8'd0; - case (k7ddrphy_bitslip21_value1) + main_k7ddrphy_bitslip212 <= 8'd0; + case (main_k7ddrphy_bitslip21_value1) 1'd0: begin - k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[8:1]; + main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[9:2]; + main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[10:3]; + main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[11:4]; + main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[12:5]; + main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[13:6]; + main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[14:7]; + main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[15:8]; + main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip220 <= 8'd0; - case (k7ddrphy_bitslip22_value0) + main_k7ddrphy_bitslip220 <= 8'd0; + case (main_k7ddrphy_bitslip22_value0) 1'd0: begin - k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[8:1]; + main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[9:2]; + main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[10:3]; + main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[11:4]; + main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[12:5]; + main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[13:6]; + main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[14:7]; + main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[15:8]; + main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip222 <= 8'd0; - case (k7ddrphy_bitslip22_value1) + main_k7ddrphy_bitslip222 <= 8'd0; + case (main_k7ddrphy_bitslip22_value1) 1'd0: begin - k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[8:1]; + main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[9:2]; + main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[10:3]; + main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[11:4]; + main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[12:5]; + main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[13:6]; + main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[14:7]; + main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[15:8]; + main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip230 <= 8'd0; - case (k7ddrphy_bitslip23_value0) + main_k7ddrphy_bitslip230 <= 8'd0; + case (main_k7ddrphy_bitslip23_value0) 1'd0: begin - k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[8:1]; + main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[9:2]; + main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[10:3]; + main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[11:4]; + main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[12:5]; + main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[13:6]; + main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[14:7]; + main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[15:8]; + main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip232 <= 8'd0; - case (k7ddrphy_bitslip23_value1) + main_k7ddrphy_bitslip232 <= 8'd0; + case (main_k7ddrphy_bitslip23_value1) 1'd0: begin - k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[8:1]; + main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[9:2]; + main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[10:3]; + main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[11:4]; + main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[12:5]; + main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[13:6]; + main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[14:7]; + main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[15:8]; + main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip240 <= 8'd0; - case (k7ddrphy_bitslip24_value0) + main_k7ddrphy_bitslip240 <= 8'd0; + case (main_k7ddrphy_bitslip24_value0) 1'd0: begin - k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[8:1]; + main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[9:2]; + main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[10:3]; + main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[11:4]; + main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[12:5]; + main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[13:6]; + main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[14:7]; + main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[15:8]; + main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip242 <= 8'd0; - case (k7ddrphy_bitslip24_value1) + main_k7ddrphy_bitslip242 <= 8'd0; + case (main_k7ddrphy_bitslip24_value1) 1'd0: begin - k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[8:1]; + main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[9:2]; + main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[10:3]; + main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[11:4]; + main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[12:5]; + main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[13:6]; + main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[14:7]; + main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[15:8]; + main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip250 <= 8'd0; - case (k7ddrphy_bitslip25_value0) + main_k7ddrphy_bitslip250 <= 8'd0; + case (main_k7ddrphy_bitslip25_value0) 1'd0: begin - k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[8:1]; + main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[9:2]; + main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[10:3]; + main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[11:4]; + main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[12:5]; + main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[13:6]; + main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[14:7]; + main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[15:8]; + main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip252 <= 8'd0; - case (k7ddrphy_bitslip25_value1) + main_k7ddrphy_bitslip252 <= 8'd0; + case (main_k7ddrphy_bitslip25_value1) 1'd0: begin - k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[8:1]; + main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[9:2]; + main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[10:3]; + main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[11:4]; + main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[12:5]; + main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[13:6]; + main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[14:7]; + main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[15:8]; + main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip260 <= 8'd0; - case (k7ddrphy_bitslip26_value0) + main_k7ddrphy_bitslip260 <= 8'd0; + case (main_k7ddrphy_bitslip26_value0) 1'd0: begin - k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[8:1]; + main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[9:2]; + main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[10:3]; + main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[11:4]; + main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[12:5]; + main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[13:6]; + main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[14:7]; + main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[15:8]; + main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip262 <= 8'd0; - case (k7ddrphy_bitslip26_value1) + main_k7ddrphy_bitslip262 <= 8'd0; + case (main_k7ddrphy_bitslip26_value1) 1'd0: begin - k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[8:1]; + main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[9:2]; + main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[10:3]; + main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[11:4]; + main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[12:5]; + main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[13:6]; + main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[14:7]; + main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[15:8]; + main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip270 <= 8'd0; - case (k7ddrphy_bitslip27_value0) + main_k7ddrphy_bitslip270 <= 8'd0; + case (main_k7ddrphy_bitslip27_value0) 1'd0: begin - k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[8:1]; + main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[9:2]; + main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[10:3]; + main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[11:4]; + main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[12:5]; + main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[13:6]; + main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[14:7]; + main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[15:8]; + main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip272 <= 8'd0; - case (k7ddrphy_bitslip27_value1) + main_k7ddrphy_bitslip272 <= 8'd0; + case (main_k7ddrphy_bitslip27_value1) 1'd0: begin - k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[8:1]; + main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[9:2]; + main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[10:3]; + main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[11:4]; + main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[12:5]; + main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[13:6]; + main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[14:7]; + main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[15:8]; + main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip280 <= 8'd0; - case (k7ddrphy_bitslip28_value0) + main_k7ddrphy_bitslip280 <= 8'd0; + case (main_k7ddrphy_bitslip28_value0) 1'd0: begin - k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[8:1]; + main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[9:2]; + main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[10:3]; + main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[11:4]; + main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[12:5]; + main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[13:6]; + main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[14:7]; + main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[15:8]; + main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip282 <= 8'd0; - case (k7ddrphy_bitslip28_value1) + main_k7ddrphy_bitslip282 <= 8'd0; + case (main_k7ddrphy_bitslip28_value1) 1'd0: begin - k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[8:1]; + main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[9:2]; + main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[10:3]; + main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[11:4]; + main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[12:5]; + main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[13:6]; + main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[14:7]; + main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[15:8]; + main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip290 <= 8'd0; - case (k7ddrphy_bitslip29_value0) + main_k7ddrphy_bitslip290 <= 8'd0; + case (main_k7ddrphy_bitslip29_value0) 1'd0: begin - k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[8:1]; + main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[9:2]; + main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[10:3]; + main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[11:4]; + main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[12:5]; + main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[13:6]; + main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[14:7]; + main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[15:8]; + main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip292 <= 8'd0; - case (k7ddrphy_bitslip29_value1) + main_k7ddrphy_bitslip292 <= 8'd0; + case (main_k7ddrphy_bitslip29_value1) 1'd0: begin - k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[8:1]; + main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[9:2]; + main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[10:3]; + main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[11:4]; + main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[12:5]; + main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[13:6]; + main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[14:7]; + main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[15:8]; + main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip300 <= 8'd0; - case (k7ddrphy_bitslip30_value0) + main_k7ddrphy_bitslip300 <= 8'd0; + case (main_k7ddrphy_bitslip30_value0) 1'd0: begin - k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[8:1]; + main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[9:2]; + main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[10:3]; + main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[11:4]; + main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[12:5]; + main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[13:6]; + main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[14:7]; + main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[15:8]; + main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip302 <= 8'd0; - case (k7ddrphy_bitslip30_value1) + main_k7ddrphy_bitslip302 <= 8'd0; + case (main_k7ddrphy_bitslip30_value1) 1'd0: begin - k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[8:1]; + main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[9:2]; + main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[10:3]; + main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[11:4]; + main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[12:5]; + main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[13:6]; + main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[14:7]; + main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[15:8]; + main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip310 <= 8'd0; - case (k7ddrphy_bitslip31_value0) + main_k7ddrphy_bitslip310 <= 8'd0; + case (main_k7ddrphy_bitslip31_value0) 1'd0: begin - k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[8:1]; + main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[8:1]; end 1'd1: begin - k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[9:2]; + main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[9:2]; end 2'd2: begin - k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[10:3]; + main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[10:3]; end 2'd3: begin - k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[11:4]; + main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[11:4]; end 3'd4: begin - k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[12:5]; + main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[12:5]; end 3'd5: begin - k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[13:6]; + main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[13:6]; end 3'd6: begin - k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[14:7]; + main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[14:7]; end 3'd7: begin - k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[15:8]; + main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[15:8]; end endcase end always @(*) begin - k7ddrphy_bitslip312 <= 8'd0; - case (k7ddrphy_bitslip31_value1) + main_k7ddrphy_bitslip312 <= 8'd0; + case (main_k7ddrphy_bitslip31_value1) 1'd0: begin - k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[8:1]; + main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[8:1]; end 1'd1: begin - k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[9:2]; + main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[9:2]; end 2'd2: begin - k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[10:3]; + main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[10:3]; end 2'd3: begin - k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[11:4]; + main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[11:4]; end 3'd4: begin - k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[12:5]; + main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[12:5]; end 3'd5: begin - k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[13:6]; + main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[13:6]; end 3'd6: begin - k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[14:7]; + main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[14:7]; end 3'd7: begin - k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[15:8]; - end - endcase -end -assign k7ddrphy_dfi_p0_address = litedramcore_master_p0_address; -assign k7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank; -assign k7ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n; -assign k7ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n; -assign k7ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n; -assign k7ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n; -assign k7ddrphy_dfi_p0_cke = litedramcore_master_p0_cke; -assign k7ddrphy_dfi_p0_odt = litedramcore_master_p0_odt; -assign k7ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n; -assign k7ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n; -assign k7ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata; -assign k7ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en; -assign k7ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask; -assign k7ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en; -assign litedramcore_master_p0_rddata = k7ddrphy_dfi_p0_rddata; -assign litedramcore_master_p0_rddata_valid = k7ddrphy_dfi_p0_rddata_valid; -assign k7ddrphy_dfi_p1_address = litedramcore_master_p1_address; -assign k7ddrphy_dfi_p1_bank = litedramcore_master_p1_bank; -assign k7ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n; -assign k7ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n; -assign k7ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n; -assign k7ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n; -assign k7ddrphy_dfi_p1_cke = litedramcore_master_p1_cke; -assign k7ddrphy_dfi_p1_odt = litedramcore_master_p1_odt; -assign k7ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n; -assign k7ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n; -assign k7ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata; -assign k7ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en; -assign k7ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask; -assign k7ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en; -assign litedramcore_master_p1_rddata = k7ddrphy_dfi_p1_rddata; -assign litedramcore_master_p1_rddata_valid = k7ddrphy_dfi_p1_rddata_valid; -assign k7ddrphy_dfi_p2_address = litedramcore_master_p2_address; -assign k7ddrphy_dfi_p2_bank = litedramcore_master_p2_bank; -assign k7ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n; -assign k7ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n; -assign k7ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n; -assign k7ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n; -assign k7ddrphy_dfi_p2_cke = litedramcore_master_p2_cke; -assign k7ddrphy_dfi_p2_odt = litedramcore_master_p2_odt; -assign k7ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n; -assign k7ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n; -assign k7ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata; -assign k7ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en; -assign k7ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask; -assign k7ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en; -assign litedramcore_master_p2_rddata = k7ddrphy_dfi_p2_rddata; -assign litedramcore_master_p2_rddata_valid = k7ddrphy_dfi_p2_rddata_valid; -assign k7ddrphy_dfi_p3_address = litedramcore_master_p3_address; -assign k7ddrphy_dfi_p3_bank = litedramcore_master_p3_bank; -assign k7ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n; -assign k7ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n; -assign k7ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n; -assign k7ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n; -assign k7ddrphy_dfi_p3_cke = litedramcore_master_p3_cke; -assign k7ddrphy_dfi_p3_odt = litedramcore_master_p3_odt; -assign k7ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n; -assign k7ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n; -assign k7ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata; -assign k7ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en; -assign k7ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask; -assign k7ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en; -assign litedramcore_master_p3_rddata = k7ddrphy_dfi_p3_rddata; -assign litedramcore_master_p3_rddata_valid = k7ddrphy_dfi_p3_rddata_valid; -assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address; -assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank; -assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n; -assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n; -assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n; -assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n; -assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke; -assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt; -assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n; -assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n; -assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata; -assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en; -assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask; -assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en; -assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata; -assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid; -assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address; -assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank; -assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n; -assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n; -assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n; -assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n; -assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke; -assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt; -assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n; -assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n; -assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata; -assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en; -assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask; -assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en; -assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata; -assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid; -assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address; -assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank; -assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n; -assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n; -assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n; -assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n; -assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke; -assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt; -assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n; -assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n; -assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata; -assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en; -assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask; -assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en; -assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata; -assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid; -assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address; -assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank; -assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n; -assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n; -assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n; -assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n; -assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke; -assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt; -assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n; -assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n; -assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata; -assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en; -assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask; -assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en; -assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata; -assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; -always @(*) begin - litedramcore_csr_dfi_p0_rddata <= 64'd0; - if (litedramcore_sel) begin + main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[15:8]; + end + endcase +end +assign main_k7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address; +assign main_k7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank; +assign main_k7ddrphy_dfi_p0_cas_n = main_litedramcore_master_p0_cas_n; +assign main_k7ddrphy_dfi_p0_cs_n = main_litedramcore_master_p0_cs_n; +assign main_k7ddrphy_dfi_p0_ras_n = main_litedramcore_master_p0_ras_n; +assign main_k7ddrphy_dfi_p0_we_n = main_litedramcore_master_p0_we_n; +assign main_k7ddrphy_dfi_p0_cke = main_litedramcore_master_p0_cke; +assign main_k7ddrphy_dfi_p0_odt = main_litedramcore_master_p0_odt; +assign main_k7ddrphy_dfi_p0_reset_n = main_litedramcore_master_p0_reset_n; +assign main_k7ddrphy_dfi_p0_act_n = main_litedramcore_master_p0_act_n; +assign main_k7ddrphy_dfi_p0_wrdata = main_litedramcore_master_p0_wrdata; +assign main_k7ddrphy_dfi_p0_wrdata_en = main_litedramcore_master_p0_wrdata_en; +assign main_k7ddrphy_dfi_p0_wrdata_mask = main_litedramcore_master_p0_wrdata_mask; +assign main_k7ddrphy_dfi_p0_rddata_en = main_litedramcore_master_p0_rddata_en; +assign main_litedramcore_master_p0_rddata = main_k7ddrphy_dfi_p0_rddata; +assign main_litedramcore_master_p0_rddata_valid = main_k7ddrphy_dfi_p0_rddata_valid; +assign main_k7ddrphy_dfi_p1_address = main_litedramcore_master_p1_address; +assign main_k7ddrphy_dfi_p1_bank = main_litedramcore_master_p1_bank; +assign main_k7ddrphy_dfi_p1_cas_n = main_litedramcore_master_p1_cas_n; +assign main_k7ddrphy_dfi_p1_cs_n = main_litedramcore_master_p1_cs_n; +assign main_k7ddrphy_dfi_p1_ras_n = main_litedramcore_master_p1_ras_n; +assign main_k7ddrphy_dfi_p1_we_n = main_litedramcore_master_p1_we_n; +assign main_k7ddrphy_dfi_p1_cke = main_litedramcore_master_p1_cke; +assign main_k7ddrphy_dfi_p1_odt = main_litedramcore_master_p1_odt; +assign main_k7ddrphy_dfi_p1_reset_n = main_litedramcore_master_p1_reset_n; +assign main_k7ddrphy_dfi_p1_act_n = main_litedramcore_master_p1_act_n; +assign main_k7ddrphy_dfi_p1_wrdata = main_litedramcore_master_p1_wrdata; +assign main_k7ddrphy_dfi_p1_wrdata_en = main_litedramcore_master_p1_wrdata_en; +assign main_k7ddrphy_dfi_p1_wrdata_mask = main_litedramcore_master_p1_wrdata_mask; +assign main_k7ddrphy_dfi_p1_rddata_en = main_litedramcore_master_p1_rddata_en; +assign main_litedramcore_master_p1_rddata = main_k7ddrphy_dfi_p1_rddata; +assign main_litedramcore_master_p1_rddata_valid = main_k7ddrphy_dfi_p1_rddata_valid; +assign main_k7ddrphy_dfi_p2_address = main_litedramcore_master_p2_address; +assign main_k7ddrphy_dfi_p2_bank = main_litedramcore_master_p2_bank; +assign main_k7ddrphy_dfi_p2_cas_n = main_litedramcore_master_p2_cas_n; +assign main_k7ddrphy_dfi_p2_cs_n = main_litedramcore_master_p2_cs_n; +assign main_k7ddrphy_dfi_p2_ras_n = main_litedramcore_master_p2_ras_n; +assign main_k7ddrphy_dfi_p2_we_n = main_litedramcore_master_p2_we_n; +assign main_k7ddrphy_dfi_p2_cke = main_litedramcore_master_p2_cke; +assign main_k7ddrphy_dfi_p2_odt = main_litedramcore_master_p2_odt; +assign main_k7ddrphy_dfi_p2_reset_n = main_litedramcore_master_p2_reset_n; +assign main_k7ddrphy_dfi_p2_act_n = main_litedramcore_master_p2_act_n; +assign main_k7ddrphy_dfi_p2_wrdata = main_litedramcore_master_p2_wrdata; +assign main_k7ddrphy_dfi_p2_wrdata_en = main_litedramcore_master_p2_wrdata_en; +assign main_k7ddrphy_dfi_p2_wrdata_mask = main_litedramcore_master_p2_wrdata_mask; +assign main_k7ddrphy_dfi_p2_rddata_en = main_litedramcore_master_p2_rddata_en; +assign main_litedramcore_master_p2_rddata = main_k7ddrphy_dfi_p2_rddata; +assign main_litedramcore_master_p2_rddata_valid = main_k7ddrphy_dfi_p2_rddata_valid; +assign main_k7ddrphy_dfi_p3_address = main_litedramcore_master_p3_address; +assign main_k7ddrphy_dfi_p3_bank = main_litedramcore_master_p3_bank; +assign main_k7ddrphy_dfi_p3_cas_n = main_litedramcore_master_p3_cas_n; +assign main_k7ddrphy_dfi_p3_cs_n = main_litedramcore_master_p3_cs_n; +assign main_k7ddrphy_dfi_p3_ras_n = main_litedramcore_master_p3_ras_n; +assign main_k7ddrphy_dfi_p3_we_n = main_litedramcore_master_p3_we_n; +assign main_k7ddrphy_dfi_p3_cke = main_litedramcore_master_p3_cke; +assign main_k7ddrphy_dfi_p3_odt = main_litedramcore_master_p3_odt; +assign main_k7ddrphy_dfi_p3_reset_n = main_litedramcore_master_p3_reset_n; +assign main_k7ddrphy_dfi_p3_act_n = main_litedramcore_master_p3_act_n; +assign main_k7ddrphy_dfi_p3_wrdata = main_litedramcore_master_p3_wrdata; +assign main_k7ddrphy_dfi_p3_wrdata_en = main_litedramcore_master_p3_wrdata_en; +assign main_k7ddrphy_dfi_p3_wrdata_mask = main_litedramcore_master_p3_wrdata_mask; +assign main_k7ddrphy_dfi_p3_rddata_en = main_litedramcore_master_p3_rddata_en; +assign main_litedramcore_master_p3_rddata = main_k7ddrphy_dfi_p3_rddata; +assign main_litedramcore_master_p3_rddata_valid = main_k7ddrphy_dfi_p3_rddata_valid; +assign main_litedramcore_slave_p0_address = main_litedramcore_dfi_p0_address; +assign main_litedramcore_slave_p0_bank = main_litedramcore_dfi_p0_bank; +assign main_litedramcore_slave_p0_cas_n = main_litedramcore_dfi_p0_cas_n; +assign main_litedramcore_slave_p0_cs_n = main_litedramcore_dfi_p0_cs_n; +assign main_litedramcore_slave_p0_ras_n = main_litedramcore_dfi_p0_ras_n; +assign main_litedramcore_slave_p0_we_n = main_litedramcore_dfi_p0_we_n; +assign main_litedramcore_slave_p0_cke = main_litedramcore_dfi_p0_cke; +assign main_litedramcore_slave_p0_odt = main_litedramcore_dfi_p0_odt; +assign main_litedramcore_slave_p0_reset_n = main_litedramcore_dfi_p0_reset_n; +assign main_litedramcore_slave_p0_act_n = main_litedramcore_dfi_p0_act_n; +assign main_litedramcore_slave_p0_wrdata = main_litedramcore_dfi_p0_wrdata; +assign main_litedramcore_slave_p0_wrdata_en = main_litedramcore_dfi_p0_wrdata_en; +assign main_litedramcore_slave_p0_wrdata_mask = main_litedramcore_dfi_p0_wrdata_mask; +assign main_litedramcore_slave_p0_rddata_en = main_litedramcore_dfi_p0_rddata_en; +assign main_litedramcore_dfi_p0_rddata = main_litedramcore_slave_p0_rddata; +assign main_litedramcore_dfi_p0_rddata_valid = main_litedramcore_slave_p0_rddata_valid; +assign main_litedramcore_slave_p1_address = main_litedramcore_dfi_p1_address; +assign main_litedramcore_slave_p1_bank = main_litedramcore_dfi_p1_bank; +assign main_litedramcore_slave_p1_cas_n = main_litedramcore_dfi_p1_cas_n; +assign main_litedramcore_slave_p1_cs_n = main_litedramcore_dfi_p1_cs_n; +assign main_litedramcore_slave_p1_ras_n = main_litedramcore_dfi_p1_ras_n; +assign main_litedramcore_slave_p1_we_n = main_litedramcore_dfi_p1_we_n; +assign main_litedramcore_slave_p1_cke = main_litedramcore_dfi_p1_cke; +assign main_litedramcore_slave_p1_odt = main_litedramcore_dfi_p1_odt; +assign main_litedramcore_slave_p1_reset_n = main_litedramcore_dfi_p1_reset_n; +assign main_litedramcore_slave_p1_act_n = main_litedramcore_dfi_p1_act_n; +assign main_litedramcore_slave_p1_wrdata = main_litedramcore_dfi_p1_wrdata; +assign main_litedramcore_slave_p1_wrdata_en = main_litedramcore_dfi_p1_wrdata_en; +assign main_litedramcore_slave_p1_wrdata_mask = main_litedramcore_dfi_p1_wrdata_mask; +assign main_litedramcore_slave_p1_rddata_en = main_litedramcore_dfi_p1_rddata_en; +assign main_litedramcore_dfi_p1_rddata = main_litedramcore_slave_p1_rddata; +assign main_litedramcore_dfi_p1_rddata_valid = main_litedramcore_slave_p1_rddata_valid; +assign main_litedramcore_slave_p2_address = main_litedramcore_dfi_p2_address; +assign main_litedramcore_slave_p2_bank = main_litedramcore_dfi_p2_bank; +assign main_litedramcore_slave_p2_cas_n = main_litedramcore_dfi_p2_cas_n; +assign main_litedramcore_slave_p2_cs_n = main_litedramcore_dfi_p2_cs_n; +assign main_litedramcore_slave_p2_ras_n = main_litedramcore_dfi_p2_ras_n; +assign main_litedramcore_slave_p2_we_n = main_litedramcore_dfi_p2_we_n; +assign main_litedramcore_slave_p2_cke = main_litedramcore_dfi_p2_cke; +assign main_litedramcore_slave_p2_odt = main_litedramcore_dfi_p2_odt; +assign main_litedramcore_slave_p2_reset_n = main_litedramcore_dfi_p2_reset_n; +assign main_litedramcore_slave_p2_act_n = main_litedramcore_dfi_p2_act_n; +assign main_litedramcore_slave_p2_wrdata = main_litedramcore_dfi_p2_wrdata; +assign main_litedramcore_slave_p2_wrdata_en = main_litedramcore_dfi_p2_wrdata_en; +assign main_litedramcore_slave_p2_wrdata_mask = main_litedramcore_dfi_p2_wrdata_mask; +assign main_litedramcore_slave_p2_rddata_en = main_litedramcore_dfi_p2_rddata_en; +assign main_litedramcore_dfi_p2_rddata = main_litedramcore_slave_p2_rddata; +assign main_litedramcore_dfi_p2_rddata_valid = main_litedramcore_slave_p2_rddata_valid; +assign main_litedramcore_slave_p3_address = main_litedramcore_dfi_p3_address; +assign main_litedramcore_slave_p3_bank = main_litedramcore_dfi_p3_bank; +assign main_litedramcore_slave_p3_cas_n = main_litedramcore_dfi_p3_cas_n; +assign main_litedramcore_slave_p3_cs_n = main_litedramcore_dfi_p3_cs_n; +assign main_litedramcore_slave_p3_ras_n = main_litedramcore_dfi_p3_ras_n; +assign main_litedramcore_slave_p3_we_n = main_litedramcore_dfi_p3_we_n; +assign main_litedramcore_slave_p3_cke = main_litedramcore_dfi_p3_cke; +assign main_litedramcore_slave_p3_odt = main_litedramcore_dfi_p3_odt; +assign main_litedramcore_slave_p3_reset_n = main_litedramcore_dfi_p3_reset_n; +assign main_litedramcore_slave_p3_act_n = main_litedramcore_dfi_p3_act_n; +assign main_litedramcore_slave_p3_wrdata = main_litedramcore_dfi_p3_wrdata; +assign main_litedramcore_slave_p3_wrdata_en = main_litedramcore_dfi_p3_wrdata_en; +assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_mask; +assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en; +assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata; +assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid; +always @(*) begin + main_litedramcore_csr_dfi_p0_rddata <= 64'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata; + main_litedramcore_csr_dfi_p0_rddata <= main_litedramcore_master_p0_rddata; end end always @(*) begin - litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + main_litedramcore_csr_dfi_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end end always @(*) begin - litedramcore_csr_dfi_p1_rddata <= 64'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p1_rddata <= 64'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata; + main_litedramcore_csr_dfi_p1_rddata <= main_litedramcore_master_p1_rddata; end end always @(*) begin - litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + main_litedramcore_csr_dfi_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end end always @(*) begin - litedramcore_csr_dfi_p2_rddata <= 64'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p2_rddata <= 64'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata; + main_litedramcore_csr_dfi_p2_rddata <= main_litedramcore_master_p2_rddata; end end always @(*) begin - litedramcore_csr_dfi_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p2_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + main_litedramcore_csr_dfi_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end end always @(*) begin - litedramcore_csr_dfi_p3_rddata <= 64'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p3_rddata <= 64'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata; + main_litedramcore_csr_dfi_p3_rddata <= main_litedramcore_master_p3_rddata; end end always @(*) begin - litedramcore_csr_dfi_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p3_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + main_litedramcore_csr_dfi_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end end always @(*) begin - litedramcore_ext_dfi_p0_rddata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata; + main_litedramcore_ext_dfi_p0_rddata <= 64'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p0_rddata <= main_litedramcore_master_p0_rddata; end else begin end end else begin end end always @(*) begin - litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + main_litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end else begin end end else begin end end always @(*) begin - litedramcore_ext_dfi_p1_rddata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata; + main_litedramcore_ext_dfi_p1_rddata <= 64'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p1_rddata <= main_litedramcore_master_p1_rddata; end else begin end end else begin end end always @(*) begin - litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + main_litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end else begin end end else begin end end always @(*) begin - litedramcore_ext_dfi_p2_rddata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata; + main_litedramcore_ext_dfi_p2_rddata <= 64'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p2_rddata <= main_litedramcore_master_p2_rddata; end else begin end end else begin end end always @(*) begin - litedramcore_ext_dfi_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + main_litedramcore_ext_dfi_p2_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end else begin end end else begin end end always @(*) begin - litedramcore_slave_p0_rddata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p0_rddata <= 64'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; + main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata; end end else begin end end always @(*) begin - litedramcore_slave_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end end else begin end end always @(*) begin - litedramcore_ext_dfi_p3_rddata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata; + main_litedramcore_ext_dfi_p3_rddata <= 64'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p3_rddata <= main_litedramcore_master_p3_rddata; end else begin end end else begin end end always @(*) begin - litedramcore_ext_dfi_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + main_litedramcore_ext_dfi_p3_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end else begin end end else begin end end always @(*) begin - litedramcore_slave_p1_rddata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p1_rddata <= 64'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; + main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata; end end else begin end end always @(*) begin - litedramcore_slave_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p1_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end end else begin end end always @(*) begin - litedramcore_slave_p2_rddata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p2_rddata <= 64'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; + main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata; end end else begin end end always @(*) begin - litedramcore_slave_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p2_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end end else begin end end always @(*) begin - litedramcore_slave_p3_rddata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p3_rddata <= 64'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; + main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata; end end else begin end end always @(*) begin - litedramcore_slave_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p3_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end end else begin end end always @(*) begin - litedramcore_master_p0_address <= 15'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address; + main_litedramcore_master_p0_address <= 15'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_address <= main_litedramcore_ext_dfi_p0_address; end else begin - litedramcore_master_p0_address <= litedramcore_slave_p0_address; + main_litedramcore_master_p0_address <= main_litedramcore_slave_p0_address; end end else begin - litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address; + main_litedramcore_master_p0_address <= main_litedramcore_csr_dfi_p0_address; end end always @(*) begin - litedramcore_master_p0_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank; + main_litedramcore_master_p0_bank <= 3'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_bank <= main_litedramcore_ext_dfi_p0_bank; end else begin - litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; + main_litedramcore_master_p0_bank <= main_litedramcore_slave_p0_bank; end end else begin - litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank; + main_litedramcore_master_p0_bank <= main_litedramcore_csr_dfi_p0_bank; end end always @(*) begin - litedramcore_master_p0_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n; + main_litedramcore_master_p0_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_cas_n <= main_litedramcore_ext_dfi_p0_cas_n; end else begin - litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; + main_litedramcore_master_p0_cas_n <= main_litedramcore_slave_p0_cas_n; end end else begin - litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n; + main_litedramcore_master_p0_cas_n <= main_litedramcore_csr_dfi_p0_cas_n; end end always @(*) begin - litedramcore_master_p0_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n; + main_litedramcore_master_p0_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_cs_n <= main_litedramcore_ext_dfi_p0_cs_n; end else begin - litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; + main_litedramcore_master_p0_cs_n <= main_litedramcore_slave_p0_cs_n; + if (1'd0) begin + main_litedramcore_master_p0_cs_n <= {2{main_litedramcore_slave_p0_cs_n}}; + end end end else begin - litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n; + main_litedramcore_master_p0_cs_n <= main_litedramcore_csr_dfi_p0_cs_n; end end always @(*) begin - litedramcore_master_p0_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n; + main_litedramcore_master_p0_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_ras_n <= main_litedramcore_ext_dfi_p0_ras_n; end else begin - litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; + main_litedramcore_master_p0_ras_n <= main_litedramcore_slave_p0_ras_n; end end else begin - litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n; + main_litedramcore_master_p0_ras_n <= main_litedramcore_csr_dfi_p0_ras_n; end end always @(*) begin - litedramcore_master_p0_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n; + main_litedramcore_master_p0_we_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_we_n <= main_litedramcore_ext_dfi_p0_we_n; end else begin - litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + main_litedramcore_master_p0_we_n <= main_litedramcore_slave_p0_we_n; end end else begin - litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n; + main_litedramcore_master_p0_we_n <= main_litedramcore_csr_dfi_p0_we_n; end end always @(*) begin - litedramcore_master_p0_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke; + main_litedramcore_master_p0_cke <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_cke <= main_litedramcore_ext_dfi_p0_cke; end else begin - litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; + main_litedramcore_master_p0_cke <= main_litedramcore_slave_p0_cke; end end else begin - litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke; + main_litedramcore_master_p0_cke <= main_litedramcore_csr_dfi_p0_cke; end end always @(*) begin - litedramcore_master_p0_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt; + main_litedramcore_master_p0_odt <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_odt <= main_litedramcore_ext_dfi_p0_odt; end else begin - litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; + main_litedramcore_master_p0_odt <= main_litedramcore_slave_p0_odt; end end else begin - litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt; + main_litedramcore_master_p0_odt <= main_litedramcore_csr_dfi_p0_odt; end end always @(*) begin - litedramcore_master_p0_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n; + main_litedramcore_master_p0_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_reset_n <= main_litedramcore_ext_dfi_p0_reset_n; end else begin - litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; + main_litedramcore_master_p0_reset_n <= main_litedramcore_slave_p0_reset_n; end end else begin - litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n; + main_litedramcore_master_p0_reset_n <= main_litedramcore_csr_dfi_p0_reset_n; end end always @(*) begin - litedramcore_master_p0_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n; + main_litedramcore_master_p0_act_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_act_n <= main_litedramcore_ext_dfi_p0_act_n; end else begin - litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; + main_litedramcore_master_p0_act_n <= main_litedramcore_slave_p0_act_n; end end else begin - litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n; + main_litedramcore_master_p0_act_n <= main_litedramcore_csr_dfi_p0_act_n; end end always @(*) begin - litedramcore_master_p0_wrdata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata; + main_litedramcore_master_p0_wrdata <= 64'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_wrdata <= main_litedramcore_ext_dfi_p0_wrdata; end else begin - litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; + main_litedramcore_master_p0_wrdata <= main_litedramcore_slave_p0_wrdata; end end else begin - litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata; + main_litedramcore_master_p0_wrdata <= main_litedramcore_csr_dfi_p0_wrdata; end end always @(*) begin - litedramcore_master_p0_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en; + main_litedramcore_master_p0_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_wrdata_en <= main_litedramcore_ext_dfi_p0_wrdata_en; end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; + main_litedramcore_master_p0_wrdata_en <= main_litedramcore_slave_p0_wrdata_en; end end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en; + main_litedramcore_master_p0_wrdata_en <= main_litedramcore_csr_dfi_p0_wrdata_en; end end always @(*) begin - litedramcore_master_p0_wrdata_mask <= 8'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask; + main_litedramcore_master_p0_wrdata_mask <= 8'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_ext_dfi_p0_wrdata_mask; end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_slave_p0_wrdata_mask; end end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask; + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_csr_dfi_p0_wrdata_mask; end end always @(*) begin - litedramcore_master_p0_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en; + main_litedramcore_master_p0_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_rddata_en <= main_litedramcore_ext_dfi_p0_rddata_en; end else begin - litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; + main_litedramcore_master_p0_rddata_en <= main_litedramcore_slave_p0_rddata_en; end end else begin - litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en; + main_litedramcore_master_p0_rddata_en <= main_litedramcore_csr_dfi_p0_rddata_en; end end always @(*) begin - litedramcore_master_p1_address <= 15'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address; + main_litedramcore_master_p1_address <= 15'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_address <= main_litedramcore_ext_dfi_p1_address; end else begin - litedramcore_master_p1_address <= litedramcore_slave_p1_address; + main_litedramcore_master_p1_address <= main_litedramcore_slave_p1_address; end end else begin - litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address; + main_litedramcore_master_p1_address <= main_litedramcore_csr_dfi_p1_address; end end always @(*) begin - litedramcore_master_p1_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank; + main_litedramcore_master_p1_bank <= 3'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_bank <= main_litedramcore_ext_dfi_p1_bank; end else begin - litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; + main_litedramcore_master_p1_bank <= main_litedramcore_slave_p1_bank; end end else begin - litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank; + main_litedramcore_master_p1_bank <= main_litedramcore_csr_dfi_p1_bank; end end always @(*) begin - litedramcore_master_p1_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n; + main_litedramcore_master_p1_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_cas_n <= main_litedramcore_ext_dfi_p1_cas_n; end else begin - litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; + main_litedramcore_master_p1_cas_n <= main_litedramcore_slave_p1_cas_n; end end else begin - litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n; + main_litedramcore_master_p1_cas_n <= main_litedramcore_csr_dfi_p1_cas_n; end end always @(*) begin - litedramcore_master_p1_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n; + main_litedramcore_master_p1_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_cs_n <= main_litedramcore_ext_dfi_p1_cs_n; end else begin - litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; + main_litedramcore_master_p1_cs_n <= main_litedramcore_slave_p1_cs_n; + if (1'd0) begin + main_litedramcore_master_p1_cs_n <= {2{main_litedramcore_slave_p1_cs_n}}; + end end end else begin - litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n; + main_litedramcore_master_p1_cs_n <= main_litedramcore_csr_dfi_p1_cs_n; end end always @(*) begin - litedramcore_master_p1_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n; + main_litedramcore_master_p1_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_ras_n <= main_litedramcore_ext_dfi_p1_ras_n; end else begin - litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; + main_litedramcore_master_p1_ras_n <= main_litedramcore_slave_p1_ras_n; end end else begin - litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n; + main_litedramcore_master_p1_ras_n <= main_litedramcore_csr_dfi_p1_ras_n; end end always @(*) begin - litedramcore_master_p1_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n; + main_litedramcore_master_p1_we_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_we_n <= main_litedramcore_ext_dfi_p1_we_n; end else begin - litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; + main_litedramcore_master_p1_we_n <= main_litedramcore_slave_p1_we_n; end end else begin - litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n; + main_litedramcore_master_p1_we_n <= main_litedramcore_csr_dfi_p1_we_n; end end always @(*) begin - litedramcore_master_p1_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke; + main_litedramcore_master_p1_cke <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_cke <= main_litedramcore_ext_dfi_p1_cke; end else begin - litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; + main_litedramcore_master_p1_cke <= main_litedramcore_slave_p1_cke; end end else begin - litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke; + main_litedramcore_master_p1_cke <= main_litedramcore_csr_dfi_p1_cke; end end always @(*) begin - litedramcore_master_p1_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt; + main_litedramcore_master_p1_odt <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_odt <= main_litedramcore_ext_dfi_p1_odt; end else begin - litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; + main_litedramcore_master_p1_odt <= main_litedramcore_slave_p1_odt; end end else begin - litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt; + main_litedramcore_master_p1_odt <= main_litedramcore_csr_dfi_p1_odt; end end always @(*) begin - litedramcore_master_p1_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n; + main_litedramcore_master_p1_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_reset_n <= main_litedramcore_ext_dfi_p1_reset_n; end else begin - litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; + main_litedramcore_master_p1_reset_n <= main_litedramcore_slave_p1_reset_n; end end else begin - litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n; + main_litedramcore_master_p1_reset_n <= main_litedramcore_csr_dfi_p1_reset_n; end end always @(*) begin - litedramcore_master_p1_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n; + main_litedramcore_master_p1_act_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_act_n <= main_litedramcore_ext_dfi_p1_act_n; end else begin - litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; + main_litedramcore_master_p1_act_n <= main_litedramcore_slave_p1_act_n; end end else begin - litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n; + main_litedramcore_master_p1_act_n <= main_litedramcore_csr_dfi_p1_act_n; end end always @(*) begin - litedramcore_master_p1_wrdata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata; + main_litedramcore_master_p1_wrdata <= 64'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_wrdata <= main_litedramcore_ext_dfi_p1_wrdata; end else begin - litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; + main_litedramcore_master_p1_wrdata <= main_litedramcore_slave_p1_wrdata; end end else begin - litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata; + main_litedramcore_master_p1_wrdata <= main_litedramcore_csr_dfi_p1_wrdata; end end always @(*) begin - litedramcore_master_p1_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en; + main_litedramcore_master_p1_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_wrdata_en <= main_litedramcore_ext_dfi_p1_wrdata_en; end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; + main_litedramcore_master_p1_wrdata_en <= main_litedramcore_slave_p1_wrdata_en; end end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en; + main_litedramcore_master_p1_wrdata_en <= main_litedramcore_csr_dfi_p1_wrdata_en; end end always @(*) begin - litedramcore_master_p1_wrdata_mask <= 8'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask; + main_litedramcore_master_p1_wrdata_mask <= 8'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_ext_dfi_p1_wrdata_mask; end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; + main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_slave_p1_wrdata_mask; end end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask; + main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_csr_dfi_p1_wrdata_mask; end end always @(*) begin - litedramcore_master_p1_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en; + main_litedramcore_master_p1_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_rddata_en <= main_litedramcore_ext_dfi_p1_rddata_en; end else begin - litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; + main_litedramcore_master_p1_rddata_en <= main_litedramcore_slave_p1_rddata_en; end end else begin - litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en; + main_litedramcore_master_p1_rddata_en <= main_litedramcore_csr_dfi_p1_rddata_en; end end always @(*) begin - litedramcore_master_p2_address <= 15'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address; + main_litedramcore_master_p2_address <= 15'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_address <= main_litedramcore_ext_dfi_p2_address; end else begin - litedramcore_master_p2_address <= litedramcore_slave_p2_address; + main_litedramcore_master_p2_address <= main_litedramcore_slave_p2_address; end end else begin - litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address; + main_litedramcore_master_p2_address <= main_litedramcore_csr_dfi_p2_address; end end always @(*) begin - litedramcore_master_p2_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank; + main_litedramcore_master_p2_bank <= 3'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_bank <= main_litedramcore_ext_dfi_p2_bank; end else begin - litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; + main_litedramcore_master_p2_bank <= main_litedramcore_slave_p2_bank; end end else begin - litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank; + main_litedramcore_master_p2_bank <= main_litedramcore_csr_dfi_p2_bank; end end always @(*) begin - litedramcore_master_p2_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n; + main_litedramcore_master_p2_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_cas_n <= main_litedramcore_ext_dfi_p2_cas_n; end else begin - litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; + main_litedramcore_master_p2_cas_n <= main_litedramcore_slave_p2_cas_n; end end else begin - litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n; + main_litedramcore_master_p2_cas_n <= main_litedramcore_csr_dfi_p2_cas_n; end end always @(*) begin - litedramcore_master_p2_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n; + main_litedramcore_master_p2_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_cs_n <= main_litedramcore_ext_dfi_p2_cs_n; end else begin - litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; + main_litedramcore_master_p2_cs_n <= main_litedramcore_slave_p2_cs_n; + if (1'd0) begin + main_litedramcore_master_p2_cs_n <= {2{main_litedramcore_slave_p2_cs_n}}; + end end end else begin - litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n; + main_litedramcore_master_p2_cs_n <= main_litedramcore_csr_dfi_p2_cs_n; end end always @(*) begin - litedramcore_master_p2_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n; + main_litedramcore_master_p2_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_ras_n <= main_litedramcore_ext_dfi_p2_ras_n; end else begin - litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; + main_litedramcore_master_p2_ras_n <= main_litedramcore_slave_p2_ras_n; end end else begin - litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n; + main_litedramcore_master_p2_ras_n <= main_litedramcore_csr_dfi_p2_ras_n; end end always @(*) begin - litedramcore_master_p2_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n; + main_litedramcore_master_p2_we_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_we_n <= main_litedramcore_ext_dfi_p2_we_n; end else begin - litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; + main_litedramcore_master_p2_we_n <= main_litedramcore_slave_p2_we_n; end end else begin - litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n; + main_litedramcore_master_p2_we_n <= main_litedramcore_csr_dfi_p2_we_n; end end always @(*) begin - litedramcore_master_p2_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke; + main_litedramcore_master_p2_cke <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_cke <= main_litedramcore_ext_dfi_p2_cke; end else begin - litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; + main_litedramcore_master_p2_cke <= main_litedramcore_slave_p2_cke; end end else begin - litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke; + main_litedramcore_master_p2_cke <= main_litedramcore_csr_dfi_p2_cke; end end always @(*) begin - litedramcore_master_p2_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt; + main_litedramcore_master_p2_odt <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_odt <= main_litedramcore_ext_dfi_p2_odt; end else begin - litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; + main_litedramcore_master_p2_odt <= main_litedramcore_slave_p2_odt; end end else begin - litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt; + main_litedramcore_master_p2_odt <= main_litedramcore_csr_dfi_p2_odt; end end always @(*) begin - litedramcore_master_p2_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n; + main_litedramcore_master_p2_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_reset_n <= main_litedramcore_ext_dfi_p2_reset_n; end else begin - litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; + main_litedramcore_master_p2_reset_n <= main_litedramcore_slave_p2_reset_n; end end else begin - litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n; + main_litedramcore_master_p2_reset_n <= main_litedramcore_csr_dfi_p2_reset_n; end end always @(*) begin - litedramcore_master_p2_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n; + main_litedramcore_master_p2_act_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_act_n <= main_litedramcore_ext_dfi_p2_act_n; end else begin - litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; + main_litedramcore_master_p2_act_n <= main_litedramcore_slave_p2_act_n; end end else begin - litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n; + main_litedramcore_master_p2_act_n <= main_litedramcore_csr_dfi_p2_act_n; end end always @(*) begin - litedramcore_master_p2_wrdata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata; + main_litedramcore_master_p2_wrdata <= 64'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_wrdata <= main_litedramcore_ext_dfi_p2_wrdata; end else begin - litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; + main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata; end end else begin - litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata; + main_litedramcore_master_p2_wrdata <= main_litedramcore_csr_dfi_p2_wrdata; end end always @(*) begin - litedramcore_master_p2_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en; + main_litedramcore_master_p2_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_wrdata_en <= main_litedramcore_ext_dfi_p2_wrdata_en; end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; + main_litedramcore_master_p2_wrdata_en <= main_litedramcore_slave_p2_wrdata_en; end end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en; + main_litedramcore_master_p2_wrdata_en <= main_litedramcore_csr_dfi_p2_wrdata_en; end end always @(*) begin - litedramcore_master_p2_wrdata_mask <= 8'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask; + main_litedramcore_master_p2_wrdata_mask <= 8'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_ext_dfi_p2_wrdata_mask; end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; + main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_slave_p2_wrdata_mask; end end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask; + main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_csr_dfi_p2_wrdata_mask; end end always @(*) begin - litedramcore_master_p2_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en; + main_litedramcore_master_p2_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_rddata_en <= main_litedramcore_ext_dfi_p2_rddata_en; end else begin - litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; + main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en; end end else begin - litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en; + main_litedramcore_master_p2_rddata_en <= main_litedramcore_csr_dfi_p2_rddata_en; end end always @(*) begin - litedramcore_master_p3_address <= 15'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address; + main_litedramcore_master_p3_address <= 15'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_address <= main_litedramcore_ext_dfi_p3_address; end else begin - litedramcore_master_p3_address <= litedramcore_slave_p3_address; + main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address; end end else begin - litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address; + main_litedramcore_master_p3_address <= main_litedramcore_csr_dfi_p3_address; end end always @(*) begin - litedramcore_master_p3_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank; + main_litedramcore_master_p3_bank <= 3'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_bank <= main_litedramcore_ext_dfi_p3_bank; end else begin - litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; + main_litedramcore_master_p3_bank <= main_litedramcore_slave_p3_bank; end end else begin - litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank; + main_litedramcore_master_p3_bank <= main_litedramcore_csr_dfi_p3_bank; end end always @(*) begin - litedramcore_master_p3_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n; + main_litedramcore_master_p3_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_cas_n <= main_litedramcore_ext_dfi_p3_cas_n; end else begin - litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; + main_litedramcore_master_p3_cas_n <= main_litedramcore_slave_p3_cas_n; end end else begin - litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n; + main_litedramcore_master_p3_cas_n <= main_litedramcore_csr_dfi_p3_cas_n; end end always @(*) begin - litedramcore_master_p3_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n; + main_litedramcore_master_p3_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_cs_n <= main_litedramcore_ext_dfi_p3_cs_n; end else begin - litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; + main_litedramcore_master_p3_cs_n <= main_litedramcore_slave_p3_cs_n; + if (1'd0) begin + main_litedramcore_master_p3_cs_n <= {2{main_litedramcore_slave_p3_cs_n}}; + end end end else begin - litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n; + main_litedramcore_master_p3_cs_n <= main_litedramcore_csr_dfi_p3_cs_n; end end always @(*) begin - litedramcore_master_p3_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n; + main_litedramcore_master_p3_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_ras_n <= main_litedramcore_ext_dfi_p3_ras_n; end else begin - litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; + main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n; end end else begin - litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n; + main_litedramcore_master_p3_ras_n <= main_litedramcore_csr_dfi_p3_ras_n; end end always @(*) begin - litedramcore_master_p3_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n; + main_litedramcore_master_p3_we_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_we_n <= main_litedramcore_ext_dfi_p3_we_n; end else begin - litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; + main_litedramcore_master_p3_we_n <= main_litedramcore_slave_p3_we_n; end end else begin - litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n; + main_litedramcore_master_p3_we_n <= main_litedramcore_csr_dfi_p3_we_n; end end always @(*) begin - litedramcore_master_p3_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke; + main_litedramcore_master_p3_cke <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_cke <= main_litedramcore_ext_dfi_p3_cke; end else begin - litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; + main_litedramcore_master_p3_cke <= main_litedramcore_slave_p3_cke; end end else begin - litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke; + main_litedramcore_master_p3_cke <= main_litedramcore_csr_dfi_p3_cke; end end always @(*) begin - litedramcore_master_p3_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt; + main_litedramcore_master_p3_odt <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_odt <= main_litedramcore_ext_dfi_p3_odt; end else begin - litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; + main_litedramcore_master_p3_odt <= main_litedramcore_slave_p3_odt; end end else begin - litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt; + main_litedramcore_master_p3_odt <= main_litedramcore_csr_dfi_p3_odt; end end always @(*) begin - litedramcore_master_p3_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n; + main_litedramcore_master_p3_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_reset_n <= main_litedramcore_ext_dfi_p3_reset_n; end else begin - litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; + main_litedramcore_master_p3_reset_n <= main_litedramcore_slave_p3_reset_n; end end else begin - litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n; + main_litedramcore_master_p3_reset_n <= main_litedramcore_csr_dfi_p3_reset_n; end end always @(*) begin - litedramcore_master_p3_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n; + main_litedramcore_master_p3_act_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_act_n <= main_litedramcore_ext_dfi_p3_act_n; end else begin - litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; + main_litedramcore_master_p3_act_n <= main_litedramcore_slave_p3_act_n; end end else begin - litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n; + main_litedramcore_master_p3_act_n <= main_litedramcore_csr_dfi_p3_act_n; end end always @(*) begin - litedramcore_master_p3_wrdata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata; + main_litedramcore_master_p3_wrdata <= 64'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_wrdata <= main_litedramcore_ext_dfi_p3_wrdata; end else begin - litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; + main_litedramcore_master_p3_wrdata <= main_litedramcore_slave_p3_wrdata; end end else begin - litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata; + main_litedramcore_master_p3_wrdata <= main_litedramcore_csr_dfi_p3_wrdata; end end always @(*) begin - litedramcore_master_p3_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en; + main_litedramcore_master_p3_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_wrdata_en <= main_litedramcore_ext_dfi_p3_wrdata_en; end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; + main_litedramcore_master_p3_wrdata_en <= main_litedramcore_slave_p3_wrdata_en; end end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en; + main_litedramcore_master_p3_wrdata_en <= main_litedramcore_csr_dfi_p3_wrdata_en; end end always @(*) begin - litedramcore_master_p3_wrdata_mask <= 8'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask; + main_litedramcore_master_p3_wrdata_mask <= 8'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_ext_dfi_p3_wrdata_mask; end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; + main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_slave_p3_wrdata_mask; end end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask; + main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_csr_dfi_p3_wrdata_mask; end end always @(*) begin - litedramcore_master_p3_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en; + main_litedramcore_master_p3_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_rddata_en <= main_litedramcore_ext_dfi_p3_rddata_en; end else begin - litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; + main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en; end end else begin - litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en; - end -end -assign litedramcore_csr_dfi_p0_cke = litedramcore_cke; -assign litedramcore_csr_dfi_p1_cke = litedramcore_cke; -assign litedramcore_csr_dfi_p2_cke = litedramcore_cke; -assign litedramcore_csr_dfi_p3_cke = litedramcore_cke; -assign litedramcore_csr_dfi_p0_odt = litedramcore_odt; -assign litedramcore_csr_dfi_p1_odt = litedramcore_odt; -assign litedramcore_csr_dfi_p2_odt = litedramcore_odt; -assign litedramcore_csr_dfi_p3_odt = litedramcore_odt; -assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n; -assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n; -assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n; -assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n; -always @(*) begin - litedramcore_csr_dfi_p0_cs_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}}; + main_litedramcore_master_p3_rddata_en <= main_litedramcore_csr_dfi_p3_rddata_en; + end +end +always @(*) begin + main_litedramcore_csr_dfi_p0_cke <= 1'd0; + main_litedramcore_csr_dfi_p0_cke <= main_litedramcore_cke; +end +always @(*) begin + main_litedramcore_csr_dfi_p1_cke <= 1'd0; + main_litedramcore_csr_dfi_p1_cke <= main_litedramcore_cke; +end +always @(*) begin + main_litedramcore_csr_dfi_p2_cke <= 1'd0; + main_litedramcore_csr_dfi_p2_cke <= main_litedramcore_cke; +end +always @(*) begin + main_litedramcore_csr_dfi_p3_cke <= 1'd0; + main_litedramcore_csr_dfi_p3_cke <= main_litedramcore_cke; +end +always @(*) begin + main_litedramcore_csr_dfi_p0_odt <= 1'd0; + main_litedramcore_csr_dfi_p0_odt <= main_litedramcore_odt; +end +always @(*) begin + main_litedramcore_csr_dfi_p1_odt <= 1'd0; + main_litedramcore_csr_dfi_p1_odt <= main_litedramcore_odt; +end +always @(*) begin + main_litedramcore_csr_dfi_p2_odt <= 1'd0; + main_litedramcore_csr_dfi_p2_odt <= main_litedramcore_odt; +end +always @(*) begin + main_litedramcore_csr_dfi_p3_odt <= 1'd0; + main_litedramcore_csr_dfi_p3_odt <= main_litedramcore_odt; +end +assign main_litedramcore_csr_dfi_p0_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_csr_dfi_p1_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_csr_dfi_p2_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_csr_dfi_p3_reset_n = main_litedramcore_reset_n; +always @(*) begin + main_litedramcore_csr_dfi_p0_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + if (main_litedramcore_phaseinjector0_csrfield_cs_top) begin + main_litedramcore_csr_dfi_p0_cs_n <= 2'd2; + end else begin + if (main_litedramcore_phaseinjector0_csrfield_cs_bottom) begin + main_litedramcore_csr_dfi_p0_cs_n <= 1'd1; + end else begin + main_litedramcore_csr_dfi_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_csrfield_cs)}}; + end + end end else begin - litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; + main_litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; end end always @(*) begin - litedramcore_csr_dfi_p0_ras_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras); + main_litedramcore_csr_dfi_p0_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_csr_dfi_p0_ras_n <= (~main_litedramcore_phaseinjector0_csrfield_ras); end else begin - litedramcore_csr_dfi_p0_ras_n <= 1'd1; + main_litedramcore_csr_dfi_p0_ras_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we); + main_litedramcore_csr_dfi_p0_we_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_csr_dfi_p0_we_n <= (~main_litedramcore_phaseinjector0_csrfield_we); end else begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; + main_litedramcore_csr_dfi_p0_we_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p0_cas_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas); + main_litedramcore_csr_dfi_p0_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_csr_dfi_p0_cas_n <= (~main_litedramcore_phaseinjector0_csrfield_cas); end else begin - litedramcore_csr_dfi_p0_cas_n <= 1'd1; + main_litedramcore_csr_dfi_p0_cas_n <= 1'd1; end end -assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage; -assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage; -assign litedramcore_csr_dfi_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_wren); -assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_rden); -assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; -assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; +assign main_litedramcore_csr_dfi_p0_address = main_litedramcore_phaseinjector0_address_storage; +assign main_litedramcore_csr_dfi_p0_bank = main_litedramcore_phaseinjector0_baddress_storage; +assign main_litedramcore_csr_dfi_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_wren); +assign main_litedramcore_csr_dfi_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_rden); +assign main_litedramcore_csr_dfi_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage; +assign main_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p1_cs_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}}; + main_litedramcore_csr_dfi_p1_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + if (main_litedramcore_phaseinjector1_csrfield_cs_top) begin + main_litedramcore_csr_dfi_p1_cs_n <= 2'd2; + end else begin + if (main_litedramcore_phaseinjector1_csrfield_cs_bottom) begin + main_litedramcore_csr_dfi_p1_cs_n <= 1'd1; + end else begin + main_litedramcore_csr_dfi_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_csrfield_cs)}}; + end + end end else begin - litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; + main_litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; end end always @(*) begin - litedramcore_csr_dfi_p1_ras_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras); + main_litedramcore_csr_dfi_p1_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_csr_dfi_p1_ras_n <= (~main_litedramcore_phaseinjector1_csrfield_ras); end else begin - litedramcore_csr_dfi_p1_ras_n <= 1'd1; + main_litedramcore_csr_dfi_p1_ras_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we); + main_litedramcore_csr_dfi_p1_we_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_csr_dfi_p1_we_n <= (~main_litedramcore_phaseinjector1_csrfield_we); end else begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; + main_litedramcore_csr_dfi_p1_we_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p1_cas_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas); + main_litedramcore_csr_dfi_p1_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_csr_dfi_p1_cas_n <= (~main_litedramcore_phaseinjector1_csrfield_cas); end else begin - litedramcore_csr_dfi_p1_cas_n <= 1'd1; + main_litedramcore_csr_dfi_p1_cas_n <= 1'd1; end end -assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage; -assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage; -assign litedramcore_csr_dfi_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_wren); -assign litedramcore_csr_dfi_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_rden); -assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; -assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; +assign main_litedramcore_csr_dfi_p1_address = main_litedramcore_phaseinjector1_address_storage; +assign main_litedramcore_csr_dfi_p1_bank = main_litedramcore_phaseinjector1_baddress_storage; +assign main_litedramcore_csr_dfi_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_wren); +assign main_litedramcore_csr_dfi_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_rden); +assign main_litedramcore_csr_dfi_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage; +assign main_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p2_cs_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}}; + main_litedramcore_csr_dfi_p2_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + if (main_litedramcore_phaseinjector2_csrfield_cs_top) begin + main_litedramcore_csr_dfi_p2_cs_n <= 2'd2; + end else begin + if (main_litedramcore_phaseinjector2_csrfield_cs_bottom) begin + main_litedramcore_csr_dfi_p2_cs_n <= 1'd1; + end else begin + main_litedramcore_csr_dfi_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_csrfield_cs)}}; + end + end end else begin - litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; + main_litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; end end always @(*) begin - litedramcore_csr_dfi_p2_ras_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras); + main_litedramcore_csr_dfi_p2_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_csr_dfi_p2_ras_n <= (~main_litedramcore_phaseinjector2_csrfield_ras); end else begin - litedramcore_csr_dfi_p2_ras_n <= 1'd1; + main_litedramcore_csr_dfi_p2_ras_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p2_we_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we); + main_litedramcore_csr_dfi_p2_we_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_csr_dfi_p2_we_n <= (~main_litedramcore_phaseinjector2_csrfield_we); end else begin - litedramcore_csr_dfi_p2_we_n <= 1'd1; + main_litedramcore_csr_dfi_p2_we_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p2_cas_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas); + main_litedramcore_csr_dfi_p2_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_csr_dfi_p2_cas_n <= (~main_litedramcore_phaseinjector2_csrfield_cas); end else begin - litedramcore_csr_dfi_p2_cas_n <= 1'd1; + main_litedramcore_csr_dfi_p2_cas_n <= 1'd1; end end -assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage; -assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage; -assign litedramcore_csr_dfi_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_wren); -assign litedramcore_csr_dfi_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_rden); -assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage; -assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; +assign main_litedramcore_csr_dfi_p2_address = main_litedramcore_phaseinjector2_address_storage; +assign main_litedramcore_csr_dfi_p2_bank = main_litedramcore_phaseinjector2_baddress_storage; +assign main_litedramcore_csr_dfi_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_wren); +assign main_litedramcore_csr_dfi_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_rden); +assign main_litedramcore_csr_dfi_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage; +assign main_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p3_cs_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}}; + main_litedramcore_csr_dfi_p3_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + if (main_litedramcore_phaseinjector3_csrfield_cs_top) begin + main_litedramcore_csr_dfi_p3_cs_n <= 2'd2; + end else begin + if (main_litedramcore_phaseinjector3_csrfield_cs_bottom) begin + main_litedramcore_csr_dfi_p3_cs_n <= 1'd1; + end else begin + main_litedramcore_csr_dfi_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_csrfield_cs)}}; + end + end end else begin - litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; + main_litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; end end always @(*) begin - litedramcore_csr_dfi_p3_ras_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras); + main_litedramcore_csr_dfi_p3_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_csr_dfi_p3_ras_n <= (~main_litedramcore_phaseinjector3_csrfield_ras); end else begin - litedramcore_csr_dfi_p3_ras_n <= 1'd1; + main_litedramcore_csr_dfi_p3_ras_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p3_we_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we); + main_litedramcore_csr_dfi_p3_we_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_csr_dfi_p3_we_n <= (~main_litedramcore_phaseinjector3_csrfield_we); end else begin - litedramcore_csr_dfi_p3_we_n <= 1'd1; + main_litedramcore_csr_dfi_p3_we_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p3_cas_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas); + main_litedramcore_csr_dfi_p3_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_csr_dfi_p3_cas_n <= (~main_litedramcore_phaseinjector3_csrfield_cas); end else begin - litedramcore_csr_dfi_p3_cas_n <= 1'd1; - end -end -assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage; -assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage; -assign litedramcore_csr_dfi_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_wren); -assign litedramcore_csr_dfi_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_rden); -assign litedramcore_csr_dfi_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage; -assign litedramcore_csr_dfi_p3_wrdata_mask = 1'd0; -assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid; -assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready; -assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we; -assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr; -assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock; -assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready; -assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid; -assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid; -assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready; -assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we; -assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr; -assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock; -assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready; -assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid; -assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid; -assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready; -assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we; -assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr; -assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock; -assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready; -assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid; -assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid; -assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready; -assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we; -assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr; -assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock; -assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready; -assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid; -assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid; -assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready; -assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we; -assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr; -assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock; -assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready; -assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid; -assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid; -assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready; -assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we; -assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr; -assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock; -assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready; -assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid; -assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid; -assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready; -assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we; -assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr; -assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock; -assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready; -assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid; -assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid; -assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready; -assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we; -assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr; -assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock; -assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready; -assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid; -assign litedramcore_timer_wait = (~litedramcore_timer_done0); -assign litedramcore_postponer_req_i = litedramcore_timer_done0; -assign litedramcore_wants_refresh = litedramcore_postponer_req_o; -assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0; -assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done); -assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0); -assign litedramcore_timer_done0 = litedramcore_timer_done1; -assign litedramcore_timer_count0 = litedramcore_timer_count1; -assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0)); -assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0)); -assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0); -assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1; -assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1; -always @(*) begin - litedramcore_refresher_next_state <= 2'd0; - litedramcore_refresher_next_state <= litedramcore_refresher_state; - case (litedramcore_refresher_state) - 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_refresher_next_state <= 2'd2; - end - end - 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - litedramcore_refresher_next_state <= 2'd3; + main_litedramcore_csr_dfi_p3_cas_n <= 1'd1; + end +end +assign main_litedramcore_csr_dfi_p3_address = main_litedramcore_phaseinjector3_address_storage; +assign main_litedramcore_csr_dfi_p3_bank = main_litedramcore_phaseinjector3_baddress_storage; +assign main_litedramcore_csr_dfi_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_wren); +assign main_litedramcore_csr_dfi_p3_rddata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_rden); +assign main_litedramcore_csr_dfi_p3_wrdata = main_litedramcore_phaseinjector3_wrdata_storage; +assign main_litedramcore_csr_dfi_p3_wrdata_mask = 1'd0; +assign main_litedramcore_bankmachine0_req_valid = main_litedramcore_interface_bank0_valid; +assign main_litedramcore_interface_bank0_ready = main_litedramcore_bankmachine0_req_ready; +assign main_litedramcore_bankmachine0_req_we = main_litedramcore_interface_bank0_we; +assign main_litedramcore_bankmachine0_req_addr = main_litedramcore_interface_bank0_addr; +assign main_litedramcore_interface_bank0_lock = main_litedramcore_bankmachine0_req_lock; +assign main_litedramcore_interface_bank0_wdata_ready = main_litedramcore_bankmachine0_req_wdata_ready; +assign main_litedramcore_interface_bank0_rdata_valid = main_litedramcore_bankmachine0_req_rdata_valid; +assign main_litedramcore_bankmachine1_req_valid = main_litedramcore_interface_bank1_valid; +assign main_litedramcore_interface_bank1_ready = main_litedramcore_bankmachine1_req_ready; +assign main_litedramcore_bankmachine1_req_we = main_litedramcore_interface_bank1_we; +assign main_litedramcore_bankmachine1_req_addr = main_litedramcore_interface_bank1_addr; +assign main_litedramcore_interface_bank1_lock = main_litedramcore_bankmachine1_req_lock; +assign main_litedramcore_interface_bank1_wdata_ready = main_litedramcore_bankmachine1_req_wdata_ready; +assign main_litedramcore_interface_bank1_rdata_valid = main_litedramcore_bankmachine1_req_rdata_valid; +assign main_litedramcore_bankmachine2_req_valid = main_litedramcore_interface_bank2_valid; +assign main_litedramcore_interface_bank2_ready = main_litedramcore_bankmachine2_req_ready; +assign main_litedramcore_bankmachine2_req_we = main_litedramcore_interface_bank2_we; +assign main_litedramcore_bankmachine2_req_addr = main_litedramcore_interface_bank2_addr; +assign main_litedramcore_interface_bank2_lock = main_litedramcore_bankmachine2_req_lock; +assign main_litedramcore_interface_bank2_wdata_ready = main_litedramcore_bankmachine2_req_wdata_ready; +assign main_litedramcore_interface_bank2_rdata_valid = main_litedramcore_bankmachine2_req_rdata_valid; +assign main_litedramcore_bankmachine3_req_valid = main_litedramcore_interface_bank3_valid; +assign main_litedramcore_interface_bank3_ready = main_litedramcore_bankmachine3_req_ready; +assign main_litedramcore_bankmachine3_req_we = main_litedramcore_interface_bank3_we; +assign main_litedramcore_bankmachine3_req_addr = main_litedramcore_interface_bank3_addr; +assign main_litedramcore_interface_bank3_lock = main_litedramcore_bankmachine3_req_lock; +assign main_litedramcore_interface_bank3_wdata_ready = main_litedramcore_bankmachine3_req_wdata_ready; +assign main_litedramcore_interface_bank3_rdata_valid = main_litedramcore_bankmachine3_req_rdata_valid; +assign main_litedramcore_bankmachine4_req_valid = main_litedramcore_interface_bank4_valid; +assign main_litedramcore_interface_bank4_ready = main_litedramcore_bankmachine4_req_ready; +assign main_litedramcore_bankmachine4_req_we = main_litedramcore_interface_bank4_we; +assign main_litedramcore_bankmachine4_req_addr = main_litedramcore_interface_bank4_addr; +assign main_litedramcore_interface_bank4_lock = main_litedramcore_bankmachine4_req_lock; +assign main_litedramcore_interface_bank4_wdata_ready = main_litedramcore_bankmachine4_req_wdata_ready; +assign main_litedramcore_interface_bank4_rdata_valid = main_litedramcore_bankmachine4_req_rdata_valid; +assign main_litedramcore_bankmachine5_req_valid = main_litedramcore_interface_bank5_valid; +assign main_litedramcore_interface_bank5_ready = main_litedramcore_bankmachine5_req_ready; +assign main_litedramcore_bankmachine5_req_we = main_litedramcore_interface_bank5_we; +assign main_litedramcore_bankmachine5_req_addr = main_litedramcore_interface_bank5_addr; +assign main_litedramcore_interface_bank5_lock = main_litedramcore_bankmachine5_req_lock; +assign main_litedramcore_interface_bank5_wdata_ready = main_litedramcore_bankmachine5_req_wdata_ready; +assign main_litedramcore_interface_bank5_rdata_valid = main_litedramcore_bankmachine5_req_rdata_valid; +assign main_litedramcore_bankmachine6_req_valid = main_litedramcore_interface_bank6_valid; +assign main_litedramcore_interface_bank6_ready = main_litedramcore_bankmachine6_req_ready; +assign main_litedramcore_bankmachine6_req_we = main_litedramcore_interface_bank6_we; +assign main_litedramcore_bankmachine6_req_addr = main_litedramcore_interface_bank6_addr; +assign main_litedramcore_interface_bank6_lock = main_litedramcore_bankmachine6_req_lock; +assign main_litedramcore_interface_bank6_wdata_ready = main_litedramcore_bankmachine6_req_wdata_ready; +assign main_litedramcore_interface_bank6_rdata_valid = main_litedramcore_bankmachine6_req_rdata_valid; +assign main_litedramcore_bankmachine7_req_valid = main_litedramcore_interface_bank7_valid; +assign main_litedramcore_interface_bank7_ready = main_litedramcore_bankmachine7_req_ready; +assign main_litedramcore_bankmachine7_req_we = main_litedramcore_interface_bank7_we; +assign main_litedramcore_bankmachine7_req_addr = main_litedramcore_interface_bank7_addr; +assign main_litedramcore_interface_bank7_lock = main_litedramcore_bankmachine7_req_lock; +assign main_litedramcore_interface_bank7_wdata_ready = main_litedramcore_bankmachine7_req_wdata_ready; +assign main_litedramcore_interface_bank7_rdata_valid = main_litedramcore_bankmachine7_req_rdata_valid; +assign main_litedramcore_timer_wait = (~main_litedramcore_timer_done0); +assign main_litedramcore_postponer_req_i = main_litedramcore_timer_done0; +assign main_litedramcore_wants_refresh = main_litedramcore_postponer_req_o; +assign main_litedramcore_wants_zqcs = main_litedramcore_zqcs_timer_done0; +assign main_litedramcore_zqcs_timer_wait = (~main_litedramcore_zqcs_executer_done); +assign main_litedramcore_timer_done1 = (main_litedramcore_timer_count1 == 1'd0); +assign main_litedramcore_timer_done0 = main_litedramcore_timer_done1; +assign main_litedramcore_timer_count0 = main_litedramcore_timer_count1; +assign main_litedramcore_sequencer_start1 = (main_litedramcore_sequencer_start0 | (main_litedramcore_sequencer_count != 1'd0)); +assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & (main_litedramcore_sequencer_count == 1'd0)); +assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0); +assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1; +assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1; +always @(*) begin + builder_refresher_next_state <= 2'd0; + builder_refresher_next_state <= builder_refresher_state; + case (builder_refresher_state) + 1'd1: begin + if (main_litedramcore_cmd_ready) begin + builder_refresher_next_state <= 2'd2; + end + end + 2'd2: begin + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + builder_refresher_next_state <= 2'd3; end else begin - litedramcore_refresher_next_state <= 1'd0; + builder_refresher_next_state <= 1'd0; end end end 2'd3: begin - if (litedramcore_zqcs_executer_done) begin - litedramcore_refresher_next_state <= 1'd0; + if (main_litedramcore_zqcs_executer_done) begin + builder_refresher_next_state <= 1'd0; end end default: begin if (1'd1) begin - if (litedramcore_wants_refresh) begin - litedramcore_refresher_next_state <= 1'd1; + if (main_litedramcore_wants_refresh) begin + builder_refresher_next_state <= 1'd1; end end end endcase end always @(*) begin - litedramcore_cmd_valid <= 1'd0; - case (litedramcore_refresher_state) + main_litedramcore_sequencer_start0 <= 1'd0; + case (builder_refresher_state) 1'd1: begin - litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_cmd_ready) begin + main_litedramcore_sequencer_start0 <= 1'd1; + end end 2'd2: begin - litedramcore_cmd_valid <= 1'd1; - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - end else begin - litedramcore_cmd_valid <= 1'd0; - end - end end 2'd3: begin - litedramcore_cmd_valid <= 1'd1; - if (litedramcore_zqcs_executer_done) begin - litedramcore_cmd_valid <= 1'd0; - end end default: begin end endcase end always @(*) begin - litedramcore_zqcs_executer_start <= 1'd0; - case (litedramcore_refresher_state) + main_litedramcore_cmd_valid <= 1'd0; + case (builder_refresher_state) 1'd1: begin + main_litedramcore_cmd_valid <= 1'd1; end 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - litedramcore_zqcs_executer_start <= 1'd1; + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin end else begin + main_litedramcore_cmd_valid <= 1'd0; end end end 2'd3: begin + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_valid <= 1'd0; + end end default: begin end endcase end always @(*) begin - litedramcore_cmd_last <= 1'd0; - case (litedramcore_refresher_state) + main_litedramcore_zqcs_executer_start <= 1'd0; + case (builder_refresher_state) 1'd1: begin end 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + main_litedramcore_zqcs_executer_start <= 1'd1; end else begin - litedramcore_cmd_last <= 1'd1; end end end 2'd3: begin - if (litedramcore_zqcs_executer_done) begin - litedramcore_cmd_last <= 1'd1; - end end default: begin end endcase end always @(*) begin - litedramcore_sequencer_start0 <= 1'd0; - case (litedramcore_refresher_state) + main_litedramcore_cmd_last <= 1'd0; + case (builder_refresher_state) 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_sequencer_start0 <= 1'd1; - end end 2'd2: begin + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + end else begin + main_litedramcore_cmd_last <= 1'd1; + end + end end 2'd3: begin + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_last <= 1'd1; + end end default: begin end endcase end -assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid; -assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready; -assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we; -assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr; -assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid; -assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready; -assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first; -assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last; -assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we; -assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr; -assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); -assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid); -assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[21:7]); -assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0; -always @(*) begin - litedramcore_bankmachine0_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine0_row_col_n_addr_sel) begin - litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_source_source_payload_addr[21:7]; +assign main_litedramcore_bankmachine0_sink_valid = main_litedramcore_bankmachine0_req_valid; +assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_sink_ready; +assign main_litedramcore_bankmachine0_sink_payload_we = main_litedramcore_bankmachine0_req_we; +assign main_litedramcore_bankmachine0_sink_payload_addr = main_litedramcore_bankmachine0_req_addr; +assign main_litedramcore_bankmachine0_sink_sink_valid = main_litedramcore_bankmachine0_source_valid; +assign main_litedramcore_bankmachine0_source_ready = main_litedramcore_bankmachine0_sink_sink_ready; +assign main_litedramcore_bankmachine0_sink_sink_first = main_litedramcore_bankmachine0_source_first; +assign main_litedramcore_bankmachine0_sink_sink_last = main_litedramcore_bankmachine0_source_last; +assign main_litedramcore_bankmachine0_sink_sink_payload_we = main_litedramcore_bankmachine0_source_payload_we; +assign main_litedramcore_bankmachine0_sink_sink_payload_addr = main_litedramcore_bankmachine0_source_payload_addr; +assign main_litedramcore_bankmachine0_source_source_ready = (main_litedramcore_bankmachine0_req_wdata_ready | main_litedramcore_bankmachine0_req_rdata_valid); +assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_source_valid | main_litedramcore_bankmachine0_source_source_valid); +assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_source_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0; +always @(*) begin + main_litedramcore_bankmachine0_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin + main_litedramcore_bankmachine0_cmd_payload_a <= main_litedramcore_bankmachine0_source_source_payload_addr[21:7]; end else begin - litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write); -assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); -assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); -always @(*) begin - litedramcore_bankmachine0_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin - if ((litedramcore_bankmachine0_source_payload_addr[21:7] != litedramcore_bankmachine0_source_source_payload_addr[21:7])) begin - litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we}; -assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; -assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; -assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; -assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; -assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable; -assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid; -assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first; -assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last; -assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we; -assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr; -assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable; -assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first; -assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last; -assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we; -assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr; -assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready; -always @(*) begin - litedramcore_bankmachine0_wrport_adr <= 4'd0; - if (litedramcore_bankmachine0_replace) begin - litedramcore_bankmachine0_wrport_adr <= (litedramcore_bankmachine0_produce - 1'd1); + main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write); +assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); +assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); +always @(*) begin + main_litedramcore_bankmachine0_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine0_source_valid & main_litedramcore_bankmachine0_source_source_valid)) begin + if ((main_litedramcore_bankmachine0_source_payload_addr[21:7] != main_litedramcore_bankmachine0_source_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine0_syncfifo0_din = {main_litedramcore_bankmachine0_fifo_in_last, main_litedramcore_bankmachine0_fifo_in_first, main_litedramcore_bankmachine0_fifo_in_payload_addr, main_litedramcore_bankmachine0_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout; +assign main_litedramcore_bankmachine0_sink_ready = main_litedramcore_bankmachine0_syncfifo0_writable; +assign main_litedramcore_bankmachine0_syncfifo0_we = main_litedramcore_bankmachine0_sink_valid; +assign main_litedramcore_bankmachine0_fifo_in_first = main_litedramcore_bankmachine0_sink_first; +assign main_litedramcore_bankmachine0_fifo_in_last = main_litedramcore_bankmachine0_sink_last; +assign main_litedramcore_bankmachine0_fifo_in_payload_we = main_litedramcore_bankmachine0_sink_payload_we; +assign main_litedramcore_bankmachine0_fifo_in_payload_addr = main_litedramcore_bankmachine0_sink_payload_addr; +assign main_litedramcore_bankmachine0_source_valid = main_litedramcore_bankmachine0_syncfifo0_readable; +assign main_litedramcore_bankmachine0_source_first = main_litedramcore_bankmachine0_fifo_out_first; +assign main_litedramcore_bankmachine0_source_last = main_litedramcore_bankmachine0_fifo_out_last; +assign main_litedramcore_bankmachine0_source_payload_we = main_litedramcore_bankmachine0_fifo_out_payload_we; +assign main_litedramcore_bankmachine0_source_payload_addr = main_litedramcore_bankmachine0_fifo_out_payload_addr; +assign main_litedramcore_bankmachine0_syncfifo0_re = main_litedramcore_bankmachine0_source_ready; +always @(*) begin + main_litedramcore_bankmachine0_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine0_replace) begin + main_litedramcore_bankmachine0_wrport_adr <= (main_litedramcore_bankmachine0_produce - 1'd1); end else begin - litedramcore_bankmachine0_wrport_adr <= litedramcore_bankmachine0_produce; - end -end -assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din; -assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace)); -assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re); -assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume; -assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r; -assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 5'd16); -assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0); -assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready); -assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid; -assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready; -assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first; -assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last; -assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we; -assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr; -assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid; -assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready; -assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first; -assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last; -assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we; -assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine0_next_state <= 4'd0; - litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - if (litedramcore_bankmachine0_cmd_ready) begin - litedramcore_bankmachine0_next_state <= 3'd5; + main_litedramcore_bankmachine0_wrport_adr <= main_litedramcore_bankmachine0_produce; + end +end +assign main_litedramcore_bankmachine0_wrport_dat_w = main_litedramcore_bankmachine0_syncfifo0_din; +assign main_litedramcore_bankmachine0_wrport_we = (main_litedramcore_bankmachine0_syncfifo0_we & (main_litedramcore_bankmachine0_syncfifo0_writable | main_litedramcore_bankmachine0_replace)); +assign main_litedramcore_bankmachine0_do_read = (main_litedramcore_bankmachine0_syncfifo0_readable & main_litedramcore_bankmachine0_syncfifo0_re); +assign main_litedramcore_bankmachine0_rdport_adr = main_litedramcore_bankmachine0_consume; +assign main_litedramcore_bankmachine0_syncfifo0_dout = main_litedramcore_bankmachine0_rdport_dat_r; +assign main_litedramcore_bankmachine0_syncfifo0_writable = (main_litedramcore_bankmachine0_level != 5'd16); +assign main_litedramcore_bankmachine0_syncfifo0_readable = (main_litedramcore_bankmachine0_level != 1'd0); +assign main_litedramcore_bankmachine0_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine0_pipe_valid_source_valid) | main_litedramcore_bankmachine0_pipe_valid_source_ready); +assign main_litedramcore_bankmachine0_pipe_valid_sink_valid = main_litedramcore_bankmachine0_sink_sink_valid; +assign main_litedramcore_bankmachine0_sink_sink_ready = main_litedramcore_bankmachine0_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine0_pipe_valid_sink_first = main_litedramcore_bankmachine0_sink_sink_first; +assign main_litedramcore_bankmachine0_pipe_valid_sink_last = main_litedramcore_bankmachine0_sink_sink_last; +assign main_litedramcore_bankmachine0_pipe_valid_sink_payload_we = main_litedramcore_bankmachine0_sink_sink_payload_we; +assign main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine0_sink_sink_payload_addr; +assign main_litedramcore_bankmachine0_source_source_valid = main_litedramcore_bankmachine0_pipe_valid_source_valid; +assign main_litedramcore_bankmachine0_pipe_valid_source_ready = main_litedramcore_bankmachine0_source_source_ready; +assign main_litedramcore_bankmachine0_source_source_first = main_litedramcore_bankmachine0_pipe_valid_source_first; +assign main_litedramcore_bankmachine0_source_source_last = main_litedramcore_bankmachine0_pipe_valid_source_last; +assign main_litedramcore_bankmachine0_source_source_payload_we = main_litedramcore_bankmachine0_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine0_source_source_payload_addr = main_litedramcore_bankmachine0_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine0_next_state <= 4'd0; + builder_bankmachine0_next_state <= builder_bankmachine0_state; + case (builder_bankmachine0_state) + 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + if (main_litedramcore_bankmachine0_cmd_ready) begin + builder_bankmachine0_next_state <= 3'd5; end end end 2'd2: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_next_state <= 3'd5; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + builder_bankmachine0_next_state <= 3'd5; end end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - if (litedramcore_bankmachine0_cmd_ready) begin - litedramcore_bankmachine0_next_state <= 3'd7; + if (main_litedramcore_bankmachine0_trccon_ready) begin + if (main_litedramcore_bankmachine0_cmd_ready) begin + builder_bankmachine0_next_state <= 3'd7; end end end 3'd4: begin - if ((~litedramcore_bankmachine0_refresh_req)) begin - litedramcore_bankmachine0_next_state <= 1'd0; + if ((~main_litedramcore_bankmachine0_refresh_req)) begin + builder_bankmachine0_next_state <= 1'd0; end end 3'd5: begin - litedramcore_bankmachine0_next_state <= 3'd6; + builder_bankmachine0_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine0_next_state <= 2'd3; + builder_bankmachine0_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine0_next_state <= 4'd8; + builder_bankmachine0_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine0_next_state <= 1'd0; + builder_bankmachine0_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - litedramcore_bankmachine0_next_state <= 3'd4; + if (main_litedramcore_bankmachine0_refresh_req) begin + builder_bankmachine0_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin - litedramcore_bankmachine0_next_state <= 2'd2; + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if ((main_litedramcore_bankmachine0_cmd_ready & main_litedramcore_bankmachine0_auto_precharge)) begin + builder_bankmachine0_next_state <= 2'd2; end end else begin - litedramcore_bankmachine0_next_state <= 1'd1; + builder_bankmachine0_next_state <= 1'd1; end end else begin - litedramcore_bankmachine0_next_state <= 2'd3; + builder_bankmachine0_next_state <= 2'd3; end end end @@ -6375,15 +6966,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6394,27 +6992,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine0_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -6432,14 +7015,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin - litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin end else begin + main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6451,8 +7034,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -6470,14 +7053,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; end else begin - litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; end end else begin end @@ -6489,8 +7072,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -6498,9 +7081,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine0_twtpcon_ready) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -6511,20 +7091,32 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin + main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine0_row_open <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_open <= 1'd1; - end end 3'd4: begin end @@ -6537,25 +7129,37 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin + end else begin + main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine0_cmd_valid <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_refresh_gnt <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine0_twtpcon_ready) begin + main_litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -6566,34 +7170,22 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine0_row_close <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_row_open <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - litedramcore_bankmachine0_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_row_open <= 1'd1; + end end 3'd4: begin - litedramcore_bankmachine0_row_close <= 1'd1; end 3'd5: begin end @@ -6608,15 +7200,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; end end 3'd4: begin @@ -6630,19 +7225,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_row_close <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin + main_litedramcore_bankmachine0_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + main_litedramcore_bankmachine0_row_close <= 1'd1; end 3'd5: begin end @@ -6653,34 +7263,19 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -6698,12 +7293,9 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -6720,15 +7312,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end else begin - end + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -6739,22 +7328,21 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6769,9 +7357,12 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -6788,14 +7379,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; end else begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6806,139 +7397,139 @@ always @(*) begin end endcase end -assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid; -assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready; -assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we; -assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr; -assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid; -assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready; -assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first; -assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last; -assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we; -assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr; -assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); -assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid); -assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[21:7]); -assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1; +assign main_litedramcore_bankmachine1_sink_valid = main_litedramcore_bankmachine1_req_valid; +assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_sink_ready; +assign main_litedramcore_bankmachine1_sink_payload_we = main_litedramcore_bankmachine1_req_we; +assign main_litedramcore_bankmachine1_sink_payload_addr = main_litedramcore_bankmachine1_req_addr; +assign main_litedramcore_bankmachine1_sink_sink_valid = main_litedramcore_bankmachine1_source_valid; +assign main_litedramcore_bankmachine1_source_ready = main_litedramcore_bankmachine1_sink_sink_ready; +assign main_litedramcore_bankmachine1_sink_sink_first = main_litedramcore_bankmachine1_source_first; +assign main_litedramcore_bankmachine1_sink_sink_last = main_litedramcore_bankmachine1_source_last; +assign main_litedramcore_bankmachine1_sink_sink_payload_we = main_litedramcore_bankmachine1_source_payload_we; +assign main_litedramcore_bankmachine1_sink_sink_payload_addr = main_litedramcore_bankmachine1_source_payload_addr; +assign main_litedramcore_bankmachine1_source_source_ready = (main_litedramcore_bankmachine1_req_wdata_ready | main_litedramcore_bankmachine1_req_rdata_valid); +assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_source_valid | main_litedramcore_bankmachine1_source_source_valid); +assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_source_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; always @(*) begin - litedramcore_bankmachine1_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine1_row_col_n_addr_sel) begin - litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_source_source_payload_addr[21:7]; + main_litedramcore_bankmachine1_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin + main_litedramcore_bankmachine1_cmd_payload_a <= main_litedramcore_bankmachine1_source_source_payload_addr[21:7]; end else begin - litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write); -assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); -assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); -always @(*) begin - litedramcore_bankmachine1_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin - if ((litedramcore_bankmachine1_source_payload_addr[21:7] != litedramcore_bankmachine1_source_source_payload_addr[21:7])) begin - litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we}; -assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; -assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; -assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; -assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; -assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable; -assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid; -assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first; -assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last; -assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we; -assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr; -assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable; -assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first; -assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last; -assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we; -assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr; -assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready; -always @(*) begin - litedramcore_bankmachine1_wrport_adr <= 4'd0; - if (litedramcore_bankmachine1_replace) begin - litedramcore_bankmachine1_wrport_adr <= (litedramcore_bankmachine1_produce - 1'd1); + main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write); +assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); +assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); +always @(*) begin + main_litedramcore_bankmachine1_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine1_source_valid & main_litedramcore_bankmachine1_source_source_valid)) begin + if ((main_litedramcore_bankmachine1_source_payload_addr[21:7] != main_litedramcore_bankmachine1_source_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine1_syncfifo1_din = {main_litedramcore_bankmachine1_fifo_in_last, main_litedramcore_bankmachine1_fifo_in_first, main_litedramcore_bankmachine1_fifo_in_payload_addr, main_litedramcore_bankmachine1_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout; +assign main_litedramcore_bankmachine1_sink_ready = main_litedramcore_bankmachine1_syncfifo1_writable; +assign main_litedramcore_bankmachine1_syncfifo1_we = main_litedramcore_bankmachine1_sink_valid; +assign main_litedramcore_bankmachine1_fifo_in_first = main_litedramcore_bankmachine1_sink_first; +assign main_litedramcore_bankmachine1_fifo_in_last = main_litedramcore_bankmachine1_sink_last; +assign main_litedramcore_bankmachine1_fifo_in_payload_we = main_litedramcore_bankmachine1_sink_payload_we; +assign main_litedramcore_bankmachine1_fifo_in_payload_addr = main_litedramcore_bankmachine1_sink_payload_addr; +assign main_litedramcore_bankmachine1_source_valid = main_litedramcore_bankmachine1_syncfifo1_readable; +assign main_litedramcore_bankmachine1_source_first = main_litedramcore_bankmachine1_fifo_out_first; +assign main_litedramcore_bankmachine1_source_last = main_litedramcore_bankmachine1_fifo_out_last; +assign main_litedramcore_bankmachine1_source_payload_we = main_litedramcore_bankmachine1_fifo_out_payload_we; +assign main_litedramcore_bankmachine1_source_payload_addr = main_litedramcore_bankmachine1_fifo_out_payload_addr; +assign main_litedramcore_bankmachine1_syncfifo1_re = main_litedramcore_bankmachine1_source_ready; +always @(*) begin + main_litedramcore_bankmachine1_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine1_replace) begin + main_litedramcore_bankmachine1_wrport_adr <= (main_litedramcore_bankmachine1_produce - 1'd1); end else begin - litedramcore_bankmachine1_wrport_adr <= litedramcore_bankmachine1_produce; - end -end -assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din; -assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace)); -assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re); -assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume; -assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r; -assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 5'd16); -assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0); -assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready); -assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid; -assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready; -assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first; -assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last; -assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we; -assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr; -assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid; -assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready; -assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first; -assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last; -assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we; -assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine1_next_state <= 4'd0; - litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - if (litedramcore_bankmachine1_cmd_ready) begin - litedramcore_bankmachine1_next_state <= 3'd5; + main_litedramcore_bankmachine1_wrport_adr <= main_litedramcore_bankmachine1_produce; + end +end +assign main_litedramcore_bankmachine1_wrport_dat_w = main_litedramcore_bankmachine1_syncfifo1_din; +assign main_litedramcore_bankmachine1_wrport_we = (main_litedramcore_bankmachine1_syncfifo1_we & (main_litedramcore_bankmachine1_syncfifo1_writable | main_litedramcore_bankmachine1_replace)); +assign main_litedramcore_bankmachine1_do_read = (main_litedramcore_bankmachine1_syncfifo1_readable & main_litedramcore_bankmachine1_syncfifo1_re); +assign main_litedramcore_bankmachine1_rdport_adr = main_litedramcore_bankmachine1_consume; +assign main_litedramcore_bankmachine1_syncfifo1_dout = main_litedramcore_bankmachine1_rdport_dat_r; +assign main_litedramcore_bankmachine1_syncfifo1_writable = (main_litedramcore_bankmachine1_level != 5'd16); +assign main_litedramcore_bankmachine1_syncfifo1_readable = (main_litedramcore_bankmachine1_level != 1'd0); +assign main_litedramcore_bankmachine1_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine1_pipe_valid_source_valid) | main_litedramcore_bankmachine1_pipe_valid_source_ready); +assign main_litedramcore_bankmachine1_pipe_valid_sink_valid = main_litedramcore_bankmachine1_sink_sink_valid; +assign main_litedramcore_bankmachine1_sink_sink_ready = main_litedramcore_bankmachine1_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine1_pipe_valid_sink_first = main_litedramcore_bankmachine1_sink_sink_first; +assign main_litedramcore_bankmachine1_pipe_valid_sink_last = main_litedramcore_bankmachine1_sink_sink_last; +assign main_litedramcore_bankmachine1_pipe_valid_sink_payload_we = main_litedramcore_bankmachine1_sink_sink_payload_we; +assign main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine1_sink_sink_payload_addr; +assign main_litedramcore_bankmachine1_source_source_valid = main_litedramcore_bankmachine1_pipe_valid_source_valid; +assign main_litedramcore_bankmachine1_pipe_valid_source_ready = main_litedramcore_bankmachine1_source_source_ready; +assign main_litedramcore_bankmachine1_source_source_first = main_litedramcore_bankmachine1_pipe_valid_source_first; +assign main_litedramcore_bankmachine1_source_source_last = main_litedramcore_bankmachine1_pipe_valid_source_last; +assign main_litedramcore_bankmachine1_source_source_payload_we = main_litedramcore_bankmachine1_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine1_source_source_payload_addr = main_litedramcore_bankmachine1_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine1_next_state <= 4'd0; + builder_bankmachine1_next_state <= builder_bankmachine1_state; + case (builder_bankmachine1_state) + 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + if (main_litedramcore_bankmachine1_cmd_ready) begin + builder_bankmachine1_next_state <= 3'd5; end end end 2'd2: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_next_state <= 3'd5; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + builder_bankmachine1_next_state <= 3'd5; end end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - if (litedramcore_bankmachine1_cmd_ready) begin - litedramcore_bankmachine1_next_state <= 3'd7; + if (main_litedramcore_bankmachine1_trccon_ready) begin + if (main_litedramcore_bankmachine1_cmd_ready) begin + builder_bankmachine1_next_state <= 3'd7; end end end 3'd4: begin - if ((~litedramcore_bankmachine1_refresh_req)) begin - litedramcore_bankmachine1_next_state <= 1'd0; + if ((~main_litedramcore_bankmachine1_refresh_req)) begin + builder_bankmachine1_next_state <= 1'd0; end end 3'd5: begin - litedramcore_bankmachine1_next_state <= 3'd6; + builder_bankmachine1_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine1_next_state <= 2'd3; + builder_bankmachine1_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine1_next_state <= 4'd8; + builder_bankmachine1_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine1_next_state <= 1'd0; + builder_bankmachine1_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - litedramcore_bankmachine1_next_state <= 3'd4; + if (main_litedramcore_bankmachine1_refresh_req) begin + builder_bankmachine1_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin - litedramcore_bankmachine1_next_state <= 2'd2; + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if ((main_litedramcore_bankmachine1_cmd_ready & main_litedramcore_bankmachine1_auto_precharge)) begin + builder_bankmachine1_next_state <= 2'd2; end end else begin - litedramcore_bankmachine1_next_state <= 1'd1; + builder_bankmachine1_next_state <= 1'd1; end end else begin - litedramcore_bankmachine1_next_state <= 2'd3; + builder_bankmachine1_next_state <= 2'd3; end end end @@ -6946,18 +7537,56 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_row_open <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_open <= 1'd1; + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end end end + endcase +end +always @(*) begin + main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (builder_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end 3'd4: begin + if (main_litedramcore_bankmachine1_twtpcon_ready) begin + main_litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -6972,18 +7601,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_valid <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; end end 3'd4: begin @@ -6997,12 +7626,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; end else begin end end else begin @@ -7013,18 +7642,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_row_close <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_row_close <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - litedramcore_bankmachine1_row_close <= 1'd1; + main_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine1_row_close <= 1'd1; + main_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine1_row_close <= 1'd1; + main_litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -7039,18 +7668,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_row_open <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_row_open <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine1_twtpcon_ready) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7065,15 +7694,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -7091,8 +7720,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -7110,12 +7739,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -7126,18 +7755,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -7155,11 +7784,11 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -7177,13 +7806,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -7196,22 +7825,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7226,8 +7855,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -7245,14 +7874,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin end else begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; end end else begin end @@ -7264,8 +7893,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -7283,13 +7912,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin + main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -7302,8 +7931,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -7321,13 +7950,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin + main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready; end else begin end end else begin @@ -7339,193 +7968,181 @@ always @(*) begin end endcase end +assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid; +assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready; +assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we; +assign main_litedramcore_bankmachine2_sink_payload_addr = main_litedramcore_bankmachine2_req_addr; +assign main_litedramcore_bankmachine2_sink_sink_valid = main_litedramcore_bankmachine2_source_valid; +assign main_litedramcore_bankmachine2_source_ready = main_litedramcore_bankmachine2_sink_sink_ready; +assign main_litedramcore_bankmachine2_sink_sink_first = main_litedramcore_bankmachine2_source_first; +assign main_litedramcore_bankmachine2_sink_sink_last = main_litedramcore_bankmachine2_source_last; +assign main_litedramcore_bankmachine2_sink_sink_payload_we = main_litedramcore_bankmachine2_source_payload_we; +assign main_litedramcore_bankmachine2_sink_sink_payload_addr = main_litedramcore_bankmachine2_source_payload_addr; +assign main_litedramcore_bankmachine2_source_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid); +assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_source_valid | main_litedramcore_bankmachine2_source_source_valid); +assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_source_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; always @(*) begin - litedramcore_bankmachine1_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin + main_litedramcore_bankmachine2_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin + main_litedramcore_bankmachine2_cmd_payload_a <= main_litedramcore_bankmachine2_source_source_payload_addr[21:7]; + end else begin + main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write); +assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); +assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); +always @(*) begin + main_litedramcore_bankmachine2_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine2_source_valid & main_litedramcore_bankmachine2_source_source_valid)) begin + if ((main_litedramcore_bankmachine2_source_payload_addr[21:7] != main_litedramcore_bankmachine2_source_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine2_syncfifo2_din = {main_litedramcore_bankmachine2_fifo_in_last, main_litedramcore_bankmachine2_fifo_in_first, main_litedramcore_bankmachine2_fifo_in_payload_addr, main_litedramcore_bankmachine2_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; +assign main_litedramcore_bankmachine2_sink_ready = main_litedramcore_bankmachine2_syncfifo2_writable; +assign main_litedramcore_bankmachine2_syncfifo2_we = main_litedramcore_bankmachine2_sink_valid; +assign main_litedramcore_bankmachine2_fifo_in_first = main_litedramcore_bankmachine2_sink_first; +assign main_litedramcore_bankmachine2_fifo_in_last = main_litedramcore_bankmachine2_sink_last; +assign main_litedramcore_bankmachine2_fifo_in_payload_we = main_litedramcore_bankmachine2_sink_payload_we; +assign main_litedramcore_bankmachine2_fifo_in_payload_addr = main_litedramcore_bankmachine2_sink_payload_addr; +assign main_litedramcore_bankmachine2_source_valid = main_litedramcore_bankmachine2_syncfifo2_readable; +assign main_litedramcore_bankmachine2_source_first = main_litedramcore_bankmachine2_fifo_out_first; +assign main_litedramcore_bankmachine2_source_last = main_litedramcore_bankmachine2_fifo_out_last; +assign main_litedramcore_bankmachine2_source_payload_we = main_litedramcore_bankmachine2_fifo_out_payload_we; +assign main_litedramcore_bankmachine2_source_payload_addr = main_litedramcore_bankmachine2_fifo_out_payload_addr; +assign main_litedramcore_bankmachine2_syncfifo2_re = main_litedramcore_bankmachine2_source_ready; +always @(*) begin + main_litedramcore_bankmachine2_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine2_replace) begin + main_litedramcore_bankmachine2_wrport_adr <= (main_litedramcore_bankmachine2_produce - 1'd1); + end else begin + main_litedramcore_bankmachine2_wrport_adr <= main_litedramcore_bankmachine2_produce; + end +end +assign main_litedramcore_bankmachine2_wrport_dat_w = main_litedramcore_bankmachine2_syncfifo2_din; +assign main_litedramcore_bankmachine2_wrport_we = (main_litedramcore_bankmachine2_syncfifo2_we & (main_litedramcore_bankmachine2_syncfifo2_writable | main_litedramcore_bankmachine2_replace)); +assign main_litedramcore_bankmachine2_do_read = (main_litedramcore_bankmachine2_syncfifo2_readable & main_litedramcore_bankmachine2_syncfifo2_re); +assign main_litedramcore_bankmachine2_rdport_adr = main_litedramcore_bankmachine2_consume; +assign main_litedramcore_bankmachine2_syncfifo2_dout = main_litedramcore_bankmachine2_rdport_dat_r; +assign main_litedramcore_bankmachine2_syncfifo2_writable = (main_litedramcore_bankmachine2_level != 5'd16); +assign main_litedramcore_bankmachine2_syncfifo2_readable = (main_litedramcore_bankmachine2_level != 1'd0); +assign main_litedramcore_bankmachine2_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine2_pipe_valid_source_valid) | main_litedramcore_bankmachine2_pipe_valid_source_ready); +assign main_litedramcore_bankmachine2_pipe_valid_sink_valid = main_litedramcore_bankmachine2_sink_sink_valid; +assign main_litedramcore_bankmachine2_sink_sink_ready = main_litedramcore_bankmachine2_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine2_pipe_valid_sink_first = main_litedramcore_bankmachine2_sink_sink_first; +assign main_litedramcore_bankmachine2_pipe_valid_sink_last = main_litedramcore_bankmachine2_sink_sink_last; +assign main_litedramcore_bankmachine2_pipe_valid_sink_payload_we = main_litedramcore_bankmachine2_sink_sink_payload_we; +assign main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine2_sink_sink_payload_addr; +assign main_litedramcore_bankmachine2_source_source_valid = main_litedramcore_bankmachine2_pipe_valid_source_valid; +assign main_litedramcore_bankmachine2_pipe_valid_source_ready = main_litedramcore_bankmachine2_source_source_ready; +assign main_litedramcore_bankmachine2_source_source_first = main_litedramcore_bankmachine2_pipe_valid_source_first; +assign main_litedramcore_bankmachine2_source_source_last = main_litedramcore_bankmachine2_pipe_valid_source_last; +assign main_litedramcore_bankmachine2_source_source_payload_we = main_litedramcore_bankmachine2_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine2_source_source_payload_addr = main_litedramcore_bankmachine2_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine2_next_state <= 4'd0; + builder_bankmachine2_next_state <= builder_bankmachine2_state; + case (builder_bankmachine2_state) + 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + if (main_litedramcore_bankmachine2_cmd_ready) begin + builder_bankmachine2_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + builder_bankmachine2_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + if (main_litedramcore_bankmachine2_cmd_ready) begin + builder_bankmachine2_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine2_refresh_req)) begin + builder_bankmachine2_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine2_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine2_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine2_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine2_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin + builder_bankmachine2_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - end else begin - litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if ((main_litedramcore_bankmachine2_cmd_ready & main_litedramcore_bankmachine2_auto_precharge)) begin + builder_bankmachine2_next_state <= 2'd2; end end else begin + builder_bankmachine2_next_state <= 1'd1; end end else begin + builder_bankmachine2_next_state <= 2'd3; end end end end endcase end -assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid; -assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready; -assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we; -assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr; -assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid; -assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready; -assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first; -assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last; -assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we; -assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr; -assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); -assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid); -assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[21:7]); -assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2; always @(*) begin - litedramcore_bankmachine2_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine2_row_col_n_addr_sel) begin - litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_source_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write); -assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); -assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); -always @(*) begin - litedramcore_bankmachine2_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin - if ((litedramcore_bankmachine2_source_payload_addr[21:7] != litedramcore_bankmachine2_source_source_payload_addr[21:7])) begin - litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we}; -assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; -assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; -assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; -assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; -assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable; -assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid; -assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first; -assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last; -assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we; -assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr; -assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable; -assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first; -assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last; -assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we; -assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr; -assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready; -always @(*) begin - litedramcore_bankmachine2_wrport_adr <= 4'd0; - if (litedramcore_bankmachine2_replace) begin - litedramcore_bankmachine2_wrport_adr <= (litedramcore_bankmachine2_produce - 1'd1); - end else begin - litedramcore_bankmachine2_wrport_adr <= litedramcore_bankmachine2_produce; - end -end -assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din; -assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace)); -assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re); -assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume; -assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r; -assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 5'd16); -assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0); -assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready); -assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid; -assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready; -assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first; -assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last; -assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we; -assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr; -assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid; -assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready; -assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first; -assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last; -assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we; -assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine2_next_state <= 4'd0; - litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - if (litedramcore_bankmachine2_cmd_ready) begin - litedramcore_bankmachine2_next_state <= 3'd5; - end - end + main_litedramcore_bankmachine2_row_close <= 1'd0; + case (builder_bankmachine2_state) + 1'd1: begin + main_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_next_state <= 3'd5; - end + main_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - if (litedramcore_bankmachine2_cmd_ready) begin - litedramcore_bankmachine2_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~litedramcore_bankmachine2_refresh_req)) begin - litedramcore_bankmachine2_next_state <= 1'd0; - end + main_litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin - litedramcore_bankmachine2_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine2_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine2_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine2_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - litedramcore_bankmachine2_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin - litedramcore_bankmachine2_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine2_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine2_next_state <= 2'd3; - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -7543,8 +8160,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -7562,12 +8179,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -7578,18 +8195,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -7607,11 +8224,11 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -7629,13 +8246,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -7648,22 +8265,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7678,8 +8295,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -7697,14 +8314,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin end else begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; end end else begin end @@ -7716,8 +8333,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -7735,13 +8352,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin + main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -7754,8 +8371,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -7773,13 +8390,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin - litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin + main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready; end else begin end end else begin @@ -7792,8 +8409,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -7811,14 +8428,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin end else begin - litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; + main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready; end end else begin end @@ -7830,8 +8447,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -7839,8 +8456,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine2_twtpcon_ready) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd1; + if (main_litedramcore_bankmachine2_twtpcon_ready) begin + main_litedramcore_bankmachine2_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -7856,15 +8473,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_row_open <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_row_open <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_row_open <= 1'd1; end end 3'd4: begin @@ -7882,18 +8499,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_valid <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_valid <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; end end 3'd4: begin @@ -7907,12 +8524,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; end else begin end end else begin @@ -7922,165 +8539,174 @@ always @(*) begin end endcase end +assign main_litedramcore_bankmachine3_sink_valid = main_litedramcore_bankmachine3_req_valid; +assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_sink_ready; +assign main_litedramcore_bankmachine3_sink_payload_we = main_litedramcore_bankmachine3_req_we; +assign main_litedramcore_bankmachine3_sink_payload_addr = main_litedramcore_bankmachine3_req_addr; +assign main_litedramcore_bankmachine3_sink_sink_valid = main_litedramcore_bankmachine3_source_valid; +assign main_litedramcore_bankmachine3_source_ready = main_litedramcore_bankmachine3_sink_sink_ready; +assign main_litedramcore_bankmachine3_sink_sink_first = main_litedramcore_bankmachine3_source_first; +assign main_litedramcore_bankmachine3_sink_sink_last = main_litedramcore_bankmachine3_source_last; +assign main_litedramcore_bankmachine3_sink_sink_payload_we = main_litedramcore_bankmachine3_source_payload_we; +assign main_litedramcore_bankmachine3_sink_sink_payload_addr = main_litedramcore_bankmachine3_source_payload_addr; +assign main_litedramcore_bankmachine3_source_source_ready = (main_litedramcore_bankmachine3_req_wdata_ready | main_litedramcore_bankmachine3_req_rdata_valid); +assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_source_valid | main_litedramcore_bankmachine3_source_source_valid); +assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_source_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; always @(*) begin - litedramcore_bankmachine2_row_close <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - litedramcore_bankmachine2_row_close <= 1'd1; + main_litedramcore_bankmachine3_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin + main_litedramcore_bankmachine3_cmd_payload_a <= main_litedramcore_bankmachine3_source_source_payload_addr[21:7]; + end else begin + main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write); +assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); +assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); +always @(*) begin + main_litedramcore_bankmachine3_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine3_source_valid & main_litedramcore_bankmachine3_source_source_valid)) begin + if ((main_litedramcore_bankmachine3_source_payload_addr[21:7] != main_litedramcore_bankmachine3_source_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine3_syncfifo3_din = {main_litedramcore_bankmachine3_fifo_in_last, main_litedramcore_bankmachine3_fifo_in_first, main_litedramcore_bankmachine3_fifo_in_payload_addr, main_litedramcore_bankmachine3_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout; +assign main_litedramcore_bankmachine3_sink_ready = main_litedramcore_bankmachine3_syncfifo3_writable; +assign main_litedramcore_bankmachine3_syncfifo3_we = main_litedramcore_bankmachine3_sink_valid; +assign main_litedramcore_bankmachine3_fifo_in_first = main_litedramcore_bankmachine3_sink_first; +assign main_litedramcore_bankmachine3_fifo_in_last = main_litedramcore_bankmachine3_sink_last; +assign main_litedramcore_bankmachine3_fifo_in_payload_we = main_litedramcore_bankmachine3_sink_payload_we; +assign main_litedramcore_bankmachine3_fifo_in_payload_addr = main_litedramcore_bankmachine3_sink_payload_addr; +assign main_litedramcore_bankmachine3_source_valid = main_litedramcore_bankmachine3_syncfifo3_readable; +assign main_litedramcore_bankmachine3_source_first = main_litedramcore_bankmachine3_fifo_out_first; +assign main_litedramcore_bankmachine3_source_last = main_litedramcore_bankmachine3_fifo_out_last; +assign main_litedramcore_bankmachine3_source_payload_we = main_litedramcore_bankmachine3_fifo_out_payload_we; +assign main_litedramcore_bankmachine3_source_payload_addr = main_litedramcore_bankmachine3_fifo_out_payload_addr; +assign main_litedramcore_bankmachine3_syncfifo3_re = main_litedramcore_bankmachine3_source_ready; +always @(*) begin + main_litedramcore_bankmachine3_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine3_replace) begin + main_litedramcore_bankmachine3_wrport_adr <= (main_litedramcore_bankmachine3_produce - 1'd1); + end else begin + main_litedramcore_bankmachine3_wrport_adr <= main_litedramcore_bankmachine3_produce; + end +end +assign main_litedramcore_bankmachine3_wrport_dat_w = main_litedramcore_bankmachine3_syncfifo3_din; +assign main_litedramcore_bankmachine3_wrport_we = (main_litedramcore_bankmachine3_syncfifo3_we & (main_litedramcore_bankmachine3_syncfifo3_writable | main_litedramcore_bankmachine3_replace)); +assign main_litedramcore_bankmachine3_do_read = (main_litedramcore_bankmachine3_syncfifo3_readable & main_litedramcore_bankmachine3_syncfifo3_re); +assign main_litedramcore_bankmachine3_rdport_adr = main_litedramcore_bankmachine3_consume; +assign main_litedramcore_bankmachine3_syncfifo3_dout = main_litedramcore_bankmachine3_rdport_dat_r; +assign main_litedramcore_bankmachine3_syncfifo3_writable = (main_litedramcore_bankmachine3_level != 5'd16); +assign main_litedramcore_bankmachine3_syncfifo3_readable = (main_litedramcore_bankmachine3_level != 1'd0); +assign main_litedramcore_bankmachine3_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine3_pipe_valid_source_valid) | main_litedramcore_bankmachine3_pipe_valid_source_ready); +assign main_litedramcore_bankmachine3_pipe_valid_sink_valid = main_litedramcore_bankmachine3_sink_sink_valid; +assign main_litedramcore_bankmachine3_sink_sink_ready = main_litedramcore_bankmachine3_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine3_pipe_valid_sink_first = main_litedramcore_bankmachine3_sink_sink_first; +assign main_litedramcore_bankmachine3_pipe_valid_sink_last = main_litedramcore_bankmachine3_sink_sink_last; +assign main_litedramcore_bankmachine3_pipe_valid_sink_payload_we = main_litedramcore_bankmachine3_sink_sink_payload_we; +assign main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine3_sink_sink_payload_addr; +assign main_litedramcore_bankmachine3_source_source_valid = main_litedramcore_bankmachine3_pipe_valid_source_valid; +assign main_litedramcore_bankmachine3_pipe_valid_source_ready = main_litedramcore_bankmachine3_source_source_ready; +assign main_litedramcore_bankmachine3_source_source_first = main_litedramcore_bankmachine3_pipe_valid_source_first; +assign main_litedramcore_bankmachine3_source_source_last = main_litedramcore_bankmachine3_pipe_valid_source_last; +assign main_litedramcore_bankmachine3_source_source_payload_we = main_litedramcore_bankmachine3_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine3_source_source_payload_addr = main_litedramcore_bankmachine3_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine3_next_state <= 4'd0; + builder_bankmachine3_next_state <= builder_bankmachine3_state; + case (builder_bankmachine3_state) + 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + if (main_litedramcore_bankmachine3_cmd_ready) begin + builder_bankmachine3_next_state <= 3'd5; + end + end end 2'd2: begin - litedramcore_bankmachine2_row_close <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + builder_bankmachine3_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + if (main_litedramcore_bankmachine3_cmd_ready) begin + builder_bankmachine3_next_state <= 3'd7; + end + end end 3'd4: begin - litedramcore_bankmachine2_row_close <= 1'd1; + if ((~main_litedramcore_bankmachine3_refresh_req)) begin + builder_bankmachine3_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine3_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine3_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine3_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine3_next_state <= 1'd0; end default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + builder_bankmachine3_next_state <= 3'd4; + end else begin + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin + builder_bankmachine3_next_state <= 2'd2; + end + end else begin + builder_bankmachine3_next_state <= 1'd1; + end + end else begin + builder_bankmachine3_next_state <= 2'd3; + end + end + end end endcase end -assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid; -assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready; -assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we; -assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr; -assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid; -assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready; -assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first; -assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last; -assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we; -assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr; -assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); -assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid); -assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[21:7]); -assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3; -always @(*) begin - litedramcore_bankmachine3_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine3_row_col_n_addr_sel) begin - litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_source_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write); -assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); -assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); -always @(*) begin - litedramcore_bankmachine3_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin - if ((litedramcore_bankmachine3_source_payload_addr[21:7] != litedramcore_bankmachine3_source_source_payload_addr[21:7])) begin - litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we}; -assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; -assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; -assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; -assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; -assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable; -assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid; -assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first; -assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last; -assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we; -assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr; -assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable; -assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first; -assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last; -assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we; -assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr; -assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready; -always @(*) begin - litedramcore_bankmachine3_wrport_adr <= 4'd0; - if (litedramcore_bankmachine3_replace) begin - litedramcore_bankmachine3_wrport_adr <= (litedramcore_bankmachine3_produce - 1'd1); - end else begin - litedramcore_bankmachine3_wrport_adr <= litedramcore_bankmachine3_produce; - end -end -assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din; -assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace)); -assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re); -assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume; -assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r; -assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 5'd16); -assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0); -assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready); -assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid; -assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready; -assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first; -assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last; -assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we; -assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr; -assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid; -assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready; -assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first; -assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last; -assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we; -assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine3_next_state <= 4'd0; - litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - if (litedramcore_bankmachine3_cmd_ready) begin - litedramcore_bankmachine3_next_state <= 3'd5; - end - end +always @(*) begin + main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (builder_bankmachine3_state) + 1'd1: begin end 2'd2: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - if (litedramcore_bankmachine3_cmd_ready) begin - litedramcore_bankmachine3_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~litedramcore_bankmachine3_refresh_req)) begin - litedramcore_bankmachine3_next_state <= 1'd0; - end end 3'd5: begin - litedramcore_bankmachine3_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine3_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine3_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine3_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - litedramcore_bankmachine3_next_state <= 3'd4; + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin - litedramcore_bankmachine3_next_state <= 2'd2; - end + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; end else begin - litedramcore_bankmachine3_next_state <= 1'd1; end end else begin - litedramcore_bankmachine3_next_state <= 2'd3; end end end @@ -8088,18 +8714,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -8117,11 +8743,11 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -8139,13 +8765,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -8158,22 +8784,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8188,8 +8814,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -8207,14 +8833,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin end else begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; end end else begin end @@ -8226,8 +8852,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -8245,13 +8871,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin + main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -8264,8 +8890,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -8283,13 +8909,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin - litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin + main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready; end else begin end end else begin @@ -8302,8 +8928,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -8321,14 +8947,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin end else begin - litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; + main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready; end end else begin end @@ -8340,8 +8966,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -8349,8 +8975,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine3_twtpcon_ready) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd1; + if (main_litedramcore_bankmachine3_twtpcon_ready) begin + main_litedramcore_bankmachine3_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -8366,15 +8992,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_row_open <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_row_open <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_open <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_open <= 1'd1; end end 3'd4: begin @@ -8392,18 +9018,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_valid <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; end end 3'd4: begin @@ -8417,12 +9043,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; end else begin end end else begin @@ -8433,18 +9059,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_row_close <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_row_close <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - litedramcore_bankmachine3_row_close <= 1'd1; + main_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine3_row_close <= 1'd1; + main_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine3_row_close <= 1'd1; + main_litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -8459,15 +9085,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -8484,174 +9110,207 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin +assign main_litedramcore_bankmachine4_sink_valid = main_litedramcore_bankmachine4_req_valid; +assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_sink_ready; +assign main_litedramcore_bankmachine4_sink_payload_we = main_litedramcore_bankmachine4_req_we; +assign main_litedramcore_bankmachine4_sink_payload_addr = main_litedramcore_bankmachine4_req_addr; +assign main_litedramcore_bankmachine4_sink_sink_valid = main_litedramcore_bankmachine4_source_valid; +assign main_litedramcore_bankmachine4_source_ready = main_litedramcore_bankmachine4_sink_sink_ready; +assign main_litedramcore_bankmachine4_sink_sink_first = main_litedramcore_bankmachine4_source_first; +assign main_litedramcore_bankmachine4_sink_sink_last = main_litedramcore_bankmachine4_source_last; +assign main_litedramcore_bankmachine4_sink_sink_payload_we = main_litedramcore_bankmachine4_source_payload_we; +assign main_litedramcore_bankmachine4_sink_sink_payload_addr = main_litedramcore_bankmachine4_source_payload_addr; +assign main_litedramcore_bankmachine4_source_source_ready = (main_litedramcore_bankmachine4_req_wdata_ready | main_litedramcore_bankmachine4_req_rdata_valid); +assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_source_valid | main_litedramcore_bankmachine4_source_source_valid); +assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_source_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; +always @(*) begin + main_litedramcore_bankmachine4_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin + main_litedramcore_bankmachine4_cmd_payload_a <= main_litedramcore_bankmachine4_source_source_payload_addr[21:7]; + end else begin + main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write); +assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); +assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); +always @(*) begin + main_litedramcore_bankmachine4_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine4_source_valid & main_litedramcore_bankmachine4_source_source_valid)) begin + if ((main_litedramcore_bankmachine4_source_payload_addr[21:7] != main_litedramcore_bankmachine4_source_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine4_syncfifo4_din = {main_litedramcore_bankmachine4_fifo_in_last, main_litedramcore_bankmachine4_fifo_in_first, main_litedramcore_bankmachine4_fifo_in_payload_addr, main_litedramcore_bankmachine4_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout; +assign main_litedramcore_bankmachine4_sink_ready = main_litedramcore_bankmachine4_syncfifo4_writable; +assign main_litedramcore_bankmachine4_syncfifo4_we = main_litedramcore_bankmachine4_sink_valid; +assign main_litedramcore_bankmachine4_fifo_in_first = main_litedramcore_bankmachine4_sink_first; +assign main_litedramcore_bankmachine4_fifo_in_last = main_litedramcore_bankmachine4_sink_last; +assign main_litedramcore_bankmachine4_fifo_in_payload_we = main_litedramcore_bankmachine4_sink_payload_we; +assign main_litedramcore_bankmachine4_fifo_in_payload_addr = main_litedramcore_bankmachine4_sink_payload_addr; +assign main_litedramcore_bankmachine4_source_valid = main_litedramcore_bankmachine4_syncfifo4_readable; +assign main_litedramcore_bankmachine4_source_first = main_litedramcore_bankmachine4_fifo_out_first; +assign main_litedramcore_bankmachine4_source_last = main_litedramcore_bankmachine4_fifo_out_last; +assign main_litedramcore_bankmachine4_source_payload_we = main_litedramcore_bankmachine4_fifo_out_payload_we; +assign main_litedramcore_bankmachine4_source_payload_addr = main_litedramcore_bankmachine4_fifo_out_payload_addr; +assign main_litedramcore_bankmachine4_syncfifo4_re = main_litedramcore_bankmachine4_source_ready; +always @(*) begin + main_litedramcore_bankmachine4_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine4_replace) begin + main_litedramcore_bankmachine4_wrport_adr <= (main_litedramcore_bankmachine4_produce - 1'd1); + end else begin + main_litedramcore_bankmachine4_wrport_adr <= main_litedramcore_bankmachine4_produce; + end +end +assign main_litedramcore_bankmachine4_wrport_dat_w = main_litedramcore_bankmachine4_syncfifo4_din; +assign main_litedramcore_bankmachine4_wrport_we = (main_litedramcore_bankmachine4_syncfifo4_we & (main_litedramcore_bankmachine4_syncfifo4_writable | main_litedramcore_bankmachine4_replace)); +assign main_litedramcore_bankmachine4_do_read = (main_litedramcore_bankmachine4_syncfifo4_readable & main_litedramcore_bankmachine4_syncfifo4_re); +assign main_litedramcore_bankmachine4_rdport_adr = main_litedramcore_bankmachine4_consume; +assign main_litedramcore_bankmachine4_syncfifo4_dout = main_litedramcore_bankmachine4_rdport_dat_r; +assign main_litedramcore_bankmachine4_syncfifo4_writable = (main_litedramcore_bankmachine4_level != 5'd16); +assign main_litedramcore_bankmachine4_syncfifo4_readable = (main_litedramcore_bankmachine4_level != 1'd0); +assign main_litedramcore_bankmachine4_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine4_pipe_valid_source_valid) | main_litedramcore_bankmachine4_pipe_valid_source_ready); +assign main_litedramcore_bankmachine4_pipe_valid_sink_valid = main_litedramcore_bankmachine4_sink_sink_valid; +assign main_litedramcore_bankmachine4_sink_sink_ready = main_litedramcore_bankmachine4_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine4_pipe_valid_sink_first = main_litedramcore_bankmachine4_sink_sink_first; +assign main_litedramcore_bankmachine4_pipe_valid_sink_last = main_litedramcore_bankmachine4_sink_sink_last; +assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_we = main_litedramcore_bankmachine4_sink_sink_payload_we; +assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine4_sink_sink_payload_addr; +assign main_litedramcore_bankmachine4_source_source_valid = main_litedramcore_bankmachine4_pipe_valid_source_valid; +assign main_litedramcore_bankmachine4_pipe_valid_source_ready = main_litedramcore_bankmachine4_source_source_ready; +assign main_litedramcore_bankmachine4_source_source_first = main_litedramcore_bankmachine4_pipe_valid_source_first; +assign main_litedramcore_bankmachine4_source_source_last = main_litedramcore_bankmachine4_pipe_valid_source_last; +assign main_litedramcore_bankmachine4_source_source_payload_we = main_litedramcore_bankmachine4_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine4_source_source_payload_addr = main_litedramcore_bankmachine4_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine4_next_state <= 4'd0; + builder_bankmachine4_next_state <= builder_bankmachine4_state; + case (builder_bankmachine4_state) + 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + if (main_litedramcore_bankmachine4_cmd_ready) begin + builder_bankmachine4_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + builder_bankmachine4_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + if (main_litedramcore_bankmachine4_cmd_ready) begin + builder_bankmachine4_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine4_refresh_req)) begin + builder_bankmachine4_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine4_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine4_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine4_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine4_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin + builder_bankmachine4_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if ((main_litedramcore_bankmachine4_cmd_ready & main_litedramcore_bankmachine4_auto_precharge)) begin + builder_bankmachine4_next_state <= 2'd2; + end end else begin + builder_bankmachine4_next_state <= 1'd1; end end else begin + builder_bankmachine4_next_state <= 2'd3; end end end end endcase end -assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid; -assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready; -assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we; -assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr; -assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid; -assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready; -assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first; -assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last; -assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we; -assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr; -assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); -assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid); -assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[21:7]); -assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4; always @(*) begin - litedramcore_bankmachine4_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine4_row_col_n_addr_sel) begin - litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_source_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write); -assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); -assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); -always @(*) begin - litedramcore_bankmachine4_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin - if ((litedramcore_bankmachine4_source_payload_addr[21:7] != litedramcore_bankmachine4_source_source_payload_addr[21:7])) begin - litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we}; -assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; -assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; -assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; -assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; -assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable; -assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid; -assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first; -assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last; -assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we; -assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr; -assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable; -assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first; -assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last; -assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we; -assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr; -assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready; -always @(*) begin - litedramcore_bankmachine4_wrport_adr <= 4'd0; - if (litedramcore_bankmachine4_replace) begin - litedramcore_bankmachine4_wrport_adr <= (litedramcore_bankmachine4_produce - 1'd1); - end else begin - litedramcore_bankmachine4_wrport_adr <= litedramcore_bankmachine4_produce; - end -end -assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din; -assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace)); -assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re); -assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume; -assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r; -assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 5'd16); -assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0); -assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready); -assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid; -assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready; -assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first; -assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last; -assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we; -assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr; -assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid; -assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready; -assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first; -assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last; -assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we; -assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine4_next_state <= 4'd0; - litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - if (litedramcore_bankmachine4_cmd_ready) begin - litedramcore_bankmachine4_next_state <= 3'd5; - end + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine4_state) + 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - if (litedramcore_bankmachine4_cmd_ready) begin - litedramcore_bankmachine4_next_state <= 3'd7; - end + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - if ((~litedramcore_bankmachine4_refresh_req)) begin - litedramcore_bankmachine4_next_state <= 1'd0; - end + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin end 3'd5: begin - litedramcore_bankmachine4_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine4_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine4_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine4_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - litedramcore_bankmachine4_next_state <= 3'd4; + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin - litedramcore_bankmachine4_next_state <= 2'd2; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin + end else begin + main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; end end else begin - litedramcore_bankmachine4_next_state <= 1'd1; end end else begin - litedramcore_bankmachine4_next_state <= 2'd3; end end end @@ -8659,8 +9318,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -8678,13 +9337,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin + main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -8697,8 +9356,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -8716,13 +9375,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin - litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin + main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready; end else begin end end else begin @@ -8735,8 +9394,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -8754,14 +9413,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin end else begin - litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; + main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready; end end else begin end @@ -8773,8 +9432,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -8782,8 +9441,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine4_twtpcon_ready) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd1; + if (main_litedramcore_bankmachine4_twtpcon_ready) begin + main_litedramcore_bankmachine4_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -8799,15 +9458,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_row_open <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_row_open <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_open <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_row_open <= 1'd1; end end 3'd4: begin @@ -8825,18 +9484,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_valid <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_valid <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; end end 3'd4: begin @@ -8850,12 +9509,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; end else begin end end else begin @@ -8866,18 +9525,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_row_close <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_row_close <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - litedramcore_bankmachine4_row_close <= 1'd1; + main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine4_row_close <= 1'd1; + main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine4_row_close <= 1'd1; + main_litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -8892,15 +9551,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -8918,8 +9577,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -8937,12 +9596,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -8953,18 +9612,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -8982,11 +9641,11 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -9004,13 +9663,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -9022,207 +9681,177 @@ always @(*) begin end endcase end +assign main_litedramcore_bankmachine5_sink_valid = main_litedramcore_bankmachine5_req_valid; +assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_sink_ready; +assign main_litedramcore_bankmachine5_sink_payload_we = main_litedramcore_bankmachine5_req_we; +assign main_litedramcore_bankmachine5_sink_payload_addr = main_litedramcore_bankmachine5_req_addr; +assign main_litedramcore_bankmachine5_sink_sink_valid = main_litedramcore_bankmachine5_source_valid; +assign main_litedramcore_bankmachine5_source_ready = main_litedramcore_bankmachine5_sink_sink_ready; +assign main_litedramcore_bankmachine5_sink_sink_first = main_litedramcore_bankmachine5_source_first; +assign main_litedramcore_bankmachine5_sink_sink_last = main_litedramcore_bankmachine5_source_last; +assign main_litedramcore_bankmachine5_sink_sink_payload_we = main_litedramcore_bankmachine5_source_payload_we; +assign main_litedramcore_bankmachine5_sink_sink_payload_addr = main_litedramcore_bankmachine5_source_payload_addr; +assign main_litedramcore_bankmachine5_source_source_ready = (main_litedramcore_bankmachine5_req_wdata_ready | main_litedramcore_bankmachine5_req_rdata_valid); +assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_source_valid | main_litedramcore_bankmachine5_source_source_valid); +assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_source_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5; always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine5_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin + main_litedramcore_bankmachine5_cmd_payload_a <= main_litedramcore_bankmachine5_source_source_payload_addr[21:7]; + end else begin + main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write); +assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); +assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); +always @(*) begin + main_litedramcore_bankmachine5_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine5_source_valid & main_litedramcore_bankmachine5_source_source_valid)) begin + if ((main_litedramcore_bankmachine5_source_payload_addr[21:7] != main_litedramcore_bankmachine5_source_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine5_syncfifo5_din = {main_litedramcore_bankmachine5_fifo_in_last, main_litedramcore_bankmachine5_fifo_in_first, main_litedramcore_bankmachine5_fifo_in_payload_addr, main_litedramcore_bankmachine5_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout; +assign main_litedramcore_bankmachine5_sink_ready = main_litedramcore_bankmachine5_syncfifo5_writable; +assign main_litedramcore_bankmachine5_syncfifo5_we = main_litedramcore_bankmachine5_sink_valid; +assign main_litedramcore_bankmachine5_fifo_in_first = main_litedramcore_bankmachine5_sink_first; +assign main_litedramcore_bankmachine5_fifo_in_last = main_litedramcore_bankmachine5_sink_last; +assign main_litedramcore_bankmachine5_fifo_in_payload_we = main_litedramcore_bankmachine5_sink_payload_we; +assign main_litedramcore_bankmachine5_fifo_in_payload_addr = main_litedramcore_bankmachine5_sink_payload_addr; +assign main_litedramcore_bankmachine5_source_valid = main_litedramcore_bankmachine5_syncfifo5_readable; +assign main_litedramcore_bankmachine5_source_first = main_litedramcore_bankmachine5_fifo_out_first; +assign main_litedramcore_bankmachine5_source_last = main_litedramcore_bankmachine5_fifo_out_last; +assign main_litedramcore_bankmachine5_source_payload_we = main_litedramcore_bankmachine5_fifo_out_payload_we; +assign main_litedramcore_bankmachine5_source_payload_addr = main_litedramcore_bankmachine5_fifo_out_payload_addr; +assign main_litedramcore_bankmachine5_syncfifo5_re = main_litedramcore_bankmachine5_source_ready; +always @(*) begin + main_litedramcore_bankmachine5_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine5_replace) begin + main_litedramcore_bankmachine5_wrport_adr <= (main_litedramcore_bankmachine5_produce - 1'd1); + end else begin + main_litedramcore_bankmachine5_wrport_adr <= main_litedramcore_bankmachine5_produce; + end +end +assign main_litedramcore_bankmachine5_wrport_dat_w = main_litedramcore_bankmachine5_syncfifo5_din; +assign main_litedramcore_bankmachine5_wrport_we = (main_litedramcore_bankmachine5_syncfifo5_we & (main_litedramcore_bankmachine5_syncfifo5_writable | main_litedramcore_bankmachine5_replace)); +assign main_litedramcore_bankmachine5_do_read = (main_litedramcore_bankmachine5_syncfifo5_readable & main_litedramcore_bankmachine5_syncfifo5_re); +assign main_litedramcore_bankmachine5_rdport_adr = main_litedramcore_bankmachine5_consume; +assign main_litedramcore_bankmachine5_syncfifo5_dout = main_litedramcore_bankmachine5_rdport_dat_r; +assign main_litedramcore_bankmachine5_syncfifo5_writable = (main_litedramcore_bankmachine5_level != 5'd16); +assign main_litedramcore_bankmachine5_syncfifo5_readable = (main_litedramcore_bankmachine5_level != 1'd0); +assign main_litedramcore_bankmachine5_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine5_pipe_valid_source_valid) | main_litedramcore_bankmachine5_pipe_valid_source_ready); +assign main_litedramcore_bankmachine5_pipe_valid_sink_valid = main_litedramcore_bankmachine5_sink_sink_valid; +assign main_litedramcore_bankmachine5_sink_sink_ready = main_litedramcore_bankmachine5_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine5_pipe_valid_sink_first = main_litedramcore_bankmachine5_sink_sink_first; +assign main_litedramcore_bankmachine5_pipe_valid_sink_last = main_litedramcore_bankmachine5_sink_sink_last; +assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_we = main_litedramcore_bankmachine5_sink_sink_payload_we; +assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine5_sink_sink_payload_addr; +assign main_litedramcore_bankmachine5_source_source_valid = main_litedramcore_bankmachine5_pipe_valid_source_valid; +assign main_litedramcore_bankmachine5_pipe_valid_source_ready = main_litedramcore_bankmachine5_source_source_ready; +assign main_litedramcore_bankmachine5_source_source_first = main_litedramcore_bankmachine5_pipe_valid_source_first; +assign main_litedramcore_bankmachine5_source_source_last = main_litedramcore_bankmachine5_pipe_valid_source_last; +assign main_litedramcore_bankmachine5_source_source_payload_we = main_litedramcore_bankmachine5_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine5_source_source_payload_addr = main_litedramcore_bankmachine5_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine5_next_state <= 4'd0; + builder_bankmachine5_next_state <= builder_bankmachine5_state; + case (builder_bankmachine5_state) + 1'd1: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + if (main_litedramcore_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd5; + end end end 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + builder_bankmachine5_next_state <= 3'd5; end end - 3'd4: begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + if (main_litedramcore_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine5_refresh_req)) begin + builder_bankmachine5_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine5_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine5_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine5_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine5_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin + builder_bankmachine5_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin - end else begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin + builder_bankmachine5_next_state <= 2'd2; end end else begin + builder_bankmachine5_next_state <= 1'd1; end end else begin + builder_bankmachine5_next_state <= 2'd3; end end end end endcase end -assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid; -assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready; -assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we; -assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr; -assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid; -assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready; -assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first; -assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last; -assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we; -assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr; -assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); -assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid); -assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[21:7]); -assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5; always @(*) begin - litedramcore_bankmachine5_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine5_row_col_n_addr_sel) begin - litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_source_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write); -assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); -assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); -always @(*) begin - litedramcore_bankmachine5_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin - if ((litedramcore_bankmachine5_source_payload_addr[21:7] != litedramcore_bankmachine5_source_source_payload_addr[21:7])) begin - litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we}; -assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; -assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; -assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; -assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; -assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable; -assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid; -assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first; -assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last; -assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we; -assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr; -assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable; -assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first; -assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last; -assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we; -assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr; -assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready; -always @(*) begin - litedramcore_bankmachine5_wrport_adr <= 4'd0; - if (litedramcore_bankmachine5_replace) begin - litedramcore_bankmachine5_wrport_adr <= (litedramcore_bankmachine5_produce - 1'd1); - end else begin - litedramcore_bankmachine5_wrport_adr <= litedramcore_bankmachine5_produce; - end -end -assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din; -assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace)); -assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re); -assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume; -assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r; -assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 5'd16); -assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0); -assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready); -assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid; -assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready; -assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first; -assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last; -assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we; -assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr; -assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid; -assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready; -assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first; -assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last; -assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we; -assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine5_next_state <= 4'd0; - litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - if (litedramcore_bankmachine5_cmd_ready) begin - litedramcore_bankmachine5_next_state <= 3'd5; - end - end + main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin end 2'd2: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - if (litedramcore_bankmachine5_cmd_ready) begin - litedramcore_bankmachine5_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~litedramcore_bankmachine5_refresh_req)) begin - litedramcore_bankmachine5_next_state <= 1'd0; - end end 3'd5: begin - litedramcore_bankmachine5_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine5_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine5_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine5_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - litedramcore_bankmachine5_next_state <= 3'd4; + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin - litedramcore_bankmachine5_next_state <= 2'd2; + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin + end else begin + main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready; end end else begin - litedramcore_bankmachine5_next_state <= 1'd1; end end else begin - litedramcore_bankmachine5_next_state <= 2'd3; end end end @@ -9230,18 +9859,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_row_open <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_open <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine5_twtpcon_ready) begin + main_litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9256,18 +9885,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_valid <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; end end 3'd4: begin @@ -9281,12 +9910,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; end else begin end end else begin @@ -9297,18 +9926,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_row_close <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_row_close <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - litedramcore_bankmachine5_row_close <= 1'd1; + main_litedramcore_bankmachine5_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine5_row_close <= 1'd1; + main_litedramcore_bankmachine5_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine5_row_close <= 1'd1; + main_litedramcore_bankmachine5_row_close <= 1'd1; end 3'd5: begin end @@ -9323,18 +9952,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_row_open <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_row_open <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine5_twtpcon_ready) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -9349,15 +9978,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -9375,8 +10004,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -9394,12 +10023,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -9410,18 +10039,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -9439,11 +10068,11 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -9461,13 +10090,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -9480,22 +10109,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9510,8 +10139,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -9529,14 +10158,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin end else begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9548,8 +10177,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -9567,13 +10196,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin + main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -9586,8 +10215,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -9605,13 +10234,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin - litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin + main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready; end else begin end end else begin @@ -9623,193 +10252,181 @@ always @(*) begin end endcase end +assign main_litedramcore_bankmachine6_sink_valid = main_litedramcore_bankmachine6_req_valid; +assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_sink_ready; +assign main_litedramcore_bankmachine6_sink_payload_we = main_litedramcore_bankmachine6_req_we; +assign main_litedramcore_bankmachine6_sink_payload_addr = main_litedramcore_bankmachine6_req_addr; +assign main_litedramcore_bankmachine6_sink_sink_valid = main_litedramcore_bankmachine6_source_valid; +assign main_litedramcore_bankmachine6_source_ready = main_litedramcore_bankmachine6_sink_sink_ready; +assign main_litedramcore_bankmachine6_sink_sink_first = main_litedramcore_bankmachine6_source_first; +assign main_litedramcore_bankmachine6_sink_sink_last = main_litedramcore_bankmachine6_source_last; +assign main_litedramcore_bankmachine6_sink_sink_payload_we = main_litedramcore_bankmachine6_source_payload_we; +assign main_litedramcore_bankmachine6_sink_sink_payload_addr = main_litedramcore_bankmachine6_source_payload_addr; +assign main_litedramcore_bankmachine6_source_source_ready = (main_litedramcore_bankmachine6_req_wdata_ready | main_litedramcore_bankmachine6_req_rdata_valid); +assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_source_valid | main_litedramcore_bankmachine6_source_source_valid); +assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_source_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; always @(*) begin - litedramcore_bankmachine5_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin + main_litedramcore_bankmachine6_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin + main_litedramcore_bankmachine6_cmd_payload_a <= main_litedramcore_bankmachine6_source_source_payload_addr[21:7]; + end else begin + main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write); +assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); +assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); +always @(*) begin + main_litedramcore_bankmachine6_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine6_source_valid & main_litedramcore_bankmachine6_source_source_valid)) begin + if ((main_litedramcore_bankmachine6_source_payload_addr[21:7] != main_litedramcore_bankmachine6_source_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine6_syncfifo6_din = {main_litedramcore_bankmachine6_fifo_in_last, main_litedramcore_bankmachine6_fifo_in_first, main_litedramcore_bankmachine6_fifo_in_payload_addr, main_litedramcore_bankmachine6_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout; +assign main_litedramcore_bankmachine6_sink_ready = main_litedramcore_bankmachine6_syncfifo6_writable; +assign main_litedramcore_bankmachine6_syncfifo6_we = main_litedramcore_bankmachine6_sink_valid; +assign main_litedramcore_bankmachine6_fifo_in_first = main_litedramcore_bankmachine6_sink_first; +assign main_litedramcore_bankmachine6_fifo_in_last = main_litedramcore_bankmachine6_sink_last; +assign main_litedramcore_bankmachine6_fifo_in_payload_we = main_litedramcore_bankmachine6_sink_payload_we; +assign main_litedramcore_bankmachine6_fifo_in_payload_addr = main_litedramcore_bankmachine6_sink_payload_addr; +assign main_litedramcore_bankmachine6_source_valid = main_litedramcore_bankmachine6_syncfifo6_readable; +assign main_litedramcore_bankmachine6_source_first = main_litedramcore_bankmachine6_fifo_out_first; +assign main_litedramcore_bankmachine6_source_last = main_litedramcore_bankmachine6_fifo_out_last; +assign main_litedramcore_bankmachine6_source_payload_we = main_litedramcore_bankmachine6_fifo_out_payload_we; +assign main_litedramcore_bankmachine6_source_payload_addr = main_litedramcore_bankmachine6_fifo_out_payload_addr; +assign main_litedramcore_bankmachine6_syncfifo6_re = main_litedramcore_bankmachine6_source_ready; +always @(*) begin + main_litedramcore_bankmachine6_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine6_replace) begin + main_litedramcore_bankmachine6_wrport_adr <= (main_litedramcore_bankmachine6_produce - 1'd1); + end else begin + main_litedramcore_bankmachine6_wrport_adr <= main_litedramcore_bankmachine6_produce; + end +end +assign main_litedramcore_bankmachine6_wrport_dat_w = main_litedramcore_bankmachine6_syncfifo6_din; +assign main_litedramcore_bankmachine6_wrport_we = (main_litedramcore_bankmachine6_syncfifo6_we & (main_litedramcore_bankmachine6_syncfifo6_writable | main_litedramcore_bankmachine6_replace)); +assign main_litedramcore_bankmachine6_do_read = (main_litedramcore_bankmachine6_syncfifo6_readable & main_litedramcore_bankmachine6_syncfifo6_re); +assign main_litedramcore_bankmachine6_rdport_adr = main_litedramcore_bankmachine6_consume; +assign main_litedramcore_bankmachine6_syncfifo6_dout = main_litedramcore_bankmachine6_rdport_dat_r; +assign main_litedramcore_bankmachine6_syncfifo6_writable = (main_litedramcore_bankmachine6_level != 5'd16); +assign main_litedramcore_bankmachine6_syncfifo6_readable = (main_litedramcore_bankmachine6_level != 1'd0); +assign main_litedramcore_bankmachine6_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine6_pipe_valid_source_valid) | main_litedramcore_bankmachine6_pipe_valid_source_ready); +assign main_litedramcore_bankmachine6_pipe_valid_sink_valid = main_litedramcore_bankmachine6_sink_sink_valid; +assign main_litedramcore_bankmachine6_sink_sink_ready = main_litedramcore_bankmachine6_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine6_pipe_valid_sink_first = main_litedramcore_bankmachine6_sink_sink_first; +assign main_litedramcore_bankmachine6_pipe_valid_sink_last = main_litedramcore_bankmachine6_sink_sink_last; +assign main_litedramcore_bankmachine6_pipe_valid_sink_payload_we = main_litedramcore_bankmachine6_sink_sink_payload_we; +assign main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine6_sink_sink_payload_addr; +assign main_litedramcore_bankmachine6_source_source_valid = main_litedramcore_bankmachine6_pipe_valid_source_valid; +assign main_litedramcore_bankmachine6_pipe_valid_source_ready = main_litedramcore_bankmachine6_source_source_ready; +assign main_litedramcore_bankmachine6_source_source_first = main_litedramcore_bankmachine6_pipe_valid_source_first; +assign main_litedramcore_bankmachine6_source_source_last = main_litedramcore_bankmachine6_pipe_valid_source_last; +assign main_litedramcore_bankmachine6_source_source_payload_we = main_litedramcore_bankmachine6_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine6_source_source_payload_addr = main_litedramcore_bankmachine6_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine6_next_state <= 4'd0; + builder_bankmachine6_next_state <= builder_bankmachine6_state; + case (builder_bankmachine6_state) + 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + if (main_litedramcore_bankmachine6_cmd_ready) begin + builder_bankmachine6_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + builder_bankmachine6_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + if (main_litedramcore_bankmachine6_cmd_ready) begin + builder_bankmachine6_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine6_refresh_req)) begin + builder_bankmachine6_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine6_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine6_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine6_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine6_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin + builder_bankmachine6_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin - end else begin - litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if ((main_litedramcore_bankmachine6_cmd_ready & main_litedramcore_bankmachine6_auto_precharge)) begin + builder_bankmachine6_next_state <= 2'd2; end end else begin + builder_bankmachine6_next_state <= 1'd1; end end else begin + builder_bankmachine6_next_state <= 2'd3; end end end end endcase end -assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid; -assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready; -assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we; -assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr; -assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid; -assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready; -assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first; -assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last; -assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we; -assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr; -assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); -assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid); -assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[21:7]); -assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6; always @(*) begin - litedramcore_bankmachine6_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine6_row_col_n_addr_sel) begin - litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_source_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write); -assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); -assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); -always @(*) begin - litedramcore_bankmachine6_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin - if ((litedramcore_bankmachine6_source_payload_addr[21:7] != litedramcore_bankmachine6_source_source_payload_addr[21:7])) begin - litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we}; -assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; -assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; -assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; -assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; -assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable; -assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid; -assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first; -assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last; -assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we; -assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr; -assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable; -assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first; -assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last; -assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we; -assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr; -assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready; -always @(*) begin - litedramcore_bankmachine6_wrport_adr <= 4'd0; - if (litedramcore_bankmachine6_replace) begin - litedramcore_bankmachine6_wrport_adr <= (litedramcore_bankmachine6_produce - 1'd1); - end else begin - litedramcore_bankmachine6_wrport_adr <= litedramcore_bankmachine6_produce; - end -end -assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din; -assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace)); -assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re); -assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume; -assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r; -assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 5'd16); -assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0); -assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready); -assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid; -assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready; -assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first; -assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last; -assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we; -assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr; -assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid; -assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready; -assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first; -assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last; -assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we; -assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine6_next_state <= 4'd0; - litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - if (litedramcore_bankmachine6_cmd_ready) begin - litedramcore_bankmachine6_next_state <= 3'd5; - end - end + main_litedramcore_bankmachine6_row_close <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_next_state <= 3'd5; - end + main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - if (litedramcore_bankmachine6_cmd_ready) begin - litedramcore_bankmachine6_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~litedramcore_bankmachine6_refresh_req)) begin - litedramcore_bankmachine6_next_state <= 1'd0; - end + main_litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin - litedramcore_bankmachine6_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine6_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine6_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine6_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - litedramcore_bankmachine6_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin - litedramcore_bankmachine6_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine6_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine6_next_state <= 2'd3; - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -9827,8 +10444,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -9846,12 +10463,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -9862,18 +10479,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -9891,11 +10508,11 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -9913,13 +10530,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -9932,22 +10549,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9962,8 +10579,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -9981,14 +10598,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin end else begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; end end else begin end @@ -10000,8 +10617,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -10019,13 +10636,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin + main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -10038,8 +10655,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -10057,13 +10674,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin - litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin + main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready; end else begin end end else begin @@ -10076,8 +10693,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -10095,14 +10712,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin end else begin - litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; + main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready; end end else begin end @@ -10114,8 +10731,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -10123,8 +10740,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine6_twtpcon_ready) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd1; + if (main_litedramcore_bankmachine6_twtpcon_ready) begin + main_litedramcore_bankmachine6_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -10140,15 +10757,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_row_open <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_row_open <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_open <= 1'd1; + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_open <= 1'd1; end end 3'd4: begin @@ -10166,18 +10783,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_valid <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_valid <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; end end 3'd4: begin @@ -10191,12 +10808,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; end else begin end end else begin @@ -10206,165 +10823,174 @@ always @(*) begin end endcase end +assign main_litedramcore_bankmachine7_sink_valid = main_litedramcore_bankmachine7_req_valid; +assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_sink_ready; +assign main_litedramcore_bankmachine7_sink_payload_we = main_litedramcore_bankmachine7_req_we; +assign main_litedramcore_bankmachine7_sink_payload_addr = main_litedramcore_bankmachine7_req_addr; +assign main_litedramcore_bankmachine7_sink_sink_valid = main_litedramcore_bankmachine7_source_valid; +assign main_litedramcore_bankmachine7_source_ready = main_litedramcore_bankmachine7_sink_sink_ready; +assign main_litedramcore_bankmachine7_sink_sink_first = main_litedramcore_bankmachine7_source_first; +assign main_litedramcore_bankmachine7_sink_sink_last = main_litedramcore_bankmachine7_source_last; +assign main_litedramcore_bankmachine7_sink_sink_payload_we = main_litedramcore_bankmachine7_source_payload_we; +assign main_litedramcore_bankmachine7_sink_sink_payload_addr = main_litedramcore_bankmachine7_source_payload_addr; +assign main_litedramcore_bankmachine7_source_source_ready = (main_litedramcore_bankmachine7_req_wdata_ready | main_litedramcore_bankmachine7_req_rdata_valid); +assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_source_valid | main_litedramcore_bankmachine7_source_source_valid); +assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_source_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7; always @(*) begin - litedramcore_bankmachine6_row_close <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - litedramcore_bankmachine6_row_close <= 1'd1; + main_litedramcore_bankmachine7_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin + main_litedramcore_bankmachine7_cmd_payload_a <= main_litedramcore_bankmachine7_source_source_payload_addr[21:7]; + end else begin + main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write); +assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); +assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); +always @(*) begin + main_litedramcore_bankmachine7_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine7_source_valid & main_litedramcore_bankmachine7_source_source_valid)) begin + if ((main_litedramcore_bankmachine7_source_payload_addr[21:7] != main_litedramcore_bankmachine7_source_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine7_syncfifo7_din = {main_litedramcore_bankmachine7_fifo_in_last, main_litedramcore_bankmachine7_fifo_in_first, main_litedramcore_bankmachine7_fifo_in_payload_addr, main_litedramcore_bankmachine7_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout; +assign main_litedramcore_bankmachine7_sink_ready = main_litedramcore_bankmachine7_syncfifo7_writable; +assign main_litedramcore_bankmachine7_syncfifo7_we = main_litedramcore_bankmachine7_sink_valid; +assign main_litedramcore_bankmachine7_fifo_in_first = main_litedramcore_bankmachine7_sink_first; +assign main_litedramcore_bankmachine7_fifo_in_last = main_litedramcore_bankmachine7_sink_last; +assign main_litedramcore_bankmachine7_fifo_in_payload_we = main_litedramcore_bankmachine7_sink_payload_we; +assign main_litedramcore_bankmachine7_fifo_in_payload_addr = main_litedramcore_bankmachine7_sink_payload_addr; +assign main_litedramcore_bankmachine7_source_valid = main_litedramcore_bankmachine7_syncfifo7_readable; +assign main_litedramcore_bankmachine7_source_first = main_litedramcore_bankmachine7_fifo_out_first; +assign main_litedramcore_bankmachine7_source_last = main_litedramcore_bankmachine7_fifo_out_last; +assign main_litedramcore_bankmachine7_source_payload_we = main_litedramcore_bankmachine7_fifo_out_payload_we; +assign main_litedramcore_bankmachine7_source_payload_addr = main_litedramcore_bankmachine7_fifo_out_payload_addr; +assign main_litedramcore_bankmachine7_syncfifo7_re = main_litedramcore_bankmachine7_source_ready; +always @(*) begin + main_litedramcore_bankmachine7_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine7_replace) begin + main_litedramcore_bankmachine7_wrport_adr <= (main_litedramcore_bankmachine7_produce - 1'd1); + end else begin + main_litedramcore_bankmachine7_wrport_adr <= main_litedramcore_bankmachine7_produce; + end +end +assign main_litedramcore_bankmachine7_wrport_dat_w = main_litedramcore_bankmachine7_syncfifo7_din; +assign main_litedramcore_bankmachine7_wrport_we = (main_litedramcore_bankmachine7_syncfifo7_we & (main_litedramcore_bankmachine7_syncfifo7_writable | main_litedramcore_bankmachine7_replace)); +assign main_litedramcore_bankmachine7_do_read = (main_litedramcore_bankmachine7_syncfifo7_readable & main_litedramcore_bankmachine7_syncfifo7_re); +assign main_litedramcore_bankmachine7_rdport_adr = main_litedramcore_bankmachine7_consume; +assign main_litedramcore_bankmachine7_syncfifo7_dout = main_litedramcore_bankmachine7_rdport_dat_r; +assign main_litedramcore_bankmachine7_syncfifo7_writable = (main_litedramcore_bankmachine7_level != 5'd16); +assign main_litedramcore_bankmachine7_syncfifo7_readable = (main_litedramcore_bankmachine7_level != 1'd0); +assign main_litedramcore_bankmachine7_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine7_pipe_valid_source_valid) | main_litedramcore_bankmachine7_pipe_valid_source_ready); +assign main_litedramcore_bankmachine7_pipe_valid_sink_valid = main_litedramcore_bankmachine7_sink_sink_valid; +assign main_litedramcore_bankmachine7_sink_sink_ready = main_litedramcore_bankmachine7_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine7_pipe_valid_sink_first = main_litedramcore_bankmachine7_sink_sink_first; +assign main_litedramcore_bankmachine7_pipe_valid_sink_last = main_litedramcore_bankmachine7_sink_sink_last; +assign main_litedramcore_bankmachine7_pipe_valid_sink_payload_we = main_litedramcore_bankmachine7_sink_sink_payload_we; +assign main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine7_sink_sink_payload_addr; +assign main_litedramcore_bankmachine7_source_source_valid = main_litedramcore_bankmachine7_pipe_valid_source_valid; +assign main_litedramcore_bankmachine7_pipe_valid_source_ready = main_litedramcore_bankmachine7_source_source_ready; +assign main_litedramcore_bankmachine7_source_source_first = main_litedramcore_bankmachine7_pipe_valid_source_first; +assign main_litedramcore_bankmachine7_source_source_last = main_litedramcore_bankmachine7_pipe_valid_source_last; +assign main_litedramcore_bankmachine7_source_source_payload_we = main_litedramcore_bankmachine7_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine7_source_source_payload_addr = main_litedramcore_bankmachine7_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine7_next_state <= 4'd0; + builder_bankmachine7_next_state <= builder_bankmachine7_state; + case (builder_bankmachine7_state) + 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + if (main_litedramcore_bankmachine7_cmd_ready) begin + builder_bankmachine7_next_state <= 3'd5; + end + end end 2'd2: begin - litedramcore_bankmachine6_row_close <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + builder_bankmachine7_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + if (main_litedramcore_bankmachine7_cmd_ready) begin + builder_bankmachine7_next_state <= 3'd7; + end + end end 3'd4: begin - litedramcore_bankmachine6_row_close <= 1'd1; + if ((~main_litedramcore_bankmachine7_refresh_req)) begin + builder_bankmachine7_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine7_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine7_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine7_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine7_next_state <= 1'd0; end default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + builder_bankmachine7_next_state <= 3'd4; + end else begin + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if ((main_litedramcore_bankmachine7_cmd_ready & main_litedramcore_bankmachine7_auto_precharge)) begin + builder_bankmachine7_next_state <= 2'd2; + end + end else begin + builder_bankmachine7_next_state <= 1'd1; + end + end else begin + builder_bankmachine7_next_state <= 2'd3; + end + end + end end endcase end -assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid; -assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready; -assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we; -assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr; -assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid; -assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready; -assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first; -assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last; -assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we; -assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr; -assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); -assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid); -assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[21:7]); -assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7; -always @(*) begin - litedramcore_bankmachine7_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine7_row_col_n_addr_sel) begin - litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_source_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write); -assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); -assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); -always @(*) begin - litedramcore_bankmachine7_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin - if ((litedramcore_bankmachine7_source_payload_addr[21:7] != litedramcore_bankmachine7_source_source_payload_addr[21:7])) begin - litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we}; -assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; -assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; -assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; -assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; -assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable; -assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid; -assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first; -assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last; -assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we; -assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr; -assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable; -assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first; -assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last; -assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we; -assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr; -assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready; -always @(*) begin - litedramcore_bankmachine7_wrport_adr <= 4'd0; - if (litedramcore_bankmachine7_replace) begin - litedramcore_bankmachine7_wrport_adr <= (litedramcore_bankmachine7_produce - 1'd1); - end else begin - litedramcore_bankmachine7_wrport_adr <= litedramcore_bankmachine7_produce; - end -end -assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din; -assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace)); -assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re); -assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume; -assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r; -assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 5'd16); -assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0); -assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready); -assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid; -assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready; -assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first; -assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last; -assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we; -assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr; -assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid; -assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready; -assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first; -assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last; -assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we; -assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine7_next_state <= 4'd0; - litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - if (litedramcore_bankmachine7_cmd_ready) begin - litedramcore_bankmachine7_next_state <= 3'd5; - end - end +always @(*) begin + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin end 2'd2: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - if (litedramcore_bankmachine7_cmd_ready) begin - litedramcore_bankmachine7_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~litedramcore_bankmachine7_refresh_req)) begin - litedramcore_bankmachine7_next_state <= 1'd0; - end end 3'd5: begin - litedramcore_bankmachine7_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine7_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine7_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine7_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - litedramcore_bankmachine7_next_state <= 3'd4; + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin - litedramcore_bankmachine7_next_state <= 2'd2; - end + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; end else begin - litedramcore_bankmachine7_next_state <= 1'd1; end end else begin - litedramcore_bankmachine7_next_state <= 2'd3; end end end @@ -10372,18 +10998,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -10401,11 +11027,11 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -10423,13 +11049,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -10442,22 +11068,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -10472,8 +11098,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -10491,14 +11117,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin end else begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; end end else begin end @@ -10510,8 +11136,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -10529,13 +11155,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -10548,8 +11174,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -10567,13 +11193,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin - litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin + main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready; end else begin end end else begin @@ -10586,8 +11212,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -10605,14 +11231,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin end else begin - litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; + main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready; end end else begin end @@ -10624,8 +11250,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -10633,8 +11259,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine7_twtpcon_ready) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd1; + if (main_litedramcore_bankmachine7_twtpcon_ready) begin + main_litedramcore_bankmachine7_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -10650,15 +11276,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_row_open <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_row_open <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_open <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_row_open <= 1'd1; end end 3'd4: begin @@ -10676,18 +11302,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_valid <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; end end 3'd4: begin @@ -10701,12 +11327,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; end else begin end end else begin @@ -10717,18 +11343,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_row_close <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_row_close <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - litedramcore_bankmachine7_row_close <= 1'd1; + main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine7_row_close <= 1'd1; + main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine7_row_close <= 1'd1; + main_litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -10743,15 +11369,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -10768,301 +11394,259 @@ always @(*) begin end endcase end +assign main_litedramcore_nphases = (main_k7ddrphy_rdphase_storage - 1'd1); +assign main_litedramcore_rdphase = (main_k7ddrphy_wrphase_storage - 1'd1); +assign main_litedramcore_trrdcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))); +assign main_litedramcore_tfawcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))); +assign main_litedramcore_ras_allowed = (main_litedramcore_trrdcon_ready & main_litedramcore_tfawcon_ready); +assign main_litedramcore_tccdcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_cmd_payload_is_write | main_litedramcore_choose_req_cmd_payload_is_read)); +assign main_litedramcore_cas_allowed = main_litedramcore_tccdcon_ready; +assign main_litedramcore_twtrcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); +assign main_litedramcore_read_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_read) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_read)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_read)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_read)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_read)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_read)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_read)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_read)); +assign main_litedramcore_write_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_write) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_write)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_write)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_write)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_write)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_write)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_write)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_write)); +assign main_litedramcore_max_time0 = (main_litedramcore_time0 == 1'd0); +assign main_litedramcore_max_time1 = (main_litedramcore_time1 == 1'd0); +assign main_litedramcore_bankmachine0_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine1_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine2_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine3_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine4_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine5_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine6_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine7_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_go_to_refresh = (((((((main_litedramcore_bankmachine0_refresh_gnt & main_litedramcore_bankmachine1_refresh_gnt) & main_litedramcore_bankmachine2_refresh_gnt) & main_litedramcore_bankmachine3_refresh_gnt) & main_litedramcore_bankmachine4_refresh_gnt) & main_litedramcore_bankmachine5_refresh_gnt) & main_litedramcore_bankmachine6_refresh_gnt) & main_litedramcore_bankmachine7_refresh_gnt); +assign main_litedramcore_interface_rdata = {main_litedramcore_dfi_p3_rddata, main_litedramcore_dfi_p2_rddata, main_litedramcore_dfi_p1_rddata, main_litedramcore_dfi_p0_rddata}; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); always @(*) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_rdcmdphase = (k7ddrphy_rdphase_storage - 1'd1); -assign litedramcore_wrcmdphase = (k7ddrphy_wrphase_storage - 1'd1); -assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); -assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); -assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready); -assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read)); -assign litedramcore_cas_allowed = litedramcore_tccdcon_ready; -assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); -assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read)); -assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write)); -assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0); -assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0); -assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid; -assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt); -assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata}; -assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; -assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; -assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; -assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; -assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); -assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); -assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); -assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); -always @(*) begin - litedramcore_choose_cmd_valids <= 8'd0; - litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids <= 8'd0; + main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); end -assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; -assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0; -assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1; -assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2; -assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; -assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; -assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; +assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids; +assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_self0; +assign main_litedramcore_choose_cmd_cmd_payload_a = builder_rhs_self1; +assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_self2; +assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_self3; +assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_self4; +assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_self5; always @(*) begin - litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; + main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_self0; end end always @(*) begin - litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; + main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_self1; end end always @(*) begin - litedramcore_choose_cmd_cmd_payload_we <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; + main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_self2; end end always @(*) begin - litedramcore_bankmachine0_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin - litedramcore_bankmachine0_cmd_ready <= 1'd1; + main_litedramcore_bankmachine0_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin + main_litedramcore_bankmachine0_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin - litedramcore_bankmachine0_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin + main_litedramcore_bankmachine0_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine1_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin - litedramcore_bankmachine1_cmd_ready <= 1'd1; + main_litedramcore_bankmachine1_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin + main_litedramcore_bankmachine1_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin - litedramcore_bankmachine1_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin + main_litedramcore_bankmachine1_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine2_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin - litedramcore_bankmachine2_cmd_ready <= 1'd1; + main_litedramcore_bankmachine2_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin + main_litedramcore_bankmachine2_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin - litedramcore_bankmachine2_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin + main_litedramcore_bankmachine2_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine3_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin - litedramcore_bankmachine3_cmd_ready <= 1'd1; + main_litedramcore_bankmachine3_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin + main_litedramcore_bankmachine3_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin - litedramcore_bankmachine3_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin + main_litedramcore_bankmachine3_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine4_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin - litedramcore_bankmachine4_cmd_ready <= 1'd1; + main_litedramcore_bankmachine4_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin + main_litedramcore_bankmachine4_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin - litedramcore_bankmachine4_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin + main_litedramcore_bankmachine4_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine5_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin - litedramcore_bankmachine5_cmd_ready <= 1'd1; + main_litedramcore_bankmachine5_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin + main_litedramcore_bankmachine5_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin - litedramcore_bankmachine5_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin + main_litedramcore_bankmachine5_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine6_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin - litedramcore_bankmachine6_cmd_ready <= 1'd1; + main_litedramcore_bankmachine6_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin + main_litedramcore_bankmachine6_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin - litedramcore_bankmachine6_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin + main_litedramcore_bankmachine6_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine7_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin - litedramcore_bankmachine7_cmd_ready <= 1'd1; + main_litedramcore_bankmachine7_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin + main_litedramcore_bankmachine7_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin - litedramcore_bankmachine7_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin + main_litedramcore_bankmachine7_cmd_ready <= 1'd1; end end -assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid)); +assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid)); always @(*) begin - litedramcore_choose_req_valids <= 8'd0; - litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids <= 8'd0; + main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); end -assign litedramcore_choose_req_request = litedramcore_choose_req_valids; -assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6; -assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7; -assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8; -assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9; -assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; -assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; +assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids; +assign main_litedramcore_choose_req_cmd_valid = builder_rhs_self6; +assign main_litedramcore_choose_req_cmd_payload_a = builder_rhs_self7; +assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_self8; +assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_self9; +assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_self10; +assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_self11; always @(*) begin - litedramcore_choose_req_cmd_payload_cas <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; + main_litedramcore_choose_req_cmd_payload_cas <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_cas <= builder_t_self3; end end always @(*) begin - litedramcore_choose_req_cmd_payload_ras <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; + main_litedramcore_choose_req_cmd_payload_ras <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_ras <= builder_t_self4; end end always @(*) begin - litedramcore_choose_req_cmd_payload_we <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; + main_litedramcore_choose_req_cmd_payload_we <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_we <= builder_t_self5; end end -assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); -assign litedramcore_dfi_p0_reset_n = 1'd1; -assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}}; -assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}}; -assign litedramcore_dfi_p1_reset_n = 1'd1; -assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}}; -assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}}; -assign litedramcore_dfi_p2_reset_n = 1'd1; -assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}}; -assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}}; -assign litedramcore_dfi_p3_reset_n = 1'd1; -assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}}; -assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}}; -assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]); +assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid)); +assign main_litedramcore_dfi_p0_reset_n = 1'd1; +assign main_litedramcore_dfi_p0_cke = {1{main_litedramcore_steerer4}}; +assign main_litedramcore_dfi_p0_odt = {1{main_litedramcore_steerer5}}; +assign main_litedramcore_dfi_p1_reset_n = 1'd1; +assign main_litedramcore_dfi_p1_cke = {1{main_litedramcore_steerer6}}; +assign main_litedramcore_dfi_p1_odt = {1{main_litedramcore_steerer7}}; +assign main_litedramcore_dfi_p2_reset_n = 1'd1; +assign main_litedramcore_dfi_p2_cke = {1{main_litedramcore_steerer8}}; +assign main_litedramcore_dfi_p2_odt = {1{main_litedramcore_steerer9}}; +assign main_litedramcore_dfi_p3_reset_n = 1'd1; +assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer10}}; +assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer11}}; +assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]); always @(*) begin - litedramcore_multiplexer_next_state <= 4'd0; - litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state; - case (litedramcore_multiplexer_state) + builder_multiplexer_next_state <= 4'd0; + builder_multiplexer_next_state <= builder_multiplexer_state; + case (builder_multiplexer_state) 1'd1: begin - if (litedramcore_read_available) begin - if (((~litedramcore_write_available) | litedramcore_max_time1)) begin - litedramcore_multiplexer_next_state <= 2'd3; + if (main_litedramcore_read_available) begin + if (((~main_litedramcore_write_available) | main_litedramcore_max_time1)) begin + builder_multiplexer_next_state <= 2'd3; end end - if (litedramcore_go_to_refresh) begin - litedramcore_multiplexer_next_state <= 2'd2; + if (main_litedramcore_go_to_refresh) begin + builder_multiplexer_next_state <= 2'd2; end end 2'd2: begin - if (litedramcore_cmd_last) begin - litedramcore_multiplexer_next_state <= 1'd0; + if (main_litedramcore_cmd_last) begin + builder_multiplexer_next_state <= 1'd0; end end 2'd3: begin - if (litedramcore_twtrcon_ready) begin - litedramcore_multiplexer_next_state <= 1'd0; + if (main_litedramcore_twtrcon_ready) begin + builder_multiplexer_next_state <= 1'd0; end end 3'd4: begin - litedramcore_multiplexer_next_state <= 3'd5; + builder_multiplexer_next_state <= 3'd5; end 3'd5: begin - litedramcore_multiplexer_next_state <= 3'd6; + builder_multiplexer_next_state <= 3'd6; end 3'd6: begin - litedramcore_multiplexer_next_state <= 3'd7; + builder_multiplexer_next_state <= 3'd7; end 3'd7: begin - litedramcore_multiplexer_next_state <= 4'd8; + builder_multiplexer_next_state <= 4'd8; end 4'd8: begin - litedramcore_multiplexer_next_state <= 4'd9; + builder_multiplexer_next_state <= 4'd9; end 4'd9: begin - litedramcore_multiplexer_next_state <= 4'd10; + builder_multiplexer_next_state <= 4'd10; end 4'd10: begin - litedramcore_multiplexer_next_state <= 1'd1; + builder_multiplexer_next_state <= 1'd1; end default: begin - if (litedramcore_write_available) begin - if (((~litedramcore_read_available) | litedramcore_max_time0)) begin - litedramcore_multiplexer_next_state <= 3'd4; + if (main_litedramcore_write_available) begin + if (((~main_litedramcore_read_available) | main_litedramcore_max_time0)) begin + builder_multiplexer_next_state <= 3'd4; end end - if (litedramcore_go_to_refresh) begin - litedramcore_multiplexer_next_state <= 2'd2; + if (main_litedramcore_go_to_refresh) begin + builder_multiplexer_next_state <= 2'd2; end end endcase end always @(*) begin - litedramcore_steerer_sel0 <= 2'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_en1 <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_steerer_sel0 <= 1'd0; - if ((k7ddrphy_wrphase_storage == 1'd0)) begin - litedramcore_steerer_sel0 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 1'd0)) begin - litedramcore_steerer_sel0 <= 1'd1; - end + main_litedramcore_en1 <= 1'd1; end 2'd2: begin - litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end @@ -11081,23 +11665,23 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel0 <= 1'd0; - if ((k7ddrphy_rdphase_storage == 1'd0)) begin - litedramcore_steerer_sel0 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 1'd0)) begin - litedramcore_steerer_sel0 <= 1'd1; - end end endcase end always @(*) begin - litedramcore_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_steerer0 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin + main_litedramcore_steerer0 <= 1'd0; + if ((main_k7ddrphy_wrphase_storage == 1'd0)) begin + main_litedramcore_steerer0 <= 2'd2; + end + if ((main_litedramcore_rdphase == 1'd0)) begin + main_litedramcore_steerer0 <= 1'd1; + end end 2'd2: begin - litedramcore_cmd_ready <= 1'd1; + main_litedramcore_steerer0 <= 2'd3; end 2'd3: begin end @@ -11116,22 +11700,23 @@ always @(*) begin 4'd10: begin end default: begin + main_litedramcore_steerer0 <= 1'd0; + if ((main_k7ddrphy_rdphase_storage == 1'd0)) begin + main_litedramcore_steerer0 <= 2'd2; + end + if ((main_litedramcore_nphases == 1'd0)) begin + main_litedramcore_steerer0 <= 1'd1; + end end endcase end always @(*) begin - litedramcore_steerer_sel1 <= 2'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_cmd_ready <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_steerer_sel1 <= 1'd0; - if ((k7ddrphy_wrphase_storage == 1'd1)) begin - litedramcore_steerer_sel1 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 1'd1)) begin - litedramcore_steerer_sel1 <= 1'd1; - end end 2'd2: begin + main_litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -11150,26 +11735,19 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel1 <= 1'd0; - if ((k7ddrphy_rdphase_storage == 1'd1)) begin - litedramcore_steerer_sel1 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 1'd1)) begin - litedramcore_steerer_sel1 <= 1'd1; - end end endcase end always @(*) begin - litedramcore_steerer_sel2 <= 2'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_steerer1 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_steerer_sel2 <= 1'd0; - if ((k7ddrphy_wrphase_storage == 2'd2)) begin - litedramcore_steerer_sel2 <= 2'd2; + main_litedramcore_steerer1 <= 1'd0; + if ((main_k7ddrphy_wrphase_storage == 1'd1)) begin + main_litedramcore_steerer1 <= 2'd2; end - if ((litedramcore_wrcmdphase == 2'd2)) begin - litedramcore_steerer_sel2 <= 1'd1; + if ((main_litedramcore_rdphase == 1'd1)) begin + main_litedramcore_steerer1 <= 1'd1; end end 2'd2: begin @@ -11191,23 +11769,26 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel2 <= 1'd0; - if ((k7ddrphy_rdphase_storage == 2'd2)) begin - litedramcore_steerer_sel2 <= 2'd2; + main_litedramcore_steerer1 <= 1'd0; + if ((main_k7ddrphy_rdphase_storage == 1'd1)) begin + main_litedramcore_steerer1 <= 2'd2; end - if ((litedramcore_rdcmdphase == 2'd2)) begin - litedramcore_steerer_sel2 <= 1'd1; + if ((main_litedramcore_nphases == 1'd1)) begin + main_litedramcore_steerer1 <= 1'd1; end end endcase end always @(*) begin - litedramcore_choose_cmd_want_activates <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_steerer2 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + main_litedramcore_steerer2 <= 1'd0; + if ((main_k7ddrphy_wrphase_storage == 2'd2)) begin + main_litedramcore_steerer2 <= 2'd2; + end + if ((main_litedramcore_rdphase == 2'd2)) begin + main_litedramcore_steerer2 <= 1'd1; end end 2'd2: begin @@ -11229,23 +11810,23 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + main_litedramcore_steerer2 <= 1'd0; + if ((main_k7ddrphy_rdphase_storage == 2'd2)) begin + main_litedramcore_steerer2 <= 2'd2; + end + if ((main_litedramcore_nphases == 2'd2)) begin + main_litedramcore_steerer2 <= 1'd1; end end endcase end always @(*) begin - litedramcore_steerer_sel3 <= 2'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_cmd_want_activates <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_steerer_sel3 <= 1'd0; - if ((k7ddrphy_wrphase_storage == 2'd3)) begin - litedramcore_steerer_sel3 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 2'd3)) begin - litedramcore_steerer_sel3 <= 1'd1; + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; end end 2'd2: begin @@ -11267,20 +11848,24 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel3 <= 1'd0; - if ((k7ddrphy_rdphase_storage == 2'd3)) begin - litedramcore_steerer_sel3 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 2'd3)) begin - litedramcore_steerer_sel3 <= 1'd1; + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; end end endcase end always @(*) begin - litedramcore_en0 <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_steerer3 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin + main_litedramcore_steerer3 <= 1'd0; + if ((main_k7ddrphy_wrphase_storage == 2'd3)) begin + main_litedramcore_steerer3 <= 2'd2; + end + if ((main_litedramcore_rdphase == 2'd3)) begin + main_litedramcore_steerer3 <= 1'd1; + end end 2'd2: begin end @@ -11301,15 +11886,20 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_en0 <= 1'd1; + main_litedramcore_steerer3 <= 1'd0; + if ((main_k7ddrphy_rdphase_storage == 2'd3)) begin + main_litedramcore_steerer3 <= 2'd2; + end + if ((main_litedramcore_nphases == 2'd3)) begin + main_litedramcore_steerer3 <= 1'd1; + end end endcase end always @(*) begin - litedramcore_en1 <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_en0 <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_en1 <= 1'd1; end 2'd2: begin end @@ -11330,16 +11920,17 @@ always @(*) begin 4'd10: begin end default: begin + main_litedramcore_en0 <= 1'd1; end endcase end always @(*) begin - litedramcore_choose_cmd_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_cmd_cmd_ready <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin if (1'd0) begin end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); end end 2'd2: begin @@ -11363,14 +11954,14 @@ always @(*) begin default: begin if (1'd0) begin end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); end end endcase end always @(*) begin - litedramcore_choose_req_want_reads <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_req_want_reads <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin end 2'd2: begin @@ -11392,15 +11983,15 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_choose_req_want_reads <= 1'd1; + main_litedramcore_choose_req_want_reads <= 1'd1; end endcase end always @(*) begin - litedramcore_choose_req_want_writes <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_req_want_writes <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_choose_req_want_writes <= 1'd1; + main_litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -11425,13 +12016,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_choose_req_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_req_cmd_ready <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; end end 2'd2: begin @@ -11454,2205 +12045,2202 @@ always @(*) begin end default: begin if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end - end - endcase -end -assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock)); -assign litedramcore_interface_bank0_addr = rhs_array_muxed12; -assign litedramcore_interface_bank0_we = rhs_array_muxed13; -assign litedramcore_interface_bank0_valid = rhs_array_muxed14; -assign litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock)); -assign litedramcore_interface_bank1_addr = rhs_array_muxed15; -assign litedramcore_interface_bank1_we = rhs_array_muxed16; -assign litedramcore_interface_bank1_valid = rhs_array_muxed17; -assign litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock)); -assign litedramcore_interface_bank2_addr = rhs_array_muxed18; -assign litedramcore_interface_bank2_we = rhs_array_muxed19; -assign litedramcore_interface_bank2_valid = rhs_array_muxed20; -assign litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock)); -assign litedramcore_interface_bank3_addr = rhs_array_muxed21; -assign litedramcore_interface_bank3_we = rhs_array_muxed22; -assign litedramcore_interface_bank3_valid = rhs_array_muxed23; -assign litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock)); -assign litedramcore_interface_bank4_addr = rhs_array_muxed24; -assign litedramcore_interface_bank4_we = rhs_array_muxed25; -assign litedramcore_interface_bank4_valid = rhs_array_muxed26; -assign litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock)); -assign litedramcore_interface_bank5_addr = rhs_array_muxed27; -assign litedramcore_interface_bank5_we = rhs_array_muxed28; -assign litedramcore_interface_bank5_valid = rhs_array_muxed29; -assign litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock)); -assign litedramcore_interface_bank6_addr = rhs_array_muxed30; -assign litedramcore_interface_bank6_we = rhs_array_muxed31; -assign litedramcore_interface_bank6_valid = rhs_array_muxed32; -assign litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock)); -assign litedramcore_interface_bank7_addr = rhs_array_muxed33; -assign litedramcore_interface_bank7_we = rhs_array_muxed34; -assign litedramcore_interface_bank7_valid = rhs_array_muxed35; -assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready)); -assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1; -assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8; -always @(*) begin - litedramcore_interface_wdata <= 256'd0; - case ({litedramcore_new_master_wdata_ready1}) - 1'd1: begin - litedramcore_interface_wdata <= user_port_wdata_payload_data; + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; + end + end + endcase +end +assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock)); +assign main_litedramcore_interface_bank0_addr = builder_rhs_self12; +assign main_litedramcore_interface_bank0_we = builder_rhs_self13; +assign main_litedramcore_interface_bank0_valid = builder_rhs_self14; +assign builder_roundrobin1_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin1_ce = ((~main_litedramcore_interface_bank1_valid) & (~main_litedramcore_interface_bank1_lock)); +assign main_litedramcore_interface_bank1_addr = builder_rhs_self15; +assign main_litedramcore_interface_bank1_we = builder_rhs_self16; +assign main_litedramcore_interface_bank1_valid = builder_rhs_self17; +assign builder_roundrobin2_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin2_ce = ((~main_litedramcore_interface_bank2_valid) & (~main_litedramcore_interface_bank2_lock)); +assign main_litedramcore_interface_bank2_addr = builder_rhs_self18; +assign main_litedramcore_interface_bank2_we = builder_rhs_self19; +assign main_litedramcore_interface_bank2_valid = builder_rhs_self20; +assign builder_roundrobin3_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin3_ce = ((~main_litedramcore_interface_bank3_valid) & (~main_litedramcore_interface_bank3_lock)); +assign main_litedramcore_interface_bank3_addr = builder_rhs_self21; +assign main_litedramcore_interface_bank3_we = builder_rhs_self22; +assign main_litedramcore_interface_bank3_valid = builder_rhs_self23; +assign builder_roundrobin4_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin4_ce = ((~main_litedramcore_interface_bank4_valid) & (~main_litedramcore_interface_bank4_lock)); +assign main_litedramcore_interface_bank4_addr = builder_rhs_self24; +assign main_litedramcore_interface_bank4_we = builder_rhs_self25; +assign main_litedramcore_interface_bank4_valid = builder_rhs_self26; +assign builder_roundrobin5_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin5_ce = ((~main_litedramcore_interface_bank5_valid) & (~main_litedramcore_interface_bank5_lock)); +assign main_litedramcore_interface_bank5_addr = builder_rhs_self27; +assign main_litedramcore_interface_bank5_we = builder_rhs_self28; +assign main_litedramcore_interface_bank5_valid = builder_rhs_self29; +assign builder_roundrobin6_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin6_ce = ((~main_litedramcore_interface_bank6_valid) & (~main_litedramcore_interface_bank6_lock)); +assign main_litedramcore_interface_bank6_addr = builder_rhs_self30; +assign main_litedramcore_interface_bank6_we = builder_rhs_self31; +assign main_litedramcore_interface_bank6_valid = builder_rhs_self32; +assign builder_roundrobin7_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin7_ce = ((~main_litedramcore_interface_bank7_valid) & (~main_litedramcore_interface_bank7_lock)); +assign main_litedramcore_interface_bank7_addr = builder_rhs_self33; +assign main_litedramcore_interface_bank7_we = builder_rhs_self34; +assign main_litedramcore_interface_bank7_valid = builder_rhs_self35; +assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready)); +assign main_user_port_wdata_ready = builder_new_master_wdata_ready1; +assign main_user_port_rdata_valid = builder_new_master_rdata_valid8; +always @(*) begin + main_litedramcore_interface_wdata_we <= 32'd0; + case ({builder_new_master_wdata_ready1}) + 1'd1: begin + main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we; end default: begin - litedramcore_interface_wdata <= 1'd0; + main_litedramcore_interface_wdata_we <= 1'd0; end endcase end always @(*) begin - litedramcore_interface_wdata_we <= 32'd0; - case ({litedramcore_new_master_wdata_ready1}) + main_litedramcore_interface_wdata <= 256'd0; + case ({builder_new_master_wdata_ready1}) 1'd1: begin - litedramcore_interface_wdata_we <= user_port_wdata_payload_we; + main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data; end default: begin - litedramcore_interface_wdata_we <= 1'd0; + main_litedramcore_interface_wdata <= 1'd0; end endcase end -assign user_port_rdata_payload_data = litedramcore_interface_rdata; -assign litedramcore_roundrobin0_grant = 1'd0; -assign litedramcore_roundrobin1_grant = 1'd0; -assign litedramcore_roundrobin2_grant = 1'd0; -assign litedramcore_roundrobin3_grant = 1'd0; -assign litedramcore_roundrobin4_grant = 1'd0; -assign litedramcore_roundrobin5_grant = 1'd0; -assign litedramcore_roundrobin6_grant = 1'd0; -assign litedramcore_roundrobin7_grant = 1'd0; +assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata; +assign builder_roundrobin0_grant = 1'd0; +assign builder_roundrobin1_grant = 1'd0; +assign builder_roundrobin2_grant = 1'd0; +assign builder_roundrobin3_grant = 1'd0; +assign builder_roundrobin4_grant = 1'd0; +assign builder_roundrobin5_grant = 1'd0; +assign builder_roundrobin6_grant = 1'd0; +assign builder_roundrobin7_grant = 1'd0; always @(*) begin - litedramcore_next_state <= 2'd0; - litedramcore_next_state <= litedramcore_state; - case (litedramcore_state) + builder_next_state <= 2'd0; + builder_next_state <= builder_state; + case (builder_state) 1'd1: begin - litedramcore_next_state <= 2'd2; + builder_next_state <= 2'd2; end 2'd2: begin - litedramcore_next_state <= 1'd0; + builder_next_state <= 1'd0; end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_next_state <= 1'd1; + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_next_state <= 1'd1; end end endcase end always @(*) begin - litedramcore_wishbone_dat_r <= 32'd0; - case (litedramcore_state) + builder_interface1_we_next_value2 <= 1'd0; + case (builder_state) 1'd1: begin + builder_interface1_we_next_value2 <= 1'd0; end 2'd2: begin - litedramcore_wishbone_dat_r <= litedramcore_dat_r; end default: begin + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_we_next_value2 <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); + end end endcase end always @(*) begin - litedramcore_wishbone_ack <= 1'd0; - case (litedramcore_state) + builder_interface1_we_next_value_ce2 <= 1'd0; + case (builder_state) 1'd1: begin + builder_interface1_we_next_value_ce2 <= 1'd1; end 2'd2: begin - litedramcore_wishbone_ack <= 1'd1; end default: begin + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_we_next_value_ce2 <= 1'd1; + end end endcase end always @(*) begin - litedramcore_dat_w_next_value0 <= 32'd0; - case (litedramcore_state) + builder_interface0_ack <= 1'd0; + case (builder_state) 1'd1: begin end 2'd2: begin + builder_interface0_ack <= 1'd1; end default: begin - litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w; end endcase end always @(*) begin - litedramcore_dat_w_next_value_ce0 <= 1'd0; - case (litedramcore_state) + builder_interface1_dat_w_next_value0 <= 32'd0; + case (builder_state) 1'd1: begin end 2'd2: begin end default: begin - litedramcore_dat_w_next_value_ce0 <= 1'd1; + builder_interface1_dat_w_next_value0 <= builder_interface0_dat_w; end endcase end always @(*) begin - litedramcore_adr_next_value1 <= 14'd0; - case (litedramcore_state) + builder_interface1_dat_w_next_value_ce0 <= 1'd0; + case (builder_state) 1'd1: begin - litedramcore_adr_next_value1 <= 1'd0; end 2'd2: begin end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value1 <= litedramcore_wishbone_adr; - end + builder_interface1_dat_w_next_value_ce0 <= 1'd1; end endcase end always @(*) begin - litedramcore_adr_next_value_ce1 <= 1'd0; - case (litedramcore_state) + builder_interface1_adr_next_value1 <= 14'd0; + case (builder_state) 1'd1: begin - litedramcore_adr_next_value_ce1 <= 1'd1; + builder_interface1_adr_next_value1 <= 1'd0; end 2'd2: begin end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value_ce1 <= 1'd1; + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_adr_next_value1 <= builder_interface0_adr[29:0]; end end endcase end always @(*) begin - litedramcore_we_next_value2 <= 1'd0; - case (litedramcore_state) + builder_interface1_adr_next_value_ce1 <= 1'd0; + case (builder_state) 1'd1: begin - litedramcore_we_next_value2 <= 1'd0; + builder_interface1_adr_next_value_ce1 <= 1'd1; end 2'd2: begin end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_adr_next_value_ce1 <= 1'd1; end end endcase end always @(*) begin - litedramcore_we_next_value_ce2 <= 1'd0; - case (litedramcore_state) + builder_interface0_dat_r <= 32'd0; + case (builder_state) 1'd1: begin - litedramcore_we_next_value_ce2 <= 1'd1; end 2'd2: begin + builder_interface0_dat_r <= builder_interface1_dat_r; end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value_ce2 <= 1'd1; - end end endcase end -assign litedramcore_wishbone_adr = wb_bus_adr; -assign litedramcore_wishbone_dat_w = wb_bus_dat_w; -assign wb_bus_dat_r = litedramcore_wishbone_dat_r; -assign litedramcore_wishbone_sel = wb_bus_sel; -assign litedramcore_wishbone_cyc = wb_bus_cyc; -assign litedramcore_wishbone_stb = wb_bus_stb; -assign wb_bus_ack = litedramcore_wishbone_ack; -assign litedramcore_wishbone_we = wb_bus_we; -assign litedramcore_wishbone_cti = wb_bus_cti; -assign litedramcore_wishbone_bte = wb_bus_bte; -assign wb_bus_err = litedramcore_wishbone_err; -assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); -assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; +assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); +assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_done0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_re <= interface0_bank_bus_we; + builder_csrbank0_init_done0_re <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we; end end always @(*) begin - csrbank0_init_done0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_we <= (~interface0_bank_bus_we); + builder_csrbank0_init_done0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we); end end -assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; +assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_error0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_we <= (~interface0_bank_bus_we); + builder_csrbank0_init_error0_re <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; end end always @(*) begin - csrbank0_init_error0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_re <= interface0_bank_bus_we; + builder_csrbank0_init_error0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we); end end -assign csrbank0_init_done0_w = init_done_storage; -assign csrbank0_init_error0_w = init_error_storage; -assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); -assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0]; +assign builder_csrbank0_init_done0_w = main_init_done_storage; +assign builder_csrbank0_init_error0_w = main_init_error_storage; +assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1); +assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - csrbank1_rst0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_rst0_we <= (~interface1_bank_bus_we); + builder_csrbank1_rst0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - csrbank1_rst0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_rst0_re <= interface1_bank_bus_we; + builder_csrbank1_rst0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we); end end -assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[3:0]; +assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[3:0]; always @(*) begin - csrbank1_dly_sel0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dly_sel0_re <= interface1_bank_bus_we; + builder_csrbank1_dly_sel0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - csrbank1_dly_sel0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dly_sel0_we <= (~interface1_bank_bus_we); + builder_csrbank1_dly_sel0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; end end -assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; +assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0]; always @(*) begin - csrbank1_half_sys8x_taps0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we; + builder_csrbank1_half_sys8x_taps0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - csrbank1_half_sys8x_taps0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we); + builder_csrbank1_half_sys8x_taps0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we); end end -assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0]; +assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - csrbank1_wlevel_en0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we); + builder_csrbank1_wlevel_en0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - csrbank1_wlevel_en0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_wlevel_en0_re <= interface1_bank_bus_we; + builder_csrbank1_wlevel_en0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we; end end -assign k7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0]; +assign main_k7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_wlevel_strobe_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - k7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we; + main_k7ddrphy_wlevel_strobe_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + main_k7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we; end end always @(*) begin - k7ddrphy_wlevel_strobe_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - k7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we); + main_k7ddrphy_wlevel_strobe_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + main_k7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we); end end -assign k7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0]; +assign main_k7ddrphy_cdly_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_cdly_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - k7ddrphy_cdly_rst_we <= (~interface1_bank_bus_we); + main_k7ddrphy_cdly_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + main_k7ddrphy_cdly_rst_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - k7ddrphy_cdly_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - k7ddrphy_cdly_rst_re <= interface1_bank_bus_we; + main_k7ddrphy_cdly_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + main_k7ddrphy_cdly_rst_re <= builder_interface1_bank_bus_we; end end -assign k7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0]; +assign main_k7ddrphy_cdly_inc_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_cdly_inc_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - k7ddrphy_cdly_inc_we <= (~interface1_bank_bus_we); + main_k7ddrphy_cdly_inc_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_k7ddrphy_cdly_inc_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - k7ddrphy_cdly_inc_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - k7ddrphy_cdly_inc_re <= interface1_bank_bus_we; + main_k7ddrphy_cdly_inc_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_k7ddrphy_cdly_inc_re <= builder_interface1_bank_bus_we; end end -assign k7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; +assign main_k7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_rdly_dq_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - k7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we); + main_k7ddrphy_rdly_dq_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + main_k7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - k7ddrphy_rdly_dq_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - k7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we; + main_k7ddrphy_rdly_dq_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + main_k7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; end end -assign k7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; +assign main_k7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_rdly_dq_inc_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - k7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we); + main_k7ddrphy_rdly_dq_inc_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + main_k7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - k7ddrphy_rdly_dq_inc_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - k7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we; + main_k7ddrphy_rdly_dq_inc_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + main_k7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; end end -assign k7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; +assign main_k7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - k7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + main_k7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + main_k7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end end always @(*) begin - k7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - k7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + main_k7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + main_k7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); end end -assign k7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; +assign main_k7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_rdly_dq_bitslip_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - k7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we; + main_k7ddrphy_rdly_dq_bitslip_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + main_k7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end end always @(*) begin - k7ddrphy_rdly_dq_bitslip_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - k7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we); + main_k7ddrphy_rdly_dq_bitslip_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + main_k7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); end end -assign k7ddrphy_wdly_dq_rst_r = interface1_bank_bus_dat_w[0]; +assign main_k7ddrphy_wdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_wdly_dq_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - k7ddrphy_wdly_dq_rst_re <= interface1_bank_bus_we; + main_k7ddrphy_wdly_dq_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + main_k7ddrphy_wdly_dq_rst_re <= builder_interface1_bank_bus_we; end end always @(*) begin - k7ddrphy_wdly_dq_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - k7ddrphy_wdly_dq_rst_we <= (~interface1_bank_bus_we); + main_k7ddrphy_wdly_dq_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + main_k7ddrphy_wdly_dq_rst_we <= (~builder_interface1_bank_bus_we); end end -assign k7ddrphy_wdly_dq_inc_r = interface1_bank_bus_dat_w[0]; +assign main_k7ddrphy_wdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_wdly_dq_inc_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - k7ddrphy_wdly_dq_inc_re <= interface1_bank_bus_we; + main_k7ddrphy_wdly_dq_inc_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + main_k7ddrphy_wdly_dq_inc_re <= builder_interface1_bank_bus_we; end end always @(*) begin - k7ddrphy_wdly_dq_inc_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - k7ddrphy_wdly_dq_inc_we <= (~interface1_bank_bus_we); + main_k7ddrphy_wdly_dq_inc_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + main_k7ddrphy_wdly_dq_inc_we <= (~builder_interface1_bank_bus_we); end end -assign k7ddrphy_wdly_dqs_rst_r = interface1_bank_bus_dat_w[0]; +assign main_k7ddrphy_wdly_dqs_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_wdly_dqs_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin - k7ddrphy_wdly_dqs_rst_we <= (~interface1_bank_bus_we); + main_k7ddrphy_wdly_dqs_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin + main_k7ddrphy_wdly_dqs_rst_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - k7ddrphy_wdly_dqs_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin - k7ddrphy_wdly_dqs_rst_re <= interface1_bank_bus_we; + main_k7ddrphy_wdly_dqs_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin + main_k7ddrphy_wdly_dqs_rst_re <= builder_interface1_bank_bus_we; end end -assign k7ddrphy_wdly_dqs_inc_r = interface1_bank_bus_dat_w[0]; +assign main_k7ddrphy_wdly_dqs_inc_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_wdly_dqs_inc_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin - k7ddrphy_wdly_dqs_inc_we <= (~interface1_bank_bus_we); + main_k7ddrphy_wdly_dqs_inc_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin + main_k7ddrphy_wdly_dqs_inc_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - k7ddrphy_wdly_dqs_inc_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin - k7ddrphy_wdly_dqs_inc_re <= interface1_bank_bus_we; + main_k7ddrphy_wdly_dqs_inc_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin + main_k7ddrphy_wdly_dqs_inc_re <= builder_interface1_bank_bus_we; end end -assign k7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; +assign main_k7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin - k7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + main_k7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin + main_k7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - k7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin - k7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + main_k7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin + main_k7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end end -assign k7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; +assign main_k7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_wdly_dq_bitslip_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin - k7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we); + main_k7ddrphy_wdly_dq_bitslip_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin + main_k7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - k7ddrphy_wdly_dq_bitslip_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin - k7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we; + main_k7ddrphy_wdly_dq_bitslip_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin + main_k7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end end -assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0]; +assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_rdphase0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin - csrbank1_rdphase0_re <= interface1_bank_bus_we; + builder_csrbank1_rdphase0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - csrbank1_rdphase0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin - csrbank1_rdphase0_we <= (~interface1_bank_bus_we); + builder_csrbank1_rdphase0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; end end -assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0]; +assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_wrphase0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin - csrbank1_wrphase0_we <= (~interface1_bank_bus_we); + builder_csrbank1_wrphase0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - csrbank1_wrphase0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin - csrbank1_wrphase0_re <= interface1_bank_bus_we; + builder_csrbank1_wrphase0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we); end end -assign csrbank1_rst0_w = k7ddrphy_rst_storage; -assign csrbank1_dly_sel0_w = k7ddrphy_dly_sel_storage[3:0]; -assign csrbank1_half_sys8x_taps0_w = k7ddrphy_half_sys8x_taps_storage[4:0]; -assign csrbank1_wlevel_en0_w = k7ddrphy_wlevel_en_storage; -assign csrbank1_rdphase0_w = k7ddrphy_rdphase_storage[1:0]; -assign csrbank1_wrphase0_w = k7ddrphy_wrphase_storage[1:0]; -assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); -assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; +assign builder_csrbank1_rst0_w = main_k7ddrphy_rst_storage; +assign builder_csrbank1_dly_sel0_w = main_k7ddrphy_dly_sel_storage[3:0]; +assign builder_csrbank1_half_sys8x_taps0_w = main_k7ddrphy_half_sys8x_taps_storage[4:0]; +assign builder_csrbank1_wlevel_en0_w = main_k7ddrphy_wlevel_en_storage; +assign builder_csrbank1_rdphase0_w = main_k7ddrphy_rdphase_storage[1:0]; +assign builder_csrbank1_wrphase0_w = main_k7ddrphy_wrphase_storage[1:0]; +assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2); +assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0]; always @(*) begin - csrbank2_dfii_control0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_control0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_control0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_control0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; +assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi0_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi0_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we; end end -assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; +assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector0_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we); + main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; end end always @(*) begin - litedramcore_phaseinjector0_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we; + main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0]; +assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[14:0]; always @(*) begin - csrbank2_dfii_pi0_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi0_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi0_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi0_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_wrdata1_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi0_wrdata1_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_wrdata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin + builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi0_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin + builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_rddata1_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi0_rddata1_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank2_dfii_pi0_rddata1_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_rddata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin + builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi0_rddata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - csrbank2_dfii_pi0_rddata0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_rddata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin + builder_csrbank2_dfii_pi0_rddata0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; +assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi1_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi1_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we; end end -assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; +assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector1_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we; + main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin + main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - litedramcore_phaseinjector1_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we); + main_litedramcore_phaseinjector1_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin + main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0]; +assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[14:0]; always @(*) begin - csrbank2_dfii_pi1_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi1_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi1_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi1_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_wrdata1_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank2_dfii_pi1_wrdata1_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi1_wrdata1_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi1_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_rddata1_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + builder_csrbank2_dfii_pi1_rddata1_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi1_rddata1_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_rddata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi1_rddata0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi1_rddata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0]; +assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi2_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin - csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi2_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin - csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we); end end -assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; +assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector2_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin - litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we; + main_litedramcore_phaseinjector2_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we; end end always @(*) begin - litedramcore_phaseinjector2_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin - litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we); + main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[14:0]; +assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[14:0]; always @(*) begin - csrbank2_dfii_pi2_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin - csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi2_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin - csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi2_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin - csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi2_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin - csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi2_wrdata1_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi2_wrdata1_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin - csrbank2_dfii_pi2_wrdata1_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi2_wrdata1_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin - csrbank2_dfii_pi2_wrdata1_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi2_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin - csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi2_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin - csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi2_rddata1_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi2_rddata1_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin - csrbank2_dfii_pi2_rddata1_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_rddata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + builder_csrbank2_dfii_pi2_rddata1_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi2_rddata1_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin - csrbank2_dfii_pi2_rddata1_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_rddata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + builder_csrbank2_dfii_pi2_rddata1_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi2_rddata0_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi2_rddata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin - csrbank2_dfii_pi2_rddata0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi2_rddata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin - csrbank2_dfii_pi2_rddata0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi2_rddata0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0]; +assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi3_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd25))) begin - csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin + builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi3_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd25))) begin - csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin + builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we; end end -assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; +assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector3_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd26))) begin - litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we); + main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin + main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - litedramcore_phaseinjector3_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd26))) begin - litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we; + main_litedramcore_phaseinjector3_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin + main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[14:0]; +assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[14:0]; always @(*) begin - csrbank2_dfii_pi3_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd27))) begin - csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin + builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi3_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd27))) begin - csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin + builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi3_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd28))) begin - csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin + builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi3_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd28))) begin - csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin + builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi3_wrdata1_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi3_wrdata1_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd29))) begin - csrbank2_dfii_pi3_wrdata1_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin + builder_csrbank2_dfii_pi3_wrdata1_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi3_wrdata1_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd29))) begin - csrbank2_dfii_pi3_wrdata1_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin + builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi3_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd30))) begin - csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin + builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi3_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd30))) begin - csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin + builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi3_rddata1_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi3_rddata1_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd31))) begin - csrbank2_dfii_pi3_rddata1_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_rddata1_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin + builder_csrbank2_dfii_pi3_rddata1_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi3_rddata1_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd31))) begin - csrbank2_dfii_pi3_rddata1_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_rddata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin + builder_csrbank2_dfii_pi3_rddata1_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi3_rddata0_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi3_rddata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 6'd32))) begin - csrbank2_dfii_pi3_rddata0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin + builder_csrbank2_dfii_pi3_rddata0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi3_rddata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 6'd32))) begin - csrbank2_dfii_pi3_rddata0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin + builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we; end end -assign litedramcore_sel = litedramcore_storage[0]; -assign litedramcore_cke = litedramcore_storage[1]; -assign litedramcore_odt = litedramcore_storage[2]; -assign litedramcore_reset_n = litedramcore_storage[3]; -assign csrbank2_dfii_control0_w = litedramcore_storage[3:0]; -assign litedramcore_phaseinjector0_csrfield_cs = litedramcore_phaseinjector0_command_storage[0]; -assign litedramcore_phaseinjector0_csrfield_we = litedramcore_phaseinjector0_command_storage[1]; -assign litedramcore_phaseinjector0_csrfield_cas = litedramcore_phaseinjector0_command_storage[2]; -assign litedramcore_phaseinjector0_csrfield_ras = litedramcore_phaseinjector0_command_storage[3]; -assign litedramcore_phaseinjector0_csrfield_wren = litedramcore_phaseinjector0_command_storage[4]; -assign litedramcore_phaseinjector0_csrfield_rden = litedramcore_phaseinjector0_command_storage[5]; -assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; -assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0]; -assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0]; -assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[63:32]; -assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0]; -assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_rddata_status[63:32]; -assign csrbank2_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_rddata_status[31:0]; -assign litedramcore_phaseinjector0_rddata_we = csrbank2_dfii_pi0_rddata0_we; -assign litedramcore_phaseinjector1_csrfield_cs = litedramcore_phaseinjector1_command_storage[0]; -assign litedramcore_phaseinjector1_csrfield_we = litedramcore_phaseinjector1_command_storage[1]; -assign litedramcore_phaseinjector1_csrfield_cas = litedramcore_phaseinjector1_command_storage[2]; -assign litedramcore_phaseinjector1_csrfield_ras = litedramcore_phaseinjector1_command_storage[3]; -assign litedramcore_phaseinjector1_csrfield_wren = litedramcore_phaseinjector1_command_storage[4]; -assign litedramcore_phaseinjector1_csrfield_rden = litedramcore_phaseinjector1_command_storage[5]; -assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0]; -assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[14:0]; -assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0]; -assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[63:32]; -assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0]; -assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_rddata_status[63:32]; -assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_rddata_status[31:0]; -assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata0_we; -assign litedramcore_phaseinjector2_csrfield_cs = litedramcore_phaseinjector2_command_storage[0]; -assign litedramcore_phaseinjector2_csrfield_we = litedramcore_phaseinjector2_command_storage[1]; -assign litedramcore_phaseinjector2_csrfield_cas = litedramcore_phaseinjector2_command_storage[2]; -assign litedramcore_phaseinjector2_csrfield_ras = litedramcore_phaseinjector2_command_storage[3]; -assign litedramcore_phaseinjector2_csrfield_wren = litedramcore_phaseinjector2_command_storage[4]; -assign litedramcore_phaseinjector2_csrfield_rden = litedramcore_phaseinjector2_command_storage[5]; -assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0]; -assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[14:0]; -assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0]; -assign csrbank2_dfii_pi2_wrdata1_w = litedramcore_phaseinjector2_wrdata_storage[63:32]; -assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0]; -assign csrbank2_dfii_pi2_rddata1_w = litedramcore_phaseinjector2_rddata_status[63:32]; -assign csrbank2_dfii_pi2_rddata0_w = litedramcore_phaseinjector2_rddata_status[31:0]; -assign litedramcore_phaseinjector2_rddata_we = csrbank2_dfii_pi2_rddata0_we; -assign litedramcore_phaseinjector3_csrfield_cs = litedramcore_phaseinjector3_command_storage[0]; -assign litedramcore_phaseinjector3_csrfield_we = litedramcore_phaseinjector3_command_storage[1]; -assign litedramcore_phaseinjector3_csrfield_cas = litedramcore_phaseinjector3_command_storage[2]; -assign litedramcore_phaseinjector3_csrfield_ras = litedramcore_phaseinjector3_command_storage[3]; -assign litedramcore_phaseinjector3_csrfield_wren = litedramcore_phaseinjector3_command_storage[4]; -assign litedramcore_phaseinjector3_csrfield_rden = litedramcore_phaseinjector3_command_storage[5]; -assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0]; -assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[14:0]; -assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0]; -assign csrbank2_dfii_pi3_wrdata1_w = litedramcore_phaseinjector3_wrdata_storage[63:32]; -assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0]; -assign csrbank2_dfii_pi3_rddata1_w = litedramcore_phaseinjector3_rddata_status[63:32]; -assign csrbank2_dfii_pi3_rddata0_w = litedramcore_phaseinjector3_rddata_status[31:0]; -assign litedramcore_phaseinjector3_rddata_we = csrbank2_dfii_pi3_rddata0_we; -assign csr_interconnect_adr = litedramcore_adr; -assign csr_interconnect_we = litedramcore_we; -assign csr_interconnect_dat_w = litedramcore_dat_w; -assign litedramcore_dat_r = csr_interconnect_dat_r; -assign interface0_bank_bus_adr = csr_interconnect_adr; -assign interface1_bank_bus_adr = csr_interconnect_adr; -assign interface2_bank_bus_adr = csr_interconnect_adr; -assign interface0_bank_bus_we = csr_interconnect_we; -assign interface1_bank_bus_we = csr_interconnect_we; -assign interface2_bank_bus_we = csr_interconnect_we; -assign interface0_bank_bus_dat_w = csr_interconnect_dat_w; -assign interface1_bank_bus_dat_w = csr_interconnect_dat_w; -assign interface2_bank_bus_dat_w = csr_interconnect_dat_w; -assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); -always @(*) begin - rhs_array_muxed0 <= 1'd0; - case (litedramcore_choose_cmd_grant) +assign main_litedramcore_sel = main_litedramcore_storage[0]; +assign main_litedramcore_cke = main_litedramcore_storage[1]; +assign main_litedramcore_odt = main_litedramcore_storage[2]; +assign main_litedramcore_reset_n = main_litedramcore_storage[3]; +assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0]; +assign main_litedramcore_phaseinjector0_csrfield_cs = main_litedramcore_phaseinjector0_command_storage[0]; +assign main_litedramcore_phaseinjector0_csrfield_we = main_litedramcore_phaseinjector0_command_storage[1]; +assign main_litedramcore_phaseinjector0_csrfield_cas = main_litedramcore_phaseinjector0_command_storage[2]; +assign main_litedramcore_phaseinjector0_csrfield_ras = main_litedramcore_phaseinjector0_command_storage[3]; +assign main_litedramcore_phaseinjector0_csrfield_wren = main_litedramcore_phaseinjector0_command_storage[4]; +assign main_litedramcore_phaseinjector0_csrfield_rden = main_litedramcore_phaseinjector0_command_storage[5]; +assign main_litedramcore_phaseinjector0_csrfield_cs_top = main_litedramcore_phaseinjector0_command_storage[6]; +assign main_litedramcore_phaseinjector0_csrfield_cs_bottom = main_litedramcore_phaseinjector0_command_storage[7]; +assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[7:0]; +assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[14:0]; +assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi0_wrdata1_w = main_litedramcore_phaseinjector0_wrdata_storage[63:32]; +assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi0_rddata1_w = main_litedramcore_phaseinjector0_rddata_status[63:32]; +assign builder_csrbank2_dfii_pi0_rddata0_w = main_litedramcore_phaseinjector0_rddata_status[31:0]; +assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata0_we; +assign main_litedramcore_phaseinjector1_csrfield_cs = main_litedramcore_phaseinjector1_command_storage[0]; +assign main_litedramcore_phaseinjector1_csrfield_we = main_litedramcore_phaseinjector1_command_storage[1]; +assign main_litedramcore_phaseinjector1_csrfield_cas = main_litedramcore_phaseinjector1_command_storage[2]; +assign main_litedramcore_phaseinjector1_csrfield_ras = main_litedramcore_phaseinjector1_command_storage[3]; +assign main_litedramcore_phaseinjector1_csrfield_wren = main_litedramcore_phaseinjector1_command_storage[4]; +assign main_litedramcore_phaseinjector1_csrfield_rden = main_litedramcore_phaseinjector1_command_storage[5]; +assign main_litedramcore_phaseinjector1_csrfield_cs_top = main_litedramcore_phaseinjector1_command_storage[6]; +assign main_litedramcore_phaseinjector1_csrfield_cs_bottom = main_litedramcore_phaseinjector1_command_storage[7]; +assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[7:0]; +assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[14:0]; +assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi1_wrdata1_w = main_litedramcore_phaseinjector1_wrdata_storage[63:32]; +assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi1_rddata1_w = main_litedramcore_phaseinjector1_rddata_status[63:32]; +assign builder_csrbank2_dfii_pi1_rddata0_w = main_litedramcore_phaseinjector1_rddata_status[31:0]; +assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata0_we; +assign main_litedramcore_phaseinjector2_csrfield_cs = main_litedramcore_phaseinjector2_command_storage[0]; +assign main_litedramcore_phaseinjector2_csrfield_we = main_litedramcore_phaseinjector2_command_storage[1]; +assign main_litedramcore_phaseinjector2_csrfield_cas = main_litedramcore_phaseinjector2_command_storage[2]; +assign main_litedramcore_phaseinjector2_csrfield_ras = main_litedramcore_phaseinjector2_command_storage[3]; +assign main_litedramcore_phaseinjector2_csrfield_wren = main_litedramcore_phaseinjector2_command_storage[4]; +assign main_litedramcore_phaseinjector2_csrfield_rden = main_litedramcore_phaseinjector2_command_storage[5]; +assign main_litedramcore_phaseinjector2_csrfield_cs_top = main_litedramcore_phaseinjector2_command_storage[6]; +assign main_litedramcore_phaseinjector2_csrfield_cs_bottom = main_litedramcore_phaseinjector2_command_storage[7]; +assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[7:0]; +assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[14:0]; +assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi2_wrdata1_w = main_litedramcore_phaseinjector2_wrdata_storage[63:32]; +assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi2_rddata1_w = main_litedramcore_phaseinjector2_rddata_status[63:32]; +assign builder_csrbank2_dfii_pi2_rddata0_w = main_litedramcore_phaseinjector2_rddata_status[31:0]; +assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata0_we; +assign main_litedramcore_phaseinjector3_csrfield_cs = main_litedramcore_phaseinjector3_command_storage[0]; +assign main_litedramcore_phaseinjector3_csrfield_we = main_litedramcore_phaseinjector3_command_storage[1]; +assign main_litedramcore_phaseinjector3_csrfield_cas = main_litedramcore_phaseinjector3_command_storage[2]; +assign main_litedramcore_phaseinjector3_csrfield_ras = main_litedramcore_phaseinjector3_command_storage[3]; +assign main_litedramcore_phaseinjector3_csrfield_wren = main_litedramcore_phaseinjector3_command_storage[4]; +assign main_litedramcore_phaseinjector3_csrfield_rden = main_litedramcore_phaseinjector3_command_storage[5]; +assign main_litedramcore_phaseinjector3_csrfield_cs_top = main_litedramcore_phaseinjector3_command_storage[6]; +assign main_litedramcore_phaseinjector3_csrfield_cs_bottom = main_litedramcore_phaseinjector3_command_storage[7]; +assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[7:0]; +assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[14:0]; +assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi3_wrdata1_w = main_litedramcore_phaseinjector3_wrdata_storage[63:32]; +assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi3_rddata1_w = main_litedramcore_phaseinjector3_rddata_status[63:32]; +assign builder_csrbank2_dfii_pi3_rddata0_w = main_litedramcore_phaseinjector3_rddata_status[31:0]; +assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata0_we; +assign builder_adr = builder_interface1_adr; +assign builder_we = builder_interface1_we; +assign builder_dat_w = builder_interface1_dat_w; +assign builder_interface1_dat_r = builder_dat_r; +assign builder_interface0_bank_bus_adr = builder_adr; +assign builder_interface1_bank_bus_adr = builder_adr; +assign builder_interface2_bank_bus_adr = builder_adr; +assign builder_interface0_bank_bus_we = builder_we; +assign builder_interface1_bank_bus_we = builder_we; +assign builder_interface2_bank_bus_we = builder_we; +assign builder_interface0_bank_bus_dat_w = builder_dat_w; +assign builder_interface1_bank_bus_dat_w = builder_dat_w; +assign builder_interface2_bank_bus_dat_w = builder_dat_w; +assign builder_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); +always @(*) begin + builder_rhs_self0 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[0]; end 1'd1: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[1]; end 2'd2: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[2]; end 2'd3: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[3]; end 3'd4: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[4]; end 3'd5: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[5]; end 3'd6: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[6]; end default: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[7]; end endcase end always @(*) begin - rhs_array_muxed1 <= 15'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self1 <= 15'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine6_cmd_payload_a; end default: begin - rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase end always @(*) begin - rhs_array_muxed2 <= 3'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self2 <= 3'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine6_cmd_payload_ba; end default: begin - rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase end always @(*) begin - rhs_array_muxed3 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self3 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase end always @(*) begin - rhs_array_muxed4 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self4 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase end always @(*) begin - rhs_array_muxed5 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self5 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase end always @(*) begin - t_array_muxed0 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_t_self0 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine6_cmd_payload_cas; end default: begin - t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase end always @(*) begin - t_array_muxed1 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_t_self1 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine6_cmd_payload_ras; end default: begin - t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase end always @(*) begin - t_array_muxed2 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_t_self2 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine6_cmd_payload_we; end default: begin - t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed6 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self6 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[0]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[0]; end 1'd1: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[1]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[1]; end 2'd2: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[2]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[2]; end 2'd3: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[3]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[3]; end 3'd4: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[4]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[4]; end 3'd5: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[5]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[5]; end 3'd6: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[6]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[6]; end default: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[7]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[7]; end endcase end always @(*) begin - rhs_array_muxed7 <= 15'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self7 <= 15'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine6_cmd_payload_a; end default: begin - rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase end always @(*) begin - rhs_array_muxed8 <= 3'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self8 <= 3'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine6_cmd_payload_ba; end default: begin - rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase end always @(*) begin - rhs_array_muxed9 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self9 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase end always @(*) begin - rhs_array_muxed10 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self10 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase end always @(*) begin - rhs_array_muxed11 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self11 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase end always @(*) begin - t_array_muxed3 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_t_self3 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine6_cmd_payload_cas; end default: begin - t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase end always @(*) begin - t_array_muxed4 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_t_self4 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine6_cmd_payload_ras; end default: begin - t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase end always @(*) begin - t_array_muxed5 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_t_self5 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine6_cmd_payload_we; end default: begin - t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed12 <= 22'd0; - case (litedramcore_roundrobin0_grant) + builder_rhs_self12 <= 22'd0; + case (builder_roundrobin0_grant) default: begin - rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self12 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed13 <= 1'd0; - case (litedramcore_roundrobin0_grant) + builder_rhs_self13 <= 1'd0; + case (builder_roundrobin0_grant) default: begin - rhs_array_muxed13 <= user_port_cmd_payload_we; + builder_rhs_self13 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed14 <= 1'd0; - case (litedramcore_roundrobin0_grant) + builder_rhs_self14 <= 1'd0; + case (builder_roundrobin0_grant) default: begin - rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed15 <= 22'd0; - case (litedramcore_roundrobin1_grant) + builder_rhs_self15 <= 22'd0; + case (builder_roundrobin1_grant) default: begin - rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self15 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed16 <= 1'd0; - case (litedramcore_roundrobin1_grant) + builder_rhs_self16 <= 1'd0; + case (builder_roundrobin1_grant) default: begin - rhs_array_muxed16 <= user_port_cmd_payload_we; + builder_rhs_self16 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed17 <= 1'd0; - case (litedramcore_roundrobin1_grant) + builder_rhs_self17 <= 1'd0; + case (builder_roundrobin1_grant) default: begin - rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed18 <= 22'd0; - case (litedramcore_roundrobin2_grant) + builder_rhs_self18 <= 22'd0; + case (builder_roundrobin2_grant) default: begin - rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self18 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed19 <= 1'd0; - case (litedramcore_roundrobin2_grant) + builder_rhs_self19 <= 1'd0; + case (builder_roundrobin2_grant) default: begin - rhs_array_muxed19 <= user_port_cmd_payload_we; + builder_rhs_self19 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed20 <= 1'd0; - case (litedramcore_roundrobin2_grant) + builder_rhs_self20 <= 1'd0; + case (builder_roundrobin2_grant) default: begin - rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed21 <= 22'd0; - case (litedramcore_roundrobin3_grant) + builder_rhs_self21 <= 22'd0; + case (builder_roundrobin3_grant) default: begin - rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self21 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed22 <= 1'd0; - case (litedramcore_roundrobin3_grant) + builder_rhs_self22 <= 1'd0; + case (builder_roundrobin3_grant) default: begin - rhs_array_muxed22 <= user_port_cmd_payload_we; + builder_rhs_self22 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed23 <= 1'd0; - case (litedramcore_roundrobin3_grant) + builder_rhs_self23 <= 1'd0; + case (builder_roundrobin3_grant) default: begin - rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed24 <= 22'd0; - case (litedramcore_roundrobin4_grant) + builder_rhs_self24 <= 22'd0; + case (builder_roundrobin4_grant) default: begin - rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self24 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed25 <= 1'd0; - case (litedramcore_roundrobin4_grant) + builder_rhs_self25 <= 1'd0; + case (builder_roundrobin4_grant) default: begin - rhs_array_muxed25 <= user_port_cmd_payload_we; + builder_rhs_self25 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed26 <= 1'd0; - case (litedramcore_roundrobin4_grant) + builder_rhs_self26 <= 1'd0; + case (builder_roundrobin4_grant) default: begin - rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed27 <= 22'd0; - case (litedramcore_roundrobin5_grant) + builder_rhs_self27 <= 22'd0; + case (builder_roundrobin5_grant) default: begin - rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self27 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed28 <= 1'd0; - case (litedramcore_roundrobin5_grant) + builder_rhs_self28 <= 1'd0; + case (builder_roundrobin5_grant) default: begin - rhs_array_muxed28 <= user_port_cmd_payload_we; + builder_rhs_self28 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed29 <= 1'd0; - case (litedramcore_roundrobin5_grant) + builder_rhs_self29 <= 1'd0; + case (builder_roundrobin5_grant) default: begin - rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed30 <= 22'd0; - case (litedramcore_roundrobin6_grant) + builder_rhs_self30 <= 22'd0; + case (builder_roundrobin6_grant) default: begin - rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self30 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed31 <= 1'd0; - case (litedramcore_roundrobin6_grant) + builder_rhs_self31 <= 1'd0; + case (builder_roundrobin6_grant) default: begin - rhs_array_muxed31 <= user_port_cmd_payload_we; + builder_rhs_self31 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed32 <= 1'd0; - case (litedramcore_roundrobin6_grant) + builder_rhs_self32 <= 1'd0; + case (builder_roundrobin6_grant) default: begin - rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed33 <= 22'd0; - case (litedramcore_roundrobin7_grant) + builder_rhs_self33 <= 22'd0; + case (builder_roundrobin7_grant) default: begin - rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self33 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed34 <= 1'd0; - case (litedramcore_roundrobin7_grant) + builder_rhs_self34 <= 1'd0; + case (builder_roundrobin7_grant) default: begin - rhs_array_muxed34 <= user_port_cmd_payload_we; + builder_rhs_self34 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed35 <= 1'd0; - case (litedramcore_roundrobin7_grant) + builder_rhs_self35 <= 1'd0; + case (builder_roundrobin7_grant) default: begin - rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - array_muxed0 <= 3'd0; - case (litedramcore_steerer_sel0) + builder_self0 <= 3'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed0 <= litedramcore_nop_ba[2:0]; + builder_self0 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed0 <= litedramcore_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed1 <= 15'd0; - case (litedramcore_steerer_sel0) + builder_self1 <= 15'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed1 <= litedramcore_nop_a; + builder_self1 <= main_litedramcore_nop_a; end 1'd1: begin - array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a; + builder_self1 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed1 <= litedramcore_choose_req_cmd_payload_a; + builder_self1 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed1 <= litedramcore_cmd_payload_a; + builder_self1 <= main_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed2 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self2 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed2 <= 1'd0; + builder_self2 <= 1'd0; end 1'd1: begin - array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + builder_self2 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + builder_self2 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + builder_self2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed3 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self3 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed3 <= 1'd0; + builder_self3 <= 1'd0; end 1'd1: begin - array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + builder_self3 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + builder_self3 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + builder_self3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed4 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self4 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed4 <= 1'd0; + builder_self4 <= 1'd0; end 1'd1: begin - array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + builder_self4 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + builder_self4 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + builder_self4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed5 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self5 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed5 <= 1'd0; + builder_self5 <= 1'd0; end 1'd1: begin - array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + builder_self5 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + builder_self5 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + builder_self5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed6 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self6 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed6 <= 1'd0; + builder_self6 <= 1'd0; end 1'd1: begin - array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + builder_self6 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + builder_self6 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + builder_self6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase end always @(*) begin - array_muxed7 <= 3'd0; - case (litedramcore_steerer_sel1) + builder_self7 <= 3'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed7 <= litedramcore_nop_ba[2:0]; + builder_self7 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed7 <= litedramcore_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed8 <= 15'd0; - case (litedramcore_steerer_sel1) + builder_self8 <= 15'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed8 <= litedramcore_nop_a; + builder_self8 <= main_litedramcore_nop_a; end 1'd1: begin - array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a; + builder_self8 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed8 <= litedramcore_choose_req_cmd_payload_a; + builder_self8 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed8 <= litedramcore_cmd_payload_a; + builder_self8 <= main_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed9 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self9 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed9 <= 1'd0; + builder_self9 <= 1'd0; end 1'd1: begin - array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + builder_self9 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + builder_self9 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + builder_self9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed10 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self10 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed10 <= 1'd0; + builder_self10 <= 1'd0; end 1'd1: begin - array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + builder_self10 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + builder_self10 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + builder_self10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed11 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self11 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed11 <= 1'd0; + builder_self11 <= 1'd0; end 1'd1: begin - array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + builder_self11 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + builder_self11 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + builder_self11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed12 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self12 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed12 <= 1'd0; + builder_self12 <= 1'd0; end 1'd1: begin - array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + builder_self12 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + builder_self12 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + builder_self12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed13 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self13 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed13 <= 1'd0; + builder_self13 <= 1'd0; end 1'd1: begin - array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + builder_self13 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + builder_self13 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + builder_self13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase end always @(*) begin - array_muxed14 <= 3'd0; - case (litedramcore_steerer_sel2) + builder_self14 <= 3'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed14 <= litedramcore_nop_ba[2:0]; + builder_self14 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed14 <= litedramcore_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed15 <= 15'd0; - case (litedramcore_steerer_sel2) + builder_self15 <= 15'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed15 <= litedramcore_nop_a; + builder_self15 <= main_litedramcore_nop_a; end 1'd1: begin - array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a; + builder_self15 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed15 <= litedramcore_choose_req_cmd_payload_a; + builder_self15 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed15 <= litedramcore_cmd_payload_a; + builder_self15 <= main_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed16 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self16 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed16 <= 1'd0; + builder_self16 <= 1'd0; end 1'd1: begin - array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + builder_self16 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + builder_self16 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + builder_self16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed17 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self17 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed17 <= 1'd0; + builder_self17 <= 1'd0; end 1'd1: begin - array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + builder_self17 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + builder_self17 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + builder_self17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed18 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self18 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed18 <= 1'd0; + builder_self18 <= 1'd0; end 1'd1: begin - array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + builder_self18 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + builder_self18 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + builder_self18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed19 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self19 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed19 <= 1'd0; + builder_self19 <= 1'd0; end 1'd1: begin - array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + builder_self19 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + builder_self19 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + builder_self19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed20 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self20 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed20 <= 1'd0; + builder_self20 <= 1'd0; end 1'd1: begin - array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + builder_self20 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + builder_self20 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + builder_self20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase end always @(*) begin - array_muxed21 <= 3'd0; - case (litedramcore_steerer_sel3) + builder_self21 <= 3'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed21 <= litedramcore_nop_ba[2:0]; + builder_self21 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed21 <= litedramcore_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed22 <= 15'd0; - case (litedramcore_steerer_sel3) + builder_self22 <= 15'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed22 <= litedramcore_nop_a; + builder_self22 <= main_litedramcore_nop_a; end 1'd1: begin - array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a; + builder_self22 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed22 <= litedramcore_choose_req_cmd_payload_a; + builder_self22 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed22 <= litedramcore_cmd_payload_a; + builder_self22 <= main_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed23 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self23 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed23 <= 1'd0; + builder_self23 <= 1'd0; end 1'd1: begin - array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + builder_self23 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + builder_self23 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + builder_self23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed24 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self24 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed24 <= 1'd0; + builder_self24 <= 1'd0; end 1'd1: begin - array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + builder_self24 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + builder_self24 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + builder_self24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed25 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self25 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed25 <= 1'd0; + builder_self25 <= 1'd0; end 1'd1: begin - array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + builder_self25 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + builder_self25 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + builder_self25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed26 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self26 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed26 <= 1'd0; + builder_self26 <= 1'd0; end 1'd1: begin - array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + builder_self26 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + builder_self26 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + builder_self26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed27 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self27 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed27 <= 1'd0; + builder_self27 <= 1'd0; end 1'd1: begin - array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + builder_self27 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + builder_self27 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + builder_self27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase end -assign xilinxasyncresetsynchronizerimpl0 = (~locked); -assign xilinxasyncresetsynchronizerimpl1 = (~locked); -assign xilinxasyncresetsynchronizerimpl2 = (~locked); -assign xilinxasyncresetsynchronizerimpl3 = (~locked); +assign builder_xilinxasyncresetsynchronizerimpl0_async_reset = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl1_async_reset = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl2_async_reset = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl3_async_reset = (~main_locked); //------------------------------------------------------------------------------ @@ -13660,1295 +14248,1295 @@ assign xilinxasyncresetsynchronizerimpl3 = (~locked); //------------------------------------------------------------------------------ always @(posedge iodelay_clk) begin - if ((reset_counter != 1'd0)) begin - reset_counter <= (reset_counter - 1'd1); + if ((main_reset_counter != 1'd0)) begin + main_reset_counter <= (main_reset_counter - 1'd1); end else begin - ic_reset <= 1'd0; + main_ic_reset <= 1'd0; end if (iodelay_rst) begin - reset_counter <= 4'd15; - ic_reset <= 1'd1; + main_reset_counter <= 4'd15; + main_ic_reset <= 1'd1; end end always @(posedge sys_clk) begin - k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= k7ddrphy_dqs_oe_delay_tappeddelayline; - k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip0_value0 <= (k7ddrphy_bitslip0_value0 + 1'd1); + main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= main_k7ddrphy_dqs_oe_delay_tappeddelayline; + main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip0_value0 <= (main_k7ddrphy_bitslip0_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip0_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip0_value0 <= 3'd7; end - k7ddrphy_bitslip0_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip0_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip1_value0 <= (k7ddrphy_bitslip1_value0 + 1'd1); + main_k7ddrphy_bitslip0_r0 <= {main_k7ddrphy_dqspattern_o, main_k7ddrphy_bitslip0_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip1_value0 <= (main_k7ddrphy_bitslip1_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip1_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip1_value0 <= 3'd7; end - k7ddrphy_bitslip1_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip1_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip2_value0 <= (k7ddrphy_bitslip2_value0 + 1'd1); + main_k7ddrphy_bitslip1_r0 <= {main_k7ddrphy_dqspattern_o, main_k7ddrphy_bitslip1_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip2_value0 <= (main_k7ddrphy_bitslip2_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip2_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip2_value0 <= 3'd7; end - k7ddrphy_bitslip2_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip2_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip3_value0 <= (k7ddrphy_bitslip3_value0 + 1'd1); + main_k7ddrphy_bitslip2_r0 <= {main_k7ddrphy_dqspattern_o, main_k7ddrphy_bitslip2_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip3_value0 <= (main_k7ddrphy_bitslip3_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip3_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip3_value0 <= 3'd7; end - k7ddrphy_bitslip3_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip3_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip0_value1 <= (k7ddrphy_bitslip0_value1 + 1'd1); + main_k7ddrphy_bitslip3_r0 <= {main_k7ddrphy_dqspattern_o, main_k7ddrphy_bitslip3_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip0_value1 <= (main_k7ddrphy_bitslip0_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip0_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip0_value1 <= 3'd7; end - k7ddrphy_bitslip0_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[4], k7ddrphy_dfi_p3_wrdata_mask[0], k7ddrphy_dfi_p2_wrdata_mask[4], k7ddrphy_dfi_p2_wrdata_mask[0], k7ddrphy_dfi_p1_wrdata_mask[4], k7ddrphy_dfi_p1_wrdata_mask[0], k7ddrphy_dfi_p0_wrdata_mask[4], k7ddrphy_dfi_p0_wrdata_mask[0]}, k7ddrphy_bitslip0_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip1_value1 <= (k7ddrphy_bitslip1_value1 + 1'd1); + main_k7ddrphy_bitslip0_r1 <= {{main_k7ddrphy_dfi_p3_wrdata_mask[4], main_k7ddrphy_dfi_p3_wrdata_mask[0], main_k7ddrphy_dfi_p2_wrdata_mask[4], main_k7ddrphy_dfi_p2_wrdata_mask[0], main_k7ddrphy_dfi_p1_wrdata_mask[4], main_k7ddrphy_dfi_p1_wrdata_mask[0], main_k7ddrphy_dfi_p0_wrdata_mask[4], main_k7ddrphy_dfi_p0_wrdata_mask[0]}, main_k7ddrphy_bitslip0_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip1_value1 <= (main_k7ddrphy_bitslip1_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip1_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip1_value1 <= 3'd7; end - k7ddrphy_bitslip1_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[5], k7ddrphy_dfi_p3_wrdata_mask[1], k7ddrphy_dfi_p2_wrdata_mask[5], k7ddrphy_dfi_p2_wrdata_mask[1], k7ddrphy_dfi_p1_wrdata_mask[5], k7ddrphy_dfi_p1_wrdata_mask[1], k7ddrphy_dfi_p0_wrdata_mask[5], k7ddrphy_dfi_p0_wrdata_mask[1]}, k7ddrphy_bitslip1_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip2_value1 <= (k7ddrphy_bitslip2_value1 + 1'd1); + main_k7ddrphy_bitslip1_r1 <= {{main_k7ddrphy_dfi_p3_wrdata_mask[5], main_k7ddrphy_dfi_p3_wrdata_mask[1], main_k7ddrphy_dfi_p2_wrdata_mask[5], main_k7ddrphy_dfi_p2_wrdata_mask[1], main_k7ddrphy_dfi_p1_wrdata_mask[5], main_k7ddrphy_dfi_p1_wrdata_mask[1], main_k7ddrphy_dfi_p0_wrdata_mask[5], main_k7ddrphy_dfi_p0_wrdata_mask[1]}, main_k7ddrphy_bitslip1_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip2_value1 <= (main_k7ddrphy_bitslip2_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip2_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip2_value1 <= 3'd7; end - k7ddrphy_bitslip2_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[6], k7ddrphy_dfi_p3_wrdata_mask[2], k7ddrphy_dfi_p2_wrdata_mask[6], k7ddrphy_dfi_p2_wrdata_mask[2], k7ddrphy_dfi_p1_wrdata_mask[6], k7ddrphy_dfi_p1_wrdata_mask[2], k7ddrphy_dfi_p0_wrdata_mask[6], k7ddrphy_dfi_p0_wrdata_mask[2]}, k7ddrphy_bitslip2_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip3_value1 <= (k7ddrphy_bitslip3_value1 + 1'd1); + main_k7ddrphy_bitslip2_r1 <= {{main_k7ddrphy_dfi_p3_wrdata_mask[6], main_k7ddrphy_dfi_p3_wrdata_mask[2], main_k7ddrphy_dfi_p2_wrdata_mask[6], main_k7ddrphy_dfi_p2_wrdata_mask[2], main_k7ddrphy_dfi_p1_wrdata_mask[6], main_k7ddrphy_dfi_p1_wrdata_mask[2], main_k7ddrphy_dfi_p0_wrdata_mask[6], main_k7ddrphy_dfi_p0_wrdata_mask[2]}, main_k7ddrphy_bitslip2_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip3_value1 <= (main_k7ddrphy_bitslip3_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip3_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip3_value1 <= 3'd7; end - k7ddrphy_bitslip3_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[7], k7ddrphy_dfi_p3_wrdata_mask[3], k7ddrphy_dfi_p2_wrdata_mask[7], k7ddrphy_dfi_p2_wrdata_mask[3], k7ddrphy_dfi_p1_wrdata_mask[7], k7ddrphy_dfi_p1_wrdata_mask[3], k7ddrphy_dfi_p0_wrdata_mask[7], k7ddrphy_dfi_p0_wrdata_mask[3]}, k7ddrphy_bitslip3_r1[15:8]}; - k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= k7ddrphy_dq_oe_delay_tappeddelayline; - k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip0_value2 <= (k7ddrphy_bitslip0_value2 + 1'd1); + main_k7ddrphy_bitslip3_r1 <= {{main_k7ddrphy_dfi_p3_wrdata_mask[7], main_k7ddrphy_dfi_p3_wrdata_mask[3], main_k7ddrphy_dfi_p2_wrdata_mask[7], main_k7ddrphy_dfi_p2_wrdata_mask[3], main_k7ddrphy_dfi_p1_wrdata_mask[7], main_k7ddrphy_dfi_p1_wrdata_mask[3], main_k7ddrphy_dfi_p0_wrdata_mask[7], main_k7ddrphy_dfi_p0_wrdata_mask[3]}, main_k7ddrphy_bitslip3_r1[15:8]}; + main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= main_k7ddrphy_dq_oe_delay_tappeddelayline; + main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip0_value2 <= (main_k7ddrphy_bitslip0_value2 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip0_value2 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip0_value2 <= 3'd7; end - k7ddrphy_bitslip0_r2 <= {{k7ddrphy_dfi_p3_wrdata[32], k7ddrphy_dfi_p3_wrdata[0], k7ddrphy_dfi_p2_wrdata[32], k7ddrphy_dfi_p2_wrdata[0], k7ddrphy_dfi_p1_wrdata[32], k7ddrphy_dfi_p1_wrdata[0], k7ddrphy_dfi_p0_wrdata[32], k7ddrphy_dfi_p0_wrdata[0]}, k7ddrphy_bitslip0_r2[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip0_value3 <= (k7ddrphy_bitslip0_value3 + 1'd1); + main_k7ddrphy_bitslip0_r2 <= {{main_k7ddrphy_dfi_p3_wrdata[32], main_k7ddrphy_dfi_p3_wrdata[0], main_k7ddrphy_dfi_p2_wrdata[32], main_k7ddrphy_dfi_p2_wrdata[0], main_k7ddrphy_dfi_p1_wrdata[32], main_k7ddrphy_dfi_p1_wrdata[0], main_k7ddrphy_dfi_p0_wrdata[32], main_k7ddrphy_dfi_p0_wrdata[0]}, main_k7ddrphy_bitslip0_r2[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip0_value3 <= (main_k7ddrphy_bitslip0_value3 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip0_value3 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip0_value3 <= 3'd7; end - k7ddrphy_bitslip0_r3 <= {k7ddrphy_bitslip03, k7ddrphy_bitslip0_r3[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip1_value2 <= (k7ddrphy_bitslip1_value2 + 1'd1); + main_k7ddrphy_bitslip0_r3 <= {main_k7ddrphy_bitslip03, main_k7ddrphy_bitslip0_r3[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip1_value2 <= (main_k7ddrphy_bitslip1_value2 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip1_value2 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip1_value2 <= 3'd7; end - k7ddrphy_bitslip1_r2 <= {{k7ddrphy_dfi_p3_wrdata[33], k7ddrphy_dfi_p3_wrdata[1], k7ddrphy_dfi_p2_wrdata[33], k7ddrphy_dfi_p2_wrdata[1], k7ddrphy_dfi_p1_wrdata[33], k7ddrphy_dfi_p1_wrdata[1], k7ddrphy_dfi_p0_wrdata[33], k7ddrphy_dfi_p0_wrdata[1]}, k7ddrphy_bitslip1_r2[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip1_value3 <= (k7ddrphy_bitslip1_value3 + 1'd1); + main_k7ddrphy_bitslip1_r2 <= {{main_k7ddrphy_dfi_p3_wrdata[33], main_k7ddrphy_dfi_p3_wrdata[1], main_k7ddrphy_dfi_p2_wrdata[33], main_k7ddrphy_dfi_p2_wrdata[1], main_k7ddrphy_dfi_p1_wrdata[33], main_k7ddrphy_dfi_p1_wrdata[1], main_k7ddrphy_dfi_p0_wrdata[33], main_k7ddrphy_dfi_p0_wrdata[1]}, main_k7ddrphy_bitslip1_r2[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip1_value3 <= (main_k7ddrphy_bitslip1_value3 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip1_value3 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip1_value3 <= 3'd7; end - k7ddrphy_bitslip1_r3 <= {k7ddrphy_bitslip13, k7ddrphy_bitslip1_r3[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip2_value2 <= (k7ddrphy_bitslip2_value2 + 1'd1); + main_k7ddrphy_bitslip1_r3 <= {main_k7ddrphy_bitslip13, main_k7ddrphy_bitslip1_r3[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip2_value2 <= (main_k7ddrphy_bitslip2_value2 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip2_value2 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip2_value2 <= 3'd7; end - k7ddrphy_bitslip2_r2 <= {{k7ddrphy_dfi_p3_wrdata[34], k7ddrphy_dfi_p3_wrdata[2], k7ddrphy_dfi_p2_wrdata[34], k7ddrphy_dfi_p2_wrdata[2], k7ddrphy_dfi_p1_wrdata[34], k7ddrphy_dfi_p1_wrdata[2], k7ddrphy_dfi_p0_wrdata[34], k7ddrphy_dfi_p0_wrdata[2]}, k7ddrphy_bitslip2_r2[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip2_value3 <= (k7ddrphy_bitslip2_value3 + 1'd1); + main_k7ddrphy_bitslip2_r2 <= {{main_k7ddrphy_dfi_p3_wrdata[34], main_k7ddrphy_dfi_p3_wrdata[2], main_k7ddrphy_dfi_p2_wrdata[34], main_k7ddrphy_dfi_p2_wrdata[2], main_k7ddrphy_dfi_p1_wrdata[34], main_k7ddrphy_dfi_p1_wrdata[2], main_k7ddrphy_dfi_p0_wrdata[34], main_k7ddrphy_dfi_p0_wrdata[2]}, main_k7ddrphy_bitslip2_r2[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip2_value3 <= (main_k7ddrphy_bitslip2_value3 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip2_value3 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip2_value3 <= 3'd7; end - k7ddrphy_bitslip2_r3 <= {k7ddrphy_bitslip23, k7ddrphy_bitslip2_r3[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip3_value2 <= (k7ddrphy_bitslip3_value2 + 1'd1); + main_k7ddrphy_bitslip2_r3 <= {main_k7ddrphy_bitslip23, main_k7ddrphy_bitslip2_r3[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip3_value2 <= (main_k7ddrphy_bitslip3_value2 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip3_value2 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip3_value2 <= 3'd7; end - k7ddrphy_bitslip3_r2 <= {{k7ddrphy_dfi_p3_wrdata[35], k7ddrphy_dfi_p3_wrdata[3], k7ddrphy_dfi_p2_wrdata[35], k7ddrphy_dfi_p2_wrdata[3], k7ddrphy_dfi_p1_wrdata[35], k7ddrphy_dfi_p1_wrdata[3], k7ddrphy_dfi_p0_wrdata[35], k7ddrphy_dfi_p0_wrdata[3]}, k7ddrphy_bitslip3_r2[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip3_value3 <= (k7ddrphy_bitslip3_value3 + 1'd1); + main_k7ddrphy_bitslip3_r2 <= {{main_k7ddrphy_dfi_p3_wrdata[35], main_k7ddrphy_dfi_p3_wrdata[3], main_k7ddrphy_dfi_p2_wrdata[35], main_k7ddrphy_dfi_p2_wrdata[3], main_k7ddrphy_dfi_p1_wrdata[35], main_k7ddrphy_dfi_p1_wrdata[3], main_k7ddrphy_dfi_p0_wrdata[35], main_k7ddrphy_dfi_p0_wrdata[3]}, main_k7ddrphy_bitslip3_r2[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip3_value3 <= (main_k7ddrphy_bitslip3_value3 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip3_value3 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip3_value3 <= 3'd7; end - k7ddrphy_bitslip3_r3 <= {k7ddrphy_bitslip33, k7ddrphy_bitslip3_r3[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip4_value0 <= (k7ddrphy_bitslip4_value0 + 1'd1); + main_k7ddrphy_bitslip3_r3 <= {main_k7ddrphy_bitslip33, main_k7ddrphy_bitslip3_r3[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip4_value0 <= (main_k7ddrphy_bitslip4_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip4_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip4_value0 <= 3'd7; end - k7ddrphy_bitslip4_r0 <= {{k7ddrphy_dfi_p3_wrdata[36], k7ddrphy_dfi_p3_wrdata[4], k7ddrphy_dfi_p2_wrdata[36], k7ddrphy_dfi_p2_wrdata[4], k7ddrphy_dfi_p1_wrdata[36], k7ddrphy_dfi_p1_wrdata[4], k7ddrphy_dfi_p0_wrdata[36], k7ddrphy_dfi_p0_wrdata[4]}, k7ddrphy_bitslip4_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip4_value1 <= (k7ddrphy_bitslip4_value1 + 1'd1); + main_k7ddrphy_bitslip4_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[36], main_k7ddrphy_dfi_p3_wrdata[4], main_k7ddrphy_dfi_p2_wrdata[36], main_k7ddrphy_dfi_p2_wrdata[4], main_k7ddrphy_dfi_p1_wrdata[36], main_k7ddrphy_dfi_p1_wrdata[4], main_k7ddrphy_dfi_p0_wrdata[36], main_k7ddrphy_dfi_p0_wrdata[4]}, main_k7ddrphy_bitslip4_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip4_value1 <= (main_k7ddrphy_bitslip4_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip4_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip4_value1 <= 3'd7; end - k7ddrphy_bitslip4_r1 <= {k7ddrphy_bitslip41, k7ddrphy_bitslip4_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip5_value0 <= (k7ddrphy_bitslip5_value0 + 1'd1); + main_k7ddrphy_bitslip4_r1 <= {main_k7ddrphy_bitslip41, main_k7ddrphy_bitslip4_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip5_value0 <= (main_k7ddrphy_bitslip5_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip5_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip5_value0 <= 3'd7; end - k7ddrphy_bitslip5_r0 <= {{k7ddrphy_dfi_p3_wrdata[37], k7ddrphy_dfi_p3_wrdata[5], k7ddrphy_dfi_p2_wrdata[37], k7ddrphy_dfi_p2_wrdata[5], k7ddrphy_dfi_p1_wrdata[37], k7ddrphy_dfi_p1_wrdata[5], k7ddrphy_dfi_p0_wrdata[37], k7ddrphy_dfi_p0_wrdata[5]}, k7ddrphy_bitslip5_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip5_value1 <= (k7ddrphy_bitslip5_value1 + 1'd1); + main_k7ddrphy_bitslip5_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[37], main_k7ddrphy_dfi_p3_wrdata[5], main_k7ddrphy_dfi_p2_wrdata[37], main_k7ddrphy_dfi_p2_wrdata[5], main_k7ddrphy_dfi_p1_wrdata[37], main_k7ddrphy_dfi_p1_wrdata[5], main_k7ddrphy_dfi_p0_wrdata[37], main_k7ddrphy_dfi_p0_wrdata[5]}, main_k7ddrphy_bitslip5_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip5_value1 <= (main_k7ddrphy_bitslip5_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip5_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip5_value1 <= 3'd7; end - k7ddrphy_bitslip5_r1 <= {k7ddrphy_bitslip51, k7ddrphy_bitslip5_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip6_value0 <= (k7ddrphy_bitslip6_value0 + 1'd1); + main_k7ddrphy_bitslip5_r1 <= {main_k7ddrphy_bitslip51, main_k7ddrphy_bitslip5_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip6_value0 <= (main_k7ddrphy_bitslip6_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip6_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip6_value0 <= 3'd7; end - k7ddrphy_bitslip6_r0 <= {{k7ddrphy_dfi_p3_wrdata[38], k7ddrphy_dfi_p3_wrdata[6], k7ddrphy_dfi_p2_wrdata[38], k7ddrphy_dfi_p2_wrdata[6], k7ddrphy_dfi_p1_wrdata[38], k7ddrphy_dfi_p1_wrdata[6], k7ddrphy_dfi_p0_wrdata[38], k7ddrphy_dfi_p0_wrdata[6]}, k7ddrphy_bitslip6_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip6_value1 <= (k7ddrphy_bitslip6_value1 + 1'd1); + main_k7ddrphy_bitslip6_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[38], main_k7ddrphy_dfi_p3_wrdata[6], main_k7ddrphy_dfi_p2_wrdata[38], main_k7ddrphy_dfi_p2_wrdata[6], main_k7ddrphy_dfi_p1_wrdata[38], main_k7ddrphy_dfi_p1_wrdata[6], main_k7ddrphy_dfi_p0_wrdata[38], main_k7ddrphy_dfi_p0_wrdata[6]}, main_k7ddrphy_bitslip6_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip6_value1 <= (main_k7ddrphy_bitslip6_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip6_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip6_value1 <= 3'd7; end - k7ddrphy_bitslip6_r1 <= {k7ddrphy_bitslip61, k7ddrphy_bitslip6_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip7_value0 <= (k7ddrphy_bitslip7_value0 + 1'd1); + main_k7ddrphy_bitslip6_r1 <= {main_k7ddrphy_bitslip61, main_k7ddrphy_bitslip6_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip7_value0 <= (main_k7ddrphy_bitslip7_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip7_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip7_value0 <= 3'd7; end - k7ddrphy_bitslip7_r0 <= {{k7ddrphy_dfi_p3_wrdata[39], k7ddrphy_dfi_p3_wrdata[7], k7ddrphy_dfi_p2_wrdata[39], k7ddrphy_dfi_p2_wrdata[7], k7ddrphy_dfi_p1_wrdata[39], k7ddrphy_dfi_p1_wrdata[7], k7ddrphy_dfi_p0_wrdata[39], k7ddrphy_dfi_p0_wrdata[7]}, k7ddrphy_bitslip7_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip7_value1 <= (k7ddrphy_bitslip7_value1 + 1'd1); + main_k7ddrphy_bitslip7_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[39], main_k7ddrphy_dfi_p3_wrdata[7], main_k7ddrphy_dfi_p2_wrdata[39], main_k7ddrphy_dfi_p2_wrdata[7], main_k7ddrphy_dfi_p1_wrdata[39], main_k7ddrphy_dfi_p1_wrdata[7], main_k7ddrphy_dfi_p0_wrdata[39], main_k7ddrphy_dfi_p0_wrdata[7]}, main_k7ddrphy_bitslip7_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip7_value1 <= (main_k7ddrphy_bitslip7_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip7_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip7_value1 <= 3'd7; end - k7ddrphy_bitslip7_r1 <= {k7ddrphy_bitslip71, k7ddrphy_bitslip7_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip8_value0 <= (k7ddrphy_bitslip8_value0 + 1'd1); + main_k7ddrphy_bitslip7_r1 <= {main_k7ddrphy_bitslip71, main_k7ddrphy_bitslip7_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip8_value0 <= (main_k7ddrphy_bitslip8_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip8_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip8_value0 <= 3'd7; end - k7ddrphy_bitslip8_r0 <= {{k7ddrphy_dfi_p3_wrdata[40], k7ddrphy_dfi_p3_wrdata[8], k7ddrphy_dfi_p2_wrdata[40], k7ddrphy_dfi_p2_wrdata[8], k7ddrphy_dfi_p1_wrdata[40], k7ddrphy_dfi_p1_wrdata[8], k7ddrphy_dfi_p0_wrdata[40], k7ddrphy_dfi_p0_wrdata[8]}, k7ddrphy_bitslip8_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip8_value1 <= (k7ddrphy_bitslip8_value1 + 1'd1); + main_k7ddrphy_bitslip8_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[40], main_k7ddrphy_dfi_p3_wrdata[8], main_k7ddrphy_dfi_p2_wrdata[40], main_k7ddrphy_dfi_p2_wrdata[8], main_k7ddrphy_dfi_p1_wrdata[40], main_k7ddrphy_dfi_p1_wrdata[8], main_k7ddrphy_dfi_p0_wrdata[40], main_k7ddrphy_dfi_p0_wrdata[8]}, main_k7ddrphy_bitslip8_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip8_value1 <= (main_k7ddrphy_bitslip8_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip8_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip8_value1 <= 3'd7; end - k7ddrphy_bitslip8_r1 <= {k7ddrphy_bitslip81, k7ddrphy_bitslip8_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip9_value0 <= (k7ddrphy_bitslip9_value0 + 1'd1); + main_k7ddrphy_bitslip8_r1 <= {main_k7ddrphy_bitslip81, main_k7ddrphy_bitslip8_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip9_value0 <= (main_k7ddrphy_bitslip9_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip9_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip9_value0 <= 3'd7; end - k7ddrphy_bitslip9_r0 <= {{k7ddrphy_dfi_p3_wrdata[41], k7ddrphy_dfi_p3_wrdata[9], k7ddrphy_dfi_p2_wrdata[41], k7ddrphy_dfi_p2_wrdata[9], k7ddrphy_dfi_p1_wrdata[41], k7ddrphy_dfi_p1_wrdata[9], k7ddrphy_dfi_p0_wrdata[41], k7ddrphy_dfi_p0_wrdata[9]}, k7ddrphy_bitslip9_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip9_value1 <= (k7ddrphy_bitslip9_value1 + 1'd1); + main_k7ddrphy_bitslip9_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[41], main_k7ddrphy_dfi_p3_wrdata[9], main_k7ddrphy_dfi_p2_wrdata[41], main_k7ddrphy_dfi_p2_wrdata[9], main_k7ddrphy_dfi_p1_wrdata[41], main_k7ddrphy_dfi_p1_wrdata[9], main_k7ddrphy_dfi_p0_wrdata[41], main_k7ddrphy_dfi_p0_wrdata[9]}, main_k7ddrphy_bitslip9_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip9_value1 <= (main_k7ddrphy_bitslip9_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip9_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip9_value1 <= 3'd7; end - k7ddrphy_bitslip9_r1 <= {k7ddrphy_bitslip91, k7ddrphy_bitslip9_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip10_value0 <= (k7ddrphy_bitslip10_value0 + 1'd1); + main_k7ddrphy_bitslip9_r1 <= {main_k7ddrphy_bitslip91, main_k7ddrphy_bitslip9_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip10_value0 <= (main_k7ddrphy_bitslip10_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip10_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip10_value0 <= 3'd7; end - k7ddrphy_bitslip10_r0 <= {{k7ddrphy_dfi_p3_wrdata[42], k7ddrphy_dfi_p3_wrdata[10], k7ddrphy_dfi_p2_wrdata[42], k7ddrphy_dfi_p2_wrdata[10], k7ddrphy_dfi_p1_wrdata[42], k7ddrphy_dfi_p1_wrdata[10], k7ddrphy_dfi_p0_wrdata[42], k7ddrphy_dfi_p0_wrdata[10]}, k7ddrphy_bitslip10_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip10_value1 <= (k7ddrphy_bitslip10_value1 + 1'd1); + main_k7ddrphy_bitslip10_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[42], main_k7ddrphy_dfi_p3_wrdata[10], main_k7ddrphy_dfi_p2_wrdata[42], main_k7ddrphy_dfi_p2_wrdata[10], main_k7ddrphy_dfi_p1_wrdata[42], main_k7ddrphy_dfi_p1_wrdata[10], main_k7ddrphy_dfi_p0_wrdata[42], main_k7ddrphy_dfi_p0_wrdata[10]}, main_k7ddrphy_bitslip10_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip10_value1 <= (main_k7ddrphy_bitslip10_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip10_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip10_value1 <= 3'd7; end - k7ddrphy_bitslip10_r1 <= {k7ddrphy_bitslip101, k7ddrphy_bitslip10_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip11_value0 <= (k7ddrphy_bitslip11_value0 + 1'd1); + main_k7ddrphy_bitslip10_r1 <= {main_k7ddrphy_bitslip101, main_k7ddrphy_bitslip10_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip11_value0 <= (main_k7ddrphy_bitslip11_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip11_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip11_value0 <= 3'd7; end - k7ddrphy_bitslip11_r0 <= {{k7ddrphy_dfi_p3_wrdata[43], k7ddrphy_dfi_p3_wrdata[11], k7ddrphy_dfi_p2_wrdata[43], k7ddrphy_dfi_p2_wrdata[11], k7ddrphy_dfi_p1_wrdata[43], k7ddrphy_dfi_p1_wrdata[11], k7ddrphy_dfi_p0_wrdata[43], k7ddrphy_dfi_p0_wrdata[11]}, k7ddrphy_bitslip11_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip11_value1 <= (k7ddrphy_bitslip11_value1 + 1'd1); + main_k7ddrphy_bitslip11_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[43], main_k7ddrphy_dfi_p3_wrdata[11], main_k7ddrphy_dfi_p2_wrdata[43], main_k7ddrphy_dfi_p2_wrdata[11], main_k7ddrphy_dfi_p1_wrdata[43], main_k7ddrphy_dfi_p1_wrdata[11], main_k7ddrphy_dfi_p0_wrdata[43], main_k7ddrphy_dfi_p0_wrdata[11]}, main_k7ddrphy_bitslip11_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip11_value1 <= (main_k7ddrphy_bitslip11_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip11_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip11_value1 <= 3'd7; end - k7ddrphy_bitslip11_r1 <= {k7ddrphy_bitslip111, k7ddrphy_bitslip11_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip12_value0 <= (k7ddrphy_bitslip12_value0 + 1'd1); + main_k7ddrphy_bitslip11_r1 <= {main_k7ddrphy_bitslip111, main_k7ddrphy_bitslip11_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip12_value0 <= (main_k7ddrphy_bitslip12_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip12_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip12_value0 <= 3'd7; end - k7ddrphy_bitslip12_r0 <= {{k7ddrphy_dfi_p3_wrdata[44], k7ddrphy_dfi_p3_wrdata[12], k7ddrphy_dfi_p2_wrdata[44], k7ddrphy_dfi_p2_wrdata[12], k7ddrphy_dfi_p1_wrdata[44], k7ddrphy_dfi_p1_wrdata[12], k7ddrphy_dfi_p0_wrdata[44], k7ddrphy_dfi_p0_wrdata[12]}, k7ddrphy_bitslip12_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip12_value1 <= (k7ddrphy_bitslip12_value1 + 1'd1); + main_k7ddrphy_bitslip12_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[44], main_k7ddrphy_dfi_p3_wrdata[12], main_k7ddrphy_dfi_p2_wrdata[44], main_k7ddrphy_dfi_p2_wrdata[12], main_k7ddrphy_dfi_p1_wrdata[44], main_k7ddrphy_dfi_p1_wrdata[12], main_k7ddrphy_dfi_p0_wrdata[44], main_k7ddrphy_dfi_p0_wrdata[12]}, main_k7ddrphy_bitslip12_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip12_value1 <= (main_k7ddrphy_bitslip12_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip12_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip12_value1 <= 3'd7; end - k7ddrphy_bitslip12_r1 <= {k7ddrphy_bitslip121, k7ddrphy_bitslip12_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip13_value0 <= (k7ddrphy_bitslip13_value0 + 1'd1); + main_k7ddrphy_bitslip12_r1 <= {main_k7ddrphy_bitslip121, main_k7ddrphy_bitslip12_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip13_value0 <= (main_k7ddrphy_bitslip13_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip13_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip13_value0 <= 3'd7; end - k7ddrphy_bitslip13_r0 <= {{k7ddrphy_dfi_p3_wrdata[45], k7ddrphy_dfi_p3_wrdata[13], k7ddrphy_dfi_p2_wrdata[45], k7ddrphy_dfi_p2_wrdata[13], k7ddrphy_dfi_p1_wrdata[45], k7ddrphy_dfi_p1_wrdata[13], k7ddrphy_dfi_p0_wrdata[45], k7ddrphy_dfi_p0_wrdata[13]}, k7ddrphy_bitslip13_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip13_value1 <= (k7ddrphy_bitslip13_value1 + 1'd1); + main_k7ddrphy_bitslip13_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[45], main_k7ddrphy_dfi_p3_wrdata[13], main_k7ddrphy_dfi_p2_wrdata[45], main_k7ddrphy_dfi_p2_wrdata[13], main_k7ddrphy_dfi_p1_wrdata[45], main_k7ddrphy_dfi_p1_wrdata[13], main_k7ddrphy_dfi_p0_wrdata[45], main_k7ddrphy_dfi_p0_wrdata[13]}, main_k7ddrphy_bitslip13_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip13_value1 <= (main_k7ddrphy_bitslip13_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip13_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip13_value1 <= 3'd7; end - k7ddrphy_bitslip13_r1 <= {k7ddrphy_bitslip131, k7ddrphy_bitslip13_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip14_value0 <= (k7ddrphy_bitslip14_value0 + 1'd1); + main_k7ddrphy_bitslip13_r1 <= {main_k7ddrphy_bitslip131, main_k7ddrphy_bitslip13_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip14_value0 <= (main_k7ddrphy_bitslip14_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip14_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip14_value0 <= 3'd7; end - k7ddrphy_bitslip14_r0 <= {{k7ddrphy_dfi_p3_wrdata[46], k7ddrphy_dfi_p3_wrdata[14], k7ddrphy_dfi_p2_wrdata[46], k7ddrphy_dfi_p2_wrdata[14], k7ddrphy_dfi_p1_wrdata[46], k7ddrphy_dfi_p1_wrdata[14], k7ddrphy_dfi_p0_wrdata[46], k7ddrphy_dfi_p0_wrdata[14]}, k7ddrphy_bitslip14_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip14_value1 <= (k7ddrphy_bitslip14_value1 + 1'd1); + main_k7ddrphy_bitslip14_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[46], main_k7ddrphy_dfi_p3_wrdata[14], main_k7ddrphy_dfi_p2_wrdata[46], main_k7ddrphy_dfi_p2_wrdata[14], main_k7ddrphy_dfi_p1_wrdata[46], main_k7ddrphy_dfi_p1_wrdata[14], main_k7ddrphy_dfi_p0_wrdata[46], main_k7ddrphy_dfi_p0_wrdata[14]}, main_k7ddrphy_bitslip14_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip14_value1 <= (main_k7ddrphy_bitslip14_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip14_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip14_value1 <= 3'd7; end - k7ddrphy_bitslip14_r1 <= {k7ddrphy_bitslip141, k7ddrphy_bitslip14_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip15_value0 <= (k7ddrphy_bitslip15_value0 + 1'd1); + main_k7ddrphy_bitslip14_r1 <= {main_k7ddrphy_bitslip141, main_k7ddrphy_bitslip14_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip15_value0 <= (main_k7ddrphy_bitslip15_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip15_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip15_value0 <= 3'd7; end - k7ddrphy_bitslip15_r0 <= {{k7ddrphy_dfi_p3_wrdata[47], k7ddrphy_dfi_p3_wrdata[15], k7ddrphy_dfi_p2_wrdata[47], k7ddrphy_dfi_p2_wrdata[15], k7ddrphy_dfi_p1_wrdata[47], k7ddrphy_dfi_p1_wrdata[15], k7ddrphy_dfi_p0_wrdata[47], k7ddrphy_dfi_p0_wrdata[15]}, k7ddrphy_bitslip15_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip15_value1 <= (k7ddrphy_bitslip15_value1 + 1'd1); + main_k7ddrphy_bitslip15_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[47], main_k7ddrphy_dfi_p3_wrdata[15], main_k7ddrphy_dfi_p2_wrdata[47], main_k7ddrphy_dfi_p2_wrdata[15], main_k7ddrphy_dfi_p1_wrdata[47], main_k7ddrphy_dfi_p1_wrdata[15], main_k7ddrphy_dfi_p0_wrdata[47], main_k7ddrphy_dfi_p0_wrdata[15]}, main_k7ddrphy_bitslip15_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip15_value1 <= (main_k7ddrphy_bitslip15_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip15_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip15_value1 <= 3'd7; end - k7ddrphy_bitslip15_r1 <= {k7ddrphy_bitslip151, k7ddrphy_bitslip15_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip16_value0 <= (k7ddrphy_bitslip16_value0 + 1'd1); + main_k7ddrphy_bitslip15_r1 <= {main_k7ddrphy_bitslip151, main_k7ddrphy_bitslip15_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip16_value0 <= (main_k7ddrphy_bitslip16_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip16_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip16_value0 <= 3'd7; end - k7ddrphy_bitslip16_r0 <= {{k7ddrphy_dfi_p3_wrdata[48], k7ddrphy_dfi_p3_wrdata[16], k7ddrphy_dfi_p2_wrdata[48], k7ddrphy_dfi_p2_wrdata[16], k7ddrphy_dfi_p1_wrdata[48], k7ddrphy_dfi_p1_wrdata[16], k7ddrphy_dfi_p0_wrdata[48], k7ddrphy_dfi_p0_wrdata[16]}, k7ddrphy_bitslip16_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip16_value1 <= (k7ddrphy_bitslip16_value1 + 1'd1); + main_k7ddrphy_bitslip16_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[48], main_k7ddrphy_dfi_p3_wrdata[16], main_k7ddrphy_dfi_p2_wrdata[48], main_k7ddrphy_dfi_p2_wrdata[16], main_k7ddrphy_dfi_p1_wrdata[48], main_k7ddrphy_dfi_p1_wrdata[16], main_k7ddrphy_dfi_p0_wrdata[48], main_k7ddrphy_dfi_p0_wrdata[16]}, main_k7ddrphy_bitslip16_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip16_value1 <= (main_k7ddrphy_bitslip16_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip16_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip16_value1 <= 3'd7; end - k7ddrphy_bitslip16_r1 <= {k7ddrphy_bitslip161, k7ddrphy_bitslip16_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip17_value0 <= (k7ddrphy_bitslip17_value0 + 1'd1); + main_k7ddrphy_bitslip16_r1 <= {main_k7ddrphy_bitslip161, main_k7ddrphy_bitslip16_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip17_value0 <= (main_k7ddrphy_bitslip17_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip17_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip17_value0 <= 3'd7; end - k7ddrphy_bitslip17_r0 <= {{k7ddrphy_dfi_p3_wrdata[49], k7ddrphy_dfi_p3_wrdata[17], k7ddrphy_dfi_p2_wrdata[49], k7ddrphy_dfi_p2_wrdata[17], k7ddrphy_dfi_p1_wrdata[49], k7ddrphy_dfi_p1_wrdata[17], k7ddrphy_dfi_p0_wrdata[49], k7ddrphy_dfi_p0_wrdata[17]}, k7ddrphy_bitslip17_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip17_value1 <= (k7ddrphy_bitslip17_value1 + 1'd1); + main_k7ddrphy_bitslip17_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[49], main_k7ddrphy_dfi_p3_wrdata[17], main_k7ddrphy_dfi_p2_wrdata[49], main_k7ddrphy_dfi_p2_wrdata[17], main_k7ddrphy_dfi_p1_wrdata[49], main_k7ddrphy_dfi_p1_wrdata[17], main_k7ddrphy_dfi_p0_wrdata[49], main_k7ddrphy_dfi_p0_wrdata[17]}, main_k7ddrphy_bitslip17_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip17_value1 <= (main_k7ddrphy_bitslip17_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip17_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip17_value1 <= 3'd7; end - k7ddrphy_bitslip17_r1 <= {k7ddrphy_bitslip171, k7ddrphy_bitslip17_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip18_value0 <= (k7ddrphy_bitslip18_value0 + 1'd1); + main_k7ddrphy_bitslip17_r1 <= {main_k7ddrphy_bitslip171, main_k7ddrphy_bitslip17_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip18_value0 <= (main_k7ddrphy_bitslip18_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip18_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip18_value0 <= 3'd7; end - k7ddrphy_bitslip18_r0 <= {{k7ddrphy_dfi_p3_wrdata[50], k7ddrphy_dfi_p3_wrdata[18], k7ddrphy_dfi_p2_wrdata[50], k7ddrphy_dfi_p2_wrdata[18], k7ddrphy_dfi_p1_wrdata[50], k7ddrphy_dfi_p1_wrdata[18], k7ddrphy_dfi_p0_wrdata[50], k7ddrphy_dfi_p0_wrdata[18]}, k7ddrphy_bitslip18_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip18_value1 <= (k7ddrphy_bitslip18_value1 + 1'd1); + main_k7ddrphy_bitslip18_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[50], main_k7ddrphy_dfi_p3_wrdata[18], main_k7ddrphy_dfi_p2_wrdata[50], main_k7ddrphy_dfi_p2_wrdata[18], main_k7ddrphy_dfi_p1_wrdata[50], main_k7ddrphy_dfi_p1_wrdata[18], main_k7ddrphy_dfi_p0_wrdata[50], main_k7ddrphy_dfi_p0_wrdata[18]}, main_k7ddrphy_bitslip18_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip18_value1 <= (main_k7ddrphy_bitslip18_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip18_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip18_value1 <= 3'd7; end - k7ddrphy_bitslip18_r1 <= {k7ddrphy_bitslip181, k7ddrphy_bitslip18_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip19_value0 <= (k7ddrphy_bitslip19_value0 + 1'd1); + main_k7ddrphy_bitslip18_r1 <= {main_k7ddrphy_bitslip181, main_k7ddrphy_bitslip18_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip19_value0 <= (main_k7ddrphy_bitslip19_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip19_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip19_value0 <= 3'd7; end - k7ddrphy_bitslip19_r0 <= {{k7ddrphy_dfi_p3_wrdata[51], k7ddrphy_dfi_p3_wrdata[19], k7ddrphy_dfi_p2_wrdata[51], k7ddrphy_dfi_p2_wrdata[19], k7ddrphy_dfi_p1_wrdata[51], k7ddrphy_dfi_p1_wrdata[19], k7ddrphy_dfi_p0_wrdata[51], k7ddrphy_dfi_p0_wrdata[19]}, k7ddrphy_bitslip19_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip19_value1 <= (k7ddrphy_bitslip19_value1 + 1'd1); + main_k7ddrphy_bitslip19_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[51], main_k7ddrphy_dfi_p3_wrdata[19], main_k7ddrphy_dfi_p2_wrdata[51], main_k7ddrphy_dfi_p2_wrdata[19], main_k7ddrphy_dfi_p1_wrdata[51], main_k7ddrphy_dfi_p1_wrdata[19], main_k7ddrphy_dfi_p0_wrdata[51], main_k7ddrphy_dfi_p0_wrdata[19]}, main_k7ddrphy_bitslip19_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip19_value1 <= (main_k7ddrphy_bitslip19_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip19_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip19_value1 <= 3'd7; end - k7ddrphy_bitslip19_r1 <= {k7ddrphy_bitslip191, k7ddrphy_bitslip19_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip20_value0 <= (k7ddrphy_bitslip20_value0 + 1'd1); + main_k7ddrphy_bitslip19_r1 <= {main_k7ddrphy_bitslip191, main_k7ddrphy_bitslip19_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip20_value0 <= (main_k7ddrphy_bitslip20_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip20_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip20_value0 <= 3'd7; end - k7ddrphy_bitslip20_r0 <= {{k7ddrphy_dfi_p3_wrdata[52], k7ddrphy_dfi_p3_wrdata[20], k7ddrphy_dfi_p2_wrdata[52], k7ddrphy_dfi_p2_wrdata[20], k7ddrphy_dfi_p1_wrdata[52], k7ddrphy_dfi_p1_wrdata[20], k7ddrphy_dfi_p0_wrdata[52], k7ddrphy_dfi_p0_wrdata[20]}, k7ddrphy_bitslip20_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip20_value1 <= (k7ddrphy_bitslip20_value1 + 1'd1); + main_k7ddrphy_bitslip20_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[52], main_k7ddrphy_dfi_p3_wrdata[20], main_k7ddrphy_dfi_p2_wrdata[52], main_k7ddrphy_dfi_p2_wrdata[20], main_k7ddrphy_dfi_p1_wrdata[52], main_k7ddrphy_dfi_p1_wrdata[20], main_k7ddrphy_dfi_p0_wrdata[52], main_k7ddrphy_dfi_p0_wrdata[20]}, main_k7ddrphy_bitslip20_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip20_value1 <= (main_k7ddrphy_bitslip20_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip20_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip20_value1 <= 3'd7; end - k7ddrphy_bitslip20_r1 <= {k7ddrphy_bitslip201, k7ddrphy_bitslip20_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip21_value0 <= (k7ddrphy_bitslip21_value0 + 1'd1); + main_k7ddrphy_bitslip20_r1 <= {main_k7ddrphy_bitslip201, main_k7ddrphy_bitslip20_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip21_value0 <= (main_k7ddrphy_bitslip21_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip21_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip21_value0 <= 3'd7; end - k7ddrphy_bitslip21_r0 <= {{k7ddrphy_dfi_p3_wrdata[53], k7ddrphy_dfi_p3_wrdata[21], k7ddrphy_dfi_p2_wrdata[53], k7ddrphy_dfi_p2_wrdata[21], k7ddrphy_dfi_p1_wrdata[53], k7ddrphy_dfi_p1_wrdata[21], k7ddrphy_dfi_p0_wrdata[53], k7ddrphy_dfi_p0_wrdata[21]}, k7ddrphy_bitslip21_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip21_value1 <= (k7ddrphy_bitslip21_value1 + 1'd1); + main_k7ddrphy_bitslip21_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[53], main_k7ddrphy_dfi_p3_wrdata[21], main_k7ddrphy_dfi_p2_wrdata[53], main_k7ddrphy_dfi_p2_wrdata[21], main_k7ddrphy_dfi_p1_wrdata[53], main_k7ddrphy_dfi_p1_wrdata[21], main_k7ddrphy_dfi_p0_wrdata[53], main_k7ddrphy_dfi_p0_wrdata[21]}, main_k7ddrphy_bitslip21_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip21_value1 <= (main_k7ddrphy_bitslip21_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip21_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip21_value1 <= 3'd7; end - k7ddrphy_bitslip21_r1 <= {k7ddrphy_bitslip211, k7ddrphy_bitslip21_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip22_value0 <= (k7ddrphy_bitslip22_value0 + 1'd1); + main_k7ddrphy_bitslip21_r1 <= {main_k7ddrphy_bitslip211, main_k7ddrphy_bitslip21_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip22_value0 <= (main_k7ddrphy_bitslip22_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip22_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip22_value0 <= 3'd7; end - k7ddrphy_bitslip22_r0 <= {{k7ddrphy_dfi_p3_wrdata[54], k7ddrphy_dfi_p3_wrdata[22], k7ddrphy_dfi_p2_wrdata[54], k7ddrphy_dfi_p2_wrdata[22], k7ddrphy_dfi_p1_wrdata[54], k7ddrphy_dfi_p1_wrdata[22], k7ddrphy_dfi_p0_wrdata[54], k7ddrphy_dfi_p0_wrdata[22]}, k7ddrphy_bitslip22_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip22_value1 <= (k7ddrphy_bitslip22_value1 + 1'd1); + main_k7ddrphy_bitslip22_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[54], main_k7ddrphy_dfi_p3_wrdata[22], main_k7ddrphy_dfi_p2_wrdata[54], main_k7ddrphy_dfi_p2_wrdata[22], main_k7ddrphy_dfi_p1_wrdata[54], main_k7ddrphy_dfi_p1_wrdata[22], main_k7ddrphy_dfi_p0_wrdata[54], main_k7ddrphy_dfi_p0_wrdata[22]}, main_k7ddrphy_bitslip22_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip22_value1 <= (main_k7ddrphy_bitslip22_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip22_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip22_value1 <= 3'd7; end - k7ddrphy_bitslip22_r1 <= {k7ddrphy_bitslip221, k7ddrphy_bitslip22_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip23_value0 <= (k7ddrphy_bitslip23_value0 + 1'd1); + main_k7ddrphy_bitslip22_r1 <= {main_k7ddrphy_bitslip221, main_k7ddrphy_bitslip22_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip23_value0 <= (main_k7ddrphy_bitslip23_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip23_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip23_value0 <= 3'd7; end - k7ddrphy_bitslip23_r0 <= {{k7ddrphy_dfi_p3_wrdata[55], k7ddrphy_dfi_p3_wrdata[23], k7ddrphy_dfi_p2_wrdata[55], k7ddrphy_dfi_p2_wrdata[23], k7ddrphy_dfi_p1_wrdata[55], k7ddrphy_dfi_p1_wrdata[23], k7ddrphy_dfi_p0_wrdata[55], k7ddrphy_dfi_p0_wrdata[23]}, k7ddrphy_bitslip23_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip23_value1 <= (k7ddrphy_bitslip23_value1 + 1'd1); + main_k7ddrphy_bitslip23_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[55], main_k7ddrphy_dfi_p3_wrdata[23], main_k7ddrphy_dfi_p2_wrdata[55], main_k7ddrphy_dfi_p2_wrdata[23], main_k7ddrphy_dfi_p1_wrdata[55], main_k7ddrphy_dfi_p1_wrdata[23], main_k7ddrphy_dfi_p0_wrdata[55], main_k7ddrphy_dfi_p0_wrdata[23]}, main_k7ddrphy_bitslip23_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip23_value1 <= (main_k7ddrphy_bitslip23_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip23_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip23_value1 <= 3'd7; end - k7ddrphy_bitslip23_r1 <= {k7ddrphy_bitslip231, k7ddrphy_bitslip23_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip24_value0 <= (k7ddrphy_bitslip24_value0 + 1'd1); + main_k7ddrphy_bitslip23_r1 <= {main_k7ddrphy_bitslip231, main_k7ddrphy_bitslip23_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip24_value0 <= (main_k7ddrphy_bitslip24_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip24_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip24_value0 <= 3'd7; end - k7ddrphy_bitslip24_r0 <= {{k7ddrphy_dfi_p3_wrdata[56], k7ddrphy_dfi_p3_wrdata[24], k7ddrphy_dfi_p2_wrdata[56], k7ddrphy_dfi_p2_wrdata[24], k7ddrphy_dfi_p1_wrdata[56], k7ddrphy_dfi_p1_wrdata[24], k7ddrphy_dfi_p0_wrdata[56], k7ddrphy_dfi_p0_wrdata[24]}, k7ddrphy_bitslip24_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip24_value1 <= (k7ddrphy_bitslip24_value1 + 1'd1); + main_k7ddrphy_bitslip24_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[56], main_k7ddrphy_dfi_p3_wrdata[24], main_k7ddrphy_dfi_p2_wrdata[56], main_k7ddrphy_dfi_p2_wrdata[24], main_k7ddrphy_dfi_p1_wrdata[56], main_k7ddrphy_dfi_p1_wrdata[24], main_k7ddrphy_dfi_p0_wrdata[56], main_k7ddrphy_dfi_p0_wrdata[24]}, main_k7ddrphy_bitslip24_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip24_value1 <= (main_k7ddrphy_bitslip24_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip24_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip24_value1 <= 3'd7; end - k7ddrphy_bitslip24_r1 <= {k7ddrphy_bitslip241, k7ddrphy_bitslip24_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip25_value0 <= (k7ddrphy_bitslip25_value0 + 1'd1); + main_k7ddrphy_bitslip24_r1 <= {main_k7ddrphy_bitslip241, main_k7ddrphy_bitslip24_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip25_value0 <= (main_k7ddrphy_bitslip25_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip25_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip25_value0 <= 3'd7; end - k7ddrphy_bitslip25_r0 <= {{k7ddrphy_dfi_p3_wrdata[57], k7ddrphy_dfi_p3_wrdata[25], k7ddrphy_dfi_p2_wrdata[57], k7ddrphy_dfi_p2_wrdata[25], k7ddrphy_dfi_p1_wrdata[57], k7ddrphy_dfi_p1_wrdata[25], k7ddrphy_dfi_p0_wrdata[57], k7ddrphy_dfi_p0_wrdata[25]}, k7ddrphy_bitslip25_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip25_value1 <= (k7ddrphy_bitslip25_value1 + 1'd1); + main_k7ddrphy_bitslip25_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[57], main_k7ddrphy_dfi_p3_wrdata[25], main_k7ddrphy_dfi_p2_wrdata[57], main_k7ddrphy_dfi_p2_wrdata[25], main_k7ddrphy_dfi_p1_wrdata[57], main_k7ddrphy_dfi_p1_wrdata[25], main_k7ddrphy_dfi_p0_wrdata[57], main_k7ddrphy_dfi_p0_wrdata[25]}, main_k7ddrphy_bitslip25_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip25_value1 <= (main_k7ddrphy_bitslip25_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip25_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip25_value1 <= 3'd7; end - k7ddrphy_bitslip25_r1 <= {k7ddrphy_bitslip251, k7ddrphy_bitslip25_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip26_value0 <= (k7ddrphy_bitslip26_value0 + 1'd1); + main_k7ddrphy_bitslip25_r1 <= {main_k7ddrphy_bitslip251, main_k7ddrphy_bitslip25_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip26_value0 <= (main_k7ddrphy_bitslip26_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip26_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip26_value0 <= 3'd7; end - k7ddrphy_bitslip26_r0 <= {{k7ddrphy_dfi_p3_wrdata[58], k7ddrphy_dfi_p3_wrdata[26], k7ddrphy_dfi_p2_wrdata[58], k7ddrphy_dfi_p2_wrdata[26], k7ddrphy_dfi_p1_wrdata[58], k7ddrphy_dfi_p1_wrdata[26], k7ddrphy_dfi_p0_wrdata[58], k7ddrphy_dfi_p0_wrdata[26]}, k7ddrphy_bitslip26_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip26_value1 <= (k7ddrphy_bitslip26_value1 + 1'd1); + main_k7ddrphy_bitslip26_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[58], main_k7ddrphy_dfi_p3_wrdata[26], main_k7ddrphy_dfi_p2_wrdata[58], main_k7ddrphy_dfi_p2_wrdata[26], main_k7ddrphy_dfi_p1_wrdata[58], main_k7ddrphy_dfi_p1_wrdata[26], main_k7ddrphy_dfi_p0_wrdata[58], main_k7ddrphy_dfi_p0_wrdata[26]}, main_k7ddrphy_bitslip26_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip26_value1 <= (main_k7ddrphy_bitslip26_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip26_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip26_value1 <= 3'd7; end - k7ddrphy_bitslip26_r1 <= {k7ddrphy_bitslip261, k7ddrphy_bitslip26_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip27_value0 <= (k7ddrphy_bitslip27_value0 + 1'd1); + main_k7ddrphy_bitslip26_r1 <= {main_k7ddrphy_bitslip261, main_k7ddrphy_bitslip26_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip27_value0 <= (main_k7ddrphy_bitslip27_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip27_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip27_value0 <= 3'd7; end - k7ddrphy_bitslip27_r0 <= {{k7ddrphy_dfi_p3_wrdata[59], k7ddrphy_dfi_p3_wrdata[27], k7ddrphy_dfi_p2_wrdata[59], k7ddrphy_dfi_p2_wrdata[27], k7ddrphy_dfi_p1_wrdata[59], k7ddrphy_dfi_p1_wrdata[27], k7ddrphy_dfi_p0_wrdata[59], k7ddrphy_dfi_p0_wrdata[27]}, k7ddrphy_bitslip27_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip27_value1 <= (k7ddrphy_bitslip27_value1 + 1'd1); + main_k7ddrphy_bitslip27_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[59], main_k7ddrphy_dfi_p3_wrdata[27], main_k7ddrphy_dfi_p2_wrdata[59], main_k7ddrphy_dfi_p2_wrdata[27], main_k7ddrphy_dfi_p1_wrdata[59], main_k7ddrphy_dfi_p1_wrdata[27], main_k7ddrphy_dfi_p0_wrdata[59], main_k7ddrphy_dfi_p0_wrdata[27]}, main_k7ddrphy_bitslip27_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip27_value1 <= (main_k7ddrphy_bitslip27_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip27_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip27_value1 <= 3'd7; end - k7ddrphy_bitslip27_r1 <= {k7ddrphy_bitslip271, k7ddrphy_bitslip27_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip28_value0 <= (k7ddrphy_bitslip28_value0 + 1'd1); + main_k7ddrphy_bitslip27_r1 <= {main_k7ddrphy_bitslip271, main_k7ddrphy_bitslip27_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip28_value0 <= (main_k7ddrphy_bitslip28_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip28_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip28_value0 <= 3'd7; end - k7ddrphy_bitslip28_r0 <= {{k7ddrphy_dfi_p3_wrdata[60], k7ddrphy_dfi_p3_wrdata[28], k7ddrphy_dfi_p2_wrdata[60], k7ddrphy_dfi_p2_wrdata[28], k7ddrphy_dfi_p1_wrdata[60], k7ddrphy_dfi_p1_wrdata[28], k7ddrphy_dfi_p0_wrdata[60], k7ddrphy_dfi_p0_wrdata[28]}, k7ddrphy_bitslip28_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip28_value1 <= (k7ddrphy_bitslip28_value1 + 1'd1); + main_k7ddrphy_bitslip28_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[60], main_k7ddrphy_dfi_p3_wrdata[28], main_k7ddrphy_dfi_p2_wrdata[60], main_k7ddrphy_dfi_p2_wrdata[28], main_k7ddrphy_dfi_p1_wrdata[60], main_k7ddrphy_dfi_p1_wrdata[28], main_k7ddrphy_dfi_p0_wrdata[60], main_k7ddrphy_dfi_p0_wrdata[28]}, main_k7ddrphy_bitslip28_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip28_value1 <= (main_k7ddrphy_bitslip28_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip28_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip28_value1 <= 3'd7; end - k7ddrphy_bitslip28_r1 <= {k7ddrphy_bitslip281, k7ddrphy_bitslip28_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip29_value0 <= (k7ddrphy_bitslip29_value0 + 1'd1); + main_k7ddrphy_bitslip28_r1 <= {main_k7ddrphy_bitslip281, main_k7ddrphy_bitslip28_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip29_value0 <= (main_k7ddrphy_bitslip29_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip29_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip29_value0 <= 3'd7; end - k7ddrphy_bitslip29_r0 <= {{k7ddrphy_dfi_p3_wrdata[61], k7ddrphy_dfi_p3_wrdata[29], k7ddrphy_dfi_p2_wrdata[61], k7ddrphy_dfi_p2_wrdata[29], k7ddrphy_dfi_p1_wrdata[61], k7ddrphy_dfi_p1_wrdata[29], k7ddrphy_dfi_p0_wrdata[61], k7ddrphy_dfi_p0_wrdata[29]}, k7ddrphy_bitslip29_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip29_value1 <= (k7ddrphy_bitslip29_value1 + 1'd1); + main_k7ddrphy_bitslip29_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[61], main_k7ddrphy_dfi_p3_wrdata[29], main_k7ddrphy_dfi_p2_wrdata[61], main_k7ddrphy_dfi_p2_wrdata[29], main_k7ddrphy_dfi_p1_wrdata[61], main_k7ddrphy_dfi_p1_wrdata[29], main_k7ddrphy_dfi_p0_wrdata[61], main_k7ddrphy_dfi_p0_wrdata[29]}, main_k7ddrphy_bitslip29_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip29_value1 <= (main_k7ddrphy_bitslip29_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip29_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip29_value1 <= 3'd7; end - k7ddrphy_bitslip29_r1 <= {k7ddrphy_bitslip291, k7ddrphy_bitslip29_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip30_value0 <= (k7ddrphy_bitslip30_value0 + 1'd1); + main_k7ddrphy_bitslip29_r1 <= {main_k7ddrphy_bitslip291, main_k7ddrphy_bitslip29_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip30_value0 <= (main_k7ddrphy_bitslip30_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip30_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip30_value0 <= 3'd7; end - k7ddrphy_bitslip30_r0 <= {{k7ddrphy_dfi_p3_wrdata[62], k7ddrphy_dfi_p3_wrdata[30], k7ddrphy_dfi_p2_wrdata[62], k7ddrphy_dfi_p2_wrdata[30], k7ddrphy_dfi_p1_wrdata[62], k7ddrphy_dfi_p1_wrdata[30], k7ddrphy_dfi_p0_wrdata[62], k7ddrphy_dfi_p0_wrdata[30]}, k7ddrphy_bitslip30_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip30_value1 <= (k7ddrphy_bitslip30_value1 + 1'd1); + main_k7ddrphy_bitslip30_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[62], main_k7ddrphy_dfi_p3_wrdata[30], main_k7ddrphy_dfi_p2_wrdata[62], main_k7ddrphy_dfi_p2_wrdata[30], main_k7ddrphy_dfi_p1_wrdata[62], main_k7ddrphy_dfi_p1_wrdata[30], main_k7ddrphy_dfi_p0_wrdata[62], main_k7ddrphy_dfi_p0_wrdata[30]}, main_k7ddrphy_bitslip30_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip30_value1 <= (main_k7ddrphy_bitslip30_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip30_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip30_value1 <= 3'd7; end - k7ddrphy_bitslip30_r1 <= {k7ddrphy_bitslip301, k7ddrphy_bitslip30_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip31_value0 <= (k7ddrphy_bitslip31_value0 + 1'd1); + main_k7ddrphy_bitslip30_r1 <= {main_k7ddrphy_bitslip301, main_k7ddrphy_bitslip30_r1[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip31_value0 <= (main_k7ddrphy_bitslip31_value0 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip31_value0 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip31_value0 <= 3'd7; end - k7ddrphy_bitslip31_r0 <= {{k7ddrphy_dfi_p3_wrdata[63], k7ddrphy_dfi_p3_wrdata[31], k7ddrphy_dfi_p2_wrdata[63], k7ddrphy_dfi_p2_wrdata[31], k7ddrphy_dfi_p1_wrdata[63], k7ddrphy_dfi_p1_wrdata[31], k7ddrphy_dfi_p0_wrdata[63], k7ddrphy_dfi_p0_wrdata[31]}, k7ddrphy_bitslip31_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip31_value1 <= (k7ddrphy_bitslip31_value1 + 1'd1); + main_k7ddrphy_bitslip31_r0 <= {{main_k7ddrphy_dfi_p3_wrdata[63], main_k7ddrphy_dfi_p3_wrdata[31], main_k7ddrphy_dfi_p2_wrdata[63], main_k7ddrphy_dfi_p2_wrdata[31], main_k7ddrphy_dfi_p1_wrdata[63], main_k7ddrphy_dfi_p1_wrdata[31], main_k7ddrphy_dfi_p0_wrdata[63], main_k7ddrphy_dfi_p0_wrdata[31]}, main_k7ddrphy_bitslip31_r0[15:8]}; + if ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_re)) begin + main_k7ddrphy_bitslip31_value1 <= (main_k7ddrphy_bitslip31_value1 + 1'd1); end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip31_value1 <= 3'd7; + if (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_bitslip_rst_re) | main_k7ddrphy_rst_storage)) begin + main_k7ddrphy_bitslip31_value1 <= 3'd7; end - k7ddrphy_bitslip31_r1 <= {k7ddrphy_bitslip311, k7ddrphy_bitslip31_r1[15:8]}; - k7ddrphy_rddata_en_tappeddelayline0 <= (((k7ddrphy_dfi_p0_rddata_en | k7ddrphy_dfi_p1_rddata_en) | k7ddrphy_dfi_p2_rddata_en) | k7ddrphy_dfi_p3_rddata_en); - k7ddrphy_rddata_en_tappeddelayline1 <= k7ddrphy_rddata_en_tappeddelayline0; - k7ddrphy_rddata_en_tappeddelayline2 <= k7ddrphy_rddata_en_tappeddelayline1; - k7ddrphy_rddata_en_tappeddelayline3 <= k7ddrphy_rddata_en_tappeddelayline2; - k7ddrphy_rddata_en_tappeddelayline4 <= k7ddrphy_rddata_en_tappeddelayline3; - k7ddrphy_rddata_en_tappeddelayline5 <= k7ddrphy_rddata_en_tappeddelayline4; - k7ddrphy_rddata_en_tappeddelayline6 <= k7ddrphy_rddata_en_tappeddelayline5; - k7ddrphy_rddata_en_tappeddelayline7 <= k7ddrphy_rddata_en_tappeddelayline6; - k7ddrphy_wrdata_en_tappeddelayline0 <= (((k7ddrphy_dfi_p0_wrdata_en | k7ddrphy_dfi_p1_wrdata_en) | k7ddrphy_dfi_p2_wrdata_en) | k7ddrphy_dfi_p3_wrdata_en); - k7ddrphy_wrdata_en_tappeddelayline1 <= k7ddrphy_wrdata_en_tappeddelayline0; - k7ddrphy_wrdata_en_tappeddelayline2 <= k7ddrphy_wrdata_en_tappeddelayline1; - if (litedramcore_csr_dfi_p0_rddata_valid) begin - litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata; + main_k7ddrphy_bitslip31_r1 <= {main_k7ddrphy_bitslip311, main_k7ddrphy_bitslip31_r1[15:8]}; + main_k7ddrphy_rddata_en_tappeddelayline0 <= (((main_k7ddrphy_dfi_p0_rddata_en | main_k7ddrphy_dfi_p1_rddata_en) | main_k7ddrphy_dfi_p2_rddata_en) | main_k7ddrphy_dfi_p3_rddata_en); + main_k7ddrphy_rddata_en_tappeddelayline1 <= main_k7ddrphy_rddata_en_tappeddelayline0; + main_k7ddrphy_rddata_en_tappeddelayline2 <= main_k7ddrphy_rddata_en_tappeddelayline1; + main_k7ddrphy_rddata_en_tappeddelayline3 <= main_k7ddrphy_rddata_en_tappeddelayline2; + main_k7ddrphy_rddata_en_tappeddelayline4 <= main_k7ddrphy_rddata_en_tappeddelayline3; + main_k7ddrphy_rddata_en_tappeddelayline5 <= main_k7ddrphy_rddata_en_tappeddelayline4; + main_k7ddrphy_rddata_en_tappeddelayline6 <= main_k7ddrphy_rddata_en_tappeddelayline5; + main_k7ddrphy_rddata_en_tappeddelayline7 <= main_k7ddrphy_rddata_en_tappeddelayline6; + main_k7ddrphy_wrdata_en_tappeddelayline0 <= (((main_k7ddrphy_dfi_p0_wrdata_en | main_k7ddrphy_dfi_p1_wrdata_en) | main_k7ddrphy_dfi_p2_wrdata_en) | main_k7ddrphy_dfi_p3_wrdata_en); + main_k7ddrphy_wrdata_en_tappeddelayline1 <= main_k7ddrphy_wrdata_en_tappeddelayline0; + main_k7ddrphy_wrdata_en_tappeddelayline2 <= main_k7ddrphy_wrdata_en_tappeddelayline1; + if (main_litedramcore_csr_dfi_p0_rddata_valid) begin + main_litedramcore_phaseinjector0_rddata_status <= main_litedramcore_csr_dfi_p0_rddata; end - if (litedramcore_csr_dfi_p1_rddata_valid) begin - litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata; + if (main_litedramcore_csr_dfi_p1_rddata_valid) begin + main_litedramcore_phaseinjector1_rddata_status <= main_litedramcore_csr_dfi_p1_rddata; end - if (litedramcore_csr_dfi_p2_rddata_valid) begin - litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata; + if (main_litedramcore_csr_dfi_p2_rddata_valid) begin + main_litedramcore_phaseinjector2_rddata_status <= main_litedramcore_csr_dfi_p2_rddata; end - if (litedramcore_csr_dfi_p3_rddata_valid) begin - litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata; + if (main_litedramcore_csr_dfi_p3_rddata_valid) begin + main_litedramcore_phaseinjector3_rddata_status <= main_litedramcore_csr_dfi_p3_rddata; end - if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin - litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); + if ((main_litedramcore_timer_wait & (~main_litedramcore_timer_done0))) begin + main_litedramcore_timer_count1 <= (main_litedramcore_timer_count1 - 1'd1); end else begin - litedramcore_timer_count1 <= 10'd781; + main_litedramcore_timer_count1 <= 10'd781; end - litedramcore_postponer_req_o <= 1'd0; - if (litedramcore_postponer_req_i) begin - litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); - if ((litedramcore_postponer_count == 1'd0)) begin - litedramcore_postponer_count <= 1'd0; - litedramcore_postponer_req_o <= 1'd1; + main_litedramcore_postponer_req_o <= 1'd0; + if (main_litedramcore_postponer_req_i) begin + main_litedramcore_postponer_count <= (main_litedramcore_postponer_count - 1'd1); + if ((main_litedramcore_postponer_count == 1'd0)) begin + main_litedramcore_postponer_count <= 1'd0; + main_litedramcore_postponer_req_o <= 1'd1; end end - if (litedramcore_sequencer_start0) begin - litedramcore_sequencer_count <= 1'd0; + if (main_litedramcore_sequencer_start0) begin + main_litedramcore_sequencer_count <= 1'd0; end else begin - if (litedramcore_sequencer_done1) begin - if ((litedramcore_sequencer_count != 1'd0)) begin - litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); - end - end - end - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_sequencer_done1 <= 1'd0; - if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_sequencer_counter == 2'd3)) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd1; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd0; - end - if ((litedramcore_sequencer_counter == 6'd55)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_sequencer_done1 <= 1'd1; - end - if ((litedramcore_sequencer_counter == 6'd55)) begin - litedramcore_sequencer_counter <= 1'd0; + if (main_litedramcore_sequencer_done1) begin + if ((main_litedramcore_sequencer_count != 1'd0)) begin + main_litedramcore_sequencer_count <= (main_litedramcore_sequencer_count - 1'd1); + end + end + end + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd0; + if ((main_litedramcore_sequencer_start1 & (main_litedramcore_sequencer_trigger == 1'd0))) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_sequencer_trigger == 2'd3)) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd1; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd0; + end + if ((main_litedramcore_sequencer_trigger == 6'd55)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd1; + end + if ((main_litedramcore_sequencer_trigger == 6'd55)) begin + main_litedramcore_sequencer_trigger <= 1'd0; end else begin - if ((litedramcore_sequencer_counter != 1'd0)) begin - litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1); + if ((main_litedramcore_sequencer_trigger != 1'd0)) begin + main_litedramcore_sequencer_trigger <= (main_litedramcore_sequencer_trigger + 1'd1); end else begin - if (litedramcore_sequencer_start1) begin - litedramcore_sequencer_counter <= 1'd1; + if (main_litedramcore_sequencer_start1) begin + main_litedramcore_sequencer_trigger <= 1'd1; end end end - if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin - litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); + if ((main_litedramcore_zqcs_timer_wait & (~main_litedramcore_zqcs_timer_done0))) begin + main_litedramcore_zqcs_timer_count1 <= (main_litedramcore_zqcs_timer_count1 - 1'd1); end else begin - litedramcore_zqcs_timer_count1 <= 27'd99999999; - end - litedramcore_zqcs_executer_done <= 1'd0; - if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 2'd3)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 5'd19)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_zqcs_executer_done <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 5'd19)) begin - litedramcore_zqcs_executer_counter <= 1'd0; + main_litedramcore_zqcs_timer_count1 <= 27'd99999999; + end + main_litedramcore_zqcs_executer_done <= 1'd0; + if ((main_litedramcore_zqcs_executer_start & (main_litedramcore_zqcs_executer_trigger == 1'd0))) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_trigger == 2'd3)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_trigger == 5'd19)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_zqcs_executer_done <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_trigger == 5'd19)) begin + main_litedramcore_zqcs_executer_trigger <= 1'd0; end else begin - if ((litedramcore_zqcs_executer_counter != 1'd0)) begin - litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1); + if ((main_litedramcore_zqcs_executer_trigger != 1'd0)) begin + main_litedramcore_zqcs_executer_trigger <= (main_litedramcore_zqcs_executer_trigger + 1'd1); end else begin - if (litedramcore_zqcs_executer_start) begin - litedramcore_zqcs_executer_counter <= 1'd1; + if (main_litedramcore_zqcs_executer_start) begin + main_litedramcore_zqcs_executer_trigger <= 1'd1; end end end - litedramcore_refresher_state <= litedramcore_refresher_next_state; - if (litedramcore_bankmachine0_row_close) begin - litedramcore_bankmachine0_row_opened <= 1'd0; + builder_refresher_state <= builder_refresher_next_state; + if (main_litedramcore_bankmachine0_row_close) begin + main_litedramcore_bankmachine0_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine0_row_open) begin - litedramcore_bankmachine0_row_opened <= 1'd1; - litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine0_row_open) begin + main_litedramcore_bankmachine0_row_opened <= 1'd1; + main_litedramcore_bankmachine0_row <= main_litedramcore_bankmachine0_source_source_payload_addr[21:7]; end end - if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin - litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1); + if (((main_litedramcore_bankmachine0_syncfifo0_we & main_litedramcore_bankmachine0_syncfifo0_writable) & (~main_litedramcore_bankmachine0_replace))) begin + main_litedramcore_bankmachine0_produce <= (main_litedramcore_bankmachine0_produce + 1'd1); end - if (litedramcore_bankmachine0_do_read) begin - litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1); + if (main_litedramcore_bankmachine0_do_read) begin + main_litedramcore_bankmachine0_consume <= (main_litedramcore_bankmachine0_consume + 1'd1); end - if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin - if ((~litedramcore_bankmachine0_do_read)) begin - litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1); + if (((main_litedramcore_bankmachine0_syncfifo0_we & main_litedramcore_bankmachine0_syncfifo0_writable) & (~main_litedramcore_bankmachine0_replace))) begin + if ((~main_litedramcore_bankmachine0_do_read)) begin + main_litedramcore_bankmachine0_level <= (main_litedramcore_bankmachine0_level + 1'd1); end end else begin - if (litedramcore_bankmachine0_do_read) begin - litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1); + if (main_litedramcore_bankmachine0_do_read) begin + main_litedramcore_bankmachine0_level <= (main_litedramcore_bankmachine0_level - 1'd1); end end - if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin - litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid; - litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first; - litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last; - litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we; - litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine0_pipe_valid_source_valid) | main_litedramcore_bankmachine0_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine0_pipe_valid_source_valid <= main_litedramcore_bankmachine0_pipe_valid_sink_valid; + main_litedramcore_bankmachine0_pipe_valid_source_first <= main_litedramcore_bankmachine0_pipe_valid_sink_first; + main_litedramcore_bankmachine0_pipe_valid_source_last <= main_litedramcore_bankmachine0_pipe_valid_sink_last; + main_litedramcore_bankmachine0_pipe_valid_source_payload_we <= main_litedramcore_bankmachine0_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine0_twtpcon_valid) begin - litedramcore_bankmachine0_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine0_twtpcon_valid) begin + main_litedramcore_bankmachine0_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine0_twtpcon_ready)) begin - litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_twtpcon_ready)) begin + main_litedramcore_bankmachine0_twtpcon_count <= (main_litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine0_trccon_valid) begin - litedramcore_bankmachine0_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine0_trccon_valid) begin + main_litedramcore_bankmachine0_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine0_trccon_ready <= 1'd1; + main_litedramcore_bankmachine0_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine0_trccon_ready <= 1'd0; + main_litedramcore_bankmachine0_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine0_trccon_ready)) begin - litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); - if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin - litedramcore_bankmachine0_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_trccon_ready)) begin + main_litedramcore_bankmachine0_trccon_count <= (main_litedramcore_bankmachine0_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine0_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine0_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine0_trascon_valid) begin - litedramcore_bankmachine0_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine0_trascon_valid) begin + main_litedramcore_bankmachine0_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine0_trascon_ready <= 1'd1; + main_litedramcore_bankmachine0_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine0_trascon_ready <= 1'd0; + main_litedramcore_bankmachine0_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); - if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin - litedramcore_bankmachine0_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_trascon_count <= (main_litedramcore_bankmachine0_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine0_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine0_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state; - if (litedramcore_bankmachine1_row_close) begin - litedramcore_bankmachine1_row_opened <= 1'd0; + builder_bankmachine0_state <= builder_bankmachine0_next_state; + if (main_litedramcore_bankmachine1_row_close) begin + main_litedramcore_bankmachine1_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine1_row_open) begin - litedramcore_bankmachine1_row_opened <= 1'd1; - litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine1_row_open) begin + main_litedramcore_bankmachine1_row_opened <= 1'd1; + main_litedramcore_bankmachine1_row <= main_litedramcore_bankmachine1_source_source_payload_addr[21:7]; end end - if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin - litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1); + if (((main_litedramcore_bankmachine1_syncfifo1_we & main_litedramcore_bankmachine1_syncfifo1_writable) & (~main_litedramcore_bankmachine1_replace))) begin + main_litedramcore_bankmachine1_produce <= (main_litedramcore_bankmachine1_produce + 1'd1); end - if (litedramcore_bankmachine1_do_read) begin - litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1); + if (main_litedramcore_bankmachine1_do_read) begin + main_litedramcore_bankmachine1_consume <= (main_litedramcore_bankmachine1_consume + 1'd1); end - if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin - if ((~litedramcore_bankmachine1_do_read)) begin - litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1); + if (((main_litedramcore_bankmachine1_syncfifo1_we & main_litedramcore_bankmachine1_syncfifo1_writable) & (~main_litedramcore_bankmachine1_replace))) begin + if ((~main_litedramcore_bankmachine1_do_read)) begin + main_litedramcore_bankmachine1_level <= (main_litedramcore_bankmachine1_level + 1'd1); end end else begin - if (litedramcore_bankmachine1_do_read) begin - litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1); + if (main_litedramcore_bankmachine1_do_read) begin + main_litedramcore_bankmachine1_level <= (main_litedramcore_bankmachine1_level - 1'd1); end end - if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin - litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid; - litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first; - litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last; - litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we; - litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine1_pipe_valid_source_valid) | main_litedramcore_bankmachine1_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine1_pipe_valid_source_valid <= main_litedramcore_bankmachine1_pipe_valid_sink_valid; + main_litedramcore_bankmachine1_pipe_valid_source_first <= main_litedramcore_bankmachine1_pipe_valid_sink_first; + main_litedramcore_bankmachine1_pipe_valid_source_last <= main_litedramcore_bankmachine1_pipe_valid_sink_last; + main_litedramcore_bankmachine1_pipe_valid_source_payload_we <= main_litedramcore_bankmachine1_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine1_twtpcon_valid) begin - litedramcore_bankmachine1_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine1_twtpcon_valid) begin + main_litedramcore_bankmachine1_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine1_twtpcon_ready)) begin - litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_twtpcon_ready)) begin + main_litedramcore_bankmachine1_twtpcon_count <= (main_litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine1_trccon_valid) begin - litedramcore_bankmachine1_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine1_trccon_valid) begin + main_litedramcore_bankmachine1_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine1_trccon_ready <= 1'd1; + main_litedramcore_bankmachine1_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine1_trccon_ready <= 1'd0; + main_litedramcore_bankmachine1_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine1_trccon_ready)) begin - litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); - if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin - litedramcore_bankmachine1_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_trccon_ready)) begin + main_litedramcore_bankmachine1_trccon_count <= (main_litedramcore_bankmachine1_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine1_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine1_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine1_trascon_valid) begin - litedramcore_bankmachine1_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine1_trascon_valid) begin + main_litedramcore_bankmachine1_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine1_trascon_ready <= 1'd1; + main_litedramcore_bankmachine1_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine1_trascon_ready <= 1'd0; + main_litedramcore_bankmachine1_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); - if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin - litedramcore_bankmachine1_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_trascon_count <= (main_litedramcore_bankmachine1_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine1_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine1_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state; - if (litedramcore_bankmachine2_row_close) begin - litedramcore_bankmachine2_row_opened <= 1'd0; + builder_bankmachine1_state <= builder_bankmachine1_next_state; + if (main_litedramcore_bankmachine2_row_close) begin + main_litedramcore_bankmachine2_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine2_row_open) begin - litedramcore_bankmachine2_row_opened <= 1'd1; - litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine2_row_open) begin + main_litedramcore_bankmachine2_row_opened <= 1'd1; + main_litedramcore_bankmachine2_row <= main_litedramcore_bankmachine2_source_source_payload_addr[21:7]; end end - if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin - litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1); + if (((main_litedramcore_bankmachine2_syncfifo2_we & main_litedramcore_bankmachine2_syncfifo2_writable) & (~main_litedramcore_bankmachine2_replace))) begin + main_litedramcore_bankmachine2_produce <= (main_litedramcore_bankmachine2_produce + 1'd1); end - if (litedramcore_bankmachine2_do_read) begin - litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1); + if (main_litedramcore_bankmachine2_do_read) begin + main_litedramcore_bankmachine2_consume <= (main_litedramcore_bankmachine2_consume + 1'd1); end - if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin - if ((~litedramcore_bankmachine2_do_read)) begin - litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1); + if (((main_litedramcore_bankmachine2_syncfifo2_we & main_litedramcore_bankmachine2_syncfifo2_writable) & (~main_litedramcore_bankmachine2_replace))) begin + if ((~main_litedramcore_bankmachine2_do_read)) begin + main_litedramcore_bankmachine2_level <= (main_litedramcore_bankmachine2_level + 1'd1); end end else begin - if (litedramcore_bankmachine2_do_read) begin - litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1); + if (main_litedramcore_bankmachine2_do_read) begin + main_litedramcore_bankmachine2_level <= (main_litedramcore_bankmachine2_level - 1'd1); end end - if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin - litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid; - litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first; - litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last; - litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we; - litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine2_pipe_valid_source_valid) | main_litedramcore_bankmachine2_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine2_pipe_valid_source_valid <= main_litedramcore_bankmachine2_pipe_valid_sink_valid; + main_litedramcore_bankmachine2_pipe_valid_source_first <= main_litedramcore_bankmachine2_pipe_valid_sink_first; + main_litedramcore_bankmachine2_pipe_valid_source_last <= main_litedramcore_bankmachine2_pipe_valid_sink_last; + main_litedramcore_bankmachine2_pipe_valid_source_payload_we <= main_litedramcore_bankmachine2_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine2_twtpcon_valid) begin - litedramcore_bankmachine2_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine2_twtpcon_valid) begin + main_litedramcore_bankmachine2_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine2_twtpcon_ready)) begin - litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_twtpcon_ready)) begin + main_litedramcore_bankmachine2_twtpcon_count <= (main_litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine2_trccon_valid) begin - litedramcore_bankmachine2_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine2_trccon_valid) begin + main_litedramcore_bankmachine2_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine2_trccon_ready <= 1'd1; + main_litedramcore_bankmachine2_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine2_trccon_ready <= 1'd0; + main_litedramcore_bankmachine2_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine2_trccon_ready)) begin - litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); - if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin - litedramcore_bankmachine2_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_trccon_ready)) begin + main_litedramcore_bankmachine2_trccon_count <= (main_litedramcore_bankmachine2_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine2_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine2_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine2_trascon_valid) begin - litedramcore_bankmachine2_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine2_trascon_valid) begin + main_litedramcore_bankmachine2_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine2_trascon_ready <= 1'd1; + main_litedramcore_bankmachine2_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine2_trascon_ready <= 1'd0; + main_litedramcore_bankmachine2_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); - if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin - litedramcore_bankmachine2_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_trascon_count <= (main_litedramcore_bankmachine2_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine2_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine2_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state; - if (litedramcore_bankmachine3_row_close) begin - litedramcore_bankmachine3_row_opened <= 1'd0; + builder_bankmachine2_state <= builder_bankmachine2_next_state; + if (main_litedramcore_bankmachine3_row_close) begin + main_litedramcore_bankmachine3_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine3_row_open) begin - litedramcore_bankmachine3_row_opened <= 1'd1; - litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine3_row_open) begin + main_litedramcore_bankmachine3_row_opened <= 1'd1; + main_litedramcore_bankmachine3_row <= main_litedramcore_bankmachine3_source_source_payload_addr[21:7]; end end - if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin - litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1); + if (((main_litedramcore_bankmachine3_syncfifo3_we & main_litedramcore_bankmachine3_syncfifo3_writable) & (~main_litedramcore_bankmachine3_replace))) begin + main_litedramcore_bankmachine3_produce <= (main_litedramcore_bankmachine3_produce + 1'd1); end - if (litedramcore_bankmachine3_do_read) begin - litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1); + if (main_litedramcore_bankmachine3_do_read) begin + main_litedramcore_bankmachine3_consume <= (main_litedramcore_bankmachine3_consume + 1'd1); end - if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin - if ((~litedramcore_bankmachine3_do_read)) begin - litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1); + if (((main_litedramcore_bankmachine3_syncfifo3_we & main_litedramcore_bankmachine3_syncfifo3_writable) & (~main_litedramcore_bankmachine3_replace))) begin + if ((~main_litedramcore_bankmachine3_do_read)) begin + main_litedramcore_bankmachine3_level <= (main_litedramcore_bankmachine3_level + 1'd1); end end else begin - if (litedramcore_bankmachine3_do_read) begin - litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1); + if (main_litedramcore_bankmachine3_do_read) begin + main_litedramcore_bankmachine3_level <= (main_litedramcore_bankmachine3_level - 1'd1); end end - if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin - litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid; - litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first; - litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last; - litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we; - litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine3_pipe_valid_source_valid) | main_litedramcore_bankmachine3_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine3_pipe_valid_source_valid <= main_litedramcore_bankmachine3_pipe_valid_sink_valid; + main_litedramcore_bankmachine3_pipe_valid_source_first <= main_litedramcore_bankmachine3_pipe_valid_sink_first; + main_litedramcore_bankmachine3_pipe_valid_source_last <= main_litedramcore_bankmachine3_pipe_valid_sink_last; + main_litedramcore_bankmachine3_pipe_valid_source_payload_we <= main_litedramcore_bankmachine3_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine3_twtpcon_valid) begin - litedramcore_bankmachine3_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine3_twtpcon_valid) begin + main_litedramcore_bankmachine3_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine3_twtpcon_ready)) begin - litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_twtpcon_ready)) begin + main_litedramcore_bankmachine3_twtpcon_count <= (main_litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine3_trccon_valid) begin - litedramcore_bankmachine3_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine3_trccon_valid) begin + main_litedramcore_bankmachine3_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine3_trccon_ready <= 1'd1; + main_litedramcore_bankmachine3_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine3_trccon_ready <= 1'd0; + main_litedramcore_bankmachine3_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine3_trccon_ready)) begin - litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); - if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin - litedramcore_bankmachine3_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_trccon_ready)) begin + main_litedramcore_bankmachine3_trccon_count <= (main_litedramcore_bankmachine3_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine3_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine3_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine3_trascon_valid) begin - litedramcore_bankmachine3_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine3_trascon_valid) begin + main_litedramcore_bankmachine3_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine3_trascon_ready <= 1'd1; + main_litedramcore_bankmachine3_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine3_trascon_ready <= 1'd0; + main_litedramcore_bankmachine3_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); - if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin - litedramcore_bankmachine3_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_trascon_count <= (main_litedramcore_bankmachine3_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine3_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine3_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state; - if (litedramcore_bankmachine4_row_close) begin - litedramcore_bankmachine4_row_opened <= 1'd0; + builder_bankmachine3_state <= builder_bankmachine3_next_state; + if (main_litedramcore_bankmachine4_row_close) begin + main_litedramcore_bankmachine4_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine4_row_open) begin - litedramcore_bankmachine4_row_opened <= 1'd1; - litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine4_row_open) begin + main_litedramcore_bankmachine4_row_opened <= 1'd1; + main_litedramcore_bankmachine4_row <= main_litedramcore_bankmachine4_source_source_payload_addr[21:7]; end end - if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin - litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1); + if (((main_litedramcore_bankmachine4_syncfifo4_we & main_litedramcore_bankmachine4_syncfifo4_writable) & (~main_litedramcore_bankmachine4_replace))) begin + main_litedramcore_bankmachine4_produce <= (main_litedramcore_bankmachine4_produce + 1'd1); end - if (litedramcore_bankmachine4_do_read) begin - litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1); + if (main_litedramcore_bankmachine4_do_read) begin + main_litedramcore_bankmachine4_consume <= (main_litedramcore_bankmachine4_consume + 1'd1); end - if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin - if ((~litedramcore_bankmachine4_do_read)) begin - litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1); + if (((main_litedramcore_bankmachine4_syncfifo4_we & main_litedramcore_bankmachine4_syncfifo4_writable) & (~main_litedramcore_bankmachine4_replace))) begin + if ((~main_litedramcore_bankmachine4_do_read)) begin + main_litedramcore_bankmachine4_level <= (main_litedramcore_bankmachine4_level + 1'd1); end end else begin - if (litedramcore_bankmachine4_do_read) begin - litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1); + if (main_litedramcore_bankmachine4_do_read) begin + main_litedramcore_bankmachine4_level <= (main_litedramcore_bankmachine4_level - 1'd1); end end - if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin - litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid; - litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first; - litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last; - litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we; - litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine4_pipe_valid_source_valid) | main_litedramcore_bankmachine4_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine4_pipe_valid_source_valid <= main_litedramcore_bankmachine4_pipe_valid_sink_valid; + main_litedramcore_bankmachine4_pipe_valid_source_first <= main_litedramcore_bankmachine4_pipe_valid_sink_first; + main_litedramcore_bankmachine4_pipe_valid_source_last <= main_litedramcore_bankmachine4_pipe_valid_sink_last; + main_litedramcore_bankmachine4_pipe_valid_source_payload_we <= main_litedramcore_bankmachine4_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine4_twtpcon_valid) begin - litedramcore_bankmachine4_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine4_twtpcon_valid) begin + main_litedramcore_bankmachine4_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine4_twtpcon_ready)) begin - litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_twtpcon_ready)) begin + main_litedramcore_bankmachine4_twtpcon_count <= (main_litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine4_trccon_valid) begin - litedramcore_bankmachine4_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine4_trccon_valid) begin + main_litedramcore_bankmachine4_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine4_trccon_ready <= 1'd1; + main_litedramcore_bankmachine4_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine4_trccon_ready <= 1'd0; + main_litedramcore_bankmachine4_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine4_trccon_ready)) begin - litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); - if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin - litedramcore_bankmachine4_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_trccon_ready)) begin + main_litedramcore_bankmachine4_trccon_count <= (main_litedramcore_bankmachine4_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine4_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine4_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine4_trascon_valid) begin - litedramcore_bankmachine4_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine4_trascon_valid) begin + main_litedramcore_bankmachine4_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine4_trascon_ready <= 1'd1; + main_litedramcore_bankmachine4_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine4_trascon_ready <= 1'd0; + main_litedramcore_bankmachine4_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); - if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin - litedramcore_bankmachine4_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_trascon_count <= (main_litedramcore_bankmachine4_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine4_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine4_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state; - if (litedramcore_bankmachine5_row_close) begin - litedramcore_bankmachine5_row_opened <= 1'd0; + builder_bankmachine4_state <= builder_bankmachine4_next_state; + if (main_litedramcore_bankmachine5_row_close) begin + main_litedramcore_bankmachine5_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine5_row_open) begin - litedramcore_bankmachine5_row_opened <= 1'd1; - litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine5_row_open) begin + main_litedramcore_bankmachine5_row_opened <= 1'd1; + main_litedramcore_bankmachine5_row <= main_litedramcore_bankmachine5_source_source_payload_addr[21:7]; end end - if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin - litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1); + if (((main_litedramcore_bankmachine5_syncfifo5_we & main_litedramcore_bankmachine5_syncfifo5_writable) & (~main_litedramcore_bankmachine5_replace))) begin + main_litedramcore_bankmachine5_produce <= (main_litedramcore_bankmachine5_produce + 1'd1); end - if (litedramcore_bankmachine5_do_read) begin - litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1); + if (main_litedramcore_bankmachine5_do_read) begin + main_litedramcore_bankmachine5_consume <= (main_litedramcore_bankmachine5_consume + 1'd1); end - if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin - if ((~litedramcore_bankmachine5_do_read)) begin - litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1); + if (((main_litedramcore_bankmachine5_syncfifo5_we & main_litedramcore_bankmachine5_syncfifo5_writable) & (~main_litedramcore_bankmachine5_replace))) begin + if ((~main_litedramcore_bankmachine5_do_read)) begin + main_litedramcore_bankmachine5_level <= (main_litedramcore_bankmachine5_level + 1'd1); end end else begin - if (litedramcore_bankmachine5_do_read) begin - litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1); + if (main_litedramcore_bankmachine5_do_read) begin + main_litedramcore_bankmachine5_level <= (main_litedramcore_bankmachine5_level - 1'd1); end end - if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin - litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid; - litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first; - litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last; - litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we; - litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine5_pipe_valid_source_valid) | main_litedramcore_bankmachine5_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine5_pipe_valid_source_valid <= main_litedramcore_bankmachine5_pipe_valid_sink_valid; + main_litedramcore_bankmachine5_pipe_valid_source_first <= main_litedramcore_bankmachine5_pipe_valid_sink_first; + main_litedramcore_bankmachine5_pipe_valid_source_last <= main_litedramcore_bankmachine5_pipe_valid_sink_last; + main_litedramcore_bankmachine5_pipe_valid_source_payload_we <= main_litedramcore_bankmachine5_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine5_twtpcon_valid) begin - litedramcore_bankmachine5_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine5_twtpcon_valid) begin + main_litedramcore_bankmachine5_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine5_twtpcon_ready)) begin - litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_twtpcon_ready)) begin + main_litedramcore_bankmachine5_twtpcon_count <= (main_litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine5_trccon_valid) begin - litedramcore_bankmachine5_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine5_trccon_valid) begin + main_litedramcore_bankmachine5_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine5_trccon_ready <= 1'd1; + main_litedramcore_bankmachine5_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine5_trccon_ready <= 1'd0; + main_litedramcore_bankmachine5_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine5_trccon_ready)) begin - litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); - if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin - litedramcore_bankmachine5_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_trccon_ready)) begin + main_litedramcore_bankmachine5_trccon_count <= (main_litedramcore_bankmachine5_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine5_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine5_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine5_trascon_valid) begin - litedramcore_bankmachine5_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine5_trascon_valid) begin + main_litedramcore_bankmachine5_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine5_trascon_ready <= 1'd1; + main_litedramcore_bankmachine5_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine5_trascon_ready <= 1'd0; + main_litedramcore_bankmachine5_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); - if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin - litedramcore_bankmachine5_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_trascon_count <= (main_litedramcore_bankmachine5_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine5_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine5_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state; - if (litedramcore_bankmachine6_row_close) begin - litedramcore_bankmachine6_row_opened <= 1'd0; + builder_bankmachine5_state <= builder_bankmachine5_next_state; + if (main_litedramcore_bankmachine6_row_close) begin + main_litedramcore_bankmachine6_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine6_row_open) begin - litedramcore_bankmachine6_row_opened <= 1'd1; - litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine6_row_open) begin + main_litedramcore_bankmachine6_row_opened <= 1'd1; + main_litedramcore_bankmachine6_row <= main_litedramcore_bankmachine6_source_source_payload_addr[21:7]; end end - if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin - litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1); + if (((main_litedramcore_bankmachine6_syncfifo6_we & main_litedramcore_bankmachine6_syncfifo6_writable) & (~main_litedramcore_bankmachine6_replace))) begin + main_litedramcore_bankmachine6_produce <= (main_litedramcore_bankmachine6_produce + 1'd1); end - if (litedramcore_bankmachine6_do_read) begin - litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1); + if (main_litedramcore_bankmachine6_do_read) begin + main_litedramcore_bankmachine6_consume <= (main_litedramcore_bankmachine6_consume + 1'd1); end - if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin - if ((~litedramcore_bankmachine6_do_read)) begin - litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1); + if (((main_litedramcore_bankmachine6_syncfifo6_we & main_litedramcore_bankmachine6_syncfifo6_writable) & (~main_litedramcore_bankmachine6_replace))) begin + if ((~main_litedramcore_bankmachine6_do_read)) begin + main_litedramcore_bankmachine6_level <= (main_litedramcore_bankmachine6_level + 1'd1); end end else begin - if (litedramcore_bankmachine6_do_read) begin - litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1); + if (main_litedramcore_bankmachine6_do_read) begin + main_litedramcore_bankmachine6_level <= (main_litedramcore_bankmachine6_level - 1'd1); end end - if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin - litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid; - litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first; - litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last; - litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we; - litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine6_pipe_valid_source_valid) | main_litedramcore_bankmachine6_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine6_pipe_valid_source_valid <= main_litedramcore_bankmachine6_pipe_valid_sink_valid; + main_litedramcore_bankmachine6_pipe_valid_source_first <= main_litedramcore_bankmachine6_pipe_valid_sink_first; + main_litedramcore_bankmachine6_pipe_valid_source_last <= main_litedramcore_bankmachine6_pipe_valid_sink_last; + main_litedramcore_bankmachine6_pipe_valid_source_payload_we <= main_litedramcore_bankmachine6_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine6_twtpcon_valid) begin - litedramcore_bankmachine6_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine6_twtpcon_valid) begin + main_litedramcore_bankmachine6_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine6_twtpcon_ready)) begin - litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_twtpcon_ready)) begin + main_litedramcore_bankmachine6_twtpcon_count <= (main_litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine6_trccon_valid) begin - litedramcore_bankmachine6_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine6_trccon_valid) begin + main_litedramcore_bankmachine6_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine6_trccon_ready <= 1'd1; + main_litedramcore_bankmachine6_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine6_trccon_ready <= 1'd0; + main_litedramcore_bankmachine6_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine6_trccon_ready)) begin - litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); - if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin - litedramcore_bankmachine6_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_trccon_ready)) begin + main_litedramcore_bankmachine6_trccon_count <= (main_litedramcore_bankmachine6_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine6_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine6_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine6_trascon_valid) begin - litedramcore_bankmachine6_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine6_trascon_valid) begin + main_litedramcore_bankmachine6_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine6_trascon_ready <= 1'd1; + main_litedramcore_bankmachine6_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine6_trascon_ready <= 1'd0; + main_litedramcore_bankmachine6_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); - if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin - litedramcore_bankmachine6_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_trascon_count <= (main_litedramcore_bankmachine6_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine6_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine6_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state; - if (litedramcore_bankmachine7_row_close) begin - litedramcore_bankmachine7_row_opened <= 1'd0; + builder_bankmachine6_state <= builder_bankmachine6_next_state; + if (main_litedramcore_bankmachine7_row_close) begin + main_litedramcore_bankmachine7_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine7_row_open) begin - litedramcore_bankmachine7_row_opened <= 1'd1; - litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine7_row_open) begin + main_litedramcore_bankmachine7_row_opened <= 1'd1; + main_litedramcore_bankmachine7_row <= main_litedramcore_bankmachine7_source_source_payload_addr[21:7]; end end - if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin - litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1); + if (((main_litedramcore_bankmachine7_syncfifo7_we & main_litedramcore_bankmachine7_syncfifo7_writable) & (~main_litedramcore_bankmachine7_replace))) begin + main_litedramcore_bankmachine7_produce <= (main_litedramcore_bankmachine7_produce + 1'd1); end - if (litedramcore_bankmachine7_do_read) begin - litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1); + if (main_litedramcore_bankmachine7_do_read) begin + main_litedramcore_bankmachine7_consume <= (main_litedramcore_bankmachine7_consume + 1'd1); end - if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin - if ((~litedramcore_bankmachine7_do_read)) begin - litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1); + if (((main_litedramcore_bankmachine7_syncfifo7_we & main_litedramcore_bankmachine7_syncfifo7_writable) & (~main_litedramcore_bankmachine7_replace))) begin + if ((~main_litedramcore_bankmachine7_do_read)) begin + main_litedramcore_bankmachine7_level <= (main_litedramcore_bankmachine7_level + 1'd1); end end else begin - if (litedramcore_bankmachine7_do_read) begin - litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1); + if (main_litedramcore_bankmachine7_do_read) begin + main_litedramcore_bankmachine7_level <= (main_litedramcore_bankmachine7_level - 1'd1); end end - if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin - litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid; - litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first; - litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last; - litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we; - litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine7_pipe_valid_source_valid) | main_litedramcore_bankmachine7_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine7_pipe_valid_source_valid <= main_litedramcore_bankmachine7_pipe_valid_sink_valid; + main_litedramcore_bankmachine7_pipe_valid_source_first <= main_litedramcore_bankmachine7_pipe_valid_sink_first; + main_litedramcore_bankmachine7_pipe_valid_source_last <= main_litedramcore_bankmachine7_pipe_valid_sink_last; + main_litedramcore_bankmachine7_pipe_valid_source_payload_we <= main_litedramcore_bankmachine7_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine7_twtpcon_valid) begin - litedramcore_bankmachine7_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine7_twtpcon_valid) begin + main_litedramcore_bankmachine7_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine7_twtpcon_ready)) begin - litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_twtpcon_ready)) begin + main_litedramcore_bankmachine7_twtpcon_count <= (main_litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine7_trccon_valid) begin - litedramcore_bankmachine7_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine7_trccon_valid) begin + main_litedramcore_bankmachine7_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine7_trccon_ready <= 1'd1; + main_litedramcore_bankmachine7_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine7_trccon_ready <= 1'd0; + main_litedramcore_bankmachine7_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine7_trccon_ready)) begin - litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); - if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin - litedramcore_bankmachine7_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_trccon_ready)) begin + main_litedramcore_bankmachine7_trccon_count <= (main_litedramcore_bankmachine7_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine7_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine7_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine7_trascon_valid) begin - litedramcore_bankmachine7_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine7_trascon_valid) begin + main_litedramcore_bankmachine7_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine7_trascon_ready <= 1'd1; + main_litedramcore_bankmachine7_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine7_trascon_ready <= 1'd0; + main_litedramcore_bankmachine7_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); - if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin - litedramcore_bankmachine7_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_trascon_count <= (main_litedramcore_bankmachine7_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine7_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine7_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state; - if ((~litedramcore_en0)) begin - litedramcore_time0 <= 5'd31; + builder_bankmachine7_state <= builder_bankmachine7_next_state; + if ((~main_litedramcore_en0)) begin + main_litedramcore_time0 <= 5'd31; end else begin - if ((~litedramcore_max_time0)) begin - litedramcore_time0 <= (litedramcore_time0 - 1'd1); + if ((~main_litedramcore_max_time0)) begin + main_litedramcore_time0 <= (main_litedramcore_time0 - 1'd1); end end - if ((~litedramcore_en1)) begin - litedramcore_time1 <= 4'd15; + if ((~main_litedramcore_en1)) begin + main_litedramcore_time1 <= 4'd15; end else begin - if ((~litedramcore_max_time1)) begin - litedramcore_time1 <= (litedramcore_time1 - 1'd1); + if ((~main_litedramcore_max_time1)) begin + main_litedramcore_time1 <= (main_litedramcore_time1 - 1'd1); end end - if (litedramcore_choose_cmd_ce) begin - case (litedramcore_choose_cmd_grant) + if (main_litedramcore_choose_cmd_ce) begin + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end end end @@ -14958,26 +15546,26 @@ always @(posedge sys_clk) begin end end 1'd1: begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end end end @@ -14987,26 +15575,26 @@ always @(posedge sys_clk) begin end end 2'd2: begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end end end @@ -15016,26 +15604,26 @@ always @(posedge sys_clk) begin end end 2'd3: begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end end end @@ -15045,26 +15633,26 @@ always @(posedge sys_clk) begin end end 3'd4: begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end end end @@ -15074,26 +15662,26 @@ always @(posedge sys_clk) begin end end 3'd5: begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end end end @@ -15103,26 +15691,26 @@ always @(posedge sys_clk) begin end end 3'd6: begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end end end @@ -15132,26 +15720,26 @@ always @(posedge sys_clk) begin end end 3'd7: begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end end end @@ -15162,29 +15750,29 @@ always @(posedge sys_clk) begin end endcase end - if (litedramcore_choose_req_ce) begin - case (litedramcore_choose_req_grant) + if (main_litedramcore_choose_req_ce) begin + case (main_litedramcore_choose_req_grant) 1'd0: begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end end end @@ -15194,26 +15782,26 @@ always @(posedge sys_clk) begin end end 1'd1: begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end end end @@ -15223,26 +15811,26 @@ always @(posedge sys_clk) begin end end 2'd2: begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end end end @@ -15252,26 +15840,26 @@ always @(posedge sys_clk) begin end end 2'd3: begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end end end @@ -15281,26 +15869,26 @@ always @(posedge sys_clk) begin end end 3'd4: begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end end end @@ -15310,26 +15898,26 @@ always @(posedge sys_clk) begin end end 3'd5: begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end end end @@ -15339,26 +15927,26 @@ always @(posedge sys_clk) begin end end 3'd6: begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end end end @@ -15368,26 +15956,26 @@ always @(posedge sys_clk) begin end end 3'd7: begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end end end @@ -15398,733 +15986,733 @@ always @(posedge sys_clk) begin end endcase end - litedramcore_dfi_p0_cs_n <= 1'd0; - litedramcore_dfi_p0_bank <= array_muxed0; - litedramcore_dfi_p0_address <= array_muxed1; - litedramcore_dfi_p0_cas_n <= (~array_muxed2); - litedramcore_dfi_p0_ras_n <= (~array_muxed3); - litedramcore_dfi_p0_we_n <= (~array_muxed4); - litedramcore_dfi_p0_rddata_en <= array_muxed5; - litedramcore_dfi_p0_wrdata_en <= array_muxed6; - litedramcore_dfi_p1_cs_n <= 1'd0; - litedramcore_dfi_p1_bank <= array_muxed7; - litedramcore_dfi_p1_address <= array_muxed8; - litedramcore_dfi_p1_cas_n <= (~array_muxed9); - litedramcore_dfi_p1_ras_n <= (~array_muxed10); - litedramcore_dfi_p1_we_n <= (~array_muxed11); - litedramcore_dfi_p1_rddata_en <= array_muxed12; - litedramcore_dfi_p1_wrdata_en <= array_muxed13; - litedramcore_dfi_p2_cs_n <= 1'd0; - litedramcore_dfi_p2_bank <= array_muxed14; - litedramcore_dfi_p2_address <= array_muxed15; - litedramcore_dfi_p2_cas_n <= (~array_muxed16); - litedramcore_dfi_p2_ras_n <= (~array_muxed17); - litedramcore_dfi_p2_we_n <= (~array_muxed18); - litedramcore_dfi_p2_rddata_en <= array_muxed19; - litedramcore_dfi_p2_wrdata_en <= array_muxed20; - litedramcore_dfi_p3_cs_n <= 1'd0; - litedramcore_dfi_p3_bank <= array_muxed21; - litedramcore_dfi_p3_address <= array_muxed22; - litedramcore_dfi_p3_cas_n <= (~array_muxed23); - litedramcore_dfi_p3_ras_n <= (~array_muxed24); - litedramcore_dfi_p3_we_n <= (~array_muxed25); - litedramcore_dfi_p3_rddata_en <= array_muxed26; - litedramcore_dfi_p3_wrdata_en <= array_muxed27; - if (litedramcore_trrdcon_valid) begin - litedramcore_trrdcon_count <= 1'd1; + main_litedramcore_dfi_p0_cs_n <= 1'd0; + main_litedramcore_dfi_p0_bank <= builder_self0; + main_litedramcore_dfi_p0_address <= builder_self1; + main_litedramcore_dfi_p0_cas_n <= (~builder_self2); + main_litedramcore_dfi_p0_ras_n <= (~builder_self3); + main_litedramcore_dfi_p0_we_n <= (~builder_self4); + main_litedramcore_dfi_p0_rddata_en <= builder_self5; + main_litedramcore_dfi_p0_wrdata_en <= builder_self6; + main_litedramcore_dfi_p1_cs_n <= 1'd0; + main_litedramcore_dfi_p1_bank <= builder_self7; + main_litedramcore_dfi_p1_address <= builder_self8; + main_litedramcore_dfi_p1_cas_n <= (~builder_self9); + main_litedramcore_dfi_p1_ras_n <= (~builder_self10); + main_litedramcore_dfi_p1_we_n <= (~builder_self11); + main_litedramcore_dfi_p1_rddata_en <= builder_self12; + main_litedramcore_dfi_p1_wrdata_en <= builder_self13; + main_litedramcore_dfi_p2_cs_n <= 1'd0; + main_litedramcore_dfi_p2_bank <= builder_self14; + main_litedramcore_dfi_p2_address <= builder_self15; + main_litedramcore_dfi_p2_cas_n <= (~builder_self16); + main_litedramcore_dfi_p2_ras_n <= (~builder_self17); + main_litedramcore_dfi_p2_we_n <= (~builder_self18); + main_litedramcore_dfi_p2_rddata_en <= builder_self19; + main_litedramcore_dfi_p2_wrdata_en <= builder_self20; + main_litedramcore_dfi_p3_cs_n <= 1'd0; + main_litedramcore_dfi_p3_bank <= builder_self21; + main_litedramcore_dfi_p3_address <= builder_self22; + main_litedramcore_dfi_p3_cas_n <= (~builder_self23); + main_litedramcore_dfi_p3_ras_n <= (~builder_self24); + main_litedramcore_dfi_p3_we_n <= (~builder_self25); + main_litedramcore_dfi_p3_rddata_en <= builder_self26; + main_litedramcore_dfi_p3_wrdata_en <= builder_self27; + if (main_litedramcore_trrdcon_valid) begin + main_litedramcore_trrdcon_count <= 1'd1; if (1'd0) begin - litedramcore_trrdcon_ready <= 1'd1; + main_litedramcore_trrdcon_ready <= 1'd1; end else begin - litedramcore_trrdcon_ready <= 1'd0; + main_litedramcore_trrdcon_ready <= 1'd0; end end else begin - if ((~litedramcore_trrdcon_ready)) begin - litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); - if ((litedramcore_trrdcon_count == 1'd1)) begin - litedramcore_trrdcon_ready <= 1'd1; + if ((~main_litedramcore_trrdcon_ready)) begin + main_litedramcore_trrdcon_count <= (main_litedramcore_trrdcon_count - 1'd1); + if ((main_litedramcore_trrdcon_count == 1'd1)) begin + main_litedramcore_trrdcon_ready <= 1'd1; end end end - litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; - if ((litedramcore_tfawcon_count < 3'd4)) begin - if ((litedramcore_tfawcon_count == 2'd3)) begin - litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); + main_litedramcore_tfawcon_window <= {main_litedramcore_tfawcon_window, main_litedramcore_tfawcon_valid}; + if ((main_litedramcore_tfawcon_count < 3'd4)) begin + if ((main_litedramcore_tfawcon_count == 2'd3)) begin + main_litedramcore_tfawcon_ready <= (~main_litedramcore_tfawcon_valid); end else begin - litedramcore_tfawcon_ready <= 1'd1; + main_litedramcore_tfawcon_ready <= 1'd1; end end - if (litedramcore_tccdcon_valid) begin - litedramcore_tccdcon_count <= 1'd0; + if (main_litedramcore_tccdcon_valid) begin + main_litedramcore_tccdcon_count <= 1'd0; if (1'd1) begin - litedramcore_tccdcon_ready <= 1'd1; + main_litedramcore_tccdcon_ready <= 1'd1; end else begin - litedramcore_tccdcon_ready <= 1'd0; + main_litedramcore_tccdcon_ready <= 1'd0; end end else begin - if ((~litedramcore_tccdcon_ready)) begin - litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); - if ((litedramcore_tccdcon_count == 1'd1)) begin - litedramcore_tccdcon_ready <= 1'd1; + if ((~main_litedramcore_tccdcon_ready)) begin + main_litedramcore_tccdcon_count <= (main_litedramcore_tccdcon_count - 1'd1); + if ((main_litedramcore_tccdcon_count == 1'd1)) begin + main_litedramcore_tccdcon_ready <= 1'd1; end end end - if (litedramcore_twtrcon_valid) begin - litedramcore_twtrcon_count <= 3'd4; + if (main_litedramcore_twtrcon_valid) begin + main_litedramcore_twtrcon_count <= 3'd4; if (1'd0) begin - litedramcore_twtrcon_ready <= 1'd1; + main_litedramcore_twtrcon_ready <= 1'd1; end else begin - litedramcore_twtrcon_ready <= 1'd0; + main_litedramcore_twtrcon_ready <= 1'd0; end end else begin - if ((~litedramcore_twtrcon_ready)) begin - litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); - if ((litedramcore_twtrcon_count == 1'd1)) begin - litedramcore_twtrcon_ready <= 1'd1; - end - end - end - litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state; - litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); - litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0; - litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); - litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0; - litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1; - litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2; - litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3; - litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4; - litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5; - litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6; - litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7; - litedramcore_state <= litedramcore_next_state; - if (litedramcore_dat_w_next_value_ce0) begin - litedramcore_dat_w <= litedramcore_dat_w_next_value0; - end - if (litedramcore_adr_next_value_ce1) begin - litedramcore_adr <= litedramcore_adr_next_value1; - end - if (litedramcore_we_next_value_ce2) begin - litedramcore_we <= litedramcore_we_next_value2; - end - interface0_bank_bus_dat_r <= 1'd0; - if (csrbank0_sel) begin - case (interface0_bank_bus_adr[8:0]) + if ((~main_litedramcore_twtrcon_ready)) begin + main_litedramcore_twtrcon_count <= (main_litedramcore_twtrcon_count - 1'd1); + if ((main_litedramcore_twtrcon_count == 1'd1)) begin + main_litedramcore_twtrcon_ready <= 1'd1; + end + end + end + builder_multiplexer_state <= builder_multiplexer_next_state; + builder_new_master_wdata_ready0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_wdata_ready)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_wdata_ready)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_wdata_ready)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_wdata_ready)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_wdata_ready)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_wdata_ready)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_wdata_ready)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_wdata_ready)); + builder_new_master_wdata_ready1 <= builder_new_master_wdata_ready0; + builder_new_master_rdata_valid0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_rdata_valid)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_rdata_valid)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_rdata_valid)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_rdata_valid)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_rdata_valid)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_rdata_valid)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_rdata_valid)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_rdata_valid)); + builder_new_master_rdata_valid1 <= builder_new_master_rdata_valid0; + builder_new_master_rdata_valid2 <= builder_new_master_rdata_valid1; + builder_new_master_rdata_valid3 <= builder_new_master_rdata_valid2; + builder_new_master_rdata_valid4 <= builder_new_master_rdata_valid3; + builder_new_master_rdata_valid5 <= builder_new_master_rdata_valid4; + builder_new_master_rdata_valid6 <= builder_new_master_rdata_valid5; + builder_new_master_rdata_valid7 <= builder_new_master_rdata_valid6; + builder_new_master_rdata_valid8 <= builder_new_master_rdata_valid7; + builder_state <= builder_next_state; + if (builder_interface1_dat_w_next_value_ce0) begin + builder_interface1_dat_w <= builder_interface1_dat_w_next_value0; + end + if (builder_interface1_adr_next_value_ce1) begin + builder_interface1_adr <= builder_interface1_adr_next_value1; + end + if (builder_interface1_we_next_value_ce2) begin + builder_interface1_we <= builder_interface1_we_next_value2; + end + builder_interface0_bank_bus_dat_r <= 1'd0; + if (builder_csrbank0_sel) begin + case (builder_interface0_bank_bus_adr[8:0]) 1'd0: begin - interface0_bank_bus_dat_r <= csrbank0_init_done0_w; + builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_done0_w; end 1'd1: begin - interface0_bank_bus_dat_r <= csrbank0_init_error0_w; + builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_error0_w; end endcase end - if (csrbank0_init_done0_re) begin - init_done_storage <= csrbank0_init_done0_r; + if (builder_csrbank0_init_done0_re) begin + main_init_done_storage <= builder_csrbank0_init_done0_r; end - init_done_re <= csrbank0_init_done0_re; - if (csrbank0_init_error0_re) begin - init_error_storage <= csrbank0_init_error0_r; + main_init_done_re <= builder_csrbank0_init_done0_re; + if (builder_csrbank0_init_error0_re) begin + main_init_error_storage <= builder_csrbank0_init_error0_r; end - init_error_re <= csrbank0_init_error0_re; - interface1_bank_bus_dat_r <= 1'd0; - if (csrbank1_sel) begin - case (interface1_bank_bus_adr[8:0]) + main_init_error_re <= builder_csrbank0_init_error0_re; + builder_interface1_bank_bus_dat_r <= 1'd0; + if (builder_csrbank1_sel) begin + case (builder_interface1_bank_bus_adr[8:0]) 1'd0: begin - interface1_bank_bus_dat_r <= csrbank1_rst0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rst0_w; end 1'd1: begin - interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_dly_sel0_w; end 2'd2: begin - interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_half_sys8x_taps0_w; end 2'd3: begin - interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_wlevel_en0_w; end 3'd4: begin - interface1_bank_bus_dat_r <= k7ddrphy_wlevel_strobe_w; + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wlevel_strobe_w; end 3'd5: begin - interface1_bank_bus_dat_r <= k7ddrphy_cdly_rst_w; + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_cdly_rst_w; end 3'd6: begin - interface1_bank_bus_dat_r <= k7ddrphy_cdly_inc_w; + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_cdly_inc_w; end 3'd7: begin - interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_rst_w; + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_rdly_dq_rst_w; end 4'd8: begin - interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_inc_w; + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_rdly_dq_inc_w; end 4'd9: begin - interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_bitslip_rst_w; + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_rdly_dq_bitslip_rst_w; end 4'd10: begin - interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_bitslip_w; + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_rdly_dq_bitslip_w; end 4'd11: begin - interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_rst_w; + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wdly_dq_rst_w; end 4'd12: begin - interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_inc_w; + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wdly_dq_inc_w; end 4'd13: begin - interface1_bank_bus_dat_r <= k7ddrphy_wdly_dqs_rst_w; + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wdly_dqs_rst_w; end 4'd14: begin - interface1_bank_bus_dat_r <= k7ddrphy_wdly_dqs_inc_w; + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wdly_dqs_inc_w; end 4'd15: begin - interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_bitslip_rst_w; + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wdly_dq_bitslip_rst_w; end 5'd16: begin - interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_bitslip_w; + builder_interface1_bank_bus_dat_r <= main_k7ddrphy_wdly_dq_bitslip_w; end 5'd17: begin - interface1_bank_bus_dat_r <= csrbank1_rdphase0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rdphase0_w; end 5'd18: begin - interface1_bank_bus_dat_r <= csrbank1_wrphase0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_wrphase0_w; end endcase end - if (csrbank1_rst0_re) begin - k7ddrphy_rst_storage <= csrbank1_rst0_r; + if (builder_csrbank1_rst0_re) begin + main_k7ddrphy_rst_storage <= builder_csrbank1_rst0_r; end - k7ddrphy_rst_re <= csrbank1_rst0_re; - if (csrbank1_dly_sel0_re) begin - k7ddrphy_dly_sel_storage[3:0] <= csrbank1_dly_sel0_r; + main_k7ddrphy_rst_re <= builder_csrbank1_rst0_re; + if (builder_csrbank1_dly_sel0_re) begin + main_k7ddrphy_dly_sel_storage[3:0] <= builder_csrbank1_dly_sel0_r; end - k7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; - if (csrbank1_half_sys8x_taps0_re) begin - k7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r; + main_k7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re; + if (builder_csrbank1_half_sys8x_taps0_re) begin + main_k7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r; end - k7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re; - if (csrbank1_wlevel_en0_re) begin - k7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r; + main_k7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re; + if (builder_csrbank1_wlevel_en0_re) begin + main_k7ddrphy_wlevel_en_storage <= builder_csrbank1_wlevel_en0_r; end - k7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re; - if (csrbank1_rdphase0_re) begin - k7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r; + main_k7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re; + if (builder_csrbank1_rdphase0_re) begin + main_k7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r; end - k7ddrphy_rdphase_re <= csrbank1_rdphase0_re; - if (csrbank1_wrphase0_re) begin - k7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r; + main_k7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re; + if (builder_csrbank1_wrphase0_re) begin + main_k7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r; end - k7ddrphy_wrphase_re <= csrbank1_wrphase0_re; - interface2_bank_bus_dat_r <= 1'd0; - if (csrbank2_sel) begin - case (interface2_bank_bus_adr[8:0]) + main_k7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re; + builder_interface2_bank_bus_dat_r <= 1'd0; + if (builder_csrbank2_sel) begin + case (builder_interface2_bank_bus_adr[8:0]) 1'd0: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_control0_w; end 1'd1: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_command0_w; end 2'd2: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w; end 3'd4: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w; end 3'd5: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata1_w; end 3'd6: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w; end 3'd7: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata1_w; end 4'd8: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata0_w; end 4'd9: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w; end 4'd10: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w; end 4'd11: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w; end 4'd12: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w; end 4'd13: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata1_w; end 4'd14: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w; end 4'd15: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata1_w; end 5'd16: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata0_w; end 5'd17: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w; end 5'd18: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w; end 5'd19: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w; end 5'd20: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w; end 5'd21: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata1_w; end 5'd22: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w; end 5'd23: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata1_w; end 5'd24: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata0_w; end 5'd25: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w; end 5'd26: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w; end 5'd27: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w; end 5'd28: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w; end 5'd29: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata1_w; end 5'd30: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w; end 5'd31: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata1_w; end 6'd32: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata0_w; end endcase end - if (csrbank2_dfii_control0_re) begin - litedramcore_storage[3:0] <= csrbank2_dfii_control0_r; + if (builder_csrbank2_dfii_control0_re) begin + main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r; end - litedramcore_re <= csrbank2_dfii_control0_re; - if (csrbank2_dfii_pi0_command0_re) begin - litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; + main_litedramcore_re <= builder_csrbank2_dfii_control0_re; + if (builder_csrbank2_dfii_pi0_command0_re) begin + main_litedramcore_phaseinjector0_command_storage[7:0] <= builder_csrbank2_dfii_pi0_command0_r; end - litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; - if (csrbank2_dfii_pi0_address0_re) begin - litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r; + main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re; + if (builder_csrbank2_dfii_pi0_address0_re) begin + main_litedramcore_phaseinjector0_address_storage[14:0] <= builder_csrbank2_dfii_pi0_address0_r; end - litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; - if (csrbank2_dfii_pi0_baddress0_re) begin - litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; + main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re; + if (builder_csrbank2_dfii_pi0_baddress0_re) begin + main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r; end - litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; - if (csrbank2_dfii_pi0_wrdata1_re) begin - litedramcore_phaseinjector0_wrdata_storage[63:32] <= csrbank2_dfii_pi0_wrdata1_r; + main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re; + if (builder_csrbank2_dfii_pi0_wrdata1_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[63:32] <= builder_csrbank2_dfii_pi0_wrdata1_r; end - if (csrbank2_dfii_pi0_wrdata0_re) begin - litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; + if (builder_csrbank2_dfii_pi0_wrdata0_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r; end - litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; - litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata0_re; - if (csrbank2_dfii_pi1_command0_re) begin - litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; + main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re; + main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata0_re; + if (builder_csrbank2_dfii_pi1_command0_re) begin + main_litedramcore_phaseinjector1_command_storage[7:0] <= builder_csrbank2_dfii_pi1_command0_r; end - litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; - if (csrbank2_dfii_pi1_address0_re) begin - litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r; + main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re; + if (builder_csrbank2_dfii_pi1_address0_re) begin + main_litedramcore_phaseinjector1_address_storage[14:0] <= builder_csrbank2_dfii_pi1_address0_r; end - litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; - if (csrbank2_dfii_pi1_baddress0_re) begin - litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; + main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re; + if (builder_csrbank2_dfii_pi1_baddress0_re) begin + main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r; end - litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; - if (csrbank2_dfii_pi1_wrdata1_re) begin - litedramcore_phaseinjector1_wrdata_storage[63:32] <= csrbank2_dfii_pi1_wrdata1_r; + main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re; + if (builder_csrbank2_dfii_pi1_wrdata1_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[63:32] <= builder_csrbank2_dfii_pi1_wrdata1_r; end - if (csrbank2_dfii_pi1_wrdata0_re) begin - litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; + if (builder_csrbank2_dfii_pi1_wrdata0_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r; end - litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; - litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata0_re; - if (csrbank2_dfii_pi2_command0_re) begin - litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; + main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re; + main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata0_re; + if (builder_csrbank2_dfii_pi2_command0_re) begin + main_litedramcore_phaseinjector2_command_storage[7:0] <= builder_csrbank2_dfii_pi2_command0_r; end - litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; - if (csrbank2_dfii_pi2_address0_re) begin - litedramcore_phaseinjector2_address_storage[14:0] <= csrbank2_dfii_pi2_address0_r; + main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re; + if (builder_csrbank2_dfii_pi2_address0_re) begin + main_litedramcore_phaseinjector2_address_storage[14:0] <= builder_csrbank2_dfii_pi2_address0_r; end - litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; - if (csrbank2_dfii_pi2_baddress0_re) begin - litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; + main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re; + if (builder_csrbank2_dfii_pi2_baddress0_re) begin + main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r; end - litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; - if (csrbank2_dfii_pi2_wrdata1_re) begin - litedramcore_phaseinjector2_wrdata_storage[63:32] <= csrbank2_dfii_pi2_wrdata1_r; + main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re; + if (builder_csrbank2_dfii_pi2_wrdata1_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[63:32] <= builder_csrbank2_dfii_pi2_wrdata1_r; end - if (csrbank2_dfii_pi2_wrdata0_re) begin - litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r; + if (builder_csrbank2_dfii_pi2_wrdata0_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r; end - litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; - litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata0_re; - if (csrbank2_dfii_pi3_command0_re) begin - litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; + main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re; + main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata0_re; + if (builder_csrbank2_dfii_pi3_command0_re) begin + main_litedramcore_phaseinjector3_command_storage[7:0] <= builder_csrbank2_dfii_pi3_command0_r; end - litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; - if (csrbank2_dfii_pi3_address0_re) begin - litedramcore_phaseinjector3_address_storage[14:0] <= csrbank2_dfii_pi3_address0_r; + main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re; + if (builder_csrbank2_dfii_pi3_address0_re) begin + main_litedramcore_phaseinjector3_address_storage[14:0] <= builder_csrbank2_dfii_pi3_address0_r; end - litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; - if (csrbank2_dfii_pi3_baddress0_re) begin - litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; + main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re; + if (builder_csrbank2_dfii_pi3_baddress0_re) begin + main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r; end - litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; - if (csrbank2_dfii_pi3_wrdata1_re) begin - litedramcore_phaseinjector3_wrdata_storage[63:32] <= csrbank2_dfii_pi3_wrdata1_r; + main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re; + if (builder_csrbank2_dfii_pi3_wrdata1_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[63:32] <= builder_csrbank2_dfii_pi3_wrdata1_r; end - if (csrbank2_dfii_pi3_wrdata0_re) begin - litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r; + if (builder_csrbank2_dfii_pi3_wrdata0_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r; end - litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; - litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata0_re; + main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re; + main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata0_re; if (sys_rst) begin - k7ddrphy_rst_storage <= 1'd0; - k7ddrphy_rst_re <= 1'd0; - k7ddrphy_dly_sel_storage <= 4'd0; - k7ddrphy_dly_sel_re <= 1'd0; - k7ddrphy_half_sys8x_taps_storage <= 5'd8; - k7ddrphy_half_sys8x_taps_re <= 1'd0; - k7ddrphy_wlevel_en_storage <= 1'd0; - k7ddrphy_wlevel_en_re <= 1'd0; - k7ddrphy_rdphase_storage <= 2'd1; - k7ddrphy_rdphase_re <= 1'd0; - k7ddrphy_wrphase_storage <= 2'd2; - k7ddrphy_wrphase_re <= 1'd0; - k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; - k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; - k7ddrphy_bitslip0_value0 <= 3'd7; - k7ddrphy_bitslip1_value0 <= 3'd7; - k7ddrphy_bitslip2_value0 <= 3'd7; - k7ddrphy_bitslip3_value0 <= 3'd7; - k7ddrphy_bitslip0_value1 <= 3'd7; - k7ddrphy_bitslip1_value1 <= 3'd7; - k7ddrphy_bitslip2_value1 <= 3'd7; - k7ddrphy_bitslip3_value1 <= 3'd7; - k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; - k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; - k7ddrphy_bitslip0_value2 <= 3'd7; - k7ddrphy_bitslip0_value3 <= 3'd7; - k7ddrphy_bitslip1_value2 <= 3'd7; - k7ddrphy_bitslip1_value3 <= 3'd7; - k7ddrphy_bitslip2_value2 <= 3'd7; - k7ddrphy_bitslip2_value3 <= 3'd7; - k7ddrphy_bitslip3_value2 <= 3'd7; - k7ddrphy_bitslip3_value3 <= 3'd7; - k7ddrphy_bitslip4_value0 <= 3'd7; - k7ddrphy_bitslip4_value1 <= 3'd7; - k7ddrphy_bitslip5_value0 <= 3'd7; - k7ddrphy_bitslip5_value1 <= 3'd7; - k7ddrphy_bitslip6_value0 <= 3'd7; - k7ddrphy_bitslip6_value1 <= 3'd7; - k7ddrphy_bitslip7_value0 <= 3'd7; - k7ddrphy_bitslip7_value1 <= 3'd7; - k7ddrphy_bitslip8_value0 <= 3'd7; - k7ddrphy_bitslip8_value1 <= 3'd7; - k7ddrphy_bitslip9_value0 <= 3'd7; - k7ddrphy_bitslip9_value1 <= 3'd7; - k7ddrphy_bitslip10_value0 <= 3'd7; - k7ddrphy_bitslip10_value1 <= 3'd7; - k7ddrphy_bitslip11_value0 <= 3'd7; - k7ddrphy_bitslip11_value1 <= 3'd7; - k7ddrphy_bitslip12_value0 <= 3'd7; - k7ddrphy_bitslip12_value1 <= 3'd7; - k7ddrphy_bitslip13_value0 <= 3'd7; - k7ddrphy_bitslip13_value1 <= 3'd7; - k7ddrphy_bitslip14_value0 <= 3'd7; - k7ddrphy_bitslip14_value1 <= 3'd7; - k7ddrphy_bitslip15_value0 <= 3'd7; - k7ddrphy_bitslip15_value1 <= 3'd7; - k7ddrphy_bitslip16_value0 <= 3'd7; - k7ddrphy_bitslip16_value1 <= 3'd7; - k7ddrphy_bitslip17_value0 <= 3'd7; - k7ddrphy_bitslip17_value1 <= 3'd7; - k7ddrphy_bitslip18_value0 <= 3'd7; - k7ddrphy_bitslip18_value1 <= 3'd7; - k7ddrphy_bitslip19_value0 <= 3'd7; - k7ddrphy_bitslip19_value1 <= 3'd7; - k7ddrphy_bitslip20_value0 <= 3'd7; - k7ddrphy_bitslip20_value1 <= 3'd7; - k7ddrphy_bitslip21_value0 <= 3'd7; - k7ddrphy_bitslip21_value1 <= 3'd7; - k7ddrphy_bitslip22_value0 <= 3'd7; - k7ddrphy_bitslip22_value1 <= 3'd7; - k7ddrphy_bitslip23_value0 <= 3'd7; - k7ddrphy_bitslip23_value1 <= 3'd7; - k7ddrphy_bitslip24_value0 <= 3'd7; - k7ddrphy_bitslip24_value1 <= 3'd7; - k7ddrphy_bitslip25_value0 <= 3'd7; - k7ddrphy_bitslip25_value1 <= 3'd7; - k7ddrphy_bitslip26_value0 <= 3'd7; - k7ddrphy_bitslip26_value1 <= 3'd7; - k7ddrphy_bitslip27_value0 <= 3'd7; - k7ddrphy_bitslip27_value1 <= 3'd7; - k7ddrphy_bitslip28_value0 <= 3'd7; - k7ddrphy_bitslip28_value1 <= 3'd7; - k7ddrphy_bitslip29_value0 <= 3'd7; - k7ddrphy_bitslip29_value1 <= 3'd7; - k7ddrphy_bitslip30_value0 <= 3'd7; - k7ddrphy_bitslip30_value1 <= 3'd7; - k7ddrphy_bitslip31_value0 <= 3'd7; - k7ddrphy_bitslip31_value1 <= 3'd7; - k7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; - k7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; - k7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; - k7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; - k7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; - k7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; - k7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; - k7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; - k7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; - k7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; - k7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; - litedramcore_storage <= 4'd1; - litedramcore_re <= 1'd0; - litedramcore_phaseinjector0_command_storage <= 6'd0; - litedramcore_phaseinjector0_command_re <= 1'd0; - litedramcore_phaseinjector0_address_re <= 1'd0; - litedramcore_phaseinjector0_baddress_re <= 1'd0; - litedramcore_phaseinjector0_wrdata_re <= 1'd0; - litedramcore_phaseinjector0_rddata_status <= 64'd0; - litedramcore_phaseinjector0_rddata_re <= 1'd0; - litedramcore_phaseinjector1_command_storage <= 6'd0; - litedramcore_phaseinjector1_command_re <= 1'd0; - litedramcore_phaseinjector1_address_re <= 1'd0; - litedramcore_phaseinjector1_baddress_re <= 1'd0; - litedramcore_phaseinjector1_wrdata_re <= 1'd0; - litedramcore_phaseinjector1_rddata_status <= 64'd0; - litedramcore_phaseinjector1_rddata_re <= 1'd0; - litedramcore_phaseinjector2_command_storage <= 6'd0; - litedramcore_phaseinjector2_command_re <= 1'd0; - litedramcore_phaseinjector2_address_re <= 1'd0; - litedramcore_phaseinjector2_baddress_re <= 1'd0; - litedramcore_phaseinjector2_wrdata_re <= 1'd0; - litedramcore_phaseinjector2_rddata_status <= 64'd0; - litedramcore_phaseinjector2_rddata_re <= 1'd0; - litedramcore_phaseinjector3_command_storage <= 6'd0; - litedramcore_phaseinjector3_command_re <= 1'd0; - litedramcore_phaseinjector3_address_re <= 1'd0; - litedramcore_phaseinjector3_baddress_re <= 1'd0; - litedramcore_phaseinjector3_wrdata_re <= 1'd0; - litedramcore_phaseinjector3_rddata_status <= 64'd0; - litedramcore_phaseinjector3_rddata_re <= 1'd0; - litedramcore_dfi_p0_address <= 15'd0; - litedramcore_dfi_p0_bank <= 3'd0; - litedramcore_dfi_p0_cas_n <= 1'd1; - litedramcore_dfi_p0_cs_n <= 1'd1; - litedramcore_dfi_p0_ras_n <= 1'd1; - litedramcore_dfi_p0_we_n <= 1'd1; - litedramcore_dfi_p0_wrdata_en <= 1'd0; - litedramcore_dfi_p0_rddata_en <= 1'd0; - litedramcore_dfi_p1_address <= 15'd0; - litedramcore_dfi_p1_bank <= 3'd0; - litedramcore_dfi_p1_cas_n <= 1'd1; - litedramcore_dfi_p1_cs_n <= 1'd1; - litedramcore_dfi_p1_ras_n <= 1'd1; - litedramcore_dfi_p1_we_n <= 1'd1; - litedramcore_dfi_p1_wrdata_en <= 1'd0; - litedramcore_dfi_p1_rddata_en <= 1'd0; - litedramcore_dfi_p2_address <= 15'd0; - litedramcore_dfi_p2_bank <= 3'd0; - litedramcore_dfi_p2_cas_n <= 1'd1; - litedramcore_dfi_p2_cs_n <= 1'd1; - litedramcore_dfi_p2_ras_n <= 1'd1; - litedramcore_dfi_p2_we_n <= 1'd1; - litedramcore_dfi_p2_wrdata_en <= 1'd0; - litedramcore_dfi_p2_rddata_en <= 1'd0; - litedramcore_dfi_p3_address <= 15'd0; - litedramcore_dfi_p3_bank <= 3'd0; - litedramcore_dfi_p3_cas_n <= 1'd1; - litedramcore_dfi_p3_cs_n <= 1'd1; - litedramcore_dfi_p3_ras_n <= 1'd1; - litedramcore_dfi_p3_we_n <= 1'd1; - litedramcore_dfi_p3_wrdata_en <= 1'd0; - litedramcore_dfi_p3_rddata_en <= 1'd0; - litedramcore_cmd_payload_a <= 15'd0; - litedramcore_cmd_payload_ba <= 3'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_timer_count1 <= 10'd781; - litedramcore_postponer_req_o <= 1'd0; - litedramcore_postponer_count <= 1'd0; - litedramcore_sequencer_done1 <= 1'd0; - litedramcore_sequencer_counter <= 6'd0; - litedramcore_sequencer_count <= 1'd0; - litedramcore_zqcs_timer_count1 <= 27'd99999999; - litedramcore_zqcs_executer_done <= 1'd0; - litedramcore_zqcs_executer_counter <= 5'd0; - litedramcore_bankmachine0_level <= 5'd0; - litedramcore_bankmachine0_produce <= 4'd0; - litedramcore_bankmachine0_consume <= 4'd0; - litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 22'd0; - litedramcore_bankmachine0_row <= 15'd0; - litedramcore_bankmachine0_row_opened <= 1'd0; - litedramcore_bankmachine0_twtpcon_ready <= 1'd0; - litedramcore_bankmachine0_twtpcon_count <= 3'd0; - litedramcore_bankmachine0_trccon_ready <= 1'd0; - litedramcore_bankmachine0_trccon_count <= 3'd0; - litedramcore_bankmachine0_trascon_ready <= 1'd0; - litedramcore_bankmachine0_trascon_count <= 3'd0; - litedramcore_bankmachine1_level <= 5'd0; - litedramcore_bankmachine1_produce <= 4'd0; - litedramcore_bankmachine1_consume <= 4'd0; - litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 22'd0; - litedramcore_bankmachine1_row <= 15'd0; - litedramcore_bankmachine1_row_opened <= 1'd0; - litedramcore_bankmachine1_twtpcon_ready <= 1'd0; - litedramcore_bankmachine1_twtpcon_count <= 3'd0; - litedramcore_bankmachine1_trccon_ready <= 1'd0; - litedramcore_bankmachine1_trccon_count <= 3'd0; - litedramcore_bankmachine1_trascon_ready <= 1'd0; - litedramcore_bankmachine1_trascon_count <= 3'd0; - litedramcore_bankmachine2_level <= 5'd0; - litedramcore_bankmachine2_produce <= 4'd0; - litedramcore_bankmachine2_consume <= 4'd0; - litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 22'd0; - litedramcore_bankmachine2_row <= 15'd0; - litedramcore_bankmachine2_row_opened <= 1'd0; - litedramcore_bankmachine2_twtpcon_ready <= 1'd0; - litedramcore_bankmachine2_twtpcon_count <= 3'd0; - litedramcore_bankmachine2_trccon_ready <= 1'd0; - litedramcore_bankmachine2_trccon_count <= 3'd0; - litedramcore_bankmachine2_trascon_ready <= 1'd0; - litedramcore_bankmachine2_trascon_count <= 3'd0; - litedramcore_bankmachine3_level <= 5'd0; - litedramcore_bankmachine3_produce <= 4'd0; - litedramcore_bankmachine3_consume <= 4'd0; - litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 22'd0; - litedramcore_bankmachine3_row <= 15'd0; - litedramcore_bankmachine3_row_opened <= 1'd0; - litedramcore_bankmachine3_twtpcon_ready <= 1'd0; - litedramcore_bankmachine3_twtpcon_count <= 3'd0; - litedramcore_bankmachine3_trccon_ready <= 1'd0; - litedramcore_bankmachine3_trccon_count <= 3'd0; - litedramcore_bankmachine3_trascon_ready <= 1'd0; - litedramcore_bankmachine3_trascon_count <= 3'd0; - litedramcore_bankmachine4_level <= 5'd0; - litedramcore_bankmachine4_produce <= 4'd0; - litedramcore_bankmachine4_consume <= 4'd0; - litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 22'd0; - litedramcore_bankmachine4_row <= 15'd0; - litedramcore_bankmachine4_row_opened <= 1'd0; - litedramcore_bankmachine4_twtpcon_ready <= 1'd0; - litedramcore_bankmachine4_twtpcon_count <= 3'd0; - litedramcore_bankmachine4_trccon_ready <= 1'd0; - litedramcore_bankmachine4_trccon_count <= 3'd0; - litedramcore_bankmachine4_trascon_ready <= 1'd0; - litedramcore_bankmachine4_trascon_count <= 3'd0; - litedramcore_bankmachine5_level <= 5'd0; - litedramcore_bankmachine5_produce <= 4'd0; - litedramcore_bankmachine5_consume <= 4'd0; - litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 22'd0; - litedramcore_bankmachine5_row <= 15'd0; - litedramcore_bankmachine5_row_opened <= 1'd0; - litedramcore_bankmachine5_twtpcon_ready <= 1'd0; - litedramcore_bankmachine5_twtpcon_count <= 3'd0; - litedramcore_bankmachine5_trccon_ready <= 1'd0; - litedramcore_bankmachine5_trccon_count <= 3'd0; - litedramcore_bankmachine5_trascon_ready <= 1'd0; - litedramcore_bankmachine5_trascon_count <= 3'd0; - litedramcore_bankmachine6_level <= 5'd0; - litedramcore_bankmachine6_produce <= 4'd0; - litedramcore_bankmachine6_consume <= 4'd0; - litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 22'd0; - litedramcore_bankmachine6_row <= 15'd0; - litedramcore_bankmachine6_row_opened <= 1'd0; - litedramcore_bankmachine6_twtpcon_ready <= 1'd0; - litedramcore_bankmachine6_twtpcon_count <= 3'd0; - litedramcore_bankmachine6_trccon_ready <= 1'd0; - litedramcore_bankmachine6_trccon_count <= 3'd0; - litedramcore_bankmachine6_trascon_ready <= 1'd0; - litedramcore_bankmachine6_trascon_count <= 3'd0; - litedramcore_bankmachine7_level <= 5'd0; - litedramcore_bankmachine7_produce <= 4'd0; - litedramcore_bankmachine7_consume <= 4'd0; - litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 22'd0; - litedramcore_bankmachine7_row <= 15'd0; - litedramcore_bankmachine7_row_opened <= 1'd0; - litedramcore_bankmachine7_twtpcon_ready <= 1'd0; - litedramcore_bankmachine7_twtpcon_count <= 3'd0; - litedramcore_bankmachine7_trccon_ready <= 1'd0; - litedramcore_bankmachine7_trccon_count <= 3'd0; - litedramcore_bankmachine7_trascon_ready <= 1'd0; - litedramcore_bankmachine7_trascon_count <= 3'd0; - litedramcore_choose_cmd_grant <= 3'd0; - litedramcore_choose_req_grant <= 3'd0; - litedramcore_trrdcon_ready <= 1'd0; - litedramcore_trrdcon_count <= 1'd0; - litedramcore_tfawcon_ready <= 1'd1; - litedramcore_tfawcon_window <= 5'd0; - litedramcore_tccdcon_ready <= 1'd0; - litedramcore_tccdcon_count <= 1'd0; - litedramcore_twtrcon_ready <= 1'd0; - litedramcore_twtrcon_count <= 3'd0; - litedramcore_time0 <= 5'd0; - litedramcore_time1 <= 4'd0; - init_done_storage <= 1'd0; - init_done_re <= 1'd0; - init_error_storage <= 1'd0; - init_error_re <= 1'd0; - litedramcore_we <= 1'd0; - litedramcore_refresher_state <= 2'd0; - litedramcore_bankmachine0_state <= 4'd0; - litedramcore_bankmachine1_state <= 4'd0; - litedramcore_bankmachine2_state <= 4'd0; - litedramcore_bankmachine3_state <= 4'd0; - litedramcore_bankmachine4_state <= 4'd0; - litedramcore_bankmachine5_state <= 4'd0; - litedramcore_bankmachine6_state <= 4'd0; - litedramcore_bankmachine7_state <= 4'd0; - litedramcore_multiplexer_state <= 4'd0; - litedramcore_new_master_wdata_ready0 <= 1'd0; - litedramcore_new_master_wdata_ready1 <= 1'd0; - litedramcore_new_master_rdata_valid0 <= 1'd0; - litedramcore_new_master_rdata_valid1 <= 1'd0; - litedramcore_new_master_rdata_valid2 <= 1'd0; - litedramcore_new_master_rdata_valid3 <= 1'd0; - litedramcore_new_master_rdata_valid4 <= 1'd0; - litedramcore_new_master_rdata_valid5 <= 1'd0; - litedramcore_new_master_rdata_valid6 <= 1'd0; - litedramcore_new_master_rdata_valid7 <= 1'd0; - litedramcore_new_master_rdata_valid8 <= 1'd0; - litedramcore_state <= 2'd0; + main_k7ddrphy_rst_storage <= 1'd0; + main_k7ddrphy_rst_re <= 1'd0; + main_k7ddrphy_dly_sel_storage <= 4'd0; + main_k7ddrphy_dly_sel_re <= 1'd0; + main_k7ddrphy_half_sys8x_taps_storage <= 5'd8; + main_k7ddrphy_half_sys8x_taps_re <= 1'd0; + main_k7ddrphy_wlevel_en_storage <= 1'd0; + main_k7ddrphy_wlevel_en_re <= 1'd0; + main_k7ddrphy_rdphase_storage <= 2'd1; + main_k7ddrphy_rdphase_re <= 1'd0; + main_k7ddrphy_wrphase_storage <= 2'd2; + main_k7ddrphy_wrphase_re <= 1'd0; + main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + main_k7ddrphy_bitslip0_value0 <= 3'd7; + main_k7ddrphy_bitslip1_value0 <= 3'd7; + main_k7ddrphy_bitslip2_value0 <= 3'd7; + main_k7ddrphy_bitslip3_value0 <= 3'd7; + main_k7ddrphy_bitslip0_value1 <= 3'd7; + main_k7ddrphy_bitslip1_value1 <= 3'd7; + main_k7ddrphy_bitslip2_value1 <= 3'd7; + main_k7ddrphy_bitslip3_value1 <= 3'd7; + main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + main_k7ddrphy_bitslip0_value2 <= 3'd7; + main_k7ddrphy_bitslip0_value3 <= 3'd7; + main_k7ddrphy_bitslip1_value2 <= 3'd7; + main_k7ddrphy_bitslip1_value3 <= 3'd7; + main_k7ddrphy_bitslip2_value2 <= 3'd7; + main_k7ddrphy_bitslip2_value3 <= 3'd7; + main_k7ddrphy_bitslip3_value2 <= 3'd7; + main_k7ddrphy_bitslip3_value3 <= 3'd7; + main_k7ddrphy_bitslip4_value0 <= 3'd7; + main_k7ddrphy_bitslip4_value1 <= 3'd7; + main_k7ddrphy_bitslip5_value0 <= 3'd7; + main_k7ddrphy_bitslip5_value1 <= 3'd7; + main_k7ddrphy_bitslip6_value0 <= 3'd7; + main_k7ddrphy_bitslip6_value1 <= 3'd7; + main_k7ddrphy_bitslip7_value0 <= 3'd7; + main_k7ddrphy_bitslip7_value1 <= 3'd7; + main_k7ddrphy_bitslip8_value0 <= 3'd7; + main_k7ddrphy_bitslip8_value1 <= 3'd7; + main_k7ddrphy_bitslip9_value0 <= 3'd7; + main_k7ddrphy_bitslip9_value1 <= 3'd7; + main_k7ddrphy_bitslip10_value0 <= 3'd7; + main_k7ddrphy_bitslip10_value1 <= 3'd7; + main_k7ddrphy_bitslip11_value0 <= 3'd7; + main_k7ddrphy_bitslip11_value1 <= 3'd7; + main_k7ddrphy_bitslip12_value0 <= 3'd7; + main_k7ddrphy_bitslip12_value1 <= 3'd7; + main_k7ddrphy_bitslip13_value0 <= 3'd7; + main_k7ddrphy_bitslip13_value1 <= 3'd7; + main_k7ddrphy_bitslip14_value0 <= 3'd7; + main_k7ddrphy_bitslip14_value1 <= 3'd7; + main_k7ddrphy_bitslip15_value0 <= 3'd7; + main_k7ddrphy_bitslip15_value1 <= 3'd7; + main_k7ddrphy_bitslip16_value0 <= 3'd7; + main_k7ddrphy_bitslip16_value1 <= 3'd7; + main_k7ddrphy_bitslip17_value0 <= 3'd7; + main_k7ddrphy_bitslip17_value1 <= 3'd7; + main_k7ddrphy_bitslip18_value0 <= 3'd7; + main_k7ddrphy_bitslip18_value1 <= 3'd7; + main_k7ddrphy_bitslip19_value0 <= 3'd7; + main_k7ddrphy_bitslip19_value1 <= 3'd7; + main_k7ddrphy_bitslip20_value0 <= 3'd7; + main_k7ddrphy_bitslip20_value1 <= 3'd7; + main_k7ddrphy_bitslip21_value0 <= 3'd7; + main_k7ddrphy_bitslip21_value1 <= 3'd7; + main_k7ddrphy_bitslip22_value0 <= 3'd7; + main_k7ddrphy_bitslip22_value1 <= 3'd7; + main_k7ddrphy_bitslip23_value0 <= 3'd7; + main_k7ddrphy_bitslip23_value1 <= 3'd7; + main_k7ddrphy_bitslip24_value0 <= 3'd7; + main_k7ddrphy_bitslip24_value1 <= 3'd7; + main_k7ddrphy_bitslip25_value0 <= 3'd7; + main_k7ddrphy_bitslip25_value1 <= 3'd7; + main_k7ddrphy_bitslip26_value0 <= 3'd7; + main_k7ddrphy_bitslip26_value1 <= 3'd7; + main_k7ddrphy_bitslip27_value0 <= 3'd7; + main_k7ddrphy_bitslip27_value1 <= 3'd7; + main_k7ddrphy_bitslip28_value0 <= 3'd7; + main_k7ddrphy_bitslip28_value1 <= 3'd7; + main_k7ddrphy_bitslip29_value0 <= 3'd7; + main_k7ddrphy_bitslip29_value1 <= 3'd7; + main_k7ddrphy_bitslip30_value0 <= 3'd7; + main_k7ddrphy_bitslip30_value1 <= 3'd7; + main_k7ddrphy_bitslip31_value0 <= 3'd7; + main_k7ddrphy_bitslip31_value1 <= 3'd7; + main_k7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; + main_k7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; + main_k7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; + main_k7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; + main_k7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; + main_k7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; + main_k7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; + main_k7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; + main_k7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; + main_k7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; + main_k7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; + main_litedramcore_storage <= 4'd1; + main_litedramcore_re <= 1'd0; + main_litedramcore_phaseinjector0_command_storage <= 8'd0; + main_litedramcore_phaseinjector0_command_re <= 1'd0; + main_litedramcore_phaseinjector0_address_re <= 1'd0; + main_litedramcore_phaseinjector0_baddress_re <= 1'd0; + main_litedramcore_phaseinjector0_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector0_rddata_status <= 64'd0; + main_litedramcore_phaseinjector0_rddata_re <= 1'd0; + main_litedramcore_phaseinjector1_command_storage <= 8'd0; + main_litedramcore_phaseinjector1_command_re <= 1'd0; + main_litedramcore_phaseinjector1_address_re <= 1'd0; + main_litedramcore_phaseinjector1_baddress_re <= 1'd0; + main_litedramcore_phaseinjector1_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector1_rddata_status <= 64'd0; + main_litedramcore_phaseinjector1_rddata_re <= 1'd0; + main_litedramcore_phaseinjector2_command_storage <= 8'd0; + main_litedramcore_phaseinjector2_command_re <= 1'd0; + main_litedramcore_phaseinjector2_address_re <= 1'd0; + main_litedramcore_phaseinjector2_baddress_re <= 1'd0; + main_litedramcore_phaseinjector2_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector2_rddata_status <= 64'd0; + main_litedramcore_phaseinjector2_rddata_re <= 1'd0; + main_litedramcore_phaseinjector3_command_storage <= 8'd0; + main_litedramcore_phaseinjector3_command_re <= 1'd0; + main_litedramcore_phaseinjector3_address_re <= 1'd0; + main_litedramcore_phaseinjector3_baddress_re <= 1'd0; + main_litedramcore_phaseinjector3_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector3_rddata_status <= 64'd0; + main_litedramcore_phaseinjector3_rddata_re <= 1'd0; + main_litedramcore_dfi_p0_address <= 15'd0; + main_litedramcore_dfi_p0_bank <= 3'd0; + main_litedramcore_dfi_p0_cas_n <= 1'd1; + main_litedramcore_dfi_p0_cs_n <= 1'd1; + main_litedramcore_dfi_p0_ras_n <= 1'd1; + main_litedramcore_dfi_p0_we_n <= 1'd1; + main_litedramcore_dfi_p0_wrdata_en <= 1'd0; + main_litedramcore_dfi_p0_rddata_en <= 1'd0; + main_litedramcore_dfi_p1_address <= 15'd0; + main_litedramcore_dfi_p1_bank <= 3'd0; + main_litedramcore_dfi_p1_cas_n <= 1'd1; + main_litedramcore_dfi_p1_cs_n <= 1'd1; + main_litedramcore_dfi_p1_ras_n <= 1'd1; + main_litedramcore_dfi_p1_we_n <= 1'd1; + main_litedramcore_dfi_p1_wrdata_en <= 1'd0; + main_litedramcore_dfi_p1_rddata_en <= 1'd0; + main_litedramcore_dfi_p2_address <= 15'd0; + main_litedramcore_dfi_p2_bank <= 3'd0; + main_litedramcore_dfi_p2_cas_n <= 1'd1; + main_litedramcore_dfi_p2_cs_n <= 1'd1; + main_litedramcore_dfi_p2_ras_n <= 1'd1; + main_litedramcore_dfi_p2_we_n <= 1'd1; + main_litedramcore_dfi_p2_wrdata_en <= 1'd0; + main_litedramcore_dfi_p2_rddata_en <= 1'd0; + main_litedramcore_dfi_p3_address <= 15'd0; + main_litedramcore_dfi_p3_bank <= 3'd0; + main_litedramcore_dfi_p3_cas_n <= 1'd1; + main_litedramcore_dfi_p3_cs_n <= 1'd1; + main_litedramcore_dfi_p3_ras_n <= 1'd1; + main_litedramcore_dfi_p3_we_n <= 1'd1; + main_litedramcore_dfi_p3_wrdata_en <= 1'd0; + main_litedramcore_dfi_p3_rddata_en <= 1'd0; + main_litedramcore_cmd_payload_a <= 15'd0; + main_litedramcore_cmd_payload_ba <= 3'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_timer_count1 <= 10'd781; + main_litedramcore_postponer_req_o <= 1'd0; + main_litedramcore_postponer_count <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd0; + main_litedramcore_sequencer_trigger <= 6'd0; + main_litedramcore_sequencer_count <= 1'd0; + main_litedramcore_zqcs_timer_count1 <= 27'd99999999; + main_litedramcore_zqcs_executer_done <= 1'd0; + main_litedramcore_zqcs_executer_trigger <= 5'd0; + main_litedramcore_bankmachine0_level <= 5'd0; + main_litedramcore_bankmachine0_produce <= 4'd0; + main_litedramcore_bankmachine0_consume <= 4'd0; + main_litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine0_row <= 15'd0; + main_litedramcore_bankmachine0_row_opened <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine0_trccon_ready <= 1'd0; + main_litedramcore_bankmachine0_trccon_count <= 3'd0; + main_litedramcore_bankmachine0_trascon_ready <= 1'd0; + main_litedramcore_bankmachine0_trascon_count <= 3'd0; + main_litedramcore_bankmachine1_level <= 5'd0; + main_litedramcore_bankmachine1_produce <= 4'd0; + main_litedramcore_bankmachine1_consume <= 4'd0; + main_litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine1_row <= 15'd0; + main_litedramcore_bankmachine1_row_opened <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine1_trccon_ready <= 1'd0; + main_litedramcore_bankmachine1_trccon_count <= 3'd0; + main_litedramcore_bankmachine1_trascon_ready <= 1'd0; + main_litedramcore_bankmachine1_trascon_count <= 3'd0; + main_litedramcore_bankmachine2_level <= 5'd0; + main_litedramcore_bankmachine2_produce <= 4'd0; + main_litedramcore_bankmachine2_consume <= 4'd0; + main_litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine2_row <= 15'd0; + main_litedramcore_bankmachine2_row_opened <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine2_trccon_ready <= 1'd0; + main_litedramcore_bankmachine2_trccon_count <= 3'd0; + main_litedramcore_bankmachine2_trascon_ready <= 1'd0; + main_litedramcore_bankmachine2_trascon_count <= 3'd0; + main_litedramcore_bankmachine3_level <= 5'd0; + main_litedramcore_bankmachine3_produce <= 4'd0; + main_litedramcore_bankmachine3_consume <= 4'd0; + main_litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine3_row <= 15'd0; + main_litedramcore_bankmachine3_row_opened <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine3_trccon_ready <= 1'd0; + main_litedramcore_bankmachine3_trccon_count <= 3'd0; + main_litedramcore_bankmachine3_trascon_ready <= 1'd0; + main_litedramcore_bankmachine3_trascon_count <= 3'd0; + main_litedramcore_bankmachine4_level <= 5'd0; + main_litedramcore_bankmachine4_produce <= 4'd0; + main_litedramcore_bankmachine4_consume <= 4'd0; + main_litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine4_row <= 15'd0; + main_litedramcore_bankmachine4_row_opened <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine4_trccon_ready <= 1'd0; + main_litedramcore_bankmachine4_trccon_count <= 3'd0; + main_litedramcore_bankmachine4_trascon_ready <= 1'd0; + main_litedramcore_bankmachine4_trascon_count <= 3'd0; + main_litedramcore_bankmachine5_level <= 5'd0; + main_litedramcore_bankmachine5_produce <= 4'd0; + main_litedramcore_bankmachine5_consume <= 4'd0; + main_litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine5_row <= 15'd0; + main_litedramcore_bankmachine5_row_opened <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine5_trccon_ready <= 1'd0; + main_litedramcore_bankmachine5_trccon_count <= 3'd0; + main_litedramcore_bankmachine5_trascon_ready <= 1'd0; + main_litedramcore_bankmachine5_trascon_count <= 3'd0; + main_litedramcore_bankmachine6_level <= 5'd0; + main_litedramcore_bankmachine6_produce <= 4'd0; + main_litedramcore_bankmachine6_consume <= 4'd0; + main_litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine6_row <= 15'd0; + main_litedramcore_bankmachine6_row_opened <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine6_trccon_ready <= 1'd0; + main_litedramcore_bankmachine6_trccon_count <= 3'd0; + main_litedramcore_bankmachine6_trascon_ready <= 1'd0; + main_litedramcore_bankmachine6_trascon_count <= 3'd0; + main_litedramcore_bankmachine7_level <= 5'd0; + main_litedramcore_bankmachine7_produce <= 4'd0; + main_litedramcore_bankmachine7_consume <= 4'd0; + main_litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine7_row <= 15'd0; + main_litedramcore_bankmachine7_row_opened <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine7_trccon_ready <= 1'd0; + main_litedramcore_bankmachine7_trccon_count <= 3'd0; + main_litedramcore_bankmachine7_trascon_ready <= 1'd0; + main_litedramcore_bankmachine7_trascon_count <= 3'd0; + main_litedramcore_choose_cmd_grant <= 3'd0; + main_litedramcore_choose_req_grant <= 3'd0; + main_litedramcore_trrdcon_ready <= 1'd0; + main_litedramcore_trrdcon_count <= 1'd0; + main_litedramcore_tfawcon_ready <= 1'd1; + main_litedramcore_tfawcon_window <= 5'd0; + main_litedramcore_tccdcon_ready <= 1'd0; + main_litedramcore_tccdcon_count <= 1'd0; + main_litedramcore_twtrcon_ready <= 1'd0; + main_litedramcore_twtrcon_count <= 3'd0; + main_litedramcore_time0 <= 5'd0; + main_litedramcore_time1 <= 4'd0; + main_init_done_storage <= 1'd0; + main_init_done_re <= 1'd0; + main_init_error_storage <= 1'd0; + main_init_error_re <= 1'd0; + builder_interface1_we <= 1'd0; + builder_refresher_state <= 2'd0; + builder_bankmachine0_state <= 4'd0; + builder_bankmachine1_state <= 4'd0; + builder_bankmachine2_state <= 4'd0; + builder_bankmachine3_state <= 4'd0; + builder_bankmachine4_state <= 4'd0; + builder_bankmachine5_state <= 4'd0; + builder_bankmachine6_state <= 4'd0; + builder_bankmachine7_state <= 4'd0; + builder_multiplexer_state <= 4'd0; + builder_new_master_wdata_ready0 <= 1'd0; + builder_new_master_wdata_ready1 <= 1'd0; + builder_new_master_rdata_valid0 <= 1'd0; + builder_new_master_rdata_valid1 <= 1'd0; + builder_new_master_rdata_valid2 <= 1'd0; + builder_new_master_rdata_valid3 <= 1'd0; + builder_new_master_rdata_valid4 <= 1'd0; + builder_new_master_rdata_valid5 <= 1'd0; + builder_new_master_rdata_valid6 <= 1'd0; + builder_new_master_rdata_valid7 <= 1'd0; + builder_new_master_rdata_valid8 <= 1'd0; + builder_state <= 2'd0; end end @@ -16133,4513 +16721,6199 @@ end // Specialized Logic //------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +// Instance BUFG of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG( - .I(clkout0), - .O(clkout_buf0) + // Inputs. + .I (main_clkout0), + + // Outputs. + .O (main_clkout_buf0) ); +//------------------------------------------------------------------------------ +// Instance BUFG_1 of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG_1( - .I(clkout1), - .O(clkout_buf1) + // Inputs. + .I (main_clkout1), + + // Outputs. + .O (main_clkout_buf1) ); +//------------------------------------------------------------------------------ +// Instance BUFG_2 of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG_2( - .I(clkout2), - .O(clkout_buf2) + // Inputs. + .I (main_clkout2), + + // Outputs. + .O (main_clkout_buf2) ); +//------------------------------------------------------------------------------ +// Instance BUFG_3 of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG_3( - .I(clkout3), - .O(clkout_buf3) + // Inputs. + .I (main_clkout3), + + // Outputs. + .O (main_clkout_buf3) ); +//------------------------------------------------------------------------------ +// Instance IDELAYCTRL of IDELAYCTRL Module. +//------------------------------------------------------------------------------ IDELAYCTRL IDELAYCTRL( - .REFCLK(iodelay_clk), - .RST(ic_reset) + // Inputs. + .REFCLK (iodelay_clk), + .RST (main_ic_reset) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(1'd0), - .D2(1'd1), - .D3(1'd0), - .D4(1'd1), - .D5(1'd0), - .D6(1'd1), - .D7(1'd0), - .D8(1'd1), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_sd_clk_se_nodelay) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (1'd0), + .D2 (1'd1), + .D3 (1'd0), + .D4 (1'd1), + .D5 (1'd0), + .D6 (1'd1), + .D7 (1'd0), + .D8 (1'd1), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_sd_clk_se_nodelay) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_sd_clk_se_delayed), - .ODATAIN(k7ddrphy_sd_clk_se_nodelay) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_sd_clk_se_delayed), + .ODATAIN (main_k7ddrphy_sd_clk_se_nodelay) ); +//------------------------------------------------------------------------------ +// Instance OBUFDS of OBUFDS Module. +//------------------------------------------------------------------------------ OBUFDS OBUFDS( - .I(k7ddrphy_sd_clk_se_delayed), - .O(ddram_clk_p), - .OB(ddram_clk_n) + // Inputs. + .I (main_k7ddrphy_sd_clk_se_delayed), + + // Outputs. + .O (ddram_clk_p), + .OB (ddram_clk_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_1 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_1 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_reset_n), - .D2(k7ddrphy_dfi_p0_reset_n), - .D3(k7ddrphy_dfi_p1_reset_n), - .D4(k7ddrphy_dfi_p1_reset_n), - .D5(k7ddrphy_dfi_p2_reset_n), - .D6(k7ddrphy_dfi_p2_reset_n), - .D7(k7ddrphy_dfi_p3_reset_n), - .D8(k7ddrphy_dfi_p3_reset_n), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq0) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_reset_n), + .D2 (main_k7ddrphy_dfi_p0_reset_n), + .D3 (main_k7ddrphy_dfi_p1_reset_n), + .D4 (main_k7ddrphy_dfi_p1_reset_n), + .D5 (main_k7ddrphy_dfi_p2_reset_n), + .D6 (main_k7ddrphy_dfi_p2_reset_n), + .D7 (main_k7ddrphy_dfi_p3_reset_n), + .D8 (main_k7ddrphy_dfi_p3_reset_n), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq0) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_1 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_1 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_reset_n), - .ODATAIN(k7ddrphy_oq0) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_reset_n), + .ODATAIN (main_k7ddrphy_oq0) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_2 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_2 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_cs_n), - .D2(k7ddrphy_dfi_p0_cs_n), - .D3(k7ddrphy_dfi_p1_cs_n), - .D4(k7ddrphy_dfi_p1_cs_n), - .D5(k7ddrphy_dfi_p2_cs_n), - .D6(k7ddrphy_dfi_p2_cs_n), - .D7(k7ddrphy_dfi_p3_cs_n), - .D8(k7ddrphy_dfi_p3_cs_n), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq1) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_cs_n), + .D2 (main_k7ddrphy_dfi_p0_cs_n), + .D3 (main_k7ddrphy_dfi_p1_cs_n), + .D4 (main_k7ddrphy_dfi_p1_cs_n), + .D5 (main_k7ddrphy_dfi_p2_cs_n), + .D6 (main_k7ddrphy_dfi_p2_cs_n), + .D7 (main_k7ddrphy_dfi_p3_cs_n), + .D8 (main_k7ddrphy_dfi_p3_cs_n), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq1) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_2 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_2 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_cs_n), - .ODATAIN(k7ddrphy_oq1) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_cs_n), + .ODATAIN (main_k7ddrphy_oq1) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_3 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_3 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_address[0]), - .D2(k7ddrphy_dfi_p0_address[0]), - .D3(k7ddrphy_dfi_p1_address[0]), - .D4(k7ddrphy_dfi_p1_address[0]), - .D5(k7ddrphy_dfi_p2_address[0]), - .D6(k7ddrphy_dfi_p2_address[0]), - .D7(k7ddrphy_dfi_p3_address[0]), - .D8(k7ddrphy_dfi_p3_address[0]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq2) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_address[0]), + .D2 (main_k7ddrphy_dfi_p0_address[0]), + .D3 (main_k7ddrphy_dfi_p1_address[0]), + .D4 (main_k7ddrphy_dfi_p1_address[0]), + .D5 (main_k7ddrphy_dfi_p2_address[0]), + .D6 (main_k7ddrphy_dfi_p2_address[0]), + .D7 (main_k7ddrphy_dfi_p3_address[0]), + .D8 (main_k7ddrphy_dfi_p3_address[0]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq2) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_3 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_3 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[0]), - .ODATAIN(k7ddrphy_oq2) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_a[0]), + .ODATAIN (main_k7ddrphy_oq2) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_4 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_4 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_address[1]), - .D2(k7ddrphy_dfi_p0_address[1]), - .D3(k7ddrphy_dfi_p1_address[1]), - .D4(k7ddrphy_dfi_p1_address[1]), - .D5(k7ddrphy_dfi_p2_address[1]), - .D6(k7ddrphy_dfi_p2_address[1]), - .D7(k7ddrphy_dfi_p3_address[1]), - .D8(k7ddrphy_dfi_p3_address[1]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq3) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_address[1]), + .D2 (main_k7ddrphy_dfi_p0_address[1]), + .D3 (main_k7ddrphy_dfi_p1_address[1]), + .D4 (main_k7ddrphy_dfi_p1_address[1]), + .D5 (main_k7ddrphy_dfi_p2_address[1]), + .D6 (main_k7ddrphy_dfi_p2_address[1]), + .D7 (main_k7ddrphy_dfi_p3_address[1]), + .D8 (main_k7ddrphy_dfi_p3_address[1]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq3) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_4 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_4 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[1]), - .ODATAIN(k7ddrphy_oq3) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_a[1]), + .ODATAIN (main_k7ddrphy_oq3) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_5 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_5 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_address[2]), - .D2(k7ddrphy_dfi_p0_address[2]), - .D3(k7ddrphy_dfi_p1_address[2]), - .D4(k7ddrphy_dfi_p1_address[2]), - .D5(k7ddrphy_dfi_p2_address[2]), - .D6(k7ddrphy_dfi_p2_address[2]), - .D7(k7ddrphy_dfi_p3_address[2]), - .D8(k7ddrphy_dfi_p3_address[2]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq4) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_address[2]), + .D2 (main_k7ddrphy_dfi_p0_address[2]), + .D3 (main_k7ddrphy_dfi_p1_address[2]), + .D4 (main_k7ddrphy_dfi_p1_address[2]), + .D5 (main_k7ddrphy_dfi_p2_address[2]), + .D6 (main_k7ddrphy_dfi_p2_address[2]), + .D7 (main_k7ddrphy_dfi_p3_address[2]), + .D8 (main_k7ddrphy_dfi_p3_address[2]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq4) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_5 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_5 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[2]), - .ODATAIN(k7ddrphy_oq4) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_a[2]), + .ODATAIN (main_k7ddrphy_oq4) ); -OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) +//------------------------------------------------------------------------------ +// Instance OSERDESE2_6 of OSERDESE2 Module. +//------------------------------------------------------------------------------ +OSERDESE2 #( + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_6 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_address[3]), - .D2(k7ddrphy_dfi_p0_address[3]), - .D3(k7ddrphy_dfi_p1_address[3]), - .D4(k7ddrphy_dfi_p1_address[3]), - .D5(k7ddrphy_dfi_p2_address[3]), - .D6(k7ddrphy_dfi_p2_address[3]), - .D7(k7ddrphy_dfi_p3_address[3]), - .D8(k7ddrphy_dfi_p3_address[3]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq5) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_address[3]), + .D2 (main_k7ddrphy_dfi_p0_address[3]), + .D3 (main_k7ddrphy_dfi_p1_address[3]), + .D4 (main_k7ddrphy_dfi_p1_address[3]), + .D5 (main_k7ddrphy_dfi_p2_address[3]), + .D6 (main_k7ddrphy_dfi_p2_address[3]), + .D7 (main_k7ddrphy_dfi_p3_address[3]), + .D8 (main_k7ddrphy_dfi_p3_address[3]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq5) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_6 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_6 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[3]), - .ODATAIN(k7ddrphy_oq5) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_a[3]), + .ODATAIN (main_k7ddrphy_oq5) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_7 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_7 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_address[4]), - .D2(k7ddrphy_dfi_p0_address[4]), - .D3(k7ddrphy_dfi_p1_address[4]), - .D4(k7ddrphy_dfi_p1_address[4]), - .D5(k7ddrphy_dfi_p2_address[4]), - .D6(k7ddrphy_dfi_p2_address[4]), - .D7(k7ddrphy_dfi_p3_address[4]), - .D8(k7ddrphy_dfi_p3_address[4]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq6) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_address[4]), + .D2 (main_k7ddrphy_dfi_p0_address[4]), + .D3 (main_k7ddrphy_dfi_p1_address[4]), + .D4 (main_k7ddrphy_dfi_p1_address[4]), + .D5 (main_k7ddrphy_dfi_p2_address[4]), + .D6 (main_k7ddrphy_dfi_p2_address[4]), + .D7 (main_k7ddrphy_dfi_p3_address[4]), + .D8 (main_k7ddrphy_dfi_p3_address[4]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq6) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_7 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_7 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[4]), - .ODATAIN(k7ddrphy_oq6) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_a[4]), + .ODATAIN (main_k7ddrphy_oq6) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_8 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_8 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_address[5]), - .D2(k7ddrphy_dfi_p0_address[5]), - .D3(k7ddrphy_dfi_p1_address[5]), - .D4(k7ddrphy_dfi_p1_address[5]), - .D5(k7ddrphy_dfi_p2_address[5]), - .D6(k7ddrphy_dfi_p2_address[5]), - .D7(k7ddrphy_dfi_p3_address[5]), - .D8(k7ddrphy_dfi_p3_address[5]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq7) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_address[5]), + .D2 (main_k7ddrphy_dfi_p0_address[5]), + .D3 (main_k7ddrphy_dfi_p1_address[5]), + .D4 (main_k7ddrphy_dfi_p1_address[5]), + .D5 (main_k7ddrphy_dfi_p2_address[5]), + .D6 (main_k7ddrphy_dfi_p2_address[5]), + .D7 (main_k7ddrphy_dfi_p3_address[5]), + .D8 (main_k7ddrphy_dfi_p3_address[5]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq7) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_8 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_8 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[5]), - .ODATAIN(k7ddrphy_oq7) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_a[5]), + .ODATAIN (main_k7ddrphy_oq7) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_9 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_9 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_address[6]), - .D2(k7ddrphy_dfi_p0_address[6]), - .D3(k7ddrphy_dfi_p1_address[6]), - .D4(k7ddrphy_dfi_p1_address[6]), - .D5(k7ddrphy_dfi_p2_address[6]), - .D6(k7ddrphy_dfi_p2_address[6]), - .D7(k7ddrphy_dfi_p3_address[6]), - .D8(k7ddrphy_dfi_p3_address[6]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq8) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_address[6]), + .D2 (main_k7ddrphy_dfi_p0_address[6]), + .D3 (main_k7ddrphy_dfi_p1_address[6]), + .D4 (main_k7ddrphy_dfi_p1_address[6]), + .D5 (main_k7ddrphy_dfi_p2_address[6]), + .D6 (main_k7ddrphy_dfi_p2_address[6]), + .D7 (main_k7ddrphy_dfi_p3_address[6]), + .D8 (main_k7ddrphy_dfi_p3_address[6]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq8) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_9 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_9 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[6]), - .ODATAIN(k7ddrphy_oq8) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_a[6]), + .ODATAIN (main_k7ddrphy_oq8) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_10 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_10 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_address[7]), - .D2(k7ddrphy_dfi_p0_address[7]), - .D3(k7ddrphy_dfi_p1_address[7]), - .D4(k7ddrphy_dfi_p1_address[7]), - .D5(k7ddrphy_dfi_p2_address[7]), - .D6(k7ddrphy_dfi_p2_address[7]), - .D7(k7ddrphy_dfi_p3_address[7]), - .D8(k7ddrphy_dfi_p3_address[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq9) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_address[7]), + .D2 (main_k7ddrphy_dfi_p0_address[7]), + .D3 (main_k7ddrphy_dfi_p1_address[7]), + .D4 (main_k7ddrphy_dfi_p1_address[7]), + .D5 (main_k7ddrphy_dfi_p2_address[7]), + .D6 (main_k7ddrphy_dfi_p2_address[7]), + .D7 (main_k7ddrphy_dfi_p3_address[7]), + .D8 (main_k7ddrphy_dfi_p3_address[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq9) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_10 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_10 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[7]), - .ODATAIN(k7ddrphy_oq9) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_a[7]), + .ODATAIN (main_k7ddrphy_oq9) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_11 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_11 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_address[8]), - .D2(k7ddrphy_dfi_p0_address[8]), - .D3(k7ddrphy_dfi_p1_address[8]), - .D4(k7ddrphy_dfi_p1_address[8]), - .D5(k7ddrphy_dfi_p2_address[8]), - .D6(k7ddrphy_dfi_p2_address[8]), - .D7(k7ddrphy_dfi_p3_address[8]), - .D8(k7ddrphy_dfi_p3_address[8]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq10) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_address[8]), + .D2 (main_k7ddrphy_dfi_p0_address[8]), + .D3 (main_k7ddrphy_dfi_p1_address[8]), + .D4 (main_k7ddrphy_dfi_p1_address[8]), + .D5 (main_k7ddrphy_dfi_p2_address[8]), + .D6 (main_k7ddrphy_dfi_p2_address[8]), + .D7 (main_k7ddrphy_dfi_p3_address[8]), + .D8 (main_k7ddrphy_dfi_p3_address[8]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq10) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_11 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_11 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[8]), - .ODATAIN(k7ddrphy_oq10) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_a[8]), + .ODATAIN (main_k7ddrphy_oq10) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_12 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_12 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_address[9]), - .D2(k7ddrphy_dfi_p0_address[9]), - .D3(k7ddrphy_dfi_p1_address[9]), - .D4(k7ddrphy_dfi_p1_address[9]), - .D5(k7ddrphy_dfi_p2_address[9]), - .D6(k7ddrphy_dfi_p2_address[9]), - .D7(k7ddrphy_dfi_p3_address[9]), - .D8(k7ddrphy_dfi_p3_address[9]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq11) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_address[9]), + .D2 (main_k7ddrphy_dfi_p0_address[9]), + .D3 (main_k7ddrphy_dfi_p1_address[9]), + .D4 (main_k7ddrphy_dfi_p1_address[9]), + .D5 (main_k7ddrphy_dfi_p2_address[9]), + .D6 (main_k7ddrphy_dfi_p2_address[9]), + .D7 (main_k7ddrphy_dfi_p3_address[9]), + .D8 (main_k7ddrphy_dfi_p3_address[9]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq11) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_12 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_12 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[9]), - .ODATAIN(k7ddrphy_oq11) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_a[9]), + .ODATAIN (main_k7ddrphy_oq11) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_13 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_13 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_address[10]), - .D2(k7ddrphy_dfi_p0_address[10]), - .D3(k7ddrphy_dfi_p1_address[10]), - .D4(k7ddrphy_dfi_p1_address[10]), - .D5(k7ddrphy_dfi_p2_address[10]), - .D6(k7ddrphy_dfi_p2_address[10]), - .D7(k7ddrphy_dfi_p3_address[10]), - .D8(k7ddrphy_dfi_p3_address[10]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq12) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_address[10]), + .D2 (main_k7ddrphy_dfi_p0_address[10]), + .D3 (main_k7ddrphy_dfi_p1_address[10]), + .D4 (main_k7ddrphy_dfi_p1_address[10]), + .D5 (main_k7ddrphy_dfi_p2_address[10]), + .D6 (main_k7ddrphy_dfi_p2_address[10]), + .D7 (main_k7ddrphy_dfi_p3_address[10]), + .D8 (main_k7ddrphy_dfi_p3_address[10]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq12) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_13 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_13 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[10]), - .ODATAIN(k7ddrphy_oq12) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_a[10]), + .ODATAIN (main_k7ddrphy_oq12) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_14 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_14 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_address[11]), - .D2(k7ddrphy_dfi_p0_address[11]), - .D3(k7ddrphy_dfi_p1_address[11]), - .D4(k7ddrphy_dfi_p1_address[11]), - .D5(k7ddrphy_dfi_p2_address[11]), - .D6(k7ddrphy_dfi_p2_address[11]), - .D7(k7ddrphy_dfi_p3_address[11]), - .D8(k7ddrphy_dfi_p3_address[11]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq13) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_address[11]), + .D2 (main_k7ddrphy_dfi_p0_address[11]), + .D3 (main_k7ddrphy_dfi_p1_address[11]), + .D4 (main_k7ddrphy_dfi_p1_address[11]), + .D5 (main_k7ddrphy_dfi_p2_address[11]), + .D6 (main_k7ddrphy_dfi_p2_address[11]), + .D7 (main_k7ddrphy_dfi_p3_address[11]), + .D8 (main_k7ddrphy_dfi_p3_address[11]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq13) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_14 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_14 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[11]), - .ODATAIN(k7ddrphy_oq13) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_a[11]), + .ODATAIN (main_k7ddrphy_oq13) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_15 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_15 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_address[12]), - .D2(k7ddrphy_dfi_p0_address[12]), - .D3(k7ddrphy_dfi_p1_address[12]), - .D4(k7ddrphy_dfi_p1_address[12]), - .D5(k7ddrphy_dfi_p2_address[12]), - .D6(k7ddrphy_dfi_p2_address[12]), - .D7(k7ddrphy_dfi_p3_address[12]), - .D8(k7ddrphy_dfi_p3_address[12]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq14) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_address[12]), + .D2 (main_k7ddrphy_dfi_p0_address[12]), + .D3 (main_k7ddrphy_dfi_p1_address[12]), + .D4 (main_k7ddrphy_dfi_p1_address[12]), + .D5 (main_k7ddrphy_dfi_p2_address[12]), + .D6 (main_k7ddrphy_dfi_p2_address[12]), + .D7 (main_k7ddrphy_dfi_p3_address[12]), + .D8 (main_k7ddrphy_dfi_p3_address[12]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq14) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_15 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_15 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[12]), - .ODATAIN(k7ddrphy_oq14) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_a[12]), + .ODATAIN (main_k7ddrphy_oq14) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_16 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_16 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_address[13]), - .D2(k7ddrphy_dfi_p0_address[13]), - .D3(k7ddrphy_dfi_p1_address[13]), - .D4(k7ddrphy_dfi_p1_address[13]), - .D5(k7ddrphy_dfi_p2_address[13]), - .D6(k7ddrphy_dfi_p2_address[13]), - .D7(k7ddrphy_dfi_p3_address[13]), - .D8(k7ddrphy_dfi_p3_address[13]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq15) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_address[13]), + .D2 (main_k7ddrphy_dfi_p0_address[13]), + .D3 (main_k7ddrphy_dfi_p1_address[13]), + .D4 (main_k7ddrphy_dfi_p1_address[13]), + .D5 (main_k7ddrphy_dfi_p2_address[13]), + .D6 (main_k7ddrphy_dfi_p2_address[13]), + .D7 (main_k7ddrphy_dfi_p3_address[13]), + .D8 (main_k7ddrphy_dfi_p3_address[13]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq15) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_16 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_16 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[13]), - .ODATAIN(k7ddrphy_oq15) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_a[13]), + .ODATAIN (main_k7ddrphy_oq15) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_17 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_17 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_address[14]), - .D2(k7ddrphy_dfi_p0_address[14]), - .D3(k7ddrphy_dfi_p1_address[14]), - .D4(k7ddrphy_dfi_p1_address[14]), - .D5(k7ddrphy_dfi_p2_address[14]), - .D6(k7ddrphy_dfi_p2_address[14]), - .D7(k7ddrphy_dfi_p3_address[14]), - .D8(k7ddrphy_dfi_p3_address[14]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq16) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_address[14]), + .D2 (main_k7ddrphy_dfi_p0_address[14]), + .D3 (main_k7ddrphy_dfi_p1_address[14]), + .D4 (main_k7ddrphy_dfi_p1_address[14]), + .D5 (main_k7ddrphy_dfi_p2_address[14]), + .D6 (main_k7ddrphy_dfi_p2_address[14]), + .D7 (main_k7ddrphy_dfi_p3_address[14]), + .D8 (main_k7ddrphy_dfi_p3_address[14]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq16) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_17 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_17 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_a[14]), - .ODATAIN(k7ddrphy_oq16) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_a[14]), + .ODATAIN (main_k7ddrphy_oq16) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_18 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_18 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_bank[0]), - .D2(k7ddrphy_dfi_p0_bank[0]), - .D3(k7ddrphy_dfi_p1_bank[0]), - .D4(k7ddrphy_dfi_p1_bank[0]), - .D5(k7ddrphy_dfi_p2_bank[0]), - .D6(k7ddrphy_dfi_p2_bank[0]), - .D7(k7ddrphy_dfi_p3_bank[0]), - .D8(k7ddrphy_dfi_p3_bank[0]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq17) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_bank[0]), + .D2 (main_k7ddrphy_dfi_p0_bank[0]), + .D3 (main_k7ddrphy_dfi_p1_bank[0]), + .D4 (main_k7ddrphy_dfi_p1_bank[0]), + .D5 (main_k7ddrphy_dfi_p2_bank[0]), + .D6 (main_k7ddrphy_dfi_p2_bank[0]), + .D7 (main_k7ddrphy_dfi_p3_bank[0]), + .D8 (main_k7ddrphy_dfi_p3_bank[0]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq17) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_18 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_18 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_pads_ba[0]), - .ODATAIN(k7ddrphy_oq17) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_pads_ba[0]), + .ODATAIN (main_k7ddrphy_oq17) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_19 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_19 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_bank[1]), - .D2(k7ddrphy_dfi_p0_bank[1]), - .D3(k7ddrphy_dfi_p1_bank[1]), - .D4(k7ddrphy_dfi_p1_bank[1]), - .D5(k7ddrphy_dfi_p2_bank[1]), - .D6(k7ddrphy_dfi_p2_bank[1]), - .D7(k7ddrphy_dfi_p3_bank[1]), - .D8(k7ddrphy_dfi_p3_bank[1]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq18) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_bank[1]), + .D2 (main_k7ddrphy_dfi_p0_bank[1]), + .D3 (main_k7ddrphy_dfi_p1_bank[1]), + .D4 (main_k7ddrphy_dfi_p1_bank[1]), + .D5 (main_k7ddrphy_dfi_p2_bank[1]), + .D6 (main_k7ddrphy_dfi_p2_bank[1]), + .D7 (main_k7ddrphy_dfi_p3_bank[1]), + .D8 (main_k7ddrphy_dfi_p3_bank[1]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq18) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_19 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_19 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_pads_ba[1]), - .ODATAIN(k7ddrphy_oq18) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_pads_ba[1]), + .ODATAIN (main_k7ddrphy_oq18) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_20 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_20 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_bank[2]), - .D2(k7ddrphy_dfi_p0_bank[2]), - .D3(k7ddrphy_dfi_p1_bank[2]), - .D4(k7ddrphy_dfi_p1_bank[2]), - .D5(k7ddrphy_dfi_p2_bank[2]), - .D6(k7ddrphy_dfi_p2_bank[2]), - .D7(k7ddrphy_dfi_p3_bank[2]), - .D8(k7ddrphy_dfi_p3_bank[2]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq19) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_bank[2]), + .D2 (main_k7ddrphy_dfi_p0_bank[2]), + .D3 (main_k7ddrphy_dfi_p1_bank[2]), + .D4 (main_k7ddrphy_dfi_p1_bank[2]), + .D5 (main_k7ddrphy_dfi_p2_bank[2]), + .D6 (main_k7ddrphy_dfi_p2_bank[2]), + .D7 (main_k7ddrphy_dfi_p3_bank[2]), + .D8 (main_k7ddrphy_dfi_p3_bank[2]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq19) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_20 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_20 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_pads_ba[2]), - .ODATAIN(k7ddrphy_oq19) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_pads_ba[2]), + .ODATAIN (main_k7ddrphy_oq19) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_21 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_21 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_ras_n), - .D2(k7ddrphy_dfi_p0_ras_n), - .D3(k7ddrphy_dfi_p1_ras_n), - .D4(k7ddrphy_dfi_p1_ras_n), - .D5(k7ddrphy_dfi_p2_ras_n), - .D6(k7ddrphy_dfi_p2_ras_n), - .D7(k7ddrphy_dfi_p3_ras_n), - .D8(k7ddrphy_dfi_p3_ras_n), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq20) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_ras_n), + .D2 (main_k7ddrphy_dfi_p0_ras_n), + .D3 (main_k7ddrphy_dfi_p1_ras_n), + .D4 (main_k7ddrphy_dfi_p1_ras_n), + .D5 (main_k7ddrphy_dfi_p2_ras_n), + .D6 (main_k7ddrphy_dfi_p2_ras_n), + .D7 (main_k7ddrphy_dfi_p3_ras_n), + .D8 (main_k7ddrphy_dfi_p3_ras_n), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq20) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_21 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_21 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_ras_n), - .ODATAIN(k7ddrphy_oq20) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_ras_n), + .ODATAIN (main_k7ddrphy_oq20) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_22 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_22 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_cas_n), - .D2(k7ddrphy_dfi_p0_cas_n), - .D3(k7ddrphy_dfi_p1_cas_n), - .D4(k7ddrphy_dfi_p1_cas_n), - .D5(k7ddrphy_dfi_p2_cas_n), - .D6(k7ddrphy_dfi_p2_cas_n), - .D7(k7ddrphy_dfi_p3_cas_n), - .D8(k7ddrphy_dfi_p3_cas_n), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq21) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_cas_n), + .D2 (main_k7ddrphy_dfi_p0_cas_n), + .D3 (main_k7ddrphy_dfi_p1_cas_n), + .D4 (main_k7ddrphy_dfi_p1_cas_n), + .D5 (main_k7ddrphy_dfi_p2_cas_n), + .D6 (main_k7ddrphy_dfi_p2_cas_n), + .D7 (main_k7ddrphy_dfi_p3_cas_n), + .D8 (main_k7ddrphy_dfi_p3_cas_n), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq21) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_22 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_22 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_cas_n), - .ODATAIN(k7ddrphy_oq21) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_cas_n), + .ODATAIN (main_k7ddrphy_oq21) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_23 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_23 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_we_n), - .D2(k7ddrphy_dfi_p0_we_n), - .D3(k7ddrphy_dfi_p1_we_n), - .D4(k7ddrphy_dfi_p1_we_n), - .D5(k7ddrphy_dfi_p2_we_n), - .D6(k7ddrphy_dfi_p2_we_n), - .D7(k7ddrphy_dfi_p3_we_n), - .D8(k7ddrphy_dfi_p3_we_n), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq22) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_we_n), + .D2 (main_k7ddrphy_dfi_p0_we_n), + .D3 (main_k7ddrphy_dfi_p1_we_n), + .D4 (main_k7ddrphy_dfi_p1_we_n), + .D5 (main_k7ddrphy_dfi_p2_we_n), + .D6 (main_k7ddrphy_dfi_p2_we_n), + .D7 (main_k7ddrphy_dfi_p3_we_n), + .D8 (main_k7ddrphy_dfi_p3_we_n), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq22) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_23 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_23 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_we_n), - .ODATAIN(k7ddrphy_oq22) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_we_n), + .ODATAIN (main_k7ddrphy_oq22) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_24 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_24 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_cke), - .D2(k7ddrphy_dfi_p0_cke), - .D3(k7ddrphy_dfi_p1_cke), - .D4(k7ddrphy_dfi_p1_cke), - .D5(k7ddrphy_dfi_p2_cke), - .D6(k7ddrphy_dfi_p2_cke), - .D7(k7ddrphy_dfi_p3_cke), - .D8(k7ddrphy_dfi_p3_cke), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq23) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_cke), + .D2 (main_k7ddrphy_dfi_p0_cke), + .D3 (main_k7ddrphy_dfi_p1_cke), + .D4 (main_k7ddrphy_dfi_p1_cke), + .D5 (main_k7ddrphy_dfi_p2_cke), + .D6 (main_k7ddrphy_dfi_p2_cke), + .D7 (main_k7ddrphy_dfi_p3_cke), + .D8 (main_k7ddrphy_dfi_p3_cke), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq23) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_24 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_24 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_cke), - .ODATAIN(k7ddrphy_oq23) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_cke), + .ODATAIN (main_k7ddrphy_oq23) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_25 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_25 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_dfi_p0_odt), - .D2(k7ddrphy_dfi_p0_odt), - .D3(k7ddrphy_dfi_p1_odt), - .D4(k7ddrphy_dfi_p1_odt), - .D5(k7ddrphy_dfi_p2_odt), - .D6(k7ddrphy_dfi_p2_odt), - .D7(k7ddrphy_dfi_p3_odt), - .D8(k7ddrphy_dfi_p3_odt), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_oq24) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_dfi_p0_odt), + .D2 (main_k7ddrphy_dfi_p0_odt), + .D3 (main_k7ddrphy_dfi_p1_odt), + .D4 (main_k7ddrphy_dfi_p1_odt), + .D5 (main_k7ddrphy_dfi_p2_odt), + .D6 (main_k7ddrphy_dfi_p2_odt), + .D7 (main_k7ddrphy_dfi_p3_odt), + .D8 (main_k7ddrphy_dfi_p3_odt), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_oq24) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_25 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_25 ( - .C(sys_clk), - .CE(k7ddrphy_cdly_inc_re), - .INC(1'd1), - .LD(((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_odt), - .ODATAIN(k7ddrphy_oq24) + // Inputs. + .C (sys_clk), + .CE (main_k7ddrphy_cdly_inc_re), + .INC (1'd1), + .LD (((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_odt), + .ODATAIN (main_k7ddrphy_oq24) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_26 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_26 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip00[0]), - .D2(k7ddrphy_bitslip00[1]), - .D3(k7ddrphy_bitslip00[2]), - .D4(k7ddrphy_bitslip00[3]), - .D5(k7ddrphy_bitslip00[4]), - .D6(k7ddrphy_bitslip00[5]), - .D7(k7ddrphy_bitslip00[6]), - .D8(k7ddrphy_bitslip00[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OFB(k7ddrphy_dqs_o_no_delay0), - .OQ(k7ddrphy0), - .TQ(k7ddrphy_dqs_t0) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip00[0]), + .D2 (main_k7ddrphy_bitslip00[1]), + .D3 (main_k7ddrphy_bitslip00[2]), + .D4 (main_k7ddrphy_bitslip00[3]), + .D5 (main_k7ddrphy_bitslip00[4]), + .D6 (main_k7ddrphy_bitslip00[5]), + .D7 (main_k7ddrphy_bitslip00[6]), + .D8 (main_k7ddrphy_bitslip00[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OFB (main_k7ddrphy_dqs_o_no_delay0), + .OQ (main_k7ddrphy0), + .TQ (main_k7ddrphy_dqs_t0) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_26 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(4'd8), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (4'd8), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_26 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dqs_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dqs_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dqs_o_delayed0), - .ODATAIN(k7ddrphy_dqs_o_no_delay0) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dqs_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dqs_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dqs_o_delayed0), + .ODATAIN (main_k7ddrphy_dqs_o_no_delay0) ); +//------------------------------------------------------------------------------ +// Instance IOBUFDS of IOBUFDS Module. +//------------------------------------------------------------------------------ IOBUFDS IOBUFDS( - .I(k7ddrphy_dqs_o_delayed0), - .T(k7ddrphy_dqs_t0), - .IO(ddram_dqs_p[0]), - .IOB(ddram_dqs_n[0]) + // Inputs. + .I (main_k7ddrphy_dqs_o_delayed0), + .T (main_k7ddrphy_dqs_t0), + + // InOuts. + .IO (ddram_dqs_p[0]), + .IOB (ddram_dqs_n[0]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_27 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_27 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip10[0]), - .D2(k7ddrphy_bitslip10[1]), - .D3(k7ddrphy_bitslip10[2]), - .D4(k7ddrphy_bitslip10[3]), - .D5(k7ddrphy_bitslip10[4]), - .D6(k7ddrphy_bitslip10[5]), - .D7(k7ddrphy_bitslip10[6]), - .D8(k7ddrphy_bitslip10[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OFB(k7ddrphy_dqs_o_no_delay1), - .OQ(k7ddrphy1), - .TQ(k7ddrphy_dqs_t1) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip10[0]), + .D2 (main_k7ddrphy_bitslip10[1]), + .D3 (main_k7ddrphy_bitslip10[2]), + .D4 (main_k7ddrphy_bitslip10[3]), + .D5 (main_k7ddrphy_bitslip10[4]), + .D6 (main_k7ddrphy_bitslip10[5]), + .D7 (main_k7ddrphy_bitslip10[6]), + .D8 (main_k7ddrphy_bitslip10[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OFB (main_k7ddrphy_dqs_o_no_delay1), + .OQ (main_k7ddrphy1), + .TQ (main_k7ddrphy_dqs_t1) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_27 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(4'd8), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (4'd8), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_27 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dqs_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dqs_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dqs_o_delayed1), - .ODATAIN(k7ddrphy_dqs_o_no_delay1) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dqs_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dqs_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dqs_o_delayed1), + .ODATAIN (main_k7ddrphy_dqs_o_no_delay1) ); +//------------------------------------------------------------------------------ +// Instance IOBUFDS_1 of IOBUFDS Module. +//------------------------------------------------------------------------------ IOBUFDS IOBUFDS_1( - .I(k7ddrphy_dqs_o_delayed1), - .T(k7ddrphy_dqs_t1), - .IO(ddram_dqs_p[1]), - .IOB(ddram_dqs_n[1]) + // Inputs. + .I (main_k7ddrphy_dqs_o_delayed1), + .T (main_k7ddrphy_dqs_t1), + + // InOuts. + .IO (ddram_dqs_p[1]), + .IOB (ddram_dqs_n[1]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_28 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_28 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip20[0]), - .D2(k7ddrphy_bitslip20[1]), - .D3(k7ddrphy_bitslip20[2]), - .D4(k7ddrphy_bitslip20[3]), - .D5(k7ddrphy_bitslip20[4]), - .D6(k7ddrphy_bitslip20[5]), - .D7(k7ddrphy_bitslip20[6]), - .D8(k7ddrphy_bitslip20[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OFB(k7ddrphy_dqs_o_no_delay2), - .OQ(k7ddrphy2), - .TQ(k7ddrphy_dqs_t2) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip20[0]), + .D2 (main_k7ddrphy_bitslip20[1]), + .D3 (main_k7ddrphy_bitslip20[2]), + .D4 (main_k7ddrphy_bitslip20[3]), + .D5 (main_k7ddrphy_bitslip20[4]), + .D6 (main_k7ddrphy_bitslip20[5]), + .D7 (main_k7ddrphy_bitslip20[6]), + .D8 (main_k7ddrphy_bitslip20[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OFB (main_k7ddrphy_dqs_o_no_delay2), + .OQ (main_k7ddrphy2), + .TQ (main_k7ddrphy_dqs_t2) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_28 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(4'd8), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (4'd8), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_28 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dqs_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dqs_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dqs_o_delayed2), - .ODATAIN(k7ddrphy_dqs_o_no_delay2) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dqs_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dqs_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dqs_o_delayed2), + .ODATAIN (main_k7ddrphy_dqs_o_no_delay2) ); +//------------------------------------------------------------------------------ +// Instance IOBUFDS_2 of IOBUFDS Module. +//------------------------------------------------------------------------------ IOBUFDS IOBUFDS_2( - .I(k7ddrphy_dqs_o_delayed2), - .T(k7ddrphy_dqs_t2), - .IO(ddram_dqs_p[2]), - .IOB(ddram_dqs_n[2]) + // Inputs. + .I (main_k7ddrphy_dqs_o_delayed2), + .T (main_k7ddrphy_dqs_t2), + + // InOuts. + .IO (ddram_dqs_p[2]), + .IOB (ddram_dqs_n[2]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_29 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_29 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip30[0]), - .D2(k7ddrphy_bitslip30[1]), - .D3(k7ddrphy_bitslip30[2]), - .D4(k7ddrphy_bitslip30[3]), - .D5(k7ddrphy_bitslip30[4]), - .D6(k7ddrphy_bitslip30[5]), - .D7(k7ddrphy_bitslip30[6]), - .D8(k7ddrphy_bitslip30[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OFB(k7ddrphy_dqs_o_no_delay3), - .OQ(k7ddrphy3), - .TQ(k7ddrphy_dqs_t3) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip30[0]), + .D2 (main_k7ddrphy_bitslip30[1]), + .D3 (main_k7ddrphy_bitslip30[2]), + .D4 (main_k7ddrphy_bitslip30[3]), + .D5 (main_k7ddrphy_bitslip30[4]), + .D6 (main_k7ddrphy_bitslip30[5]), + .D7 (main_k7ddrphy_bitslip30[6]), + .D8 (main_k7ddrphy_bitslip30[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OFB (main_k7ddrphy_dqs_o_no_delay3), + .OQ (main_k7ddrphy3), + .TQ (main_k7ddrphy_dqs_t3) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_29 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(4'd8), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (4'd8), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_29 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dqs_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dqs_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dqs_o_delayed3), - .ODATAIN(k7ddrphy_dqs_o_no_delay3) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dqs_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dqs_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dqs_o_delayed3), + .ODATAIN (main_k7ddrphy_dqs_o_no_delay3) ); +//------------------------------------------------------------------------------ +// Instance IOBUFDS_3 of IOBUFDS Module. +//------------------------------------------------------------------------------ IOBUFDS IOBUFDS_3( - .I(k7ddrphy_dqs_o_delayed3), - .T(k7ddrphy_dqs_t3), - .IO(ddram_dqs_p[3]), - .IOB(ddram_dqs_n[3]) + // Inputs. + .I (main_k7ddrphy_dqs_o_delayed3), + .T (main_k7ddrphy_dqs_t3), + + // InOuts. + .IO (ddram_dqs_p[3]), + .IOB (ddram_dqs_n[3]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_30 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_30 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip01[0]), - .D2(k7ddrphy_bitslip01[1]), - .D3(k7ddrphy_bitslip01[2]), - .D4(k7ddrphy_bitslip01[3]), - .D5(k7ddrphy_bitslip01[4]), - .D6(k7ddrphy_bitslip01[5]), - .D7(k7ddrphy_bitslip01[6]), - .D8(k7ddrphy_bitslip01[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_dm_o_nodelay0) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip01[0]), + .D2 (main_k7ddrphy_bitslip01[1]), + .D3 (main_k7ddrphy_bitslip01[2]), + .D4 (main_k7ddrphy_bitslip01[3]), + .D5 (main_k7ddrphy_bitslip01[4]), + .D6 (main_k7ddrphy_bitslip01[5]), + .D7 (main_k7ddrphy_bitslip01[6]), + .D8 (main_k7ddrphy_bitslip01[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_dm_o_nodelay0) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_30 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_30 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_dm[0]), - .ODATAIN(k7ddrphy_dm_o_nodelay0) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_dm[0]), + .ODATAIN (main_k7ddrphy_dm_o_nodelay0) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_31 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_31 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip11[0]), - .D2(k7ddrphy_bitslip11[1]), - .D3(k7ddrphy_bitslip11[2]), - .D4(k7ddrphy_bitslip11[3]), - .D5(k7ddrphy_bitslip11[4]), - .D6(k7ddrphy_bitslip11[5]), - .D7(k7ddrphy_bitslip11[6]), - .D8(k7ddrphy_bitslip11[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_dm_o_nodelay1) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip11[0]), + .D2 (main_k7ddrphy_bitslip11[1]), + .D3 (main_k7ddrphy_bitslip11[2]), + .D4 (main_k7ddrphy_bitslip11[3]), + .D5 (main_k7ddrphy_bitslip11[4]), + .D6 (main_k7ddrphy_bitslip11[5]), + .D7 (main_k7ddrphy_bitslip11[6]), + .D8 (main_k7ddrphy_bitslip11[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_dm_o_nodelay1) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_31 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_31 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_dm[1]), - .ODATAIN(k7ddrphy_dm_o_nodelay1) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_dm[1]), + .ODATAIN (main_k7ddrphy_dm_o_nodelay1) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_32 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_32 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip21[0]), - .D2(k7ddrphy_bitslip21[1]), - .D3(k7ddrphy_bitslip21[2]), - .D4(k7ddrphy_bitslip21[3]), - .D5(k7ddrphy_bitslip21[4]), - .D6(k7ddrphy_bitslip21[5]), - .D7(k7ddrphy_bitslip21[6]), - .D8(k7ddrphy_bitslip21[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_dm_o_nodelay2) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip21[0]), + .D2 (main_k7ddrphy_bitslip21[1]), + .D3 (main_k7ddrphy_bitslip21[2]), + .D4 (main_k7ddrphy_bitslip21[3]), + .D5 (main_k7ddrphy_bitslip21[4]), + .D6 (main_k7ddrphy_bitslip21[5]), + .D7 (main_k7ddrphy_bitslip21[6]), + .D8 (main_k7ddrphy_bitslip21[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_dm_o_nodelay2) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_32 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_32 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_dm[2]), - .ODATAIN(k7ddrphy_dm_o_nodelay2) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_dm[2]), + .ODATAIN (main_k7ddrphy_dm_o_nodelay2) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_33 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_33 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip31[0]), - .D2(k7ddrphy_bitslip31[1]), - .D3(k7ddrphy_bitslip31[2]), - .D4(k7ddrphy_bitslip31[3]), - .D5(k7ddrphy_bitslip31[4]), - .D6(k7ddrphy_bitslip31[5]), - .D7(k7ddrphy_bitslip31[6]), - .D8(k7ddrphy_bitslip31[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .OQ(k7ddrphy_dm_o_nodelay3) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip31[0]), + .D2 (main_k7ddrphy_bitslip31[1]), + .D3 (main_k7ddrphy_bitslip31[2]), + .D4 (main_k7ddrphy_bitslip31[3]), + .D5 (main_k7ddrphy_bitslip31[4]), + .D6 (main_k7ddrphy_bitslip31[5]), + .D7 (main_k7ddrphy_bitslip31[6]), + .D8 (main_k7ddrphy_bitslip31[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_k7ddrphy_dm_o_nodelay3) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_33 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_33 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(ddram_dm[3]), - .ODATAIN(k7ddrphy_dm_o_nodelay3) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (ddram_dm[3]), + .ODATAIN (main_k7ddrphy_dm_o_nodelay3) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_34 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_34 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip02[0]), - .D2(k7ddrphy_bitslip02[1]), - .D3(k7ddrphy_bitslip02[2]), - .D4(k7ddrphy_bitslip02[3]), - .D5(k7ddrphy_bitslip02[4]), - .D6(k7ddrphy_bitslip02[5]), - .D7(k7ddrphy_bitslip02[6]), - .D8(k7ddrphy_bitslip02[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay0), - .TQ(k7ddrphy_dq_t0) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip02[0]), + .D2 (main_k7ddrphy_bitslip02[1]), + .D3 (main_k7ddrphy_bitslip02[2]), + .D4 (main_k7ddrphy_bitslip02[3]), + .D5 (main_k7ddrphy_bitslip02[4]), + .D6 (main_k7ddrphy_bitslip02[5]), + .D7 (main_k7ddrphy_bitslip02[6]), + .D8 (main_k7ddrphy_bitslip02[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay0), + .TQ (main_k7ddrphy_dq_t0) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed0), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip03[7]), - .Q2(k7ddrphy_bitslip03[6]), - .Q3(k7ddrphy_bitslip03[5]), - .Q4(k7ddrphy_bitslip03[4]), - .Q5(k7ddrphy_bitslip03[3]), - .Q6(k7ddrphy_bitslip03[2]), - .Q7(k7ddrphy_bitslip03[1]), - .Q8(k7ddrphy_bitslip03[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed0), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip03[7]), + .Q2 (main_k7ddrphy_bitslip03[6]), + .Q3 (main_k7ddrphy_bitslip03[5]), + .Q4 (main_k7ddrphy_bitslip03[4]), + .Q5 (main_k7ddrphy_bitslip03[3]), + .Q6 (main_k7ddrphy_bitslip03[2]), + .Q7 (main_k7ddrphy_bitslip03[1]), + .Q8 (main_k7ddrphy_bitslip03[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_34 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_34 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed0), - .ODATAIN(k7ddrphy_dq_o_nodelay0) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed0), + .ODATAIN (main_k7ddrphy_dq_o_nodelay0) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay0), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed0) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay0), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed0) ); +//------------------------------------------------------------------------------ +// Instance IOBUF of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF( - .I(k7ddrphy_dq_o_delayed0), - .T(k7ddrphy_dq_t0), - .IO(ddram_dq[0]), - .O(k7ddrphy_dq_i_nodelay0) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed0), + .T (main_k7ddrphy_dq_t0), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay0), + + // InOuts. + .IO (ddram_dq[0]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_35 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_35 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip12[0]), - .D2(k7ddrphy_bitslip12[1]), - .D3(k7ddrphy_bitslip12[2]), - .D4(k7ddrphy_bitslip12[3]), - .D5(k7ddrphy_bitslip12[4]), - .D6(k7ddrphy_bitslip12[5]), - .D7(k7ddrphy_bitslip12[6]), - .D8(k7ddrphy_bitslip12[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay1), - .TQ(k7ddrphy_dq_t1) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip12[0]), + .D2 (main_k7ddrphy_bitslip12[1]), + .D3 (main_k7ddrphy_bitslip12[2]), + .D4 (main_k7ddrphy_bitslip12[3]), + .D5 (main_k7ddrphy_bitslip12[4]), + .D6 (main_k7ddrphy_bitslip12[5]), + .D7 (main_k7ddrphy_bitslip12[6]), + .D8 (main_k7ddrphy_bitslip12[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay1), + .TQ (main_k7ddrphy_dq_t1) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_1 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_1 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip13[7]), - .Q2(k7ddrphy_bitslip13[6]), - .Q3(k7ddrphy_bitslip13[5]), - .Q4(k7ddrphy_bitslip13[4]), - .Q5(k7ddrphy_bitslip13[3]), - .Q6(k7ddrphy_bitslip13[2]), - .Q7(k7ddrphy_bitslip13[1]), - .Q8(k7ddrphy_bitslip13[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip13[7]), + .Q2 (main_k7ddrphy_bitslip13[6]), + .Q3 (main_k7ddrphy_bitslip13[5]), + .Q4 (main_k7ddrphy_bitslip13[4]), + .Q5 (main_k7ddrphy_bitslip13[3]), + .Q6 (main_k7ddrphy_bitslip13[2]), + .Q7 (main_k7ddrphy_bitslip13[1]), + .Q8 (main_k7ddrphy_bitslip13[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_35 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_35 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed1), - .ODATAIN(k7ddrphy_dq_o_nodelay1) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed1), + .ODATAIN (main_k7ddrphy_dq_o_nodelay1) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_1 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_1 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay1), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed1) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay1), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed1) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_1 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_1( - .I(k7ddrphy_dq_o_delayed1), - .T(k7ddrphy_dq_t1), - .IO(ddram_dq[1]), - .O(k7ddrphy_dq_i_nodelay1) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed1), + .T (main_k7ddrphy_dq_t1), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay1), + + // InOuts. + .IO (ddram_dq[1]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_36 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_36 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip22[0]), - .D2(k7ddrphy_bitslip22[1]), - .D3(k7ddrphy_bitslip22[2]), - .D4(k7ddrphy_bitslip22[3]), - .D5(k7ddrphy_bitslip22[4]), - .D6(k7ddrphy_bitslip22[5]), - .D7(k7ddrphy_bitslip22[6]), - .D8(k7ddrphy_bitslip22[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay2), - .TQ(k7ddrphy_dq_t2) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip22[0]), + .D2 (main_k7ddrphy_bitslip22[1]), + .D3 (main_k7ddrphy_bitslip22[2]), + .D4 (main_k7ddrphy_bitslip22[3]), + .D5 (main_k7ddrphy_bitslip22[4]), + .D6 (main_k7ddrphy_bitslip22[5]), + .D7 (main_k7ddrphy_bitslip22[6]), + .D8 (main_k7ddrphy_bitslip22[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay2), + .TQ (main_k7ddrphy_dq_t2) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_2 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_2 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed2), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip23[7]), - .Q2(k7ddrphy_bitslip23[6]), - .Q3(k7ddrphy_bitslip23[5]), - .Q4(k7ddrphy_bitslip23[4]), - .Q5(k7ddrphy_bitslip23[3]), - .Q6(k7ddrphy_bitslip23[2]), - .Q7(k7ddrphy_bitslip23[1]), - .Q8(k7ddrphy_bitslip23[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed2), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip23[7]), + .Q2 (main_k7ddrphy_bitslip23[6]), + .Q3 (main_k7ddrphy_bitslip23[5]), + .Q4 (main_k7ddrphy_bitslip23[4]), + .Q5 (main_k7ddrphy_bitslip23[3]), + .Q6 (main_k7ddrphy_bitslip23[2]), + .Q7 (main_k7ddrphy_bitslip23[1]), + .Q8 (main_k7ddrphy_bitslip23[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_36 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_36 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed2), - .ODATAIN(k7ddrphy_dq_o_nodelay2) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed2), + .ODATAIN (main_k7ddrphy_dq_o_nodelay2) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_2 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_2 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay2), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed2) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay2), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed2) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_2 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_2( - .I(k7ddrphy_dq_o_delayed2), - .T(k7ddrphy_dq_t2), - .IO(ddram_dq[2]), - .O(k7ddrphy_dq_i_nodelay2) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed2), + .T (main_k7ddrphy_dq_t2), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay2), + + // InOuts. + .IO (ddram_dq[2]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_37 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_37 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip32[0]), - .D2(k7ddrphy_bitslip32[1]), - .D3(k7ddrphy_bitslip32[2]), - .D4(k7ddrphy_bitslip32[3]), - .D5(k7ddrphy_bitslip32[4]), - .D6(k7ddrphy_bitslip32[5]), - .D7(k7ddrphy_bitslip32[6]), - .D8(k7ddrphy_bitslip32[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay3), - .TQ(k7ddrphy_dq_t3) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip32[0]), + .D2 (main_k7ddrphy_bitslip32[1]), + .D3 (main_k7ddrphy_bitslip32[2]), + .D4 (main_k7ddrphy_bitslip32[3]), + .D5 (main_k7ddrphy_bitslip32[4]), + .D6 (main_k7ddrphy_bitslip32[5]), + .D7 (main_k7ddrphy_bitslip32[6]), + .D8 (main_k7ddrphy_bitslip32[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay3), + .TQ (main_k7ddrphy_dq_t3) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_3 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_3 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed3), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip33[7]), - .Q2(k7ddrphy_bitslip33[6]), - .Q3(k7ddrphy_bitslip33[5]), - .Q4(k7ddrphy_bitslip33[4]), - .Q5(k7ddrphy_bitslip33[3]), - .Q6(k7ddrphy_bitslip33[2]), - .Q7(k7ddrphy_bitslip33[1]), - .Q8(k7ddrphy_bitslip33[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed3), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip33[7]), + .Q2 (main_k7ddrphy_bitslip33[6]), + .Q3 (main_k7ddrphy_bitslip33[5]), + .Q4 (main_k7ddrphy_bitslip33[4]), + .Q5 (main_k7ddrphy_bitslip33[3]), + .Q6 (main_k7ddrphy_bitslip33[2]), + .Q7 (main_k7ddrphy_bitslip33[1]), + .Q8 (main_k7ddrphy_bitslip33[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_37 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_37 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed3), - .ODATAIN(k7ddrphy_dq_o_nodelay3) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed3), + .ODATAIN (main_k7ddrphy_dq_o_nodelay3) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_3 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_3 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay3), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed3) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay3), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed3) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_3 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_3( - .I(k7ddrphy_dq_o_delayed3), - .T(k7ddrphy_dq_t3), - .IO(ddram_dq[3]), - .O(k7ddrphy_dq_i_nodelay3) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed3), + .T (main_k7ddrphy_dq_t3), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay3), + + // InOuts. + .IO (ddram_dq[3]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_38 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_38 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip40[0]), - .D2(k7ddrphy_bitslip40[1]), - .D3(k7ddrphy_bitslip40[2]), - .D4(k7ddrphy_bitslip40[3]), - .D5(k7ddrphy_bitslip40[4]), - .D6(k7ddrphy_bitslip40[5]), - .D7(k7ddrphy_bitslip40[6]), - .D8(k7ddrphy_bitslip40[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay4), - .TQ(k7ddrphy_dq_t4) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip40[0]), + .D2 (main_k7ddrphy_bitslip40[1]), + .D3 (main_k7ddrphy_bitslip40[2]), + .D4 (main_k7ddrphy_bitslip40[3]), + .D5 (main_k7ddrphy_bitslip40[4]), + .D6 (main_k7ddrphy_bitslip40[5]), + .D7 (main_k7ddrphy_bitslip40[6]), + .D8 (main_k7ddrphy_bitslip40[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay4), + .TQ (main_k7ddrphy_dq_t4) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_4 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_4 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed4), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip41[7]), - .Q2(k7ddrphy_bitslip41[6]), - .Q3(k7ddrphy_bitslip41[5]), - .Q4(k7ddrphy_bitslip41[4]), - .Q5(k7ddrphy_bitslip41[3]), - .Q6(k7ddrphy_bitslip41[2]), - .Q7(k7ddrphy_bitslip41[1]), - .Q8(k7ddrphy_bitslip41[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed4), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip41[7]), + .Q2 (main_k7ddrphy_bitslip41[6]), + .Q3 (main_k7ddrphy_bitslip41[5]), + .Q4 (main_k7ddrphy_bitslip41[4]), + .Q5 (main_k7ddrphy_bitslip41[3]), + .Q6 (main_k7ddrphy_bitslip41[2]), + .Q7 (main_k7ddrphy_bitslip41[1]), + .Q8 (main_k7ddrphy_bitslip41[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_38 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_38 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed4), - .ODATAIN(k7ddrphy_dq_o_nodelay4) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed4), + .ODATAIN (main_k7ddrphy_dq_o_nodelay4) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_4 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_4 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay4), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed4) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay4), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed4) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_4 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_4( - .I(k7ddrphy_dq_o_delayed4), - .T(k7ddrphy_dq_t4), - .IO(ddram_dq[4]), - .O(k7ddrphy_dq_i_nodelay4) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed4), + .T (main_k7ddrphy_dq_t4), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay4), + + // InOuts. + .IO (ddram_dq[4]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_39 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_39 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip50[0]), - .D2(k7ddrphy_bitslip50[1]), - .D3(k7ddrphy_bitslip50[2]), - .D4(k7ddrphy_bitslip50[3]), - .D5(k7ddrphy_bitslip50[4]), - .D6(k7ddrphy_bitslip50[5]), - .D7(k7ddrphy_bitslip50[6]), - .D8(k7ddrphy_bitslip50[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay5), - .TQ(k7ddrphy_dq_t5) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip50[0]), + .D2 (main_k7ddrphy_bitslip50[1]), + .D3 (main_k7ddrphy_bitslip50[2]), + .D4 (main_k7ddrphy_bitslip50[3]), + .D5 (main_k7ddrphy_bitslip50[4]), + .D6 (main_k7ddrphy_bitslip50[5]), + .D7 (main_k7ddrphy_bitslip50[6]), + .D8 (main_k7ddrphy_bitslip50[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay5), + .TQ (main_k7ddrphy_dq_t5) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_5 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_5 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed5), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip51[7]), - .Q2(k7ddrphy_bitslip51[6]), - .Q3(k7ddrphy_bitslip51[5]), - .Q4(k7ddrphy_bitslip51[4]), - .Q5(k7ddrphy_bitslip51[3]), - .Q6(k7ddrphy_bitslip51[2]), - .Q7(k7ddrphy_bitslip51[1]), - .Q8(k7ddrphy_bitslip51[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed5), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip51[7]), + .Q2 (main_k7ddrphy_bitslip51[6]), + .Q3 (main_k7ddrphy_bitslip51[5]), + .Q4 (main_k7ddrphy_bitslip51[4]), + .Q5 (main_k7ddrphy_bitslip51[3]), + .Q6 (main_k7ddrphy_bitslip51[2]), + .Q7 (main_k7ddrphy_bitslip51[1]), + .Q8 (main_k7ddrphy_bitslip51[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_39 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_39 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed5), - .ODATAIN(k7ddrphy_dq_o_nodelay5) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed5), + .ODATAIN (main_k7ddrphy_dq_o_nodelay5) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_5 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_5 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay5), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed5) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay5), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed5) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_5 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_5( - .I(k7ddrphy_dq_o_delayed5), - .T(k7ddrphy_dq_t5), - .IO(ddram_dq[5]), - .O(k7ddrphy_dq_i_nodelay5) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed5), + .T (main_k7ddrphy_dq_t5), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay5), + + // InOuts. + .IO (ddram_dq[5]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_40 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_40 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip60[0]), - .D2(k7ddrphy_bitslip60[1]), - .D3(k7ddrphy_bitslip60[2]), - .D4(k7ddrphy_bitslip60[3]), - .D5(k7ddrphy_bitslip60[4]), - .D6(k7ddrphy_bitslip60[5]), - .D7(k7ddrphy_bitslip60[6]), - .D8(k7ddrphy_bitslip60[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay6), - .TQ(k7ddrphy_dq_t6) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip60[0]), + .D2 (main_k7ddrphy_bitslip60[1]), + .D3 (main_k7ddrphy_bitslip60[2]), + .D4 (main_k7ddrphy_bitslip60[3]), + .D5 (main_k7ddrphy_bitslip60[4]), + .D6 (main_k7ddrphy_bitslip60[5]), + .D7 (main_k7ddrphy_bitslip60[6]), + .D8 (main_k7ddrphy_bitslip60[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay6), + .TQ (main_k7ddrphy_dq_t6) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_6 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_6 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed6), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip61[7]), - .Q2(k7ddrphy_bitslip61[6]), - .Q3(k7ddrphy_bitslip61[5]), - .Q4(k7ddrphy_bitslip61[4]), - .Q5(k7ddrphy_bitslip61[3]), - .Q6(k7ddrphy_bitslip61[2]), - .Q7(k7ddrphy_bitslip61[1]), - .Q8(k7ddrphy_bitslip61[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed6), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip61[7]), + .Q2 (main_k7ddrphy_bitslip61[6]), + .Q3 (main_k7ddrphy_bitslip61[5]), + .Q4 (main_k7ddrphy_bitslip61[4]), + .Q5 (main_k7ddrphy_bitslip61[3]), + .Q6 (main_k7ddrphy_bitslip61[2]), + .Q7 (main_k7ddrphy_bitslip61[1]), + .Q8 (main_k7ddrphy_bitslip61[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_40 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_40 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed6), - .ODATAIN(k7ddrphy_dq_o_nodelay6) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed6), + .ODATAIN (main_k7ddrphy_dq_o_nodelay6) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_6 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_6 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay6), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed6) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay6), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed6) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_6 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_6( - .I(k7ddrphy_dq_o_delayed6), - .T(k7ddrphy_dq_t6), - .IO(ddram_dq[6]), - .O(k7ddrphy_dq_i_nodelay6) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed6), + .T (main_k7ddrphy_dq_t6), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay6), + + // InOuts. + .IO (ddram_dq[6]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_41 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_41 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip70[0]), - .D2(k7ddrphy_bitslip70[1]), - .D3(k7ddrphy_bitslip70[2]), - .D4(k7ddrphy_bitslip70[3]), - .D5(k7ddrphy_bitslip70[4]), - .D6(k7ddrphy_bitslip70[5]), - .D7(k7ddrphy_bitslip70[6]), - .D8(k7ddrphy_bitslip70[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay7), - .TQ(k7ddrphy_dq_t7) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip70[0]), + .D2 (main_k7ddrphy_bitslip70[1]), + .D3 (main_k7ddrphy_bitslip70[2]), + .D4 (main_k7ddrphy_bitslip70[3]), + .D5 (main_k7ddrphy_bitslip70[4]), + .D6 (main_k7ddrphy_bitslip70[5]), + .D7 (main_k7ddrphy_bitslip70[6]), + .D8 (main_k7ddrphy_bitslip70[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay7), + .TQ (main_k7ddrphy_dq_t7) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_7 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_7 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed7), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip71[7]), - .Q2(k7ddrphy_bitslip71[6]), - .Q3(k7ddrphy_bitslip71[5]), - .Q4(k7ddrphy_bitslip71[4]), - .Q5(k7ddrphy_bitslip71[3]), - .Q6(k7ddrphy_bitslip71[2]), - .Q7(k7ddrphy_bitslip71[1]), - .Q8(k7ddrphy_bitslip71[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed7), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip71[7]), + .Q2 (main_k7ddrphy_bitslip71[6]), + .Q3 (main_k7ddrphy_bitslip71[5]), + .Q4 (main_k7ddrphy_bitslip71[4]), + .Q5 (main_k7ddrphy_bitslip71[3]), + .Q6 (main_k7ddrphy_bitslip71[2]), + .Q7 (main_k7ddrphy_bitslip71[1]), + .Q8 (main_k7ddrphy_bitslip71[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_41 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_41 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed7), - .ODATAIN(k7ddrphy_dq_o_nodelay7) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed7), + .ODATAIN (main_k7ddrphy_dq_o_nodelay7) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_7 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_7 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay7), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed7) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay7), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[0] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed7) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_7 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_7( - .I(k7ddrphy_dq_o_delayed7), - .T(k7ddrphy_dq_t7), - .IO(ddram_dq[7]), - .O(k7ddrphy_dq_i_nodelay7) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed7), + .T (main_k7ddrphy_dq_t7), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay7), + + // InOuts. + .IO (ddram_dq[7]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_42 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_42 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip80[0]), - .D2(k7ddrphy_bitslip80[1]), - .D3(k7ddrphy_bitslip80[2]), - .D4(k7ddrphy_bitslip80[3]), - .D5(k7ddrphy_bitslip80[4]), - .D6(k7ddrphy_bitslip80[5]), - .D7(k7ddrphy_bitslip80[6]), - .D8(k7ddrphy_bitslip80[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay8), - .TQ(k7ddrphy_dq_t8) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip80[0]), + .D2 (main_k7ddrphy_bitslip80[1]), + .D3 (main_k7ddrphy_bitslip80[2]), + .D4 (main_k7ddrphy_bitslip80[3]), + .D5 (main_k7ddrphy_bitslip80[4]), + .D6 (main_k7ddrphy_bitslip80[5]), + .D7 (main_k7ddrphy_bitslip80[6]), + .D8 (main_k7ddrphy_bitslip80[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay8), + .TQ (main_k7ddrphy_dq_t8) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_8 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_8 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed8), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip81[7]), - .Q2(k7ddrphy_bitslip81[6]), - .Q3(k7ddrphy_bitslip81[5]), - .Q4(k7ddrphy_bitslip81[4]), - .Q5(k7ddrphy_bitslip81[3]), - .Q6(k7ddrphy_bitslip81[2]), - .Q7(k7ddrphy_bitslip81[1]), - .Q8(k7ddrphy_bitslip81[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed8), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip81[7]), + .Q2 (main_k7ddrphy_bitslip81[6]), + .Q3 (main_k7ddrphy_bitslip81[5]), + .Q4 (main_k7ddrphy_bitslip81[4]), + .Q5 (main_k7ddrphy_bitslip81[3]), + .Q6 (main_k7ddrphy_bitslip81[2]), + .Q7 (main_k7ddrphy_bitslip81[1]), + .Q8 (main_k7ddrphy_bitslip81[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_42 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_42 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed8), - .ODATAIN(k7ddrphy_dq_o_nodelay8) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed8), + .ODATAIN (main_k7ddrphy_dq_o_nodelay8) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_8 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_8 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay8), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed8) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay8), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed8) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_8 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_8( - .I(k7ddrphy_dq_o_delayed8), - .T(k7ddrphy_dq_t8), - .IO(ddram_dq[8]), - .O(k7ddrphy_dq_i_nodelay8) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed8), + .T (main_k7ddrphy_dq_t8), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay8), + + // InOuts. + .IO (ddram_dq[8]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_43 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_43 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip90[0]), - .D2(k7ddrphy_bitslip90[1]), - .D3(k7ddrphy_bitslip90[2]), - .D4(k7ddrphy_bitslip90[3]), - .D5(k7ddrphy_bitslip90[4]), - .D6(k7ddrphy_bitslip90[5]), - .D7(k7ddrphy_bitslip90[6]), - .D8(k7ddrphy_bitslip90[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay9), - .TQ(k7ddrphy_dq_t9) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip90[0]), + .D2 (main_k7ddrphy_bitslip90[1]), + .D3 (main_k7ddrphy_bitslip90[2]), + .D4 (main_k7ddrphy_bitslip90[3]), + .D5 (main_k7ddrphy_bitslip90[4]), + .D6 (main_k7ddrphy_bitslip90[5]), + .D7 (main_k7ddrphy_bitslip90[6]), + .D8 (main_k7ddrphy_bitslip90[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay9), + .TQ (main_k7ddrphy_dq_t9) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_9 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_9 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed9), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip91[7]), - .Q2(k7ddrphy_bitslip91[6]), - .Q3(k7ddrphy_bitslip91[5]), - .Q4(k7ddrphy_bitslip91[4]), - .Q5(k7ddrphy_bitslip91[3]), - .Q6(k7ddrphy_bitslip91[2]), - .Q7(k7ddrphy_bitslip91[1]), - .Q8(k7ddrphy_bitslip91[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed9), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip91[7]), + .Q2 (main_k7ddrphy_bitslip91[6]), + .Q3 (main_k7ddrphy_bitslip91[5]), + .Q4 (main_k7ddrphy_bitslip91[4]), + .Q5 (main_k7ddrphy_bitslip91[3]), + .Q6 (main_k7ddrphy_bitslip91[2]), + .Q7 (main_k7ddrphy_bitslip91[1]), + .Q8 (main_k7ddrphy_bitslip91[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_43 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_43 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed9), - .ODATAIN(k7ddrphy_dq_o_nodelay9) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed9), + .ODATAIN (main_k7ddrphy_dq_o_nodelay9) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_9 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_9 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay9), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed9) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay9), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed9) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_9 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_9( - .I(k7ddrphy_dq_o_delayed9), - .T(k7ddrphy_dq_t9), - .IO(ddram_dq[9]), - .O(k7ddrphy_dq_i_nodelay9) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed9), + .T (main_k7ddrphy_dq_t9), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay9), + + // InOuts. + .IO (ddram_dq[9]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_44 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_44 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip100[0]), - .D2(k7ddrphy_bitslip100[1]), - .D3(k7ddrphy_bitslip100[2]), - .D4(k7ddrphy_bitslip100[3]), - .D5(k7ddrphy_bitslip100[4]), - .D6(k7ddrphy_bitslip100[5]), - .D7(k7ddrphy_bitslip100[6]), - .D8(k7ddrphy_bitslip100[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay10), - .TQ(k7ddrphy_dq_t10) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip100[0]), + .D2 (main_k7ddrphy_bitslip100[1]), + .D3 (main_k7ddrphy_bitslip100[2]), + .D4 (main_k7ddrphy_bitslip100[3]), + .D5 (main_k7ddrphy_bitslip100[4]), + .D6 (main_k7ddrphy_bitslip100[5]), + .D7 (main_k7ddrphy_bitslip100[6]), + .D8 (main_k7ddrphy_bitslip100[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay10), + .TQ (main_k7ddrphy_dq_t10) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_10 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_10 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed10), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip101[7]), - .Q2(k7ddrphy_bitslip101[6]), - .Q3(k7ddrphy_bitslip101[5]), - .Q4(k7ddrphy_bitslip101[4]), - .Q5(k7ddrphy_bitslip101[3]), - .Q6(k7ddrphy_bitslip101[2]), - .Q7(k7ddrphy_bitslip101[1]), - .Q8(k7ddrphy_bitslip101[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed10), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip101[7]), + .Q2 (main_k7ddrphy_bitslip101[6]), + .Q3 (main_k7ddrphy_bitslip101[5]), + .Q4 (main_k7ddrphy_bitslip101[4]), + .Q5 (main_k7ddrphy_bitslip101[3]), + .Q6 (main_k7ddrphy_bitslip101[2]), + .Q7 (main_k7ddrphy_bitslip101[1]), + .Q8 (main_k7ddrphy_bitslip101[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_44 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_44 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed10), - .ODATAIN(k7ddrphy_dq_o_nodelay10) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed10), + .ODATAIN (main_k7ddrphy_dq_o_nodelay10) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_10 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_10 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay10), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed10) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay10), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed10) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_10 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_10( - .I(k7ddrphy_dq_o_delayed10), - .T(k7ddrphy_dq_t10), - .IO(ddram_dq[10]), - .O(k7ddrphy_dq_i_nodelay10) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed10), + .T (main_k7ddrphy_dq_t10), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay10), + + // InOuts. + .IO (ddram_dq[10]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_45 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_45 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip110[0]), - .D2(k7ddrphy_bitslip110[1]), - .D3(k7ddrphy_bitslip110[2]), - .D4(k7ddrphy_bitslip110[3]), - .D5(k7ddrphy_bitslip110[4]), - .D6(k7ddrphy_bitslip110[5]), - .D7(k7ddrphy_bitslip110[6]), - .D8(k7ddrphy_bitslip110[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay11), - .TQ(k7ddrphy_dq_t11) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip110[0]), + .D2 (main_k7ddrphy_bitslip110[1]), + .D3 (main_k7ddrphy_bitslip110[2]), + .D4 (main_k7ddrphy_bitslip110[3]), + .D5 (main_k7ddrphy_bitslip110[4]), + .D6 (main_k7ddrphy_bitslip110[5]), + .D7 (main_k7ddrphy_bitslip110[6]), + .D8 (main_k7ddrphy_bitslip110[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay11), + .TQ (main_k7ddrphy_dq_t11) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_11 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_11 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed11), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip111[7]), - .Q2(k7ddrphy_bitslip111[6]), - .Q3(k7ddrphy_bitslip111[5]), - .Q4(k7ddrphy_bitslip111[4]), - .Q5(k7ddrphy_bitslip111[3]), - .Q6(k7ddrphy_bitslip111[2]), - .Q7(k7ddrphy_bitslip111[1]), - .Q8(k7ddrphy_bitslip111[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed11), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip111[7]), + .Q2 (main_k7ddrphy_bitslip111[6]), + .Q3 (main_k7ddrphy_bitslip111[5]), + .Q4 (main_k7ddrphy_bitslip111[4]), + .Q5 (main_k7ddrphy_bitslip111[3]), + .Q6 (main_k7ddrphy_bitslip111[2]), + .Q7 (main_k7ddrphy_bitslip111[1]), + .Q8 (main_k7ddrphy_bitslip111[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_45 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_45 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed11), - .ODATAIN(k7ddrphy_dq_o_nodelay11) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed11), + .ODATAIN (main_k7ddrphy_dq_o_nodelay11) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_11 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_11 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay11), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed11) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay11), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed11) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_11 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_11( - .I(k7ddrphy_dq_o_delayed11), - .T(k7ddrphy_dq_t11), - .IO(ddram_dq[11]), - .O(k7ddrphy_dq_i_nodelay11) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed11), + .T (main_k7ddrphy_dq_t11), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay11), + + // InOuts. + .IO (ddram_dq[11]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_46 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_46 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip120[0]), - .D2(k7ddrphy_bitslip120[1]), - .D3(k7ddrphy_bitslip120[2]), - .D4(k7ddrphy_bitslip120[3]), - .D5(k7ddrphy_bitslip120[4]), - .D6(k7ddrphy_bitslip120[5]), - .D7(k7ddrphy_bitslip120[6]), - .D8(k7ddrphy_bitslip120[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay12), - .TQ(k7ddrphy_dq_t12) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip120[0]), + .D2 (main_k7ddrphy_bitslip120[1]), + .D3 (main_k7ddrphy_bitslip120[2]), + .D4 (main_k7ddrphy_bitslip120[3]), + .D5 (main_k7ddrphy_bitslip120[4]), + .D6 (main_k7ddrphy_bitslip120[5]), + .D7 (main_k7ddrphy_bitslip120[6]), + .D8 (main_k7ddrphy_bitslip120[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay12), + .TQ (main_k7ddrphy_dq_t12) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_12 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_12 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed12), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip121[7]), - .Q2(k7ddrphy_bitslip121[6]), - .Q3(k7ddrphy_bitslip121[5]), - .Q4(k7ddrphy_bitslip121[4]), - .Q5(k7ddrphy_bitslip121[3]), - .Q6(k7ddrphy_bitslip121[2]), - .Q7(k7ddrphy_bitslip121[1]), - .Q8(k7ddrphy_bitslip121[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed12), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip121[7]), + .Q2 (main_k7ddrphy_bitslip121[6]), + .Q3 (main_k7ddrphy_bitslip121[5]), + .Q4 (main_k7ddrphy_bitslip121[4]), + .Q5 (main_k7ddrphy_bitslip121[3]), + .Q6 (main_k7ddrphy_bitslip121[2]), + .Q7 (main_k7ddrphy_bitslip121[1]), + .Q8 (main_k7ddrphy_bitslip121[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_46 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_46 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed12), - .ODATAIN(k7ddrphy_dq_o_nodelay12) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed12), + .ODATAIN (main_k7ddrphy_dq_o_nodelay12) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_12 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_12 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay12), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed12) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay12), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed12) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_12 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_12( - .I(k7ddrphy_dq_o_delayed12), - .T(k7ddrphy_dq_t12), - .IO(ddram_dq[12]), - .O(k7ddrphy_dq_i_nodelay12) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed12), + .T (main_k7ddrphy_dq_t12), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay12), + + // InOuts. + .IO (ddram_dq[12]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_47 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_47 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip130[0]), - .D2(k7ddrphy_bitslip130[1]), - .D3(k7ddrphy_bitslip130[2]), - .D4(k7ddrphy_bitslip130[3]), - .D5(k7ddrphy_bitslip130[4]), - .D6(k7ddrphy_bitslip130[5]), - .D7(k7ddrphy_bitslip130[6]), - .D8(k7ddrphy_bitslip130[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay13), - .TQ(k7ddrphy_dq_t13) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip130[0]), + .D2 (main_k7ddrphy_bitslip130[1]), + .D3 (main_k7ddrphy_bitslip130[2]), + .D4 (main_k7ddrphy_bitslip130[3]), + .D5 (main_k7ddrphy_bitslip130[4]), + .D6 (main_k7ddrphy_bitslip130[5]), + .D7 (main_k7ddrphy_bitslip130[6]), + .D8 (main_k7ddrphy_bitslip130[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay13), + .TQ (main_k7ddrphy_dq_t13) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_13 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_13 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed13), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip131[7]), - .Q2(k7ddrphy_bitslip131[6]), - .Q3(k7ddrphy_bitslip131[5]), - .Q4(k7ddrphy_bitslip131[4]), - .Q5(k7ddrphy_bitslip131[3]), - .Q6(k7ddrphy_bitslip131[2]), - .Q7(k7ddrphy_bitslip131[1]), - .Q8(k7ddrphy_bitslip131[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed13), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip131[7]), + .Q2 (main_k7ddrphy_bitslip131[6]), + .Q3 (main_k7ddrphy_bitslip131[5]), + .Q4 (main_k7ddrphy_bitslip131[4]), + .Q5 (main_k7ddrphy_bitslip131[3]), + .Q6 (main_k7ddrphy_bitslip131[2]), + .Q7 (main_k7ddrphy_bitslip131[1]), + .Q8 (main_k7ddrphy_bitslip131[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_47 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_47 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed13), - .ODATAIN(k7ddrphy_dq_o_nodelay13) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed13), + .ODATAIN (main_k7ddrphy_dq_o_nodelay13) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_13 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_13 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay13), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed13) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay13), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed13) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_13 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_13( - .I(k7ddrphy_dq_o_delayed13), - .T(k7ddrphy_dq_t13), - .IO(ddram_dq[13]), - .O(k7ddrphy_dq_i_nodelay13) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed13), + .T (main_k7ddrphy_dq_t13), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay13), + + // InOuts. + .IO (ddram_dq[13]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_48 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_48 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip140[0]), - .D2(k7ddrphy_bitslip140[1]), - .D3(k7ddrphy_bitslip140[2]), - .D4(k7ddrphy_bitslip140[3]), - .D5(k7ddrphy_bitslip140[4]), - .D6(k7ddrphy_bitslip140[5]), - .D7(k7ddrphy_bitslip140[6]), - .D8(k7ddrphy_bitslip140[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay14), - .TQ(k7ddrphy_dq_t14) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip140[0]), + .D2 (main_k7ddrphy_bitslip140[1]), + .D3 (main_k7ddrphy_bitslip140[2]), + .D4 (main_k7ddrphy_bitslip140[3]), + .D5 (main_k7ddrphy_bitslip140[4]), + .D6 (main_k7ddrphy_bitslip140[5]), + .D7 (main_k7ddrphy_bitslip140[6]), + .D8 (main_k7ddrphy_bitslip140[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay14), + .TQ (main_k7ddrphy_dq_t14) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_14 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_14 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed14), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip141[7]), - .Q2(k7ddrphy_bitslip141[6]), - .Q3(k7ddrphy_bitslip141[5]), - .Q4(k7ddrphy_bitslip141[4]), - .Q5(k7ddrphy_bitslip141[3]), - .Q6(k7ddrphy_bitslip141[2]), - .Q7(k7ddrphy_bitslip141[1]), - .Q8(k7ddrphy_bitslip141[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed14), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip141[7]), + .Q2 (main_k7ddrphy_bitslip141[6]), + .Q3 (main_k7ddrphy_bitslip141[5]), + .Q4 (main_k7ddrphy_bitslip141[4]), + .Q5 (main_k7ddrphy_bitslip141[3]), + .Q6 (main_k7ddrphy_bitslip141[2]), + .Q7 (main_k7ddrphy_bitslip141[1]), + .Q8 (main_k7ddrphy_bitslip141[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_48 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_48 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed14), - .ODATAIN(k7ddrphy_dq_o_nodelay14) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed14), + .ODATAIN (main_k7ddrphy_dq_o_nodelay14) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_14 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_14 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay14), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed14) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay14), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed14) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_14 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_14( - .I(k7ddrphy_dq_o_delayed14), - .T(k7ddrphy_dq_t14), - .IO(ddram_dq[14]), - .O(k7ddrphy_dq_i_nodelay14) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed14), + .T (main_k7ddrphy_dq_t14), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay14), + + // InOuts. + .IO (ddram_dq[14]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_49 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_49 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip150[0]), - .D2(k7ddrphy_bitslip150[1]), - .D3(k7ddrphy_bitslip150[2]), - .D4(k7ddrphy_bitslip150[3]), - .D5(k7ddrphy_bitslip150[4]), - .D6(k7ddrphy_bitslip150[5]), - .D7(k7ddrphy_bitslip150[6]), - .D8(k7ddrphy_bitslip150[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay15), - .TQ(k7ddrphy_dq_t15) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip150[0]), + .D2 (main_k7ddrphy_bitslip150[1]), + .D3 (main_k7ddrphy_bitslip150[2]), + .D4 (main_k7ddrphy_bitslip150[3]), + .D5 (main_k7ddrphy_bitslip150[4]), + .D6 (main_k7ddrphy_bitslip150[5]), + .D7 (main_k7ddrphy_bitslip150[6]), + .D8 (main_k7ddrphy_bitslip150[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay15), + .TQ (main_k7ddrphy_dq_t15) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_15 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_15 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed15), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip151[7]), - .Q2(k7ddrphy_bitslip151[6]), - .Q3(k7ddrphy_bitslip151[5]), - .Q4(k7ddrphy_bitslip151[4]), - .Q5(k7ddrphy_bitslip151[3]), - .Q6(k7ddrphy_bitslip151[2]), - .Q7(k7ddrphy_bitslip151[1]), - .Q8(k7ddrphy_bitslip151[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed15), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip151[7]), + .Q2 (main_k7ddrphy_bitslip151[6]), + .Q3 (main_k7ddrphy_bitslip151[5]), + .Q4 (main_k7ddrphy_bitslip151[4]), + .Q5 (main_k7ddrphy_bitslip151[3]), + .Q6 (main_k7ddrphy_bitslip151[2]), + .Q7 (main_k7ddrphy_bitslip151[1]), + .Q8 (main_k7ddrphy_bitslip151[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_49 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_49 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed15), - .ODATAIN(k7ddrphy_dq_o_nodelay15) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed15), + .ODATAIN (main_k7ddrphy_dq_o_nodelay15) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_15 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_15 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay15), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed15) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay15), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[1] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed15) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_15 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_15( - .I(k7ddrphy_dq_o_delayed15), - .T(k7ddrphy_dq_t15), - .IO(ddram_dq[15]), - .O(k7ddrphy_dq_i_nodelay15) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed15), + .T (main_k7ddrphy_dq_t15), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay15), + + // InOuts. + .IO (ddram_dq[15]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_50 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_50 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip160[0]), - .D2(k7ddrphy_bitslip160[1]), - .D3(k7ddrphy_bitslip160[2]), - .D4(k7ddrphy_bitslip160[3]), - .D5(k7ddrphy_bitslip160[4]), - .D6(k7ddrphy_bitslip160[5]), - .D7(k7ddrphy_bitslip160[6]), - .D8(k7ddrphy_bitslip160[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay16), - .TQ(k7ddrphy_dq_t16) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip160[0]), + .D2 (main_k7ddrphy_bitslip160[1]), + .D3 (main_k7ddrphy_bitslip160[2]), + .D4 (main_k7ddrphy_bitslip160[3]), + .D5 (main_k7ddrphy_bitslip160[4]), + .D6 (main_k7ddrphy_bitslip160[5]), + .D7 (main_k7ddrphy_bitslip160[6]), + .D8 (main_k7ddrphy_bitslip160[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay16), + .TQ (main_k7ddrphy_dq_t16) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_16 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_16 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed16), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip161[7]), - .Q2(k7ddrphy_bitslip161[6]), - .Q3(k7ddrphy_bitslip161[5]), - .Q4(k7ddrphy_bitslip161[4]), - .Q5(k7ddrphy_bitslip161[3]), - .Q6(k7ddrphy_bitslip161[2]), - .Q7(k7ddrphy_bitslip161[1]), - .Q8(k7ddrphy_bitslip161[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed16), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip161[7]), + .Q2 (main_k7ddrphy_bitslip161[6]), + .Q3 (main_k7ddrphy_bitslip161[5]), + .Q4 (main_k7ddrphy_bitslip161[4]), + .Q5 (main_k7ddrphy_bitslip161[3]), + .Q6 (main_k7ddrphy_bitslip161[2]), + .Q7 (main_k7ddrphy_bitslip161[1]), + .Q8 (main_k7ddrphy_bitslip161[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_50 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_50 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed16), - .ODATAIN(k7ddrphy_dq_o_nodelay16) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed16), + .ODATAIN (main_k7ddrphy_dq_o_nodelay16) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_16 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_16 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay16), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed16) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay16), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed16) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_16 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_16( - .I(k7ddrphy_dq_o_delayed16), - .T(k7ddrphy_dq_t16), - .IO(ddram_dq[16]), - .O(k7ddrphy_dq_i_nodelay16) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed16), + .T (main_k7ddrphy_dq_t16), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay16), + + // InOuts. + .IO (ddram_dq[16]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_51 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_51 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip170[0]), - .D2(k7ddrphy_bitslip170[1]), - .D3(k7ddrphy_bitslip170[2]), - .D4(k7ddrphy_bitslip170[3]), - .D5(k7ddrphy_bitslip170[4]), - .D6(k7ddrphy_bitslip170[5]), - .D7(k7ddrphy_bitslip170[6]), - .D8(k7ddrphy_bitslip170[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay17), - .TQ(k7ddrphy_dq_t17) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip170[0]), + .D2 (main_k7ddrphy_bitslip170[1]), + .D3 (main_k7ddrphy_bitslip170[2]), + .D4 (main_k7ddrphy_bitslip170[3]), + .D5 (main_k7ddrphy_bitslip170[4]), + .D6 (main_k7ddrphy_bitslip170[5]), + .D7 (main_k7ddrphy_bitslip170[6]), + .D8 (main_k7ddrphy_bitslip170[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay17), + .TQ (main_k7ddrphy_dq_t17) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_17 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_17 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed17), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip171[7]), - .Q2(k7ddrphy_bitslip171[6]), - .Q3(k7ddrphy_bitslip171[5]), - .Q4(k7ddrphy_bitslip171[4]), - .Q5(k7ddrphy_bitslip171[3]), - .Q6(k7ddrphy_bitslip171[2]), - .Q7(k7ddrphy_bitslip171[1]), - .Q8(k7ddrphy_bitslip171[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed17), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip171[7]), + .Q2 (main_k7ddrphy_bitslip171[6]), + .Q3 (main_k7ddrphy_bitslip171[5]), + .Q4 (main_k7ddrphy_bitslip171[4]), + .Q5 (main_k7ddrphy_bitslip171[3]), + .Q6 (main_k7ddrphy_bitslip171[2]), + .Q7 (main_k7ddrphy_bitslip171[1]), + .Q8 (main_k7ddrphy_bitslip171[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_51 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_51 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed17), - .ODATAIN(k7ddrphy_dq_o_nodelay17) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed17), + .ODATAIN (main_k7ddrphy_dq_o_nodelay17) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_17 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_17 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay17), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed17) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay17), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed17) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_17 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_17( - .I(k7ddrphy_dq_o_delayed17), - .T(k7ddrphy_dq_t17), - .IO(ddram_dq[17]), - .O(k7ddrphy_dq_i_nodelay17) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed17), + .T (main_k7ddrphy_dq_t17), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay17), + + // InOuts. + .IO (ddram_dq[17]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_52 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_52 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip180[0]), - .D2(k7ddrphy_bitslip180[1]), - .D3(k7ddrphy_bitslip180[2]), - .D4(k7ddrphy_bitslip180[3]), - .D5(k7ddrphy_bitslip180[4]), - .D6(k7ddrphy_bitslip180[5]), - .D7(k7ddrphy_bitslip180[6]), - .D8(k7ddrphy_bitslip180[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay18), - .TQ(k7ddrphy_dq_t18) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip180[0]), + .D2 (main_k7ddrphy_bitslip180[1]), + .D3 (main_k7ddrphy_bitslip180[2]), + .D4 (main_k7ddrphy_bitslip180[3]), + .D5 (main_k7ddrphy_bitslip180[4]), + .D6 (main_k7ddrphy_bitslip180[5]), + .D7 (main_k7ddrphy_bitslip180[6]), + .D8 (main_k7ddrphy_bitslip180[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay18), + .TQ (main_k7ddrphy_dq_t18) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_18 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_18 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed18), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip181[7]), - .Q2(k7ddrphy_bitslip181[6]), - .Q3(k7ddrphy_bitslip181[5]), - .Q4(k7ddrphy_bitslip181[4]), - .Q5(k7ddrphy_bitslip181[3]), - .Q6(k7ddrphy_bitslip181[2]), - .Q7(k7ddrphy_bitslip181[1]), - .Q8(k7ddrphy_bitslip181[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed18), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip181[7]), + .Q2 (main_k7ddrphy_bitslip181[6]), + .Q3 (main_k7ddrphy_bitslip181[5]), + .Q4 (main_k7ddrphy_bitslip181[4]), + .Q5 (main_k7ddrphy_bitslip181[3]), + .Q6 (main_k7ddrphy_bitslip181[2]), + .Q7 (main_k7ddrphy_bitslip181[1]), + .Q8 (main_k7ddrphy_bitslip181[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_52 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_52 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed18), - .ODATAIN(k7ddrphy_dq_o_nodelay18) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed18), + .ODATAIN (main_k7ddrphy_dq_o_nodelay18) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_18 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_18 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay18), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed18) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay18), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed18) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_18 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_18( - .I(k7ddrphy_dq_o_delayed18), - .T(k7ddrphy_dq_t18), - .IO(ddram_dq[18]), - .O(k7ddrphy_dq_i_nodelay18) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed18), + .T (main_k7ddrphy_dq_t18), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay18), + + // InOuts. + .IO (ddram_dq[18]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_53 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_53 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip190[0]), - .D2(k7ddrphy_bitslip190[1]), - .D3(k7ddrphy_bitslip190[2]), - .D4(k7ddrphy_bitslip190[3]), - .D5(k7ddrphy_bitslip190[4]), - .D6(k7ddrphy_bitslip190[5]), - .D7(k7ddrphy_bitslip190[6]), - .D8(k7ddrphy_bitslip190[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay19), - .TQ(k7ddrphy_dq_t19) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip190[0]), + .D2 (main_k7ddrphy_bitslip190[1]), + .D3 (main_k7ddrphy_bitslip190[2]), + .D4 (main_k7ddrphy_bitslip190[3]), + .D5 (main_k7ddrphy_bitslip190[4]), + .D6 (main_k7ddrphy_bitslip190[5]), + .D7 (main_k7ddrphy_bitslip190[6]), + .D8 (main_k7ddrphy_bitslip190[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay19), + .TQ (main_k7ddrphy_dq_t19) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_19 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_19 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed19), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip191[7]), - .Q2(k7ddrphy_bitslip191[6]), - .Q3(k7ddrphy_bitslip191[5]), - .Q4(k7ddrphy_bitslip191[4]), - .Q5(k7ddrphy_bitslip191[3]), - .Q6(k7ddrphy_bitslip191[2]), - .Q7(k7ddrphy_bitslip191[1]), - .Q8(k7ddrphy_bitslip191[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed19), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip191[7]), + .Q2 (main_k7ddrphy_bitslip191[6]), + .Q3 (main_k7ddrphy_bitslip191[5]), + .Q4 (main_k7ddrphy_bitslip191[4]), + .Q5 (main_k7ddrphy_bitslip191[3]), + .Q6 (main_k7ddrphy_bitslip191[2]), + .Q7 (main_k7ddrphy_bitslip191[1]), + .Q8 (main_k7ddrphy_bitslip191[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_53 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_53 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed19), - .ODATAIN(k7ddrphy_dq_o_nodelay19) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed19), + .ODATAIN (main_k7ddrphy_dq_o_nodelay19) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_19 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_19 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay19), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed19) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay19), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed19) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_19 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_19( - .I(k7ddrphy_dq_o_delayed19), - .T(k7ddrphy_dq_t19), - .IO(ddram_dq[19]), - .O(k7ddrphy_dq_i_nodelay19) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed19), + .T (main_k7ddrphy_dq_t19), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay19), + + // InOuts. + .IO (ddram_dq[19]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_54 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_54 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip200[0]), - .D2(k7ddrphy_bitslip200[1]), - .D3(k7ddrphy_bitslip200[2]), - .D4(k7ddrphy_bitslip200[3]), - .D5(k7ddrphy_bitslip200[4]), - .D6(k7ddrphy_bitslip200[5]), - .D7(k7ddrphy_bitslip200[6]), - .D8(k7ddrphy_bitslip200[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay20), - .TQ(k7ddrphy_dq_t20) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip200[0]), + .D2 (main_k7ddrphy_bitslip200[1]), + .D3 (main_k7ddrphy_bitslip200[2]), + .D4 (main_k7ddrphy_bitslip200[3]), + .D5 (main_k7ddrphy_bitslip200[4]), + .D6 (main_k7ddrphy_bitslip200[5]), + .D7 (main_k7ddrphy_bitslip200[6]), + .D8 (main_k7ddrphy_bitslip200[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay20), + .TQ (main_k7ddrphy_dq_t20) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_20 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_20 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed20), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip201[7]), - .Q2(k7ddrphy_bitslip201[6]), - .Q3(k7ddrphy_bitslip201[5]), - .Q4(k7ddrphy_bitslip201[4]), - .Q5(k7ddrphy_bitslip201[3]), - .Q6(k7ddrphy_bitslip201[2]), - .Q7(k7ddrphy_bitslip201[1]), - .Q8(k7ddrphy_bitslip201[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed20), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip201[7]), + .Q2 (main_k7ddrphy_bitslip201[6]), + .Q3 (main_k7ddrphy_bitslip201[5]), + .Q4 (main_k7ddrphy_bitslip201[4]), + .Q5 (main_k7ddrphy_bitslip201[3]), + .Q6 (main_k7ddrphy_bitslip201[2]), + .Q7 (main_k7ddrphy_bitslip201[1]), + .Q8 (main_k7ddrphy_bitslip201[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_54 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_54 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed20), - .ODATAIN(k7ddrphy_dq_o_nodelay20) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed20), + .ODATAIN (main_k7ddrphy_dq_o_nodelay20) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_20 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_20 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay20), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed20) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay20), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed20) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_20 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_20( - .I(k7ddrphy_dq_o_delayed20), - .T(k7ddrphy_dq_t20), - .IO(ddram_dq[20]), - .O(k7ddrphy_dq_i_nodelay20) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed20), + .T (main_k7ddrphy_dq_t20), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay20), + + // InOuts. + .IO (ddram_dq[20]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_55 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_55 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip210[0]), - .D2(k7ddrphy_bitslip210[1]), - .D3(k7ddrphy_bitslip210[2]), - .D4(k7ddrphy_bitslip210[3]), - .D5(k7ddrphy_bitslip210[4]), - .D6(k7ddrphy_bitslip210[5]), - .D7(k7ddrphy_bitslip210[6]), - .D8(k7ddrphy_bitslip210[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay21), - .TQ(k7ddrphy_dq_t21) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip210[0]), + .D2 (main_k7ddrphy_bitslip210[1]), + .D3 (main_k7ddrphy_bitslip210[2]), + .D4 (main_k7ddrphy_bitslip210[3]), + .D5 (main_k7ddrphy_bitslip210[4]), + .D6 (main_k7ddrphy_bitslip210[5]), + .D7 (main_k7ddrphy_bitslip210[6]), + .D8 (main_k7ddrphy_bitslip210[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay21), + .TQ (main_k7ddrphy_dq_t21) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_21 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_21 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed21), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip211[7]), - .Q2(k7ddrphy_bitslip211[6]), - .Q3(k7ddrphy_bitslip211[5]), - .Q4(k7ddrphy_bitslip211[4]), - .Q5(k7ddrphy_bitslip211[3]), - .Q6(k7ddrphy_bitslip211[2]), - .Q7(k7ddrphy_bitslip211[1]), - .Q8(k7ddrphy_bitslip211[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed21), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip211[7]), + .Q2 (main_k7ddrphy_bitslip211[6]), + .Q3 (main_k7ddrphy_bitslip211[5]), + .Q4 (main_k7ddrphy_bitslip211[4]), + .Q5 (main_k7ddrphy_bitslip211[3]), + .Q6 (main_k7ddrphy_bitslip211[2]), + .Q7 (main_k7ddrphy_bitslip211[1]), + .Q8 (main_k7ddrphy_bitslip211[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_55 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_55 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed21), - .ODATAIN(k7ddrphy_dq_o_nodelay21) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed21), + .ODATAIN (main_k7ddrphy_dq_o_nodelay21) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_21 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_21 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay21), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed21) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay21), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed21) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_21 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_21( - .I(k7ddrphy_dq_o_delayed21), - .T(k7ddrphy_dq_t21), - .IO(ddram_dq[21]), - .O(k7ddrphy_dq_i_nodelay21) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed21), + .T (main_k7ddrphy_dq_t21), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay21), + + // InOuts. + .IO (ddram_dq[21]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_56 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_56 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip220[0]), - .D2(k7ddrphy_bitslip220[1]), - .D3(k7ddrphy_bitslip220[2]), - .D4(k7ddrphy_bitslip220[3]), - .D5(k7ddrphy_bitslip220[4]), - .D6(k7ddrphy_bitslip220[5]), - .D7(k7ddrphy_bitslip220[6]), - .D8(k7ddrphy_bitslip220[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay22), - .TQ(k7ddrphy_dq_t22) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip220[0]), + .D2 (main_k7ddrphy_bitslip220[1]), + .D3 (main_k7ddrphy_bitslip220[2]), + .D4 (main_k7ddrphy_bitslip220[3]), + .D5 (main_k7ddrphy_bitslip220[4]), + .D6 (main_k7ddrphy_bitslip220[5]), + .D7 (main_k7ddrphy_bitslip220[6]), + .D8 (main_k7ddrphy_bitslip220[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay22), + .TQ (main_k7ddrphy_dq_t22) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_22 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_22 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed22), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip221[7]), - .Q2(k7ddrphy_bitslip221[6]), - .Q3(k7ddrphy_bitslip221[5]), - .Q4(k7ddrphy_bitslip221[4]), - .Q5(k7ddrphy_bitslip221[3]), - .Q6(k7ddrphy_bitslip221[2]), - .Q7(k7ddrphy_bitslip221[1]), - .Q8(k7ddrphy_bitslip221[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed22), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip221[7]), + .Q2 (main_k7ddrphy_bitslip221[6]), + .Q3 (main_k7ddrphy_bitslip221[5]), + .Q4 (main_k7ddrphy_bitslip221[4]), + .Q5 (main_k7ddrphy_bitslip221[3]), + .Q6 (main_k7ddrphy_bitslip221[2]), + .Q7 (main_k7ddrphy_bitslip221[1]), + .Q8 (main_k7ddrphy_bitslip221[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_56 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_56 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed22), - .ODATAIN(k7ddrphy_dq_o_nodelay22) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed22), + .ODATAIN (main_k7ddrphy_dq_o_nodelay22) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_22 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_22 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay22), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed22) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay22), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed22) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_22 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_22( - .I(k7ddrphy_dq_o_delayed22), - .T(k7ddrphy_dq_t22), - .IO(ddram_dq[22]), - .O(k7ddrphy_dq_i_nodelay22) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed22), + .T (main_k7ddrphy_dq_t22), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay22), + + // InOuts. + .IO (ddram_dq[22]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_57 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_57 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip230[0]), - .D2(k7ddrphy_bitslip230[1]), - .D3(k7ddrphy_bitslip230[2]), - .D4(k7ddrphy_bitslip230[3]), - .D5(k7ddrphy_bitslip230[4]), - .D6(k7ddrphy_bitslip230[5]), - .D7(k7ddrphy_bitslip230[6]), - .D8(k7ddrphy_bitslip230[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay23), - .TQ(k7ddrphy_dq_t23) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip230[0]), + .D2 (main_k7ddrphy_bitslip230[1]), + .D3 (main_k7ddrphy_bitslip230[2]), + .D4 (main_k7ddrphy_bitslip230[3]), + .D5 (main_k7ddrphy_bitslip230[4]), + .D6 (main_k7ddrphy_bitslip230[5]), + .D7 (main_k7ddrphy_bitslip230[6]), + .D8 (main_k7ddrphy_bitslip230[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay23), + .TQ (main_k7ddrphy_dq_t23) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_23 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_23 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed23), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip231[7]), - .Q2(k7ddrphy_bitslip231[6]), - .Q3(k7ddrphy_bitslip231[5]), - .Q4(k7ddrphy_bitslip231[4]), - .Q5(k7ddrphy_bitslip231[3]), - .Q6(k7ddrphy_bitslip231[2]), - .Q7(k7ddrphy_bitslip231[1]), - .Q8(k7ddrphy_bitslip231[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed23), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip231[7]), + .Q2 (main_k7ddrphy_bitslip231[6]), + .Q3 (main_k7ddrphy_bitslip231[5]), + .Q4 (main_k7ddrphy_bitslip231[4]), + .Q5 (main_k7ddrphy_bitslip231[3]), + .Q6 (main_k7ddrphy_bitslip231[2]), + .Q7 (main_k7ddrphy_bitslip231[1]), + .Q8 (main_k7ddrphy_bitslip231[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_57 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_57 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed23), - .ODATAIN(k7ddrphy_dq_o_nodelay23) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed23), + .ODATAIN (main_k7ddrphy_dq_o_nodelay23) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_23 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_23 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay23), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed23) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay23), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[2] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed23) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_23 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_23( - .I(k7ddrphy_dq_o_delayed23), - .T(k7ddrphy_dq_t23), - .IO(ddram_dq[23]), - .O(k7ddrphy_dq_i_nodelay23) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed23), + .T (main_k7ddrphy_dq_t23), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay23), + + // InOuts. + .IO (ddram_dq[23]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_58 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_58 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip240[0]), - .D2(k7ddrphy_bitslip240[1]), - .D3(k7ddrphy_bitslip240[2]), - .D4(k7ddrphy_bitslip240[3]), - .D5(k7ddrphy_bitslip240[4]), - .D6(k7ddrphy_bitslip240[5]), - .D7(k7ddrphy_bitslip240[6]), - .D8(k7ddrphy_bitslip240[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay24), - .TQ(k7ddrphy_dq_t24) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip240[0]), + .D2 (main_k7ddrphy_bitslip240[1]), + .D3 (main_k7ddrphy_bitslip240[2]), + .D4 (main_k7ddrphy_bitslip240[3]), + .D5 (main_k7ddrphy_bitslip240[4]), + .D6 (main_k7ddrphy_bitslip240[5]), + .D7 (main_k7ddrphy_bitslip240[6]), + .D8 (main_k7ddrphy_bitslip240[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay24), + .TQ (main_k7ddrphy_dq_t24) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_24 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_24 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed24), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip241[7]), - .Q2(k7ddrphy_bitslip241[6]), - .Q3(k7ddrphy_bitslip241[5]), - .Q4(k7ddrphy_bitslip241[4]), - .Q5(k7ddrphy_bitslip241[3]), - .Q6(k7ddrphy_bitslip241[2]), - .Q7(k7ddrphy_bitslip241[1]), - .Q8(k7ddrphy_bitslip241[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed24), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip241[7]), + .Q2 (main_k7ddrphy_bitslip241[6]), + .Q3 (main_k7ddrphy_bitslip241[5]), + .Q4 (main_k7ddrphy_bitslip241[4]), + .Q5 (main_k7ddrphy_bitslip241[3]), + .Q6 (main_k7ddrphy_bitslip241[2]), + .Q7 (main_k7ddrphy_bitslip241[1]), + .Q8 (main_k7ddrphy_bitslip241[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_58 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_58 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed24), - .ODATAIN(k7ddrphy_dq_o_nodelay24) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed24), + .ODATAIN (main_k7ddrphy_dq_o_nodelay24) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_24 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_24 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay24), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed24) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay24), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed24) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_24 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_24( - .I(k7ddrphy_dq_o_delayed24), - .T(k7ddrphy_dq_t24), - .IO(ddram_dq[24]), - .O(k7ddrphy_dq_i_nodelay24) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed24), + .T (main_k7ddrphy_dq_t24), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay24), + + // InOuts. + .IO (ddram_dq[24]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_59 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_59 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip250[0]), - .D2(k7ddrphy_bitslip250[1]), - .D3(k7ddrphy_bitslip250[2]), - .D4(k7ddrphy_bitslip250[3]), - .D5(k7ddrphy_bitslip250[4]), - .D6(k7ddrphy_bitslip250[5]), - .D7(k7ddrphy_bitslip250[6]), - .D8(k7ddrphy_bitslip250[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay25), - .TQ(k7ddrphy_dq_t25) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip250[0]), + .D2 (main_k7ddrphy_bitslip250[1]), + .D3 (main_k7ddrphy_bitslip250[2]), + .D4 (main_k7ddrphy_bitslip250[3]), + .D5 (main_k7ddrphy_bitslip250[4]), + .D6 (main_k7ddrphy_bitslip250[5]), + .D7 (main_k7ddrphy_bitslip250[6]), + .D8 (main_k7ddrphy_bitslip250[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay25), + .TQ (main_k7ddrphy_dq_t25) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_25 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_25 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed25), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip251[7]), - .Q2(k7ddrphy_bitslip251[6]), - .Q3(k7ddrphy_bitslip251[5]), - .Q4(k7ddrphy_bitslip251[4]), - .Q5(k7ddrphy_bitslip251[3]), - .Q6(k7ddrphy_bitslip251[2]), - .Q7(k7ddrphy_bitslip251[1]), - .Q8(k7ddrphy_bitslip251[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed25), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip251[7]), + .Q2 (main_k7ddrphy_bitslip251[6]), + .Q3 (main_k7ddrphy_bitslip251[5]), + .Q4 (main_k7ddrphy_bitslip251[4]), + .Q5 (main_k7ddrphy_bitslip251[3]), + .Q6 (main_k7ddrphy_bitslip251[2]), + .Q7 (main_k7ddrphy_bitslip251[1]), + .Q8 (main_k7ddrphy_bitslip251[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_59 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_59 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed25), - .ODATAIN(k7ddrphy_dq_o_nodelay25) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed25), + .ODATAIN (main_k7ddrphy_dq_o_nodelay25) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_25 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_25 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay25), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed25) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay25), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed25) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_25 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_25( - .I(k7ddrphy_dq_o_delayed25), - .T(k7ddrphy_dq_t25), - .IO(ddram_dq[25]), - .O(k7ddrphy_dq_i_nodelay25) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed25), + .T (main_k7ddrphy_dq_t25), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay25), + + // InOuts. + .IO (ddram_dq[25]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_60 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_60 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip260[0]), - .D2(k7ddrphy_bitslip260[1]), - .D3(k7ddrphy_bitslip260[2]), - .D4(k7ddrphy_bitslip260[3]), - .D5(k7ddrphy_bitslip260[4]), - .D6(k7ddrphy_bitslip260[5]), - .D7(k7ddrphy_bitslip260[6]), - .D8(k7ddrphy_bitslip260[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay26), - .TQ(k7ddrphy_dq_t26) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip260[0]), + .D2 (main_k7ddrphy_bitslip260[1]), + .D3 (main_k7ddrphy_bitslip260[2]), + .D4 (main_k7ddrphy_bitslip260[3]), + .D5 (main_k7ddrphy_bitslip260[4]), + .D6 (main_k7ddrphy_bitslip260[5]), + .D7 (main_k7ddrphy_bitslip260[6]), + .D8 (main_k7ddrphy_bitslip260[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay26), + .TQ (main_k7ddrphy_dq_t26) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_26 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_26 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed26), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip261[7]), - .Q2(k7ddrphy_bitslip261[6]), - .Q3(k7ddrphy_bitslip261[5]), - .Q4(k7ddrphy_bitslip261[4]), - .Q5(k7ddrphy_bitslip261[3]), - .Q6(k7ddrphy_bitslip261[2]), - .Q7(k7ddrphy_bitslip261[1]), - .Q8(k7ddrphy_bitslip261[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed26), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip261[7]), + .Q2 (main_k7ddrphy_bitslip261[6]), + .Q3 (main_k7ddrphy_bitslip261[5]), + .Q4 (main_k7ddrphy_bitslip261[4]), + .Q5 (main_k7ddrphy_bitslip261[3]), + .Q6 (main_k7ddrphy_bitslip261[2]), + .Q7 (main_k7ddrphy_bitslip261[1]), + .Q8 (main_k7ddrphy_bitslip261[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_60 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_60 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed26), - .ODATAIN(k7ddrphy_dq_o_nodelay26) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed26), + .ODATAIN (main_k7ddrphy_dq_o_nodelay26) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_26 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_26 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay26), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed26) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay26), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed26) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_26 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_26( - .I(k7ddrphy_dq_o_delayed26), - .T(k7ddrphy_dq_t26), - .IO(ddram_dq[26]), - .O(k7ddrphy_dq_i_nodelay26) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed26), + .T (main_k7ddrphy_dq_t26), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay26), + + // InOuts. + .IO (ddram_dq[26]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_61 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_61 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip270[0]), - .D2(k7ddrphy_bitslip270[1]), - .D3(k7ddrphy_bitslip270[2]), - .D4(k7ddrphy_bitslip270[3]), - .D5(k7ddrphy_bitslip270[4]), - .D6(k7ddrphy_bitslip270[5]), - .D7(k7ddrphy_bitslip270[6]), - .D8(k7ddrphy_bitslip270[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay27), - .TQ(k7ddrphy_dq_t27) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip270[0]), + .D2 (main_k7ddrphy_bitslip270[1]), + .D3 (main_k7ddrphy_bitslip270[2]), + .D4 (main_k7ddrphy_bitslip270[3]), + .D5 (main_k7ddrphy_bitslip270[4]), + .D6 (main_k7ddrphy_bitslip270[5]), + .D7 (main_k7ddrphy_bitslip270[6]), + .D8 (main_k7ddrphy_bitslip270[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay27), + .TQ (main_k7ddrphy_dq_t27) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_27 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_27 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed27), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip271[7]), - .Q2(k7ddrphy_bitslip271[6]), - .Q3(k7ddrphy_bitslip271[5]), - .Q4(k7ddrphy_bitslip271[4]), - .Q5(k7ddrphy_bitslip271[3]), - .Q6(k7ddrphy_bitslip271[2]), - .Q7(k7ddrphy_bitslip271[1]), - .Q8(k7ddrphy_bitslip271[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed27), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip271[7]), + .Q2 (main_k7ddrphy_bitslip271[6]), + .Q3 (main_k7ddrphy_bitslip271[5]), + .Q4 (main_k7ddrphy_bitslip271[4]), + .Q5 (main_k7ddrphy_bitslip271[3]), + .Q6 (main_k7ddrphy_bitslip271[2]), + .Q7 (main_k7ddrphy_bitslip271[1]), + .Q8 (main_k7ddrphy_bitslip271[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_61 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_61 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed27), - .ODATAIN(k7ddrphy_dq_o_nodelay27) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed27), + .ODATAIN (main_k7ddrphy_dq_o_nodelay27) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_27 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_27 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay27), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed27) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay27), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed27) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_27 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_27( - .I(k7ddrphy_dq_o_delayed27), - .T(k7ddrphy_dq_t27), - .IO(ddram_dq[27]), - .O(k7ddrphy_dq_i_nodelay27) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed27), + .T (main_k7ddrphy_dq_t27), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay27), + + // InOuts. + .IO (ddram_dq[27]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_62 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_62 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip280[0]), - .D2(k7ddrphy_bitslip280[1]), - .D3(k7ddrphy_bitslip280[2]), - .D4(k7ddrphy_bitslip280[3]), - .D5(k7ddrphy_bitslip280[4]), - .D6(k7ddrphy_bitslip280[5]), - .D7(k7ddrphy_bitslip280[6]), - .D8(k7ddrphy_bitslip280[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay28), - .TQ(k7ddrphy_dq_t28) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip280[0]), + .D2 (main_k7ddrphy_bitslip280[1]), + .D3 (main_k7ddrphy_bitslip280[2]), + .D4 (main_k7ddrphy_bitslip280[3]), + .D5 (main_k7ddrphy_bitslip280[4]), + .D6 (main_k7ddrphy_bitslip280[5]), + .D7 (main_k7ddrphy_bitslip280[6]), + .D8 (main_k7ddrphy_bitslip280[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay28), + .TQ (main_k7ddrphy_dq_t28) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_28 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_28 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed28), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip281[7]), - .Q2(k7ddrphy_bitslip281[6]), - .Q3(k7ddrphy_bitslip281[5]), - .Q4(k7ddrphy_bitslip281[4]), - .Q5(k7ddrphy_bitslip281[3]), - .Q6(k7ddrphy_bitslip281[2]), - .Q7(k7ddrphy_bitslip281[1]), - .Q8(k7ddrphy_bitslip281[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed28), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip281[7]), + .Q2 (main_k7ddrphy_bitslip281[6]), + .Q3 (main_k7ddrphy_bitslip281[5]), + .Q4 (main_k7ddrphy_bitslip281[4]), + .Q5 (main_k7ddrphy_bitslip281[3]), + .Q6 (main_k7ddrphy_bitslip281[2]), + .Q7 (main_k7ddrphy_bitslip281[1]), + .Q8 (main_k7ddrphy_bitslip281[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_62 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_62 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed28), - .ODATAIN(k7ddrphy_dq_o_nodelay28) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed28), + .ODATAIN (main_k7ddrphy_dq_o_nodelay28) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_28 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_28 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay28), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed28) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay28), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed28) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_28 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_28( - .I(k7ddrphy_dq_o_delayed28), - .T(k7ddrphy_dq_t28), - .IO(ddram_dq[28]), - .O(k7ddrphy_dq_i_nodelay28) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed28), + .T (main_k7ddrphy_dq_t28), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay28), + + // InOuts. + .IO (ddram_dq[28]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_63 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_63 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip290[0]), - .D2(k7ddrphy_bitslip290[1]), - .D3(k7ddrphy_bitslip290[2]), - .D4(k7ddrphy_bitslip290[3]), - .D5(k7ddrphy_bitslip290[4]), - .D6(k7ddrphy_bitslip290[5]), - .D7(k7ddrphy_bitslip290[6]), - .D8(k7ddrphy_bitslip290[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay29), - .TQ(k7ddrphy_dq_t29) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip290[0]), + .D2 (main_k7ddrphy_bitslip290[1]), + .D3 (main_k7ddrphy_bitslip290[2]), + .D4 (main_k7ddrphy_bitslip290[3]), + .D5 (main_k7ddrphy_bitslip290[4]), + .D6 (main_k7ddrphy_bitslip290[5]), + .D7 (main_k7ddrphy_bitslip290[6]), + .D8 (main_k7ddrphy_bitslip290[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay29), + .TQ (main_k7ddrphy_dq_t29) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_29 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_29 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed29), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip291[7]), - .Q2(k7ddrphy_bitslip291[6]), - .Q3(k7ddrphy_bitslip291[5]), - .Q4(k7ddrphy_bitslip291[4]), - .Q5(k7ddrphy_bitslip291[3]), - .Q6(k7ddrphy_bitslip291[2]), - .Q7(k7ddrphy_bitslip291[1]), - .Q8(k7ddrphy_bitslip291[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed29), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip291[7]), + .Q2 (main_k7ddrphy_bitslip291[6]), + .Q3 (main_k7ddrphy_bitslip291[5]), + .Q4 (main_k7ddrphy_bitslip291[4]), + .Q5 (main_k7ddrphy_bitslip291[3]), + .Q6 (main_k7ddrphy_bitslip291[2]), + .Q7 (main_k7ddrphy_bitslip291[1]), + .Q8 (main_k7ddrphy_bitslip291[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_63 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_63 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed29), - .ODATAIN(k7ddrphy_dq_o_nodelay29) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed29), + .ODATAIN (main_k7ddrphy_dq_o_nodelay29) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_29 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_29 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay29), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed29) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay29), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed29) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_29 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_29( - .I(k7ddrphy_dq_o_delayed29), - .T(k7ddrphy_dq_t29), - .IO(ddram_dq[29]), - .O(k7ddrphy_dq_i_nodelay29) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed29), + .T (main_k7ddrphy_dq_t29), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay29), + + // InOuts. + .IO (ddram_dq[29]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_64 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_64 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip300[0]), - .D2(k7ddrphy_bitslip300[1]), - .D3(k7ddrphy_bitslip300[2]), - .D4(k7ddrphy_bitslip300[3]), - .D5(k7ddrphy_bitslip300[4]), - .D6(k7ddrphy_bitslip300[5]), - .D7(k7ddrphy_bitslip300[6]), - .D8(k7ddrphy_bitslip300[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay30), - .TQ(k7ddrphy_dq_t30) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip300[0]), + .D2 (main_k7ddrphy_bitslip300[1]), + .D3 (main_k7ddrphy_bitslip300[2]), + .D4 (main_k7ddrphy_bitslip300[3]), + .D5 (main_k7ddrphy_bitslip300[4]), + .D6 (main_k7ddrphy_bitslip300[5]), + .D7 (main_k7ddrphy_bitslip300[6]), + .D8 (main_k7ddrphy_bitslip300[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay30), + .TQ (main_k7ddrphy_dq_t30) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_30 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_30 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed30), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip301[7]), - .Q2(k7ddrphy_bitslip301[6]), - .Q3(k7ddrphy_bitslip301[5]), - .Q4(k7ddrphy_bitslip301[4]), - .Q5(k7ddrphy_bitslip301[3]), - .Q6(k7ddrphy_bitslip301[2]), - .Q7(k7ddrphy_bitslip301[1]), - .Q8(k7ddrphy_bitslip301[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed30), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip301[7]), + .Q2 (main_k7ddrphy_bitslip301[6]), + .Q3 (main_k7ddrphy_bitslip301[5]), + .Q4 (main_k7ddrphy_bitslip301[4]), + .Q5 (main_k7ddrphy_bitslip301[3]), + .Q6 (main_k7ddrphy_bitslip301[2]), + .Q7 (main_k7ddrphy_bitslip301[1]), + .Q8 (main_k7ddrphy_bitslip301[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_64 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_64 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed30), - .ODATAIN(k7ddrphy_dq_o_nodelay30) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed30), + .ODATAIN (main_k7ddrphy_dq_o_nodelay30) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_30 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_30 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay30), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed30) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay30), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed30) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_30 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_30( - .I(k7ddrphy_dq_o_delayed30), - .T(k7ddrphy_dq_t30), - .IO(ddram_dq[30]), - .O(k7ddrphy_dq_i_nodelay30) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed30), + .T (main_k7ddrphy_dq_t30), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay30), + + // InOuts. + .IO (ddram_dq[30]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_65 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_65 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(k7ddrphy_bitslip310[0]), - .D2(k7ddrphy_bitslip310[1]), - .D3(k7ddrphy_bitslip310[2]), - .D4(k7ddrphy_bitslip310[3]), - .D5(k7ddrphy_bitslip310[4]), - .D6(k7ddrphy_bitslip310[5]), - .D7(k7ddrphy_bitslip310[6]), - .D8(k7ddrphy_bitslip310[7]), - .OCE(1'd1), - .RST((sys_rst | k7ddrphy_rst_storage)), - .T1((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(k7ddrphy_dq_o_nodelay31), - .TQ(k7ddrphy_dq_t31) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_k7ddrphy_bitslip310[0]), + .D2 (main_k7ddrphy_bitslip310[1]), + .D3 (main_k7ddrphy_bitslip310[2]), + .D4 (main_k7ddrphy_bitslip310[3]), + .D5 (main_k7ddrphy_bitslip310[4]), + .D6 (main_k7ddrphy_bitslip310[5]), + .D7 (main_k7ddrphy_bitslip310[6]), + .D8 (main_k7ddrphy_bitslip310[7]), + .OCE (1'd1), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + .T1 ((~main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_k7ddrphy_dq_o_nodelay31), + .TQ (main_k7ddrphy_dq_t31) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_31 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_31 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(k7ddrphy_dq_i_delayed31), - .RST((sys_rst | k7ddrphy_rst_storage)), - .Q1(k7ddrphy_bitslip311[7]), - .Q2(k7ddrphy_bitslip311[6]), - .Q3(k7ddrphy_bitslip311[5]), - .Q4(k7ddrphy_bitslip311[4]), - .Q5(k7ddrphy_bitslip311[3]), - .Q6(k7ddrphy_bitslip311[2]), - .Q7(k7ddrphy_bitslip311[1]), - .Q8(k7ddrphy_bitslip311[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_k7ddrphy_dq_i_delayed31), + .RST ((sys_rst | main_k7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_k7ddrphy_bitslip311[7]), + .Q2 (main_k7ddrphy_bitslip311[6]), + .Q3 (main_k7ddrphy_bitslip311[5]), + .Q4 (main_k7ddrphy_bitslip311[4]), + .Q5 (main_k7ddrphy_bitslip311[3]), + .Q6 (main_k7ddrphy_bitslip311[2]), + .Q7 (main_k7ddrphy_bitslip311[1]), + .Q8 (main_k7ddrphy_bitslip311[0]) ); +//------------------------------------------------------------------------------ +// Instance ODELAYE2_65 of ODELAYE2 Module. +//------------------------------------------------------------------------------ ODELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("ODATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .ODELAY_TYPE("VARIABLE"), - .ODELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .ODELAY_TYPE ("VARIABLE"), + .ODELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) ODELAYE2_65 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_o_delayed31), - .ODATAIN(k7ddrphy_dq_o_nodelay31) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_inc_re)), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_wdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_o_delayed31), + .ODATAIN (main_k7ddrphy_dq_o_nodelay31) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_31 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_31 ( - .C(sys_clk), - .CE((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)), - .IDATAIN(k7ddrphy_dq_i_nodelay31), - .INC(1'd1), - .LD(((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(k7ddrphy_dq_i_delayed31) + // Inputs. + .C (sys_clk), + .CE ((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_k7ddrphy_dq_i_nodelay31), + .INC (1'd1), + .LD (((main_k7ddrphy_dly_sel_storage[3] & main_k7ddrphy_rdly_dq_rst_re) | main_k7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_k7ddrphy_dq_i_delayed31) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_31 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_31( - .I(k7ddrphy_dq_o_delayed31), - .T(k7ddrphy_dq_t31), - .IO(ddram_dq[31]), - .O(k7ddrphy_dq_i_nodelay31) + // Inputs. + .I (main_k7ddrphy_dq_o_delayed31), + .T (main_k7ddrphy_dq_t31), + + // Outputs. + .O (main_k7ddrphy_dq_i_nodelay31), + + // InOuts. + .IO (ddram_dq[31]) ); //------------------------------------------------------------------------------ @@ -20650,14 +22924,14 @@ IOBUF IOBUF_31( reg [24:0] storage[0:15]; reg [24:0] storage_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine0_wrport_we) - storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w; - storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr]; + if (main_litedramcore_bankmachine0_wrport_we) + storage[main_litedramcore_bankmachine0_wrport_adr] <= main_litedramcore_bankmachine0_wrport_dat_w; + storage_dat0 <= storage[main_litedramcore_bankmachine0_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0; -assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr]; +assign main_litedramcore_bankmachine0_wrport_dat_r = storage_dat0; +assign main_litedramcore_bankmachine0_rdport_dat_r = storage[main_litedramcore_bankmachine0_rdport_adr]; //------------------------------------------------------------------------------ @@ -20668,14 +22942,14 @@ assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine reg [24:0] storage_1[0:15]; reg [24:0] storage_1_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine1_wrport_we) - storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w; - storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr]; + if (main_litedramcore_bankmachine1_wrport_we) + storage_1[main_litedramcore_bankmachine1_wrport_adr] <= main_litedramcore_bankmachine1_wrport_dat_w; + storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0; -assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr]; +assign main_litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0; +assign main_litedramcore_bankmachine1_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_rdport_adr]; //------------------------------------------------------------------------------ @@ -20686,14 +22960,14 @@ assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachi reg [24:0] storage_2[0:15]; reg [24:0] storage_2_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine2_wrport_we) - storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w; - storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr]; + if (main_litedramcore_bankmachine2_wrport_we) + storage_2[main_litedramcore_bankmachine2_wrport_adr] <= main_litedramcore_bankmachine2_wrport_dat_w; + storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0; -assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr]; +assign main_litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0; +assign main_litedramcore_bankmachine2_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_rdport_adr]; //------------------------------------------------------------------------------ @@ -20704,14 +22978,14 @@ assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachi reg [24:0] storage_3[0:15]; reg [24:0] storage_3_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine3_wrport_we) - storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w; - storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr]; + if (main_litedramcore_bankmachine3_wrport_we) + storage_3[main_litedramcore_bankmachine3_wrport_adr] <= main_litedramcore_bankmachine3_wrport_dat_w; + storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0; -assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr]; +assign main_litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0; +assign main_litedramcore_bankmachine3_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_rdport_adr]; //------------------------------------------------------------------------------ @@ -20722,14 +22996,14 @@ assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachi reg [24:0] storage_4[0:15]; reg [24:0] storage_4_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine4_wrport_we) - storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w; - storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr]; + if (main_litedramcore_bankmachine4_wrport_we) + storage_4[main_litedramcore_bankmachine4_wrport_adr] <= main_litedramcore_bankmachine4_wrport_dat_w; + storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0; -assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr]; +assign main_litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0; +assign main_litedramcore_bankmachine4_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_rdport_adr]; //------------------------------------------------------------------------------ @@ -20740,14 +23014,14 @@ assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachi reg [24:0] storage_5[0:15]; reg [24:0] storage_5_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine5_wrport_we) - storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w; - storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr]; + if (main_litedramcore_bankmachine5_wrport_we) + storage_5[main_litedramcore_bankmachine5_wrport_adr] <= main_litedramcore_bankmachine5_wrport_dat_w; + storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0; -assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr]; +assign main_litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0; +assign main_litedramcore_bankmachine5_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_rdport_adr]; //------------------------------------------------------------------------------ @@ -20758,14 +23032,14 @@ assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachi reg [24:0] storage_6[0:15]; reg [24:0] storage_6_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine6_wrport_we) - storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w; - storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr]; + if (main_litedramcore_bankmachine6_wrport_we) + storage_6[main_litedramcore_bankmachine6_wrport_adr] <= main_litedramcore_bankmachine6_wrport_dat_w; + storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0; -assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr]; +assign main_litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0; +assign main_litedramcore_bankmachine6_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_rdport_adr]; //------------------------------------------------------------------------------ @@ -20776,197 +23050,308 @@ assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachi reg [24:0] storage_7[0:15]; reg [24:0] storage_7_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine7_wrport_we) - storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w; - storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr]; + if (main_litedramcore_bankmachine7_wrport_we) + storage_7[main_litedramcore_bankmachine7_wrport_adr] <= main_litedramcore_bankmachine7_wrport_dat_w; + storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0; -assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr]; +assign main_litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0; +assign main_litedramcore_bankmachine7_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_rdport_adr]; +//------------------------------------------------------------------------------ +// Instance FDCE of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(reset), - .Q(litedramcore_reset0) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (main_reset), + + // Outputs. + .Q (builder_reset0) ); +//------------------------------------------------------------------------------ +// Instance FDCE_1 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_1( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset0), - .Q(litedramcore_reset1) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset0), + + // Outputs. + .Q (builder_reset1) ); +//------------------------------------------------------------------------------ +// Instance FDCE_2 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_2( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset1), - .Q(litedramcore_reset2) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset1), + + // Outputs. + .Q (builder_reset2) ); +//------------------------------------------------------------------------------ +// Instance FDCE_3 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_3( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset2), - .Q(litedramcore_reset3) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset2), + + // Outputs. + .Q (builder_reset3) ); +//------------------------------------------------------------------------------ +// Instance FDCE_4 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_4( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset3), - .Q(litedramcore_reset4) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset3), + + // Outputs. + .Q (builder_reset4) ); +//------------------------------------------------------------------------------ +// Instance FDCE_5 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_5( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset4), - .Q(litedramcore_reset5) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset4), + + // Outputs. + .Q (builder_reset5) ); +//------------------------------------------------------------------------------ +// Instance FDCE_6 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_6( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset5), - .Q(litedramcore_reset6) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset5), + + // Outputs. + .Q (builder_reset6) ); +//------------------------------------------------------------------------------ +// Instance FDCE_7 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_7( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset6), - .Q(litedramcore_reset7) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset6), + + // Outputs. + .Q (builder_reset7) ); +//------------------------------------------------------------------------------ +// Instance PLLE2_ADV of PLLE2_ADV Module. +//------------------------------------------------------------------------------ PLLE2_ADV #( - .CLKFBOUT_MULT(4'd8), - .CLKIN1_PERIOD(5.0), - .CLKOUT0_DIVIDE(4'd8), - .CLKOUT0_PHASE(1'd0), - .CLKOUT1_DIVIDE(5'd16), - .CLKOUT1_PHASE(1'd0), - .CLKOUT2_DIVIDE(3'd4), - .CLKOUT2_PHASE(1'd0), - .CLKOUT3_DIVIDE(3'd4), - .CLKOUT3_PHASE(7'd90), - .DIVCLK_DIVIDE(1'd1), - .REF_JITTER1(0.01), - .STARTUP_WAIT("FALSE") + // Parameters. + .CLKFBOUT_MULT (4'd8), + .CLKIN1_PERIOD (5.0), + .CLKOUT0_DIVIDE (4'd8), + .CLKOUT0_PHASE (1'd0), + .CLKOUT1_DIVIDE (5'd16), + .CLKOUT1_PHASE (1'd0), + .CLKOUT2_DIVIDE (3'd4), + .CLKOUT2_PHASE (1'd0), + .CLKOUT3_DIVIDE (3'd4), + .CLKOUT3_PHASE (7'd90), + .DIVCLK_DIVIDE (1'd1), + .REF_JITTER1 (0.01), + .STARTUP_WAIT ("FALSE") ) PLLE2_ADV ( - .CLKFBIN(litedramcore_pll_fb), - .CLKIN1(clkin), - .PWRDWN(power_down), - .RST(litedramcore_reset7), - .CLKFBOUT(litedramcore_pll_fb), - .CLKOUT0(clkout0), - .CLKOUT1(clkout1), - .CLKOUT2(clkout2), - .CLKOUT3(clkout3), - .LOCKED(locked) + // Inputs. + .CLKFBIN (builder_pll_fb), + .CLKIN1 (main_clkin), + .PWRDWN (main_power_down), + .RST (builder_reset7), + + // Outputs. + .CLKFBOUT (builder_pll_fb), + .CLKOUT0 (main_clkout0), + .CLKOUT1 (main_clkout1), + .CLKOUT2 (main_clkout2), + .CLKOUT3 (main_clkout3), + .LOCKED (main_locked) ); (* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE ( - .C(iodelay_clk), - .CE(1'd1), - .D(1'd0), - .PRE(xilinxasyncresetsynchronizerimpl0), - .Q(xilinxasyncresetsynchronizerimpl0_rst_meta) + // Inputs. + .C (iodelay_clk), + .CE (1'd1), + .D (1'd0), + .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl0_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_1 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_1 ( - .C(iodelay_clk), - .CE(1'd1), - .D(xilinxasyncresetsynchronizerimpl0_rst_meta), - .PRE(xilinxasyncresetsynchronizerimpl0), - .Q(iodelay_rst) + // Inputs. + .C (iodelay_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl0_rst_meta), + .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + + // Outputs. + .Q (iodelay_rst) ); (* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_2 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_2 ( - .C(sys_clk), - .CE(1'd1), - .D(1'd0), - .PRE(xilinxasyncresetsynchronizerimpl1), - .Q(xilinxasyncresetsynchronizerimpl1_rst_meta) + // Inputs. + .C (sys_clk), + .CE (1'd1), + .D (1'd0), + .PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl1_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_3 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_3 ( - .C(sys_clk), - .CE(1'd1), - .D(xilinxasyncresetsynchronizerimpl1_rst_meta), - .PRE(xilinxasyncresetsynchronizerimpl1), - .Q(sys_rst) + // Inputs. + .C (sys_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl1_rst_meta), + .PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset), + + // Outputs. + .Q (sys_rst) ); (* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_4 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_4 ( - .C(sys4x_clk), - .CE(1'd1), - .D(1'd0), - .PRE(xilinxasyncresetsynchronizerimpl2), - .Q(xilinxasyncresetsynchronizerimpl2_rst_meta) + // Inputs. + .C (sys4x_clk), + .CE (1'd1), + .D (1'd0), + .PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl2_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_5 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_5 ( - .C(sys4x_clk), - .CE(1'd1), - .D(xilinxasyncresetsynchronizerimpl2_rst_meta), - .PRE(xilinxasyncresetsynchronizerimpl2), - .Q(xilinxasyncresetsynchronizerimpl2_expr) + // Inputs. + .C (sys4x_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl2_rst_meta), + .PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl2_expr) ); (* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_6 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_6 ( - .C(sys4x_dqs_clk), - .CE(1'd1), - .D(1'd0), - .PRE(xilinxasyncresetsynchronizerimpl3), - .Q(xilinxasyncresetsynchronizerimpl3_rst_meta) + // Inputs. + .C (sys4x_dqs_clk), + .CE (1'd1), + .D (1'd0), + .PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl3_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_7 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_7 ( - .C(sys4x_dqs_clk), - .CE(1'd1), - .D(xilinxasyncresetsynchronizerimpl3_rst_meta), - .PRE(xilinxasyncresetsynchronizerimpl3), - .Q(xilinxasyncresetsynchronizerimpl3_expr) + // Inputs. + .C (sys4x_dqs_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl3_rst_meta), + .PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl3_expr) ); endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2022-10-28 19:01:22. +// Auto-Generated by LiteX on 2024-04-01 10:12:08. //------------------------------------------------------------------------------ diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init index 61e54f3..0573632 100644 --- a/litedram/generated/nexys-video/litedram_core.init +++ b/litedram/generated/nexys-video/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ff00782107c6 3d80000060215f00 798c07c6618c0000 -618c10e0658cff00 +618c10d4658cff00 4e8004217d8903a6 4e8004207c6903a6 0000000000000000 @@ -510,677 +510,687 @@ a64b5a7d14004a39 0000000000000000 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10:12:06 //------------------------------------------------------------------------------ +`timescale 1ns / 1ps //------------------------------------------------------------------------------ // Module @@ -19,4659 +20,5077 @@ module litedram_core ( input wire clk, - input wire rst, - output wire pll_locked, output wire [14:0] ddram_a, output wire [2:0] ddram_ba, - output wire ddram_ras_n, output wire ddram_cas_n, - output wire ddram_we_n, + output wire ddram_cke, + output wire ddram_clk_n, + output wire ddram_clk_p, output wire ddram_cs_n, output wire [1:0] ddram_dm, inout wire [15:0] ddram_dq, - inout wire [1:0] ddram_dqs_p, inout wire [1:0] ddram_dqs_n, - output wire ddram_clk_p, - output wire ddram_clk_n, - output wire ddram_cke, + inout wire [1:0] ddram_dqs_p, output wire ddram_odt, + output wire ddram_ras_n, output wire ddram_reset_n, + output wire ddram_we_n, output wire init_done, output wire init_error, - input wire [29:0] wb_ctrl_adr, - input wire [31:0] wb_ctrl_dat_w, - output wire [31:0] wb_ctrl_dat_r, - input wire [3:0] wb_ctrl_sel, - input wire wb_ctrl_cyc, - input wire wb_ctrl_stb, - output wire wb_ctrl_ack, - input wire wb_ctrl_we, - input wire [2:0] wb_ctrl_cti, - input wire [1:0] wb_ctrl_bte, - output wire wb_ctrl_err, + output wire pll_locked, + input wire rst, output wire user_clk, - output wire user_rst, - input wire user_port_native_0_cmd_valid, + input wire [24:0] user_port_native_0_cmd_addr, output wire user_port_native_0_cmd_ready, + input wire user_port_native_0_cmd_valid, input wire user_port_native_0_cmd_we, - input wire [24:0] user_port_native_0_cmd_addr, - input wire user_port_native_0_wdata_valid, + output wire [127:0] user_port_native_0_rdata_data, + input wire user_port_native_0_rdata_ready, + output wire user_port_native_0_rdata_valid, + input wire [127:0] user_port_native_0_wdata_data, output wire user_port_native_0_wdata_ready, + input wire user_port_native_0_wdata_valid, input wire [15:0] user_port_native_0_wdata_we, - input wire [127:0] user_port_native_0_wdata_data, - output wire user_port_native_0_rdata_valid, - input wire user_port_native_0_rdata_ready, - output wire [127:0] user_port_native_0_rdata_data + output wire user_rst, + output wire wb_ctrl_ack, + input wire [29:0] wb_ctrl_adr, + input wire [1:0] wb_ctrl_bte, + input wire [2:0] wb_ctrl_cti, + input wire wb_ctrl_cyc, + output wire [31:0] wb_ctrl_dat_r, + input wire [31:0] wb_ctrl_dat_w, + output wire wb_ctrl_err, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_stb, + input wire wb_ctrl_we ); +//------------------------------------------------------------------------------ +// Hierarchy +//------------------------------------------------------------------------------ + +/* +LiteDRAMCore +└─── bus (SoCBusHandler) +│ └─── _interconnect (InterconnectPointToPoint) +└─── csr (SoCCSRHandler) +└─── irq (SoCIRQHandler) +└─── cpu (CPUNone) +└─── crg (LiteDRAMS7DDRPHYCRG) +│ └─── pll (S7PLL) +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [BUFG] +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [BUFG] +│ │ └─── [BUFG] +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [PLLE2_ADV] +│ │ └─── [BUFG] +│ └─── idelayctrl (S7IDELAYCTRL) +│ │ └─── [IDELAYCTRL] +└─── ddrphy (A7DDRPHY) +│ └─── tappeddelayline_0* (TappedDelayLine) +│ └─── dqspattern_0* (DQSPattern) +│ └─── bitslip_0* (BitSlip) +│ └─── bitslip_1* (BitSlip) +│ └─── bitslip_2* (BitSlip) +│ └─── bitslip_3* (BitSlip) +│ └─── tappeddelayline_1* (TappedDelayLine) +│ └─── bitslip_4* (BitSlip) +│ └─── bitslip_5* (BitSlip) +│ └─── bitslip_6* (BitSlip) +│ └─── bitslip_7* (BitSlip) +│ └─── bitslip_8* (BitSlip) +│ └─── bitslip_9* (BitSlip) +│ └─── bitslip_10* (BitSlip) +│ └─── bitslip_11* (BitSlip) +│ └─── bitslip_12* (BitSlip) +│ └─── bitslip_13* (BitSlip) +│ └─── bitslip_14* (BitSlip) +│ └─── bitslip_15* (BitSlip) +│ └─── bitslip_16* (BitSlip) +│ └─── bitslip_17* (BitSlip) +│ └─── bitslip_18* (BitSlip) +│ └─── bitslip_19* (BitSlip) +│ └─── bitslip_20* (BitSlip) +│ └─── bitslip_21* (BitSlip) +│ └─── bitslip_22* (BitSlip) +│ └─── bitslip_23* (BitSlip) +│ └─── bitslip_24* (BitSlip) +│ └─── bitslip_25* (BitSlip) +│ └─── bitslip_26* (BitSlip) +│ └─── bitslip_27* (BitSlip) +│ └─── bitslip_28* (BitSlip) +│ └─── bitslip_29* (BitSlip) +│ └─── bitslip_30* (BitSlip) +│ └─── bitslip_31* (BitSlip) +│ └─── bitslip_32* (BitSlip) +│ └─── bitslip_33* (BitSlip) +│ └─── bitslip_34* (BitSlip) +│ └─── bitslip_35* (BitSlip) +│ └─── tappeddelayline_2* (TappedDelayLine) +│ └─── tappeddelayline_3* (TappedDelayLine) +│ └─── [IOBUF] +│ └─── [ISERDESE2] +│ └─── [IOBUFDS] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [IDELAYE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [OBUFDS] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUFDS] +│ └─── [IOBUF] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [IOBUF] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +└─── sdram (LiteDRAMCore) +│ └─── dfii (DFIInjector) +│ │ └─── pi0 (PhaseInjector) +│ │ └─── pi1 (PhaseInjector) +│ │ └─── pi2 (PhaseInjector) +│ │ └─── pi3 (PhaseInjector) +│ └─── controller (LiteDRAMController) +│ │ └─── refresher (Refresher) +│ │ │ └─── timer (RefreshTimer) +│ │ │ └─── postponer (RefreshPostponer) +│ │ │ └─── sequencer (RefreshSequencer) +│ │ │ │ └─── refreshexecuter_0* (RefreshExecuter) +│ │ │ └─── zqcs_timer (RefreshTimer) +│ │ │ └─── zqs_executer (ZQCSExecuter) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_0* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_1* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_2* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_3* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_4* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_5* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_6* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_7* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── multiplexer (Multiplexer) +│ │ │ └─── choose_cmd (_CommandChooser) +│ │ │ │ └─── roundrobin_0* (RoundRobin) +│ │ │ └─── choose_req (_CommandChooser) +│ │ │ │ └─── roundrobin_0* (RoundRobin) +│ │ │ └─── _steerer_0* (_Steerer) +│ │ │ └─── trrdcon (tXXDController) +│ │ │ └─── tfawcon (tFAWController) +│ │ │ └─── tccdcon (tXXDController) +│ │ │ └─── twtrcon (tXXDController) +│ │ │ └─── fsm (FSM) +│ └─── crossbar (LiteDRAMCrossbar) +│ │ └─── roundrobin_0* (RoundRobin) +│ │ └─── roundrobin_1* (RoundRobin) +│ │ └─── roundrobin_2* (RoundRobin) +│ │ └─── roundrobin_3* (RoundRobin) +│ │ └─── roundrobin_4* (RoundRobin) +│ │ └─── roundrobin_5* (RoundRobin) +│ │ └─── roundrobin_6* (RoundRobin) +│ │ └─── roundrobin_7* (RoundRobin) +└─── ddrctrl (LiteDRAMCoreControl) +└─── csr_bridge (Wishbone2CSR) +│ └─── fsm (FSM) +└─── csr_bankarray (CSRBankArray) +│ └─── csrbank_0* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ └─── csrbank_1* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstorage_4* (CSRStorage) +│ │ └─── csrstorage_5* (CSRStorage) +│ └─── csrbank_2* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstorage_4* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstorage_5* (CSRStorage) +│ │ └─── csrstorage_6* (CSRStorage) +│ │ └─── csrstorage_7* (CSRStorage) +│ │ └─── csrstorage_8* (CSRStorage) +│ │ └─── csrstatus_1* (CSRStatus) +│ │ └─── csrstorage_9* (CSRStorage) +│ │ └─── csrstorage_10* (CSRStorage) +│ │ └─── csrstorage_11* (CSRStorage) +│ │ └─── csrstorage_12* (CSRStorage) +│ │ └─── csrstatus_2* (CSRStatus) +│ │ └─── csrstorage_13* (CSRStorage) +│ │ └─── csrstorage_14* (CSRStorage) +│ │ └─── csrstorage_15* (CSRStorage) +│ │ └─── csrstorage_16* (CSRStorage) +│ │ └─── csrstatus_3* (CSRStatus) +└─── csr_interconnect (InterconnectShared) +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +* : Generated name. +[]: BlackBox. +*/ + //------------------------------------------------------------------------------ // Signals //------------------------------------------------------------------------------ -reg rst_1 = 1'd0; -wire sys_clk; -wire sys_rst; -wire sys4x_clk; -wire sys4x_dqs_clk; +wire [13:0] builder_adr; +reg [3:0] builder_bankmachine0_next_state = 4'd0; +reg [3:0] builder_bankmachine0_state = 4'd0; +reg [3:0] builder_bankmachine1_next_state = 4'd0; +reg [3:0] builder_bankmachine1_state = 4'd0; +reg [3:0] builder_bankmachine2_next_state = 4'd0; +reg [3:0] builder_bankmachine2_state = 4'd0; +reg [3:0] builder_bankmachine3_next_state = 4'd0; +reg [3:0] builder_bankmachine3_state = 4'd0; +reg [3:0] builder_bankmachine4_next_state = 4'd0; +reg [3:0] builder_bankmachine4_state = 4'd0; +reg [3:0] builder_bankmachine5_next_state = 4'd0; +reg [3:0] builder_bankmachine5_state = 4'd0; +reg [3:0] builder_bankmachine6_next_state = 4'd0; +reg [3:0] builder_bankmachine6_state = 4'd0; +reg [3:0] builder_bankmachine7_next_state = 4'd0; +reg [3:0] builder_bankmachine7_state = 4'd0; +wire builder_csrbank0_init_done0_r; +reg builder_csrbank0_init_done0_re = 1'd0; +wire builder_csrbank0_init_done0_w; +reg builder_csrbank0_init_done0_we = 1'd0; +wire builder_csrbank0_init_error0_r; +reg builder_csrbank0_init_error0_re = 1'd0; +wire builder_csrbank0_init_error0_w; +reg builder_csrbank0_init_error0_we = 1'd0; +wire builder_csrbank0_sel; +wire [1:0] builder_csrbank1_dly_sel0_r; +reg builder_csrbank1_dly_sel0_re = 1'd0; +wire [1:0] builder_csrbank1_dly_sel0_w; +reg builder_csrbank1_dly_sel0_we = 1'd0; +wire [4:0] builder_csrbank1_half_sys8x_taps0_r; +reg builder_csrbank1_half_sys8x_taps0_re = 1'd0; +wire [4:0] builder_csrbank1_half_sys8x_taps0_w; +reg builder_csrbank1_half_sys8x_taps0_we = 1'd0; +wire [1:0] builder_csrbank1_rdphase0_r; +reg builder_csrbank1_rdphase0_re = 1'd0; +wire [1:0] builder_csrbank1_rdphase0_w; +reg builder_csrbank1_rdphase0_we = 1'd0; +wire builder_csrbank1_rst0_r; +reg builder_csrbank1_rst0_re = 1'd0; +wire builder_csrbank1_rst0_w; +reg builder_csrbank1_rst0_we = 1'd0; +wire builder_csrbank1_sel; +wire builder_csrbank1_wlevel_en0_r; +reg builder_csrbank1_wlevel_en0_re = 1'd0; +wire builder_csrbank1_wlevel_en0_w; +reg builder_csrbank1_wlevel_en0_we = 1'd0; +wire [1:0] builder_csrbank1_wrphase0_r; +reg builder_csrbank1_wrphase0_re = 1'd0; +wire [1:0] builder_csrbank1_wrphase0_w; +reg builder_csrbank1_wrphase0_we = 1'd0; +wire [3:0] builder_csrbank2_dfii_control0_r; +reg builder_csrbank2_dfii_control0_re = 1'd0; +wire [3:0] builder_csrbank2_dfii_control0_w; +reg builder_csrbank2_dfii_control0_we = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi0_address0_r; +reg builder_csrbank2_dfii_pi0_address0_re = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi0_address0_w; +reg builder_csrbank2_dfii_pi0_address0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r; +reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w; +reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_command0_r; +reg builder_csrbank2_dfii_pi0_command0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_command0_w; +reg builder_csrbank2_dfii_pi0_command0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_rddata_r; +reg builder_csrbank2_dfii_pi0_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_rddata_w; +reg builder_csrbank2_dfii_pi0_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_r; +reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_w; +reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi1_address0_r; +reg builder_csrbank2_dfii_pi1_address0_re = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi1_address0_w; +reg builder_csrbank2_dfii_pi1_address0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r; +reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w; +reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_command0_r; +reg builder_csrbank2_dfii_pi1_command0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_command0_w; +reg builder_csrbank2_dfii_pi1_command0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_rddata_r; +reg builder_csrbank2_dfii_pi1_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_rddata_w; +reg builder_csrbank2_dfii_pi1_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_r; +reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_w; +reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi2_address0_r; +reg builder_csrbank2_dfii_pi2_address0_re = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi2_address0_w; +reg builder_csrbank2_dfii_pi2_address0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r; +reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w; +reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_command0_r; +reg builder_csrbank2_dfii_pi2_command0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_command0_w; +reg builder_csrbank2_dfii_pi2_command0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_rddata_r; +reg builder_csrbank2_dfii_pi2_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_rddata_w; +reg builder_csrbank2_dfii_pi2_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_r; +reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_w; +reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi3_address0_r; +reg builder_csrbank2_dfii_pi3_address0_re = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi3_address0_w; +reg builder_csrbank2_dfii_pi3_address0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r; +reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w; +reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_command0_r; +reg builder_csrbank2_dfii_pi3_command0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_command0_w; +reg builder_csrbank2_dfii_pi3_command0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_rddata_r; +reg builder_csrbank2_dfii_pi3_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_rddata_w; +reg builder_csrbank2_dfii_pi3_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_r; +reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_w; +reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0; +wire builder_csrbank2_sel; +wire [31:0] builder_dat_r; +wire [31:0] builder_dat_w; +reg builder_interface0_ack = 1'd0; +wire [29:0] builder_interface0_adr; +wire [13:0] builder_interface0_bank_bus_adr; +reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface0_bank_bus_dat_w; +wire builder_interface0_bank_bus_we; +wire [1:0] builder_interface0_bte; +wire [2:0] builder_interface0_cti; +wire builder_interface0_cyc; +reg [31:0] builder_interface0_dat_r = 32'd0; +wire [31:0] builder_interface0_dat_w; +reg builder_interface0_err = 1'd0; +wire [3:0] builder_interface0_sel; +wire builder_interface0_stb; +wire builder_interface0_we; +reg [13:0] builder_interface1_adr = 14'd0; +reg [13:0] builder_interface1_adr_next_value1 = 14'd0; +reg builder_interface1_adr_next_value_ce1 = 1'd0; +wire [13:0] builder_interface1_bank_bus_adr; +reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface1_bank_bus_dat_w; +wire builder_interface1_bank_bus_we; +wire [31:0] builder_interface1_dat_r; +reg [31:0] builder_interface1_dat_w = 32'd0; +reg [31:0] builder_interface1_dat_w_next_value0 = 32'd0; +reg builder_interface1_dat_w_next_value_ce0 = 1'd0; +reg builder_interface1_we = 1'd0; +reg builder_interface1_we_next_value2 = 1'd0; +reg builder_interface1_we_next_value_ce2 = 1'd0; +wire [13:0] builder_interface2_bank_bus_adr; +reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface2_bank_bus_dat_w; +wire builder_interface2_bank_bus_we; +reg builder_locked0 = 1'd0; +reg builder_locked1 = 1'd0; +reg builder_locked2 = 1'd0; +reg builder_locked3 = 1'd0; +reg builder_locked4 = 1'd0; +reg builder_locked5 = 1'd0; +reg builder_locked6 = 1'd0; +reg builder_locked7 = 1'd0; +reg [3:0] builder_multiplexer_next_state = 4'd0; +reg [3:0] builder_multiplexer_state = 4'd0; +reg builder_new_master_rdata_valid0 = 1'd0; +reg builder_new_master_rdata_valid1 = 1'd0; +reg builder_new_master_rdata_valid2 = 1'd0; +reg builder_new_master_rdata_valid3 = 1'd0; +reg builder_new_master_rdata_valid4 = 1'd0; +reg builder_new_master_rdata_valid5 = 1'd0; +reg builder_new_master_rdata_valid6 = 1'd0; +reg builder_new_master_rdata_valid7 = 1'd0; +reg builder_new_master_rdata_valid8 = 1'd0; +reg builder_new_master_wdata_ready0 = 1'd0; +reg builder_new_master_wdata_ready1 = 1'd0; +reg [1:0] builder_next_state = 2'd0; +wire builder_pll_fb; +reg [1:0] builder_refresher_next_state = 2'd0; +reg [1:0] builder_refresher_state = 2'd0; +wire builder_reset0; +wire builder_reset1; +wire builder_reset2; +wire builder_reset3; +wire builder_reset4; +wire builder_reset5; +wire builder_reset6; +wire builder_reset7; +reg builder_rhs_self0 = 1'd0; +reg [14:0] builder_rhs_self1 = 15'd0; +reg builder_rhs_self10 = 1'd0; +reg builder_rhs_self11 = 1'd0; +reg [21:0] builder_rhs_self12 = 22'd0; +reg builder_rhs_self13 = 1'd0; +reg builder_rhs_self14 = 1'd0; +reg [21:0] builder_rhs_self15 = 22'd0; +reg builder_rhs_self16 = 1'd0; +reg builder_rhs_self17 = 1'd0; +reg [21:0] builder_rhs_self18 = 22'd0; +reg builder_rhs_self19 = 1'd0; +reg [2:0] builder_rhs_self2 = 3'd0; +reg builder_rhs_self20 = 1'd0; +reg [21:0] builder_rhs_self21 = 22'd0; +reg builder_rhs_self22 = 1'd0; +reg builder_rhs_self23 = 1'd0; +reg [21:0] builder_rhs_self24 = 22'd0; +reg builder_rhs_self25 = 1'd0; +reg builder_rhs_self26 = 1'd0; +reg [21:0] builder_rhs_self27 = 22'd0; +reg builder_rhs_self28 = 1'd0; +reg builder_rhs_self29 = 1'd0; +reg builder_rhs_self3 = 1'd0; +reg [21:0] builder_rhs_self30 = 22'd0; +reg builder_rhs_self31 = 1'd0; +reg builder_rhs_self32 = 1'd0; +reg [21:0] builder_rhs_self33 = 22'd0; +reg builder_rhs_self34 = 1'd0; +reg builder_rhs_self35 = 1'd0; +reg builder_rhs_self4 = 1'd0; +reg builder_rhs_self5 = 1'd0; +reg builder_rhs_self6 = 1'd0; +reg [14:0] builder_rhs_self7 = 15'd0; +reg [2:0] builder_rhs_self8 = 3'd0; +reg builder_rhs_self9 = 1'd0; +wire builder_roundrobin0_ce; +wire builder_roundrobin0_grant; +wire builder_roundrobin0_request; +wire builder_roundrobin1_ce; +wire builder_roundrobin1_grant; +wire builder_roundrobin1_request; +wire builder_roundrobin2_ce; +wire builder_roundrobin2_grant; +wire builder_roundrobin2_request; +wire builder_roundrobin3_ce; +wire builder_roundrobin3_grant; +wire builder_roundrobin3_request; +wire builder_roundrobin4_ce; +wire builder_roundrobin4_grant; +wire builder_roundrobin4_request; +wire builder_roundrobin5_ce; +wire builder_roundrobin5_grant; +wire builder_roundrobin5_request; +wire builder_roundrobin6_ce; +wire builder_roundrobin6_grant; +wire builder_roundrobin6_request; +wire builder_roundrobin7_ce; +wire builder_roundrobin7_grant; +wire builder_roundrobin7_request; +reg [2:0] builder_self0 = 3'd0; +reg [14:0] builder_self1 = 15'd0; +reg builder_self10 = 1'd0; +reg builder_self11 = 1'd0; +reg builder_self12 = 1'd0; +reg builder_self13 = 1'd0; +reg [2:0] builder_self14 = 3'd0; +reg [14:0] builder_self15 = 15'd0; +reg builder_self16 = 1'd0; +reg builder_self17 = 1'd0; +reg builder_self18 = 1'd0; +reg builder_self19 = 1'd0; +reg builder_self2 = 1'd0; +reg builder_self20 = 1'd0; +reg [2:0] builder_self21 = 3'd0; +reg [14:0] builder_self22 = 15'd0; +reg builder_self23 = 1'd0; +reg builder_self24 = 1'd0; +reg builder_self25 = 1'd0; +reg builder_self26 = 1'd0; +reg builder_self27 = 1'd0; +reg builder_self3 = 1'd0; +reg builder_self4 = 1'd0; +reg builder_self5 = 1'd0; +reg builder_self6 = 1'd0; +reg [2:0] builder_self7 = 3'd0; +reg [14:0] builder_self8 = 15'd0; +reg builder_self9 = 1'd0; +reg [1:0] builder_state = 2'd0; +reg builder_t_self0 = 1'd0; +reg builder_t_self1 = 1'd0; +reg builder_t_self2 = 1'd0; +reg builder_t_self3 = 1'd0; +reg builder_t_self4 = 1'd0; +reg builder_t_self5 = 1'd0; +wire builder_we; +wire builder_xilinxasyncresetsynchronizerimpl0_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl1_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl2_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl2_expr; +wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl3_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl3_expr; +wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta; wire iodelay_clk; wire iodelay_rst; -wire reset; -reg power_down = 1'd0; -wire locked; -wire clkin; -wire clkout0; -wire clkout_buf0; -wire clkout1; -wire clkout_buf1; -wire clkout2; -wire clkout_buf2; -wire clkout3; -wire clkout_buf3; -reg [3:0] reset_counter = 4'd15; -reg ic_reset = 1'd1; -reg a7ddrphy_rst_storage = 1'd0; -reg a7ddrphy_rst_re = 1'd0; -reg [1:0] a7ddrphy_dly_sel_storage = 2'd0; -reg a7ddrphy_dly_sel_re = 1'd0; -reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8; -reg a7ddrphy_half_sys8x_taps_re = 1'd0; -reg a7ddrphy_wlevel_en_storage = 1'd0; -reg a7ddrphy_wlevel_en_re = 1'd0; -reg a7ddrphy_wlevel_strobe_re = 1'd0; -wire a7ddrphy_wlevel_strobe_r; -reg a7ddrphy_wlevel_strobe_we = 1'd0; -reg a7ddrphy_wlevel_strobe_w = 1'd0; -reg a7ddrphy_rdly_dq_rst_re = 1'd0; -wire a7ddrphy_rdly_dq_rst_r; -reg a7ddrphy_rdly_dq_rst_we = 1'd0; -reg a7ddrphy_rdly_dq_rst_w = 1'd0; -reg a7ddrphy_rdly_dq_inc_re = 1'd0; -wire a7ddrphy_rdly_dq_inc_r; -reg a7ddrphy_rdly_dq_inc_we = 1'd0; -reg a7ddrphy_rdly_dq_inc_w = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; -wire a7ddrphy_rdly_dq_bitslip_rst_r; -reg a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_re = 1'd0; -wire a7ddrphy_rdly_dq_bitslip_r; -reg a7ddrphy_rdly_dq_bitslip_we = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_w = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; -wire a7ddrphy_wdly_dq_bitslip_rst_r; -reg a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_re = 1'd0; -wire a7ddrphy_wdly_dq_bitslip_r; -reg a7ddrphy_wdly_dq_bitslip_we = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_w = 1'd0; -reg [1:0] a7ddrphy_rdphase_storage = 2'd2; -reg a7ddrphy_rdphase_re = 1'd0; -reg [1:0] a7ddrphy_wrphase_storage = 2'd3; -reg a7ddrphy_wrphase_re = 1'd0; -wire [14:0] a7ddrphy_dfi_p0_address; -wire [2:0] a7ddrphy_dfi_p0_bank; -wire a7ddrphy_dfi_p0_cas_n; -wire a7ddrphy_dfi_p0_cs_n; -wire a7ddrphy_dfi_p0_ras_n; -wire a7ddrphy_dfi_p0_we_n; -wire a7ddrphy_dfi_p0_cke; -wire a7ddrphy_dfi_p0_odt; -wire a7ddrphy_dfi_p0_reset_n; -wire a7ddrphy_dfi_p0_act_n; -wire [31:0] a7ddrphy_dfi_p0_wrdata; -wire a7ddrphy_dfi_p0_wrdata_en; -wire [3:0] a7ddrphy_dfi_p0_wrdata_mask; -wire a7ddrphy_dfi_p0_rddata_en; -reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0; -wire a7ddrphy_dfi_p0_rddata_valid; -wire [14:0] a7ddrphy_dfi_p1_address; -wire [2:0] a7ddrphy_dfi_p1_bank; -wire a7ddrphy_dfi_p1_cas_n; -wire a7ddrphy_dfi_p1_cs_n; -wire a7ddrphy_dfi_p1_ras_n; -wire a7ddrphy_dfi_p1_we_n; -wire a7ddrphy_dfi_p1_cke; -wire a7ddrphy_dfi_p1_odt; -wire a7ddrphy_dfi_p1_reset_n; -wire a7ddrphy_dfi_p1_act_n; -wire [31:0] a7ddrphy_dfi_p1_wrdata; -wire a7ddrphy_dfi_p1_wrdata_en; -wire [3:0] a7ddrphy_dfi_p1_wrdata_mask; -wire a7ddrphy_dfi_p1_rddata_en; -reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0; -wire a7ddrphy_dfi_p1_rddata_valid; -wire [14:0] a7ddrphy_dfi_p2_address; -wire [2:0] a7ddrphy_dfi_p2_bank; -wire a7ddrphy_dfi_p2_cas_n; -wire a7ddrphy_dfi_p2_cs_n; -wire a7ddrphy_dfi_p2_ras_n; -wire a7ddrphy_dfi_p2_we_n; -wire a7ddrphy_dfi_p2_cke; -wire a7ddrphy_dfi_p2_odt; -wire a7ddrphy_dfi_p2_reset_n; -wire a7ddrphy_dfi_p2_act_n; -wire [31:0] a7ddrphy_dfi_p2_wrdata; -wire a7ddrphy_dfi_p2_wrdata_en; -wire [3:0] a7ddrphy_dfi_p2_wrdata_mask; -wire a7ddrphy_dfi_p2_rddata_en; -reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0; -wire a7ddrphy_dfi_p2_rddata_valid; -wire [14:0] a7ddrphy_dfi_p3_address; -wire [2:0] a7ddrphy_dfi_p3_bank; -wire a7ddrphy_dfi_p3_cas_n; -wire a7ddrphy_dfi_p3_cs_n; -wire a7ddrphy_dfi_p3_ras_n; -wire a7ddrphy_dfi_p3_we_n; -wire a7ddrphy_dfi_p3_cke; -wire a7ddrphy_dfi_p3_odt; -wire a7ddrphy_dfi_p3_reset_n; -wire a7ddrphy_dfi_p3_act_n; -wire [31:0] a7ddrphy_dfi_p3_wrdata; -wire a7ddrphy_dfi_p3_wrdata_en; -wire [3:0] a7ddrphy_dfi_p3_wrdata_mask; -wire a7ddrphy_dfi_p3_rddata_en; -reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0; -wire a7ddrphy_dfi_p3_rddata_valid; -wire a7ddrphy_sd_clk_se_nodelay; -wire [2:0] a7ddrphy_pads_ba; -reg a7ddrphy_dqs_oe = 1'd0; -wire a7ddrphy_dqs_preamble; -wire a7ddrphy_dqs_postamble; -wire a7ddrphy_dqs_oe_delay_tappeddelayline; -reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -reg a7ddrphy_dqspattern0 = 1'd0; -reg a7ddrphy_dqspattern1 = 1'd0; -reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0; -reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0; -wire a7ddrphy_dqs_o_no_delay0; -wire a7ddrphy_dqs_t0; -reg [7:0] a7ddrphy_bitslip00 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r0 = 16'd0; -wire a7ddrphy0; -wire a7ddrphy_dqs_o_no_delay1; -wire a7ddrphy_dqs_t1; -reg [7:0] a7ddrphy_bitslip10 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r0 = 16'd0; -wire a7ddrphy1; -reg [7:0] a7ddrphy_bitslip01 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r1 = 16'd0; -reg [7:0] a7ddrphy_bitslip11 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r1 = 16'd0; -wire a7ddrphy_dq_oe; -wire a7ddrphy_dq_oe_delay_tappeddelayline; -reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -wire a7ddrphy_dq_o_nodelay0; -wire a7ddrphy_dq_i_nodelay0; -wire a7ddrphy_dq_i_delayed0; -wire a7ddrphy_dq_t0; -reg [7:0] a7ddrphy_bitslip02 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value2 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r2 = 16'd0; -wire [7:0] a7ddrphy_bitslip03; -reg [7:0] a7ddrphy_bitslip04 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value3 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r3 = 16'd0; -wire a7ddrphy_dq_o_nodelay1; -wire a7ddrphy_dq_i_nodelay1; -wire a7ddrphy_dq_i_delayed1; -wire a7ddrphy_dq_t1; -reg [7:0] a7ddrphy_bitslip12 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value2 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r2 = 16'd0; -wire [7:0] a7ddrphy_bitslip13; -reg [7:0] a7ddrphy_bitslip14 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value3 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r3 = 16'd0; -wire a7ddrphy_dq_o_nodelay2; -wire a7ddrphy_dq_i_nodelay2; -wire a7ddrphy_dq_i_delayed2; -wire a7ddrphy_dq_t2; -reg [7:0] a7ddrphy_bitslip20 = 8'd0; -reg [2:0] a7ddrphy_bitslip2_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip2_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip21; -reg [7:0] a7ddrphy_bitslip22 = 8'd0; -reg [2:0] a7ddrphy_bitslip2_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip2_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay3; -wire a7ddrphy_dq_i_nodelay3; -wire a7ddrphy_dq_i_delayed3; -wire a7ddrphy_dq_t3; -reg [7:0] a7ddrphy_bitslip30 = 8'd0; -reg [2:0] a7ddrphy_bitslip3_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip3_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip31; -reg [7:0] a7ddrphy_bitslip32 = 8'd0; -reg [2:0] a7ddrphy_bitslip3_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip3_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay4; -wire a7ddrphy_dq_i_nodelay4; -wire a7ddrphy_dq_i_delayed4; -wire a7ddrphy_dq_t4; -reg [7:0] a7ddrphy_bitslip40 = 8'd0; -reg [2:0] a7ddrphy_bitslip4_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip4_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip41; -reg [7:0] a7ddrphy_bitslip42 = 8'd0; -reg [2:0] a7ddrphy_bitslip4_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip4_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay5; -wire a7ddrphy_dq_i_nodelay5; -wire a7ddrphy_dq_i_delayed5; -wire a7ddrphy_dq_t5; -reg [7:0] a7ddrphy_bitslip50 = 8'd0; -reg [2:0] a7ddrphy_bitslip5_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip5_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip51; -reg [7:0] a7ddrphy_bitslip52 = 8'd0; -reg [2:0] a7ddrphy_bitslip5_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip5_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay6; -wire a7ddrphy_dq_i_nodelay6; -wire a7ddrphy_dq_i_delayed6; -wire a7ddrphy_dq_t6; -reg [7:0] a7ddrphy_bitslip60 = 8'd0; -reg [2:0] a7ddrphy_bitslip6_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip6_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip61; -reg [7:0] a7ddrphy_bitslip62 = 8'd0; -reg [2:0] a7ddrphy_bitslip6_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip6_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay7; -wire a7ddrphy_dq_i_nodelay7; -wire a7ddrphy_dq_i_delayed7; -wire a7ddrphy_dq_t7; -reg [7:0] a7ddrphy_bitslip70 = 8'd0; -reg [2:0] a7ddrphy_bitslip7_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip7_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip71; -reg [7:0] a7ddrphy_bitslip72 = 8'd0; -reg [2:0] a7ddrphy_bitslip7_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip7_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay8; -wire a7ddrphy_dq_i_nodelay8; -wire a7ddrphy_dq_i_delayed8; -wire a7ddrphy_dq_t8; -reg [7:0] a7ddrphy_bitslip80 = 8'd0; -reg [2:0] a7ddrphy_bitslip8_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip8_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip81; -reg [7:0] a7ddrphy_bitslip82 = 8'd0; -reg [2:0] a7ddrphy_bitslip8_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip8_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay9; -wire a7ddrphy_dq_i_nodelay9; -wire a7ddrphy_dq_i_delayed9; -wire a7ddrphy_dq_t9; -reg [7:0] a7ddrphy_bitslip90 = 8'd0; -reg [2:0] a7ddrphy_bitslip9_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip9_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip91; -reg [7:0] a7ddrphy_bitslip92 = 8'd0; -reg [2:0] a7ddrphy_bitslip9_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip9_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay10; -wire a7ddrphy_dq_i_nodelay10; -wire a7ddrphy_dq_i_delayed10; -wire a7ddrphy_dq_t10; -reg [7:0] a7ddrphy_bitslip100 = 8'd0; -reg [2:0] a7ddrphy_bitslip10_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip10_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip101; -reg [7:0] a7ddrphy_bitslip102 = 8'd0; -reg [2:0] a7ddrphy_bitslip10_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip10_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay11; -wire a7ddrphy_dq_i_nodelay11; -wire a7ddrphy_dq_i_delayed11; -wire a7ddrphy_dq_t11; -reg [7:0] a7ddrphy_bitslip110 = 8'd0; -reg [2:0] a7ddrphy_bitslip11_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip11_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip111; -reg [7:0] a7ddrphy_bitslip112 = 8'd0; -reg [2:0] a7ddrphy_bitslip11_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip11_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay12; -wire a7ddrphy_dq_i_nodelay12; -wire a7ddrphy_dq_i_delayed12; -wire a7ddrphy_dq_t12; -reg [7:0] a7ddrphy_bitslip120 = 8'd0; -reg [2:0] a7ddrphy_bitslip12_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip12_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip121; -reg [7:0] a7ddrphy_bitslip122 = 8'd0; -reg [2:0] a7ddrphy_bitslip12_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip12_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay13; -wire a7ddrphy_dq_i_nodelay13; -wire a7ddrphy_dq_i_delayed13; -wire a7ddrphy_dq_t13; -reg [7:0] a7ddrphy_bitslip130 = 8'd0; -reg [2:0] a7ddrphy_bitslip13_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip13_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip131; -reg [7:0] a7ddrphy_bitslip132 = 8'd0; -reg [2:0] a7ddrphy_bitslip13_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip13_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay14; -wire a7ddrphy_dq_i_nodelay14; -wire a7ddrphy_dq_i_delayed14; -wire a7ddrphy_dq_t14; -reg [7:0] a7ddrphy_bitslip140 = 8'd0; -reg [2:0] a7ddrphy_bitslip14_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip14_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip141; -reg [7:0] a7ddrphy_bitslip142 = 8'd0; -reg [2:0] a7ddrphy_bitslip14_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip14_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay15; -wire a7ddrphy_dq_i_nodelay15; -wire a7ddrphy_dq_i_delayed15; -wire a7ddrphy_dq_t15; -reg [7:0] a7ddrphy_bitslip150 = 8'd0; -reg [2:0] a7ddrphy_bitslip15_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip15_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip151; -reg [7:0] a7ddrphy_bitslip152 = 8'd0; -reg [2:0] a7ddrphy_bitslip15_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip15_r1 = 16'd0; -reg a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; -reg a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; -reg a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; -reg a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; -wire [14:0] litedramcore_slave_p0_address; -wire [2:0] litedramcore_slave_p0_bank; -wire litedramcore_slave_p0_cas_n; -wire litedramcore_slave_p0_cs_n; -wire litedramcore_slave_p0_ras_n; -wire litedramcore_slave_p0_we_n; -wire litedramcore_slave_p0_cke; -wire litedramcore_slave_p0_odt; -wire litedramcore_slave_p0_reset_n; -wire litedramcore_slave_p0_act_n; -wire [31:0] litedramcore_slave_p0_wrdata; -wire litedramcore_slave_p0_wrdata_en; -wire [3:0] litedramcore_slave_p0_wrdata_mask; -wire litedramcore_slave_p0_rddata_en; -reg [31:0] litedramcore_slave_p0_rddata = 32'd0; -reg litedramcore_slave_p0_rddata_valid = 1'd0; -wire [14:0] litedramcore_slave_p1_address; -wire [2:0] litedramcore_slave_p1_bank; -wire litedramcore_slave_p1_cas_n; -wire litedramcore_slave_p1_cs_n; -wire litedramcore_slave_p1_ras_n; -wire litedramcore_slave_p1_we_n; -wire litedramcore_slave_p1_cke; -wire litedramcore_slave_p1_odt; -wire litedramcore_slave_p1_reset_n; -wire litedramcore_slave_p1_act_n; -wire [31:0] litedramcore_slave_p1_wrdata; -wire litedramcore_slave_p1_wrdata_en; -wire [3:0] litedramcore_slave_p1_wrdata_mask; -wire litedramcore_slave_p1_rddata_en; -reg [31:0] litedramcore_slave_p1_rddata = 32'd0; -reg litedramcore_slave_p1_rddata_valid = 1'd0; -wire [14:0] litedramcore_slave_p2_address; -wire [2:0] litedramcore_slave_p2_bank; -wire litedramcore_slave_p2_cas_n; -wire litedramcore_slave_p2_cs_n; -wire litedramcore_slave_p2_ras_n; -wire litedramcore_slave_p2_we_n; -wire litedramcore_slave_p2_cke; -wire litedramcore_slave_p2_odt; -wire litedramcore_slave_p2_reset_n; -wire litedramcore_slave_p2_act_n; -wire [31:0] litedramcore_slave_p2_wrdata; -wire litedramcore_slave_p2_wrdata_en; -wire [3:0] litedramcore_slave_p2_wrdata_mask; -wire litedramcore_slave_p2_rddata_en; -reg [31:0] litedramcore_slave_p2_rddata = 32'd0; -reg litedramcore_slave_p2_rddata_valid = 1'd0; -wire [14:0] litedramcore_slave_p3_address; -wire [2:0] litedramcore_slave_p3_bank; -wire litedramcore_slave_p3_cas_n; -wire litedramcore_slave_p3_cs_n; -wire litedramcore_slave_p3_ras_n; -wire litedramcore_slave_p3_we_n; -wire litedramcore_slave_p3_cke; -wire litedramcore_slave_p3_odt; -wire litedramcore_slave_p3_reset_n; -wire litedramcore_slave_p3_act_n; -wire [31:0] litedramcore_slave_p3_wrdata; -wire litedramcore_slave_p3_wrdata_en; -wire [3:0] litedramcore_slave_p3_wrdata_mask; -wire litedramcore_slave_p3_rddata_en; -reg [31:0] litedramcore_slave_p3_rddata = 32'd0; -reg litedramcore_slave_p3_rddata_valid = 1'd0; -reg [14:0] litedramcore_master_p0_address = 15'd0; -reg [2:0] litedramcore_master_p0_bank = 3'd0; -reg litedramcore_master_p0_cas_n = 1'd1; -reg litedramcore_master_p0_cs_n = 1'd1; -reg litedramcore_master_p0_ras_n = 1'd1; -reg litedramcore_master_p0_we_n = 1'd1; -reg litedramcore_master_p0_cke = 1'd0; -reg litedramcore_master_p0_odt = 1'd0; -reg litedramcore_master_p0_reset_n = 1'd0; -reg litedramcore_master_p0_act_n = 1'd1; -reg [31:0] litedramcore_master_p0_wrdata = 32'd0; -reg litedramcore_master_p0_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0; -reg litedramcore_master_p0_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p0_rddata; -wire litedramcore_master_p0_rddata_valid; -reg [14:0] litedramcore_master_p1_address = 15'd0; -reg [2:0] litedramcore_master_p1_bank = 3'd0; -reg litedramcore_master_p1_cas_n = 1'd1; -reg litedramcore_master_p1_cs_n = 1'd1; -reg litedramcore_master_p1_ras_n = 1'd1; -reg litedramcore_master_p1_we_n = 1'd1; -reg litedramcore_master_p1_cke = 1'd0; -reg litedramcore_master_p1_odt = 1'd0; -reg litedramcore_master_p1_reset_n = 1'd0; -reg litedramcore_master_p1_act_n = 1'd1; -reg [31:0] litedramcore_master_p1_wrdata = 32'd0; -reg litedramcore_master_p1_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0; -reg litedramcore_master_p1_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p1_rddata; -wire litedramcore_master_p1_rddata_valid; -reg [14:0] litedramcore_master_p2_address = 15'd0; -reg [2:0] litedramcore_master_p2_bank = 3'd0; -reg litedramcore_master_p2_cas_n = 1'd1; -reg litedramcore_master_p2_cs_n = 1'd1; -reg litedramcore_master_p2_ras_n = 1'd1; -reg litedramcore_master_p2_we_n = 1'd1; -reg litedramcore_master_p2_cke = 1'd0; -reg litedramcore_master_p2_odt = 1'd0; -reg litedramcore_master_p2_reset_n = 1'd0; -reg litedramcore_master_p2_act_n = 1'd1; -reg [31:0] litedramcore_master_p2_wrdata = 32'd0; -reg litedramcore_master_p2_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0; -reg litedramcore_master_p2_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p2_rddata; -wire litedramcore_master_p2_rddata_valid; -reg [14:0] litedramcore_master_p3_address = 15'd0; -reg [2:0] litedramcore_master_p3_bank = 3'd0; -reg litedramcore_master_p3_cas_n = 1'd1; -reg litedramcore_master_p3_cs_n = 1'd1; -reg litedramcore_master_p3_ras_n = 1'd1; -reg litedramcore_master_p3_we_n = 1'd1; -reg litedramcore_master_p3_cke = 1'd0; -reg litedramcore_master_p3_odt = 1'd0; -reg litedramcore_master_p3_reset_n = 1'd0; -reg litedramcore_master_p3_act_n = 1'd1; -reg [31:0] litedramcore_master_p3_wrdata = 32'd0; -reg litedramcore_master_p3_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0; -reg litedramcore_master_p3_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p3_rddata; -wire litedramcore_master_p3_rddata_valid; -wire [14:0] litedramcore_csr_dfi_p0_address; -wire [2:0] litedramcore_csr_dfi_p0_bank; -reg litedramcore_csr_dfi_p0_cas_n = 1'd1; -reg litedramcore_csr_dfi_p0_cs_n = 1'd1; -reg litedramcore_csr_dfi_p0_ras_n = 1'd1; -reg litedramcore_csr_dfi_p0_we_n = 1'd1; -wire litedramcore_csr_dfi_p0_cke; -wire litedramcore_csr_dfi_p0_odt; -wire litedramcore_csr_dfi_p0_reset_n; -reg litedramcore_csr_dfi_p0_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p0_wrdata; -wire litedramcore_csr_dfi_p0_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask; -wire litedramcore_csr_dfi_p0_rddata_en; -reg [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0; -reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0; -wire [14:0] litedramcore_csr_dfi_p1_address; -wire [2:0] litedramcore_csr_dfi_p1_bank; -reg litedramcore_csr_dfi_p1_cas_n = 1'd1; -reg litedramcore_csr_dfi_p1_cs_n = 1'd1; -reg litedramcore_csr_dfi_p1_ras_n = 1'd1; -reg litedramcore_csr_dfi_p1_we_n = 1'd1; -wire litedramcore_csr_dfi_p1_cke; -wire litedramcore_csr_dfi_p1_odt; -wire litedramcore_csr_dfi_p1_reset_n; -reg litedramcore_csr_dfi_p1_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p1_wrdata; -wire litedramcore_csr_dfi_p1_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask; -wire litedramcore_csr_dfi_p1_rddata_en; -reg [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0; -reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0; -wire [14:0] litedramcore_csr_dfi_p2_address; -wire [2:0] litedramcore_csr_dfi_p2_bank; -reg litedramcore_csr_dfi_p2_cas_n = 1'd1; -reg litedramcore_csr_dfi_p2_cs_n = 1'd1; -reg litedramcore_csr_dfi_p2_ras_n = 1'd1; -reg litedramcore_csr_dfi_p2_we_n = 1'd1; -wire litedramcore_csr_dfi_p2_cke; -wire litedramcore_csr_dfi_p2_odt; -wire litedramcore_csr_dfi_p2_reset_n; -reg litedramcore_csr_dfi_p2_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p2_wrdata; -wire litedramcore_csr_dfi_p2_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask; -wire litedramcore_csr_dfi_p2_rddata_en; -reg [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0; -reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0; -wire [14:0] litedramcore_csr_dfi_p3_address; -wire [2:0] litedramcore_csr_dfi_p3_bank; -reg litedramcore_csr_dfi_p3_cas_n = 1'd1; -reg litedramcore_csr_dfi_p3_cs_n = 1'd1; -reg litedramcore_csr_dfi_p3_ras_n = 1'd1; -reg litedramcore_csr_dfi_p3_we_n = 1'd1; -wire litedramcore_csr_dfi_p3_cke; -wire litedramcore_csr_dfi_p3_odt; -wire litedramcore_csr_dfi_p3_reset_n; -reg litedramcore_csr_dfi_p3_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p3_wrdata; -wire litedramcore_csr_dfi_p3_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask; -wire litedramcore_csr_dfi_p3_rddata_en; -reg [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0; -reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0; -reg [14:0] litedramcore_ext_dfi_p0_address = 15'd0; -reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0; -reg litedramcore_ext_dfi_p0_cas_n = 1'd1; -reg litedramcore_ext_dfi_p0_cs_n = 1'd1; -reg litedramcore_ext_dfi_p0_ras_n = 1'd1; -reg litedramcore_ext_dfi_p0_we_n = 1'd1; -reg litedramcore_ext_dfi_p0_cke = 1'd0; -reg litedramcore_ext_dfi_p0_odt = 1'd0; -reg litedramcore_ext_dfi_p0_reset_n = 1'd0; -reg litedramcore_ext_dfi_p0_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0; -reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p0_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0; -reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0; -reg [14:0] litedramcore_ext_dfi_p1_address = 15'd0; -reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0; -reg litedramcore_ext_dfi_p1_cas_n = 1'd1; -reg litedramcore_ext_dfi_p1_cs_n = 1'd1; -reg litedramcore_ext_dfi_p1_ras_n = 1'd1; -reg litedramcore_ext_dfi_p1_we_n = 1'd1; -reg litedramcore_ext_dfi_p1_cke = 1'd0; -reg litedramcore_ext_dfi_p1_odt = 1'd0; -reg litedramcore_ext_dfi_p1_reset_n = 1'd0; -reg litedramcore_ext_dfi_p1_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0; -reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p1_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0; -reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0; -reg [14:0] litedramcore_ext_dfi_p2_address = 15'd0; -reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0; -reg litedramcore_ext_dfi_p2_cas_n = 1'd1; -reg litedramcore_ext_dfi_p2_cs_n = 1'd1; -reg litedramcore_ext_dfi_p2_ras_n = 1'd1; -reg litedramcore_ext_dfi_p2_we_n = 1'd1; -reg litedramcore_ext_dfi_p2_cke = 1'd0; -reg litedramcore_ext_dfi_p2_odt = 1'd0; -reg litedramcore_ext_dfi_p2_reset_n = 1'd0; -reg litedramcore_ext_dfi_p2_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0; -reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p2_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0; -reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0; -reg [14:0] litedramcore_ext_dfi_p3_address = 15'd0; -reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0; -reg litedramcore_ext_dfi_p3_cas_n = 1'd1; -reg litedramcore_ext_dfi_p3_cs_n = 1'd1; -reg litedramcore_ext_dfi_p3_ras_n = 1'd1; -reg litedramcore_ext_dfi_p3_we_n = 1'd1; -reg litedramcore_ext_dfi_p3_cke = 1'd0; -reg litedramcore_ext_dfi_p3_odt = 1'd0; -reg litedramcore_ext_dfi_p3_reset_n = 1'd0; -reg litedramcore_ext_dfi_p3_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0; -reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p3_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0; -reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0; -reg litedramcore_ext_dfi_sel = 1'd0; -wire litedramcore_sel; -wire litedramcore_cke; -wire litedramcore_odt; -wire litedramcore_reset_n; -reg [3:0] litedramcore_storage = 4'd1; -reg litedramcore_re = 1'd0; -wire litedramcore_phaseinjector0_csrfield_cs; -wire litedramcore_phaseinjector0_csrfield_we; -wire litedramcore_phaseinjector0_csrfield_cas; -wire litedramcore_phaseinjector0_csrfield_ras; -wire litedramcore_phaseinjector0_csrfield_wren; -wire litedramcore_phaseinjector0_csrfield_rden; -reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; -reg litedramcore_phaseinjector0_command_re = 1'd0; -reg litedramcore_phaseinjector0_command_issue_re = 1'd0; -wire litedramcore_phaseinjector0_command_issue_r; -reg litedramcore_phaseinjector0_command_issue_we = 1'd0; -reg litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [14:0] litedramcore_phaseinjector0_address_storage = 15'd0; -reg litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0; -wire litedramcore_phaseinjector0_rddata_we; -reg litedramcore_phaseinjector0_rddata_re = 1'd0; -wire litedramcore_phaseinjector1_csrfield_cs; -wire litedramcore_phaseinjector1_csrfield_we; -wire litedramcore_phaseinjector1_csrfield_cas; -wire litedramcore_phaseinjector1_csrfield_ras; -wire litedramcore_phaseinjector1_csrfield_wren; -wire litedramcore_phaseinjector1_csrfield_rden; -reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0; -reg litedramcore_phaseinjector1_command_re = 1'd0; -reg litedramcore_phaseinjector1_command_issue_re = 1'd0; -wire litedramcore_phaseinjector1_command_issue_r; -reg litedramcore_phaseinjector1_command_issue_we = 1'd0; -reg litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [14:0] litedramcore_phaseinjector1_address_storage = 15'd0; -reg litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0; -wire litedramcore_phaseinjector1_rddata_we; -reg litedramcore_phaseinjector1_rddata_re = 1'd0; -wire litedramcore_phaseinjector2_csrfield_cs; -wire litedramcore_phaseinjector2_csrfield_we; -wire litedramcore_phaseinjector2_csrfield_cas; -wire litedramcore_phaseinjector2_csrfield_ras; -wire litedramcore_phaseinjector2_csrfield_wren; -wire litedramcore_phaseinjector2_csrfield_rden; -reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0; -reg litedramcore_phaseinjector2_command_re = 1'd0; -reg litedramcore_phaseinjector2_command_issue_re = 1'd0; -wire litedramcore_phaseinjector2_command_issue_r; -reg litedramcore_phaseinjector2_command_issue_we = 1'd0; -reg litedramcore_phaseinjector2_command_issue_w = 1'd0; -reg [14:0] litedramcore_phaseinjector2_address_storage = 15'd0; -reg litedramcore_phaseinjector2_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0; -reg litedramcore_phaseinjector2_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector2_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0; -wire litedramcore_phaseinjector2_rddata_we; -reg litedramcore_phaseinjector2_rddata_re = 1'd0; -wire litedramcore_phaseinjector3_csrfield_cs; -wire litedramcore_phaseinjector3_csrfield_we; -wire litedramcore_phaseinjector3_csrfield_cas; -wire litedramcore_phaseinjector3_csrfield_ras; -wire litedramcore_phaseinjector3_csrfield_wren; -wire litedramcore_phaseinjector3_csrfield_rden; -reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0; -reg litedramcore_phaseinjector3_command_re = 1'd0; -reg litedramcore_phaseinjector3_command_issue_re = 1'd0; -wire litedramcore_phaseinjector3_command_issue_r; -reg litedramcore_phaseinjector3_command_issue_we = 1'd0; -reg litedramcore_phaseinjector3_command_issue_w = 1'd0; -reg [14:0] litedramcore_phaseinjector3_address_storage = 15'd0; -reg litedramcore_phaseinjector3_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0; -reg litedramcore_phaseinjector3_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector3_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0; -wire litedramcore_phaseinjector3_rddata_we; -reg litedramcore_phaseinjector3_rddata_re = 1'd0; -wire litedramcore_interface_bank0_valid; -wire litedramcore_interface_bank0_ready; -wire litedramcore_interface_bank0_we; -wire [21:0] litedramcore_interface_bank0_addr; -wire litedramcore_interface_bank0_lock; -wire litedramcore_interface_bank0_wdata_ready; -wire litedramcore_interface_bank0_rdata_valid; -wire litedramcore_interface_bank1_valid; -wire litedramcore_interface_bank1_ready; -wire litedramcore_interface_bank1_we; -wire [21:0] litedramcore_interface_bank1_addr; -wire litedramcore_interface_bank1_lock; -wire litedramcore_interface_bank1_wdata_ready; -wire litedramcore_interface_bank1_rdata_valid; -wire litedramcore_interface_bank2_valid; -wire litedramcore_interface_bank2_ready; -wire litedramcore_interface_bank2_we; -wire [21:0] litedramcore_interface_bank2_addr; -wire litedramcore_interface_bank2_lock; -wire litedramcore_interface_bank2_wdata_ready; -wire litedramcore_interface_bank2_rdata_valid; -wire litedramcore_interface_bank3_valid; -wire litedramcore_interface_bank3_ready; -wire litedramcore_interface_bank3_we; -wire [21:0] litedramcore_interface_bank3_addr; -wire litedramcore_interface_bank3_lock; -wire litedramcore_interface_bank3_wdata_ready; -wire litedramcore_interface_bank3_rdata_valid; -wire litedramcore_interface_bank4_valid; -wire litedramcore_interface_bank4_ready; -wire litedramcore_interface_bank4_we; -wire [21:0] litedramcore_interface_bank4_addr; -wire litedramcore_interface_bank4_lock; -wire litedramcore_interface_bank4_wdata_ready; -wire litedramcore_interface_bank4_rdata_valid; -wire litedramcore_interface_bank5_valid; -wire litedramcore_interface_bank5_ready; -wire litedramcore_interface_bank5_we; -wire [21:0] litedramcore_interface_bank5_addr; -wire litedramcore_interface_bank5_lock; -wire litedramcore_interface_bank5_wdata_ready; -wire litedramcore_interface_bank5_rdata_valid; -wire litedramcore_interface_bank6_valid; -wire litedramcore_interface_bank6_ready; -wire litedramcore_interface_bank6_we; -wire [21:0] litedramcore_interface_bank6_addr; -wire litedramcore_interface_bank6_lock; -wire litedramcore_interface_bank6_wdata_ready; -wire litedramcore_interface_bank6_rdata_valid; -wire litedramcore_interface_bank7_valid; -wire litedramcore_interface_bank7_ready; -wire litedramcore_interface_bank7_we; -wire [21:0] litedramcore_interface_bank7_addr; -wire litedramcore_interface_bank7_lock; -wire litedramcore_interface_bank7_wdata_ready; -wire litedramcore_interface_bank7_rdata_valid; -reg [127:0] litedramcore_interface_wdata = 128'd0; -reg [15:0] litedramcore_interface_wdata_we = 16'd0; -wire [127:0] litedramcore_interface_rdata; -reg [14:0] litedramcore_dfi_p0_address = 15'd0; -reg [2:0] litedramcore_dfi_p0_bank = 3'd0; -reg litedramcore_dfi_p0_cas_n = 1'd1; -reg litedramcore_dfi_p0_cs_n = 1'd1; -reg litedramcore_dfi_p0_ras_n = 1'd1; -reg litedramcore_dfi_p0_we_n = 1'd1; -wire litedramcore_dfi_p0_cke; -wire litedramcore_dfi_p0_odt; -wire litedramcore_dfi_p0_reset_n; -reg litedramcore_dfi_p0_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p0_wrdata; -reg litedramcore_dfi_p0_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p0_wrdata_mask; -reg litedramcore_dfi_p0_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p0_rddata; -wire litedramcore_dfi_p0_rddata_valid; -reg [14:0] litedramcore_dfi_p1_address = 15'd0; -reg [2:0] litedramcore_dfi_p1_bank = 3'd0; -reg litedramcore_dfi_p1_cas_n = 1'd1; -reg litedramcore_dfi_p1_cs_n = 1'd1; -reg litedramcore_dfi_p1_ras_n = 1'd1; -reg litedramcore_dfi_p1_we_n = 1'd1; -wire litedramcore_dfi_p1_cke; -wire litedramcore_dfi_p1_odt; -wire litedramcore_dfi_p1_reset_n; -reg litedramcore_dfi_p1_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p1_wrdata; -reg litedramcore_dfi_p1_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p1_wrdata_mask; -reg litedramcore_dfi_p1_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p1_rddata; -wire litedramcore_dfi_p1_rddata_valid; -reg [14:0] litedramcore_dfi_p2_address = 15'd0; -reg [2:0] litedramcore_dfi_p2_bank = 3'd0; -reg litedramcore_dfi_p2_cas_n = 1'd1; -reg litedramcore_dfi_p2_cs_n = 1'd1; -reg litedramcore_dfi_p2_ras_n = 1'd1; -reg litedramcore_dfi_p2_we_n = 1'd1; -wire litedramcore_dfi_p2_cke; -wire litedramcore_dfi_p2_odt; -wire litedramcore_dfi_p2_reset_n; -reg litedramcore_dfi_p2_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p2_wrdata; -reg litedramcore_dfi_p2_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p2_wrdata_mask; -reg litedramcore_dfi_p2_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p2_rddata; -wire litedramcore_dfi_p2_rddata_valid; -reg [14:0] litedramcore_dfi_p3_address = 15'd0; -reg [2:0] litedramcore_dfi_p3_bank = 3'd0; -reg litedramcore_dfi_p3_cas_n = 1'd1; -reg litedramcore_dfi_p3_cs_n = 1'd1; -reg litedramcore_dfi_p3_ras_n = 1'd1; -reg litedramcore_dfi_p3_we_n = 1'd1; -wire litedramcore_dfi_p3_cke; -wire litedramcore_dfi_p3_odt; -wire litedramcore_dfi_p3_reset_n; -reg litedramcore_dfi_p3_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p3_wrdata; -reg litedramcore_dfi_p3_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p3_wrdata_mask; -reg litedramcore_dfi_p3_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p3_rddata; -wire litedramcore_dfi_p3_rddata_valid; -reg litedramcore_cmd_valid = 1'd0; -reg litedramcore_cmd_ready = 1'd0; -reg litedramcore_cmd_last = 1'd0; -reg [14:0] litedramcore_cmd_payload_a = 15'd0; -reg [2:0] litedramcore_cmd_payload_ba = 3'd0; -reg litedramcore_cmd_payload_cas = 1'd0; -reg litedramcore_cmd_payload_ras = 1'd0; -reg litedramcore_cmd_payload_we = 1'd0; -reg litedramcore_cmd_payload_is_read = 1'd0; -reg litedramcore_cmd_payload_is_write = 1'd0; -wire litedramcore_wants_refresh; -wire litedramcore_wants_zqcs; -wire litedramcore_timer_wait; -wire litedramcore_timer_done0; -wire [9:0] litedramcore_timer_count0; -wire litedramcore_timer_done1; -reg [9:0] litedramcore_timer_count1 = 10'd781; -wire litedramcore_postponer_req_i; -reg litedramcore_postponer_req_o = 1'd0; -reg litedramcore_postponer_count = 1'd0; -reg litedramcore_sequencer_start0 = 1'd0; -wire litedramcore_sequencer_done0; -wire litedramcore_sequencer_start1; -reg litedramcore_sequencer_done1 = 1'd0; -reg [5:0] litedramcore_sequencer_counter = 6'd0; -reg litedramcore_sequencer_count = 1'd0; -wire litedramcore_zqcs_timer_wait; -wire litedramcore_zqcs_timer_done0; -wire [26:0] litedramcore_zqcs_timer_count0; -wire litedramcore_zqcs_timer_done1; -reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999; -reg litedramcore_zqcs_executer_start = 1'd0; -reg litedramcore_zqcs_executer_done = 1'd0; -reg [4:0] litedramcore_zqcs_executer_counter = 5'd0; -wire litedramcore_bankmachine0_req_valid; -wire litedramcore_bankmachine0_req_ready; -wire litedramcore_bankmachine0_req_we; -wire [21:0] litedramcore_bankmachine0_req_addr; -wire litedramcore_bankmachine0_req_lock; -reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine0_refresh_req; -reg litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg litedramcore_bankmachine0_cmd_valid = 1'd0; -reg litedramcore_bankmachine0_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; -reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine0_auto_precharge = 1'd0; -wire litedramcore_bankmachine0_sink_valid; -wire litedramcore_bankmachine0_sink_ready; -reg litedramcore_bankmachine0_sink_first = 1'd0; -reg litedramcore_bankmachine0_sink_last = 1'd0; -wire litedramcore_bankmachine0_sink_payload_we; -wire [21:0] litedramcore_bankmachine0_sink_payload_addr; -wire litedramcore_bankmachine0_source_valid; -wire litedramcore_bankmachine0_source_ready; -wire litedramcore_bankmachine0_source_first; -wire litedramcore_bankmachine0_source_last; -wire litedramcore_bankmachine0_source_payload_we; -wire [21:0] litedramcore_bankmachine0_source_payload_addr; -wire litedramcore_bankmachine0_syncfifo0_we; -wire litedramcore_bankmachine0_syncfifo0_writable; -wire litedramcore_bankmachine0_syncfifo0_re; -wire litedramcore_bankmachine0_syncfifo0_readable; -wire [24:0] litedramcore_bankmachine0_syncfifo0_din; -wire [24:0] litedramcore_bankmachine0_syncfifo0_dout; -reg [4:0] litedramcore_bankmachine0_level = 5'd0; -reg litedramcore_bankmachine0_replace = 1'd0; -reg [3:0] litedramcore_bankmachine0_produce = 4'd0; -reg [3:0] litedramcore_bankmachine0_consume = 4'd0; -reg [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine0_wrport_dat_r; -wire litedramcore_bankmachine0_wrport_we; -wire [24:0] litedramcore_bankmachine0_wrport_dat_w; -wire litedramcore_bankmachine0_do_read; -wire [3:0] litedramcore_bankmachine0_rdport_adr; -wire [24:0] litedramcore_bankmachine0_rdport_dat_r; -wire litedramcore_bankmachine0_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine0_fifo_in_payload_addr; -wire litedramcore_bankmachine0_fifo_in_first; -wire litedramcore_bankmachine0_fifo_in_last; -wire litedramcore_bankmachine0_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine0_fifo_out_payload_addr; -wire litedramcore_bankmachine0_fifo_out_first; -wire litedramcore_bankmachine0_fifo_out_last; -wire litedramcore_bankmachine0_sink_sink_valid; -wire litedramcore_bankmachine0_sink_sink_ready; -wire litedramcore_bankmachine0_sink_sink_first; -wire litedramcore_bankmachine0_sink_sink_last; -wire litedramcore_bankmachine0_sink_sink_payload_we; -wire [21:0] litedramcore_bankmachine0_sink_sink_payload_addr; -wire litedramcore_bankmachine0_source_source_valid; -wire litedramcore_bankmachine0_source_source_ready; -wire litedramcore_bankmachine0_source_source_first; -wire litedramcore_bankmachine0_source_source_last; -wire litedramcore_bankmachine0_source_source_payload_we; -wire [21:0] litedramcore_bankmachine0_source_source_payload_addr; -wire litedramcore_bankmachine0_pipe_valid_sink_valid; -wire litedramcore_bankmachine0_pipe_valid_sink_ready; -wire litedramcore_bankmachine0_pipe_valid_sink_first; -wire litedramcore_bankmachine0_pipe_valid_sink_last; -wire litedramcore_bankmachine0_pipe_valid_sink_payload_we; -wire [21:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine0_pipe_valid_source_ready; -reg litedramcore_bankmachine0_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine0_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine0_row = 15'd0; -reg litedramcore_bankmachine0_row_opened = 1'd0; -wire litedramcore_bankmachine0_row_hit; -reg litedramcore_bankmachine0_row_open = 1'd0; -reg litedramcore_bankmachine0_row_close = 1'd0; -reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine0_twtpcon_valid; +wire main_a7ddrphy0; +wire main_a7ddrphy1; +reg [7:0] main_a7ddrphy_bitslip00 = 8'd0; +reg [7:0] main_a7ddrphy_bitslip01 = 8'd0; +reg [7:0] main_a7ddrphy_bitslip02 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip03; +reg [7:0] main_a7ddrphy_bitslip04 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip10 = 8'd0; +reg [7:0] main_a7ddrphy_bitslip100 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip101; +reg [7:0] main_a7ddrphy_bitslip102 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip11 = 8'd0; +reg [7:0] main_a7ddrphy_bitslip110 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip111; +reg [7:0] main_a7ddrphy_bitslip112 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip12 = 8'd0; +reg [7:0] main_a7ddrphy_bitslip120 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip121; +reg [7:0] main_a7ddrphy_bitslip122 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7; +wire [7:0] main_a7ddrphy_bitslip13; +reg [7:0] main_a7ddrphy_bitslip130 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip131; +reg [7:0] main_a7ddrphy_bitslip132 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip14 = 8'd0; +reg [7:0] main_a7ddrphy_bitslip140 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip141; +reg [7:0] main_a7ddrphy_bitslip142 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip150 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip151; +reg [7:0] main_a7ddrphy_bitslip152 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip20 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip21; +reg [7:0] main_a7ddrphy_bitslip22 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip30 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip31; +reg [7:0] main_a7ddrphy_bitslip32 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip40 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip41; +reg [7:0] main_a7ddrphy_bitslip42 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip50 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip51; +reg [7:0] main_a7ddrphy_bitslip52 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip60 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip61; +reg [7:0] main_a7ddrphy_bitslip62 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip70 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip71; +reg [7:0] main_a7ddrphy_bitslip72 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip80 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip81; +reg [7:0] main_a7ddrphy_bitslip82 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip90 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip91; +reg [7:0] main_a7ddrphy_bitslip92 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7; +wire main_a7ddrphy_dfi_p0_act_n; +wire [14:0] main_a7ddrphy_dfi_p0_address; +wire [2:0] main_a7ddrphy_dfi_p0_bank; +wire main_a7ddrphy_dfi_p0_cas_n; +wire main_a7ddrphy_dfi_p0_cke; +wire main_a7ddrphy_dfi_p0_cs_n; +wire main_a7ddrphy_dfi_p0_odt; +wire main_a7ddrphy_dfi_p0_ras_n; +reg [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0; +wire main_a7ddrphy_dfi_p0_rddata_en; +wire main_a7ddrphy_dfi_p0_rddata_valid; +wire main_a7ddrphy_dfi_p0_reset_n; +wire main_a7ddrphy_dfi_p0_we_n; +wire [31:0] main_a7ddrphy_dfi_p0_wrdata; +wire main_a7ddrphy_dfi_p0_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p0_wrdata_mask; +wire main_a7ddrphy_dfi_p1_act_n; +wire [14:0] main_a7ddrphy_dfi_p1_address; +wire [2:0] main_a7ddrphy_dfi_p1_bank; +wire main_a7ddrphy_dfi_p1_cas_n; +wire main_a7ddrphy_dfi_p1_cke; +wire main_a7ddrphy_dfi_p1_cs_n; +wire main_a7ddrphy_dfi_p1_odt; +wire main_a7ddrphy_dfi_p1_ras_n; +reg [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0; +wire main_a7ddrphy_dfi_p1_rddata_en; +wire main_a7ddrphy_dfi_p1_rddata_valid; +wire main_a7ddrphy_dfi_p1_reset_n; +wire main_a7ddrphy_dfi_p1_we_n; +wire [31:0] main_a7ddrphy_dfi_p1_wrdata; +wire main_a7ddrphy_dfi_p1_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p1_wrdata_mask; +wire main_a7ddrphy_dfi_p2_act_n; +wire [14:0] main_a7ddrphy_dfi_p2_address; +wire [2:0] main_a7ddrphy_dfi_p2_bank; +wire main_a7ddrphy_dfi_p2_cas_n; +wire main_a7ddrphy_dfi_p2_cke; +wire main_a7ddrphy_dfi_p2_cs_n; +wire main_a7ddrphy_dfi_p2_odt; +wire main_a7ddrphy_dfi_p2_ras_n; +reg [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0; +wire main_a7ddrphy_dfi_p2_rddata_en; +wire main_a7ddrphy_dfi_p2_rddata_valid; +wire main_a7ddrphy_dfi_p2_reset_n; +wire main_a7ddrphy_dfi_p2_we_n; +wire [31:0] main_a7ddrphy_dfi_p2_wrdata; +wire main_a7ddrphy_dfi_p2_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p2_wrdata_mask; +wire main_a7ddrphy_dfi_p3_act_n; +wire [14:0] main_a7ddrphy_dfi_p3_address; +wire [2:0] main_a7ddrphy_dfi_p3_bank; +wire main_a7ddrphy_dfi_p3_cas_n; +wire main_a7ddrphy_dfi_p3_cke; +wire main_a7ddrphy_dfi_p3_cs_n; +wire main_a7ddrphy_dfi_p3_odt; +wire main_a7ddrphy_dfi_p3_ras_n; +reg [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0; +wire main_a7ddrphy_dfi_p3_rddata_en; +wire main_a7ddrphy_dfi_p3_rddata_valid; +wire main_a7ddrphy_dfi_p3_reset_n; +wire main_a7ddrphy_dfi_p3_we_n; +wire [31:0] main_a7ddrphy_dfi_p3_wrdata; +wire main_a7ddrphy_dfi_p3_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p3_wrdata_mask; +reg main_a7ddrphy_dly_sel_re = 1'd0; +reg [1:0] main_a7ddrphy_dly_sel_storage = 2'd0; +wire main_a7ddrphy_dq_i_delayed0; +wire main_a7ddrphy_dq_i_delayed1; +wire main_a7ddrphy_dq_i_delayed10; +wire main_a7ddrphy_dq_i_delayed11; +wire main_a7ddrphy_dq_i_delayed12; +wire main_a7ddrphy_dq_i_delayed13; +wire main_a7ddrphy_dq_i_delayed14; +wire main_a7ddrphy_dq_i_delayed15; +wire main_a7ddrphy_dq_i_delayed2; +wire main_a7ddrphy_dq_i_delayed3; +wire main_a7ddrphy_dq_i_delayed4; +wire main_a7ddrphy_dq_i_delayed5; +wire main_a7ddrphy_dq_i_delayed6; +wire main_a7ddrphy_dq_i_delayed7; +wire main_a7ddrphy_dq_i_delayed8; +wire main_a7ddrphy_dq_i_delayed9; +wire main_a7ddrphy_dq_i_nodelay0; +wire main_a7ddrphy_dq_i_nodelay1; +wire main_a7ddrphy_dq_i_nodelay10; +wire main_a7ddrphy_dq_i_nodelay11; +wire main_a7ddrphy_dq_i_nodelay12; +wire main_a7ddrphy_dq_i_nodelay13; +wire main_a7ddrphy_dq_i_nodelay14; +wire main_a7ddrphy_dq_i_nodelay15; +wire main_a7ddrphy_dq_i_nodelay2; +wire main_a7ddrphy_dq_i_nodelay3; +wire main_a7ddrphy_dq_i_nodelay4; +wire main_a7ddrphy_dq_i_nodelay5; +wire main_a7ddrphy_dq_i_nodelay6; +wire main_a7ddrphy_dq_i_nodelay7; +wire main_a7ddrphy_dq_i_nodelay8; +wire main_a7ddrphy_dq_i_nodelay9; +wire main_a7ddrphy_dq_o_nodelay0; +wire main_a7ddrphy_dq_o_nodelay1; +wire main_a7ddrphy_dq_o_nodelay10; +wire main_a7ddrphy_dq_o_nodelay11; +wire main_a7ddrphy_dq_o_nodelay12; +wire main_a7ddrphy_dq_o_nodelay13; +wire main_a7ddrphy_dq_o_nodelay14; +wire main_a7ddrphy_dq_o_nodelay15; +wire main_a7ddrphy_dq_o_nodelay2; +wire main_a7ddrphy_dq_o_nodelay3; +wire main_a7ddrphy_dq_o_nodelay4; +wire main_a7ddrphy_dq_o_nodelay5; +wire main_a7ddrphy_dq_o_nodelay6; +wire main_a7ddrphy_dq_o_nodelay7; +wire main_a7ddrphy_dq_o_nodelay8; +wire main_a7ddrphy_dq_o_nodelay9; +wire main_a7ddrphy_dq_oe; +wire main_a7ddrphy_dq_oe_delay_tappeddelayline; +reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +wire main_a7ddrphy_dq_t0; +wire main_a7ddrphy_dq_t1; +wire main_a7ddrphy_dq_t10; +wire main_a7ddrphy_dq_t11; +wire main_a7ddrphy_dq_t12; +wire main_a7ddrphy_dq_t13; +wire main_a7ddrphy_dq_t14; +wire main_a7ddrphy_dq_t15; +wire main_a7ddrphy_dq_t2; +wire main_a7ddrphy_dq_t3; +wire main_a7ddrphy_dq_t4; +wire main_a7ddrphy_dq_t5; +wire main_a7ddrphy_dq_t6; +wire main_a7ddrphy_dq_t7; +wire main_a7ddrphy_dq_t8; +wire main_a7ddrphy_dq_t9; +wire main_a7ddrphy_dqs_o_no_delay0; +wire main_a7ddrphy_dqs_o_no_delay1; +reg main_a7ddrphy_dqs_oe = 1'd0; +wire main_a7ddrphy_dqs_oe_delay_tappeddelayline; +reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +wire main_a7ddrphy_dqs_postamble; +wire main_a7ddrphy_dqs_preamble; +wire main_a7ddrphy_dqs_t0; +wire main_a7ddrphy_dqs_t1; +reg main_a7ddrphy_dqspattern0 = 1'd0; +reg main_a7ddrphy_dqspattern1 = 1'd0; +reg [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0; +reg [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0; +reg main_a7ddrphy_half_sys8x_taps_re = 1'd0; +reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8; +wire [2:0] main_a7ddrphy_pads_ba; +reg main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; +wire main_a7ddrphy_rdly_dq_bitslip_r; +reg main_a7ddrphy_rdly_dq_bitslip_re = 1'd0; +wire main_a7ddrphy_rdly_dq_bitslip_rst_r; +reg main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_w = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_we = 1'd0; +wire main_a7ddrphy_rdly_dq_inc_r; +reg main_a7ddrphy_rdly_dq_inc_re = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_w = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_we = 1'd0; +wire main_a7ddrphy_rdly_dq_rst_r; +reg main_a7ddrphy_rdly_dq_rst_re = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_w = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_we = 1'd0; +reg main_a7ddrphy_rdphase_re = 1'd0; +reg [1:0] main_a7ddrphy_rdphase_storage = 2'd2; +reg main_a7ddrphy_rst_re = 1'd0; +reg main_a7ddrphy_rst_storage = 1'd0; +wire main_a7ddrphy_sd_clk_se_nodelay; +wire main_a7ddrphy_wdly_dq_bitslip_r; +reg main_a7ddrphy_wdly_dq_bitslip_re = 1'd0; +wire main_a7ddrphy_wdly_dq_bitslip_rst_r; +reg main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_w = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_we = 1'd0; +reg main_a7ddrphy_wlevel_en_re = 1'd0; +reg main_a7ddrphy_wlevel_en_storage = 1'd0; +wire main_a7ddrphy_wlevel_strobe_r; +reg main_a7ddrphy_wlevel_strobe_re = 1'd0; +reg main_a7ddrphy_wlevel_strobe_w = 1'd0; +reg main_a7ddrphy_wlevel_strobe_we = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +reg main_a7ddrphy_wrphase_re = 1'd0; +reg [1:0] main_a7ddrphy_wrphase_storage = 2'd3; +wire main_clkin; +wire main_clkout0; +wire main_clkout1; +wire main_clkout2; +wire main_clkout3; +wire main_clkout_buf0; +wire main_clkout_buf1; +wire main_clkout_buf2; +wire main_clkout_buf3; +reg main_ic_reset = 1'd1; +reg main_init_done_re = 1'd0; +reg main_init_done_storage = 1'd0; +reg main_init_error_re = 1'd0; +reg main_init_error_storage = 1'd0; +reg main_litedramcore_bankmachine0_auto_precharge = 1'd0; +reg [14:0] main_litedramcore_bankmachine0_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba; +reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine0_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine0_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine0_consume = 4'd0; +wire main_litedramcore_bankmachine0_do_read; +wire main_litedramcore_bankmachine0_fifo_in_first; +wire main_litedramcore_bankmachine0_fifo_in_last; +wire [21:0] main_litedramcore_bankmachine0_fifo_in_payload_addr; +wire main_litedramcore_bankmachine0_fifo_in_payload_we; +wire main_litedramcore_bankmachine0_fifo_out_first; +wire main_litedramcore_bankmachine0_fifo_out_last; +wire [21:0] main_litedramcore_bankmachine0_fifo_out_payload_addr; +wire main_litedramcore_bankmachine0_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine0_level = 5'd0; +wire main_litedramcore_bankmachine0_pipe_valid_sink_first; +wire main_litedramcore_bankmachine0_pipe_valid_sink_last; +wire [21:0] main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine0_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine0_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine0_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine0_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine0_pipe_valid_source_last = 1'd0; +reg [21:0] main_litedramcore_bankmachine0_pipe_valid_source_payload_addr = 22'd0; +reg main_litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine0_pipe_valid_source_ready; +reg main_litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine0_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine0_rdport_adr; +wire [24:0] main_litedramcore_bankmachine0_rdport_dat_r; +reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine0_refresh_req; +reg main_litedramcore_bankmachine0_replace = 1'd0; +wire [21:0] main_litedramcore_bankmachine0_req_addr; +wire main_litedramcore_bankmachine0_req_lock; +reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine0_req_ready; +wire main_litedramcore_bankmachine0_req_valid; +reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine0_req_we; +reg [14:0] main_litedramcore_bankmachine0_row = 15'd0; +reg main_litedramcore_bankmachine0_row_close = 1'd0; +reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine0_row_hit; +reg main_litedramcore_bankmachine0_row_open = 1'd0; +reg main_litedramcore_bankmachine0_row_opened = 1'd0; +reg main_litedramcore_bankmachine0_sink_first = 1'd0; +reg main_litedramcore_bankmachine0_sink_last = 1'd0; +wire [21:0] main_litedramcore_bankmachine0_sink_payload_addr; +wire main_litedramcore_bankmachine0_sink_payload_we; +wire main_litedramcore_bankmachine0_sink_ready; +wire main_litedramcore_bankmachine0_sink_sink_first; +wire main_litedramcore_bankmachine0_sink_sink_last; +wire [21:0] main_litedramcore_bankmachine0_sink_sink_payload_addr; +wire main_litedramcore_bankmachine0_sink_sink_payload_we; +wire main_litedramcore_bankmachine0_sink_sink_ready; +wire main_litedramcore_bankmachine0_sink_sink_valid; +wire main_litedramcore_bankmachine0_sink_valid; +wire main_litedramcore_bankmachine0_source_first; +wire main_litedramcore_bankmachine0_source_last; +wire [21:0] main_litedramcore_bankmachine0_source_payload_addr; +wire main_litedramcore_bankmachine0_source_payload_we; +wire main_litedramcore_bankmachine0_source_ready; +wire main_litedramcore_bankmachine0_source_source_first; +wire main_litedramcore_bankmachine0_source_source_last; +wire [21:0] main_litedramcore_bankmachine0_source_source_payload_addr; +wire main_litedramcore_bankmachine0_source_source_payload_we; +wire main_litedramcore_bankmachine0_source_source_ready; +wire main_litedramcore_bankmachine0_source_source_valid; +wire main_litedramcore_bankmachine0_source_valid; +wire [24:0] main_litedramcore_bankmachine0_syncfifo0_din; +wire [24:0] main_litedramcore_bankmachine0_syncfifo0_dout; +wire main_litedramcore_bankmachine0_syncfifo0_re; +wire main_litedramcore_bankmachine0_syncfifo0_readable; +wire main_litedramcore_bankmachine0_syncfifo0_we; +wire main_litedramcore_bankmachine0_syncfifo0_writable; +reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; -wire litedramcore_bankmachine0_trccon_valid; +reg main_litedramcore_bankmachine0_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine0_trascon_valid; +reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0; -wire litedramcore_bankmachine0_trascon_valid; +reg main_litedramcore_bankmachine0_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine0_trccon_valid; +reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine0_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0; -wire litedramcore_bankmachine1_req_valid; -wire litedramcore_bankmachine1_req_ready; -wire litedramcore_bankmachine1_req_we; -wire [21:0] litedramcore_bankmachine1_req_addr; -wire litedramcore_bankmachine1_req_lock; -reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine1_refresh_req; -reg litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg litedramcore_bankmachine1_cmd_valid = 1'd0; -reg litedramcore_bankmachine1_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; -reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine1_auto_precharge = 1'd0; -wire litedramcore_bankmachine1_sink_valid; -wire litedramcore_bankmachine1_sink_ready; -reg litedramcore_bankmachine1_sink_first = 1'd0; -reg litedramcore_bankmachine1_sink_last = 1'd0; -wire litedramcore_bankmachine1_sink_payload_we; -wire [21:0] litedramcore_bankmachine1_sink_payload_addr; -wire litedramcore_bankmachine1_source_valid; -wire litedramcore_bankmachine1_source_ready; -wire litedramcore_bankmachine1_source_first; -wire litedramcore_bankmachine1_source_last; -wire litedramcore_bankmachine1_source_payload_we; -wire [21:0] litedramcore_bankmachine1_source_payload_addr; -wire litedramcore_bankmachine1_syncfifo1_we; -wire litedramcore_bankmachine1_syncfifo1_writable; -wire litedramcore_bankmachine1_syncfifo1_re; -wire litedramcore_bankmachine1_syncfifo1_readable; -wire [24:0] litedramcore_bankmachine1_syncfifo1_din; -wire [24:0] litedramcore_bankmachine1_syncfifo1_dout; -reg [4:0] litedramcore_bankmachine1_level = 5'd0; -reg litedramcore_bankmachine1_replace = 1'd0; -reg [3:0] litedramcore_bankmachine1_produce = 4'd0; -reg [3:0] litedramcore_bankmachine1_consume = 4'd0; -reg [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine1_wrport_dat_r; -wire litedramcore_bankmachine1_wrport_we; -wire [24:0] litedramcore_bankmachine1_wrport_dat_w; -wire litedramcore_bankmachine1_do_read; -wire [3:0] litedramcore_bankmachine1_rdport_adr; -wire [24:0] litedramcore_bankmachine1_rdport_dat_r; -wire litedramcore_bankmachine1_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine1_fifo_in_payload_addr; -wire litedramcore_bankmachine1_fifo_in_first; -wire litedramcore_bankmachine1_fifo_in_last; -wire litedramcore_bankmachine1_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine1_fifo_out_payload_addr; -wire litedramcore_bankmachine1_fifo_out_first; -wire litedramcore_bankmachine1_fifo_out_last; -wire litedramcore_bankmachine1_sink_sink_valid; -wire litedramcore_bankmachine1_sink_sink_ready; -wire litedramcore_bankmachine1_sink_sink_first; -wire litedramcore_bankmachine1_sink_sink_last; -wire litedramcore_bankmachine1_sink_sink_payload_we; -wire [21:0] litedramcore_bankmachine1_sink_sink_payload_addr; -wire litedramcore_bankmachine1_source_source_valid; -wire litedramcore_bankmachine1_source_source_ready; -wire litedramcore_bankmachine1_source_source_first; -wire litedramcore_bankmachine1_source_source_last; -wire litedramcore_bankmachine1_source_source_payload_we; -wire [21:0] litedramcore_bankmachine1_source_source_payload_addr; -wire litedramcore_bankmachine1_pipe_valid_sink_valid; -wire litedramcore_bankmachine1_pipe_valid_sink_ready; -wire litedramcore_bankmachine1_pipe_valid_sink_first; -wire litedramcore_bankmachine1_pipe_valid_sink_last; -wire litedramcore_bankmachine1_pipe_valid_sink_payload_we; -wire [21:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine1_pipe_valid_source_ready; -reg litedramcore_bankmachine1_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine1_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine1_row = 15'd0; -reg litedramcore_bankmachine1_row_opened = 1'd0; -wire litedramcore_bankmachine1_row_hit; -reg litedramcore_bankmachine1_row_open = 1'd0; -reg litedramcore_bankmachine1_row_close = 1'd0; -reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine1_twtpcon_valid; +reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine0_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine0_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine0_wrport_dat_r; +wire [24:0] main_litedramcore_bankmachine0_wrport_dat_w; +wire main_litedramcore_bankmachine0_wrport_we; +reg main_litedramcore_bankmachine1_auto_precharge = 1'd0; +reg [14:0] main_litedramcore_bankmachine1_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba; +reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine1_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine1_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine1_consume = 4'd0; +wire main_litedramcore_bankmachine1_do_read; +wire main_litedramcore_bankmachine1_fifo_in_first; +wire main_litedramcore_bankmachine1_fifo_in_last; +wire [21:0] main_litedramcore_bankmachine1_fifo_in_payload_addr; +wire main_litedramcore_bankmachine1_fifo_in_payload_we; +wire main_litedramcore_bankmachine1_fifo_out_first; +wire main_litedramcore_bankmachine1_fifo_out_last; +wire [21:0] main_litedramcore_bankmachine1_fifo_out_payload_addr; +wire main_litedramcore_bankmachine1_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine1_level = 5'd0; +wire main_litedramcore_bankmachine1_pipe_valid_sink_first; +wire main_litedramcore_bankmachine1_pipe_valid_sink_last; +wire [21:0] main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine1_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine1_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine1_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine1_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine1_pipe_valid_source_last = 1'd0; +reg [21:0] main_litedramcore_bankmachine1_pipe_valid_source_payload_addr = 22'd0; +reg main_litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine1_pipe_valid_source_ready; +reg main_litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine1_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine1_rdport_adr; +wire [24:0] main_litedramcore_bankmachine1_rdport_dat_r; +reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine1_refresh_req; +reg main_litedramcore_bankmachine1_replace = 1'd0; +wire [21:0] main_litedramcore_bankmachine1_req_addr; +wire main_litedramcore_bankmachine1_req_lock; +reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine1_req_ready; +wire main_litedramcore_bankmachine1_req_valid; +reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine1_req_we; +reg [14:0] main_litedramcore_bankmachine1_row = 15'd0; +reg main_litedramcore_bankmachine1_row_close = 1'd0; +reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine1_row_hit; +reg main_litedramcore_bankmachine1_row_open = 1'd0; +reg main_litedramcore_bankmachine1_row_opened = 1'd0; +reg main_litedramcore_bankmachine1_sink_first = 1'd0; +reg main_litedramcore_bankmachine1_sink_last = 1'd0; +wire [21:0] main_litedramcore_bankmachine1_sink_payload_addr; +wire main_litedramcore_bankmachine1_sink_payload_we; +wire main_litedramcore_bankmachine1_sink_ready; +wire main_litedramcore_bankmachine1_sink_sink_first; +wire main_litedramcore_bankmachine1_sink_sink_last; +wire [21:0] main_litedramcore_bankmachine1_sink_sink_payload_addr; +wire main_litedramcore_bankmachine1_sink_sink_payload_we; +wire main_litedramcore_bankmachine1_sink_sink_ready; +wire main_litedramcore_bankmachine1_sink_sink_valid; +wire main_litedramcore_bankmachine1_sink_valid; +wire main_litedramcore_bankmachine1_source_first; +wire main_litedramcore_bankmachine1_source_last; +wire [21:0] main_litedramcore_bankmachine1_source_payload_addr; +wire main_litedramcore_bankmachine1_source_payload_we; +wire main_litedramcore_bankmachine1_source_ready; +wire main_litedramcore_bankmachine1_source_source_first; +wire main_litedramcore_bankmachine1_source_source_last; +wire [21:0] main_litedramcore_bankmachine1_source_source_payload_addr; +wire main_litedramcore_bankmachine1_source_source_payload_we; +wire main_litedramcore_bankmachine1_source_source_ready; +wire main_litedramcore_bankmachine1_source_source_valid; +wire main_litedramcore_bankmachine1_source_valid; +wire [24:0] main_litedramcore_bankmachine1_syncfifo1_din; +wire [24:0] main_litedramcore_bankmachine1_syncfifo1_dout; +wire main_litedramcore_bankmachine1_syncfifo1_re; +wire main_litedramcore_bankmachine1_syncfifo1_readable; +wire main_litedramcore_bankmachine1_syncfifo1_we; +wire main_litedramcore_bankmachine1_syncfifo1_writable; +reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; -wire litedramcore_bankmachine1_trccon_valid; +reg main_litedramcore_bankmachine1_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine1_trascon_valid; +reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0; -wire litedramcore_bankmachine1_trascon_valid; +reg main_litedramcore_bankmachine1_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine1_trccon_valid; +reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine1_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0; -wire litedramcore_bankmachine2_req_valid; -wire litedramcore_bankmachine2_req_ready; -wire litedramcore_bankmachine2_req_we; -wire [21:0] litedramcore_bankmachine2_req_addr; -wire litedramcore_bankmachine2_req_lock; -reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine2_refresh_req; -reg litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg litedramcore_bankmachine2_cmd_valid = 1'd0; -reg litedramcore_bankmachine2_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; -reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine2_auto_precharge = 1'd0; -wire litedramcore_bankmachine2_sink_valid; -wire litedramcore_bankmachine2_sink_ready; -reg litedramcore_bankmachine2_sink_first = 1'd0; -reg litedramcore_bankmachine2_sink_last = 1'd0; -wire litedramcore_bankmachine2_sink_payload_we; -wire [21:0] litedramcore_bankmachine2_sink_payload_addr; -wire litedramcore_bankmachine2_source_valid; -wire litedramcore_bankmachine2_source_ready; -wire litedramcore_bankmachine2_source_first; -wire litedramcore_bankmachine2_source_last; -wire litedramcore_bankmachine2_source_payload_we; -wire [21:0] litedramcore_bankmachine2_source_payload_addr; -wire litedramcore_bankmachine2_syncfifo2_we; -wire litedramcore_bankmachine2_syncfifo2_writable; -wire litedramcore_bankmachine2_syncfifo2_re; -wire litedramcore_bankmachine2_syncfifo2_readable; -wire [24:0] litedramcore_bankmachine2_syncfifo2_din; -wire [24:0] litedramcore_bankmachine2_syncfifo2_dout; -reg [4:0] litedramcore_bankmachine2_level = 5'd0; -reg litedramcore_bankmachine2_replace = 1'd0; -reg [3:0] litedramcore_bankmachine2_produce = 4'd0; -reg [3:0] litedramcore_bankmachine2_consume = 4'd0; -reg [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine2_wrport_dat_r; -wire litedramcore_bankmachine2_wrport_we; -wire [24:0] litedramcore_bankmachine2_wrport_dat_w; -wire litedramcore_bankmachine2_do_read; -wire [3:0] litedramcore_bankmachine2_rdport_adr; -wire [24:0] litedramcore_bankmachine2_rdport_dat_r; -wire litedramcore_bankmachine2_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine2_fifo_in_payload_addr; -wire litedramcore_bankmachine2_fifo_in_first; -wire litedramcore_bankmachine2_fifo_in_last; -wire litedramcore_bankmachine2_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine2_fifo_out_payload_addr; -wire litedramcore_bankmachine2_fifo_out_first; -wire litedramcore_bankmachine2_fifo_out_last; -wire litedramcore_bankmachine2_sink_sink_valid; -wire litedramcore_bankmachine2_sink_sink_ready; -wire litedramcore_bankmachine2_sink_sink_first; -wire litedramcore_bankmachine2_sink_sink_last; -wire litedramcore_bankmachine2_sink_sink_payload_we; -wire [21:0] litedramcore_bankmachine2_sink_sink_payload_addr; -wire litedramcore_bankmachine2_source_source_valid; -wire litedramcore_bankmachine2_source_source_ready; -wire litedramcore_bankmachine2_source_source_first; -wire litedramcore_bankmachine2_source_source_last; -wire litedramcore_bankmachine2_source_source_payload_we; -wire [21:0] litedramcore_bankmachine2_source_source_payload_addr; -wire litedramcore_bankmachine2_pipe_valid_sink_valid; -wire litedramcore_bankmachine2_pipe_valid_sink_ready; -wire litedramcore_bankmachine2_pipe_valid_sink_first; -wire litedramcore_bankmachine2_pipe_valid_sink_last; -wire litedramcore_bankmachine2_pipe_valid_sink_payload_we; -wire [21:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine2_pipe_valid_source_ready; -reg litedramcore_bankmachine2_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine2_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine2_row = 15'd0; -reg litedramcore_bankmachine2_row_opened = 1'd0; -wire litedramcore_bankmachine2_row_hit; -reg litedramcore_bankmachine2_row_open = 1'd0; -reg litedramcore_bankmachine2_row_close = 1'd0; -reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine2_twtpcon_valid; +reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine1_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine1_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine1_wrport_dat_r; +wire [24:0] main_litedramcore_bankmachine1_wrport_dat_w; +wire main_litedramcore_bankmachine1_wrport_we; +reg main_litedramcore_bankmachine2_auto_precharge = 1'd0; +reg [14:0] main_litedramcore_bankmachine2_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba; +reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine2_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine2_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine2_consume = 4'd0; +wire main_litedramcore_bankmachine2_do_read; +wire main_litedramcore_bankmachine2_fifo_in_first; +wire main_litedramcore_bankmachine2_fifo_in_last; +wire [21:0] main_litedramcore_bankmachine2_fifo_in_payload_addr; +wire main_litedramcore_bankmachine2_fifo_in_payload_we; +wire main_litedramcore_bankmachine2_fifo_out_first; +wire main_litedramcore_bankmachine2_fifo_out_last; +wire [21:0] main_litedramcore_bankmachine2_fifo_out_payload_addr; +wire main_litedramcore_bankmachine2_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine2_level = 5'd0; +wire main_litedramcore_bankmachine2_pipe_valid_sink_first; +wire main_litedramcore_bankmachine2_pipe_valid_sink_last; +wire [21:0] main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine2_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine2_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine2_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine2_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine2_pipe_valid_source_last = 1'd0; +reg [21:0] main_litedramcore_bankmachine2_pipe_valid_source_payload_addr = 22'd0; +reg main_litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine2_pipe_valid_source_ready; +reg main_litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine2_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine2_rdport_adr; +wire [24:0] main_litedramcore_bankmachine2_rdport_dat_r; +reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine2_refresh_req; +reg main_litedramcore_bankmachine2_replace = 1'd0; +wire [21:0] main_litedramcore_bankmachine2_req_addr; +wire main_litedramcore_bankmachine2_req_lock; +reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine2_req_ready; +wire main_litedramcore_bankmachine2_req_valid; +reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine2_req_we; +reg [14:0] main_litedramcore_bankmachine2_row = 15'd0; +reg main_litedramcore_bankmachine2_row_close = 1'd0; +reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine2_row_hit; +reg main_litedramcore_bankmachine2_row_open = 1'd0; +reg main_litedramcore_bankmachine2_row_opened = 1'd0; +reg main_litedramcore_bankmachine2_sink_first = 1'd0; +reg main_litedramcore_bankmachine2_sink_last = 1'd0; +wire [21:0] main_litedramcore_bankmachine2_sink_payload_addr; +wire main_litedramcore_bankmachine2_sink_payload_we; +wire main_litedramcore_bankmachine2_sink_ready; +wire main_litedramcore_bankmachine2_sink_sink_first; +wire main_litedramcore_bankmachine2_sink_sink_last; +wire [21:0] main_litedramcore_bankmachine2_sink_sink_payload_addr; +wire main_litedramcore_bankmachine2_sink_sink_payload_we; +wire main_litedramcore_bankmachine2_sink_sink_ready; +wire main_litedramcore_bankmachine2_sink_sink_valid; +wire main_litedramcore_bankmachine2_sink_valid; +wire main_litedramcore_bankmachine2_source_first; +wire main_litedramcore_bankmachine2_source_last; +wire [21:0] main_litedramcore_bankmachine2_source_payload_addr; +wire main_litedramcore_bankmachine2_source_payload_we; +wire main_litedramcore_bankmachine2_source_ready; +wire main_litedramcore_bankmachine2_source_source_first; +wire main_litedramcore_bankmachine2_source_source_last; +wire [21:0] main_litedramcore_bankmachine2_source_source_payload_addr; +wire main_litedramcore_bankmachine2_source_source_payload_we; +wire main_litedramcore_bankmachine2_source_source_ready; +wire main_litedramcore_bankmachine2_source_source_valid; +wire main_litedramcore_bankmachine2_source_valid; +wire [24:0] main_litedramcore_bankmachine2_syncfifo2_din; +wire [24:0] main_litedramcore_bankmachine2_syncfifo2_dout; +wire main_litedramcore_bankmachine2_syncfifo2_re; +wire main_litedramcore_bankmachine2_syncfifo2_readable; +wire main_litedramcore_bankmachine2_syncfifo2_we; +wire main_litedramcore_bankmachine2_syncfifo2_writable; +reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; -wire litedramcore_bankmachine2_trccon_valid; +reg main_litedramcore_bankmachine2_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine2_trascon_valid; +reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0; -wire litedramcore_bankmachine2_trascon_valid; +reg main_litedramcore_bankmachine2_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine2_trccon_valid; +reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine2_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0; -wire litedramcore_bankmachine3_req_valid; -wire litedramcore_bankmachine3_req_ready; -wire litedramcore_bankmachine3_req_we; -wire [21:0] litedramcore_bankmachine3_req_addr; -wire litedramcore_bankmachine3_req_lock; -reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine3_refresh_req; -reg litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg litedramcore_bankmachine3_cmd_valid = 1'd0; -reg litedramcore_bankmachine3_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; -reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine3_auto_precharge = 1'd0; -wire litedramcore_bankmachine3_sink_valid; -wire litedramcore_bankmachine3_sink_ready; -reg litedramcore_bankmachine3_sink_first = 1'd0; -reg litedramcore_bankmachine3_sink_last = 1'd0; -wire litedramcore_bankmachine3_sink_payload_we; -wire [21:0] litedramcore_bankmachine3_sink_payload_addr; -wire litedramcore_bankmachine3_source_valid; -wire litedramcore_bankmachine3_source_ready; -wire litedramcore_bankmachine3_source_first; -wire litedramcore_bankmachine3_source_last; -wire litedramcore_bankmachine3_source_payload_we; -wire [21:0] litedramcore_bankmachine3_source_payload_addr; -wire litedramcore_bankmachine3_syncfifo3_we; -wire litedramcore_bankmachine3_syncfifo3_writable; -wire litedramcore_bankmachine3_syncfifo3_re; -wire litedramcore_bankmachine3_syncfifo3_readable; -wire [24:0] litedramcore_bankmachine3_syncfifo3_din; -wire [24:0] litedramcore_bankmachine3_syncfifo3_dout; -reg [4:0] litedramcore_bankmachine3_level = 5'd0; -reg litedramcore_bankmachine3_replace = 1'd0; -reg [3:0] litedramcore_bankmachine3_produce = 4'd0; -reg [3:0] litedramcore_bankmachine3_consume = 4'd0; -reg [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine3_wrport_dat_r; -wire litedramcore_bankmachine3_wrport_we; -wire [24:0] litedramcore_bankmachine3_wrport_dat_w; -wire litedramcore_bankmachine3_do_read; -wire [3:0] litedramcore_bankmachine3_rdport_adr; -wire [24:0] litedramcore_bankmachine3_rdport_dat_r; -wire litedramcore_bankmachine3_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine3_fifo_in_payload_addr; -wire litedramcore_bankmachine3_fifo_in_first; -wire litedramcore_bankmachine3_fifo_in_last; -wire litedramcore_bankmachine3_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine3_fifo_out_payload_addr; -wire litedramcore_bankmachine3_fifo_out_first; -wire litedramcore_bankmachine3_fifo_out_last; -wire litedramcore_bankmachine3_sink_sink_valid; -wire litedramcore_bankmachine3_sink_sink_ready; -wire litedramcore_bankmachine3_sink_sink_first; -wire litedramcore_bankmachine3_sink_sink_last; -wire litedramcore_bankmachine3_sink_sink_payload_we; -wire [21:0] litedramcore_bankmachine3_sink_sink_payload_addr; -wire litedramcore_bankmachine3_source_source_valid; -wire litedramcore_bankmachine3_source_source_ready; -wire litedramcore_bankmachine3_source_source_first; -wire litedramcore_bankmachine3_source_source_last; -wire litedramcore_bankmachine3_source_source_payload_we; -wire [21:0] litedramcore_bankmachine3_source_source_payload_addr; -wire litedramcore_bankmachine3_pipe_valid_sink_valid; -wire litedramcore_bankmachine3_pipe_valid_sink_ready; -wire litedramcore_bankmachine3_pipe_valid_sink_first; -wire litedramcore_bankmachine3_pipe_valid_sink_last; -wire litedramcore_bankmachine3_pipe_valid_sink_payload_we; -wire [21:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine3_pipe_valid_source_ready; -reg litedramcore_bankmachine3_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine3_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine3_row = 15'd0; -reg litedramcore_bankmachine3_row_opened = 1'd0; -wire litedramcore_bankmachine3_row_hit; -reg litedramcore_bankmachine3_row_open = 1'd0; -reg litedramcore_bankmachine3_row_close = 1'd0; -reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine3_twtpcon_valid; +reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine2_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine2_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine2_wrport_dat_r; +wire [24:0] main_litedramcore_bankmachine2_wrport_dat_w; +wire main_litedramcore_bankmachine2_wrport_we; +reg main_litedramcore_bankmachine3_auto_precharge = 1'd0; +reg [14:0] main_litedramcore_bankmachine3_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba; +reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine3_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine3_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine3_consume = 4'd0; +wire main_litedramcore_bankmachine3_do_read; +wire main_litedramcore_bankmachine3_fifo_in_first; +wire main_litedramcore_bankmachine3_fifo_in_last; +wire [21:0] main_litedramcore_bankmachine3_fifo_in_payload_addr; +wire main_litedramcore_bankmachine3_fifo_in_payload_we; +wire main_litedramcore_bankmachine3_fifo_out_first; +wire main_litedramcore_bankmachine3_fifo_out_last; +wire [21:0] main_litedramcore_bankmachine3_fifo_out_payload_addr; +wire main_litedramcore_bankmachine3_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine3_level = 5'd0; +wire main_litedramcore_bankmachine3_pipe_valid_sink_first; +wire main_litedramcore_bankmachine3_pipe_valid_sink_last; +wire [21:0] main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine3_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine3_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine3_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine3_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine3_pipe_valid_source_last = 1'd0; +reg [21:0] main_litedramcore_bankmachine3_pipe_valid_source_payload_addr = 22'd0; +reg main_litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine3_pipe_valid_source_ready; +reg main_litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine3_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine3_rdport_adr; +wire [24:0] main_litedramcore_bankmachine3_rdport_dat_r; +reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine3_refresh_req; +reg main_litedramcore_bankmachine3_replace = 1'd0; +wire [21:0] main_litedramcore_bankmachine3_req_addr; +wire main_litedramcore_bankmachine3_req_lock; +reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine3_req_ready; +wire main_litedramcore_bankmachine3_req_valid; +reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine3_req_we; +reg [14:0] main_litedramcore_bankmachine3_row = 15'd0; +reg main_litedramcore_bankmachine3_row_close = 1'd0; +reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine3_row_hit; +reg main_litedramcore_bankmachine3_row_open = 1'd0; +reg main_litedramcore_bankmachine3_row_opened = 1'd0; +reg main_litedramcore_bankmachine3_sink_first = 1'd0; +reg main_litedramcore_bankmachine3_sink_last = 1'd0; +wire [21:0] main_litedramcore_bankmachine3_sink_payload_addr; +wire main_litedramcore_bankmachine3_sink_payload_we; +wire main_litedramcore_bankmachine3_sink_ready; +wire main_litedramcore_bankmachine3_sink_sink_first; +wire main_litedramcore_bankmachine3_sink_sink_last; +wire [21:0] main_litedramcore_bankmachine3_sink_sink_payload_addr; +wire main_litedramcore_bankmachine3_sink_sink_payload_we; +wire main_litedramcore_bankmachine3_sink_sink_ready; +wire main_litedramcore_bankmachine3_sink_sink_valid; +wire main_litedramcore_bankmachine3_sink_valid; +wire main_litedramcore_bankmachine3_source_first; +wire main_litedramcore_bankmachine3_source_last; +wire [21:0] main_litedramcore_bankmachine3_source_payload_addr; +wire main_litedramcore_bankmachine3_source_payload_we; +wire main_litedramcore_bankmachine3_source_ready; +wire main_litedramcore_bankmachine3_source_source_first; +wire main_litedramcore_bankmachine3_source_source_last; +wire [21:0] main_litedramcore_bankmachine3_source_source_payload_addr; +wire main_litedramcore_bankmachine3_source_source_payload_we; +wire main_litedramcore_bankmachine3_source_source_ready; +wire main_litedramcore_bankmachine3_source_source_valid; +wire main_litedramcore_bankmachine3_source_valid; +wire [24:0] main_litedramcore_bankmachine3_syncfifo3_din; +wire [24:0] main_litedramcore_bankmachine3_syncfifo3_dout; +wire main_litedramcore_bankmachine3_syncfifo3_re; +wire main_litedramcore_bankmachine3_syncfifo3_readable; +wire main_litedramcore_bankmachine3_syncfifo3_we; +wire main_litedramcore_bankmachine3_syncfifo3_writable; +reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; -wire litedramcore_bankmachine3_trccon_valid; +reg main_litedramcore_bankmachine3_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine3_trascon_valid; +reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0; -wire litedramcore_bankmachine3_trascon_valid; +reg main_litedramcore_bankmachine3_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine3_trccon_valid; +reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine3_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0; -wire litedramcore_bankmachine4_req_valid; -wire litedramcore_bankmachine4_req_ready; -wire litedramcore_bankmachine4_req_we; -wire [21:0] litedramcore_bankmachine4_req_addr; -wire litedramcore_bankmachine4_req_lock; -reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine4_refresh_req; -reg litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg litedramcore_bankmachine4_cmd_valid = 1'd0; -reg litedramcore_bankmachine4_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; -reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine4_auto_precharge = 1'd0; -wire litedramcore_bankmachine4_sink_valid; -wire litedramcore_bankmachine4_sink_ready; -reg litedramcore_bankmachine4_sink_first = 1'd0; -reg litedramcore_bankmachine4_sink_last = 1'd0; -wire litedramcore_bankmachine4_sink_payload_we; -wire [21:0] litedramcore_bankmachine4_sink_payload_addr; -wire litedramcore_bankmachine4_source_valid; -wire litedramcore_bankmachine4_source_ready; -wire litedramcore_bankmachine4_source_first; -wire litedramcore_bankmachine4_source_last; -wire litedramcore_bankmachine4_source_payload_we; -wire [21:0] litedramcore_bankmachine4_source_payload_addr; -wire litedramcore_bankmachine4_syncfifo4_we; -wire litedramcore_bankmachine4_syncfifo4_writable; -wire litedramcore_bankmachine4_syncfifo4_re; -wire litedramcore_bankmachine4_syncfifo4_readable; -wire [24:0] litedramcore_bankmachine4_syncfifo4_din; -wire [24:0] litedramcore_bankmachine4_syncfifo4_dout; -reg [4:0] litedramcore_bankmachine4_level = 5'd0; -reg litedramcore_bankmachine4_replace = 1'd0; -reg [3:0] litedramcore_bankmachine4_produce = 4'd0; -reg [3:0] litedramcore_bankmachine4_consume = 4'd0; -reg [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine4_wrport_dat_r; -wire litedramcore_bankmachine4_wrport_we; -wire [24:0] litedramcore_bankmachine4_wrport_dat_w; -wire litedramcore_bankmachine4_do_read; -wire [3:0] litedramcore_bankmachine4_rdport_adr; -wire [24:0] litedramcore_bankmachine4_rdport_dat_r; -wire litedramcore_bankmachine4_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine4_fifo_in_payload_addr; -wire litedramcore_bankmachine4_fifo_in_first; -wire litedramcore_bankmachine4_fifo_in_last; -wire litedramcore_bankmachine4_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine4_fifo_out_payload_addr; -wire litedramcore_bankmachine4_fifo_out_first; -wire litedramcore_bankmachine4_fifo_out_last; -wire litedramcore_bankmachine4_sink_sink_valid; -wire litedramcore_bankmachine4_sink_sink_ready; -wire litedramcore_bankmachine4_sink_sink_first; -wire litedramcore_bankmachine4_sink_sink_last; -wire litedramcore_bankmachine4_sink_sink_payload_we; -wire [21:0] litedramcore_bankmachine4_sink_sink_payload_addr; -wire litedramcore_bankmachine4_source_source_valid; -wire litedramcore_bankmachine4_source_source_ready; -wire litedramcore_bankmachine4_source_source_first; -wire litedramcore_bankmachine4_source_source_last; -wire litedramcore_bankmachine4_source_source_payload_we; -wire [21:0] litedramcore_bankmachine4_source_source_payload_addr; -wire litedramcore_bankmachine4_pipe_valid_sink_valid; -wire litedramcore_bankmachine4_pipe_valid_sink_ready; -wire litedramcore_bankmachine4_pipe_valid_sink_first; -wire litedramcore_bankmachine4_pipe_valid_sink_last; -wire litedramcore_bankmachine4_pipe_valid_sink_payload_we; -wire [21:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine4_pipe_valid_source_ready; -reg litedramcore_bankmachine4_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine4_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine4_row = 15'd0; -reg litedramcore_bankmachine4_row_opened = 1'd0; -wire litedramcore_bankmachine4_row_hit; -reg litedramcore_bankmachine4_row_open = 1'd0; -reg litedramcore_bankmachine4_row_close = 1'd0; -reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine4_twtpcon_valid; +reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine3_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine3_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine3_wrport_dat_r; +wire [24:0] main_litedramcore_bankmachine3_wrport_dat_w; +wire main_litedramcore_bankmachine3_wrport_we; +reg main_litedramcore_bankmachine4_auto_precharge = 1'd0; +reg [14:0] main_litedramcore_bankmachine4_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba; +reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine4_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine4_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine4_consume = 4'd0; +wire main_litedramcore_bankmachine4_do_read; +wire main_litedramcore_bankmachine4_fifo_in_first; +wire main_litedramcore_bankmachine4_fifo_in_last; +wire [21:0] main_litedramcore_bankmachine4_fifo_in_payload_addr; +wire main_litedramcore_bankmachine4_fifo_in_payload_we; +wire main_litedramcore_bankmachine4_fifo_out_first; +wire main_litedramcore_bankmachine4_fifo_out_last; +wire [21:0] main_litedramcore_bankmachine4_fifo_out_payload_addr; +wire main_litedramcore_bankmachine4_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine4_level = 5'd0; +wire main_litedramcore_bankmachine4_pipe_valid_sink_first; +wire main_litedramcore_bankmachine4_pipe_valid_sink_last; +wire [21:0] main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine4_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine4_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine4_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine4_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine4_pipe_valid_source_last = 1'd0; +reg [21:0] main_litedramcore_bankmachine4_pipe_valid_source_payload_addr = 22'd0; +reg main_litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine4_pipe_valid_source_ready; +reg main_litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine4_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine4_rdport_adr; +wire [24:0] main_litedramcore_bankmachine4_rdport_dat_r; +reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine4_refresh_req; +reg main_litedramcore_bankmachine4_replace = 1'd0; +wire [21:0] main_litedramcore_bankmachine4_req_addr; +wire main_litedramcore_bankmachine4_req_lock; +reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine4_req_ready; +wire main_litedramcore_bankmachine4_req_valid; +reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine4_req_we; +reg [14:0] main_litedramcore_bankmachine4_row = 15'd0; +reg main_litedramcore_bankmachine4_row_close = 1'd0; +reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine4_row_hit; +reg main_litedramcore_bankmachine4_row_open = 1'd0; +reg main_litedramcore_bankmachine4_row_opened = 1'd0; +reg main_litedramcore_bankmachine4_sink_first = 1'd0; +reg main_litedramcore_bankmachine4_sink_last = 1'd0; +wire [21:0] main_litedramcore_bankmachine4_sink_payload_addr; +wire main_litedramcore_bankmachine4_sink_payload_we; +wire main_litedramcore_bankmachine4_sink_ready; +wire main_litedramcore_bankmachine4_sink_sink_first; +wire main_litedramcore_bankmachine4_sink_sink_last; +wire [21:0] main_litedramcore_bankmachine4_sink_sink_payload_addr; +wire main_litedramcore_bankmachine4_sink_sink_payload_we; +wire main_litedramcore_bankmachine4_sink_sink_ready; +wire main_litedramcore_bankmachine4_sink_sink_valid; +wire main_litedramcore_bankmachine4_sink_valid; +wire main_litedramcore_bankmachine4_source_first; +wire main_litedramcore_bankmachine4_source_last; +wire [21:0] main_litedramcore_bankmachine4_source_payload_addr; +wire main_litedramcore_bankmachine4_source_payload_we; +wire main_litedramcore_bankmachine4_source_ready; +wire main_litedramcore_bankmachine4_source_source_first; +wire main_litedramcore_bankmachine4_source_source_last; +wire [21:0] main_litedramcore_bankmachine4_source_source_payload_addr; +wire main_litedramcore_bankmachine4_source_source_payload_we; +wire main_litedramcore_bankmachine4_source_source_ready; +wire main_litedramcore_bankmachine4_source_source_valid; +wire main_litedramcore_bankmachine4_source_valid; +wire [24:0] main_litedramcore_bankmachine4_syncfifo4_din; +wire [24:0] main_litedramcore_bankmachine4_syncfifo4_dout; +wire main_litedramcore_bankmachine4_syncfifo4_re; +wire main_litedramcore_bankmachine4_syncfifo4_readable; +wire main_litedramcore_bankmachine4_syncfifo4_we; +wire main_litedramcore_bankmachine4_syncfifo4_writable; +reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; -wire litedramcore_bankmachine4_trccon_valid; +reg main_litedramcore_bankmachine4_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine4_trascon_valid; +reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0; -wire litedramcore_bankmachine4_trascon_valid; +reg main_litedramcore_bankmachine4_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine4_trccon_valid; +reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine4_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0; -wire litedramcore_bankmachine5_req_valid; -wire litedramcore_bankmachine5_req_ready; -wire litedramcore_bankmachine5_req_we; -wire [21:0] litedramcore_bankmachine5_req_addr; -wire litedramcore_bankmachine5_req_lock; -reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine5_refresh_req; -reg litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg litedramcore_bankmachine5_cmd_valid = 1'd0; -reg litedramcore_bankmachine5_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; -reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine5_auto_precharge = 1'd0; -wire litedramcore_bankmachine5_sink_valid; -wire litedramcore_bankmachine5_sink_ready; -reg litedramcore_bankmachine5_sink_first = 1'd0; -reg litedramcore_bankmachine5_sink_last = 1'd0; -wire litedramcore_bankmachine5_sink_payload_we; -wire [21:0] litedramcore_bankmachine5_sink_payload_addr; -wire litedramcore_bankmachine5_source_valid; -wire litedramcore_bankmachine5_source_ready; -wire litedramcore_bankmachine5_source_first; -wire litedramcore_bankmachine5_source_last; -wire litedramcore_bankmachine5_source_payload_we; -wire [21:0] litedramcore_bankmachine5_source_payload_addr; -wire litedramcore_bankmachine5_syncfifo5_we; -wire litedramcore_bankmachine5_syncfifo5_writable; -wire litedramcore_bankmachine5_syncfifo5_re; -wire litedramcore_bankmachine5_syncfifo5_readable; -wire [24:0] litedramcore_bankmachine5_syncfifo5_din; -wire [24:0] litedramcore_bankmachine5_syncfifo5_dout; -reg [4:0] litedramcore_bankmachine5_level = 5'd0; -reg litedramcore_bankmachine5_replace = 1'd0; -reg [3:0] litedramcore_bankmachine5_produce = 4'd0; -reg [3:0] litedramcore_bankmachine5_consume = 4'd0; -reg [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine5_wrport_dat_r; -wire litedramcore_bankmachine5_wrport_we; -wire [24:0] litedramcore_bankmachine5_wrport_dat_w; -wire litedramcore_bankmachine5_do_read; -wire [3:0] litedramcore_bankmachine5_rdport_adr; -wire [24:0] litedramcore_bankmachine5_rdport_dat_r; -wire litedramcore_bankmachine5_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine5_fifo_in_payload_addr; -wire litedramcore_bankmachine5_fifo_in_first; -wire litedramcore_bankmachine5_fifo_in_last; -wire litedramcore_bankmachine5_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine5_fifo_out_payload_addr; -wire litedramcore_bankmachine5_fifo_out_first; -wire litedramcore_bankmachine5_fifo_out_last; -wire litedramcore_bankmachine5_sink_sink_valid; -wire litedramcore_bankmachine5_sink_sink_ready; -wire litedramcore_bankmachine5_sink_sink_first; -wire litedramcore_bankmachine5_sink_sink_last; -wire litedramcore_bankmachine5_sink_sink_payload_we; -wire [21:0] litedramcore_bankmachine5_sink_sink_payload_addr; -wire litedramcore_bankmachine5_source_source_valid; -wire litedramcore_bankmachine5_source_source_ready; -wire litedramcore_bankmachine5_source_source_first; -wire litedramcore_bankmachine5_source_source_last; -wire litedramcore_bankmachine5_source_source_payload_we; -wire [21:0] litedramcore_bankmachine5_source_source_payload_addr; -wire litedramcore_bankmachine5_pipe_valid_sink_valid; -wire litedramcore_bankmachine5_pipe_valid_sink_ready; -wire litedramcore_bankmachine5_pipe_valid_sink_first; -wire litedramcore_bankmachine5_pipe_valid_sink_last; -wire litedramcore_bankmachine5_pipe_valid_sink_payload_we; -wire [21:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine5_pipe_valid_source_ready; -reg litedramcore_bankmachine5_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine5_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine5_row = 15'd0; -reg litedramcore_bankmachine5_row_opened = 1'd0; -wire litedramcore_bankmachine5_row_hit; -reg litedramcore_bankmachine5_row_open = 1'd0; -reg litedramcore_bankmachine5_row_close = 1'd0; -reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine5_twtpcon_valid; +reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine4_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine4_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine4_wrport_dat_r; +wire [24:0] main_litedramcore_bankmachine4_wrport_dat_w; +wire main_litedramcore_bankmachine4_wrport_we; +reg main_litedramcore_bankmachine5_auto_precharge = 1'd0; +reg [14:0] main_litedramcore_bankmachine5_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba; +reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine5_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine5_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine5_consume = 4'd0; +wire main_litedramcore_bankmachine5_do_read; +wire main_litedramcore_bankmachine5_fifo_in_first; +wire main_litedramcore_bankmachine5_fifo_in_last; +wire [21:0] main_litedramcore_bankmachine5_fifo_in_payload_addr; +wire main_litedramcore_bankmachine5_fifo_in_payload_we; +wire main_litedramcore_bankmachine5_fifo_out_first; +wire main_litedramcore_bankmachine5_fifo_out_last; +wire [21:0] main_litedramcore_bankmachine5_fifo_out_payload_addr; +wire main_litedramcore_bankmachine5_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine5_level = 5'd0; +wire main_litedramcore_bankmachine5_pipe_valid_sink_first; +wire main_litedramcore_bankmachine5_pipe_valid_sink_last; +wire [21:0] main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine5_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine5_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine5_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine5_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine5_pipe_valid_source_last = 1'd0; +reg [21:0] main_litedramcore_bankmachine5_pipe_valid_source_payload_addr = 22'd0; +reg main_litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine5_pipe_valid_source_ready; +reg main_litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine5_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine5_rdport_adr; +wire [24:0] main_litedramcore_bankmachine5_rdport_dat_r; +reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine5_refresh_req; +reg main_litedramcore_bankmachine5_replace = 1'd0; +wire [21:0] main_litedramcore_bankmachine5_req_addr; +wire main_litedramcore_bankmachine5_req_lock; +reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine5_req_ready; +wire main_litedramcore_bankmachine5_req_valid; +reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine5_req_we; +reg [14:0] main_litedramcore_bankmachine5_row = 15'd0; +reg main_litedramcore_bankmachine5_row_close = 1'd0; +reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine5_row_hit; +reg main_litedramcore_bankmachine5_row_open = 1'd0; +reg main_litedramcore_bankmachine5_row_opened = 1'd0; +reg main_litedramcore_bankmachine5_sink_first = 1'd0; +reg main_litedramcore_bankmachine5_sink_last = 1'd0; +wire [21:0] main_litedramcore_bankmachine5_sink_payload_addr; +wire main_litedramcore_bankmachine5_sink_payload_we; +wire main_litedramcore_bankmachine5_sink_ready; +wire main_litedramcore_bankmachine5_sink_sink_first; +wire main_litedramcore_bankmachine5_sink_sink_last; +wire [21:0] main_litedramcore_bankmachine5_sink_sink_payload_addr; +wire main_litedramcore_bankmachine5_sink_sink_payload_we; +wire main_litedramcore_bankmachine5_sink_sink_ready; +wire main_litedramcore_bankmachine5_sink_sink_valid; +wire main_litedramcore_bankmachine5_sink_valid; +wire main_litedramcore_bankmachine5_source_first; +wire main_litedramcore_bankmachine5_source_last; +wire [21:0] main_litedramcore_bankmachine5_source_payload_addr; +wire main_litedramcore_bankmachine5_source_payload_we; +wire main_litedramcore_bankmachine5_source_ready; +wire main_litedramcore_bankmachine5_source_source_first; +wire main_litedramcore_bankmachine5_source_source_last; +wire [21:0] main_litedramcore_bankmachine5_source_source_payload_addr; +wire main_litedramcore_bankmachine5_source_source_payload_we; +wire main_litedramcore_bankmachine5_source_source_ready; +wire main_litedramcore_bankmachine5_source_source_valid; +wire main_litedramcore_bankmachine5_source_valid; +wire [24:0] main_litedramcore_bankmachine5_syncfifo5_din; +wire [24:0] main_litedramcore_bankmachine5_syncfifo5_dout; +wire main_litedramcore_bankmachine5_syncfifo5_re; +wire main_litedramcore_bankmachine5_syncfifo5_readable; +wire main_litedramcore_bankmachine5_syncfifo5_we; +wire main_litedramcore_bankmachine5_syncfifo5_writable; +reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; -wire litedramcore_bankmachine5_trccon_valid; +reg main_litedramcore_bankmachine5_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine5_trascon_valid; +reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0; -wire litedramcore_bankmachine5_trascon_valid; +reg main_litedramcore_bankmachine5_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine5_trccon_valid; +reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine5_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0; -wire litedramcore_bankmachine6_req_valid; -wire litedramcore_bankmachine6_req_ready; -wire litedramcore_bankmachine6_req_we; -wire [21:0] litedramcore_bankmachine6_req_addr; -wire litedramcore_bankmachine6_req_lock; -reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine6_refresh_req; -reg litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg litedramcore_bankmachine6_cmd_valid = 1'd0; -reg litedramcore_bankmachine6_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; -reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine6_auto_precharge = 1'd0; -wire litedramcore_bankmachine6_sink_valid; -wire litedramcore_bankmachine6_sink_ready; -reg litedramcore_bankmachine6_sink_first = 1'd0; -reg litedramcore_bankmachine6_sink_last = 1'd0; -wire litedramcore_bankmachine6_sink_payload_we; -wire [21:0] litedramcore_bankmachine6_sink_payload_addr; -wire litedramcore_bankmachine6_source_valid; -wire litedramcore_bankmachine6_source_ready; -wire litedramcore_bankmachine6_source_first; -wire litedramcore_bankmachine6_source_last; -wire litedramcore_bankmachine6_source_payload_we; -wire [21:0] litedramcore_bankmachine6_source_payload_addr; -wire litedramcore_bankmachine6_syncfifo6_we; -wire litedramcore_bankmachine6_syncfifo6_writable; -wire litedramcore_bankmachine6_syncfifo6_re; -wire litedramcore_bankmachine6_syncfifo6_readable; -wire [24:0] litedramcore_bankmachine6_syncfifo6_din; -wire [24:0] litedramcore_bankmachine6_syncfifo6_dout; -reg [4:0] litedramcore_bankmachine6_level = 5'd0; -reg litedramcore_bankmachine6_replace = 1'd0; -reg [3:0] litedramcore_bankmachine6_produce = 4'd0; -reg [3:0] litedramcore_bankmachine6_consume = 4'd0; -reg [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine6_wrport_dat_r; -wire litedramcore_bankmachine6_wrport_we; -wire [24:0] litedramcore_bankmachine6_wrport_dat_w; -wire litedramcore_bankmachine6_do_read; -wire [3:0] litedramcore_bankmachine6_rdport_adr; -wire [24:0] litedramcore_bankmachine6_rdport_dat_r; -wire litedramcore_bankmachine6_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine6_fifo_in_payload_addr; -wire litedramcore_bankmachine6_fifo_in_first; -wire litedramcore_bankmachine6_fifo_in_last; -wire litedramcore_bankmachine6_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine6_fifo_out_payload_addr; -wire litedramcore_bankmachine6_fifo_out_first; -wire litedramcore_bankmachine6_fifo_out_last; -wire litedramcore_bankmachine6_sink_sink_valid; -wire litedramcore_bankmachine6_sink_sink_ready; -wire litedramcore_bankmachine6_sink_sink_first; -wire litedramcore_bankmachine6_sink_sink_last; -wire litedramcore_bankmachine6_sink_sink_payload_we; -wire [21:0] litedramcore_bankmachine6_sink_sink_payload_addr; -wire litedramcore_bankmachine6_source_source_valid; -wire litedramcore_bankmachine6_source_source_ready; -wire litedramcore_bankmachine6_source_source_first; -wire litedramcore_bankmachine6_source_source_last; -wire litedramcore_bankmachine6_source_source_payload_we; -wire [21:0] litedramcore_bankmachine6_source_source_payload_addr; -wire litedramcore_bankmachine6_pipe_valid_sink_valid; -wire litedramcore_bankmachine6_pipe_valid_sink_ready; -wire litedramcore_bankmachine6_pipe_valid_sink_first; -wire litedramcore_bankmachine6_pipe_valid_sink_last; -wire litedramcore_bankmachine6_pipe_valid_sink_payload_we; -wire [21:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine6_pipe_valid_source_ready; -reg litedramcore_bankmachine6_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine6_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine6_row = 15'd0; -reg litedramcore_bankmachine6_row_opened = 1'd0; -wire litedramcore_bankmachine6_row_hit; -reg litedramcore_bankmachine6_row_open = 1'd0; -reg litedramcore_bankmachine6_row_close = 1'd0; -reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine6_twtpcon_valid; +reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine5_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine5_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine5_wrport_dat_r; +wire [24:0] main_litedramcore_bankmachine5_wrport_dat_w; +wire main_litedramcore_bankmachine5_wrport_we; +reg main_litedramcore_bankmachine6_auto_precharge = 1'd0; +reg [14:0] main_litedramcore_bankmachine6_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba; +reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine6_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine6_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine6_consume = 4'd0; +wire main_litedramcore_bankmachine6_do_read; +wire main_litedramcore_bankmachine6_fifo_in_first; +wire main_litedramcore_bankmachine6_fifo_in_last; +wire [21:0] main_litedramcore_bankmachine6_fifo_in_payload_addr; +wire main_litedramcore_bankmachine6_fifo_in_payload_we; +wire main_litedramcore_bankmachine6_fifo_out_first; +wire main_litedramcore_bankmachine6_fifo_out_last; +wire [21:0] main_litedramcore_bankmachine6_fifo_out_payload_addr; +wire main_litedramcore_bankmachine6_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine6_level = 5'd0; +wire main_litedramcore_bankmachine6_pipe_valid_sink_first; +wire main_litedramcore_bankmachine6_pipe_valid_sink_last; +wire [21:0] main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine6_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine6_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine6_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine6_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine6_pipe_valid_source_last = 1'd0; +reg [21:0] main_litedramcore_bankmachine6_pipe_valid_source_payload_addr = 22'd0; +reg main_litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine6_pipe_valid_source_ready; +reg main_litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine6_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine6_rdport_adr; +wire [24:0] main_litedramcore_bankmachine6_rdport_dat_r; +reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine6_refresh_req; +reg main_litedramcore_bankmachine6_replace = 1'd0; +wire [21:0] main_litedramcore_bankmachine6_req_addr; +wire main_litedramcore_bankmachine6_req_lock; +reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine6_req_ready; +wire main_litedramcore_bankmachine6_req_valid; +reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine6_req_we; +reg [14:0] main_litedramcore_bankmachine6_row = 15'd0; +reg main_litedramcore_bankmachine6_row_close = 1'd0; +reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine6_row_hit; +reg main_litedramcore_bankmachine6_row_open = 1'd0; +reg main_litedramcore_bankmachine6_row_opened = 1'd0; +reg main_litedramcore_bankmachine6_sink_first = 1'd0; +reg main_litedramcore_bankmachine6_sink_last = 1'd0; +wire [21:0] main_litedramcore_bankmachine6_sink_payload_addr; +wire main_litedramcore_bankmachine6_sink_payload_we; +wire main_litedramcore_bankmachine6_sink_ready; +wire main_litedramcore_bankmachine6_sink_sink_first; +wire main_litedramcore_bankmachine6_sink_sink_last; +wire [21:0] main_litedramcore_bankmachine6_sink_sink_payload_addr; +wire main_litedramcore_bankmachine6_sink_sink_payload_we; +wire main_litedramcore_bankmachine6_sink_sink_ready; +wire main_litedramcore_bankmachine6_sink_sink_valid; +wire main_litedramcore_bankmachine6_sink_valid; +wire main_litedramcore_bankmachine6_source_first; +wire main_litedramcore_bankmachine6_source_last; +wire [21:0] main_litedramcore_bankmachine6_source_payload_addr; +wire main_litedramcore_bankmachine6_source_payload_we; +wire main_litedramcore_bankmachine6_source_ready; +wire main_litedramcore_bankmachine6_source_source_first; +wire main_litedramcore_bankmachine6_source_source_last; +wire [21:0] main_litedramcore_bankmachine6_source_source_payload_addr; +wire main_litedramcore_bankmachine6_source_source_payload_we; +wire main_litedramcore_bankmachine6_source_source_ready; +wire main_litedramcore_bankmachine6_source_source_valid; +wire main_litedramcore_bankmachine6_source_valid; +wire [24:0] main_litedramcore_bankmachine6_syncfifo6_din; +wire [24:0] main_litedramcore_bankmachine6_syncfifo6_dout; +wire main_litedramcore_bankmachine6_syncfifo6_re; +wire main_litedramcore_bankmachine6_syncfifo6_readable; +wire main_litedramcore_bankmachine6_syncfifo6_we; +wire main_litedramcore_bankmachine6_syncfifo6_writable; +reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; -wire litedramcore_bankmachine6_trccon_valid; +reg main_litedramcore_bankmachine6_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine6_trascon_valid; +reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0; -wire litedramcore_bankmachine6_trascon_valid; +reg main_litedramcore_bankmachine6_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine6_trccon_valid; +reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine6_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0; -wire litedramcore_bankmachine7_req_valid; -wire litedramcore_bankmachine7_req_ready; -wire litedramcore_bankmachine7_req_we; -wire [21:0] litedramcore_bankmachine7_req_addr; -wire litedramcore_bankmachine7_req_lock; -reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine7_refresh_req; -reg litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg litedramcore_bankmachine7_cmd_valid = 1'd0; -reg litedramcore_bankmachine7_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; -reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine7_auto_precharge = 1'd0; -wire litedramcore_bankmachine7_sink_valid; -wire litedramcore_bankmachine7_sink_ready; -reg litedramcore_bankmachine7_sink_first = 1'd0; -reg litedramcore_bankmachine7_sink_last = 1'd0; -wire litedramcore_bankmachine7_sink_payload_we; -wire [21:0] litedramcore_bankmachine7_sink_payload_addr; -wire litedramcore_bankmachine7_source_valid; -wire litedramcore_bankmachine7_source_ready; -wire litedramcore_bankmachine7_source_first; -wire litedramcore_bankmachine7_source_last; -wire litedramcore_bankmachine7_source_payload_we; -wire [21:0] litedramcore_bankmachine7_source_payload_addr; -wire litedramcore_bankmachine7_syncfifo7_we; -wire litedramcore_bankmachine7_syncfifo7_writable; -wire litedramcore_bankmachine7_syncfifo7_re; -wire litedramcore_bankmachine7_syncfifo7_readable; -wire [24:0] litedramcore_bankmachine7_syncfifo7_din; -wire [24:0] litedramcore_bankmachine7_syncfifo7_dout; -reg [4:0] litedramcore_bankmachine7_level = 5'd0; -reg litedramcore_bankmachine7_replace = 1'd0; -reg [3:0] litedramcore_bankmachine7_produce = 4'd0; -reg [3:0] litedramcore_bankmachine7_consume = 4'd0; -reg [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine7_wrport_dat_r; -wire litedramcore_bankmachine7_wrport_we; -wire [24:0] litedramcore_bankmachine7_wrport_dat_w; -wire litedramcore_bankmachine7_do_read; -wire [3:0] litedramcore_bankmachine7_rdport_adr; -wire [24:0] litedramcore_bankmachine7_rdport_dat_r; -wire litedramcore_bankmachine7_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine7_fifo_in_payload_addr; -wire litedramcore_bankmachine7_fifo_in_first; -wire litedramcore_bankmachine7_fifo_in_last; -wire litedramcore_bankmachine7_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine7_fifo_out_payload_addr; -wire litedramcore_bankmachine7_fifo_out_first; -wire litedramcore_bankmachine7_fifo_out_last; -wire litedramcore_bankmachine7_sink_sink_valid; -wire litedramcore_bankmachine7_sink_sink_ready; -wire litedramcore_bankmachine7_sink_sink_first; -wire litedramcore_bankmachine7_sink_sink_last; -wire litedramcore_bankmachine7_sink_sink_payload_we; -wire [21:0] litedramcore_bankmachine7_sink_sink_payload_addr; -wire litedramcore_bankmachine7_source_source_valid; -wire litedramcore_bankmachine7_source_source_ready; -wire litedramcore_bankmachine7_source_source_first; -wire litedramcore_bankmachine7_source_source_last; -wire litedramcore_bankmachine7_source_source_payload_we; -wire [21:0] litedramcore_bankmachine7_source_source_payload_addr; -wire litedramcore_bankmachine7_pipe_valid_sink_valid; -wire litedramcore_bankmachine7_pipe_valid_sink_ready; -wire litedramcore_bankmachine7_pipe_valid_sink_first; -wire litedramcore_bankmachine7_pipe_valid_sink_last; -wire litedramcore_bankmachine7_pipe_valid_sink_payload_we; -wire [21:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine7_pipe_valid_source_ready; -reg litedramcore_bankmachine7_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine7_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine7_row = 15'd0; -reg litedramcore_bankmachine7_row_opened = 1'd0; -wire litedramcore_bankmachine7_row_hit; -reg litedramcore_bankmachine7_row_open = 1'd0; -reg litedramcore_bankmachine7_row_close = 1'd0; -reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine7_twtpcon_valid; +reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine6_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine6_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine6_wrport_dat_r; +wire [24:0] main_litedramcore_bankmachine6_wrport_dat_w; +wire main_litedramcore_bankmachine6_wrport_we; +reg main_litedramcore_bankmachine7_auto_precharge = 1'd0; +reg [14:0] main_litedramcore_bankmachine7_cmd_payload_a = 15'd0; +wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba; +reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine7_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine7_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine7_consume = 4'd0; +wire main_litedramcore_bankmachine7_do_read; +wire main_litedramcore_bankmachine7_fifo_in_first; +wire main_litedramcore_bankmachine7_fifo_in_last; +wire [21:0] main_litedramcore_bankmachine7_fifo_in_payload_addr; +wire main_litedramcore_bankmachine7_fifo_in_payload_we; +wire main_litedramcore_bankmachine7_fifo_out_first; +wire main_litedramcore_bankmachine7_fifo_out_last; +wire [21:0] main_litedramcore_bankmachine7_fifo_out_payload_addr; +wire main_litedramcore_bankmachine7_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine7_level = 5'd0; +wire main_litedramcore_bankmachine7_pipe_valid_sink_first; +wire main_litedramcore_bankmachine7_pipe_valid_sink_last; +wire [21:0] main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine7_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine7_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine7_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine7_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine7_pipe_valid_source_last = 1'd0; +reg [21:0] main_litedramcore_bankmachine7_pipe_valid_source_payload_addr = 22'd0; +reg main_litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine7_pipe_valid_source_ready; +reg main_litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine7_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine7_rdport_adr; +wire [24:0] main_litedramcore_bankmachine7_rdport_dat_r; +reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine7_refresh_req; +reg main_litedramcore_bankmachine7_replace = 1'd0; +wire [21:0] main_litedramcore_bankmachine7_req_addr; +wire main_litedramcore_bankmachine7_req_lock; +reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine7_req_ready; +wire main_litedramcore_bankmachine7_req_valid; +reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine7_req_we; +reg [14:0] main_litedramcore_bankmachine7_row = 15'd0; +reg main_litedramcore_bankmachine7_row_close = 1'd0; +reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine7_row_hit; +reg main_litedramcore_bankmachine7_row_open = 1'd0; +reg main_litedramcore_bankmachine7_row_opened = 1'd0; +reg main_litedramcore_bankmachine7_sink_first = 1'd0; +reg main_litedramcore_bankmachine7_sink_last = 1'd0; +wire [21:0] main_litedramcore_bankmachine7_sink_payload_addr; +wire main_litedramcore_bankmachine7_sink_payload_we; +wire main_litedramcore_bankmachine7_sink_ready; +wire main_litedramcore_bankmachine7_sink_sink_first; +wire main_litedramcore_bankmachine7_sink_sink_last; +wire [21:0] main_litedramcore_bankmachine7_sink_sink_payload_addr; +wire main_litedramcore_bankmachine7_sink_sink_payload_we; +wire main_litedramcore_bankmachine7_sink_sink_ready; +wire main_litedramcore_bankmachine7_sink_sink_valid; +wire main_litedramcore_bankmachine7_sink_valid; +wire main_litedramcore_bankmachine7_source_first; +wire main_litedramcore_bankmachine7_source_last; +wire [21:0] main_litedramcore_bankmachine7_source_payload_addr; +wire main_litedramcore_bankmachine7_source_payload_we; +wire main_litedramcore_bankmachine7_source_ready; +wire main_litedramcore_bankmachine7_source_source_first; +wire main_litedramcore_bankmachine7_source_source_last; +wire [21:0] main_litedramcore_bankmachine7_source_source_payload_addr; +wire main_litedramcore_bankmachine7_source_source_payload_we; +wire main_litedramcore_bankmachine7_source_source_ready; +wire main_litedramcore_bankmachine7_source_source_valid; +wire main_litedramcore_bankmachine7_source_valid; +wire [24:0] main_litedramcore_bankmachine7_syncfifo7_din; +wire [24:0] main_litedramcore_bankmachine7_syncfifo7_dout; +wire main_litedramcore_bankmachine7_syncfifo7_re; +wire main_litedramcore_bankmachine7_syncfifo7_readable; +wire main_litedramcore_bankmachine7_syncfifo7_we; +wire main_litedramcore_bankmachine7_syncfifo7_writable; +reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; -wire litedramcore_bankmachine7_trccon_valid; +reg main_litedramcore_bankmachine7_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine7_trascon_valid; +reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0; -wire litedramcore_bankmachine7_trascon_valid; +reg main_litedramcore_bankmachine7_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine7_trccon_valid; +reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine7_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0; -wire litedramcore_ras_allowed; -wire litedramcore_cas_allowed; -wire [1:0] litedramcore_rdcmdphase; -wire [1:0] litedramcore_wrcmdphase; -reg litedramcore_choose_cmd_want_reads = 1'd0; -reg litedramcore_choose_cmd_want_writes = 1'd0; -reg litedramcore_choose_cmd_want_cmds = 1'd0; -reg litedramcore_choose_cmd_want_activates = 1'd0; -wire litedramcore_choose_cmd_cmd_valid; -reg litedramcore_choose_cmd_cmd_ready = 1'd0; -wire [14:0] litedramcore_choose_cmd_cmd_payload_a; -wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; -reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; -wire litedramcore_choose_cmd_cmd_payload_is_cmd; -wire litedramcore_choose_cmd_cmd_payload_is_read; -wire litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] litedramcore_choose_cmd_valids = 8'd0; -wire [7:0] litedramcore_choose_cmd_request; -reg [2:0] litedramcore_choose_cmd_grant = 3'd0; -wire litedramcore_choose_cmd_ce; -reg litedramcore_choose_req_want_reads = 1'd0; -reg litedramcore_choose_req_want_writes = 1'd0; -reg litedramcore_choose_req_want_cmds = 1'd0; -reg litedramcore_choose_req_want_activates = 1'd0; -wire litedramcore_choose_req_cmd_valid; -reg litedramcore_choose_req_cmd_ready = 1'd0; -wire [14:0] litedramcore_choose_req_cmd_payload_a; -wire [2:0] litedramcore_choose_req_cmd_payload_ba; -reg litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg litedramcore_choose_req_cmd_payload_we = 1'd0; -wire litedramcore_choose_req_cmd_payload_is_cmd; -wire litedramcore_choose_req_cmd_payload_is_read; -wire litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] litedramcore_choose_req_valids = 8'd0; -wire [7:0] litedramcore_choose_req_request; -reg [2:0] litedramcore_choose_req_grant = 3'd0; -wire litedramcore_choose_req_ce; -reg [14:0] litedramcore_nop_a = 15'd0; -reg [2:0] litedramcore_nop_ba = 3'd0; -reg [1:0] litedramcore_steerer_sel0 = 2'd0; -reg [1:0] litedramcore_steerer_sel1 = 2'd0; -reg [1:0] litedramcore_steerer_sel2 = 2'd0; -reg [1:0] litedramcore_steerer_sel3 = 2'd0; -reg litedramcore_steerer0 = 1'd1; -reg litedramcore_steerer1 = 1'd1; -reg litedramcore_steerer2 = 1'd1; -reg litedramcore_steerer3 = 1'd1; -reg litedramcore_steerer4 = 1'd1; -reg litedramcore_steerer5 = 1'd1; -reg litedramcore_steerer6 = 1'd1; -reg litedramcore_steerer7 = 1'd1; -wire litedramcore_trrdcon_valid; +reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine7_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine7_wrport_adr = 4'd0; +wire [24:0] main_litedramcore_bankmachine7_wrport_dat_r; +wire [24:0] main_litedramcore_bankmachine7_wrport_dat_w; +wire main_litedramcore_bankmachine7_wrport_we; +wire main_litedramcore_cas_allowed; +wire main_litedramcore_choose_cmd_ce; +wire [14:0] main_litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba; +reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +wire main_litedramcore_choose_cmd_cmd_payload_is_cmd; +wire main_litedramcore_choose_cmd_cmd_payload_is_read; +wire main_litedramcore_choose_cmd_cmd_payload_is_write; +reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0; +reg main_litedramcore_choose_cmd_cmd_ready = 1'd0; +wire main_litedramcore_choose_cmd_cmd_valid; +reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0; +wire [7:0] main_litedramcore_choose_cmd_request; +reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0; +reg main_litedramcore_choose_cmd_want_activates = 1'd0; +reg main_litedramcore_choose_cmd_want_cmds = 1'd0; +reg main_litedramcore_choose_cmd_want_reads = 1'd0; +reg main_litedramcore_choose_cmd_want_writes = 1'd0; +wire main_litedramcore_choose_req_ce; +wire [14:0] main_litedramcore_choose_req_cmd_payload_a; +wire [2:0] main_litedramcore_choose_req_cmd_payload_ba; +reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0; +wire main_litedramcore_choose_req_cmd_payload_is_cmd; +wire main_litedramcore_choose_req_cmd_payload_is_read; +wire main_litedramcore_choose_req_cmd_payload_is_write; +reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_we = 1'd0; +reg main_litedramcore_choose_req_cmd_ready = 1'd0; +wire main_litedramcore_choose_req_cmd_valid; +reg [2:0] main_litedramcore_choose_req_grant = 3'd0; +wire [7:0] main_litedramcore_choose_req_request; +reg [7:0] main_litedramcore_choose_req_valids = 8'd0; +reg main_litedramcore_choose_req_want_activates = 1'd0; +reg main_litedramcore_choose_req_want_cmds = 1'd0; +reg main_litedramcore_choose_req_want_reads = 1'd0; +reg main_litedramcore_choose_req_want_writes = 1'd0; +wire main_litedramcore_cke; +reg main_litedramcore_cmd_last = 1'd0; +reg [14:0] main_litedramcore_cmd_payload_a = 15'd0; +reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0; +reg main_litedramcore_cmd_payload_cas = 1'd0; +reg main_litedramcore_cmd_payload_is_read = 1'd0; +reg main_litedramcore_cmd_payload_is_write = 1'd0; +reg main_litedramcore_cmd_payload_ras = 1'd0; +reg main_litedramcore_cmd_payload_we = 1'd0; +reg main_litedramcore_cmd_ready = 1'd0; +reg main_litedramcore_cmd_valid = 1'd0; +reg main_litedramcore_csr_dfi_p0_act_n = 1'd1; +wire [14:0] main_litedramcore_csr_dfi_p0_address; +wire [2:0] main_litedramcore_csr_dfi_p0_bank; +reg main_litedramcore_csr_dfi_p0_cas_n = 1'd1; +reg main_litedramcore_csr_dfi_p0_cke = 1'd0; +reg main_litedramcore_csr_dfi_p0_cs_n = 1'd1; +reg main_litedramcore_csr_dfi_p0_odt = 1'd0; +reg main_litedramcore_csr_dfi_p0_ras_n = 1'd1; +reg [31:0] main_litedramcore_csr_dfi_p0_rddata = 32'd0; +wire main_litedramcore_csr_dfi_p0_rddata_en; +reg main_litedramcore_csr_dfi_p0_rddata_valid = 1'd0; +wire main_litedramcore_csr_dfi_p0_reset_n; +reg main_litedramcore_csr_dfi_p0_we_n = 1'd1; +wire [31:0] main_litedramcore_csr_dfi_p0_wrdata; +wire main_litedramcore_csr_dfi_p0_wrdata_en; +wire [3:0] main_litedramcore_csr_dfi_p0_wrdata_mask; +reg main_litedramcore_csr_dfi_p1_act_n = 1'd1; +wire [14:0] main_litedramcore_csr_dfi_p1_address; +wire [2:0] main_litedramcore_csr_dfi_p1_bank; +reg main_litedramcore_csr_dfi_p1_cas_n = 1'd1; +reg main_litedramcore_csr_dfi_p1_cke = 1'd0; +reg main_litedramcore_csr_dfi_p1_cs_n = 1'd1; +reg main_litedramcore_csr_dfi_p1_odt = 1'd0; +reg main_litedramcore_csr_dfi_p1_ras_n = 1'd1; +reg [31:0] main_litedramcore_csr_dfi_p1_rddata = 32'd0; +wire main_litedramcore_csr_dfi_p1_rddata_en; +reg main_litedramcore_csr_dfi_p1_rddata_valid = 1'd0; +wire main_litedramcore_csr_dfi_p1_reset_n; +reg main_litedramcore_csr_dfi_p1_we_n = 1'd1; +wire [31:0] main_litedramcore_csr_dfi_p1_wrdata; +wire main_litedramcore_csr_dfi_p1_wrdata_en; +wire [3:0] main_litedramcore_csr_dfi_p1_wrdata_mask; +reg main_litedramcore_csr_dfi_p2_act_n = 1'd1; +wire [14:0] main_litedramcore_csr_dfi_p2_address; +wire [2:0] main_litedramcore_csr_dfi_p2_bank; +reg main_litedramcore_csr_dfi_p2_cas_n = 1'd1; +reg main_litedramcore_csr_dfi_p2_cke = 1'd0; +reg main_litedramcore_csr_dfi_p2_cs_n = 1'd1; +reg main_litedramcore_csr_dfi_p2_odt = 1'd0; +reg main_litedramcore_csr_dfi_p2_ras_n = 1'd1; +reg [31:0] main_litedramcore_csr_dfi_p2_rddata = 32'd0; +wire main_litedramcore_csr_dfi_p2_rddata_en; +reg main_litedramcore_csr_dfi_p2_rddata_valid = 1'd0; +wire main_litedramcore_csr_dfi_p2_reset_n; +reg main_litedramcore_csr_dfi_p2_we_n = 1'd1; +wire [31:0] main_litedramcore_csr_dfi_p2_wrdata; +wire main_litedramcore_csr_dfi_p2_wrdata_en; +wire [3:0] main_litedramcore_csr_dfi_p2_wrdata_mask; +reg main_litedramcore_csr_dfi_p3_act_n = 1'd1; +wire [14:0] main_litedramcore_csr_dfi_p3_address; +wire [2:0] main_litedramcore_csr_dfi_p3_bank; +reg main_litedramcore_csr_dfi_p3_cas_n = 1'd1; +reg main_litedramcore_csr_dfi_p3_cke = 1'd0; +reg main_litedramcore_csr_dfi_p3_cs_n = 1'd1; +reg main_litedramcore_csr_dfi_p3_odt = 1'd0; +reg main_litedramcore_csr_dfi_p3_ras_n = 1'd1; +reg [31:0] main_litedramcore_csr_dfi_p3_rddata = 32'd0; +wire main_litedramcore_csr_dfi_p3_rddata_en; +reg main_litedramcore_csr_dfi_p3_rddata_valid = 1'd0; +wire main_litedramcore_csr_dfi_p3_reset_n; +reg main_litedramcore_csr_dfi_p3_we_n = 1'd1; +wire [31:0] main_litedramcore_csr_dfi_p3_wrdata; +wire main_litedramcore_csr_dfi_p3_wrdata_en; +wire [3:0] main_litedramcore_csr_dfi_p3_wrdata_mask; +reg main_litedramcore_dfi_p0_act_n = 1'd1; +reg [14:0] main_litedramcore_dfi_p0_address = 15'd0; +reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0; +reg main_litedramcore_dfi_p0_cas_n = 1'd1; +wire main_litedramcore_dfi_p0_cke; +reg main_litedramcore_dfi_p0_cs_n = 1'd1; +wire main_litedramcore_dfi_p0_odt; +reg main_litedramcore_dfi_p0_ras_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p0_rddata; +reg main_litedramcore_dfi_p0_rddata_en = 1'd0; +wire main_litedramcore_dfi_p0_rddata_valid; +wire main_litedramcore_dfi_p0_reset_n; +reg main_litedramcore_dfi_p0_we_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p0_wrdata; +reg main_litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p0_wrdata_mask; +reg main_litedramcore_dfi_p1_act_n = 1'd1; +reg [14:0] main_litedramcore_dfi_p1_address = 15'd0; +reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0; +reg main_litedramcore_dfi_p1_cas_n = 1'd1; +wire main_litedramcore_dfi_p1_cke; +reg main_litedramcore_dfi_p1_cs_n = 1'd1; +wire main_litedramcore_dfi_p1_odt; +reg main_litedramcore_dfi_p1_ras_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p1_rddata; +reg main_litedramcore_dfi_p1_rddata_en = 1'd0; +wire main_litedramcore_dfi_p1_rddata_valid; +wire main_litedramcore_dfi_p1_reset_n; +reg main_litedramcore_dfi_p1_we_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p1_wrdata; +reg main_litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p1_wrdata_mask; +reg main_litedramcore_dfi_p2_act_n = 1'd1; +reg [14:0] main_litedramcore_dfi_p2_address = 15'd0; +reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0; +reg main_litedramcore_dfi_p2_cas_n = 1'd1; +wire main_litedramcore_dfi_p2_cke; +reg main_litedramcore_dfi_p2_cs_n = 1'd1; +wire main_litedramcore_dfi_p2_odt; +reg main_litedramcore_dfi_p2_ras_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p2_rddata; +reg main_litedramcore_dfi_p2_rddata_en = 1'd0; +wire main_litedramcore_dfi_p2_rddata_valid; +wire main_litedramcore_dfi_p2_reset_n; +reg main_litedramcore_dfi_p2_we_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p2_wrdata; +reg main_litedramcore_dfi_p2_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p2_wrdata_mask; +reg main_litedramcore_dfi_p3_act_n = 1'd1; +reg [14:0] main_litedramcore_dfi_p3_address = 15'd0; +reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0; +reg main_litedramcore_dfi_p3_cas_n = 1'd1; +wire main_litedramcore_dfi_p3_cke; +reg main_litedramcore_dfi_p3_cs_n = 1'd1; +wire main_litedramcore_dfi_p3_odt; +reg main_litedramcore_dfi_p3_ras_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p3_rddata; +reg main_litedramcore_dfi_p3_rddata_en = 1'd0; +wire main_litedramcore_dfi_p3_rddata_valid; +wire main_litedramcore_dfi_p3_reset_n; +reg main_litedramcore_dfi_p3_we_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p3_wrdata; +reg main_litedramcore_dfi_p3_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p3_wrdata_mask; +reg main_litedramcore_en0 = 1'd0; +reg main_litedramcore_en1 = 1'd0; +reg main_litedramcore_ext_dfi_p0_act_n = 1'd1; +reg [14:0] main_litedramcore_ext_dfi_p0_address = 15'd0; +reg [2:0] main_litedramcore_ext_dfi_p0_bank = 3'd0; +reg main_litedramcore_ext_dfi_p0_cas_n = 1'd1; +reg main_litedramcore_ext_dfi_p0_cke = 1'd0; +reg main_litedramcore_ext_dfi_p0_cs_n = 1'd1; +reg main_litedramcore_ext_dfi_p0_odt = 1'd0; +reg main_litedramcore_ext_dfi_p0_ras_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p0_rddata = 32'd0; +reg main_litedramcore_ext_dfi_p0_rddata_en = 1'd0; +reg main_litedramcore_ext_dfi_p0_rddata_valid = 1'd0; +reg main_litedramcore_ext_dfi_p0_reset_n = 1'd0; +reg main_litedramcore_ext_dfi_p0_we_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p0_wrdata = 32'd0; +reg main_litedramcore_ext_dfi_p0_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_ext_dfi_p0_wrdata_mask = 4'd0; +reg main_litedramcore_ext_dfi_p1_act_n = 1'd1; +reg [14:0] main_litedramcore_ext_dfi_p1_address = 15'd0; +reg [2:0] main_litedramcore_ext_dfi_p1_bank = 3'd0; +reg main_litedramcore_ext_dfi_p1_cas_n = 1'd1; +reg main_litedramcore_ext_dfi_p1_cke = 1'd0; +reg main_litedramcore_ext_dfi_p1_cs_n = 1'd1; +reg main_litedramcore_ext_dfi_p1_odt = 1'd0; +reg main_litedramcore_ext_dfi_p1_ras_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p1_rddata = 32'd0; +reg main_litedramcore_ext_dfi_p1_rddata_en = 1'd0; +reg main_litedramcore_ext_dfi_p1_rddata_valid = 1'd0; +reg main_litedramcore_ext_dfi_p1_reset_n = 1'd0; +reg main_litedramcore_ext_dfi_p1_we_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p1_wrdata = 32'd0; +reg main_litedramcore_ext_dfi_p1_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_ext_dfi_p1_wrdata_mask = 4'd0; +reg main_litedramcore_ext_dfi_p2_act_n = 1'd1; +reg [14:0] main_litedramcore_ext_dfi_p2_address = 15'd0; +reg [2:0] main_litedramcore_ext_dfi_p2_bank = 3'd0; +reg main_litedramcore_ext_dfi_p2_cas_n = 1'd1; +reg main_litedramcore_ext_dfi_p2_cke = 1'd0; +reg main_litedramcore_ext_dfi_p2_cs_n = 1'd1; +reg main_litedramcore_ext_dfi_p2_odt = 1'd0; +reg main_litedramcore_ext_dfi_p2_ras_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p2_rddata = 32'd0; +reg main_litedramcore_ext_dfi_p2_rddata_en = 1'd0; +reg main_litedramcore_ext_dfi_p2_rddata_valid = 1'd0; +reg main_litedramcore_ext_dfi_p2_reset_n = 1'd0; +reg main_litedramcore_ext_dfi_p2_we_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p2_wrdata = 32'd0; +reg main_litedramcore_ext_dfi_p2_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_ext_dfi_p2_wrdata_mask = 4'd0; +reg main_litedramcore_ext_dfi_p3_act_n = 1'd1; +reg [14:0] main_litedramcore_ext_dfi_p3_address = 15'd0; +reg [2:0] main_litedramcore_ext_dfi_p3_bank = 3'd0; +reg main_litedramcore_ext_dfi_p3_cas_n = 1'd1; +reg main_litedramcore_ext_dfi_p3_cke = 1'd0; +reg main_litedramcore_ext_dfi_p3_cs_n = 1'd1; +reg main_litedramcore_ext_dfi_p3_odt = 1'd0; +reg main_litedramcore_ext_dfi_p3_ras_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p3_rddata = 32'd0; +reg main_litedramcore_ext_dfi_p3_rddata_en = 1'd0; +reg main_litedramcore_ext_dfi_p3_rddata_valid = 1'd0; +reg main_litedramcore_ext_dfi_p3_reset_n = 1'd0; +reg main_litedramcore_ext_dfi_p3_we_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p3_wrdata = 32'd0; +reg main_litedramcore_ext_dfi_p3_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_ext_dfi_p3_wrdata_mask = 4'd0; +reg main_litedramcore_ext_dfi_sel = 1'd0; +wire main_litedramcore_go_to_refresh; +wire [21:0] main_litedramcore_interface_bank0_addr; +wire main_litedramcore_interface_bank0_lock; +wire main_litedramcore_interface_bank0_rdata_valid; +wire main_litedramcore_interface_bank0_ready; +wire main_litedramcore_interface_bank0_valid; +wire main_litedramcore_interface_bank0_wdata_ready; +wire main_litedramcore_interface_bank0_we; +wire [21:0] main_litedramcore_interface_bank1_addr; +wire main_litedramcore_interface_bank1_lock; +wire main_litedramcore_interface_bank1_rdata_valid; +wire main_litedramcore_interface_bank1_ready; +wire main_litedramcore_interface_bank1_valid; +wire main_litedramcore_interface_bank1_wdata_ready; +wire main_litedramcore_interface_bank1_we; +wire [21:0] main_litedramcore_interface_bank2_addr; +wire main_litedramcore_interface_bank2_lock; +wire main_litedramcore_interface_bank2_rdata_valid; +wire main_litedramcore_interface_bank2_ready; +wire main_litedramcore_interface_bank2_valid; +wire main_litedramcore_interface_bank2_wdata_ready; +wire main_litedramcore_interface_bank2_we; +wire [21:0] main_litedramcore_interface_bank3_addr; +wire main_litedramcore_interface_bank3_lock; +wire main_litedramcore_interface_bank3_rdata_valid; +wire main_litedramcore_interface_bank3_ready; +wire main_litedramcore_interface_bank3_valid; +wire main_litedramcore_interface_bank3_wdata_ready; +wire main_litedramcore_interface_bank3_we; +wire [21:0] main_litedramcore_interface_bank4_addr; +wire main_litedramcore_interface_bank4_lock; +wire main_litedramcore_interface_bank4_rdata_valid; +wire main_litedramcore_interface_bank4_ready; +wire main_litedramcore_interface_bank4_valid; +wire main_litedramcore_interface_bank4_wdata_ready; +wire main_litedramcore_interface_bank4_we; +wire [21:0] main_litedramcore_interface_bank5_addr; +wire main_litedramcore_interface_bank5_lock; +wire main_litedramcore_interface_bank5_rdata_valid; +wire main_litedramcore_interface_bank5_ready; +wire main_litedramcore_interface_bank5_valid; +wire main_litedramcore_interface_bank5_wdata_ready; +wire main_litedramcore_interface_bank5_we; +wire [21:0] main_litedramcore_interface_bank6_addr; +wire main_litedramcore_interface_bank6_lock; +wire main_litedramcore_interface_bank6_rdata_valid; +wire main_litedramcore_interface_bank6_ready; +wire main_litedramcore_interface_bank6_valid; +wire main_litedramcore_interface_bank6_wdata_ready; +wire main_litedramcore_interface_bank6_we; +wire [21:0] main_litedramcore_interface_bank7_addr; +wire main_litedramcore_interface_bank7_lock; +wire main_litedramcore_interface_bank7_rdata_valid; +wire main_litedramcore_interface_bank7_ready; +wire main_litedramcore_interface_bank7_valid; +wire main_litedramcore_interface_bank7_wdata_ready; +wire main_litedramcore_interface_bank7_we; +wire [127:0] main_litedramcore_interface_rdata; +reg [127:0] main_litedramcore_interface_wdata = 128'd0; +reg [15:0] main_litedramcore_interface_wdata_we = 16'd0; +reg main_litedramcore_master_p0_act_n = 1'd1; +reg [14:0] main_litedramcore_master_p0_address = 15'd0; +reg [2:0] main_litedramcore_master_p0_bank = 3'd0; +reg main_litedramcore_master_p0_cas_n = 1'd1; +reg main_litedramcore_master_p0_cke = 1'd0; +reg main_litedramcore_master_p0_cs_n = 1'd1; +reg main_litedramcore_master_p0_odt = 1'd0; +reg main_litedramcore_master_p0_ras_n = 1'd1; +wire [31:0] main_litedramcore_master_p0_rddata; +reg main_litedramcore_master_p0_rddata_en = 1'd0; +wire main_litedramcore_master_p0_rddata_valid; +reg main_litedramcore_master_p0_reset_n = 1'd0; +reg main_litedramcore_master_p0_we_n = 1'd1; +reg [31:0] main_litedramcore_master_p0_wrdata = 32'd0; +reg main_litedramcore_master_p0_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0; +reg main_litedramcore_master_p1_act_n = 1'd1; +reg [14:0] main_litedramcore_master_p1_address = 15'd0; +reg [2:0] main_litedramcore_master_p1_bank = 3'd0; +reg main_litedramcore_master_p1_cas_n = 1'd1; +reg main_litedramcore_master_p1_cke = 1'd0; +reg main_litedramcore_master_p1_cs_n = 1'd1; +reg main_litedramcore_master_p1_odt = 1'd0; +reg main_litedramcore_master_p1_ras_n = 1'd1; +wire [31:0] main_litedramcore_master_p1_rddata; +reg main_litedramcore_master_p1_rddata_en = 1'd0; +wire main_litedramcore_master_p1_rddata_valid; +reg main_litedramcore_master_p1_reset_n = 1'd0; +reg main_litedramcore_master_p1_we_n = 1'd1; +reg [31:0] main_litedramcore_master_p1_wrdata = 32'd0; +reg main_litedramcore_master_p1_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0; +reg main_litedramcore_master_p2_act_n = 1'd1; +reg [14:0] main_litedramcore_master_p2_address = 15'd0; +reg [2:0] main_litedramcore_master_p2_bank = 3'd0; +reg main_litedramcore_master_p2_cas_n = 1'd1; +reg main_litedramcore_master_p2_cke = 1'd0; +reg main_litedramcore_master_p2_cs_n = 1'd1; +reg main_litedramcore_master_p2_odt = 1'd0; +reg main_litedramcore_master_p2_ras_n = 1'd1; +wire [31:0] main_litedramcore_master_p2_rddata; +reg main_litedramcore_master_p2_rddata_en = 1'd0; +wire main_litedramcore_master_p2_rddata_valid; +reg main_litedramcore_master_p2_reset_n = 1'd0; +reg main_litedramcore_master_p2_we_n = 1'd1; +reg [31:0] main_litedramcore_master_p2_wrdata = 32'd0; +reg main_litedramcore_master_p2_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0; +reg main_litedramcore_master_p3_act_n = 1'd1; +reg [14:0] main_litedramcore_master_p3_address = 15'd0; +reg [2:0] main_litedramcore_master_p3_bank = 3'd0; +reg main_litedramcore_master_p3_cas_n = 1'd1; +reg main_litedramcore_master_p3_cke = 1'd0; +reg main_litedramcore_master_p3_cs_n = 1'd1; +reg main_litedramcore_master_p3_odt = 1'd0; +reg main_litedramcore_master_p3_ras_n = 1'd1; +wire [31:0] main_litedramcore_master_p3_rddata; +reg main_litedramcore_master_p3_rddata_en = 1'd0; +wire main_litedramcore_master_p3_rddata_valid; +reg main_litedramcore_master_p3_reset_n = 1'd0; +reg main_litedramcore_master_p3_we_n = 1'd1; +reg [31:0] main_litedramcore_master_p3_wrdata = 32'd0; +reg main_litedramcore_master_p3_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0; +wire main_litedramcore_max_time0; +wire main_litedramcore_max_time1; +reg [14:0] main_litedramcore_nop_a = 15'd0; +reg [2:0] main_litedramcore_nop_ba = 3'd0; +wire [1:0] main_litedramcore_nphases; +wire main_litedramcore_odt; +reg main_litedramcore_phaseinjector0_address_re = 1'd0; +reg [14:0] main_litedramcore_phaseinjector0_address_storage = 15'd0; +reg main_litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0; +wire main_litedramcore_phaseinjector0_command_issue_r; +reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector0_command_re = 1'd0; +reg [7:0] main_litedramcore_phaseinjector0_command_storage = 8'd0; +wire main_litedramcore_phaseinjector0_csrfield_cas; +wire main_litedramcore_phaseinjector0_csrfield_cs; +wire main_litedramcore_phaseinjector0_csrfield_cs_bottom; +wire main_litedramcore_phaseinjector0_csrfield_cs_top; +wire main_litedramcore_phaseinjector0_csrfield_ras; +wire main_litedramcore_phaseinjector0_csrfield_rden; +wire main_litedramcore_phaseinjector0_csrfield_we; +wire main_litedramcore_phaseinjector0_csrfield_wren; +reg main_litedramcore_phaseinjector0_rddata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector0_rddata_we; +reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector1_address_re = 1'd0; +reg [14:0] main_litedramcore_phaseinjector1_address_storage = 15'd0; +reg main_litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0; +wire main_litedramcore_phaseinjector1_command_issue_r; +reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector1_command_re = 1'd0; +reg [7:0] main_litedramcore_phaseinjector1_command_storage = 8'd0; +wire main_litedramcore_phaseinjector1_csrfield_cas; +wire main_litedramcore_phaseinjector1_csrfield_cs; +wire main_litedramcore_phaseinjector1_csrfield_cs_bottom; +wire main_litedramcore_phaseinjector1_csrfield_cs_top; +wire main_litedramcore_phaseinjector1_csrfield_ras; +wire main_litedramcore_phaseinjector1_csrfield_rden; +wire main_litedramcore_phaseinjector1_csrfield_we; +wire main_litedramcore_phaseinjector1_csrfield_wren; +reg main_litedramcore_phaseinjector1_rddata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector1_rddata_we; +reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector2_address_re = 1'd0; +reg [14:0] main_litedramcore_phaseinjector2_address_storage = 15'd0; +reg main_litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0; +wire main_litedramcore_phaseinjector2_command_issue_r; +reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector2_command_re = 1'd0; +reg [7:0] main_litedramcore_phaseinjector2_command_storage = 8'd0; +wire main_litedramcore_phaseinjector2_csrfield_cas; +wire main_litedramcore_phaseinjector2_csrfield_cs; +wire main_litedramcore_phaseinjector2_csrfield_cs_bottom; +wire main_litedramcore_phaseinjector2_csrfield_cs_top; +wire main_litedramcore_phaseinjector2_csrfield_ras; +wire main_litedramcore_phaseinjector2_csrfield_rden; +wire main_litedramcore_phaseinjector2_csrfield_we; +wire main_litedramcore_phaseinjector2_csrfield_wren; +reg main_litedramcore_phaseinjector2_rddata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector2_rddata_we; +reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector3_address_re = 1'd0; +reg [14:0] main_litedramcore_phaseinjector3_address_storage = 15'd0; +reg main_litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0; +wire main_litedramcore_phaseinjector3_command_issue_r; +reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector3_command_re = 1'd0; +reg [7:0] main_litedramcore_phaseinjector3_command_storage = 8'd0; +wire main_litedramcore_phaseinjector3_csrfield_cas; +wire main_litedramcore_phaseinjector3_csrfield_cs; +wire main_litedramcore_phaseinjector3_csrfield_cs_bottom; +wire main_litedramcore_phaseinjector3_csrfield_cs_top; +wire main_litedramcore_phaseinjector3_csrfield_ras; +wire main_litedramcore_phaseinjector3_csrfield_rden; +wire main_litedramcore_phaseinjector3_csrfield_we; +wire main_litedramcore_phaseinjector3_csrfield_wren; +reg main_litedramcore_phaseinjector3_rddata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector3_rddata_we; +reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0; +reg main_litedramcore_postponer_count = 1'd0; +wire main_litedramcore_postponer_req_i; +reg main_litedramcore_postponer_req_o = 1'd0; +wire main_litedramcore_ras_allowed; +wire [1:0] main_litedramcore_rdphase; +reg main_litedramcore_re = 1'd0; +wire main_litedramcore_read_available; +wire main_litedramcore_reset_n; +wire main_litedramcore_sel; +reg main_litedramcore_sequencer_count = 1'd0; +wire main_litedramcore_sequencer_done0; +reg main_litedramcore_sequencer_done1 = 1'd0; +reg main_litedramcore_sequencer_start0 = 1'd0; +wire main_litedramcore_sequencer_start1; +reg [5:0] main_litedramcore_sequencer_trigger = 6'd0; +wire main_litedramcore_slave_p0_act_n; +wire [14:0] main_litedramcore_slave_p0_address; +wire [2:0] main_litedramcore_slave_p0_bank; +wire main_litedramcore_slave_p0_cas_n; +wire main_litedramcore_slave_p0_cke; +wire main_litedramcore_slave_p0_cs_n; +wire main_litedramcore_slave_p0_odt; +wire main_litedramcore_slave_p0_ras_n; +reg [31:0] main_litedramcore_slave_p0_rddata = 32'd0; +wire main_litedramcore_slave_p0_rddata_en; +reg main_litedramcore_slave_p0_rddata_valid = 1'd0; +wire main_litedramcore_slave_p0_reset_n; +wire main_litedramcore_slave_p0_we_n; +wire [31:0] main_litedramcore_slave_p0_wrdata; +wire main_litedramcore_slave_p0_wrdata_en; +wire [3:0] main_litedramcore_slave_p0_wrdata_mask; +wire main_litedramcore_slave_p1_act_n; +wire [14:0] main_litedramcore_slave_p1_address; +wire [2:0] main_litedramcore_slave_p1_bank; +wire main_litedramcore_slave_p1_cas_n; +wire main_litedramcore_slave_p1_cke; +wire main_litedramcore_slave_p1_cs_n; +wire main_litedramcore_slave_p1_odt; +wire main_litedramcore_slave_p1_ras_n; +reg [31:0] main_litedramcore_slave_p1_rddata = 32'd0; +wire main_litedramcore_slave_p1_rddata_en; +reg main_litedramcore_slave_p1_rddata_valid = 1'd0; +wire main_litedramcore_slave_p1_reset_n; +wire main_litedramcore_slave_p1_we_n; +wire [31:0] main_litedramcore_slave_p1_wrdata; +wire main_litedramcore_slave_p1_wrdata_en; +wire [3:0] main_litedramcore_slave_p1_wrdata_mask; +wire main_litedramcore_slave_p2_act_n; +wire [14:0] main_litedramcore_slave_p2_address; +wire [2:0] main_litedramcore_slave_p2_bank; +wire main_litedramcore_slave_p2_cas_n; +wire main_litedramcore_slave_p2_cke; +wire main_litedramcore_slave_p2_cs_n; +wire main_litedramcore_slave_p2_odt; +wire main_litedramcore_slave_p2_ras_n; +reg [31:0] main_litedramcore_slave_p2_rddata = 32'd0; +wire main_litedramcore_slave_p2_rddata_en; +reg main_litedramcore_slave_p2_rddata_valid = 1'd0; +wire main_litedramcore_slave_p2_reset_n; +wire main_litedramcore_slave_p2_we_n; +wire [31:0] main_litedramcore_slave_p2_wrdata; +wire main_litedramcore_slave_p2_wrdata_en; +wire [3:0] main_litedramcore_slave_p2_wrdata_mask; +wire main_litedramcore_slave_p3_act_n; +wire [14:0] main_litedramcore_slave_p3_address; +wire [2:0] main_litedramcore_slave_p3_bank; +wire main_litedramcore_slave_p3_cas_n; +wire main_litedramcore_slave_p3_cke; +wire main_litedramcore_slave_p3_cs_n; +wire main_litedramcore_slave_p3_odt; +wire main_litedramcore_slave_p3_ras_n; +reg [31:0] main_litedramcore_slave_p3_rddata = 32'd0; +wire main_litedramcore_slave_p3_rddata_en; +reg main_litedramcore_slave_p3_rddata_valid = 1'd0; +wire main_litedramcore_slave_p3_reset_n; +wire main_litedramcore_slave_p3_we_n; +wire [31:0] main_litedramcore_slave_p3_wrdata; +wire main_litedramcore_slave_p3_wrdata_en; +wire [3:0] main_litedramcore_slave_p3_wrdata_mask; +reg [1:0] main_litedramcore_steerer0 = 2'd0; +reg [1:0] main_litedramcore_steerer1 = 2'd0; +reg main_litedramcore_steerer10 = 1'd1; +reg main_litedramcore_steerer11 = 1'd1; +reg [1:0] main_litedramcore_steerer2 = 2'd0; +reg [1:0] main_litedramcore_steerer3 = 2'd0; +reg main_litedramcore_steerer4 = 1'd1; +reg main_litedramcore_steerer5 = 1'd1; +reg main_litedramcore_steerer6 = 1'd1; +reg main_litedramcore_steerer7 = 1'd1; +reg main_litedramcore_steerer8 = 1'd1; +reg main_litedramcore_steerer9 = 1'd1; +reg [3:0] main_litedramcore_storage = 4'd1; +reg main_litedramcore_tccdcon_count = 1'd0; (* dont_touch = "true" *) -reg litedramcore_trrdcon_ready = 1'd0; -reg litedramcore_trrdcon_count = 1'd0; -wire litedramcore_tfawcon_valid; +reg main_litedramcore_tccdcon_ready = 1'd0; +wire main_litedramcore_tccdcon_valid; +wire [2:0] main_litedramcore_tfawcon_count; (* dont_touch = "true" *) -reg litedramcore_tfawcon_ready = 1'd1; -wire [2:0] litedramcore_tfawcon_count; -reg [4:0] litedramcore_tfawcon_window = 5'd0; -wire litedramcore_tccdcon_valid; +reg main_litedramcore_tfawcon_ready = 1'd1; +wire main_litedramcore_tfawcon_valid; +reg [4:0] main_litedramcore_tfawcon_window = 5'd0; +reg [4:0] main_litedramcore_time0 = 5'd0; +reg [3:0] main_litedramcore_time1 = 4'd0; +wire [9:0] main_litedramcore_timer_count0; +reg [9:0] main_litedramcore_timer_count1 = 10'd781; +wire main_litedramcore_timer_done0; +wire main_litedramcore_timer_done1; +wire main_litedramcore_timer_wait; +reg main_litedramcore_trrdcon_count = 1'd0; (* dont_touch = "true" *) -reg litedramcore_tccdcon_ready = 1'd0; -reg litedramcore_tccdcon_count = 1'd0; -wire litedramcore_twtrcon_valid; +reg main_litedramcore_trrdcon_ready = 1'd0; +wire main_litedramcore_trrdcon_valid; +reg [2:0] main_litedramcore_twtrcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_twtrcon_ready = 1'd0; -reg [2:0] litedramcore_twtrcon_count = 3'd0; -wire litedramcore_read_available; -wire litedramcore_write_available; -reg litedramcore_en0 = 1'd0; -wire litedramcore_max_time0; -reg [4:0] litedramcore_time0 = 5'd0; -reg litedramcore_en1 = 1'd0; -wire litedramcore_max_time1; -reg [3:0] litedramcore_time1 = 4'd0; -wire litedramcore_go_to_refresh; -reg init_done_storage = 1'd0; -reg init_done_re = 1'd0; -reg init_error_storage = 1'd0; -reg init_error_re = 1'd0; -wire [29:0] wb_bus_adr; -wire [31:0] wb_bus_dat_w; -wire [31:0] wb_bus_dat_r; -wire [3:0] wb_bus_sel; -wire wb_bus_cyc; -wire wb_bus_stb; -wire wb_bus_ack; -wire wb_bus_we; -wire [2:0] wb_bus_cti; -wire [1:0] wb_bus_bte; -wire wb_bus_err; -wire user_enable; -wire user_port_cmd_valid; -wire user_port_cmd_ready; -wire user_port_cmd_payload_we; -wire [24:0] user_port_cmd_payload_addr; -wire user_port_wdata_valid; -wire user_port_wdata_ready; -wire [127:0] user_port_wdata_payload_data; -wire [15:0] user_port_wdata_payload_we; -wire user_port_rdata_valid; -wire user_port_rdata_ready; -wire [127:0] user_port_rdata_payload_data; -reg [13:0] litedramcore_adr = 14'd0; -reg litedramcore_we = 1'd0; -reg [31:0] litedramcore_dat_w = 32'd0; -wire [31:0] litedramcore_dat_r; -wire [29:0] litedramcore_wishbone_adr; -wire [31:0] litedramcore_wishbone_dat_w; -reg [31:0] litedramcore_wishbone_dat_r = 32'd0; -wire [3:0] litedramcore_wishbone_sel; -wire litedramcore_wishbone_cyc; -wire litedramcore_wishbone_stb; -reg litedramcore_wishbone_ack = 1'd0; -wire litedramcore_wishbone_we; -wire [2:0] litedramcore_wishbone_cti; -wire [1:0] litedramcore_wishbone_bte; -reg litedramcore_wishbone_err = 1'd0; -wire [13:0] interface0_bank_bus_adr; -wire interface0_bank_bus_we; -wire [31:0] interface0_bank_bus_dat_w; -reg [31:0] interface0_bank_bus_dat_r = 32'd0; -reg csrbank0_init_done0_re = 1'd0; -wire csrbank0_init_done0_r; -reg csrbank0_init_done0_we = 1'd0; -wire csrbank0_init_done0_w; -reg csrbank0_init_error0_re = 1'd0; -wire csrbank0_init_error0_r; -reg csrbank0_init_error0_we = 1'd0; -wire csrbank0_init_error0_w; -wire csrbank0_sel; -wire [13:0] interface1_bank_bus_adr; -wire interface1_bank_bus_we; -wire [31:0] interface1_bank_bus_dat_w; -reg [31:0] interface1_bank_bus_dat_r = 32'd0; -reg csrbank1_rst0_re = 1'd0; -wire csrbank1_rst0_r; -reg csrbank1_rst0_we = 1'd0; -wire csrbank1_rst0_w; -reg csrbank1_dly_sel0_re = 1'd0; -wire [1:0] csrbank1_dly_sel0_r; -reg csrbank1_dly_sel0_we = 1'd0; -wire [1:0] csrbank1_dly_sel0_w; -reg csrbank1_half_sys8x_taps0_re = 1'd0; -wire [4:0] csrbank1_half_sys8x_taps0_r; -reg csrbank1_half_sys8x_taps0_we = 1'd0; -wire [4:0] csrbank1_half_sys8x_taps0_w; -reg csrbank1_wlevel_en0_re = 1'd0; -wire csrbank1_wlevel_en0_r; -reg csrbank1_wlevel_en0_we = 1'd0; -wire csrbank1_wlevel_en0_w; -reg csrbank1_rdphase0_re = 1'd0; -wire [1:0] csrbank1_rdphase0_r; -reg csrbank1_rdphase0_we = 1'd0; -wire [1:0] csrbank1_rdphase0_w; -reg csrbank1_wrphase0_re = 1'd0; -wire [1:0] csrbank1_wrphase0_r; -reg csrbank1_wrphase0_we = 1'd0; -wire [1:0] csrbank1_wrphase0_w; -wire csrbank1_sel; -wire [13:0] interface2_bank_bus_adr; -wire interface2_bank_bus_we; -wire [31:0] interface2_bank_bus_dat_w; -reg [31:0] interface2_bank_bus_dat_r = 32'd0; -reg csrbank2_dfii_control0_re = 1'd0; -wire [3:0] csrbank2_dfii_control0_r; -reg csrbank2_dfii_control0_we = 1'd0; -wire [3:0] csrbank2_dfii_control0_w; -reg csrbank2_dfii_pi0_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi0_command0_r; -reg csrbank2_dfii_pi0_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi0_command0_w; -reg csrbank2_dfii_pi0_address0_re = 1'd0; -wire [14:0] csrbank2_dfii_pi0_address0_r; -reg csrbank2_dfii_pi0_address0_we = 1'd0; -wire [14:0] csrbank2_dfii_pi0_address0_w; -reg csrbank2_dfii_pi0_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi0_baddress0_r; -reg csrbank2_dfii_pi0_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi0_baddress0_w; -reg csrbank2_dfii_pi0_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata0_r; -reg csrbank2_dfii_pi0_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata0_w; -reg csrbank2_dfii_pi0_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata_r; -reg csrbank2_dfii_pi0_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata_w; -reg csrbank2_dfii_pi1_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi1_command0_r; -reg csrbank2_dfii_pi1_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi1_command0_w; -reg csrbank2_dfii_pi1_address0_re = 1'd0; -wire [14:0] csrbank2_dfii_pi1_address0_r; -reg csrbank2_dfii_pi1_address0_we = 1'd0; -wire [14:0] csrbank2_dfii_pi1_address0_w; -reg csrbank2_dfii_pi1_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi1_baddress0_r; -reg csrbank2_dfii_pi1_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi1_baddress0_w; -reg csrbank2_dfii_pi1_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata0_r; -reg csrbank2_dfii_pi1_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata0_w; -reg csrbank2_dfii_pi1_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata_r; -reg csrbank2_dfii_pi1_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata_w; -reg csrbank2_dfii_pi2_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi2_command0_r; -reg csrbank2_dfii_pi2_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi2_command0_w; -reg csrbank2_dfii_pi2_address0_re = 1'd0; -wire [14:0] csrbank2_dfii_pi2_address0_r; -reg csrbank2_dfii_pi2_address0_we = 1'd0; -wire [14:0] csrbank2_dfii_pi2_address0_w; -reg csrbank2_dfii_pi2_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi2_baddress0_r; -reg csrbank2_dfii_pi2_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi2_baddress0_w; -reg csrbank2_dfii_pi2_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi2_wrdata0_r; -reg csrbank2_dfii_pi2_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi2_wrdata0_w; -reg csrbank2_dfii_pi2_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi2_rddata_r; -reg csrbank2_dfii_pi2_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi2_rddata_w; -reg csrbank2_dfii_pi3_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi3_command0_r; -reg csrbank2_dfii_pi3_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi3_command0_w; -reg csrbank2_dfii_pi3_address0_re = 1'd0; -wire [14:0] csrbank2_dfii_pi3_address0_r; -reg csrbank2_dfii_pi3_address0_we = 1'd0; -wire [14:0] csrbank2_dfii_pi3_address0_w; -reg csrbank2_dfii_pi3_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi3_baddress0_r; -reg csrbank2_dfii_pi3_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi3_baddress0_w; -reg csrbank2_dfii_pi3_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi3_wrdata0_r; -reg csrbank2_dfii_pi3_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi3_wrdata0_w; -reg csrbank2_dfii_pi3_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi3_rddata_r; -reg csrbank2_dfii_pi3_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi3_rddata_w; -wire csrbank2_sel; -wire [13:0] csr_interconnect_adr; -wire csr_interconnect_we; -wire [31:0] csr_interconnect_dat_w; -wire [31:0] csr_interconnect_dat_r; -wire litedramcore_reset0; -wire litedramcore_reset1; -wire litedramcore_reset2; -wire litedramcore_reset3; -wire litedramcore_reset4; -wire litedramcore_reset5; -wire litedramcore_reset6; -wire litedramcore_reset7; -wire litedramcore_pll_fb; -reg [1:0] litedramcore_refresher_state = 2'd0; -reg [1:0] litedramcore_refresher_next_state = 2'd0; -reg [3:0] litedramcore_bankmachine0_state = 4'd0; -reg [3:0] litedramcore_bankmachine0_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine1_state = 4'd0; -reg [3:0] litedramcore_bankmachine1_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine2_state = 4'd0; -reg [3:0] litedramcore_bankmachine2_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine3_state = 4'd0; -reg [3:0] litedramcore_bankmachine3_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine4_state = 4'd0; -reg [3:0] litedramcore_bankmachine4_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine5_state = 4'd0; -reg [3:0] litedramcore_bankmachine5_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine6_state = 4'd0; -reg [3:0] litedramcore_bankmachine6_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine7_state = 4'd0; -reg [3:0] litedramcore_bankmachine7_next_state = 4'd0; -reg [3:0] litedramcore_multiplexer_state = 4'd0; -reg [3:0] litedramcore_multiplexer_next_state = 4'd0; -wire litedramcore_roundrobin0_request; -wire litedramcore_roundrobin0_grant; -wire litedramcore_roundrobin0_ce; -wire litedramcore_roundrobin1_request; -wire litedramcore_roundrobin1_grant; -wire litedramcore_roundrobin1_ce; -wire litedramcore_roundrobin2_request; -wire litedramcore_roundrobin2_grant; -wire litedramcore_roundrobin2_ce; -wire litedramcore_roundrobin3_request; -wire litedramcore_roundrobin3_grant; -wire litedramcore_roundrobin3_ce; -wire litedramcore_roundrobin4_request; -wire litedramcore_roundrobin4_grant; -wire litedramcore_roundrobin4_ce; -wire litedramcore_roundrobin5_request; -wire litedramcore_roundrobin5_grant; -wire litedramcore_roundrobin5_ce; -wire litedramcore_roundrobin6_request; -wire litedramcore_roundrobin6_grant; -wire litedramcore_roundrobin6_ce; -wire litedramcore_roundrobin7_request; -wire litedramcore_roundrobin7_grant; -wire litedramcore_roundrobin7_ce; -reg litedramcore_locked0 = 1'd0; -reg litedramcore_locked1 = 1'd0; -reg litedramcore_locked2 = 1'd0; -reg litedramcore_locked3 = 1'd0; -reg litedramcore_locked4 = 1'd0; -reg litedramcore_locked5 = 1'd0; -reg litedramcore_locked6 = 1'd0; -reg litedramcore_locked7 = 1'd0; -reg litedramcore_new_master_wdata_ready0 = 1'd0; -reg litedramcore_new_master_wdata_ready1 = 1'd0; -reg litedramcore_new_master_rdata_valid0 = 1'd0; -reg litedramcore_new_master_rdata_valid1 = 1'd0; -reg litedramcore_new_master_rdata_valid2 = 1'd0; -reg litedramcore_new_master_rdata_valid3 = 1'd0; -reg litedramcore_new_master_rdata_valid4 = 1'd0; -reg litedramcore_new_master_rdata_valid5 = 1'd0; -reg litedramcore_new_master_rdata_valid6 = 1'd0; -reg litedramcore_new_master_rdata_valid7 = 1'd0; -reg litedramcore_new_master_rdata_valid8 = 1'd0; -reg [1:0] litedramcore_state = 2'd0; -reg [1:0] litedramcore_next_state = 2'd0; -reg [31:0] litedramcore_dat_w_next_value0 = 32'd0; -reg litedramcore_dat_w_next_value_ce0 = 1'd0; -reg [13:0] litedramcore_adr_next_value1 = 14'd0; -reg litedramcore_adr_next_value_ce1 = 1'd0; -reg litedramcore_we_next_value2 = 1'd0; -reg litedramcore_we_next_value_ce2 = 1'd0; -reg rhs_array_muxed0 = 1'd0; -reg [14:0] rhs_array_muxed1 = 15'd0; -reg [2:0] rhs_array_muxed2 = 3'd0; -reg rhs_array_muxed3 = 1'd0; -reg rhs_array_muxed4 = 1'd0; -reg rhs_array_muxed5 = 1'd0; -reg t_array_muxed0 = 1'd0; -reg t_array_muxed1 = 1'd0; -reg t_array_muxed2 = 1'd0; -reg rhs_array_muxed6 = 1'd0; -reg [14:0] rhs_array_muxed7 = 15'd0; -reg [2:0] rhs_array_muxed8 = 3'd0; -reg rhs_array_muxed9 = 1'd0; -reg rhs_array_muxed10 = 1'd0; -reg rhs_array_muxed11 = 1'd0; -reg t_array_muxed3 = 1'd0; -reg t_array_muxed4 = 1'd0; -reg t_array_muxed5 = 1'd0; -reg [21:0] rhs_array_muxed12 = 22'd0; -reg rhs_array_muxed13 = 1'd0; -reg rhs_array_muxed14 = 1'd0; -reg [21:0] rhs_array_muxed15 = 22'd0; -reg rhs_array_muxed16 = 1'd0; -reg rhs_array_muxed17 = 1'd0; -reg [21:0] rhs_array_muxed18 = 22'd0; -reg rhs_array_muxed19 = 1'd0; -reg rhs_array_muxed20 = 1'd0; -reg [21:0] rhs_array_muxed21 = 22'd0; -reg rhs_array_muxed22 = 1'd0; -reg rhs_array_muxed23 = 1'd0; -reg [21:0] rhs_array_muxed24 = 22'd0; -reg rhs_array_muxed25 = 1'd0; -reg rhs_array_muxed26 = 1'd0; -reg [21:0] rhs_array_muxed27 = 22'd0; -reg rhs_array_muxed28 = 1'd0; -reg rhs_array_muxed29 = 1'd0; -reg [21:0] rhs_array_muxed30 = 22'd0; -reg rhs_array_muxed31 = 1'd0; -reg rhs_array_muxed32 = 1'd0; -reg [21:0] rhs_array_muxed33 = 22'd0; -reg rhs_array_muxed34 = 1'd0; -reg rhs_array_muxed35 = 1'd0; -reg [2:0] array_muxed0 = 3'd0; -reg [14:0] array_muxed1 = 15'd0; -reg array_muxed2 = 1'd0; -reg array_muxed3 = 1'd0; -reg array_muxed4 = 1'd0; -reg array_muxed5 = 1'd0; -reg array_muxed6 = 1'd0; -reg [2:0] array_muxed7 = 3'd0; -reg [14:0] array_muxed8 = 15'd0; -reg array_muxed9 = 1'd0; -reg array_muxed10 = 1'd0; -reg array_muxed11 = 1'd0; -reg array_muxed12 = 1'd0; -reg array_muxed13 = 1'd0; -reg [2:0] array_muxed14 = 3'd0; -reg [14:0] array_muxed15 = 15'd0; -reg array_muxed16 = 1'd0; -reg array_muxed17 = 1'd0; -reg array_muxed18 = 1'd0; -reg array_muxed19 = 1'd0; -reg array_muxed20 = 1'd0; -reg [2:0] array_muxed21 = 3'd0; -reg [14:0] array_muxed22 = 15'd0; -reg array_muxed23 = 1'd0; -reg array_muxed24 = 1'd0; -reg array_muxed25 = 1'd0; -reg array_muxed26 = 1'd0; -reg array_muxed27 = 1'd0; -wire xilinxasyncresetsynchronizerimpl0; -wire xilinxasyncresetsynchronizerimpl0_rst_meta; -wire xilinxasyncresetsynchronizerimpl1; -wire xilinxasyncresetsynchronizerimpl1_rst_meta; -wire xilinxasyncresetsynchronizerimpl2; -wire xilinxasyncresetsynchronizerimpl2_rst_meta; -wire xilinxasyncresetsynchronizerimpl2_expr; -wire xilinxasyncresetsynchronizerimpl3; -wire xilinxasyncresetsynchronizerimpl3_rst_meta; -wire xilinxasyncresetsynchronizerimpl3_expr; +reg main_litedramcore_twtrcon_ready = 1'd0; +wire main_litedramcore_twtrcon_valid; +wire main_litedramcore_wants_refresh; +wire main_litedramcore_wants_zqcs; +wire main_litedramcore_write_available; +reg main_litedramcore_zqcs_executer_done = 1'd0; +reg main_litedramcore_zqcs_executer_start = 1'd0; +reg [4:0] main_litedramcore_zqcs_executer_trigger = 5'd0; +wire [26:0] main_litedramcore_zqcs_timer_count0; +reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999; +wire main_litedramcore_zqcs_timer_done0; +wire main_litedramcore_zqcs_timer_done1; +wire main_litedramcore_zqcs_timer_wait; +wire main_locked; +reg main_power_down = 1'd0; +wire main_reset; +reg [3:0] main_reset_counter = 4'd15; +reg main_rst = 1'd0; +wire main_user_enable; +wire [24:0] main_user_port_cmd_payload_addr; +wire main_user_port_cmd_payload_we; +wire main_user_port_cmd_ready; +wire main_user_port_cmd_valid; +wire [127:0] main_user_port_rdata_payload_data; +wire main_user_port_rdata_ready; +wire main_user_port_rdata_valid; +wire [127:0] main_user_port_wdata_payload_data; +wire [15:0] main_user_port_wdata_payload_we; +wire main_user_port_wdata_ready; +wire main_user_port_wdata_valid; +wire main_wb_bus_ack; +wire [29:0] main_wb_bus_adr; +wire [1:0] main_wb_bus_bte; +wire [2:0] main_wb_bus_cti; +wire main_wb_bus_cyc; +wire [31:0] main_wb_bus_dat_r; +wire [31:0] main_wb_bus_dat_w; +wire main_wb_bus_err; +wire [3:0] main_wb_bus_sel; +wire main_wb_bus_stb; +wire main_wb_bus_we; +wire sys4x_clk; +wire sys4x_dqs_clk; +wire sys_clk; +wire sys_rst; //------------------------------------------------------------------------------ // Combinatorial Logic //------------------------------------------------------------------------------ -assign init_done = init_done_storage; -assign init_error = init_error_storage; -assign wb_bus_adr = wb_ctrl_adr; -assign wb_bus_dat_w = wb_ctrl_dat_w; -assign wb_ctrl_dat_r = wb_bus_dat_r; -assign wb_bus_sel = wb_ctrl_sel; -assign wb_bus_cyc = wb_ctrl_cyc; -assign wb_bus_stb = wb_ctrl_stb; -assign wb_ctrl_ack = wb_bus_ack; -assign wb_bus_we = wb_ctrl_we; -assign wb_bus_cti = wb_ctrl_cti; -assign wb_bus_bte = wb_ctrl_bte; -assign wb_ctrl_err = wb_bus_err; +assign init_done = main_init_done_storage; +assign init_error = main_init_error_storage; +assign main_wb_bus_adr = wb_ctrl_adr; +assign main_wb_bus_dat_w = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = main_wb_bus_dat_r; +assign main_wb_bus_sel = wb_ctrl_sel; +assign main_wb_bus_cyc = wb_ctrl_cyc; +assign main_wb_bus_stb = wb_ctrl_stb; +assign wb_ctrl_ack = main_wb_bus_ack; +assign main_wb_bus_we = wb_ctrl_we; +assign main_wb_bus_cti = wb_ctrl_cti; +assign main_wb_bus_bte = wb_ctrl_bte; +assign wb_ctrl_err = main_wb_bus_err; assign user_clk = sys_clk; assign user_rst = sys_rst; -assign user_enable = 1'd1; -assign user_port_cmd_valid = (user_port_native_0_cmd_valid & user_enable); -assign user_port_native_0_cmd_ready = (user_port_cmd_ready & user_enable); -assign user_port_cmd_payload_we = user_port_native_0_cmd_we; -assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr; -assign user_port_wdata_valid = (user_port_native_0_wdata_valid & user_enable); -assign user_port_native_0_wdata_ready = (user_port_wdata_ready & user_enable); -assign user_port_wdata_payload_we = user_port_native_0_wdata_we; -assign user_port_wdata_payload_data = user_port_native_0_wdata_data; -assign user_port_native_0_rdata_valid = (user_port_rdata_valid & user_enable); -assign user_port_rdata_ready = (user_port_native_0_rdata_ready & user_enable); -assign user_port_native_0_rdata_data = user_port_rdata_payload_data; -assign reset = (rst | rst_1); -assign pll_locked = locked; -assign clkin = clk; -assign iodelay_clk = clkout_buf0; -assign sys_clk = clkout_buf1; -assign sys4x_clk = clkout_buf2; -assign sys4x_dqs_clk = clkout_buf3; -assign ddram_ba = a7ddrphy_pads_ba; -assign a7ddrphy_dqs_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dqs_oe) | a7ddrphy_dqs_postamble); -assign a7ddrphy_dq_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dq_oe) | a7ddrphy_dqs_postamble); -always @(*) begin - a7ddrphy_dfi_p0_rddata <= 32'd0; - a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0]; - a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1]; - a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0]; - a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1]; - a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0]; - a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1]; - a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0]; - a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1]; - a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0]; - a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1]; - a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0]; - a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1]; - a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0]; - a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1]; - a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0]; - a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1]; - a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0]; - a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1]; - a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0]; - a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1]; - a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0]; - a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1]; - a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0]; - a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1]; - a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0]; - a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1]; - a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0]; - a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1]; - a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0]; - a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1]; - a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0]; - a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1]; -end -always @(*) begin - a7ddrphy_dfi_p1_rddata <= 32'd0; - a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2]; - a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3]; - a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2]; - a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3]; - a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2]; - a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3]; - a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2]; - a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3]; - a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2]; - a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3]; - a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2]; - a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3]; - a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2]; - a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3]; - a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2]; - a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3]; - a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2]; - a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3]; - a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2]; - a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3]; - a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2]; - a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3]; - a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2]; - a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3]; - a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2]; - a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3]; - a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2]; - a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3]; - a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2]; - a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3]; - a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2]; - a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3]; -end -always @(*) begin - a7ddrphy_dfi_p2_rddata <= 32'd0; - a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4]; - a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5]; - a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4]; - a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5]; - a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4]; - a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5]; - a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4]; - a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5]; - a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4]; - a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5]; - a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4]; - a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5]; - a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4]; - a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5]; - a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4]; - a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5]; - a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4]; - a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5]; - a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4]; - a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5]; - a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4]; - a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5]; - a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4]; - a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5]; - a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4]; - a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5]; - a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4]; - a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5]; - a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4]; - a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5]; - a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4]; - a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5]; -end -always @(*) begin - a7ddrphy_dfi_p3_rddata <= 32'd0; - a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6]; - a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7]; - a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6]; - a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7]; - a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6]; - a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7]; - a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6]; - a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7]; - a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6]; - a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7]; - a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6]; - a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7]; - a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6]; - a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7]; - a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6]; - a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7]; - a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6]; - a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7]; - a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6]; - a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7]; - a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6]; - a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7]; - a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6]; - a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7]; - a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6]; - a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7]; - a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6]; - a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7]; - a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6]; - a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7]; - a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6]; - a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7]; -end -assign a7ddrphy_dfi_p0_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); -assign a7ddrphy_dfi_p1_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); -assign a7ddrphy_dfi_p2_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); -assign a7ddrphy_dfi_p3_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); -assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en_tappeddelayline1; -always @(*) begin - a7ddrphy_dqs_oe <= 1'd0; - if (a7ddrphy_wlevel_en_storage) begin - a7ddrphy_dqs_oe <= 1'd1; - end else begin - a7ddrphy_dqs_oe <= a7ddrphy_dq_oe; - end -end -assign a7ddrphy_dqs_preamble = (a7ddrphy_wrdata_en_tappeddelayline0 & (~a7ddrphy_wrdata_en_tappeddelayline1)); -assign a7ddrphy_dqs_postamble = (a7ddrphy_wrdata_en_tappeddelayline2 & (~a7ddrphy_wrdata_en_tappeddelayline1)); -always @(*) begin - a7ddrphy_dqspattern_o0 <= 8'd0; - a7ddrphy_dqspattern_o0 <= 7'd85; - if (a7ddrphy_dqspattern0) begin - a7ddrphy_dqspattern_o0 <= 5'd21; - end - if (a7ddrphy_dqspattern1) begin - a7ddrphy_dqspattern_o0 <= 7'd84; - end - if (a7ddrphy_wlevel_en_storage) begin - a7ddrphy_dqspattern_o0 <= 1'd0; - if (a7ddrphy_wlevel_strobe_re) begin - a7ddrphy_dqspattern_o0 <= 1'd1; - end - end -end -always @(*) begin - a7ddrphy_bitslip00 <= 8'd0; - case (a7ddrphy_bitslip0_value0) +assign main_user_enable = 1'd1; +assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable); +assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable); +assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we; +assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr; +assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable); +assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable); +assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we; +assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data; +assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable); +assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable); +assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data; +assign builder_interface0_adr = main_wb_bus_adr; +assign builder_interface0_dat_w = main_wb_bus_dat_w; +assign main_wb_bus_dat_r = builder_interface0_dat_r; +assign builder_interface0_sel = main_wb_bus_sel; +assign builder_interface0_cyc = main_wb_bus_cyc; +assign builder_interface0_stb = main_wb_bus_stb; +assign main_wb_bus_ack = builder_interface0_ack; +assign builder_interface0_we = main_wb_bus_we; +assign builder_interface0_cti = main_wb_bus_cti; +assign builder_interface0_bte = main_wb_bus_bte; +assign main_wb_bus_err = builder_interface0_err; +assign main_reset = (rst | main_rst); +assign pll_locked = main_locked; +assign main_clkin = clk; +assign iodelay_clk = main_clkout_buf0; +assign sys_clk = main_clkout_buf1; +assign sys4x_clk = main_clkout_buf2; +assign sys4x_dqs_clk = main_clkout_buf3; +assign ddram_ba = main_a7ddrphy_pads_ba; +assign main_a7ddrphy_dqs_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_oe) | main_a7ddrphy_dqs_postamble); +assign main_a7ddrphy_dq_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dq_oe) | main_a7ddrphy_dqs_postamble); +always @(*) begin + main_a7ddrphy_dfi_p0_rddata <= 32'd0; + main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip04[0]; + main_a7ddrphy_dfi_p0_rddata[16] <= main_a7ddrphy_bitslip04[1]; + main_a7ddrphy_dfi_p0_rddata[1] <= main_a7ddrphy_bitslip14[0]; + main_a7ddrphy_dfi_p0_rddata[17] <= main_a7ddrphy_bitslip14[1]; + main_a7ddrphy_dfi_p0_rddata[2] <= main_a7ddrphy_bitslip22[0]; + main_a7ddrphy_dfi_p0_rddata[18] <= main_a7ddrphy_bitslip22[1]; + main_a7ddrphy_dfi_p0_rddata[3] <= main_a7ddrphy_bitslip32[0]; + main_a7ddrphy_dfi_p0_rddata[19] <= main_a7ddrphy_bitslip32[1]; + main_a7ddrphy_dfi_p0_rddata[4] <= main_a7ddrphy_bitslip42[0]; + main_a7ddrphy_dfi_p0_rddata[20] <= main_a7ddrphy_bitslip42[1]; + main_a7ddrphy_dfi_p0_rddata[5] <= main_a7ddrphy_bitslip52[0]; + main_a7ddrphy_dfi_p0_rddata[21] <= main_a7ddrphy_bitslip52[1]; + main_a7ddrphy_dfi_p0_rddata[6] <= main_a7ddrphy_bitslip62[0]; + main_a7ddrphy_dfi_p0_rddata[22] <= main_a7ddrphy_bitslip62[1]; + main_a7ddrphy_dfi_p0_rddata[7] <= main_a7ddrphy_bitslip72[0]; + main_a7ddrphy_dfi_p0_rddata[23] <= main_a7ddrphy_bitslip72[1]; + main_a7ddrphy_dfi_p0_rddata[8] <= main_a7ddrphy_bitslip82[0]; + main_a7ddrphy_dfi_p0_rddata[24] <= main_a7ddrphy_bitslip82[1]; + main_a7ddrphy_dfi_p0_rddata[9] <= main_a7ddrphy_bitslip92[0]; + main_a7ddrphy_dfi_p0_rddata[25] <= main_a7ddrphy_bitslip92[1]; + main_a7ddrphy_dfi_p0_rddata[10] <= main_a7ddrphy_bitslip102[0]; + main_a7ddrphy_dfi_p0_rddata[26] <= main_a7ddrphy_bitslip102[1]; + main_a7ddrphy_dfi_p0_rddata[11] <= main_a7ddrphy_bitslip112[0]; + main_a7ddrphy_dfi_p0_rddata[27] <= main_a7ddrphy_bitslip112[1]; + main_a7ddrphy_dfi_p0_rddata[12] <= main_a7ddrphy_bitslip122[0]; + main_a7ddrphy_dfi_p0_rddata[28] <= main_a7ddrphy_bitslip122[1]; + main_a7ddrphy_dfi_p0_rddata[13] <= main_a7ddrphy_bitslip132[0]; + main_a7ddrphy_dfi_p0_rddata[29] <= main_a7ddrphy_bitslip132[1]; + main_a7ddrphy_dfi_p0_rddata[14] <= main_a7ddrphy_bitslip142[0]; + main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip142[1]; + main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip152[0]; + main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip152[1]; +end +always @(*) begin + main_a7ddrphy_dfi_p1_rddata <= 32'd0; + main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip04[2]; + main_a7ddrphy_dfi_p1_rddata[16] <= main_a7ddrphy_bitslip04[3]; + main_a7ddrphy_dfi_p1_rddata[1] <= main_a7ddrphy_bitslip14[2]; + main_a7ddrphy_dfi_p1_rddata[17] <= main_a7ddrphy_bitslip14[3]; + main_a7ddrphy_dfi_p1_rddata[2] <= main_a7ddrphy_bitslip22[2]; + main_a7ddrphy_dfi_p1_rddata[18] <= main_a7ddrphy_bitslip22[3]; + main_a7ddrphy_dfi_p1_rddata[3] <= main_a7ddrphy_bitslip32[2]; + main_a7ddrphy_dfi_p1_rddata[19] <= main_a7ddrphy_bitslip32[3]; + main_a7ddrphy_dfi_p1_rddata[4] <= main_a7ddrphy_bitslip42[2]; + main_a7ddrphy_dfi_p1_rddata[20] <= main_a7ddrphy_bitslip42[3]; + main_a7ddrphy_dfi_p1_rddata[5] <= main_a7ddrphy_bitslip52[2]; + main_a7ddrphy_dfi_p1_rddata[21] <= main_a7ddrphy_bitslip52[3]; + main_a7ddrphy_dfi_p1_rddata[6] <= main_a7ddrphy_bitslip62[2]; + main_a7ddrphy_dfi_p1_rddata[22] <= main_a7ddrphy_bitslip62[3]; + main_a7ddrphy_dfi_p1_rddata[7] <= main_a7ddrphy_bitslip72[2]; + main_a7ddrphy_dfi_p1_rddata[23] <= main_a7ddrphy_bitslip72[3]; + main_a7ddrphy_dfi_p1_rddata[8] <= main_a7ddrphy_bitslip82[2]; + main_a7ddrphy_dfi_p1_rddata[24] <= main_a7ddrphy_bitslip82[3]; + main_a7ddrphy_dfi_p1_rddata[9] <= main_a7ddrphy_bitslip92[2]; + main_a7ddrphy_dfi_p1_rddata[25] <= main_a7ddrphy_bitslip92[3]; + main_a7ddrphy_dfi_p1_rddata[10] <= main_a7ddrphy_bitslip102[2]; + main_a7ddrphy_dfi_p1_rddata[26] <= main_a7ddrphy_bitslip102[3]; + main_a7ddrphy_dfi_p1_rddata[11] <= main_a7ddrphy_bitslip112[2]; + main_a7ddrphy_dfi_p1_rddata[27] <= main_a7ddrphy_bitslip112[3]; + main_a7ddrphy_dfi_p1_rddata[12] <= main_a7ddrphy_bitslip122[2]; + main_a7ddrphy_dfi_p1_rddata[28] <= main_a7ddrphy_bitslip122[3]; + main_a7ddrphy_dfi_p1_rddata[13] <= main_a7ddrphy_bitslip132[2]; + main_a7ddrphy_dfi_p1_rddata[29] <= main_a7ddrphy_bitslip132[3]; + main_a7ddrphy_dfi_p1_rddata[14] <= main_a7ddrphy_bitslip142[2]; + main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip142[3]; + main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip152[2]; + main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip152[3]; +end +always @(*) begin + main_a7ddrphy_dfi_p2_rddata <= 32'd0; + main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip04[4]; + main_a7ddrphy_dfi_p2_rddata[16] <= main_a7ddrphy_bitslip04[5]; + main_a7ddrphy_dfi_p2_rddata[1] <= main_a7ddrphy_bitslip14[4]; + main_a7ddrphy_dfi_p2_rddata[17] <= main_a7ddrphy_bitslip14[5]; + main_a7ddrphy_dfi_p2_rddata[2] <= main_a7ddrphy_bitslip22[4]; + main_a7ddrphy_dfi_p2_rddata[18] <= main_a7ddrphy_bitslip22[5]; + main_a7ddrphy_dfi_p2_rddata[3] <= main_a7ddrphy_bitslip32[4]; + main_a7ddrphy_dfi_p2_rddata[19] <= main_a7ddrphy_bitslip32[5]; + main_a7ddrphy_dfi_p2_rddata[4] <= main_a7ddrphy_bitslip42[4]; + main_a7ddrphy_dfi_p2_rddata[20] <= main_a7ddrphy_bitslip42[5]; + main_a7ddrphy_dfi_p2_rddata[5] <= main_a7ddrphy_bitslip52[4]; + main_a7ddrphy_dfi_p2_rddata[21] <= main_a7ddrphy_bitslip52[5]; + main_a7ddrphy_dfi_p2_rddata[6] <= main_a7ddrphy_bitslip62[4]; + main_a7ddrphy_dfi_p2_rddata[22] <= main_a7ddrphy_bitslip62[5]; + main_a7ddrphy_dfi_p2_rddata[7] <= main_a7ddrphy_bitslip72[4]; + main_a7ddrphy_dfi_p2_rddata[23] <= main_a7ddrphy_bitslip72[5]; + main_a7ddrphy_dfi_p2_rddata[8] <= main_a7ddrphy_bitslip82[4]; + main_a7ddrphy_dfi_p2_rddata[24] <= main_a7ddrphy_bitslip82[5]; + main_a7ddrphy_dfi_p2_rddata[9] <= main_a7ddrphy_bitslip92[4]; + main_a7ddrphy_dfi_p2_rddata[25] <= main_a7ddrphy_bitslip92[5]; + main_a7ddrphy_dfi_p2_rddata[10] <= main_a7ddrphy_bitslip102[4]; + main_a7ddrphy_dfi_p2_rddata[26] <= main_a7ddrphy_bitslip102[5]; + main_a7ddrphy_dfi_p2_rddata[11] <= main_a7ddrphy_bitslip112[4]; + main_a7ddrphy_dfi_p2_rddata[27] <= main_a7ddrphy_bitslip112[5]; + main_a7ddrphy_dfi_p2_rddata[12] <= main_a7ddrphy_bitslip122[4]; + main_a7ddrphy_dfi_p2_rddata[28] <= main_a7ddrphy_bitslip122[5]; + main_a7ddrphy_dfi_p2_rddata[13] <= main_a7ddrphy_bitslip132[4]; + main_a7ddrphy_dfi_p2_rddata[29] <= main_a7ddrphy_bitslip132[5]; + main_a7ddrphy_dfi_p2_rddata[14] <= main_a7ddrphy_bitslip142[4]; + main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip142[5]; + main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip152[4]; + main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip152[5]; +end +always @(*) begin + main_a7ddrphy_dfi_p3_rddata <= 32'd0; + main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip04[6]; + main_a7ddrphy_dfi_p3_rddata[16] <= main_a7ddrphy_bitslip04[7]; + main_a7ddrphy_dfi_p3_rddata[1] <= main_a7ddrphy_bitslip14[6]; + main_a7ddrphy_dfi_p3_rddata[17] <= main_a7ddrphy_bitslip14[7]; + main_a7ddrphy_dfi_p3_rddata[2] <= main_a7ddrphy_bitslip22[6]; + main_a7ddrphy_dfi_p3_rddata[18] <= main_a7ddrphy_bitslip22[7]; + main_a7ddrphy_dfi_p3_rddata[3] <= main_a7ddrphy_bitslip32[6]; + main_a7ddrphy_dfi_p3_rddata[19] <= main_a7ddrphy_bitslip32[7]; + main_a7ddrphy_dfi_p3_rddata[4] <= main_a7ddrphy_bitslip42[6]; + main_a7ddrphy_dfi_p3_rddata[20] <= main_a7ddrphy_bitslip42[7]; + main_a7ddrphy_dfi_p3_rddata[5] <= main_a7ddrphy_bitslip52[6]; + main_a7ddrphy_dfi_p3_rddata[21] <= main_a7ddrphy_bitslip52[7]; + main_a7ddrphy_dfi_p3_rddata[6] <= main_a7ddrphy_bitslip62[6]; + main_a7ddrphy_dfi_p3_rddata[22] <= main_a7ddrphy_bitslip62[7]; + main_a7ddrphy_dfi_p3_rddata[7] <= main_a7ddrphy_bitslip72[6]; + main_a7ddrphy_dfi_p3_rddata[23] <= main_a7ddrphy_bitslip72[7]; + main_a7ddrphy_dfi_p3_rddata[8] <= main_a7ddrphy_bitslip82[6]; + main_a7ddrphy_dfi_p3_rddata[24] <= main_a7ddrphy_bitslip82[7]; + main_a7ddrphy_dfi_p3_rddata[9] <= main_a7ddrphy_bitslip92[6]; + main_a7ddrphy_dfi_p3_rddata[25] <= main_a7ddrphy_bitslip92[7]; + main_a7ddrphy_dfi_p3_rddata[10] <= main_a7ddrphy_bitslip102[6]; + main_a7ddrphy_dfi_p3_rddata[26] <= main_a7ddrphy_bitslip102[7]; + main_a7ddrphy_dfi_p3_rddata[11] <= main_a7ddrphy_bitslip112[6]; + main_a7ddrphy_dfi_p3_rddata[27] <= main_a7ddrphy_bitslip112[7]; + main_a7ddrphy_dfi_p3_rddata[12] <= main_a7ddrphy_bitslip122[6]; + main_a7ddrphy_dfi_p3_rddata[28] <= main_a7ddrphy_bitslip122[7]; + main_a7ddrphy_dfi_p3_rddata[13] <= main_a7ddrphy_bitslip132[6]; + main_a7ddrphy_dfi_p3_rddata[29] <= main_a7ddrphy_bitslip132[7]; + main_a7ddrphy_dfi_p3_rddata[14] <= main_a7ddrphy_bitslip142[6]; + main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip142[7]; + main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip152[6]; + main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip152[7]; +end +assign main_a7ddrphy_dfi_p0_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dfi_p1_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dfi_p2_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dfi_p3_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dq_oe = main_a7ddrphy_wrdata_en_tappeddelayline1; +always @(*) begin + main_a7ddrphy_dqs_oe <= 1'd0; + if (main_a7ddrphy_wlevel_en_storage) begin + main_a7ddrphy_dqs_oe <= 1'd1; + end else begin + main_a7ddrphy_dqs_oe <= main_a7ddrphy_dq_oe; + end +end +assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_wrdata_en_tappeddelayline0 & (~main_a7ddrphy_wrdata_en_tappeddelayline1)); +assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_wrdata_en_tappeddelayline2 & (~main_a7ddrphy_wrdata_en_tappeddelayline1)); +always @(*) begin + main_a7ddrphy_dqspattern_o0 <= 8'd0; + main_a7ddrphy_dqspattern_o0 <= 7'd85; + if (main_a7ddrphy_dqspattern0) begin + main_a7ddrphy_dqspattern_o0 <= 5'd21; + end + if (main_a7ddrphy_dqspattern1) begin + main_a7ddrphy_dqspattern_o0 <= 7'd84; + end + if (main_a7ddrphy_wlevel_en_storage) begin + main_a7ddrphy_dqspattern_o0 <= 1'd0; + if (main_a7ddrphy_wlevel_strobe_re) begin + main_a7ddrphy_dqspattern_o0 <= 1'd1; + end + end +end +always @(*) begin + main_a7ddrphy_bitslip00 <= 8'd0; + case (main_a7ddrphy_bitslip0_value0) 1'd0: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip10 <= 8'd0; - case (a7ddrphy_bitslip1_value0) + main_a7ddrphy_bitslip10 <= 8'd0; + case (main_a7ddrphy_bitslip1_value0) 1'd0: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip01 <= 8'd0; - case (a7ddrphy_bitslip0_value1) + main_a7ddrphy_bitslip01 <= 8'd0; + case (main_a7ddrphy_bitslip0_value1) 1'd0: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip11 <= 8'd0; - case (a7ddrphy_bitslip1_value1) + main_a7ddrphy_bitslip11 <= 8'd0; + case (main_a7ddrphy_bitslip1_value1) 1'd0: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip02 <= 8'd0; - case (a7ddrphy_bitslip0_value2) + main_a7ddrphy_bitslip02 <= 8'd0; + case (main_a7ddrphy_bitslip0_value2) 1'd0: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[8:1]; end 1'd1: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[9:2]; end 2'd2: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[10:3]; end 2'd3: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[11:4]; end 3'd4: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[12:5]; end 3'd5: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[13:6]; end 3'd6: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[14:7]; end 3'd7: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip04 <= 8'd0; - case (a7ddrphy_bitslip0_value3) + main_a7ddrphy_bitslip04 <= 8'd0; + case (main_a7ddrphy_bitslip0_value3) 1'd0: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[8:1]; end 1'd1: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[9:2]; end 2'd2: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[10:3]; end 2'd3: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[11:4]; end 3'd4: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[12:5]; end 3'd5: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[13:6]; end 3'd6: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[14:7]; end 3'd7: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip12 <= 8'd0; - case (a7ddrphy_bitslip1_value2) + main_a7ddrphy_bitslip12 <= 8'd0; + case (main_a7ddrphy_bitslip1_value2) 1'd0: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[8:1]; end 1'd1: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[9:2]; end 2'd2: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[10:3]; end 2'd3: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[11:4]; end 3'd4: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[12:5]; end 3'd5: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[13:6]; end 3'd6: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[14:7]; end 3'd7: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip14 <= 8'd0; - case (a7ddrphy_bitslip1_value3) + main_a7ddrphy_bitslip14 <= 8'd0; + case (main_a7ddrphy_bitslip1_value3) 1'd0: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[8:1]; end 1'd1: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[9:2]; end 2'd2: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[10:3]; end 2'd3: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[11:4]; end 3'd4: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[12:5]; end 3'd5: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[13:6]; end 3'd6: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[14:7]; end 3'd7: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip20 <= 8'd0; - case (a7ddrphy_bitslip2_value0) + main_a7ddrphy_bitslip20 <= 8'd0; + case (main_a7ddrphy_bitslip2_value0) 1'd0: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip22 <= 8'd0; - case (a7ddrphy_bitslip2_value1) + main_a7ddrphy_bitslip22 <= 8'd0; + case (main_a7ddrphy_bitslip2_value1) 1'd0: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip30 <= 8'd0; - case (a7ddrphy_bitslip3_value0) + main_a7ddrphy_bitslip30 <= 8'd0; + case (main_a7ddrphy_bitslip3_value0) 1'd0: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip32 <= 8'd0; - case (a7ddrphy_bitslip3_value1) + main_a7ddrphy_bitslip32 <= 8'd0; + case (main_a7ddrphy_bitslip3_value1) 1'd0: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip40 <= 8'd0; - case (a7ddrphy_bitslip4_value0) + main_a7ddrphy_bitslip40 <= 8'd0; + case (main_a7ddrphy_bitslip4_value0) 1'd0: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip42 <= 8'd0; - case (a7ddrphy_bitslip4_value1) + main_a7ddrphy_bitslip42 <= 8'd0; + case (main_a7ddrphy_bitslip4_value1) 1'd0: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip50 <= 8'd0; - case (a7ddrphy_bitslip5_value0) + main_a7ddrphy_bitslip50 <= 8'd0; + case (main_a7ddrphy_bitslip5_value0) 1'd0: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip52 <= 8'd0; - case (a7ddrphy_bitslip5_value1) + main_a7ddrphy_bitslip52 <= 8'd0; + case (main_a7ddrphy_bitslip5_value1) 1'd0: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip60 <= 8'd0; - case (a7ddrphy_bitslip6_value0) + main_a7ddrphy_bitslip60 <= 8'd0; + case (main_a7ddrphy_bitslip6_value0) 1'd0: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip62 <= 8'd0; - case (a7ddrphy_bitslip6_value1) + main_a7ddrphy_bitslip62 <= 8'd0; + case (main_a7ddrphy_bitslip6_value1) 1'd0: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip70 <= 8'd0; - case (a7ddrphy_bitslip7_value0) + main_a7ddrphy_bitslip70 <= 8'd0; + case (main_a7ddrphy_bitslip7_value0) 1'd0: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip72 <= 8'd0; - case (a7ddrphy_bitslip7_value1) + main_a7ddrphy_bitslip72 <= 8'd0; + case (main_a7ddrphy_bitslip7_value1) 1'd0: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip80 <= 8'd0; - case (a7ddrphy_bitslip8_value0) + main_a7ddrphy_bitslip80 <= 8'd0; + case (main_a7ddrphy_bitslip8_value0) 1'd0: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip82 <= 8'd0; - case (a7ddrphy_bitslip8_value1) + main_a7ddrphy_bitslip82 <= 8'd0; + case (main_a7ddrphy_bitslip8_value1) 1'd0: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip90 <= 8'd0; - case (a7ddrphy_bitslip9_value0) + main_a7ddrphy_bitslip90 <= 8'd0; + case (main_a7ddrphy_bitslip9_value0) 1'd0: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip92 <= 8'd0; - case (a7ddrphy_bitslip9_value1) + main_a7ddrphy_bitslip92 <= 8'd0; + case (main_a7ddrphy_bitslip9_value1) 1'd0: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip100 <= 8'd0; - case (a7ddrphy_bitslip10_value0) + main_a7ddrphy_bitslip100 <= 8'd0; + case (main_a7ddrphy_bitslip10_value0) 1'd0: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip102 <= 8'd0; - case (a7ddrphy_bitslip10_value1) + main_a7ddrphy_bitslip102 <= 8'd0; + case (main_a7ddrphy_bitslip10_value1) 1'd0: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip110 <= 8'd0; - case (a7ddrphy_bitslip11_value0) + main_a7ddrphy_bitslip110 <= 8'd0; + case (main_a7ddrphy_bitslip11_value0) 1'd0: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip112 <= 8'd0; - case (a7ddrphy_bitslip11_value1) + main_a7ddrphy_bitslip112 <= 8'd0; + case (main_a7ddrphy_bitslip11_value1) 1'd0: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip120 <= 8'd0; - case (a7ddrphy_bitslip12_value0) + main_a7ddrphy_bitslip120 <= 8'd0; + case (main_a7ddrphy_bitslip12_value0) 1'd0: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip122 <= 8'd0; - case (a7ddrphy_bitslip12_value1) + main_a7ddrphy_bitslip122 <= 8'd0; + case (main_a7ddrphy_bitslip12_value1) 1'd0: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip130 <= 8'd0; - case (a7ddrphy_bitslip13_value0) + main_a7ddrphy_bitslip130 <= 8'd0; + case (main_a7ddrphy_bitslip13_value0) 1'd0: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip132 <= 8'd0; - case (a7ddrphy_bitslip13_value1) + main_a7ddrphy_bitslip132 <= 8'd0; + case (main_a7ddrphy_bitslip13_value1) 1'd0: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip140 <= 8'd0; - case (a7ddrphy_bitslip14_value0) + main_a7ddrphy_bitslip140 <= 8'd0; + case (main_a7ddrphy_bitslip14_value0) 1'd0: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip142 <= 8'd0; - case (a7ddrphy_bitslip14_value1) + main_a7ddrphy_bitslip142 <= 8'd0; + case (main_a7ddrphy_bitslip14_value1) 1'd0: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip150 <= 8'd0; - case (a7ddrphy_bitslip15_value0) + main_a7ddrphy_bitslip150 <= 8'd0; + case (main_a7ddrphy_bitslip15_value0) 1'd0: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip152 <= 8'd0; - case (a7ddrphy_bitslip15_value1) + main_a7ddrphy_bitslip152 <= 8'd0; + case (main_a7ddrphy_bitslip15_value1) 1'd0: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8]; - end - endcase -end -assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address; -assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank; -assign a7ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n; -assign a7ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n; -assign a7ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n; -assign a7ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n; -assign a7ddrphy_dfi_p0_cke = litedramcore_master_p0_cke; -assign a7ddrphy_dfi_p0_odt = litedramcore_master_p0_odt; -assign a7ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n; -assign a7ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n; -assign a7ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata; -assign a7ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en; -assign a7ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask; -assign a7ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en; -assign litedramcore_master_p0_rddata = a7ddrphy_dfi_p0_rddata; -assign litedramcore_master_p0_rddata_valid = a7ddrphy_dfi_p0_rddata_valid; -assign a7ddrphy_dfi_p1_address = litedramcore_master_p1_address; -assign a7ddrphy_dfi_p1_bank = litedramcore_master_p1_bank; -assign a7ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n; -assign a7ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n; -assign a7ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n; -assign a7ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n; -assign a7ddrphy_dfi_p1_cke = litedramcore_master_p1_cke; -assign a7ddrphy_dfi_p1_odt = litedramcore_master_p1_odt; -assign a7ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n; -assign a7ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n; -assign a7ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata; -assign a7ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en; -assign a7ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask; -assign a7ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en; -assign litedramcore_master_p1_rddata = a7ddrphy_dfi_p1_rddata; -assign litedramcore_master_p1_rddata_valid = a7ddrphy_dfi_p1_rddata_valid; -assign a7ddrphy_dfi_p2_address = litedramcore_master_p2_address; -assign a7ddrphy_dfi_p2_bank = litedramcore_master_p2_bank; -assign a7ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n; -assign a7ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n; -assign a7ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n; -assign a7ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n; -assign a7ddrphy_dfi_p2_cke = litedramcore_master_p2_cke; -assign a7ddrphy_dfi_p2_odt = litedramcore_master_p2_odt; -assign a7ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n; -assign a7ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n; -assign a7ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata; -assign a7ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en; -assign a7ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask; -assign a7ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en; -assign litedramcore_master_p2_rddata = a7ddrphy_dfi_p2_rddata; -assign litedramcore_master_p2_rddata_valid = a7ddrphy_dfi_p2_rddata_valid; -assign a7ddrphy_dfi_p3_address = litedramcore_master_p3_address; -assign a7ddrphy_dfi_p3_bank = litedramcore_master_p3_bank; -assign a7ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n; -assign a7ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n; -assign a7ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n; -assign a7ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n; -assign a7ddrphy_dfi_p3_cke = litedramcore_master_p3_cke; -assign a7ddrphy_dfi_p3_odt = litedramcore_master_p3_odt; -assign a7ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n; -assign a7ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n; -assign a7ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata; -assign a7ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en; -assign a7ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask; -assign a7ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en; -assign litedramcore_master_p3_rddata = a7ddrphy_dfi_p3_rddata; -assign litedramcore_master_p3_rddata_valid = a7ddrphy_dfi_p3_rddata_valid; -assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address; -assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank; -assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n; -assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n; -assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n; -assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n; -assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke; -assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt; -assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n; -assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n; -assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata; -assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en; -assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask; -assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en; -assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata; -assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid; -assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address; -assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank; -assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n; -assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n; -assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n; -assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n; -assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke; -assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt; -assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n; -assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n; -assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata; -assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en; -assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask; -assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en; -assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata; -assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid; -assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address; -assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank; -assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n; -assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n; -assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n; -assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n; -assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke; -assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt; -assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n; -assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n; -assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata; -assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en; -assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask; -assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en; -assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata; -assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid; -assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address; -assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank; -assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n; -assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n; -assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n; -assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n; -assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke; -assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt; -assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n; -assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n; -assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata; -assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en; -assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask; -assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en; -assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata; -assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; -always @(*) begin - litedramcore_csr_dfi_p0_rddata <= 32'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata; - end -end -always @(*) begin - litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; - end -end -always @(*) begin - litedramcore_csr_dfi_p1_rddata <= 32'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata; - end -end -always @(*) begin - litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[15:8]; + end + endcase +end +assign main_a7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address; +assign main_a7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank; +assign main_a7ddrphy_dfi_p0_cas_n = main_litedramcore_master_p0_cas_n; +assign main_a7ddrphy_dfi_p0_cs_n = main_litedramcore_master_p0_cs_n; +assign main_a7ddrphy_dfi_p0_ras_n = main_litedramcore_master_p0_ras_n; +assign main_a7ddrphy_dfi_p0_we_n = main_litedramcore_master_p0_we_n; +assign main_a7ddrphy_dfi_p0_cke = main_litedramcore_master_p0_cke; +assign main_a7ddrphy_dfi_p0_odt = main_litedramcore_master_p0_odt; +assign main_a7ddrphy_dfi_p0_reset_n = main_litedramcore_master_p0_reset_n; +assign main_a7ddrphy_dfi_p0_act_n = main_litedramcore_master_p0_act_n; +assign main_a7ddrphy_dfi_p0_wrdata = main_litedramcore_master_p0_wrdata; +assign main_a7ddrphy_dfi_p0_wrdata_en = main_litedramcore_master_p0_wrdata_en; +assign main_a7ddrphy_dfi_p0_wrdata_mask = main_litedramcore_master_p0_wrdata_mask; +assign main_a7ddrphy_dfi_p0_rddata_en = main_litedramcore_master_p0_rddata_en; +assign main_litedramcore_master_p0_rddata = main_a7ddrphy_dfi_p0_rddata; +assign main_litedramcore_master_p0_rddata_valid = main_a7ddrphy_dfi_p0_rddata_valid; +assign main_a7ddrphy_dfi_p1_address = main_litedramcore_master_p1_address; +assign main_a7ddrphy_dfi_p1_bank = main_litedramcore_master_p1_bank; +assign main_a7ddrphy_dfi_p1_cas_n = main_litedramcore_master_p1_cas_n; +assign main_a7ddrphy_dfi_p1_cs_n = main_litedramcore_master_p1_cs_n; +assign main_a7ddrphy_dfi_p1_ras_n = main_litedramcore_master_p1_ras_n; +assign main_a7ddrphy_dfi_p1_we_n = main_litedramcore_master_p1_we_n; +assign main_a7ddrphy_dfi_p1_cke = main_litedramcore_master_p1_cke; +assign main_a7ddrphy_dfi_p1_odt = main_litedramcore_master_p1_odt; +assign main_a7ddrphy_dfi_p1_reset_n = main_litedramcore_master_p1_reset_n; +assign main_a7ddrphy_dfi_p1_act_n = main_litedramcore_master_p1_act_n; +assign main_a7ddrphy_dfi_p1_wrdata = main_litedramcore_master_p1_wrdata; +assign main_a7ddrphy_dfi_p1_wrdata_en = main_litedramcore_master_p1_wrdata_en; +assign main_a7ddrphy_dfi_p1_wrdata_mask = main_litedramcore_master_p1_wrdata_mask; +assign main_a7ddrphy_dfi_p1_rddata_en = main_litedramcore_master_p1_rddata_en; +assign main_litedramcore_master_p1_rddata = main_a7ddrphy_dfi_p1_rddata; +assign main_litedramcore_master_p1_rddata_valid = main_a7ddrphy_dfi_p1_rddata_valid; +assign main_a7ddrphy_dfi_p2_address = main_litedramcore_master_p2_address; +assign main_a7ddrphy_dfi_p2_bank = main_litedramcore_master_p2_bank; +assign main_a7ddrphy_dfi_p2_cas_n = main_litedramcore_master_p2_cas_n; +assign main_a7ddrphy_dfi_p2_cs_n = main_litedramcore_master_p2_cs_n; +assign main_a7ddrphy_dfi_p2_ras_n = main_litedramcore_master_p2_ras_n; +assign main_a7ddrphy_dfi_p2_we_n = main_litedramcore_master_p2_we_n; +assign main_a7ddrphy_dfi_p2_cke = main_litedramcore_master_p2_cke; +assign main_a7ddrphy_dfi_p2_odt = main_litedramcore_master_p2_odt; +assign main_a7ddrphy_dfi_p2_reset_n = main_litedramcore_master_p2_reset_n; +assign main_a7ddrphy_dfi_p2_act_n = main_litedramcore_master_p2_act_n; +assign main_a7ddrphy_dfi_p2_wrdata = main_litedramcore_master_p2_wrdata; +assign main_a7ddrphy_dfi_p2_wrdata_en = main_litedramcore_master_p2_wrdata_en; +assign main_a7ddrphy_dfi_p2_wrdata_mask = main_litedramcore_master_p2_wrdata_mask; +assign main_a7ddrphy_dfi_p2_rddata_en = main_litedramcore_master_p2_rddata_en; +assign main_litedramcore_master_p2_rddata = main_a7ddrphy_dfi_p2_rddata; +assign main_litedramcore_master_p2_rddata_valid = main_a7ddrphy_dfi_p2_rddata_valid; +assign main_a7ddrphy_dfi_p3_address = main_litedramcore_master_p3_address; +assign main_a7ddrphy_dfi_p3_bank = main_litedramcore_master_p3_bank; +assign main_a7ddrphy_dfi_p3_cas_n = main_litedramcore_master_p3_cas_n; +assign main_a7ddrphy_dfi_p3_cs_n = main_litedramcore_master_p3_cs_n; +assign main_a7ddrphy_dfi_p3_ras_n = main_litedramcore_master_p3_ras_n; +assign main_a7ddrphy_dfi_p3_we_n = main_litedramcore_master_p3_we_n; +assign main_a7ddrphy_dfi_p3_cke = main_litedramcore_master_p3_cke; +assign main_a7ddrphy_dfi_p3_odt = main_litedramcore_master_p3_odt; +assign main_a7ddrphy_dfi_p3_reset_n = main_litedramcore_master_p3_reset_n; +assign main_a7ddrphy_dfi_p3_act_n = main_litedramcore_master_p3_act_n; +assign main_a7ddrphy_dfi_p3_wrdata = main_litedramcore_master_p3_wrdata; +assign main_a7ddrphy_dfi_p3_wrdata_en = main_litedramcore_master_p3_wrdata_en; +assign main_a7ddrphy_dfi_p3_wrdata_mask = main_litedramcore_master_p3_wrdata_mask; +assign main_a7ddrphy_dfi_p3_rddata_en = main_litedramcore_master_p3_rddata_en; +assign main_litedramcore_master_p3_rddata = main_a7ddrphy_dfi_p3_rddata; +assign main_litedramcore_master_p3_rddata_valid = main_a7ddrphy_dfi_p3_rddata_valid; +assign main_litedramcore_slave_p0_address = main_litedramcore_dfi_p0_address; +assign main_litedramcore_slave_p0_bank = main_litedramcore_dfi_p0_bank; +assign main_litedramcore_slave_p0_cas_n = main_litedramcore_dfi_p0_cas_n; +assign main_litedramcore_slave_p0_cs_n = main_litedramcore_dfi_p0_cs_n; +assign main_litedramcore_slave_p0_ras_n = main_litedramcore_dfi_p0_ras_n; +assign main_litedramcore_slave_p0_we_n = main_litedramcore_dfi_p0_we_n; +assign main_litedramcore_slave_p0_cke = main_litedramcore_dfi_p0_cke; +assign main_litedramcore_slave_p0_odt = main_litedramcore_dfi_p0_odt; +assign main_litedramcore_slave_p0_reset_n = main_litedramcore_dfi_p0_reset_n; +assign main_litedramcore_slave_p0_act_n = main_litedramcore_dfi_p0_act_n; +assign main_litedramcore_slave_p0_wrdata = main_litedramcore_dfi_p0_wrdata; +assign main_litedramcore_slave_p0_wrdata_en = main_litedramcore_dfi_p0_wrdata_en; +assign main_litedramcore_slave_p0_wrdata_mask = main_litedramcore_dfi_p0_wrdata_mask; +assign main_litedramcore_slave_p0_rddata_en = main_litedramcore_dfi_p0_rddata_en; +assign main_litedramcore_dfi_p0_rddata = main_litedramcore_slave_p0_rddata; +assign main_litedramcore_dfi_p0_rddata_valid = main_litedramcore_slave_p0_rddata_valid; +assign main_litedramcore_slave_p1_address = main_litedramcore_dfi_p1_address; +assign main_litedramcore_slave_p1_bank = main_litedramcore_dfi_p1_bank; +assign main_litedramcore_slave_p1_cas_n = main_litedramcore_dfi_p1_cas_n; +assign main_litedramcore_slave_p1_cs_n = main_litedramcore_dfi_p1_cs_n; +assign main_litedramcore_slave_p1_ras_n = main_litedramcore_dfi_p1_ras_n; +assign main_litedramcore_slave_p1_we_n = main_litedramcore_dfi_p1_we_n; +assign main_litedramcore_slave_p1_cke = main_litedramcore_dfi_p1_cke; +assign main_litedramcore_slave_p1_odt = main_litedramcore_dfi_p1_odt; +assign main_litedramcore_slave_p1_reset_n = main_litedramcore_dfi_p1_reset_n; +assign main_litedramcore_slave_p1_act_n = main_litedramcore_dfi_p1_act_n; +assign main_litedramcore_slave_p1_wrdata = main_litedramcore_dfi_p1_wrdata; +assign main_litedramcore_slave_p1_wrdata_en = main_litedramcore_dfi_p1_wrdata_en; +assign main_litedramcore_slave_p1_wrdata_mask = main_litedramcore_dfi_p1_wrdata_mask; +assign main_litedramcore_slave_p1_rddata_en = main_litedramcore_dfi_p1_rddata_en; +assign main_litedramcore_dfi_p1_rddata = main_litedramcore_slave_p1_rddata; +assign main_litedramcore_dfi_p1_rddata_valid = main_litedramcore_slave_p1_rddata_valid; +assign main_litedramcore_slave_p2_address = main_litedramcore_dfi_p2_address; +assign main_litedramcore_slave_p2_bank = main_litedramcore_dfi_p2_bank; +assign main_litedramcore_slave_p2_cas_n = main_litedramcore_dfi_p2_cas_n; +assign main_litedramcore_slave_p2_cs_n = main_litedramcore_dfi_p2_cs_n; +assign main_litedramcore_slave_p2_ras_n = main_litedramcore_dfi_p2_ras_n; +assign main_litedramcore_slave_p2_we_n = main_litedramcore_dfi_p2_we_n; +assign main_litedramcore_slave_p2_cke = main_litedramcore_dfi_p2_cke; +assign main_litedramcore_slave_p2_odt = main_litedramcore_dfi_p2_odt; +assign main_litedramcore_slave_p2_reset_n = main_litedramcore_dfi_p2_reset_n; +assign main_litedramcore_slave_p2_act_n = main_litedramcore_dfi_p2_act_n; +assign main_litedramcore_slave_p2_wrdata = main_litedramcore_dfi_p2_wrdata; +assign main_litedramcore_slave_p2_wrdata_en = main_litedramcore_dfi_p2_wrdata_en; +assign main_litedramcore_slave_p2_wrdata_mask = main_litedramcore_dfi_p2_wrdata_mask; +assign main_litedramcore_slave_p2_rddata_en = main_litedramcore_dfi_p2_rddata_en; +assign main_litedramcore_dfi_p2_rddata = main_litedramcore_slave_p2_rddata; +assign main_litedramcore_dfi_p2_rddata_valid = main_litedramcore_slave_p2_rddata_valid; +assign main_litedramcore_slave_p3_address = main_litedramcore_dfi_p3_address; +assign main_litedramcore_slave_p3_bank = main_litedramcore_dfi_p3_bank; +assign main_litedramcore_slave_p3_cas_n = main_litedramcore_dfi_p3_cas_n; +assign main_litedramcore_slave_p3_cs_n = main_litedramcore_dfi_p3_cs_n; +assign main_litedramcore_slave_p3_ras_n = main_litedramcore_dfi_p3_ras_n; +assign main_litedramcore_slave_p3_we_n = main_litedramcore_dfi_p3_we_n; +assign main_litedramcore_slave_p3_cke = main_litedramcore_dfi_p3_cke; +assign main_litedramcore_slave_p3_odt = main_litedramcore_dfi_p3_odt; +assign main_litedramcore_slave_p3_reset_n = main_litedramcore_dfi_p3_reset_n; +assign main_litedramcore_slave_p3_act_n = main_litedramcore_dfi_p3_act_n; +assign main_litedramcore_slave_p3_wrdata = main_litedramcore_dfi_p3_wrdata; +assign main_litedramcore_slave_p3_wrdata_en = main_litedramcore_dfi_p3_wrdata_en; +assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_mask; +assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en; +assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata; +assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid; +always @(*) begin + main_litedramcore_csr_dfi_p0_rddata <= 32'd0; + if (main_litedramcore_sel) begin + end else begin + main_litedramcore_csr_dfi_p0_rddata <= main_litedramcore_master_p0_rddata; end end always @(*) begin - litedramcore_csr_dfi_p2_rddata <= 32'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata; + main_litedramcore_csr_dfi_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end end always @(*) begin - litedramcore_csr_dfi_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p1_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + main_litedramcore_csr_dfi_p1_rddata <= main_litedramcore_master_p1_rddata; end end always @(*) begin - litedramcore_csr_dfi_p3_rddata <= 32'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata; + main_litedramcore_csr_dfi_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end end always @(*) begin - litedramcore_csr_dfi_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p2_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + main_litedramcore_csr_dfi_p2_rddata <= main_litedramcore_master_p2_rddata; end end always @(*) begin - litedramcore_ext_dfi_p0_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata; - end else begin - end + main_litedramcore_csr_dfi_p2_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + end else begin + main_litedramcore_csr_dfi_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; + end +end +always @(*) begin + main_litedramcore_csr_dfi_p3_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin + main_litedramcore_csr_dfi_p3_rddata <= main_litedramcore_master_p3_rddata; end end always @(*) begin - litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + main_litedramcore_csr_dfi_p3_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + end else begin + main_litedramcore_csr_dfi_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; + end +end +always @(*) begin + main_litedramcore_ext_dfi_p0_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p0_rddata <= main_litedramcore_master_p0_rddata; end else begin end end else begin end end always @(*) begin - litedramcore_ext_dfi_p1_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata; + main_litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end else begin end end else begin end end always @(*) begin - litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + main_litedramcore_ext_dfi_p1_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p1_rddata <= main_litedramcore_master_p1_rddata; end else begin end end else begin end end always @(*) begin - litedramcore_ext_dfi_p2_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata; + main_litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end else begin end end else begin end end always @(*) begin - litedramcore_ext_dfi_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + main_litedramcore_ext_dfi_p2_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p2_rddata <= main_litedramcore_master_p2_rddata; end else begin end end else begin end end always @(*) begin - litedramcore_slave_p0_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p2_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end else begin - litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; end end else begin end end always @(*) begin - litedramcore_slave_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p0_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata; end end else begin end end always @(*) begin - litedramcore_ext_dfi_p3_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata; + main_litedramcore_slave_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin + main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end end else begin end end always @(*) begin - litedramcore_ext_dfi_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + main_litedramcore_ext_dfi_p3_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p3_rddata <= main_litedramcore_master_p3_rddata; end else begin end end else begin end end always @(*) begin - litedramcore_slave_p1_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p3_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end else begin - litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; end end else begin end end always @(*) begin - litedramcore_slave_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p1_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata; end end else begin end end always @(*) begin - litedramcore_slave_p2_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p1_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; + main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end end else begin end end always @(*) begin - litedramcore_slave_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p2_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata; end end else begin end end always @(*) begin - litedramcore_slave_p3_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p2_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; + main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end end else begin end end always @(*) begin - litedramcore_slave_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p3_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata; end end else begin end end always @(*) begin - litedramcore_master_p0_address <= 15'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address; + main_litedramcore_slave_p3_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_master_p0_address <= litedramcore_slave_p0_address; + main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end end else begin - litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address; end end always @(*) begin - litedramcore_master_p0_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank; + main_litedramcore_master_p0_address <= 15'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_address <= main_litedramcore_ext_dfi_p0_address; end else begin - litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; + main_litedramcore_master_p0_address <= main_litedramcore_slave_p0_address; end end else begin - litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank; + main_litedramcore_master_p0_address <= main_litedramcore_csr_dfi_p0_address; end end always @(*) begin - litedramcore_master_p0_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n; + main_litedramcore_master_p0_bank <= 3'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_bank <= main_litedramcore_ext_dfi_p0_bank; end else begin - litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; + main_litedramcore_master_p0_bank <= main_litedramcore_slave_p0_bank; end end else begin - litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n; + main_litedramcore_master_p0_bank <= main_litedramcore_csr_dfi_p0_bank; end end always @(*) begin - litedramcore_master_p0_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n; + main_litedramcore_master_p0_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_cas_n <= main_litedramcore_ext_dfi_p0_cas_n; end else begin - litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; + main_litedramcore_master_p0_cas_n <= main_litedramcore_slave_p0_cas_n; end end else begin - litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n; + main_litedramcore_master_p0_cas_n <= main_litedramcore_csr_dfi_p0_cas_n; end end always @(*) begin - litedramcore_master_p0_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n; + main_litedramcore_master_p0_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_cs_n <= main_litedramcore_ext_dfi_p0_cs_n; end else begin - litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; + main_litedramcore_master_p0_cs_n <= main_litedramcore_slave_p0_cs_n; + if (1'd0) begin + main_litedramcore_master_p0_cs_n <= {2{main_litedramcore_slave_p0_cs_n}}; + end end end else begin - litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n; + main_litedramcore_master_p0_cs_n <= main_litedramcore_csr_dfi_p0_cs_n; end end always @(*) begin - litedramcore_master_p0_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n; + main_litedramcore_master_p0_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_ras_n <= main_litedramcore_ext_dfi_p0_ras_n; end else begin - litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + main_litedramcore_master_p0_ras_n <= main_litedramcore_slave_p0_ras_n; end end else begin - litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n; + main_litedramcore_master_p0_ras_n <= main_litedramcore_csr_dfi_p0_ras_n; end end always @(*) begin - litedramcore_master_p0_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke; + main_litedramcore_master_p0_we_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_we_n <= main_litedramcore_ext_dfi_p0_we_n; end else begin - litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; + main_litedramcore_master_p0_we_n <= main_litedramcore_slave_p0_we_n; end end else begin - litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke; + main_litedramcore_master_p0_we_n <= main_litedramcore_csr_dfi_p0_we_n; end end always @(*) begin - litedramcore_master_p0_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt; + main_litedramcore_master_p0_cke <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_cke <= main_litedramcore_ext_dfi_p0_cke; end else begin - litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; + main_litedramcore_master_p0_cke <= main_litedramcore_slave_p0_cke; end end else begin - litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt; + main_litedramcore_master_p0_cke <= main_litedramcore_csr_dfi_p0_cke; end end always @(*) begin - litedramcore_master_p0_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n; + main_litedramcore_master_p0_odt <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_odt <= main_litedramcore_ext_dfi_p0_odt; end else begin - litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; + main_litedramcore_master_p0_odt <= main_litedramcore_slave_p0_odt; end end else begin - litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n; + main_litedramcore_master_p0_odt <= main_litedramcore_csr_dfi_p0_odt; end end always @(*) begin - litedramcore_master_p0_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n; + main_litedramcore_master_p0_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_reset_n <= main_litedramcore_ext_dfi_p0_reset_n; end else begin - litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; + main_litedramcore_master_p0_reset_n <= main_litedramcore_slave_p0_reset_n; end end else begin - litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n; + main_litedramcore_master_p0_reset_n <= main_litedramcore_csr_dfi_p0_reset_n; end end always @(*) begin - litedramcore_master_p0_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata; + main_litedramcore_master_p0_act_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_act_n <= main_litedramcore_ext_dfi_p0_act_n; end else begin - litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; + main_litedramcore_master_p0_act_n <= main_litedramcore_slave_p0_act_n; end end else begin - litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata; + main_litedramcore_master_p0_act_n <= main_litedramcore_csr_dfi_p0_act_n; end end always @(*) begin - litedramcore_master_p0_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en; + main_litedramcore_master_p0_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_wrdata <= main_litedramcore_ext_dfi_p0_wrdata; end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; + main_litedramcore_master_p0_wrdata <= main_litedramcore_slave_p0_wrdata; end end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en; + main_litedramcore_master_p0_wrdata <= main_litedramcore_csr_dfi_p0_wrdata; end end always @(*) begin - litedramcore_master_p0_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask; + main_litedramcore_master_p0_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_wrdata_en <= main_litedramcore_ext_dfi_p0_wrdata_en; end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; + main_litedramcore_master_p0_wrdata_en <= main_litedramcore_slave_p0_wrdata_en; end end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask; + main_litedramcore_master_p0_wrdata_en <= main_litedramcore_csr_dfi_p0_wrdata_en; end end always @(*) begin - litedramcore_master_p0_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en; + main_litedramcore_master_p0_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_ext_dfi_p0_wrdata_mask; end else begin - litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_slave_p0_wrdata_mask; end end else begin - litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en; + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_csr_dfi_p0_wrdata_mask; end end always @(*) begin - litedramcore_master_p1_address <= 15'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address; + main_litedramcore_master_p0_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_rddata_en <= main_litedramcore_ext_dfi_p0_rddata_en; end else begin - litedramcore_master_p1_address <= litedramcore_slave_p1_address; + main_litedramcore_master_p0_rddata_en <= main_litedramcore_slave_p0_rddata_en; end end else begin - litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address; + main_litedramcore_master_p0_rddata_en <= main_litedramcore_csr_dfi_p0_rddata_en; end end always @(*) begin - litedramcore_master_p1_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank; + main_litedramcore_master_p1_address <= 15'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_address <= main_litedramcore_ext_dfi_p1_address; end else begin - litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; + main_litedramcore_master_p1_address <= main_litedramcore_slave_p1_address; end end else begin - litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank; + main_litedramcore_master_p1_address <= main_litedramcore_csr_dfi_p1_address; end end always @(*) begin - litedramcore_master_p1_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n; + main_litedramcore_master_p1_bank <= 3'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_bank <= main_litedramcore_ext_dfi_p1_bank; end else begin - litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; + main_litedramcore_master_p1_bank <= main_litedramcore_slave_p1_bank; end end else begin - litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n; + main_litedramcore_master_p1_bank <= main_litedramcore_csr_dfi_p1_bank; end end always @(*) begin - litedramcore_master_p1_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n; + main_litedramcore_master_p1_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_cas_n <= main_litedramcore_ext_dfi_p1_cas_n; end else begin - litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; + main_litedramcore_master_p1_cas_n <= main_litedramcore_slave_p1_cas_n; end end else begin - litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n; + main_litedramcore_master_p1_cas_n <= main_litedramcore_csr_dfi_p1_cas_n; end end always @(*) begin - litedramcore_master_p1_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n; + main_litedramcore_master_p1_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_cs_n <= main_litedramcore_ext_dfi_p1_cs_n; end else begin - litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; + main_litedramcore_master_p1_cs_n <= main_litedramcore_slave_p1_cs_n; + if (1'd0) begin + main_litedramcore_master_p1_cs_n <= {2{main_litedramcore_slave_p1_cs_n}}; + end end end else begin - litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n; + main_litedramcore_master_p1_cs_n <= main_litedramcore_csr_dfi_p1_cs_n; end end always @(*) begin - litedramcore_master_p1_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n; + main_litedramcore_master_p1_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_ras_n <= main_litedramcore_ext_dfi_p1_ras_n; end else begin - litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; + main_litedramcore_master_p1_ras_n <= main_litedramcore_slave_p1_ras_n; end end else begin - litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n; + main_litedramcore_master_p1_ras_n <= main_litedramcore_csr_dfi_p1_ras_n; end end always @(*) begin - litedramcore_master_p1_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke; + main_litedramcore_master_p1_we_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_we_n <= main_litedramcore_ext_dfi_p1_we_n; end else begin - litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; + main_litedramcore_master_p1_we_n <= main_litedramcore_slave_p1_we_n; end end else begin - litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke; + main_litedramcore_master_p1_we_n <= main_litedramcore_csr_dfi_p1_we_n; end end always @(*) begin - litedramcore_master_p1_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt; + main_litedramcore_master_p1_cke <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_cke <= main_litedramcore_ext_dfi_p1_cke; end else begin - litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; + main_litedramcore_master_p1_cke <= main_litedramcore_slave_p1_cke; end end else begin - litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt; + main_litedramcore_master_p1_cke <= main_litedramcore_csr_dfi_p1_cke; end end always @(*) begin - litedramcore_master_p1_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n; + main_litedramcore_master_p1_odt <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_odt <= main_litedramcore_ext_dfi_p1_odt; end else begin - litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; + main_litedramcore_master_p1_odt <= main_litedramcore_slave_p1_odt; end end else begin - litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n; + main_litedramcore_master_p1_odt <= main_litedramcore_csr_dfi_p1_odt; end end always @(*) begin - litedramcore_master_p1_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n; + main_litedramcore_master_p1_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_reset_n <= main_litedramcore_ext_dfi_p1_reset_n; end else begin - litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; + main_litedramcore_master_p1_reset_n <= main_litedramcore_slave_p1_reset_n; end end else begin - litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n; + main_litedramcore_master_p1_reset_n <= main_litedramcore_csr_dfi_p1_reset_n; end end always @(*) begin - litedramcore_master_p1_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata; + main_litedramcore_master_p1_act_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_act_n <= main_litedramcore_ext_dfi_p1_act_n; end else begin - litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; + main_litedramcore_master_p1_act_n <= main_litedramcore_slave_p1_act_n; end end else begin - litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata; + main_litedramcore_master_p1_act_n <= main_litedramcore_csr_dfi_p1_act_n; end end always @(*) begin - litedramcore_master_p1_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en; + main_litedramcore_master_p1_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_wrdata <= main_litedramcore_ext_dfi_p1_wrdata; end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; + main_litedramcore_master_p1_wrdata <= main_litedramcore_slave_p1_wrdata; end end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en; + main_litedramcore_master_p1_wrdata <= main_litedramcore_csr_dfi_p1_wrdata; end end always @(*) begin - litedramcore_master_p1_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask; + main_litedramcore_master_p1_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_wrdata_en <= main_litedramcore_ext_dfi_p1_wrdata_en; end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; + main_litedramcore_master_p1_wrdata_en <= main_litedramcore_slave_p1_wrdata_en; end end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask; + main_litedramcore_master_p1_wrdata_en <= main_litedramcore_csr_dfi_p1_wrdata_en; end end always @(*) begin - litedramcore_master_p1_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en; + main_litedramcore_master_p1_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_ext_dfi_p1_wrdata_mask; end else begin - litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; + main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_slave_p1_wrdata_mask; end end else begin - litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en; + main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_csr_dfi_p1_wrdata_mask; end end always @(*) begin - litedramcore_master_p2_address <= 15'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address; + main_litedramcore_master_p1_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_rddata_en <= main_litedramcore_ext_dfi_p1_rddata_en; end else begin - litedramcore_master_p2_address <= litedramcore_slave_p2_address; + main_litedramcore_master_p1_rddata_en <= main_litedramcore_slave_p1_rddata_en; end end else begin - litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address; + main_litedramcore_master_p1_rddata_en <= main_litedramcore_csr_dfi_p1_rddata_en; end end always @(*) begin - litedramcore_master_p2_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank; + main_litedramcore_master_p2_address <= 15'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_address <= main_litedramcore_ext_dfi_p2_address; end else begin - litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; + main_litedramcore_master_p2_address <= main_litedramcore_slave_p2_address; end end else begin - litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank; + main_litedramcore_master_p2_address <= main_litedramcore_csr_dfi_p2_address; end end always @(*) begin - litedramcore_master_p2_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n; + main_litedramcore_master_p2_bank <= 3'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_bank <= main_litedramcore_ext_dfi_p2_bank; end else begin - litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; + main_litedramcore_master_p2_bank <= main_litedramcore_slave_p2_bank; end end else begin - litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n; + main_litedramcore_master_p2_bank <= main_litedramcore_csr_dfi_p2_bank; end end always @(*) begin - litedramcore_master_p2_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n; + main_litedramcore_master_p2_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_cas_n <= main_litedramcore_ext_dfi_p2_cas_n; end else begin - litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; + main_litedramcore_master_p2_cas_n <= main_litedramcore_slave_p2_cas_n; end end else begin - litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n; + main_litedramcore_master_p2_cas_n <= main_litedramcore_csr_dfi_p2_cas_n; end end always @(*) begin - litedramcore_master_p2_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n; + main_litedramcore_master_p2_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_cs_n <= main_litedramcore_ext_dfi_p2_cs_n; end else begin - litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; + main_litedramcore_master_p2_cs_n <= main_litedramcore_slave_p2_cs_n; + if (1'd0) begin + main_litedramcore_master_p2_cs_n <= {2{main_litedramcore_slave_p2_cs_n}}; + end end end else begin - litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n; + main_litedramcore_master_p2_cs_n <= main_litedramcore_csr_dfi_p2_cs_n; end end always @(*) begin - litedramcore_master_p2_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n; + main_litedramcore_master_p2_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_ras_n <= main_litedramcore_ext_dfi_p2_ras_n; end else begin - litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; + main_litedramcore_master_p2_ras_n <= main_litedramcore_slave_p2_ras_n; end end else begin - litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n; + main_litedramcore_master_p2_ras_n <= main_litedramcore_csr_dfi_p2_ras_n; end end always @(*) begin - litedramcore_master_p2_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke; + main_litedramcore_master_p2_we_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_we_n <= main_litedramcore_ext_dfi_p2_we_n; end else begin - litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; + main_litedramcore_master_p2_we_n <= main_litedramcore_slave_p2_we_n; end end else begin - litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke; + main_litedramcore_master_p2_we_n <= main_litedramcore_csr_dfi_p2_we_n; end end always @(*) begin - litedramcore_master_p2_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt; + main_litedramcore_master_p2_cke <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_cke <= main_litedramcore_ext_dfi_p2_cke; end else begin - litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; + main_litedramcore_master_p2_cke <= main_litedramcore_slave_p2_cke; end end else begin - litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt; + main_litedramcore_master_p2_cke <= main_litedramcore_csr_dfi_p2_cke; end end always @(*) begin - litedramcore_master_p2_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n; + main_litedramcore_master_p2_odt <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_odt <= main_litedramcore_ext_dfi_p2_odt; end else begin - litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; + main_litedramcore_master_p2_odt <= main_litedramcore_slave_p2_odt; end end else begin - litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n; + main_litedramcore_master_p2_odt <= main_litedramcore_csr_dfi_p2_odt; end end always @(*) begin - litedramcore_master_p2_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n; + main_litedramcore_master_p2_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_reset_n <= main_litedramcore_ext_dfi_p2_reset_n; end else begin - litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; + main_litedramcore_master_p2_reset_n <= main_litedramcore_slave_p2_reset_n; end end else begin - litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n; + main_litedramcore_master_p2_reset_n <= main_litedramcore_csr_dfi_p2_reset_n; end end always @(*) begin - litedramcore_master_p2_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata; + main_litedramcore_master_p2_act_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_act_n <= main_litedramcore_ext_dfi_p2_act_n; end else begin - litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; + main_litedramcore_master_p2_act_n <= main_litedramcore_slave_p2_act_n; end end else begin - litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata; + main_litedramcore_master_p2_act_n <= main_litedramcore_csr_dfi_p2_act_n; end end always @(*) begin - litedramcore_master_p2_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en; + main_litedramcore_master_p2_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_wrdata <= main_litedramcore_ext_dfi_p2_wrdata; end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; + main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata; end end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en; + main_litedramcore_master_p2_wrdata <= main_litedramcore_csr_dfi_p2_wrdata; end end always @(*) begin - litedramcore_master_p2_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask; + main_litedramcore_master_p2_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_wrdata_en <= main_litedramcore_ext_dfi_p2_wrdata_en; end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; + main_litedramcore_master_p2_wrdata_en <= main_litedramcore_slave_p2_wrdata_en; end end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask; + main_litedramcore_master_p2_wrdata_en <= main_litedramcore_csr_dfi_p2_wrdata_en; end end always @(*) begin - litedramcore_master_p2_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en; + main_litedramcore_master_p2_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_ext_dfi_p2_wrdata_mask; end else begin - litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; + main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_slave_p2_wrdata_mask; end end else begin - litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en; + main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_csr_dfi_p2_wrdata_mask; end end always @(*) begin - litedramcore_master_p3_address <= 15'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address; + main_litedramcore_master_p2_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_rddata_en <= main_litedramcore_ext_dfi_p2_rddata_en; end else begin - litedramcore_master_p3_address <= litedramcore_slave_p3_address; + main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en; end end else begin - litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address; + main_litedramcore_master_p2_rddata_en <= main_litedramcore_csr_dfi_p2_rddata_en; end end always @(*) begin - litedramcore_master_p3_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank; + main_litedramcore_master_p3_address <= 15'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_address <= main_litedramcore_ext_dfi_p3_address; end else begin - litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; + main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address; end end else begin - litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank; + main_litedramcore_master_p3_address <= main_litedramcore_csr_dfi_p3_address; end end always @(*) begin - litedramcore_master_p3_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n; + main_litedramcore_master_p3_bank <= 3'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_bank <= main_litedramcore_ext_dfi_p3_bank; end else begin - litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; + main_litedramcore_master_p3_bank <= main_litedramcore_slave_p3_bank; end end else begin - litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n; + main_litedramcore_master_p3_bank <= main_litedramcore_csr_dfi_p3_bank; end end always @(*) begin - litedramcore_master_p3_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n; + main_litedramcore_master_p3_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_cas_n <= main_litedramcore_ext_dfi_p3_cas_n; end else begin - litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; + main_litedramcore_master_p3_cas_n <= main_litedramcore_slave_p3_cas_n; end end else begin - litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n; + main_litedramcore_master_p3_cas_n <= main_litedramcore_csr_dfi_p3_cas_n; end end always @(*) begin - litedramcore_master_p3_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n; + main_litedramcore_master_p3_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_cs_n <= main_litedramcore_ext_dfi_p3_cs_n; end else begin - litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; + main_litedramcore_master_p3_cs_n <= main_litedramcore_slave_p3_cs_n; + if (1'd0) begin + main_litedramcore_master_p3_cs_n <= {2{main_litedramcore_slave_p3_cs_n}}; + end end end else begin - litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n; + main_litedramcore_master_p3_cs_n <= main_litedramcore_csr_dfi_p3_cs_n; end end always @(*) begin - litedramcore_master_p3_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n; + main_litedramcore_master_p3_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_ras_n <= main_litedramcore_ext_dfi_p3_ras_n; end else begin - litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; + main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n; end end else begin - litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n; + main_litedramcore_master_p3_ras_n <= main_litedramcore_csr_dfi_p3_ras_n; end end always @(*) begin - litedramcore_master_p3_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke; + main_litedramcore_master_p3_we_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_we_n <= main_litedramcore_ext_dfi_p3_we_n; end else begin - litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; + main_litedramcore_master_p3_we_n <= main_litedramcore_slave_p3_we_n; end end else begin - litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke; + main_litedramcore_master_p3_we_n <= main_litedramcore_csr_dfi_p3_we_n; end end always @(*) begin - litedramcore_master_p3_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt; + main_litedramcore_master_p3_cke <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_cke <= main_litedramcore_ext_dfi_p3_cke; end else begin - litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; + main_litedramcore_master_p3_cke <= main_litedramcore_slave_p3_cke; end end else begin - litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt; + main_litedramcore_master_p3_cke <= main_litedramcore_csr_dfi_p3_cke; end end always @(*) begin - litedramcore_master_p3_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n; + main_litedramcore_master_p3_odt <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_odt <= main_litedramcore_ext_dfi_p3_odt; end else begin - litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; + main_litedramcore_master_p3_odt <= main_litedramcore_slave_p3_odt; end end else begin - litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n; + main_litedramcore_master_p3_odt <= main_litedramcore_csr_dfi_p3_odt; end end always @(*) begin - litedramcore_master_p3_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n; + main_litedramcore_master_p3_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_reset_n <= main_litedramcore_ext_dfi_p3_reset_n; end else begin - litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; + main_litedramcore_master_p3_reset_n <= main_litedramcore_slave_p3_reset_n; end end else begin - litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n; + main_litedramcore_master_p3_reset_n <= main_litedramcore_csr_dfi_p3_reset_n; end end always @(*) begin - litedramcore_master_p3_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata; + main_litedramcore_master_p3_act_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_act_n <= main_litedramcore_ext_dfi_p3_act_n; end else begin - litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; + main_litedramcore_master_p3_act_n <= main_litedramcore_slave_p3_act_n; end end else begin - litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata; + main_litedramcore_master_p3_act_n <= main_litedramcore_csr_dfi_p3_act_n; end end always @(*) begin - litedramcore_master_p3_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en; + main_litedramcore_master_p3_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_wrdata <= main_litedramcore_ext_dfi_p3_wrdata; end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; + main_litedramcore_master_p3_wrdata <= main_litedramcore_slave_p3_wrdata; end end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en; + main_litedramcore_master_p3_wrdata <= main_litedramcore_csr_dfi_p3_wrdata; end end always @(*) begin - litedramcore_master_p3_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask; + main_litedramcore_master_p3_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_wrdata_en <= main_litedramcore_ext_dfi_p3_wrdata_en; end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; + main_litedramcore_master_p3_wrdata_en <= main_litedramcore_slave_p3_wrdata_en; end end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask; + main_litedramcore_master_p3_wrdata_en <= main_litedramcore_csr_dfi_p3_wrdata_en; end end always @(*) begin - litedramcore_master_p3_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en; + main_litedramcore_master_p3_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_ext_dfi_p3_wrdata_mask; end else begin - litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; + main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_slave_p3_wrdata_mask; end end else begin - litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en; + main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_csr_dfi_p3_wrdata_mask; end end -assign litedramcore_csr_dfi_p0_cke = litedramcore_cke; -assign litedramcore_csr_dfi_p1_cke = litedramcore_cke; -assign litedramcore_csr_dfi_p2_cke = litedramcore_cke; -assign litedramcore_csr_dfi_p3_cke = litedramcore_cke; -assign litedramcore_csr_dfi_p0_odt = litedramcore_odt; -assign litedramcore_csr_dfi_p1_odt = litedramcore_odt; -assign litedramcore_csr_dfi_p2_odt = litedramcore_odt; -assign litedramcore_csr_dfi_p3_odt = litedramcore_odt; -assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n; -assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n; -assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n; -assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n; always @(*) begin - litedramcore_csr_dfi_p0_ras_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras); + main_litedramcore_master_p3_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_rddata_en <= main_litedramcore_ext_dfi_p3_rddata_en; + end else begin + main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en; + end end else begin - litedramcore_csr_dfi_p0_ras_n <= 1'd1; + main_litedramcore_master_p3_rddata_en <= main_litedramcore_csr_dfi_p3_rddata_en; end end always @(*) begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we); + main_litedramcore_csr_dfi_p0_cke <= 1'd0; + main_litedramcore_csr_dfi_p0_cke <= main_litedramcore_cke; +end +always @(*) begin + main_litedramcore_csr_dfi_p1_cke <= 1'd0; + main_litedramcore_csr_dfi_p1_cke <= main_litedramcore_cke; +end +always @(*) begin + main_litedramcore_csr_dfi_p2_cke <= 1'd0; + main_litedramcore_csr_dfi_p2_cke <= main_litedramcore_cke; +end +always @(*) begin + main_litedramcore_csr_dfi_p3_cke <= 1'd0; + main_litedramcore_csr_dfi_p3_cke <= main_litedramcore_cke; +end +always @(*) begin + main_litedramcore_csr_dfi_p0_odt <= 1'd0; + main_litedramcore_csr_dfi_p0_odt <= main_litedramcore_odt; +end +always @(*) begin + main_litedramcore_csr_dfi_p1_odt <= 1'd0; + main_litedramcore_csr_dfi_p1_odt <= main_litedramcore_odt; +end +always @(*) begin + main_litedramcore_csr_dfi_p2_odt <= 1'd0; + main_litedramcore_csr_dfi_p2_odt <= main_litedramcore_odt; +end +always @(*) begin + main_litedramcore_csr_dfi_p3_odt <= 1'd0; + main_litedramcore_csr_dfi_p3_odt <= main_litedramcore_odt; +end +assign main_litedramcore_csr_dfi_p0_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_csr_dfi_p1_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_csr_dfi_p2_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_csr_dfi_p3_reset_n = main_litedramcore_reset_n; +always @(*) begin + main_litedramcore_csr_dfi_p0_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_csr_dfi_p0_ras_n <= (~main_litedramcore_phaseinjector0_csrfield_ras); end else begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; + main_litedramcore_csr_dfi_p0_ras_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p0_cas_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas); + main_litedramcore_csr_dfi_p0_we_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_csr_dfi_p0_we_n <= (~main_litedramcore_phaseinjector0_csrfield_we); end else begin - litedramcore_csr_dfi_p0_cas_n <= 1'd1; + main_litedramcore_csr_dfi_p0_we_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p0_cs_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}}; + main_litedramcore_csr_dfi_p0_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_csr_dfi_p0_cas_n <= (~main_litedramcore_phaseinjector0_csrfield_cas); end else begin - litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; + main_litedramcore_csr_dfi_p0_cas_n <= 1'd1; end end -assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage; -assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage; -assign litedramcore_csr_dfi_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_wren); -assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_rden); -assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; -assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p1_ras_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras); + main_litedramcore_csr_dfi_p0_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + if (main_litedramcore_phaseinjector0_csrfield_cs_top) begin + main_litedramcore_csr_dfi_p0_cs_n <= 2'd2; + end else begin + if (main_litedramcore_phaseinjector0_csrfield_cs_bottom) begin + main_litedramcore_csr_dfi_p0_cs_n <= 1'd1; + end else begin + main_litedramcore_csr_dfi_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_csrfield_cs)}}; + end + end end else begin - litedramcore_csr_dfi_p1_ras_n <= 1'd1; + main_litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; end end +assign main_litedramcore_csr_dfi_p0_address = main_litedramcore_phaseinjector0_address_storage; +assign main_litedramcore_csr_dfi_p0_bank = main_litedramcore_phaseinjector0_baddress_storage; +assign main_litedramcore_csr_dfi_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_wren); +assign main_litedramcore_csr_dfi_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_rden); +assign main_litedramcore_csr_dfi_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage; +assign main_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we); + main_litedramcore_csr_dfi_p1_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_csr_dfi_p1_ras_n <= (~main_litedramcore_phaseinjector1_csrfield_ras); end else begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; + main_litedramcore_csr_dfi_p1_ras_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p1_cas_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas); + main_litedramcore_csr_dfi_p1_we_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_csr_dfi_p1_we_n <= (~main_litedramcore_phaseinjector1_csrfield_we); end else begin - litedramcore_csr_dfi_p1_cas_n <= 1'd1; + main_litedramcore_csr_dfi_p1_we_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p1_cs_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}}; + main_litedramcore_csr_dfi_p1_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_csr_dfi_p1_cas_n <= (~main_litedramcore_phaseinjector1_csrfield_cas); end else begin - litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; + main_litedramcore_csr_dfi_p1_cas_n <= 1'd1; end end -assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage; -assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage; -assign litedramcore_csr_dfi_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_wren); -assign litedramcore_csr_dfi_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_rden); -assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; -assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p2_ras_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras); + main_litedramcore_csr_dfi_p1_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + if (main_litedramcore_phaseinjector1_csrfield_cs_top) begin + main_litedramcore_csr_dfi_p1_cs_n <= 2'd2; + end else begin + if (main_litedramcore_phaseinjector1_csrfield_cs_bottom) begin + main_litedramcore_csr_dfi_p1_cs_n <= 1'd1; + end else begin + main_litedramcore_csr_dfi_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_csrfield_cs)}}; + end + end end else begin - litedramcore_csr_dfi_p2_ras_n <= 1'd1; + main_litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; end end +assign main_litedramcore_csr_dfi_p1_address = main_litedramcore_phaseinjector1_address_storage; +assign main_litedramcore_csr_dfi_p1_bank = main_litedramcore_phaseinjector1_baddress_storage; +assign main_litedramcore_csr_dfi_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_wren); +assign main_litedramcore_csr_dfi_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_rden); +assign main_litedramcore_csr_dfi_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage; +assign main_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p2_we_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we); + main_litedramcore_csr_dfi_p2_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_csr_dfi_p2_ras_n <= (~main_litedramcore_phaseinjector2_csrfield_ras); end else begin - litedramcore_csr_dfi_p2_we_n <= 1'd1; + main_litedramcore_csr_dfi_p2_ras_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p2_cas_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas); + main_litedramcore_csr_dfi_p2_we_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_csr_dfi_p2_we_n <= (~main_litedramcore_phaseinjector2_csrfield_we); end else begin - litedramcore_csr_dfi_p2_cas_n <= 1'd1; + main_litedramcore_csr_dfi_p2_we_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p2_cs_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}}; + main_litedramcore_csr_dfi_p2_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_csr_dfi_p2_cas_n <= (~main_litedramcore_phaseinjector2_csrfield_cas); end else begin - litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; + main_litedramcore_csr_dfi_p2_cas_n <= 1'd1; end end -assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage; -assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage; -assign litedramcore_csr_dfi_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_wren); -assign litedramcore_csr_dfi_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_rden); -assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage; -assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p3_ras_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras); + main_litedramcore_csr_dfi_p2_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + if (main_litedramcore_phaseinjector2_csrfield_cs_top) begin + main_litedramcore_csr_dfi_p2_cs_n <= 2'd2; + end else begin + if (main_litedramcore_phaseinjector2_csrfield_cs_bottom) begin + main_litedramcore_csr_dfi_p2_cs_n <= 1'd1; + end else begin + main_litedramcore_csr_dfi_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_csrfield_cs)}}; + end + end end else begin - litedramcore_csr_dfi_p3_ras_n <= 1'd1; + main_litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; end end +assign main_litedramcore_csr_dfi_p2_address = main_litedramcore_phaseinjector2_address_storage; +assign main_litedramcore_csr_dfi_p2_bank = main_litedramcore_phaseinjector2_baddress_storage; +assign main_litedramcore_csr_dfi_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_wren); +assign main_litedramcore_csr_dfi_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_rden); +assign main_litedramcore_csr_dfi_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage; +assign main_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p3_we_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we); + main_litedramcore_csr_dfi_p3_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_csr_dfi_p3_ras_n <= (~main_litedramcore_phaseinjector3_csrfield_ras); end else begin - litedramcore_csr_dfi_p3_we_n <= 1'd1; + main_litedramcore_csr_dfi_p3_ras_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p3_cas_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas); + main_litedramcore_csr_dfi_p3_we_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_csr_dfi_p3_we_n <= (~main_litedramcore_phaseinjector3_csrfield_we); end else begin - litedramcore_csr_dfi_p3_cas_n <= 1'd1; + main_litedramcore_csr_dfi_p3_we_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p3_cs_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}}; + main_litedramcore_csr_dfi_p3_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_csr_dfi_p3_cas_n <= (~main_litedramcore_phaseinjector3_csrfield_cas); end else begin - litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; + main_litedramcore_csr_dfi_p3_cas_n <= 1'd1; end end -assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage; -assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage; -assign litedramcore_csr_dfi_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_wren); -assign litedramcore_csr_dfi_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_rden); -assign litedramcore_csr_dfi_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage; -assign litedramcore_csr_dfi_p3_wrdata_mask = 1'd0; -assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid; -assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready; -assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we; -assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr; -assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock; -assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready; -assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid; -assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid; -assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready; -assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we; -assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr; -assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock; -assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready; -assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid; -assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid; -assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready; -assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we; -assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr; -assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock; -assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready; -assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid; -assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid; -assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready; -assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we; -assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr; -assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock; -assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready; -assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid; -assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid; -assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready; -assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we; -assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr; -assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock; -assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready; -assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid; -assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid; -assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready; -assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we; -assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr; -assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock; -assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready; -assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid; -assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid; -assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready; -assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we; -assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr; -assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock; -assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready; -assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid; -assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid; -assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready; -assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we; -assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr; -assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock; -assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready; -assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid; -assign litedramcore_timer_wait = (~litedramcore_timer_done0); -assign litedramcore_postponer_req_i = litedramcore_timer_done0; -assign litedramcore_wants_refresh = litedramcore_postponer_req_o; -assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0; -assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done); -assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0); -assign litedramcore_timer_done0 = litedramcore_timer_done1; -assign litedramcore_timer_count0 = litedramcore_timer_count1; -assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0)); -assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0)); -assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0); -assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1; -assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1; -always @(*) begin - litedramcore_refresher_next_state <= 2'd0; - litedramcore_refresher_next_state <= litedramcore_refresher_state; - case (litedramcore_refresher_state) - 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_refresher_next_state <= 2'd2; - end - end - 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - litedramcore_refresher_next_state <= 2'd3; +always @(*) begin + main_litedramcore_csr_dfi_p3_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + if (main_litedramcore_phaseinjector3_csrfield_cs_top) begin + main_litedramcore_csr_dfi_p3_cs_n <= 2'd2; + end else begin + if (main_litedramcore_phaseinjector3_csrfield_cs_bottom) begin + main_litedramcore_csr_dfi_p3_cs_n <= 1'd1; + end else begin + main_litedramcore_csr_dfi_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_csrfield_cs)}}; + end + end + end else begin + main_litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; + end +end +assign main_litedramcore_csr_dfi_p3_address = main_litedramcore_phaseinjector3_address_storage; +assign main_litedramcore_csr_dfi_p3_bank = main_litedramcore_phaseinjector3_baddress_storage; +assign main_litedramcore_csr_dfi_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_wren); +assign main_litedramcore_csr_dfi_p3_rddata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_rden); +assign main_litedramcore_csr_dfi_p3_wrdata = main_litedramcore_phaseinjector3_wrdata_storage; +assign main_litedramcore_csr_dfi_p3_wrdata_mask = 1'd0; +assign main_litedramcore_bankmachine0_req_valid = main_litedramcore_interface_bank0_valid; +assign main_litedramcore_interface_bank0_ready = main_litedramcore_bankmachine0_req_ready; +assign main_litedramcore_bankmachine0_req_we = main_litedramcore_interface_bank0_we; +assign main_litedramcore_bankmachine0_req_addr = main_litedramcore_interface_bank0_addr; +assign main_litedramcore_interface_bank0_lock = main_litedramcore_bankmachine0_req_lock; +assign main_litedramcore_interface_bank0_wdata_ready = main_litedramcore_bankmachine0_req_wdata_ready; +assign main_litedramcore_interface_bank0_rdata_valid = main_litedramcore_bankmachine0_req_rdata_valid; +assign main_litedramcore_bankmachine1_req_valid = main_litedramcore_interface_bank1_valid; +assign main_litedramcore_interface_bank1_ready = main_litedramcore_bankmachine1_req_ready; +assign main_litedramcore_bankmachine1_req_we = main_litedramcore_interface_bank1_we; +assign main_litedramcore_bankmachine1_req_addr = main_litedramcore_interface_bank1_addr; +assign main_litedramcore_interface_bank1_lock = main_litedramcore_bankmachine1_req_lock; +assign main_litedramcore_interface_bank1_wdata_ready = main_litedramcore_bankmachine1_req_wdata_ready; +assign main_litedramcore_interface_bank1_rdata_valid = main_litedramcore_bankmachine1_req_rdata_valid; +assign main_litedramcore_bankmachine2_req_valid = main_litedramcore_interface_bank2_valid; +assign main_litedramcore_interface_bank2_ready = main_litedramcore_bankmachine2_req_ready; +assign main_litedramcore_bankmachine2_req_we = main_litedramcore_interface_bank2_we; +assign main_litedramcore_bankmachine2_req_addr = main_litedramcore_interface_bank2_addr; +assign main_litedramcore_interface_bank2_lock = main_litedramcore_bankmachine2_req_lock; +assign main_litedramcore_interface_bank2_wdata_ready = main_litedramcore_bankmachine2_req_wdata_ready; +assign main_litedramcore_interface_bank2_rdata_valid = main_litedramcore_bankmachine2_req_rdata_valid; +assign main_litedramcore_bankmachine3_req_valid = main_litedramcore_interface_bank3_valid; +assign main_litedramcore_interface_bank3_ready = main_litedramcore_bankmachine3_req_ready; +assign main_litedramcore_bankmachine3_req_we = main_litedramcore_interface_bank3_we; +assign main_litedramcore_bankmachine3_req_addr = main_litedramcore_interface_bank3_addr; +assign main_litedramcore_interface_bank3_lock = main_litedramcore_bankmachine3_req_lock; +assign main_litedramcore_interface_bank3_wdata_ready = main_litedramcore_bankmachine3_req_wdata_ready; +assign main_litedramcore_interface_bank3_rdata_valid = main_litedramcore_bankmachine3_req_rdata_valid; +assign main_litedramcore_bankmachine4_req_valid = main_litedramcore_interface_bank4_valid; +assign main_litedramcore_interface_bank4_ready = main_litedramcore_bankmachine4_req_ready; +assign main_litedramcore_bankmachine4_req_we = main_litedramcore_interface_bank4_we; +assign main_litedramcore_bankmachine4_req_addr = main_litedramcore_interface_bank4_addr; +assign main_litedramcore_interface_bank4_lock = main_litedramcore_bankmachine4_req_lock; +assign main_litedramcore_interface_bank4_wdata_ready = main_litedramcore_bankmachine4_req_wdata_ready; +assign main_litedramcore_interface_bank4_rdata_valid = main_litedramcore_bankmachine4_req_rdata_valid; +assign main_litedramcore_bankmachine5_req_valid = main_litedramcore_interface_bank5_valid; +assign main_litedramcore_interface_bank5_ready = main_litedramcore_bankmachine5_req_ready; +assign main_litedramcore_bankmachine5_req_we = main_litedramcore_interface_bank5_we; +assign main_litedramcore_bankmachine5_req_addr = main_litedramcore_interface_bank5_addr; +assign main_litedramcore_interface_bank5_lock = main_litedramcore_bankmachine5_req_lock; +assign main_litedramcore_interface_bank5_wdata_ready = main_litedramcore_bankmachine5_req_wdata_ready; +assign main_litedramcore_interface_bank5_rdata_valid = main_litedramcore_bankmachine5_req_rdata_valid; +assign main_litedramcore_bankmachine6_req_valid = main_litedramcore_interface_bank6_valid; +assign main_litedramcore_interface_bank6_ready = main_litedramcore_bankmachine6_req_ready; +assign main_litedramcore_bankmachine6_req_we = main_litedramcore_interface_bank6_we; +assign main_litedramcore_bankmachine6_req_addr = main_litedramcore_interface_bank6_addr; +assign main_litedramcore_interface_bank6_lock = main_litedramcore_bankmachine6_req_lock; +assign main_litedramcore_interface_bank6_wdata_ready = main_litedramcore_bankmachine6_req_wdata_ready; +assign main_litedramcore_interface_bank6_rdata_valid = main_litedramcore_bankmachine6_req_rdata_valid; +assign main_litedramcore_bankmachine7_req_valid = main_litedramcore_interface_bank7_valid; +assign main_litedramcore_interface_bank7_ready = main_litedramcore_bankmachine7_req_ready; +assign main_litedramcore_bankmachine7_req_we = main_litedramcore_interface_bank7_we; +assign main_litedramcore_bankmachine7_req_addr = main_litedramcore_interface_bank7_addr; +assign main_litedramcore_interface_bank7_lock = main_litedramcore_bankmachine7_req_lock; +assign main_litedramcore_interface_bank7_wdata_ready = main_litedramcore_bankmachine7_req_wdata_ready; +assign main_litedramcore_interface_bank7_rdata_valid = main_litedramcore_bankmachine7_req_rdata_valid; +assign main_litedramcore_timer_wait = (~main_litedramcore_timer_done0); +assign main_litedramcore_postponer_req_i = main_litedramcore_timer_done0; +assign main_litedramcore_wants_refresh = main_litedramcore_postponer_req_o; +assign main_litedramcore_wants_zqcs = main_litedramcore_zqcs_timer_done0; +assign main_litedramcore_zqcs_timer_wait = (~main_litedramcore_zqcs_executer_done); +assign main_litedramcore_timer_done1 = (main_litedramcore_timer_count1 == 1'd0); +assign main_litedramcore_timer_done0 = main_litedramcore_timer_done1; +assign main_litedramcore_timer_count0 = main_litedramcore_timer_count1; +assign main_litedramcore_sequencer_start1 = (main_litedramcore_sequencer_start0 | (main_litedramcore_sequencer_count != 1'd0)); +assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & (main_litedramcore_sequencer_count == 1'd0)); +assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0); +assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1; +assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1; +always @(*) begin + builder_refresher_next_state <= 2'd0; + builder_refresher_next_state <= builder_refresher_state; + case (builder_refresher_state) + 1'd1: begin + if (main_litedramcore_cmd_ready) begin + builder_refresher_next_state <= 2'd2; + end + end + 2'd2: begin + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + builder_refresher_next_state <= 2'd3; end else begin - litedramcore_refresher_next_state <= 1'd0; + builder_refresher_next_state <= 1'd0; end end end 2'd3: begin - if (litedramcore_zqcs_executer_done) begin - litedramcore_refresher_next_state <= 1'd0; + if (main_litedramcore_zqcs_executer_done) begin + builder_refresher_next_state <= 1'd0; end end default: begin if (1'd1) begin - if (litedramcore_wants_refresh) begin - litedramcore_refresher_next_state <= 1'd1; + if (main_litedramcore_wants_refresh) begin + builder_refresher_next_state <= 1'd1; end end end endcase end always @(*) begin - litedramcore_sequencer_start0 <= 1'd0; - case (litedramcore_refresher_state) + main_litedramcore_sequencer_start0 <= 1'd0; + case (builder_refresher_state) 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_sequencer_start0 <= 1'd1; + if (main_litedramcore_cmd_ready) begin + main_litedramcore_sequencer_start0 <= 1'd1; end end 2'd2: begin @@ -4683,24 +5102,24 @@ always @(*) begin endcase end always @(*) begin - litedramcore_cmd_valid <= 1'd0; - case (litedramcore_refresher_state) + main_litedramcore_cmd_valid <= 1'd0; + case (builder_refresher_state) 1'd1: begin - litedramcore_cmd_valid <= 1'd1; + main_litedramcore_cmd_valid <= 1'd1; end 2'd2: begin - litedramcore_cmd_valid <= 1'd1; - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin end else begin - litedramcore_cmd_valid <= 1'd0; + main_litedramcore_cmd_valid <= 1'd0; end end end 2'd3: begin - litedramcore_cmd_valid <= 1'd1; - if (litedramcore_zqcs_executer_done) begin - litedramcore_cmd_valid <= 1'd0; + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_valid <= 1'd0; end end default: begin @@ -4708,14 +5127,14 @@ always @(*) begin endcase end always @(*) begin - litedramcore_zqcs_executer_start <= 1'd0; - case (litedramcore_refresher_state) + main_litedramcore_zqcs_executer_start <= 1'd0; + case (builder_refresher_state) 1'd1: begin end 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - litedramcore_zqcs_executer_start <= 1'd1; + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + main_litedramcore_zqcs_executer_start <= 1'd1; end else begin end end @@ -4727,160 +5146,160 @@ always @(*) begin endcase end always @(*) begin - litedramcore_cmd_last <= 1'd0; - case (litedramcore_refresher_state) + main_litedramcore_cmd_last <= 1'd0; + case (builder_refresher_state) 1'd1: begin end 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin end else begin - litedramcore_cmd_last <= 1'd1; + main_litedramcore_cmd_last <= 1'd1; end end end 2'd3: begin - if (litedramcore_zqcs_executer_done) begin - litedramcore_cmd_last <= 1'd1; - end - end - default: begin - end - endcase -end -assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid; -assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready; -assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we; -assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr; -assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid; -assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready; -assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first; -assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last; -assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we; -assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr; -assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); -assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid); -assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[21:7]); -assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0; -always @(*) begin - litedramcore_bankmachine0_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine0_row_col_n_addr_sel) begin - litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_source_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write); -assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); -assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); -always @(*) begin - litedramcore_bankmachine0_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin - if ((litedramcore_bankmachine0_source_payload_addr[21:7] != litedramcore_bankmachine0_source_source_payload_addr[21:7])) begin - litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we}; -assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; -assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; -assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; -assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; -assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable; -assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid; -assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first; -assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last; -assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we; -assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr; -assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable; -assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first; -assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last; -assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we; -assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr; -assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready; -always @(*) begin - litedramcore_bankmachine0_wrport_adr <= 4'd0; - if (litedramcore_bankmachine0_replace) begin - litedramcore_bankmachine0_wrport_adr <= (litedramcore_bankmachine0_produce - 1'd1); - end else begin - litedramcore_bankmachine0_wrport_adr <= litedramcore_bankmachine0_produce; - end -end -assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din; -assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace)); -assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re); -assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume; -assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r; -assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 5'd16); -assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0); -assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready); -assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid; -assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready; -assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first; -assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last; -assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we; -assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr; -assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid; -assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready; -assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first; -assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last; -assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we; -assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine0_next_state <= 4'd0; - litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - if (litedramcore_bankmachine0_cmd_ready) begin - litedramcore_bankmachine0_next_state <= 3'd5; + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_last <= 1'd1; + end + end + default: begin + end + endcase +end +assign main_litedramcore_bankmachine0_sink_valid = main_litedramcore_bankmachine0_req_valid; +assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_sink_ready; +assign main_litedramcore_bankmachine0_sink_payload_we = main_litedramcore_bankmachine0_req_we; +assign main_litedramcore_bankmachine0_sink_payload_addr = main_litedramcore_bankmachine0_req_addr; +assign main_litedramcore_bankmachine0_sink_sink_valid = main_litedramcore_bankmachine0_source_valid; +assign main_litedramcore_bankmachine0_source_ready = main_litedramcore_bankmachine0_sink_sink_ready; +assign main_litedramcore_bankmachine0_sink_sink_first = main_litedramcore_bankmachine0_source_first; +assign main_litedramcore_bankmachine0_sink_sink_last = main_litedramcore_bankmachine0_source_last; +assign main_litedramcore_bankmachine0_sink_sink_payload_we = main_litedramcore_bankmachine0_source_payload_we; +assign main_litedramcore_bankmachine0_sink_sink_payload_addr = main_litedramcore_bankmachine0_source_payload_addr; +assign main_litedramcore_bankmachine0_source_source_ready = (main_litedramcore_bankmachine0_req_wdata_ready | main_litedramcore_bankmachine0_req_rdata_valid); +assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_source_valid | main_litedramcore_bankmachine0_source_source_valid); +assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_source_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0; +always @(*) begin + main_litedramcore_bankmachine0_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin + main_litedramcore_bankmachine0_cmd_payload_a <= main_litedramcore_bankmachine0_source_source_payload_addr[21:7]; + end else begin + main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write); +assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); +assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); +always @(*) begin + main_litedramcore_bankmachine0_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine0_source_valid & main_litedramcore_bankmachine0_source_source_valid)) begin + if ((main_litedramcore_bankmachine0_source_payload_addr[21:7] != main_litedramcore_bankmachine0_source_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine0_syncfifo0_din = {main_litedramcore_bankmachine0_fifo_in_last, main_litedramcore_bankmachine0_fifo_in_first, main_litedramcore_bankmachine0_fifo_in_payload_addr, main_litedramcore_bankmachine0_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout; +assign main_litedramcore_bankmachine0_sink_ready = main_litedramcore_bankmachine0_syncfifo0_writable; +assign main_litedramcore_bankmachine0_syncfifo0_we = main_litedramcore_bankmachine0_sink_valid; +assign main_litedramcore_bankmachine0_fifo_in_first = main_litedramcore_bankmachine0_sink_first; +assign main_litedramcore_bankmachine0_fifo_in_last = main_litedramcore_bankmachine0_sink_last; +assign main_litedramcore_bankmachine0_fifo_in_payload_we = main_litedramcore_bankmachine0_sink_payload_we; +assign main_litedramcore_bankmachine0_fifo_in_payload_addr = main_litedramcore_bankmachine0_sink_payload_addr; +assign main_litedramcore_bankmachine0_source_valid = main_litedramcore_bankmachine0_syncfifo0_readable; +assign main_litedramcore_bankmachine0_source_first = main_litedramcore_bankmachine0_fifo_out_first; +assign main_litedramcore_bankmachine0_source_last = main_litedramcore_bankmachine0_fifo_out_last; +assign main_litedramcore_bankmachine0_source_payload_we = main_litedramcore_bankmachine0_fifo_out_payload_we; +assign main_litedramcore_bankmachine0_source_payload_addr = main_litedramcore_bankmachine0_fifo_out_payload_addr; +assign main_litedramcore_bankmachine0_syncfifo0_re = main_litedramcore_bankmachine0_source_ready; +always @(*) begin + main_litedramcore_bankmachine0_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine0_replace) begin + main_litedramcore_bankmachine0_wrport_adr <= (main_litedramcore_bankmachine0_produce - 1'd1); + end else begin + main_litedramcore_bankmachine0_wrport_adr <= main_litedramcore_bankmachine0_produce; + end +end +assign main_litedramcore_bankmachine0_wrport_dat_w = main_litedramcore_bankmachine0_syncfifo0_din; +assign main_litedramcore_bankmachine0_wrport_we = (main_litedramcore_bankmachine0_syncfifo0_we & (main_litedramcore_bankmachine0_syncfifo0_writable | main_litedramcore_bankmachine0_replace)); +assign main_litedramcore_bankmachine0_do_read = (main_litedramcore_bankmachine0_syncfifo0_readable & main_litedramcore_bankmachine0_syncfifo0_re); +assign main_litedramcore_bankmachine0_rdport_adr = main_litedramcore_bankmachine0_consume; +assign main_litedramcore_bankmachine0_syncfifo0_dout = main_litedramcore_bankmachine0_rdport_dat_r; +assign main_litedramcore_bankmachine0_syncfifo0_writable = (main_litedramcore_bankmachine0_level != 5'd16); +assign main_litedramcore_bankmachine0_syncfifo0_readable = (main_litedramcore_bankmachine0_level != 1'd0); +assign main_litedramcore_bankmachine0_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine0_pipe_valid_source_valid) | main_litedramcore_bankmachine0_pipe_valid_source_ready); +assign main_litedramcore_bankmachine0_pipe_valid_sink_valid = main_litedramcore_bankmachine0_sink_sink_valid; +assign main_litedramcore_bankmachine0_sink_sink_ready = main_litedramcore_bankmachine0_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine0_pipe_valid_sink_first = main_litedramcore_bankmachine0_sink_sink_first; +assign main_litedramcore_bankmachine0_pipe_valid_sink_last = main_litedramcore_bankmachine0_sink_sink_last; +assign main_litedramcore_bankmachine0_pipe_valid_sink_payload_we = main_litedramcore_bankmachine0_sink_sink_payload_we; +assign main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine0_sink_sink_payload_addr; +assign main_litedramcore_bankmachine0_source_source_valid = main_litedramcore_bankmachine0_pipe_valid_source_valid; +assign main_litedramcore_bankmachine0_pipe_valid_source_ready = main_litedramcore_bankmachine0_source_source_ready; +assign main_litedramcore_bankmachine0_source_source_first = main_litedramcore_bankmachine0_pipe_valid_source_first; +assign main_litedramcore_bankmachine0_source_source_last = main_litedramcore_bankmachine0_pipe_valid_source_last; +assign main_litedramcore_bankmachine0_source_source_payload_we = main_litedramcore_bankmachine0_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine0_source_source_payload_addr = main_litedramcore_bankmachine0_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine0_next_state <= 4'd0; + builder_bankmachine0_next_state <= builder_bankmachine0_state; + case (builder_bankmachine0_state) + 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + if (main_litedramcore_bankmachine0_cmd_ready) begin + builder_bankmachine0_next_state <= 3'd5; end end end 2'd2: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_next_state <= 3'd5; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + builder_bankmachine0_next_state <= 3'd5; end end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - if (litedramcore_bankmachine0_cmd_ready) begin - litedramcore_bankmachine0_next_state <= 3'd7; + if (main_litedramcore_bankmachine0_trccon_ready) begin + if (main_litedramcore_bankmachine0_cmd_ready) begin + builder_bankmachine0_next_state <= 3'd7; end end end 3'd4: begin - if ((~litedramcore_bankmachine0_refresh_req)) begin - litedramcore_bankmachine0_next_state <= 1'd0; + if ((~main_litedramcore_bankmachine0_refresh_req)) begin + builder_bankmachine0_next_state <= 1'd0; end end 3'd5: begin - litedramcore_bankmachine0_next_state <= 3'd6; + builder_bankmachine0_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine0_next_state <= 2'd3; + builder_bankmachine0_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine0_next_state <= 4'd8; + builder_bankmachine0_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine0_next_state <= 1'd0; + builder_bankmachine0_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - litedramcore_bankmachine0_next_state <= 3'd4; + if (main_litedramcore_bankmachine0_refresh_req) begin + builder_bankmachine0_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin - litedramcore_bankmachine0_next_state <= 2'd2; + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if ((main_litedramcore_bankmachine0_cmd_ready & main_litedramcore_bankmachine0_auto_precharge)) begin + builder_bankmachine0_next_state <= 2'd2; end end else begin - litedramcore_bankmachine0_next_state <= 1'd1; + builder_bankmachine0_next_state <= 1'd1; end end else begin - litedramcore_bankmachine0_next_state <= 2'd3; + builder_bankmachine0_next_state <= 2'd3; end end end @@ -4888,15 +5307,41 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_row_close <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin + main_litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd2: begin + main_litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + main_litedramcore_bankmachine0_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -4914,8 +5359,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -4933,12 +5378,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -4949,18 +5394,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -4978,11 +5423,11 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -5000,13 +5445,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -5019,22 +5464,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5049,8 +5494,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5068,14 +5513,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin end else begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; end end else begin end @@ -5087,8 +5532,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5106,13 +5551,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -5125,8 +5570,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5144,13 +5589,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin - litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin + main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready; end else begin end end else begin @@ -5163,8 +5608,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5182,14 +5627,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin end else begin - litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; + main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready; end end else begin end @@ -5201,8 +5646,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_refresh_gnt <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5210,8 +5655,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine0_twtpcon_ready) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd1; + if (main_litedramcore_bankmachine0_twtpcon_ready) begin + main_litedramcore_bankmachine0_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -5227,15 +5672,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_row_open <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_row_open <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_open <= 1'd1; + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_row_open <= 1'd1; end end 3'd4: begin @@ -5253,18 +5698,21 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_row_close <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - litedramcore_bankmachine0_row_close <= 1'd1; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end end 2'd2: begin - litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end end 3'd4: begin - litedramcore_bankmachine0_row_close <= 1'd1; end 3'd5: begin end @@ -5275,183 +5723,189 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end -always @(*) begin - litedramcore_bankmachine0_cmd_valid <= 1'd0; - case (litedramcore_bankmachine0_state) +assign main_litedramcore_bankmachine1_sink_valid = main_litedramcore_bankmachine1_req_valid; +assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_sink_ready; +assign main_litedramcore_bankmachine1_sink_payload_we = main_litedramcore_bankmachine1_req_we; +assign main_litedramcore_bankmachine1_sink_payload_addr = main_litedramcore_bankmachine1_req_addr; +assign main_litedramcore_bankmachine1_sink_sink_valid = main_litedramcore_bankmachine1_source_valid; +assign main_litedramcore_bankmachine1_source_ready = main_litedramcore_bankmachine1_sink_sink_ready; +assign main_litedramcore_bankmachine1_sink_sink_first = main_litedramcore_bankmachine1_source_first; +assign main_litedramcore_bankmachine1_sink_sink_last = main_litedramcore_bankmachine1_source_last; +assign main_litedramcore_bankmachine1_sink_sink_payload_we = main_litedramcore_bankmachine1_source_payload_we; +assign main_litedramcore_bankmachine1_sink_sink_payload_addr = main_litedramcore_bankmachine1_source_payload_addr; +assign main_litedramcore_bankmachine1_source_source_ready = (main_litedramcore_bankmachine1_req_wdata_ready | main_litedramcore_bankmachine1_req_rdata_valid); +assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_source_valid | main_litedramcore_bankmachine1_source_source_valid); +assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_source_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; +always @(*) begin + main_litedramcore_bankmachine1_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin + main_litedramcore_bankmachine1_cmd_payload_a <= main_litedramcore_bankmachine1_source_source_payload_addr[21:7]; + end else begin + main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write); +assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); +assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); +always @(*) begin + main_litedramcore_bankmachine1_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine1_source_valid & main_litedramcore_bankmachine1_source_source_valid)) begin + if ((main_litedramcore_bankmachine1_source_payload_addr[21:7] != main_litedramcore_bankmachine1_source_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine1_syncfifo1_din = {main_litedramcore_bankmachine1_fifo_in_last, main_litedramcore_bankmachine1_fifo_in_first, main_litedramcore_bankmachine1_fifo_in_payload_addr, main_litedramcore_bankmachine1_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout; +assign main_litedramcore_bankmachine1_sink_ready = main_litedramcore_bankmachine1_syncfifo1_writable; +assign main_litedramcore_bankmachine1_syncfifo1_we = main_litedramcore_bankmachine1_sink_valid; +assign main_litedramcore_bankmachine1_fifo_in_first = main_litedramcore_bankmachine1_sink_first; +assign main_litedramcore_bankmachine1_fifo_in_last = main_litedramcore_bankmachine1_sink_last; +assign main_litedramcore_bankmachine1_fifo_in_payload_we = main_litedramcore_bankmachine1_sink_payload_we; +assign main_litedramcore_bankmachine1_fifo_in_payload_addr = main_litedramcore_bankmachine1_sink_payload_addr; +assign main_litedramcore_bankmachine1_source_valid = main_litedramcore_bankmachine1_syncfifo1_readable; +assign main_litedramcore_bankmachine1_source_first = main_litedramcore_bankmachine1_fifo_out_first; +assign main_litedramcore_bankmachine1_source_last = main_litedramcore_bankmachine1_fifo_out_last; +assign main_litedramcore_bankmachine1_source_payload_we = main_litedramcore_bankmachine1_fifo_out_payload_we; +assign main_litedramcore_bankmachine1_source_payload_addr = main_litedramcore_bankmachine1_fifo_out_payload_addr; +assign main_litedramcore_bankmachine1_syncfifo1_re = main_litedramcore_bankmachine1_source_ready; +always @(*) begin + main_litedramcore_bankmachine1_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine1_replace) begin + main_litedramcore_bankmachine1_wrport_adr <= (main_litedramcore_bankmachine1_produce - 1'd1); + end else begin + main_litedramcore_bankmachine1_wrport_adr <= main_litedramcore_bankmachine1_produce; + end +end +assign main_litedramcore_bankmachine1_wrport_dat_w = main_litedramcore_bankmachine1_syncfifo1_din; +assign main_litedramcore_bankmachine1_wrport_we = (main_litedramcore_bankmachine1_syncfifo1_we & (main_litedramcore_bankmachine1_syncfifo1_writable | main_litedramcore_bankmachine1_replace)); +assign main_litedramcore_bankmachine1_do_read = (main_litedramcore_bankmachine1_syncfifo1_readable & main_litedramcore_bankmachine1_syncfifo1_re); +assign main_litedramcore_bankmachine1_rdport_adr = main_litedramcore_bankmachine1_consume; +assign main_litedramcore_bankmachine1_syncfifo1_dout = main_litedramcore_bankmachine1_rdport_dat_r; +assign main_litedramcore_bankmachine1_syncfifo1_writable = (main_litedramcore_bankmachine1_level != 5'd16); +assign main_litedramcore_bankmachine1_syncfifo1_readable = (main_litedramcore_bankmachine1_level != 1'd0); +assign main_litedramcore_bankmachine1_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine1_pipe_valid_source_valid) | main_litedramcore_bankmachine1_pipe_valid_source_ready); +assign main_litedramcore_bankmachine1_pipe_valid_sink_valid = main_litedramcore_bankmachine1_sink_sink_valid; +assign main_litedramcore_bankmachine1_sink_sink_ready = main_litedramcore_bankmachine1_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine1_pipe_valid_sink_first = main_litedramcore_bankmachine1_sink_sink_first; +assign main_litedramcore_bankmachine1_pipe_valid_sink_last = main_litedramcore_bankmachine1_sink_sink_last; +assign main_litedramcore_bankmachine1_pipe_valid_sink_payload_we = main_litedramcore_bankmachine1_sink_sink_payload_we; +assign main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine1_sink_sink_payload_addr; +assign main_litedramcore_bankmachine1_source_source_valid = main_litedramcore_bankmachine1_pipe_valid_source_valid; +assign main_litedramcore_bankmachine1_pipe_valid_source_ready = main_litedramcore_bankmachine1_source_source_ready; +assign main_litedramcore_bankmachine1_source_source_first = main_litedramcore_bankmachine1_pipe_valid_source_first; +assign main_litedramcore_bankmachine1_source_source_last = main_litedramcore_bankmachine1_pipe_valid_source_last; +assign main_litedramcore_bankmachine1_source_source_payload_we = main_litedramcore_bankmachine1_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine1_source_source_payload_addr = main_litedramcore_bankmachine1_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine1_next_state <= 4'd0; + builder_bankmachine1_next_state <= builder_bankmachine1_state; + case (builder_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + if (main_litedramcore_bankmachine1_cmd_ready) begin + builder_bankmachine1_next_state <= 3'd5; + end end end 2'd2: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + builder_bankmachine1_next_state <= 3'd5; + end end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + if (main_litedramcore_bankmachine1_cmd_ready) begin + builder_bankmachine1_next_state <= 3'd7; + end end end 3'd4: begin + if ((~main_litedramcore_bankmachine1_refresh_req)) begin + builder_bankmachine1_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine1_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine1_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine1_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine1_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin + builder_bankmachine1_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if ((main_litedramcore_bankmachine1_cmd_ready & main_litedramcore_bankmachine1_auto_precharge)) begin + builder_bankmachine1_next_state <= 2'd2; + end end else begin + builder_bankmachine1_next_state <= 1'd1; end end else begin + builder_bankmachine1_next_state <= 2'd3; end end end end endcase end -assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid; -assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready; -assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we; -assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr; -assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid; -assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready; -assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first; -assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last; -assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we; -assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr; -assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); -assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid); -assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[21:7]); -assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1; -always @(*) begin - litedramcore_bankmachine1_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine1_row_col_n_addr_sel) begin - litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_source_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write); -assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); -assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); -always @(*) begin - litedramcore_bankmachine1_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin - if ((litedramcore_bankmachine1_source_payload_addr[21:7] != litedramcore_bankmachine1_source_source_payload_addr[21:7])) begin - litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we}; -assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; -assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; -assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; -assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; -assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable; -assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid; -assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first; -assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last; -assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we; -assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr; -assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable; -assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first; -assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last; -assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we; -assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr; -assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready; -always @(*) begin - litedramcore_bankmachine1_wrport_adr <= 4'd0; - if (litedramcore_bankmachine1_replace) begin - litedramcore_bankmachine1_wrport_adr <= (litedramcore_bankmachine1_produce - 1'd1); - end else begin - litedramcore_bankmachine1_wrport_adr <= litedramcore_bankmachine1_produce; - end -end -assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din; -assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace)); -assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re); -assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume; -assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r; -assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 5'd16); -assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0); -assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready); -assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid; -assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready; -assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first; -assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last; -assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we; -assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr; -assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid; -assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready; -assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first; -assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last; -assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we; -assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine1_next_state <= 4'd0; - litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - if (litedramcore_bankmachine1_cmd_ready) begin - litedramcore_bankmachine1_next_state <= 3'd5; - end - end +always @(*) begin + main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (builder_bankmachine1_state) + 1'd1: begin end 2'd2: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - if (litedramcore_bankmachine1_cmd_ready) begin - litedramcore_bankmachine1_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~litedramcore_bankmachine1_refresh_req)) begin - litedramcore_bankmachine1_next_state <= 1'd0; - end end 3'd5: begin - litedramcore_bankmachine1_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine1_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine1_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine1_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - litedramcore_bankmachine1_next_state <= 3'd4; + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin - litedramcore_bankmachine1_next_state <= 2'd2; - end + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; end else begin - litedramcore_bankmachine1_next_state <= 1'd1; end end else begin - litedramcore_bankmachine1_next_state <= 2'd3; end end end @@ -5459,11 +5913,40 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (builder_bankmachine1_state) + 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -5481,13 +5964,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -5500,22 +5983,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5530,8 +6013,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -5549,14 +6032,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin end else begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; end end else begin end @@ -5568,8 +6051,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -5587,13 +6070,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin + main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -5606,8 +6089,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -5625,13 +6108,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin + main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready; end else begin end end else begin @@ -5644,8 +6127,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -5663,14 +6146,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin end else begin - litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; + main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready; end end else begin end @@ -5682,18 +6165,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine1_twtpcon_ready) begin + main_litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -5708,15 +6191,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_row_open <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_row_open <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_open <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_row_open <= 1'd1; end end 3'd4: begin @@ -5734,18 +6217,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_valid <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; end end 3'd4: begin @@ -5759,12 +6242,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; end else begin end end else begin @@ -5775,18 +6258,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_row_close <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_row_close <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - litedramcore_bankmachine1_row_close <= 1'd1; + main_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine1_row_close <= 1'd1; + main_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine1_row_close <= 1'd1; + main_litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -5801,18 +6284,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine1_twtpcon_ready) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -5826,35 +6309,139 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine1_state) +assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid; +assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready; +assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we; +assign main_litedramcore_bankmachine2_sink_payload_addr = main_litedramcore_bankmachine2_req_addr; +assign main_litedramcore_bankmachine2_sink_sink_valid = main_litedramcore_bankmachine2_source_valid; +assign main_litedramcore_bankmachine2_source_ready = main_litedramcore_bankmachine2_sink_sink_ready; +assign main_litedramcore_bankmachine2_sink_sink_first = main_litedramcore_bankmachine2_source_first; +assign main_litedramcore_bankmachine2_sink_sink_last = main_litedramcore_bankmachine2_source_last; +assign main_litedramcore_bankmachine2_sink_sink_payload_we = main_litedramcore_bankmachine2_source_payload_we; +assign main_litedramcore_bankmachine2_sink_sink_payload_addr = main_litedramcore_bankmachine2_source_payload_addr; +assign main_litedramcore_bankmachine2_source_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid); +assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_source_valid | main_litedramcore_bankmachine2_source_source_valid); +assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_source_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; +always @(*) begin + main_litedramcore_bankmachine2_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin + main_litedramcore_bankmachine2_cmd_payload_a <= main_litedramcore_bankmachine2_source_source_payload_addr[21:7]; + end else begin + main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write); +assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); +assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); +always @(*) begin + main_litedramcore_bankmachine2_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine2_source_valid & main_litedramcore_bankmachine2_source_source_valid)) begin + if ((main_litedramcore_bankmachine2_source_payload_addr[21:7] != main_litedramcore_bankmachine2_source_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine2_syncfifo2_din = {main_litedramcore_bankmachine2_fifo_in_last, main_litedramcore_bankmachine2_fifo_in_first, main_litedramcore_bankmachine2_fifo_in_payload_addr, main_litedramcore_bankmachine2_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; +assign main_litedramcore_bankmachine2_sink_ready = main_litedramcore_bankmachine2_syncfifo2_writable; +assign main_litedramcore_bankmachine2_syncfifo2_we = main_litedramcore_bankmachine2_sink_valid; +assign main_litedramcore_bankmachine2_fifo_in_first = main_litedramcore_bankmachine2_sink_first; +assign main_litedramcore_bankmachine2_fifo_in_last = main_litedramcore_bankmachine2_sink_last; +assign main_litedramcore_bankmachine2_fifo_in_payload_we = main_litedramcore_bankmachine2_sink_payload_we; +assign main_litedramcore_bankmachine2_fifo_in_payload_addr = main_litedramcore_bankmachine2_sink_payload_addr; +assign main_litedramcore_bankmachine2_source_valid = main_litedramcore_bankmachine2_syncfifo2_readable; +assign main_litedramcore_bankmachine2_source_first = main_litedramcore_bankmachine2_fifo_out_first; +assign main_litedramcore_bankmachine2_source_last = main_litedramcore_bankmachine2_fifo_out_last; +assign main_litedramcore_bankmachine2_source_payload_we = main_litedramcore_bankmachine2_fifo_out_payload_we; +assign main_litedramcore_bankmachine2_source_payload_addr = main_litedramcore_bankmachine2_fifo_out_payload_addr; +assign main_litedramcore_bankmachine2_syncfifo2_re = main_litedramcore_bankmachine2_source_ready; +always @(*) begin + main_litedramcore_bankmachine2_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine2_replace) begin + main_litedramcore_bankmachine2_wrport_adr <= (main_litedramcore_bankmachine2_produce - 1'd1); + end else begin + main_litedramcore_bankmachine2_wrport_adr <= main_litedramcore_bankmachine2_produce; + end +end +assign main_litedramcore_bankmachine2_wrport_dat_w = main_litedramcore_bankmachine2_syncfifo2_din; +assign main_litedramcore_bankmachine2_wrport_we = (main_litedramcore_bankmachine2_syncfifo2_we & (main_litedramcore_bankmachine2_syncfifo2_writable | main_litedramcore_bankmachine2_replace)); +assign main_litedramcore_bankmachine2_do_read = (main_litedramcore_bankmachine2_syncfifo2_readable & main_litedramcore_bankmachine2_syncfifo2_re); +assign main_litedramcore_bankmachine2_rdport_adr = main_litedramcore_bankmachine2_consume; +assign main_litedramcore_bankmachine2_syncfifo2_dout = main_litedramcore_bankmachine2_rdport_dat_r; +assign main_litedramcore_bankmachine2_syncfifo2_writable = (main_litedramcore_bankmachine2_level != 5'd16); +assign main_litedramcore_bankmachine2_syncfifo2_readable = (main_litedramcore_bankmachine2_level != 1'd0); +assign main_litedramcore_bankmachine2_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine2_pipe_valid_source_valid) | main_litedramcore_bankmachine2_pipe_valid_source_ready); +assign main_litedramcore_bankmachine2_pipe_valid_sink_valid = main_litedramcore_bankmachine2_sink_sink_valid; +assign main_litedramcore_bankmachine2_sink_sink_ready = main_litedramcore_bankmachine2_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine2_pipe_valid_sink_first = main_litedramcore_bankmachine2_sink_sink_first; +assign main_litedramcore_bankmachine2_pipe_valid_sink_last = main_litedramcore_bankmachine2_sink_sink_last; +assign main_litedramcore_bankmachine2_pipe_valid_sink_payload_we = main_litedramcore_bankmachine2_sink_sink_payload_we; +assign main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine2_sink_sink_payload_addr; +assign main_litedramcore_bankmachine2_source_source_valid = main_litedramcore_bankmachine2_pipe_valid_source_valid; +assign main_litedramcore_bankmachine2_pipe_valid_source_ready = main_litedramcore_bankmachine2_source_source_ready; +assign main_litedramcore_bankmachine2_source_source_first = main_litedramcore_bankmachine2_pipe_valid_source_first; +assign main_litedramcore_bankmachine2_source_source_last = main_litedramcore_bankmachine2_pipe_valid_source_last; +assign main_litedramcore_bankmachine2_source_source_payload_we = main_litedramcore_bankmachine2_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine2_source_source_payload_addr = main_litedramcore_bankmachine2_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine2_next_state <= 4'd0; + builder_bankmachine2_next_state <= builder_bankmachine2_state; + case (builder_bankmachine2_state) 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + if (main_litedramcore_bankmachine2_cmd_ready) begin + builder_bankmachine2_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + builder_bankmachine2_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + if (main_litedramcore_bankmachine2_cmd_ready) begin + builder_bankmachine2_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine2_refresh_req)) begin + builder_bankmachine2_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine2_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine2_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine2_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine2_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin + builder_bankmachine2_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if ((main_litedramcore_bankmachine2_cmd_ready & main_litedramcore_bankmachine2_auto_precharge)) begin + builder_bankmachine2_next_state <= 2'd2; + end end else begin + builder_bankmachine2_next_state <= 1'd1; end end else begin + builder_bankmachine2_next_state <= 2'd3; end end end @@ -5862,21 +6449,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5890,139 +6478,38 @@ always @(*) begin end endcase end -assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid; -assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready; -assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we; -assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr; -assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid; -assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready; -assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first; -assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last; -assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we; -assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr; -assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); -assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid); -assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[21:7]); -assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2; -always @(*) begin - litedramcore_bankmachine2_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine2_row_col_n_addr_sel) begin - litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_source_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write); -assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); -assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); -always @(*) begin - litedramcore_bankmachine2_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin - if ((litedramcore_bankmachine2_source_payload_addr[21:7] != litedramcore_bankmachine2_source_source_payload_addr[21:7])) begin - litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we}; -assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; -assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; -assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; -assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; -assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable; -assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid; -assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first; -assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last; -assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we; -assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr; -assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable; -assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first; -assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last; -assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we; -assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr; -assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready; -always @(*) begin - litedramcore_bankmachine2_wrport_adr <= 4'd0; - if (litedramcore_bankmachine2_replace) begin - litedramcore_bankmachine2_wrport_adr <= (litedramcore_bankmachine2_produce - 1'd1); - end else begin - litedramcore_bankmachine2_wrport_adr <= litedramcore_bankmachine2_produce; - end -end -assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din; -assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace)); -assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re); -assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume; -assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r; -assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 5'd16); -assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0); -assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready); -assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid; -assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready; -assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first; -assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last; -assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we; -assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr; -assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid; -assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready; -assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first; -assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last; -assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we; -assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine2_next_state <= 4'd0; - litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - if (litedramcore_bankmachine2_cmd_ready) begin - litedramcore_bankmachine2_next_state <= 3'd5; - end - end +always @(*) begin + main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine2_state) + 1'd1: begin end 2'd2: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - if (litedramcore_bankmachine2_cmd_ready) begin - litedramcore_bankmachine2_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~litedramcore_bankmachine2_refresh_req)) begin - litedramcore_bankmachine2_next_state <= 1'd0; - end end 3'd5: begin - litedramcore_bankmachine2_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine2_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine2_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine2_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - litedramcore_bankmachine2_next_state <= 3'd4; + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin - litedramcore_bankmachine2_next_state <= 2'd2; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin + end else begin + main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; end end else begin - litedramcore_bankmachine2_next_state <= 1'd1; end end else begin - litedramcore_bankmachine2_next_state <= 2'd3; end end end @@ -6030,8 +6517,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6049,13 +6536,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin - litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin + main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -6068,8 +6555,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6087,14 +6574,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin + main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready; end else begin - litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; end end else begin end @@ -6106,8 +6593,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6115,9 +6602,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine2_twtpcon_ready) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -6128,22 +6612,37 @@ always @(*) begin 4'd8: begin end default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_row_open <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin + end else begin + main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (builder_bankmachine2_state) + 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine2_twtpcon_ready) begin + main_litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -6158,18 +6657,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_valid <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_row_open <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_row_open <= 1'd1; end end 3'd4: begin @@ -6183,34 +6679,25 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine2_row_close <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_valid <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - litedramcore_bankmachine2_row_close <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 2'd2: begin - litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 3'd4: begin - litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -6221,22 +6708,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_row_close <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin + main_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin + main_litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -6251,16 +6750,16 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -6273,27 +6772,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6311,12 +6795,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -6327,18 +6811,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -6356,22 +6840,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6382,41 +6862,157 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine2_state) +assign main_litedramcore_bankmachine3_sink_valid = main_litedramcore_bankmachine3_req_valid; +assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_sink_ready; +assign main_litedramcore_bankmachine3_sink_payload_we = main_litedramcore_bankmachine3_req_we; +assign main_litedramcore_bankmachine3_sink_payload_addr = main_litedramcore_bankmachine3_req_addr; +assign main_litedramcore_bankmachine3_sink_sink_valid = main_litedramcore_bankmachine3_source_valid; +assign main_litedramcore_bankmachine3_source_ready = main_litedramcore_bankmachine3_sink_sink_ready; +assign main_litedramcore_bankmachine3_sink_sink_first = main_litedramcore_bankmachine3_source_first; +assign main_litedramcore_bankmachine3_sink_sink_last = main_litedramcore_bankmachine3_source_last; +assign main_litedramcore_bankmachine3_sink_sink_payload_we = main_litedramcore_bankmachine3_source_payload_we; +assign main_litedramcore_bankmachine3_sink_sink_payload_addr = main_litedramcore_bankmachine3_source_payload_addr; +assign main_litedramcore_bankmachine3_source_source_ready = (main_litedramcore_bankmachine3_req_wdata_ready | main_litedramcore_bankmachine3_req_rdata_valid); +assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_source_valid | main_litedramcore_bankmachine3_source_source_valid); +assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_source_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; +always @(*) begin + main_litedramcore_bankmachine3_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin + main_litedramcore_bankmachine3_cmd_payload_a <= main_litedramcore_bankmachine3_source_source_payload_addr[21:7]; + end else begin + main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write); +assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); +assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); +always @(*) begin + main_litedramcore_bankmachine3_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine3_source_valid & main_litedramcore_bankmachine3_source_source_valid)) begin + if ((main_litedramcore_bankmachine3_source_payload_addr[21:7] != main_litedramcore_bankmachine3_source_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine3_syncfifo3_din = {main_litedramcore_bankmachine3_fifo_in_last, main_litedramcore_bankmachine3_fifo_in_first, main_litedramcore_bankmachine3_fifo_in_payload_addr, main_litedramcore_bankmachine3_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout; +assign main_litedramcore_bankmachine3_sink_ready = main_litedramcore_bankmachine3_syncfifo3_writable; +assign main_litedramcore_bankmachine3_syncfifo3_we = main_litedramcore_bankmachine3_sink_valid; +assign main_litedramcore_bankmachine3_fifo_in_first = main_litedramcore_bankmachine3_sink_first; +assign main_litedramcore_bankmachine3_fifo_in_last = main_litedramcore_bankmachine3_sink_last; +assign main_litedramcore_bankmachine3_fifo_in_payload_we = main_litedramcore_bankmachine3_sink_payload_we; +assign main_litedramcore_bankmachine3_fifo_in_payload_addr = main_litedramcore_bankmachine3_sink_payload_addr; +assign main_litedramcore_bankmachine3_source_valid = main_litedramcore_bankmachine3_syncfifo3_readable; +assign main_litedramcore_bankmachine3_source_first = main_litedramcore_bankmachine3_fifo_out_first; +assign main_litedramcore_bankmachine3_source_last = main_litedramcore_bankmachine3_fifo_out_last; +assign main_litedramcore_bankmachine3_source_payload_we = main_litedramcore_bankmachine3_fifo_out_payload_we; +assign main_litedramcore_bankmachine3_source_payload_addr = main_litedramcore_bankmachine3_fifo_out_payload_addr; +assign main_litedramcore_bankmachine3_syncfifo3_re = main_litedramcore_bankmachine3_source_ready; +always @(*) begin + main_litedramcore_bankmachine3_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine3_replace) begin + main_litedramcore_bankmachine3_wrport_adr <= (main_litedramcore_bankmachine3_produce - 1'd1); + end else begin + main_litedramcore_bankmachine3_wrport_adr <= main_litedramcore_bankmachine3_produce; + end +end +assign main_litedramcore_bankmachine3_wrport_dat_w = main_litedramcore_bankmachine3_syncfifo3_din; +assign main_litedramcore_bankmachine3_wrport_we = (main_litedramcore_bankmachine3_syncfifo3_we & (main_litedramcore_bankmachine3_syncfifo3_writable | main_litedramcore_bankmachine3_replace)); +assign main_litedramcore_bankmachine3_do_read = (main_litedramcore_bankmachine3_syncfifo3_readable & main_litedramcore_bankmachine3_syncfifo3_re); +assign main_litedramcore_bankmachine3_rdport_adr = main_litedramcore_bankmachine3_consume; +assign main_litedramcore_bankmachine3_syncfifo3_dout = main_litedramcore_bankmachine3_rdport_dat_r; +assign main_litedramcore_bankmachine3_syncfifo3_writable = (main_litedramcore_bankmachine3_level != 5'd16); +assign main_litedramcore_bankmachine3_syncfifo3_readable = (main_litedramcore_bankmachine3_level != 1'd0); +assign main_litedramcore_bankmachine3_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine3_pipe_valid_source_valid) | main_litedramcore_bankmachine3_pipe_valid_source_ready); +assign main_litedramcore_bankmachine3_pipe_valid_sink_valid = main_litedramcore_bankmachine3_sink_sink_valid; +assign main_litedramcore_bankmachine3_sink_sink_ready = main_litedramcore_bankmachine3_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine3_pipe_valid_sink_first = main_litedramcore_bankmachine3_sink_sink_first; +assign main_litedramcore_bankmachine3_pipe_valid_sink_last = main_litedramcore_bankmachine3_sink_sink_last; +assign main_litedramcore_bankmachine3_pipe_valid_sink_payload_we = main_litedramcore_bankmachine3_sink_sink_payload_we; +assign main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine3_sink_sink_payload_addr; +assign main_litedramcore_bankmachine3_source_source_valid = main_litedramcore_bankmachine3_pipe_valid_source_valid; +assign main_litedramcore_bankmachine3_pipe_valid_source_ready = main_litedramcore_bankmachine3_source_source_ready; +assign main_litedramcore_bankmachine3_source_source_first = main_litedramcore_bankmachine3_pipe_valid_source_first; +assign main_litedramcore_bankmachine3_source_source_last = main_litedramcore_bankmachine3_pipe_valid_source_last; +assign main_litedramcore_bankmachine3_source_source_payload_we = main_litedramcore_bankmachine3_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine3_source_source_payload_addr = main_litedramcore_bankmachine3_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine3_next_state <= 4'd0; + builder_bankmachine3_next_state <= builder_bankmachine3_state; + case (builder_bankmachine3_state) 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + if (main_litedramcore_bankmachine3_cmd_ready) begin + builder_bankmachine3_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + builder_bankmachine3_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + if (main_litedramcore_bankmachine3_cmd_ready) begin + builder_bankmachine3_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine3_refresh_req)) begin + builder_bankmachine3_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine3_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine3_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine3_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine3_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin + builder_bankmachine3_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin - end else begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin + builder_bankmachine3_next_state <= 2'd2; end end else begin + builder_bankmachine3_next_state <= 1'd1; end end else begin + builder_bankmachine3_next_state <= 2'd3; end end end @@ -6424,8 +7020,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -6443,14 +7039,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin end else begin + main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready; end end else begin end @@ -6461,155 +7057,42 @@ always @(*) begin end endcase end -assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid; -assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready; -assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we; -assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr; -assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid; -assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready; -assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first; -assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last; -assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we; -assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr; -assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); -assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid); -assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[21:7]); -assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3; -always @(*) begin - litedramcore_bankmachine3_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine3_row_col_n_addr_sel) begin - litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_source_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write); -assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); -assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); -always @(*) begin - litedramcore_bankmachine3_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin - if ((litedramcore_bankmachine3_source_payload_addr[21:7] != litedramcore_bankmachine3_source_source_payload_addr[21:7])) begin - litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we}; -assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; -assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; -assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; -assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; -assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable; -assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid; -assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first; -assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last; -assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we; -assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr; -assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable; -assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first; -assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last; -assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we; -assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr; -assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready; -always @(*) begin - litedramcore_bankmachine3_wrport_adr <= 4'd0; - if (litedramcore_bankmachine3_replace) begin - litedramcore_bankmachine3_wrport_adr <= (litedramcore_bankmachine3_produce - 1'd1); - end else begin - litedramcore_bankmachine3_wrport_adr <= litedramcore_bankmachine3_produce; - end -end -assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din; -assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace)); -assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re); -assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume; -assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r; -assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 5'd16); -assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0); -assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready); -assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid; -assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready; -assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first; -assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last; -assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we; -assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr; -assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid; -assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready; -assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first; -assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last; -assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we; -assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine3_next_state <= 4'd0; - litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - if (litedramcore_bankmachine3_cmd_ready) begin - litedramcore_bankmachine3_next_state <= 3'd5; - end - end +always @(*) begin + main_litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (builder_bankmachine3_state) + 1'd1: begin end 2'd2: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - if (litedramcore_bankmachine3_cmd_ready) begin - litedramcore_bankmachine3_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~litedramcore_bankmachine3_refresh_req)) begin - litedramcore_bankmachine3_next_state <= 1'd0; + if (main_litedramcore_bankmachine3_twtpcon_ready) begin + main_litedramcore_bankmachine3_refresh_gnt <= 1'd1; end end 3'd5: begin - litedramcore_bankmachine3_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine3_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine3_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine3_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - litedramcore_bankmachine3_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin - litedramcore_bankmachine3_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine3_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine3_next_state <= 2'd3; - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine3_row_open <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_row_open <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_open <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_open <= 1'd1; end end 3'd4: begin @@ -6627,18 +7110,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_valid <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; end end 3'd4: begin @@ -6652,12 +7135,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; end else begin end end else begin @@ -6668,18 +7151,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_row_close <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_row_close <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - litedramcore_bankmachine3_row_close <= 1'd1; + main_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine3_row_close <= 1'd1; + main_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine3_row_close <= 1'd1; + main_litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -6694,15 +7177,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -6720,8 +7203,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -6739,12 +7222,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -6755,18 +7238,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -6784,11 +7267,11 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -6806,13 +7289,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -6825,22 +7308,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6855,8 +7338,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -6874,14 +7357,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin end else begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6893,8 +7376,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -6912,13 +7395,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin + main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -6931,8 +7414,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -6950,14 +7433,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin + main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready; end else begin - litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; end end else begin end @@ -6968,38 +7451,139 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine3_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine3_state) +assign main_litedramcore_bankmachine4_sink_valid = main_litedramcore_bankmachine4_req_valid; +assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_sink_ready; +assign main_litedramcore_bankmachine4_sink_payload_we = main_litedramcore_bankmachine4_req_we; +assign main_litedramcore_bankmachine4_sink_payload_addr = main_litedramcore_bankmachine4_req_addr; +assign main_litedramcore_bankmachine4_sink_sink_valid = main_litedramcore_bankmachine4_source_valid; +assign main_litedramcore_bankmachine4_source_ready = main_litedramcore_bankmachine4_sink_sink_ready; +assign main_litedramcore_bankmachine4_sink_sink_first = main_litedramcore_bankmachine4_source_first; +assign main_litedramcore_bankmachine4_sink_sink_last = main_litedramcore_bankmachine4_source_last; +assign main_litedramcore_bankmachine4_sink_sink_payload_we = main_litedramcore_bankmachine4_source_payload_we; +assign main_litedramcore_bankmachine4_sink_sink_payload_addr = main_litedramcore_bankmachine4_source_payload_addr; +assign main_litedramcore_bankmachine4_source_source_ready = (main_litedramcore_bankmachine4_req_wdata_ready | main_litedramcore_bankmachine4_req_rdata_valid); +assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_source_valid | main_litedramcore_bankmachine4_source_source_valid); +assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_source_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; +always @(*) begin + main_litedramcore_bankmachine4_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin + main_litedramcore_bankmachine4_cmd_payload_a <= main_litedramcore_bankmachine4_source_source_payload_addr[21:7]; + end else begin + main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write); +assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); +assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); +always @(*) begin + main_litedramcore_bankmachine4_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine4_source_valid & main_litedramcore_bankmachine4_source_source_valid)) begin + if ((main_litedramcore_bankmachine4_source_payload_addr[21:7] != main_litedramcore_bankmachine4_source_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine4_syncfifo4_din = {main_litedramcore_bankmachine4_fifo_in_last, main_litedramcore_bankmachine4_fifo_in_first, main_litedramcore_bankmachine4_fifo_in_payload_addr, main_litedramcore_bankmachine4_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout; +assign main_litedramcore_bankmachine4_sink_ready = main_litedramcore_bankmachine4_syncfifo4_writable; +assign main_litedramcore_bankmachine4_syncfifo4_we = main_litedramcore_bankmachine4_sink_valid; +assign main_litedramcore_bankmachine4_fifo_in_first = main_litedramcore_bankmachine4_sink_first; +assign main_litedramcore_bankmachine4_fifo_in_last = main_litedramcore_bankmachine4_sink_last; +assign main_litedramcore_bankmachine4_fifo_in_payload_we = main_litedramcore_bankmachine4_sink_payload_we; +assign main_litedramcore_bankmachine4_fifo_in_payload_addr = main_litedramcore_bankmachine4_sink_payload_addr; +assign main_litedramcore_bankmachine4_source_valid = main_litedramcore_bankmachine4_syncfifo4_readable; +assign main_litedramcore_bankmachine4_source_first = main_litedramcore_bankmachine4_fifo_out_first; +assign main_litedramcore_bankmachine4_source_last = main_litedramcore_bankmachine4_fifo_out_last; +assign main_litedramcore_bankmachine4_source_payload_we = main_litedramcore_bankmachine4_fifo_out_payload_we; +assign main_litedramcore_bankmachine4_source_payload_addr = main_litedramcore_bankmachine4_fifo_out_payload_addr; +assign main_litedramcore_bankmachine4_syncfifo4_re = main_litedramcore_bankmachine4_source_ready; +always @(*) begin + main_litedramcore_bankmachine4_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine4_replace) begin + main_litedramcore_bankmachine4_wrport_adr <= (main_litedramcore_bankmachine4_produce - 1'd1); + end else begin + main_litedramcore_bankmachine4_wrport_adr <= main_litedramcore_bankmachine4_produce; + end +end +assign main_litedramcore_bankmachine4_wrport_dat_w = main_litedramcore_bankmachine4_syncfifo4_din; +assign main_litedramcore_bankmachine4_wrport_we = (main_litedramcore_bankmachine4_syncfifo4_we & (main_litedramcore_bankmachine4_syncfifo4_writable | main_litedramcore_bankmachine4_replace)); +assign main_litedramcore_bankmachine4_do_read = (main_litedramcore_bankmachine4_syncfifo4_readable & main_litedramcore_bankmachine4_syncfifo4_re); +assign main_litedramcore_bankmachine4_rdport_adr = main_litedramcore_bankmachine4_consume; +assign main_litedramcore_bankmachine4_syncfifo4_dout = main_litedramcore_bankmachine4_rdport_dat_r; +assign main_litedramcore_bankmachine4_syncfifo4_writable = (main_litedramcore_bankmachine4_level != 5'd16); +assign main_litedramcore_bankmachine4_syncfifo4_readable = (main_litedramcore_bankmachine4_level != 1'd0); +assign main_litedramcore_bankmachine4_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine4_pipe_valid_source_valid) | main_litedramcore_bankmachine4_pipe_valid_source_ready); +assign main_litedramcore_bankmachine4_pipe_valid_sink_valid = main_litedramcore_bankmachine4_sink_sink_valid; +assign main_litedramcore_bankmachine4_sink_sink_ready = main_litedramcore_bankmachine4_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine4_pipe_valid_sink_first = main_litedramcore_bankmachine4_sink_sink_first; +assign main_litedramcore_bankmachine4_pipe_valid_sink_last = main_litedramcore_bankmachine4_sink_sink_last; +assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_we = main_litedramcore_bankmachine4_sink_sink_payload_we; +assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine4_sink_sink_payload_addr; +assign main_litedramcore_bankmachine4_source_source_valid = main_litedramcore_bankmachine4_pipe_valid_source_valid; +assign main_litedramcore_bankmachine4_pipe_valid_source_ready = main_litedramcore_bankmachine4_source_source_ready; +assign main_litedramcore_bankmachine4_source_source_first = main_litedramcore_bankmachine4_pipe_valid_source_first; +assign main_litedramcore_bankmachine4_source_source_last = main_litedramcore_bankmachine4_pipe_valid_source_last; +assign main_litedramcore_bankmachine4_source_source_payload_we = main_litedramcore_bankmachine4_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine4_source_source_payload_addr = main_litedramcore_bankmachine4_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine4_next_state <= 4'd0; + builder_bankmachine4_next_state <= builder_bankmachine4_state; + case (builder_bankmachine4_state) 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + if (main_litedramcore_bankmachine4_cmd_ready) begin + builder_bankmachine4_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + builder_bankmachine4_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + if (main_litedramcore_bankmachine4_cmd_ready) begin + builder_bankmachine4_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine4_refresh_req)) begin + builder_bankmachine4_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine4_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine4_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine4_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine4_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin + builder_bankmachine4_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin - litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; - end else begin + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if ((main_litedramcore_bankmachine4_cmd_ready & main_litedramcore_bankmachine4_auto_precharge)) begin + builder_bankmachine4_next_state <= 2'd2; end end else begin + builder_bankmachine4_next_state <= 1'd1; end end else begin + builder_bankmachine4_next_state <= 2'd3; end end end @@ -7007,18 +7591,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine3_twtpcon_ready) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7032,139 +7616,35 @@ always @(*) begin end endcase end -assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid; -assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready; -assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we; -assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr; -assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid; -assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready; -assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first; -assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last; -assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we; -assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr; -assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); -assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid); -assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[21:7]); -assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4; -always @(*) begin - litedramcore_bankmachine4_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine4_row_col_n_addr_sel) begin - litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_source_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write); -assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); -assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); -always @(*) begin - litedramcore_bankmachine4_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin - if ((litedramcore_bankmachine4_source_payload_addr[21:7] != litedramcore_bankmachine4_source_source_payload_addr[21:7])) begin - litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we}; -assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; -assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; -assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; -assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; -assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable; -assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid; -assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first; -assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last; -assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we; -assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr; -assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable; -assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first; -assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last; -assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we; -assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr; -assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready; -always @(*) begin - litedramcore_bankmachine4_wrport_adr <= 4'd0; - if (litedramcore_bankmachine4_replace) begin - litedramcore_bankmachine4_wrport_adr <= (litedramcore_bankmachine4_produce - 1'd1); - end else begin - litedramcore_bankmachine4_wrport_adr <= litedramcore_bankmachine4_produce; - end -end -assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din; -assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace)); -assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re); -assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume; -assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r; -assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 5'd16); -assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0); -assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready); -assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid; -assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready; -assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first; -assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last; -assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we; -assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr; -assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid; -assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready; -assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first; -assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last; -assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we; -assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine4_next_state <= 4'd0; - litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - if (litedramcore_bankmachine4_cmd_ready) begin - litedramcore_bankmachine4_next_state <= 3'd5; - end - end +always @(*) begin + main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (builder_bankmachine4_state) + 1'd1: begin end 2'd2: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - if (litedramcore_bankmachine4_cmd_ready) begin - litedramcore_bankmachine4_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~litedramcore_bankmachine4_refresh_req)) begin - litedramcore_bankmachine4_next_state <= 1'd0; - end end 3'd5: begin - litedramcore_bankmachine4_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine4_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine4_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine4_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - litedramcore_bankmachine4_next_state <= 3'd4; + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin - litedramcore_bankmachine4_next_state <= 2'd2; - end + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; end else begin - litedramcore_bankmachine4_next_state <= 1'd1; end end else begin - litedramcore_bankmachine4_next_state <= 2'd3; end end end @@ -7172,18 +7652,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_row_close <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin + main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin + main_litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -7198,13 +7678,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -7217,35 +7703,20 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine4_cmd_valid <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -7258,12 +7729,15 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -7274,21 +7748,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7303,12 +7778,9 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -7325,14 +7797,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin end else begin + main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; end end else begin end @@ -7344,22 +7816,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7370,12 +7835,27 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin + main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7393,14 +7873,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin + main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready; end else begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; end end else begin end @@ -7412,8 +7892,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7431,14 +7911,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin end else begin + main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready; end end else begin end @@ -7450,8 +7930,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7459,6 +7939,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine4_twtpcon_ready) begin + main_litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -7469,32 +7952,20 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin - litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine4_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_row_open <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_row_open <= 1'd1; + end end 3'd4: begin end @@ -7507,37 +7978,25 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin - end else begin - litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_valid <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine4_twtpcon_ready) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7548,48 +8007,170 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end -always @(*) begin - litedramcore_bankmachine4_row_open <= 1'd0; - case (litedramcore_bankmachine4_state) +assign main_litedramcore_bankmachine5_sink_valid = main_litedramcore_bankmachine5_req_valid; +assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_sink_ready; +assign main_litedramcore_bankmachine5_sink_payload_we = main_litedramcore_bankmachine5_req_we; +assign main_litedramcore_bankmachine5_sink_payload_addr = main_litedramcore_bankmachine5_req_addr; +assign main_litedramcore_bankmachine5_sink_sink_valid = main_litedramcore_bankmachine5_source_valid; +assign main_litedramcore_bankmachine5_source_ready = main_litedramcore_bankmachine5_sink_sink_ready; +assign main_litedramcore_bankmachine5_sink_sink_first = main_litedramcore_bankmachine5_source_first; +assign main_litedramcore_bankmachine5_sink_sink_last = main_litedramcore_bankmachine5_source_last; +assign main_litedramcore_bankmachine5_sink_sink_payload_we = main_litedramcore_bankmachine5_source_payload_we; +assign main_litedramcore_bankmachine5_sink_sink_payload_addr = main_litedramcore_bankmachine5_source_payload_addr; +assign main_litedramcore_bankmachine5_source_source_ready = (main_litedramcore_bankmachine5_req_wdata_ready | main_litedramcore_bankmachine5_req_rdata_valid); +assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_source_valid | main_litedramcore_bankmachine5_source_source_valid); +assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_source_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5; +always @(*) begin + main_litedramcore_bankmachine5_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin + main_litedramcore_bankmachine5_cmd_payload_a <= main_litedramcore_bankmachine5_source_source_payload_addr[21:7]; + end else begin + main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write); +assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); +assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); +always @(*) begin + main_litedramcore_bankmachine5_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine5_source_valid & main_litedramcore_bankmachine5_source_source_valid)) begin + if ((main_litedramcore_bankmachine5_source_payload_addr[21:7] != main_litedramcore_bankmachine5_source_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine5_syncfifo5_din = {main_litedramcore_bankmachine5_fifo_in_last, main_litedramcore_bankmachine5_fifo_in_first, main_litedramcore_bankmachine5_fifo_in_payload_addr, main_litedramcore_bankmachine5_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout; +assign main_litedramcore_bankmachine5_sink_ready = main_litedramcore_bankmachine5_syncfifo5_writable; +assign main_litedramcore_bankmachine5_syncfifo5_we = main_litedramcore_bankmachine5_sink_valid; +assign main_litedramcore_bankmachine5_fifo_in_first = main_litedramcore_bankmachine5_sink_first; +assign main_litedramcore_bankmachine5_fifo_in_last = main_litedramcore_bankmachine5_sink_last; +assign main_litedramcore_bankmachine5_fifo_in_payload_we = main_litedramcore_bankmachine5_sink_payload_we; +assign main_litedramcore_bankmachine5_fifo_in_payload_addr = main_litedramcore_bankmachine5_sink_payload_addr; +assign main_litedramcore_bankmachine5_source_valid = main_litedramcore_bankmachine5_syncfifo5_readable; +assign main_litedramcore_bankmachine5_source_first = main_litedramcore_bankmachine5_fifo_out_first; +assign main_litedramcore_bankmachine5_source_last = main_litedramcore_bankmachine5_fifo_out_last; +assign main_litedramcore_bankmachine5_source_payload_we = main_litedramcore_bankmachine5_fifo_out_payload_we; +assign main_litedramcore_bankmachine5_source_payload_addr = main_litedramcore_bankmachine5_fifo_out_payload_addr; +assign main_litedramcore_bankmachine5_syncfifo5_re = main_litedramcore_bankmachine5_source_ready; +always @(*) begin + main_litedramcore_bankmachine5_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine5_replace) begin + main_litedramcore_bankmachine5_wrport_adr <= (main_litedramcore_bankmachine5_produce - 1'd1); + end else begin + main_litedramcore_bankmachine5_wrport_adr <= main_litedramcore_bankmachine5_produce; + end +end +assign main_litedramcore_bankmachine5_wrport_dat_w = main_litedramcore_bankmachine5_syncfifo5_din; +assign main_litedramcore_bankmachine5_wrport_we = (main_litedramcore_bankmachine5_syncfifo5_we & (main_litedramcore_bankmachine5_syncfifo5_writable | main_litedramcore_bankmachine5_replace)); +assign main_litedramcore_bankmachine5_do_read = (main_litedramcore_bankmachine5_syncfifo5_readable & main_litedramcore_bankmachine5_syncfifo5_re); +assign main_litedramcore_bankmachine5_rdport_adr = main_litedramcore_bankmachine5_consume; +assign main_litedramcore_bankmachine5_syncfifo5_dout = main_litedramcore_bankmachine5_rdport_dat_r; +assign main_litedramcore_bankmachine5_syncfifo5_writable = (main_litedramcore_bankmachine5_level != 5'd16); +assign main_litedramcore_bankmachine5_syncfifo5_readable = (main_litedramcore_bankmachine5_level != 1'd0); +assign main_litedramcore_bankmachine5_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine5_pipe_valid_source_valid) | main_litedramcore_bankmachine5_pipe_valid_source_ready); +assign main_litedramcore_bankmachine5_pipe_valid_sink_valid = main_litedramcore_bankmachine5_sink_sink_valid; +assign main_litedramcore_bankmachine5_sink_sink_ready = main_litedramcore_bankmachine5_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine5_pipe_valid_sink_first = main_litedramcore_bankmachine5_sink_sink_first; +assign main_litedramcore_bankmachine5_pipe_valid_sink_last = main_litedramcore_bankmachine5_sink_sink_last; +assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_we = main_litedramcore_bankmachine5_sink_sink_payload_we; +assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine5_sink_sink_payload_addr; +assign main_litedramcore_bankmachine5_source_source_valid = main_litedramcore_bankmachine5_pipe_valid_source_valid; +assign main_litedramcore_bankmachine5_pipe_valid_source_ready = main_litedramcore_bankmachine5_source_source_ready; +assign main_litedramcore_bankmachine5_source_source_first = main_litedramcore_bankmachine5_pipe_valid_source_first; +assign main_litedramcore_bankmachine5_source_source_last = main_litedramcore_bankmachine5_pipe_valid_source_last; +assign main_litedramcore_bankmachine5_source_source_payload_we = main_litedramcore_bankmachine5_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine5_source_source_payload_addr = main_litedramcore_bankmachine5_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine5_next_state <= 4'd0; + builder_bankmachine5_next_state <= builder_bankmachine5_state; + case (builder_bankmachine5_state) 1'd1: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + if (main_litedramcore_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + builder_bankmachine5_next_state <= 3'd5; + end end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_open <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + if (main_litedramcore_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd7; + end end end 3'd4: begin + if ((~main_litedramcore_bankmachine5_refresh_req)) begin + builder_bankmachine5_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine5_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine5_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine5_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine5_next_state <= 1'd0; end default: begin + if (main_litedramcore_bankmachine5_refresh_req) begin + builder_bankmachine5_next_state <= 3'd4; + end else begin + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin + builder_bankmachine5_next_state <= 2'd2; + end + end else begin + builder_bankmachine5_next_state <= 1'd1; + end + end else begin + builder_bankmachine5_next_state <= 2'd3; + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine4_row_close <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -7600,154 +8181,56 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end -assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid; -assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready; -assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we; -assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr; -assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid; -assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready; -assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first; -assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last; -assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we; -assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr; -assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); -assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid); -assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[21:7]); -assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5; -always @(*) begin - litedramcore_bankmachine5_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine5_row_col_n_addr_sel) begin - litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_source_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write); -assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); -assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); -always @(*) begin - litedramcore_bankmachine5_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin - if ((litedramcore_bankmachine5_source_payload_addr[21:7] != litedramcore_bankmachine5_source_source_payload_addr[21:7])) begin - litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we}; -assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; -assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; -assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; -assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; -assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable; -assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid; -assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first; -assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last; -assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we; -assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr; -assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable; -assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first; -assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last; -assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we; -assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr; -assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready; -always @(*) begin - litedramcore_bankmachine5_wrport_adr <= 4'd0; - if (litedramcore_bankmachine5_replace) begin - litedramcore_bankmachine5_wrport_adr <= (litedramcore_bankmachine5_produce - 1'd1); - end else begin - litedramcore_bankmachine5_wrport_adr <= litedramcore_bankmachine5_produce; - end -end -assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din; -assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace)); -assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re); -assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume; -assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r; -assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 5'd16); -assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0); -assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready); -assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid; -assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready; -assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first; -assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last; -assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we; -assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr; -assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid; -assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready; -assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first; -assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last; -assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we; -assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine5_next_state <= 4'd0; - litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - if (litedramcore_bankmachine5_cmd_ready) begin - litedramcore_bankmachine5_next_state <= 3'd5; - end +always @(*) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; end end 2'd2: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - if (litedramcore_bankmachine5_cmd_ready) begin - litedramcore_bankmachine5_next_state <= 3'd7; - end + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; end end 3'd4: begin - if ((~litedramcore_bankmachine5_refresh_req)) begin - litedramcore_bankmachine5_next_state <= 1'd0; - end end 3'd5: begin - litedramcore_bankmachine5_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine5_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine5_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine5_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - litedramcore_bankmachine5_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin - litedramcore_bankmachine5_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine5_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine5_next_state <= 2'd3; - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -7765,13 +8248,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -7784,22 +8267,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7814,8 +8297,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -7833,14 +8316,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin end else begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; end end else begin end @@ -7852,8 +8335,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -7871,13 +8354,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin + main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -7890,8 +8373,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -7909,13 +8392,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin - litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin + main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready; end else begin end end else begin @@ -7928,8 +8411,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -7947,14 +8430,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin end else begin - litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; + main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready; end end else begin end @@ -7966,8 +8449,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -7975,8 +8458,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine5_twtpcon_ready) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd1; + if (main_litedramcore_bankmachine5_twtpcon_ready) begin + main_litedramcore_bankmachine5_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -7992,15 +8475,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_row_open <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_row_open <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_open <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_row_open <= 1'd1; end end 3'd4: begin @@ -8018,18 +8501,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_valid <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; end end 3'd4: begin @@ -8043,12 +8526,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; end else begin end end else begin @@ -8059,18 +8542,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_row_close <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_row_close <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - litedramcore_bankmachine5_row_close <= 1'd1; + main_litedramcore_bankmachine5_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine5_row_close <= 1'd1; + main_litedramcore_bankmachine5_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine5_row_close <= 1'd1; + main_litedramcore_bankmachine5_row_close <= 1'd1; end 3'd5: begin end @@ -8085,15 +8568,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -8110,35 +8593,139 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine5_state) +assign main_litedramcore_bankmachine6_sink_valid = main_litedramcore_bankmachine6_req_valid; +assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_sink_ready; +assign main_litedramcore_bankmachine6_sink_payload_we = main_litedramcore_bankmachine6_req_we; +assign main_litedramcore_bankmachine6_sink_payload_addr = main_litedramcore_bankmachine6_req_addr; +assign main_litedramcore_bankmachine6_sink_sink_valid = main_litedramcore_bankmachine6_source_valid; +assign main_litedramcore_bankmachine6_source_ready = main_litedramcore_bankmachine6_sink_sink_ready; +assign main_litedramcore_bankmachine6_sink_sink_first = main_litedramcore_bankmachine6_source_first; +assign main_litedramcore_bankmachine6_sink_sink_last = main_litedramcore_bankmachine6_source_last; +assign main_litedramcore_bankmachine6_sink_sink_payload_we = main_litedramcore_bankmachine6_source_payload_we; +assign main_litedramcore_bankmachine6_sink_sink_payload_addr = main_litedramcore_bankmachine6_source_payload_addr; +assign main_litedramcore_bankmachine6_source_source_ready = (main_litedramcore_bankmachine6_req_wdata_ready | main_litedramcore_bankmachine6_req_rdata_valid); +assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_source_valid | main_litedramcore_bankmachine6_source_source_valid); +assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_source_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; +always @(*) begin + main_litedramcore_bankmachine6_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin + main_litedramcore_bankmachine6_cmd_payload_a <= main_litedramcore_bankmachine6_source_source_payload_addr[21:7]; + end else begin + main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write); +assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); +assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); +always @(*) begin + main_litedramcore_bankmachine6_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine6_source_valid & main_litedramcore_bankmachine6_source_source_valid)) begin + if ((main_litedramcore_bankmachine6_source_payload_addr[21:7] != main_litedramcore_bankmachine6_source_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine6_syncfifo6_din = {main_litedramcore_bankmachine6_fifo_in_last, main_litedramcore_bankmachine6_fifo_in_first, main_litedramcore_bankmachine6_fifo_in_payload_addr, main_litedramcore_bankmachine6_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout; +assign main_litedramcore_bankmachine6_sink_ready = main_litedramcore_bankmachine6_syncfifo6_writable; +assign main_litedramcore_bankmachine6_syncfifo6_we = main_litedramcore_bankmachine6_sink_valid; +assign main_litedramcore_bankmachine6_fifo_in_first = main_litedramcore_bankmachine6_sink_first; +assign main_litedramcore_bankmachine6_fifo_in_last = main_litedramcore_bankmachine6_sink_last; +assign main_litedramcore_bankmachine6_fifo_in_payload_we = main_litedramcore_bankmachine6_sink_payload_we; +assign main_litedramcore_bankmachine6_fifo_in_payload_addr = main_litedramcore_bankmachine6_sink_payload_addr; +assign main_litedramcore_bankmachine6_source_valid = main_litedramcore_bankmachine6_syncfifo6_readable; +assign main_litedramcore_bankmachine6_source_first = main_litedramcore_bankmachine6_fifo_out_first; +assign main_litedramcore_bankmachine6_source_last = main_litedramcore_bankmachine6_fifo_out_last; +assign main_litedramcore_bankmachine6_source_payload_we = main_litedramcore_bankmachine6_fifo_out_payload_we; +assign main_litedramcore_bankmachine6_source_payload_addr = main_litedramcore_bankmachine6_fifo_out_payload_addr; +assign main_litedramcore_bankmachine6_syncfifo6_re = main_litedramcore_bankmachine6_source_ready; +always @(*) begin + main_litedramcore_bankmachine6_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine6_replace) begin + main_litedramcore_bankmachine6_wrport_adr <= (main_litedramcore_bankmachine6_produce - 1'd1); + end else begin + main_litedramcore_bankmachine6_wrport_adr <= main_litedramcore_bankmachine6_produce; + end +end +assign main_litedramcore_bankmachine6_wrport_dat_w = main_litedramcore_bankmachine6_syncfifo6_din; +assign main_litedramcore_bankmachine6_wrport_we = (main_litedramcore_bankmachine6_syncfifo6_we & (main_litedramcore_bankmachine6_syncfifo6_writable | main_litedramcore_bankmachine6_replace)); +assign main_litedramcore_bankmachine6_do_read = (main_litedramcore_bankmachine6_syncfifo6_readable & main_litedramcore_bankmachine6_syncfifo6_re); +assign main_litedramcore_bankmachine6_rdport_adr = main_litedramcore_bankmachine6_consume; +assign main_litedramcore_bankmachine6_syncfifo6_dout = main_litedramcore_bankmachine6_rdport_dat_r; +assign main_litedramcore_bankmachine6_syncfifo6_writable = (main_litedramcore_bankmachine6_level != 5'd16); +assign main_litedramcore_bankmachine6_syncfifo6_readable = (main_litedramcore_bankmachine6_level != 1'd0); +assign main_litedramcore_bankmachine6_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine6_pipe_valid_source_valid) | main_litedramcore_bankmachine6_pipe_valid_source_ready); +assign main_litedramcore_bankmachine6_pipe_valid_sink_valid = main_litedramcore_bankmachine6_sink_sink_valid; +assign main_litedramcore_bankmachine6_sink_sink_ready = main_litedramcore_bankmachine6_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine6_pipe_valid_sink_first = main_litedramcore_bankmachine6_sink_sink_first; +assign main_litedramcore_bankmachine6_pipe_valid_sink_last = main_litedramcore_bankmachine6_sink_sink_last; +assign main_litedramcore_bankmachine6_pipe_valid_sink_payload_we = main_litedramcore_bankmachine6_sink_sink_payload_we; +assign main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine6_sink_sink_payload_addr; +assign main_litedramcore_bankmachine6_source_source_valid = main_litedramcore_bankmachine6_pipe_valid_source_valid; +assign main_litedramcore_bankmachine6_pipe_valid_source_ready = main_litedramcore_bankmachine6_source_source_ready; +assign main_litedramcore_bankmachine6_source_source_first = main_litedramcore_bankmachine6_pipe_valid_source_first; +assign main_litedramcore_bankmachine6_source_source_last = main_litedramcore_bankmachine6_pipe_valid_source_last; +assign main_litedramcore_bankmachine6_source_source_payload_we = main_litedramcore_bankmachine6_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine6_source_source_payload_addr = main_litedramcore_bankmachine6_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine6_next_state <= 4'd0; + builder_bankmachine6_next_state <= builder_bankmachine6_state; + case (builder_bankmachine6_state) 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + if (main_litedramcore_bankmachine6_cmd_ready) begin + builder_bankmachine6_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + builder_bankmachine6_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + if (main_litedramcore_bankmachine6_cmd_ready) begin + builder_bankmachine6_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine6_refresh_req)) begin + builder_bankmachine6_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine6_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine6_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine6_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine6_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin + builder_bankmachine6_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if ((main_litedramcore_bankmachine6_cmd_ready & main_litedramcore_bankmachine6_auto_precharge)) begin + builder_bankmachine6_next_state <= 2'd2; + end end else begin + builder_bankmachine6_next_state <= 1'd1; end end else begin + builder_bankmachine6_next_state <= 2'd3; end end end @@ -8146,21 +8733,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8174,139 +8762,76 @@ always @(*) begin end endcase end -assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid; -assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready; -assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we; -assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr; -assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid; -assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready; -assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first; -assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last; -assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we; -assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr; -assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); -assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid); -assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[21:7]); -assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6; -always @(*) begin - litedramcore_bankmachine6_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine6_row_col_n_addr_sel) begin - litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_source_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write); -assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); -assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); -always @(*) begin - litedramcore_bankmachine6_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin - if ((litedramcore_bankmachine6_source_payload_addr[21:7] != litedramcore_bankmachine6_source_source_payload_addr[21:7])) begin - litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we}; -assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; -assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; -assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; -assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; -assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable; -assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid; -assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first; -assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last; -assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we; -assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr; -assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable; -assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first; -assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last; -assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we; -assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr; -assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready; -always @(*) begin - litedramcore_bankmachine6_wrport_adr <= 4'd0; - if (litedramcore_bankmachine6_replace) begin - litedramcore_bankmachine6_wrport_adr <= (litedramcore_bankmachine6_produce - 1'd1); - end else begin - litedramcore_bankmachine6_wrport_adr <= litedramcore_bankmachine6_produce; - end -end -assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din; -assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace)); -assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re); -assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume; -assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r; -assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 5'd16); -assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0); -assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready); -assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid; -assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready; -assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first; -assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last; -assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we; -assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr; -assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid; -assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready; -assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first; -assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last; -assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we; -assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine6_next_state <= 4'd0; - litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - if (litedramcore_bankmachine6_cmd_ready) begin - litedramcore_bankmachine6_next_state <= 3'd5; - end - end +always @(*) begin + main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin end 2'd2: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - if (litedramcore_bankmachine6_cmd_ready) begin - litedramcore_bankmachine6_next_state <= 3'd7; + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin + end else begin + main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end end end end + endcase +end +always @(*) begin + main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end 3'd4: begin - if ((~litedramcore_bankmachine6_refresh_req)) begin - litedramcore_bankmachine6_next_state <= 1'd0; - end end 3'd5: begin - litedramcore_bankmachine6_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine6_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine6_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine6_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - litedramcore_bankmachine6_next_state <= 3'd4; + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin - litedramcore_bankmachine6_next_state <= 2'd2; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin + main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + end else begin end end else begin - litedramcore_bankmachine6_next_state <= 1'd1; end end else begin - litedramcore_bankmachine6_next_state <= 2'd3; end end end @@ -8314,8 +8839,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8333,13 +8858,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin - litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin + main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready; end else begin end end else begin @@ -8352,8 +8877,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8371,14 +8896,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin end else begin - litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; + main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready; end end else begin end @@ -8390,8 +8915,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8399,8 +8924,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine6_twtpcon_ready) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd1; + if (main_litedramcore_bankmachine6_twtpcon_ready) begin + main_litedramcore_bankmachine6_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -8416,15 +8941,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_row_open <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_row_open <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_open <= 1'd1; + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_open <= 1'd1; end end 3'd4: begin @@ -8442,18 +8967,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_valid <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_valid <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; end end 3'd4: begin @@ -8467,12 +8992,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; end else begin end end else begin @@ -8483,18 +9008,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_row_close <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_row_close <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - litedramcore_bankmachine6_row_close <= 1'd1; + main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine6_row_close <= 1'd1; + main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine6_row_close <= 1'd1; + main_litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -8509,15 +9034,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -8535,8 +9060,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8554,12 +9079,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -8570,18 +9095,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -8599,11 +9124,11 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -8621,13 +9146,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -8639,39 +9164,148 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine6_state) +assign main_litedramcore_bankmachine7_sink_valid = main_litedramcore_bankmachine7_req_valid; +assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_sink_ready; +assign main_litedramcore_bankmachine7_sink_payload_we = main_litedramcore_bankmachine7_req_we; +assign main_litedramcore_bankmachine7_sink_payload_addr = main_litedramcore_bankmachine7_req_addr; +assign main_litedramcore_bankmachine7_sink_sink_valid = main_litedramcore_bankmachine7_source_valid; +assign main_litedramcore_bankmachine7_source_ready = main_litedramcore_bankmachine7_sink_sink_ready; +assign main_litedramcore_bankmachine7_sink_sink_first = main_litedramcore_bankmachine7_source_first; +assign main_litedramcore_bankmachine7_sink_sink_last = main_litedramcore_bankmachine7_source_last; +assign main_litedramcore_bankmachine7_sink_sink_payload_we = main_litedramcore_bankmachine7_source_payload_we; +assign main_litedramcore_bankmachine7_sink_sink_payload_addr = main_litedramcore_bankmachine7_source_payload_addr; +assign main_litedramcore_bankmachine7_source_source_ready = (main_litedramcore_bankmachine7_req_wdata_ready | main_litedramcore_bankmachine7_req_rdata_valid); +assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_source_valid | main_litedramcore_bankmachine7_source_source_valid); +assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_source_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7; +always @(*) begin + main_litedramcore_bankmachine7_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin + main_litedramcore_bankmachine7_cmd_payload_a <= main_litedramcore_bankmachine7_source_source_payload_addr[21:7]; + end else begin + main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write); +assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); +assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); +always @(*) begin + main_litedramcore_bankmachine7_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine7_source_valid & main_litedramcore_bankmachine7_source_source_valid)) begin + if ((main_litedramcore_bankmachine7_source_payload_addr[21:7] != main_litedramcore_bankmachine7_source_source_payload_addr[21:7])) begin + main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine7_syncfifo7_din = {main_litedramcore_bankmachine7_fifo_in_last, main_litedramcore_bankmachine7_fifo_in_first, main_litedramcore_bankmachine7_fifo_in_payload_addr, main_litedramcore_bankmachine7_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout; +assign main_litedramcore_bankmachine7_sink_ready = main_litedramcore_bankmachine7_syncfifo7_writable; +assign main_litedramcore_bankmachine7_syncfifo7_we = main_litedramcore_bankmachine7_sink_valid; +assign main_litedramcore_bankmachine7_fifo_in_first = main_litedramcore_bankmachine7_sink_first; +assign main_litedramcore_bankmachine7_fifo_in_last = main_litedramcore_bankmachine7_sink_last; +assign main_litedramcore_bankmachine7_fifo_in_payload_we = main_litedramcore_bankmachine7_sink_payload_we; +assign main_litedramcore_bankmachine7_fifo_in_payload_addr = main_litedramcore_bankmachine7_sink_payload_addr; +assign main_litedramcore_bankmachine7_source_valid = main_litedramcore_bankmachine7_syncfifo7_readable; +assign main_litedramcore_bankmachine7_source_first = main_litedramcore_bankmachine7_fifo_out_first; +assign main_litedramcore_bankmachine7_source_last = main_litedramcore_bankmachine7_fifo_out_last; +assign main_litedramcore_bankmachine7_source_payload_we = main_litedramcore_bankmachine7_fifo_out_payload_we; +assign main_litedramcore_bankmachine7_source_payload_addr = main_litedramcore_bankmachine7_fifo_out_payload_addr; +assign main_litedramcore_bankmachine7_syncfifo7_re = main_litedramcore_bankmachine7_source_ready; +always @(*) begin + main_litedramcore_bankmachine7_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine7_replace) begin + main_litedramcore_bankmachine7_wrport_adr <= (main_litedramcore_bankmachine7_produce - 1'd1); + end else begin + main_litedramcore_bankmachine7_wrport_adr <= main_litedramcore_bankmachine7_produce; + end +end +assign main_litedramcore_bankmachine7_wrport_dat_w = main_litedramcore_bankmachine7_syncfifo7_din; +assign main_litedramcore_bankmachine7_wrport_we = (main_litedramcore_bankmachine7_syncfifo7_we & (main_litedramcore_bankmachine7_syncfifo7_writable | main_litedramcore_bankmachine7_replace)); +assign main_litedramcore_bankmachine7_do_read = (main_litedramcore_bankmachine7_syncfifo7_readable & main_litedramcore_bankmachine7_syncfifo7_re); +assign main_litedramcore_bankmachine7_rdport_adr = main_litedramcore_bankmachine7_consume; +assign main_litedramcore_bankmachine7_syncfifo7_dout = main_litedramcore_bankmachine7_rdport_dat_r; +assign main_litedramcore_bankmachine7_syncfifo7_writable = (main_litedramcore_bankmachine7_level != 5'd16); +assign main_litedramcore_bankmachine7_syncfifo7_readable = (main_litedramcore_bankmachine7_level != 1'd0); +assign main_litedramcore_bankmachine7_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine7_pipe_valid_source_valid) | main_litedramcore_bankmachine7_pipe_valid_source_ready); +assign main_litedramcore_bankmachine7_pipe_valid_sink_valid = main_litedramcore_bankmachine7_sink_sink_valid; +assign main_litedramcore_bankmachine7_sink_sink_ready = main_litedramcore_bankmachine7_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine7_pipe_valid_sink_first = main_litedramcore_bankmachine7_sink_sink_first; +assign main_litedramcore_bankmachine7_pipe_valid_sink_last = main_litedramcore_bankmachine7_sink_sink_last; +assign main_litedramcore_bankmachine7_pipe_valid_sink_payload_we = main_litedramcore_bankmachine7_sink_sink_payload_we; +assign main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine7_sink_sink_payload_addr; +assign main_litedramcore_bankmachine7_source_source_valid = main_litedramcore_bankmachine7_pipe_valid_source_valid; +assign main_litedramcore_bankmachine7_pipe_valid_source_ready = main_litedramcore_bankmachine7_source_source_ready; +assign main_litedramcore_bankmachine7_source_source_first = main_litedramcore_bankmachine7_pipe_valid_source_first; +assign main_litedramcore_bankmachine7_source_source_last = main_litedramcore_bankmachine7_pipe_valid_source_last; +assign main_litedramcore_bankmachine7_source_source_payload_we = main_litedramcore_bankmachine7_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine7_source_source_payload_addr = main_litedramcore_bankmachine7_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine7_next_state <= 4'd0; + builder_bankmachine7_next_state <= builder_bankmachine7_state; + case (builder_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + if (main_litedramcore_bankmachine7_cmd_ready) begin + builder_bankmachine7_next_state <= 3'd5; + end end end 2'd2: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + builder_bankmachine7_next_state <= 3'd5; + end end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + if (main_litedramcore_bankmachine7_cmd_ready) begin + builder_bankmachine7_next_state <= 3'd7; + end end end 3'd4: begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + if ((~main_litedramcore_bankmachine7_refresh_req)) begin + builder_bankmachine7_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine7_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine7_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine7_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine7_next_state <= 1'd0; end default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + builder_bankmachine7_next_state <= 3'd4; + end else begin + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if ((main_litedramcore_bankmachine7_cmd_ready & main_litedramcore_bankmachine7_auto_precharge)) begin + builder_bankmachine7_next_state <= 2'd2; + end + end else begin + builder_bankmachine7_next_state <= 1'd1; + end + end else begin + builder_bankmachine7_next_state <= 2'd3; + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -8689,14 +9323,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin end else begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready; end end else begin end @@ -8708,8 +9342,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -8717,6 +9351,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine7_twtpcon_ready) begin + main_litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -8727,173 +9364,19 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid; -assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready; -assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we; -assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr; -assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid; -assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready; -assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first; -assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last; -assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we; -assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr; -assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); -assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid); -assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[21:7]); -assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7; -always @(*) begin - litedramcore_bankmachine7_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine7_row_col_n_addr_sel) begin - litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_source_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write); -assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); -assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); -always @(*) begin - litedramcore_bankmachine7_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin - if ((litedramcore_bankmachine7_source_payload_addr[21:7] != litedramcore_bankmachine7_source_source_payload_addr[21:7])) begin - litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we}; -assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; -assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; -assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; -assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; -assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable; -assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid; -assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first; -assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last; -assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we; -assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr; -assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable; -assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first; -assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last; -assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we; -assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr; -assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready; -always @(*) begin - litedramcore_bankmachine7_wrport_adr <= 4'd0; - if (litedramcore_bankmachine7_replace) begin - litedramcore_bankmachine7_wrport_adr <= (litedramcore_bankmachine7_produce - 1'd1); - end else begin - litedramcore_bankmachine7_wrport_adr <= litedramcore_bankmachine7_produce; - end -end -assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din; -assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace)); -assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re); -assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume; -assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r; -assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 5'd16); -assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0); -assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready); -assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid; -assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready; -assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first; -assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last; -assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we; -assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr; -assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid; -assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready; -assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first; -assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last; -assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we; -assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine7_next_state <= 4'd0; - litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - if (litedramcore_bankmachine7_cmd_ready) begin - litedramcore_bankmachine7_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - if (litedramcore_bankmachine7_cmd_ready) begin - litedramcore_bankmachine7_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine7_refresh_req)) begin - litedramcore_bankmachine7_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine7_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine7_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine7_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine7_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - litedramcore_bankmachine7_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin - litedramcore_bankmachine7_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine7_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine7_next_state <= 2'd3; - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine7_row_open <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_row_open <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_open <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_row_open <= 1'd1; end end 3'd4: begin @@ -8911,18 +9394,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_valid <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; end end 3'd4: begin @@ -8936,12 +9419,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; end else begin end end else begin @@ -8952,41 +9435,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_row_close <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_row_close <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -8997,34 +9457,19 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin - litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -9042,8 +9487,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -9061,12 +9506,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -9077,18 +9522,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -9106,11 +9551,11 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -9128,13 +9573,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -9147,22 +9592,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9177,8 +9622,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -9196,14 +9641,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin end else begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9215,8 +9660,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -9234,13 +9679,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -9253,8 +9698,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -9272,14 +9717,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin + main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready; end else begin - litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; end end else begin end @@ -9290,283 +9735,256 @@ always @(*) begin end endcase end +assign main_litedramcore_nphases = (main_a7ddrphy_rdphase_storage - 1'd1); +assign main_litedramcore_rdphase = (main_a7ddrphy_wrphase_storage - 1'd1); +assign main_litedramcore_trrdcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))); +assign main_litedramcore_tfawcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))); +assign main_litedramcore_ras_allowed = (main_litedramcore_trrdcon_ready & main_litedramcore_tfawcon_ready); +assign main_litedramcore_tccdcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_cmd_payload_is_write | main_litedramcore_choose_req_cmd_payload_is_read)); +assign main_litedramcore_cas_allowed = main_litedramcore_tccdcon_ready; +assign main_litedramcore_twtrcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); +assign main_litedramcore_read_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_read) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_read)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_read)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_read)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_read)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_read)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_read)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_read)); +assign main_litedramcore_write_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_write) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_write)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_write)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_write)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_write)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_write)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_write)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_write)); +assign main_litedramcore_max_time0 = (main_litedramcore_time0 == 1'd0); +assign main_litedramcore_max_time1 = (main_litedramcore_time1 == 1'd0); +assign main_litedramcore_bankmachine0_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine1_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine2_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine3_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine4_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine5_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine6_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine7_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_go_to_refresh = (((((((main_litedramcore_bankmachine0_refresh_gnt & main_litedramcore_bankmachine1_refresh_gnt) & main_litedramcore_bankmachine2_refresh_gnt) & main_litedramcore_bankmachine3_refresh_gnt) & main_litedramcore_bankmachine4_refresh_gnt) & main_litedramcore_bankmachine5_refresh_gnt) & main_litedramcore_bankmachine6_refresh_gnt) & main_litedramcore_bankmachine7_refresh_gnt); +assign main_litedramcore_interface_rdata = {main_litedramcore_dfi_p3_rddata, main_litedramcore_dfi_p2_rddata, main_litedramcore_dfi_p1_rddata, main_litedramcore_dfi_p0_rddata}; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); always @(*) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine7_twtpcon_ready) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -assign litedramcore_rdcmdphase = (a7ddrphy_rdphase_storage - 1'd1); -assign litedramcore_wrcmdphase = (a7ddrphy_wrphase_storage - 1'd1); -assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); -assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); -assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready); -assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read)); -assign litedramcore_cas_allowed = litedramcore_tccdcon_ready; -assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); -assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read)); -assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write)); -assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0); -assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0); -assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid; -assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt); -assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata}; -assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; -assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; -assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; -assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; -assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); -assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); -assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); -assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); -always @(*) begin - litedramcore_choose_cmd_valids <= 8'd0; - litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids <= 8'd0; + main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); end -assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; -assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0; -assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1; -assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2; -assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; -assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; -assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; +assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids; +assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_self0; +assign main_litedramcore_choose_cmd_cmd_payload_a = builder_rhs_self1; +assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_self2; +assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_self3; +assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_self4; +assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_self5; always @(*) begin - litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; + main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_self0; end end always @(*) begin - litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; + main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_self1; end end always @(*) begin - litedramcore_choose_cmd_cmd_payload_we <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; + main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_self2; end end always @(*) begin - litedramcore_bankmachine0_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin - litedramcore_bankmachine0_cmd_ready <= 1'd1; + main_litedramcore_bankmachine0_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin + main_litedramcore_bankmachine0_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin - litedramcore_bankmachine0_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin + main_litedramcore_bankmachine0_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine1_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin - litedramcore_bankmachine1_cmd_ready <= 1'd1; + main_litedramcore_bankmachine1_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin + main_litedramcore_bankmachine1_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin - litedramcore_bankmachine1_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin + main_litedramcore_bankmachine1_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine2_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin - litedramcore_bankmachine2_cmd_ready <= 1'd1; + main_litedramcore_bankmachine2_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin + main_litedramcore_bankmachine2_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin - litedramcore_bankmachine2_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin + main_litedramcore_bankmachine2_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine3_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin - litedramcore_bankmachine3_cmd_ready <= 1'd1; + main_litedramcore_bankmachine3_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin + main_litedramcore_bankmachine3_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin - litedramcore_bankmachine3_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin + main_litedramcore_bankmachine3_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine4_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin - litedramcore_bankmachine4_cmd_ready <= 1'd1; + main_litedramcore_bankmachine4_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin + main_litedramcore_bankmachine4_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin - litedramcore_bankmachine4_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin + main_litedramcore_bankmachine4_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine5_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin - litedramcore_bankmachine5_cmd_ready <= 1'd1; + main_litedramcore_bankmachine5_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin + main_litedramcore_bankmachine5_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin - litedramcore_bankmachine5_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin + main_litedramcore_bankmachine5_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine6_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin - litedramcore_bankmachine6_cmd_ready <= 1'd1; + main_litedramcore_bankmachine6_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin + main_litedramcore_bankmachine6_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin - litedramcore_bankmachine6_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin + main_litedramcore_bankmachine6_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine7_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin - litedramcore_bankmachine7_cmd_ready <= 1'd1; + main_litedramcore_bankmachine7_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin + main_litedramcore_bankmachine7_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin - litedramcore_bankmachine7_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin + main_litedramcore_bankmachine7_cmd_ready <= 1'd1; end end -assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid)); +assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid)); always @(*) begin - litedramcore_choose_req_valids <= 8'd0; - litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids <= 8'd0; + main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); end -assign litedramcore_choose_req_request = litedramcore_choose_req_valids; -assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6; -assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7; -assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8; -assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9; -assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; -assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; +assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids; +assign main_litedramcore_choose_req_cmd_valid = builder_rhs_self6; +assign main_litedramcore_choose_req_cmd_payload_a = builder_rhs_self7; +assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_self8; +assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_self9; +assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_self10; +assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_self11; always @(*) begin - litedramcore_choose_req_cmd_payload_cas <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; + main_litedramcore_choose_req_cmd_payload_cas <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_cas <= builder_t_self3; end end always @(*) begin - litedramcore_choose_req_cmd_payload_ras <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; + main_litedramcore_choose_req_cmd_payload_ras <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_ras <= builder_t_self4; end end always @(*) begin - litedramcore_choose_req_cmd_payload_we <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; + main_litedramcore_choose_req_cmd_payload_we <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_we <= builder_t_self5; end end -assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); -assign litedramcore_dfi_p0_reset_n = 1'd1; -assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}}; -assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}}; -assign litedramcore_dfi_p1_reset_n = 1'd1; -assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}}; -assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}}; -assign litedramcore_dfi_p2_reset_n = 1'd1; -assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}}; -assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}}; -assign litedramcore_dfi_p3_reset_n = 1'd1; -assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}}; -assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}}; -assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]); +assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid)); +assign main_litedramcore_dfi_p0_reset_n = 1'd1; +assign main_litedramcore_dfi_p0_cke = {1{main_litedramcore_steerer4}}; +assign main_litedramcore_dfi_p0_odt = {1{main_litedramcore_steerer5}}; +assign main_litedramcore_dfi_p1_reset_n = 1'd1; +assign main_litedramcore_dfi_p1_cke = {1{main_litedramcore_steerer6}}; +assign main_litedramcore_dfi_p1_odt = {1{main_litedramcore_steerer7}}; +assign main_litedramcore_dfi_p2_reset_n = 1'd1; +assign main_litedramcore_dfi_p2_cke = {1{main_litedramcore_steerer8}}; +assign main_litedramcore_dfi_p2_odt = {1{main_litedramcore_steerer9}}; +assign main_litedramcore_dfi_p3_reset_n = 1'd1; +assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer10}}; +assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer11}}; +assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]); always @(*) begin - litedramcore_multiplexer_next_state <= 4'd0; - litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state; - case (litedramcore_multiplexer_state) + builder_multiplexer_next_state <= 4'd0; + builder_multiplexer_next_state <= builder_multiplexer_state; + case (builder_multiplexer_state) 1'd1: begin - if (litedramcore_read_available) begin - if (((~litedramcore_write_available) | litedramcore_max_time1)) begin - litedramcore_multiplexer_next_state <= 2'd3; + if (main_litedramcore_read_available) begin + if (((~main_litedramcore_write_available) | main_litedramcore_max_time1)) begin + builder_multiplexer_next_state <= 2'd3; end end - if (litedramcore_go_to_refresh) begin - litedramcore_multiplexer_next_state <= 2'd2; + if (main_litedramcore_go_to_refresh) begin + builder_multiplexer_next_state <= 2'd2; end end 2'd2: begin - if (litedramcore_cmd_last) begin - litedramcore_multiplexer_next_state <= 1'd0; + if (main_litedramcore_cmd_last) begin + builder_multiplexer_next_state <= 1'd0; end end 2'd3: begin - if (litedramcore_twtrcon_ready) begin - litedramcore_multiplexer_next_state <= 1'd0; + if (main_litedramcore_twtrcon_ready) begin + builder_multiplexer_next_state <= 1'd0; end end 3'd4: begin - litedramcore_multiplexer_next_state <= 3'd5; + builder_multiplexer_next_state <= 3'd5; end 3'd5: begin - litedramcore_multiplexer_next_state <= 3'd6; + builder_multiplexer_next_state <= 3'd6; end 3'd6: begin - litedramcore_multiplexer_next_state <= 3'd7; + builder_multiplexer_next_state <= 3'd7; end 3'd7: begin - litedramcore_multiplexer_next_state <= 4'd8; + builder_multiplexer_next_state <= 4'd8; end 4'd8: begin - litedramcore_multiplexer_next_state <= 4'd9; + builder_multiplexer_next_state <= 4'd9; end 4'd9: begin - litedramcore_multiplexer_next_state <= 4'd10; + builder_multiplexer_next_state <= 4'd10; end 4'd10: begin - litedramcore_multiplexer_next_state <= 1'd1; + builder_multiplexer_next_state <= 1'd1; end default: begin - if (litedramcore_write_available) begin - if (((~litedramcore_read_available) | litedramcore_max_time0)) begin - litedramcore_multiplexer_next_state <= 3'd4; + if (main_litedramcore_write_available) begin + if (((~main_litedramcore_read_available) | main_litedramcore_max_time0)) begin + builder_multiplexer_next_state <= 3'd4; end end - if (litedramcore_go_to_refresh) begin - litedramcore_multiplexer_next_state <= 2'd2; + if (main_litedramcore_go_to_refresh) begin + builder_multiplexer_next_state <= 2'd2; end end endcase end always @(*) begin - litedramcore_choose_req_want_writes <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_en0 <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -9587,19 +10005,17 @@ always @(*) begin 4'd10: begin end default: begin + main_litedramcore_en0 <= 1'd1; end endcase end always @(*) begin - litedramcore_steerer_sel3 <= 2'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_cmd_cmd_ready <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_steerer_sel3 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 2'd3)) begin - litedramcore_steerer_sel3 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 2'd3)) begin - litedramcore_steerer_sel3 <= 1'd1; + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); end end 2'd2: begin @@ -9621,25 +10037,17 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel3 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 2'd3)) begin - litedramcore_steerer_sel3 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 2'd3)) begin - litedramcore_steerer_sel3 <= 1'd1; + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); end end endcase end always @(*) begin - litedramcore_choose_req_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_req_want_reads <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end end 2'd2: begin end @@ -9660,19 +10068,15 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end + main_litedramcore_choose_req_want_reads <= 1'd1; end endcase end always @(*) begin - litedramcore_en1 <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_req_want_writes <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_en1 <= 1'd1; + main_litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -9697,19 +10101,16 @@ always @(*) begin endcase end always @(*) begin - litedramcore_steerer_sel0 <= 2'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_req_cmd_ready <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_steerer_sel0 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 1'd0)) begin - litedramcore_steerer_sel0 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 1'd0)) begin - litedramcore_steerer_sel0 <= 1'd1; + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; end end 2'd2: begin - litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end @@ -9728,23 +10129,21 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel0 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 1'd0)) begin - litedramcore_steerer_sel0 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 1'd0)) begin - litedramcore_steerer_sel0 <= 1'd1; + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; end end endcase end always @(*) begin - litedramcore_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_en1 <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin + main_litedramcore_en1 <= 1'd1; end 2'd2: begin - litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -9767,15 +10166,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_steerer_sel1 <= 2'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_steerer3 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_steerer_sel1 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 1'd1)) begin - litedramcore_steerer_sel1 <= 2'd2; + main_litedramcore_steerer3 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin + main_litedramcore_steerer3 <= 2'd2; end - if ((litedramcore_wrcmdphase == 1'd1)) begin - litedramcore_steerer_sel1 <= 1'd1; + if ((main_litedramcore_rdphase == 2'd3)) begin + main_litedramcore_steerer3 <= 1'd1; end end 2'd2: begin @@ -9797,29 +10196,30 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel1 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 1'd1)) begin - litedramcore_steerer_sel1 <= 2'd2; + main_litedramcore_steerer3 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin + main_litedramcore_steerer3 <= 2'd2; end - if ((litedramcore_rdcmdphase == 1'd1)) begin - litedramcore_steerer_sel1 <= 1'd1; + if ((main_litedramcore_nphases == 2'd3)) begin + main_litedramcore_steerer3 <= 1'd1; end end endcase end always @(*) begin - litedramcore_steerer_sel2 <= 2'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_steerer0 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_steerer_sel2 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 2'd2)) begin - litedramcore_steerer_sel2 <= 2'd2; + main_litedramcore_steerer0 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 1'd0)) begin + main_litedramcore_steerer0 <= 2'd2; end - if ((litedramcore_wrcmdphase == 2'd2)) begin - litedramcore_steerer_sel2 <= 1'd1; + if ((main_litedramcore_rdphase == 1'd0)) begin + main_litedramcore_steerer0 <= 1'd1; end end 2'd2: begin + main_litedramcore_steerer0 <= 2'd3; end 2'd3: begin end @@ -9838,26 +10238,23 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel2 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 2'd2)) begin - litedramcore_steerer_sel2 <= 2'd2; + main_litedramcore_steerer0 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 1'd0)) begin + main_litedramcore_steerer0 <= 2'd2; end - if ((litedramcore_rdcmdphase == 2'd2)) begin - litedramcore_steerer_sel2 <= 1'd1; + if ((main_litedramcore_nphases == 1'd0)) begin + main_litedramcore_steerer0 <= 1'd1; end end endcase end always @(*) begin - litedramcore_choose_cmd_want_activates <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_cmd_ready <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end end 2'd2: begin + main_litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -9876,17 +10273,20 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end end endcase end always @(*) begin - litedramcore_en0 <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_steerer1 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin + main_litedramcore_steerer1 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin + main_litedramcore_steerer1 <= 2'd2; + end + if ((main_litedramcore_rdphase == 1'd1)) begin + main_litedramcore_steerer1 <= 1'd1; + end end 2'd2: begin end @@ -9907,17 +10307,26 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_en0 <= 1'd1; + main_litedramcore_steerer1 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin + main_litedramcore_steerer1 <= 2'd2; + end + if ((main_litedramcore_nphases == 1'd1)) begin + main_litedramcore_steerer1 <= 1'd1; + end end endcase end always @(*) begin - litedramcore_choose_cmd_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_steerer2 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + main_litedramcore_steerer2 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 2'd2)) begin + main_litedramcore_steerer2 <= 2'd2; + end + if ((main_litedramcore_rdphase == 2'd2)) begin + main_litedramcore_steerer2 <= 1'd1; end end 2'd2: begin @@ -9939,17 +10348,24 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + main_litedramcore_steerer2 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 2'd2)) begin + main_litedramcore_steerer2 <= 2'd2; + end + if ((main_litedramcore_nphases == 2'd2)) begin + main_litedramcore_steerer2 <= 1'd1; end end endcase end always @(*) begin - litedramcore_choose_req_want_reads <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_cmd_want_activates <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; + end end 2'd2: begin end @@ -9970,2012 +10386,2012 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_choose_req_want_reads <= 1'd1; + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; + end end endcase end -assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock)); -assign litedramcore_interface_bank0_addr = rhs_array_muxed12; -assign litedramcore_interface_bank0_we = rhs_array_muxed13; -assign litedramcore_interface_bank0_valid = rhs_array_muxed14; -assign litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock)); -assign litedramcore_interface_bank1_addr = rhs_array_muxed15; -assign litedramcore_interface_bank1_we = rhs_array_muxed16; -assign litedramcore_interface_bank1_valid = rhs_array_muxed17; -assign litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock)); -assign litedramcore_interface_bank2_addr = rhs_array_muxed18; -assign litedramcore_interface_bank2_we = rhs_array_muxed19; -assign litedramcore_interface_bank2_valid = rhs_array_muxed20; -assign litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock)); -assign litedramcore_interface_bank3_addr = rhs_array_muxed21; -assign litedramcore_interface_bank3_we = rhs_array_muxed22; -assign litedramcore_interface_bank3_valid = rhs_array_muxed23; -assign litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock)); -assign litedramcore_interface_bank4_addr = rhs_array_muxed24; -assign litedramcore_interface_bank4_we = rhs_array_muxed25; -assign litedramcore_interface_bank4_valid = rhs_array_muxed26; -assign litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock)); -assign litedramcore_interface_bank5_addr = rhs_array_muxed27; -assign litedramcore_interface_bank5_we = rhs_array_muxed28; -assign litedramcore_interface_bank5_valid = rhs_array_muxed29; -assign litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock)); -assign litedramcore_interface_bank6_addr = rhs_array_muxed30; -assign litedramcore_interface_bank6_we = rhs_array_muxed31; -assign litedramcore_interface_bank6_valid = rhs_array_muxed32; -assign litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock)); -assign litedramcore_interface_bank7_addr = rhs_array_muxed33; -assign litedramcore_interface_bank7_we = rhs_array_muxed34; -assign litedramcore_interface_bank7_valid = rhs_array_muxed35; -assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready)); -assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1; -assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8; -always @(*) begin - litedramcore_interface_wdata <= 128'd0; - case ({litedramcore_new_master_wdata_ready1}) +assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock)); +assign main_litedramcore_interface_bank0_addr = builder_rhs_self12; +assign main_litedramcore_interface_bank0_we = builder_rhs_self13; +assign main_litedramcore_interface_bank0_valid = builder_rhs_self14; +assign builder_roundrobin1_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin1_ce = ((~main_litedramcore_interface_bank1_valid) & (~main_litedramcore_interface_bank1_lock)); +assign main_litedramcore_interface_bank1_addr = builder_rhs_self15; +assign main_litedramcore_interface_bank1_we = builder_rhs_self16; +assign main_litedramcore_interface_bank1_valid = builder_rhs_self17; +assign builder_roundrobin2_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin2_ce = ((~main_litedramcore_interface_bank2_valid) & (~main_litedramcore_interface_bank2_lock)); +assign main_litedramcore_interface_bank2_addr = builder_rhs_self18; +assign main_litedramcore_interface_bank2_we = builder_rhs_self19; +assign main_litedramcore_interface_bank2_valid = builder_rhs_self20; +assign builder_roundrobin3_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin3_ce = ((~main_litedramcore_interface_bank3_valid) & (~main_litedramcore_interface_bank3_lock)); +assign main_litedramcore_interface_bank3_addr = builder_rhs_self21; +assign main_litedramcore_interface_bank3_we = builder_rhs_self22; +assign main_litedramcore_interface_bank3_valid = builder_rhs_self23; +assign builder_roundrobin4_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin4_ce = ((~main_litedramcore_interface_bank4_valid) & (~main_litedramcore_interface_bank4_lock)); +assign main_litedramcore_interface_bank4_addr = builder_rhs_self24; +assign main_litedramcore_interface_bank4_we = builder_rhs_self25; +assign main_litedramcore_interface_bank4_valid = builder_rhs_self26; +assign builder_roundrobin5_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin5_ce = ((~main_litedramcore_interface_bank5_valid) & (~main_litedramcore_interface_bank5_lock)); +assign main_litedramcore_interface_bank5_addr = builder_rhs_self27; +assign main_litedramcore_interface_bank5_we = builder_rhs_self28; +assign main_litedramcore_interface_bank5_valid = builder_rhs_self29; +assign builder_roundrobin6_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin6_ce = ((~main_litedramcore_interface_bank6_valid) & (~main_litedramcore_interface_bank6_lock)); +assign main_litedramcore_interface_bank6_addr = builder_rhs_self30; +assign main_litedramcore_interface_bank6_we = builder_rhs_self31; +assign main_litedramcore_interface_bank6_valid = builder_rhs_self32; +assign builder_roundrobin7_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin7_ce = ((~main_litedramcore_interface_bank7_valid) & (~main_litedramcore_interface_bank7_lock)); +assign main_litedramcore_interface_bank7_addr = builder_rhs_self33; +assign main_litedramcore_interface_bank7_we = builder_rhs_self34; +assign main_litedramcore_interface_bank7_valid = builder_rhs_self35; +assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready)); +assign main_user_port_wdata_ready = builder_new_master_wdata_ready1; +assign main_user_port_rdata_valid = builder_new_master_rdata_valid8; +always @(*) begin + main_litedramcore_interface_wdata <= 128'd0; + case ({builder_new_master_wdata_ready1}) 1'd1: begin - litedramcore_interface_wdata <= user_port_wdata_payload_data; + main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data; end default: begin - litedramcore_interface_wdata <= 1'd0; + main_litedramcore_interface_wdata <= 1'd0; end endcase end always @(*) begin - litedramcore_interface_wdata_we <= 16'd0; - case ({litedramcore_new_master_wdata_ready1}) + main_litedramcore_interface_wdata_we <= 16'd0; + case ({builder_new_master_wdata_ready1}) 1'd1: begin - litedramcore_interface_wdata_we <= user_port_wdata_payload_we; + main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we; end default: begin - litedramcore_interface_wdata_we <= 1'd0; + main_litedramcore_interface_wdata_we <= 1'd0; end endcase end -assign user_port_rdata_payload_data = litedramcore_interface_rdata; -assign litedramcore_roundrobin0_grant = 1'd0; -assign litedramcore_roundrobin1_grant = 1'd0; -assign litedramcore_roundrobin2_grant = 1'd0; -assign litedramcore_roundrobin3_grant = 1'd0; -assign litedramcore_roundrobin4_grant = 1'd0; -assign litedramcore_roundrobin5_grant = 1'd0; -assign litedramcore_roundrobin6_grant = 1'd0; -assign litedramcore_roundrobin7_grant = 1'd0; -always @(*) begin - litedramcore_next_state <= 2'd0; - litedramcore_next_state <= litedramcore_state; - case (litedramcore_state) +assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata; +assign builder_roundrobin0_grant = 1'd0; +assign builder_roundrobin1_grant = 1'd0; +assign builder_roundrobin2_grant = 1'd0; +assign builder_roundrobin3_grant = 1'd0; +assign builder_roundrobin4_grant = 1'd0; +assign builder_roundrobin5_grant = 1'd0; +assign builder_roundrobin6_grant = 1'd0; +assign builder_roundrobin7_grant = 1'd0; +always @(*) begin + builder_next_state <= 2'd0; + builder_next_state <= builder_state; + case (builder_state) 1'd1: begin - litedramcore_next_state <= 2'd2; + builder_next_state <= 2'd2; end 2'd2: begin - litedramcore_next_state <= 1'd0; + builder_next_state <= 1'd0; end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_next_state <= 1'd1; + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_next_state <= 1'd1; end end endcase end always @(*) begin - litedramcore_dat_w_next_value0 <= 32'd0; - case (litedramcore_state) + builder_interface0_dat_r <= 32'd0; + case (builder_state) 1'd1: begin end 2'd2: begin + builder_interface0_dat_r <= builder_interface1_dat_r; end default: begin - litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w; end endcase end always @(*) begin - litedramcore_dat_w_next_value_ce0 <= 1'd0; - case (litedramcore_state) + builder_interface1_dat_w_next_value0 <= 32'd0; + case (builder_state) 1'd1: begin end 2'd2: begin end default: begin - litedramcore_dat_w_next_value_ce0 <= 1'd1; + builder_interface1_dat_w_next_value0 <= builder_interface0_dat_w; end endcase end always @(*) begin - litedramcore_adr_next_value1 <= 14'd0; - case (litedramcore_state) + builder_interface1_dat_w_next_value_ce0 <= 1'd0; + case (builder_state) 1'd1: begin - litedramcore_adr_next_value1 <= 1'd0; end 2'd2: begin end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value1 <= litedramcore_wishbone_adr; - end + builder_interface1_dat_w_next_value_ce0 <= 1'd1; end endcase end always @(*) begin - litedramcore_adr_next_value_ce1 <= 1'd0; - case (litedramcore_state) + builder_interface1_adr_next_value1 <= 14'd0; + case (builder_state) 1'd1: begin - litedramcore_adr_next_value_ce1 <= 1'd1; + builder_interface1_adr_next_value1 <= 1'd0; end 2'd2: begin end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value_ce1 <= 1'd1; + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_adr_next_value1 <= builder_interface0_adr[29:0]; end end endcase end always @(*) begin - litedramcore_wishbone_dat_r <= 32'd0; - case (litedramcore_state) + builder_interface0_ack <= 1'd0; + case (builder_state) 1'd1: begin end 2'd2: begin - litedramcore_wishbone_dat_r <= litedramcore_dat_r; + builder_interface0_ack <= 1'd1; end default: begin end endcase end always @(*) begin - litedramcore_we_next_value2 <= 1'd0; - case (litedramcore_state) + builder_interface1_adr_next_value_ce1 <= 1'd0; + case (builder_state) 1'd1: begin - litedramcore_we_next_value2 <= 1'd0; + builder_interface1_adr_next_value_ce1 <= 1'd1; end 2'd2: begin end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_adr_next_value_ce1 <= 1'd1; end end endcase end always @(*) begin - litedramcore_we_next_value_ce2 <= 1'd0; - case (litedramcore_state) + builder_interface1_we_next_value2 <= 1'd0; + case (builder_state) 1'd1: begin - litedramcore_we_next_value_ce2 <= 1'd1; + builder_interface1_we_next_value2 <= 1'd0; end 2'd2: begin end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value_ce2 <= 1'd1; + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_we_next_value2 <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); end end endcase end always @(*) begin - litedramcore_wishbone_ack <= 1'd0; - case (litedramcore_state) + builder_interface1_we_next_value_ce2 <= 1'd0; + case (builder_state) 1'd1: begin + builder_interface1_we_next_value_ce2 <= 1'd1; end 2'd2: begin - litedramcore_wishbone_ack <= 1'd1; end default: begin + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_we_next_value_ce2 <= 1'd1; + end end endcase end -assign litedramcore_wishbone_adr = wb_bus_adr; -assign litedramcore_wishbone_dat_w = wb_bus_dat_w; -assign wb_bus_dat_r = litedramcore_wishbone_dat_r; -assign litedramcore_wishbone_sel = wb_bus_sel; -assign litedramcore_wishbone_cyc = wb_bus_cyc; -assign litedramcore_wishbone_stb = wb_bus_stb; -assign wb_bus_ack = litedramcore_wishbone_ack; -assign litedramcore_wishbone_we = wb_bus_we; -assign litedramcore_wishbone_cti = wb_bus_cti; -assign litedramcore_wishbone_bte = wb_bus_bte; -assign wb_bus_err = litedramcore_wishbone_err; -assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); -assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; +assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); +assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_done0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_re <= interface0_bank_bus_we; + builder_csrbank0_init_done0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we); end end always @(*) begin - csrbank0_init_done0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_we <= (~interface0_bank_bus_we); + builder_csrbank0_init_done0_re <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we; end end -assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; +assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_error0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_we <= (~interface0_bank_bus_we); + builder_csrbank0_init_error0_re <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; end end always @(*) begin - csrbank0_init_error0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_re <= interface0_bank_bus_we; + builder_csrbank0_init_error0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we); end end -assign csrbank0_init_done0_w = init_done_storage; -assign csrbank0_init_error0_w = init_error_storage; -assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); -assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0]; +assign builder_csrbank0_init_done0_w = main_init_done_storage; +assign builder_csrbank0_init_error0_w = main_init_error_storage; +assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1); +assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - csrbank1_rst0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_rst0_we <= (~interface1_bank_bus_we); + builder_csrbank1_rst0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - csrbank1_rst0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_rst0_re <= interface1_bank_bus_we; + builder_csrbank1_rst0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we); end end -assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; +assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_dly_sel0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dly_sel0_we <= (~interface1_bank_bus_we); + builder_csrbank1_dly_sel0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - csrbank1_dly_sel0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dly_sel0_re <= interface1_bank_bus_we; + builder_csrbank1_dly_sel0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; end end -assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; +assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0]; always @(*) begin - csrbank1_half_sys8x_taps0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we; + builder_csrbank1_half_sys8x_taps0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - csrbank1_half_sys8x_taps0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we); + builder_csrbank1_half_sys8x_taps0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we); end end -assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0]; +assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - csrbank1_wlevel_en0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we); + builder_csrbank1_wlevel_en0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - csrbank1_wlevel_en0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_wlevel_en0_re <= interface1_bank_bus_we; + builder_csrbank1_wlevel_en0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we); end end -assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_wlevel_strobe_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we; + main_a7ddrphy_wlevel_strobe_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we; end end always @(*) begin - a7ddrphy_wlevel_strobe_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we); + main_a7ddrphy_wlevel_strobe_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we); end end -assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; end end always @(*) begin - a7ddrphy_rdly_dq_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we); end end -assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_inc_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_inc_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; end end always @(*) begin - a7ddrphy_rdly_dq_inc_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_inc_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we); end end -assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end end -assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_bitslip_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - a7ddrphy_rdly_dq_bitslip_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end end -assign a7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end end -assign a7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_wdly_dq_bitslip_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we); + main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - a7ddrphy_wdly_dq_bitslip_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we; + main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end end -assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0]; +assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_rdphase0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - csrbank1_rdphase0_re <= interface1_bank_bus_we; + builder_csrbank1_rdphase0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - csrbank1_rdphase0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - csrbank1_rdphase0_we <= (~interface1_bank_bus_we); + builder_csrbank1_rdphase0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; end end -assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0]; +assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_wrphase0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - csrbank1_wrphase0_re <= interface1_bank_bus_we; + builder_csrbank1_wrphase0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - csrbank1_wrphase0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - csrbank1_wrphase0_we <= (~interface1_bank_bus_we); + builder_csrbank1_wrphase0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we); end end -assign csrbank1_rst0_w = a7ddrphy_rst_storage; -assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; -assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0]; -assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage; -assign csrbank1_rdphase0_w = a7ddrphy_rdphase_storage[1:0]; -assign csrbank1_wrphase0_w = a7ddrphy_wrphase_storage[1:0]; -assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); -assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; +assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage; +assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0]; +assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0]; +assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage; +assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0]; +assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0]; +assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2); +assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0]; always @(*) begin - csrbank2_dfii_control0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_control0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_control0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_control0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; +assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi0_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi0_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we); end end -assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; +assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector0_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we); + main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; end end always @(*) begin - litedramcore_phaseinjector0_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we; + main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0]; +assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[14:0]; always @(*) begin - csrbank2_dfii_pi0_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi0_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi0_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi0_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi0_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin + builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi0_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin + builder_csrbank2_dfii_pi0_rddata_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; +assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi1_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi1_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we; end end -assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; +assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector1_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we); + main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin + main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - litedramcore_phaseinjector1_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we; + main_litedramcore_phaseinjector1_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin + main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0]; +assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[14:0]; always @(*) begin - csrbank2_dfii_pi1_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi1_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi1_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi1_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi1_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi1_rddata_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi1_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0]; +assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi2_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi2_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we; end end -assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; +assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector2_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we; + main_litedramcore_phaseinjector2_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we; end end always @(*) begin - litedramcore_phaseinjector2_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we); + main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[14:0]; +assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[14:0]; always @(*) begin - csrbank2_dfii_pi2_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi2_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi2_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi2_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi2_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin - csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi2_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin - csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi2_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin - csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank2_dfii_pi2_rddata_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi2_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin - csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0]; +assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi3_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin - csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi3_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin - csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we); end end -assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; +assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector3_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin - litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we); + main_litedramcore_phaseinjector3_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we; end end always @(*) begin - litedramcore_phaseinjector3_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin - litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we; + main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[14:0]; +assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[14:0]; always @(*) begin - csrbank2_dfii_pi3_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin - csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi3_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin - csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi3_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin - csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi3_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin - csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi3_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin - csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi3_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin - csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi3_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin - csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi3_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin - csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi3_rddata_re <= builder_interface2_bank_bus_we; end end -assign litedramcore_sel = litedramcore_storage[0]; -assign litedramcore_cke = litedramcore_storage[1]; -assign litedramcore_odt = litedramcore_storage[2]; -assign litedramcore_reset_n = litedramcore_storage[3]; -assign csrbank2_dfii_control0_w = litedramcore_storage[3:0]; -assign litedramcore_phaseinjector0_csrfield_cs = litedramcore_phaseinjector0_command_storage[0]; -assign litedramcore_phaseinjector0_csrfield_we = litedramcore_phaseinjector0_command_storage[1]; -assign litedramcore_phaseinjector0_csrfield_cas = litedramcore_phaseinjector0_command_storage[2]; -assign litedramcore_phaseinjector0_csrfield_ras = litedramcore_phaseinjector0_command_storage[3]; -assign litedramcore_phaseinjector0_csrfield_wren = litedramcore_phaseinjector0_command_storage[4]; -assign litedramcore_phaseinjector0_csrfield_rden = litedramcore_phaseinjector0_command_storage[5]; -assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; -assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0]; -assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0]; -assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0]; -assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_rddata_status[31:0]; -assign litedramcore_phaseinjector0_rddata_we = csrbank2_dfii_pi0_rddata_we; -assign litedramcore_phaseinjector1_csrfield_cs = litedramcore_phaseinjector1_command_storage[0]; -assign litedramcore_phaseinjector1_csrfield_we = litedramcore_phaseinjector1_command_storage[1]; -assign litedramcore_phaseinjector1_csrfield_cas = litedramcore_phaseinjector1_command_storage[2]; -assign litedramcore_phaseinjector1_csrfield_ras = litedramcore_phaseinjector1_command_storage[3]; -assign litedramcore_phaseinjector1_csrfield_wren = litedramcore_phaseinjector1_command_storage[4]; -assign litedramcore_phaseinjector1_csrfield_rden = litedramcore_phaseinjector1_command_storage[5]; -assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0]; -assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[14:0]; -assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0]; -assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0]; -assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_rddata_status[31:0]; -assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata_we; -assign litedramcore_phaseinjector2_csrfield_cs = litedramcore_phaseinjector2_command_storage[0]; -assign litedramcore_phaseinjector2_csrfield_we = litedramcore_phaseinjector2_command_storage[1]; -assign litedramcore_phaseinjector2_csrfield_cas = litedramcore_phaseinjector2_command_storage[2]; -assign litedramcore_phaseinjector2_csrfield_ras = litedramcore_phaseinjector2_command_storage[3]; -assign litedramcore_phaseinjector2_csrfield_wren = litedramcore_phaseinjector2_command_storage[4]; -assign litedramcore_phaseinjector2_csrfield_rden = litedramcore_phaseinjector2_command_storage[5]; -assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0]; -assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[14:0]; -assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0]; -assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0]; -assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_rddata_status[31:0]; -assign litedramcore_phaseinjector2_rddata_we = csrbank2_dfii_pi2_rddata_we; -assign litedramcore_phaseinjector3_csrfield_cs = litedramcore_phaseinjector3_command_storage[0]; -assign litedramcore_phaseinjector3_csrfield_we = litedramcore_phaseinjector3_command_storage[1]; -assign litedramcore_phaseinjector3_csrfield_cas = litedramcore_phaseinjector3_command_storage[2]; -assign litedramcore_phaseinjector3_csrfield_ras = litedramcore_phaseinjector3_command_storage[3]; -assign litedramcore_phaseinjector3_csrfield_wren = litedramcore_phaseinjector3_command_storage[4]; -assign litedramcore_phaseinjector3_csrfield_rden = litedramcore_phaseinjector3_command_storage[5]; -assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0]; -assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[14:0]; -assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0]; -assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0]; -assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_rddata_status[31:0]; -assign litedramcore_phaseinjector3_rddata_we = csrbank2_dfii_pi3_rddata_we; -assign csr_interconnect_adr = litedramcore_adr; -assign csr_interconnect_we = litedramcore_we; -assign csr_interconnect_dat_w = litedramcore_dat_w; -assign litedramcore_dat_r = csr_interconnect_dat_r; -assign interface0_bank_bus_adr = csr_interconnect_adr; -assign interface1_bank_bus_adr = csr_interconnect_adr; -assign interface2_bank_bus_adr = csr_interconnect_adr; -assign interface0_bank_bus_we = csr_interconnect_we; -assign interface1_bank_bus_we = csr_interconnect_we; -assign interface2_bank_bus_we = csr_interconnect_we; -assign interface0_bank_bus_dat_w = csr_interconnect_dat_w; -assign interface1_bank_bus_dat_w = csr_interconnect_dat_w; -assign interface2_bank_bus_dat_w = csr_interconnect_dat_w; -assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); -always @(*) begin - rhs_array_muxed0 <= 1'd0; - case (litedramcore_choose_cmd_grant) +assign main_litedramcore_sel = main_litedramcore_storage[0]; +assign main_litedramcore_cke = main_litedramcore_storage[1]; +assign main_litedramcore_odt = main_litedramcore_storage[2]; +assign main_litedramcore_reset_n = main_litedramcore_storage[3]; +assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0]; +assign main_litedramcore_phaseinjector0_csrfield_cs = main_litedramcore_phaseinjector0_command_storage[0]; +assign main_litedramcore_phaseinjector0_csrfield_we = main_litedramcore_phaseinjector0_command_storage[1]; +assign main_litedramcore_phaseinjector0_csrfield_cas = main_litedramcore_phaseinjector0_command_storage[2]; +assign main_litedramcore_phaseinjector0_csrfield_ras = main_litedramcore_phaseinjector0_command_storage[3]; +assign main_litedramcore_phaseinjector0_csrfield_wren = main_litedramcore_phaseinjector0_command_storage[4]; +assign main_litedramcore_phaseinjector0_csrfield_rden = main_litedramcore_phaseinjector0_command_storage[5]; +assign main_litedramcore_phaseinjector0_csrfield_cs_top = main_litedramcore_phaseinjector0_command_storage[6]; +assign main_litedramcore_phaseinjector0_csrfield_cs_bottom = main_litedramcore_phaseinjector0_command_storage[7]; +assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[7:0]; +assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[14:0]; +assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0]; +assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we; +assign main_litedramcore_phaseinjector1_csrfield_cs = main_litedramcore_phaseinjector1_command_storage[0]; +assign main_litedramcore_phaseinjector1_csrfield_we = main_litedramcore_phaseinjector1_command_storage[1]; +assign main_litedramcore_phaseinjector1_csrfield_cas = main_litedramcore_phaseinjector1_command_storage[2]; +assign main_litedramcore_phaseinjector1_csrfield_ras = main_litedramcore_phaseinjector1_command_storage[3]; +assign main_litedramcore_phaseinjector1_csrfield_wren = main_litedramcore_phaseinjector1_command_storage[4]; +assign main_litedramcore_phaseinjector1_csrfield_rden = main_litedramcore_phaseinjector1_command_storage[5]; +assign main_litedramcore_phaseinjector1_csrfield_cs_top = main_litedramcore_phaseinjector1_command_storage[6]; +assign main_litedramcore_phaseinjector1_csrfield_cs_bottom = main_litedramcore_phaseinjector1_command_storage[7]; +assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[7:0]; +assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[14:0]; +assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0]; +assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we; +assign main_litedramcore_phaseinjector2_csrfield_cs = main_litedramcore_phaseinjector2_command_storage[0]; +assign main_litedramcore_phaseinjector2_csrfield_we = main_litedramcore_phaseinjector2_command_storage[1]; +assign main_litedramcore_phaseinjector2_csrfield_cas = main_litedramcore_phaseinjector2_command_storage[2]; +assign main_litedramcore_phaseinjector2_csrfield_ras = main_litedramcore_phaseinjector2_command_storage[3]; +assign main_litedramcore_phaseinjector2_csrfield_wren = main_litedramcore_phaseinjector2_command_storage[4]; +assign main_litedramcore_phaseinjector2_csrfield_rden = main_litedramcore_phaseinjector2_command_storage[5]; +assign main_litedramcore_phaseinjector2_csrfield_cs_top = main_litedramcore_phaseinjector2_command_storage[6]; +assign main_litedramcore_phaseinjector2_csrfield_cs_bottom = main_litedramcore_phaseinjector2_command_storage[7]; +assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[7:0]; +assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[14:0]; +assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0]; +assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we; +assign main_litedramcore_phaseinjector3_csrfield_cs = main_litedramcore_phaseinjector3_command_storage[0]; +assign main_litedramcore_phaseinjector3_csrfield_we = main_litedramcore_phaseinjector3_command_storage[1]; +assign main_litedramcore_phaseinjector3_csrfield_cas = main_litedramcore_phaseinjector3_command_storage[2]; +assign main_litedramcore_phaseinjector3_csrfield_ras = main_litedramcore_phaseinjector3_command_storage[3]; +assign main_litedramcore_phaseinjector3_csrfield_wren = main_litedramcore_phaseinjector3_command_storage[4]; +assign main_litedramcore_phaseinjector3_csrfield_rden = main_litedramcore_phaseinjector3_command_storage[5]; +assign main_litedramcore_phaseinjector3_csrfield_cs_top = main_litedramcore_phaseinjector3_command_storage[6]; +assign main_litedramcore_phaseinjector3_csrfield_cs_bottom = main_litedramcore_phaseinjector3_command_storage[7]; +assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[7:0]; +assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[14:0]; +assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0]; +assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we; +assign builder_adr = builder_interface1_adr; +assign builder_we = builder_interface1_we; +assign builder_dat_w = builder_interface1_dat_w; +assign builder_interface1_dat_r = builder_dat_r; +assign builder_interface0_bank_bus_adr = builder_adr; +assign builder_interface1_bank_bus_adr = builder_adr; +assign builder_interface2_bank_bus_adr = builder_adr; +assign builder_interface0_bank_bus_we = builder_we; +assign builder_interface1_bank_bus_we = builder_we; +assign builder_interface2_bank_bus_we = builder_we; +assign builder_interface0_bank_bus_dat_w = builder_dat_w; +assign builder_interface1_bank_bus_dat_w = builder_dat_w; +assign builder_interface2_bank_bus_dat_w = builder_dat_w; +assign builder_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); +always @(*) begin + builder_rhs_self0 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[0]; end 1'd1: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[1]; end 2'd2: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[2]; end 2'd3: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[3]; end 3'd4: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[4]; end 3'd5: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[5]; end 3'd6: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[6]; end default: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[7]; end endcase end always @(*) begin - rhs_array_muxed1 <= 15'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self1 <= 15'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine6_cmd_payload_a; end default: begin - rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase end always @(*) begin - rhs_array_muxed2 <= 3'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self2 <= 3'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine6_cmd_payload_ba; end default: begin - rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase end always @(*) begin - rhs_array_muxed3 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self3 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase end always @(*) begin - rhs_array_muxed4 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self4 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase end always @(*) begin - rhs_array_muxed5 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self5 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase end always @(*) begin - t_array_muxed0 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_t_self0 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine6_cmd_payload_cas; end default: begin - t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase end always @(*) begin - t_array_muxed1 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_t_self1 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine6_cmd_payload_ras; end default: begin - t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase end always @(*) begin - t_array_muxed2 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_t_self2 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine6_cmd_payload_we; end default: begin - t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed6 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self6 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[0]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[0]; end 1'd1: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[1]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[1]; end 2'd2: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[2]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[2]; end 2'd3: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[3]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[3]; end 3'd4: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[4]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[4]; end 3'd5: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[5]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[5]; end 3'd6: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[6]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[6]; end default: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[7]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[7]; end endcase end always @(*) begin - rhs_array_muxed7 <= 15'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self7 <= 15'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine6_cmd_payload_a; end default: begin - rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase end always @(*) begin - rhs_array_muxed8 <= 3'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self8 <= 3'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine6_cmd_payload_ba; end default: begin - rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase end always @(*) begin - rhs_array_muxed9 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self9 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase end always @(*) begin - rhs_array_muxed10 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self10 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase end always @(*) begin - rhs_array_muxed11 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self11 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase end always @(*) begin - t_array_muxed3 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_t_self3 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine6_cmd_payload_cas; end default: begin - t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase end always @(*) begin - t_array_muxed4 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_t_self4 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine6_cmd_payload_ras; end default: begin - t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase end always @(*) begin - t_array_muxed5 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_t_self5 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine6_cmd_payload_we; end default: begin - t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed12 <= 22'd0; - case (litedramcore_roundrobin0_grant) + builder_rhs_self12 <= 22'd0; + case (builder_roundrobin0_grant) default: begin - rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self12 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed13 <= 1'd0; - case (litedramcore_roundrobin0_grant) + builder_rhs_self13 <= 1'd0; + case (builder_roundrobin0_grant) default: begin - rhs_array_muxed13 <= user_port_cmd_payload_we; + builder_rhs_self13 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed14 <= 1'd0; - case (litedramcore_roundrobin0_grant) + builder_rhs_self14 <= 1'd0; + case (builder_roundrobin0_grant) default: begin - rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed15 <= 22'd0; - case (litedramcore_roundrobin1_grant) + builder_rhs_self15 <= 22'd0; + case (builder_roundrobin1_grant) default: begin - rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self15 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed16 <= 1'd0; - case (litedramcore_roundrobin1_grant) + builder_rhs_self16 <= 1'd0; + case (builder_roundrobin1_grant) default: begin - rhs_array_muxed16 <= user_port_cmd_payload_we; + builder_rhs_self16 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed17 <= 1'd0; - case (litedramcore_roundrobin1_grant) + builder_rhs_self17 <= 1'd0; + case (builder_roundrobin1_grant) default: begin - rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed18 <= 22'd0; - case (litedramcore_roundrobin2_grant) + builder_rhs_self18 <= 22'd0; + case (builder_roundrobin2_grant) default: begin - rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self18 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed19 <= 1'd0; - case (litedramcore_roundrobin2_grant) + builder_rhs_self19 <= 1'd0; + case (builder_roundrobin2_grant) default: begin - rhs_array_muxed19 <= user_port_cmd_payload_we; + builder_rhs_self19 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed20 <= 1'd0; - case (litedramcore_roundrobin2_grant) + builder_rhs_self20 <= 1'd0; + case (builder_roundrobin2_grant) default: begin - rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed21 <= 22'd0; - case (litedramcore_roundrobin3_grant) + builder_rhs_self21 <= 22'd0; + case (builder_roundrobin3_grant) default: begin - rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self21 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed22 <= 1'd0; - case (litedramcore_roundrobin3_grant) + builder_rhs_self22 <= 1'd0; + case (builder_roundrobin3_grant) default: begin - rhs_array_muxed22 <= user_port_cmd_payload_we; + builder_rhs_self22 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed23 <= 1'd0; - case (litedramcore_roundrobin3_grant) + builder_rhs_self23 <= 1'd0; + case (builder_roundrobin3_grant) default: begin - rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed24 <= 22'd0; - case (litedramcore_roundrobin4_grant) + builder_rhs_self24 <= 22'd0; + case (builder_roundrobin4_grant) default: begin - rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self24 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed25 <= 1'd0; - case (litedramcore_roundrobin4_grant) + builder_rhs_self25 <= 1'd0; + case (builder_roundrobin4_grant) default: begin - rhs_array_muxed25 <= user_port_cmd_payload_we; + builder_rhs_self25 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed26 <= 1'd0; - case (litedramcore_roundrobin4_grant) + builder_rhs_self26 <= 1'd0; + case (builder_roundrobin4_grant) default: begin - rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed27 <= 22'd0; - case (litedramcore_roundrobin5_grant) + builder_rhs_self27 <= 22'd0; + case (builder_roundrobin5_grant) default: begin - rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self27 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed28 <= 1'd0; - case (litedramcore_roundrobin5_grant) + builder_rhs_self28 <= 1'd0; + case (builder_roundrobin5_grant) default: begin - rhs_array_muxed28 <= user_port_cmd_payload_we; + builder_rhs_self28 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed29 <= 1'd0; - case (litedramcore_roundrobin5_grant) + builder_rhs_self29 <= 1'd0; + case (builder_roundrobin5_grant) default: begin - rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed30 <= 22'd0; - case (litedramcore_roundrobin6_grant) + builder_rhs_self30 <= 22'd0; + case (builder_roundrobin6_grant) default: begin - rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self30 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed31 <= 1'd0; - case (litedramcore_roundrobin6_grant) + builder_rhs_self31 <= 1'd0; + case (builder_roundrobin6_grant) default: begin - rhs_array_muxed31 <= user_port_cmd_payload_we; + builder_rhs_self31 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed32 <= 1'd0; - case (litedramcore_roundrobin6_grant) + builder_rhs_self32 <= 1'd0; + case (builder_roundrobin6_grant) default: begin - rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed33 <= 22'd0; - case (litedramcore_roundrobin7_grant) + builder_rhs_self33 <= 22'd0; + case (builder_roundrobin7_grant) default: begin - rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self33 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed34 <= 1'd0; - case (litedramcore_roundrobin7_grant) + builder_rhs_self34 <= 1'd0; + case (builder_roundrobin7_grant) default: begin - rhs_array_muxed34 <= user_port_cmd_payload_we; + builder_rhs_self34 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed35 <= 1'd0; - case (litedramcore_roundrobin7_grant) + builder_rhs_self35 <= 1'd0; + case (builder_roundrobin7_grant) default: begin - rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - array_muxed0 <= 3'd0; - case (litedramcore_steerer_sel0) + builder_self0 <= 3'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed0 <= litedramcore_nop_ba[2:0]; + builder_self0 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed0 <= litedramcore_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed1 <= 15'd0; - case (litedramcore_steerer_sel0) + builder_self1 <= 15'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed1 <= litedramcore_nop_a; + builder_self1 <= main_litedramcore_nop_a; end 1'd1: begin - array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a; + builder_self1 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed1 <= litedramcore_choose_req_cmd_payload_a; + builder_self1 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed1 <= litedramcore_cmd_payload_a; + builder_self1 <= main_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed2 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self2 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed2 <= 1'd0; + builder_self2 <= 1'd0; end 1'd1: begin - array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + builder_self2 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + builder_self2 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + builder_self2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed3 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self3 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed3 <= 1'd0; + builder_self3 <= 1'd0; end 1'd1: begin - array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + builder_self3 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + builder_self3 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + builder_self3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed4 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self4 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed4 <= 1'd0; + builder_self4 <= 1'd0; end 1'd1: begin - array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + builder_self4 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + builder_self4 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + builder_self4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed5 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self5 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed5 <= 1'd0; + builder_self5 <= 1'd0; end 1'd1: begin - array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + builder_self5 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + builder_self5 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + builder_self5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed6 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self6 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed6 <= 1'd0; + builder_self6 <= 1'd0; end 1'd1: begin - array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + builder_self6 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + builder_self6 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + builder_self6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase end always @(*) begin - array_muxed7 <= 3'd0; - case (litedramcore_steerer_sel1) + builder_self7 <= 3'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed7 <= litedramcore_nop_ba[2:0]; + builder_self7 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed7 <= litedramcore_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed8 <= 15'd0; - case (litedramcore_steerer_sel1) + builder_self8 <= 15'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed8 <= litedramcore_nop_a; + builder_self8 <= main_litedramcore_nop_a; end 1'd1: begin - array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a; + builder_self8 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed8 <= litedramcore_choose_req_cmd_payload_a; + builder_self8 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed8 <= litedramcore_cmd_payload_a; + builder_self8 <= main_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed9 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self9 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed9 <= 1'd0; + builder_self9 <= 1'd0; end 1'd1: begin - array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + builder_self9 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + builder_self9 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + builder_self9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed10 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self10 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed10 <= 1'd0; + builder_self10 <= 1'd0; end 1'd1: begin - array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + builder_self10 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + builder_self10 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + builder_self10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed11 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self11 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed11 <= 1'd0; + builder_self11 <= 1'd0; end 1'd1: begin - array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + builder_self11 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + builder_self11 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + builder_self11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed12 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self12 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed12 <= 1'd0; + builder_self12 <= 1'd0; end 1'd1: begin - array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + builder_self12 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + builder_self12 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + builder_self12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed13 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self13 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed13 <= 1'd0; + builder_self13 <= 1'd0; end 1'd1: begin - array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + builder_self13 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + builder_self13 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + builder_self13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase end always @(*) begin - array_muxed14 <= 3'd0; - case (litedramcore_steerer_sel2) + builder_self14 <= 3'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed14 <= litedramcore_nop_ba[2:0]; + builder_self14 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed14 <= litedramcore_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed15 <= 15'd0; - case (litedramcore_steerer_sel2) + builder_self15 <= 15'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed15 <= litedramcore_nop_a; + builder_self15 <= main_litedramcore_nop_a; end 1'd1: begin - array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a; + builder_self15 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed15 <= litedramcore_choose_req_cmd_payload_a; + builder_self15 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed15 <= litedramcore_cmd_payload_a; + builder_self15 <= main_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed16 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self16 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed16 <= 1'd0; + builder_self16 <= 1'd0; end 1'd1: begin - array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + builder_self16 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + builder_self16 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + builder_self16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed17 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self17 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed17 <= 1'd0; + builder_self17 <= 1'd0; end 1'd1: begin - array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + builder_self17 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + builder_self17 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + builder_self17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed18 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self18 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed18 <= 1'd0; + builder_self18 <= 1'd0; end 1'd1: begin - array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + builder_self18 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + builder_self18 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + builder_self18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed19 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self19 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed19 <= 1'd0; + builder_self19 <= 1'd0; end 1'd1: begin - array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + builder_self19 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + builder_self19 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + builder_self19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed20 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self20 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed20 <= 1'd0; + builder_self20 <= 1'd0; end 1'd1: begin - array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + builder_self20 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + builder_self20 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + builder_self20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase end always @(*) begin - array_muxed21 <= 3'd0; - case (litedramcore_steerer_sel3) + builder_self21 <= 3'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed21 <= litedramcore_nop_ba[2:0]; + builder_self21 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed21 <= litedramcore_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed22 <= 15'd0; - case (litedramcore_steerer_sel3) + builder_self22 <= 15'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed22 <= litedramcore_nop_a; + builder_self22 <= main_litedramcore_nop_a; end 1'd1: begin - array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a; + builder_self22 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed22 <= litedramcore_choose_req_cmd_payload_a; + builder_self22 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed22 <= litedramcore_cmd_payload_a; + builder_self22 <= main_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed23 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self23 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed23 <= 1'd0; + builder_self23 <= 1'd0; end 1'd1: begin - array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + builder_self23 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + builder_self23 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + builder_self23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed24 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self24 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed24 <= 1'd0; + builder_self24 <= 1'd0; end 1'd1: begin - array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + builder_self24 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + builder_self24 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + builder_self24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed25 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self25 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed25 <= 1'd0; + builder_self25 <= 1'd0; end 1'd1: begin - array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + builder_self25 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + builder_self25 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + builder_self25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed26 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self26 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed26 <= 1'd0; + builder_self26 <= 1'd0; end 1'd1: begin - array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + builder_self26 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + builder_self26 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + builder_self26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed27 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self27 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed27 <= 1'd0; + builder_self27 <= 1'd0; end 1'd1: begin - array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + builder_self27 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + builder_self27 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + builder_self27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase end -assign xilinxasyncresetsynchronizerimpl0 = (~locked); -assign xilinxasyncresetsynchronizerimpl1 = (~locked); -assign xilinxasyncresetsynchronizerimpl2 = (~locked); -assign xilinxasyncresetsynchronizerimpl3 = (~locked); +assign builder_xilinxasyncresetsynchronizerimpl0_async_reset = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl1_async_reset = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl2_async_reset = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl3_async_reset = (~main_locked); //------------------------------------------------------------------------------ @@ -11983,1044 +12399,1044 @@ assign xilinxasyncresetsynchronizerimpl3 = (~locked); //------------------------------------------------------------------------------ always @(posedge iodelay_clk) begin - if ((reset_counter != 1'd0)) begin - reset_counter <= (reset_counter - 1'd1); + if ((main_reset_counter != 1'd0)) begin + main_reset_counter <= (main_reset_counter - 1'd1); end else begin - ic_reset <= 1'd0; + main_ic_reset <= 1'd0; end if (iodelay_rst) begin - reset_counter <= 4'd15; - ic_reset <= 1'd1; + main_reset_counter <= 4'd15; + main_ic_reset <= 1'd1; end end always @(posedge sys_clk) begin - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline; - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; - a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1); + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline; + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; + main_a7ddrphy_dqspattern_o1 <= main_a7ddrphy_dqspattern_o0; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value0 <= (main_a7ddrphy_bitslip0_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value0 <= 3'd7; end - a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1); + main_a7ddrphy_bitslip0_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip0_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value0 <= (main_a7ddrphy_bitslip1_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value0 <= 3'd7; end - a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1); + main_a7ddrphy_bitslip1_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip1_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value1 <= (main_a7ddrphy_bitslip0_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value1 <= 3'd7; end - a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1); + main_a7ddrphy_bitslip0_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[2], main_a7ddrphy_dfi_p3_wrdata_mask[0], main_a7ddrphy_dfi_p2_wrdata_mask[2], main_a7ddrphy_dfi_p2_wrdata_mask[0], main_a7ddrphy_dfi_p1_wrdata_mask[2], main_a7ddrphy_dfi_p1_wrdata_mask[0], main_a7ddrphy_dfi_p0_wrdata_mask[2], main_a7ddrphy_dfi_p0_wrdata_mask[0]}, main_a7ddrphy_bitslip0_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value1 <= (main_a7ddrphy_bitslip1_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value1 <= 3'd7; end - a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]}; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1); + main_a7ddrphy_bitslip1_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[3], main_a7ddrphy_dfi_p3_wrdata_mask[1], main_a7ddrphy_dfi_p2_wrdata_mask[3], main_a7ddrphy_dfi_p2_wrdata_mask[1], main_a7ddrphy_dfi_p1_wrdata_mask[3], main_a7ddrphy_dfi_p1_wrdata_mask[1], main_a7ddrphy_dfi_p0_wrdata_mask[3], main_a7ddrphy_dfi_p0_wrdata_mask[1]}, main_a7ddrphy_bitslip1_r1[15:8]}; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dq_oe_delay_tappeddelayline; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value2 <= (main_a7ddrphy_bitslip0_value2 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value2 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value2 <= 3'd7; end - a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1); + main_a7ddrphy_bitslip0_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[16], main_a7ddrphy_dfi_p3_wrdata[0], main_a7ddrphy_dfi_p2_wrdata[16], main_a7ddrphy_dfi_p2_wrdata[0], main_a7ddrphy_dfi_p1_wrdata[16], main_a7ddrphy_dfi_p1_wrdata[0], main_a7ddrphy_dfi_p0_wrdata[16], main_a7ddrphy_dfi_p0_wrdata[0]}, main_a7ddrphy_bitslip0_r2[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value3 <= (main_a7ddrphy_bitslip0_value3 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value3 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value3 <= 3'd7; end - a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1); + main_a7ddrphy_bitslip0_r3 <= {main_a7ddrphy_bitslip03, main_a7ddrphy_bitslip0_r3[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value2 <= (main_a7ddrphy_bitslip1_value2 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value2 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value2 <= 3'd7; end - a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1); + main_a7ddrphy_bitslip1_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[17], main_a7ddrphy_dfi_p3_wrdata[1], main_a7ddrphy_dfi_p2_wrdata[17], main_a7ddrphy_dfi_p2_wrdata[1], main_a7ddrphy_dfi_p1_wrdata[17], main_a7ddrphy_dfi_p1_wrdata[1], main_a7ddrphy_dfi_p0_wrdata[17], main_a7ddrphy_dfi_p0_wrdata[1]}, main_a7ddrphy_bitslip1_r2[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value3 <= (main_a7ddrphy_bitslip1_value3 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value3 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value3 <= 3'd7; end - a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1); + main_a7ddrphy_bitslip1_r3 <= {main_a7ddrphy_bitslip13, main_a7ddrphy_bitslip1_r3[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip2_value0 <= (main_a7ddrphy_bitslip2_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip2_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip2_value0 <= 3'd7; end - a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1); + main_a7ddrphy_bitslip2_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[18], main_a7ddrphy_dfi_p3_wrdata[2], main_a7ddrphy_dfi_p2_wrdata[18], main_a7ddrphy_dfi_p2_wrdata[2], main_a7ddrphy_dfi_p1_wrdata[18], main_a7ddrphy_dfi_p1_wrdata[2], main_a7ddrphy_dfi_p0_wrdata[18], main_a7ddrphy_dfi_p0_wrdata[2]}, main_a7ddrphy_bitslip2_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip2_value1 <= (main_a7ddrphy_bitslip2_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip2_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip2_value1 <= 3'd7; end - a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1); + main_a7ddrphy_bitslip2_r1 <= {main_a7ddrphy_bitslip21, main_a7ddrphy_bitslip2_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip3_value0 <= (main_a7ddrphy_bitslip3_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip3_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip3_value0 <= 3'd7; end - a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1); + main_a7ddrphy_bitslip3_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[19], main_a7ddrphy_dfi_p3_wrdata[3], main_a7ddrphy_dfi_p2_wrdata[19], main_a7ddrphy_dfi_p2_wrdata[3], main_a7ddrphy_dfi_p1_wrdata[19], main_a7ddrphy_dfi_p1_wrdata[3], main_a7ddrphy_dfi_p0_wrdata[19], main_a7ddrphy_dfi_p0_wrdata[3]}, main_a7ddrphy_bitslip3_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip3_value1 <= (main_a7ddrphy_bitslip3_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip3_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip3_value1 <= 3'd7; end - a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1); + main_a7ddrphy_bitslip3_r1 <= {main_a7ddrphy_bitslip31, main_a7ddrphy_bitslip3_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip4_value0 <= (main_a7ddrphy_bitslip4_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip4_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip4_value0 <= 3'd7; end - a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1); + main_a7ddrphy_bitslip4_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[20], main_a7ddrphy_dfi_p3_wrdata[4], main_a7ddrphy_dfi_p2_wrdata[20], main_a7ddrphy_dfi_p2_wrdata[4], main_a7ddrphy_dfi_p1_wrdata[20], main_a7ddrphy_dfi_p1_wrdata[4], main_a7ddrphy_dfi_p0_wrdata[20], main_a7ddrphy_dfi_p0_wrdata[4]}, main_a7ddrphy_bitslip4_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip4_value1 <= (main_a7ddrphy_bitslip4_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip4_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip4_value1 <= 3'd7; end - a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1); + main_a7ddrphy_bitslip4_r1 <= {main_a7ddrphy_bitslip41, main_a7ddrphy_bitslip4_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip5_value0 <= (main_a7ddrphy_bitslip5_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip5_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip5_value0 <= 3'd7; end - a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1); + main_a7ddrphy_bitslip5_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[21], main_a7ddrphy_dfi_p3_wrdata[5], main_a7ddrphy_dfi_p2_wrdata[21], main_a7ddrphy_dfi_p2_wrdata[5], main_a7ddrphy_dfi_p1_wrdata[21], main_a7ddrphy_dfi_p1_wrdata[5], main_a7ddrphy_dfi_p0_wrdata[21], main_a7ddrphy_dfi_p0_wrdata[5]}, main_a7ddrphy_bitslip5_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip5_value1 <= (main_a7ddrphy_bitslip5_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip5_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip5_value1 <= 3'd7; end - a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1); + main_a7ddrphy_bitslip5_r1 <= {main_a7ddrphy_bitslip51, main_a7ddrphy_bitslip5_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip6_value0 <= (main_a7ddrphy_bitslip6_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip6_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip6_value0 <= 3'd7; end - a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1); + main_a7ddrphy_bitslip6_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[22], main_a7ddrphy_dfi_p3_wrdata[6], main_a7ddrphy_dfi_p2_wrdata[22], main_a7ddrphy_dfi_p2_wrdata[6], main_a7ddrphy_dfi_p1_wrdata[22], main_a7ddrphy_dfi_p1_wrdata[6], main_a7ddrphy_dfi_p0_wrdata[22], main_a7ddrphy_dfi_p0_wrdata[6]}, main_a7ddrphy_bitslip6_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip6_value1 <= (main_a7ddrphy_bitslip6_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip6_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip6_value1 <= 3'd7; end - a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1); + main_a7ddrphy_bitslip6_r1 <= {main_a7ddrphy_bitslip61, main_a7ddrphy_bitslip6_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip7_value0 <= (main_a7ddrphy_bitslip7_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip7_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip7_value0 <= 3'd7; end - a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1); + main_a7ddrphy_bitslip7_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[23], main_a7ddrphy_dfi_p3_wrdata[7], main_a7ddrphy_dfi_p2_wrdata[23], main_a7ddrphy_dfi_p2_wrdata[7], main_a7ddrphy_dfi_p1_wrdata[23], main_a7ddrphy_dfi_p1_wrdata[7], main_a7ddrphy_dfi_p0_wrdata[23], main_a7ddrphy_dfi_p0_wrdata[7]}, main_a7ddrphy_bitslip7_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip7_value1 <= (main_a7ddrphy_bitslip7_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip7_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip7_value1 <= 3'd7; end - a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1); + main_a7ddrphy_bitslip7_r1 <= {main_a7ddrphy_bitslip71, main_a7ddrphy_bitslip7_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip8_value0 <= (main_a7ddrphy_bitslip8_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip8_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip8_value0 <= 3'd7; end - a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1); + main_a7ddrphy_bitslip8_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[24], main_a7ddrphy_dfi_p3_wrdata[8], main_a7ddrphy_dfi_p2_wrdata[24], main_a7ddrphy_dfi_p2_wrdata[8], main_a7ddrphy_dfi_p1_wrdata[24], main_a7ddrphy_dfi_p1_wrdata[8], main_a7ddrphy_dfi_p0_wrdata[24], main_a7ddrphy_dfi_p0_wrdata[8]}, main_a7ddrphy_bitslip8_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip8_value1 <= (main_a7ddrphy_bitslip8_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip8_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip8_value1 <= 3'd7; end - a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1); + main_a7ddrphy_bitslip8_r1 <= {main_a7ddrphy_bitslip81, main_a7ddrphy_bitslip8_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip9_value0 <= (main_a7ddrphy_bitslip9_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip9_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip9_value0 <= 3'd7; end - a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1); + main_a7ddrphy_bitslip9_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[25], main_a7ddrphy_dfi_p3_wrdata[9], main_a7ddrphy_dfi_p2_wrdata[25], main_a7ddrphy_dfi_p2_wrdata[9], main_a7ddrphy_dfi_p1_wrdata[25], main_a7ddrphy_dfi_p1_wrdata[9], main_a7ddrphy_dfi_p0_wrdata[25], main_a7ddrphy_dfi_p0_wrdata[9]}, main_a7ddrphy_bitslip9_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip9_value1 <= (main_a7ddrphy_bitslip9_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip9_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip9_value1 <= 3'd7; end - a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1); + main_a7ddrphy_bitslip9_r1 <= {main_a7ddrphy_bitslip91, main_a7ddrphy_bitslip9_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip10_value0 <= (main_a7ddrphy_bitslip10_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip10_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip10_value0 <= 3'd7; end - a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1); + main_a7ddrphy_bitslip10_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[26], main_a7ddrphy_dfi_p3_wrdata[10], main_a7ddrphy_dfi_p2_wrdata[26], main_a7ddrphy_dfi_p2_wrdata[10], main_a7ddrphy_dfi_p1_wrdata[26], main_a7ddrphy_dfi_p1_wrdata[10], main_a7ddrphy_dfi_p0_wrdata[26], main_a7ddrphy_dfi_p0_wrdata[10]}, main_a7ddrphy_bitslip10_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip10_value1 <= (main_a7ddrphy_bitslip10_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip10_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip10_value1 <= 3'd7; end - a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1); + main_a7ddrphy_bitslip10_r1 <= {main_a7ddrphy_bitslip101, main_a7ddrphy_bitslip10_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip11_value0 <= (main_a7ddrphy_bitslip11_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip11_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip11_value0 <= 3'd7; end - a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1); + main_a7ddrphy_bitslip11_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[27], main_a7ddrphy_dfi_p3_wrdata[11], main_a7ddrphy_dfi_p2_wrdata[27], main_a7ddrphy_dfi_p2_wrdata[11], main_a7ddrphy_dfi_p1_wrdata[27], main_a7ddrphy_dfi_p1_wrdata[11], main_a7ddrphy_dfi_p0_wrdata[27], main_a7ddrphy_dfi_p0_wrdata[11]}, main_a7ddrphy_bitslip11_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip11_value1 <= (main_a7ddrphy_bitslip11_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip11_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip11_value1 <= 3'd7; end - a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1); + main_a7ddrphy_bitslip11_r1 <= {main_a7ddrphy_bitslip111, main_a7ddrphy_bitslip11_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip12_value0 <= (main_a7ddrphy_bitslip12_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip12_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip12_value0 <= 3'd7; end - a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1); + main_a7ddrphy_bitslip12_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[28], main_a7ddrphy_dfi_p3_wrdata[12], main_a7ddrphy_dfi_p2_wrdata[28], main_a7ddrphy_dfi_p2_wrdata[12], main_a7ddrphy_dfi_p1_wrdata[28], main_a7ddrphy_dfi_p1_wrdata[12], main_a7ddrphy_dfi_p0_wrdata[28], main_a7ddrphy_dfi_p0_wrdata[12]}, main_a7ddrphy_bitslip12_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip12_value1 <= (main_a7ddrphy_bitslip12_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip12_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip12_value1 <= 3'd7; end - a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1); + main_a7ddrphy_bitslip12_r1 <= {main_a7ddrphy_bitslip121, main_a7ddrphy_bitslip12_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip13_value0 <= (main_a7ddrphy_bitslip13_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip13_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip13_value0 <= 3'd7; end - a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1); + main_a7ddrphy_bitslip13_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[29], main_a7ddrphy_dfi_p3_wrdata[13], main_a7ddrphy_dfi_p2_wrdata[29], main_a7ddrphy_dfi_p2_wrdata[13], main_a7ddrphy_dfi_p1_wrdata[29], main_a7ddrphy_dfi_p1_wrdata[13], main_a7ddrphy_dfi_p0_wrdata[29], main_a7ddrphy_dfi_p0_wrdata[13]}, main_a7ddrphy_bitslip13_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip13_value1 <= (main_a7ddrphy_bitslip13_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip13_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip13_value1 <= 3'd7; end - a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1); + main_a7ddrphy_bitslip13_r1 <= {main_a7ddrphy_bitslip131, main_a7ddrphy_bitslip13_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip14_value0 <= (main_a7ddrphy_bitslip14_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip14_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip14_value0 <= 3'd7; end - a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1); + main_a7ddrphy_bitslip14_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[30], main_a7ddrphy_dfi_p3_wrdata[14], main_a7ddrphy_dfi_p2_wrdata[30], main_a7ddrphy_dfi_p2_wrdata[14], main_a7ddrphy_dfi_p1_wrdata[30], main_a7ddrphy_dfi_p1_wrdata[14], main_a7ddrphy_dfi_p0_wrdata[30], main_a7ddrphy_dfi_p0_wrdata[14]}, main_a7ddrphy_bitslip14_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip14_value1 <= (main_a7ddrphy_bitslip14_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip14_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip14_value1 <= 3'd7; end - a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1); + main_a7ddrphy_bitslip14_r1 <= {main_a7ddrphy_bitslip141, main_a7ddrphy_bitslip14_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip15_value0 <= (main_a7ddrphy_bitslip15_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip15_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip15_value0 <= 3'd7; end - a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1); + main_a7ddrphy_bitslip15_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[31], main_a7ddrphy_dfi_p3_wrdata[15], main_a7ddrphy_dfi_p2_wrdata[31], main_a7ddrphy_dfi_p2_wrdata[15], main_a7ddrphy_dfi_p1_wrdata[31], main_a7ddrphy_dfi_p1_wrdata[15], main_a7ddrphy_dfi_p0_wrdata[31], main_a7ddrphy_dfi_p0_wrdata[15]}, main_a7ddrphy_bitslip15_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip15_value1 <= (main_a7ddrphy_bitslip15_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip15_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip15_value1 <= 3'd7; end - a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]}; - a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en); - a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0; - a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1; - a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2; - a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3; - a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4; - a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5; - a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6; - a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en); - a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0; - a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1; - if (litedramcore_csr_dfi_p0_rddata_valid) begin - litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata; + main_a7ddrphy_bitslip15_r1 <= {main_a7ddrphy_bitslip151, main_a7ddrphy_bitslip15_r1[15:8]}; + main_a7ddrphy_rddata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_rddata_en | main_a7ddrphy_dfi_p1_rddata_en) | main_a7ddrphy_dfi_p2_rddata_en) | main_a7ddrphy_dfi_p3_rddata_en); + main_a7ddrphy_rddata_en_tappeddelayline1 <= main_a7ddrphy_rddata_en_tappeddelayline0; + main_a7ddrphy_rddata_en_tappeddelayline2 <= main_a7ddrphy_rddata_en_tappeddelayline1; + main_a7ddrphy_rddata_en_tappeddelayline3 <= main_a7ddrphy_rddata_en_tappeddelayline2; + main_a7ddrphy_rddata_en_tappeddelayline4 <= main_a7ddrphy_rddata_en_tappeddelayline3; + main_a7ddrphy_rddata_en_tappeddelayline5 <= main_a7ddrphy_rddata_en_tappeddelayline4; + main_a7ddrphy_rddata_en_tappeddelayline6 <= main_a7ddrphy_rddata_en_tappeddelayline5; + main_a7ddrphy_rddata_en_tappeddelayline7 <= main_a7ddrphy_rddata_en_tappeddelayline6; + main_a7ddrphy_wrdata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_wrdata_en | main_a7ddrphy_dfi_p1_wrdata_en) | main_a7ddrphy_dfi_p2_wrdata_en) | main_a7ddrphy_dfi_p3_wrdata_en); + main_a7ddrphy_wrdata_en_tappeddelayline1 <= main_a7ddrphy_wrdata_en_tappeddelayline0; + main_a7ddrphy_wrdata_en_tappeddelayline2 <= main_a7ddrphy_wrdata_en_tappeddelayline1; + if (main_litedramcore_csr_dfi_p0_rddata_valid) begin + main_litedramcore_phaseinjector0_rddata_status <= main_litedramcore_csr_dfi_p0_rddata; end - if (litedramcore_csr_dfi_p1_rddata_valid) begin - litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata; + if (main_litedramcore_csr_dfi_p1_rddata_valid) begin + main_litedramcore_phaseinjector1_rddata_status <= main_litedramcore_csr_dfi_p1_rddata; end - if (litedramcore_csr_dfi_p2_rddata_valid) begin - litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata; + if (main_litedramcore_csr_dfi_p2_rddata_valid) begin + main_litedramcore_phaseinjector2_rddata_status <= main_litedramcore_csr_dfi_p2_rddata; end - if (litedramcore_csr_dfi_p3_rddata_valid) begin - litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata; - end - if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin - litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); + if (main_litedramcore_csr_dfi_p3_rddata_valid) begin + main_litedramcore_phaseinjector3_rddata_status <= main_litedramcore_csr_dfi_p3_rddata; + end + if ((main_litedramcore_timer_wait & (~main_litedramcore_timer_done0))) begin + main_litedramcore_timer_count1 <= (main_litedramcore_timer_count1 - 1'd1); end else begin - litedramcore_timer_count1 <= 10'd781; + main_litedramcore_timer_count1 <= 10'd781; end - litedramcore_postponer_req_o <= 1'd0; - if (litedramcore_postponer_req_i) begin - litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); - if ((litedramcore_postponer_count == 1'd0)) begin - litedramcore_postponer_count <= 1'd0; - litedramcore_postponer_req_o <= 1'd1; - end + main_litedramcore_postponer_req_o <= 1'd0; + if (main_litedramcore_postponer_req_i) begin + main_litedramcore_postponer_count <= (main_litedramcore_postponer_count - 1'd1); + if ((main_litedramcore_postponer_count == 1'd0)) begin + main_litedramcore_postponer_count <= 1'd0; + main_litedramcore_postponer_req_o <= 1'd1; + end end - if (litedramcore_sequencer_start0) begin - litedramcore_sequencer_count <= 1'd0; - end else begin - if (litedramcore_sequencer_done1) begin - if ((litedramcore_sequencer_count != 1'd0)) begin - litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); - end - end - end - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_sequencer_done1 <= 1'd0; - if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_sequencer_counter == 2'd3)) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd1; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd0; - end - if ((litedramcore_sequencer_counter == 6'd55)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_sequencer_done1 <= 1'd1; - end - if ((litedramcore_sequencer_counter == 6'd55)) begin - litedramcore_sequencer_counter <= 1'd0; - end else begin - if ((litedramcore_sequencer_counter != 1'd0)) begin - litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1); + if (main_litedramcore_sequencer_start0) begin + main_litedramcore_sequencer_count <= 1'd0; + end else begin + if (main_litedramcore_sequencer_done1) begin + if ((main_litedramcore_sequencer_count != 1'd0)) begin + main_litedramcore_sequencer_count <= (main_litedramcore_sequencer_count - 1'd1); + end + end + end + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd0; + if ((main_litedramcore_sequencer_start1 & (main_litedramcore_sequencer_trigger == 1'd0))) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_sequencer_trigger == 2'd3)) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd1; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd0; + end + if ((main_litedramcore_sequencer_trigger == 6'd55)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd1; + end + if ((main_litedramcore_sequencer_trigger == 6'd55)) begin + main_litedramcore_sequencer_trigger <= 1'd0; + end else begin + if ((main_litedramcore_sequencer_trigger != 1'd0)) begin + main_litedramcore_sequencer_trigger <= (main_litedramcore_sequencer_trigger + 1'd1); end else begin - if (litedramcore_sequencer_start1) begin - litedramcore_sequencer_counter <= 1'd1; + if (main_litedramcore_sequencer_start1) begin + main_litedramcore_sequencer_trigger <= 1'd1; end end end - if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin - litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); + if ((main_litedramcore_zqcs_timer_wait & (~main_litedramcore_zqcs_timer_done0))) begin + main_litedramcore_zqcs_timer_count1 <= (main_litedramcore_zqcs_timer_count1 - 1'd1); end else begin - litedramcore_zqcs_timer_count1 <= 27'd99999999; - end - litedramcore_zqcs_executer_done <= 1'd0; - if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 2'd3)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 5'd19)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_zqcs_executer_done <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 5'd19)) begin - litedramcore_zqcs_executer_counter <= 1'd0; + main_litedramcore_zqcs_timer_count1 <= 27'd99999999; + end + main_litedramcore_zqcs_executer_done <= 1'd0; + if ((main_litedramcore_zqcs_executer_start & (main_litedramcore_zqcs_executer_trigger == 1'd0))) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_trigger == 2'd3)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_trigger == 5'd19)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_zqcs_executer_done <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_trigger == 5'd19)) begin + main_litedramcore_zqcs_executer_trigger <= 1'd0; end else begin - if ((litedramcore_zqcs_executer_counter != 1'd0)) begin - litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1); + if ((main_litedramcore_zqcs_executer_trigger != 1'd0)) begin + main_litedramcore_zqcs_executer_trigger <= (main_litedramcore_zqcs_executer_trigger + 1'd1); end else begin - if (litedramcore_zqcs_executer_start) begin - litedramcore_zqcs_executer_counter <= 1'd1; + if (main_litedramcore_zqcs_executer_start) begin + main_litedramcore_zqcs_executer_trigger <= 1'd1; end end end - litedramcore_refresher_state <= litedramcore_refresher_next_state; - if (litedramcore_bankmachine0_row_close) begin - litedramcore_bankmachine0_row_opened <= 1'd0; + builder_refresher_state <= builder_refresher_next_state; + if (main_litedramcore_bankmachine0_row_close) begin + main_litedramcore_bankmachine0_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine0_row_open) begin - litedramcore_bankmachine0_row_opened <= 1'd1; - litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine0_row_open) begin + main_litedramcore_bankmachine0_row_opened <= 1'd1; + main_litedramcore_bankmachine0_row <= main_litedramcore_bankmachine0_source_source_payload_addr[21:7]; end end - if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin - litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1); + if (((main_litedramcore_bankmachine0_syncfifo0_we & main_litedramcore_bankmachine0_syncfifo0_writable) & (~main_litedramcore_bankmachine0_replace))) begin + main_litedramcore_bankmachine0_produce <= (main_litedramcore_bankmachine0_produce + 1'd1); end - if (litedramcore_bankmachine0_do_read) begin - litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1); + if (main_litedramcore_bankmachine0_do_read) begin + main_litedramcore_bankmachine0_consume <= (main_litedramcore_bankmachine0_consume + 1'd1); end - if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin - if ((~litedramcore_bankmachine0_do_read)) begin - litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1); + if (((main_litedramcore_bankmachine0_syncfifo0_we & main_litedramcore_bankmachine0_syncfifo0_writable) & (~main_litedramcore_bankmachine0_replace))) begin + if ((~main_litedramcore_bankmachine0_do_read)) begin + main_litedramcore_bankmachine0_level <= (main_litedramcore_bankmachine0_level + 1'd1); end end else begin - if (litedramcore_bankmachine0_do_read) begin - litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1); + if (main_litedramcore_bankmachine0_do_read) begin + main_litedramcore_bankmachine0_level <= (main_litedramcore_bankmachine0_level - 1'd1); end end - if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin - litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid; - litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first; - litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last; - litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we; - litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine0_pipe_valid_source_valid) | main_litedramcore_bankmachine0_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine0_pipe_valid_source_valid <= main_litedramcore_bankmachine0_pipe_valid_sink_valid; + main_litedramcore_bankmachine0_pipe_valid_source_first <= main_litedramcore_bankmachine0_pipe_valid_sink_first; + main_litedramcore_bankmachine0_pipe_valid_source_last <= main_litedramcore_bankmachine0_pipe_valid_sink_last; + main_litedramcore_bankmachine0_pipe_valid_source_payload_we <= main_litedramcore_bankmachine0_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine0_twtpcon_valid) begin - litedramcore_bankmachine0_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine0_twtpcon_valid) begin + main_litedramcore_bankmachine0_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine0_twtpcon_ready)) begin - litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_twtpcon_ready)) begin + main_litedramcore_bankmachine0_twtpcon_count <= (main_litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine0_trccon_valid) begin - litedramcore_bankmachine0_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine0_trccon_valid) begin + main_litedramcore_bankmachine0_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine0_trccon_ready <= 1'd1; + main_litedramcore_bankmachine0_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine0_trccon_ready <= 1'd0; + main_litedramcore_bankmachine0_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine0_trccon_ready)) begin - litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); - if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin - litedramcore_bankmachine0_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_trccon_ready)) begin + main_litedramcore_bankmachine0_trccon_count <= (main_litedramcore_bankmachine0_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine0_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine0_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine0_trascon_valid) begin - litedramcore_bankmachine0_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine0_trascon_valid) begin + main_litedramcore_bankmachine0_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine0_trascon_ready <= 1'd1; + main_litedramcore_bankmachine0_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine0_trascon_ready <= 1'd0; + main_litedramcore_bankmachine0_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); - if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin - litedramcore_bankmachine0_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_trascon_count <= (main_litedramcore_bankmachine0_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine0_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine0_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state; - if (litedramcore_bankmachine1_row_close) begin - litedramcore_bankmachine1_row_opened <= 1'd0; + builder_bankmachine0_state <= builder_bankmachine0_next_state; + if (main_litedramcore_bankmachine1_row_close) begin + main_litedramcore_bankmachine1_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine1_row_open) begin - litedramcore_bankmachine1_row_opened <= 1'd1; - litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine1_row_open) begin + main_litedramcore_bankmachine1_row_opened <= 1'd1; + main_litedramcore_bankmachine1_row <= main_litedramcore_bankmachine1_source_source_payload_addr[21:7]; end end - if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin - litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1); + if (((main_litedramcore_bankmachine1_syncfifo1_we & main_litedramcore_bankmachine1_syncfifo1_writable) & (~main_litedramcore_bankmachine1_replace))) begin + main_litedramcore_bankmachine1_produce <= (main_litedramcore_bankmachine1_produce + 1'd1); end - if (litedramcore_bankmachine1_do_read) begin - litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1); + if (main_litedramcore_bankmachine1_do_read) begin + main_litedramcore_bankmachine1_consume <= (main_litedramcore_bankmachine1_consume + 1'd1); end - if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin - if ((~litedramcore_bankmachine1_do_read)) begin - litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1); + if (((main_litedramcore_bankmachine1_syncfifo1_we & main_litedramcore_bankmachine1_syncfifo1_writable) & (~main_litedramcore_bankmachine1_replace))) begin + if ((~main_litedramcore_bankmachine1_do_read)) begin + main_litedramcore_bankmachine1_level <= (main_litedramcore_bankmachine1_level + 1'd1); end end else begin - if (litedramcore_bankmachine1_do_read) begin - litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1); + if (main_litedramcore_bankmachine1_do_read) begin + main_litedramcore_bankmachine1_level <= (main_litedramcore_bankmachine1_level - 1'd1); end end - if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin - litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid; - litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first; - litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last; - litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we; - litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine1_pipe_valid_source_valid) | main_litedramcore_bankmachine1_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine1_pipe_valid_source_valid <= main_litedramcore_bankmachine1_pipe_valid_sink_valid; + main_litedramcore_bankmachine1_pipe_valid_source_first <= main_litedramcore_bankmachine1_pipe_valid_sink_first; + main_litedramcore_bankmachine1_pipe_valid_source_last <= main_litedramcore_bankmachine1_pipe_valid_sink_last; + main_litedramcore_bankmachine1_pipe_valid_source_payload_we <= main_litedramcore_bankmachine1_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine1_twtpcon_valid) begin - litedramcore_bankmachine1_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine1_twtpcon_valid) begin + main_litedramcore_bankmachine1_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine1_twtpcon_ready)) begin - litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_twtpcon_ready)) begin + main_litedramcore_bankmachine1_twtpcon_count <= (main_litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine1_trccon_valid) begin - litedramcore_bankmachine1_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine1_trccon_valid) begin + main_litedramcore_bankmachine1_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine1_trccon_ready <= 1'd1; + main_litedramcore_bankmachine1_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine1_trccon_ready <= 1'd0; + main_litedramcore_bankmachine1_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine1_trccon_ready)) begin - litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); - if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin - litedramcore_bankmachine1_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_trccon_ready)) begin + main_litedramcore_bankmachine1_trccon_count <= (main_litedramcore_bankmachine1_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine1_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine1_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine1_trascon_valid) begin - litedramcore_bankmachine1_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine1_trascon_valid) begin + main_litedramcore_bankmachine1_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine1_trascon_ready <= 1'd1; + main_litedramcore_bankmachine1_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine1_trascon_ready <= 1'd0; + main_litedramcore_bankmachine1_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); - if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin - litedramcore_bankmachine1_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_trascon_count <= (main_litedramcore_bankmachine1_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine1_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine1_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state; - if (litedramcore_bankmachine2_row_close) begin - litedramcore_bankmachine2_row_opened <= 1'd0; + builder_bankmachine1_state <= builder_bankmachine1_next_state; + if (main_litedramcore_bankmachine2_row_close) begin + main_litedramcore_bankmachine2_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine2_row_open) begin - litedramcore_bankmachine2_row_opened <= 1'd1; - litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine2_row_open) begin + main_litedramcore_bankmachine2_row_opened <= 1'd1; + main_litedramcore_bankmachine2_row <= main_litedramcore_bankmachine2_source_source_payload_addr[21:7]; end end - if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin - litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1); + if (((main_litedramcore_bankmachine2_syncfifo2_we & main_litedramcore_bankmachine2_syncfifo2_writable) & (~main_litedramcore_bankmachine2_replace))) begin + main_litedramcore_bankmachine2_produce <= (main_litedramcore_bankmachine2_produce + 1'd1); end - if (litedramcore_bankmachine2_do_read) begin - litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1); + if (main_litedramcore_bankmachine2_do_read) begin + main_litedramcore_bankmachine2_consume <= (main_litedramcore_bankmachine2_consume + 1'd1); end - if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin - if ((~litedramcore_bankmachine2_do_read)) begin - litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1); + if (((main_litedramcore_bankmachine2_syncfifo2_we & main_litedramcore_bankmachine2_syncfifo2_writable) & (~main_litedramcore_bankmachine2_replace))) begin + if ((~main_litedramcore_bankmachine2_do_read)) begin + main_litedramcore_bankmachine2_level <= (main_litedramcore_bankmachine2_level + 1'd1); end end else begin - if (litedramcore_bankmachine2_do_read) begin - litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1); + if (main_litedramcore_bankmachine2_do_read) begin + main_litedramcore_bankmachine2_level <= (main_litedramcore_bankmachine2_level - 1'd1); end end - if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin - litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid; - litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first; - litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last; - litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we; - litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine2_pipe_valid_source_valid) | main_litedramcore_bankmachine2_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine2_pipe_valid_source_valid <= main_litedramcore_bankmachine2_pipe_valid_sink_valid; + main_litedramcore_bankmachine2_pipe_valid_source_first <= main_litedramcore_bankmachine2_pipe_valid_sink_first; + main_litedramcore_bankmachine2_pipe_valid_source_last <= main_litedramcore_bankmachine2_pipe_valid_sink_last; + main_litedramcore_bankmachine2_pipe_valid_source_payload_we <= main_litedramcore_bankmachine2_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine2_twtpcon_valid) begin - litedramcore_bankmachine2_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine2_twtpcon_valid) begin + main_litedramcore_bankmachine2_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine2_twtpcon_ready)) begin - litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_twtpcon_ready)) begin + main_litedramcore_bankmachine2_twtpcon_count <= (main_litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine2_trccon_valid) begin - litedramcore_bankmachine2_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine2_trccon_valid) begin + main_litedramcore_bankmachine2_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine2_trccon_ready <= 1'd1; + main_litedramcore_bankmachine2_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine2_trccon_ready <= 1'd0; + main_litedramcore_bankmachine2_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine2_trccon_ready)) begin - litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); - if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin - litedramcore_bankmachine2_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_trccon_ready)) begin + main_litedramcore_bankmachine2_trccon_count <= (main_litedramcore_bankmachine2_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine2_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine2_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine2_trascon_valid) begin - litedramcore_bankmachine2_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine2_trascon_valid) begin + main_litedramcore_bankmachine2_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine2_trascon_ready <= 1'd1; + main_litedramcore_bankmachine2_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine2_trascon_ready <= 1'd0; + main_litedramcore_bankmachine2_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); - if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin - litedramcore_bankmachine2_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_trascon_count <= (main_litedramcore_bankmachine2_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine2_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine2_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state; - if (litedramcore_bankmachine3_row_close) begin - litedramcore_bankmachine3_row_opened <= 1'd0; + builder_bankmachine2_state <= builder_bankmachine2_next_state; + if (main_litedramcore_bankmachine3_row_close) begin + main_litedramcore_bankmachine3_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine3_row_open) begin - litedramcore_bankmachine3_row_opened <= 1'd1; - litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine3_row_open) begin + main_litedramcore_bankmachine3_row_opened <= 1'd1; + main_litedramcore_bankmachine3_row <= main_litedramcore_bankmachine3_source_source_payload_addr[21:7]; end end - if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin - litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1); + if (((main_litedramcore_bankmachine3_syncfifo3_we & main_litedramcore_bankmachine3_syncfifo3_writable) & (~main_litedramcore_bankmachine3_replace))) begin + main_litedramcore_bankmachine3_produce <= (main_litedramcore_bankmachine3_produce + 1'd1); end - if (litedramcore_bankmachine3_do_read) begin - litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1); + if (main_litedramcore_bankmachine3_do_read) begin + main_litedramcore_bankmachine3_consume <= (main_litedramcore_bankmachine3_consume + 1'd1); end - if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin - if ((~litedramcore_bankmachine3_do_read)) begin - litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1); + if (((main_litedramcore_bankmachine3_syncfifo3_we & main_litedramcore_bankmachine3_syncfifo3_writable) & (~main_litedramcore_bankmachine3_replace))) begin + if ((~main_litedramcore_bankmachine3_do_read)) begin + main_litedramcore_bankmachine3_level <= (main_litedramcore_bankmachine3_level + 1'd1); end end else begin - if (litedramcore_bankmachine3_do_read) begin - litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1); + if (main_litedramcore_bankmachine3_do_read) begin + main_litedramcore_bankmachine3_level <= (main_litedramcore_bankmachine3_level - 1'd1); end end - if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin - litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid; - litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first; - litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last; - litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we; - litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine3_pipe_valid_source_valid) | main_litedramcore_bankmachine3_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine3_pipe_valid_source_valid <= main_litedramcore_bankmachine3_pipe_valid_sink_valid; + main_litedramcore_bankmachine3_pipe_valid_source_first <= main_litedramcore_bankmachine3_pipe_valid_sink_first; + main_litedramcore_bankmachine3_pipe_valid_source_last <= main_litedramcore_bankmachine3_pipe_valid_sink_last; + main_litedramcore_bankmachine3_pipe_valid_source_payload_we <= main_litedramcore_bankmachine3_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine3_twtpcon_valid) begin - litedramcore_bankmachine3_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine3_twtpcon_valid) begin + main_litedramcore_bankmachine3_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine3_twtpcon_ready)) begin - litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_twtpcon_ready)) begin + main_litedramcore_bankmachine3_twtpcon_count <= (main_litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine3_trccon_valid) begin - litedramcore_bankmachine3_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine3_trccon_valid) begin + main_litedramcore_bankmachine3_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine3_trccon_ready <= 1'd1; + main_litedramcore_bankmachine3_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine3_trccon_ready <= 1'd0; + main_litedramcore_bankmachine3_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine3_trccon_ready)) begin - litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); - if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin - litedramcore_bankmachine3_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_trccon_ready)) begin + main_litedramcore_bankmachine3_trccon_count <= (main_litedramcore_bankmachine3_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine3_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine3_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine3_trascon_valid) begin - litedramcore_bankmachine3_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine3_trascon_valid) begin + main_litedramcore_bankmachine3_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine3_trascon_ready <= 1'd1; + main_litedramcore_bankmachine3_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine3_trascon_ready <= 1'd0; + main_litedramcore_bankmachine3_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); - if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin - litedramcore_bankmachine3_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_trascon_count <= (main_litedramcore_bankmachine3_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine3_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine3_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state; - if (litedramcore_bankmachine4_row_close) begin - litedramcore_bankmachine4_row_opened <= 1'd0; + builder_bankmachine3_state <= builder_bankmachine3_next_state; + if (main_litedramcore_bankmachine4_row_close) begin + main_litedramcore_bankmachine4_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine4_row_open) begin - litedramcore_bankmachine4_row_opened <= 1'd1; - litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine4_row_open) begin + main_litedramcore_bankmachine4_row_opened <= 1'd1; + main_litedramcore_bankmachine4_row <= main_litedramcore_bankmachine4_source_source_payload_addr[21:7]; end end - if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin - litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1); + if (((main_litedramcore_bankmachine4_syncfifo4_we & main_litedramcore_bankmachine4_syncfifo4_writable) & (~main_litedramcore_bankmachine4_replace))) begin + main_litedramcore_bankmachine4_produce <= (main_litedramcore_bankmachine4_produce + 1'd1); end - if (litedramcore_bankmachine4_do_read) begin - litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1); + if (main_litedramcore_bankmachine4_do_read) begin + main_litedramcore_bankmachine4_consume <= (main_litedramcore_bankmachine4_consume + 1'd1); end - if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin - if ((~litedramcore_bankmachine4_do_read)) begin - litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1); + if (((main_litedramcore_bankmachine4_syncfifo4_we & main_litedramcore_bankmachine4_syncfifo4_writable) & (~main_litedramcore_bankmachine4_replace))) begin + if ((~main_litedramcore_bankmachine4_do_read)) begin + main_litedramcore_bankmachine4_level <= (main_litedramcore_bankmachine4_level + 1'd1); end end else begin - if (litedramcore_bankmachine4_do_read) begin - litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1); + if (main_litedramcore_bankmachine4_do_read) begin + main_litedramcore_bankmachine4_level <= (main_litedramcore_bankmachine4_level - 1'd1); end end - if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin - litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid; - litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first; - litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last; - litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we; - litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine4_pipe_valid_source_valid) | main_litedramcore_bankmachine4_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine4_pipe_valid_source_valid <= main_litedramcore_bankmachine4_pipe_valid_sink_valid; + main_litedramcore_bankmachine4_pipe_valid_source_first <= main_litedramcore_bankmachine4_pipe_valid_sink_first; + main_litedramcore_bankmachine4_pipe_valid_source_last <= main_litedramcore_bankmachine4_pipe_valid_sink_last; + main_litedramcore_bankmachine4_pipe_valid_source_payload_we <= main_litedramcore_bankmachine4_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine4_twtpcon_valid) begin - litedramcore_bankmachine4_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine4_twtpcon_valid) begin + main_litedramcore_bankmachine4_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine4_twtpcon_ready)) begin - litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_twtpcon_ready)) begin + main_litedramcore_bankmachine4_twtpcon_count <= (main_litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine4_trccon_valid) begin - litedramcore_bankmachine4_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine4_trccon_valid) begin + main_litedramcore_bankmachine4_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine4_trccon_ready <= 1'd1; + main_litedramcore_bankmachine4_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine4_trccon_ready <= 1'd0; + main_litedramcore_bankmachine4_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine4_trccon_ready)) begin - litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); - if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin - litedramcore_bankmachine4_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_trccon_ready)) begin + main_litedramcore_bankmachine4_trccon_count <= (main_litedramcore_bankmachine4_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine4_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine4_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine4_trascon_valid) begin - litedramcore_bankmachine4_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine4_trascon_valid) begin + main_litedramcore_bankmachine4_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine4_trascon_ready <= 1'd1; + main_litedramcore_bankmachine4_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine4_trascon_ready <= 1'd0; + main_litedramcore_bankmachine4_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); - if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin - litedramcore_bankmachine4_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_trascon_count <= (main_litedramcore_bankmachine4_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine4_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine4_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state; - if (litedramcore_bankmachine5_row_close) begin - litedramcore_bankmachine5_row_opened <= 1'd0; + builder_bankmachine4_state <= builder_bankmachine4_next_state; + if (main_litedramcore_bankmachine5_row_close) begin + main_litedramcore_bankmachine5_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine5_row_open) begin - litedramcore_bankmachine5_row_opened <= 1'd1; - litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine5_row_open) begin + main_litedramcore_bankmachine5_row_opened <= 1'd1; + main_litedramcore_bankmachine5_row <= main_litedramcore_bankmachine5_source_source_payload_addr[21:7]; end end - if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin - litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1); + if (((main_litedramcore_bankmachine5_syncfifo5_we & main_litedramcore_bankmachine5_syncfifo5_writable) & (~main_litedramcore_bankmachine5_replace))) begin + main_litedramcore_bankmachine5_produce <= (main_litedramcore_bankmachine5_produce + 1'd1); end - if (litedramcore_bankmachine5_do_read) begin - litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1); + if (main_litedramcore_bankmachine5_do_read) begin + main_litedramcore_bankmachine5_consume <= (main_litedramcore_bankmachine5_consume + 1'd1); end - if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin - if ((~litedramcore_bankmachine5_do_read)) begin - litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1); + if (((main_litedramcore_bankmachine5_syncfifo5_we & main_litedramcore_bankmachine5_syncfifo5_writable) & (~main_litedramcore_bankmachine5_replace))) begin + if ((~main_litedramcore_bankmachine5_do_read)) begin + main_litedramcore_bankmachine5_level <= (main_litedramcore_bankmachine5_level + 1'd1); end end else begin - if (litedramcore_bankmachine5_do_read) begin - litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1); + if (main_litedramcore_bankmachine5_do_read) begin + main_litedramcore_bankmachine5_level <= (main_litedramcore_bankmachine5_level - 1'd1); end end - if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin - litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid; - litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first; - litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last; - litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we; - litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine5_pipe_valid_source_valid) | main_litedramcore_bankmachine5_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine5_pipe_valid_source_valid <= main_litedramcore_bankmachine5_pipe_valid_sink_valid; + main_litedramcore_bankmachine5_pipe_valid_source_first <= main_litedramcore_bankmachine5_pipe_valid_sink_first; + main_litedramcore_bankmachine5_pipe_valid_source_last <= main_litedramcore_bankmachine5_pipe_valid_sink_last; + main_litedramcore_bankmachine5_pipe_valid_source_payload_we <= main_litedramcore_bankmachine5_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine5_twtpcon_valid) begin - litedramcore_bankmachine5_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine5_twtpcon_valid) begin + main_litedramcore_bankmachine5_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine5_twtpcon_ready)) begin - litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_twtpcon_ready)) begin + main_litedramcore_bankmachine5_twtpcon_count <= (main_litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine5_trccon_valid) begin - litedramcore_bankmachine5_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine5_trccon_valid) begin + main_litedramcore_bankmachine5_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine5_trccon_ready <= 1'd1; + main_litedramcore_bankmachine5_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine5_trccon_ready <= 1'd0; + main_litedramcore_bankmachine5_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine5_trccon_ready)) begin - litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); - if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin - litedramcore_bankmachine5_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_trccon_ready)) begin + main_litedramcore_bankmachine5_trccon_count <= (main_litedramcore_bankmachine5_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine5_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine5_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine5_trascon_valid) begin - litedramcore_bankmachine5_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine5_trascon_valid) begin + main_litedramcore_bankmachine5_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine5_trascon_ready <= 1'd1; + main_litedramcore_bankmachine5_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine5_trascon_ready <= 1'd0; + main_litedramcore_bankmachine5_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); - if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin - litedramcore_bankmachine5_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_trascon_count <= (main_litedramcore_bankmachine5_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine5_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine5_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state; - if (litedramcore_bankmachine6_row_close) begin - litedramcore_bankmachine6_row_opened <= 1'd0; + builder_bankmachine5_state <= builder_bankmachine5_next_state; + if (main_litedramcore_bankmachine6_row_close) begin + main_litedramcore_bankmachine6_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine6_row_open) begin - litedramcore_bankmachine6_row_opened <= 1'd1; - litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine6_row_open) begin + main_litedramcore_bankmachine6_row_opened <= 1'd1; + main_litedramcore_bankmachine6_row <= main_litedramcore_bankmachine6_source_source_payload_addr[21:7]; end end - if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin - litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1); + if (((main_litedramcore_bankmachine6_syncfifo6_we & main_litedramcore_bankmachine6_syncfifo6_writable) & (~main_litedramcore_bankmachine6_replace))) begin + main_litedramcore_bankmachine6_produce <= (main_litedramcore_bankmachine6_produce + 1'd1); end - if (litedramcore_bankmachine6_do_read) begin - litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1); + if (main_litedramcore_bankmachine6_do_read) begin + main_litedramcore_bankmachine6_consume <= (main_litedramcore_bankmachine6_consume + 1'd1); end - if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin - if ((~litedramcore_bankmachine6_do_read)) begin - litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1); + if (((main_litedramcore_bankmachine6_syncfifo6_we & main_litedramcore_bankmachine6_syncfifo6_writable) & (~main_litedramcore_bankmachine6_replace))) begin + if ((~main_litedramcore_bankmachine6_do_read)) begin + main_litedramcore_bankmachine6_level <= (main_litedramcore_bankmachine6_level + 1'd1); end end else begin - if (litedramcore_bankmachine6_do_read) begin - litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1); + if (main_litedramcore_bankmachine6_do_read) begin + main_litedramcore_bankmachine6_level <= (main_litedramcore_bankmachine6_level - 1'd1); end end - if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin - litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid; - litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first; - litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last; - litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we; - litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine6_pipe_valid_source_valid) | main_litedramcore_bankmachine6_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine6_pipe_valid_source_valid <= main_litedramcore_bankmachine6_pipe_valid_sink_valid; + main_litedramcore_bankmachine6_pipe_valid_source_first <= main_litedramcore_bankmachine6_pipe_valid_sink_first; + main_litedramcore_bankmachine6_pipe_valid_source_last <= main_litedramcore_bankmachine6_pipe_valid_sink_last; + main_litedramcore_bankmachine6_pipe_valid_source_payload_we <= main_litedramcore_bankmachine6_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine6_twtpcon_valid) begin - litedramcore_bankmachine6_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine6_twtpcon_valid) begin + main_litedramcore_bankmachine6_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine6_twtpcon_ready)) begin - litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_twtpcon_ready)) begin + main_litedramcore_bankmachine6_twtpcon_count <= (main_litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine6_trccon_valid) begin - litedramcore_bankmachine6_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine6_trccon_valid) begin + main_litedramcore_bankmachine6_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine6_trccon_ready <= 1'd1; + main_litedramcore_bankmachine6_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine6_trccon_ready <= 1'd0; + main_litedramcore_bankmachine6_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine6_trccon_ready)) begin - litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); - if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin - litedramcore_bankmachine6_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_trccon_ready)) begin + main_litedramcore_bankmachine6_trccon_count <= (main_litedramcore_bankmachine6_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine6_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine6_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine6_trascon_valid) begin - litedramcore_bankmachine6_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine6_trascon_valid) begin + main_litedramcore_bankmachine6_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine6_trascon_ready <= 1'd1; + main_litedramcore_bankmachine6_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine6_trascon_ready <= 1'd0; + main_litedramcore_bankmachine6_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); - if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin - litedramcore_bankmachine6_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_trascon_count <= (main_litedramcore_bankmachine6_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine6_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine6_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state; - if (litedramcore_bankmachine7_row_close) begin - litedramcore_bankmachine7_row_opened <= 1'd0; + builder_bankmachine6_state <= builder_bankmachine6_next_state; + if (main_litedramcore_bankmachine7_row_close) begin + main_litedramcore_bankmachine7_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine7_row_open) begin - litedramcore_bankmachine7_row_opened <= 1'd1; - litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[21:7]; + if (main_litedramcore_bankmachine7_row_open) begin + main_litedramcore_bankmachine7_row_opened <= 1'd1; + main_litedramcore_bankmachine7_row <= main_litedramcore_bankmachine7_source_source_payload_addr[21:7]; end end - if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin - litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1); + if (((main_litedramcore_bankmachine7_syncfifo7_we & main_litedramcore_bankmachine7_syncfifo7_writable) & (~main_litedramcore_bankmachine7_replace))) begin + main_litedramcore_bankmachine7_produce <= (main_litedramcore_bankmachine7_produce + 1'd1); end - if (litedramcore_bankmachine7_do_read) begin - litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1); + if (main_litedramcore_bankmachine7_do_read) begin + main_litedramcore_bankmachine7_consume <= (main_litedramcore_bankmachine7_consume + 1'd1); end - if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin - if ((~litedramcore_bankmachine7_do_read)) begin - litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1); + if (((main_litedramcore_bankmachine7_syncfifo7_we & main_litedramcore_bankmachine7_syncfifo7_writable) & (~main_litedramcore_bankmachine7_replace))) begin + if ((~main_litedramcore_bankmachine7_do_read)) begin + main_litedramcore_bankmachine7_level <= (main_litedramcore_bankmachine7_level + 1'd1); end end else begin - if (litedramcore_bankmachine7_do_read) begin - litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1); + if (main_litedramcore_bankmachine7_do_read) begin + main_litedramcore_bankmachine7_level <= (main_litedramcore_bankmachine7_level - 1'd1); end end - if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin - litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid; - litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first; - litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last; - litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we; - litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine7_pipe_valid_source_valid) | main_litedramcore_bankmachine7_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine7_pipe_valid_source_valid <= main_litedramcore_bankmachine7_pipe_valid_sink_valid; + main_litedramcore_bankmachine7_pipe_valid_source_first <= main_litedramcore_bankmachine7_pipe_valid_sink_first; + main_litedramcore_bankmachine7_pipe_valid_source_last <= main_litedramcore_bankmachine7_pipe_valid_sink_last; + main_litedramcore_bankmachine7_pipe_valid_source_payload_we <= main_litedramcore_bankmachine7_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine7_twtpcon_valid) begin - litedramcore_bankmachine7_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine7_twtpcon_valid) begin + main_litedramcore_bankmachine7_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine7_twtpcon_ready)) begin - litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_twtpcon_ready)) begin + main_litedramcore_bankmachine7_twtpcon_count <= (main_litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine7_trccon_valid) begin - litedramcore_bankmachine7_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine7_trccon_valid) begin + main_litedramcore_bankmachine7_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine7_trccon_ready <= 1'd1; + main_litedramcore_bankmachine7_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine7_trccon_ready <= 1'd0; + main_litedramcore_bankmachine7_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine7_trccon_ready)) begin - litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); - if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin - litedramcore_bankmachine7_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_trccon_ready)) begin + main_litedramcore_bankmachine7_trccon_count <= (main_litedramcore_bankmachine7_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine7_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine7_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine7_trascon_valid) begin - litedramcore_bankmachine7_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine7_trascon_valid) begin + main_litedramcore_bankmachine7_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine7_trascon_ready <= 1'd1; + main_litedramcore_bankmachine7_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine7_trascon_ready <= 1'd0; + main_litedramcore_bankmachine7_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); - if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin - litedramcore_bankmachine7_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_trascon_count <= (main_litedramcore_bankmachine7_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine7_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine7_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state; - if ((~litedramcore_en0)) begin - litedramcore_time0 <= 5'd31; + builder_bankmachine7_state <= builder_bankmachine7_next_state; + if ((~main_litedramcore_en0)) begin + main_litedramcore_time0 <= 5'd31; end else begin - if ((~litedramcore_max_time0)) begin - litedramcore_time0 <= (litedramcore_time0 - 1'd1); + if ((~main_litedramcore_max_time0)) begin + main_litedramcore_time0 <= (main_litedramcore_time0 - 1'd1); end end - if ((~litedramcore_en1)) begin - litedramcore_time1 <= 4'd15; + if ((~main_litedramcore_en1)) begin + main_litedramcore_time1 <= 4'd15; end else begin - if ((~litedramcore_max_time1)) begin - litedramcore_time1 <= (litedramcore_time1 - 1'd1); + if ((~main_litedramcore_max_time1)) begin + main_litedramcore_time1 <= (main_litedramcore_time1 - 1'd1); end end - if (litedramcore_choose_cmd_ce) begin - case (litedramcore_choose_cmd_grant) + if (main_litedramcore_choose_cmd_ce) begin + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end end end @@ -13030,26 +13446,26 @@ always @(posedge sys_clk) begin end end 1'd1: begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end end end @@ -13059,26 +13475,26 @@ always @(posedge sys_clk) begin end end 2'd2: begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end end end @@ -13088,26 +13504,26 @@ always @(posedge sys_clk) begin end end 2'd3: begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end end end @@ -13117,26 +13533,26 @@ always @(posedge sys_clk) begin end end 3'd4: begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end end end @@ -13146,26 +13562,26 @@ always @(posedge sys_clk) begin end end 3'd5: begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end end end @@ -13175,26 +13591,26 @@ always @(posedge sys_clk) begin end end 3'd6: begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end end end @@ -13204,26 +13620,26 @@ always @(posedge sys_clk) begin end end 3'd7: begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end end end @@ -13234,29 +13650,29 @@ always @(posedge sys_clk) begin end endcase end - if (litedramcore_choose_req_ce) begin - case (litedramcore_choose_req_grant) + if (main_litedramcore_choose_req_ce) begin + case (main_litedramcore_choose_req_grant) 1'd0: begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end end end @@ -13266,26 +13682,26 @@ always @(posedge sys_clk) begin end end 1'd1: begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end end end @@ -13295,26 +13711,26 @@ always @(posedge sys_clk) begin end end 2'd2: begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end end end @@ -13324,26 +13740,26 @@ always @(posedge sys_clk) begin end end 2'd3: begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end end end @@ -13353,26 +13769,26 @@ always @(posedge sys_clk) begin end end 3'd4: begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end end end @@ -13382,26 +13798,26 @@ always @(posedge sys_clk) begin end end 3'd5: begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end end end @@ -13411,26 +13827,26 @@ always @(posedge sys_clk) begin end end 3'd6: begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end end end @@ -13440,26 +13856,26 @@ always @(posedge sys_clk) begin end end 3'd7: begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end end end @@ -13470,644 +13886,644 @@ always @(posedge sys_clk) begin end endcase end - litedramcore_dfi_p0_cs_n <= 1'd0; - litedramcore_dfi_p0_bank <= array_muxed0; - litedramcore_dfi_p0_address <= array_muxed1; - litedramcore_dfi_p0_cas_n <= (~array_muxed2); - litedramcore_dfi_p0_ras_n <= (~array_muxed3); - litedramcore_dfi_p0_we_n <= (~array_muxed4); - litedramcore_dfi_p0_rddata_en <= array_muxed5; - litedramcore_dfi_p0_wrdata_en <= array_muxed6; - litedramcore_dfi_p1_cs_n <= 1'd0; - litedramcore_dfi_p1_bank <= array_muxed7; - litedramcore_dfi_p1_address <= array_muxed8; - litedramcore_dfi_p1_cas_n <= (~array_muxed9); - litedramcore_dfi_p1_ras_n <= (~array_muxed10); - litedramcore_dfi_p1_we_n <= (~array_muxed11); - litedramcore_dfi_p1_rddata_en <= array_muxed12; - litedramcore_dfi_p1_wrdata_en <= array_muxed13; - litedramcore_dfi_p2_cs_n <= 1'd0; - litedramcore_dfi_p2_bank <= array_muxed14; - litedramcore_dfi_p2_address <= array_muxed15; - litedramcore_dfi_p2_cas_n <= (~array_muxed16); - litedramcore_dfi_p2_ras_n <= (~array_muxed17); - litedramcore_dfi_p2_we_n <= (~array_muxed18); - litedramcore_dfi_p2_rddata_en <= array_muxed19; - litedramcore_dfi_p2_wrdata_en <= array_muxed20; - litedramcore_dfi_p3_cs_n <= 1'd0; - litedramcore_dfi_p3_bank <= array_muxed21; - litedramcore_dfi_p3_address <= array_muxed22; - litedramcore_dfi_p3_cas_n <= (~array_muxed23); - litedramcore_dfi_p3_ras_n <= (~array_muxed24); - litedramcore_dfi_p3_we_n <= (~array_muxed25); - litedramcore_dfi_p3_rddata_en <= array_muxed26; - litedramcore_dfi_p3_wrdata_en <= array_muxed27; - if (litedramcore_trrdcon_valid) begin - litedramcore_trrdcon_count <= 1'd1; + main_litedramcore_dfi_p0_cs_n <= 1'd0; + main_litedramcore_dfi_p0_bank <= builder_self0; + main_litedramcore_dfi_p0_address <= builder_self1; + main_litedramcore_dfi_p0_cas_n <= (~builder_self2); + main_litedramcore_dfi_p0_ras_n <= (~builder_self3); + main_litedramcore_dfi_p0_we_n <= (~builder_self4); + main_litedramcore_dfi_p0_rddata_en <= builder_self5; + main_litedramcore_dfi_p0_wrdata_en <= builder_self6; + main_litedramcore_dfi_p1_cs_n <= 1'd0; + main_litedramcore_dfi_p1_bank <= builder_self7; + main_litedramcore_dfi_p1_address <= builder_self8; + main_litedramcore_dfi_p1_cas_n <= (~builder_self9); + main_litedramcore_dfi_p1_ras_n <= (~builder_self10); + main_litedramcore_dfi_p1_we_n <= (~builder_self11); + main_litedramcore_dfi_p1_rddata_en <= builder_self12; + main_litedramcore_dfi_p1_wrdata_en <= builder_self13; + main_litedramcore_dfi_p2_cs_n <= 1'd0; + main_litedramcore_dfi_p2_bank <= builder_self14; + main_litedramcore_dfi_p2_address <= builder_self15; + main_litedramcore_dfi_p2_cas_n <= (~builder_self16); + main_litedramcore_dfi_p2_ras_n <= (~builder_self17); + main_litedramcore_dfi_p2_we_n <= (~builder_self18); + main_litedramcore_dfi_p2_rddata_en <= builder_self19; + main_litedramcore_dfi_p2_wrdata_en <= builder_self20; + main_litedramcore_dfi_p3_cs_n <= 1'd0; + main_litedramcore_dfi_p3_bank <= builder_self21; + main_litedramcore_dfi_p3_address <= builder_self22; + main_litedramcore_dfi_p3_cas_n <= (~builder_self23); + main_litedramcore_dfi_p3_ras_n <= (~builder_self24); + main_litedramcore_dfi_p3_we_n <= (~builder_self25); + main_litedramcore_dfi_p3_rddata_en <= builder_self26; + main_litedramcore_dfi_p3_wrdata_en <= builder_self27; + if (main_litedramcore_trrdcon_valid) begin + main_litedramcore_trrdcon_count <= 1'd1; if (1'd0) begin - litedramcore_trrdcon_ready <= 1'd1; + main_litedramcore_trrdcon_ready <= 1'd1; end else begin - litedramcore_trrdcon_ready <= 1'd0; + main_litedramcore_trrdcon_ready <= 1'd0; end end else begin - if ((~litedramcore_trrdcon_ready)) begin - litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); - if ((litedramcore_trrdcon_count == 1'd1)) begin - litedramcore_trrdcon_ready <= 1'd1; + if ((~main_litedramcore_trrdcon_ready)) begin + main_litedramcore_trrdcon_count <= (main_litedramcore_trrdcon_count - 1'd1); + if ((main_litedramcore_trrdcon_count == 1'd1)) begin + main_litedramcore_trrdcon_ready <= 1'd1; end end end - litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; - if ((litedramcore_tfawcon_count < 3'd4)) begin - if ((litedramcore_tfawcon_count == 2'd3)) begin - litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); + main_litedramcore_tfawcon_window <= {main_litedramcore_tfawcon_window, main_litedramcore_tfawcon_valid}; + if ((main_litedramcore_tfawcon_count < 3'd4)) begin + if ((main_litedramcore_tfawcon_count == 2'd3)) begin + main_litedramcore_tfawcon_ready <= (~main_litedramcore_tfawcon_valid); end else begin - litedramcore_tfawcon_ready <= 1'd1; + main_litedramcore_tfawcon_ready <= 1'd1; end end - if (litedramcore_tccdcon_valid) begin - litedramcore_tccdcon_count <= 1'd0; + if (main_litedramcore_tccdcon_valid) begin + main_litedramcore_tccdcon_count <= 1'd0; if (1'd1) begin - litedramcore_tccdcon_ready <= 1'd1; + main_litedramcore_tccdcon_ready <= 1'd1; end else begin - litedramcore_tccdcon_ready <= 1'd0; + main_litedramcore_tccdcon_ready <= 1'd0; end end else begin - if ((~litedramcore_tccdcon_ready)) begin - litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); - if ((litedramcore_tccdcon_count == 1'd1)) begin - litedramcore_tccdcon_ready <= 1'd1; + if ((~main_litedramcore_tccdcon_ready)) begin + main_litedramcore_tccdcon_count <= (main_litedramcore_tccdcon_count - 1'd1); + if ((main_litedramcore_tccdcon_count == 1'd1)) begin + main_litedramcore_tccdcon_ready <= 1'd1; end end end - if (litedramcore_twtrcon_valid) begin - litedramcore_twtrcon_count <= 3'd4; + if (main_litedramcore_twtrcon_valid) begin + main_litedramcore_twtrcon_count <= 3'd4; if (1'd0) begin - litedramcore_twtrcon_ready <= 1'd1; + main_litedramcore_twtrcon_ready <= 1'd1; end else begin - litedramcore_twtrcon_ready <= 1'd0; + main_litedramcore_twtrcon_ready <= 1'd0; end end else begin - if ((~litedramcore_twtrcon_ready)) begin - litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); - if ((litedramcore_twtrcon_count == 1'd1)) begin - litedramcore_twtrcon_ready <= 1'd1; - end - end - end - litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state; - litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); - litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0; - litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); - litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0; - litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1; - litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2; - litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3; - litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4; - litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5; - litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6; - litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7; - litedramcore_state <= litedramcore_next_state; - if (litedramcore_dat_w_next_value_ce0) begin - litedramcore_dat_w <= litedramcore_dat_w_next_value0; - end - if (litedramcore_adr_next_value_ce1) begin - litedramcore_adr <= litedramcore_adr_next_value1; - end - if (litedramcore_we_next_value_ce2) begin - litedramcore_we <= litedramcore_we_next_value2; - end - interface0_bank_bus_dat_r <= 1'd0; - if (csrbank0_sel) begin - case (interface0_bank_bus_adr[8:0]) + if ((~main_litedramcore_twtrcon_ready)) begin + main_litedramcore_twtrcon_count <= (main_litedramcore_twtrcon_count - 1'd1); + if ((main_litedramcore_twtrcon_count == 1'd1)) begin + main_litedramcore_twtrcon_ready <= 1'd1; + end + end + end + builder_multiplexer_state <= builder_multiplexer_next_state; + builder_new_master_wdata_ready0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_wdata_ready)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_wdata_ready)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_wdata_ready)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_wdata_ready)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_wdata_ready)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_wdata_ready)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_wdata_ready)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_wdata_ready)); + builder_new_master_wdata_ready1 <= builder_new_master_wdata_ready0; + builder_new_master_rdata_valid0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_rdata_valid)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_rdata_valid)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_rdata_valid)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_rdata_valid)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_rdata_valid)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_rdata_valid)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_rdata_valid)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_rdata_valid)); + builder_new_master_rdata_valid1 <= builder_new_master_rdata_valid0; + builder_new_master_rdata_valid2 <= builder_new_master_rdata_valid1; + builder_new_master_rdata_valid3 <= builder_new_master_rdata_valid2; + builder_new_master_rdata_valid4 <= builder_new_master_rdata_valid3; + builder_new_master_rdata_valid5 <= builder_new_master_rdata_valid4; + builder_new_master_rdata_valid6 <= builder_new_master_rdata_valid5; + builder_new_master_rdata_valid7 <= builder_new_master_rdata_valid6; + builder_new_master_rdata_valid8 <= builder_new_master_rdata_valid7; + builder_state <= builder_next_state; + if (builder_interface1_dat_w_next_value_ce0) begin + builder_interface1_dat_w <= builder_interface1_dat_w_next_value0; + end + if (builder_interface1_adr_next_value_ce1) begin + builder_interface1_adr <= builder_interface1_adr_next_value1; + end + if (builder_interface1_we_next_value_ce2) begin + builder_interface1_we <= builder_interface1_we_next_value2; + end + builder_interface0_bank_bus_dat_r <= 1'd0; + if (builder_csrbank0_sel) begin + case (builder_interface0_bank_bus_adr[8:0]) 1'd0: begin - interface0_bank_bus_dat_r <= csrbank0_init_done0_w; + builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_done0_w; end 1'd1: begin - interface0_bank_bus_dat_r <= csrbank0_init_error0_w; + builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_error0_w; end endcase end - if (csrbank0_init_done0_re) begin - init_done_storage <= csrbank0_init_done0_r; + if (builder_csrbank0_init_done0_re) begin + main_init_done_storage <= builder_csrbank0_init_done0_r; end - init_done_re <= csrbank0_init_done0_re; - if (csrbank0_init_error0_re) begin - init_error_storage <= csrbank0_init_error0_r; + main_init_done_re <= builder_csrbank0_init_done0_re; + if (builder_csrbank0_init_error0_re) begin + main_init_error_storage <= builder_csrbank0_init_error0_r; end - init_error_re <= csrbank0_init_error0_re; - interface1_bank_bus_dat_r <= 1'd0; - if (csrbank1_sel) begin - case (interface1_bank_bus_adr[8:0]) + main_init_error_re <= builder_csrbank0_init_error0_re; + builder_interface1_bank_bus_dat_r <= 1'd0; + if (builder_csrbank1_sel) begin + case (builder_interface1_bank_bus_adr[8:0]) 1'd0: begin - interface1_bank_bus_dat_r <= csrbank1_rst0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rst0_w; end 1'd1: begin - interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_dly_sel0_w; end 2'd2: begin - interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_half_sys8x_taps0_w; end 2'd3: begin - interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_wlevel_en0_w; end 3'd4: begin - interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wlevel_strobe_w; end 3'd5: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_rst_w; end 3'd6: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_inc_w; end 3'd7: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_rst_w; end 4'd8: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_w; end 4'd9: begin - interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_rst_w; end 4'd10: begin - interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_w; end 4'd11: begin - interface1_bank_bus_dat_r <= csrbank1_rdphase0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rdphase0_w; end 4'd12: begin - interface1_bank_bus_dat_r <= csrbank1_wrphase0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_wrphase0_w; end endcase end - if (csrbank1_rst0_re) begin - a7ddrphy_rst_storage <= csrbank1_rst0_r; + if (builder_csrbank1_rst0_re) begin + main_a7ddrphy_rst_storage <= builder_csrbank1_rst0_r; end - a7ddrphy_rst_re <= csrbank1_rst0_re; - if (csrbank1_dly_sel0_re) begin - a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r; + main_a7ddrphy_rst_re <= builder_csrbank1_rst0_re; + if (builder_csrbank1_dly_sel0_re) begin + main_a7ddrphy_dly_sel_storage[1:0] <= builder_csrbank1_dly_sel0_r; end - a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; - if (csrbank1_half_sys8x_taps0_re) begin - a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r; + main_a7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re; + if (builder_csrbank1_half_sys8x_taps0_re) begin + main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r; end - a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re; - if (csrbank1_wlevel_en0_re) begin - a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r; + main_a7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re; + if (builder_csrbank1_wlevel_en0_re) begin + main_a7ddrphy_wlevel_en_storage <= builder_csrbank1_wlevel_en0_r; end - a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re; - if (csrbank1_rdphase0_re) begin - a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r; + main_a7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re; + if (builder_csrbank1_rdphase0_re) begin + main_a7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r; end - a7ddrphy_rdphase_re <= csrbank1_rdphase0_re; - if (csrbank1_wrphase0_re) begin - a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r; + main_a7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re; + if (builder_csrbank1_wrphase0_re) begin + main_a7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r; end - a7ddrphy_wrphase_re <= csrbank1_wrphase0_re; - interface2_bank_bus_dat_r <= 1'd0; - if (csrbank2_sel) begin - case (interface2_bank_bus_adr[8:0]) + main_a7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re; + builder_interface2_bank_bus_dat_r <= 1'd0; + if (builder_csrbank2_sel) begin + case (builder_interface2_bank_bus_adr[8:0]) 1'd0: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_control0_w; end 1'd1: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_command0_w; end 2'd2: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w; end 3'd4: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w; end 3'd5: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w; end 3'd6: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata_w; end 3'd7: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w; end 4'd8: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w; end 4'd9: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w; end 4'd10: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w; end 4'd11: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w; end 4'd12: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata_w; end 4'd13: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w; end 4'd14: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w; end 4'd15: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w; end 5'd16: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w; end 5'd17: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w; end 5'd18: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata_w; end 5'd19: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w; end 5'd20: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w; end 5'd21: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w; end 5'd22: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w; end 5'd23: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w; end 5'd24: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata_w; end endcase end - if (csrbank2_dfii_control0_re) begin - litedramcore_storage[3:0] <= csrbank2_dfii_control0_r; + if (builder_csrbank2_dfii_control0_re) begin + main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r; end - litedramcore_re <= csrbank2_dfii_control0_re; - if (csrbank2_dfii_pi0_command0_re) begin - litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; + main_litedramcore_re <= builder_csrbank2_dfii_control0_re; + if (builder_csrbank2_dfii_pi0_command0_re) begin + main_litedramcore_phaseinjector0_command_storage[7:0] <= builder_csrbank2_dfii_pi0_command0_r; end - litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; - if (csrbank2_dfii_pi0_address0_re) begin - litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r; + main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re; + if (builder_csrbank2_dfii_pi0_address0_re) begin + main_litedramcore_phaseinjector0_address_storage[14:0] <= builder_csrbank2_dfii_pi0_address0_r; end - litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; - if (csrbank2_dfii_pi0_baddress0_re) begin - litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; + main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re; + if (builder_csrbank2_dfii_pi0_baddress0_re) begin + main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r; end - litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; - if (csrbank2_dfii_pi0_wrdata0_re) begin - litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; + main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re; + if (builder_csrbank2_dfii_pi0_wrdata0_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r; end - litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; - litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re; - if (csrbank2_dfii_pi1_command0_re) begin - litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; + main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re; + main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re; + if (builder_csrbank2_dfii_pi1_command0_re) begin + main_litedramcore_phaseinjector1_command_storage[7:0] <= builder_csrbank2_dfii_pi1_command0_r; end - litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; - if (csrbank2_dfii_pi1_address0_re) begin - litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r; + main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re; + if (builder_csrbank2_dfii_pi1_address0_re) begin + main_litedramcore_phaseinjector1_address_storage[14:0] <= builder_csrbank2_dfii_pi1_address0_r; end - litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; - if (csrbank2_dfii_pi1_baddress0_re) begin - litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; + main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re; + if (builder_csrbank2_dfii_pi1_baddress0_re) begin + main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r; end - litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; - if (csrbank2_dfii_pi1_wrdata0_re) begin - litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; + main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re; + if (builder_csrbank2_dfii_pi1_wrdata0_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r; end - litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; - litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re; - if (csrbank2_dfii_pi2_command0_re) begin - litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; + main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re; + main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re; + if (builder_csrbank2_dfii_pi2_command0_re) begin + main_litedramcore_phaseinjector2_command_storage[7:0] <= builder_csrbank2_dfii_pi2_command0_r; end - litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; - if (csrbank2_dfii_pi2_address0_re) begin - litedramcore_phaseinjector2_address_storage[14:0] <= csrbank2_dfii_pi2_address0_r; + main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re; + if (builder_csrbank2_dfii_pi2_address0_re) begin + main_litedramcore_phaseinjector2_address_storage[14:0] <= builder_csrbank2_dfii_pi2_address0_r; end - litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; - if (csrbank2_dfii_pi2_baddress0_re) begin - litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; + main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re; + if (builder_csrbank2_dfii_pi2_baddress0_re) begin + main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r; end - litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; - if (csrbank2_dfii_pi2_wrdata0_re) begin - litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r; + main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re; + if (builder_csrbank2_dfii_pi2_wrdata0_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r; end - litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; - litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re; - if (csrbank2_dfii_pi3_command0_re) begin - litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; + main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re; + main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re; + if (builder_csrbank2_dfii_pi3_command0_re) begin + main_litedramcore_phaseinjector3_command_storage[7:0] <= builder_csrbank2_dfii_pi3_command0_r; end - litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; - if (csrbank2_dfii_pi3_address0_re) begin - litedramcore_phaseinjector3_address_storage[14:0] <= csrbank2_dfii_pi3_address0_r; + main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re; + if (builder_csrbank2_dfii_pi3_address0_re) begin + main_litedramcore_phaseinjector3_address_storage[14:0] <= builder_csrbank2_dfii_pi3_address0_r; end - litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; - if (csrbank2_dfii_pi3_baddress0_re) begin - litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; + main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re; + if (builder_csrbank2_dfii_pi3_baddress0_re) begin + main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r; end - litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; - if (csrbank2_dfii_pi3_wrdata0_re) begin - litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r; + main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re; + if (builder_csrbank2_dfii_pi3_wrdata0_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r; end - litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; - litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re; + main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re; + main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re; if (sys_rst) begin - a7ddrphy_rst_storage <= 1'd0; - a7ddrphy_rst_re <= 1'd0; - a7ddrphy_dly_sel_storage <= 2'd0; - a7ddrphy_dly_sel_re <= 1'd0; - a7ddrphy_half_sys8x_taps_storage <= 5'd8; - a7ddrphy_half_sys8x_taps_re <= 1'd0; - a7ddrphy_wlevel_en_storage <= 1'd0; - a7ddrphy_wlevel_en_re <= 1'd0; - a7ddrphy_rdphase_storage <= 2'd2; - a7ddrphy_rdphase_re <= 1'd0; - a7ddrphy_wrphase_storage <= 2'd3; - a7ddrphy_wrphase_re <= 1'd0; - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; - a7ddrphy_dqspattern_o1 <= 8'd0; - a7ddrphy_bitslip0_value0 <= 3'd7; - a7ddrphy_bitslip1_value0 <= 3'd7; - a7ddrphy_bitslip0_value1 <= 3'd7; - a7ddrphy_bitslip1_value1 <= 3'd7; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; - a7ddrphy_bitslip0_value2 <= 3'd7; - a7ddrphy_bitslip0_value3 <= 3'd7; - a7ddrphy_bitslip1_value2 <= 3'd7; - a7ddrphy_bitslip1_value3 <= 3'd7; - a7ddrphy_bitslip2_value0 <= 3'd7; - a7ddrphy_bitslip2_value1 <= 3'd7; - a7ddrphy_bitslip3_value0 <= 3'd7; - a7ddrphy_bitslip3_value1 <= 3'd7; - a7ddrphy_bitslip4_value0 <= 3'd7; - a7ddrphy_bitslip4_value1 <= 3'd7; - a7ddrphy_bitslip5_value0 <= 3'd7; - a7ddrphy_bitslip5_value1 <= 3'd7; - a7ddrphy_bitslip6_value0 <= 3'd7; - a7ddrphy_bitslip6_value1 <= 3'd7; - a7ddrphy_bitslip7_value0 <= 3'd7; - a7ddrphy_bitslip7_value1 <= 3'd7; - a7ddrphy_bitslip8_value0 <= 3'd7; - a7ddrphy_bitslip8_value1 <= 3'd7; - a7ddrphy_bitslip9_value0 <= 3'd7; - a7ddrphy_bitslip9_value1 <= 3'd7; - a7ddrphy_bitslip10_value0 <= 3'd7; - a7ddrphy_bitslip10_value1 <= 3'd7; - a7ddrphy_bitslip11_value0 <= 3'd7; - a7ddrphy_bitslip11_value1 <= 3'd7; - a7ddrphy_bitslip12_value0 <= 3'd7; - a7ddrphy_bitslip12_value1 <= 3'd7; - a7ddrphy_bitslip13_value0 <= 3'd7; - a7ddrphy_bitslip13_value1 <= 3'd7; - a7ddrphy_bitslip14_value0 <= 3'd7; - a7ddrphy_bitslip14_value1 <= 3'd7; - a7ddrphy_bitslip15_value0 <= 3'd7; - a7ddrphy_bitslip15_value1 <= 3'd7; - a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; - a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; - a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; - a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; - litedramcore_storage <= 4'd1; - litedramcore_re <= 1'd0; - litedramcore_phaseinjector0_command_storage <= 6'd0; - litedramcore_phaseinjector0_command_re <= 1'd0; - litedramcore_phaseinjector0_address_re <= 1'd0; - litedramcore_phaseinjector0_baddress_re <= 1'd0; - litedramcore_phaseinjector0_wrdata_re <= 1'd0; - litedramcore_phaseinjector0_rddata_status <= 32'd0; - litedramcore_phaseinjector0_rddata_re <= 1'd0; - litedramcore_phaseinjector1_command_storage <= 6'd0; - litedramcore_phaseinjector1_command_re <= 1'd0; - litedramcore_phaseinjector1_address_re <= 1'd0; - litedramcore_phaseinjector1_baddress_re <= 1'd0; - litedramcore_phaseinjector1_wrdata_re <= 1'd0; - litedramcore_phaseinjector1_rddata_status <= 32'd0; - litedramcore_phaseinjector1_rddata_re <= 1'd0; - litedramcore_phaseinjector2_command_storage <= 6'd0; - litedramcore_phaseinjector2_command_re <= 1'd0; - litedramcore_phaseinjector2_address_re <= 1'd0; - litedramcore_phaseinjector2_baddress_re <= 1'd0; - litedramcore_phaseinjector2_wrdata_re <= 1'd0; - litedramcore_phaseinjector2_rddata_status <= 32'd0; - litedramcore_phaseinjector2_rddata_re <= 1'd0; - litedramcore_phaseinjector3_command_storage <= 6'd0; - litedramcore_phaseinjector3_command_re <= 1'd0; - litedramcore_phaseinjector3_address_re <= 1'd0; - litedramcore_phaseinjector3_baddress_re <= 1'd0; - litedramcore_phaseinjector3_wrdata_re <= 1'd0; - litedramcore_phaseinjector3_rddata_status <= 32'd0; - litedramcore_phaseinjector3_rddata_re <= 1'd0; - litedramcore_dfi_p0_address <= 15'd0; - litedramcore_dfi_p0_bank <= 3'd0; - litedramcore_dfi_p0_cas_n <= 1'd1; - litedramcore_dfi_p0_cs_n <= 1'd1; - litedramcore_dfi_p0_ras_n <= 1'd1; - litedramcore_dfi_p0_we_n <= 1'd1; - litedramcore_dfi_p0_wrdata_en <= 1'd0; - litedramcore_dfi_p0_rddata_en <= 1'd0; - litedramcore_dfi_p1_address <= 15'd0; - litedramcore_dfi_p1_bank <= 3'd0; - litedramcore_dfi_p1_cas_n <= 1'd1; - litedramcore_dfi_p1_cs_n <= 1'd1; - litedramcore_dfi_p1_ras_n <= 1'd1; - litedramcore_dfi_p1_we_n <= 1'd1; - litedramcore_dfi_p1_wrdata_en <= 1'd0; - litedramcore_dfi_p1_rddata_en <= 1'd0; - litedramcore_dfi_p2_address <= 15'd0; - litedramcore_dfi_p2_bank <= 3'd0; - litedramcore_dfi_p2_cas_n <= 1'd1; - litedramcore_dfi_p2_cs_n <= 1'd1; - litedramcore_dfi_p2_ras_n <= 1'd1; - litedramcore_dfi_p2_we_n <= 1'd1; - litedramcore_dfi_p2_wrdata_en <= 1'd0; - litedramcore_dfi_p2_rddata_en <= 1'd0; - litedramcore_dfi_p3_address <= 15'd0; - litedramcore_dfi_p3_bank <= 3'd0; - litedramcore_dfi_p3_cas_n <= 1'd1; - litedramcore_dfi_p3_cs_n <= 1'd1; - litedramcore_dfi_p3_ras_n <= 1'd1; - litedramcore_dfi_p3_we_n <= 1'd1; - litedramcore_dfi_p3_wrdata_en <= 1'd0; - litedramcore_dfi_p3_rddata_en <= 1'd0; - litedramcore_cmd_payload_a <= 15'd0; - litedramcore_cmd_payload_ba <= 3'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_timer_count1 <= 10'd781; - litedramcore_postponer_req_o <= 1'd0; - litedramcore_postponer_count <= 1'd0; - litedramcore_sequencer_done1 <= 1'd0; - litedramcore_sequencer_counter <= 6'd0; - litedramcore_sequencer_count <= 1'd0; - litedramcore_zqcs_timer_count1 <= 27'd99999999; - litedramcore_zqcs_executer_done <= 1'd0; - litedramcore_zqcs_executer_counter <= 5'd0; - litedramcore_bankmachine0_level <= 5'd0; - litedramcore_bankmachine0_produce <= 4'd0; - litedramcore_bankmachine0_consume <= 4'd0; - litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 22'd0; - litedramcore_bankmachine0_row <= 15'd0; - litedramcore_bankmachine0_row_opened <= 1'd0; - litedramcore_bankmachine0_twtpcon_ready <= 1'd0; - litedramcore_bankmachine0_twtpcon_count <= 3'd0; - litedramcore_bankmachine0_trccon_ready <= 1'd0; - litedramcore_bankmachine0_trccon_count <= 3'd0; - litedramcore_bankmachine0_trascon_ready <= 1'd0; - litedramcore_bankmachine0_trascon_count <= 3'd0; - litedramcore_bankmachine1_level <= 5'd0; - litedramcore_bankmachine1_produce <= 4'd0; - litedramcore_bankmachine1_consume <= 4'd0; - litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 22'd0; - litedramcore_bankmachine1_row <= 15'd0; - litedramcore_bankmachine1_row_opened <= 1'd0; - litedramcore_bankmachine1_twtpcon_ready <= 1'd0; - litedramcore_bankmachine1_twtpcon_count <= 3'd0; - litedramcore_bankmachine1_trccon_ready <= 1'd0; - litedramcore_bankmachine1_trccon_count <= 3'd0; - litedramcore_bankmachine1_trascon_ready <= 1'd0; - litedramcore_bankmachine1_trascon_count <= 3'd0; - litedramcore_bankmachine2_level <= 5'd0; - litedramcore_bankmachine2_produce <= 4'd0; - litedramcore_bankmachine2_consume <= 4'd0; - litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 22'd0; - litedramcore_bankmachine2_row <= 15'd0; - litedramcore_bankmachine2_row_opened <= 1'd0; - litedramcore_bankmachine2_twtpcon_ready <= 1'd0; - litedramcore_bankmachine2_twtpcon_count <= 3'd0; - litedramcore_bankmachine2_trccon_ready <= 1'd0; - litedramcore_bankmachine2_trccon_count <= 3'd0; - litedramcore_bankmachine2_trascon_ready <= 1'd0; - litedramcore_bankmachine2_trascon_count <= 3'd0; - litedramcore_bankmachine3_level <= 5'd0; - litedramcore_bankmachine3_produce <= 4'd0; - litedramcore_bankmachine3_consume <= 4'd0; - litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 22'd0; - litedramcore_bankmachine3_row <= 15'd0; - litedramcore_bankmachine3_row_opened <= 1'd0; - litedramcore_bankmachine3_twtpcon_ready <= 1'd0; - litedramcore_bankmachine3_twtpcon_count <= 3'd0; - litedramcore_bankmachine3_trccon_ready <= 1'd0; - litedramcore_bankmachine3_trccon_count <= 3'd0; - litedramcore_bankmachine3_trascon_ready <= 1'd0; - litedramcore_bankmachine3_trascon_count <= 3'd0; - litedramcore_bankmachine4_level <= 5'd0; - litedramcore_bankmachine4_produce <= 4'd0; - litedramcore_bankmachine4_consume <= 4'd0; - litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 22'd0; - litedramcore_bankmachine4_row <= 15'd0; - litedramcore_bankmachine4_row_opened <= 1'd0; - litedramcore_bankmachine4_twtpcon_ready <= 1'd0; - litedramcore_bankmachine4_twtpcon_count <= 3'd0; - litedramcore_bankmachine4_trccon_ready <= 1'd0; - litedramcore_bankmachine4_trccon_count <= 3'd0; - litedramcore_bankmachine4_trascon_ready <= 1'd0; - litedramcore_bankmachine4_trascon_count <= 3'd0; - litedramcore_bankmachine5_level <= 5'd0; - litedramcore_bankmachine5_produce <= 4'd0; - litedramcore_bankmachine5_consume <= 4'd0; - litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 22'd0; - litedramcore_bankmachine5_row <= 15'd0; - litedramcore_bankmachine5_row_opened <= 1'd0; - litedramcore_bankmachine5_twtpcon_ready <= 1'd0; - litedramcore_bankmachine5_twtpcon_count <= 3'd0; - litedramcore_bankmachine5_trccon_ready <= 1'd0; - litedramcore_bankmachine5_trccon_count <= 3'd0; - litedramcore_bankmachine5_trascon_ready <= 1'd0; - litedramcore_bankmachine5_trascon_count <= 3'd0; - litedramcore_bankmachine6_level <= 5'd0; - litedramcore_bankmachine6_produce <= 4'd0; - litedramcore_bankmachine6_consume <= 4'd0; - litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 22'd0; - litedramcore_bankmachine6_row <= 15'd0; - litedramcore_bankmachine6_row_opened <= 1'd0; - litedramcore_bankmachine6_twtpcon_ready <= 1'd0; - litedramcore_bankmachine6_twtpcon_count <= 3'd0; - litedramcore_bankmachine6_trccon_ready <= 1'd0; - litedramcore_bankmachine6_trccon_count <= 3'd0; - litedramcore_bankmachine6_trascon_ready <= 1'd0; - litedramcore_bankmachine6_trascon_count <= 3'd0; - litedramcore_bankmachine7_level <= 5'd0; - litedramcore_bankmachine7_produce <= 4'd0; - litedramcore_bankmachine7_consume <= 4'd0; - litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 22'd0; - litedramcore_bankmachine7_row <= 15'd0; - litedramcore_bankmachine7_row_opened <= 1'd0; - litedramcore_bankmachine7_twtpcon_ready <= 1'd0; - litedramcore_bankmachine7_twtpcon_count <= 3'd0; - litedramcore_bankmachine7_trccon_ready <= 1'd0; - litedramcore_bankmachine7_trccon_count <= 3'd0; - litedramcore_bankmachine7_trascon_ready <= 1'd0; - litedramcore_bankmachine7_trascon_count <= 3'd0; - litedramcore_choose_cmd_grant <= 3'd0; - litedramcore_choose_req_grant <= 3'd0; - litedramcore_trrdcon_ready <= 1'd0; - litedramcore_trrdcon_count <= 1'd0; - litedramcore_tfawcon_ready <= 1'd1; - litedramcore_tfawcon_window <= 5'd0; - litedramcore_tccdcon_ready <= 1'd0; - litedramcore_tccdcon_count <= 1'd0; - litedramcore_twtrcon_ready <= 1'd0; - litedramcore_twtrcon_count <= 3'd0; - litedramcore_time0 <= 5'd0; - litedramcore_time1 <= 4'd0; - init_done_storage <= 1'd0; - init_done_re <= 1'd0; - init_error_storage <= 1'd0; - init_error_re <= 1'd0; - litedramcore_we <= 1'd0; - litedramcore_refresher_state <= 2'd0; - litedramcore_bankmachine0_state <= 4'd0; - litedramcore_bankmachine1_state <= 4'd0; - litedramcore_bankmachine2_state <= 4'd0; - litedramcore_bankmachine3_state <= 4'd0; - litedramcore_bankmachine4_state <= 4'd0; - litedramcore_bankmachine5_state <= 4'd0; - litedramcore_bankmachine6_state <= 4'd0; - litedramcore_bankmachine7_state <= 4'd0; - litedramcore_multiplexer_state <= 4'd0; - litedramcore_new_master_wdata_ready0 <= 1'd0; - litedramcore_new_master_wdata_ready1 <= 1'd0; - litedramcore_new_master_rdata_valid0 <= 1'd0; - litedramcore_new_master_rdata_valid1 <= 1'd0; - litedramcore_new_master_rdata_valid2 <= 1'd0; - litedramcore_new_master_rdata_valid3 <= 1'd0; - litedramcore_new_master_rdata_valid4 <= 1'd0; - litedramcore_new_master_rdata_valid5 <= 1'd0; - litedramcore_new_master_rdata_valid6 <= 1'd0; - litedramcore_new_master_rdata_valid7 <= 1'd0; - litedramcore_new_master_rdata_valid8 <= 1'd0; - litedramcore_state <= 2'd0; + main_a7ddrphy_rst_storage <= 1'd0; + main_a7ddrphy_rst_re <= 1'd0; + main_a7ddrphy_dly_sel_storage <= 2'd0; + main_a7ddrphy_dly_sel_re <= 1'd0; + main_a7ddrphy_half_sys8x_taps_storage <= 5'd8; + main_a7ddrphy_half_sys8x_taps_re <= 1'd0; + main_a7ddrphy_wlevel_en_storage <= 1'd0; + main_a7ddrphy_wlevel_en_re <= 1'd0; + main_a7ddrphy_rdphase_storage <= 2'd2; + main_a7ddrphy_rdphase_re <= 1'd0; + main_a7ddrphy_wrphase_storage <= 2'd3; + main_a7ddrphy_wrphase_re <= 1'd0; + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + main_a7ddrphy_dqspattern_o1 <= 8'd0; + main_a7ddrphy_bitslip0_value0 <= 3'd7; + main_a7ddrphy_bitslip1_value0 <= 3'd7; + main_a7ddrphy_bitslip0_value1 <= 3'd7; + main_a7ddrphy_bitslip1_value1 <= 3'd7; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + main_a7ddrphy_bitslip0_value2 <= 3'd7; + main_a7ddrphy_bitslip0_value3 <= 3'd7; + main_a7ddrphy_bitslip1_value2 <= 3'd7; + main_a7ddrphy_bitslip1_value3 <= 3'd7; + main_a7ddrphy_bitslip2_value0 <= 3'd7; + main_a7ddrphy_bitslip2_value1 <= 3'd7; + main_a7ddrphy_bitslip3_value0 <= 3'd7; + main_a7ddrphy_bitslip3_value1 <= 3'd7; + main_a7ddrphy_bitslip4_value0 <= 3'd7; + main_a7ddrphy_bitslip4_value1 <= 3'd7; + main_a7ddrphy_bitslip5_value0 <= 3'd7; + main_a7ddrphy_bitslip5_value1 <= 3'd7; + main_a7ddrphy_bitslip6_value0 <= 3'd7; + main_a7ddrphy_bitslip6_value1 <= 3'd7; + main_a7ddrphy_bitslip7_value0 <= 3'd7; + main_a7ddrphy_bitslip7_value1 <= 3'd7; + main_a7ddrphy_bitslip8_value0 <= 3'd7; + main_a7ddrphy_bitslip8_value1 <= 3'd7; + main_a7ddrphy_bitslip9_value0 <= 3'd7; + main_a7ddrphy_bitslip9_value1 <= 3'd7; + main_a7ddrphy_bitslip10_value0 <= 3'd7; + main_a7ddrphy_bitslip10_value1 <= 3'd7; + main_a7ddrphy_bitslip11_value0 <= 3'd7; + main_a7ddrphy_bitslip11_value1 <= 3'd7; + main_a7ddrphy_bitslip12_value0 <= 3'd7; + main_a7ddrphy_bitslip12_value1 <= 3'd7; + main_a7ddrphy_bitslip13_value0 <= 3'd7; + main_a7ddrphy_bitslip13_value1 <= 3'd7; + main_a7ddrphy_bitslip14_value0 <= 3'd7; + main_a7ddrphy_bitslip14_value1 <= 3'd7; + main_a7ddrphy_bitslip15_value0 <= 3'd7; + main_a7ddrphy_bitslip15_value1 <= 3'd7; + main_a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; + main_a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; + main_a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; + main_a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; + main_litedramcore_storage <= 4'd1; + main_litedramcore_re <= 1'd0; + main_litedramcore_phaseinjector0_command_storage <= 8'd0; + main_litedramcore_phaseinjector0_command_re <= 1'd0; + main_litedramcore_phaseinjector0_address_re <= 1'd0; + main_litedramcore_phaseinjector0_baddress_re <= 1'd0; + main_litedramcore_phaseinjector0_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector0_rddata_status <= 32'd0; + main_litedramcore_phaseinjector0_rddata_re <= 1'd0; + main_litedramcore_phaseinjector1_command_storage <= 8'd0; + main_litedramcore_phaseinjector1_command_re <= 1'd0; + main_litedramcore_phaseinjector1_address_re <= 1'd0; + main_litedramcore_phaseinjector1_baddress_re <= 1'd0; + main_litedramcore_phaseinjector1_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector1_rddata_status <= 32'd0; + main_litedramcore_phaseinjector1_rddata_re <= 1'd0; + main_litedramcore_phaseinjector2_command_storage <= 8'd0; + main_litedramcore_phaseinjector2_command_re <= 1'd0; + main_litedramcore_phaseinjector2_address_re <= 1'd0; + main_litedramcore_phaseinjector2_baddress_re <= 1'd0; + main_litedramcore_phaseinjector2_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector2_rddata_status <= 32'd0; + main_litedramcore_phaseinjector2_rddata_re <= 1'd0; + main_litedramcore_phaseinjector3_command_storage <= 8'd0; + main_litedramcore_phaseinjector3_command_re <= 1'd0; + main_litedramcore_phaseinjector3_address_re <= 1'd0; + main_litedramcore_phaseinjector3_baddress_re <= 1'd0; + main_litedramcore_phaseinjector3_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector3_rddata_status <= 32'd0; + main_litedramcore_phaseinjector3_rddata_re <= 1'd0; + main_litedramcore_dfi_p0_address <= 15'd0; + main_litedramcore_dfi_p0_bank <= 3'd0; + main_litedramcore_dfi_p0_cas_n <= 1'd1; + main_litedramcore_dfi_p0_cs_n <= 1'd1; + main_litedramcore_dfi_p0_ras_n <= 1'd1; + main_litedramcore_dfi_p0_we_n <= 1'd1; + main_litedramcore_dfi_p0_wrdata_en <= 1'd0; + main_litedramcore_dfi_p0_rddata_en <= 1'd0; + main_litedramcore_dfi_p1_address <= 15'd0; + main_litedramcore_dfi_p1_bank <= 3'd0; + main_litedramcore_dfi_p1_cas_n <= 1'd1; + main_litedramcore_dfi_p1_cs_n <= 1'd1; + main_litedramcore_dfi_p1_ras_n <= 1'd1; + main_litedramcore_dfi_p1_we_n <= 1'd1; + main_litedramcore_dfi_p1_wrdata_en <= 1'd0; + main_litedramcore_dfi_p1_rddata_en <= 1'd0; + main_litedramcore_dfi_p2_address <= 15'd0; + main_litedramcore_dfi_p2_bank <= 3'd0; + main_litedramcore_dfi_p2_cas_n <= 1'd1; + main_litedramcore_dfi_p2_cs_n <= 1'd1; + main_litedramcore_dfi_p2_ras_n <= 1'd1; + main_litedramcore_dfi_p2_we_n <= 1'd1; + main_litedramcore_dfi_p2_wrdata_en <= 1'd0; + main_litedramcore_dfi_p2_rddata_en <= 1'd0; + main_litedramcore_dfi_p3_address <= 15'd0; + main_litedramcore_dfi_p3_bank <= 3'd0; + main_litedramcore_dfi_p3_cas_n <= 1'd1; + main_litedramcore_dfi_p3_cs_n <= 1'd1; + main_litedramcore_dfi_p3_ras_n <= 1'd1; + main_litedramcore_dfi_p3_we_n <= 1'd1; + main_litedramcore_dfi_p3_wrdata_en <= 1'd0; + main_litedramcore_dfi_p3_rddata_en <= 1'd0; + main_litedramcore_cmd_payload_a <= 15'd0; + main_litedramcore_cmd_payload_ba <= 3'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_timer_count1 <= 10'd781; + main_litedramcore_postponer_req_o <= 1'd0; + main_litedramcore_postponer_count <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd0; + main_litedramcore_sequencer_trigger <= 6'd0; + main_litedramcore_sequencer_count <= 1'd0; + main_litedramcore_zqcs_timer_count1 <= 27'd99999999; + main_litedramcore_zqcs_executer_done <= 1'd0; + main_litedramcore_zqcs_executer_trigger <= 5'd0; + main_litedramcore_bankmachine0_level <= 5'd0; + main_litedramcore_bankmachine0_produce <= 4'd0; + main_litedramcore_bankmachine0_consume <= 4'd0; + main_litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine0_row <= 15'd0; + main_litedramcore_bankmachine0_row_opened <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine0_trccon_ready <= 1'd0; + main_litedramcore_bankmachine0_trccon_count <= 3'd0; + main_litedramcore_bankmachine0_trascon_ready <= 1'd0; + main_litedramcore_bankmachine0_trascon_count <= 3'd0; + main_litedramcore_bankmachine1_level <= 5'd0; + main_litedramcore_bankmachine1_produce <= 4'd0; + main_litedramcore_bankmachine1_consume <= 4'd0; + main_litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine1_row <= 15'd0; + main_litedramcore_bankmachine1_row_opened <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine1_trccon_ready <= 1'd0; + main_litedramcore_bankmachine1_trccon_count <= 3'd0; + main_litedramcore_bankmachine1_trascon_ready <= 1'd0; + main_litedramcore_bankmachine1_trascon_count <= 3'd0; + main_litedramcore_bankmachine2_level <= 5'd0; + main_litedramcore_bankmachine2_produce <= 4'd0; + main_litedramcore_bankmachine2_consume <= 4'd0; + main_litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine2_row <= 15'd0; + main_litedramcore_bankmachine2_row_opened <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine2_trccon_ready <= 1'd0; + main_litedramcore_bankmachine2_trccon_count <= 3'd0; + main_litedramcore_bankmachine2_trascon_ready <= 1'd0; + main_litedramcore_bankmachine2_trascon_count <= 3'd0; + main_litedramcore_bankmachine3_level <= 5'd0; + main_litedramcore_bankmachine3_produce <= 4'd0; + main_litedramcore_bankmachine3_consume <= 4'd0; + main_litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine3_row <= 15'd0; + main_litedramcore_bankmachine3_row_opened <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine3_trccon_ready <= 1'd0; + main_litedramcore_bankmachine3_trccon_count <= 3'd0; + main_litedramcore_bankmachine3_trascon_ready <= 1'd0; + main_litedramcore_bankmachine3_trascon_count <= 3'd0; + main_litedramcore_bankmachine4_level <= 5'd0; + main_litedramcore_bankmachine4_produce <= 4'd0; + main_litedramcore_bankmachine4_consume <= 4'd0; + main_litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine4_row <= 15'd0; + main_litedramcore_bankmachine4_row_opened <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine4_trccon_ready <= 1'd0; + main_litedramcore_bankmachine4_trccon_count <= 3'd0; + main_litedramcore_bankmachine4_trascon_ready <= 1'd0; + main_litedramcore_bankmachine4_trascon_count <= 3'd0; + main_litedramcore_bankmachine5_level <= 5'd0; + main_litedramcore_bankmachine5_produce <= 4'd0; + main_litedramcore_bankmachine5_consume <= 4'd0; + main_litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine5_row <= 15'd0; + main_litedramcore_bankmachine5_row_opened <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine5_trccon_ready <= 1'd0; + main_litedramcore_bankmachine5_trccon_count <= 3'd0; + main_litedramcore_bankmachine5_trascon_ready <= 1'd0; + main_litedramcore_bankmachine5_trascon_count <= 3'd0; + main_litedramcore_bankmachine6_level <= 5'd0; + main_litedramcore_bankmachine6_produce <= 4'd0; + main_litedramcore_bankmachine6_consume <= 4'd0; + main_litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine6_row <= 15'd0; + main_litedramcore_bankmachine6_row_opened <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine6_trccon_ready <= 1'd0; + main_litedramcore_bankmachine6_trccon_count <= 3'd0; + main_litedramcore_bankmachine6_trascon_ready <= 1'd0; + main_litedramcore_bankmachine6_trascon_count <= 3'd0; + main_litedramcore_bankmachine7_level <= 5'd0; + main_litedramcore_bankmachine7_produce <= 4'd0; + main_litedramcore_bankmachine7_consume <= 4'd0; + main_litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 22'd0; + main_litedramcore_bankmachine7_row <= 15'd0; + main_litedramcore_bankmachine7_row_opened <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine7_trccon_ready <= 1'd0; + main_litedramcore_bankmachine7_trccon_count <= 3'd0; + main_litedramcore_bankmachine7_trascon_ready <= 1'd0; + main_litedramcore_bankmachine7_trascon_count <= 3'd0; + main_litedramcore_choose_cmd_grant <= 3'd0; + main_litedramcore_choose_req_grant <= 3'd0; + main_litedramcore_trrdcon_ready <= 1'd0; + main_litedramcore_trrdcon_count <= 1'd0; + main_litedramcore_tfawcon_ready <= 1'd1; + main_litedramcore_tfawcon_window <= 5'd0; + main_litedramcore_tccdcon_ready <= 1'd0; + main_litedramcore_tccdcon_count <= 1'd0; + main_litedramcore_twtrcon_ready <= 1'd0; + main_litedramcore_twtrcon_count <= 3'd0; + main_litedramcore_time0 <= 5'd0; + main_litedramcore_time1 <= 4'd0; + main_init_done_storage <= 1'd0; + main_init_done_re <= 1'd0; + main_init_error_storage <= 1'd0; + main_init_error_re <= 1'd0; + builder_interface1_we <= 1'd0; + builder_refresher_state <= 2'd0; + builder_bankmachine0_state <= 4'd0; + builder_bankmachine1_state <= 4'd0; + builder_bankmachine2_state <= 4'd0; + builder_bankmachine3_state <= 4'd0; + builder_bankmachine4_state <= 4'd0; + builder_bankmachine5_state <= 4'd0; + builder_bankmachine6_state <= 4'd0; + builder_bankmachine7_state <= 4'd0; + builder_multiplexer_state <= 4'd0; + builder_new_master_wdata_ready0 <= 1'd0; + builder_new_master_wdata_ready1 <= 1'd0; + builder_new_master_rdata_valid0 <= 1'd0; + builder_new_master_rdata_valid1 <= 1'd0; + builder_new_master_rdata_valid2 <= 1'd0; + builder_new_master_rdata_valid3 <= 1'd0; + builder_new_master_rdata_valid4 <= 1'd0; + builder_new_master_rdata_valid5 <= 1'd0; + builder_new_master_rdata_valid6 <= 1'd0; + builder_new_master_rdata_valid7 <= 1'd0; + builder_new_master_rdata_valid8 <= 1'd0; + builder_state <= 2'd0; end end @@ -14116,1933 +14532,2653 @@ end // Specialized Logic //------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +// Instance BUFG of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG( - .I(clkout0), - .O(clkout_buf0) + // Inputs. + .I (main_clkout0), + + // Outputs. + .O (main_clkout_buf0) ); +//------------------------------------------------------------------------------ +// Instance BUFG_1 of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG_1( - .I(clkout1), - .O(clkout_buf1) + // Inputs. + .I (main_clkout1), + + // Outputs. + .O (main_clkout_buf1) ); +//------------------------------------------------------------------------------ +// Instance BUFG_2 of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG_2( - .I(clkout2), - .O(clkout_buf2) + // Inputs. + .I (main_clkout2), + + // Outputs. + .O (main_clkout_buf2) ); +//------------------------------------------------------------------------------ +// Instance BUFG_3 of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG_3( - .I(clkout3), - .O(clkout_buf3) + // Inputs. + .I (main_clkout3), + + // Outputs. + .O (main_clkout_buf3) ); +//------------------------------------------------------------------------------ +// Instance IDELAYCTRL of IDELAYCTRL Module. +//------------------------------------------------------------------------------ IDELAYCTRL IDELAYCTRL( - .REFCLK(iodelay_clk), - .RST(ic_reset) + // Inputs. + .REFCLK (iodelay_clk), + .RST (main_ic_reset) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(1'd0), - .D2(1'd1), - .D3(1'd0), - .D4(1'd1), - .D5(1'd0), - .D6(1'd1), - .D7(1'd0), - .D8(1'd1), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(a7ddrphy_sd_clk_se_nodelay) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (1'd0), + .D2 (1'd1), + .D3 (1'd0), + .D4 (1'd1), + .D5 (1'd0), + .D6 (1'd1), + .D7 (1'd0), + .D8 (1'd1), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_a7ddrphy_sd_clk_se_nodelay) ); +//------------------------------------------------------------------------------ +// Instance OBUFDS of OBUFDS Module. +//------------------------------------------------------------------------------ OBUFDS OBUFDS( - .I(a7ddrphy_sd_clk_se_nodelay), - .O(ddram_clk_p), - .OB(ddram_clk_n) + // Inputs. + .I (main_a7ddrphy_sd_clk_se_nodelay), + + // Outputs. + .O (ddram_clk_p), + .OB (ddram_clk_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_1 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_1 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_reset_n), - .D2(a7ddrphy_dfi_p0_reset_n), - .D3(a7ddrphy_dfi_p1_reset_n), - .D4(a7ddrphy_dfi_p1_reset_n), - .D5(a7ddrphy_dfi_p2_reset_n), - .D6(a7ddrphy_dfi_p2_reset_n), - .D7(a7ddrphy_dfi_p3_reset_n), - .D8(a7ddrphy_dfi_p3_reset_n), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_reset_n) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_reset_n), + .D2 (main_a7ddrphy_dfi_p0_reset_n), + .D3 (main_a7ddrphy_dfi_p1_reset_n), + .D4 (main_a7ddrphy_dfi_p1_reset_n), + .D5 (main_a7ddrphy_dfi_p2_reset_n), + .D6 (main_a7ddrphy_dfi_p2_reset_n), + .D7 (main_a7ddrphy_dfi_p3_reset_n), + .D8 (main_a7ddrphy_dfi_p3_reset_n), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_reset_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_2 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_2 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_cs_n), - .D2(a7ddrphy_dfi_p0_cs_n), - .D3(a7ddrphy_dfi_p1_cs_n), - .D4(a7ddrphy_dfi_p1_cs_n), - .D5(a7ddrphy_dfi_p2_cs_n), - .D6(a7ddrphy_dfi_p2_cs_n), - .D7(a7ddrphy_dfi_p3_cs_n), - .D8(a7ddrphy_dfi_p3_cs_n), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_cs_n) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_cs_n), + .D2 (main_a7ddrphy_dfi_p0_cs_n), + .D3 (main_a7ddrphy_dfi_p1_cs_n), + .D4 (main_a7ddrphy_dfi_p1_cs_n), + .D5 (main_a7ddrphy_dfi_p2_cs_n), + .D6 (main_a7ddrphy_dfi_p2_cs_n), + .D7 (main_a7ddrphy_dfi_p3_cs_n), + .D8 (main_a7ddrphy_dfi_p3_cs_n), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_cs_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_3 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_3 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[0]), - .D2(a7ddrphy_dfi_p0_address[0]), - .D3(a7ddrphy_dfi_p1_address[0]), - .D4(a7ddrphy_dfi_p1_address[0]), - .D5(a7ddrphy_dfi_p2_address[0]), - .D6(a7ddrphy_dfi_p2_address[0]), - .D7(a7ddrphy_dfi_p3_address[0]), - .D8(a7ddrphy_dfi_p3_address[0]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[0]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[0]), + .D2 (main_a7ddrphy_dfi_p0_address[0]), + .D3 (main_a7ddrphy_dfi_p1_address[0]), + .D4 (main_a7ddrphy_dfi_p1_address[0]), + .D5 (main_a7ddrphy_dfi_p2_address[0]), + .D6 (main_a7ddrphy_dfi_p2_address[0]), + .D7 (main_a7ddrphy_dfi_p3_address[0]), + .D8 (main_a7ddrphy_dfi_p3_address[0]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[0]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_4 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_4 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[1]), - .D2(a7ddrphy_dfi_p0_address[1]), - .D3(a7ddrphy_dfi_p1_address[1]), - .D4(a7ddrphy_dfi_p1_address[1]), - .D5(a7ddrphy_dfi_p2_address[1]), - .D6(a7ddrphy_dfi_p2_address[1]), - .D7(a7ddrphy_dfi_p3_address[1]), - .D8(a7ddrphy_dfi_p3_address[1]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[1]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[1]), + .D2 (main_a7ddrphy_dfi_p0_address[1]), + .D3 (main_a7ddrphy_dfi_p1_address[1]), + .D4 (main_a7ddrphy_dfi_p1_address[1]), + .D5 (main_a7ddrphy_dfi_p2_address[1]), + .D6 (main_a7ddrphy_dfi_p2_address[1]), + .D7 (main_a7ddrphy_dfi_p3_address[1]), + .D8 (main_a7ddrphy_dfi_p3_address[1]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[1]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_5 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_5 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[2]), - .D2(a7ddrphy_dfi_p0_address[2]), - .D3(a7ddrphy_dfi_p1_address[2]), - .D4(a7ddrphy_dfi_p1_address[2]), - .D5(a7ddrphy_dfi_p2_address[2]), - .D6(a7ddrphy_dfi_p2_address[2]), - .D7(a7ddrphy_dfi_p3_address[2]), - .D8(a7ddrphy_dfi_p3_address[2]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[2]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[2]), + .D2 (main_a7ddrphy_dfi_p0_address[2]), + .D3 (main_a7ddrphy_dfi_p1_address[2]), + .D4 (main_a7ddrphy_dfi_p1_address[2]), + .D5 (main_a7ddrphy_dfi_p2_address[2]), + .D6 (main_a7ddrphy_dfi_p2_address[2]), + .D7 (main_a7ddrphy_dfi_p3_address[2]), + .D8 (main_a7ddrphy_dfi_p3_address[2]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[2]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_6 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_6 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[3]), - .D2(a7ddrphy_dfi_p0_address[3]), - .D3(a7ddrphy_dfi_p1_address[3]), - .D4(a7ddrphy_dfi_p1_address[3]), - .D5(a7ddrphy_dfi_p2_address[3]), - .D6(a7ddrphy_dfi_p2_address[3]), - .D7(a7ddrphy_dfi_p3_address[3]), - .D8(a7ddrphy_dfi_p3_address[3]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[3]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[3]), + .D2 (main_a7ddrphy_dfi_p0_address[3]), + .D3 (main_a7ddrphy_dfi_p1_address[3]), + .D4 (main_a7ddrphy_dfi_p1_address[3]), + .D5 (main_a7ddrphy_dfi_p2_address[3]), + .D6 (main_a7ddrphy_dfi_p2_address[3]), + .D7 (main_a7ddrphy_dfi_p3_address[3]), + .D8 (main_a7ddrphy_dfi_p3_address[3]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[3]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_7 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_7 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[4]), - .D2(a7ddrphy_dfi_p0_address[4]), - .D3(a7ddrphy_dfi_p1_address[4]), - .D4(a7ddrphy_dfi_p1_address[4]), - .D5(a7ddrphy_dfi_p2_address[4]), - .D6(a7ddrphy_dfi_p2_address[4]), - .D7(a7ddrphy_dfi_p3_address[4]), - .D8(a7ddrphy_dfi_p3_address[4]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[4]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[4]), + .D2 (main_a7ddrphy_dfi_p0_address[4]), + .D3 (main_a7ddrphy_dfi_p1_address[4]), + .D4 (main_a7ddrphy_dfi_p1_address[4]), + .D5 (main_a7ddrphy_dfi_p2_address[4]), + .D6 (main_a7ddrphy_dfi_p2_address[4]), + .D7 (main_a7ddrphy_dfi_p3_address[4]), + .D8 (main_a7ddrphy_dfi_p3_address[4]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[4]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_8 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_8 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[5]), - .D2(a7ddrphy_dfi_p0_address[5]), - .D3(a7ddrphy_dfi_p1_address[5]), - .D4(a7ddrphy_dfi_p1_address[5]), - .D5(a7ddrphy_dfi_p2_address[5]), - .D6(a7ddrphy_dfi_p2_address[5]), - .D7(a7ddrphy_dfi_p3_address[5]), - .D8(a7ddrphy_dfi_p3_address[5]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[5]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[5]), + .D2 (main_a7ddrphy_dfi_p0_address[5]), + .D3 (main_a7ddrphy_dfi_p1_address[5]), + .D4 (main_a7ddrphy_dfi_p1_address[5]), + .D5 (main_a7ddrphy_dfi_p2_address[5]), + .D6 (main_a7ddrphy_dfi_p2_address[5]), + .D7 (main_a7ddrphy_dfi_p3_address[5]), + .D8 (main_a7ddrphy_dfi_p3_address[5]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[5]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_9 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_9 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[6]), - .D2(a7ddrphy_dfi_p0_address[6]), - .D3(a7ddrphy_dfi_p1_address[6]), - .D4(a7ddrphy_dfi_p1_address[6]), - .D5(a7ddrphy_dfi_p2_address[6]), - .D6(a7ddrphy_dfi_p2_address[6]), - .D7(a7ddrphy_dfi_p3_address[6]), - .D8(a7ddrphy_dfi_p3_address[6]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[6]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[6]), + .D2 (main_a7ddrphy_dfi_p0_address[6]), + .D3 (main_a7ddrphy_dfi_p1_address[6]), + .D4 (main_a7ddrphy_dfi_p1_address[6]), + .D5 (main_a7ddrphy_dfi_p2_address[6]), + .D6 (main_a7ddrphy_dfi_p2_address[6]), + .D7 (main_a7ddrphy_dfi_p3_address[6]), + .D8 (main_a7ddrphy_dfi_p3_address[6]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[6]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_10 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_10 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[7]), - .D2(a7ddrphy_dfi_p0_address[7]), - .D3(a7ddrphy_dfi_p1_address[7]), - .D4(a7ddrphy_dfi_p1_address[7]), - .D5(a7ddrphy_dfi_p2_address[7]), - .D6(a7ddrphy_dfi_p2_address[7]), - .D7(a7ddrphy_dfi_p3_address[7]), - .D8(a7ddrphy_dfi_p3_address[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[7]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[7]), + .D2 (main_a7ddrphy_dfi_p0_address[7]), + .D3 (main_a7ddrphy_dfi_p1_address[7]), + .D4 (main_a7ddrphy_dfi_p1_address[7]), + .D5 (main_a7ddrphy_dfi_p2_address[7]), + .D6 (main_a7ddrphy_dfi_p2_address[7]), + .D7 (main_a7ddrphy_dfi_p3_address[7]), + .D8 (main_a7ddrphy_dfi_p3_address[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[7]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_11 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_11 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[8]), - .D2(a7ddrphy_dfi_p0_address[8]), - .D3(a7ddrphy_dfi_p1_address[8]), - .D4(a7ddrphy_dfi_p1_address[8]), - .D5(a7ddrphy_dfi_p2_address[8]), - .D6(a7ddrphy_dfi_p2_address[8]), - .D7(a7ddrphy_dfi_p3_address[8]), - .D8(a7ddrphy_dfi_p3_address[8]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[8]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[8]), + .D2 (main_a7ddrphy_dfi_p0_address[8]), + .D3 (main_a7ddrphy_dfi_p1_address[8]), + .D4 (main_a7ddrphy_dfi_p1_address[8]), + .D5 (main_a7ddrphy_dfi_p2_address[8]), + .D6 (main_a7ddrphy_dfi_p2_address[8]), + .D7 (main_a7ddrphy_dfi_p3_address[8]), + .D8 (main_a7ddrphy_dfi_p3_address[8]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[8]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_12 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_12 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[9]), - .D2(a7ddrphy_dfi_p0_address[9]), - .D3(a7ddrphy_dfi_p1_address[9]), - .D4(a7ddrphy_dfi_p1_address[9]), - .D5(a7ddrphy_dfi_p2_address[9]), - .D6(a7ddrphy_dfi_p2_address[9]), - .D7(a7ddrphy_dfi_p3_address[9]), - .D8(a7ddrphy_dfi_p3_address[9]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[9]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[9]), + .D2 (main_a7ddrphy_dfi_p0_address[9]), + .D3 (main_a7ddrphy_dfi_p1_address[9]), + .D4 (main_a7ddrphy_dfi_p1_address[9]), + .D5 (main_a7ddrphy_dfi_p2_address[9]), + .D6 (main_a7ddrphy_dfi_p2_address[9]), + .D7 (main_a7ddrphy_dfi_p3_address[9]), + .D8 (main_a7ddrphy_dfi_p3_address[9]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[9]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_13 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_13 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[10]), - .D2(a7ddrphy_dfi_p0_address[10]), - .D3(a7ddrphy_dfi_p1_address[10]), - .D4(a7ddrphy_dfi_p1_address[10]), - .D5(a7ddrphy_dfi_p2_address[10]), - .D6(a7ddrphy_dfi_p2_address[10]), - .D7(a7ddrphy_dfi_p3_address[10]), - .D8(a7ddrphy_dfi_p3_address[10]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[10]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[10]), + .D2 (main_a7ddrphy_dfi_p0_address[10]), + .D3 (main_a7ddrphy_dfi_p1_address[10]), + .D4 (main_a7ddrphy_dfi_p1_address[10]), + .D5 (main_a7ddrphy_dfi_p2_address[10]), + .D6 (main_a7ddrphy_dfi_p2_address[10]), + .D7 (main_a7ddrphy_dfi_p3_address[10]), + .D8 (main_a7ddrphy_dfi_p3_address[10]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[10]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_14 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_14 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[11]), - .D2(a7ddrphy_dfi_p0_address[11]), - .D3(a7ddrphy_dfi_p1_address[11]), - .D4(a7ddrphy_dfi_p1_address[11]), - .D5(a7ddrphy_dfi_p2_address[11]), - .D6(a7ddrphy_dfi_p2_address[11]), - .D7(a7ddrphy_dfi_p3_address[11]), - .D8(a7ddrphy_dfi_p3_address[11]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[11]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[11]), + .D2 (main_a7ddrphy_dfi_p0_address[11]), + .D3 (main_a7ddrphy_dfi_p1_address[11]), + .D4 (main_a7ddrphy_dfi_p1_address[11]), + .D5 (main_a7ddrphy_dfi_p2_address[11]), + .D6 (main_a7ddrphy_dfi_p2_address[11]), + .D7 (main_a7ddrphy_dfi_p3_address[11]), + .D8 (main_a7ddrphy_dfi_p3_address[11]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[11]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_15 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_15 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[12]), - .D2(a7ddrphy_dfi_p0_address[12]), - .D3(a7ddrphy_dfi_p1_address[12]), - .D4(a7ddrphy_dfi_p1_address[12]), - .D5(a7ddrphy_dfi_p2_address[12]), - .D6(a7ddrphy_dfi_p2_address[12]), - .D7(a7ddrphy_dfi_p3_address[12]), - .D8(a7ddrphy_dfi_p3_address[12]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[12]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[12]), + .D2 (main_a7ddrphy_dfi_p0_address[12]), + .D3 (main_a7ddrphy_dfi_p1_address[12]), + .D4 (main_a7ddrphy_dfi_p1_address[12]), + .D5 (main_a7ddrphy_dfi_p2_address[12]), + .D6 (main_a7ddrphy_dfi_p2_address[12]), + .D7 (main_a7ddrphy_dfi_p3_address[12]), + .D8 (main_a7ddrphy_dfi_p3_address[12]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[12]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_16 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_16 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[13]), - .D2(a7ddrphy_dfi_p0_address[13]), - .D3(a7ddrphy_dfi_p1_address[13]), - .D4(a7ddrphy_dfi_p1_address[13]), - .D5(a7ddrphy_dfi_p2_address[13]), - .D6(a7ddrphy_dfi_p2_address[13]), - .D7(a7ddrphy_dfi_p3_address[13]), - .D8(a7ddrphy_dfi_p3_address[13]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[13]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[13]), + .D2 (main_a7ddrphy_dfi_p0_address[13]), + .D3 (main_a7ddrphy_dfi_p1_address[13]), + .D4 (main_a7ddrphy_dfi_p1_address[13]), + .D5 (main_a7ddrphy_dfi_p2_address[13]), + .D6 (main_a7ddrphy_dfi_p2_address[13]), + .D7 (main_a7ddrphy_dfi_p3_address[13]), + .D8 (main_a7ddrphy_dfi_p3_address[13]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[13]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_17 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_17 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[14]), - .D2(a7ddrphy_dfi_p0_address[14]), - .D3(a7ddrphy_dfi_p1_address[14]), - .D4(a7ddrphy_dfi_p1_address[14]), - .D5(a7ddrphy_dfi_p2_address[14]), - .D6(a7ddrphy_dfi_p2_address[14]), - .D7(a7ddrphy_dfi_p3_address[14]), - .D8(a7ddrphy_dfi_p3_address[14]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[14]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[14]), + .D2 (main_a7ddrphy_dfi_p0_address[14]), + .D3 (main_a7ddrphy_dfi_p1_address[14]), + .D4 (main_a7ddrphy_dfi_p1_address[14]), + .D5 (main_a7ddrphy_dfi_p2_address[14]), + .D6 (main_a7ddrphy_dfi_p2_address[14]), + .D7 (main_a7ddrphy_dfi_p3_address[14]), + .D8 (main_a7ddrphy_dfi_p3_address[14]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[14]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_18 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_18 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_bank[0]), - .D2(a7ddrphy_dfi_p0_bank[0]), - .D3(a7ddrphy_dfi_p1_bank[0]), - .D4(a7ddrphy_dfi_p1_bank[0]), - .D5(a7ddrphy_dfi_p2_bank[0]), - .D6(a7ddrphy_dfi_p2_bank[0]), - .D7(a7ddrphy_dfi_p3_bank[0]), - .D8(a7ddrphy_dfi_p3_bank[0]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(a7ddrphy_pads_ba[0]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_bank[0]), + .D2 (main_a7ddrphy_dfi_p0_bank[0]), + .D3 (main_a7ddrphy_dfi_p1_bank[0]), + .D4 (main_a7ddrphy_dfi_p1_bank[0]), + .D5 (main_a7ddrphy_dfi_p2_bank[0]), + .D6 (main_a7ddrphy_dfi_p2_bank[0]), + .D7 (main_a7ddrphy_dfi_p3_bank[0]), + .D8 (main_a7ddrphy_dfi_p3_bank[0]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_a7ddrphy_pads_ba[0]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_19 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_19 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_bank[1]), - .D2(a7ddrphy_dfi_p0_bank[1]), - .D3(a7ddrphy_dfi_p1_bank[1]), - .D4(a7ddrphy_dfi_p1_bank[1]), - .D5(a7ddrphy_dfi_p2_bank[1]), - .D6(a7ddrphy_dfi_p2_bank[1]), - .D7(a7ddrphy_dfi_p3_bank[1]), - .D8(a7ddrphy_dfi_p3_bank[1]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(a7ddrphy_pads_ba[1]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_bank[1]), + .D2 (main_a7ddrphy_dfi_p0_bank[1]), + .D3 (main_a7ddrphy_dfi_p1_bank[1]), + .D4 (main_a7ddrphy_dfi_p1_bank[1]), + .D5 (main_a7ddrphy_dfi_p2_bank[1]), + .D6 (main_a7ddrphy_dfi_p2_bank[1]), + .D7 (main_a7ddrphy_dfi_p3_bank[1]), + .D8 (main_a7ddrphy_dfi_p3_bank[1]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_a7ddrphy_pads_ba[1]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_20 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_20 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_bank[2]), - .D2(a7ddrphy_dfi_p0_bank[2]), - .D3(a7ddrphy_dfi_p1_bank[2]), - .D4(a7ddrphy_dfi_p1_bank[2]), - .D5(a7ddrphy_dfi_p2_bank[2]), - .D6(a7ddrphy_dfi_p2_bank[2]), - .D7(a7ddrphy_dfi_p3_bank[2]), - .D8(a7ddrphy_dfi_p3_bank[2]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(a7ddrphy_pads_ba[2]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_bank[2]), + .D2 (main_a7ddrphy_dfi_p0_bank[2]), + .D3 (main_a7ddrphy_dfi_p1_bank[2]), + .D4 (main_a7ddrphy_dfi_p1_bank[2]), + .D5 (main_a7ddrphy_dfi_p2_bank[2]), + .D6 (main_a7ddrphy_dfi_p2_bank[2]), + .D7 (main_a7ddrphy_dfi_p3_bank[2]), + .D8 (main_a7ddrphy_dfi_p3_bank[2]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_a7ddrphy_pads_ba[2]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_21 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_21 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_ras_n), - .D2(a7ddrphy_dfi_p0_ras_n), - .D3(a7ddrphy_dfi_p1_ras_n), - .D4(a7ddrphy_dfi_p1_ras_n), - .D5(a7ddrphy_dfi_p2_ras_n), - .D6(a7ddrphy_dfi_p2_ras_n), - .D7(a7ddrphy_dfi_p3_ras_n), - .D8(a7ddrphy_dfi_p3_ras_n), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_ras_n) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_ras_n), + .D2 (main_a7ddrphy_dfi_p0_ras_n), + .D3 (main_a7ddrphy_dfi_p1_ras_n), + .D4 (main_a7ddrphy_dfi_p1_ras_n), + .D5 (main_a7ddrphy_dfi_p2_ras_n), + .D6 (main_a7ddrphy_dfi_p2_ras_n), + .D7 (main_a7ddrphy_dfi_p3_ras_n), + .D8 (main_a7ddrphy_dfi_p3_ras_n), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_ras_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_22 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_22 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_cas_n), - .D2(a7ddrphy_dfi_p0_cas_n), - .D3(a7ddrphy_dfi_p1_cas_n), - .D4(a7ddrphy_dfi_p1_cas_n), - .D5(a7ddrphy_dfi_p2_cas_n), - .D6(a7ddrphy_dfi_p2_cas_n), - .D7(a7ddrphy_dfi_p3_cas_n), - .D8(a7ddrphy_dfi_p3_cas_n), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_cas_n) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_cas_n), + .D2 (main_a7ddrphy_dfi_p0_cas_n), + .D3 (main_a7ddrphy_dfi_p1_cas_n), + .D4 (main_a7ddrphy_dfi_p1_cas_n), + .D5 (main_a7ddrphy_dfi_p2_cas_n), + .D6 (main_a7ddrphy_dfi_p2_cas_n), + .D7 (main_a7ddrphy_dfi_p3_cas_n), + .D8 (main_a7ddrphy_dfi_p3_cas_n), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_cas_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_23 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_23 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_we_n), - .D2(a7ddrphy_dfi_p0_we_n), - .D3(a7ddrphy_dfi_p1_we_n), - .D4(a7ddrphy_dfi_p1_we_n), - .D5(a7ddrphy_dfi_p2_we_n), - .D6(a7ddrphy_dfi_p2_we_n), - .D7(a7ddrphy_dfi_p3_we_n), - .D8(a7ddrphy_dfi_p3_we_n), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_we_n) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_we_n), + .D2 (main_a7ddrphy_dfi_p0_we_n), + .D3 (main_a7ddrphy_dfi_p1_we_n), + .D4 (main_a7ddrphy_dfi_p1_we_n), + .D5 (main_a7ddrphy_dfi_p2_we_n), + .D6 (main_a7ddrphy_dfi_p2_we_n), + .D7 (main_a7ddrphy_dfi_p3_we_n), + .D8 (main_a7ddrphy_dfi_p3_we_n), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_we_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_24 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_24 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_cke), - .D2(a7ddrphy_dfi_p0_cke), - .D3(a7ddrphy_dfi_p1_cke), - .D4(a7ddrphy_dfi_p1_cke), - .D5(a7ddrphy_dfi_p2_cke), - .D6(a7ddrphy_dfi_p2_cke), - .D7(a7ddrphy_dfi_p3_cke), - .D8(a7ddrphy_dfi_p3_cke), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_cke) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_cke), + .D2 (main_a7ddrphy_dfi_p0_cke), + .D3 (main_a7ddrphy_dfi_p1_cke), + .D4 (main_a7ddrphy_dfi_p1_cke), + .D5 (main_a7ddrphy_dfi_p2_cke), + .D6 (main_a7ddrphy_dfi_p2_cke), + .D7 (main_a7ddrphy_dfi_p3_cke), + .D8 (main_a7ddrphy_dfi_p3_cke), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_cke) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_25 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_25 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_odt), - .D2(a7ddrphy_dfi_p0_odt), - .D3(a7ddrphy_dfi_p1_odt), - .D4(a7ddrphy_dfi_p1_odt), - .D5(a7ddrphy_dfi_p2_odt), - .D6(a7ddrphy_dfi_p2_odt), - .D7(a7ddrphy_dfi_p3_odt), - .D8(a7ddrphy_dfi_p3_odt), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_odt) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_odt), + .D2 (main_a7ddrphy_dfi_p0_odt), + .D3 (main_a7ddrphy_dfi_p1_odt), + .D4 (main_a7ddrphy_dfi_p1_odt), + .D5 (main_a7ddrphy_dfi_p2_odt), + .D6 (main_a7ddrphy_dfi_p2_odt), + .D7 (main_a7ddrphy_dfi_p3_odt), + .D8 (main_a7ddrphy_dfi_p3_odt), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_odt) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_26 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_26 ( - .CLK(sys4x_dqs_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip00[0]), - .D2(a7ddrphy_bitslip00[1]), - .D3(a7ddrphy_bitslip00[2]), - .D4(a7ddrphy_bitslip00[3]), - .D5(a7ddrphy_bitslip00[4]), - .D6(a7ddrphy_bitslip00[5]), - .D7(a7ddrphy_bitslip00[6]), - .D8(a7ddrphy_bitslip00[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OFB(a7ddrphy0), - .OQ(a7ddrphy_dqs_o_no_delay0), - .TQ(a7ddrphy_dqs_t0) + // Inputs. + .CLK (sys4x_dqs_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip00[0]), + .D2 (main_a7ddrphy_bitslip00[1]), + .D3 (main_a7ddrphy_bitslip00[2]), + .D4 (main_a7ddrphy_bitslip00[3]), + .D5 (main_a7ddrphy_bitslip00[4]), + .D6 (main_a7ddrphy_bitslip00[5]), + .D7 (main_a7ddrphy_bitslip00[6]), + .D8 (main_a7ddrphy_bitslip00[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OFB (main_a7ddrphy0), + .OQ (main_a7ddrphy_dqs_o_no_delay0), + .TQ (main_a7ddrphy_dqs_t0) ); +//------------------------------------------------------------------------------ +// Instance IOBUFDS of IOBUFDS Module. +//------------------------------------------------------------------------------ IOBUFDS IOBUFDS( - .I(a7ddrphy_dqs_o_no_delay0), - .T(a7ddrphy_dqs_t0), - .IO(ddram_dqs_p[0]), - .IOB(ddram_dqs_n[0]) + // Inputs. + .I (main_a7ddrphy_dqs_o_no_delay0), + .T (main_a7ddrphy_dqs_t0), + + // InOuts. + .IO (ddram_dqs_p[0]), + .IOB (ddram_dqs_n[0]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_27 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_27 ( - .CLK(sys4x_dqs_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip10[0]), - .D2(a7ddrphy_bitslip10[1]), - .D3(a7ddrphy_bitslip10[2]), - .D4(a7ddrphy_bitslip10[3]), - .D5(a7ddrphy_bitslip10[4]), - .D6(a7ddrphy_bitslip10[5]), - .D7(a7ddrphy_bitslip10[6]), - .D8(a7ddrphy_bitslip10[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OFB(a7ddrphy1), - .OQ(a7ddrphy_dqs_o_no_delay1), - .TQ(a7ddrphy_dqs_t1) -); + // Inputs. + .CLK (sys4x_dqs_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip10[0]), + .D2 (main_a7ddrphy_bitslip10[1]), + .D3 (main_a7ddrphy_bitslip10[2]), + .D4 (main_a7ddrphy_bitslip10[3]), + .D5 (main_a7ddrphy_bitslip10[4]), + .D6 (main_a7ddrphy_bitslip10[5]), + .D7 (main_a7ddrphy_bitslip10[6]), + .D8 (main_a7ddrphy_bitslip10[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), -IOBUFDS IOBUFDS_1( - .I(a7ddrphy_dqs_o_no_delay1), - .T(a7ddrphy_dqs_t1), - .IO(ddram_dqs_p[1]), - .IOB(ddram_dqs_n[1]) + // Outputs. + .OFB (main_a7ddrphy1), + .OQ (main_a7ddrphy_dqs_o_no_delay1), + .TQ (main_a7ddrphy_dqs_t1) ); -OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) +//------------------------------------------------------------------------------ +// Instance IOBUFDS_1 of IOBUFDS Module. +//------------------------------------------------------------------------------ +IOBUFDS IOBUFDS_1( + // Inputs. + .I (main_a7ddrphy_dqs_o_no_delay1), + .T (main_a7ddrphy_dqs_t1), + + // InOuts. + .IO (ddram_dqs_p[1]), + .IOB (ddram_dqs_n[1]) +); + +//------------------------------------------------------------------------------ +// Instance OSERDESE2_28 of OSERDESE2 Module. +//------------------------------------------------------------------------------ +OSERDESE2 #( + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_28 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip01[0]), - .D2(a7ddrphy_bitslip01[1]), - .D3(a7ddrphy_bitslip01[2]), - .D4(a7ddrphy_bitslip01[3]), - .D5(a7ddrphy_bitslip01[4]), - .D6(a7ddrphy_bitslip01[5]), - .D7(a7ddrphy_bitslip01[6]), - .D8(a7ddrphy_bitslip01[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_dm[0]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip01[0]), + .D2 (main_a7ddrphy_bitslip01[1]), + .D3 (main_a7ddrphy_bitslip01[2]), + .D4 (main_a7ddrphy_bitslip01[3]), + .D5 (main_a7ddrphy_bitslip01[4]), + .D6 (main_a7ddrphy_bitslip01[5]), + .D7 (main_a7ddrphy_bitslip01[6]), + .D8 (main_a7ddrphy_bitslip01[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_dm[0]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_29 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_29 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip11[0]), - .D2(a7ddrphy_bitslip11[1]), - .D3(a7ddrphy_bitslip11[2]), - .D4(a7ddrphy_bitslip11[3]), - .D5(a7ddrphy_bitslip11[4]), - .D6(a7ddrphy_bitslip11[5]), - .D7(a7ddrphy_bitslip11[6]), - .D8(a7ddrphy_bitslip11[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_dm[1]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip11[0]), + .D2 (main_a7ddrphy_bitslip11[1]), + .D3 (main_a7ddrphy_bitslip11[2]), + .D4 (main_a7ddrphy_bitslip11[3]), + .D5 (main_a7ddrphy_bitslip11[4]), + .D6 (main_a7ddrphy_bitslip11[5]), + .D7 (main_a7ddrphy_bitslip11[6]), + .D8 (main_a7ddrphy_bitslip11[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_dm[1]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_30 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_30 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip02[0]), - .D2(a7ddrphy_bitslip02[1]), - .D3(a7ddrphy_bitslip02[2]), - .D4(a7ddrphy_bitslip02[3]), - .D5(a7ddrphy_bitslip02[4]), - .D6(a7ddrphy_bitslip02[5]), - .D7(a7ddrphy_bitslip02[6]), - .D8(a7ddrphy_bitslip02[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay0), - .TQ(a7ddrphy_dq_t0) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip02[0]), + .D2 (main_a7ddrphy_bitslip02[1]), + .D3 (main_a7ddrphy_bitslip02[2]), + .D4 (main_a7ddrphy_bitslip02[3]), + .D5 (main_a7ddrphy_bitslip02[4]), + .D6 (main_a7ddrphy_bitslip02[5]), + .D7 (main_a7ddrphy_bitslip02[6]), + .D8 (main_a7ddrphy_bitslip02[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay0), + .TQ (main_a7ddrphy_dq_t0) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed0), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip03[7]), - .Q2(a7ddrphy_bitslip03[6]), - .Q3(a7ddrphy_bitslip03[5]), - .Q4(a7ddrphy_bitslip03[4]), - .Q5(a7ddrphy_bitslip03[3]), - .Q6(a7ddrphy_bitslip03[2]), - .Q7(a7ddrphy_bitslip03[1]), - .Q8(a7ddrphy_bitslip03[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed0), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip03[7]), + .Q2 (main_a7ddrphy_bitslip03[6]), + .Q3 (main_a7ddrphy_bitslip03[5]), + .Q4 (main_a7ddrphy_bitslip03[4]), + .Q5 (main_a7ddrphy_bitslip03[3]), + .Q6 (main_a7ddrphy_bitslip03[2]), + .Q7 (main_a7ddrphy_bitslip03[1]), + .Q8 (main_a7ddrphy_bitslip03[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay0), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed0) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay0), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed0) ); +//------------------------------------------------------------------------------ +// Instance IOBUF of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF( - .I(a7ddrphy_dq_o_nodelay0), - .T(a7ddrphy_dq_t0), - .IO(ddram_dq[0]), - .O(a7ddrphy_dq_i_nodelay0) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay0), + .T (main_a7ddrphy_dq_t0), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay0), + + // InOuts. + .IO (ddram_dq[0]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_31 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_31 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip12[0]), - .D2(a7ddrphy_bitslip12[1]), - .D3(a7ddrphy_bitslip12[2]), - .D4(a7ddrphy_bitslip12[3]), - .D5(a7ddrphy_bitslip12[4]), - .D6(a7ddrphy_bitslip12[5]), - .D7(a7ddrphy_bitslip12[6]), - .D8(a7ddrphy_bitslip12[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay1), - .TQ(a7ddrphy_dq_t1) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip12[0]), + .D2 (main_a7ddrphy_bitslip12[1]), + .D3 (main_a7ddrphy_bitslip12[2]), + .D4 (main_a7ddrphy_bitslip12[3]), + .D5 (main_a7ddrphy_bitslip12[4]), + .D6 (main_a7ddrphy_bitslip12[5]), + .D7 (main_a7ddrphy_bitslip12[6]), + .D8 (main_a7ddrphy_bitslip12[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay1), + .TQ (main_a7ddrphy_dq_t1) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_1 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_1 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip13[7]), - .Q2(a7ddrphy_bitslip13[6]), - .Q3(a7ddrphy_bitslip13[5]), - .Q4(a7ddrphy_bitslip13[4]), - .Q5(a7ddrphy_bitslip13[3]), - .Q6(a7ddrphy_bitslip13[2]), - .Q7(a7ddrphy_bitslip13[1]), - .Q8(a7ddrphy_bitslip13[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip13[7]), + .Q2 (main_a7ddrphy_bitslip13[6]), + .Q3 (main_a7ddrphy_bitslip13[5]), + .Q4 (main_a7ddrphy_bitslip13[4]), + .Q5 (main_a7ddrphy_bitslip13[3]), + .Q6 (main_a7ddrphy_bitslip13[2]), + .Q7 (main_a7ddrphy_bitslip13[1]), + .Q8 (main_a7ddrphy_bitslip13[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_1 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_1 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay1), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed1) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay1), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed1) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_1 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_1( - .I(a7ddrphy_dq_o_nodelay1), - .T(a7ddrphy_dq_t1), - .IO(ddram_dq[1]), - .O(a7ddrphy_dq_i_nodelay1) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay1), + .T (main_a7ddrphy_dq_t1), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay1), + + // InOuts. + .IO (ddram_dq[1]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_32 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_32 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip20[0]), - .D2(a7ddrphy_bitslip20[1]), - .D3(a7ddrphy_bitslip20[2]), - .D4(a7ddrphy_bitslip20[3]), - .D5(a7ddrphy_bitslip20[4]), - .D6(a7ddrphy_bitslip20[5]), - .D7(a7ddrphy_bitslip20[6]), - .D8(a7ddrphy_bitslip20[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay2), - .TQ(a7ddrphy_dq_t2) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip20[0]), + .D2 (main_a7ddrphy_bitslip20[1]), + .D3 (main_a7ddrphy_bitslip20[2]), + .D4 (main_a7ddrphy_bitslip20[3]), + .D5 (main_a7ddrphy_bitslip20[4]), + .D6 (main_a7ddrphy_bitslip20[5]), + .D7 (main_a7ddrphy_bitslip20[6]), + .D8 (main_a7ddrphy_bitslip20[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay2), + .TQ (main_a7ddrphy_dq_t2) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_2 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_2 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed2), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip21[7]), - .Q2(a7ddrphy_bitslip21[6]), - .Q3(a7ddrphy_bitslip21[5]), - .Q4(a7ddrphy_bitslip21[4]), - .Q5(a7ddrphy_bitslip21[3]), - .Q6(a7ddrphy_bitslip21[2]), - .Q7(a7ddrphy_bitslip21[1]), - .Q8(a7ddrphy_bitslip21[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed2), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip21[7]), + .Q2 (main_a7ddrphy_bitslip21[6]), + .Q3 (main_a7ddrphy_bitslip21[5]), + .Q4 (main_a7ddrphy_bitslip21[4]), + .Q5 (main_a7ddrphy_bitslip21[3]), + .Q6 (main_a7ddrphy_bitslip21[2]), + .Q7 (main_a7ddrphy_bitslip21[1]), + .Q8 (main_a7ddrphy_bitslip21[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_2 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_2 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay2), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed2) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay2), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed2) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_2 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_2( - .I(a7ddrphy_dq_o_nodelay2), - .T(a7ddrphy_dq_t2), - .IO(ddram_dq[2]), - .O(a7ddrphy_dq_i_nodelay2) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay2), + .T (main_a7ddrphy_dq_t2), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay2), + + // InOuts. + .IO (ddram_dq[2]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_33 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_33 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip30[0]), - .D2(a7ddrphy_bitslip30[1]), - .D3(a7ddrphy_bitslip30[2]), - .D4(a7ddrphy_bitslip30[3]), - .D5(a7ddrphy_bitslip30[4]), - .D6(a7ddrphy_bitslip30[5]), - .D7(a7ddrphy_bitslip30[6]), - .D8(a7ddrphy_bitslip30[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay3), - .TQ(a7ddrphy_dq_t3) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip30[0]), + .D2 (main_a7ddrphy_bitslip30[1]), + .D3 (main_a7ddrphy_bitslip30[2]), + .D4 (main_a7ddrphy_bitslip30[3]), + .D5 (main_a7ddrphy_bitslip30[4]), + .D6 (main_a7ddrphy_bitslip30[5]), + .D7 (main_a7ddrphy_bitslip30[6]), + .D8 (main_a7ddrphy_bitslip30[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay3), + .TQ (main_a7ddrphy_dq_t3) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_3 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_3 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed3), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip31[7]), - .Q2(a7ddrphy_bitslip31[6]), - .Q3(a7ddrphy_bitslip31[5]), - .Q4(a7ddrphy_bitslip31[4]), - .Q5(a7ddrphy_bitslip31[3]), - .Q6(a7ddrphy_bitslip31[2]), - .Q7(a7ddrphy_bitslip31[1]), - .Q8(a7ddrphy_bitslip31[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed3), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip31[7]), + .Q2 (main_a7ddrphy_bitslip31[6]), + .Q3 (main_a7ddrphy_bitslip31[5]), + .Q4 (main_a7ddrphy_bitslip31[4]), + .Q5 (main_a7ddrphy_bitslip31[3]), + .Q6 (main_a7ddrphy_bitslip31[2]), + .Q7 (main_a7ddrphy_bitslip31[1]), + .Q8 (main_a7ddrphy_bitslip31[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_3 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_3 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay3), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed3) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay3), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed3) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_3 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_3( - .I(a7ddrphy_dq_o_nodelay3), - .T(a7ddrphy_dq_t3), - .IO(ddram_dq[3]), - .O(a7ddrphy_dq_i_nodelay3) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay3), + .T (main_a7ddrphy_dq_t3), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay3), + + // InOuts. + .IO (ddram_dq[3]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_34 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_34 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip40[0]), - .D2(a7ddrphy_bitslip40[1]), - .D3(a7ddrphy_bitslip40[2]), - .D4(a7ddrphy_bitslip40[3]), - .D5(a7ddrphy_bitslip40[4]), - .D6(a7ddrphy_bitslip40[5]), - .D7(a7ddrphy_bitslip40[6]), - .D8(a7ddrphy_bitslip40[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay4), - .TQ(a7ddrphy_dq_t4) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip40[0]), + .D2 (main_a7ddrphy_bitslip40[1]), + .D3 (main_a7ddrphy_bitslip40[2]), + .D4 (main_a7ddrphy_bitslip40[3]), + .D5 (main_a7ddrphy_bitslip40[4]), + .D6 (main_a7ddrphy_bitslip40[5]), + .D7 (main_a7ddrphy_bitslip40[6]), + .D8 (main_a7ddrphy_bitslip40[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay4), + .TQ (main_a7ddrphy_dq_t4) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_4 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_4 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed4), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip41[7]), - .Q2(a7ddrphy_bitslip41[6]), - .Q3(a7ddrphy_bitslip41[5]), - .Q4(a7ddrphy_bitslip41[4]), - .Q5(a7ddrphy_bitslip41[3]), - .Q6(a7ddrphy_bitslip41[2]), - .Q7(a7ddrphy_bitslip41[1]), - .Q8(a7ddrphy_bitslip41[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed4), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip41[7]), + .Q2 (main_a7ddrphy_bitslip41[6]), + .Q3 (main_a7ddrphy_bitslip41[5]), + .Q4 (main_a7ddrphy_bitslip41[4]), + .Q5 (main_a7ddrphy_bitslip41[3]), + .Q6 (main_a7ddrphy_bitslip41[2]), + .Q7 (main_a7ddrphy_bitslip41[1]), + .Q8 (main_a7ddrphy_bitslip41[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_4 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_4 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay4), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed4) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay4), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed4) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_4 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_4( - .I(a7ddrphy_dq_o_nodelay4), - .T(a7ddrphy_dq_t4), - .IO(ddram_dq[4]), - .O(a7ddrphy_dq_i_nodelay4) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay4), + .T (main_a7ddrphy_dq_t4), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay4), + + // InOuts. + .IO (ddram_dq[4]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_35 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_35 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip50[0]), - .D2(a7ddrphy_bitslip50[1]), - .D3(a7ddrphy_bitslip50[2]), - .D4(a7ddrphy_bitslip50[3]), - .D5(a7ddrphy_bitslip50[4]), - .D6(a7ddrphy_bitslip50[5]), - .D7(a7ddrphy_bitslip50[6]), - .D8(a7ddrphy_bitslip50[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay5), - .TQ(a7ddrphy_dq_t5) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip50[0]), + .D2 (main_a7ddrphy_bitslip50[1]), + .D3 (main_a7ddrphy_bitslip50[2]), + .D4 (main_a7ddrphy_bitslip50[3]), + .D5 (main_a7ddrphy_bitslip50[4]), + .D6 (main_a7ddrphy_bitslip50[5]), + .D7 (main_a7ddrphy_bitslip50[6]), + .D8 (main_a7ddrphy_bitslip50[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay5), + .TQ (main_a7ddrphy_dq_t5) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_5 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_5 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed5), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip51[7]), - .Q2(a7ddrphy_bitslip51[6]), - .Q3(a7ddrphy_bitslip51[5]), - .Q4(a7ddrphy_bitslip51[4]), - .Q5(a7ddrphy_bitslip51[3]), - .Q6(a7ddrphy_bitslip51[2]), - .Q7(a7ddrphy_bitslip51[1]), - .Q8(a7ddrphy_bitslip51[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed5), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip51[7]), + .Q2 (main_a7ddrphy_bitslip51[6]), + .Q3 (main_a7ddrphy_bitslip51[5]), + .Q4 (main_a7ddrphy_bitslip51[4]), + .Q5 (main_a7ddrphy_bitslip51[3]), + .Q6 (main_a7ddrphy_bitslip51[2]), + .Q7 (main_a7ddrphy_bitslip51[1]), + .Q8 (main_a7ddrphy_bitslip51[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_5 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_5 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay5), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed5) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay5), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed5) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_5 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_5( - .I(a7ddrphy_dq_o_nodelay5), - .T(a7ddrphy_dq_t5), - .IO(ddram_dq[5]), - .O(a7ddrphy_dq_i_nodelay5) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay5), + .T (main_a7ddrphy_dq_t5), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay5), + + // InOuts. + .IO (ddram_dq[5]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_36 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_36 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip60[0]), - .D2(a7ddrphy_bitslip60[1]), - .D3(a7ddrphy_bitslip60[2]), - .D4(a7ddrphy_bitslip60[3]), - .D5(a7ddrphy_bitslip60[4]), - .D6(a7ddrphy_bitslip60[5]), - .D7(a7ddrphy_bitslip60[6]), - .D8(a7ddrphy_bitslip60[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay6), - .TQ(a7ddrphy_dq_t6) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip60[0]), + .D2 (main_a7ddrphy_bitslip60[1]), + .D3 (main_a7ddrphy_bitslip60[2]), + .D4 (main_a7ddrphy_bitslip60[3]), + .D5 (main_a7ddrphy_bitslip60[4]), + .D6 (main_a7ddrphy_bitslip60[5]), + .D7 (main_a7ddrphy_bitslip60[6]), + .D8 (main_a7ddrphy_bitslip60[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay6), + .TQ (main_a7ddrphy_dq_t6) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_6 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_6 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed6), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip61[7]), - .Q2(a7ddrphy_bitslip61[6]), - .Q3(a7ddrphy_bitslip61[5]), - .Q4(a7ddrphy_bitslip61[4]), - .Q5(a7ddrphy_bitslip61[3]), - .Q6(a7ddrphy_bitslip61[2]), - .Q7(a7ddrphy_bitslip61[1]), - .Q8(a7ddrphy_bitslip61[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed6), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip61[7]), + .Q2 (main_a7ddrphy_bitslip61[6]), + .Q3 (main_a7ddrphy_bitslip61[5]), + .Q4 (main_a7ddrphy_bitslip61[4]), + .Q5 (main_a7ddrphy_bitslip61[3]), + .Q6 (main_a7ddrphy_bitslip61[2]), + .Q7 (main_a7ddrphy_bitslip61[1]), + .Q8 (main_a7ddrphy_bitslip61[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_6 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_6 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay6), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed6) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay6), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed6) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_6 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_6( - .I(a7ddrphy_dq_o_nodelay6), - .T(a7ddrphy_dq_t6), - .IO(ddram_dq[6]), - .O(a7ddrphy_dq_i_nodelay6) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay6), + .T (main_a7ddrphy_dq_t6), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay6), + + // InOuts. + .IO (ddram_dq[6]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_37 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_37 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip70[0]), - .D2(a7ddrphy_bitslip70[1]), - .D3(a7ddrphy_bitslip70[2]), - .D4(a7ddrphy_bitslip70[3]), - .D5(a7ddrphy_bitslip70[4]), - .D6(a7ddrphy_bitslip70[5]), - .D7(a7ddrphy_bitslip70[6]), - .D8(a7ddrphy_bitslip70[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay7), - .TQ(a7ddrphy_dq_t7) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip70[0]), + .D2 (main_a7ddrphy_bitslip70[1]), + .D3 (main_a7ddrphy_bitslip70[2]), + .D4 (main_a7ddrphy_bitslip70[3]), + .D5 (main_a7ddrphy_bitslip70[4]), + .D6 (main_a7ddrphy_bitslip70[5]), + .D7 (main_a7ddrphy_bitslip70[6]), + .D8 (main_a7ddrphy_bitslip70[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay7), + .TQ (main_a7ddrphy_dq_t7) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_7 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_7 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed7), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip71[7]), - .Q2(a7ddrphy_bitslip71[6]), - .Q3(a7ddrphy_bitslip71[5]), - .Q4(a7ddrphy_bitslip71[4]), - .Q5(a7ddrphy_bitslip71[3]), - .Q6(a7ddrphy_bitslip71[2]), - .Q7(a7ddrphy_bitslip71[1]), - .Q8(a7ddrphy_bitslip71[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed7), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip71[7]), + .Q2 (main_a7ddrphy_bitslip71[6]), + .Q3 (main_a7ddrphy_bitslip71[5]), + .Q4 (main_a7ddrphy_bitslip71[4]), + .Q5 (main_a7ddrphy_bitslip71[3]), + .Q6 (main_a7ddrphy_bitslip71[2]), + .Q7 (main_a7ddrphy_bitslip71[1]), + .Q8 (main_a7ddrphy_bitslip71[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_7 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_7 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay7), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed7) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay7), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed7) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_7 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_7( - .I(a7ddrphy_dq_o_nodelay7), - .T(a7ddrphy_dq_t7), - .IO(ddram_dq[7]), - .O(a7ddrphy_dq_i_nodelay7) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay7), + .T (main_a7ddrphy_dq_t7), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay7), + + // InOuts. + .IO (ddram_dq[7]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_38 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_38 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip80[0]), - .D2(a7ddrphy_bitslip80[1]), - .D3(a7ddrphy_bitslip80[2]), - .D4(a7ddrphy_bitslip80[3]), - .D5(a7ddrphy_bitslip80[4]), - .D6(a7ddrphy_bitslip80[5]), - .D7(a7ddrphy_bitslip80[6]), - .D8(a7ddrphy_bitslip80[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay8), - .TQ(a7ddrphy_dq_t8) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip80[0]), + .D2 (main_a7ddrphy_bitslip80[1]), + .D3 (main_a7ddrphy_bitslip80[2]), + .D4 (main_a7ddrphy_bitslip80[3]), + .D5 (main_a7ddrphy_bitslip80[4]), + .D6 (main_a7ddrphy_bitslip80[5]), + .D7 (main_a7ddrphy_bitslip80[6]), + .D8 (main_a7ddrphy_bitslip80[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay8), + .TQ (main_a7ddrphy_dq_t8) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_8 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_8 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed8), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip81[7]), - .Q2(a7ddrphy_bitslip81[6]), - .Q3(a7ddrphy_bitslip81[5]), - .Q4(a7ddrphy_bitslip81[4]), - .Q5(a7ddrphy_bitslip81[3]), - .Q6(a7ddrphy_bitslip81[2]), - .Q7(a7ddrphy_bitslip81[1]), - .Q8(a7ddrphy_bitslip81[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed8), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip81[7]), + .Q2 (main_a7ddrphy_bitslip81[6]), + .Q3 (main_a7ddrphy_bitslip81[5]), + .Q4 (main_a7ddrphy_bitslip81[4]), + .Q5 (main_a7ddrphy_bitslip81[3]), + .Q6 (main_a7ddrphy_bitslip81[2]), + .Q7 (main_a7ddrphy_bitslip81[1]), + .Q8 (main_a7ddrphy_bitslip81[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_8 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_8 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay8), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed8) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay8), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed8) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_8 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_8( - .I(a7ddrphy_dq_o_nodelay8), - .T(a7ddrphy_dq_t8), - .IO(ddram_dq[8]), - .O(a7ddrphy_dq_i_nodelay8) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay8), + .T (main_a7ddrphy_dq_t8), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay8), + + // InOuts. + .IO (ddram_dq[8]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_39 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_39 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip90[0]), - .D2(a7ddrphy_bitslip90[1]), - .D3(a7ddrphy_bitslip90[2]), - .D4(a7ddrphy_bitslip90[3]), - .D5(a7ddrphy_bitslip90[4]), - .D6(a7ddrphy_bitslip90[5]), - .D7(a7ddrphy_bitslip90[6]), - .D8(a7ddrphy_bitslip90[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay9), - .TQ(a7ddrphy_dq_t9) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip90[0]), + .D2 (main_a7ddrphy_bitslip90[1]), + .D3 (main_a7ddrphy_bitslip90[2]), + .D4 (main_a7ddrphy_bitslip90[3]), + .D5 (main_a7ddrphy_bitslip90[4]), + .D6 (main_a7ddrphy_bitslip90[5]), + .D7 (main_a7ddrphy_bitslip90[6]), + .D8 (main_a7ddrphy_bitslip90[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay9), + .TQ (main_a7ddrphy_dq_t9) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_9 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_9 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed9), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip91[7]), - .Q2(a7ddrphy_bitslip91[6]), - .Q3(a7ddrphy_bitslip91[5]), - .Q4(a7ddrphy_bitslip91[4]), - .Q5(a7ddrphy_bitslip91[3]), - .Q6(a7ddrphy_bitslip91[2]), - .Q7(a7ddrphy_bitslip91[1]), - .Q8(a7ddrphy_bitslip91[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed9), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip91[7]), + .Q2 (main_a7ddrphy_bitslip91[6]), + .Q3 (main_a7ddrphy_bitslip91[5]), + .Q4 (main_a7ddrphy_bitslip91[4]), + .Q5 (main_a7ddrphy_bitslip91[3]), + .Q6 (main_a7ddrphy_bitslip91[2]), + .Q7 (main_a7ddrphy_bitslip91[1]), + .Q8 (main_a7ddrphy_bitslip91[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_9 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_9 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay9), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed9) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay9), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed9) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_9 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_9( - .I(a7ddrphy_dq_o_nodelay9), - .T(a7ddrphy_dq_t9), - .IO(ddram_dq[9]), - .O(a7ddrphy_dq_i_nodelay9) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay9), + .T (main_a7ddrphy_dq_t9), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay9), + + // InOuts. + .IO (ddram_dq[9]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_40 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_40 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip100[0]), - .D2(a7ddrphy_bitslip100[1]), - .D3(a7ddrphy_bitslip100[2]), - .D4(a7ddrphy_bitslip100[3]), - .D5(a7ddrphy_bitslip100[4]), - .D6(a7ddrphy_bitslip100[5]), - .D7(a7ddrphy_bitslip100[6]), - .D8(a7ddrphy_bitslip100[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay10), - .TQ(a7ddrphy_dq_t10) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip100[0]), + .D2 (main_a7ddrphy_bitslip100[1]), + .D3 (main_a7ddrphy_bitslip100[2]), + .D4 (main_a7ddrphy_bitslip100[3]), + .D5 (main_a7ddrphy_bitslip100[4]), + .D6 (main_a7ddrphy_bitslip100[5]), + .D7 (main_a7ddrphy_bitslip100[6]), + .D8 (main_a7ddrphy_bitslip100[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay10), + .TQ (main_a7ddrphy_dq_t10) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_10 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_10 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed10), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip101[7]), - .Q2(a7ddrphy_bitslip101[6]), - .Q3(a7ddrphy_bitslip101[5]), - .Q4(a7ddrphy_bitslip101[4]), - .Q5(a7ddrphy_bitslip101[3]), - .Q6(a7ddrphy_bitslip101[2]), - .Q7(a7ddrphy_bitslip101[1]), - .Q8(a7ddrphy_bitslip101[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed10), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip101[7]), + .Q2 (main_a7ddrphy_bitslip101[6]), + .Q3 (main_a7ddrphy_bitslip101[5]), + .Q4 (main_a7ddrphy_bitslip101[4]), + .Q5 (main_a7ddrphy_bitslip101[3]), + .Q6 (main_a7ddrphy_bitslip101[2]), + .Q7 (main_a7ddrphy_bitslip101[1]), + .Q8 (main_a7ddrphy_bitslip101[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_10 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_10 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay10), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed10) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay10), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed10) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_10 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_10( - .I(a7ddrphy_dq_o_nodelay10), - .T(a7ddrphy_dq_t10), - .IO(ddram_dq[10]), - .O(a7ddrphy_dq_i_nodelay10) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay10), + .T (main_a7ddrphy_dq_t10), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay10), + + // InOuts. + .IO (ddram_dq[10]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_41 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_41 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip110[0]), - .D2(a7ddrphy_bitslip110[1]), - .D3(a7ddrphy_bitslip110[2]), - .D4(a7ddrphy_bitslip110[3]), - .D5(a7ddrphy_bitslip110[4]), - .D6(a7ddrphy_bitslip110[5]), - .D7(a7ddrphy_bitslip110[6]), - .D8(a7ddrphy_bitslip110[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay11), - .TQ(a7ddrphy_dq_t11) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip110[0]), + .D2 (main_a7ddrphy_bitslip110[1]), + .D3 (main_a7ddrphy_bitslip110[2]), + .D4 (main_a7ddrphy_bitslip110[3]), + .D5 (main_a7ddrphy_bitslip110[4]), + .D6 (main_a7ddrphy_bitslip110[5]), + .D7 (main_a7ddrphy_bitslip110[6]), + .D8 (main_a7ddrphy_bitslip110[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay11), + .TQ (main_a7ddrphy_dq_t11) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_11 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_11 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed11), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip111[7]), - .Q2(a7ddrphy_bitslip111[6]), - .Q3(a7ddrphy_bitslip111[5]), - .Q4(a7ddrphy_bitslip111[4]), - .Q5(a7ddrphy_bitslip111[3]), - .Q6(a7ddrphy_bitslip111[2]), - .Q7(a7ddrphy_bitslip111[1]), - .Q8(a7ddrphy_bitslip111[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed11), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip111[7]), + .Q2 (main_a7ddrphy_bitslip111[6]), + .Q3 (main_a7ddrphy_bitslip111[5]), + .Q4 (main_a7ddrphy_bitslip111[4]), + .Q5 (main_a7ddrphy_bitslip111[3]), + .Q6 (main_a7ddrphy_bitslip111[2]), + .Q7 (main_a7ddrphy_bitslip111[1]), + .Q8 (main_a7ddrphy_bitslip111[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_11 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_11 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay11), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed11) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay11), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed11) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_11 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_11( - .I(a7ddrphy_dq_o_nodelay11), - .T(a7ddrphy_dq_t11), - .IO(ddram_dq[11]), - .O(a7ddrphy_dq_i_nodelay11) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay11), + .T (main_a7ddrphy_dq_t11), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay11), + + // InOuts. + .IO (ddram_dq[11]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_42 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_42 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip120[0]), - .D2(a7ddrphy_bitslip120[1]), - .D3(a7ddrphy_bitslip120[2]), - .D4(a7ddrphy_bitslip120[3]), - .D5(a7ddrphy_bitslip120[4]), - .D6(a7ddrphy_bitslip120[5]), - .D7(a7ddrphy_bitslip120[6]), - .D8(a7ddrphy_bitslip120[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay12), - .TQ(a7ddrphy_dq_t12) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip120[0]), + .D2 (main_a7ddrphy_bitslip120[1]), + .D3 (main_a7ddrphy_bitslip120[2]), + .D4 (main_a7ddrphy_bitslip120[3]), + .D5 (main_a7ddrphy_bitslip120[4]), + .D6 (main_a7ddrphy_bitslip120[5]), + .D7 (main_a7ddrphy_bitslip120[6]), + .D8 (main_a7ddrphy_bitslip120[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay12), + .TQ (main_a7ddrphy_dq_t12) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_12 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_12 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed12), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip121[7]), - .Q2(a7ddrphy_bitslip121[6]), - .Q3(a7ddrphy_bitslip121[5]), - .Q4(a7ddrphy_bitslip121[4]), - .Q5(a7ddrphy_bitslip121[3]), - .Q6(a7ddrphy_bitslip121[2]), - .Q7(a7ddrphy_bitslip121[1]), - .Q8(a7ddrphy_bitslip121[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed12), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip121[7]), + .Q2 (main_a7ddrphy_bitslip121[6]), + .Q3 (main_a7ddrphy_bitslip121[5]), + .Q4 (main_a7ddrphy_bitslip121[4]), + .Q5 (main_a7ddrphy_bitslip121[3]), + .Q6 (main_a7ddrphy_bitslip121[2]), + .Q7 (main_a7ddrphy_bitslip121[1]), + .Q8 (main_a7ddrphy_bitslip121[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_12 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_12 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay12), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed12) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay12), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed12) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_12 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_12( - .I(a7ddrphy_dq_o_nodelay12), - .T(a7ddrphy_dq_t12), - .IO(ddram_dq[12]), - .O(a7ddrphy_dq_i_nodelay12) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay12), + .T (main_a7ddrphy_dq_t12), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay12), + + // InOuts. + .IO (ddram_dq[12]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_43 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_43 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip130[0]), - .D2(a7ddrphy_bitslip130[1]), - .D3(a7ddrphy_bitslip130[2]), - .D4(a7ddrphy_bitslip130[3]), - .D5(a7ddrphy_bitslip130[4]), - .D6(a7ddrphy_bitslip130[5]), - .D7(a7ddrphy_bitslip130[6]), - .D8(a7ddrphy_bitslip130[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay13), - .TQ(a7ddrphy_dq_t13) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip130[0]), + .D2 (main_a7ddrphy_bitslip130[1]), + .D3 (main_a7ddrphy_bitslip130[2]), + .D4 (main_a7ddrphy_bitslip130[3]), + .D5 (main_a7ddrphy_bitslip130[4]), + .D6 (main_a7ddrphy_bitslip130[5]), + .D7 (main_a7ddrphy_bitslip130[6]), + .D8 (main_a7ddrphy_bitslip130[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay13), + .TQ (main_a7ddrphy_dq_t13) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_13 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_13 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed13), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip131[7]), - .Q2(a7ddrphy_bitslip131[6]), - .Q3(a7ddrphy_bitslip131[5]), - .Q4(a7ddrphy_bitslip131[4]), - .Q5(a7ddrphy_bitslip131[3]), - .Q6(a7ddrphy_bitslip131[2]), - .Q7(a7ddrphy_bitslip131[1]), - .Q8(a7ddrphy_bitslip131[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed13), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip131[7]), + .Q2 (main_a7ddrphy_bitslip131[6]), + .Q3 (main_a7ddrphy_bitslip131[5]), + .Q4 (main_a7ddrphy_bitslip131[4]), + .Q5 (main_a7ddrphy_bitslip131[3]), + .Q6 (main_a7ddrphy_bitslip131[2]), + .Q7 (main_a7ddrphy_bitslip131[1]), + .Q8 (main_a7ddrphy_bitslip131[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_13 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_13 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay13), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed13) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay13), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed13) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_13 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_13( - .I(a7ddrphy_dq_o_nodelay13), - .T(a7ddrphy_dq_t13), - .IO(ddram_dq[13]), - .O(a7ddrphy_dq_i_nodelay13) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay13), + .T (main_a7ddrphy_dq_t13), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay13), + + // InOuts. + .IO (ddram_dq[13]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_44 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_44 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip140[0]), - .D2(a7ddrphy_bitslip140[1]), - .D3(a7ddrphy_bitslip140[2]), - .D4(a7ddrphy_bitslip140[3]), - .D5(a7ddrphy_bitslip140[4]), - .D6(a7ddrphy_bitslip140[5]), - .D7(a7ddrphy_bitslip140[6]), - .D8(a7ddrphy_bitslip140[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay14), - .TQ(a7ddrphy_dq_t14) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip140[0]), + .D2 (main_a7ddrphy_bitslip140[1]), + .D3 (main_a7ddrphy_bitslip140[2]), + .D4 (main_a7ddrphy_bitslip140[3]), + .D5 (main_a7ddrphy_bitslip140[4]), + .D6 (main_a7ddrphy_bitslip140[5]), + .D7 (main_a7ddrphy_bitslip140[6]), + .D8 (main_a7ddrphy_bitslip140[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay14), + .TQ (main_a7ddrphy_dq_t14) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_14 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_14 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed14), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip141[7]), - .Q2(a7ddrphy_bitslip141[6]), - .Q3(a7ddrphy_bitslip141[5]), - .Q4(a7ddrphy_bitslip141[4]), - .Q5(a7ddrphy_bitslip141[3]), - .Q6(a7ddrphy_bitslip141[2]), - .Q7(a7ddrphy_bitslip141[1]), - .Q8(a7ddrphy_bitslip141[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed14), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip141[7]), + .Q2 (main_a7ddrphy_bitslip141[6]), + .Q3 (main_a7ddrphy_bitslip141[5]), + .Q4 (main_a7ddrphy_bitslip141[4]), + .Q5 (main_a7ddrphy_bitslip141[3]), + .Q6 (main_a7ddrphy_bitslip141[2]), + .Q7 (main_a7ddrphy_bitslip141[1]), + .Q8 (main_a7ddrphy_bitslip141[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_14 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_14 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay14), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed14) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay14), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed14) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_14 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_14( - .I(a7ddrphy_dq_o_nodelay14), - .T(a7ddrphy_dq_t14), - .IO(ddram_dq[14]), - .O(a7ddrphy_dq_i_nodelay14) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay14), + .T (main_a7ddrphy_dq_t14), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay14), + + // InOuts. + .IO (ddram_dq[14]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_45 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_45 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip150[0]), - .D2(a7ddrphy_bitslip150[1]), - .D3(a7ddrphy_bitslip150[2]), - .D4(a7ddrphy_bitslip150[3]), - .D5(a7ddrphy_bitslip150[4]), - .D6(a7ddrphy_bitslip150[5]), - .D7(a7ddrphy_bitslip150[6]), - .D8(a7ddrphy_bitslip150[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay15), - .TQ(a7ddrphy_dq_t15) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip150[0]), + .D2 (main_a7ddrphy_bitslip150[1]), + .D3 (main_a7ddrphy_bitslip150[2]), + .D4 (main_a7ddrphy_bitslip150[3]), + .D5 (main_a7ddrphy_bitslip150[4]), + .D6 (main_a7ddrphy_bitslip150[5]), + .D7 (main_a7ddrphy_bitslip150[6]), + .D8 (main_a7ddrphy_bitslip150[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay15), + .TQ (main_a7ddrphy_dq_t15) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_15 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_15 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed15), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip151[7]), - .Q2(a7ddrphy_bitslip151[6]), - .Q3(a7ddrphy_bitslip151[5]), - .Q4(a7ddrphy_bitslip151[4]), - .Q5(a7ddrphy_bitslip151[3]), - .Q6(a7ddrphy_bitslip151[2]), - .Q7(a7ddrphy_bitslip151[1]), - .Q8(a7ddrphy_bitslip151[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed15), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip151[7]), + .Q2 (main_a7ddrphy_bitslip151[6]), + .Q3 (main_a7ddrphy_bitslip151[5]), + .Q4 (main_a7ddrphy_bitslip151[4]), + .Q5 (main_a7ddrphy_bitslip151[3]), + .Q6 (main_a7ddrphy_bitslip151[2]), + .Q7 (main_a7ddrphy_bitslip151[1]), + .Q8 (main_a7ddrphy_bitslip151[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_15 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_15 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay15), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed15) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay15), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed15) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_15 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_15( - .I(a7ddrphy_dq_o_nodelay15), - .T(a7ddrphy_dq_t15), - .IO(ddram_dq[15]), - .O(a7ddrphy_dq_i_nodelay15) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay15), + .T (main_a7ddrphy_dq_t15), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay15), + + // InOuts. + .IO (ddram_dq[15]) ); //------------------------------------------------------------------------------ @@ -16053,14 +17189,14 @@ IOBUF IOBUF_15( reg [24:0] storage[0:15]; reg [24:0] storage_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine0_wrport_we) - storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w; - storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr]; + if (main_litedramcore_bankmachine0_wrport_we) + storage[main_litedramcore_bankmachine0_wrport_adr] <= main_litedramcore_bankmachine0_wrport_dat_w; + storage_dat0 <= storage[main_litedramcore_bankmachine0_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0; -assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr]; +assign main_litedramcore_bankmachine0_wrport_dat_r = storage_dat0; +assign main_litedramcore_bankmachine0_rdport_dat_r = storage[main_litedramcore_bankmachine0_rdport_adr]; //------------------------------------------------------------------------------ @@ -16071,14 +17207,14 @@ assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine reg [24:0] storage_1[0:15]; reg [24:0] storage_1_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine1_wrport_we) - storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w; - storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr]; + if (main_litedramcore_bankmachine1_wrport_we) + storage_1[main_litedramcore_bankmachine1_wrport_adr] <= main_litedramcore_bankmachine1_wrport_dat_w; + storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0; -assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr]; +assign main_litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0; +assign main_litedramcore_bankmachine1_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_rdport_adr]; //------------------------------------------------------------------------------ @@ -16089,14 +17225,14 @@ assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachi reg [24:0] storage_2[0:15]; reg [24:0] storage_2_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine2_wrport_we) - storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w; - storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr]; + if (main_litedramcore_bankmachine2_wrport_we) + storage_2[main_litedramcore_bankmachine2_wrport_adr] <= main_litedramcore_bankmachine2_wrport_dat_w; + storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0; -assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr]; +assign main_litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0; +assign main_litedramcore_bankmachine2_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_rdport_adr]; //------------------------------------------------------------------------------ @@ -16107,14 +17243,14 @@ assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachi reg [24:0] storage_3[0:15]; reg [24:0] storage_3_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine3_wrport_we) - storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w; - storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr]; + if (main_litedramcore_bankmachine3_wrport_we) + storage_3[main_litedramcore_bankmachine3_wrport_adr] <= main_litedramcore_bankmachine3_wrport_dat_w; + storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0; -assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr]; +assign main_litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0; +assign main_litedramcore_bankmachine3_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_rdport_adr]; //------------------------------------------------------------------------------ @@ -16125,14 +17261,14 @@ assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachi reg [24:0] storage_4[0:15]; reg [24:0] storage_4_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine4_wrport_we) - storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w; - storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr]; + if (main_litedramcore_bankmachine4_wrport_we) + storage_4[main_litedramcore_bankmachine4_wrport_adr] <= main_litedramcore_bankmachine4_wrport_dat_w; + storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0; -assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr]; +assign main_litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0; +assign main_litedramcore_bankmachine4_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_rdport_adr]; //------------------------------------------------------------------------------ @@ -16143,14 +17279,14 @@ assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachi reg [24:0] storage_5[0:15]; reg [24:0] storage_5_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine5_wrport_we) - storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w; - storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr]; + if (main_litedramcore_bankmachine5_wrport_we) + storage_5[main_litedramcore_bankmachine5_wrport_adr] <= main_litedramcore_bankmachine5_wrport_dat_w; + storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0; -assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr]; +assign main_litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0; +assign main_litedramcore_bankmachine5_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_rdport_adr]; //------------------------------------------------------------------------------ @@ -16161,14 +17297,14 @@ assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachi reg [24:0] storage_6[0:15]; reg [24:0] storage_6_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine6_wrport_we) - storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w; - storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr]; + if (main_litedramcore_bankmachine6_wrport_we) + storage_6[main_litedramcore_bankmachine6_wrport_adr] <= main_litedramcore_bankmachine6_wrport_dat_w; + storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0; -assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr]; +assign main_litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0; +assign main_litedramcore_bankmachine6_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_rdport_adr]; //------------------------------------------------------------------------------ @@ -16179,197 +17315,308 @@ assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachi reg [24:0] storage_7[0:15]; reg [24:0] storage_7_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine7_wrport_we) - storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w; - storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr]; + if (main_litedramcore_bankmachine7_wrport_we) + storage_7[main_litedramcore_bankmachine7_wrport_adr] <= main_litedramcore_bankmachine7_wrport_dat_w; + storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0; -assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr]; +assign main_litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0; +assign main_litedramcore_bankmachine7_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_rdport_adr]; +//------------------------------------------------------------------------------ +// Instance FDCE of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(reset), - .Q(litedramcore_reset0) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (main_reset), + + // Outputs. + .Q (builder_reset0) ); +//------------------------------------------------------------------------------ +// Instance FDCE_1 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_1( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset0), - .Q(litedramcore_reset1) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset0), + + // Outputs. + .Q (builder_reset1) ); +//------------------------------------------------------------------------------ +// Instance FDCE_2 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_2( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset1), - .Q(litedramcore_reset2) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset1), + + // Outputs. + .Q (builder_reset2) ); +//------------------------------------------------------------------------------ +// Instance FDCE_3 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_3( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset2), - .Q(litedramcore_reset3) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset2), + + // Outputs. + .Q (builder_reset3) ); +//------------------------------------------------------------------------------ +// Instance FDCE_4 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_4( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset3), - .Q(litedramcore_reset4) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset3), + + // Outputs. + .Q (builder_reset4) ); +//------------------------------------------------------------------------------ +// Instance FDCE_5 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_5( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset4), - .Q(litedramcore_reset5) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset4), + + // Outputs. + .Q (builder_reset5) ); +//------------------------------------------------------------------------------ +// Instance FDCE_6 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_6( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset5), - .Q(litedramcore_reset6) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset5), + + // Outputs. + .Q (builder_reset6) ); +//------------------------------------------------------------------------------ +// Instance FDCE_7 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_7( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset6), - .Q(litedramcore_reset7) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset6), + + // Outputs. + .Q (builder_reset7) ); +//------------------------------------------------------------------------------ +// Instance PLLE2_ADV of PLLE2_ADV Module. +//------------------------------------------------------------------------------ PLLE2_ADV #( - .CLKFBOUT_MULT(5'd16), - .CLKIN1_PERIOD(10.0), - .CLKOUT0_DIVIDE(4'd8), - .CLKOUT0_PHASE(1'd0), - .CLKOUT1_DIVIDE(5'd16), - .CLKOUT1_PHASE(1'd0), - .CLKOUT2_DIVIDE(3'd4), - .CLKOUT2_PHASE(1'd0), - .CLKOUT3_DIVIDE(3'd4), - .CLKOUT3_PHASE(7'd90), - .DIVCLK_DIVIDE(1'd1), - .REF_JITTER1(0.01), - .STARTUP_WAIT("FALSE") + // Parameters. + .CLKFBOUT_MULT (5'd16), + .CLKIN1_PERIOD (10.0), + .CLKOUT0_DIVIDE (4'd8), + .CLKOUT0_PHASE (1'd0), + .CLKOUT1_DIVIDE (5'd16), + .CLKOUT1_PHASE (1'd0), + .CLKOUT2_DIVIDE (3'd4), + .CLKOUT2_PHASE (1'd0), + .CLKOUT3_DIVIDE (3'd4), + .CLKOUT3_PHASE (7'd90), + .DIVCLK_DIVIDE (1'd1), + .REF_JITTER1 (0.01), + .STARTUP_WAIT ("FALSE") ) PLLE2_ADV ( - .CLKFBIN(litedramcore_pll_fb), - .CLKIN1(clkin), - .PWRDWN(power_down), - .RST(litedramcore_reset7), - .CLKFBOUT(litedramcore_pll_fb), - .CLKOUT0(clkout0), - .CLKOUT1(clkout1), - .CLKOUT2(clkout2), - .CLKOUT3(clkout3), - .LOCKED(locked) + // Inputs. + .CLKFBIN (builder_pll_fb), + .CLKIN1 (main_clkin), + .PWRDWN (main_power_down), + .RST (builder_reset7), + + // Outputs. + .CLKFBOUT (builder_pll_fb), + .CLKOUT0 (main_clkout0), + .CLKOUT1 (main_clkout1), + .CLKOUT2 (main_clkout2), + .CLKOUT3 (main_clkout3), + .LOCKED (main_locked) ); (* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE ( - .C(iodelay_clk), - .CE(1'd1), - .D(1'd0), - .PRE(xilinxasyncresetsynchronizerimpl0), - .Q(xilinxasyncresetsynchronizerimpl0_rst_meta) + // Inputs. + .C (iodelay_clk), + .CE (1'd1), + .D (1'd0), + .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl0_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_1 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_1 ( - .C(iodelay_clk), - .CE(1'd1), - .D(xilinxasyncresetsynchronizerimpl0_rst_meta), - .PRE(xilinxasyncresetsynchronizerimpl0), - .Q(iodelay_rst) + // Inputs. + .C (iodelay_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl0_rst_meta), + .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + + // Outputs. + .Q (iodelay_rst) ); (* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_2 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_2 ( - .C(sys_clk), - .CE(1'd1), - .D(1'd0), - .PRE(xilinxasyncresetsynchronizerimpl1), - .Q(xilinxasyncresetsynchronizerimpl1_rst_meta) + // Inputs. + .C (sys_clk), + .CE (1'd1), + .D (1'd0), + .PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl1_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_3 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_3 ( - .C(sys_clk), - .CE(1'd1), - .D(xilinxasyncresetsynchronizerimpl1_rst_meta), - .PRE(xilinxasyncresetsynchronizerimpl1), - .Q(sys_rst) + // Inputs. + .C (sys_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl1_rst_meta), + .PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset), + + // Outputs. + .Q (sys_rst) ); (* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_4 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_4 ( - .C(sys4x_clk), - .CE(1'd1), - .D(1'd0), - .PRE(xilinxasyncresetsynchronizerimpl2), - .Q(xilinxasyncresetsynchronizerimpl2_rst_meta) + // Inputs. + .C (sys4x_clk), + .CE (1'd1), + .D (1'd0), + .PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl2_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_5 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_5 ( - .C(sys4x_clk), - .CE(1'd1), - .D(xilinxasyncresetsynchronizerimpl2_rst_meta), - .PRE(xilinxasyncresetsynchronizerimpl2), - .Q(xilinxasyncresetsynchronizerimpl2_expr) + // Inputs. + .C (sys4x_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl2_rst_meta), + .PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl2_expr) ); (* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_6 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_6 ( - .C(sys4x_dqs_clk), - .CE(1'd1), - .D(1'd0), - .PRE(xilinxasyncresetsynchronizerimpl3), - .Q(xilinxasyncresetsynchronizerimpl3_rst_meta) + // Inputs. + .C (sys4x_dqs_clk), + .CE (1'd1), + .D (1'd0), + .PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl3_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_7 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_7 ( - .C(sys4x_dqs_clk), - .CE(1'd1), - .D(xilinxasyncresetsynchronizerimpl3_rst_meta), - .PRE(xilinxasyncresetsynchronizerimpl3), - .Q(xilinxasyncresetsynchronizerimpl3_expr) + // Inputs. + .C (sys4x_dqs_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl3_rst_meta), + .PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl3_expr) ); endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2022-10-28 19:01:20. +// Auto-Generated by LiteX on 2024-04-01 10:12:07. //------------------------------------------------------------------------------ diff --git a/litedram/generated/orangecrab-85-0.2/litedram_core.init b/litedram/generated/orangecrab-85-0.2/litedram_core.init index 2a3035b..51e4b9f 100644 --- a/litedram/generated/orangecrab-85-0.2/litedram_core.init +++ b/litedram/generated/orangecrab-85-0.2/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ff00782107c6 3d80000060215f00 798c07c6618c0000 -618c10e0658cff00 +618c10d4658cff00 4e8004217d8903a6 4e8004207c6903a6 0000000000000000 @@ -510,928 +510,949 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -392000003d40c000 -794a0020614a6004 -7d2057aa7c0004ac +3920000039406004 +7c0004ac654ac000 +600000007d2057aa 6000000060000000 6000000060000000 -4e80002060000000 +000000004e800020 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52445320676e697a 3025783040204d41 000a2e2e2e786c38 +000000540000002a +6000000000000024 0000000042756c25 4b756c252e756c25 0000000000004269 diff --git a/litedram/generated/orangecrab-85-0.2/litedram_core.v b/litedram/generated/orangecrab-85-0.2/litedram_core.v index 3bd3682..f5dc552 100644 --- a/litedram/generated/orangecrab-85-0.2/litedram_core.v +++ b/litedram/generated/orangecrab-85-0.2/litedram_core.v @@ -8,10 +8,11 @@ // // Filename : litedram_core.v // Device : LFE5U-85F-8MG285C -// LiteX sha1 : -------- -// Date : 2022-10-28 19:01:26 +// LiteX sha1 : 87137c30 +// Date : 2024-04-01 10:12:11 //------------------------------------------------------------------------------ +`timescale 1ns / 1ps //------------------------------------------------------------------------------ // Module @@ -19,160 +20,765 @@ module litedram_core ( input wire clk, - input wire rst, - output wire pll_locked, output wire [14:0] ddram_a, output wire [2:0] ddram_ba, - output wire ddram_ras_n, output wire ddram_cas_n, - output wire ddram_we_n, + output wire ddram_cke, + input wire ddram_clk_n, + output wire ddram_clk_p, output wire ddram_cs_n, output wire [1:0] ddram_dm, input wire [15:0] ddram_dq, - input wire [1:0] ddram_dqs_p, input wire [1:0] ddram_dqs_n, - output wire ddram_clk_p, - input wire ddram_clk_n, - output wire ddram_cke, + input wire [1:0] ddram_dqs_p, output wire ddram_odt, + output wire ddram_ras_n, output wire ddram_reset_n, + output wire ddram_we_n, output wire init_done, output wire init_error, - input wire [29:0] wb_ctrl_adr, - input wire [31:0] wb_ctrl_dat_w, - output wire [31:0] wb_ctrl_dat_r, - input wire [3:0] wb_ctrl_sel, - input wire wb_ctrl_cyc, - input wire wb_ctrl_stb, - output wire wb_ctrl_ack, - input wire wb_ctrl_we, - input wire [2:0] wb_ctrl_cti, - input wire [1:0] wb_ctrl_bte, - output wire wb_ctrl_err, + output wire pll_locked, + input wire rst, output wire user_clk, - output wire user_rst, - input wire user_port_native_0_cmd_valid, + input wire [24:0] user_port_native_0_cmd_addr, output wire user_port_native_0_cmd_ready, + input wire user_port_native_0_cmd_valid, input wire user_port_native_0_cmd_we, - input wire [24:0] user_port_native_0_cmd_addr, - input wire user_port_native_0_wdata_valid, + output wire [127:0] user_port_native_0_rdata_data, + input wire user_port_native_0_rdata_ready, + output wire user_port_native_0_rdata_valid, + input wire [127:0] user_port_native_0_wdata_data, output wire user_port_native_0_wdata_ready, + input wire user_port_native_0_wdata_valid, input wire [15:0] user_port_native_0_wdata_we, - input wire [127:0] user_port_native_0_wdata_data, - output wire user_port_native_0_rdata_valid, - input wire user_port_native_0_rdata_ready, - output wire [127:0] user_port_native_0_rdata_data + output wire user_rst, + output wire wb_ctrl_ack, + input wire [29:0] wb_ctrl_adr, + input wire [1:0] wb_ctrl_bte, + input wire [2:0] wb_ctrl_cti, + input wire wb_ctrl_cyc, + output wire [31:0] wb_ctrl_dat_r, + input wire [31:0] wb_ctrl_dat_w, + output wire wb_ctrl_err, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_stb, + input wire wb_ctrl_we ); +//------------------------------------------------------------------------------ +// Hierarchy +//------------------------------------------------------------------------------ + +/* +LiteDRAMCore +└─── bus (SoCBusHandler) +│ └─── _interconnect (InterconnectPointToPoint) +└─── csr (SoCCSRHandler) +└─── irq (SoCIRQHandler) +└─── cpu (CPUNone) +└─── crg (LiteDRAMECP5DDRPHYCRG) +│ └─── pll (ECP5PLL) +│ │ └─── [EHXPLLL] +│ └─── [ECLKSYNCB] +│ └─── [CLKDIVF] +│ └─── [ECLKBRIDGECS] +└─── ddrphy (ECP5DDRPHY) +│ └─── init (ECP5DDRPHYInit) +│ │ └─── [DDRDLLA] +│ └─── bitslip_0* (BitSlip) +│ └─── bitslip_1* (BitSlip) +│ └─── bitslip_2* (BitSlip) +│ └─── bitslip_3* (BitSlip) +│ └─── bitslip_4* (BitSlip) +│ └─── bitslip_5* (BitSlip) +│ └─── bitslip_6* (BitSlip) +│ └─── bitslip_7* (BitSlip) +│ └─── bitslip_8* (BitSlip) +│ └─── bitslip_9* (BitSlip) +│ └─── bitslip_10* (BitSlip) +│ └─── bitslip_11* (BitSlip) +│ └─── bitslip_12* (BitSlip) +│ └─── bitslip_13* (BitSlip) +│ └─── bitslip_14* (BitSlip) +│ └─── bitslip_15* (BitSlip) +│ └─── tappeddelayline_0* (TappedDelayLine) +│ └─── tappeddelayline_1* (TappedDelayLine) +│ └─── [TSHX2DQA] +│ └─── [ODDRX2F] +│ └─── [TSHX2DQA] +│ └─── [DELAYG] +│ └─── [ODDRX2F] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [ODDRX2F] +│ └─── [DELAYG] +│ └─── [TSHX2DQA] +│ └─── [TSHX2DQA] +│ └─── [ODDRX2DQSB] +│ └─── [ODDRX2F] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [TSHX2DQA] +│ └─── [ODDRX2DQA] +│ └─── [ODDRX2F] +│ └─── [TSHX2DQA] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [TSHX2DQA] +│ └─── [ODDRX2DQA] +│ └─── [ODDRX2F] +│ └─── [ODDRX2DQA] +│ └─── [ODDRX2DQA] +│ └─── [ODDRX2DQA] +│ └─── [ODDRX2F] +│ └─── [DELAYG] +│ └─── [ODDRX2DQA] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [ODDRX2DQA] +│ └─── [IDDRX2DQA] +│ └─── [ODDRX2DQA] +│ └─── [ODDRX2F] +│ └─── [ODDRX2F] +│ └─── [DELAYG] +│ └─── [IDDRX2DQA] +│ └─── [TSHX2DQSA] +│ └─── [DELAYG] +│ └─── [IDDRX2DQA] +│ └─── [IDDRX2DQA] +│ └─── [ODDRX2DQA] +│ └─── [IDDRX2DQA] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [IDDRX2DQA] +│ └─── [DQSBUFM] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [ODDRX2F] +│ └─── [ODDRX2F] +│ └─── [ODDRX2DQA] +│ └─── [TSHX2DQA] +│ └─── [DELAYG] +│ └─── [IDDRX2DQA] +│ └─── [TSHX2DQSA] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [IDDRX2DQA] +│ └─── [TSHX2DQA] +│ └─── [TSHX2DQA] +│ └─── [ODDRX2F] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [ODDRX2F] +│ └─── [TSHX2DQA] +│ └─── [TSHX2DQA] +│ └─── [DELAYG] +│ └─── [ODDRX2DQA] +│ └─── [IDDRX2DQA] +│ └─── [ODDRX2F] +│ └─── [TSHX2DQA] +│ └─── [DELAYG] +│ └─── [TSHX2DQA] +│ └─── [ODDRX2DQA] +│ └─── [ODDRX2DQA] +│ └─── [ODDRX2F] +│ └─── [ODDRX2F] +│ └─── [ODDRX2F] +│ └─── [ODDRX2DQA] +│ └─── [ODDRX2DQA] +│ └─── [TSHX2DQA] +│ └─── [ODDRX2F] +│ └─── [ODDRX2DQA] +│ └─── [IDDRX2DQA] +│ └─── [ODDRX2F] +│ └─── [ODDRX2DQA] +│ └─── [DELAYG] +│ └─── [ODDRX2F] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [IDDRX2DQA] +│ └─── [ODDRX2F] +│ └─── [IDDRX2DQA] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [IDDRX2DQA] +│ └─── [ODDRX2DQA] +│ └─── [ODDRX2F] +│ └─── [ODDRX2F] +│ └─── [DELAYG] +│ └─── [ODDRX2F] +│ └─── [DELAYG] +│ └─── [ODDRX2DQSB] +│ └─── [IDDRX2DQA] +│ └─── [DELAYG] +│ └─── [IDDRX2DQA] +│ └─── [ODDRX2F] +│ └─── [ODDRX2F] +│ └─── [DELAYG] +│ └─── [TSHX2DQA] +│ └─── [DQSBUFM] +│ └─── [IDDRX2DQA] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [DELAYG] +│ └─── [DELAYG] +└─── sdram (LiteDRAMCore) +│ └─── dfii (DFIInjector) +│ │ └─── pi0 (PhaseInjector) +│ │ └─── pi1 (PhaseInjector) +│ └─── controller (LiteDRAMController) +│ │ └─── refresher (Refresher) +│ │ │ └─── timer (RefreshTimer) +│ │ │ └─── postponer (RefreshPostponer) +│ │ │ └─── sequencer (RefreshSequencer) +│ │ │ │ └─── refreshexecuter_0* (RefreshExecuter) +│ │ │ └─── zqcs_timer (RefreshTimer) +│ │ │ └─── zqs_executer (ZQCSExecuter) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_0* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_1* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_2* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_3* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_4* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_5* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_6* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_7* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── multiplexer (Multiplexer) +│ │ │ └─── choose_cmd (_CommandChooser) +│ │ │ │ └─── roundrobin_0* (RoundRobin) +│ │ │ └─── choose_req (_CommandChooser) +│ │ │ │ └─── roundrobin_0* (RoundRobin) +│ │ │ └─── _steerer_0* (_Steerer) +│ │ │ └─── trrdcon (tXXDController) +│ │ │ └─── tfawcon (tFAWController) +│ │ │ └─── tccdcon (tXXDController) +│ │ │ └─── twtrcon (tXXDController) +│ │ │ └─── fsm (FSM) +│ └─── crossbar (LiteDRAMCrossbar) +│ │ └─── roundrobin_0* (RoundRobin) +│ │ └─── roundrobin_1* (RoundRobin) +│ │ └─── roundrobin_2* (RoundRobin) +│ │ └─── roundrobin_3* (RoundRobin) +│ │ └─── roundrobin_4* (RoundRobin) +│ │ └─── roundrobin_5* (RoundRobin) +│ │ └─── roundrobin_6* (RoundRobin) +│ │ └─── roundrobin_7* (RoundRobin) +└─── ddrctrl (LiteDRAMCoreControl) +└─── csr_bridge (Wishbone2CSR) +│ └─── fsm (FSM) +└─── csr_bankarray (CSRBankArray) +│ └─── csrbank_0* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ └─── csrbank_1* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ └─── csrbank_2* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstorage_4* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstorage_5* (CSRStorage) +│ │ └─── csrstorage_6* (CSRStorage) +│ │ └─── csrstorage_7* (CSRStorage) +│ │ └─── csrstorage_8* (CSRStorage) +│ │ └─── csrstatus_1* (CSRStatus) +└─── csr_interconnect (InterconnectShared) +└─── [FD1S3BX] +└─── [FD1S3BX] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +└─── [FD1S3BX] +└─── [FD1S3BX] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +└─── [FD1S3BX] +└─── [FD1S3BX] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +└─── [FD1S3BX] +└─── [TRELLIS_IO] +└─── [FD1S3BX] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +└─── [TRELLIS_IO] +* : Generated name. +[]: BlackBox. +*/ + //------------------------------------------------------------------------------ // Signals //------------------------------------------------------------------------------ -reg crg_rst = 1'd0; -wire init_clk; -wire init_rst; -wire por_clk; -wire sys_clk; -wire sys_rst; -wire sys2x_clk; -wire sys2x_rst; -wire sys2x_i_clk; -wire crg_stop; -wire crg_reset0; +wire [13:0] adr; +wire crg_clkin; +wire crg_clkout0; +wire crg_clkout1; +wire crg_locked; reg [15:0] crg_por_count = 16'd65535; wire crg_por_done; -wire crg_sys2x_clk_ecsout; +wire crg_reset0; wire crg_reset1; -wire crg_locked; +reg crg_rst = 1'd0; reg crg_stdby = 1'd0; -wire crg_clkin; -wire crg_clkout0; -wire crg_clkout1; -wire ddrphy_pause0; -wire ddrphy_stop0; -wire ddrphy_delay0; -wire ddrphy_reset0; -wire ddrphy_new_lock; -reg ddrphy_update = 1'd0; -reg ddrphy_stop1 = 1'd0; -reg ddrphy_freeze = 1'd0; -reg ddrphy_pause1 = 1'd0; -reg ddrphy_reset1 = 1'd0; -wire ddrphy_lock0; -wire ddrphy_delay1; -wire ddrphy_lock1; -reg ddrphy_lock_d = 1'd0; -reg [6:0] ddrphy_counter = 7'd0; -reg [1:0] ddrphy_dly_sel_storage = 2'd0; -reg ddrphy_dly_sel_re = 1'd0; -reg ddrphy_rdly_dq_rst_re = 1'd0; -wire ddrphy_rdly_dq_rst_r; -reg ddrphy_rdly_dq_rst_we = 1'd0; -reg ddrphy_rdly_dq_rst_w = 1'd0; -reg ddrphy_rdly_dq_inc_re = 1'd0; -wire ddrphy_rdly_dq_inc_r; -reg ddrphy_rdly_dq_inc_we = 1'd0; -reg ddrphy_rdly_dq_inc_w = 1'd0; -reg ddrphy_rdly_dq_bitslip_rst_re = 1'd0; -wire ddrphy_rdly_dq_bitslip_rst_r; -reg ddrphy_rdly_dq_bitslip_rst_we = 1'd0; -reg ddrphy_rdly_dq_bitslip_rst_w = 1'd0; -reg ddrphy_rdly_dq_bitslip_re = 1'd0; -wire ddrphy_rdly_dq_bitslip_r; -reg ddrphy_rdly_dq_bitslip_we = 1'd0; -reg ddrphy_rdly_dq_bitslip_w = 1'd0; -reg ddrphy_burstdet_clr_re = 1'd0; +wire crg_stop; +wire crg_sys2x_clk_ecsout; +wire csrbank0_init_done0_r; +reg csrbank0_init_done0_re = 1'd0; +wire csrbank0_init_done0_w; +reg csrbank0_init_done0_we = 1'd0; +wire csrbank0_init_error0_r; +reg csrbank0_init_error0_re = 1'd0; +wire csrbank0_init_error0_w; +reg csrbank0_init_error0_we = 1'd0; +wire csrbank0_sel; +wire [1:0] csrbank1_burstdet_seen_r; +reg csrbank1_burstdet_seen_re = 1'd0; +wire [1:0] csrbank1_burstdet_seen_w; +reg csrbank1_burstdet_seen_we = 1'd0; +wire [1:0] csrbank1_dly_sel0_r; +reg csrbank1_dly_sel0_re = 1'd0; +wire [1:0] csrbank1_dly_sel0_w; +reg csrbank1_dly_sel0_we = 1'd0; +wire csrbank1_sel; +wire [3:0] csrbank2_dfii_control0_r; +reg csrbank2_dfii_control0_re = 1'd0; +wire [3:0] csrbank2_dfii_control0_w; +reg csrbank2_dfii_control0_we = 1'd0; +wire [14:0] csrbank2_dfii_pi0_address0_r; +reg csrbank2_dfii_pi0_address0_re = 1'd0; +wire [14:0] csrbank2_dfii_pi0_address0_w; +reg csrbank2_dfii_pi0_address0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi0_baddress0_r; +reg csrbank2_dfii_pi0_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi0_baddress0_w; +reg csrbank2_dfii_pi0_baddress0_we = 1'd0; +wire [7:0] csrbank2_dfii_pi0_command0_r; +reg csrbank2_dfii_pi0_command0_re = 1'd0; +wire [7:0] csrbank2_dfii_pi0_command0_w; +reg csrbank2_dfii_pi0_command0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata0_r; +reg csrbank2_dfii_pi0_rddata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata0_w; +reg csrbank2_dfii_pi0_rddata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata1_r; +reg csrbank2_dfii_pi0_rddata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata1_w; +reg csrbank2_dfii_pi0_rddata1_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata0_r; +reg csrbank2_dfii_pi0_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata0_w; +reg csrbank2_dfii_pi0_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata1_r; +reg csrbank2_dfii_pi0_wrdata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata1_w; +reg csrbank2_dfii_pi0_wrdata1_we = 1'd0; +wire [14:0] csrbank2_dfii_pi1_address0_r; +reg csrbank2_dfii_pi1_address0_re = 1'd0; +wire [14:0] csrbank2_dfii_pi1_address0_w; +reg csrbank2_dfii_pi1_address0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi1_baddress0_r; +reg csrbank2_dfii_pi1_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi1_baddress0_w; +reg csrbank2_dfii_pi1_baddress0_we = 1'd0; +wire [7:0] csrbank2_dfii_pi1_command0_r; +reg csrbank2_dfii_pi1_command0_re = 1'd0; +wire [7:0] csrbank2_dfii_pi1_command0_w; +reg csrbank2_dfii_pi1_command0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata0_r; +reg csrbank2_dfii_pi1_rddata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata0_w; +reg csrbank2_dfii_pi1_rddata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata1_r; +reg csrbank2_dfii_pi1_rddata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata1_w; +reg csrbank2_dfii_pi1_rddata1_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata0_r; +reg csrbank2_dfii_pi1_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata0_w; +reg csrbank2_dfii_pi1_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata1_r; +reg csrbank2_dfii_pi1_wrdata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata1_w; +reg csrbank2_dfii_pi1_wrdata1_we = 1'd0; +wire csrbank2_sel; +wire [31:0] dat_r; +wire [31:0] dat_w; +wire [3:0] ddrphy_bitslip0_i; +reg [3:0] ddrphy_bitslip0_o = 4'd0; +reg [7:0] ddrphy_bitslip0_r = 8'd0; +reg [1:0] ddrphy_bitslip0_value = 2'd0; +wire [3:0] ddrphy_bitslip10_i; +reg [3:0] ddrphy_bitslip10_o = 4'd0; +reg [7:0] ddrphy_bitslip10_r = 8'd0; +reg [1:0] ddrphy_bitslip10_value = 2'd0; +wire [3:0] ddrphy_bitslip11_i; +reg [3:0] ddrphy_bitslip11_o = 4'd0; +reg [7:0] ddrphy_bitslip11_r = 8'd0; +reg [1:0] ddrphy_bitslip11_value = 2'd0; +wire [3:0] ddrphy_bitslip12_i; +reg [3:0] ddrphy_bitslip12_o = 4'd0; +reg [7:0] ddrphy_bitslip12_r = 8'd0; +reg [1:0] ddrphy_bitslip12_value = 2'd0; +wire [3:0] ddrphy_bitslip13_i; +reg [3:0] ddrphy_bitslip13_o = 4'd0; +reg [7:0] ddrphy_bitslip13_r = 8'd0; +reg [1:0] ddrphy_bitslip13_value = 2'd0; +wire [3:0] ddrphy_bitslip14_i; +reg [3:0] ddrphy_bitslip14_o = 4'd0; +reg [7:0] ddrphy_bitslip14_r = 8'd0; +reg [1:0] ddrphy_bitslip14_value = 2'd0; +wire [3:0] ddrphy_bitslip15_i; +reg [3:0] ddrphy_bitslip15_o = 4'd0; +reg [7:0] ddrphy_bitslip15_r = 8'd0; +reg [1:0] ddrphy_bitslip15_value = 2'd0; +wire [3:0] ddrphy_bitslip1_i; +reg [3:0] ddrphy_bitslip1_o = 4'd0; +reg [7:0] ddrphy_bitslip1_r = 8'd0; +reg [1:0] ddrphy_bitslip1_value = 2'd0; +wire [3:0] ddrphy_bitslip2_i; +reg [3:0] ddrphy_bitslip2_o = 4'd0; +reg [7:0] ddrphy_bitslip2_r = 8'd0; +reg [1:0] ddrphy_bitslip2_value = 2'd0; +wire [3:0] ddrphy_bitslip3_i; +reg [3:0] ddrphy_bitslip3_o = 4'd0; +reg [7:0] ddrphy_bitslip3_r = 8'd0; +reg [1:0] ddrphy_bitslip3_value = 2'd0; +wire [3:0] ddrphy_bitslip4_i; +reg [3:0] ddrphy_bitslip4_o = 4'd0; +reg [7:0] ddrphy_bitslip4_r = 8'd0; +reg [1:0] ddrphy_bitslip4_value = 2'd0; +wire [3:0] ddrphy_bitslip5_i; +reg [3:0] ddrphy_bitslip5_o = 4'd0; +reg [7:0] ddrphy_bitslip5_r = 8'd0; +reg [1:0] ddrphy_bitslip5_value = 2'd0; +wire [3:0] ddrphy_bitslip6_i; +reg [3:0] ddrphy_bitslip6_o = 4'd0; +reg [7:0] ddrphy_bitslip6_r = 8'd0; +reg [1:0] ddrphy_bitslip6_value = 2'd0; +wire [3:0] ddrphy_bitslip7_i; +reg [3:0] ddrphy_bitslip7_o = 4'd0; +reg [7:0] ddrphy_bitslip7_r = 8'd0; +reg [1:0] ddrphy_bitslip7_value = 2'd0; +wire [3:0] ddrphy_bitslip8_i; +reg [3:0] ddrphy_bitslip8_o = 4'd0; +reg [7:0] ddrphy_bitslip8_r = 8'd0; +reg [1:0] ddrphy_bitslip8_value = 2'd0; +wire [3:0] ddrphy_bitslip9_i; +reg [3:0] ddrphy_bitslip9_o = 4'd0; +reg [7:0] ddrphy_bitslip9_r = 8'd0; +reg [1:0] ddrphy_bitslip9_value = 2'd0; +wire ddrphy_bl8_chunk; +wire ddrphy_burstdet0; +wire ddrphy_burstdet1; wire ddrphy_burstdet_clr_r; -reg ddrphy_burstdet_clr_we = 1'd0; +reg ddrphy_burstdet_clr_re = 1'd0; reg ddrphy_burstdet_clr_w = 1'd0; -reg [1:0] ddrphy_burstdet_seen_status = 2'd0; -wire ddrphy_burstdet_seen_we; +reg ddrphy_burstdet_clr_we = 1'd0; +reg ddrphy_burstdet_d0 = 1'd0; +reg ddrphy_burstdet_d1 = 1'd0; reg ddrphy_burstdet_seen_re = 1'd0; +reg [1:0] ddrphy_burstdet_seen_status = 2'd0; +wire ddrphy_burstdet_seen_we; wire [1:0] ddrphy_datavalid; +wire ddrphy_delay0; +wire ddrphy_delay1; +wire ddrphy_dfi_p0_act_n; wire [14:0] ddrphy_dfi_p0_address; wire [2:0] ddrphy_dfi_p0_bank; wire ddrphy_dfi_p0_cas_n; -wire ddrphy_dfi_p0_cs_n; -wire ddrphy_dfi_p0_ras_n; -wire ddrphy_dfi_p0_we_n; wire ddrphy_dfi_p0_cke; +wire ddrphy_dfi_p0_cs_n; wire ddrphy_dfi_p0_odt; +wire ddrphy_dfi_p0_ras_n; +reg [63:0] ddrphy_dfi_p0_rddata = 64'd0; +wire ddrphy_dfi_p0_rddata_en; +wire ddrphy_dfi_p0_rddata_valid; wire ddrphy_dfi_p0_reset_n; -wire ddrphy_dfi_p0_act_n; +wire ddrphy_dfi_p0_we_n; wire [63:0] ddrphy_dfi_p0_wrdata; wire ddrphy_dfi_p0_wrdata_en; wire [7:0] ddrphy_dfi_p0_wrdata_mask; -wire ddrphy_dfi_p0_rddata_en; -reg [63:0] ddrphy_dfi_p0_rddata = 64'd0; -wire ddrphy_dfi_p0_rddata_valid; +wire ddrphy_dfi_p1_act_n; wire [14:0] ddrphy_dfi_p1_address; wire [2:0] ddrphy_dfi_p1_bank; wire ddrphy_dfi_p1_cas_n; -wire ddrphy_dfi_p1_cs_n; -wire ddrphy_dfi_p1_ras_n; -wire ddrphy_dfi_p1_we_n; wire ddrphy_dfi_p1_cke; +wire ddrphy_dfi_p1_cs_n; wire ddrphy_dfi_p1_odt; +wire ddrphy_dfi_p1_ras_n; +reg [63:0] ddrphy_dfi_p1_rddata = 64'd0; +wire ddrphy_dfi_p1_rddata_en; +wire ddrphy_dfi_p1_rddata_valid; wire ddrphy_dfi_p1_reset_n; -wire ddrphy_dfi_p1_act_n; +wire ddrphy_dfi_p1_we_n; wire [63:0] ddrphy_dfi_p1_wrdata; wire ddrphy_dfi_p1_wrdata_en; wire [7:0] ddrphy_dfi_p1_wrdata_mask; -wire ddrphy_dfi_p1_rddata_en; -reg [63:0] ddrphy_dfi_p1_rddata = 64'd0; -wire ddrphy_dfi_p1_rddata_valid; -wire ddrphy_bl8_chunk; +reg ddrphy_dly_sel_re = 1'd0; +reg [1:0] ddrphy_dly_sel_storage = 2'd0; +reg [7:0] ddrphy_dm_o_data0 = 8'd0; +reg [7:0] ddrphy_dm_o_data1 = 8'd0; +reg [7:0] ddrphy_dm_o_data_d0 = 8'd0; +reg [7:0] ddrphy_dm_o_data_d1 = 8'd0; +reg [3:0] ddrphy_dm_o_data_muxed0 = 4'd0; +reg [3:0] ddrphy_dm_o_data_muxed1 = 4'd0; +wire ddrphy_dq_i0; +wire ddrphy_dq_i1; +wire ddrphy_dq_i10; +wire ddrphy_dq_i11; +wire ddrphy_dq_i12; +wire ddrphy_dq_i13; +wire ddrphy_dq_i14; +wire ddrphy_dq_i15; +wire ddrphy_dq_i2; +wire ddrphy_dq_i3; +wire ddrphy_dq_i4; +wire ddrphy_dq_i5; +wire ddrphy_dq_i6; +wire ddrphy_dq_i7; +wire ddrphy_dq_i8; +wire ddrphy_dq_i9; +reg [3:0] ddrphy_dq_i_bitslip_o_d0 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d1 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d10 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d11 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d12 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d13 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d14 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d15 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d2 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d3 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d4 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d5 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d6 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d7 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d8 = 4'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d9 = 4'd0; +wire [7:0] ddrphy_dq_i_data0; +wire [7:0] ddrphy_dq_i_data1; +wire [7:0] ddrphy_dq_i_data10; +wire [7:0] ddrphy_dq_i_data11; +wire [7:0] ddrphy_dq_i_data12; +wire [7:0] ddrphy_dq_i_data13; +wire [7:0] ddrphy_dq_i_data14; +wire [7:0] ddrphy_dq_i_data15; +wire [7:0] ddrphy_dq_i_data2; +wire [7:0] ddrphy_dq_i_data3; +wire [7:0] ddrphy_dq_i_data4; +wire [7:0] ddrphy_dq_i_data5; +wire [7:0] ddrphy_dq_i_data6; +wire [7:0] ddrphy_dq_i_data7; +wire [7:0] ddrphy_dq_i_data8; +wire [7:0] ddrphy_dq_i_data9; +wire ddrphy_dq_i_delayed0; +wire ddrphy_dq_i_delayed1; +wire ddrphy_dq_i_delayed10; +wire ddrphy_dq_i_delayed11; +wire ddrphy_dq_i_delayed12; +wire ddrphy_dq_i_delayed13; +wire ddrphy_dq_i_delayed14; +wire ddrphy_dq_i_delayed15; +wire ddrphy_dq_i_delayed2; +wire ddrphy_dq_i_delayed3; +wire ddrphy_dq_i_delayed4; +wire ddrphy_dq_i_delayed5; +wire ddrphy_dq_i_delayed6; +wire ddrphy_dq_i_delayed7; +wire ddrphy_dq_i_delayed8; +wire ddrphy_dq_i_delayed9; +wire ddrphy_dq_o0; +wire ddrphy_dq_o1; +wire ddrphy_dq_o10; +wire ddrphy_dq_o11; +wire ddrphy_dq_o12; +wire ddrphy_dq_o13; +wire ddrphy_dq_o14; +wire ddrphy_dq_o15; +wire ddrphy_dq_o2; +wire ddrphy_dq_o3; +wire ddrphy_dq_o4; +wire ddrphy_dq_o5; +wire ddrphy_dq_o6; +wire ddrphy_dq_o7; +wire ddrphy_dq_o8; +wire ddrphy_dq_o9; +reg [7:0] ddrphy_dq_o_data0 = 8'd0; +reg [7:0] ddrphy_dq_o_data1 = 8'd0; +reg [7:0] ddrphy_dq_o_data10 = 8'd0; +reg [7:0] ddrphy_dq_o_data11 = 8'd0; +reg [7:0] ddrphy_dq_o_data12 = 8'd0; +reg [7:0] ddrphy_dq_o_data13 = 8'd0; +reg [7:0] ddrphy_dq_o_data14 = 8'd0; +reg [7:0] ddrphy_dq_o_data15 = 8'd0; +reg [7:0] ddrphy_dq_o_data2 = 8'd0; +reg [7:0] ddrphy_dq_o_data3 = 8'd0; +reg [7:0] ddrphy_dq_o_data4 = 8'd0; +reg [7:0] ddrphy_dq_o_data5 = 8'd0; +reg [7:0] ddrphy_dq_o_data6 = 8'd0; +reg [7:0] ddrphy_dq_o_data7 = 8'd0; +reg [7:0] ddrphy_dq_o_data8 = 8'd0; +reg [7:0] ddrphy_dq_o_data9 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d0 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d1 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d10 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d11 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d12 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d13 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d14 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d15 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d2 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d3 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d4 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d5 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d6 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d7 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d8 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d9 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed0 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed1 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed10 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed11 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed12 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed13 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed14 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed15 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed2 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed3 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed4 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed5 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed6 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed7 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed8 = 4'd0; +reg [3:0] ddrphy_dq_o_data_muxed9 = 4'd0; +wire ddrphy_dq_oe; +wire ddrphy_dq_oe_n0; +wire ddrphy_dq_oe_n1; +wire ddrphy_dq_oe_n10; +wire ddrphy_dq_oe_n11; +wire ddrphy_dq_oe_n12; +wire ddrphy_dq_oe_n13; +wire ddrphy_dq_oe_n14; +wire ddrphy_dq_oe_n15; +wire ddrphy_dq_oe_n2; +wire ddrphy_dq_oe_n3; +wire ddrphy_dq_oe_n4; +wire ddrphy_dq_oe_n5; +wire ddrphy_dq_oe_n6; +wire ddrphy_dq_oe_n7; +wire ddrphy_dq_oe_n8; +wire ddrphy_dq_oe_n9; +wire ddrphy_dqs0; +wire ddrphy_dqs1; +wire ddrphy_dqs_i0; +wire ddrphy_dqs_i1; +wire ddrphy_dqs_oe; +wire ddrphy_dqs_oe_n0; +wire ddrphy_dqs_oe_n1; +wire ddrphy_dqs_postamble; +wire ddrphy_dqs_preamble; +wire ddrphy_dqs_re; +wire ddrphy_dqsr900; +wire ddrphy_dqsr901; +wire ddrphy_dqsw0; +wire ddrphy_dqsw1; +wire ddrphy_dqsw2700; +wire ddrphy_dqsw2701; +reg ddrphy_freeze = 1'd0; +wire ddrphy_lock0; +wire ddrphy_lock1; +reg ddrphy_lock_d = 1'd0; +wire ddrphy_new_lock; wire ddrphy_pad_oddrx2f0; wire ddrphy_pad_oddrx2f1; -wire ddrphy_pad_oddrx2f2; -wire ddrphy_pad_oddrx2f3; -wire ddrphy_pad_oddrx2f4; -wire ddrphy_pad_oddrx2f5; -wire ddrphy_pad_oddrx2f6; -wire ddrphy_pad_oddrx2f7; -wire ddrphy_pad_oddrx2f8; -wire ddrphy_pad_oddrx2f9; wire ddrphy_pad_oddrx2f10; wire ddrphy_pad_oddrx2f11; wire ddrphy_pad_oddrx2f12; @@ -183,1691 +789,1418 @@ wire ddrphy_pad_oddrx2f16; wire ddrphy_pad_oddrx2f17; wire ddrphy_pad_oddrx2f18; wire ddrphy_pad_oddrx2f19; +wire ddrphy_pad_oddrx2f2; wire ddrphy_pad_oddrx2f20; wire ddrphy_pad_oddrx2f21; wire ddrphy_pad_oddrx2f22; wire ddrphy_pad_oddrx2f23; wire ddrphy_pad_oddrx2f24; wire ddrphy_pad_oddrx2f25; -wire ddrphy_dq_oe; -wire ddrphy_dqs_re; -wire ddrphy_dqs_oe; -wire ddrphy_dqs_postamble; -wire ddrphy_dqs_preamble; -wire ddrphy_dqs_i0; -wire ddrphy_dqsr900; -wire ddrphy_dqsw2700; -wire ddrphy_dqsw0; -wire [2:0] ddrphy_rdpntr0; -wire [2:0] ddrphy_wrpntr0; +wire ddrphy_pad_oddrx2f3; +wire ddrphy_pad_oddrx2f4; +wire ddrphy_pad_oddrx2f5; +wire ddrphy_pad_oddrx2f6; +wire ddrphy_pad_oddrx2f7; +wire ddrphy_pad_oddrx2f8; +wire ddrphy_pad_oddrx2f9; +wire ddrphy_pause0; +reg ddrphy_pause1 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline10 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline11 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline12 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline7 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline8 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline9 = 1'd0; reg [2:0] ddrphy_rdly0 = 3'd0; -wire ddrphy_burstdet0; -reg ddrphy_burstdet_d0 = 1'd0; -wire ddrphy_dqs0; -wire ddrphy_dqs_oe_n0; -reg [7:0] ddrphy_dm_o_data0 = 8'd0; -reg [7:0] ddrphy_dm_o_data_d0 = 8'd0; -reg [3:0] ddrphy_dm_o_data_muxed0 = 4'd0; -wire ddrphy_dq_o0; -wire ddrphy_dq_i0; -wire ddrphy_dq_oe_n0; -wire ddrphy_dq_i_delayed0; -wire [7:0] ddrphy_dq_i_data0; -reg [7:0] ddrphy_dq_o_data0 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d0 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed0 = 4'd0; -wire [3:0] ddrphy_bitslip0_i; -reg [3:0] ddrphy_bitslip0_o = 4'd0; -reg [1:0] ddrphy_bitslip0_value = 2'd0; -reg [7:0] ddrphy_bitslip0_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d0 = 4'd0; -wire ddrphy_dq_o1; -wire ddrphy_dq_i1; -wire ddrphy_dq_oe_n1; -wire ddrphy_dq_i_delayed1; -wire [7:0] ddrphy_dq_i_data1; -reg [7:0] ddrphy_dq_o_data1 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d1 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed1 = 4'd0; -wire [3:0] ddrphy_bitslip1_i; -reg [3:0] ddrphy_bitslip1_o = 4'd0; -reg [1:0] ddrphy_bitslip1_value = 2'd0; -reg [7:0] ddrphy_bitslip1_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d1 = 4'd0; -wire ddrphy_dq_o2; -wire ddrphy_dq_i2; -wire ddrphy_dq_oe_n2; -wire ddrphy_dq_i_delayed2; -wire [7:0] ddrphy_dq_i_data2; -reg [7:0] ddrphy_dq_o_data2 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d2 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed2 = 4'd0; -wire [3:0] ddrphy_bitslip2_i; -reg [3:0] ddrphy_bitslip2_o = 4'd0; -reg [1:0] ddrphy_bitslip2_value = 2'd0; -reg [7:0] ddrphy_bitslip2_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d2 = 4'd0; -wire ddrphy_dq_o3; -wire ddrphy_dq_i3; -wire ddrphy_dq_oe_n3; -wire ddrphy_dq_i_delayed3; -wire [7:0] ddrphy_dq_i_data3; -reg [7:0] ddrphy_dq_o_data3 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d3 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed3 = 4'd0; -wire [3:0] ddrphy_bitslip3_i; -reg [3:0] ddrphy_bitslip3_o = 4'd0; -reg [1:0] ddrphy_bitslip3_value = 2'd0; -reg [7:0] ddrphy_bitslip3_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d3 = 4'd0; -wire ddrphy_dq_o4; -wire ddrphy_dq_i4; -wire ddrphy_dq_oe_n4; -wire ddrphy_dq_i_delayed4; -wire [7:0] ddrphy_dq_i_data4; -reg [7:0] ddrphy_dq_o_data4 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d4 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed4 = 4'd0; -wire [3:0] ddrphy_bitslip4_i; -reg [3:0] ddrphy_bitslip4_o = 4'd0; -reg [1:0] ddrphy_bitslip4_value = 2'd0; -reg [7:0] ddrphy_bitslip4_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d4 = 4'd0; -wire ddrphy_dq_o5; -wire ddrphy_dq_i5; -wire ddrphy_dq_oe_n5; -wire ddrphy_dq_i_delayed5; -wire [7:0] ddrphy_dq_i_data5; -reg [7:0] ddrphy_dq_o_data5 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d5 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed5 = 4'd0; -wire [3:0] ddrphy_bitslip5_i; -reg [3:0] ddrphy_bitslip5_o = 4'd0; -reg [1:0] ddrphy_bitslip5_value = 2'd0; -reg [7:0] ddrphy_bitslip5_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d5 = 4'd0; -wire ddrphy_dq_o6; -wire ddrphy_dq_i6; -wire ddrphy_dq_oe_n6; -wire ddrphy_dq_i_delayed6; -wire [7:0] ddrphy_dq_i_data6; -reg [7:0] ddrphy_dq_o_data6 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d6 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed6 = 4'd0; -wire [3:0] ddrphy_bitslip6_i; -reg [3:0] ddrphy_bitslip6_o = 4'd0; -reg [1:0] ddrphy_bitslip6_value = 2'd0; -reg [7:0] ddrphy_bitslip6_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d6 = 4'd0; -wire ddrphy_dq_o7; -wire ddrphy_dq_i7; -wire ddrphy_dq_oe_n7; -wire ddrphy_dq_i_delayed7; -wire [7:0] ddrphy_dq_i_data7; -reg [7:0] ddrphy_dq_o_data7 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d7 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed7 = 4'd0; -wire [3:0] ddrphy_bitslip7_i; -reg [3:0] ddrphy_bitslip7_o = 4'd0; -reg [1:0] ddrphy_bitslip7_value = 2'd0; -reg [7:0] ddrphy_bitslip7_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d7 = 4'd0; -wire ddrphy_dqs_i1; -wire ddrphy_dqsr901; -wire ddrphy_dqsw2701; -wire ddrphy_dqsw1; +reg [2:0] ddrphy_rdly1 = 3'd0; +wire ddrphy_rdly_dq_bitslip_r; +reg ddrphy_rdly_dq_bitslip_re = 1'd0; +wire ddrphy_rdly_dq_bitslip_rst_r; +reg ddrphy_rdly_dq_bitslip_rst_re = 1'd0; +reg ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +reg ddrphy_rdly_dq_bitslip_rst_we = 1'd0; +reg ddrphy_rdly_dq_bitslip_w = 1'd0; +reg ddrphy_rdly_dq_bitslip_we = 1'd0; +wire ddrphy_rdly_dq_inc_r; +reg ddrphy_rdly_dq_inc_re = 1'd0; +reg ddrphy_rdly_dq_inc_w = 1'd0; +reg ddrphy_rdly_dq_inc_we = 1'd0; +wire ddrphy_rdly_dq_rst_r; +reg ddrphy_rdly_dq_rst_re = 1'd0; +reg ddrphy_rdly_dq_rst_w = 1'd0; +reg ddrphy_rdly_dq_rst_we = 1'd0; +wire [2:0] ddrphy_rdpntr0; wire [2:0] ddrphy_rdpntr1; +wire ddrphy_reset0; +reg ddrphy_reset1 = 1'd0; +wire ddrphy_stop0; +reg ddrphy_stop1 = 1'd0; +reg [6:0] ddrphy_trigger = 7'd0; +reg ddrphy_update = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline3 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline4 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline5 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline6 = 1'd0; +wire [2:0] ddrphy_wrpntr0; wire [2:0] ddrphy_wrpntr1; -reg [2:0] ddrphy_rdly1 = 3'd0; -wire ddrphy_burstdet1; -reg ddrphy_burstdet_d1 = 1'd0; -wire ddrphy_dqs1; -wire ddrphy_dqs_oe_n1; -reg [7:0] ddrphy_dm_o_data1 = 8'd0; -reg [7:0] ddrphy_dm_o_data_d1 = 8'd0; -reg [3:0] ddrphy_dm_o_data_muxed1 = 4'd0; -wire ddrphy_dq_o8; -wire ddrphy_dq_i8; -wire ddrphy_dq_oe_n8; -wire ddrphy_dq_i_delayed8; -wire [7:0] ddrphy_dq_i_data8; -reg [7:0] ddrphy_dq_o_data8 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d8 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed8 = 4'd0; -wire [3:0] ddrphy_bitslip8_i; -reg [3:0] ddrphy_bitslip8_o = 4'd0; -reg [1:0] ddrphy_bitslip8_value = 2'd0; -reg [7:0] ddrphy_bitslip8_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d8 = 4'd0; -wire ddrphy_dq_o9; -wire ddrphy_dq_i9; -wire ddrphy_dq_oe_n9; -wire ddrphy_dq_i_delayed9; -wire [7:0] ddrphy_dq_i_data9; -reg [7:0] ddrphy_dq_o_data9 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d9 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed9 = 4'd0; -wire [3:0] ddrphy_bitslip9_i; -reg [3:0] ddrphy_bitslip9_o = 4'd0; -reg [1:0] ddrphy_bitslip9_value = 2'd0; -reg [7:0] ddrphy_bitslip9_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d9 = 4'd0; -wire ddrphy_dq_o10; -wire ddrphy_dq_i10; -wire ddrphy_dq_oe_n10; -wire ddrphy_dq_i_delayed10; -wire [7:0] ddrphy_dq_i_data10; -reg [7:0] ddrphy_dq_o_data10 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d10 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed10 = 4'd0; -wire [3:0] ddrphy_bitslip10_i; -reg [3:0] ddrphy_bitslip10_o = 4'd0; -reg [1:0] ddrphy_bitslip10_value = 2'd0; -reg [7:0] ddrphy_bitslip10_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d10 = 4'd0; -wire ddrphy_dq_o11; -wire ddrphy_dq_i11; -wire ddrphy_dq_oe_n11; -wire ddrphy_dq_i_delayed11; -wire [7:0] ddrphy_dq_i_data11; -reg [7:0] ddrphy_dq_o_data11 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d11 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed11 = 4'd0; -wire [3:0] ddrphy_bitslip11_i; -reg [3:0] ddrphy_bitslip11_o = 4'd0; -reg [1:0] ddrphy_bitslip11_value = 2'd0; -reg [7:0] ddrphy_bitslip11_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d11 = 4'd0; -wire ddrphy_dq_o12; -wire ddrphy_dq_i12; -wire ddrphy_dq_oe_n12; -wire ddrphy_dq_i_delayed12; -wire [7:0] ddrphy_dq_i_data12; -reg [7:0] ddrphy_dq_o_data12 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d12 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed12 = 4'd0; -wire [3:0] ddrphy_bitslip12_i; -reg [3:0] ddrphy_bitslip12_o = 4'd0; -reg [1:0] ddrphy_bitslip12_value = 2'd0; -reg [7:0] ddrphy_bitslip12_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d12 = 4'd0; -wire ddrphy_dq_o13; -wire ddrphy_dq_i13; -wire ddrphy_dq_oe_n13; -wire ddrphy_dq_i_delayed13; -wire [7:0] ddrphy_dq_i_data13; -reg [7:0] ddrphy_dq_o_data13 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d13 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed13 = 4'd0; -wire [3:0] ddrphy_bitslip13_i; -reg [3:0] ddrphy_bitslip13_o = 4'd0; -reg [1:0] ddrphy_bitslip13_value = 2'd0; -reg [7:0] ddrphy_bitslip13_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d13 = 4'd0; -wire ddrphy_dq_o14; -wire ddrphy_dq_i14; -wire ddrphy_dq_oe_n14; -wire ddrphy_dq_i_delayed14; -wire [7:0] ddrphy_dq_i_data14; -reg [7:0] ddrphy_dq_o_data14 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d14 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed14 = 4'd0; -wire [3:0] ddrphy_bitslip14_i; -reg [3:0] ddrphy_bitslip14_o = 4'd0; -reg [1:0] ddrphy_bitslip14_value = 2'd0; -reg [7:0] ddrphy_bitslip14_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d14 = 4'd0; -wire ddrphy_dq_o15; -wire ddrphy_dq_i15; -wire ddrphy_dq_oe_n15; -wire ddrphy_dq_i_delayed15; -wire [7:0] ddrphy_dq_i_data15; -reg [7:0] ddrphy_dq_o_data15 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d15 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed15 = 4'd0; -wire [3:0] ddrphy_bitslip15_i; -reg [3:0] ddrphy_bitslip15_o = 4'd0; -reg [1:0] ddrphy_bitslip15_value = 2'd0; -reg [7:0] ddrphy_bitslip15_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d15 = 4'd0; -reg ddrphy_rddata_en_tappeddelayline0 = 1'd0; -reg ddrphy_rddata_en_tappeddelayline1 = 1'd0; -reg ddrphy_rddata_en_tappeddelayline2 = 1'd0; -reg ddrphy_rddata_en_tappeddelayline3 = 1'd0; -reg ddrphy_rddata_en_tappeddelayline4 = 1'd0; -reg ddrphy_rddata_en_tappeddelayline5 = 1'd0; -reg ddrphy_rddata_en_tappeddelayline6 = 1'd0; -reg ddrphy_rddata_en_tappeddelayline7 = 1'd0; -reg ddrphy_rddata_en_tappeddelayline8 = 1'd0; -reg ddrphy_rddata_en_tappeddelayline9 = 1'd0; -reg ddrphy_rddata_en_tappeddelayline10 = 1'd0; -reg ddrphy_rddata_en_tappeddelayline11 = 1'd0; -reg ddrphy_rddata_en_tappeddelayline12 = 1'd0; -reg ddrphy_wrdata_en_tappeddelayline0 = 1'd0; -reg ddrphy_wrdata_en_tappeddelayline1 = 1'd0; -reg ddrphy_wrdata_en_tappeddelayline2 = 1'd0; -reg ddrphy_wrdata_en_tappeddelayline3 = 1'd0; -reg ddrphy_wrdata_en_tappeddelayline4 = 1'd0; -reg ddrphy_wrdata_en_tappeddelayline5 = 1'd0; -reg ddrphy_wrdata_en_tappeddelayline6 = 1'd0; -wire [14:0] litedramcore_slave_p0_address; -wire [2:0] litedramcore_slave_p0_bank; -wire litedramcore_slave_p0_cas_n; -wire litedramcore_slave_p0_cs_n; -wire litedramcore_slave_p0_ras_n; -wire litedramcore_slave_p0_we_n; -wire litedramcore_slave_p0_cke; -wire litedramcore_slave_p0_odt; -wire litedramcore_slave_p0_reset_n; -wire litedramcore_slave_p0_act_n; -wire [63:0] litedramcore_slave_p0_wrdata; -wire litedramcore_slave_p0_wrdata_en; -wire [7:0] litedramcore_slave_p0_wrdata_mask; -wire litedramcore_slave_p0_rddata_en; -reg [63:0] litedramcore_slave_p0_rddata = 64'd0; -reg litedramcore_slave_p0_rddata_valid = 1'd0; -wire [14:0] litedramcore_slave_p1_address; -wire [2:0] litedramcore_slave_p1_bank; -wire litedramcore_slave_p1_cas_n; -wire litedramcore_slave_p1_cs_n; -wire litedramcore_slave_p1_ras_n; -wire litedramcore_slave_p1_we_n; -wire litedramcore_slave_p1_cke; -wire litedramcore_slave_p1_odt; -wire litedramcore_slave_p1_reset_n; -wire litedramcore_slave_p1_act_n; -wire [63:0] litedramcore_slave_p1_wrdata; -wire litedramcore_slave_p1_wrdata_en; -wire [7:0] litedramcore_slave_p1_wrdata_mask; -wire litedramcore_slave_p1_rddata_en; -reg [63:0] litedramcore_slave_p1_rddata = 64'd0; -reg litedramcore_slave_p1_rddata_valid = 1'd0; -reg [14:0] litedramcore_master_p0_address = 15'd0; -reg [2:0] litedramcore_master_p0_bank = 3'd0; -reg litedramcore_master_p0_cas_n = 1'd1; -reg litedramcore_master_p0_cs_n = 1'd1; -reg litedramcore_master_p0_ras_n = 1'd1; -reg litedramcore_master_p0_we_n = 1'd1; -reg litedramcore_master_p0_cke = 1'd0; -reg litedramcore_master_p0_odt = 1'd0; -reg litedramcore_master_p0_reset_n = 1'd0; -reg litedramcore_master_p0_act_n = 1'd1; -reg [63:0] litedramcore_master_p0_wrdata = 64'd0; -reg litedramcore_master_p0_wrdata_en = 1'd0; -reg [7:0] litedramcore_master_p0_wrdata_mask = 8'd0; -reg litedramcore_master_p0_rddata_en = 1'd0; -wire [63:0] litedramcore_master_p0_rddata; -wire litedramcore_master_p0_rddata_valid; -reg [14:0] litedramcore_master_p1_address = 15'd0; -reg [2:0] litedramcore_master_p1_bank = 3'd0; -reg litedramcore_master_p1_cas_n = 1'd1; -reg litedramcore_master_p1_cs_n = 1'd1; -reg litedramcore_master_p1_ras_n = 1'd1; -reg litedramcore_master_p1_we_n = 1'd1; -reg litedramcore_master_p1_cke = 1'd0; -reg litedramcore_master_p1_odt = 1'd0; -reg litedramcore_master_p1_reset_n = 1'd0; -reg litedramcore_master_p1_act_n = 1'd1; -reg [63:0] litedramcore_master_p1_wrdata = 64'd0; -reg litedramcore_master_p1_wrdata_en = 1'd0; -reg [7:0] litedramcore_master_p1_wrdata_mask = 8'd0; -reg litedramcore_master_p1_rddata_en = 1'd0; -wire [63:0] litedramcore_master_p1_rddata; -wire litedramcore_master_p1_rddata_valid; -wire [14:0] litedramcore_csr_dfi_p0_address; -wire [2:0] litedramcore_csr_dfi_p0_bank; -reg litedramcore_csr_dfi_p0_cas_n = 1'd1; -reg litedramcore_csr_dfi_p0_cs_n = 1'd1; -reg litedramcore_csr_dfi_p0_ras_n = 1'd1; -reg litedramcore_csr_dfi_p0_we_n = 1'd1; -wire litedramcore_csr_dfi_p0_cke; -wire litedramcore_csr_dfi_p0_odt; -wire litedramcore_csr_dfi_p0_reset_n; -reg litedramcore_csr_dfi_p0_act_n = 1'd1; -wire [63:0] litedramcore_csr_dfi_p0_wrdata; -wire litedramcore_csr_dfi_p0_wrdata_en; -wire [7:0] litedramcore_csr_dfi_p0_wrdata_mask; -wire litedramcore_csr_dfi_p0_rddata_en; -reg [63:0] litedramcore_csr_dfi_p0_rddata = 64'd0; -reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0; -wire [14:0] litedramcore_csr_dfi_p1_address; -wire [2:0] litedramcore_csr_dfi_p1_bank; -reg litedramcore_csr_dfi_p1_cas_n = 1'd1; -reg litedramcore_csr_dfi_p1_cs_n = 1'd1; -reg litedramcore_csr_dfi_p1_ras_n = 1'd1; -reg litedramcore_csr_dfi_p1_we_n = 1'd1; -wire litedramcore_csr_dfi_p1_cke; -wire litedramcore_csr_dfi_p1_odt; -wire litedramcore_csr_dfi_p1_reset_n; -reg litedramcore_csr_dfi_p1_act_n = 1'd1; -wire [63:0] litedramcore_csr_dfi_p1_wrdata; -wire litedramcore_csr_dfi_p1_wrdata_en; -wire [7:0] litedramcore_csr_dfi_p1_wrdata_mask; -wire litedramcore_csr_dfi_p1_rddata_en; -reg [63:0] litedramcore_csr_dfi_p1_rddata = 64'd0; -reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0; -reg [14:0] litedramcore_ext_dfi_p0_address = 15'd0; -reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0; -reg litedramcore_ext_dfi_p0_cas_n = 1'd1; -reg litedramcore_ext_dfi_p0_cs_n = 1'd1; -reg litedramcore_ext_dfi_p0_ras_n = 1'd1; -reg litedramcore_ext_dfi_p0_we_n = 1'd1; -reg litedramcore_ext_dfi_p0_cke = 1'd0; -reg litedramcore_ext_dfi_p0_odt = 1'd0; -reg litedramcore_ext_dfi_p0_reset_n = 1'd0; -reg litedramcore_ext_dfi_p0_act_n = 1'd1; -reg [63:0] litedramcore_ext_dfi_p0_wrdata = 64'd0; -reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0; -reg [7:0] litedramcore_ext_dfi_p0_wrdata_mask = 8'd0; -reg litedramcore_ext_dfi_p0_rddata_en = 1'd0; -reg [63:0] litedramcore_ext_dfi_p0_rddata = 64'd0; -reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0; -reg [14:0] litedramcore_ext_dfi_p1_address = 15'd0; -reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0; -reg litedramcore_ext_dfi_p1_cas_n = 1'd1; -reg litedramcore_ext_dfi_p1_cs_n = 1'd1; -reg litedramcore_ext_dfi_p1_ras_n = 1'd1; -reg litedramcore_ext_dfi_p1_we_n = 1'd1; -reg litedramcore_ext_dfi_p1_cke = 1'd0; -reg litedramcore_ext_dfi_p1_odt = 1'd0; -reg litedramcore_ext_dfi_p1_reset_n = 1'd0; -reg litedramcore_ext_dfi_p1_act_n = 1'd1; -reg [63:0] litedramcore_ext_dfi_p1_wrdata = 64'd0; -reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0; -reg [7:0] litedramcore_ext_dfi_p1_wrdata_mask = 8'd0; -reg litedramcore_ext_dfi_p1_rddata_en = 1'd0; -reg [63:0] litedramcore_ext_dfi_p1_rddata = 64'd0; -reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0; -reg litedramcore_ext_dfi_sel = 1'd0; -wire litedramcore_sel; -wire litedramcore_cke; -wire litedramcore_odt; -wire litedramcore_reset_n; -reg [3:0] litedramcore_storage = 4'd1; -reg litedramcore_re = 1'd0; -wire litedramcore_phaseinjector0_csrfield_cs; -wire litedramcore_phaseinjector0_csrfield_we; -wire litedramcore_phaseinjector0_csrfield_cas; -wire litedramcore_phaseinjector0_csrfield_ras; -wire litedramcore_phaseinjector0_csrfield_wren; -wire litedramcore_phaseinjector0_csrfield_rden; -reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; -reg litedramcore_phaseinjector0_command_re = 1'd0; -reg litedramcore_phaseinjector0_command_issue_re = 1'd0; -wire litedramcore_phaseinjector0_command_issue_r; -reg litedramcore_phaseinjector0_command_issue_we = 1'd0; -reg litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [14:0] litedramcore_phaseinjector0_address_storage = 15'd0; -reg litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [63:0] litedramcore_phaseinjector0_wrdata_storage = 64'd0; -reg litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [63:0] litedramcore_phaseinjector0_rddata_status = 64'd0; -wire litedramcore_phaseinjector0_rddata_we; -reg litedramcore_phaseinjector0_rddata_re = 1'd0; -wire litedramcore_phaseinjector1_csrfield_cs; -wire litedramcore_phaseinjector1_csrfield_we; -wire litedramcore_phaseinjector1_csrfield_cas; -wire litedramcore_phaseinjector1_csrfield_ras; -wire litedramcore_phaseinjector1_csrfield_wren; -wire litedramcore_phaseinjector1_csrfield_rden; -reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0; -reg litedramcore_phaseinjector1_command_re = 1'd0; -reg litedramcore_phaseinjector1_command_issue_re = 1'd0; -wire litedramcore_phaseinjector1_command_issue_r; -reg litedramcore_phaseinjector1_command_issue_we = 1'd0; -reg litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [14:0] litedramcore_phaseinjector1_address_storage = 15'd0; -reg litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [63:0] litedramcore_phaseinjector1_wrdata_storage = 64'd0; -reg litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [63:0] litedramcore_phaseinjector1_rddata_status = 64'd0; -wire litedramcore_phaseinjector1_rddata_we; -reg litedramcore_phaseinjector1_rddata_re = 1'd0; -wire litedramcore_interface_bank0_valid; -wire litedramcore_interface_bank0_ready; -wire litedramcore_interface_bank0_we; -wire [21:0] litedramcore_interface_bank0_addr; -wire litedramcore_interface_bank0_lock; -wire litedramcore_interface_bank0_wdata_ready; -wire litedramcore_interface_bank0_rdata_valid; -wire litedramcore_interface_bank1_valid; -wire litedramcore_interface_bank1_ready; -wire litedramcore_interface_bank1_we; -wire [21:0] litedramcore_interface_bank1_addr; -wire litedramcore_interface_bank1_lock; -wire litedramcore_interface_bank1_wdata_ready; -wire litedramcore_interface_bank1_rdata_valid; -wire litedramcore_interface_bank2_valid; -wire litedramcore_interface_bank2_ready; -wire litedramcore_interface_bank2_we; -wire [21:0] litedramcore_interface_bank2_addr; -wire litedramcore_interface_bank2_lock; -wire litedramcore_interface_bank2_wdata_ready; -wire litedramcore_interface_bank2_rdata_valid; -wire litedramcore_interface_bank3_valid; -wire litedramcore_interface_bank3_ready; -wire litedramcore_interface_bank3_we; -wire [21:0] litedramcore_interface_bank3_addr; -wire litedramcore_interface_bank3_lock; -wire litedramcore_interface_bank3_wdata_ready; -wire litedramcore_interface_bank3_rdata_valid; -wire litedramcore_interface_bank4_valid; -wire litedramcore_interface_bank4_ready; -wire litedramcore_interface_bank4_we; -wire [21:0] litedramcore_interface_bank4_addr; -wire litedramcore_interface_bank4_lock; -wire litedramcore_interface_bank4_wdata_ready; -wire litedramcore_interface_bank4_rdata_valid; -wire litedramcore_interface_bank5_valid; -wire litedramcore_interface_bank5_ready; -wire litedramcore_interface_bank5_we; -wire [21:0] litedramcore_interface_bank5_addr; -wire litedramcore_interface_bank5_lock; -wire litedramcore_interface_bank5_wdata_ready; -wire litedramcore_interface_bank5_rdata_valid; -wire litedramcore_interface_bank6_valid; -wire litedramcore_interface_bank6_ready; -wire litedramcore_interface_bank6_we; -wire [21:0] litedramcore_interface_bank6_addr; -wire litedramcore_interface_bank6_lock; -wire litedramcore_interface_bank6_wdata_ready; -wire litedramcore_interface_bank6_rdata_valid; -wire litedramcore_interface_bank7_valid; -wire litedramcore_interface_bank7_ready; -wire litedramcore_interface_bank7_we; -wire [21:0] litedramcore_interface_bank7_addr; -wire litedramcore_interface_bank7_lock; -wire litedramcore_interface_bank7_wdata_ready; -wire litedramcore_interface_bank7_rdata_valid; -reg [127:0] litedramcore_interface_wdata = 128'd0; -reg [15:0] litedramcore_interface_wdata_we = 16'd0; -wire [127:0] litedramcore_interface_rdata; -reg [14:0] litedramcore_dfi_p0_address = 15'd0; -reg [2:0] litedramcore_dfi_p0_bank = 3'd0; -reg litedramcore_dfi_p0_cas_n = 1'd1; -reg litedramcore_dfi_p0_cs_n = 1'd1; -reg litedramcore_dfi_p0_ras_n = 1'd1; -reg litedramcore_dfi_p0_we_n = 1'd1; -wire litedramcore_dfi_p0_cke; -wire litedramcore_dfi_p0_odt; -wire litedramcore_dfi_p0_reset_n; -reg litedramcore_dfi_p0_act_n = 1'd1; -wire [63:0] litedramcore_dfi_p0_wrdata; -reg litedramcore_dfi_p0_wrdata_en = 1'd0; -wire [7:0] litedramcore_dfi_p0_wrdata_mask; -reg litedramcore_dfi_p0_rddata_en = 1'd0; -wire [63:0] litedramcore_dfi_p0_rddata; -wire litedramcore_dfi_p0_rddata_valid; -reg [14:0] litedramcore_dfi_p1_address = 15'd0; -reg [2:0] litedramcore_dfi_p1_bank = 3'd0; -reg litedramcore_dfi_p1_cas_n = 1'd1; -reg litedramcore_dfi_p1_cs_n = 1'd1; -reg litedramcore_dfi_p1_ras_n = 1'd1; -reg litedramcore_dfi_p1_we_n = 1'd1; -wire litedramcore_dfi_p1_cke; -wire litedramcore_dfi_p1_odt; -wire litedramcore_dfi_p1_reset_n; -reg litedramcore_dfi_p1_act_n = 1'd1; -wire [63:0] litedramcore_dfi_p1_wrdata; -reg litedramcore_dfi_p1_wrdata_en = 1'd0; -wire [7:0] litedramcore_dfi_p1_wrdata_mask; -reg litedramcore_dfi_p1_rddata_en = 1'd0; -wire [63:0] litedramcore_dfi_p1_rddata; -wire litedramcore_dfi_p1_rddata_valid; -reg litedramcore_cmd_valid = 1'd0; -reg litedramcore_cmd_ready = 1'd0; -reg litedramcore_cmd_last = 1'd0; -reg [14:0] litedramcore_cmd_payload_a = 15'd0; -reg [2:0] litedramcore_cmd_payload_ba = 3'd0; -reg litedramcore_cmd_payload_cas = 1'd0; -reg litedramcore_cmd_payload_ras = 1'd0; -reg litedramcore_cmd_payload_we = 1'd0; -reg litedramcore_cmd_payload_is_read = 1'd0; -reg litedramcore_cmd_payload_is_write = 1'd0; -wire litedramcore_wants_refresh; -wire litedramcore_wants_zqcs; -wire litedramcore_timer_wait; -wire litedramcore_timer_done0; -wire [8:0] litedramcore_timer_count0; -wire litedramcore_timer_done1; -reg [8:0] litedramcore_timer_count1 = 9'd374; -wire litedramcore_postponer_req_i; -reg litedramcore_postponer_req_o = 1'd0; -reg litedramcore_postponer_count = 1'd0; -reg litedramcore_sequencer_start0 = 1'd0; -wire litedramcore_sequencer_done0; -wire litedramcore_sequencer_start1; -reg litedramcore_sequencer_done1 = 1'd0; -reg [6:0] litedramcore_sequencer_counter = 7'd0; -reg litedramcore_sequencer_count = 1'd0; -wire litedramcore_zqcs_timer_wait; -wire litedramcore_zqcs_timer_done0; -wire [25:0] litedramcore_zqcs_timer_count0; -wire litedramcore_zqcs_timer_done1; -reg [25:0] litedramcore_zqcs_timer_count1 = 26'd47999999; -reg litedramcore_zqcs_executer_start = 1'd0; -reg litedramcore_zqcs_executer_done = 1'd0; -reg [5:0] litedramcore_zqcs_executer_counter = 6'd0; -wire litedramcore_bankmachine0_req_valid; -wire litedramcore_bankmachine0_req_ready; -wire litedramcore_bankmachine0_req_we; -wire [21:0] litedramcore_bankmachine0_req_addr; -wire litedramcore_bankmachine0_req_lock; -reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine0_refresh_req; -reg litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg litedramcore_bankmachine0_cmd_valid = 1'd0; -reg litedramcore_bankmachine0_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; -reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine0_auto_precharge = 1'd0; -wire litedramcore_bankmachine0_sink_valid; -wire litedramcore_bankmachine0_sink_ready; -reg litedramcore_bankmachine0_sink_first = 1'd0; -reg litedramcore_bankmachine0_sink_last = 1'd0; -wire litedramcore_bankmachine0_sink_payload_we; -wire [21:0] litedramcore_bankmachine0_sink_payload_addr; -wire litedramcore_bankmachine0_source_valid; -wire litedramcore_bankmachine0_source_ready; -wire litedramcore_bankmachine0_source_first; -wire litedramcore_bankmachine0_source_last; -wire litedramcore_bankmachine0_source_payload_we; -wire [21:0] litedramcore_bankmachine0_source_payload_addr; -wire litedramcore_bankmachine0_syncfifo0_we; -wire litedramcore_bankmachine0_syncfifo0_writable; -wire litedramcore_bankmachine0_syncfifo0_re; -wire litedramcore_bankmachine0_syncfifo0_readable; -wire [24:0] litedramcore_bankmachine0_syncfifo0_din; -wire [24:0] litedramcore_bankmachine0_syncfifo0_dout; -reg [4:0] litedramcore_bankmachine0_level = 5'd0; -reg litedramcore_bankmachine0_replace = 1'd0; -reg [3:0] litedramcore_bankmachine0_produce = 4'd0; +wire init_clk; +reg init_done_re = 1'd0; +reg init_done_storage = 1'd0; +reg init_error_re = 1'd0; +reg init_error_storage = 1'd0; +wire init_rst; +reg interface0_ack = 1'd0; +wire [29:0] interface0_adr; +wire [13:0] interface0_bank_bus_adr; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; +wire [31:0] interface0_bank_bus_dat_w; +wire interface0_bank_bus_we; +wire [1:0] interface0_bte; +wire [2:0] interface0_cti; +wire interface0_cyc; +reg [31:0] interface0_dat_r = 32'd0; +wire [31:0] interface0_dat_w; +reg interface0_err = 1'd0; +wire [3:0] interface0_sel; +wire interface0_stb; +wire interface0_we; +reg [13:0] interface1_adr = 14'd0; +reg [13:0] interface1_adr_next_value1 = 14'd0; +reg interface1_adr_next_value_ce1 = 1'd0; +wire [13:0] interface1_bank_bus_adr; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; +wire [31:0] interface1_bank_bus_dat_w; +wire interface1_bank_bus_we; +wire [31:0] interface1_dat_r; +reg [31:0] interface1_dat_w = 32'd0; +reg [31:0] interface1_dat_w_next_value0 = 32'd0; +reg interface1_dat_w_next_value_ce0 = 1'd0; +reg interface1_we = 1'd0; +reg interface1_we_next_value2 = 1'd0; +reg interface1_we_next_value_ce2 = 1'd0; +wire [13:0] interface2_bank_bus_adr; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; +wire [31:0] interface2_bank_bus_dat_w; +wire interface2_bank_bus_we; +wire latticeecp5asyncresetsynchronizerimpl0_expr; +wire latticeecp5asyncresetsynchronizerimpl0_rst1; +wire latticeecp5asyncresetsynchronizerimpl1_rst1; +wire latticeecp5asyncresetsynchronizerimpl2_rst1; +wire latticeecp5asyncresetsynchronizerimpl3_rst1; +reg litedramcore_bankmachine0_auto_precharge = 1'd0; +reg [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; +reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine0_cmd_ready = 1'd0; +reg litedramcore_bankmachine0_cmd_valid = 1'd0; reg [3:0] litedramcore_bankmachine0_consume = 4'd0; -reg [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine0_wrport_dat_r; -wire litedramcore_bankmachine0_wrport_we; -wire [24:0] litedramcore_bankmachine0_wrport_dat_w; wire litedramcore_bankmachine0_do_read; -wire [3:0] litedramcore_bankmachine0_rdport_adr; -wire [24:0] litedramcore_bankmachine0_rdport_dat_r; -wire litedramcore_bankmachine0_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine0_fifo_in_payload_addr; wire litedramcore_bankmachine0_fifo_in_first; wire litedramcore_bankmachine0_fifo_in_last; -wire litedramcore_bankmachine0_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine0_fifo_out_payload_addr; +wire [21:0] litedramcore_bankmachine0_fifo_in_payload_addr; +wire litedramcore_bankmachine0_fifo_in_payload_we; wire litedramcore_bankmachine0_fifo_out_first; wire litedramcore_bankmachine0_fifo_out_last; -wire litedramcore_bankmachine0_sink_sink_valid; -wire litedramcore_bankmachine0_sink_sink_ready; -wire litedramcore_bankmachine0_sink_sink_first; -wire litedramcore_bankmachine0_sink_sink_last; -wire litedramcore_bankmachine0_sink_sink_payload_we; -wire [21:0] litedramcore_bankmachine0_sink_sink_payload_addr; -wire litedramcore_bankmachine0_source_source_valid; -wire litedramcore_bankmachine0_source_source_ready; -wire litedramcore_bankmachine0_source_source_first; -wire litedramcore_bankmachine0_source_source_last; -wire litedramcore_bankmachine0_source_source_payload_we; -wire [21:0] litedramcore_bankmachine0_source_source_payload_addr; -wire litedramcore_bankmachine0_pipe_valid_sink_valid; -wire litedramcore_bankmachine0_pipe_valid_sink_ready; +wire [21:0] litedramcore_bankmachine0_fifo_out_payload_addr; +wire litedramcore_bankmachine0_fifo_out_payload_we; +reg [4:0] litedramcore_bankmachine0_level = 5'd0; +reg [2:0] litedramcore_bankmachine0_next_state = 3'd0; wire litedramcore_bankmachine0_pipe_valid_sink_first; wire litedramcore_bankmachine0_pipe_valid_sink_last; -wire litedramcore_bankmachine0_pipe_valid_sink_payload_we; wire [21:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine0_pipe_valid_source_ready; +wire litedramcore_bankmachine0_pipe_valid_sink_payload_we; +wire litedramcore_bankmachine0_pipe_valid_sink_ready; +wire litedramcore_bankmachine0_pipe_valid_sink_valid; reg litedramcore_bankmachine0_pipe_valid_source_first = 1'd0; reg litedramcore_bankmachine0_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; reg [21:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 22'd0; +reg litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; +wire litedramcore_bankmachine0_pipe_valid_source_ready; +reg litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; +reg [3:0] litedramcore_bankmachine0_produce = 4'd0; +wire [3:0] litedramcore_bankmachine0_rdport_adr; +wire [24:0] litedramcore_bankmachine0_rdport_dat_r; +reg litedramcore_bankmachine0_refresh_gnt = 1'd0; +wire litedramcore_bankmachine0_refresh_req; +reg litedramcore_bankmachine0_replace = 1'd0; +wire [21:0] litedramcore_bankmachine0_req_addr; +wire litedramcore_bankmachine0_req_lock; +reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine0_req_ready; +wire litedramcore_bankmachine0_req_valid; +reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; +wire litedramcore_bankmachine0_req_we; reg [14:0] litedramcore_bankmachine0_row = 15'd0; -reg litedramcore_bankmachine0_row_opened = 1'd0; -wire litedramcore_bankmachine0_row_hit; -reg litedramcore_bankmachine0_row_open = 1'd0; reg litedramcore_bankmachine0_row_close = 1'd0; reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine0_twtpcon_valid; -reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; -wire litedramcore_bankmachine0_trccon_valid; -reg litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [1:0] litedramcore_bankmachine0_trccon_count = 2'd0; -wire litedramcore_bankmachine0_trascon_valid; -reg litedramcore_bankmachine0_trascon_ready = 1'd0; +wire litedramcore_bankmachine0_row_hit; +reg litedramcore_bankmachine0_row_open = 1'd0; +reg litedramcore_bankmachine0_row_opened = 1'd0; +reg litedramcore_bankmachine0_sink_first = 1'd0; +reg litedramcore_bankmachine0_sink_last = 1'd0; +wire [21:0] litedramcore_bankmachine0_sink_payload_addr; +wire litedramcore_bankmachine0_sink_payload_we; +wire litedramcore_bankmachine0_sink_ready; +wire litedramcore_bankmachine0_sink_sink_first; +wire litedramcore_bankmachine0_sink_sink_last; +wire [21:0] litedramcore_bankmachine0_sink_sink_payload_addr; +wire litedramcore_bankmachine0_sink_sink_payload_we; +wire litedramcore_bankmachine0_sink_sink_ready; +wire litedramcore_bankmachine0_sink_sink_valid; +wire litedramcore_bankmachine0_sink_valid; +wire litedramcore_bankmachine0_source_first; +wire litedramcore_bankmachine0_source_last; +wire [21:0] litedramcore_bankmachine0_source_payload_addr; +wire litedramcore_bankmachine0_source_payload_we; +wire litedramcore_bankmachine0_source_ready; +wire litedramcore_bankmachine0_source_source_first; +wire litedramcore_bankmachine0_source_source_last; +wire [21:0] litedramcore_bankmachine0_source_source_payload_addr; +wire litedramcore_bankmachine0_source_source_payload_we; +wire litedramcore_bankmachine0_source_source_ready; +wire litedramcore_bankmachine0_source_source_valid; +wire litedramcore_bankmachine0_source_valid; +reg [2:0] litedramcore_bankmachine0_state = 3'd0; +wire [24:0] litedramcore_bankmachine0_syncfifo0_din; +wire [24:0] litedramcore_bankmachine0_syncfifo0_dout; +wire litedramcore_bankmachine0_syncfifo0_re; +wire litedramcore_bankmachine0_syncfifo0_readable; +wire litedramcore_bankmachine0_syncfifo0_we; +wire litedramcore_bankmachine0_syncfifo0_writable; reg [1:0] litedramcore_bankmachine0_trascon_count = 2'd0; -wire litedramcore_bankmachine1_req_valid; -wire litedramcore_bankmachine1_req_ready; -wire litedramcore_bankmachine1_req_we; -wire [21:0] litedramcore_bankmachine1_req_addr; -wire litedramcore_bankmachine1_req_lock; -reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine1_refresh_req; -reg litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg litedramcore_bankmachine1_cmd_valid = 1'd0; -reg litedramcore_bankmachine1_cmd_ready = 1'd0; +reg litedramcore_bankmachine0_trascon_ready = 1'd0; +wire litedramcore_bankmachine0_trascon_valid; +reg [1:0] litedramcore_bankmachine0_trccon_count = 2'd0; +reg litedramcore_bankmachine0_trccon_ready = 1'd0; +wire litedramcore_bankmachine0_trccon_valid; +reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; +reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; +wire litedramcore_bankmachine0_twtpcon_valid; +reg [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine0_wrport_dat_r; +wire [24:0] litedramcore_bankmachine0_wrport_dat_w; +wire litedramcore_bankmachine0_wrport_we; +reg litedramcore_bankmachine1_auto_precharge = 1'd0; reg [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0; wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine1_auto_precharge = 1'd0; -wire litedramcore_bankmachine1_sink_valid; -wire litedramcore_bankmachine1_sink_ready; -reg litedramcore_bankmachine1_sink_first = 1'd0; -reg litedramcore_bankmachine1_sink_last = 1'd0; -wire litedramcore_bankmachine1_sink_payload_we; -wire [21:0] litedramcore_bankmachine1_sink_payload_addr; -wire litedramcore_bankmachine1_source_valid; -wire litedramcore_bankmachine1_source_ready; -wire litedramcore_bankmachine1_source_first; -wire litedramcore_bankmachine1_source_last; -wire litedramcore_bankmachine1_source_payload_we; -wire [21:0] litedramcore_bankmachine1_source_payload_addr; -wire litedramcore_bankmachine1_syncfifo1_we; -wire litedramcore_bankmachine1_syncfifo1_writable; -wire litedramcore_bankmachine1_syncfifo1_re; -wire litedramcore_bankmachine1_syncfifo1_readable; -wire [24:0] litedramcore_bankmachine1_syncfifo1_din; -wire [24:0] litedramcore_bankmachine1_syncfifo1_dout; -reg [4:0] litedramcore_bankmachine1_level = 5'd0; -reg litedramcore_bankmachine1_replace = 1'd0; -reg [3:0] litedramcore_bankmachine1_produce = 4'd0; +reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine1_cmd_ready = 1'd0; +reg litedramcore_bankmachine1_cmd_valid = 1'd0; reg [3:0] litedramcore_bankmachine1_consume = 4'd0; -reg [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine1_wrport_dat_r; -wire litedramcore_bankmachine1_wrport_we; -wire [24:0] litedramcore_bankmachine1_wrport_dat_w; wire litedramcore_bankmachine1_do_read; -wire [3:0] litedramcore_bankmachine1_rdport_adr; -wire [24:0] litedramcore_bankmachine1_rdport_dat_r; -wire litedramcore_bankmachine1_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine1_fifo_in_payload_addr; wire litedramcore_bankmachine1_fifo_in_first; wire litedramcore_bankmachine1_fifo_in_last; -wire litedramcore_bankmachine1_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine1_fifo_out_payload_addr; +wire [21:0] litedramcore_bankmachine1_fifo_in_payload_addr; +wire litedramcore_bankmachine1_fifo_in_payload_we; wire litedramcore_bankmachine1_fifo_out_first; wire litedramcore_bankmachine1_fifo_out_last; -wire litedramcore_bankmachine1_sink_sink_valid; -wire litedramcore_bankmachine1_sink_sink_ready; -wire litedramcore_bankmachine1_sink_sink_first; -wire litedramcore_bankmachine1_sink_sink_last; -wire litedramcore_bankmachine1_sink_sink_payload_we; -wire [21:0] litedramcore_bankmachine1_sink_sink_payload_addr; -wire litedramcore_bankmachine1_source_source_valid; -wire litedramcore_bankmachine1_source_source_ready; -wire litedramcore_bankmachine1_source_source_first; -wire litedramcore_bankmachine1_source_source_last; -wire litedramcore_bankmachine1_source_source_payload_we; -wire [21:0] litedramcore_bankmachine1_source_source_payload_addr; -wire litedramcore_bankmachine1_pipe_valid_sink_valid; -wire litedramcore_bankmachine1_pipe_valid_sink_ready; +wire [21:0] litedramcore_bankmachine1_fifo_out_payload_addr; +wire litedramcore_bankmachine1_fifo_out_payload_we; +reg [4:0] litedramcore_bankmachine1_level = 5'd0; +reg [2:0] litedramcore_bankmachine1_next_state = 3'd0; wire litedramcore_bankmachine1_pipe_valid_sink_first; wire litedramcore_bankmachine1_pipe_valid_sink_last; -wire litedramcore_bankmachine1_pipe_valid_sink_payload_we; wire [21:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine1_pipe_valid_source_ready; +wire litedramcore_bankmachine1_pipe_valid_sink_payload_we; +wire litedramcore_bankmachine1_pipe_valid_sink_ready; +wire litedramcore_bankmachine1_pipe_valid_sink_valid; reg litedramcore_bankmachine1_pipe_valid_source_first = 1'd0; reg litedramcore_bankmachine1_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; reg [21:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 22'd0; +reg litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; +wire litedramcore_bankmachine1_pipe_valid_source_ready; +reg litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; +reg [3:0] litedramcore_bankmachine1_produce = 4'd0; +wire [3:0] litedramcore_bankmachine1_rdport_adr; +wire [24:0] litedramcore_bankmachine1_rdport_dat_r; +reg litedramcore_bankmachine1_refresh_gnt = 1'd0; +wire litedramcore_bankmachine1_refresh_req; +reg litedramcore_bankmachine1_replace = 1'd0; +wire [21:0] litedramcore_bankmachine1_req_addr; +wire litedramcore_bankmachine1_req_lock; +reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine1_req_ready; +wire litedramcore_bankmachine1_req_valid; +reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; +wire litedramcore_bankmachine1_req_we; reg [14:0] litedramcore_bankmachine1_row = 15'd0; -reg litedramcore_bankmachine1_row_opened = 1'd0; -wire litedramcore_bankmachine1_row_hit; -reg litedramcore_bankmachine1_row_open = 1'd0; reg litedramcore_bankmachine1_row_close = 1'd0; reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine1_twtpcon_valid; -reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; -wire litedramcore_bankmachine1_trccon_valid; -reg litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [1:0] litedramcore_bankmachine1_trccon_count = 2'd0; -wire litedramcore_bankmachine1_trascon_valid; -reg litedramcore_bankmachine1_trascon_ready = 1'd0; +wire litedramcore_bankmachine1_row_hit; +reg litedramcore_bankmachine1_row_open = 1'd0; +reg litedramcore_bankmachine1_row_opened = 1'd0; +reg litedramcore_bankmachine1_sink_first = 1'd0; +reg litedramcore_bankmachine1_sink_last = 1'd0; +wire [21:0] litedramcore_bankmachine1_sink_payload_addr; +wire litedramcore_bankmachine1_sink_payload_we; +wire litedramcore_bankmachine1_sink_ready; +wire litedramcore_bankmachine1_sink_sink_first; +wire litedramcore_bankmachine1_sink_sink_last; +wire [21:0] litedramcore_bankmachine1_sink_sink_payload_addr; +wire litedramcore_bankmachine1_sink_sink_payload_we; +wire litedramcore_bankmachine1_sink_sink_ready; +wire litedramcore_bankmachine1_sink_sink_valid; +wire litedramcore_bankmachine1_sink_valid; +wire litedramcore_bankmachine1_source_first; +wire litedramcore_bankmachine1_source_last; +wire [21:0] litedramcore_bankmachine1_source_payload_addr; +wire litedramcore_bankmachine1_source_payload_we; +wire litedramcore_bankmachine1_source_ready; +wire litedramcore_bankmachine1_source_source_first; +wire litedramcore_bankmachine1_source_source_last; +wire [21:0] litedramcore_bankmachine1_source_source_payload_addr; +wire litedramcore_bankmachine1_source_source_payload_we; +wire litedramcore_bankmachine1_source_source_ready; +wire litedramcore_bankmachine1_source_source_valid; +wire litedramcore_bankmachine1_source_valid; +reg [2:0] litedramcore_bankmachine1_state = 3'd0; +wire [24:0] litedramcore_bankmachine1_syncfifo1_din; +wire [24:0] litedramcore_bankmachine1_syncfifo1_dout; +wire litedramcore_bankmachine1_syncfifo1_re; +wire litedramcore_bankmachine1_syncfifo1_readable; +wire litedramcore_bankmachine1_syncfifo1_we; +wire litedramcore_bankmachine1_syncfifo1_writable; reg [1:0] litedramcore_bankmachine1_trascon_count = 2'd0; -wire litedramcore_bankmachine2_req_valid; -wire litedramcore_bankmachine2_req_ready; -wire litedramcore_bankmachine2_req_we; -wire [21:0] litedramcore_bankmachine2_req_addr; -wire litedramcore_bankmachine2_req_lock; -reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine2_refresh_req; -reg litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg litedramcore_bankmachine2_cmd_valid = 1'd0; -reg litedramcore_bankmachine2_cmd_ready = 1'd0; +reg litedramcore_bankmachine1_trascon_ready = 1'd0; +wire litedramcore_bankmachine1_trascon_valid; +reg [1:0] litedramcore_bankmachine1_trccon_count = 2'd0; +reg litedramcore_bankmachine1_trccon_ready = 1'd0; +wire litedramcore_bankmachine1_trccon_valid; +reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; +reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; +wire litedramcore_bankmachine1_twtpcon_valid; +reg [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine1_wrport_dat_r; +wire [24:0] litedramcore_bankmachine1_wrport_dat_w; +wire litedramcore_bankmachine1_wrport_we; +reg litedramcore_bankmachine2_auto_precharge = 1'd0; reg [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0; wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine2_auto_precharge = 1'd0; -wire litedramcore_bankmachine2_sink_valid; -wire litedramcore_bankmachine2_sink_ready; -reg litedramcore_bankmachine2_sink_first = 1'd0; -reg litedramcore_bankmachine2_sink_last = 1'd0; -wire litedramcore_bankmachine2_sink_payload_we; -wire [21:0] litedramcore_bankmachine2_sink_payload_addr; -wire litedramcore_bankmachine2_source_valid; -wire litedramcore_bankmachine2_source_ready; -wire litedramcore_bankmachine2_source_first; -wire litedramcore_bankmachine2_source_last; -wire litedramcore_bankmachine2_source_payload_we; -wire [21:0] litedramcore_bankmachine2_source_payload_addr; -wire litedramcore_bankmachine2_syncfifo2_we; -wire litedramcore_bankmachine2_syncfifo2_writable; -wire litedramcore_bankmachine2_syncfifo2_re; -wire litedramcore_bankmachine2_syncfifo2_readable; -wire [24:0] litedramcore_bankmachine2_syncfifo2_din; -wire [24:0] litedramcore_bankmachine2_syncfifo2_dout; -reg [4:0] litedramcore_bankmachine2_level = 5'd0; -reg litedramcore_bankmachine2_replace = 1'd0; -reg [3:0] litedramcore_bankmachine2_produce = 4'd0; +reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine2_cmd_ready = 1'd0; +reg litedramcore_bankmachine2_cmd_valid = 1'd0; reg [3:0] litedramcore_bankmachine2_consume = 4'd0; -reg [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine2_wrport_dat_r; -wire litedramcore_bankmachine2_wrport_we; -wire [24:0] litedramcore_bankmachine2_wrport_dat_w; wire litedramcore_bankmachine2_do_read; -wire [3:0] litedramcore_bankmachine2_rdport_adr; -wire [24:0] litedramcore_bankmachine2_rdport_dat_r; -wire litedramcore_bankmachine2_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine2_fifo_in_payload_addr; wire litedramcore_bankmachine2_fifo_in_first; wire litedramcore_bankmachine2_fifo_in_last; -wire litedramcore_bankmachine2_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine2_fifo_out_payload_addr; +wire [21:0] litedramcore_bankmachine2_fifo_in_payload_addr; +wire litedramcore_bankmachine2_fifo_in_payload_we; wire litedramcore_bankmachine2_fifo_out_first; wire litedramcore_bankmachine2_fifo_out_last; -wire litedramcore_bankmachine2_sink_sink_valid; -wire litedramcore_bankmachine2_sink_sink_ready; -wire litedramcore_bankmachine2_sink_sink_first; -wire litedramcore_bankmachine2_sink_sink_last; -wire litedramcore_bankmachine2_sink_sink_payload_we; -wire [21:0] litedramcore_bankmachine2_sink_sink_payload_addr; -wire litedramcore_bankmachine2_source_source_valid; -wire litedramcore_bankmachine2_source_source_ready; -wire litedramcore_bankmachine2_source_source_first; -wire litedramcore_bankmachine2_source_source_last; -wire litedramcore_bankmachine2_source_source_payload_we; -wire [21:0] litedramcore_bankmachine2_source_source_payload_addr; -wire litedramcore_bankmachine2_pipe_valid_sink_valid; -wire litedramcore_bankmachine2_pipe_valid_sink_ready; +wire [21:0] litedramcore_bankmachine2_fifo_out_payload_addr; +wire litedramcore_bankmachine2_fifo_out_payload_we; +reg [4:0] litedramcore_bankmachine2_level = 5'd0; +reg [2:0] litedramcore_bankmachine2_next_state = 3'd0; wire litedramcore_bankmachine2_pipe_valid_sink_first; wire litedramcore_bankmachine2_pipe_valid_sink_last; -wire litedramcore_bankmachine2_pipe_valid_sink_payload_we; wire [21:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine2_pipe_valid_source_ready; +wire litedramcore_bankmachine2_pipe_valid_sink_payload_we; +wire litedramcore_bankmachine2_pipe_valid_sink_ready; +wire litedramcore_bankmachine2_pipe_valid_sink_valid; reg litedramcore_bankmachine2_pipe_valid_source_first = 1'd0; reg litedramcore_bankmachine2_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; reg [21:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 22'd0; +reg litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; +wire litedramcore_bankmachine2_pipe_valid_source_ready; +reg litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; +reg [3:0] litedramcore_bankmachine2_produce = 4'd0; +wire [3:0] litedramcore_bankmachine2_rdport_adr; +wire [24:0] litedramcore_bankmachine2_rdport_dat_r; +reg litedramcore_bankmachine2_refresh_gnt = 1'd0; +wire litedramcore_bankmachine2_refresh_req; +reg litedramcore_bankmachine2_replace = 1'd0; +wire [21:0] litedramcore_bankmachine2_req_addr; +wire litedramcore_bankmachine2_req_lock; +reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine2_req_ready; +wire litedramcore_bankmachine2_req_valid; +reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; +wire litedramcore_bankmachine2_req_we; reg [14:0] litedramcore_bankmachine2_row = 15'd0; -reg litedramcore_bankmachine2_row_opened = 1'd0; -wire litedramcore_bankmachine2_row_hit; -reg litedramcore_bankmachine2_row_open = 1'd0; reg litedramcore_bankmachine2_row_close = 1'd0; reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine2_twtpcon_valid; -reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; -wire litedramcore_bankmachine2_trccon_valid; -reg litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [1:0] litedramcore_bankmachine2_trccon_count = 2'd0; -wire litedramcore_bankmachine2_trascon_valid; -reg litedramcore_bankmachine2_trascon_ready = 1'd0; +wire litedramcore_bankmachine2_row_hit; +reg litedramcore_bankmachine2_row_open = 1'd0; +reg litedramcore_bankmachine2_row_opened = 1'd0; +reg litedramcore_bankmachine2_sink_first = 1'd0; +reg litedramcore_bankmachine2_sink_last = 1'd0; +wire [21:0] litedramcore_bankmachine2_sink_payload_addr; +wire litedramcore_bankmachine2_sink_payload_we; +wire litedramcore_bankmachine2_sink_ready; +wire litedramcore_bankmachine2_sink_sink_first; +wire litedramcore_bankmachine2_sink_sink_last; +wire [21:0] litedramcore_bankmachine2_sink_sink_payload_addr; +wire litedramcore_bankmachine2_sink_sink_payload_we; +wire litedramcore_bankmachine2_sink_sink_ready; +wire litedramcore_bankmachine2_sink_sink_valid; +wire litedramcore_bankmachine2_sink_valid; +wire litedramcore_bankmachine2_source_first; +wire litedramcore_bankmachine2_source_last; +wire [21:0] litedramcore_bankmachine2_source_payload_addr; +wire litedramcore_bankmachine2_source_payload_we; +wire litedramcore_bankmachine2_source_ready; +wire litedramcore_bankmachine2_source_source_first; +wire litedramcore_bankmachine2_source_source_last; +wire [21:0] litedramcore_bankmachine2_source_source_payload_addr; +wire litedramcore_bankmachine2_source_source_payload_we; +wire litedramcore_bankmachine2_source_source_ready; +wire litedramcore_bankmachine2_source_source_valid; +wire litedramcore_bankmachine2_source_valid; +reg [2:0] litedramcore_bankmachine2_state = 3'd0; +wire [24:0] litedramcore_bankmachine2_syncfifo2_din; +wire [24:0] litedramcore_bankmachine2_syncfifo2_dout; +wire litedramcore_bankmachine2_syncfifo2_re; +wire litedramcore_bankmachine2_syncfifo2_readable; +wire litedramcore_bankmachine2_syncfifo2_we; +wire litedramcore_bankmachine2_syncfifo2_writable; reg [1:0] litedramcore_bankmachine2_trascon_count = 2'd0; -wire litedramcore_bankmachine3_req_valid; -wire litedramcore_bankmachine3_req_ready; -wire litedramcore_bankmachine3_req_we; -wire [21:0] litedramcore_bankmachine3_req_addr; -wire litedramcore_bankmachine3_req_lock; -reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine3_refresh_req; -reg litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg litedramcore_bankmachine3_cmd_valid = 1'd0; -reg litedramcore_bankmachine3_cmd_ready = 1'd0; +reg litedramcore_bankmachine2_trascon_ready = 1'd0; +wire litedramcore_bankmachine2_trascon_valid; +reg [1:0] litedramcore_bankmachine2_trccon_count = 2'd0; +reg litedramcore_bankmachine2_trccon_ready = 1'd0; +wire litedramcore_bankmachine2_trccon_valid; +reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; +reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; +wire litedramcore_bankmachine2_twtpcon_valid; +reg [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine2_wrport_dat_r; +wire [24:0] litedramcore_bankmachine2_wrport_dat_w; +wire litedramcore_bankmachine2_wrport_we; +reg litedramcore_bankmachine3_auto_precharge = 1'd0; reg [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0; wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine3_auto_precharge = 1'd0; -wire litedramcore_bankmachine3_sink_valid; -wire litedramcore_bankmachine3_sink_ready; -reg litedramcore_bankmachine3_sink_first = 1'd0; -reg litedramcore_bankmachine3_sink_last = 1'd0; -wire litedramcore_bankmachine3_sink_payload_we; -wire [21:0] litedramcore_bankmachine3_sink_payload_addr; -wire litedramcore_bankmachine3_source_valid; -wire litedramcore_bankmachine3_source_ready; -wire litedramcore_bankmachine3_source_first; -wire litedramcore_bankmachine3_source_last; -wire litedramcore_bankmachine3_source_payload_we; -wire [21:0] litedramcore_bankmachine3_source_payload_addr; -wire litedramcore_bankmachine3_syncfifo3_we; -wire litedramcore_bankmachine3_syncfifo3_writable; -wire litedramcore_bankmachine3_syncfifo3_re; -wire litedramcore_bankmachine3_syncfifo3_readable; -wire [24:0] litedramcore_bankmachine3_syncfifo3_din; -wire [24:0] litedramcore_bankmachine3_syncfifo3_dout; -reg [4:0] litedramcore_bankmachine3_level = 5'd0; -reg litedramcore_bankmachine3_replace = 1'd0; -reg [3:0] litedramcore_bankmachine3_produce = 4'd0; +reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine3_cmd_ready = 1'd0; +reg litedramcore_bankmachine3_cmd_valid = 1'd0; reg [3:0] litedramcore_bankmachine3_consume = 4'd0; -reg [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine3_wrport_dat_r; -wire litedramcore_bankmachine3_wrport_we; -wire [24:0] litedramcore_bankmachine3_wrport_dat_w; wire litedramcore_bankmachine3_do_read; -wire [3:0] litedramcore_bankmachine3_rdport_adr; -wire [24:0] litedramcore_bankmachine3_rdport_dat_r; -wire litedramcore_bankmachine3_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine3_fifo_in_payload_addr; wire litedramcore_bankmachine3_fifo_in_first; wire litedramcore_bankmachine3_fifo_in_last; -wire litedramcore_bankmachine3_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine3_fifo_out_payload_addr; +wire [21:0] litedramcore_bankmachine3_fifo_in_payload_addr; +wire litedramcore_bankmachine3_fifo_in_payload_we; wire litedramcore_bankmachine3_fifo_out_first; wire litedramcore_bankmachine3_fifo_out_last; -wire litedramcore_bankmachine3_sink_sink_valid; -wire litedramcore_bankmachine3_sink_sink_ready; -wire litedramcore_bankmachine3_sink_sink_first; -wire litedramcore_bankmachine3_sink_sink_last; -wire litedramcore_bankmachine3_sink_sink_payload_we; -wire [21:0] litedramcore_bankmachine3_sink_sink_payload_addr; -wire litedramcore_bankmachine3_source_source_valid; -wire litedramcore_bankmachine3_source_source_ready; -wire litedramcore_bankmachine3_source_source_first; -wire litedramcore_bankmachine3_source_source_last; -wire litedramcore_bankmachine3_source_source_payload_we; -wire [21:0] litedramcore_bankmachine3_source_source_payload_addr; -wire litedramcore_bankmachine3_pipe_valid_sink_valid; -wire litedramcore_bankmachine3_pipe_valid_sink_ready; +wire [21:0] litedramcore_bankmachine3_fifo_out_payload_addr; +wire litedramcore_bankmachine3_fifo_out_payload_we; +reg [4:0] litedramcore_bankmachine3_level = 5'd0; +reg [2:0] litedramcore_bankmachine3_next_state = 3'd0; wire litedramcore_bankmachine3_pipe_valid_sink_first; wire litedramcore_bankmachine3_pipe_valid_sink_last; -wire litedramcore_bankmachine3_pipe_valid_sink_payload_we; wire [21:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine3_pipe_valid_source_ready; +wire litedramcore_bankmachine3_pipe_valid_sink_payload_we; +wire litedramcore_bankmachine3_pipe_valid_sink_ready; +wire litedramcore_bankmachine3_pipe_valid_sink_valid; reg litedramcore_bankmachine3_pipe_valid_source_first = 1'd0; reg litedramcore_bankmachine3_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; reg [21:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 22'd0; +reg litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; +wire litedramcore_bankmachine3_pipe_valid_source_ready; +reg litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; +reg [3:0] litedramcore_bankmachine3_produce = 4'd0; +wire [3:0] litedramcore_bankmachine3_rdport_adr; +wire [24:0] litedramcore_bankmachine3_rdport_dat_r; +reg litedramcore_bankmachine3_refresh_gnt = 1'd0; +wire litedramcore_bankmachine3_refresh_req; +reg litedramcore_bankmachine3_replace = 1'd0; +wire [21:0] litedramcore_bankmachine3_req_addr; +wire litedramcore_bankmachine3_req_lock; +reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine3_req_ready; +wire litedramcore_bankmachine3_req_valid; +reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; +wire litedramcore_bankmachine3_req_we; reg [14:0] litedramcore_bankmachine3_row = 15'd0; -reg litedramcore_bankmachine3_row_opened = 1'd0; -wire litedramcore_bankmachine3_row_hit; -reg litedramcore_bankmachine3_row_open = 1'd0; reg litedramcore_bankmachine3_row_close = 1'd0; reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine3_twtpcon_valid; -reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; -wire litedramcore_bankmachine3_trccon_valid; -reg litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [1:0] litedramcore_bankmachine3_trccon_count = 2'd0; -wire litedramcore_bankmachine3_trascon_valid; -reg litedramcore_bankmachine3_trascon_ready = 1'd0; +wire litedramcore_bankmachine3_row_hit; +reg litedramcore_bankmachine3_row_open = 1'd0; +reg litedramcore_bankmachine3_row_opened = 1'd0; +reg litedramcore_bankmachine3_sink_first = 1'd0; +reg litedramcore_bankmachine3_sink_last = 1'd0; +wire [21:0] litedramcore_bankmachine3_sink_payload_addr; +wire litedramcore_bankmachine3_sink_payload_we; +wire litedramcore_bankmachine3_sink_ready; +wire litedramcore_bankmachine3_sink_sink_first; +wire litedramcore_bankmachine3_sink_sink_last; +wire [21:0] litedramcore_bankmachine3_sink_sink_payload_addr; +wire litedramcore_bankmachine3_sink_sink_payload_we; +wire litedramcore_bankmachine3_sink_sink_ready; +wire litedramcore_bankmachine3_sink_sink_valid; +wire litedramcore_bankmachine3_sink_valid; +wire litedramcore_bankmachine3_source_first; +wire litedramcore_bankmachine3_source_last; +wire [21:0] litedramcore_bankmachine3_source_payload_addr; +wire litedramcore_bankmachine3_source_payload_we; +wire litedramcore_bankmachine3_source_ready; +wire litedramcore_bankmachine3_source_source_first; +wire litedramcore_bankmachine3_source_source_last; +wire [21:0] litedramcore_bankmachine3_source_source_payload_addr; +wire litedramcore_bankmachine3_source_source_payload_we; +wire litedramcore_bankmachine3_source_source_ready; +wire litedramcore_bankmachine3_source_source_valid; +wire litedramcore_bankmachine3_source_valid; +reg [2:0] litedramcore_bankmachine3_state = 3'd0; +wire [24:0] litedramcore_bankmachine3_syncfifo3_din; +wire [24:0] litedramcore_bankmachine3_syncfifo3_dout; +wire litedramcore_bankmachine3_syncfifo3_re; +wire litedramcore_bankmachine3_syncfifo3_readable; +wire litedramcore_bankmachine3_syncfifo3_we; +wire litedramcore_bankmachine3_syncfifo3_writable; reg [1:0] litedramcore_bankmachine3_trascon_count = 2'd0; -wire litedramcore_bankmachine4_req_valid; -wire litedramcore_bankmachine4_req_ready; -wire litedramcore_bankmachine4_req_we; -wire [21:0] litedramcore_bankmachine4_req_addr; -wire litedramcore_bankmachine4_req_lock; -reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine4_refresh_req; -reg litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg litedramcore_bankmachine4_cmd_valid = 1'd0; -reg litedramcore_bankmachine4_cmd_ready = 1'd0; +reg litedramcore_bankmachine3_trascon_ready = 1'd0; +wire litedramcore_bankmachine3_trascon_valid; +reg [1:0] litedramcore_bankmachine3_trccon_count = 2'd0; +reg litedramcore_bankmachine3_trccon_ready = 1'd0; +wire litedramcore_bankmachine3_trccon_valid; +reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; +reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; +wire litedramcore_bankmachine3_twtpcon_valid; +reg [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine3_wrport_dat_r; +wire [24:0] litedramcore_bankmachine3_wrport_dat_w; +wire litedramcore_bankmachine3_wrport_we; +reg litedramcore_bankmachine4_auto_precharge = 1'd0; reg [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0; wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine4_auto_precharge = 1'd0; -wire litedramcore_bankmachine4_sink_valid; -wire litedramcore_bankmachine4_sink_ready; -reg litedramcore_bankmachine4_sink_first = 1'd0; -reg litedramcore_bankmachine4_sink_last = 1'd0; -wire litedramcore_bankmachine4_sink_payload_we; -wire [21:0] litedramcore_bankmachine4_sink_payload_addr; -wire litedramcore_bankmachine4_source_valid; -wire litedramcore_bankmachine4_source_ready; -wire litedramcore_bankmachine4_source_first; -wire litedramcore_bankmachine4_source_last; -wire litedramcore_bankmachine4_source_payload_we; -wire [21:0] litedramcore_bankmachine4_source_payload_addr; -wire litedramcore_bankmachine4_syncfifo4_we; -wire litedramcore_bankmachine4_syncfifo4_writable; -wire litedramcore_bankmachine4_syncfifo4_re; -wire litedramcore_bankmachine4_syncfifo4_readable; -wire [24:0] litedramcore_bankmachine4_syncfifo4_din; -wire [24:0] litedramcore_bankmachine4_syncfifo4_dout; -reg [4:0] litedramcore_bankmachine4_level = 5'd0; -reg litedramcore_bankmachine4_replace = 1'd0; -reg [3:0] litedramcore_bankmachine4_produce = 4'd0; +reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine4_cmd_ready = 1'd0; +reg litedramcore_bankmachine4_cmd_valid = 1'd0; reg [3:0] litedramcore_bankmachine4_consume = 4'd0; -reg [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine4_wrport_dat_r; -wire litedramcore_bankmachine4_wrport_we; -wire [24:0] litedramcore_bankmachine4_wrport_dat_w; wire litedramcore_bankmachine4_do_read; -wire [3:0] litedramcore_bankmachine4_rdport_adr; -wire [24:0] litedramcore_bankmachine4_rdport_dat_r; -wire litedramcore_bankmachine4_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine4_fifo_in_payload_addr; wire litedramcore_bankmachine4_fifo_in_first; wire litedramcore_bankmachine4_fifo_in_last; -wire litedramcore_bankmachine4_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine4_fifo_out_payload_addr; +wire [21:0] litedramcore_bankmachine4_fifo_in_payload_addr; +wire litedramcore_bankmachine4_fifo_in_payload_we; wire litedramcore_bankmachine4_fifo_out_first; wire litedramcore_bankmachine4_fifo_out_last; -wire litedramcore_bankmachine4_sink_sink_valid; -wire litedramcore_bankmachine4_sink_sink_ready; -wire litedramcore_bankmachine4_sink_sink_first; -wire litedramcore_bankmachine4_sink_sink_last; -wire litedramcore_bankmachine4_sink_sink_payload_we; -wire [21:0] litedramcore_bankmachine4_sink_sink_payload_addr; -wire litedramcore_bankmachine4_source_source_valid; -wire litedramcore_bankmachine4_source_source_ready; -wire litedramcore_bankmachine4_source_source_first; -wire litedramcore_bankmachine4_source_source_last; -wire litedramcore_bankmachine4_source_source_payload_we; -wire [21:0] litedramcore_bankmachine4_source_source_payload_addr; -wire litedramcore_bankmachine4_pipe_valid_sink_valid; -wire litedramcore_bankmachine4_pipe_valid_sink_ready; +wire [21:0] litedramcore_bankmachine4_fifo_out_payload_addr; +wire litedramcore_bankmachine4_fifo_out_payload_we; +reg [4:0] litedramcore_bankmachine4_level = 5'd0; +reg [2:0] litedramcore_bankmachine4_next_state = 3'd0; wire litedramcore_bankmachine4_pipe_valid_sink_first; wire litedramcore_bankmachine4_pipe_valid_sink_last; -wire litedramcore_bankmachine4_pipe_valid_sink_payload_we; wire [21:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine4_pipe_valid_source_ready; +wire litedramcore_bankmachine4_pipe_valid_sink_payload_we; +wire litedramcore_bankmachine4_pipe_valid_sink_ready; +wire litedramcore_bankmachine4_pipe_valid_sink_valid; reg litedramcore_bankmachine4_pipe_valid_source_first = 1'd0; reg litedramcore_bankmachine4_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; reg [21:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 22'd0; +reg litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; +wire litedramcore_bankmachine4_pipe_valid_source_ready; +reg litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; +reg [3:0] litedramcore_bankmachine4_produce = 4'd0; +wire [3:0] litedramcore_bankmachine4_rdport_adr; +wire [24:0] litedramcore_bankmachine4_rdport_dat_r; +reg litedramcore_bankmachine4_refresh_gnt = 1'd0; +wire litedramcore_bankmachine4_refresh_req; +reg litedramcore_bankmachine4_replace = 1'd0; +wire [21:0] litedramcore_bankmachine4_req_addr; +wire litedramcore_bankmachine4_req_lock; +reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine4_req_ready; +wire litedramcore_bankmachine4_req_valid; +reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; +wire litedramcore_bankmachine4_req_we; reg [14:0] litedramcore_bankmachine4_row = 15'd0; -reg litedramcore_bankmachine4_row_opened = 1'd0; -wire litedramcore_bankmachine4_row_hit; -reg litedramcore_bankmachine4_row_open = 1'd0; reg litedramcore_bankmachine4_row_close = 1'd0; reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine4_twtpcon_valid; -reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; -wire litedramcore_bankmachine4_trccon_valid; -reg litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [1:0] litedramcore_bankmachine4_trccon_count = 2'd0; -wire litedramcore_bankmachine4_trascon_valid; -reg litedramcore_bankmachine4_trascon_ready = 1'd0; +wire litedramcore_bankmachine4_row_hit; +reg litedramcore_bankmachine4_row_open = 1'd0; +reg litedramcore_bankmachine4_row_opened = 1'd0; +reg litedramcore_bankmachine4_sink_first = 1'd0; +reg litedramcore_bankmachine4_sink_last = 1'd0; +wire [21:0] litedramcore_bankmachine4_sink_payload_addr; +wire litedramcore_bankmachine4_sink_payload_we; +wire litedramcore_bankmachine4_sink_ready; +wire litedramcore_bankmachine4_sink_sink_first; +wire litedramcore_bankmachine4_sink_sink_last; +wire [21:0] litedramcore_bankmachine4_sink_sink_payload_addr; +wire litedramcore_bankmachine4_sink_sink_payload_we; +wire litedramcore_bankmachine4_sink_sink_ready; +wire litedramcore_bankmachine4_sink_sink_valid; +wire litedramcore_bankmachine4_sink_valid; +wire litedramcore_bankmachine4_source_first; +wire litedramcore_bankmachine4_source_last; +wire [21:0] litedramcore_bankmachine4_source_payload_addr; +wire litedramcore_bankmachine4_source_payload_we; +wire litedramcore_bankmachine4_source_ready; +wire litedramcore_bankmachine4_source_source_first; +wire litedramcore_bankmachine4_source_source_last; +wire [21:0] litedramcore_bankmachine4_source_source_payload_addr; +wire litedramcore_bankmachine4_source_source_payload_we; +wire litedramcore_bankmachine4_source_source_ready; +wire litedramcore_bankmachine4_source_source_valid; +wire litedramcore_bankmachine4_source_valid; +reg [2:0] litedramcore_bankmachine4_state = 3'd0; +wire [24:0] litedramcore_bankmachine4_syncfifo4_din; +wire [24:0] litedramcore_bankmachine4_syncfifo4_dout; +wire litedramcore_bankmachine4_syncfifo4_re; +wire litedramcore_bankmachine4_syncfifo4_readable; +wire litedramcore_bankmachine4_syncfifo4_we; +wire litedramcore_bankmachine4_syncfifo4_writable; reg [1:0] litedramcore_bankmachine4_trascon_count = 2'd0; -wire litedramcore_bankmachine5_req_valid; -wire litedramcore_bankmachine5_req_ready; -wire litedramcore_bankmachine5_req_we; -wire [21:0] litedramcore_bankmachine5_req_addr; -wire litedramcore_bankmachine5_req_lock; -reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine5_refresh_req; -reg litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg litedramcore_bankmachine5_cmd_valid = 1'd0; -reg litedramcore_bankmachine5_cmd_ready = 1'd0; +reg litedramcore_bankmachine4_trascon_ready = 1'd0; +wire litedramcore_bankmachine4_trascon_valid; +reg [1:0] litedramcore_bankmachine4_trccon_count = 2'd0; +reg litedramcore_bankmachine4_trccon_ready = 1'd0; +wire litedramcore_bankmachine4_trccon_valid; +reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; +reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; +wire litedramcore_bankmachine4_twtpcon_valid; +reg [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine4_wrport_dat_r; +wire [24:0] litedramcore_bankmachine4_wrport_dat_w; +wire litedramcore_bankmachine4_wrport_we; +reg litedramcore_bankmachine5_auto_precharge = 1'd0; reg [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0; wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine5_auto_precharge = 1'd0; -wire litedramcore_bankmachine5_sink_valid; -wire litedramcore_bankmachine5_sink_ready; -reg litedramcore_bankmachine5_sink_first = 1'd0; -reg litedramcore_bankmachine5_sink_last = 1'd0; -wire litedramcore_bankmachine5_sink_payload_we; -wire [21:0] litedramcore_bankmachine5_sink_payload_addr; -wire litedramcore_bankmachine5_source_valid; -wire litedramcore_bankmachine5_source_ready; -wire litedramcore_bankmachine5_source_first; -wire litedramcore_bankmachine5_source_last; -wire litedramcore_bankmachine5_source_payload_we; -wire [21:0] litedramcore_bankmachine5_source_payload_addr; -wire litedramcore_bankmachine5_syncfifo5_we; -wire litedramcore_bankmachine5_syncfifo5_writable; -wire litedramcore_bankmachine5_syncfifo5_re; -wire litedramcore_bankmachine5_syncfifo5_readable; -wire [24:0] litedramcore_bankmachine5_syncfifo5_din; -wire [24:0] litedramcore_bankmachine5_syncfifo5_dout; -reg [4:0] litedramcore_bankmachine5_level = 5'd0; -reg litedramcore_bankmachine5_replace = 1'd0; -reg [3:0] litedramcore_bankmachine5_produce = 4'd0; +reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine5_cmd_ready = 1'd0; +reg litedramcore_bankmachine5_cmd_valid = 1'd0; reg [3:0] litedramcore_bankmachine5_consume = 4'd0; -reg [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine5_wrport_dat_r; -wire litedramcore_bankmachine5_wrport_we; -wire [24:0] litedramcore_bankmachine5_wrport_dat_w; -wire litedramcore_bankmachine5_do_read; -wire [3:0] litedramcore_bankmachine5_rdport_adr; -wire [24:0] litedramcore_bankmachine5_rdport_dat_r; -wire litedramcore_bankmachine5_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine5_fifo_in_payload_addr; +wire litedramcore_bankmachine5_do_read; wire litedramcore_bankmachine5_fifo_in_first; wire litedramcore_bankmachine5_fifo_in_last; -wire litedramcore_bankmachine5_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine5_fifo_out_payload_addr; +wire [21:0] litedramcore_bankmachine5_fifo_in_payload_addr; +wire litedramcore_bankmachine5_fifo_in_payload_we; wire litedramcore_bankmachine5_fifo_out_first; wire litedramcore_bankmachine5_fifo_out_last; -wire litedramcore_bankmachine5_sink_sink_valid; -wire litedramcore_bankmachine5_sink_sink_ready; -wire litedramcore_bankmachine5_sink_sink_first; -wire litedramcore_bankmachine5_sink_sink_last; -wire litedramcore_bankmachine5_sink_sink_payload_we; -wire [21:0] litedramcore_bankmachine5_sink_sink_payload_addr; -wire litedramcore_bankmachine5_source_source_valid; -wire litedramcore_bankmachine5_source_source_ready; -wire litedramcore_bankmachine5_source_source_first; -wire litedramcore_bankmachine5_source_source_last; -wire litedramcore_bankmachine5_source_source_payload_we; -wire [21:0] litedramcore_bankmachine5_source_source_payload_addr; -wire litedramcore_bankmachine5_pipe_valid_sink_valid; -wire litedramcore_bankmachine5_pipe_valid_sink_ready; +wire [21:0] litedramcore_bankmachine5_fifo_out_payload_addr; +wire litedramcore_bankmachine5_fifo_out_payload_we; +reg [4:0] litedramcore_bankmachine5_level = 5'd0; +reg [2:0] litedramcore_bankmachine5_next_state = 3'd0; wire litedramcore_bankmachine5_pipe_valid_sink_first; wire litedramcore_bankmachine5_pipe_valid_sink_last; -wire litedramcore_bankmachine5_pipe_valid_sink_payload_we; wire [21:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine5_pipe_valid_source_ready; +wire litedramcore_bankmachine5_pipe_valid_sink_payload_we; +wire litedramcore_bankmachine5_pipe_valid_sink_ready; +wire litedramcore_bankmachine5_pipe_valid_sink_valid; reg litedramcore_bankmachine5_pipe_valid_source_first = 1'd0; reg litedramcore_bankmachine5_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; reg [21:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 22'd0; +reg litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; +wire litedramcore_bankmachine5_pipe_valid_source_ready; +reg litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; +reg [3:0] litedramcore_bankmachine5_produce = 4'd0; +wire [3:0] litedramcore_bankmachine5_rdport_adr; +wire [24:0] litedramcore_bankmachine5_rdport_dat_r; +reg litedramcore_bankmachine5_refresh_gnt = 1'd0; +wire litedramcore_bankmachine5_refresh_req; +reg litedramcore_bankmachine5_replace = 1'd0; +wire [21:0] litedramcore_bankmachine5_req_addr; +wire litedramcore_bankmachine5_req_lock; +reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine5_req_ready; +wire litedramcore_bankmachine5_req_valid; +reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; +wire litedramcore_bankmachine5_req_we; reg [14:0] litedramcore_bankmachine5_row = 15'd0; -reg litedramcore_bankmachine5_row_opened = 1'd0; -wire litedramcore_bankmachine5_row_hit; -reg litedramcore_bankmachine5_row_open = 1'd0; reg litedramcore_bankmachine5_row_close = 1'd0; reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine5_twtpcon_valid; -reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; -wire litedramcore_bankmachine5_trccon_valid; -reg litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [1:0] litedramcore_bankmachine5_trccon_count = 2'd0; -wire litedramcore_bankmachine5_trascon_valid; -reg litedramcore_bankmachine5_trascon_ready = 1'd0; +wire litedramcore_bankmachine5_row_hit; +reg litedramcore_bankmachine5_row_open = 1'd0; +reg litedramcore_bankmachine5_row_opened = 1'd0; +reg litedramcore_bankmachine5_sink_first = 1'd0; +reg litedramcore_bankmachine5_sink_last = 1'd0; +wire [21:0] litedramcore_bankmachine5_sink_payload_addr; +wire litedramcore_bankmachine5_sink_payload_we; +wire litedramcore_bankmachine5_sink_ready; +wire litedramcore_bankmachine5_sink_sink_first; +wire litedramcore_bankmachine5_sink_sink_last; +wire [21:0] litedramcore_bankmachine5_sink_sink_payload_addr; +wire litedramcore_bankmachine5_sink_sink_payload_we; +wire litedramcore_bankmachine5_sink_sink_ready; +wire litedramcore_bankmachine5_sink_sink_valid; +wire litedramcore_bankmachine5_sink_valid; +wire litedramcore_bankmachine5_source_first; +wire litedramcore_bankmachine5_source_last; +wire [21:0] litedramcore_bankmachine5_source_payload_addr; +wire litedramcore_bankmachine5_source_payload_we; +wire litedramcore_bankmachine5_source_ready; +wire litedramcore_bankmachine5_source_source_first; +wire litedramcore_bankmachine5_source_source_last; +wire [21:0] litedramcore_bankmachine5_source_source_payload_addr; +wire litedramcore_bankmachine5_source_source_payload_we; +wire litedramcore_bankmachine5_source_source_ready; +wire litedramcore_bankmachine5_source_source_valid; +wire litedramcore_bankmachine5_source_valid; +reg [2:0] litedramcore_bankmachine5_state = 3'd0; +wire [24:0] litedramcore_bankmachine5_syncfifo5_din; +wire [24:0] litedramcore_bankmachine5_syncfifo5_dout; +wire litedramcore_bankmachine5_syncfifo5_re; +wire litedramcore_bankmachine5_syncfifo5_readable; +wire litedramcore_bankmachine5_syncfifo5_we; +wire litedramcore_bankmachine5_syncfifo5_writable; reg [1:0] litedramcore_bankmachine5_trascon_count = 2'd0; -wire litedramcore_bankmachine6_req_valid; -wire litedramcore_bankmachine6_req_ready; -wire litedramcore_bankmachine6_req_we; -wire [21:0] litedramcore_bankmachine6_req_addr; -wire litedramcore_bankmachine6_req_lock; -reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine6_refresh_req; -reg litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg litedramcore_bankmachine6_cmd_valid = 1'd0; -reg litedramcore_bankmachine6_cmd_ready = 1'd0; +reg litedramcore_bankmachine5_trascon_ready = 1'd0; +wire litedramcore_bankmachine5_trascon_valid; +reg [1:0] litedramcore_bankmachine5_trccon_count = 2'd0; +reg litedramcore_bankmachine5_trccon_ready = 1'd0; +wire litedramcore_bankmachine5_trccon_valid; +reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; +reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; +wire litedramcore_bankmachine5_twtpcon_valid; +reg [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine5_wrport_dat_r; +wire [24:0] litedramcore_bankmachine5_wrport_dat_w; +wire litedramcore_bankmachine5_wrport_we; +reg litedramcore_bankmachine6_auto_precharge = 1'd0; reg [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0; wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine6_auto_precharge = 1'd0; -wire litedramcore_bankmachine6_sink_valid; -wire litedramcore_bankmachine6_sink_ready; -reg litedramcore_bankmachine6_sink_first = 1'd0; -reg litedramcore_bankmachine6_sink_last = 1'd0; -wire litedramcore_bankmachine6_sink_payload_we; -wire [21:0] litedramcore_bankmachine6_sink_payload_addr; -wire litedramcore_bankmachine6_source_valid; -wire litedramcore_bankmachine6_source_ready; -wire litedramcore_bankmachine6_source_first; -wire litedramcore_bankmachine6_source_last; -wire litedramcore_bankmachine6_source_payload_we; -wire [21:0] litedramcore_bankmachine6_source_payload_addr; -wire litedramcore_bankmachine6_syncfifo6_we; -wire litedramcore_bankmachine6_syncfifo6_writable; -wire litedramcore_bankmachine6_syncfifo6_re; -wire litedramcore_bankmachine6_syncfifo6_readable; -wire [24:0] litedramcore_bankmachine6_syncfifo6_din; -wire [24:0] litedramcore_bankmachine6_syncfifo6_dout; -reg [4:0] litedramcore_bankmachine6_level = 5'd0; -reg litedramcore_bankmachine6_replace = 1'd0; -reg [3:0] litedramcore_bankmachine6_produce = 4'd0; +reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine6_cmd_ready = 1'd0; +reg litedramcore_bankmachine6_cmd_valid = 1'd0; reg [3:0] litedramcore_bankmachine6_consume = 4'd0; -reg [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine6_wrport_dat_r; -wire litedramcore_bankmachine6_wrport_we; -wire [24:0] litedramcore_bankmachine6_wrport_dat_w; wire litedramcore_bankmachine6_do_read; -wire [3:0] litedramcore_bankmachine6_rdport_adr; -wire [24:0] litedramcore_bankmachine6_rdport_dat_r; -wire litedramcore_bankmachine6_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine6_fifo_in_payload_addr; wire litedramcore_bankmachine6_fifo_in_first; wire litedramcore_bankmachine6_fifo_in_last; -wire litedramcore_bankmachine6_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine6_fifo_out_payload_addr; +wire [21:0] litedramcore_bankmachine6_fifo_in_payload_addr; +wire litedramcore_bankmachine6_fifo_in_payload_we; wire litedramcore_bankmachine6_fifo_out_first; wire litedramcore_bankmachine6_fifo_out_last; -wire litedramcore_bankmachine6_sink_sink_valid; -wire litedramcore_bankmachine6_sink_sink_ready; -wire litedramcore_bankmachine6_sink_sink_first; -wire litedramcore_bankmachine6_sink_sink_last; -wire litedramcore_bankmachine6_sink_sink_payload_we; -wire [21:0] litedramcore_bankmachine6_sink_sink_payload_addr; -wire litedramcore_bankmachine6_source_source_valid; -wire litedramcore_bankmachine6_source_source_ready; -wire litedramcore_bankmachine6_source_source_first; -wire litedramcore_bankmachine6_source_source_last; -wire litedramcore_bankmachine6_source_source_payload_we; -wire [21:0] litedramcore_bankmachine6_source_source_payload_addr; -wire litedramcore_bankmachine6_pipe_valid_sink_valid; -wire litedramcore_bankmachine6_pipe_valid_sink_ready; +wire [21:0] litedramcore_bankmachine6_fifo_out_payload_addr; +wire litedramcore_bankmachine6_fifo_out_payload_we; +reg [4:0] litedramcore_bankmachine6_level = 5'd0; +reg [2:0] litedramcore_bankmachine6_next_state = 3'd0; wire litedramcore_bankmachine6_pipe_valid_sink_first; wire litedramcore_bankmachine6_pipe_valid_sink_last; -wire litedramcore_bankmachine6_pipe_valid_sink_payload_we; wire [21:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine6_pipe_valid_source_ready; +wire litedramcore_bankmachine6_pipe_valid_sink_payload_we; +wire litedramcore_bankmachine6_pipe_valid_sink_ready; +wire litedramcore_bankmachine6_pipe_valid_sink_valid; reg litedramcore_bankmachine6_pipe_valid_source_first = 1'd0; reg litedramcore_bankmachine6_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; reg [21:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 22'd0; +reg litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; +wire litedramcore_bankmachine6_pipe_valid_source_ready; +reg litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; +reg [3:0] litedramcore_bankmachine6_produce = 4'd0; +wire [3:0] litedramcore_bankmachine6_rdport_adr; +wire [24:0] litedramcore_bankmachine6_rdport_dat_r; +reg litedramcore_bankmachine6_refresh_gnt = 1'd0; +wire litedramcore_bankmachine6_refresh_req; +reg litedramcore_bankmachine6_replace = 1'd0; +wire [21:0] litedramcore_bankmachine6_req_addr; +wire litedramcore_bankmachine6_req_lock; +reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine6_req_ready; +wire litedramcore_bankmachine6_req_valid; +reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; +wire litedramcore_bankmachine6_req_we; reg [14:0] litedramcore_bankmachine6_row = 15'd0; -reg litedramcore_bankmachine6_row_opened = 1'd0; -wire litedramcore_bankmachine6_row_hit; -reg litedramcore_bankmachine6_row_open = 1'd0; reg litedramcore_bankmachine6_row_close = 1'd0; reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine6_twtpcon_valid; -reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; -wire litedramcore_bankmachine6_trccon_valid; -reg litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [1:0] litedramcore_bankmachine6_trccon_count = 2'd0; -wire litedramcore_bankmachine6_trascon_valid; -reg litedramcore_bankmachine6_trascon_ready = 1'd0; +wire litedramcore_bankmachine6_row_hit; +reg litedramcore_bankmachine6_row_open = 1'd0; +reg litedramcore_bankmachine6_row_opened = 1'd0; +reg litedramcore_bankmachine6_sink_first = 1'd0; +reg litedramcore_bankmachine6_sink_last = 1'd0; +wire [21:0] litedramcore_bankmachine6_sink_payload_addr; +wire litedramcore_bankmachine6_sink_payload_we; +wire litedramcore_bankmachine6_sink_ready; +wire litedramcore_bankmachine6_sink_sink_first; +wire litedramcore_bankmachine6_sink_sink_last; +wire [21:0] litedramcore_bankmachine6_sink_sink_payload_addr; +wire litedramcore_bankmachine6_sink_sink_payload_we; +wire litedramcore_bankmachine6_sink_sink_ready; +wire litedramcore_bankmachine6_sink_sink_valid; +wire litedramcore_bankmachine6_sink_valid; +wire litedramcore_bankmachine6_source_first; +wire litedramcore_bankmachine6_source_last; +wire [21:0] litedramcore_bankmachine6_source_payload_addr; +wire litedramcore_bankmachine6_source_payload_we; +wire litedramcore_bankmachine6_source_ready; +wire litedramcore_bankmachine6_source_source_first; +wire litedramcore_bankmachine6_source_source_last; +wire [21:0] litedramcore_bankmachine6_source_source_payload_addr; +wire litedramcore_bankmachine6_source_source_payload_we; +wire litedramcore_bankmachine6_source_source_ready; +wire litedramcore_bankmachine6_source_source_valid; +wire litedramcore_bankmachine6_source_valid; +reg [2:0] litedramcore_bankmachine6_state = 3'd0; +wire [24:0] litedramcore_bankmachine6_syncfifo6_din; +wire [24:0] litedramcore_bankmachine6_syncfifo6_dout; +wire litedramcore_bankmachine6_syncfifo6_re; +wire litedramcore_bankmachine6_syncfifo6_readable; +wire litedramcore_bankmachine6_syncfifo6_we; +wire litedramcore_bankmachine6_syncfifo6_writable; reg [1:0] litedramcore_bankmachine6_trascon_count = 2'd0; -wire litedramcore_bankmachine7_req_valid; -wire litedramcore_bankmachine7_req_ready; -wire litedramcore_bankmachine7_req_we; -wire [21:0] litedramcore_bankmachine7_req_addr; -wire litedramcore_bankmachine7_req_lock; -reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine7_refresh_req; -reg litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg litedramcore_bankmachine7_cmd_valid = 1'd0; -reg litedramcore_bankmachine7_cmd_ready = 1'd0; +reg litedramcore_bankmachine6_trascon_ready = 1'd0; +wire litedramcore_bankmachine6_trascon_valid; +reg [1:0] litedramcore_bankmachine6_trccon_count = 2'd0; +reg litedramcore_bankmachine6_trccon_ready = 1'd0; +wire litedramcore_bankmachine6_trccon_valid; +reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; +reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; +wire litedramcore_bankmachine6_twtpcon_valid; +reg [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine6_wrport_dat_r; +wire [24:0] litedramcore_bankmachine6_wrport_dat_w; +wire litedramcore_bankmachine6_wrport_we; +reg litedramcore_bankmachine7_auto_precharge = 1'd0; reg [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0; wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine7_auto_precharge = 1'd0; -wire litedramcore_bankmachine7_sink_valid; -wire litedramcore_bankmachine7_sink_ready; -reg litedramcore_bankmachine7_sink_first = 1'd0; -reg litedramcore_bankmachine7_sink_last = 1'd0; -wire litedramcore_bankmachine7_sink_payload_we; -wire [21:0] litedramcore_bankmachine7_sink_payload_addr; -wire litedramcore_bankmachine7_source_valid; -wire litedramcore_bankmachine7_source_ready; -wire litedramcore_bankmachine7_source_first; -wire litedramcore_bankmachine7_source_last; -wire litedramcore_bankmachine7_source_payload_we; -wire [21:0] litedramcore_bankmachine7_source_payload_addr; -wire litedramcore_bankmachine7_syncfifo7_we; -wire litedramcore_bankmachine7_syncfifo7_writable; -wire litedramcore_bankmachine7_syncfifo7_re; -wire litedramcore_bankmachine7_syncfifo7_readable; -wire [24:0] litedramcore_bankmachine7_syncfifo7_din; -wire [24:0] litedramcore_bankmachine7_syncfifo7_dout; -reg [4:0] litedramcore_bankmachine7_level = 5'd0; -reg litedramcore_bankmachine7_replace = 1'd0; -reg [3:0] litedramcore_bankmachine7_produce = 4'd0; +reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine7_cmd_ready = 1'd0; +reg litedramcore_bankmachine7_cmd_valid = 1'd0; reg [3:0] litedramcore_bankmachine7_consume = 4'd0; -reg [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine7_wrport_dat_r; -wire litedramcore_bankmachine7_wrport_we; -wire [24:0] litedramcore_bankmachine7_wrport_dat_w; wire litedramcore_bankmachine7_do_read; -wire [3:0] litedramcore_bankmachine7_rdport_adr; -wire [24:0] litedramcore_bankmachine7_rdport_dat_r; -wire litedramcore_bankmachine7_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine7_fifo_in_payload_addr; wire litedramcore_bankmachine7_fifo_in_first; wire litedramcore_bankmachine7_fifo_in_last; -wire litedramcore_bankmachine7_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine7_fifo_out_payload_addr; +wire [21:0] litedramcore_bankmachine7_fifo_in_payload_addr; +wire litedramcore_bankmachine7_fifo_in_payload_we; wire litedramcore_bankmachine7_fifo_out_first; wire litedramcore_bankmachine7_fifo_out_last; -wire litedramcore_bankmachine7_sink_sink_valid; -wire litedramcore_bankmachine7_sink_sink_ready; -wire litedramcore_bankmachine7_sink_sink_first; -wire litedramcore_bankmachine7_sink_sink_last; -wire litedramcore_bankmachine7_sink_sink_payload_we; -wire [21:0] litedramcore_bankmachine7_sink_sink_payload_addr; -wire litedramcore_bankmachine7_source_source_valid; -wire litedramcore_bankmachine7_source_source_ready; -wire litedramcore_bankmachine7_source_source_first; -wire litedramcore_bankmachine7_source_source_last; -wire litedramcore_bankmachine7_source_source_payload_we; -wire [21:0] litedramcore_bankmachine7_source_source_payload_addr; -wire litedramcore_bankmachine7_pipe_valid_sink_valid; -wire litedramcore_bankmachine7_pipe_valid_sink_ready; +wire [21:0] litedramcore_bankmachine7_fifo_out_payload_addr; +wire litedramcore_bankmachine7_fifo_out_payload_we; +reg [4:0] litedramcore_bankmachine7_level = 5'd0; +reg [2:0] litedramcore_bankmachine7_next_state = 3'd0; wire litedramcore_bankmachine7_pipe_valid_sink_first; wire litedramcore_bankmachine7_pipe_valid_sink_last; -wire litedramcore_bankmachine7_pipe_valid_sink_payload_we; wire [21:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine7_pipe_valid_source_ready; +wire litedramcore_bankmachine7_pipe_valid_sink_payload_we; +wire litedramcore_bankmachine7_pipe_valid_sink_ready; +wire litedramcore_bankmachine7_pipe_valid_sink_valid; reg litedramcore_bankmachine7_pipe_valid_source_first = 1'd0; reg litedramcore_bankmachine7_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; reg [21:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 22'd0; +reg litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; +wire litedramcore_bankmachine7_pipe_valid_source_ready; +reg litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; +reg [3:0] litedramcore_bankmachine7_produce = 4'd0; +wire [3:0] litedramcore_bankmachine7_rdport_adr; +wire [24:0] litedramcore_bankmachine7_rdport_dat_r; +reg litedramcore_bankmachine7_refresh_gnt = 1'd0; +wire litedramcore_bankmachine7_refresh_req; +reg litedramcore_bankmachine7_replace = 1'd0; +wire [21:0] litedramcore_bankmachine7_req_addr; +wire litedramcore_bankmachine7_req_lock; +reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine7_req_ready; +wire litedramcore_bankmachine7_req_valid; +reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; +wire litedramcore_bankmachine7_req_we; reg [14:0] litedramcore_bankmachine7_row = 15'd0; -reg litedramcore_bankmachine7_row_opened = 1'd0; -wire litedramcore_bankmachine7_row_hit; -reg litedramcore_bankmachine7_row_open = 1'd0; reg litedramcore_bankmachine7_row_close = 1'd0; reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine7_twtpcon_valid; -reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; -wire litedramcore_bankmachine7_trccon_valid; -reg litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [1:0] litedramcore_bankmachine7_trccon_count = 2'd0; -wire litedramcore_bankmachine7_trascon_valid; -reg litedramcore_bankmachine7_trascon_ready = 1'd0; +wire litedramcore_bankmachine7_row_hit; +reg litedramcore_bankmachine7_row_open = 1'd0; +reg litedramcore_bankmachine7_row_opened = 1'd0; +reg litedramcore_bankmachine7_sink_first = 1'd0; +reg litedramcore_bankmachine7_sink_last = 1'd0; +wire [21:0] litedramcore_bankmachine7_sink_payload_addr; +wire litedramcore_bankmachine7_sink_payload_we; +wire litedramcore_bankmachine7_sink_ready; +wire litedramcore_bankmachine7_sink_sink_first; +wire litedramcore_bankmachine7_sink_sink_last; +wire [21:0] litedramcore_bankmachine7_sink_sink_payload_addr; +wire litedramcore_bankmachine7_sink_sink_payload_we; +wire litedramcore_bankmachine7_sink_sink_ready; +wire litedramcore_bankmachine7_sink_sink_valid; +wire litedramcore_bankmachine7_sink_valid; +wire litedramcore_bankmachine7_source_first; +wire litedramcore_bankmachine7_source_last; +wire [21:0] litedramcore_bankmachine7_source_payload_addr; +wire litedramcore_bankmachine7_source_payload_we; +wire litedramcore_bankmachine7_source_ready; +wire litedramcore_bankmachine7_source_source_first; +wire litedramcore_bankmachine7_source_source_last; +wire [21:0] litedramcore_bankmachine7_source_source_payload_addr; +wire litedramcore_bankmachine7_source_source_payload_we; +wire litedramcore_bankmachine7_source_source_ready; +wire litedramcore_bankmachine7_source_source_valid; +wire litedramcore_bankmachine7_source_valid; +reg [2:0] litedramcore_bankmachine7_state = 3'd0; +wire [24:0] litedramcore_bankmachine7_syncfifo7_din; +wire [24:0] litedramcore_bankmachine7_syncfifo7_dout; +wire litedramcore_bankmachine7_syncfifo7_re; +wire litedramcore_bankmachine7_syncfifo7_readable; +wire litedramcore_bankmachine7_syncfifo7_we; +wire litedramcore_bankmachine7_syncfifo7_writable; reg [1:0] litedramcore_bankmachine7_trascon_count = 2'd0; -wire litedramcore_ras_allowed; +reg litedramcore_bankmachine7_trascon_ready = 1'd0; +wire litedramcore_bankmachine7_trascon_valid; +reg [1:0] litedramcore_bankmachine7_trccon_count = 2'd0; +reg litedramcore_bankmachine7_trccon_ready = 1'd0; +wire litedramcore_bankmachine7_trccon_valid; +reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; +reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; +wire litedramcore_bankmachine7_twtpcon_valid; +reg [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine7_wrport_dat_r; +wire [24:0] litedramcore_bankmachine7_wrport_dat_w; +wire litedramcore_bankmachine7_wrport_we; wire litedramcore_cas_allowed; -reg litedramcore_choose_cmd_want_reads = 1'd0; -reg litedramcore_choose_cmd_want_writes = 1'd0; -reg litedramcore_choose_cmd_want_cmds = 1'd0; -reg litedramcore_choose_cmd_want_activates = 1'd0; -wire litedramcore_choose_cmd_cmd_valid; -reg litedramcore_choose_cmd_cmd_ready = 1'd0; +wire litedramcore_choose_cmd_ce; wire [14:0] litedramcore_choose_cmd_cmd_payload_a; wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; wire litedramcore_choose_cmd_cmd_payload_is_cmd; wire litedramcore_choose_cmd_cmd_payload_is_read; wire litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] litedramcore_choose_cmd_valids = 8'd0; -wire [7:0] litedramcore_choose_cmd_request; +reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; +reg litedramcore_choose_cmd_cmd_ready = 1'd0; +wire litedramcore_choose_cmd_cmd_valid; reg [2:0] litedramcore_choose_cmd_grant = 3'd0; -wire litedramcore_choose_cmd_ce; -reg litedramcore_choose_req_want_reads = 1'd0; -reg litedramcore_choose_req_want_writes = 1'd0; -reg litedramcore_choose_req_want_cmds = 1'd0; -reg litedramcore_choose_req_want_activates = 1'd0; -wire litedramcore_choose_req_cmd_valid; -reg litedramcore_choose_req_cmd_ready = 1'd0; +wire [7:0] litedramcore_choose_cmd_request; +reg [7:0] litedramcore_choose_cmd_valids = 8'd0; +reg litedramcore_choose_cmd_want_activates = 1'd0; +reg litedramcore_choose_cmd_want_cmds = 1'd0; +reg litedramcore_choose_cmd_want_reads = 1'd0; +reg litedramcore_choose_cmd_want_writes = 1'd0; +wire litedramcore_choose_req_ce; wire [14:0] litedramcore_choose_req_cmd_payload_a; wire [2:0] litedramcore_choose_req_cmd_payload_ba; reg litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg litedramcore_choose_req_cmd_payload_we = 1'd0; wire litedramcore_choose_req_cmd_payload_is_cmd; wire litedramcore_choose_req_cmd_payload_is_read; wire litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] litedramcore_choose_req_valids = 8'd0; -wire [7:0] litedramcore_choose_req_request; +reg litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg litedramcore_choose_req_cmd_payload_we = 1'd0; +reg litedramcore_choose_req_cmd_ready = 1'd0; +wire litedramcore_choose_req_cmd_valid; reg [2:0] litedramcore_choose_req_grant = 3'd0; -wire litedramcore_choose_req_ce; +wire [7:0] litedramcore_choose_req_request; +reg [7:0] litedramcore_choose_req_valids = 8'd0; +reg litedramcore_choose_req_want_activates = 1'd0; +reg litedramcore_choose_req_want_cmds = 1'd0; +reg litedramcore_choose_req_want_reads = 1'd0; +reg litedramcore_choose_req_want_writes = 1'd0; +wire litedramcore_cke; +reg litedramcore_cmd_last = 1'd0; +reg [14:0] litedramcore_cmd_payload_a = 15'd0; +reg [2:0] litedramcore_cmd_payload_ba = 3'd0; +reg litedramcore_cmd_payload_cas = 1'd0; +reg litedramcore_cmd_payload_is_read = 1'd0; +reg litedramcore_cmd_payload_is_write = 1'd0; +reg litedramcore_cmd_payload_ras = 1'd0; +reg litedramcore_cmd_payload_we = 1'd0; +reg litedramcore_cmd_ready = 1'd0; +reg litedramcore_cmd_valid = 1'd0; +reg litedramcore_csr_dfi_p0_act_n = 1'd1; +wire [14:0] litedramcore_csr_dfi_p0_address; +wire [2:0] litedramcore_csr_dfi_p0_bank; +reg litedramcore_csr_dfi_p0_cas_n = 1'd1; +reg litedramcore_csr_dfi_p0_cke = 1'd0; +reg litedramcore_csr_dfi_p0_cs_n = 1'd1; +reg litedramcore_csr_dfi_p0_odt = 1'd0; +reg litedramcore_csr_dfi_p0_ras_n = 1'd1; +reg [63:0] litedramcore_csr_dfi_p0_rddata = 64'd0; +wire litedramcore_csr_dfi_p0_rddata_en; +reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0; +wire litedramcore_csr_dfi_p0_reset_n; +reg litedramcore_csr_dfi_p0_we_n = 1'd1; +wire [63:0] litedramcore_csr_dfi_p0_wrdata; +wire litedramcore_csr_dfi_p0_wrdata_en; +wire [7:0] litedramcore_csr_dfi_p0_wrdata_mask; +reg litedramcore_csr_dfi_p1_act_n = 1'd1; +wire [14:0] litedramcore_csr_dfi_p1_address; +wire [2:0] litedramcore_csr_dfi_p1_bank; +reg litedramcore_csr_dfi_p1_cas_n = 1'd1; +reg litedramcore_csr_dfi_p1_cke = 1'd0; +reg litedramcore_csr_dfi_p1_cs_n = 1'd1; +reg litedramcore_csr_dfi_p1_odt = 1'd0; +reg litedramcore_csr_dfi_p1_ras_n = 1'd1; +reg [63:0] litedramcore_csr_dfi_p1_rddata = 64'd0; +wire litedramcore_csr_dfi_p1_rddata_en; +reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0; +wire litedramcore_csr_dfi_p1_reset_n; +reg litedramcore_csr_dfi_p1_we_n = 1'd1; +wire [63:0] litedramcore_csr_dfi_p1_wrdata; +wire litedramcore_csr_dfi_p1_wrdata_en; +wire [7:0] litedramcore_csr_dfi_p1_wrdata_mask; +reg litedramcore_dfi_p0_act_n = 1'd1; +reg [14:0] litedramcore_dfi_p0_address = 15'd0; +reg [2:0] litedramcore_dfi_p0_bank = 3'd0; +reg litedramcore_dfi_p0_cas_n = 1'd1; +wire litedramcore_dfi_p0_cke; +reg litedramcore_dfi_p0_cs_n = 1'd1; +wire litedramcore_dfi_p0_odt; +reg litedramcore_dfi_p0_ras_n = 1'd1; +wire [63:0] litedramcore_dfi_p0_rddata; +reg litedramcore_dfi_p0_rddata_en = 1'd0; +wire litedramcore_dfi_p0_rddata_valid; +wire litedramcore_dfi_p0_reset_n; +reg litedramcore_dfi_p0_we_n = 1'd1; +wire [63:0] litedramcore_dfi_p0_wrdata; +reg litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [7:0] litedramcore_dfi_p0_wrdata_mask; +reg litedramcore_dfi_p1_act_n = 1'd1; +reg [14:0] litedramcore_dfi_p1_address = 15'd0; +reg [2:0] litedramcore_dfi_p1_bank = 3'd0; +reg litedramcore_dfi_p1_cas_n = 1'd1; +wire litedramcore_dfi_p1_cke; +reg litedramcore_dfi_p1_cs_n = 1'd1; +wire litedramcore_dfi_p1_odt; +reg litedramcore_dfi_p1_ras_n = 1'd1; +wire [63:0] litedramcore_dfi_p1_rddata; +reg litedramcore_dfi_p1_rddata_en = 1'd0; +wire litedramcore_dfi_p1_rddata_valid; +wire litedramcore_dfi_p1_reset_n; +reg litedramcore_dfi_p1_we_n = 1'd1; +wire [63:0] litedramcore_dfi_p1_wrdata; +reg litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [7:0] litedramcore_dfi_p1_wrdata_mask; +reg litedramcore_en0 = 1'd0; +reg litedramcore_en1 = 1'd0; +reg litedramcore_ext_dfi_p0_act_n = 1'd1; +reg [14:0] litedramcore_ext_dfi_p0_address = 15'd0; +reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0; +reg litedramcore_ext_dfi_p0_cas_n = 1'd1; +reg litedramcore_ext_dfi_p0_cke = 1'd0; +reg litedramcore_ext_dfi_p0_cs_n = 1'd1; +reg litedramcore_ext_dfi_p0_odt = 1'd0; +reg litedramcore_ext_dfi_p0_ras_n = 1'd1; +reg [63:0] litedramcore_ext_dfi_p0_rddata = 64'd0; +reg litedramcore_ext_dfi_p0_rddata_en = 1'd0; +reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0; +reg litedramcore_ext_dfi_p0_reset_n = 1'd0; +reg litedramcore_ext_dfi_p0_we_n = 1'd1; +reg [63:0] litedramcore_ext_dfi_p0_wrdata = 64'd0; +reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0; +reg [7:0] litedramcore_ext_dfi_p0_wrdata_mask = 8'd0; +reg litedramcore_ext_dfi_p1_act_n = 1'd1; +reg [14:0] litedramcore_ext_dfi_p1_address = 15'd0; +reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0; +reg litedramcore_ext_dfi_p1_cas_n = 1'd1; +reg litedramcore_ext_dfi_p1_cke = 1'd0; +reg litedramcore_ext_dfi_p1_cs_n = 1'd1; +reg litedramcore_ext_dfi_p1_odt = 1'd0; +reg litedramcore_ext_dfi_p1_ras_n = 1'd1; +reg [63:0] litedramcore_ext_dfi_p1_rddata = 64'd0; +reg litedramcore_ext_dfi_p1_rddata_en = 1'd0; +reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0; +reg litedramcore_ext_dfi_p1_reset_n = 1'd0; +reg litedramcore_ext_dfi_p1_we_n = 1'd1; +reg [63:0] litedramcore_ext_dfi_p1_wrdata = 64'd0; +reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0; +reg [7:0] litedramcore_ext_dfi_p1_wrdata_mask = 8'd0; +reg litedramcore_ext_dfi_sel = 1'd0; +wire litedramcore_go_to_refresh; +wire [21:0] litedramcore_interface_bank0_addr; +wire litedramcore_interface_bank0_lock; +wire litedramcore_interface_bank0_rdata_valid; +wire litedramcore_interface_bank0_ready; +wire litedramcore_interface_bank0_valid; +wire litedramcore_interface_bank0_wdata_ready; +wire litedramcore_interface_bank0_we; +wire [21:0] litedramcore_interface_bank1_addr; +wire litedramcore_interface_bank1_lock; +wire litedramcore_interface_bank1_rdata_valid; +wire litedramcore_interface_bank1_ready; +wire litedramcore_interface_bank1_valid; +wire litedramcore_interface_bank1_wdata_ready; +wire litedramcore_interface_bank1_we; +wire [21:0] litedramcore_interface_bank2_addr; +wire litedramcore_interface_bank2_lock; +wire litedramcore_interface_bank2_rdata_valid; +wire litedramcore_interface_bank2_ready; +wire litedramcore_interface_bank2_valid; +wire litedramcore_interface_bank2_wdata_ready; +wire litedramcore_interface_bank2_we; +wire [21:0] litedramcore_interface_bank3_addr; +wire litedramcore_interface_bank3_lock; +wire litedramcore_interface_bank3_rdata_valid; +wire litedramcore_interface_bank3_ready; +wire litedramcore_interface_bank3_valid; +wire litedramcore_interface_bank3_wdata_ready; +wire litedramcore_interface_bank3_we; +wire [21:0] litedramcore_interface_bank4_addr; +wire litedramcore_interface_bank4_lock; +wire litedramcore_interface_bank4_rdata_valid; +wire litedramcore_interface_bank4_ready; +wire litedramcore_interface_bank4_valid; +wire litedramcore_interface_bank4_wdata_ready; +wire litedramcore_interface_bank4_we; +wire [21:0] litedramcore_interface_bank5_addr; +wire litedramcore_interface_bank5_lock; +wire litedramcore_interface_bank5_rdata_valid; +wire litedramcore_interface_bank5_ready; +wire litedramcore_interface_bank5_valid; +wire litedramcore_interface_bank5_wdata_ready; +wire litedramcore_interface_bank5_we; +wire [21:0] litedramcore_interface_bank6_addr; +wire litedramcore_interface_bank6_lock; +wire litedramcore_interface_bank6_rdata_valid; +wire litedramcore_interface_bank6_ready; +wire litedramcore_interface_bank6_valid; +wire litedramcore_interface_bank6_wdata_ready; +wire litedramcore_interface_bank6_we; +wire [21:0] litedramcore_interface_bank7_addr; +wire litedramcore_interface_bank7_lock; +wire litedramcore_interface_bank7_rdata_valid; +wire litedramcore_interface_bank7_ready; +wire litedramcore_interface_bank7_valid; +wire litedramcore_interface_bank7_wdata_ready; +wire litedramcore_interface_bank7_we; +wire [127:0] litedramcore_interface_rdata; +reg [127:0] litedramcore_interface_wdata = 128'd0; +reg [15:0] litedramcore_interface_wdata_we = 16'd0; +reg litedramcore_locked0 = 1'd0; +reg litedramcore_locked1 = 1'd0; +reg litedramcore_locked2 = 1'd0; +reg litedramcore_locked3 = 1'd0; +reg litedramcore_locked4 = 1'd0; +reg litedramcore_locked5 = 1'd0; +reg litedramcore_locked6 = 1'd0; +reg litedramcore_locked7 = 1'd0; +reg litedramcore_master_p0_act_n = 1'd1; +reg [14:0] litedramcore_master_p0_address = 15'd0; +reg [2:0] litedramcore_master_p0_bank = 3'd0; +reg litedramcore_master_p0_cas_n = 1'd1; +reg litedramcore_master_p0_cke = 1'd0; +reg litedramcore_master_p0_cs_n = 1'd1; +reg litedramcore_master_p0_odt = 1'd0; +reg litedramcore_master_p0_ras_n = 1'd1; +wire [63:0] litedramcore_master_p0_rddata; +reg litedramcore_master_p0_rddata_en = 1'd0; +wire litedramcore_master_p0_rddata_valid; +reg litedramcore_master_p0_reset_n = 1'd0; +reg litedramcore_master_p0_we_n = 1'd1; +reg [63:0] litedramcore_master_p0_wrdata = 64'd0; +reg litedramcore_master_p0_wrdata_en = 1'd0; +reg [7:0] litedramcore_master_p0_wrdata_mask = 8'd0; +reg litedramcore_master_p1_act_n = 1'd1; +reg [14:0] litedramcore_master_p1_address = 15'd0; +reg [2:0] litedramcore_master_p1_bank = 3'd0; +reg litedramcore_master_p1_cas_n = 1'd1; +reg litedramcore_master_p1_cke = 1'd0; +reg litedramcore_master_p1_cs_n = 1'd1; +reg litedramcore_master_p1_odt = 1'd0; +reg litedramcore_master_p1_ras_n = 1'd1; +wire [63:0] litedramcore_master_p1_rddata; +reg litedramcore_master_p1_rddata_en = 1'd0; +wire litedramcore_master_p1_rddata_valid; +reg litedramcore_master_p1_reset_n = 1'd0; +reg litedramcore_master_p1_we_n = 1'd1; +reg [63:0] litedramcore_master_p1_wrdata = 64'd0; +reg litedramcore_master_p1_wrdata_en = 1'd0; +reg [7:0] litedramcore_master_p1_wrdata_mask = 8'd0; +wire litedramcore_max_time0; +wire litedramcore_max_time1; +reg [3:0] litedramcore_multiplexer_next_state = 4'd0; +reg [3:0] litedramcore_multiplexer_state = 4'd0; +reg litedramcore_new_master_rdata_valid0 = 1'd0; +reg litedramcore_new_master_rdata_valid1 = 1'd0; +reg litedramcore_new_master_rdata_valid10 = 1'd0; +reg litedramcore_new_master_rdata_valid11 = 1'd0; +reg litedramcore_new_master_rdata_valid12 = 1'd0; +reg litedramcore_new_master_rdata_valid13 = 1'd0; +reg litedramcore_new_master_rdata_valid2 = 1'd0; +reg litedramcore_new_master_rdata_valid3 = 1'd0; +reg litedramcore_new_master_rdata_valid4 = 1'd0; +reg litedramcore_new_master_rdata_valid5 = 1'd0; +reg litedramcore_new_master_rdata_valid6 = 1'd0; +reg litedramcore_new_master_rdata_valid7 = 1'd0; +reg litedramcore_new_master_rdata_valid8 = 1'd0; +reg litedramcore_new_master_rdata_valid9 = 1'd0; +reg litedramcore_new_master_wdata_ready0 = 1'd0; +reg litedramcore_new_master_wdata_ready1 = 1'd0; +reg litedramcore_new_master_wdata_ready2 = 1'd0; +reg litedramcore_new_master_wdata_ready3 = 1'd0; reg [14:0] litedramcore_nop_a = 15'd0; reg [2:0] litedramcore_nop_ba = 3'd0; -reg [1:0] litedramcore_steerer_sel0 = 2'd0; -reg [1:0] litedramcore_steerer_sel1 = 2'd0; -reg litedramcore_steerer0 = 1'd1; -reg litedramcore_steerer1 = 1'd1; +wire litedramcore_odt; +reg litedramcore_phaseinjector0_address_re = 1'd0; +reg [14:0] litedramcore_phaseinjector0_address_storage = 15'd0; +reg litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; +wire litedramcore_phaseinjector0_command_issue_r; +reg litedramcore_phaseinjector0_command_issue_re = 1'd0; +reg litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg litedramcore_phaseinjector0_command_re = 1'd0; +reg [7:0] litedramcore_phaseinjector0_command_storage = 8'd0; +wire litedramcore_phaseinjector0_csrfield_cas; +wire litedramcore_phaseinjector0_csrfield_cs; +wire litedramcore_phaseinjector0_csrfield_cs_bottom; +wire litedramcore_phaseinjector0_csrfield_cs_top; +wire litedramcore_phaseinjector0_csrfield_ras; +wire litedramcore_phaseinjector0_csrfield_rden; +wire litedramcore_phaseinjector0_csrfield_we; +wire litedramcore_phaseinjector0_csrfield_wren; +reg litedramcore_phaseinjector0_rddata_re = 1'd0; +reg [63:0] litedramcore_phaseinjector0_rddata_status = 64'd0; +wire litedramcore_phaseinjector0_rddata_we; +reg litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [63:0] litedramcore_phaseinjector0_wrdata_storage = 64'd0; +reg litedramcore_phaseinjector1_address_re = 1'd0; +reg [14:0] litedramcore_phaseinjector1_address_storage = 15'd0; +reg litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; +wire litedramcore_phaseinjector1_command_issue_r; +reg litedramcore_phaseinjector1_command_issue_re = 1'd0; +reg litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg litedramcore_phaseinjector1_command_re = 1'd0; +reg [7:0] litedramcore_phaseinjector1_command_storage = 8'd0; +wire litedramcore_phaseinjector1_csrfield_cas; +wire litedramcore_phaseinjector1_csrfield_cs; +wire litedramcore_phaseinjector1_csrfield_cs_bottom; +wire litedramcore_phaseinjector1_csrfield_cs_top; +wire litedramcore_phaseinjector1_csrfield_ras; +wire litedramcore_phaseinjector1_csrfield_rden; +wire litedramcore_phaseinjector1_csrfield_we; +wire litedramcore_phaseinjector1_csrfield_wren; +reg litedramcore_phaseinjector1_rddata_re = 1'd0; +reg [63:0] litedramcore_phaseinjector1_rddata_status = 64'd0; +wire litedramcore_phaseinjector1_rddata_we; +reg litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [63:0] litedramcore_phaseinjector1_wrdata_storage = 64'd0; +reg litedramcore_postponer_count = 1'd0; +wire litedramcore_postponer_req_i; +reg litedramcore_postponer_req_o = 1'd0; +wire litedramcore_ras_allowed; +reg litedramcore_re = 1'd0; +wire litedramcore_read_available; +reg [1:0] litedramcore_refresher_next_state = 2'd0; +reg [1:0] litedramcore_refresher_state = 2'd0; +wire litedramcore_reset_n; +wire litedramcore_roundrobin0_ce; +wire litedramcore_roundrobin0_grant; +wire litedramcore_roundrobin0_request; +wire litedramcore_roundrobin1_ce; +wire litedramcore_roundrobin1_grant; +wire litedramcore_roundrobin1_request; +wire litedramcore_roundrobin2_ce; +wire litedramcore_roundrobin2_grant; +wire litedramcore_roundrobin2_request; +wire litedramcore_roundrobin3_ce; +wire litedramcore_roundrobin3_grant; +wire litedramcore_roundrobin3_request; +wire litedramcore_roundrobin4_ce; +wire litedramcore_roundrobin4_grant; +wire litedramcore_roundrobin4_request; +wire litedramcore_roundrobin5_ce; +wire litedramcore_roundrobin5_grant; +wire litedramcore_roundrobin5_request; +wire litedramcore_roundrobin6_ce; +wire litedramcore_roundrobin6_grant; +wire litedramcore_roundrobin6_request; +wire litedramcore_roundrobin7_ce; +wire litedramcore_roundrobin7_grant; +wire litedramcore_roundrobin7_request; +wire litedramcore_sel; +reg litedramcore_sequencer_count = 1'd0; +wire litedramcore_sequencer_done0; +reg litedramcore_sequencer_done1 = 1'd0; +reg litedramcore_sequencer_start0 = 1'd0; +wire litedramcore_sequencer_start1; +reg [6:0] litedramcore_sequencer_trigger = 7'd0; +wire litedramcore_slave_p0_act_n; +wire [14:0] litedramcore_slave_p0_address; +wire [2:0] litedramcore_slave_p0_bank; +wire litedramcore_slave_p0_cas_n; +wire litedramcore_slave_p0_cke; +wire litedramcore_slave_p0_cs_n; +wire litedramcore_slave_p0_odt; +wire litedramcore_slave_p0_ras_n; +reg [63:0] litedramcore_slave_p0_rddata = 64'd0; +wire litedramcore_slave_p0_rddata_en; +reg litedramcore_slave_p0_rddata_valid = 1'd0; +wire litedramcore_slave_p0_reset_n; +wire litedramcore_slave_p0_we_n; +wire [63:0] litedramcore_slave_p0_wrdata; +wire litedramcore_slave_p0_wrdata_en; +wire [7:0] litedramcore_slave_p0_wrdata_mask; +wire litedramcore_slave_p1_act_n; +wire [14:0] litedramcore_slave_p1_address; +wire [2:0] litedramcore_slave_p1_bank; +wire litedramcore_slave_p1_cas_n; +wire litedramcore_slave_p1_cke; +wire litedramcore_slave_p1_cs_n; +wire litedramcore_slave_p1_odt; +wire litedramcore_slave_p1_ras_n; +reg [63:0] litedramcore_slave_p1_rddata = 64'd0; +wire litedramcore_slave_p1_rddata_en; +reg litedramcore_slave_p1_rddata_valid = 1'd0; +wire litedramcore_slave_p1_reset_n; +wire litedramcore_slave_p1_we_n; +wire [63:0] litedramcore_slave_p1_wrdata; +wire litedramcore_slave_p1_wrdata_en; +wire [7:0] litedramcore_slave_p1_wrdata_mask; +reg [1:0] litedramcore_steerer0 = 2'd0; +reg [1:0] litedramcore_steerer1 = 2'd0; reg litedramcore_steerer2 = 1'd1; reg litedramcore_steerer3 = 1'd1; -wire litedramcore_trrdcon_valid; -reg litedramcore_trrdcon_ready = 1'd0; -reg litedramcore_trrdcon_count = 1'd0; -wire litedramcore_tfawcon_valid; -reg litedramcore_tfawcon_ready = 1'd1; +reg litedramcore_steerer4 = 1'd1; +reg litedramcore_steerer5 = 1'd1; +reg [3:0] litedramcore_storage = 4'd1; +reg litedramcore_tccdcon_count = 1'd0; +reg litedramcore_tccdcon_ready = 1'd0; +wire litedramcore_tccdcon_valid; wire [1:0] litedramcore_tfawcon_count; +reg litedramcore_tfawcon_ready = 1'd1; +wire litedramcore_tfawcon_valid; reg [2:0] litedramcore_tfawcon_window = 3'd0; -wire litedramcore_tccdcon_valid; -reg litedramcore_tccdcon_ready = 1'd0; -reg litedramcore_tccdcon_count = 1'd0; -wire litedramcore_twtrcon_valid; -reg litedramcore_twtrcon_ready = 1'd0; -reg [2:0] litedramcore_twtrcon_count = 3'd0; -wire litedramcore_read_available; -wire litedramcore_write_available; -reg litedramcore_en0 = 1'd0; -wire litedramcore_max_time0; reg [4:0] litedramcore_time0 = 5'd0; -reg litedramcore_en1 = 1'd0; -wire litedramcore_max_time1; reg [3:0] litedramcore_time1 = 4'd0; -wire litedramcore_go_to_refresh; -reg init_done_storage = 1'd0; -reg init_done_re = 1'd0; -reg init_error_storage = 1'd0; -reg init_error_re = 1'd0; +wire [8:0] litedramcore_timer_count0; +reg [8:0] litedramcore_timer_count1 = 9'd374; +wire litedramcore_timer_done0; +wire litedramcore_timer_done1; +wire litedramcore_timer_wait; +reg litedramcore_trrdcon_count = 1'd0; +reg litedramcore_trrdcon_ready = 1'd0; +wire litedramcore_trrdcon_valid; +reg [2:0] litedramcore_twtrcon_count = 3'd0; +reg litedramcore_twtrcon_ready = 1'd0; +wire litedramcore_twtrcon_valid; +wire litedramcore_wants_refresh; +wire litedramcore_wants_zqcs; +wire litedramcore_write_available; +reg litedramcore_zqcs_executer_done = 1'd0; +reg litedramcore_zqcs_executer_start = 1'd0; +reg [5:0] litedramcore_zqcs_executer_trigger = 6'd0; +wire [25:0] litedramcore_zqcs_timer_count0; +reg [25:0] litedramcore_zqcs_timer_count1 = 26'd47999999; +wire litedramcore_zqcs_timer_done0; +wire litedramcore_zqcs_timer_done1; +wire litedramcore_zqcs_timer_wait; +wire litedramecp5ddrphycrg_ecp5pll; +wire litedramecp5ddrphycrg_locked; +reg multiregimpl0 = 1'd0; +reg multiregimpl1 = 1'd0; +reg [1:0] next_state = 2'd0; +wire por_clk; +reg rhs_self0 = 1'd0; +reg [14:0] rhs_self1 = 15'd0; +reg rhs_self10 = 1'd0; +reg rhs_self11 = 1'd0; +reg [21:0] rhs_self12 = 22'd0; +reg rhs_self13 = 1'd0; +reg rhs_self14 = 1'd0; +reg [21:0] rhs_self15 = 22'd0; +reg rhs_self16 = 1'd0; +reg rhs_self17 = 1'd0; +reg [21:0] rhs_self18 = 22'd0; +reg rhs_self19 = 1'd0; +reg [2:0] rhs_self2 = 3'd0; +reg rhs_self20 = 1'd0; +reg [21:0] rhs_self21 = 22'd0; +reg rhs_self22 = 1'd0; +reg rhs_self23 = 1'd0; +reg [21:0] rhs_self24 = 22'd0; +reg rhs_self25 = 1'd0; +reg rhs_self26 = 1'd0; +reg [21:0] rhs_self27 = 22'd0; +reg rhs_self28 = 1'd0; +reg rhs_self29 = 1'd0; +reg rhs_self3 = 1'd0; +reg [21:0] rhs_self30 = 22'd0; +reg rhs_self31 = 1'd0; +reg rhs_self32 = 1'd0; +reg [21:0] rhs_self33 = 22'd0; +reg rhs_self34 = 1'd0; +reg rhs_self35 = 1'd0; +reg rhs_self4 = 1'd0; +reg rhs_self5 = 1'd0; +reg rhs_self6 = 1'd0; +reg [14:0] rhs_self7 = 15'd0; +reg [2:0] rhs_self8 = 3'd0; +reg rhs_self9 = 1'd0; +reg [2:0] self0 = 3'd0; +reg [14:0] self1 = 15'd0; +reg self10 = 1'd0; +reg self11 = 1'd0; +reg self12 = 1'd0; +reg self13 = 1'd0; +reg self2 = 1'd0; +reg self3 = 1'd0; +reg self4 = 1'd0; +reg self5 = 1'd0; +reg self6 = 1'd0; +reg [2:0] self7 = 3'd0; +reg [14:0] self8 = 15'd0; +reg self9 = 1'd0; +reg [1:0] state = 2'd0; +wire sys2x_clk; +wire sys2x_i_clk; +wire sys2x_rst; +wire sys_clk; +wire sys_rst; +reg t_self0 = 1'd0; +reg t_self1 = 1'd0; +reg t_self2 = 1'd0; +reg t_self3 = 1'd0; +reg t_self4 = 1'd0; +reg t_self5 = 1'd0; +wire user_enable; +wire [24:0] user_port_cmd_payload_addr; +wire user_port_cmd_payload_we; +wire user_port_cmd_ready; +wire user_port_cmd_valid; +wire [127:0] user_port_rdata_payload_data; +wire user_port_rdata_ready; +wire user_port_rdata_valid; +wire [127:0] user_port_wdata_payload_data; +wire [15:0] user_port_wdata_payload_we; +wire user_port_wdata_ready; +wire user_port_wdata_valid; +wire wb_bus_ack; wire [29:0] wb_bus_adr; -wire [31:0] wb_bus_dat_w; +wire [1:0] wb_bus_bte; +wire [2:0] wb_bus_cti; +wire wb_bus_cyc; wire [31:0] wb_bus_dat_r; +wire [31:0] wb_bus_dat_w; +wire wb_bus_err; wire [3:0] wb_bus_sel; -wire wb_bus_cyc; wire wb_bus_stb; -wire wb_bus_ack; wire wb_bus_we; -wire [2:0] wb_bus_cti; -wire [1:0] wb_bus_bte; -wire wb_bus_err; -wire user_enable; -wire user_port_cmd_valid; -wire user_port_cmd_ready; -wire user_port_cmd_payload_we; -wire [24:0] user_port_cmd_payload_addr; -wire user_port_wdata_valid; -wire user_port_wdata_ready; -wire [127:0] user_port_wdata_payload_data; -wire [15:0] user_port_wdata_payload_we; -wire user_port_rdata_valid; -wire user_port_rdata_ready; -wire [127:0] user_port_rdata_payload_data; -reg [13:0] litedramcore_adr = 14'd0; -reg litedramcore_we = 1'd0; -reg [31:0] litedramcore_dat_w = 32'd0; -wire [31:0] litedramcore_dat_r; -wire [29:0] litedramcore_wishbone_adr; -wire [31:0] litedramcore_wishbone_dat_w; -reg [31:0] litedramcore_wishbone_dat_r = 32'd0; -wire [3:0] litedramcore_wishbone_sel; -wire litedramcore_wishbone_cyc; -wire litedramcore_wishbone_stb; -reg litedramcore_wishbone_ack = 1'd0; -wire litedramcore_wishbone_we; -wire [2:0] litedramcore_wishbone_cti; -wire [1:0] litedramcore_wishbone_bte; -reg litedramcore_wishbone_err = 1'd0; -wire [13:0] interface0_bank_bus_adr; -wire interface0_bank_bus_we; -wire [31:0] interface0_bank_bus_dat_w; -reg [31:0] interface0_bank_bus_dat_r = 32'd0; -reg csrbank0_init_done0_re = 1'd0; -wire csrbank0_init_done0_r; -reg csrbank0_init_done0_we = 1'd0; -wire csrbank0_init_done0_w; -reg csrbank0_init_error0_re = 1'd0; -wire csrbank0_init_error0_r; -reg csrbank0_init_error0_we = 1'd0; -wire csrbank0_init_error0_w; -wire csrbank0_sel; -wire [13:0] interface1_bank_bus_adr; -wire interface1_bank_bus_we; -wire [31:0] interface1_bank_bus_dat_w; -reg [31:0] interface1_bank_bus_dat_r = 32'd0; -reg csrbank1_dly_sel0_re = 1'd0; -wire [1:0] csrbank1_dly_sel0_r; -reg csrbank1_dly_sel0_we = 1'd0; -wire [1:0] csrbank1_dly_sel0_w; -reg csrbank1_burstdet_seen_re = 1'd0; -wire [1:0] csrbank1_burstdet_seen_r; -reg csrbank1_burstdet_seen_we = 1'd0; -wire [1:0] csrbank1_burstdet_seen_w; -wire csrbank1_sel; -wire [13:0] interface2_bank_bus_adr; -wire interface2_bank_bus_we; -wire [31:0] interface2_bank_bus_dat_w; -reg [31:0] interface2_bank_bus_dat_r = 32'd0; -reg csrbank2_dfii_control0_re = 1'd0; -wire [3:0] csrbank2_dfii_control0_r; -reg csrbank2_dfii_control0_we = 1'd0; -wire [3:0] csrbank2_dfii_control0_w; -reg csrbank2_dfii_pi0_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi0_command0_r; -reg csrbank2_dfii_pi0_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi0_command0_w; -reg csrbank2_dfii_pi0_address0_re = 1'd0; -wire [14:0] csrbank2_dfii_pi0_address0_r; -reg csrbank2_dfii_pi0_address0_we = 1'd0; -wire [14:0] csrbank2_dfii_pi0_address0_w; -reg csrbank2_dfii_pi0_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi0_baddress0_r; -reg csrbank2_dfii_pi0_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi0_baddress0_w; -reg csrbank2_dfii_pi0_wrdata1_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata1_r; -reg csrbank2_dfii_pi0_wrdata1_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata1_w; -reg csrbank2_dfii_pi0_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata0_r; -reg csrbank2_dfii_pi0_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata0_w; -reg csrbank2_dfii_pi0_rddata1_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata1_r; -reg csrbank2_dfii_pi0_rddata1_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata1_w; -reg csrbank2_dfii_pi0_rddata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata0_r; -reg csrbank2_dfii_pi0_rddata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata0_w; -reg csrbank2_dfii_pi1_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi1_command0_r; -reg csrbank2_dfii_pi1_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi1_command0_w; -reg csrbank2_dfii_pi1_address0_re = 1'd0; -wire [14:0] csrbank2_dfii_pi1_address0_r; -reg csrbank2_dfii_pi1_address0_we = 1'd0; -wire [14:0] csrbank2_dfii_pi1_address0_w; -reg csrbank2_dfii_pi1_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi1_baddress0_r; -reg csrbank2_dfii_pi1_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi1_baddress0_w; -reg csrbank2_dfii_pi1_wrdata1_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata1_r; -reg csrbank2_dfii_pi1_wrdata1_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata1_w; -reg csrbank2_dfii_pi1_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata0_r; -reg csrbank2_dfii_pi1_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata0_w; -reg csrbank2_dfii_pi1_rddata1_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata1_r; -reg csrbank2_dfii_pi1_rddata1_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata1_w; -reg csrbank2_dfii_pi1_rddata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata0_r; -reg csrbank2_dfii_pi1_rddata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata0_w; -wire csrbank2_sel; -wire [13:0] csr_interconnect_adr; -wire csr_interconnect_we; -wire [31:0] csr_interconnect_dat_w; -wire [31:0] csr_interconnect_dat_r; -wire litedramcore_litedramecp5ddrphycrg_ecp5pll; -wire litedramcore_litedramecp5ddrphycrg_locked; -reg [1:0] litedramcore_litedramcore_refresher_state = 2'd0; -reg [1:0] litedramcore_litedramcore_refresher_next_state = 2'd0; -reg [2:0] litedramcore_litedramcore_bankmachine0_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine0_next_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine1_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine1_next_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine2_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine2_next_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine3_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine3_next_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine4_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine4_next_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine5_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine5_next_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine6_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine6_next_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine7_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine7_next_state = 3'd0; -reg [3:0] litedramcore_litedramcore_multiplexer_state = 4'd0; -reg [3:0] litedramcore_litedramcore_multiplexer_next_state = 4'd0; -wire litedramcore_litedramcore_roundrobin0_request; -wire litedramcore_litedramcore_roundrobin0_grant; -wire litedramcore_litedramcore_roundrobin0_ce; -wire litedramcore_litedramcore_roundrobin1_request; -wire litedramcore_litedramcore_roundrobin1_grant; -wire litedramcore_litedramcore_roundrobin1_ce; -wire litedramcore_litedramcore_roundrobin2_request; -wire litedramcore_litedramcore_roundrobin2_grant; -wire litedramcore_litedramcore_roundrobin2_ce; -wire litedramcore_litedramcore_roundrobin3_request; -wire litedramcore_litedramcore_roundrobin3_grant; -wire litedramcore_litedramcore_roundrobin3_ce; -wire litedramcore_litedramcore_roundrobin4_request; -wire litedramcore_litedramcore_roundrobin4_grant; -wire litedramcore_litedramcore_roundrobin4_ce; -wire litedramcore_litedramcore_roundrobin5_request; -wire litedramcore_litedramcore_roundrobin5_grant; -wire litedramcore_litedramcore_roundrobin5_ce; -wire litedramcore_litedramcore_roundrobin6_request; -wire litedramcore_litedramcore_roundrobin6_grant; -wire litedramcore_litedramcore_roundrobin6_ce; -wire litedramcore_litedramcore_roundrobin7_request; -wire litedramcore_litedramcore_roundrobin7_grant; -wire litedramcore_litedramcore_roundrobin7_ce; -reg litedramcore_litedramcore_locked0 = 1'd0; -reg litedramcore_litedramcore_locked1 = 1'd0; -reg litedramcore_litedramcore_locked2 = 1'd0; -reg litedramcore_litedramcore_locked3 = 1'd0; -reg litedramcore_litedramcore_locked4 = 1'd0; -reg litedramcore_litedramcore_locked5 = 1'd0; -reg litedramcore_litedramcore_locked6 = 1'd0; -reg litedramcore_litedramcore_locked7 = 1'd0; -reg litedramcore_litedramcore_new_master_wdata_ready0 = 1'd0; -reg litedramcore_litedramcore_new_master_wdata_ready1 = 1'd0; -reg litedramcore_litedramcore_new_master_wdata_ready2 = 1'd0; -reg litedramcore_litedramcore_new_master_wdata_ready3 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid0 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid1 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid2 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid3 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid4 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid5 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid6 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid7 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid8 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid9 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid10 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid11 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid12 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid13 = 1'd0; -reg [1:0] litedramcore_state = 2'd0; -reg [1:0] litedramcore_next_state = 2'd0; -reg [31:0] litedramcore_dat_w_next_value0 = 32'd0; -reg litedramcore_dat_w_next_value_ce0 = 1'd0; -reg [13:0] litedramcore_adr_next_value1 = 14'd0; -reg litedramcore_adr_next_value_ce1 = 1'd0; -reg litedramcore_we_next_value2 = 1'd0; -reg litedramcore_we_next_value_ce2 = 1'd0; -reg rhs_array_muxed0 = 1'd0; -reg [14:0] rhs_array_muxed1 = 15'd0; -reg [2:0] rhs_array_muxed2 = 3'd0; -reg rhs_array_muxed3 = 1'd0; -reg rhs_array_muxed4 = 1'd0; -reg rhs_array_muxed5 = 1'd0; -reg t_array_muxed0 = 1'd0; -reg t_array_muxed1 = 1'd0; -reg t_array_muxed2 = 1'd0; -reg rhs_array_muxed6 = 1'd0; -reg [14:0] rhs_array_muxed7 = 15'd0; -reg [2:0] rhs_array_muxed8 = 3'd0; -reg rhs_array_muxed9 = 1'd0; -reg rhs_array_muxed10 = 1'd0; -reg rhs_array_muxed11 = 1'd0; -reg t_array_muxed3 = 1'd0; -reg t_array_muxed4 = 1'd0; -reg t_array_muxed5 = 1'd0; -reg [21:0] rhs_array_muxed12 = 22'd0; -reg rhs_array_muxed13 = 1'd0; -reg rhs_array_muxed14 = 1'd0; -reg [21:0] rhs_array_muxed15 = 22'd0; -reg rhs_array_muxed16 = 1'd0; -reg rhs_array_muxed17 = 1'd0; -reg [21:0] rhs_array_muxed18 = 22'd0; -reg rhs_array_muxed19 = 1'd0; -reg rhs_array_muxed20 = 1'd0; -reg [21:0] rhs_array_muxed21 = 22'd0; -reg rhs_array_muxed22 = 1'd0; -reg rhs_array_muxed23 = 1'd0; -reg [21:0] rhs_array_muxed24 = 22'd0; -reg rhs_array_muxed25 = 1'd0; -reg rhs_array_muxed26 = 1'd0; -reg [21:0] rhs_array_muxed27 = 22'd0; -reg rhs_array_muxed28 = 1'd0; -reg rhs_array_muxed29 = 1'd0; -reg [21:0] rhs_array_muxed30 = 22'd0; -reg rhs_array_muxed31 = 1'd0; -reg rhs_array_muxed32 = 1'd0; -reg [21:0] rhs_array_muxed33 = 22'd0; -reg rhs_array_muxed34 = 1'd0; -reg rhs_array_muxed35 = 1'd0; -reg [2:0] array_muxed0 = 3'd0; -reg [14:0] array_muxed1 = 15'd0; -reg array_muxed2 = 1'd0; -reg array_muxed3 = 1'd0; -reg array_muxed4 = 1'd0; -reg array_muxed5 = 1'd0; -reg array_muxed6 = 1'd0; -reg [2:0] array_muxed7 = 3'd0; -reg [14:0] array_muxed8 = 15'd0; -reg array_muxed9 = 1'd0; -reg array_muxed10 = 1'd0; -reg array_muxed11 = 1'd0; -reg array_muxed12 = 1'd0; -reg array_muxed13 = 1'd0; -wire latticeecp5asyncresetsynchronizerimpl0_rst1; -wire latticeecp5asyncresetsynchronizerimpl0_expr; -wire latticeecp5asyncresetsynchronizerimpl1_rst1; -wire latticeecp5asyncresetsynchronizerimpl2_rst1; -wire latticeecp5asyncresetsynchronizerimpl3_rst1; -reg regs0 = 1'd0; -reg regs1 = 1'd0; +wire we; //------------------------------------------------------------------------------ // Combinatorial Logic @@ -1902,6 +2235,17 @@ assign user_port_wdata_payload_data = user_port_native_0_wdata_data; assign user_port_native_0_rdata_valid = (user_port_rdata_valid & user_enable); assign user_port_rdata_ready = (user_port_native_0_rdata_ready & user_enable); assign user_port_native_0_rdata_data = user_port_rdata_payload_data; +assign interface0_adr = wb_bus_adr; +assign interface0_dat_w = wb_bus_dat_w; +assign wb_bus_dat_r = interface0_dat_r; +assign interface0_sel = wb_bus_sel; +assign interface0_cyc = wb_bus_cyc; +assign interface0_stb = wb_bus_stb; +assign wb_bus_ack = interface0_ack; +assign interface0_we = wb_bus_we; +assign interface0_cti = wb_bus_cti; +assign interface0_bte = wb_bus_bte; +assign wb_bus_err = interface0_err; assign por_clk = clk; assign crg_por_done = (crg_por_count == 1'd0); assign crg_reset1 = (((~crg_por_done) | rst) | crg_rst); @@ -1909,7 +2253,7 @@ assign pll_locked = crg_locked; assign crg_clkin = clk; assign sys2x_i_clk = crg_clkout0; assign init_clk = crg_clkout1; -assign crg_locked = (litedramcore_litedramecp5ddrphycrg_locked & (~crg_reset1)); +assign crg_locked = (litedramecp5ddrphycrg_locked & (~crg_reset1)); always @(*) begin ddrphy_dm_o_data0 <= 8'd0; ddrphy_dm_o_data0[0] <= ddrphy_dfi_p0_wrdata_mask[1]; @@ -2614,6 +2958,9 @@ always @(*) begin litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n; end else begin litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; + if (1'd0) begin + litedramcore_master_p0_cs_n <= {2{litedramcore_slave_p0_cs_n}}; + end end end else begin litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n; @@ -2796,6 +3143,9 @@ always @(*) begin litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n; end else begin litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; + if (1'd0) begin + litedramcore_master_p1_cs_n <= {2{litedramcore_slave_p1_cs_n}}; + end end end else begin litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n; @@ -3051,10 +3401,22 @@ always @(*) begin litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n; end end -assign litedramcore_csr_dfi_p0_cke = litedramcore_cke; -assign litedramcore_csr_dfi_p1_cke = litedramcore_cke; -assign litedramcore_csr_dfi_p0_odt = litedramcore_odt; -assign litedramcore_csr_dfi_p1_odt = litedramcore_odt; +always @(*) begin + litedramcore_csr_dfi_p0_cke <= 1'd0; + litedramcore_csr_dfi_p0_cke <= litedramcore_cke; +end +always @(*) begin + litedramcore_csr_dfi_p1_cke <= 1'd0; + litedramcore_csr_dfi_p1_cke <= litedramcore_cke; +end +always @(*) begin + litedramcore_csr_dfi_p0_odt <= 1'd0; + litedramcore_csr_dfi_p0_odt <= litedramcore_odt; +end +always @(*) begin + litedramcore_csr_dfi_p1_odt <= 1'd0; + litedramcore_csr_dfi_p1_odt <= litedramcore_odt; +end assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n; assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n; always @(*) begin @@ -3068,7 +3430,15 @@ end always @(*) begin litedramcore_csr_dfi_p0_cs_n <= 1'd1; if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}}; + if (litedramcore_phaseinjector0_csrfield_cs_top) begin + litedramcore_csr_dfi_p0_cs_n <= 2'd2; + end else begin + if (litedramcore_phaseinjector0_csrfield_cs_bottom) begin + litedramcore_csr_dfi_p0_cs_n <= 1'd1; + end else begin + litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}}; + end + end end else begin litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; end @@ -3106,7 +3476,15 @@ end always @(*) begin litedramcore_csr_dfi_p1_cs_n <= 1'd1; if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}}; + if (litedramcore_phaseinjector1_csrfield_cs_top) begin + litedramcore_csr_dfi_p1_cs_n <= 2'd2; + end else begin + if (litedramcore_phaseinjector1_csrfield_cs_bottom) begin + litedramcore_csr_dfi_p1_cs_n <= 1'd1; + end else begin + litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}}; + end + end end else begin litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; end @@ -3203,32 +3581,32 @@ assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0); assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1; assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1; always @(*) begin - litedramcore_litedramcore_refresher_next_state <= 2'd0; - litedramcore_litedramcore_refresher_next_state <= litedramcore_litedramcore_refresher_state; - case (litedramcore_litedramcore_refresher_state) + litedramcore_refresher_next_state <= 2'd0; + litedramcore_refresher_next_state <= litedramcore_refresher_state; + case (litedramcore_refresher_state) 1'd1: begin if (litedramcore_cmd_ready) begin - litedramcore_litedramcore_refresher_next_state <= 2'd2; + litedramcore_refresher_next_state <= 2'd2; end end 2'd2: begin if (litedramcore_sequencer_done0) begin if (litedramcore_wants_zqcs) begin - litedramcore_litedramcore_refresher_next_state <= 2'd3; + litedramcore_refresher_next_state <= 2'd3; end else begin - litedramcore_litedramcore_refresher_next_state <= 1'd0; + litedramcore_refresher_next_state <= 1'd0; end end end 2'd3: begin if (litedramcore_zqcs_executer_done) begin - litedramcore_litedramcore_refresher_next_state <= 1'd0; + litedramcore_refresher_next_state <= 1'd0; end end default: begin if (1'd1) begin if (litedramcore_wants_refresh) begin - litedramcore_litedramcore_refresher_next_state <= 1'd1; + litedramcore_refresher_next_state <= 1'd1; end end end @@ -3236,7 +3614,7 @@ always @(*) begin end always @(*) begin litedramcore_sequencer_start0 <= 1'd0; - case (litedramcore_litedramcore_refresher_state) + case (litedramcore_refresher_state) 1'd1: begin if (litedramcore_cmd_ready) begin litedramcore_sequencer_start0 <= 1'd1; @@ -3252,7 +3630,7 @@ always @(*) begin end always @(*) begin litedramcore_cmd_valid <= 1'd0; - case (litedramcore_litedramcore_refresher_state) + case (litedramcore_refresher_state) 1'd1: begin litedramcore_cmd_valid <= 1'd1; end @@ -3277,7 +3655,7 @@ always @(*) begin end always @(*) begin litedramcore_zqcs_executer_start <= 1'd0; - case (litedramcore_litedramcore_refresher_state) + case (litedramcore_refresher_state) 1'd1: begin end 2'd2: begin @@ -3296,7 +3674,7 @@ always @(*) begin end always @(*) begin litedramcore_cmd_last <= 1'd0; - case (litedramcore_litedramcore_refresher_state) + case (litedramcore_refresher_state) 1'd1: begin end 2'd2: begin @@ -3395,169 +3773,54 @@ assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_ assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we; assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr; always @(*) begin - litedramcore_litedramcore_bankmachine0_next_state <= 3'd0; - litedramcore_litedramcore_bankmachine0_next_state <= litedramcore_litedramcore_bankmachine0_state; - case (litedramcore_litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - if (litedramcore_bankmachine0_cmd_ready) begin - litedramcore_litedramcore_bankmachine0_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_litedramcore_bankmachine0_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - if (litedramcore_bankmachine0_cmd_ready) begin - litedramcore_litedramcore_bankmachine0_next_state <= 3'd6; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine0_refresh_req)) begin - litedramcore_litedramcore_bankmachine0_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_litedramcore_bankmachine0_next_state <= 2'd3; - end - 3'd6: begin - litedramcore_litedramcore_bankmachine0_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - litedramcore_litedramcore_bankmachine0_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin - litedramcore_litedramcore_bankmachine0_next_state <= 2'd2; - end - end else begin - litedramcore_litedramcore_bankmachine0_next_state <= 1'd1; - end - end else begin - litedramcore_litedramcore_bankmachine0_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) + litedramcore_bankmachine0_next_state <= 3'd0; + litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state; + case (litedramcore_bankmachine0_state) 1'd1: begin if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + if (litedramcore_bankmachine0_cmd_ready) begin + litedramcore_bankmachine0_next_state <= 3'd5; + end end end 2'd2: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_next_state <= 3'd5; + end end 2'd3: begin if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + if (litedramcore_bankmachine0_cmd_ready) begin + litedramcore_bankmachine0_next_state <= 3'd6; + end end end 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + if ((~litedramcore_bankmachine0_refresh_req)) begin + litedramcore_bankmachine0_next_state <= 1'd0; end end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end 3'd5: begin + litedramcore_bankmachine0_next_state <= 2'd3; end 3'd6: begin + litedramcore_bankmachine0_next_state <= 1'd0; end default: begin if (litedramcore_bankmachine0_refresh_req) begin + litedramcore_bankmachine0_next_state <= 3'd4; end else begin if (litedramcore_bankmachine0_source_source_valid) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end else begin + if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin + litedramcore_bankmachine0_next_state <= 2'd2; end end else begin + litedramcore_bankmachine0_next_state <= 1'd1; end end else begin + litedramcore_bankmachine0_next_state <= 2'd3; end end end @@ -3566,7 +3829,7 @@ always @(*) begin end always @(*) begin litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) + case (litedramcore_bankmachine0_state) 1'd1: begin if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; @@ -3592,7 +3855,7 @@ always @(*) begin end always @(*) begin litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) + case (litedramcore_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -3626,7 +3889,7 @@ always @(*) begin end always @(*) begin litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) + case (litedramcore_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -3660,7 +3923,7 @@ always @(*) begin end always @(*) begin litedramcore_bankmachine0_req_wdata_ready <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) + case (litedramcore_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -3694,7 +3957,7 @@ always @(*) begin end always @(*) begin litedramcore_bankmachine0_req_rdata_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) + case (litedramcore_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -3728,7 +3991,7 @@ always @(*) begin end always @(*) begin litedramcore_bankmachine0_refresh_gnt <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) + case (litedramcore_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -3750,7 +4013,7 @@ always @(*) begin end always @(*) begin litedramcore_bankmachine0_row_open <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) + case (litedramcore_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -3772,7 +4035,7 @@ always @(*) begin end always @(*) begin litedramcore_bankmachine0_cmd_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) + case (litedramcore_bankmachine0_state) 1'd1: begin if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin litedramcore_bankmachine0_cmd_valid <= 1'd1; @@ -3809,7 +4072,7 @@ always @(*) begin end always @(*) begin litedramcore_bankmachine0_row_close <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) + case (litedramcore_bankmachine0_state) 1'd1: begin litedramcore_bankmachine0_row_close <= 1'd1; end @@ -3829,6 +4092,121 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid; assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready; assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we; @@ -3908,54 +4286,54 @@ assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_ assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we; assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr; always @(*) begin - litedramcore_litedramcore_bankmachine1_next_state <= 3'd0; - litedramcore_litedramcore_bankmachine1_next_state <= litedramcore_litedramcore_bankmachine1_state; - case (litedramcore_litedramcore_bankmachine1_state) + litedramcore_bankmachine1_next_state <= 3'd0; + litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state; + case (litedramcore_bankmachine1_state) 1'd1: begin if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin if (litedramcore_bankmachine1_cmd_ready) begin - litedramcore_litedramcore_bankmachine1_next_state <= 3'd5; + litedramcore_bankmachine1_next_state <= 3'd5; end end end 2'd2: begin if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_litedramcore_bankmachine1_next_state <= 3'd5; + litedramcore_bankmachine1_next_state <= 3'd5; end end 2'd3: begin if (litedramcore_bankmachine1_trccon_ready) begin if (litedramcore_bankmachine1_cmd_ready) begin - litedramcore_litedramcore_bankmachine1_next_state <= 3'd6; + litedramcore_bankmachine1_next_state <= 3'd6; end end end 3'd4: begin if ((~litedramcore_bankmachine1_refresh_req)) begin - litedramcore_litedramcore_bankmachine1_next_state <= 1'd0; + litedramcore_bankmachine1_next_state <= 1'd0; end end 3'd5: begin - litedramcore_litedramcore_bankmachine1_next_state <= 2'd3; + litedramcore_bankmachine1_next_state <= 2'd3; end 3'd6: begin - litedramcore_litedramcore_bankmachine1_next_state <= 1'd0; + litedramcore_bankmachine1_next_state <= 1'd0; end default: begin if (litedramcore_bankmachine1_refresh_req) begin - litedramcore_litedramcore_bankmachine1_next_state <= 3'd4; + litedramcore_bankmachine1_next_state <= 3'd4; end else begin if (litedramcore_bankmachine1_source_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin - litedramcore_litedramcore_bankmachine1_next_state <= 2'd2; + litedramcore_bankmachine1_next_state <= 2'd2; end end else begin - litedramcore_litedramcore_bankmachine1_next_state <= 1'd1; + litedramcore_bankmachine1_next_state <= 1'd1; end end else begin - litedramcore_litedramcore_bankmachine1_next_state <= 2'd3; + litedramcore_bankmachine1_next_state <= 2'd3; end end end @@ -3963,8 +4341,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) + litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -3983,7 +4361,10 @@ always @(*) begin if (litedramcore_bankmachine1_source_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; + end end else begin end end else begin @@ -3994,18 +4375,37 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) + litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine1_twtpcon_ready) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd1; end end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_open <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + litedramcore_bankmachine1_row_open <= 1'd1; end end 3'd4: begin @@ -4019,16 +4419,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) + litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (litedramcore_bankmachine1_state) 1'd1: begin if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + litedramcore_bankmachine1_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -4042,10 +4445,7 @@ always @(*) begin if (litedramcore_bankmachine1_source_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end else begin - end + litedramcore_bankmachine1_cmd_valid <= 1'd1; end else begin end end else begin @@ -4056,22 +4456,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) + litedramcore_bankmachine1_row_close <= 1'd0; + case (litedramcore_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end + litedramcore_bankmachine1_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -4082,13 +4478,16 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -4097,27 +4496,12 @@ always @(*) begin 3'd6: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - end else begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) + litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -4136,10 +4520,7 @@ always @(*) begin if (litedramcore_bankmachine1_source_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; - end else begin - end + litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -4150,43 +4531,37 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_req_wdata_ready <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) + litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end 3'd5: begin end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end + 3'd6: begin + end + default: begin + end endcase end always @(*) begin - litedramcore_bankmachine1_req_rdata_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) + litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -4205,8 +4580,8 @@ always @(*) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end else begin - litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; end end else begin end @@ -4218,40 +4593,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine1_state) 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine1_twtpcon_ready) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd1; + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_row_open <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) - 1'd1: begin - end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_open <= 1'd1; + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -4262,19 +4619,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -4288,7 +4639,10 @@ always @(*) begin if (litedramcore_bankmachine1_source_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; + if (litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; + end end else begin end end else begin @@ -4299,38 +4653,47 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_row_close <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine1_state) 1'd1: begin - litedramcore_bankmachine1_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end 3'd6: begin end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) + litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -4339,6 +4702,21 @@ always @(*) begin 3'd6: begin end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end @@ -4421,54 +4799,54 @@ assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_ assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we; assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr; always @(*) begin - litedramcore_litedramcore_bankmachine2_next_state <= 3'd0; - litedramcore_litedramcore_bankmachine2_next_state <= litedramcore_litedramcore_bankmachine2_state; - case (litedramcore_litedramcore_bankmachine2_state) + litedramcore_bankmachine2_next_state <= 3'd0; + litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state; + case (litedramcore_bankmachine2_state) 1'd1: begin if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin if (litedramcore_bankmachine2_cmd_ready) begin - litedramcore_litedramcore_bankmachine2_next_state <= 3'd5; + litedramcore_bankmachine2_next_state <= 3'd5; end end end 2'd2: begin if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_litedramcore_bankmachine2_next_state <= 3'd5; + litedramcore_bankmachine2_next_state <= 3'd5; end end 2'd3: begin if (litedramcore_bankmachine2_trccon_ready) begin if (litedramcore_bankmachine2_cmd_ready) begin - litedramcore_litedramcore_bankmachine2_next_state <= 3'd6; + litedramcore_bankmachine2_next_state <= 3'd6; end end end 3'd4: begin if ((~litedramcore_bankmachine2_refresh_req)) begin - litedramcore_litedramcore_bankmachine2_next_state <= 1'd0; + litedramcore_bankmachine2_next_state <= 1'd0; end end 3'd5: begin - litedramcore_litedramcore_bankmachine2_next_state <= 2'd3; + litedramcore_bankmachine2_next_state <= 2'd3; end 3'd6: begin - litedramcore_litedramcore_bankmachine2_next_state <= 1'd0; + litedramcore_bankmachine2_next_state <= 1'd0; end default: begin if (litedramcore_bankmachine2_refresh_req) begin - litedramcore_litedramcore_bankmachine2_next_state <= 3'd4; + litedramcore_bankmachine2_next_state <= 3'd4; end else begin if (litedramcore_bankmachine2_source_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin - litedramcore_litedramcore_bankmachine2_next_state <= 2'd2; + litedramcore_bankmachine2_next_state <= 2'd2; end end else begin - litedramcore_litedramcore_bankmachine2_next_state <= 1'd1; + litedramcore_bankmachine2_next_state <= 1'd1; end end else begin - litedramcore_litedramcore_bankmachine2_next_state <= 2'd3; + litedramcore_bankmachine2_next_state <= 2'd3; end end end @@ -4476,82 +4854,39 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) + litedramcore_bankmachine2_row_close <= 1'd0; + case (litedramcore_bankmachine2_state) 1'd1: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end 3'd6: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin - end else begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; end end - endcase -end -always @(*) begin - litedramcore_bankmachine2_req_wdata_ready <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end 3'd4: begin end 3'd5: begin @@ -4559,27 +4894,12 @@ always @(*) begin 3'd6: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin - litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine2_req_rdata_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) + litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -4598,10 +4918,7 @@ always @(*) begin if (litedramcore_bankmachine2_source_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin - end else begin - litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; - end + litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -4612,37 +4929,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) + litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine2_state) 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine2_twtpcon_ready) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd1; + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_row_open <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) - 1'd1: begin - end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open <= 1'd1; + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -4656,19 +4954,16 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) + litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine2_state) 1'd1: begin if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -4682,7 +4977,10 @@ always @(*) begin if (litedramcore_bankmachine2_source_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -4693,18 +4991,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_row_close <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine2_state) 1'd1: begin - litedramcore_bankmachine2_row_close <= 1'd1; + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin - litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin - litedramcore_bankmachine2_row_close <= 1'd1; + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -4715,19 +5017,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -4736,20 +5032,32 @@ always @(*) begin 3'd6: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + end else begin + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -4758,12 +5066,27 @@ always @(*) begin 3'd6: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) + litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -4782,7 +5105,10 @@ always @(*) begin if (litedramcore_bankmachine2_source_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; + end else begin + end end else begin end end else begin @@ -4793,12 +5119,9 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) + litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -4817,8 +5140,8 @@ always @(*) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin if (litedramcore_bankmachine2_source_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end else begin + litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; end end else begin end @@ -4830,28 +5153,83 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) + litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine2_twtpcon_ready) begin + litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_open <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_valid <= 1'd0; + case (litedramcore_bankmachine2_state) 1'd1: begin if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine2_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine2_cmd_valid <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end 3'd6: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end @@ -4934,54 +5312,54 @@ assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_ assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we; assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr; always @(*) begin - litedramcore_litedramcore_bankmachine3_next_state <= 3'd0; - litedramcore_litedramcore_bankmachine3_next_state <= litedramcore_litedramcore_bankmachine3_state; - case (litedramcore_litedramcore_bankmachine3_state) + litedramcore_bankmachine3_next_state <= 3'd0; + litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state; + case (litedramcore_bankmachine3_state) 1'd1: begin if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin if (litedramcore_bankmachine3_cmd_ready) begin - litedramcore_litedramcore_bankmachine3_next_state <= 3'd5; + litedramcore_bankmachine3_next_state <= 3'd5; end end end 2'd2: begin if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_litedramcore_bankmachine3_next_state <= 3'd5; + litedramcore_bankmachine3_next_state <= 3'd5; end end 2'd3: begin if (litedramcore_bankmachine3_trccon_ready) begin if (litedramcore_bankmachine3_cmd_ready) begin - litedramcore_litedramcore_bankmachine3_next_state <= 3'd6; + litedramcore_bankmachine3_next_state <= 3'd6; end end end 3'd4: begin if ((~litedramcore_bankmachine3_refresh_req)) begin - litedramcore_litedramcore_bankmachine3_next_state <= 1'd0; + litedramcore_bankmachine3_next_state <= 1'd0; end end 3'd5: begin - litedramcore_litedramcore_bankmachine3_next_state <= 2'd3; + litedramcore_bankmachine3_next_state <= 2'd3; end 3'd6: begin - litedramcore_litedramcore_bankmachine3_next_state <= 1'd0; + litedramcore_bankmachine3_next_state <= 1'd0; end default: begin if (litedramcore_bankmachine3_refresh_req) begin - litedramcore_litedramcore_bankmachine3_next_state <= 3'd4; + litedramcore_bankmachine3_next_state <= 3'd4; end else begin if (litedramcore_bankmachine3_source_source_valid) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin - litedramcore_litedramcore_bankmachine3_next_state <= 2'd2; + litedramcore_bankmachine3_next_state <= 2'd2; end end else begin - litedramcore_litedramcore_bankmachine3_next_state <= 1'd1; + litedramcore_bankmachine3_next_state <= 1'd1; end end else begin - litedramcore_litedramcore_bankmachine3_next_state <= 2'd3; + litedramcore_bankmachine3_next_state <= 2'd3; end end end @@ -4989,8 +5367,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) + litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -4998,28 +5376,40 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine3_twtpcon_ready) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd1; - end end 3'd5: begin end 3'd6: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine3_row_open <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) + litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine3_state) 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_open <= 1'd1; + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -5033,19 +5423,16 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) + litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine3_state) 1'd1: begin if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -5059,7 +5446,10 @@ always @(*) begin if (litedramcore_bankmachine3_source_source_valid) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -5070,18 +5460,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_row_close <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine3_state) 1'd1: begin - litedramcore_bankmachine3_row_close <= 1'd1; + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin - litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin - litedramcore_bankmachine3_row_close <= 1'd1; + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5092,16 +5486,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -5110,12 +5501,27 @@ always @(*) begin 3'd6: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + end else begin + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -5134,7 +5540,10 @@ always @(*) begin if (litedramcore_bankmachine3_source_source_valid) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + end else begin + end end else begin end end else begin @@ -5145,19 +5554,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) + litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -5166,16 +5569,28 @@ always @(*) begin 3'd6: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) + litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -5194,8 +5609,8 @@ always @(*) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin if (litedramcore_bankmachine3_source_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; end else begin + litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; end end else begin end @@ -5207,22 +5622,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) + litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + if (litedramcore_bankmachine3_twtpcon_ready) begin + litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -5233,13 +5644,16 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) + litedramcore_bankmachine3_row_open <= 1'd0; + case (litedramcore_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_open <= 1'd1; + end end 3'd4: begin end @@ -5248,32 +5662,23 @@ always @(*) begin 3'd6: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin - end else begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) + litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (litedramcore_bankmachine3_state) 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -5287,10 +5692,7 @@ always @(*) begin if (litedramcore_bankmachine3_source_source_valid) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; - end else begin - end + litedramcore_bankmachine3_cmd_valid <= 1'd1; end else begin end end else begin @@ -5301,47 +5703,38 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_req_wdata_ready <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) + litedramcore_bankmachine3_row_close <= 1'd0; + case (litedramcore_bankmachine3_state) 1'd1: begin + litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine3_row_close <= 1'd1; end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin - litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end + 3'd5: begin + end + 3'd6: begin + end + default: begin end endcase end always @(*) begin - litedramcore_bankmachine3_req_rdata_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -5350,21 +5743,6 @@ always @(*) begin 3'd6: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin - end else begin - litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end @@ -5447,54 +5825,54 @@ assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_ assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we; assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr; always @(*) begin - litedramcore_litedramcore_bankmachine4_next_state <= 3'd0; - litedramcore_litedramcore_bankmachine4_next_state <= litedramcore_litedramcore_bankmachine4_state; - case (litedramcore_litedramcore_bankmachine4_state) + litedramcore_bankmachine4_next_state <= 3'd0; + litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state; + case (litedramcore_bankmachine4_state) 1'd1: begin if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin if (litedramcore_bankmachine4_cmd_ready) begin - litedramcore_litedramcore_bankmachine4_next_state <= 3'd5; + litedramcore_bankmachine4_next_state <= 3'd5; end end end 2'd2: begin if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_litedramcore_bankmachine4_next_state <= 3'd5; + litedramcore_bankmachine4_next_state <= 3'd5; end end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin if (litedramcore_bankmachine4_cmd_ready) begin - litedramcore_litedramcore_bankmachine4_next_state <= 3'd6; + litedramcore_bankmachine4_next_state <= 3'd6; end end end 3'd4: begin if ((~litedramcore_bankmachine4_refresh_req)) begin - litedramcore_litedramcore_bankmachine4_next_state <= 1'd0; + litedramcore_bankmachine4_next_state <= 1'd0; end end 3'd5: begin - litedramcore_litedramcore_bankmachine4_next_state <= 2'd3; + litedramcore_bankmachine4_next_state <= 2'd3; end 3'd6: begin - litedramcore_litedramcore_bankmachine4_next_state <= 1'd0; + litedramcore_bankmachine4_next_state <= 1'd0; end default: begin if (litedramcore_bankmachine4_refresh_req) begin - litedramcore_litedramcore_bankmachine4_next_state <= 3'd4; + litedramcore_bankmachine4_next_state <= 3'd4; end else begin if (litedramcore_bankmachine4_source_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin - litedramcore_litedramcore_bankmachine4_next_state <= 2'd2; + litedramcore_bankmachine4_next_state <= 2'd2; end end else begin - litedramcore_litedramcore_bankmachine4_next_state <= 1'd1; + litedramcore_bankmachine4_next_state <= 1'd1; end end else begin - litedramcore_litedramcore_bankmachine4_next_state <= 2'd3; + litedramcore_bankmachine4_next_state <= 2'd3; end end end @@ -5502,18 +5880,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5524,8 +5906,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -5544,7 +5926,10 @@ always @(*) begin if (litedramcore_bankmachine4_source_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine4_source_source_payload_we) begin + end else begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + end end else begin end end else begin @@ -5555,37 +5940,9 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -5604,7 +5961,7 @@ always @(*) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin if (litedramcore_bankmachine4_source_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -5617,34 +5974,42 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) + litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end 3'd6: begin end default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) + litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -5665,7 +6030,7 @@ always @(*) begin if (litedramcore_bankmachine4_row_hit) begin if (litedramcore_bankmachine4_source_source_payload_we) begin end else begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; end end else begin end @@ -5677,8 +6042,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) + litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -5686,38 +6051,29 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (litedramcore_bankmachine4_twtpcon_ready) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end end 3'd5: begin end 3'd6: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine4_req_wdata_ready <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) + litedramcore_bankmachine4_row_open <= 1'd0; + case (litedramcore_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_open <= 1'd1; + end end 3'd4: begin end @@ -5726,32 +6082,23 @@ always @(*) begin 3'd6: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin - litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine4_req_rdata_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) + litedramcore_bankmachine4_cmd_valid <= 1'd0; + case (litedramcore_bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -5765,10 +6112,7 @@ always @(*) begin if (litedramcore_bankmachine4_source_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin - end else begin - litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; - end + litedramcore_bankmachine4_cmd_valid <= 1'd1; end else begin end end else begin @@ -5779,18 +6123,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) + litedramcore_bankmachine4_row_close <= 1'd0; + case (litedramcore_bankmachine4_state) 1'd1: begin + litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine4_twtpcon_ready) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd1; - end + litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -5801,15 +6145,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_row_open <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_open <= 1'd1; + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -5823,19 +6167,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) + litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -5849,7 +6187,7 @@ always @(*) begin if (litedramcore_bankmachine4_source_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; + litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -5860,18 +6198,21 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_row_close <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) + litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine4_state) 1'd1: begin - litedramcore_bankmachine4_row_close <= 1'd1; + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end end 2'd2: begin - litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end end 3'd4: begin - litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -5881,6 +6222,43 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid; assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready; assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we; @@ -5960,54 +6338,54 @@ assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_ assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we; assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr; always @(*) begin - litedramcore_litedramcore_bankmachine5_next_state <= 3'd0; - litedramcore_litedramcore_bankmachine5_next_state <= litedramcore_litedramcore_bankmachine5_state; - case (litedramcore_litedramcore_bankmachine5_state) + litedramcore_bankmachine5_next_state <= 3'd0; + litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state; + case (litedramcore_bankmachine5_state) 1'd1: begin if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin if (litedramcore_bankmachine5_cmd_ready) begin - litedramcore_litedramcore_bankmachine5_next_state <= 3'd5; + litedramcore_bankmachine5_next_state <= 3'd5; end end end 2'd2: begin if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_litedramcore_bankmachine5_next_state <= 3'd5; + litedramcore_bankmachine5_next_state <= 3'd5; end end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin if (litedramcore_bankmachine5_cmd_ready) begin - litedramcore_litedramcore_bankmachine5_next_state <= 3'd6; + litedramcore_bankmachine5_next_state <= 3'd6; end end end 3'd4: begin if ((~litedramcore_bankmachine5_refresh_req)) begin - litedramcore_litedramcore_bankmachine5_next_state <= 1'd0; + litedramcore_bankmachine5_next_state <= 1'd0; end end 3'd5: begin - litedramcore_litedramcore_bankmachine5_next_state <= 2'd3; + litedramcore_bankmachine5_next_state <= 2'd3; end 3'd6: begin - litedramcore_litedramcore_bankmachine5_next_state <= 1'd0; + litedramcore_bankmachine5_next_state <= 1'd0; end default: begin if (litedramcore_bankmachine5_refresh_req) begin - litedramcore_litedramcore_bankmachine5_next_state <= 3'd4; + litedramcore_bankmachine5_next_state <= 3'd4; end else begin if (litedramcore_bankmachine5_source_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin - litedramcore_litedramcore_bankmachine5_next_state <= 2'd2; + litedramcore_bankmachine5_next_state <= 2'd2; end end else begin - litedramcore_litedramcore_bankmachine5_next_state <= 1'd1; + litedramcore_bankmachine5_next_state <= 1'd1; end end else begin - litedramcore_litedramcore_bankmachine5_next_state <= 2'd3; + litedramcore_bankmachine5_next_state <= 2'd3; end end end @@ -6015,8 +6393,42 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) + litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + end else begin + litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -6024,40 +6436,28 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (litedramcore_bankmachine5_twtpcon_ready) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end end 3'd5: begin end 3'd6: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) + litedramcore_bankmachine5_row_open <= 1'd0; + case (litedramcore_bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + litedramcore_bankmachine5_row_open <= 1'd1; end end 3'd4: begin @@ -6071,16 +6471,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) + litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (litedramcore_bankmachine5_state) 1'd1: begin if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + litedramcore_bankmachine5_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -6094,10 +6497,7 @@ always @(*) begin if (litedramcore_bankmachine5_source_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; - end else begin - end + litedramcore_bankmachine5_cmd_valid <= 1'd1; end else begin end end else begin @@ -6108,22 +6508,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) + litedramcore_bankmachine5_row_close <= 1'd0; + case (litedramcore_bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end + litedramcore_bankmachine5_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine5_row_close <= 1'd1; end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine5_row_close <= 1'd1; end 3'd5: begin end @@ -6134,13 +6530,16 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -6149,27 +6548,12 @@ always @(*) begin 3'd6: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin - end else begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) + litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -6188,10 +6572,7 @@ always @(*) begin if (litedramcore_bankmachine5_source_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; - end else begin - end + litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -6202,13 +6583,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_req_wdata_ready <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) + litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine5_state) 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -6217,28 +6604,16 @@ always @(*) begin 3'd6: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin - litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine5_req_rdata_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) + litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine5_state) 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -6257,8 +6632,8 @@ always @(*) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; end else begin - litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; end end else begin end @@ -6270,40 +6645,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine5_state) 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine5_twtpcon_ready) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd1; + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_row_open <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) - 1'd1: begin - end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_open <= 1'd1; + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6314,19 +6671,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -6340,7 +6691,10 @@ always @(*) begin if (litedramcore_bankmachine5_source_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; + if (litedramcore_bankmachine5_source_source_payload_we) begin + end else begin + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + end end else begin end end else begin @@ -6351,38 +6705,47 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_row_close <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine5_state) 1'd1: begin - litedramcore_bankmachine5_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine5_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine5_row_close <= 1'd1; end 3'd5: begin end 3'd6: begin end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) + litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -6391,6 +6754,21 @@ always @(*) begin 3'd6: begin end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end @@ -6473,54 +6851,54 @@ assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_ assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we; assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr; always @(*) begin - litedramcore_litedramcore_bankmachine6_next_state <= 3'd0; - litedramcore_litedramcore_bankmachine6_next_state <= litedramcore_litedramcore_bankmachine6_state; - case (litedramcore_litedramcore_bankmachine6_state) + litedramcore_bankmachine6_next_state <= 3'd0; + litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state; + case (litedramcore_bankmachine6_state) 1'd1: begin if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin if (litedramcore_bankmachine6_cmd_ready) begin - litedramcore_litedramcore_bankmachine6_next_state <= 3'd5; + litedramcore_bankmachine6_next_state <= 3'd5; end end end 2'd2: begin if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_litedramcore_bankmachine6_next_state <= 3'd5; + litedramcore_bankmachine6_next_state <= 3'd5; end end 2'd3: begin if (litedramcore_bankmachine6_trccon_ready) begin if (litedramcore_bankmachine6_cmd_ready) begin - litedramcore_litedramcore_bankmachine6_next_state <= 3'd6; + litedramcore_bankmachine6_next_state <= 3'd6; end end end 3'd4: begin if ((~litedramcore_bankmachine6_refresh_req)) begin - litedramcore_litedramcore_bankmachine6_next_state <= 1'd0; + litedramcore_bankmachine6_next_state <= 1'd0; end end 3'd5: begin - litedramcore_litedramcore_bankmachine6_next_state <= 2'd3; + litedramcore_bankmachine6_next_state <= 2'd3; end 3'd6: begin - litedramcore_litedramcore_bankmachine6_next_state <= 1'd0; + litedramcore_bankmachine6_next_state <= 1'd0; end default: begin if (litedramcore_bankmachine6_refresh_req) begin - litedramcore_litedramcore_bankmachine6_next_state <= 3'd4; + litedramcore_bankmachine6_next_state <= 3'd4; end else begin if (litedramcore_bankmachine6_source_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin - litedramcore_litedramcore_bankmachine6_next_state <= 2'd2; + litedramcore_bankmachine6_next_state <= 2'd2; end end else begin - litedramcore_litedramcore_bankmachine6_next_state <= 1'd1; + litedramcore_bankmachine6_next_state <= 1'd1; end end else begin - litedramcore_litedramcore_bankmachine6_next_state <= 2'd3; + litedramcore_bankmachine6_next_state <= 2'd3; end end end @@ -6528,82 +6906,39 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) + litedramcore_bankmachine6_row_close <= 1'd0; + case (litedramcore_bankmachine6_state) 1'd1: begin + litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end 3'd6: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin - end else begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; end end - endcase -end -always @(*) begin - litedramcore_bankmachine6_req_wdata_ready <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end 3'd4: begin end 3'd5: begin @@ -6611,27 +6946,12 @@ always @(*) begin 3'd6: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin - litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine6_req_rdata_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) + litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -6650,10 +6970,7 @@ always @(*) begin if (litedramcore_bankmachine6_source_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin - end else begin - litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; - end + litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -6664,15 +6981,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_row_open <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) + litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine6_state) 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_open <= 1'd1; + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -6686,19 +7006,16 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) + litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine6_state) 1'd1: begin if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -6712,7 +7029,10 @@ always @(*) begin if (litedramcore_bankmachine6_source_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -6723,18 +7043,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_row_close <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) + litedramcore_bankmachine6_row_open <= 1'd0; + case (litedramcore_bankmachine6_state) 1'd1: begin - litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_open <= 1'd1; + end end 3'd4: begin - litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -6745,18 +7065,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine6_state) 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine6_twtpcon_ready) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6767,16 +7091,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -6785,12 +7106,27 @@ always @(*) begin 3'd6: begin end default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + end else begin + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -6809,7 +7145,10 @@ always @(*) begin if (litedramcore_bankmachine6_source_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + end else begin + end end else begin end end else begin @@ -6820,19 +7159,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) + litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -6841,16 +7174,28 @@ always @(*) begin 3'd6: begin end default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) + litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -6869,8 +7214,8 @@ always @(*) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin if (litedramcore_bankmachine6_source_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; end else begin + litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; end end else begin end @@ -6882,28 +7227,61 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) + litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine6_twtpcon_ready) begin + litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_valid <= 1'd0; + case (litedramcore_bankmachine6_state) 1'd1: begin if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine6_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine6_cmd_valid <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end 3'd6: begin end default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end @@ -6986,54 +7364,54 @@ assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_ assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we; assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr; always @(*) begin - litedramcore_litedramcore_bankmachine7_next_state <= 3'd0; - litedramcore_litedramcore_bankmachine7_next_state <= litedramcore_litedramcore_bankmachine7_state; - case (litedramcore_litedramcore_bankmachine7_state) + litedramcore_bankmachine7_next_state <= 3'd0; + litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state; + case (litedramcore_bankmachine7_state) 1'd1: begin if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin if (litedramcore_bankmachine7_cmd_ready) begin - litedramcore_litedramcore_bankmachine7_next_state <= 3'd5; + litedramcore_bankmachine7_next_state <= 3'd5; end end end 2'd2: begin if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_litedramcore_bankmachine7_next_state <= 3'd5; + litedramcore_bankmachine7_next_state <= 3'd5; end end 2'd3: begin if (litedramcore_bankmachine7_trccon_ready) begin if (litedramcore_bankmachine7_cmd_ready) begin - litedramcore_litedramcore_bankmachine7_next_state <= 3'd6; + litedramcore_bankmachine7_next_state <= 3'd6; end end end 3'd4: begin if ((~litedramcore_bankmachine7_refresh_req)) begin - litedramcore_litedramcore_bankmachine7_next_state <= 1'd0; + litedramcore_bankmachine7_next_state <= 1'd0; end end 3'd5: begin - litedramcore_litedramcore_bankmachine7_next_state <= 2'd3; + litedramcore_bankmachine7_next_state <= 2'd3; end 3'd6: begin - litedramcore_litedramcore_bankmachine7_next_state <= 1'd0; + litedramcore_bankmachine7_next_state <= 1'd0; end default: begin if (litedramcore_bankmachine7_refresh_req) begin - litedramcore_litedramcore_bankmachine7_next_state <= 3'd4; + litedramcore_bankmachine7_next_state <= 3'd4; end else begin if (litedramcore_bankmachine7_source_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin - litedramcore_litedramcore_bankmachine7_next_state <= 2'd2; + litedramcore_bankmachine7_next_state <= 2'd2; end end else begin - litedramcore_litedramcore_bankmachine7_next_state <= 1'd1; + litedramcore_bankmachine7_next_state <= 1'd1; end end else begin - litedramcore_litedramcore_bankmachine7_next_state <= 2'd3; + litedramcore_bankmachine7_next_state <= 2'd3; end end end @@ -7041,8 +7419,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) + litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -7050,28 +7428,40 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine7_twtpcon_ready) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd1; - end end 3'd5: begin end 3'd6: begin end default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine7_row_open <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) + litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_open <= 1'd1; + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -7085,19 +7475,16 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) + litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine7_state) 1'd1: begin if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -7111,7 +7498,10 @@ always @(*) begin if (litedramcore_bankmachine7_source_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -7122,18 +7512,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_row_close <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine7_state) 1'd1: begin - litedramcore_bankmachine7_row_close <= 1'd1; + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin - litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin - litedramcore_bankmachine7_row_close <= 1'd1; + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7144,16 +7538,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -7162,12 +7553,27 @@ always @(*) begin 3'd6: begin end default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + end else begin + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -7186,7 +7592,10 @@ always @(*) begin if (litedramcore_bankmachine7_source_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + end else begin + end end else begin end end else begin @@ -7197,19 +7606,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) + litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -7218,16 +7621,28 @@ always @(*) begin 3'd6: begin end default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) + litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -7246,8 +7661,8 @@ always @(*) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin if (litedramcore_bankmachine7_source_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end else begin + litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; end end else begin end @@ -7259,22 +7674,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) + litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - end + 2'd3: begin + end 3'd4: begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if (litedramcore_bankmachine7_twtpcon_ready) begin + litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -7285,13 +7696,16 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) + litedramcore_bankmachine7_row_open <= 1'd0; + case (litedramcore_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_open <= 1'd1; + end end 3'd4: begin end @@ -7300,32 +7714,23 @@ always @(*) begin 3'd6: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin - end else begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) + litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (litedramcore_bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -7339,10 +7744,7 @@ always @(*) begin if (litedramcore_bankmachine7_source_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; - end else begin - end + litedramcore_bankmachine7_cmd_valid <= 1'd1; end else begin end end else begin @@ -7353,47 +7755,38 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_req_wdata_ready <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) + litedramcore_bankmachine7_row_close <= 1'd0; + case (litedramcore_bankmachine7_state) 1'd1: begin + litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end 3'd6: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin - litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine7_req_rdata_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -7402,21 +7795,6 @@ always @(*) begin 3'd6: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin - end else begin - litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end @@ -7456,28 +7834,28 @@ always @(*) begin litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); end assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; -assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0; -assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1; -assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2; -assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; -assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; -assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; +assign litedramcore_choose_cmd_cmd_valid = rhs_self0; +assign litedramcore_choose_cmd_cmd_payload_a = rhs_self1; +assign litedramcore_choose_cmd_cmd_payload_ba = rhs_self2; +assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_self3; +assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_self4; +assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_self5; always @(*) begin litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; + litedramcore_choose_cmd_cmd_payload_cas <= t_self0; end end always @(*) begin litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; + litedramcore_choose_cmd_cmd_payload_ras <= t_self1; end end always @(*) begin litedramcore_choose_cmd_cmd_payload_we <= 1'd0; if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; + litedramcore_choose_cmd_cmd_payload_we <= t_self2; end end always @(*) begin @@ -7565,121 +7943,124 @@ always @(*) begin litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); end assign litedramcore_choose_req_request = litedramcore_choose_req_valids; -assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6; -assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7; -assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8; -assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9; -assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; -assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; +assign litedramcore_choose_req_cmd_valid = rhs_self6; +assign litedramcore_choose_req_cmd_payload_a = rhs_self7; +assign litedramcore_choose_req_cmd_payload_ba = rhs_self8; +assign litedramcore_choose_req_cmd_payload_is_read = rhs_self9; +assign litedramcore_choose_req_cmd_payload_is_write = rhs_self10; +assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_self11; always @(*) begin litedramcore_choose_req_cmd_payload_cas <= 1'd0; if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; + litedramcore_choose_req_cmd_payload_cas <= t_self3; end end always @(*) begin litedramcore_choose_req_cmd_payload_ras <= 1'd0; if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; + litedramcore_choose_req_cmd_payload_ras <= t_self4; end end always @(*) begin litedramcore_choose_req_cmd_payload_we <= 1'd0; if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; + litedramcore_choose_req_cmd_payload_we <= t_self5; end end assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); assign litedramcore_dfi_p0_reset_n = 1'd1; -assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}}; -assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}}; +assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer2}}; +assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer3}}; assign litedramcore_dfi_p1_reset_n = 1'd1; -assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}}; -assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}}; +assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer4}}; +assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer5}}; assign litedramcore_tfawcon_count = ((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]); always @(*) begin - litedramcore_litedramcore_multiplexer_next_state <= 4'd0; - litedramcore_litedramcore_multiplexer_next_state <= litedramcore_litedramcore_multiplexer_state; - case (litedramcore_litedramcore_multiplexer_state) + litedramcore_multiplexer_next_state <= 4'd0; + litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state; + case (litedramcore_multiplexer_state) 1'd1: begin if (litedramcore_read_available) begin if (((~litedramcore_write_available) | litedramcore_max_time1)) begin - litedramcore_litedramcore_multiplexer_next_state <= 2'd3; + litedramcore_multiplexer_next_state <= 2'd3; end end if (litedramcore_go_to_refresh) begin - litedramcore_litedramcore_multiplexer_next_state <= 2'd2; + litedramcore_multiplexer_next_state <= 2'd2; end end 2'd2: begin if (litedramcore_cmd_last) begin - litedramcore_litedramcore_multiplexer_next_state <= 1'd0; + litedramcore_multiplexer_next_state <= 1'd0; end end 2'd3: begin if (litedramcore_twtrcon_ready) begin - litedramcore_litedramcore_multiplexer_next_state <= 1'd0; + litedramcore_multiplexer_next_state <= 1'd0; end end 3'd4: begin - litedramcore_litedramcore_multiplexer_next_state <= 3'd5; + litedramcore_multiplexer_next_state <= 3'd5; end 3'd5: begin - litedramcore_litedramcore_multiplexer_next_state <= 3'd6; + litedramcore_multiplexer_next_state <= 3'd6; end 3'd6: begin - litedramcore_litedramcore_multiplexer_next_state <= 3'd7; + litedramcore_multiplexer_next_state <= 3'd7; end 3'd7: begin - litedramcore_litedramcore_multiplexer_next_state <= 4'd8; + litedramcore_multiplexer_next_state <= 4'd8; end 4'd8: begin - litedramcore_litedramcore_multiplexer_next_state <= 4'd9; + litedramcore_multiplexer_next_state <= 4'd9; end 4'd9: begin - litedramcore_litedramcore_multiplexer_next_state <= 4'd10; + litedramcore_multiplexer_next_state <= 4'd10; end 4'd10: begin - litedramcore_litedramcore_multiplexer_next_state <= 4'd11; + litedramcore_multiplexer_next_state <= 4'd11; end 4'd11: begin - litedramcore_litedramcore_multiplexer_next_state <= 4'd12; + litedramcore_multiplexer_next_state <= 4'd12; end 4'd12: begin - litedramcore_litedramcore_multiplexer_next_state <= 4'd13; + litedramcore_multiplexer_next_state <= 4'd13; end 4'd13: begin - litedramcore_litedramcore_multiplexer_next_state <= 4'd14; + litedramcore_multiplexer_next_state <= 4'd14; end 4'd14: begin - litedramcore_litedramcore_multiplexer_next_state <= 4'd15; + litedramcore_multiplexer_next_state <= 4'd15; end 4'd15: begin - litedramcore_litedramcore_multiplexer_next_state <= 1'd1; + litedramcore_multiplexer_next_state <= 1'd1; end default: begin if (litedramcore_write_available) begin if (((~litedramcore_read_available) | litedramcore_max_time0)) begin - litedramcore_litedramcore_multiplexer_next_state <= 3'd4; + litedramcore_multiplexer_next_state <= 3'd4; end end if (litedramcore_go_to_refresh) begin - litedramcore_litedramcore_multiplexer_next_state <= 2'd2; + litedramcore_multiplexer_next_state <= 2'd2; end end endcase end always @(*) begin - litedramcore_choose_req_cmd_ready <= 1'd0; - case (litedramcore_litedramcore_multiplexer_state) + litedramcore_steerer0 <= 2'd0; + case (litedramcore_multiplexer_state) 1'd1: begin + litedramcore_steerer0 <= 1'd0; if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + litedramcore_steerer0 <= 2'd2; + end + if (1'd1) begin + litedramcore_steerer0 <= 1'd1; end end 2'd2: begin + litedramcore_steerer0 <= 2'd3; end 2'd3: begin end @@ -7708,19 +8089,27 @@ always @(*) begin 4'd15: begin end default: begin + litedramcore_steerer0 <= 1'd0; + if (1'd1) begin + litedramcore_steerer0 <= 2'd2; + end if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + litedramcore_steerer0 <= 1'd1; end end endcase end always @(*) begin - litedramcore_en1 <= 1'd0; - case (litedramcore_litedramcore_multiplexer_state) + litedramcore_steerer1 <= 2'd0; + case (litedramcore_multiplexer_state) 1'd1: begin - litedramcore_en1 <= 1'd1; + litedramcore_steerer1 <= 1'd0; + if (1'd1) begin + litedramcore_steerer1 <= 2'd2; + end + if (1'd0) begin + litedramcore_steerer1 <= 1'd1; + end end 2'd2: begin end @@ -7751,23 +8140,26 @@ always @(*) begin 4'd15: begin end default: begin + litedramcore_steerer1 <= 1'd0; + if (1'd0) begin + litedramcore_steerer1 <= 2'd2; + end + if (1'd1) begin + litedramcore_steerer1 <= 1'd1; + end end endcase end always @(*) begin - litedramcore_steerer_sel0 <= 2'd0; - case (litedramcore_litedramcore_multiplexer_state) + litedramcore_choose_cmd_want_activates <= 1'd0; + case (litedramcore_multiplexer_state) 1'd1: begin - litedramcore_steerer_sel0 <= 1'd0; if (1'd0) begin - litedramcore_steerer_sel0 <= 2'd2; - end - if (1'd1) begin - litedramcore_steerer_sel0 <= 1'd1; + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; end end 2'd2: begin - litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end @@ -7796,29 +8188,20 @@ always @(*) begin 4'd15: begin end default: begin - litedramcore_steerer_sel0 <= 1'd0; - if (1'd1) begin - litedramcore_steerer_sel0 <= 2'd2; - end if (1'd0) begin - litedramcore_steerer_sel0 <= 1'd1; + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; end end endcase end always @(*) begin - litedramcore_steerer_sel1 <= 2'd0; - case (litedramcore_litedramcore_multiplexer_state) + litedramcore_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) 1'd1: begin - litedramcore_steerer_sel1 <= 1'd0; - if (1'd1) begin - litedramcore_steerer_sel1 <= 2'd2; - end - if (1'd0) begin - litedramcore_steerer_sel1 <= 1'd1; - end end 2'd2: begin + litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -7847,23 +8230,16 @@ always @(*) begin 4'd15: begin end default: begin - litedramcore_steerer_sel1 <= 1'd0; - if (1'd0) begin - litedramcore_steerer_sel1 <= 2'd2; - end - if (1'd1) begin - litedramcore_steerer_sel1 <= 1'd1; - end end endcase end always @(*) begin - litedramcore_choose_cmd_want_activates <= 1'd0; - case (litedramcore_litedramcore_multiplexer_state) + litedramcore_choose_cmd_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) 1'd1: begin if (1'd0) begin end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); end end 2'd2: begin @@ -7897,18 +8273,17 @@ always @(*) begin default: begin if (1'd0) begin end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); end end endcase end always @(*) begin - litedramcore_cmd_ready <= 1'd0; - case (litedramcore_litedramcore_multiplexer_state) + litedramcore_choose_req_want_reads <= 1'd0; + case (litedramcore_multiplexer_state) 1'd1: begin end 2'd2: begin - litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -7937,17 +8312,15 @@ always @(*) begin 4'd15: begin end default: begin + litedramcore_choose_req_want_reads <= 1'd1; end endcase end always @(*) begin - litedramcore_choose_cmd_cmd_ready <= 1'd0; - case (litedramcore_litedramcore_multiplexer_state) + litedramcore_choose_req_want_writes <= 1'd0; + case (litedramcore_multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end + litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -7978,16 +8351,12 @@ always @(*) begin 4'd15: begin end default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end end endcase end always @(*) begin - litedramcore_choose_req_want_reads <= 1'd0; - case (litedramcore_litedramcore_multiplexer_state) + litedramcore_en0 <= 1'd0; + case (litedramcore_multiplexer_state) 1'd1: begin end 2'd2: begin @@ -8019,15 +8388,19 @@ always @(*) begin 4'd15: begin end default: begin - litedramcore_choose_req_want_reads <= 1'd1; + litedramcore_en0 <= 1'd1; end endcase end always @(*) begin - litedramcore_choose_req_want_writes <= 1'd0; - case (litedramcore_litedramcore_multiplexer_state) + litedramcore_choose_req_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) 1'd1: begin - litedramcore_choose_req_want_writes <= 1'd1; + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end end 2'd2: begin end @@ -8058,13 +8431,19 @@ always @(*) begin 4'd15: begin end default: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end end endcase end always @(*) begin - litedramcore_en0 <= 1'd0; - case (litedramcore_litedramcore_multiplexer_state) + litedramcore_en1 <= 1'd0; + case (litedramcore_multiplexer_state) 1'd1: begin + litedramcore_en1 <= 1'd1; end 2'd2: begin end @@ -8095,56 +8474,55 @@ always @(*) begin 4'd15: begin end default: begin - litedramcore_en0 <= 1'd1; end endcase end -assign litedramcore_litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock)); -assign litedramcore_interface_bank0_addr = rhs_array_muxed12; -assign litedramcore_interface_bank0_we = rhs_array_muxed13; -assign litedramcore_interface_bank0_valid = rhs_array_muxed14; -assign litedramcore_litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock)); -assign litedramcore_interface_bank1_addr = rhs_array_muxed15; -assign litedramcore_interface_bank1_we = rhs_array_muxed16; -assign litedramcore_interface_bank1_valid = rhs_array_muxed17; -assign litedramcore_litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock)); -assign litedramcore_interface_bank2_addr = rhs_array_muxed18; -assign litedramcore_interface_bank2_we = rhs_array_muxed19; -assign litedramcore_interface_bank2_valid = rhs_array_muxed20; -assign litedramcore_litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock)); -assign litedramcore_interface_bank3_addr = rhs_array_muxed21; -assign litedramcore_interface_bank3_we = rhs_array_muxed22; -assign litedramcore_interface_bank3_valid = rhs_array_muxed23; -assign litedramcore_litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock)); -assign litedramcore_interface_bank4_addr = rhs_array_muxed24; -assign litedramcore_interface_bank4_we = rhs_array_muxed25; -assign litedramcore_interface_bank4_valid = rhs_array_muxed26; -assign litedramcore_litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock)); -assign litedramcore_interface_bank5_addr = rhs_array_muxed27; -assign litedramcore_interface_bank5_we = rhs_array_muxed28; -assign litedramcore_interface_bank5_valid = rhs_array_muxed29; -assign litedramcore_litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock)); -assign litedramcore_interface_bank6_addr = rhs_array_muxed30; -assign litedramcore_interface_bank6_we = rhs_array_muxed31; -assign litedramcore_interface_bank6_valid = rhs_array_muxed32; -assign litedramcore_litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock)); -assign litedramcore_interface_bank7_addr = rhs_array_muxed33; -assign litedramcore_interface_bank7_we = rhs_array_muxed34; -assign litedramcore_interface_bank7_valid = rhs_array_muxed35; -assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready)); -assign user_port_wdata_ready = litedramcore_litedramcore_new_master_wdata_ready3; -assign user_port_rdata_valid = litedramcore_litedramcore_new_master_rdata_valid13; +assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock)); +assign litedramcore_interface_bank0_addr = rhs_self12; +assign litedramcore_interface_bank0_we = rhs_self13; +assign litedramcore_interface_bank0_valid = rhs_self14; +assign litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock)); +assign litedramcore_interface_bank1_addr = rhs_self15; +assign litedramcore_interface_bank1_we = rhs_self16; +assign litedramcore_interface_bank1_valid = rhs_self17; +assign litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock)); +assign litedramcore_interface_bank2_addr = rhs_self18; +assign litedramcore_interface_bank2_we = rhs_self19; +assign litedramcore_interface_bank2_valid = rhs_self20; +assign litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock)); +assign litedramcore_interface_bank3_addr = rhs_self21; +assign litedramcore_interface_bank3_we = rhs_self22; +assign litedramcore_interface_bank3_valid = rhs_self23; +assign litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock)); +assign litedramcore_interface_bank4_addr = rhs_self24; +assign litedramcore_interface_bank4_we = rhs_self25; +assign litedramcore_interface_bank4_valid = rhs_self26; +assign litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock)); +assign litedramcore_interface_bank5_addr = rhs_self27; +assign litedramcore_interface_bank5_we = rhs_self28; +assign litedramcore_interface_bank5_valid = rhs_self29; +assign litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock)); +assign litedramcore_interface_bank6_addr = rhs_self30; +assign litedramcore_interface_bank6_we = rhs_self31; +assign litedramcore_interface_bank6_valid = rhs_self32; +assign litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)}; +assign litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock)); +assign litedramcore_interface_bank7_addr = rhs_self33; +assign litedramcore_interface_bank7_we = rhs_self34; +assign litedramcore_interface_bank7_valid = rhs_self35; +assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready)); +assign user_port_wdata_ready = litedramcore_new_master_wdata_ready3; +assign user_port_rdata_valid = litedramcore_new_master_rdata_valid13; always @(*) begin litedramcore_interface_wdata <= 128'd0; - case ({litedramcore_litedramcore_new_master_wdata_ready3}) + case ({litedramcore_new_master_wdata_ready3}) 1'd1: begin litedramcore_interface_wdata <= user_port_wdata_payload_data; end @@ -8155,7 +8533,7 @@ always @(*) begin end always @(*) begin litedramcore_interface_wdata_we <= 16'd0; - case ({litedramcore_litedramcore_new_master_wdata_ready3}) + case ({litedramcore_new_master_wdata_ready3}) 1'd1: begin litedramcore_interface_wdata_we <= user_port_wdata_payload_we; end @@ -8165,175 +8543,164 @@ always @(*) begin endcase end assign user_port_rdata_payload_data = litedramcore_interface_rdata; -assign litedramcore_litedramcore_roundrobin0_grant = 1'd0; -assign litedramcore_litedramcore_roundrobin1_grant = 1'd0; -assign litedramcore_litedramcore_roundrobin2_grant = 1'd0; -assign litedramcore_litedramcore_roundrobin3_grant = 1'd0; -assign litedramcore_litedramcore_roundrobin4_grant = 1'd0; -assign litedramcore_litedramcore_roundrobin5_grant = 1'd0; -assign litedramcore_litedramcore_roundrobin6_grant = 1'd0; -assign litedramcore_litedramcore_roundrobin7_grant = 1'd0; +assign litedramcore_roundrobin0_grant = 1'd0; +assign litedramcore_roundrobin1_grant = 1'd0; +assign litedramcore_roundrobin2_grant = 1'd0; +assign litedramcore_roundrobin3_grant = 1'd0; +assign litedramcore_roundrobin4_grant = 1'd0; +assign litedramcore_roundrobin5_grant = 1'd0; +assign litedramcore_roundrobin6_grant = 1'd0; +assign litedramcore_roundrobin7_grant = 1'd0; always @(*) begin - litedramcore_next_state <= 2'd0; - litedramcore_next_state <= litedramcore_state; - case (litedramcore_state) + next_state <= 2'd0; + next_state <= state; + case (state) 1'd1: begin - litedramcore_next_state <= 2'd2; + next_state <= 2'd2; end 2'd2: begin - litedramcore_next_state <= 1'd0; + next_state <= 1'd0; end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_next_state <= 1'd1; + if ((interface0_cyc & interface0_stb)) begin + next_state <= 1'd1; end end endcase end always @(*) begin - litedramcore_adr_next_value1 <= 14'd0; - case (litedramcore_state) + interface0_ack <= 1'd0; + case (state) 1'd1: begin - litedramcore_adr_next_value1 <= 1'd0; end 2'd2: begin + interface0_ack <= 1'd1; end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value1 <= litedramcore_wishbone_adr; - end end endcase end always @(*) begin - litedramcore_adr_next_value_ce1 <= 1'd0; - case (litedramcore_state) + interface0_dat_r <= 32'd0; + case (state) 1'd1: begin - litedramcore_adr_next_value_ce1 <= 1'd1; end 2'd2: begin + interface0_dat_r <= interface1_dat_r; end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value_ce1 <= 1'd1; - end end endcase end always @(*) begin - litedramcore_we_next_value2 <= 1'd0; - case (litedramcore_state) + interface1_dat_w_next_value0 <= 32'd0; + case (state) 1'd1: begin - litedramcore_we_next_value2 <= 1'd0; end 2'd2: begin end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); - end + interface1_dat_w_next_value0 <= interface0_dat_w; end endcase end always @(*) begin - litedramcore_we_next_value_ce2 <= 1'd0; - case (litedramcore_state) + interface1_dat_w_next_value_ce0 <= 1'd0; + case (state) 1'd1: begin - litedramcore_we_next_value_ce2 <= 1'd1; end 2'd2: begin end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value_ce2 <= 1'd1; - end + interface1_dat_w_next_value_ce0 <= 1'd1; end endcase end always @(*) begin - litedramcore_wishbone_dat_r <= 32'd0; - case (litedramcore_state) + interface1_adr_next_value1 <= 14'd0; + case (state) 1'd1: begin + interface1_adr_next_value1 <= 1'd0; end 2'd2: begin - litedramcore_wishbone_dat_r <= litedramcore_dat_r; end default: begin + if ((interface0_cyc & interface0_stb)) begin + interface1_adr_next_value1 <= interface0_adr[29:0]; + end end endcase end always @(*) begin - litedramcore_wishbone_ack <= 1'd0; - case (litedramcore_state) + interface1_adr_next_value_ce1 <= 1'd0; + case (state) 1'd1: begin + interface1_adr_next_value_ce1 <= 1'd1; end 2'd2: begin - litedramcore_wishbone_ack <= 1'd1; end default: begin + if ((interface0_cyc & interface0_stb)) begin + interface1_adr_next_value_ce1 <= 1'd1; + end end endcase end always @(*) begin - litedramcore_dat_w_next_value0 <= 32'd0; - case (litedramcore_state) + interface1_we_next_value2 <= 1'd0; + case (state) 1'd1: begin + interface1_we_next_value2 <= 1'd0; end 2'd2: begin end default: begin - litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w; + if ((interface0_cyc & interface0_stb)) begin + interface1_we_next_value2 <= (interface0_we & (interface0_sel != 1'd0)); + end end endcase end always @(*) begin - litedramcore_dat_w_next_value_ce0 <= 1'd0; - case (litedramcore_state) + interface1_we_next_value_ce2 <= 1'd0; + case (state) 1'd1: begin + interface1_we_next_value_ce2 <= 1'd1; end 2'd2: begin end default: begin - litedramcore_dat_w_next_value_ce0 <= 1'd1; + if ((interface0_cyc & interface0_stb)) begin + interface1_we_next_value_ce2 <= 1'd1; + end end endcase end -assign litedramcore_wishbone_adr = wb_bus_adr; -assign litedramcore_wishbone_dat_w = wb_bus_dat_w; -assign wb_bus_dat_r = litedramcore_wishbone_dat_r; -assign litedramcore_wishbone_sel = wb_bus_sel; -assign litedramcore_wishbone_cyc = wb_bus_cyc; -assign litedramcore_wishbone_stb = wb_bus_stb; -assign wb_bus_ack = litedramcore_wishbone_ack; -assign litedramcore_wishbone_we = wb_bus_we; -assign litedramcore_wishbone_cti = wb_bus_cti; -assign litedramcore_wishbone_bte = wb_bus_bte; -assign wb_bus_err = litedramcore_wishbone_err; assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_done0_we <= 1'd0; + csrbank0_init_done0_re <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_we <= (~interface0_bank_bus_we); + csrbank0_init_done0_re <= interface0_bank_bus_we; end end always @(*) begin - csrbank0_init_done0_re <= 1'd0; + csrbank0_init_done0_we <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_re <= interface0_bank_bus_we; + csrbank0_init_done0_we <= (~interface0_bank_bus_we); end end assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_error0_re <= 1'd0; + csrbank0_init_error0_we <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_re <= interface0_bank_bus_we; + csrbank0_init_error0_we <= (~interface0_bank_bus_we); end end always @(*) begin - csrbank0_init_error0_we <= 1'd0; + csrbank0_init_error0_re <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_we <= (~interface0_bank_bus_we); + csrbank0_init_error0_re <= interface0_bank_bus_we; end end assign csrbank0_init_done0_w = init_done_storage; @@ -8341,15 +8708,15 @@ assign csrbank0_init_error0_w = init_error_storage; assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_dly_sel0_re <= 1'd0; + csrbank1_dly_sel0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_dly_sel0_re <= interface1_bank_bus_we; + csrbank1_dly_sel0_we <= (~interface1_bank_bus_we); end end always @(*) begin - csrbank1_dly_sel0_we <= 1'd0; + csrbank1_dly_sel0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_dly_sel0_we <= (~interface1_bank_bus_we); + csrbank1_dly_sel0_re <= interface1_bank_bus_we; end end assign ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; @@ -8419,15 +8786,15 @@ always @(*) begin end assign csrbank1_burstdet_seen_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_burstdet_seen_we <= 1'd0; + csrbank1_burstdet_seen_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - csrbank1_burstdet_seen_we <= (~interface1_bank_bus_we); + csrbank1_burstdet_seen_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_burstdet_seen_re <= 1'd0; + csrbank1_burstdet_seen_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - csrbank1_burstdet_seen_re <= interface1_bank_bus_we; + csrbank1_burstdet_seen_we <= (~interface1_bank_bus_we); end end assign csrbank1_dly_sel0_w = ddrphy_dly_sel_storage[1:0]; @@ -8436,28 +8803,28 @@ assign ddrphy_burstdet_seen_we = csrbank1_burstdet_seen_we; assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; always @(*) begin - csrbank2_dfii_control0_we <= 1'd0; + csrbank2_dfii_control0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_control0_re <= interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_control0_re <= 1'd0; + csrbank2_dfii_control0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_re <= interface2_bank_bus_we; + csrbank2_dfii_control0_we <= (~interface2_bank_bus_we); end end -assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; +assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi0_command0_re <= 1'd0; + csrbank2_dfii_pi0_command0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; + csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi0_command0_we <= 1'd0; + csrbank2_dfii_pi0_command0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; end end assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; @@ -8475,93 +8842,93 @@ always @(*) begin end assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0]; always @(*) begin - csrbank2_dfii_pi0_address0_we <= 1'd0; + csrbank2_dfii_pi0_address0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi0_address0_re <= 1'd0; + csrbank2_dfii_pi0_address0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; + csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we); end end assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi0_baddress0_we <= 1'd0; + csrbank2_dfii_pi0_baddress0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi0_baddress0_re <= 1'd0; + csrbank2_dfii_pi0_baddress0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we; + csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we); end end assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_wrdata1_re <= 1'd0; + csrbank2_dfii_pi0_wrdata1_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we; + csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi0_wrdata1_we <= 1'd0; + csrbank2_dfii_pi0_wrdata1_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we; end end assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_wrdata0_we <= 1'd0; + csrbank2_dfii_pi0_wrdata0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi0_wrdata0_re <= 1'd0; + csrbank2_dfii_pi0_wrdata0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; + csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we); end end assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_rddata1_re <= 1'd0; + csrbank2_dfii_pi0_rddata1_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we; + csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi0_rddata1_we <= 1'd0; + csrbank2_dfii_pi0_rddata1_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we; end end assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_rddata0_re <= 1'd0; + csrbank2_dfii_pi0_rddata0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - csrbank2_dfii_pi0_rddata0_re <= interface2_bank_bus_we; + csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi0_rddata0_we <= 1'd0; + csrbank2_dfii_pi0_rddata0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi0_rddata0_re <= interface2_bank_bus_we; end end -assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; +assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi1_command0_we <= 1'd0; + csrbank2_dfii_pi1_command0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi1_command0_re <= 1'd0; + csrbank2_dfii_pi1_command0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; + csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we); end end assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; @@ -8579,80 +8946,80 @@ always @(*) begin end assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0]; always @(*) begin - csrbank2_dfii_pi1_address0_we <= 1'd0; + csrbank2_dfii_pi1_address0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi1_address0_re <= 1'd0; + csrbank2_dfii_pi1_address0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we; + csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we); end end assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi1_baddress0_re <= 1'd0; + csrbank2_dfii_pi1_baddress0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we; + csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi1_baddress0_we <= 1'd0; + csrbank2_dfii_pi1_baddress0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we; end end assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_wrdata1_we <= 1'd0; + csrbank2_dfii_pi1_wrdata1_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi1_wrdata1_re <= 1'd0; + csrbank2_dfii_pi1_wrdata1_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we; + csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we); end end assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_wrdata0_re <= 1'd0; + csrbank2_dfii_pi1_wrdata0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; + csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi1_wrdata0_we <= 1'd0; + csrbank2_dfii_pi1_wrdata0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; end end assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_rddata1_re <= 1'd0; + csrbank2_dfii_pi1_rddata1_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we; + csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi1_rddata1_we <= 1'd0; + csrbank2_dfii_pi1_rddata1_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we; end end assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_rddata0_we <= 1'd0; + csrbank2_dfii_pi1_rddata0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi1_rddata0_re <= 1'd0; + csrbank2_dfii_pi1_rddata0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we; + csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we); end end assign litedramcore_sel = litedramcore_storage[0]; @@ -8666,7 +9033,9 @@ assign litedramcore_phaseinjector0_csrfield_cas = litedramcore_phaseinjector0_co assign litedramcore_phaseinjector0_csrfield_ras = litedramcore_phaseinjector0_command_storage[3]; assign litedramcore_phaseinjector0_csrfield_wren = litedramcore_phaseinjector0_command_storage[4]; assign litedramcore_phaseinjector0_csrfield_rden = litedramcore_phaseinjector0_command_storage[5]; -assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; +assign litedramcore_phaseinjector0_csrfield_cs_top = litedramcore_phaseinjector0_command_storage[6]; +assign litedramcore_phaseinjector0_csrfield_cs_bottom = litedramcore_phaseinjector0_command_storage[7]; +assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[7:0]; assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0]; assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0]; assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[63:32]; @@ -8680,7 +9049,9 @@ assign litedramcore_phaseinjector1_csrfield_cas = litedramcore_phaseinjector1_co assign litedramcore_phaseinjector1_csrfield_ras = litedramcore_phaseinjector1_command_storage[3]; assign litedramcore_phaseinjector1_csrfield_wren = litedramcore_phaseinjector1_command_storage[4]; assign litedramcore_phaseinjector1_csrfield_rden = litedramcore_phaseinjector1_command_storage[5]; -assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0]; +assign litedramcore_phaseinjector1_csrfield_cs_top = litedramcore_phaseinjector1_command_storage[6]; +assign litedramcore_phaseinjector1_csrfield_cs_bottom = litedramcore_phaseinjector1_command_storage[7]; +assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[7:0]; assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[14:0]; assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0]; assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[63:32]; @@ -8688,973 +9059,973 @@ assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[ assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_rddata_status[63:32]; assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_rddata_status[31:0]; assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata0_we; -assign csr_interconnect_adr = litedramcore_adr; -assign csr_interconnect_we = litedramcore_we; -assign csr_interconnect_dat_w = litedramcore_dat_w; -assign litedramcore_dat_r = csr_interconnect_dat_r; -assign interface0_bank_bus_adr = csr_interconnect_adr; -assign interface1_bank_bus_adr = csr_interconnect_adr; -assign interface2_bank_bus_adr = csr_interconnect_adr; -assign interface0_bank_bus_we = csr_interconnect_we; -assign interface1_bank_bus_we = csr_interconnect_we; -assign interface2_bank_bus_we = csr_interconnect_we; -assign interface0_bank_bus_dat_w = csr_interconnect_dat_w; -assign interface1_bank_bus_dat_w = csr_interconnect_dat_w; -assign interface2_bank_bus_dat_w = csr_interconnect_dat_w; -assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); -always @(*) begin - rhs_array_muxed0 <= 1'd0; +assign adr = interface1_adr; +assign we = interface1_we; +assign dat_w = interface1_dat_w; +assign interface1_dat_r = dat_r; +assign interface0_bank_bus_adr = adr; +assign interface1_bank_bus_adr = adr; +assign interface2_bank_bus_adr = adr; +assign interface0_bank_bus_we = we; +assign interface1_bank_bus_we = we; +assign interface2_bank_bus_we = we; +assign interface0_bank_bus_dat_w = dat_w; +assign interface1_bank_bus_dat_w = dat_w; +assign interface2_bank_bus_dat_w = dat_w; +assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); +always @(*) begin + rhs_self0 <= 1'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0]; + rhs_self0 <= litedramcore_choose_cmd_valids[0]; end 1'd1: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1]; + rhs_self0 <= litedramcore_choose_cmd_valids[1]; end 2'd2: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2]; + rhs_self0 <= litedramcore_choose_cmd_valids[2]; end 2'd3: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3]; + rhs_self0 <= litedramcore_choose_cmd_valids[3]; end 3'd4: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4]; + rhs_self0 <= litedramcore_choose_cmd_valids[4]; end 3'd5: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5]; + rhs_self0 <= litedramcore_choose_cmd_valids[5]; end 3'd6: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6]; + rhs_self0 <= litedramcore_choose_cmd_valids[6]; end default: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7]; + rhs_self0 <= litedramcore_choose_cmd_valids[7]; end endcase end always @(*) begin - rhs_array_muxed1 <= 15'd0; + rhs_self1 <= 15'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a; + rhs_self1 <= litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a; + rhs_self1 <= litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a; + rhs_self1 <= litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a; + rhs_self1 <= litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a; + rhs_self1 <= litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a; + rhs_self1 <= litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a; + rhs_self1 <= litedramcore_bankmachine6_cmd_payload_a; end default: begin - rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a; + rhs_self1 <= litedramcore_bankmachine7_cmd_payload_a; end endcase end always @(*) begin - rhs_array_muxed2 <= 3'd0; + rhs_self2 <= 3'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba; + rhs_self2 <= litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba; + rhs_self2 <= litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba; + rhs_self2 <= litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba; + rhs_self2 <= litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba; + rhs_self2 <= litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba; + rhs_self2 <= litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba; + rhs_self2 <= litedramcore_bankmachine6_cmd_payload_ba; end default: begin - rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba; + rhs_self2 <= litedramcore_bankmachine7_cmd_payload_ba; end endcase end always @(*) begin - rhs_array_muxed3 <= 1'd0; + rhs_self3 <= 1'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read; + rhs_self3 <= litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read; + rhs_self3 <= litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read; + rhs_self3 <= litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read; + rhs_self3 <= litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read; + rhs_self3 <= litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read; + rhs_self3 <= litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read; + rhs_self3 <= litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read; + rhs_self3 <= litedramcore_bankmachine7_cmd_payload_is_read; end endcase end always @(*) begin - rhs_array_muxed4 <= 1'd0; + rhs_self4 <= 1'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write; + rhs_self4 <= litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write; + rhs_self4 <= litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write; + rhs_self4 <= litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write; + rhs_self4 <= litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write; + rhs_self4 <= litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write; + rhs_self4 <= litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write; + rhs_self4 <= litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write; + rhs_self4 <= litedramcore_bankmachine7_cmd_payload_is_write; end endcase end always @(*) begin - rhs_array_muxed5 <= 1'd0; + rhs_self5 <= 1'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + rhs_self5 <= litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + rhs_self5 <= litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + rhs_self5 <= litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + rhs_self5 <= litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + rhs_self5 <= litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + rhs_self5 <= litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + rhs_self5 <= litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + rhs_self5 <= litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase end always @(*) begin - t_array_muxed0 <= 1'd0; + t_self0 <= 1'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas; + t_self0 <= litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas; + t_self0 <= litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas; + t_self0 <= litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas; + t_self0 <= litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas; + t_self0 <= litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas; + t_self0 <= litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas; + t_self0 <= litedramcore_bankmachine6_cmd_payload_cas; end default: begin - t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas; + t_self0 <= litedramcore_bankmachine7_cmd_payload_cas; end endcase end always @(*) begin - t_array_muxed1 <= 1'd0; + t_self1 <= 1'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras; + t_self1 <= litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras; + t_self1 <= litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras; + t_self1 <= litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras; + t_self1 <= litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras; + t_self1 <= litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras; + t_self1 <= litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras; + t_self1 <= litedramcore_bankmachine6_cmd_payload_ras; end default: begin - t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras; + t_self1 <= litedramcore_bankmachine7_cmd_payload_ras; end endcase end always @(*) begin - t_array_muxed2 <= 1'd0; + t_self2 <= 1'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we; + t_self2 <= litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we; + t_self2 <= litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we; + t_self2 <= litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we; + t_self2 <= litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we; + t_self2 <= litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we; + t_self2 <= litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we; + t_self2 <= litedramcore_bankmachine6_cmd_payload_we; end default: begin - t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we; + t_self2 <= litedramcore_bankmachine7_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed6 <= 1'd0; + rhs_self6 <= 1'd0; case (litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[0]; + rhs_self6 <= litedramcore_choose_req_valids[0]; end 1'd1: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[1]; + rhs_self6 <= litedramcore_choose_req_valids[1]; end 2'd2: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[2]; + rhs_self6 <= litedramcore_choose_req_valids[2]; end 2'd3: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[3]; + rhs_self6 <= litedramcore_choose_req_valids[3]; end 3'd4: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[4]; + rhs_self6 <= litedramcore_choose_req_valids[4]; end 3'd5: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[5]; + rhs_self6 <= litedramcore_choose_req_valids[5]; end 3'd6: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[6]; + rhs_self6 <= litedramcore_choose_req_valids[6]; end default: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[7]; + rhs_self6 <= litedramcore_choose_req_valids[7]; end endcase end always @(*) begin - rhs_array_muxed7 <= 15'd0; + rhs_self7 <= 15'd0; case (litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a; + rhs_self7 <= litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a; + rhs_self7 <= litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a; + rhs_self7 <= litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a; + rhs_self7 <= litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a; + rhs_self7 <= litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a; + rhs_self7 <= litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a; + rhs_self7 <= litedramcore_bankmachine6_cmd_payload_a; end default: begin - rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a; + rhs_self7 <= litedramcore_bankmachine7_cmd_payload_a; end endcase end always @(*) begin - rhs_array_muxed8 <= 3'd0; + rhs_self8 <= 3'd0; case (litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba; + rhs_self8 <= litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba; + rhs_self8 <= litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba; + rhs_self8 <= litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba; + rhs_self8 <= litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba; + rhs_self8 <= litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba; + rhs_self8 <= litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba; + rhs_self8 <= litedramcore_bankmachine6_cmd_payload_ba; end default: begin - rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba; + rhs_self8 <= litedramcore_bankmachine7_cmd_payload_ba; end endcase end always @(*) begin - rhs_array_muxed9 <= 1'd0; + rhs_self9 <= 1'd0; case (litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read; + rhs_self9 <= litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read; + rhs_self9 <= litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read; + rhs_self9 <= litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read; + rhs_self9 <= litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read; + rhs_self9 <= litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read; + rhs_self9 <= litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read; + rhs_self9 <= litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read; + rhs_self9 <= litedramcore_bankmachine7_cmd_payload_is_read; end endcase end always @(*) begin - rhs_array_muxed10 <= 1'd0; + rhs_self10 <= 1'd0; case (litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write; + rhs_self10 <= litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write; + rhs_self10 <= litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write; + rhs_self10 <= litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write; + rhs_self10 <= litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write; + rhs_self10 <= litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write; + rhs_self10 <= litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write; + rhs_self10 <= litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write; + rhs_self10 <= litedramcore_bankmachine7_cmd_payload_is_write; end endcase end always @(*) begin - rhs_array_muxed11 <= 1'd0; + rhs_self11 <= 1'd0; case (litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + rhs_self11 <= litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + rhs_self11 <= litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + rhs_self11 <= litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + rhs_self11 <= litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + rhs_self11 <= litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + rhs_self11 <= litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + rhs_self11 <= litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + rhs_self11 <= litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase end always @(*) begin - t_array_muxed3 <= 1'd0; + t_self3 <= 1'd0; case (litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas; + t_self3 <= litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas; + t_self3 <= litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas; + t_self3 <= litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas; + t_self3 <= litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas; + t_self3 <= litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas; + t_self3 <= litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas; + t_self3 <= litedramcore_bankmachine6_cmd_payload_cas; end default: begin - t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas; + t_self3 <= litedramcore_bankmachine7_cmd_payload_cas; end endcase end always @(*) begin - t_array_muxed4 <= 1'd0; + t_self4 <= 1'd0; case (litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras; + t_self4 <= litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras; + t_self4 <= litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras; + t_self4 <= litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras; + t_self4 <= litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras; + t_self4 <= litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras; + t_self4 <= litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras; + t_self4 <= litedramcore_bankmachine6_cmd_payload_ras; end default: begin - t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras; + t_self4 <= litedramcore_bankmachine7_cmd_payload_ras; end endcase end always @(*) begin - t_array_muxed5 <= 1'd0; + t_self5 <= 1'd0; case (litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we; + t_self5 <= litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we; + t_self5 <= litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we; + t_self5 <= litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we; + t_self5 <= litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we; + t_self5 <= litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we; + t_self5 <= litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we; + t_self5 <= litedramcore_bankmachine6_cmd_payload_we; end default: begin - t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we; + t_self5 <= litedramcore_bankmachine7_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed12 <= 22'd0; - case (litedramcore_litedramcore_roundrobin0_grant) + rhs_self12 <= 22'd0; + case (litedramcore_roundrobin0_grant) default: begin - rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + rhs_self12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed13 <= 1'd0; - case (litedramcore_litedramcore_roundrobin0_grant) + rhs_self13 <= 1'd0; + case (litedramcore_roundrobin0_grant) default: begin - rhs_array_muxed13 <= user_port_cmd_payload_we; + rhs_self13 <= user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed14 <= 1'd0; - case (litedramcore_litedramcore_roundrobin0_grant) + rhs_self14 <= 1'd0; + case (litedramcore_roundrobin0_grant) default: begin - rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + rhs_self14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed15 <= 22'd0; - case (litedramcore_litedramcore_roundrobin1_grant) + rhs_self15 <= 22'd0; + case (litedramcore_roundrobin1_grant) default: begin - rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + rhs_self15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed16 <= 1'd0; - case (litedramcore_litedramcore_roundrobin1_grant) + rhs_self16 <= 1'd0; + case (litedramcore_roundrobin1_grant) default: begin - rhs_array_muxed16 <= user_port_cmd_payload_we; + rhs_self16 <= user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed17 <= 1'd0; - case (litedramcore_litedramcore_roundrobin1_grant) + rhs_self17 <= 1'd0; + case (litedramcore_roundrobin1_grant) default: begin - rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + rhs_self17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed18 <= 22'd0; - case (litedramcore_litedramcore_roundrobin2_grant) + rhs_self18 <= 22'd0; + case (litedramcore_roundrobin2_grant) default: begin - rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + rhs_self18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed19 <= 1'd0; - case (litedramcore_litedramcore_roundrobin2_grant) + rhs_self19 <= 1'd0; + case (litedramcore_roundrobin2_grant) default: begin - rhs_array_muxed19 <= user_port_cmd_payload_we; + rhs_self19 <= user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed20 <= 1'd0; - case (litedramcore_litedramcore_roundrobin2_grant) + rhs_self20 <= 1'd0; + case (litedramcore_roundrobin2_grant) default: begin - rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + rhs_self20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed21 <= 22'd0; - case (litedramcore_litedramcore_roundrobin3_grant) + rhs_self21 <= 22'd0; + case (litedramcore_roundrobin3_grant) default: begin - rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + rhs_self21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed22 <= 1'd0; - case (litedramcore_litedramcore_roundrobin3_grant) + rhs_self22 <= 1'd0; + case (litedramcore_roundrobin3_grant) default: begin - rhs_array_muxed22 <= user_port_cmd_payload_we; + rhs_self22 <= user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed23 <= 1'd0; - case (litedramcore_litedramcore_roundrobin3_grant) + rhs_self23 <= 1'd0; + case (litedramcore_roundrobin3_grant) default: begin - rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + rhs_self23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed24 <= 22'd0; - case (litedramcore_litedramcore_roundrobin4_grant) + rhs_self24 <= 22'd0; + case (litedramcore_roundrobin4_grant) default: begin - rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + rhs_self24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed25 <= 1'd0; - case (litedramcore_litedramcore_roundrobin4_grant) + rhs_self25 <= 1'd0; + case (litedramcore_roundrobin4_grant) default: begin - rhs_array_muxed25 <= user_port_cmd_payload_we; + rhs_self25 <= user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed26 <= 1'd0; - case (litedramcore_litedramcore_roundrobin4_grant) + rhs_self26 <= 1'd0; + case (litedramcore_roundrobin4_grant) default: begin - rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + rhs_self26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed27 <= 22'd0; - case (litedramcore_litedramcore_roundrobin5_grant) + rhs_self27 <= 22'd0; + case (litedramcore_roundrobin5_grant) default: begin - rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + rhs_self27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed28 <= 1'd0; - case (litedramcore_litedramcore_roundrobin5_grant) + rhs_self28 <= 1'd0; + case (litedramcore_roundrobin5_grant) default: begin - rhs_array_muxed28 <= user_port_cmd_payload_we; + rhs_self28 <= user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed29 <= 1'd0; - case (litedramcore_litedramcore_roundrobin5_grant) + rhs_self29 <= 1'd0; + case (litedramcore_roundrobin5_grant) default: begin - rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + rhs_self29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed30 <= 22'd0; - case (litedramcore_litedramcore_roundrobin6_grant) + rhs_self30 <= 22'd0; + case (litedramcore_roundrobin6_grant) default: begin - rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + rhs_self30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed31 <= 1'd0; - case (litedramcore_litedramcore_roundrobin6_grant) + rhs_self31 <= 1'd0; + case (litedramcore_roundrobin6_grant) default: begin - rhs_array_muxed31 <= user_port_cmd_payload_we; + rhs_self31 <= user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed32 <= 1'd0; - case (litedramcore_litedramcore_roundrobin6_grant) + rhs_self32 <= 1'd0; + case (litedramcore_roundrobin6_grant) default: begin - rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + rhs_self32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed33 <= 22'd0; - case (litedramcore_litedramcore_roundrobin7_grant) + rhs_self33 <= 22'd0; + case (litedramcore_roundrobin7_grant) default: begin - rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + rhs_self33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed34 <= 1'd0; - case (litedramcore_litedramcore_roundrobin7_grant) + rhs_self34 <= 1'd0; + case (litedramcore_roundrobin7_grant) default: begin - rhs_array_muxed34 <= user_port_cmd_payload_we; + rhs_self34 <= user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed35 <= 1'd0; - case (litedramcore_litedramcore_roundrobin7_grant) + rhs_self35 <= 1'd0; + case (litedramcore_roundrobin7_grant) default: begin - rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); + rhs_self35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); end endcase end always @(*) begin - array_muxed0 <= 3'd0; - case (litedramcore_steerer_sel0) + self0 <= 3'd0; + case (litedramcore_steerer0) 1'd0: begin - array_muxed0 <= litedramcore_nop_ba[2:0]; + self0 <= litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + self0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + self0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed0 <= litedramcore_cmd_payload_ba[2:0]; + self0 <= litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed1 <= 15'd0; - case (litedramcore_steerer_sel0) + self1 <= 15'd0; + case (litedramcore_steerer0) 1'd0: begin - array_muxed1 <= litedramcore_nop_a; + self1 <= litedramcore_nop_a; end 1'd1: begin - array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a; + self1 <= litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed1 <= litedramcore_choose_req_cmd_payload_a; + self1 <= litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed1 <= litedramcore_cmd_payload_a; + self1 <= litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed2 <= 1'd0; - case (litedramcore_steerer_sel0) + self2 <= 1'd0; + case (litedramcore_steerer0) 1'd0: begin - array_muxed2 <= 1'd0; + self2 <= 1'd0; end 1'd1: begin - array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + self2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + self2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + self2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed3 <= 1'd0; - case (litedramcore_steerer_sel0) + self3 <= 1'd0; + case (litedramcore_steerer0) 1'd0: begin - array_muxed3 <= 1'd0; + self3 <= 1'd0; end 1'd1: begin - array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + self3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + self3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + self3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed4 <= 1'd0; - case (litedramcore_steerer_sel0) + self4 <= 1'd0; + case (litedramcore_steerer0) 1'd0: begin - array_muxed4 <= 1'd0; + self4 <= 1'd0; end 1'd1: begin - array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + self4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + self4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + self4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed5 <= 1'd0; - case (litedramcore_steerer_sel0) + self5 <= 1'd0; + case (litedramcore_steerer0) 1'd0: begin - array_muxed5 <= 1'd0; + self5 <= 1'd0; end 1'd1: begin - array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + self5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + self5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + self5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed6 <= 1'd0; - case (litedramcore_steerer_sel0) + self6 <= 1'd0; + case (litedramcore_steerer0) 1'd0: begin - array_muxed6 <= 1'd0; + self6 <= 1'd0; end 1'd1: begin - array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + self6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + self6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + self6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); end endcase end always @(*) begin - array_muxed7 <= 3'd0; - case (litedramcore_steerer_sel1) + self7 <= 3'd0; + case (litedramcore_steerer1) 1'd0: begin - array_muxed7 <= litedramcore_nop_ba[2:0]; + self7 <= litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + self7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + self7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed7 <= litedramcore_cmd_payload_ba[2:0]; + self7 <= litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed8 <= 15'd0; - case (litedramcore_steerer_sel1) + self8 <= 15'd0; + case (litedramcore_steerer1) 1'd0: begin - array_muxed8 <= litedramcore_nop_a; + self8 <= litedramcore_nop_a; end 1'd1: begin - array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a; + self8 <= litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed8 <= litedramcore_choose_req_cmd_payload_a; + self8 <= litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed8 <= litedramcore_cmd_payload_a; + self8 <= litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed9 <= 1'd0; - case (litedramcore_steerer_sel1) + self9 <= 1'd0; + case (litedramcore_steerer1) 1'd0: begin - array_muxed9 <= 1'd0; + self9 <= 1'd0; end 1'd1: begin - array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + self9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + self9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + self9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed10 <= 1'd0; - case (litedramcore_steerer_sel1) + self10 <= 1'd0; + case (litedramcore_steerer1) 1'd0: begin - array_muxed10 <= 1'd0; + self10 <= 1'd0; end 1'd1: begin - array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + self10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + self10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + self10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed11 <= 1'd0; - case (litedramcore_steerer_sel1) + self11 <= 1'd0; + case (litedramcore_steerer1) 1'd0: begin - array_muxed11 <= 1'd0; + self11 <= 1'd0; end 1'd1: begin - array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + self11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + self11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + self11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed12 <= 1'd0; - case (litedramcore_steerer_sel1) + self12 <= 1'd0; + case (litedramcore_steerer1) 1'd0: begin - array_muxed12 <= 1'd0; + self12 <= 1'd0; end 1'd1: begin - array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + self12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + self12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + self12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed13 <= 1'd0; - case (litedramcore_steerer_sel1) + self13 <= 1'd0; + case (litedramcore_steerer1) 1'd0: begin - array_muxed13 <= 1'd0; + self13 <= 1'd0; end 1'd1: begin - array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + self13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + self13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + self13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); end endcase end -assign ddrphy_lock1 = regs1; +assign ddrphy_lock1 = multiregimpl1; //------------------------------------------------------------------------------ @@ -9663,44 +10034,44 @@ assign ddrphy_lock1 = regs1; always @(posedge init_clk) begin ddrphy_lock_d <= ddrphy_lock1; - if ((ddrphy_counter == 4'd8)) begin + if ((ddrphy_trigger == 4'd8)) begin ddrphy_freeze <= 1'd1; end - if ((ddrphy_counter == 5'd16)) begin + if ((ddrphy_trigger == 5'd16)) begin ddrphy_stop1 <= 1'd1; end - if ((ddrphy_counter == 5'd24)) begin + if ((ddrphy_trigger == 5'd24)) begin ddrphy_reset1 <= 1'd1; end - if ((ddrphy_counter == 6'd32)) begin + if ((ddrphy_trigger == 6'd32)) begin ddrphy_reset1 <= 1'd0; end - if ((ddrphy_counter == 6'd40)) begin + if ((ddrphy_trigger == 6'd40)) begin ddrphy_stop1 <= 1'd0; end - if ((ddrphy_counter == 6'd48)) begin + if ((ddrphy_trigger == 6'd48)) begin ddrphy_freeze <= 1'd0; end - if ((ddrphy_counter == 6'd56)) begin + if ((ddrphy_trigger == 6'd56)) begin ddrphy_pause1 <= 1'd1; end - if ((ddrphy_counter == 7'd64)) begin + if ((ddrphy_trigger == 7'd64)) begin ddrphy_update <= 1'd1; end - if ((ddrphy_counter == 7'd72)) begin + if ((ddrphy_trigger == 7'd72)) begin ddrphy_update <= 1'd0; end - if ((ddrphy_counter == 7'd80)) begin + if ((ddrphy_trigger == 7'd80)) begin ddrphy_pause1 <= 1'd0; end - if ((ddrphy_counter == 7'd80)) begin - ddrphy_counter <= 1'd0; + if ((ddrphy_trigger == 7'd80)) begin + ddrphy_trigger <= 1'd0; end else begin - if ((ddrphy_counter != 1'd0)) begin - ddrphy_counter <= (ddrphy_counter + 1'd1); + if ((ddrphy_trigger != 1'd0)) begin + ddrphy_trigger <= (ddrphy_trigger + 1'd1); end else begin if (ddrphy_new_lock) begin - ddrphy_counter <= 1'd1; + ddrphy_trigger <= 1'd1; end end end @@ -9711,10 +10082,10 @@ always @(posedge init_clk) begin ddrphy_pause1 <= 1'd0; ddrphy_reset1 <= 1'd0; ddrphy_lock_d <= 1'd0; - ddrphy_counter <= 7'd0; + ddrphy_trigger <= 7'd0; end - regs0 <= ddrphy_lock0; - regs1 <= regs0; + multiregimpl0 <= ddrphy_lock0; + multiregimpl1 <= multiregimpl0; end always @(posedge por_clk) begin @@ -10094,21 +10465,21 @@ always @(posedge sys_clk) begin litedramcore_cmd_payload_ras <= 1'd0; litedramcore_cmd_payload_we <= 1'd0; litedramcore_sequencer_done1 <= 1'd0; - if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin + if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_trigger == 1'd0))) begin litedramcore_cmd_payload_a <= 11'd1024; litedramcore_cmd_payload_ba <= 1'd0; litedramcore_cmd_payload_cas <= 1'd0; litedramcore_cmd_payload_ras <= 1'd1; litedramcore_cmd_payload_we <= 1'd1; end - if ((litedramcore_sequencer_counter == 2'd2)) begin + if ((litedramcore_sequencer_trigger == 2'd2)) begin litedramcore_cmd_payload_a <= 11'd1024; litedramcore_cmd_payload_ba <= 1'd0; litedramcore_cmd_payload_cas <= 1'd1; litedramcore_cmd_payload_ras <= 1'd1; litedramcore_cmd_payload_we <= 1'd0; end - if ((litedramcore_sequencer_counter == 7'd106)) begin + if ((litedramcore_sequencer_trigger == 7'd106)) begin litedramcore_cmd_payload_a <= 1'd0; litedramcore_cmd_payload_ba <= 1'd0; litedramcore_cmd_payload_cas <= 1'd0; @@ -10116,14 +10487,14 @@ always @(posedge sys_clk) begin litedramcore_cmd_payload_we <= 1'd0; litedramcore_sequencer_done1 <= 1'd1; end - if ((litedramcore_sequencer_counter == 7'd106)) begin - litedramcore_sequencer_counter <= 1'd0; + if ((litedramcore_sequencer_trigger == 7'd106)) begin + litedramcore_sequencer_trigger <= 1'd0; end else begin - if ((litedramcore_sequencer_counter != 1'd0)) begin - litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1); + if ((litedramcore_sequencer_trigger != 1'd0)) begin + litedramcore_sequencer_trigger <= (litedramcore_sequencer_trigger + 1'd1); end else begin if (litedramcore_sequencer_start1) begin - litedramcore_sequencer_counter <= 1'd1; + litedramcore_sequencer_trigger <= 1'd1; end end end @@ -10133,21 +10504,21 @@ always @(posedge sys_clk) begin litedramcore_zqcs_timer_count1 <= 26'd47999999; end litedramcore_zqcs_executer_done <= 1'd0; - if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin + if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_trigger == 1'd0))) begin litedramcore_cmd_payload_a <= 11'd1024; litedramcore_cmd_payload_ba <= 1'd0; litedramcore_cmd_payload_cas <= 1'd0; litedramcore_cmd_payload_ras <= 1'd1; litedramcore_cmd_payload_we <= 1'd1; end - if ((litedramcore_zqcs_executer_counter == 2'd2)) begin + if ((litedramcore_zqcs_executer_trigger == 2'd2)) begin litedramcore_cmd_payload_a <= 1'd0; litedramcore_cmd_payload_ba <= 1'd0; litedramcore_cmd_payload_cas <= 1'd0; litedramcore_cmd_payload_ras <= 1'd0; litedramcore_cmd_payload_we <= 1'd1; end - if ((litedramcore_zqcs_executer_counter == 6'd34)) begin + if ((litedramcore_zqcs_executer_trigger == 6'd34)) begin litedramcore_cmd_payload_a <= 1'd0; litedramcore_cmd_payload_ba <= 1'd0; litedramcore_cmd_payload_cas <= 1'd0; @@ -10155,18 +10526,18 @@ always @(posedge sys_clk) begin litedramcore_cmd_payload_we <= 1'd0; litedramcore_zqcs_executer_done <= 1'd1; end - if ((litedramcore_zqcs_executer_counter == 6'd34)) begin - litedramcore_zqcs_executer_counter <= 1'd0; + if ((litedramcore_zqcs_executer_trigger == 6'd34)) begin + litedramcore_zqcs_executer_trigger <= 1'd0; end else begin - if ((litedramcore_zqcs_executer_counter != 1'd0)) begin - litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1); + if ((litedramcore_zqcs_executer_trigger != 1'd0)) begin + litedramcore_zqcs_executer_trigger <= (litedramcore_zqcs_executer_trigger + 1'd1); end else begin if (litedramcore_zqcs_executer_start) begin - litedramcore_zqcs_executer_counter <= 1'd1; + litedramcore_zqcs_executer_trigger <= 1'd1; end end end - litedramcore_litedramcore_refresher_state <= litedramcore_litedramcore_refresher_next_state; + litedramcore_refresher_state <= litedramcore_refresher_next_state; if (litedramcore_bankmachine0_row_close) begin litedramcore_bankmachine0_row_opened <= 1'd0; end else begin @@ -10242,7 +10613,7 @@ always @(posedge sys_clk) begin end end end - litedramcore_litedramcore_bankmachine0_state <= litedramcore_litedramcore_bankmachine0_next_state; + litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state; if (litedramcore_bankmachine1_row_close) begin litedramcore_bankmachine1_row_opened <= 1'd0; end else begin @@ -10318,7 +10689,7 @@ always @(posedge sys_clk) begin end end end - litedramcore_litedramcore_bankmachine1_state <= litedramcore_litedramcore_bankmachine1_next_state; + litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state; if (litedramcore_bankmachine2_row_close) begin litedramcore_bankmachine2_row_opened <= 1'd0; end else begin @@ -10394,7 +10765,7 @@ always @(posedge sys_clk) begin end end end - litedramcore_litedramcore_bankmachine2_state <= litedramcore_litedramcore_bankmachine2_next_state; + litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state; if (litedramcore_bankmachine3_row_close) begin litedramcore_bankmachine3_row_opened <= 1'd0; end else begin @@ -10470,7 +10841,7 @@ always @(posedge sys_clk) begin end end end - litedramcore_litedramcore_bankmachine3_state <= litedramcore_litedramcore_bankmachine3_next_state; + litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state; if (litedramcore_bankmachine4_row_close) begin litedramcore_bankmachine4_row_opened <= 1'd0; end else begin @@ -10546,7 +10917,7 @@ always @(posedge sys_clk) begin end end end - litedramcore_litedramcore_bankmachine4_state <= litedramcore_litedramcore_bankmachine4_next_state; + litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state; if (litedramcore_bankmachine5_row_close) begin litedramcore_bankmachine5_row_opened <= 1'd0; end else begin @@ -10622,7 +10993,7 @@ always @(posedge sys_clk) begin end end end - litedramcore_litedramcore_bankmachine5_state <= litedramcore_litedramcore_bankmachine5_next_state; + litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state; if (litedramcore_bankmachine6_row_close) begin litedramcore_bankmachine6_row_opened <= 1'd0; end else begin @@ -10698,7 +11069,7 @@ always @(posedge sys_clk) begin end end end - litedramcore_litedramcore_bankmachine6_state <= litedramcore_litedramcore_bankmachine6_next_state; + litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state; if (litedramcore_bankmachine7_row_close) begin litedramcore_bankmachine7_row_opened <= 1'd0; end else begin @@ -10774,7 +11145,7 @@ always @(posedge sys_clk) begin end end end - litedramcore_litedramcore_bankmachine7_state <= litedramcore_litedramcore_bankmachine7_next_state; + litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state; if ((~litedramcore_en0)) begin litedramcore_time0 <= 5'd31; end else begin @@ -11262,21 +11633,21 @@ always @(posedge sys_clk) begin endcase end litedramcore_dfi_p0_cs_n <= 1'd0; - litedramcore_dfi_p0_bank <= array_muxed0; - litedramcore_dfi_p0_address <= array_muxed1; - litedramcore_dfi_p0_cas_n <= (~array_muxed2); - litedramcore_dfi_p0_ras_n <= (~array_muxed3); - litedramcore_dfi_p0_we_n <= (~array_muxed4); - litedramcore_dfi_p0_rddata_en <= array_muxed5; - litedramcore_dfi_p0_wrdata_en <= array_muxed6; + litedramcore_dfi_p0_bank <= self0; + litedramcore_dfi_p0_address <= self1; + litedramcore_dfi_p0_cas_n <= (~self2); + litedramcore_dfi_p0_ras_n <= (~self3); + litedramcore_dfi_p0_we_n <= (~self4); + litedramcore_dfi_p0_rddata_en <= self5; + litedramcore_dfi_p0_wrdata_en <= self6; litedramcore_dfi_p1_cs_n <= 1'd0; - litedramcore_dfi_p1_bank <= array_muxed7; - litedramcore_dfi_p1_address <= array_muxed8; - litedramcore_dfi_p1_cas_n <= (~array_muxed9); - litedramcore_dfi_p1_ras_n <= (~array_muxed10); - litedramcore_dfi_p1_we_n <= (~array_muxed11); - litedramcore_dfi_p1_rddata_en <= array_muxed12; - litedramcore_dfi_p1_wrdata_en <= array_muxed13; + litedramcore_dfi_p1_bank <= self7; + litedramcore_dfi_p1_address <= self8; + litedramcore_dfi_p1_cas_n <= (~self9); + litedramcore_dfi_p1_ras_n <= (~self10); + litedramcore_dfi_p1_we_n <= (~self11); + litedramcore_dfi_p1_rddata_en <= self12; + litedramcore_dfi_p1_wrdata_en <= self13; if (litedramcore_trrdcon_valid) begin litedramcore_trrdcon_count <= 1'd1; if (1'd0) begin @@ -11330,34 +11701,34 @@ always @(posedge sys_clk) begin end end end - litedramcore_litedramcore_multiplexer_state <= litedramcore_litedramcore_multiplexer_next_state; - litedramcore_litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); - litedramcore_litedramcore_new_master_wdata_ready1 <= litedramcore_litedramcore_new_master_wdata_ready0; - litedramcore_litedramcore_new_master_wdata_ready2 <= litedramcore_litedramcore_new_master_wdata_ready1; - litedramcore_litedramcore_new_master_wdata_ready3 <= litedramcore_litedramcore_new_master_wdata_ready2; - litedramcore_litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); - litedramcore_litedramcore_new_master_rdata_valid1 <= litedramcore_litedramcore_new_master_rdata_valid0; - litedramcore_litedramcore_new_master_rdata_valid2 <= litedramcore_litedramcore_new_master_rdata_valid1; - litedramcore_litedramcore_new_master_rdata_valid3 <= litedramcore_litedramcore_new_master_rdata_valid2; - litedramcore_litedramcore_new_master_rdata_valid4 <= litedramcore_litedramcore_new_master_rdata_valid3; - litedramcore_litedramcore_new_master_rdata_valid5 <= litedramcore_litedramcore_new_master_rdata_valid4; - litedramcore_litedramcore_new_master_rdata_valid6 <= litedramcore_litedramcore_new_master_rdata_valid5; - litedramcore_litedramcore_new_master_rdata_valid7 <= litedramcore_litedramcore_new_master_rdata_valid6; - litedramcore_litedramcore_new_master_rdata_valid8 <= litedramcore_litedramcore_new_master_rdata_valid7; - litedramcore_litedramcore_new_master_rdata_valid9 <= litedramcore_litedramcore_new_master_rdata_valid8; - litedramcore_litedramcore_new_master_rdata_valid10 <= litedramcore_litedramcore_new_master_rdata_valid9; - litedramcore_litedramcore_new_master_rdata_valid11 <= litedramcore_litedramcore_new_master_rdata_valid10; - litedramcore_litedramcore_new_master_rdata_valid12 <= litedramcore_litedramcore_new_master_rdata_valid11; - litedramcore_litedramcore_new_master_rdata_valid13 <= litedramcore_litedramcore_new_master_rdata_valid12; - litedramcore_state <= litedramcore_next_state; - if (litedramcore_dat_w_next_value_ce0) begin - litedramcore_dat_w <= litedramcore_dat_w_next_value0; - end - if (litedramcore_adr_next_value_ce1) begin - litedramcore_adr <= litedramcore_adr_next_value1; - end - if (litedramcore_we_next_value_ce2) begin - litedramcore_we <= litedramcore_we_next_value2; + litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state; + litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); + litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0; + litedramcore_new_master_wdata_ready2 <= litedramcore_new_master_wdata_ready1; + litedramcore_new_master_wdata_ready3 <= litedramcore_new_master_wdata_ready2; + litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); + litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0; + litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1; + litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2; + litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3; + litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4; + litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5; + litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6; + litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7; + litedramcore_new_master_rdata_valid9 <= litedramcore_new_master_rdata_valid8; + litedramcore_new_master_rdata_valid10 <= litedramcore_new_master_rdata_valid9; + litedramcore_new_master_rdata_valid11 <= litedramcore_new_master_rdata_valid10; + litedramcore_new_master_rdata_valid12 <= litedramcore_new_master_rdata_valid11; + litedramcore_new_master_rdata_valid13 <= litedramcore_new_master_rdata_valid12; + state <= next_state; + if (interface1_dat_w_next_value_ce0) begin + interface1_dat_w <= interface1_dat_w_next_value0; + end + if (interface1_adr_next_value_ce1) begin + interface1_adr <= interface1_adr_next_value1; + end + if (interface1_we_next_value_ce2) begin + interface1_we <= interface1_we_next_value2; end interface0_bank_bus_dat_r <= 1'd0; if (csrbank0_sel) begin @@ -11470,7 +11841,7 @@ always @(posedge sys_clk) begin end litedramcore_re <= csrbank2_dfii_control0_re; if (csrbank2_dfii_pi0_command0_re) begin - litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; + litedramcore_phaseinjector0_command_storage[7:0] <= csrbank2_dfii_pi0_command0_r; end litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; if (csrbank2_dfii_pi0_address0_re) begin @@ -11490,7 +11861,7 @@ always @(posedge sys_clk) begin litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata0_re; if (csrbank2_dfii_pi1_command0_re) begin - litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; + litedramcore_phaseinjector1_command_storage[7:0] <= csrbank2_dfii_pi1_command0_r; end litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; if (csrbank2_dfii_pi1_address0_re) begin @@ -11608,14 +11979,14 @@ always @(posedge sys_clk) begin ddrphy_wrdata_en_tappeddelayline6 <= 1'd0; litedramcore_storage <= 4'd1; litedramcore_re <= 1'd0; - litedramcore_phaseinjector0_command_storage <= 6'd0; + litedramcore_phaseinjector0_command_storage <= 8'd0; litedramcore_phaseinjector0_command_re <= 1'd0; litedramcore_phaseinjector0_address_re <= 1'd0; litedramcore_phaseinjector0_baddress_re <= 1'd0; litedramcore_phaseinjector0_wrdata_re <= 1'd0; litedramcore_phaseinjector0_rddata_status <= 64'd0; litedramcore_phaseinjector0_rddata_re <= 1'd0; - litedramcore_phaseinjector1_command_storage <= 6'd0; + litedramcore_phaseinjector1_command_storage <= 8'd0; litedramcore_phaseinjector1_command_re <= 1'd0; litedramcore_phaseinjector1_address_re <= 1'd0; litedramcore_phaseinjector1_baddress_re <= 1'd0; @@ -11647,11 +12018,11 @@ always @(posedge sys_clk) begin litedramcore_postponer_req_o <= 1'd0; litedramcore_postponer_count <= 1'd0; litedramcore_sequencer_done1 <= 1'd0; - litedramcore_sequencer_counter <= 7'd0; + litedramcore_sequencer_trigger <= 7'd0; litedramcore_sequencer_count <= 1'd0; litedramcore_zqcs_timer_count1 <= 26'd47999999; litedramcore_zqcs_executer_done <= 1'd0; - litedramcore_zqcs_executer_counter <= 6'd0; + litedramcore_zqcs_executer_trigger <= 6'd0; litedramcore_bankmachine0_level <= 5'd0; litedramcore_bankmachine0_produce <= 4'd0; litedramcore_bankmachine0_consume <= 4'd0; @@ -11780,36 +12151,36 @@ always @(posedge sys_clk) begin init_done_re <= 1'd0; init_error_storage <= 1'd0; init_error_re <= 1'd0; - litedramcore_we <= 1'd0; - litedramcore_litedramcore_refresher_state <= 2'd0; - litedramcore_litedramcore_bankmachine0_state <= 3'd0; - litedramcore_litedramcore_bankmachine1_state <= 3'd0; - litedramcore_litedramcore_bankmachine2_state <= 3'd0; - litedramcore_litedramcore_bankmachine3_state <= 3'd0; - litedramcore_litedramcore_bankmachine4_state <= 3'd0; - litedramcore_litedramcore_bankmachine5_state <= 3'd0; - litedramcore_litedramcore_bankmachine6_state <= 3'd0; - litedramcore_litedramcore_bankmachine7_state <= 3'd0; - litedramcore_litedramcore_multiplexer_state <= 4'd0; - litedramcore_litedramcore_new_master_wdata_ready0 <= 1'd0; - litedramcore_litedramcore_new_master_wdata_ready1 <= 1'd0; - litedramcore_litedramcore_new_master_wdata_ready2 <= 1'd0; - litedramcore_litedramcore_new_master_wdata_ready3 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid0 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid1 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid2 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid3 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid4 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid5 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid6 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid7 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid8 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid9 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid10 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid11 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid12 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid13 <= 1'd0; - litedramcore_state <= 2'd0; + interface1_we <= 1'd0; + litedramcore_refresher_state <= 2'd0; + litedramcore_bankmachine0_state <= 3'd0; + litedramcore_bankmachine1_state <= 3'd0; + litedramcore_bankmachine2_state <= 3'd0; + litedramcore_bankmachine3_state <= 3'd0; + litedramcore_bankmachine4_state <= 3'd0; + litedramcore_bankmachine5_state <= 3'd0; + litedramcore_bankmachine6_state <= 3'd0; + litedramcore_bankmachine7_state <= 3'd0; + litedramcore_multiplexer_state <= 4'd0; + litedramcore_new_master_wdata_ready0 <= 1'd0; + litedramcore_new_master_wdata_ready1 <= 1'd0; + litedramcore_new_master_wdata_ready2 <= 1'd0; + litedramcore_new_master_wdata_ready3 <= 1'd0; + litedramcore_new_master_rdata_valid0 <= 1'd0; + litedramcore_new_master_rdata_valid1 <= 1'd0; + litedramcore_new_master_rdata_valid2 <= 1'd0; + litedramcore_new_master_rdata_valid3 <= 1'd0; + litedramcore_new_master_rdata_valid4 <= 1'd0; + litedramcore_new_master_rdata_valid5 <= 1'd0; + litedramcore_new_master_rdata_valid6 <= 1'd0; + litedramcore_new_master_rdata_valid7 <= 1'd0; + litedramcore_new_master_rdata_valid8 <= 1'd0; + litedramcore_new_master_rdata_valid9 <= 1'd0; + litedramcore_new_master_rdata_valid10 <= 1'd0; + litedramcore_new_master_rdata_valid11 <= 1'd0; + litedramcore_new_master_rdata_valid12 <= 1'd0; + litedramcore_new_master_rdata_valid13 <= 1'd0; + state <= 2'd0; end end @@ -11818,1394 +12189,2207 @@ end // Specialized Logic //------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +// Instance ECLKBRIDGECS of ECLKBRIDGECS Module. +//------------------------------------------------------------------------------ ECLKBRIDGECS ECLKBRIDGECS( - .CLK0(sys2x_i_clk), - .SEL(1'd0), - .ECSOUT(crg_sys2x_clk_ecsout) + // Inputs. + .CLK0 (sys2x_i_clk), + .SEL (1'd0), + + // Outputs. + .ECSOUT (crg_sys2x_clk_ecsout) ); +//------------------------------------------------------------------------------ +// Instance ECLKSYNCB of ECLKSYNCB Module. +//------------------------------------------------------------------------------ ECLKSYNCB ECLKSYNCB( - .ECLKI(crg_sys2x_clk_ecsout), - .STOP(crg_stop), - .ECLKO(sys2x_clk) + // Inputs. + .ECLKI (crg_sys2x_clk_ecsout), + .STOP (crg_stop), + + // Outputs. + .ECLKO (sys2x_clk) ); +//------------------------------------------------------------------------------ +// Instance CLKDIVF of CLKDIVF Module. +//------------------------------------------------------------------------------ CLKDIVF #( - .DIV("2.0") + // Parameters. + .DIV ("2.0") ) CLKDIVF ( - .ALIGNWD(1'd0), - .CLKI(sys2x_clk), - .RST(crg_reset0), - .CDIVX(sys_clk) + // Inputs. + .ALIGNWD (1'd0), + .CLKI (sys2x_clk), + .RST (crg_reset0), + + // Outputs. + .CDIVX (sys_clk) ); +//------------------------------------------------------------------------------ +// Instance DDRDLLA of DDRDLLA Module. +//------------------------------------------------------------------------------ DDRDLLA DDRDLLA( - .CLK(sys2x_clk), - .FREEZE(ddrphy_freeze), - .RST(init_rst), - .UDDCNTLN((~ddrphy_update)), - .DDRDEL(ddrphy_delay1), - .LOCK(ddrphy_lock0) + // Inputs. + .CLK (sys2x_clk), + .FREEZE (ddrphy_freeze), + .RST (init_rst), + .UDDCNTLN ((~ddrphy_update)), + + // Outputs. + .DDRDEL (ddrphy_delay1), + .LOCK (ddrphy_lock0) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F( - .D0(1'd0), - .D1(1'd1), - .D2(1'd0), - .D3(1'd1), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f0) + // Inputs. + .D0 (1'd0), + .D1 (1'd1), + .D2 (1'd0), + .D3 (1'd1), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f0) ); +//------------------------------------------------------------------------------ +// Instance DELAYG of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG ( - .A(ddrphy_pad_oddrx2f0), - .Z(ddram_clk_p) + // Inputs. + .A (ddrphy_pad_oddrx2f0), + + // Outputs. + .Z (ddram_clk_p) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_1 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_1( - .D0(ddrphy_dfi_p0_reset_n), - .D1(ddrphy_dfi_p0_reset_n), - .D2(ddrphy_dfi_p1_reset_n), - .D3(ddrphy_dfi_p1_reset_n), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f1) + // Inputs. + .D0 (ddrphy_dfi_p0_reset_n), + .D1 (ddrphy_dfi_p0_reset_n), + .D2 (ddrphy_dfi_p1_reset_n), + .D3 (ddrphy_dfi_p1_reset_n), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f1) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_1 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_1 ( - .A(ddrphy_pad_oddrx2f1), - .Z(ddram_reset_n) + // Inputs. + .A (ddrphy_pad_oddrx2f1), + + // Outputs. + .Z (ddram_reset_n) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_2 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_2( - .D0(ddrphy_dfi_p0_cs_n), - .D1(ddrphy_dfi_p0_cs_n), - .D2(ddrphy_dfi_p1_cs_n), - .D3(ddrphy_dfi_p1_cs_n), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f2) + // Inputs. + .D0 (ddrphy_dfi_p0_cs_n), + .D1 (ddrphy_dfi_p0_cs_n), + .D2 (ddrphy_dfi_p1_cs_n), + .D3 (ddrphy_dfi_p1_cs_n), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f2) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_2 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_2 ( - .A(ddrphy_pad_oddrx2f2), - .Z(ddram_cs_n) + // Inputs. + .A (ddrphy_pad_oddrx2f2), + + // Outputs. + .Z (ddram_cs_n) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_3 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_3( - .D0(ddrphy_dfi_p0_address[0]), - .D1(ddrphy_dfi_p0_address[0]), - .D2(ddrphy_dfi_p1_address[0]), - .D3(ddrphy_dfi_p1_address[0]), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f3) + // Inputs. + .D0 (ddrphy_dfi_p0_address[0]), + .D1 (ddrphy_dfi_p0_address[0]), + .D2 (ddrphy_dfi_p1_address[0]), + .D3 (ddrphy_dfi_p1_address[0]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f3) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_3 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_3 ( - .A(ddrphy_pad_oddrx2f3), - .Z(ddram_a[0]) + // Inputs. + .A (ddrphy_pad_oddrx2f3), + + // Outputs. + .Z (ddram_a[0]) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_4 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_4( - .D0(ddrphy_dfi_p0_address[1]), - .D1(ddrphy_dfi_p0_address[1]), - .D2(ddrphy_dfi_p1_address[1]), - .D3(ddrphy_dfi_p1_address[1]), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f4) + // Inputs. + .D0 (ddrphy_dfi_p0_address[1]), + .D1 (ddrphy_dfi_p0_address[1]), + .D2 (ddrphy_dfi_p1_address[1]), + .D3 (ddrphy_dfi_p1_address[1]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f4) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_4 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_4 ( - .A(ddrphy_pad_oddrx2f4), - .Z(ddram_a[1]) + // Inputs. + .A (ddrphy_pad_oddrx2f4), + + // Outputs. + .Z (ddram_a[1]) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_5 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_5( - .D0(ddrphy_dfi_p0_address[2]), - .D1(ddrphy_dfi_p0_address[2]), - .D2(ddrphy_dfi_p1_address[2]), - .D3(ddrphy_dfi_p1_address[2]), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f5) + // Inputs. + .D0 (ddrphy_dfi_p0_address[2]), + .D1 (ddrphy_dfi_p0_address[2]), + .D2 (ddrphy_dfi_p1_address[2]), + .D3 (ddrphy_dfi_p1_address[2]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f5) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_5 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_5 ( - .A(ddrphy_pad_oddrx2f5), - .Z(ddram_a[2]) + // Inputs. + .A (ddrphy_pad_oddrx2f5), + + // Outputs. + .Z (ddram_a[2]) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_6 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_6( - .D0(ddrphy_dfi_p0_address[3]), - .D1(ddrphy_dfi_p0_address[3]), - .D2(ddrphy_dfi_p1_address[3]), - .D3(ddrphy_dfi_p1_address[3]), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f6) + // Inputs. + .D0 (ddrphy_dfi_p0_address[3]), + .D1 (ddrphy_dfi_p0_address[3]), + .D2 (ddrphy_dfi_p1_address[3]), + .D3 (ddrphy_dfi_p1_address[3]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f6) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_6 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_6 ( - .A(ddrphy_pad_oddrx2f6), - .Z(ddram_a[3]) + // Inputs. + .A (ddrphy_pad_oddrx2f6), + + // Outputs. + .Z (ddram_a[3]) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_7 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_7( - .D0(ddrphy_dfi_p0_address[4]), - .D1(ddrphy_dfi_p0_address[4]), - .D2(ddrphy_dfi_p1_address[4]), - .D3(ddrphy_dfi_p1_address[4]), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f7) + // Inputs. + .D0 (ddrphy_dfi_p0_address[4]), + .D1 (ddrphy_dfi_p0_address[4]), + .D2 (ddrphy_dfi_p1_address[4]), + .D3 (ddrphy_dfi_p1_address[4]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f7) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_7 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_7 ( - .A(ddrphy_pad_oddrx2f7), - .Z(ddram_a[4]) + // Inputs. + .A (ddrphy_pad_oddrx2f7), + + // Outputs. + .Z (ddram_a[4]) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_8 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_8( - .D0(ddrphy_dfi_p0_address[5]), - .D1(ddrphy_dfi_p0_address[5]), - .D2(ddrphy_dfi_p1_address[5]), - .D3(ddrphy_dfi_p1_address[5]), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f8) + // Inputs. + .D0 (ddrphy_dfi_p0_address[5]), + .D1 (ddrphy_dfi_p0_address[5]), + .D2 (ddrphy_dfi_p1_address[5]), + .D3 (ddrphy_dfi_p1_address[5]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f8) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_8 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_8 ( - .A(ddrphy_pad_oddrx2f8), - .Z(ddram_a[5]) + // Inputs. + .A (ddrphy_pad_oddrx2f8), + + // Outputs. + .Z (ddram_a[5]) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_9 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_9( - .D0(ddrphy_dfi_p0_address[6]), - .D1(ddrphy_dfi_p0_address[6]), - .D2(ddrphy_dfi_p1_address[6]), - .D3(ddrphy_dfi_p1_address[6]), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f9) + // Inputs. + .D0 (ddrphy_dfi_p0_address[6]), + .D1 (ddrphy_dfi_p0_address[6]), + .D2 (ddrphy_dfi_p1_address[6]), + .D3 (ddrphy_dfi_p1_address[6]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f9) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_9 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_9 ( - .A(ddrphy_pad_oddrx2f9), - .Z(ddram_a[6]) + // Inputs. + .A (ddrphy_pad_oddrx2f9), + + // Outputs. + .Z (ddram_a[6]) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_10 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_10( - .D0(ddrphy_dfi_p0_address[7]), - .D1(ddrphy_dfi_p0_address[7]), - .D2(ddrphy_dfi_p1_address[7]), - .D3(ddrphy_dfi_p1_address[7]), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f10) + // Inputs. + .D0 (ddrphy_dfi_p0_address[7]), + .D1 (ddrphy_dfi_p0_address[7]), + .D2 (ddrphy_dfi_p1_address[7]), + .D3 (ddrphy_dfi_p1_address[7]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f10) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_10 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_10 ( - .A(ddrphy_pad_oddrx2f10), - .Z(ddram_a[7]) + // Inputs. + .A (ddrphy_pad_oddrx2f10), + + // Outputs. + .Z (ddram_a[7]) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_11 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_11( - .D0(ddrphy_dfi_p0_address[8]), - .D1(ddrphy_dfi_p0_address[8]), - .D2(ddrphy_dfi_p1_address[8]), - .D3(ddrphy_dfi_p1_address[8]), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f11) + // Inputs. + .D0 (ddrphy_dfi_p0_address[8]), + .D1 (ddrphy_dfi_p0_address[8]), + .D2 (ddrphy_dfi_p1_address[8]), + .D3 (ddrphy_dfi_p1_address[8]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f11) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_11 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_11 ( - .A(ddrphy_pad_oddrx2f11), - .Z(ddram_a[8]) + // Inputs. + .A (ddrphy_pad_oddrx2f11), + + // Outputs. + .Z (ddram_a[8]) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_12 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_12( - .D0(ddrphy_dfi_p0_address[9]), - .D1(ddrphy_dfi_p0_address[9]), - .D2(ddrphy_dfi_p1_address[9]), - .D3(ddrphy_dfi_p1_address[9]), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f12) + // Inputs. + .D0 (ddrphy_dfi_p0_address[9]), + .D1 (ddrphy_dfi_p0_address[9]), + .D2 (ddrphy_dfi_p1_address[9]), + .D3 (ddrphy_dfi_p1_address[9]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f12) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_12 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_12 ( - .A(ddrphy_pad_oddrx2f12), - .Z(ddram_a[9]) + // Inputs. + .A (ddrphy_pad_oddrx2f12), + + // Outputs. + .Z (ddram_a[9]) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_13 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_13( - .D0(ddrphy_dfi_p0_address[10]), - .D1(ddrphy_dfi_p0_address[10]), - .D2(ddrphy_dfi_p1_address[10]), - .D3(ddrphy_dfi_p1_address[10]), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f13) + // Inputs. + .D0 (ddrphy_dfi_p0_address[10]), + .D1 (ddrphy_dfi_p0_address[10]), + .D2 (ddrphy_dfi_p1_address[10]), + .D3 (ddrphy_dfi_p1_address[10]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f13) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_13 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_13 ( - .A(ddrphy_pad_oddrx2f13), - .Z(ddram_a[10]) + // Inputs. + .A (ddrphy_pad_oddrx2f13), + + // Outputs. + .Z (ddram_a[10]) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_14 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_14( - .D0(ddrphy_dfi_p0_address[11]), - .D1(ddrphy_dfi_p0_address[11]), - .D2(ddrphy_dfi_p1_address[11]), - .D3(ddrphy_dfi_p1_address[11]), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f14) + // Inputs. + .D0 (ddrphy_dfi_p0_address[11]), + .D1 (ddrphy_dfi_p0_address[11]), + .D2 (ddrphy_dfi_p1_address[11]), + .D3 (ddrphy_dfi_p1_address[11]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f14) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_14 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_14 ( - .A(ddrphy_pad_oddrx2f14), - .Z(ddram_a[11]) + // Inputs. + .A (ddrphy_pad_oddrx2f14), + + // Outputs. + .Z (ddram_a[11]) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_15 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_15( - .D0(ddrphy_dfi_p0_address[12]), - .D1(ddrphy_dfi_p0_address[12]), - .D2(ddrphy_dfi_p1_address[12]), - .D3(ddrphy_dfi_p1_address[12]), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f15) + // Inputs. + .D0 (ddrphy_dfi_p0_address[12]), + .D1 (ddrphy_dfi_p0_address[12]), + .D2 (ddrphy_dfi_p1_address[12]), + .D3 (ddrphy_dfi_p1_address[12]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f15) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_15 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_15 ( - .A(ddrphy_pad_oddrx2f15), - .Z(ddram_a[12]) + // Inputs. + .A (ddrphy_pad_oddrx2f15), + + // Outputs. + .Z (ddram_a[12]) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_16 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_16( - .D0(ddrphy_dfi_p0_address[13]), - .D1(ddrphy_dfi_p0_address[13]), - .D2(ddrphy_dfi_p1_address[13]), - .D3(ddrphy_dfi_p1_address[13]), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f16) + // Inputs. + .D0 (ddrphy_dfi_p0_address[13]), + .D1 (ddrphy_dfi_p0_address[13]), + .D2 (ddrphy_dfi_p1_address[13]), + .D3 (ddrphy_dfi_p1_address[13]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f16) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_16 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_16 ( - .A(ddrphy_pad_oddrx2f16), - .Z(ddram_a[13]) + // Inputs. + .A (ddrphy_pad_oddrx2f16), + + // Outputs. + .Z (ddram_a[13]) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_17 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_17( - .D0(ddrphy_dfi_p0_address[14]), - .D1(ddrphy_dfi_p0_address[14]), - .D2(ddrphy_dfi_p1_address[14]), - .D3(ddrphy_dfi_p1_address[14]), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f17) + // Inputs. + .D0 (ddrphy_dfi_p0_address[14]), + .D1 (ddrphy_dfi_p0_address[14]), + .D2 (ddrphy_dfi_p1_address[14]), + .D3 (ddrphy_dfi_p1_address[14]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f17) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_17 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_17 ( - .A(ddrphy_pad_oddrx2f17), - .Z(ddram_a[14]) + // Inputs. + .A (ddrphy_pad_oddrx2f17), + + // Outputs. + .Z (ddram_a[14]) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_18 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_18( - .D0(ddrphy_dfi_p0_bank[0]), - .D1(ddrphy_dfi_p0_bank[0]), - .D2(ddrphy_dfi_p1_bank[0]), - .D3(ddrphy_dfi_p1_bank[0]), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f18) + // Inputs. + .D0 (ddrphy_dfi_p0_bank[0]), + .D1 (ddrphy_dfi_p0_bank[0]), + .D2 (ddrphy_dfi_p1_bank[0]), + .D3 (ddrphy_dfi_p1_bank[0]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f18) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_18 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_18 ( - .A(ddrphy_pad_oddrx2f18), - .Z(ddram_ba[0]) + // Inputs. + .A (ddrphy_pad_oddrx2f18), + + // Outputs. + .Z (ddram_ba[0]) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_19 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_19( - .D0(ddrphy_dfi_p0_bank[1]), - .D1(ddrphy_dfi_p0_bank[1]), - .D2(ddrphy_dfi_p1_bank[1]), - .D3(ddrphy_dfi_p1_bank[1]), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f19) + // Inputs. + .D0 (ddrphy_dfi_p0_bank[1]), + .D1 (ddrphy_dfi_p0_bank[1]), + .D2 (ddrphy_dfi_p1_bank[1]), + .D3 (ddrphy_dfi_p1_bank[1]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f19) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_19 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_19 ( - .A(ddrphy_pad_oddrx2f19), - .Z(ddram_ba[1]) + // Inputs. + .A (ddrphy_pad_oddrx2f19), + + // Outputs. + .Z (ddram_ba[1]) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_20 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_20( - .D0(ddrphy_dfi_p0_bank[2]), - .D1(ddrphy_dfi_p0_bank[2]), - .D2(ddrphy_dfi_p1_bank[2]), - .D3(ddrphy_dfi_p1_bank[2]), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f20) + // Inputs. + .D0 (ddrphy_dfi_p0_bank[2]), + .D1 (ddrphy_dfi_p0_bank[2]), + .D2 (ddrphy_dfi_p1_bank[2]), + .D3 (ddrphy_dfi_p1_bank[2]), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f20) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_20 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_20 ( - .A(ddrphy_pad_oddrx2f20), - .Z(ddram_ba[2]) + // Inputs. + .A (ddrphy_pad_oddrx2f20), + + // Outputs. + .Z (ddram_ba[2]) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_21 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_21( - .D0(ddrphy_dfi_p0_ras_n), - .D1(ddrphy_dfi_p0_ras_n), - .D2(ddrphy_dfi_p1_ras_n), - .D3(ddrphy_dfi_p1_ras_n), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f21) + // Inputs. + .D0 (ddrphy_dfi_p0_ras_n), + .D1 (ddrphy_dfi_p0_ras_n), + .D2 (ddrphy_dfi_p1_ras_n), + .D3 (ddrphy_dfi_p1_ras_n), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f21) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_21 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_21 ( - .A(ddrphy_pad_oddrx2f21), - .Z(ddram_ras_n) + // Inputs. + .A (ddrphy_pad_oddrx2f21), + + // Outputs. + .Z (ddram_ras_n) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_22 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_22( - .D0(ddrphy_dfi_p0_cas_n), - .D1(ddrphy_dfi_p0_cas_n), - .D2(ddrphy_dfi_p1_cas_n), - .D3(ddrphy_dfi_p1_cas_n), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f22) + // Inputs. + .D0 (ddrphy_dfi_p0_cas_n), + .D1 (ddrphy_dfi_p0_cas_n), + .D2 (ddrphy_dfi_p1_cas_n), + .D3 (ddrphy_dfi_p1_cas_n), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f22) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_22 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_22 ( - .A(ddrphy_pad_oddrx2f22), - .Z(ddram_cas_n) + // Inputs. + .A (ddrphy_pad_oddrx2f22), + + // Outputs. + .Z (ddram_cas_n) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_23 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_23( - .D0(ddrphy_dfi_p0_we_n), - .D1(ddrphy_dfi_p0_we_n), - .D2(ddrphy_dfi_p1_we_n), - .D3(ddrphy_dfi_p1_we_n), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f23) + // Inputs. + .D0 (ddrphy_dfi_p0_we_n), + .D1 (ddrphy_dfi_p0_we_n), + .D2 (ddrphy_dfi_p1_we_n), + .D3 (ddrphy_dfi_p1_we_n), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f23) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_23 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_23 ( - .A(ddrphy_pad_oddrx2f23), - .Z(ddram_we_n) + // Inputs. + .A (ddrphy_pad_oddrx2f23), + + // Outputs. + .Z (ddram_we_n) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_24 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_24( - .D0(ddrphy_dfi_p0_cke), - .D1(ddrphy_dfi_p0_cke), - .D2(ddrphy_dfi_p1_cke), - .D3(ddrphy_dfi_p1_cke), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f24) + // Inputs. + .D0 (ddrphy_dfi_p0_cke), + .D1 (ddrphy_dfi_p0_cke), + .D2 (ddrphy_dfi_p1_cke), + .D3 (ddrphy_dfi_p1_cke), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f24) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_24 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_24 ( - .A(ddrphy_pad_oddrx2f24), - .Z(ddram_cke) + // Inputs. + .A (ddrphy_pad_oddrx2f24), + + // Outputs. + .Z (ddram_cke) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2F_25 of ODDRX2F Module. +//------------------------------------------------------------------------------ ODDRX2F ODDRX2F_25( - .D0(ddrphy_dfi_p0_odt), - .D1(ddrphy_dfi_p0_odt), - .D2(ddrphy_dfi_p1_odt), - .D3(ddrphy_dfi_p1_odt), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_pad_oddrx2f25) + // Inputs. + .D0 (ddrphy_dfi_p0_odt), + .D1 (ddrphy_dfi_p0_odt), + .D2 (ddrphy_dfi_p1_odt), + .D3 (ddrphy_dfi_p1_odt), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_pad_oddrx2f25) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_25 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_VALUE(7'd100) + // Parameters. + .DEL_VALUE (7'd100) ) DELAYG_25 ( - .A(ddrphy_pad_oddrx2f25), - .Z(ddram_odt) + // Inputs. + .A (ddrphy_pad_oddrx2f25), + + // Outputs. + .Z (ddram_odt) ); +//------------------------------------------------------------------------------ +// Instance DQSBUFM of DQSBUFM Module. +//------------------------------------------------------------------------------ DQSBUFM #( - .DQS_LI_DEL_ADJ("MINUS"), - .DQS_LI_DEL_VAL(1'd1), - .DQS_LO_DEL_ADJ("MINUS"), - .DQS_LO_DEL_VAL(3'd4) + // Parameters. + .DQS_LI_DEL_ADJ ("MINUS"), + .DQS_LI_DEL_VAL (1'd1), + .DQS_LO_DEL_ADJ ("MINUS"), + .DQS_LO_DEL_VAL (3'd4) ) DQSBUFM ( - .DDRDEL(ddrphy_delay0), - .DQSI(ddrphy_dqs_i0), - .ECLK(sys2x_clk), - .PAUSE((ddrphy_pause0 | ddrphy_dly_sel_storage[0])), - .RDDIRECTION(1'd1), - .RDLOADN(1'd0), - .RDMOVE(1'd0), - .READ0(ddrphy_dqs_re), - .READ1(ddrphy_dqs_re), - .READCLKSEL0(ddrphy_rdly0[0]), - .READCLKSEL1(ddrphy_rdly0[1]), - .READCLKSEL2(ddrphy_rdly0[2]), - .RST(sys_rst), - .SCLK(sys_clk), - .WRDIRECTION(1'd1), - .WRLOADN(1'd0), - .WRMOVE(1'd0), - .BURSTDET(ddrphy_burstdet0), - .DATAVALID(ddrphy_datavalid[0]), - .DQSR90(ddrphy_dqsr900), - .DQSW(ddrphy_dqsw0), - .DQSW270(ddrphy_dqsw2700), - .RDPNTR0(ddrphy_rdpntr0[0]), - .RDPNTR1(ddrphy_rdpntr0[1]), - .RDPNTR2(ddrphy_rdpntr0[2]), - .WRPNTR0(ddrphy_wrpntr0[0]), - .WRPNTR1(ddrphy_wrpntr0[1]), - .WRPNTR2(ddrphy_wrpntr0[2]) + // Inputs. + .DDRDEL (ddrphy_delay0), + .DQSI (ddrphy_dqs_i0), + .ECLK (sys2x_clk), + .PAUSE ((ddrphy_pause0 | ddrphy_dly_sel_storage[0])), + .RDDIRECTION (1'd1), + .RDLOADN (1'd0), + .RDMOVE (1'd0), + .READ0 (ddrphy_dqs_re), + .READ1 (ddrphy_dqs_re), + .READCLKSEL0 (ddrphy_rdly0[0]), + .READCLKSEL1 (ddrphy_rdly0[1]), + .READCLKSEL2 (ddrphy_rdly0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRDIRECTION (1'd1), + .WRLOADN (1'd0), + .WRMOVE (1'd0), + + // Outputs. + .BURSTDET (ddrphy_burstdet0), + .DATAVALID (ddrphy_datavalid[0]), + .DQSR90 (ddrphy_dqsr900), + .DQSW (ddrphy_dqsw0), + .DQSW270 (ddrphy_dqsw2700), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2DQSB of ODDRX2DQSB Module. +//------------------------------------------------------------------------------ ODDRX2DQSB ODDRX2DQSB( - .D0(1'd0), - .D1(1'd1), - .D2(1'd0), - .D3(1'd1), - .DQSW(ddrphy_dqsw0), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_dqs0) + // Inputs. + .D0 (1'd0), + .D1 (1'd1), + .D2 (1'd0), + .D3 (1'd1), + .DQSW (ddrphy_dqsw0), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dqs0) ); +//------------------------------------------------------------------------------ +// Instance TSHX2DQSA of TSHX2DQSA Module. +//------------------------------------------------------------------------------ TSHX2DQSA TSHX2DQSA( - .DQSW(ddrphy_dqsw0), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .T0((~(ddrphy_dqs_oe | ddrphy_dqs_postamble))), - .T1((~(ddrphy_dqs_oe | ddrphy_dqs_preamble))), - .Q(ddrphy_dqs_oe_n0) + // Inputs. + .DQSW (ddrphy_dqsw0), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~(ddrphy_dqs_oe | ddrphy_dqs_postamble))), + .T1 ((~(ddrphy_dqs_oe | ddrphy_dqs_preamble))), + + // Outputs. + .Q (ddrphy_dqs_oe_n0) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA of ODDRX2DQA Module. +//------------------------------------------------------------------------------ ODDRX2DQA ODDRX2DQA( - .D0(ddrphy_dm_o_data_muxed0[0]), - .D1(ddrphy_dm_o_data_muxed0[1]), - .D2(ddrphy_dm_o_data_muxed0[2]), - .D3(ddrphy_dm_o_data_muxed0[3]), - .DQSW270(ddrphy_dqsw2700), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddram_dm[0]) + // Inputs. + .D0 (ddrphy_dm_o_data_muxed0[0]), + .D1 (ddrphy_dm_o_data_muxed0[1]), + .D2 (ddrphy_dm_o_data_muxed0[2]), + .D3 (ddrphy_dm_o_data_muxed0[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddram_dm[0]) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_1 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ ODDRX2DQA ODDRX2DQA_1( - .D0(ddrphy_dq_o_data_muxed0[0]), - .D1(ddrphy_dq_o_data_muxed0[1]), - .D2(ddrphy_dq_o_data_muxed0[2]), - .D3(ddrphy_dq_o_data_muxed0[3]), - .DQSW270(ddrphy_dqsw2700), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_dq_o0) + // Inputs. + .D0 (ddrphy_dq_o_data_muxed0[0]), + .D1 (ddrphy_dq_o_data_muxed0[1]), + .D2 (ddrphy_dq_o_data_muxed0[2]), + .D3 (ddrphy_dq_o_data_muxed0[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o0) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_26 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_MODE("DQS_ALIGNED_X2") + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") ) DELAYG_26 ( - .A(ddrphy_dq_i0), - .Z(ddrphy_dq_i_delayed0) + // Inputs. + .A (ddrphy_dq_i0), + + // Outputs. + .Z (ddrphy_dq_i_delayed0) ); +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA of IDDRX2DQA Module. +//------------------------------------------------------------------------------ IDDRX2DQA IDDRX2DQA( - .D(ddrphy_dq_i_delayed0), - .DQSR90(ddrphy_dqsr900), - .ECLK(sys2x_clk), - .RDPNTR0(ddrphy_rdpntr0[0]), - .RDPNTR1(ddrphy_rdpntr0[1]), - .RDPNTR2(ddrphy_rdpntr0[2]), - .RST(sys_rst), - .SCLK(sys_clk), - .WRPNTR0(ddrphy_wrpntr0[0]), - .WRPNTR1(ddrphy_wrpntr0[1]), - .WRPNTR2(ddrphy_wrpntr0[2]), - .Q0(ddrphy_bitslip0_i[0]), - .Q1(ddrphy_bitslip0_i[1]), - .Q2(ddrphy_bitslip0_i[2]), - .Q3(ddrphy_bitslip0_i[3]) + // Inputs. + .D (ddrphy_dq_i_delayed0), + .DQSR90 (ddrphy_dqsr900), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]), + + // Outputs. + .Q0 (ddrphy_bitslip0_i[0]), + .Q1 (ddrphy_bitslip0_i[1]), + .Q2 (ddrphy_bitslip0_i[2]), + .Q3 (ddrphy_bitslip0_i[3]) ); +//------------------------------------------------------------------------------ +// Instance TSHX2DQA of TSHX2DQA Module. +//------------------------------------------------------------------------------ TSHX2DQA TSHX2DQA( - .DQSW270(ddrphy_dqsw2700), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .T0((~ddrphy_dq_oe)), - .T1((~ddrphy_dq_oe)), - .Q(ddrphy_dq_oe_n0) + // Inputs. + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n0) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_2 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ ODDRX2DQA ODDRX2DQA_2( - .D0(ddrphy_dq_o_data_muxed1[0]), - .D1(ddrphy_dq_o_data_muxed1[1]), - .D2(ddrphy_dq_o_data_muxed1[2]), - .D3(ddrphy_dq_o_data_muxed1[3]), - .DQSW270(ddrphy_dqsw2700), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_dq_o1) + // Inputs. + .D0 (ddrphy_dq_o_data_muxed1[0]), + .D1 (ddrphy_dq_o_data_muxed1[1]), + .D2 (ddrphy_dq_o_data_muxed1[2]), + .D3 (ddrphy_dq_o_data_muxed1[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o1) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_27 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_MODE("DQS_ALIGNED_X2") + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") ) DELAYG_27 ( - .A(ddrphy_dq_i1), - .Z(ddrphy_dq_i_delayed1) + // Inputs. + .A (ddrphy_dq_i1), + + // Outputs. + .Z (ddrphy_dq_i_delayed1) ); +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_1 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ IDDRX2DQA IDDRX2DQA_1( - .D(ddrphy_dq_i_delayed1), - .DQSR90(ddrphy_dqsr900), - .ECLK(sys2x_clk), - .RDPNTR0(ddrphy_rdpntr0[0]), - .RDPNTR1(ddrphy_rdpntr0[1]), - .RDPNTR2(ddrphy_rdpntr0[2]), - .RST(sys_rst), - .SCLK(sys_clk), - .WRPNTR0(ddrphy_wrpntr0[0]), - .WRPNTR1(ddrphy_wrpntr0[1]), - .WRPNTR2(ddrphy_wrpntr0[2]), - .Q0(ddrphy_bitslip1_i[0]), - .Q1(ddrphy_bitslip1_i[1]), - .Q2(ddrphy_bitslip1_i[2]), - .Q3(ddrphy_bitslip1_i[3]) + // Inputs. + .D (ddrphy_dq_i_delayed1), + .DQSR90 (ddrphy_dqsr900), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]), + + // Outputs. + .Q0 (ddrphy_bitslip1_i[0]), + .Q1 (ddrphy_bitslip1_i[1]), + .Q2 (ddrphy_bitslip1_i[2]), + .Q3 (ddrphy_bitslip1_i[3]) ); +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_1 of TSHX2DQA Module. +//------------------------------------------------------------------------------ TSHX2DQA TSHX2DQA_1( - .DQSW270(ddrphy_dqsw2700), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .T0((~ddrphy_dq_oe)), - .T1((~ddrphy_dq_oe)), - .Q(ddrphy_dq_oe_n1) + // Inputs. + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n1) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_3 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ ODDRX2DQA ODDRX2DQA_3( - .D0(ddrphy_dq_o_data_muxed2[0]), - .D1(ddrphy_dq_o_data_muxed2[1]), - .D2(ddrphy_dq_o_data_muxed2[2]), - .D3(ddrphy_dq_o_data_muxed2[3]), - .DQSW270(ddrphy_dqsw2700), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_dq_o2) + // Inputs. + .D0 (ddrphy_dq_o_data_muxed2[0]), + .D1 (ddrphy_dq_o_data_muxed2[1]), + .D2 (ddrphy_dq_o_data_muxed2[2]), + .D3 (ddrphy_dq_o_data_muxed2[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o2) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_28 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_MODE("DQS_ALIGNED_X2") + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") ) DELAYG_28 ( - .A(ddrphy_dq_i2), - .Z(ddrphy_dq_i_delayed2) + // Inputs. + .A (ddrphy_dq_i2), + + // Outputs. + .Z (ddrphy_dq_i_delayed2) ); +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_2 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ IDDRX2DQA IDDRX2DQA_2( - .D(ddrphy_dq_i_delayed2), - .DQSR90(ddrphy_dqsr900), - .ECLK(sys2x_clk), - .RDPNTR0(ddrphy_rdpntr0[0]), - .RDPNTR1(ddrphy_rdpntr0[1]), - .RDPNTR2(ddrphy_rdpntr0[2]), - .RST(sys_rst), - .SCLK(sys_clk), - .WRPNTR0(ddrphy_wrpntr0[0]), - .WRPNTR1(ddrphy_wrpntr0[1]), - .WRPNTR2(ddrphy_wrpntr0[2]), - .Q0(ddrphy_bitslip2_i[0]), - .Q1(ddrphy_bitslip2_i[1]), - .Q2(ddrphy_bitslip2_i[2]), - .Q3(ddrphy_bitslip2_i[3]) + // Inputs. + .D (ddrphy_dq_i_delayed2), + .DQSR90 (ddrphy_dqsr900), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]), + + // Outputs. + .Q0 (ddrphy_bitslip2_i[0]), + .Q1 (ddrphy_bitslip2_i[1]), + .Q2 (ddrphy_bitslip2_i[2]), + .Q3 (ddrphy_bitslip2_i[3]) ); +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_2 of TSHX2DQA Module. +//------------------------------------------------------------------------------ TSHX2DQA TSHX2DQA_2( - .DQSW270(ddrphy_dqsw2700), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .T0((~ddrphy_dq_oe)), - .T1((~ddrphy_dq_oe)), - .Q(ddrphy_dq_oe_n2) + // Inputs. + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n2) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_4 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ ODDRX2DQA ODDRX2DQA_4( - .D0(ddrphy_dq_o_data_muxed3[0]), - .D1(ddrphy_dq_o_data_muxed3[1]), - .D2(ddrphy_dq_o_data_muxed3[2]), - .D3(ddrphy_dq_o_data_muxed3[3]), - .DQSW270(ddrphy_dqsw2700), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_dq_o3) + // Inputs. + .D0 (ddrphy_dq_o_data_muxed3[0]), + .D1 (ddrphy_dq_o_data_muxed3[1]), + .D2 (ddrphy_dq_o_data_muxed3[2]), + .D3 (ddrphy_dq_o_data_muxed3[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o3) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_29 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_MODE("DQS_ALIGNED_X2") + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") ) DELAYG_29 ( - .A(ddrphy_dq_i3), - .Z(ddrphy_dq_i_delayed3) + // Inputs. + .A (ddrphy_dq_i3), + + // Outputs. + .Z (ddrphy_dq_i_delayed3) ); +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_3 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ IDDRX2DQA IDDRX2DQA_3( - .D(ddrphy_dq_i_delayed3), - .DQSR90(ddrphy_dqsr900), - .ECLK(sys2x_clk), - .RDPNTR0(ddrphy_rdpntr0[0]), - .RDPNTR1(ddrphy_rdpntr0[1]), - .RDPNTR2(ddrphy_rdpntr0[2]), - .RST(sys_rst), - .SCLK(sys_clk), - .WRPNTR0(ddrphy_wrpntr0[0]), - .WRPNTR1(ddrphy_wrpntr0[1]), - .WRPNTR2(ddrphy_wrpntr0[2]), - .Q0(ddrphy_bitslip3_i[0]), - .Q1(ddrphy_bitslip3_i[1]), - .Q2(ddrphy_bitslip3_i[2]), - .Q3(ddrphy_bitslip3_i[3]) + // Inputs. + .D (ddrphy_dq_i_delayed3), + .DQSR90 (ddrphy_dqsr900), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]), + + // Outputs. + .Q0 (ddrphy_bitslip3_i[0]), + .Q1 (ddrphy_bitslip3_i[1]), + .Q2 (ddrphy_bitslip3_i[2]), + .Q3 (ddrphy_bitslip3_i[3]) ); +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_3 of TSHX2DQA Module. +//------------------------------------------------------------------------------ TSHX2DQA TSHX2DQA_3( - .DQSW270(ddrphy_dqsw2700), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .T0((~ddrphy_dq_oe)), - .T1((~ddrphy_dq_oe)), - .Q(ddrphy_dq_oe_n3) + // Inputs. + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n3) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_5 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ ODDRX2DQA ODDRX2DQA_5( - .D0(ddrphy_dq_o_data_muxed4[0]), - .D1(ddrphy_dq_o_data_muxed4[1]), - .D2(ddrphy_dq_o_data_muxed4[2]), - .D3(ddrphy_dq_o_data_muxed4[3]), - .DQSW270(ddrphy_dqsw2700), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_dq_o4) + // Inputs. + .D0 (ddrphy_dq_o_data_muxed4[0]), + .D1 (ddrphy_dq_o_data_muxed4[1]), + .D2 (ddrphy_dq_o_data_muxed4[2]), + .D3 (ddrphy_dq_o_data_muxed4[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o4) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_30 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_MODE("DQS_ALIGNED_X2") + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") ) DELAYG_30 ( - .A(ddrphy_dq_i4), - .Z(ddrphy_dq_i_delayed4) + // Inputs. + .A (ddrphy_dq_i4), + + // Outputs. + .Z (ddrphy_dq_i_delayed4) ); +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_4 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ IDDRX2DQA IDDRX2DQA_4( - .D(ddrphy_dq_i_delayed4), - .DQSR90(ddrphy_dqsr900), - .ECLK(sys2x_clk), - .RDPNTR0(ddrphy_rdpntr0[0]), - .RDPNTR1(ddrphy_rdpntr0[1]), - .RDPNTR2(ddrphy_rdpntr0[2]), - .RST(sys_rst), - .SCLK(sys_clk), - .WRPNTR0(ddrphy_wrpntr0[0]), - .WRPNTR1(ddrphy_wrpntr0[1]), - .WRPNTR2(ddrphy_wrpntr0[2]), - .Q0(ddrphy_bitslip4_i[0]), - .Q1(ddrphy_bitslip4_i[1]), - .Q2(ddrphy_bitslip4_i[2]), - .Q3(ddrphy_bitslip4_i[3]) + // Inputs. + .D (ddrphy_dq_i_delayed4), + .DQSR90 (ddrphy_dqsr900), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]), + + // Outputs. + .Q0 (ddrphy_bitslip4_i[0]), + .Q1 (ddrphy_bitslip4_i[1]), + .Q2 (ddrphy_bitslip4_i[2]), + .Q3 (ddrphy_bitslip4_i[3]) ); +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_4 of TSHX2DQA Module. +//------------------------------------------------------------------------------ TSHX2DQA TSHX2DQA_4( - .DQSW270(ddrphy_dqsw2700), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .T0((~ddrphy_dq_oe)), - .T1((~ddrphy_dq_oe)), - .Q(ddrphy_dq_oe_n4) + // Inputs. + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n4) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_6 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ ODDRX2DQA ODDRX2DQA_6( - .D0(ddrphy_dq_o_data_muxed5[0]), - .D1(ddrphy_dq_o_data_muxed5[1]), - .D2(ddrphy_dq_o_data_muxed5[2]), - .D3(ddrphy_dq_o_data_muxed5[3]), - .DQSW270(ddrphy_dqsw2700), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_dq_o5) + // Inputs. + .D0 (ddrphy_dq_o_data_muxed5[0]), + .D1 (ddrphy_dq_o_data_muxed5[1]), + .D2 (ddrphy_dq_o_data_muxed5[2]), + .D3 (ddrphy_dq_o_data_muxed5[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o5) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_31 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_MODE("DQS_ALIGNED_X2") + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") ) DELAYG_31 ( - .A(ddrphy_dq_i5), - .Z(ddrphy_dq_i_delayed5) + // Inputs. + .A (ddrphy_dq_i5), + + // Outputs. + .Z (ddrphy_dq_i_delayed5) ); +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_5 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ IDDRX2DQA IDDRX2DQA_5( - .D(ddrphy_dq_i_delayed5), - .DQSR90(ddrphy_dqsr900), - .ECLK(sys2x_clk), - .RDPNTR0(ddrphy_rdpntr0[0]), - .RDPNTR1(ddrphy_rdpntr0[1]), - .RDPNTR2(ddrphy_rdpntr0[2]), - .RST(sys_rst), - .SCLK(sys_clk), - .WRPNTR0(ddrphy_wrpntr0[0]), - .WRPNTR1(ddrphy_wrpntr0[1]), - .WRPNTR2(ddrphy_wrpntr0[2]), - .Q0(ddrphy_bitslip5_i[0]), - .Q1(ddrphy_bitslip5_i[1]), - .Q2(ddrphy_bitslip5_i[2]), - .Q3(ddrphy_bitslip5_i[3]) + // Inputs. + .D (ddrphy_dq_i_delayed5), + .DQSR90 (ddrphy_dqsr900), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]), + + // Outputs. + .Q0 (ddrphy_bitslip5_i[0]), + .Q1 (ddrphy_bitslip5_i[1]), + .Q2 (ddrphy_bitslip5_i[2]), + .Q3 (ddrphy_bitslip5_i[3]) ); +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_5 of TSHX2DQA Module. +//------------------------------------------------------------------------------ TSHX2DQA TSHX2DQA_5( - .DQSW270(ddrphy_dqsw2700), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .T0((~ddrphy_dq_oe)), - .T1((~ddrphy_dq_oe)), - .Q(ddrphy_dq_oe_n5) + // Inputs. + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n5) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_7 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ ODDRX2DQA ODDRX2DQA_7( - .D0(ddrphy_dq_o_data_muxed6[0]), - .D1(ddrphy_dq_o_data_muxed6[1]), - .D2(ddrphy_dq_o_data_muxed6[2]), - .D3(ddrphy_dq_o_data_muxed6[3]), - .DQSW270(ddrphy_dqsw2700), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_dq_o6) + // Inputs. + .D0 (ddrphy_dq_o_data_muxed6[0]), + .D1 (ddrphy_dq_o_data_muxed6[1]), + .D2 (ddrphy_dq_o_data_muxed6[2]), + .D3 (ddrphy_dq_o_data_muxed6[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o6) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_32 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_MODE("DQS_ALIGNED_X2") + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") ) DELAYG_32 ( - .A(ddrphy_dq_i6), - .Z(ddrphy_dq_i_delayed6) + // Inputs. + .A (ddrphy_dq_i6), + + // Outputs. + .Z (ddrphy_dq_i_delayed6) ); +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_6 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ IDDRX2DQA IDDRX2DQA_6( - .D(ddrphy_dq_i_delayed6), - .DQSR90(ddrphy_dqsr900), - .ECLK(sys2x_clk), - .RDPNTR0(ddrphy_rdpntr0[0]), - .RDPNTR1(ddrphy_rdpntr0[1]), - .RDPNTR2(ddrphy_rdpntr0[2]), - .RST(sys_rst), - .SCLK(sys_clk), - .WRPNTR0(ddrphy_wrpntr0[0]), - .WRPNTR1(ddrphy_wrpntr0[1]), - .WRPNTR2(ddrphy_wrpntr0[2]), - .Q0(ddrphy_bitslip6_i[0]), - .Q1(ddrphy_bitslip6_i[1]), - .Q2(ddrphy_bitslip6_i[2]), - .Q3(ddrphy_bitslip6_i[3]) + // Inputs. + .D (ddrphy_dq_i_delayed6), + .DQSR90 (ddrphy_dqsr900), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]), + + // Outputs. + .Q0 (ddrphy_bitslip6_i[0]), + .Q1 (ddrphy_bitslip6_i[1]), + .Q2 (ddrphy_bitslip6_i[2]), + .Q3 (ddrphy_bitslip6_i[3]) ); +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_6 of TSHX2DQA Module. +//------------------------------------------------------------------------------ TSHX2DQA TSHX2DQA_6( - .DQSW270(ddrphy_dqsw2700), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .T0((~ddrphy_dq_oe)), - .T1((~ddrphy_dq_oe)), - .Q(ddrphy_dq_oe_n6) + // Inputs. + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n6) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_8 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ ODDRX2DQA ODDRX2DQA_8( - .D0(ddrphy_dq_o_data_muxed7[0]), - .D1(ddrphy_dq_o_data_muxed7[1]), - .D2(ddrphy_dq_o_data_muxed7[2]), - .D3(ddrphy_dq_o_data_muxed7[3]), - .DQSW270(ddrphy_dqsw2700), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_dq_o7) + // Inputs. + .D0 (ddrphy_dq_o_data_muxed7[0]), + .D1 (ddrphy_dq_o_data_muxed7[1]), + .D2 (ddrphy_dq_o_data_muxed7[2]), + .D3 (ddrphy_dq_o_data_muxed7[3]), + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o7) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_33 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_MODE("DQS_ALIGNED_X2") + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") ) DELAYG_33 ( - .A(ddrphy_dq_i7), - .Z(ddrphy_dq_i_delayed7) + // Inputs. + .A (ddrphy_dq_i7), + + // Outputs. + .Z (ddrphy_dq_i_delayed7) ); +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_7 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ IDDRX2DQA IDDRX2DQA_7( - .D(ddrphy_dq_i_delayed7), - .DQSR90(ddrphy_dqsr900), - .ECLK(sys2x_clk), - .RDPNTR0(ddrphy_rdpntr0[0]), - .RDPNTR1(ddrphy_rdpntr0[1]), - .RDPNTR2(ddrphy_rdpntr0[2]), - .RST(sys_rst), - .SCLK(sys_clk), - .WRPNTR0(ddrphy_wrpntr0[0]), - .WRPNTR1(ddrphy_wrpntr0[1]), - .WRPNTR2(ddrphy_wrpntr0[2]), - .Q0(ddrphy_bitslip7_i[0]), - .Q1(ddrphy_bitslip7_i[1]), - .Q2(ddrphy_bitslip7_i[2]), - .Q3(ddrphy_bitslip7_i[3]) + // Inputs. + .D (ddrphy_dq_i_delayed7), + .DQSR90 (ddrphy_dqsr900), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr0[0]), + .RDPNTR1 (ddrphy_rdpntr0[1]), + .RDPNTR2 (ddrphy_rdpntr0[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr0[0]), + .WRPNTR1 (ddrphy_wrpntr0[1]), + .WRPNTR2 (ddrphy_wrpntr0[2]), + + // Outputs. + .Q0 (ddrphy_bitslip7_i[0]), + .Q1 (ddrphy_bitslip7_i[1]), + .Q2 (ddrphy_bitslip7_i[2]), + .Q3 (ddrphy_bitslip7_i[3]) ); +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_7 of TSHX2DQA Module. +//------------------------------------------------------------------------------ TSHX2DQA TSHX2DQA_7( - .DQSW270(ddrphy_dqsw2700), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .T0((~ddrphy_dq_oe)), - .T1((~ddrphy_dq_oe)), - .Q(ddrphy_dq_oe_n7) + // Inputs. + .DQSW270 (ddrphy_dqsw2700), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n7) ); +//------------------------------------------------------------------------------ +// Instance DQSBUFM_1 of DQSBUFM Module. +//------------------------------------------------------------------------------ DQSBUFM #( - .DQS_LI_DEL_ADJ("MINUS"), - .DQS_LI_DEL_VAL(1'd1), - .DQS_LO_DEL_ADJ("MINUS"), - .DQS_LO_DEL_VAL(3'd4) + // Parameters. + .DQS_LI_DEL_ADJ ("MINUS"), + .DQS_LI_DEL_VAL (1'd1), + .DQS_LO_DEL_ADJ ("MINUS"), + .DQS_LO_DEL_VAL (3'd4) ) DQSBUFM_1 ( - .DDRDEL(ddrphy_delay0), - .DQSI(ddrphy_dqs_i1), - .ECLK(sys2x_clk), - .PAUSE((ddrphy_pause0 | ddrphy_dly_sel_storage[1])), - .RDDIRECTION(1'd1), - .RDLOADN(1'd0), - .RDMOVE(1'd0), - .READ0(ddrphy_dqs_re), - .READ1(ddrphy_dqs_re), - .READCLKSEL0(ddrphy_rdly1[0]), - .READCLKSEL1(ddrphy_rdly1[1]), - .READCLKSEL2(ddrphy_rdly1[2]), - .RST(sys_rst), - .SCLK(sys_clk), - .WRDIRECTION(1'd1), - .WRLOADN(1'd0), - .WRMOVE(1'd0), - .BURSTDET(ddrphy_burstdet1), - .DATAVALID(ddrphy_datavalid[1]), - .DQSR90(ddrphy_dqsr901), - .DQSW(ddrphy_dqsw1), - .DQSW270(ddrphy_dqsw2701), - .RDPNTR0(ddrphy_rdpntr1[0]), - .RDPNTR1(ddrphy_rdpntr1[1]), - .RDPNTR2(ddrphy_rdpntr1[2]), - .WRPNTR0(ddrphy_wrpntr1[0]), - .WRPNTR1(ddrphy_wrpntr1[1]), - .WRPNTR2(ddrphy_wrpntr1[2]) + // Inputs. + .DDRDEL (ddrphy_delay0), + .DQSI (ddrphy_dqs_i1), + .ECLK (sys2x_clk), + .PAUSE ((ddrphy_pause0 | ddrphy_dly_sel_storage[1])), + .RDDIRECTION (1'd1), + .RDLOADN (1'd0), + .RDMOVE (1'd0), + .READ0 (ddrphy_dqs_re), + .READ1 (ddrphy_dqs_re), + .READCLKSEL0 (ddrphy_rdly1[0]), + .READCLKSEL1 (ddrphy_rdly1[1]), + .READCLKSEL2 (ddrphy_rdly1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRDIRECTION (1'd1), + .WRLOADN (1'd0), + .WRMOVE (1'd0), + + // Outputs. + .BURSTDET (ddrphy_burstdet1), + .DATAVALID (ddrphy_datavalid[1]), + .DQSR90 (ddrphy_dqsr901), + .DQSW (ddrphy_dqsw1), + .DQSW270 (ddrphy_dqsw2701), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2DQSB_1 of ODDRX2DQSB Module. +//------------------------------------------------------------------------------ ODDRX2DQSB ODDRX2DQSB_1( - .D0(1'd0), - .D1(1'd1), - .D2(1'd0), - .D3(1'd1), - .DQSW(ddrphy_dqsw1), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_dqs1) + // Inputs. + .D0 (1'd0), + .D1 (1'd1), + .D2 (1'd0), + .D3 (1'd1), + .DQSW (ddrphy_dqsw1), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dqs1) ); +//------------------------------------------------------------------------------ +// Instance TSHX2DQSA_1 of TSHX2DQSA Module. +//------------------------------------------------------------------------------ TSHX2DQSA TSHX2DQSA_1( - .DQSW(ddrphy_dqsw1), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .T0((~(ddrphy_dqs_oe | ddrphy_dqs_postamble))), - .T1((~(ddrphy_dqs_oe | ddrphy_dqs_preamble))), - .Q(ddrphy_dqs_oe_n1) + // Inputs. + .DQSW (ddrphy_dqsw1), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~(ddrphy_dqs_oe | ddrphy_dqs_postamble))), + .T1 ((~(ddrphy_dqs_oe | ddrphy_dqs_preamble))), + + // Outputs. + .Q (ddrphy_dqs_oe_n1) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_9 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ ODDRX2DQA ODDRX2DQA_9( - .D0(ddrphy_dm_o_data_muxed1[0]), - .D1(ddrphy_dm_o_data_muxed1[1]), - .D2(ddrphy_dm_o_data_muxed1[2]), - .D3(ddrphy_dm_o_data_muxed1[3]), - .DQSW270(ddrphy_dqsw2701), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddram_dm[1]) + // Inputs. + .D0 (ddrphy_dm_o_data_muxed1[0]), + .D1 (ddrphy_dm_o_data_muxed1[1]), + .D2 (ddrphy_dm_o_data_muxed1[2]), + .D3 (ddrphy_dm_o_data_muxed1[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddram_dm[1]) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_10 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ ODDRX2DQA ODDRX2DQA_10( - .D0(ddrphy_dq_o_data_muxed8[0]), - .D1(ddrphy_dq_o_data_muxed8[1]), - .D2(ddrphy_dq_o_data_muxed8[2]), - .D3(ddrphy_dq_o_data_muxed8[3]), - .DQSW270(ddrphy_dqsw2701), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_dq_o8) + // Inputs. + .D0 (ddrphy_dq_o_data_muxed8[0]), + .D1 (ddrphy_dq_o_data_muxed8[1]), + .D2 (ddrphy_dq_o_data_muxed8[2]), + .D3 (ddrphy_dq_o_data_muxed8[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o8) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_34 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_MODE("DQS_ALIGNED_X2") + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") ) DELAYG_34 ( - .A(ddrphy_dq_i8), - .Z(ddrphy_dq_i_delayed8) + // Inputs. + .A (ddrphy_dq_i8), + + // Outputs. + .Z (ddrphy_dq_i_delayed8) ); +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_8 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ IDDRX2DQA IDDRX2DQA_8( - .D(ddrphy_dq_i_delayed8), - .DQSR90(ddrphy_dqsr901), - .ECLK(sys2x_clk), - .RDPNTR0(ddrphy_rdpntr1[0]), - .RDPNTR1(ddrphy_rdpntr1[1]), - .RDPNTR2(ddrphy_rdpntr1[2]), - .RST(sys_rst), - .SCLK(sys_clk), - .WRPNTR0(ddrphy_wrpntr1[0]), - .WRPNTR1(ddrphy_wrpntr1[1]), - .WRPNTR2(ddrphy_wrpntr1[2]), - .Q0(ddrphy_bitslip8_i[0]), - .Q1(ddrphy_bitslip8_i[1]), - .Q2(ddrphy_bitslip8_i[2]), - .Q3(ddrphy_bitslip8_i[3]) + // Inputs. + .D (ddrphy_dq_i_delayed8), + .DQSR90 (ddrphy_dqsr901), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]), + + // Outputs. + .Q0 (ddrphy_bitslip8_i[0]), + .Q1 (ddrphy_bitslip8_i[1]), + .Q2 (ddrphy_bitslip8_i[2]), + .Q3 (ddrphy_bitslip8_i[3]) ); +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_8 of TSHX2DQA Module. +//------------------------------------------------------------------------------ TSHX2DQA TSHX2DQA_8( - .DQSW270(ddrphy_dqsw2701), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .T0((~ddrphy_dq_oe)), - .T1((~ddrphy_dq_oe)), - .Q(ddrphy_dq_oe_n8) + // Inputs. + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n8) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_11 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ ODDRX2DQA ODDRX2DQA_11( - .D0(ddrphy_dq_o_data_muxed9[0]), - .D1(ddrphy_dq_o_data_muxed9[1]), - .D2(ddrphy_dq_o_data_muxed9[2]), - .D3(ddrphy_dq_o_data_muxed9[3]), - .DQSW270(ddrphy_dqsw2701), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_dq_o9) + // Inputs. + .D0 (ddrphy_dq_o_data_muxed9[0]), + .D1 (ddrphy_dq_o_data_muxed9[1]), + .D2 (ddrphy_dq_o_data_muxed9[2]), + .D3 (ddrphy_dq_o_data_muxed9[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o9) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_35 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_MODE("DQS_ALIGNED_X2") + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") ) DELAYG_35 ( - .A(ddrphy_dq_i9), - .Z(ddrphy_dq_i_delayed9) + // Inputs. + .A (ddrphy_dq_i9), + + // Outputs. + .Z (ddrphy_dq_i_delayed9) ); +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_9 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ IDDRX2DQA IDDRX2DQA_9( - .D(ddrphy_dq_i_delayed9), - .DQSR90(ddrphy_dqsr901), - .ECLK(sys2x_clk), - .RDPNTR0(ddrphy_rdpntr1[0]), - .RDPNTR1(ddrphy_rdpntr1[1]), - .RDPNTR2(ddrphy_rdpntr1[2]), - .RST(sys_rst), - .SCLK(sys_clk), - .WRPNTR0(ddrphy_wrpntr1[0]), - .WRPNTR1(ddrphy_wrpntr1[1]), - .WRPNTR2(ddrphy_wrpntr1[2]), - .Q0(ddrphy_bitslip9_i[0]), - .Q1(ddrphy_bitslip9_i[1]), - .Q2(ddrphy_bitslip9_i[2]), - .Q3(ddrphy_bitslip9_i[3]) + // Inputs. + .D (ddrphy_dq_i_delayed9), + .DQSR90 (ddrphy_dqsr901), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]), + + // Outputs. + .Q0 (ddrphy_bitslip9_i[0]), + .Q1 (ddrphy_bitslip9_i[1]), + .Q2 (ddrphy_bitslip9_i[2]), + .Q3 (ddrphy_bitslip9_i[3]) ); +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_9 of TSHX2DQA Module. +//------------------------------------------------------------------------------ TSHX2DQA TSHX2DQA_9( - .DQSW270(ddrphy_dqsw2701), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .T0((~ddrphy_dq_oe)), - .T1((~ddrphy_dq_oe)), - .Q(ddrphy_dq_oe_n9) + // Inputs. + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n9) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_12 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ ODDRX2DQA ODDRX2DQA_12( - .D0(ddrphy_dq_o_data_muxed10[0]), - .D1(ddrphy_dq_o_data_muxed10[1]), - .D2(ddrphy_dq_o_data_muxed10[2]), - .D3(ddrphy_dq_o_data_muxed10[3]), - .DQSW270(ddrphy_dqsw2701), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_dq_o10) + // Inputs. + .D0 (ddrphy_dq_o_data_muxed10[0]), + .D1 (ddrphy_dq_o_data_muxed10[1]), + .D2 (ddrphy_dq_o_data_muxed10[2]), + .D3 (ddrphy_dq_o_data_muxed10[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o10) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_36 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_MODE("DQS_ALIGNED_X2") + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") ) DELAYG_36 ( - .A(ddrphy_dq_i10), - .Z(ddrphy_dq_i_delayed10) + // Inputs. + .A (ddrphy_dq_i10), + + // Outputs. + .Z (ddrphy_dq_i_delayed10) ); +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_10 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ IDDRX2DQA IDDRX2DQA_10( - .D(ddrphy_dq_i_delayed10), - .DQSR90(ddrphy_dqsr901), - .ECLK(sys2x_clk), - .RDPNTR0(ddrphy_rdpntr1[0]), - .RDPNTR1(ddrphy_rdpntr1[1]), - .RDPNTR2(ddrphy_rdpntr1[2]), - .RST(sys_rst), - .SCLK(sys_clk), - .WRPNTR0(ddrphy_wrpntr1[0]), - .WRPNTR1(ddrphy_wrpntr1[1]), - .WRPNTR2(ddrphy_wrpntr1[2]), - .Q0(ddrphy_bitslip10_i[0]), - .Q1(ddrphy_bitslip10_i[1]), - .Q2(ddrphy_bitslip10_i[2]), - .Q3(ddrphy_bitslip10_i[3]) + // Inputs. + .D (ddrphy_dq_i_delayed10), + .DQSR90 (ddrphy_dqsr901), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]), + + // Outputs. + .Q0 (ddrphy_bitslip10_i[0]), + .Q1 (ddrphy_bitslip10_i[1]), + .Q2 (ddrphy_bitslip10_i[2]), + .Q3 (ddrphy_bitslip10_i[3]) ); +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_10 of TSHX2DQA Module. +//------------------------------------------------------------------------------ TSHX2DQA TSHX2DQA_10( - .DQSW270(ddrphy_dqsw2701), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .T0((~ddrphy_dq_oe)), - .T1((~ddrphy_dq_oe)), - .Q(ddrphy_dq_oe_n10) + // Inputs. + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n10) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_13 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ ODDRX2DQA ODDRX2DQA_13( - .D0(ddrphy_dq_o_data_muxed11[0]), - .D1(ddrphy_dq_o_data_muxed11[1]), - .D2(ddrphy_dq_o_data_muxed11[2]), - .D3(ddrphy_dq_o_data_muxed11[3]), - .DQSW270(ddrphy_dqsw2701), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_dq_o11) + // Inputs. + .D0 (ddrphy_dq_o_data_muxed11[0]), + .D1 (ddrphy_dq_o_data_muxed11[1]), + .D2 (ddrphy_dq_o_data_muxed11[2]), + .D3 (ddrphy_dq_o_data_muxed11[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o11) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_37 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_MODE("DQS_ALIGNED_X2") + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") ) DELAYG_37 ( - .A(ddrphy_dq_i11), - .Z(ddrphy_dq_i_delayed11) + // Inputs. + .A (ddrphy_dq_i11), + + // Outputs. + .Z (ddrphy_dq_i_delayed11) ); +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_11 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ IDDRX2DQA IDDRX2DQA_11( - .D(ddrphy_dq_i_delayed11), - .DQSR90(ddrphy_dqsr901), - .ECLK(sys2x_clk), - .RDPNTR0(ddrphy_rdpntr1[0]), - .RDPNTR1(ddrphy_rdpntr1[1]), - .RDPNTR2(ddrphy_rdpntr1[2]), - .RST(sys_rst), - .SCLK(sys_clk), - .WRPNTR0(ddrphy_wrpntr1[0]), - .WRPNTR1(ddrphy_wrpntr1[1]), - .WRPNTR2(ddrphy_wrpntr1[2]), - .Q0(ddrphy_bitslip11_i[0]), - .Q1(ddrphy_bitslip11_i[1]), - .Q2(ddrphy_bitslip11_i[2]), - .Q3(ddrphy_bitslip11_i[3]) + // Inputs. + .D (ddrphy_dq_i_delayed11), + .DQSR90 (ddrphy_dqsr901), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]), + + // Outputs. + .Q0 (ddrphy_bitslip11_i[0]), + .Q1 (ddrphy_bitslip11_i[1]), + .Q2 (ddrphy_bitslip11_i[2]), + .Q3 (ddrphy_bitslip11_i[3]) ); +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_11 of TSHX2DQA Module. +//------------------------------------------------------------------------------ TSHX2DQA TSHX2DQA_11( - .DQSW270(ddrphy_dqsw2701), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .T0((~ddrphy_dq_oe)), - .T1((~ddrphy_dq_oe)), - .Q(ddrphy_dq_oe_n11) + // Inputs. + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n11) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_14 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ ODDRX2DQA ODDRX2DQA_14( - .D0(ddrphy_dq_o_data_muxed12[0]), - .D1(ddrphy_dq_o_data_muxed12[1]), - .D2(ddrphy_dq_o_data_muxed12[2]), - .D3(ddrphy_dq_o_data_muxed12[3]), - .DQSW270(ddrphy_dqsw2701), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_dq_o12) + // Inputs. + .D0 (ddrphy_dq_o_data_muxed12[0]), + .D1 (ddrphy_dq_o_data_muxed12[1]), + .D2 (ddrphy_dq_o_data_muxed12[2]), + .D3 (ddrphy_dq_o_data_muxed12[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o12) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_38 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_MODE("DQS_ALIGNED_X2") + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") ) DELAYG_38 ( - .A(ddrphy_dq_i12), - .Z(ddrphy_dq_i_delayed12) + // Inputs. + .A (ddrphy_dq_i12), + + // Outputs. + .Z (ddrphy_dq_i_delayed12) ); +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_12 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ IDDRX2DQA IDDRX2DQA_12( - .D(ddrphy_dq_i_delayed12), - .DQSR90(ddrphy_dqsr901), - .ECLK(sys2x_clk), - .RDPNTR0(ddrphy_rdpntr1[0]), - .RDPNTR1(ddrphy_rdpntr1[1]), - .RDPNTR2(ddrphy_rdpntr1[2]), - .RST(sys_rst), - .SCLK(sys_clk), - .WRPNTR0(ddrphy_wrpntr1[0]), - .WRPNTR1(ddrphy_wrpntr1[1]), - .WRPNTR2(ddrphy_wrpntr1[2]), - .Q0(ddrphy_bitslip12_i[0]), - .Q1(ddrphy_bitslip12_i[1]), - .Q2(ddrphy_bitslip12_i[2]), - .Q3(ddrphy_bitslip12_i[3]) + // Inputs. + .D (ddrphy_dq_i_delayed12), + .DQSR90 (ddrphy_dqsr901), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]), + + // Outputs. + .Q0 (ddrphy_bitslip12_i[0]), + .Q1 (ddrphy_bitslip12_i[1]), + .Q2 (ddrphy_bitslip12_i[2]), + .Q3 (ddrphy_bitslip12_i[3]) ); +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_12 of TSHX2DQA Module. +//------------------------------------------------------------------------------ TSHX2DQA TSHX2DQA_12( - .DQSW270(ddrphy_dqsw2701), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .T0((~ddrphy_dq_oe)), - .T1((~ddrphy_dq_oe)), - .Q(ddrphy_dq_oe_n12) + // Inputs. + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n12) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_15 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ ODDRX2DQA ODDRX2DQA_15( - .D0(ddrphy_dq_o_data_muxed13[0]), - .D1(ddrphy_dq_o_data_muxed13[1]), - .D2(ddrphy_dq_o_data_muxed13[2]), - .D3(ddrphy_dq_o_data_muxed13[3]), - .DQSW270(ddrphy_dqsw2701), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_dq_o13) + // Inputs. + .D0 (ddrphy_dq_o_data_muxed13[0]), + .D1 (ddrphy_dq_o_data_muxed13[1]), + .D2 (ddrphy_dq_o_data_muxed13[2]), + .D3 (ddrphy_dq_o_data_muxed13[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o13) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_39 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_MODE("DQS_ALIGNED_X2") + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") ) DELAYG_39 ( - .A(ddrphy_dq_i13), - .Z(ddrphy_dq_i_delayed13) + // Inputs. + .A (ddrphy_dq_i13), + + // Outputs. + .Z (ddrphy_dq_i_delayed13) ); +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_13 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ IDDRX2DQA IDDRX2DQA_13( - .D(ddrphy_dq_i_delayed13), - .DQSR90(ddrphy_dqsr901), - .ECLK(sys2x_clk), - .RDPNTR0(ddrphy_rdpntr1[0]), - .RDPNTR1(ddrphy_rdpntr1[1]), - .RDPNTR2(ddrphy_rdpntr1[2]), - .RST(sys_rst), - .SCLK(sys_clk), - .WRPNTR0(ddrphy_wrpntr1[0]), - .WRPNTR1(ddrphy_wrpntr1[1]), - .WRPNTR2(ddrphy_wrpntr1[2]), - .Q0(ddrphy_bitslip13_i[0]), - .Q1(ddrphy_bitslip13_i[1]), - .Q2(ddrphy_bitslip13_i[2]), - .Q3(ddrphy_bitslip13_i[3]) + // Inputs. + .D (ddrphy_dq_i_delayed13), + .DQSR90 (ddrphy_dqsr901), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]), + + // Outputs. + .Q0 (ddrphy_bitslip13_i[0]), + .Q1 (ddrphy_bitslip13_i[1]), + .Q2 (ddrphy_bitslip13_i[2]), + .Q3 (ddrphy_bitslip13_i[3]) ); +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_13 of TSHX2DQA Module. +//------------------------------------------------------------------------------ TSHX2DQA TSHX2DQA_13( - .DQSW270(ddrphy_dqsw2701), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .T0((~ddrphy_dq_oe)), - .T1((~ddrphy_dq_oe)), - .Q(ddrphy_dq_oe_n13) + // Inputs. + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n13) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_16 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ ODDRX2DQA ODDRX2DQA_16( - .D0(ddrphy_dq_o_data_muxed14[0]), - .D1(ddrphy_dq_o_data_muxed14[1]), - .D2(ddrphy_dq_o_data_muxed14[2]), - .D3(ddrphy_dq_o_data_muxed14[3]), - .DQSW270(ddrphy_dqsw2701), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_dq_o14) + // Inputs. + .D0 (ddrphy_dq_o_data_muxed14[0]), + .D1 (ddrphy_dq_o_data_muxed14[1]), + .D2 (ddrphy_dq_o_data_muxed14[2]), + .D3 (ddrphy_dq_o_data_muxed14[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o14) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_40 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_MODE("DQS_ALIGNED_X2") + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") ) DELAYG_40 ( - .A(ddrphy_dq_i14), - .Z(ddrphy_dq_i_delayed14) + // Inputs. + .A (ddrphy_dq_i14), + + // Outputs. + .Z (ddrphy_dq_i_delayed14) ); +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_14 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ IDDRX2DQA IDDRX2DQA_14( - .D(ddrphy_dq_i_delayed14), - .DQSR90(ddrphy_dqsr901), - .ECLK(sys2x_clk), - .RDPNTR0(ddrphy_rdpntr1[0]), - .RDPNTR1(ddrphy_rdpntr1[1]), - .RDPNTR2(ddrphy_rdpntr1[2]), - .RST(sys_rst), - .SCLK(sys_clk), - .WRPNTR0(ddrphy_wrpntr1[0]), - .WRPNTR1(ddrphy_wrpntr1[1]), - .WRPNTR2(ddrphy_wrpntr1[2]), - .Q0(ddrphy_bitslip14_i[0]), - .Q1(ddrphy_bitslip14_i[1]), - .Q2(ddrphy_bitslip14_i[2]), - .Q3(ddrphy_bitslip14_i[3]) + // Inputs. + .D (ddrphy_dq_i_delayed14), + .DQSR90 (ddrphy_dqsr901), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]), + + // Outputs. + .Q0 (ddrphy_bitslip14_i[0]), + .Q1 (ddrphy_bitslip14_i[1]), + .Q2 (ddrphy_bitslip14_i[2]), + .Q3 (ddrphy_bitslip14_i[3]) ); +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_14 of TSHX2DQA Module. +//------------------------------------------------------------------------------ TSHX2DQA TSHX2DQA_14( - .DQSW270(ddrphy_dqsw2701), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .T0((~ddrphy_dq_oe)), - .T1((~ddrphy_dq_oe)), - .Q(ddrphy_dq_oe_n14) + // Inputs. + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n14) ); +//------------------------------------------------------------------------------ +// Instance ODDRX2DQA_17 of ODDRX2DQA Module. +//------------------------------------------------------------------------------ ODDRX2DQA ODDRX2DQA_17( - .D0(ddrphy_dq_o_data_muxed15[0]), - .D1(ddrphy_dq_o_data_muxed15[1]), - .D2(ddrphy_dq_o_data_muxed15[2]), - .D3(ddrphy_dq_o_data_muxed15[3]), - .DQSW270(ddrphy_dqsw2701), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .Q(ddrphy_dq_o15) + // Inputs. + .D0 (ddrphy_dq_o_data_muxed15[0]), + .D1 (ddrphy_dq_o_data_muxed15[1]), + .D2 (ddrphy_dq_o_data_muxed15[2]), + .D3 (ddrphy_dq_o_data_muxed15[3]), + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + + // Outputs. + .Q (ddrphy_dq_o15) ); +//------------------------------------------------------------------------------ +// Instance DELAYG_41 of DELAYG Module. +//------------------------------------------------------------------------------ DELAYG #( - .DEL_MODE("DQS_ALIGNED_X2") + // Parameters. + .DEL_MODE ("DQS_ALIGNED_X2") ) DELAYG_41 ( - .A(ddrphy_dq_i15), - .Z(ddrphy_dq_i_delayed15) + // Inputs. + .A (ddrphy_dq_i15), + + // Outputs. + .Z (ddrphy_dq_i_delayed15) ); +//------------------------------------------------------------------------------ +// Instance IDDRX2DQA_15 of IDDRX2DQA Module. +//------------------------------------------------------------------------------ IDDRX2DQA IDDRX2DQA_15( - .D(ddrphy_dq_i_delayed15), - .DQSR90(ddrphy_dqsr901), - .ECLK(sys2x_clk), - .RDPNTR0(ddrphy_rdpntr1[0]), - .RDPNTR1(ddrphy_rdpntr1[1]), - .RDPNTR2(ddrphy_rdpntr1[2]), - .RST(sys_rst), - .SCLK(sys_clk), - .WRPNTR0(ddrphy_wrpntr1[0]), - .WRPNTR1(ddrphy_wrpntr1[1]), - .WRPNTR2(ddrphy_wrpntr1[2]), - .Q0(ddrphy_bitslip15_i[0]), - .Q1(ddrphy_bitslip15_i[1]), - .Q2(ddrphy_bitslip15_i[2]), - .Q3(ddrphy_bitslip15_i[3]) + // Inputs. + .D (ddrphy_dq_i_delayed15), + .DQSR90 (ddrphy_dqsr901), + .ECLK (sys2x_clk), + .RDPNTR0 (ddrphy_rdpntr1[0]), + .RDPNTR1 (ddrphy_rdpntr1[1]), + .RDPNTR2 (ddrphy_rdpntr1[2]), + .RST (sys_rst), + .SCLK (sys_clk), + .WRPNTR0 (ddrphy_wrpntr1[0]), + .WRPNTR1 (ddrphy_wrpntr1[1]), + .WRPNTR2 (ddrphy_wrpntr1[2]), + + // Outputs. + .Q0 (ddrphy_bitslip15_i[0]), + .Q1 (ddrphy_bitslip15_i[1]), + .Q2 (ddrphy_bitslip15_i[2]), + .Q3 (ddrphy_bitslip15_i[3]) ); +//------------------------------------------------------------------------------ +// Instance TSHX2DQA_15 of TSHX2DQA Module. +//------------------------------------------------------------------------------ TSHX2DQA TSHX2DQA_15( - .DQSW270(ddrphy_dqsw2701), - .ECLK(sys2x_clk), - .RST(sys_rst), - .SCLK(sys_clk), - .T0((~ddrphy_dq_oe)), - .T1((~ddrphy_dq_oe)), - .Q(ddrphy_dq_oe_n15) + // Inputs. + .DQSW270 (ddrphy_dqsw2701), + .ECLK (sys2x_clk), + .RST (sys_rst), + .SCLK (sys_clk), + .T0 ((~ddrphy_dq_oe)), + .T1 ((~ddrphy_dq_oe)), + + // Outputs. + .Q (ddrphy_dq_oe_n15) ); //------------------------------------------------------------------------------ @@ -13353,252 +14537,433 @@ assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachi (* FREQUENCY_PIN_CLKI = "48.0", FREQUENCY_PIN_CLKOP = "96.0", FREQUENCY_PIN_CLKOS = "24.0", ICP_CURRENT = "6", LPF_RESISTOR = "16", MFG_ENABLE_FILTEROPAMP = "1", MFG_GMCREF_SEL = "2" *) +//------------------------------------------------------------------------------ +// Instance EHXPLLL of EHXPLLL Module. +//------------------------------------------------------------------------------ EHXPLLL #( - .CLKFB_DIV(4'd10), - .CLKI_DIV(1'd1), - .CLKOP_CPHASE(3'd4), - .CLKOP_DIV(3'd5), - .CLKOP_ENABLE("ENABLED"), - .CLKOP_FPHASE(1'd0), - .CLKOS2_CPHASE(1'd0), - .CLKOS2_DIV(1'd1), - .CLKOS2_ENABLE("ENABLED"), - .CLKOS2_FPHASE(1'd0), - .CLKOS_CPHASE(5'd19), - .CLKOS_DIV(5'd20), - .CLKOS_ENABLE("ENABLED"), - .CLKOS_FPHASE(1'd0), - .FEEDBK_PATH("INT_OS2") + // Parameters. + .CLKFB_DIV (4'd10), + .CLKI_DIV (1'd1), + .CLKOP_CPHASE (3'd4), + .CLKOP_DIV (3'd5), + .CLKOP_ENABLE ("ENABLED"), + .CLKOP_FPHASE (1'd0), + .CLKOS2_CPHASE (1'd0), + .CLKOS2_DIV (1'd1), + .CLKOS2_ENABLE ("ENABLED"), + .CLKOS2_FPHASE (1'd0), + .CLKOS_CPHASE (5'd19), + .CLKOS_DIV (5'd20), + .CLKOS_ENABLE ("ENABLED"), + .CLKOS_FPHASE (1'd0), + .FEEDBK_PATH ("INT_OS2") ) EHXPLLL ( - .CLKI(crg_clkin), - .RST(crg_reset1), - .STDBY(crg_stdby), - .CLKOP(crg_clkout0), - .CLKOS(crg_clkout1), - .CLKOS2(litedramcore_litedramecp5ddrphycrg_ecp5pll), - .LOCK(litedramcore_litedramecp5ddrphycrg_locked) + // Inputs. + .CLKI (crg_clkin), + .RST (crg_reset1), + .STDBY (crg_stdby), + + // Outputs. + .CLKOP (crg_clkout0), + .CLKOS (crg_clkout1), + .CLKOS2 (litedramecp5ddrphycrg_ecp5pll), + .LOCK (litedramecp5ddrphycrg_locked) ); +//------------------------------------------------------------------------------ +// Instance FD1S3BX of FD1S3BX Module. +//------------------------------------------------------------------------------ FD1S3BX FD1S3BX( - .CK(sys2x_i_clk), - .D(1'd0), - .PD((~crg_locked)), - .Q(latticeecp5asyncresetsynchronizerimpl0_rst1) + // Inputs. + .CK (sys2x_i_clk), + .D (1'd0), + .PD ((~crg_locked)), + + // Outputs. + .Q (latticeecp5asyncresetsynchronizerimpl0_rst1) ); +//------------------------------------------------------------------------------ +// Instance FD1S3BX_1 of FD1S3BX Module. +//------------------------------------------------------------------------------ FD1S3BX FD1S3BX_1( - .CK(sys2x_i_clk), - .D(latticeecp5asyncresetsynchronizerimpl0_rst1), - .PD((~crg_locked)), - .Q(latticeecp5asyncresetsynchronizerimpl0_expr) + // Inputs. + .CK (sys2x_i_clk), + .D (latticeecp5asyncresetsynchronizerimpl0_rst1), + .PD ((~crg_locked)), + + // Outputs. + .Q (latticeecp5asyncresetsynchronizerimpl0_expr) ); +//------------------------------------------------------------------------------ +// Instance FD1S3BX_2 of FD1S3BX Module. +//------------------------------------------------------------------------------ FD1S3BX FD1S3BX_2( - .CK(init_clk), - .D(1'd0), - .PD((~crg_locked)), - .Q(latticeecp5asyncresetsynchronizerimpl1_rst1) + // Inputs. + .CK (init_clk), + .D (1'd0), + .PD ((~crg_locked)), + + // Outputs. + .Q (latticeecp5asyncresetsynchronizerimpl1_rst1) ); +//------------------------------------------------------------------------------ +// Instance FD1S3BX_3 of FD1S3BX Module. +//------------------------------------------------------------------------------ FD1S3BX FD1S3BX_3( - .CK(init_clk), - .D(latticeecp5asyncresetsynchronizerimpl1_rst1), - .PD((~crg_locked)), - .Q(init_rst) + // Inputs. + .CK (init_clk), + .D (latticeecp5asyncresetsynchronizerimpl1_rst1), + .PD ((~crg_locked)), + + // Outputs. + .Q (init_rst) ); +//------------------------------------------------------------------------------ +// Instance FD1S3BX_4 of FD1S3BX Module. +//------------------------------------------------------------------------------ FD1S3BX FD1S3BX_4( - .CK(sys_clk), - .D(1'd0), - .PD(((~crg_locked) | crg_reset0)), - .Q(latticeecp5asyncresetsynchronizerimpl2_rst1) + // Inputs. + .CK (sys_clk), + .D (1'd0), + .PD (((~crg_locked) | crg_reset0)), + + // Outputs. + .Q (latticeecp5asyncresetsynchronizerimpl2_rst1) ); +//------------------------------------------------------------------------------ +// Instance FD1S3BX_5 of FD1S3BX Module. +//------------------------------------------------------------------------------ FD1S3BX FD1S3BX_5( - .CK(sys_clk), - .D(latticeecp5asyncresetsynchronizerimpl2_rst1), - .PD(((~crg_locked) | crg_reset0)), - .Q(sys_rst) + // Inputs. + .CK (sys_clk), + .D (latticeecp5asyncresetsynchronizerimpl2_rst1), + .PD (((~crg_locked) | crg_reset0)), + + // Outputs. + .Q (sys_rst) ); +//------------------------------------------------------------------------------ +// Instance FD1S3BX_6 of FD1S3BX Module. +//------------------------------------------------------------------------------ FD1S3BX FD1S3BX_6( - .CK(sys2x_clk), - .D(1'd0), - .PD(((~crg_locked) | crg_reset0)), - .Q(latticeecp5asyncresetsynchronizerimpl3_rst1) + // Inputs. + .CK (sys2x_clk), + .D (1'd0), + .PD (((~crg_locked) | crg_reset0)), + + // Outputs. + .Q (latticeecp5asyncresetsynchronizerimpl3_rst1) ); +//------------------------------------------------------------------------------ +// Instance FD1S3BX_7 of FD1S3BX Module. +//------------------------------------------------------------------------------ FD1S3BX FD1S3BX_7( - .CK(sys2x_clk), - .D(latticeecp5asyncresetsynchronizerimpl3_rst1), - .PD(((~crg_locked) | crg_reset0)), - .Q(sys2x_rst) + // Inputs. + .CK (sys2x_clk), + .D (latticeecp5asyncresetsynchronizerimpl3_rst1), + .PD (((~crg_locked) | crg_reset0)), + + // Outputs. + .Q (sys2x_rst) ); +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO of TRELLIS_IO Module. +//------------------------------------------------------------------------------ TRELLIS_IO #( - .DIR("BIDIR") + // Parameters. + .DIR ("BIDIR") ) TRELLIS_IO ( - .B(ddram_dqs_p[0]), - .I(ddrphy_dqs0), - .T((~(~ddrphy_dqs_oe_n0))), - .O(ddrphy_dqs_i0) + // Inputs. + .B (ddram_dqs_p[0]), + .I (ddrphy_dqs0), + .T ((~(~ddrphy_dqs_oe_n0))), + + // Outputs. + .O (ddrphy_dqs_i0) ); +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_1 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ TRELLIS_IO #( - .DIR("BIDIR") + // Parameters. + .DIR ("BIDIR") ) TRELLIS_IO_1 ( - .B(ddram_dq[0]), - .I(ddrphy_dq_o0), - .T((~(~ddrphy_dq_oe_n0))), - .O(ddrphy_dq_i0) + // Inputs. + .B (ddram_dq[0]), + .I (ddrphy_dq_o0), + .T ((~(~ddrphy_dq_oe_n0))), + + // Outputs. + .O (ddrphy_dq_i0) ); +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_2 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ TRELLIS_IO #( - .DIR("BIDIR") + // Parameters. + .DIR ("BIDIR") ) TRELLIS_IO_2 ( - .B(ddram_dq[1]), - .I(ddrphy_dq_o1), - .T((~(~ddrphy_dq_oe_n1))), - .O(ddrphy_dq_i1) + // Inputs. + .B (ddram_dq[1]), + .I (ddrphy_dq_o1), + .T ((~(~ddrphy_dq_oe_n1))), + + // Outputs. + .O (ddrphy_dq_i1) ); +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_3 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ TRELLIS_IO #( - .DIR("BIDIR") + // Parameters. + .DIR ("BIDIR") ) TRELLIS_IO_3 ( - .B(ddram_dq[2]), - .I(ddrphy_dq_o2), - .T((~(~ddrphy_dq_oe_n2))), - .O(ddrphy_dq_i2) + // Inputs. + .B (ddram_dq[2]), + .I (ddrphy_dq_o2), + .T ((~(~ddrphy_dq_oe_n2))), + + // Outputs. + .O (ddrphy_dq_i2) ); +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_4 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ TRELLIS_IO #( - .DIR("BIDIR") + // Parameters. + .DIR ("BIDIR") ) TRELLIS_IO_4 ( - .B(ddram_dq[3]), - .I(ddrphy_dq_o3), - .T((~(~ddrphy_dq_oe_n3))), - .O(ddrphy_dq_i3) + // Inputs. + .B (ddram_dq[3]), + .I (ddrphy_dq_o3), + .T ((~(~ddrphy_dq_oe_n3))), + + // Outputs. + .O (ddrphy_dq_i3) ); +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_5 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ TRELLIS_IO #( - .DIR("BIDIR") + // Parameters. + .DIR ("BIDIR") ) TRELLIS_IO_5 ( - .B(ddram_dq[4]), - .I(ddrphy_dq_o4), - .T((~(~ddrphy_dq_oe_n4))), - .O(ddrphy_dq_i4) + // Inputs. + .B (ddram_dq[4]), + .I (ddrphy_dq_o4), + .T ((~(~ddrphy_dq_oe_n4))), + + // Outputs. + .O (ddrphy_dq_i4) ); +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_6 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ TRELLIS_IO #( - .DIR("BIDIR") + // Parameters. + .DIR ("BIDIR") ) TRELLIS_IO_6 ( - .B(ddram_dq[5]), - .I(ddrphy_dq_o5), - .T((~(~ddrphy_dq_oe_n5))), - .O(ddrphy_dq_i5) + // Inputs. + .B (ddram_dq[5]), + .I (ddrphy_dq_o5), + .T ((~(~ddrphy_dq_oe_n5))), + + // Outputs. + .O (ddrphy_dq_i5) ); +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_7 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ TRELLIS_IO #( - .DIR("BIDIR") + // Parameters. + .DIR ("BIDIR") ) TRELLIS_IO_7 ( - .B(ddram_dq[6]), - .I(ddrphy_dq_o6), - .T((~(~ddrphy_dq_oe_n6))), - .O(ddrphy_dq_i6) + // Inputs. + .B (ddram_dq[6]), + .I (ddrphy_dq_o6), + .T ((~(~ddrphy_dq_oe_n6))), + + // Outputs. + .O (ddrphy_dq_i6) ); +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_8 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ TRELLIS_IO #( - .DIR("BIDIR") + // Parameters. + .DIR ("BIDIR") ) TRELLIS_IO_8 ( - .B(ddram_dq[7]), - .I(ddrphy_dq_o7), - .T((~(~ddrphy_dq_oe_n7))), - .O(ddrphy_dq_i7) + // Inputs. + .B (ddram_dq[7]), + .I (ddrphy_dq_o7), + .T ((~(~ddrphy_dq_oe_n7))), + + // Outputs. + .O (ddrphy_dq_i7) ); +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_9 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ TRELLIS_IO #( - .DIR("BIDIR") + // Parameters. + .DIR ("BIDIR") ) TRELLIS_IO_9 ( - .B(ddram_dqs_p[1]), - .I(ddrphy_dqs1), - .T((~(~ddrphy_dqs_oe_n1))), - .O(ddrphy_dqs_i1) + // Inputs. + .B (ddram_dqs_p[1]), + .I (ddrphy_dqs1), + .T ((~(~ddrphy_dqs_oe_n1))), + + // Outputs. + .O (ddrphy_dqs_i1) ); +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_10 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ TRELLIS_IO #( - .DIR("BIDIR") + // Parameters. + .DIR ("BIDIR") ) TRELLIS_IO_10 ( - .B(ddram_dq[8]), - .I(ddrphy_dq_o8), - .T((~(~ddrphy_dq_oe_n8))), - .O(ddrphy_dq_i8) + // Inputs. + .B (ddram_dq[8]), + .I (ddrphy_dq_o8), + .T ((~(~ddrphy_dq_oe_n8))), + + // Outputs. + .O (ddrphy_dq_i8) ); +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_11 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ TRELLIS_IO #( - .DIR("BIDIR") + // Parameters. + .DIR ("BIDIR") ) TRELLIS_IO_11 ( - .B(ddram_dq[9]), - .I(ddrphy_dq_o9), - .T((~(~ddrphy_dq_oe_n9))), - .O(ddrphy_dq_i9) + // Inputs. + .B (ddram_dq[9]), + .I (ddrphy_dq_o9), + .T ((~(~ddrphy_dq_oe_n9))), + + // Outputs. + .O (ddrphy_dq_i9) ); +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_12 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ TRELLIS_IO #( - .DIR("BIDIR") + // Parameters. + .DIR ("BIDIR") ) TRELLIS_IO_12 ( - .B(ddram_dq[10]), - .I(ddrphy_dq_o10), - .T((~(~ddrphy_dq_oe_n10))), - .O(ddrphy_dq_i10) + // Inputs. + .B (ddram_dq[10]), + .I (ddrphy_dq_o10), + .T ((~(~ddrphy_dq_oe_n10))), + + // Outputs. + .O (ddrphy_dq_i10) ); +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_13 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ TRELLIS_IO #( - .DIR("BIDIR") + // Parameters. + .DIR ("BIDIR") ) TRELLIS_IO_13 ( - .B(ddram_dq[11]), - .I(ddrphy_dq_o11), - .T((~(~ddrphy_dq_oe_n11))), - .O(ddrphy_dq_i11) + // Inputs. + .B (ddram_dq[11]), + .I (ddrphy_dq_o11), + .T ((~(~ddrphy_dq_oe_n11))), + + // Outputs. + .O (ddrphy_dq_i11) ); +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_14 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ TRELLIS_IO #( - .DIR("BIDIR") + // Parameters. + .DIR ("BIDIR") ) TRELLIS_IO_14 ( - .B(ddram_dq[12]), - .I(ddrphy_dq_o12), - .T((~(~ddrphy_dq_oe_n12))), - .O(ddrphy_dq_i12) + // Inputs. + .B (ddram_dq[12]), + .I (ddrphy_dq_o12), + .T ((~(~ddrphy_dq_oe_n12))), + + // Outputs. + .O (ddrphy_dq_i12) ); +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_15 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ TRELLIS_IO #( - .DIR("BIDIR") + // Parameters. + .DIR ("BIDIR") ) TRELLIS_IO_15 ( - .B(ddram_dq[13]), - .I(ddrphy_dq_o13), - .T((~(~ddrphy_dq_oe_n13))), - .O(ddrphy_dq_i13) + // Inputs. + .B (ddram_dq[13]), + .I (ddrphy_dq_o13), + .T ((~(~ddrphy_dq_oe_n13))), + + // Outputs. + .O (ddrphy_dq_i13) ); +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_16 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ TRELLIS_IO #( - .DIR("BIDIR") + // Parameters. + .DIR ("BIDIR") ) TRELLIS_IO_16 ( - .B(ddram_dq[14]), - .I(ddrphy_dq_o14), - .T((~(~ddrphy_dq_oe_n14))), - .O(ddrphy_dq_i14) + // Inputs. + .B (ddram_dq[14]), + .I (ddrphy_dq_o14), + .T ((~(~ddrphy_dq_oe_n14))), + + // Outputs. + .O (ddrphy_dq_i14) ); +//------------------------------------------------------------------------------ +// Instance TRELLIS_IO_17 of TRELLIS_IO Module. +//------------------------------------------------------------------------------ TRELLIS_IO #( - .DIR("BIDIR") + // Parameters. + .DIR ("BIDIR") ) TRELLIS_IO_17 ( - .B(ddram_dq[15]), - .I(ddrphy_dq_o15), - .T((~(~ddrphy_dq_oe_n15))), - .O(ddrphy_dq_i15) + // Inputs. + .B (ddram_dq[15]), + .I (ddrphy_dq_o15), + .T ((~(~ddrphy_dq_oe_n15))), + + // Outputs. + .O (ddrphy_dq_i15) ); endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2022-10-28 19:01:26. +// Auto-Generated by LiteX on 2024-04-01 10:12:11. //------------------------------------------------------------------------------ diff --git a/litedram/generated/sim/litedram_core.init b/litedram/generated/sim/litedram_core.init index 71d4b3f..7cf9fda 100644 --- a/litedram/generated/sim/litedram_core.init +++ b/litedram/generated/sim/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ff00782107c6 3d80000060215f00 798c07c6618c0000 -618c10e0658cff00 +618c10d4658cff00 4e8004217d8903a6 4e8004207c6903a6 0000000000000000 @@ -510,323 +510,307 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -392000003d40c000 -794a0020614a6004 -7d2057aa7c0004ac +3920000039406004 +7c0004ac654ac000 +600000007d2057aa 6000000060000000 6000000060000000 -4e80002060000000 +000000004e800020 0000000000000000 -3c4c000100000000 -7c0802a63842a3c4 -fbe1fff8fbc1fff0 +3842a2c83c4c0001 +fbe1fff87c0802a6 f821ff51f8010010 -f88100d83bc10020 -f8c100e8f8a100e0 -38c100d87c651b78 -f8e100f038800080 -7fc3f378f90100f8 -f9410108f9210100 -6000000048001789 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a/litedram/generated/sim/litedram_core.v +++ b/litedram/generated/sim/litedram_core.v @@ -8,2028 +8,2211 @@ // // Filename : litedram_core.v // Device : -// LiteX sha1 : -------- -// Date : 2022-10-28 19:01:27 +// LiteX sha1 : 87137c30 +// Date : 2024-04-01 10:12:12 //------------------------------------------------------------------------------ +`timescale 1ns / 1ps //------------------------------------------------------------------------------ // Module //------------------------------------------------------------------------------ module litedram_core ( - input wire sim_trace, input wire clk, output wire init_done, output wire init_error, - input wire [29:0] wb_ctrl_adr, - input wire [31:0] wb_ctrl_dat_w, - output wire [31:0] wb_ctrl_dat_r, - input wire [3:0] wb_ctrl_sel, - input wire wb_ctrl_cyc, - input wire wb_ctrl_stb, - output wire wb_ctrl_ack, - input wire wb_ctrl_we, - input wire [2:0] wb_ctrl_cti, - input wire [1:0] wb_ctrl_bte, - output wire wb_ctrl_err, + input wire sim_trace, output wire user_clk, - output wire user_rst, - input wire user_port_native_0_cmd_valid, + input wire [23:0] user_port_native_0_cmd_addr, output wire user_port_native_0_cmd_ready, + input wire user_port_native_0_cmd_valid, input wire user_port_native_0_cmd_we, - input wire [23:0] user_port_native_0_cmd_addr, - input wire user_port_native_0_wdata_valid, + output wire [127:0] user_port_native_0_rdata_data, + input wire user_port_native_0_rdata_ready, + output wire user_port_native_0_rdata_valid, + input wire [127:0] user_port_native_0_wdata_data, output wire user_port_native_0_wdata_ready, + input wire user_port_native_0_wdata_valid, input wire [15:0] user_port_native_0_wdata_we, - input wire [127:0] user_port_native_0_wdata_data, - output wire user_port_native_0_rdata_valid, - input wire user_port_native_0_rdata_ready, - output wire [127:0] user_port_native_0_rdata_data + output wire user_rst, + output wire wb_ctrl_ack, + input wire [29:0] wb_ctrl_adr, + input wire [1:0] wb_ctrl_bte, + input wire [2:0] wb_ctrl_cti, + input wire wb_ctrl_cyc, + output wire [31:0] wb_ctrl_dat_r, + input wire [31:0] wb_ctrl_dat_w, + output wire wb_ctrl_err, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_stb, + input wire wb_ctrl_we ); +//------------------------------------------------------------------------------ +// Hierarchy +//------------------------------------------------------------------------------ + +/* +LiteDRAMCore +└─── bus (SoCBusHandler) +│ └─── _interconnect (InterconnectPointToPoint) +└─── csr (SoCCSRHandler) +└─── irq (SoCIRQHandler) +└─── cpu (CPUNone) +└─── crg (CRG) +└─── ddrphy (SDRAMPHYModel) +│ └─── dfiphasemodel_0* (DFIPhaseModel) +│ └─── dfiphasemodel_1* (DFIPhaseModel) +│ └─── dfiphasemodel_2* (DFIPhaseModel) +│ └─── dfiphasemodel_3* (DFIPhaseModel) +│ └─── bankmodel_0* (BankModel) +│ └─── bankmodel_1* (BankModel) +│ └─── bankmodel_2* (BankModel) +│ └─── bankmodel_3* (BankModel) +│ └─── bankmodel_4* (BankModel) +│ └─── bankmodel_5* (BankModel) +│ └─── bankmodel_6* (BankModel) +│ └─── bankmodel_7* (BankModel) +└─── sdram (LiteDRAMCore) +│ └─── dfii (DFIInjector) +│ │ └─── pi0 (PhaseInjector) +│ │ └─── pi1 (PhaseInjector) +│ │ └─── pi2 (PhaseInjector) +│ │ └─── pi3 (PhaseInjector) +│ └─── controller (LiteDRAMController) +│ │ └─── refresher (Refresher) +│ │ │ └─── timer (RefreshTimer) +│ │ │ └─── postponer (RefreshPostponer) +│ │ │ └─── sequencer (RefreshSequencer) +│ │ │ │ └─── refreshexecuter_0* (RefreshExecuter) +│ │ │ └─── zqcs_timer (RefreshTimer) +│ │ │ └─── zqs_executer (ZQCSExecuter) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_0* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_1* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_2* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_3* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_4* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_5* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_6* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_7* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── multiplexer (Multiplexer) +│ │ │ └─── choose_cmd (_CommandChooser) +│ │ │ │ └─── roundrobin_0* (RoundRobin) +│ │ │ └─── choose_req (_CommandChooser) +│ │ │ │ └─── roundrobin_0* (RoundRobin) +│ │ │ └─── _steerer_0* (_Steerer) +│ │ │ └─── trrdcon (tXXDController) +│ │ │ └─── tfawcon (tFAWController) +│ │ │ └─── tccdcon (tXXDController) +│ │ │ └─── twtrcon (tXXDController) +│ │ │ └─── fsm (FSM) +│ └─── crossbar (LiteDRAMCrossbar) +│ │ └─── roundrobin_0* (RoundRobin) +│ │ └─── roundrobin_1* (RoundRobin) +│ │ └─── roundrobin_2* (RoundRobin) +│ │ └─── roundrobin_3* (RoundRobin) +│ │ └─── roundrobin_4* (RoundRobin) +│ │ └─── roundrobin_5* (RoundRobin) +│ │ └─── roundrobin_6* (RoundRobin) +│ │ └─── roundrobin_7* (RoundRobin) +└─── ddrctrl (LiteDRAMCoreControl) +└─── csr_bridge (Wishbone2CSR) +│ └─── fsm (FSM) +└─── csr_bankarray (CSRBankArray) +│ └─── csrbank_0* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ └─── csrbank_1* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstorage_4* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstorage_5* (CSRStorage) +│ │ └─── csrstorage_6* (CSRStorage) +│ │ └─── csrstorage_7* (CSRStorage) +│ │ └─── csrstorage_8* (CSRStorage) +│ │ └─── csrstatus_1* (CSRStatus) +│ │ └─── csrstorage_9* (CSRStorage) +│ │ └─── csrstorage_10* (CSRStorage) +│ │ └─── csrstorage_11* (CSRStorage) +│ │ └─── csrstorage_12* (CSRStorage) +│ │ └─── csrstatus_2* (CSRStatus) +│ │ └─── csrstorage_13* (CSRStorage) +│ │ └─── csrstorage_14* (CSRStorage) +│ │ └─── csrstorage_15* (CSRStorage) +│ │ └─── csrstorage_16* (CSRStorage) +│ │ └─── csrstatus_3* (CSRStatus) +└─── csr_interconnect (InterconnectShared) +* : Generated name. +[]: BlackBox. +*/ + //------------------------------------------------------------------------------ // Signals //------------------------------------------------------------------------------ -wire sys_clk; -wire sys_rst; +wire [13:0] adr; +reg [3:0] bankmachine0_next_state = 4'd0; +reg [3:0] bankmachine0_state = 4'd0; +reg [3:0] bankmachine1_next_state = 4'd0; +reg [3:0] bankmachine1_state = 4'd0; +reg [3:0] bankmachine2_next_state = 4'd0; +reg [3:0] bankmachine2_state = 4'd0; +reg [3:0] bankmachine3_next_state = 4'd0; +reg [3:0] bankmachine3_state = 4'd0; +reg [3:0] bankmachine4_next_state = 4'd0; +reg [3:0] bankmachine4_state = 4'd0; +reg [3:0] bankmachine5_next_state = 4'd0; +reg [3:0] bankmachine5_state = 4'd0; +reg [3:0] bankmachine6_next_state = 4'd0; +reg [3:0] bankmachine6_state = 4'd0; +reg [3:0] bankmachine7_next_state = 4'd0; +reg [3:0] bankmachine7_state = 4'd0; +wire csrbank0_init_done0_r; +reg csrbank0_init_done0_re = 1'd0; +wire csrbank0_init_done0_w; +reg csrbank0_init_done0_we = 1'd0; +wire csrbank0_init_error0_r; +reg csrbank0_init_error0_re = 1'd0; +wire csrbank0_init_error0_w; +reg csrbank0_init_error0_we = 1'd0; +wire csrbank0_sel; +wire [3:0] csrbank1_dfii_control0_r; +reg csrbank1_dfii_control0_re = 1'd0; +wire [3:0] csrbank1_dfii_control0_w; +reg csrbank1_dfii_control0_we = 1'd0; +wire [13:0] csrbank1_dfii_pi0_address0_r; +reg csrbank1_dfii_pi0_address0_re = 1'd0; +wire [13:0] csrbank1_dfii_pi0_address0_w; +reg csrbank1_dfii_pi0_address0_we = 1'd0; +wire [2:0] csrbank1_dfii_pi0_baddress0_r; +reg csrbank1_dfii_pi0_baddress0_re = 1'd0; +wire [2:0] csrbank1_dfii_pi0_baddress0_w; +reg csrbank1_dfii_pi0_baddress0_we = 1'd0; +wire [7:0] csrbank1_dfii_pi0_command0_r; +reg csrbank1_dfii_pi0_command0_re = 1'd0; +wire [7:0] csrbank1_dfii_pi0_command0_w; +reg csrbank1_dfii_pi0_command0_we = 1'd0; +wire [31:0] csrbank1_dfii_pi0_rddata_r; +reg csrbank1_dfii_pi0_rddata_re = 1'd0; +wire [31:0] csrbank1_dfii_pi0_rddata_w; +reg csrbank1_dfii_pi0_rddata_we = 1'd0; +wire [31:0] csrbank1_dfii_pi0_wrdata0_r; +reg csrbank1_dfii_pi0_wrdata0_re = 1'd0; +wire [31:0] csrbank1_dfii_pi0_wrdata0_w; +reg csrbank1_dfii_pi0_wrdata0_we = 1'd0; +wire [13:0] csrbank1_dfii_pi1_address0_r; +reg csrbank1_dfii_pi1_address0_re = 1'd0; +wire [13:0] csrbank1_dfii_pi1_address0_w; +reg csrbank1_dfii_pi1_address0_we = 1'd0; +wire [2:0] csrbank1_dfii_pi1_baddress0_r; +reg csrbank1_dfii_pi1_baddress0_re = 1'd0; +wire [2:0] csrbank1_dfii_pi1_baddress0_w; +reg csrbank1_dfii_pi1_baddress0_we = 1'd0; +wire [7:0] csrbank1_dfii_pi1_command0_r; +reg csrbank1_dfii_pi1_command0_re = 1'd0; +wire [7:0] csrbank1_dfii_pi1_command0_w; +reg csrbank1_dfii_pi1_command0_we = 1'd0; +wire [31:0] csrbank1_dfii_pi1_rddata_r; +reg csrbank1_dfii_pi1_rddata_re = 1'd0; +wire [31:0] csrbank1_dfii_pi1_rddata_w; +reg csrbank1_dfii_pi1_rddata_we = 1'd0; +wire [31:0] csrbank1_dfii_pi1_wrdata0_r; +reg csrbank1_dfii_pi1_wrdata0_re = 1'd0; +wire [31:0] csrbank1_dfii_pi1_wrdata0_w; +reg csrbank1_dfii_pi1_wrdata0_we = 1'd0; +wire [13:0] csrbank1_dfii_pi2_address0_r; +reg csrbank1_dfii_pi2_address0_re = 1'd0; +wire [13:0] csrbank1_dfii_pi2_address0_w; +reg csrbank1_dfii_pi2_address0_we = 1'd0; +wire [2:0] csrbank1_dfii_pi2_baddress0_r; +reg csrbank1_dfii_pi2_baddress0_re = 1'd0; +wire [2:0] csrbank1_dfii_pi2_baddress0_w; +reg csrbank1_dfii_pi2_baddress0_we = 1'd0; +wire [7:0] csrbank1_dfii_pi2_command0_r; +reg csrbank1_dfii_pi2_command0_re = 1'd0; +wire [7:0] csrbank1_dfii_pi2_command0_w; +reg csrbank1_dfii_pi2_command0_we = 1'd0; +wire [31:0] csrbank1_dfii_pi2_rddata_r; +reg csrbank1_dfii_pi2_rddata_re = 1'd0; +wire [31:0] csrbank1_dfii_pi2_rddata_w; +reg csrbank1_dfii_pi2_rddata_we = 1'd0; +wire [31:0] csrbank1_dfii_pi2_wrdata0_r; +reg csrbank1_dfii_pi2_wrdata0_re = 1'd0; +wire [31:0] csrbank1_dfii_pi2_wrdata0_w; +reg csrbank1_dfii_pi2_wrdata0_we = 1'd0; +wire [13:0] csrbank1_dfii_pi3_address0_r; +reg csrbank1_dfii_pi3_address0_re = 1'd0; +wire [13:0] csrbank1_dfii_pi3_address0_w; +reg csrbank1_dfii_pi3_address0_we = 1'd0; +wire [2:0] csrbank1_dfii_pi3_baddress0_r; +reg csrbank1_dfii_pi3_baddress0_re = 1'd0; +wire [2:0] csrbank1_dfii_pi3_baddress0_w; +reg csrbank1_dfii_pi3_baddress0_we = 1'd0; +wire [7:0] csrbank1_dfii_pi3_command0_r; +reg csrbank1_dfii_pi3_command0_re = 1'd0; +wire [7:0] csrbank1_dfii_pi3_command0_w; +reg csrbank1_dfii_pi3_command0_we = 1'd0; +wire [31:0] csrbank1_dfii_pi3_rddata_r; +reg csrbank1_dfii_pi3_rddata_re = 1'd0; +wire [31:0] csrbank1_dfii_pi3_rddata_w; +reg csrbank1_dfii_pi3_rddata_we = 1'd0; +wire [31:0] csrbank1_dfii_pi3_wrdata0_r; +reg csrbank1_dfii_pi3_wrdata0_re = 1'd0; +wire [31:0] csrbank1_dfii_pi3_wrdata0_w; +reg csrbank1_dfii_pi3_wrdata0_we = 1'd0; +wire csrbank1_sel; +wire [31:0] dat_r; +wire [31:0] dat_w; +reg interface0_ack = 1'd0; +wire [29:0] interface0_adr; +wire [13:0] interface0_bank_bus_adr; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; +wire [31:0] interface0_bank_bus_dat_w; +wire interface0_bank_bus_we; +wire [1:0] interface0_bte; +wire [2:0] interface0_cti; +wire interface0_cyc; +reg [31:0] interface0_dat_r = 32'd0; +wire [31:0] interface0_dat_w; +reg interface0_err = 1'd0; +wire [3:0] interface0_sel; +wire interface0_stb; +wire interface0_we; +reg [13:0] interface1_adr = 14'd0; +reg [13:0] interface1_adr_next_value1 = 14'd0; +reg interface1_adr_next_value_ce1 = 1'd0; +wire [13:0] interface1_bank_bus_adr; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; +wire [31:0] interface1_bank_bus_dat_w; +wire interface1_bank_bus_we; +wire [31:0] interface1_dat_r; +reg [31:0] interface1_dat_w = 32'd0; +reg [31:0] interface1_dat_w_next_value0 = 32'd0; +reg interface1_dat_w_next_value_ce0 = 1'd0; +reg interface1_we = 1'd0; +reg interface1_we_next_value2 = 1'd0; +reg interface1_we_next_value_ce2 = 1'd0; +reg locked0 = 1'd0; +reg locked1 = 1'd0; +reg locked2 = 1'd0; +reg locked3 = 1'd0; +reg locked4 = 1'd0; +reg locked5 = 1'd0; +reg locked6 = 1'd0; +reg locked7 = 1'd0; +reg [3:0] multiplexer_next_state = 4'd0; +reg [3:0] multiplexer_state = 4'd0; +reg new_master_rdata_valid0 = 1'd0; +reg new_master_rdata_valid1 = 1'd0; +reg new_master_rdata_valid2 = 1'd0; +reg new_master_rdata_valid3 = 1'd0; +reg new_master_rdata_valid4 = 1'd0; +reg new_master_rdata_valid5 = 1'd0; +reg new_master_rdata_valid6 = 1'd0; +reg new_master_rdata_valid7 = 1'd0; +reg new_master_rdata_valid8 = 1'd0; +reg new_master_wdata_ready0 = 1'd0; +reg new_master_wdata_ready1 = 1'd0; +reg [1:0] next_state = 2'd0; wire por_clk; -reg soc_int_rst = 1'd1; -wire [13:0] soc_ddrphy_dfi_p0_address; -wire [2:0] soc_ddrphy_dfi_p0_bank; -wire soc_ddrphy_dfi_p0_cas_n; -wire soc_ddrphy_dfi_p0_cs_n; -wire soc_ddrphy_dfi_p0_ras_n; -wire soc_ddrphy_dfi_p0_we_n; -wire soc_ddrphy_dfi_p0_cke; -wire soc_ddrphy_dfi_p0_odt; -wire soc_ddrphy_dfi_p0_reset_n; -wire soc_ddrphy_dfi_p0_act_n; -wire [31:0] soc_ddrphy_dfi_p0_wrdata; -wire soc_ddrphy_dfi_p0_wrdata_en; -wire [3:0] soc_ddrphy_dfi_p0_wrdata_mask; -wire soc_ddrphy_dfi_p0_rddata_en; -wire [31:0] soc_ddrphy_dfi_p0_rddata; -wire soc_ddrphy_dfi_p0_rddata_valid; -wire [13:0] soc_ddrphy_dfi_p1_address; -wire [2:0] soc_ddrphy_dfi_p1_bank; -wire soc_ddrphy_dfi_p1_cas_n; -wire soc_ddrphy_dfi_p1_cs_n; -wire soc_ddrphy_dfi_p1_ras_n; -wire soc_ddrphy_dfi_p1_we_n; -wire soc_ddrphy_dfi_p1_cke; -wire soc_ddrphy_dfi_p1_odt; -wire soc_ddrphy_dfi_p1_reset_n; -wire soc_ddrphy_dfi_p1_act_n; -wire [31:0] soc_ddrphy_dfi_p1_wrdata; -wire soc_ddrphy_dfi_p1_wrdata_en; -wire [3:0] soc_ddrphy_dfi_p1_wrdata_mask; -wire soc_ddrphy_dfi_p1_rddata_en; -wire [31:0] soc_ddrphy_dfi_p1_rddata; -wire soc_ddrphy_dfi_p1_rddata_valid; -wire [13:0] soc_ddrphy_dfi_p2_address; -wire [2:0] soc_ddrphy_dfi_p2_bank; -wire soc_ddrphy_dfi_p2_cas_n; -wire soc_ddrphy_dfi_p2_cs_n; -wire soc_ddrphy_dfi_p2_ras_n; -wire soc_ddrphy_dfi_p2_we_n; -wire soc_ddrphy_dfi_p2_cke; -wire soc_ddrphy_dfi_p2_odt; -wire soc_ddrphy_dfi_p2_reset_n; -wire soc_ddrphy_dfi_p2_act_n; -wire [31:0] soc_ddrphy_dfi_p2_wrdata; -wire soc_ddrphy_dfi_p2_wrdata_en; -wire [3:0] soc_ddrphy_dfi_p2_wrdata_mask; -wire soc_ddrphy_dfi_p2_rddata_en; -wire [31:0] soc_ddrphy_dfi_p2_rddata; -wire soc_ddrphy_dfi_p2_rddata_valid; -wire [13:0] soc_ddrphy_dfi_p3_address; -wire [2:0] soc_ddrphy_dfi_p3_bank; -wire soc_ddrphy_dfi_p3_cas_n; -wire soc_ddrphy_dfi_p3_cs_n; -wire soc_ddrphy_dfi_p3_ras_n; -wire soc_ddrphy_dfi_p3_we_n; -wire soc_ddrphy_dfi_p3_cke; -wire soc_ddrphy_dfi_p3_odt; -wire soc_ddrphy_dfi_p3_reset_n; -wire soc_ddrphy_dfi_p3_act_n; -wire [31:0] soc_ddrphy_dfi_p3_wrdata; -wire soc_ddrphy_dfi_p3_wrdata_en; -wire [3:0] soc_ddrphy_dfi_p3_wrdata_mask; -wire soc_ddrphy_dfi_p3_rddata_en; -wire [31:0] soc_ddrphy_dfi_p3_rddata; -wire soc_ddrphy_dfi_p3_rddata_valid; -reg soc_ddrphy_dfiphasemodel0_activate = 1'd0; -reg soc_ddrphy_dfiphasemodel0_precharge = 1'd0; -reg soc_ddrphy_dfiphasemodel0_write = 1'd0; -reg soc_ddrphy_dfiphasemodel0_read = 1'd0; -reg soc_ddrphy_dfiphasemodel1_activate = 1'd0; -reg soc_ddrphy_dfiphasemodel1_precharge = 1'd0; -reg soc_ddrphy_dfiphasemodel1_write = 1'd0; -reg soc_ddrphy_dfiphasemodel1_read = 1'd0; -reg soc_ddrphy_dfiphasemodel2_activate = 1'd0; -reg soc_ddrphy_dfiphasemodel2_precharge = 1'd0; -reg soc_ddrphy_dfiphasemodel2_write = 1'd0; -reg soc_ddrphy_dfiphasemodel2_read = 1'd0; -reg soc_ddrphy_dfiphasemodel3_activate = 1'd0; -reg soc_ddrphy_dfiphasemodel3_precharge = 1'd0; -reg soc_ddrphy_dfiphasemodel3_write = 1'd0; -reg soc_ddrphy_dfiphasemodel3_read = 1'd0; -reg soc_ddrphy_bankmodel0_activate = 1'd0; -reg [13:0] soc_ddrphy_bankmodel0_activate_row = 14'd0; -reg soc_ddrphy_bankmodel0_precharge = 1'd0; -wire soc_ddrphy_bankmodel0_write; -wire [9:0] soc_ddrphy_bankmodel0_write_col; -wire [127:0] soc_ddrphy_bankmodel0_write_data; -wire [15:0] soc_ddrphy_bankmodel0_write_mask; -reg soc_ddrphy_bankmodel0_read = 1'd0; -reg [9:0] soc_ddrphy_bankmodel0_read_col = 10'd0; -reg [127:0] soc_ddrphy_bankmodel0_read_data = 128'd0; -reg soc_ddrphy_bankmodel0_active = 1'd0; -reg [13:0] soc_ddrphy_bankmodel0_row = 14'd0; -reg [20:0] soc_ddrphy_bankmodel0_write_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel0_write_port_dat_r; -reg [15:0] soc_ddrphy_bankmodel0_write_port_we = 16'd0; -reg [127:0] soc_ddrphy_bankmodel0_write_port_dat_w = 128'd0; -reg [20:0] soc_ddrphy_bankmodel0_read_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel0_read_port_dat_r; -wire [20:0] soc_ddrphy_bankmodel0_wraddr; -wire [20:0] soc_ddrphy_bankmodel0_rdaddr; -reg soc_ddrphy_bankmodel1_activate = 1'd0; -reg [13:0] soc_ddrphy_bankmodel1_activate_row = 14'd0; -reg soc_ddrphy_bankmodel1_precharge = 1'd0; -wire soc_ddrphy_bankmodel1_write; -wire [9:0] soc_ddrphy_bankmodel1_write_col; -wire [127:0] soc_ddrphy_bankmodel1_write_data; -wire [15:0] soc_ddrphy_bankmodel1_write_mask; -reg soc_ddrphy_bankmodel1_read = 1'd0; -reg [9:0] soc_ddrphy_bankmodel1_read_col = 10'd0; -reg [127:0] soc_ddrphy_bankmodel1_read_data = 128'd0; -reg soc_ddrphy_bankmodel1_active = 1'd0; -reg [13:0] soc_ddrphy_bankmodel1_row = 14'd0; -reg [20:0] soc_ddrphy_bankmodel1_write_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel1_write_port_dat_r; -reg [15:0] soc_ddrphy_bankmodel1_write_port_we = 16'd0; -reg [127:0] soc_ddrphy_bankmodel1_write_port_dat_w = 128'd0; -reg [20:0] soc_ddrphy_bankmodel1_read_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel1_read_port_dat_r; -wire [20:0] soc_ddrphy_bankmodel1_wraddr; +reg [1:0] refresher_next_state = 2'd0; +reg [1:0] refresher_state = 2'd0; +reg rhs_self0 = 1'd0; +reg [13:0] rhs_self1 = 14'd0; +reg rhs_self10 = 1'd0; +reg rhs_self11 = 1'd0; +reg [20:0] rhs_self12 = 21'd0; +reg rhs_self13 = 1'd0; +reg rhs_self14 = 1'd0; +reg [20:0] rhs_self15 = 21'd0; +reg rhs_self16 = 1'd0; +reg rhs_self17 = 1'd0; +reg [20:0] rhs_self18 = 21'd0; +reg rhs_self19 = 1'd0; +reg [2:0] rhs_self2 = 3'd0; +reg rhs_self20 = 1'd0; +reg [20:0] rhs_self21 = 21'd0; +reg rhs_self22 = 1'd0; +reg rhs_self23 = 1'd0; +reg [20:0] rhs_self24 = 21'd0; +reg rhs_self25 = 1'd0; +reg rhs_self26 = 1'd0; +reg [20:0] rhs_self27 = 21'd0; +reg rhs_self28 = 1'd0; +reg rhs_self29 = 1'd0; +reg rhs_self3 = 1'd0; +reg [20:0] rhs_self30 = 21'd0; +reg rhs_self31 = 1'd0; +reg rhs_self32 = 1'd0; +reg [20:0] rhs_self33 = 21'd0; +reg rhs_self34 = 1'd0; +reg rhs_self35 = 1'd0; +reg rhs_self4 = 1'd0; +reg rhs_self5 = 1'd0; +reg rhs_self6 = 1'd0; +reg [13:0] rhs_self7 = 14'd0; +reg [2:0] rhs_self8 = 3'd0; +reg rhs_self9 = 1'd0; +wire roundrobin0_ce; +wire roundrobin0_grant; +wire roundrobin0_request; +wire roundrobin1_ce; +wire roundrobin1_grant; +wire roundrobin1_request; +wire roundrobin2_ce; +wire roundrobin2_grant; +wire roundrobin2_request; +wire roundrobin3_ce; +wire roundrobin3_grant; +wire roundrobin3_request; +wire roundrobin4_ce; +wire roundrobin4_grant; +wire roundrobin4_request; +wire roundrobin5_ce; +wire roundrobin5_grant; +wire roundrobin5_request; +wire roundrobin6_ce; +wire roundrobin6_grant; +wire roundrobin6_request; +wire roundrobin7_ce; +wire roundrobin7_grant; +wire roundrobin7_request; +reg [2:0] self0 = 3'd0; +reg [13:0] self1 = 14'd0; +reg self10 = 1'd0; +reg self11 = 1'd0; +reg self12 = 1'd0; +reg self13 = 1'd0; +reg [2:0] self14 = 3'd0; +reg [13:0] self15 = 14'd0; +reg self16 = 1'd0; +reg self17 = 1'd0; +reg self18 = 1'd0; +reg self19 = 1'd0; +reg self2 = 1'd0; +reg self20 = 1'd0; +reg [2:0] self21 = 3'd0; +reg [13:0] self22 = 14'd0; +reg self23 = 1'd0; +reg self24 = 1'd0; +reg self25 = 1'd0; +reg self26 = 1'd0; +reg self27 = 1'd0; +reg self3 = 1'd0; +reg self4 = 1'd0; +reg self5 = 1'd0; +reg self6 = 1'd0; +reg [2:0] self7 = 3'd0; +reg [13:0] self8 = 14'd0; +reg self9 = 1'd0; +wire [24:0] slice_proxy0; +wire [24:0] slice_proxy1; +wire [24:0] slice_proxy10; +wire [24:0] slice_proxy11; +wire [24:0] slice_proxy12; +wire [24:0] slice_proxy13; +wire [24:0] slice_proxy14; +wire [24:0] slice_proxy15; +wire [24:0] slice_proxy2; +wire [24:0] slice_proxy3; +wire [24:0] slice_proxy4; +wire [24:0] slice_proxy5; +wire [24:0] slice_proxy6; +wire [24:0] slice_proxy7; +wire [24:0] slice_proxy8; +wire [24:0] slice_proxy9; +reg [3:0] soc_ddrphy_activates0 = 4'd0; +reg [3:0] soc_ddrphy_activates1 = 4'd0; +reg [3:0] soc_ddrphy_activates2 = 4'd0; +reg [3:0] soc_ddrphy_activates3 = 4'd0; +reg [3:0] soc_ddrphy_activates4 = 4'd0; +reg [3:0] soc_ddrphy_activates5 = 4'd0; +reg [3:0] soc_ddrphy_activates6 = 4'd0; +reg [3:0] soc_ddrphy_activates7 = 4'd0; +reg soc_ddrphy_bank_write0 = 1'd0; +reg soc_ddrphy_bank_write1 = 1'd0; +reg soc_ddrphy_bank_write2 = 1'd0; +reg soc_ddrphy_bank_write3 = 1'd0; +reg soc_ddrphy_bank_write4 = 1'd0; +reg soc_ddrphy_bank_write5 = 1'd0; +reg soc_ddrphy_bank_write6 = 1'd0; +reg soc_ddrphy_bank_write7 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col0 = 10'd0; +reg [9:0] soc_ddrphy_bank_write_col1 = 10'd0; +reg [9:0] soc_ddrphy_bank_write_col2 = 10'd0; +reg [9:0] soc_ddrphy_bank_write_col3 = 10'd0; +reg [9:0] soc_ddrphy_bank_write_col4 = 10'd0; +reg [9:0] soc_ddrphy_bank_write_col5 = 10'd0; +reg [9:0] soc_ddrphy_bank_write_col6 = 10'd0; +reg [9:0] soc_ddrphy_bank_write_col7 = 10'd0; +reg soc_ddrphy_bankmodel0_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel0_activate_row = 14'd0; +reg soc_ddrphy_bankmodel0_active = 1'd0; +reg soc_ddrphy_bankmodel0_precharge = 1'd0; +wire [20:0] soc_ddrphy_bankmodel0_rdaddr; +reg soc_ddrphy_bankmodel0_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel0_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel0_read_data = 128'd0; +reg [20:0] soc_ddrphy_bankmodel0_read_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel0_read_port_dat_r; +reg [13:0] soc_ddrphy_bankmodel0_row = 14'd0; +wire [20:0] soc_ddrphy_bankmodel0_wraddr; +wire soc_ddrphy_bankmodel0_write; +wire [9:0] soc_ddrphy_bankmodel0_write_col; +wire [127:0] soc_ddrphy_bankmodel0_write_data; +wire [15:0] soc_ddrphy_bankmodel0_write_mask; +reg [20:0] soc_ddrphy_bankmodel0_write_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel0_write_port_dat_r; +reg [127:0] soc_ddrphy_bankmodel0_write_port_dat_w = 128'd0; +reg [15:0] soc_ddrphy_bankmodel0_write_port_we = 16'd0; +reg soc_ddrphy_bankmodel1_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel1_activate_row = 14'd0; +reg soc_ddrphy_bankmodel1_active = 1'd0; +reg soc_ddrphy_bankmodel1_precharge = 1'd0; wire [20:0] soc_ddrphy_bankmodel1_rdaddr; +reg soc_ddrphy_bankmodel1_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel1_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel1_read_data = 128'd0; +reg [20:0] soc_ddrphy_bankmodel1_read_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel1_read_port_dat_r; +reg [13:0] soc_ddrphy_bankmodel1_row = 14'd0; +wire [20:0] soc_ddrphy_bankmodel1_wraddr; +wire soc_ddrphy_bankmodel1_write; +wire [9:0] soc_ddrphy_bankmodel1_write_col; +wire [127:0] soc_ddrphy_bankmodel1_write_data; +wire [15:0] soc_ddrphy_bankmodel1_write_mask; +reg [20:0] soc_ddrphy_bankmodel1_write_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel1_write_port_dat_r; +reg [127:0] soc_ddrphy_bankmodel1_write_port_dat_w = 128'd0; +reg [15:0] soc_ddrphy_bankmodel1_write_port_we = 16'd0; reg soc_ddrphy_bankmodel2_activate = 1'd0; reg [13:0] soc_ddrphy_bankmodel2_activate_row = 14'd0; +reg soc_ddrphy_bankmodel2_active = 1'd0; reg soc_ddrphy_bankmodel2_precharge = 1'd0; -wire soc_ddrphy_bankmodel2_write; -wire [9:0] soc_ddrphy_bankmodel2_write_col; -wire [127:0] soc_ddrphy_bankmodel2_write_data; -wire [15:0] soc_ddrphy_bankmodel2_write_mask; +wire [20:0] soc_ddrphy_bankmodel2_rdaddr; reg soc_ddrphy_bankmodel2_read = 1'd0; reg [9:0] soc_ddrphy_bankmodel2_read_col = 10'd0; reg [127:0] soc_ddrphy_bankmodel2_read_data = 128'd0; -reg soc_ddrphy_bankmodel2_active = 1'd0; +reg [20:0] soc_ddrphy_bankmodel2_read_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel2_read_port_dat_r; reg [13:0] soc_ddrphy_bankmodel2_row = 14'd0; +wire [20:0] soc_ddrphy_bankmodel2_wraddr; +wire soc_ddrphy_bankmodel2_write; +wire [9:0] soc_ddrphy_bankmodel2_write_col; +wire [127:0] soc_ddrphy_bankmodel2_write_data; +wire [15:0] soc_ddrphy_bankmodel2_write_mask; reg [20:0] soc_ddrphy_bankmodel2_write_port_adr = 21'd0; wire [127:0] soc_ddrphy_bankmodel2_write_port_dat_r; -reg [15:0] soc_ddrphy_bankmodel2_write_port_we = 16'd0; reg [127:0] soc_ddrphy_bankmodel2_write_port_dat_w = 128'd0; -reg [20:0] soc_ddrphy_bankmodel2_read_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel2_read_port_dat_r; -wire [20:0] soc_ddrphy_bankmodel2_wraddr; -wire [20:0] soc_ddrphy_bankmodel2_rdaddr; +reg [15:0] soc_ddrphy_bankmodel2_write_port_we = 16'd0; reg soc_ddrphy_bankmodel3_activate = 1'd0; reg [13:0] soc_ddrphy_bankmodel3_activate_row = 14'd0; +reg soc_ddrphy_bankmodel3_active = 1'd0; reg soc_ddrphy_bankmodel3_precharge = 1'd0; -wire soc_ddrphy_bankmodel3_write; -wire [9:0] soc_ddrphy_bankmodel3_write_col; -wire [127:0] soc_ddrphy_bankmodel3_write_data; -wire [15:0] soc_ddrphy_bankmodel3_write_mask; +wire [20:0] soc_ddrphy_bankmodel3_rdaddr; reg soc_ddrphy_bankmodel3_read = 1'd0; reg [9:0] soc_ddrphy_bankmodel3_read_col = 10'd0; reg [127:0] soc_ddrphy_bankmodel3_read_data = 128'd0; -reg soc_ddrphy_bankmodel3_active = 1'd0; +reg [20:0] soc_ddrphy_bankmodel3_read_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel3_read_port_dat_r; reg [13:0] soc_ddrphy_bankmodel3_row = 14'd0; +wire [20:0] soc_ddrphy_bankmodel3_wraddr; +wire soc_ddrphy_bankmodel3_write; +wire [9:0] soc_ddrphy_bankmodel3_write_col; +wire [127:0] soc_ddrphy_bankmodel3_write_data; +wire [15:0] soc_ddrphy_bankmodel3_write_mask; reg [20:0] soc_ddrphy_bankmodel3_write_port_adr = 21'd0; wire [127:0] soc_ddrphy_bankmodel3_write_port_dat_r; -reg [15:0] soc_ddrphy_bankmodel3_write_port_we = 16'd0; reg [127:0] soc_ddrphy_bankmodel3_write_port_dat_w = 128'd0; -reg [20:0] soc_ddrphy_bankmodel3_read_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel3_read_port_dat_r; -wire [20:0] soc_ddrphy_bankmodel3_wraddr; -wire [20:0] soc_ddrphy_bankmodel3_rdaddr; +reg [15:0] soc_ddrphy_bankmodel3_write_port_we = 16'd0; reg soc_ddrphy_bankmodel4_activate = 1'd0; reg [13:0] soc_ddrphy_bankmodel4_activate_row = 14'd0; +reg soc_ddrphy_bankmodel4_active = 1'd0; reg soc_ddrphy_bankmodel4_precharge = 1'd0; -wire soc_ddrphy_bankmodel4_write; -wire [9:0] soc_ddrphy_bankmodel4_write_col; -wire [127:0] soc_ddrphy_bankmodel4_write_data; -wire [15:0] soc_ddrphy_bankmodel4_write_mask; +wire [20:0] soc_ddrphy_bankmodel4_rdaddr; reg soc_ddrphy_bankmodel4_read = 1'd0; reg [9:0] soc_ddrphy_bankmodel4_read_col = 10'd0; reg [127:0] soc_ddrphy_bankmodel4_read_data = 128'd0; -reg soc_ddrphy_bankmodel4_active = 1'd0; +reg [20:0] soc_ddrphy_bankmodel4_read_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel4_read_port_dat_r; reg [13:0] soc_ddrphy_bankmodel4_row = 14'd0; +wire [20:0] soc_ddrphy_bankmodel4_wraddr; +wire soc_ddrphy_bankmodel4_write; +wire [9:0] soc_ddrphy_bankmodel4_write_col; +wire [127:0] soc_ddrphy_bankmodel4_write_data; +wire [15:0] soc_ddrphy_bankmodel4_write_mask; reg [20:0] soc_ddrphy_bankmodel4_write_port_adr = 21'd0; wire [127:0] soc_ddrphy_bankmodel4_write_port_dat_r; -reg [15:0] soc_ddrphy_bankmodel4_write_port_we = 16'd0; reg [127:0] soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0; -reg [20:0] soc_ddrphy_bankmodel4_read_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel4_read_port_dat_r; -wire [20:0] soc_ddrphy_bankmodel4_wraddr; -wire [20:0] soc_ddrphy_bankmodel4_rdaddr; +reg [15:0] soc_ddrphy_bankmodel4_write_port_we = 16'd0; reg soc_ddrphy_bankmodel5_activate = 1'd0; reg [13:0] soc_ddrphy_bankmodel5_activate_row = 14'd0; +reg soc_ddrphy_bankmodel5_active = 1'd0; reg soc_ddrphy_bankmodel5_precharge = 1'd0; -wire soc_ddrphy_bankmodel5_write; -wire [9:0] soc_ddrphy_bankmodel5_write_col; -wire [127:0] soc_ddrphy_bankmodel5_write_data; -wire [15:0] soc_ddrphy_bankmodel5_write_mask; +wire [20:0] soc_ddrphy_bankmodel5_rdaddr; reg soc_ddrphy_bankmodel5_read = 1'd0; reg [9:0] soc_ddrphy_bankmodel5_read_col = 10'd0; reg [127:0] soc_ddrphy_bankmodel5_read_data = 128'd0; -reg soc_ddrphy_bankmodel5_active = 1'd0; +reg [20:0] soc_ddrphy_bankmodel5_read_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel5_read_port_dat_r; reg [13:0] soc_ddrphy_bankmodel5_row = 14'd0; +wire [20:0] soc_ddrphy_bankmodel5_wraddr; +wire soc_ddrphy_bankmodel5_write; +wire [9:0] soc_ddrphy_bankmodel5_write_col; +wire [127:0] soc_ddrphy_bankmodel5_write_data; +wire [15:0] soc_ddrphy_bankmodel5_write_mask; reg [20:0] soc_ddrphy_bankmodel5_write_port_adr = 21'd0; wire [127:0] soc_ddrphy_bankmodel5_write_port_dat_r; -reg [15:0] soc_ddrphy_bankmodel5_write_port_we = 16'd0; reg [127:0] soc_ddrphy_bankmodel5_write_port_dat_w = 128'd0; -reg [20:0] soc_ddrphy_bankmodel5_read_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel5_read_port_dat_r; -wire [20:0] soc_ddrphy_bankmodel5_wraddr; -wire [20:0] soc_ddrphy_bankmodel5_rdaddr; +reg [15:0] soc_ddrphy_bankmodel5_write_port_we = 16'd0; reg soc_ddrphy_bankmodel6_activate = 1'd0; reg [13:0] soc_ddrphy_bankmodel6_activate_row = 14'd0; +reg soc_ddrphy_bankmodel6_active = 1'd0; reg soc_ddrphy_bankmodel6_precharge = 1'd0; -wire soc_ddrphy_bankmodel6_write; -wire [9:0] soc_ddrphy_bankmodel6_write_col; -wire [127:0] soc_ddrphy_bankmodel6_write_data; -wire [15:0] soc_ddrphy_bankmodel6_write_mask; +wire [20:0] soc_ddrphy_bankmodel6_rdaddr; reg soc_ddrphy_bankmodel6_read = 1'd0; reg [9:0] soc_ddrphy_bankmodel6_read_col = 10'd0; reg [127:0] soc_ddrphy_bankmodel6_read_data = 128'd0; -reg soc_ddrphy_bankmodel6_active = 1'd0; +reg [20:0] soc_ddrphy_bankmodel6_read_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel6_read_port_dat_r; reg [13:0] soc_ddrphy_bankmodel6_row = 14'd0; +wire [20:0] soc_ddrphy_bankmodel6_wraddr; +wire soc_ddrphy_bankmodel6_write; +wire [9:0] soc_ddrphy_bankmodel6_write_col; +wire [127:0] soc_ddrphy_bankmodel6_write_data; +wire [15:0] soc_ddrphy_bankmodel6_write_mask; reg [20:0] soc_ddrphy_bankmodel6_write_port_adr = 21'd0; wire [127:0] soc_ddrphy_bankmodel6_write_port_dat_r; -reg [15:0] soc_ddrphy_bankmodel6_write_port_we = 16'd0; reg [127:0] soc_ddrphy_bankmodel6_write_port_dat_w = 128'd0; -reg [20:0] soc_ddrphy_bankmodel6_read_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel6_read_port_dat_r; -wire [20:0] soc_ddrphy_bankmodel6_wraddr; -wire [20:0] soc_ddrphy_bankmodel6_rdaddr; +reg [15:0] soc_ddrphy_bankmodel6_write_port_we = 16'd0; reg soc_ddrphy_bankmodel7_activate = 1'd0; reg [13:0] soc_ddrphy_bankmodel7_activate_row = 14'd0; +reg soc_ddrphy_bankmodel7_active = 1'd0; reg soc_ddrphy_bankmodel7_precharge = 1'd0; -wire soc_ddrphy_bankmodel7_write; -wire [9:0] soc_ddrphy_bankmodel7_write_col; -wire [127:0] soc_ddrphy_bankmodel7_write_data; -wire [15:0] soc_ddrphy_bankmodel7_write_mask; +wire [20:0] soc_ddrphy_bankmodel7_rdaddr; reg soc_ddrphy_bankmodel7_read = 1'd0; reg [9:0] soc_ddrphy_bankmodel7_read_col = 10'd0; reg [127:0] soc_ddrphy_bankmodel7_read_data = 128'd0; -reg soc_ddrphy_bankmodel7_active = 1'd0; +reg [20:0] soc_ddrphy_bankmodel7_read_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel7_read_port_dat_r; reg [13:0] soc_ddrphy_bankmodel7_row = 14'd0; +wire [20:0] soc_ddrphy_bankmodel7_wraddr; +wire soc_ddrphy_bankmodel7_write; +wire [9:0] soc_ddrphy_bankmodel7_write_col; +wire [127:0] soc_ddrphy_bankmodel7_write_data; +wire [15:0] soc_ddrphy_bankmodel7_write_mask; reg [20:0] soc_ddrphy_bankmodel7_write_port_adr = 21'd0; wire [127:0] soc_ddrphy_bankmodel7_write_port_dat_r; -reg [15:0] soc_ddrphy_bankmodel7_write_port_we = 16'd0; reg [127:0] soc_ddrphy_bankmodel7_write_port_dat_w = 128'd0; -reg [20:0] soc_ddrphy_bankmodel7_read_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel7_read_port_dat_r; -wire [20:0] soc_ddrphy_bankmodel7_wraddr; -wire [20:0] soc_ddrphy_bankmodel7_rdaddr; -reg [3:0] soc_ddrphy_activates0 = 4'd0; -reg [3:0] soc_ddrphy_precharges0 = 4'd0; -reg soc_ddrphy_bank_write0 = 1'd0; -reg [9:0] soc_ddrphy_bank_write_col0 = 10'd0; -reg [3:0] soc_ddrphy_writes0 = 4'd0; -reg soc_ddrphy_new_bank_write0 = 1'd0; -reg [9:0] soc_ddrphy_new_bank_write_col0 = 10'd0; -reg [3:0] soc_ddrphy_reads0 = 4'd0; -reg [3:0] soc_ddrphy_activates1 = 4'd0; -reg [3:0] soc_ddrphy_precharges1 = 4'd0; -reg soc_ddrphy_bank_write1 = 1'd0; -reg [9:0] soc_ddrphy_bank_write_col1 = 10'd0; -reg [3:0] soc_ddrphy_writes1 = 4'd0; -reg soc_ddrphy_new_bank_write1 = 1'd0; -reg [9:0] soc_ddrphy_new_bank_write_col1 = 10'd0; -reg [3:0] soc_ddrphy_reads1 = 4'd0; -reg [3:0] soc_ddrphy_activates2 = 4'd0; -reg [3:0] soc_ddrphy_precharges2 = 4'd0; -reg soc_ddrphy_bank_write2 = 1'd0; -reg [9:0] soc_ddrphy_bank_write_col2 = 10'd0; -reg [3:0] soc_ddrphy_writes2 = 4'd0; -reg soc_ddrphy_new_bank_write2 = 1'd0; -reg [9:0] soc_ddrphy_new_bank_write_col2 = 10'd0; -reg [3:0] soc_ddrphy_reads2 = 4'd0; -reg [3:0] soc_ddrphy_activates3 = 4'd0; -reg [3:0] soc_ddrphy_precharges3 = 4'd0; -reg soc_ddrphy_bank_write3 = 1'd0; -reg [9:0] soc_ddrphy_bank_write_col3 = 10'd0; -reg [3:0] soc_ddrphy_writes3 = 4'd0; -reg soc_ddrphy_new_bank_write3 = 1'd0; -reg [9:0] soc_ddrphy_new_bank_write_col3 = 10'd0; -reg [3:0] soc_ddrphy_reads3 = 4'd0; -reg [3:0] soc_ddrphy_activates4 = 4'd0; -reg [3:0] soc_ddrphy_precharges4 = 4'd0; -reg soc_ddrphy_bank_write4 = 1'd0; -reg [9:0] soc_ddrphy_bank_write_col4 = 10'd0; -reg [3:0] soc_ddrphy_writes4 = 4'd0; -reg soc_ddrphy_new_bank_write4 = 1'd0; -reg [9:0] soc_ddrphy_new_bank_write_col4 = 10'd0; -reg [3:0] soc_ddrphy_reads4 = 4'd0; -reg [3:0] soc_ddrphy_activates5 = 4'd0; -reg [3:0] soc_ddrphy_precharges5 = 4'd0; -reg soc_ddrphy_bank_write5 = 1'd0; -reg [9:0] soc_ddrphy_bank_write_col5 = 10'd0; -reg [3:0] soc_ddrphy_writes5 = 4'd0; -reg soc_ddrphy_new_bank_write5 = 1'd0; -reg [9:0] soc_ddrphy_new_bank_write_col5 = 10'd0; -reg [3:0] soc_ddrphy_reads5 = 4'd0; -reg [3:0] soc_ddrphy_activates6 = 4'd0; -reg [3:0] soc_ddrphy_precharges6 = 4'd0; -reg soc_ddrphy_bank_write6 = 1'd0; -reg [9:0] soc_ddrphy_bank_write_col6 = 10'd0; -reg [3:0] soc_ddrphy_writes6 = 4'd0; -reg soc_ddrphy_new_bank_write6 = 1'd0; -reg [9:0] soc_ddrphy_new_bank_write_col6 = 10'd0; -reg [3:0] soc_ddrphy_reads6 = 4'd0; -reg [3:0] soc_ddrphy_activates7 = 4'd0; -reg [3:0] soc_ddrphy_precharges7 = 4'd0; -reg soc_ddrphy_bank_write7 = 1'd0; -reg [9:0] soc_ddrphy_bank_write_col7 = 10'd0; -reg [3:0] soc_ddrphy_writes7 = 4'd0; -reg soc_ddrphy_new_bank_write7 = 1'd0; -reg [9:0] soc_ddrphy_new_bank_write_col7 = 10'd0; -reg [3:0] soc_ddrphy_reads7 = 4'd0; +reg [15:0] soc_ddrphy_bankmodel7_write_port_we = 16'd0; wire soc_ddrphy_banks_read; wire [127:0] soc_ddrphy_banks_read_data; +wire soc_ddrphy_dfi_p0_act_n; +wire [13:0] soc_ddrphy_dfi_p0_address; +wire [2:0] soc_ddrphy_dfi_p0_bank; +wire soc_ddrphy_dfi_p0_cas_n; +wire soc_ddrphy_dfi_p0_cke; +wire soc_ddrphy_dfi_p0_cs_n; +wire soc_ddrphy_dfi_p0_odt; +wire soc_ddrphy_dfi_p0_ras_n; +wire [31:0] soc_ddrphy_dfi_p0_rddata; +wire soc_ddrphy_dfi_p0_rddata_en; +wire soc_ddrphy_dfi_p0_rddata_valid; +wire soc_ddrphy_dfi_p0_reset_n; +wire soc_ddrphy_dfi_p0_we_n; +wire [31:0] soc_ddrphy_dfi_p0_wrdata; +wire soc_ddrphy_dfi_p0_wrdata_en; +wire [3:0] soc_ddrphy_dfi_p0_wrdata_mask; +wire soc_ddrphy_dfi_p1_act_n; +wire [13:0] soc_ddrphy_dfi_p1_address; +wire [2:0] soc_ddrphy_dfi_p1_bank; +wire soc_ddrphy_dfi_p1_cas_n; +wire soc_ddrphy_dfi_p1_cke; +wire soc_ddrphy_dfi_p1_cs_n; +wire soc_ddrphy_dfi_p1_odt; +wire soc_ddrphy_dfi_p1_ras_n; +wire [31:0] soc_ddrphy_dfi_p1_rddata; +wire soc_ddrphy_dfi_p1_rddata_en; +wire soc_ddrphy_dfi_p1_rddata_valid; +wire soc_ddrphy_dfi_p1_reset_n; +wire soc_ddrphy_dfi_p1_we_n; +wire [31:0] soc_ddrphy_dfi_p1_wrdata; +wire soc_ddrphy_dfi_p1_wrdata_en; +wire [3:0] soc_ddrphy_dfi_p1_wrdata_mask; +wire soc_ddrphy_dfi_p2_act_n; +wire [13:0] soc_ddrphy_dfi_p2_address; +wire [2:0] soc_ddrphy_dfi_p2_bank; +wire soc_ddrphy_dfi_p2_cas_n; +wire soc_ddrphy_dfi_p2_cke; +wire soc_ddrphy_dfi_p2_cs_n; +wire soc_ddrphy_dfi_p2_odt; +wire soc_ddrphy_dfi_p2_ras_n; +wire [31:0] soc_ddrphy_dfi_p2_rddata; +wire soc_ddrphy_dfi_p2_rddata_en; +wire soc_ddrphy_dfi_p2_rddata_valid; +wire soc_ddrphy_dfi_p2_reset_n; +wire soc_ddrphy_dfi_p2_we_n; +wire [31:0] soc_ddrphy_dfi_p2_wrdata; +wire soc_ddrphy_dfi_p2_wrdata_en; +wire [3:0] soc_ddrphy_dfi_p2_wrdata_mask; +wire soc_ddrphy_dfi_p3_act_n; +wire [13:0] soc_ddrphy_dfi_p3_address; +wire [2:0] soc_ddrphy_dfi_p3_bank; +wire soc_ddrphy_dfi_p3_cas_n; +wire soc_ddrphy_dfi_p3_cke; +wire soc_ddrphy_dfi_p3_cs_n; +wire soc_ddrphy_dfi_p3_odt; +wire soc_ddrphy_dfi_p3_ras_n; +wire [31:0] soc_ddrphy_dfi_p3_rddata; +wire soc_ddrphy_dfi_p3_rddata_en; +wire soc_ddrphy_dfi_p3_rddata_valid; +wire soc_ddrphy_dfi_p3_reset_n; +wire soc_ddrphy_dfi_p3_we_n; +wire [31:0] soc_ddrphy_dfi_p3_wrdata; +wire soc_ddrphy_dfi_p3_wrdata_en; +wire [3:0] soc_ddrphy_dfi_p3_wrdata_mask; +reg soc_ddrphy_dfiphasemodel0_activate = 1'd0; +reg soc_ddrphy_dfiphasemodel0_precharge = 1'd0; +reg soc_ddrphy_dfiphasemodel0_read = 1'd0; +reg soc_ddrphy_dfiphasemodel0_write = 1'd0; +reg soc_ddrphy_dfiphasemodel1_activate = 1'd0; +reg soc_ddrphy_dfiphasemodel1_precharge = 1'd0; +reg soc_ddrphy_dfiphasemodel1_read = 1'd0; +reg soc_ddrphy_dfiphasemodel1_write = 1'd0; +reg soc_ddrphy_dfiphasemodel2_activate = 1'd0; +reg soc_ddrphy_dfiphasemodel2_precharge = 1'd0; +reg soc_ddrphy_dfiphasemodel2_read = 1'd0; +reg soc_ddrphy_dfiphasemodel2_write = 1'd0; +reg soc_ddrphy_dfiphasemodel3_activate = 1'd0; +reg soc_ddrphy_dfiphasemodel3_precharge = 1'd0; +reg soc_ddrphy_dfiphasemodel3_read = 1'd0; +reg soc_ddrphy_dfiphasemodel3_write = 1'd0; +reg soc_ddrphy_new_bank_write0 = 1'd0; +reg soc_ddrphy_new_bank_write1 = 1'd0; +reg soc_ddrphy_new_bank_write2 = 1'd0; +reg soc_ddrphy_new_bank_write3 = 1'd0; +reg soc_ddrphy_new_bank_write4 = 1'd0; +reg soc_ddrphy_new_bank_write5 = 1'd0; +reg soc_ddrphy_new_bank_write6 = 1'd0; +reg soc_ddrphy_new_bank_write7 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col0 = 10'd0; +reg [9:0] soc_ddrphy_new_bank_write_col1 = 10'd0; +reg [9:0] soc_ddrphy_new_bank_write_col2 = 10'd0; +reg [9:0] soc_ddrphy_new_bank_write_col3 = 10'd0; +reg [9:0] soc_ddrphy_new_bank_write_col4 = 10'd0; +reg [9:0] soc_ddrphy_new_bank_write_col5 = 10'd0; +reg [9:0] soc_ddrphy_new_bank_write_col6 = 10'd0; +reg [9:0] soc_ddrphy_new_bank_write_col7 = 10'd0; reg soc_ddrphy_new_banks_read0 = 1'd0; -reg [127:0] soc_ddrphy_new_banks_read_data0 = 128'd0; reg soc_ddrphy_new_banks_read1 = 1'd0; -reg [127:0] soc_ddrphy_new_banks_read_data1 = 128'd0; reg soc_ddrphy_new_banks_read2 = 1'd0; -reg [127:0] soc_ddrphy_new_banks_read_data2 = 128'd0; reg soc_ddrphy_new_banks_read3 = 1'd0; -reg [127:0] soc_ddrphy_new_banks_read_data3 = 128'd0; reg soc_ddrphy_new_banks_read4 = 1'd0; -reg [127:0] soc_ddrphy_new_banks_read_data4 = 128'd0; reg soc_ddrphy_new_banks_read5 = 1'd0; -reg [127:0] soc_ddrphy_new_banks_read_data5 = 128'd0; reg soc_ddrphy_new_banks_read6 = 1'd0; -reg [127:0] soc_ddrphy_new_banks_read_data6 = 128'd0; reg soc_ddrphy_new_banks_read7 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data0 = 128'd0; +reg [127:0] soc_ddrphy_new_banks_read_data1 = 128'd0; +reg [127:0] soc_ddrphy_new_banks_read_data2 = 128'd0; +reg [127:0] soc_ddrphy_new_banks_read_data3 = 128'd0; +reg [127:0] soc_ddrphy_new_banks_read_data4 = 128'd0; +reg [127:0] soc_ddrphy_new_banks_read_data5 = 128'd0; +reg [127:0] soc_ddrphy_new_banks_read_data6 = 128'd0; reg [127:0] soc_ddrphy_new_banks_read_data7 = 128'd0; -wire [13:0] soc_litedramcore_slave_p0_address; -wire [2:0] soc_litedramcore_slave_p0_bank; -wire soc_litedramcore_slave_p0_cas_n; -wire soc_litedramcore_slave_p0_cs_n; -wire soc_litedramcore_slave_p0_ras_n; -wire soc_litedramcore_slave_p0_we_n; -wire soc_litedramcore_slave_p0_cke; -wire soc_litedramcore_slave_p0_odt; -wire soc_litedramcore_slave_p0_reset_n; -wire soc_litedramcore_slave_p0_act_n; -wire [31:0] soc_litedramcore_slave_p0_wrdata; -wire soc_litedramcore_slave_p0_wrdata_en; -wire [3:0] soc_litedramcore_slave_p0_wrdata_mask; -wire soc_litedramcore_slave_p0_rddata_en; -reg [31:0] soc_litedramcore_slave_p0_rddata = 32'd0; -reg soc_litedramcore_slave_p0_rddata_valid = 1'd0; -wire [13:0] soc_litedramcore_slave_p1_address; -wire [2:0] soc_litedramcore_slave_p1_bank; -wire soc_litedramcore_slave_p1_cas_n; -wire soc_litedramcore_slave_p1_cs_n; -wire soc_litedramcore_slave_p1_ras_n; -wire soc_litedramcore_slave_p1_we_n; -wire soc_litedramcore_slave_p1_cke; -wire soc_litedramcore_slave_p1_odt; -wire soc_litedramcore_slave_p1_reset_n; -wire soc_litedramcore_slave_p1_act_n; -wire [31:0] soc_litedramcore_slave_p1_wrdata; -wire soc_litedramcore_slave_p1_wrdata_en; -wire [3:0] soc_litedramcore_slave_p1_wrdata_mask; -wire soc_litedramcore_slave_p1_rddata_en; -reg [31:0] soc_litedramcore_slave_p1_rddata = 32'd0; -reg soc_litedramcore_slave_p1_rddata_valid = 1'd0; -wire [13:0] soc_litedramcore_slave_p2_address; -wire [2:0] soc_litedramcore_slave_p2_bank; -wire soc_litedramcore_slave_p2_cas_n; -wire soc_litedramcore_slave_p2_cs_n; -wire soc_litedramcore_slave_p2_ras_n; -wire soc_litedramcore_slave_p2_we_n; -wire soc_litedramcore_slave_p2_cke; -wire soc_litedramcore_slave_p2_odt; -wire soc_litedramcore_slave_p2_reset_n; -wire soc_litedramcore_slave_p2_act_n; -wire [31:0] soc_litedramcore_slave_p2_wrdata; -wire soc_litedramcore_slave_p2_wrdata_en; -wire [3:0] soc_litedramcore_slave_p2_wrdata_mask; -wire soc_litedramcore_slave_p2_rddata_en; -reg [31:0] soc_litedramcore_slave_p2_rddata = 32'd0; -reg soc_litedramcore_slave_p2_rddata_valid = 1'd0; -wire [13:0] soc_litedramcore_slave_p3_address; -wire [2:0] soc_litedramcore_slave_p3_bank; -wire soc_litedramcore_slave_p3_cas_n; -wire soc_litedramcore_slave_p3_cs_n; -wire soc_litedramcore_slave_p3_ras_n; -wire soc_litedramcore_slave_p3_we_n; -wire soc_litedramcore_slave_p3_cke; -wire soc_litedramcore_slave_p3_odt; -wire soc_litedramcore_slave_p3_reset_n; -wire soc_litedramcore_slave_p3_act_n; -wire [31:0] soc_litedramcore_slave_p3_wrdata; -wire soc_litedramcore_slave_p3_wrdata_en; -wire [3:0] soc_litedramcore_slave_p3_wrdata_mask; -wire soc_litedramcore_slave_p3_rddata_en; -reg [31:0] soc_litedramcore_slave_p3_rddata = 32'd0; -reg soc_litedramcore_slave_p3_rddata_valid = 1'd0; -reg [13:0] soc_litedramcore_master_p0_address = 14'd0; -reg [2:0] soc_litedramcore_master_p0_bank = 3'd0; -reg soc_litedramcore_master_p0_cas_n = 1'd1; -reg soc_litedramcore_master_p0_cs_n = 1'd1; -reg soc_litedramcore_master_p0_ras_n = 1'd1; -reg soc_litedramcore_master_p0_we_n = 1'd1; -reg soc_litedramcore_master_p0_cke = 1'd0; -reg soc_litedramcore_master_p0_odt = 1'd0; -reg soc_litedramcore_master_p0_reset_n = 1'd0; -reg soc_litedramcore_master_p0_act_n = 1'd1; -reg [31:0] soc_litedramcore_master_p0_wrdata = 32'd0; -reg soc_litedramcore_master_p0_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_master_p0_wrdata_mask = 4'd0; -reg soc_litedramcore_master_p0_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_master_p0_rddata; -wire soc_litedramcore_master_p0_rddata_valid; -reg [13:0] soc_litedramcore_master_p1_address = 14'd0; -reg [2:0] soc_litedramcore_master_p1_bank = 3'd0; -reg soc_litedramcore_master_p1_cas_n = 1'd1; -reg soc_litedramcore_master_p1_cs_n = 1'd1; -reg soc_litedramcore_master_p1_ras_n = 1'd1; -reg soc_litedramcore_master_p1_we_n = 1'd1; -reg soc_litedramcore_master_p1_cke = 1'd0; -reg soc_litedramcore_master_p1_odt = 1'd0; -reg soc_litedramcore_master_p1_reset_n = 1'd0; -reg soc_litedramcore_master_p1_act_n = 1'd1; -reg [31:0] soc_litedramcore_master_p1_wrdata = 32'd0; -reg soc_litedramcore_master_p1_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_master_p1_wrdata_mask = 4'd0; -reg soc_litedramcore_master_p1_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_master_p1_rddata; -wire soc_litedramcore_master_p1_rddata_valid; -reg [13:0] soc_litedramcore_master_p2_address = 14'd0; -reg [2:0] soc_litedramcore_master_p2_bank = 3'd0; -reg soc_litedramcore_master_p2_cas_n = 1'd1; -reg soc_litedramcore_master_p2_cs_n = 1'd1; -reg soc_litedramcore_master_p2_ras_n = 1'd1; -reg soc_litedramcore_master_p2_we_n = 1'd1; -reg soc_litedramcore_master_p2_cke = 1'd0; -reg soc_litedramcore_master_p2_odt = 1'd0; -reg soc_litedramcore_master_p2_reset_n = 1'd0; -reg soc_litedramcore_master_p2_act_n = 1'd1; -reg [31:0] soc_litedramcore_master_p2_wrdata = 32'd0; -reg soc_litedramcore_master_p2_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_master_p2_wrdata_mask = 4'd0; -reg soc_litedramcore_master_p2_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_master_p2_rddata; -wire soc_litedramcore_master_p2_rddata_valid; -reg [13:0] soc_litedramcore_master_p3_address = 14'd0; -reg [2:0] soc_litedramcore_master_p3_bank = 3'd0; -reg soc_litedramcore_master_p3_cas_n = 1'd1; -reg soc_litedramcore_master_p3_cs_n = 1'd1; -reg soc_litedramcore_master_p3_ras_n = 1'd1; -reg soc_litedramcore_master_p3_we_n = 1'd1; -reg soc_litedramcore_master_p3_cke = 1'd0; -reg soc_litedramcore_master_p3_odt = 1'd0; -reg soc_litedramcore_master_p3_reset_n = 1'd0; -reg soc_litedramcore_master_p3_act_n = 1'd1; -reg [31:0] soc_litedramcore_master_p3_wrdata = 32'd0; -reg soc_litedramcore_master_p3_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_master_p3_wrdata_mask = 4'd0; -reg soc_litedramcore_master_p3_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_master_p3_rddata; -wire soc_litedramcore_master_p3_rddata_valid; -wire [13:0] soc_litedramcore_csr_dfi_p0_address; -wire [2:0] soc_litedramcore_csr_dfi_p0_bank; -reg soc_litedramcore_csr_dfi_p0_cas_n = 1'd1; -reg soc_litedramcore_csr_dfi_p0_cs_n = 1'd1; -reg soc_litedramcore_csr_dfi_p0_ras_n = 1'd1; -reg soc_litedramcore_csr_dfi_p0_we_n = 1'd1; -wire soc_litedramcore_csr_dfi_p0_cke; -wire soc_litedramcore_csr_dfi_p0_odt; -wire soc_litedramcore_csr_dfi_p0_reset_n; -reg soc_litedramcore_csr_dfi_p0_act_n = 1'd1; -wire [31:0] soc_litedramcore_csr_dfi_p0_wrdata; -wire soc_litedramcore_csr_dfi_p0_wrdata_en; -wire [3:0] soc_litedramcore_csr_dfi_p0_wrdata_mask; -wire soc_litedramcore_csr_dfi_p0_rddata_en; -reg [31:0] soc_litedramcore_csr_dfi_p0_rddata = 32'd0; -reg soc_litedramcore_csr_dfi_p0_rddata_valid = 1'd0; -wire [13:0] soc_litedramcore_csr_dfi_p1_address; -wire [2:0] soc_litedramcore_csr_dfi_p1_bank; -reg soc_litedramcore_csr_dfi_p1_cas_n = 1'd1; -reg soc_litedramcore_csr_dfi_p1_cs_n = 1'd1; -reg soc_litedramcore_csr_dfi_p1_ras_n = 1'd1; -reg soc_litedramcore_csr_dfi_p1_we_n = 1'd1; -wire soc_litedramcore_csr_dfi_p1_cke; -wire soc_litedramcore_csr_dfi_p1_odt; -wire soc_litedramcore_csr_dfi_p1_reset_n; -reg soc_litedramcore_csr_dfi_p1_act_n = 1'd1; -wire [31:0] soc_litedramcore_csr_dfi_p1_wrdata; -wire soc_litedramcore_csr_dfi_p1_wrdata_en; -wire [3:0] soc_litedramcore_csr_dfi_p1_wrdata_mask; -wire soc_litedramcore_csr_dfi_p1_rddata_en; -reg [31:0] soc_litedramcore_csr_dfi_p1_rddata = 32'd0; -reg soc_litedramcore_csr_dfi_p1_rddata_valid = 1'd0; -wire [13:0] soc_litedramcore_csr_dfi_p2_address; -wire [2:0] soc_litedramcore_csr_dfi_p2_bank; -reg soc_litedramcore_csr_dfi_p2_cas_n = 1'd1; -reg soc_litedramcore_csr_dfi_p2_cs_n = 1'd1; -reg soc_litedramcore_csr_dfi_p2_ras_n = 1'd1; -reg soc_litedramcore_csr_dfi_p2_we_n = 1'd1; -wire soc_litedramcore_csr_dfi_p2_cke; -wire soc_litedramcore_csr_dfi_p2_odt; -wire soc_litedramcore_csr_dfi_p2_reset_n; -reg soc_litedramcore_csr_dfi_p2_act_n = 1'd1; -wire [31:0] soc_litedramcore_csr_dfi_p2_wrdata; -wire soc_litedramcore_csr_dfi_p2_wrdata_en; -wire [3:0] soc_litedramcore_csr_dfi_p2_wrdata_mask; -wire soc_litedramcore_csr_dfi_p2_rddata_en; -reg [31:0] soc_litedramcore_csr_dfi_p2_rddata = 32'd0; -reg soc_litedramcore_csr_dfi_p2_rddata_valid = 1'd0; -wire [13:0] soc_litedramcore_csr_dfi_p3_address; -wire [2:0] soc_litedramcore_csr_dfi_p3_bank; -reg soc_litedramcore_csr_dfi_p3_cas_n = 1'd1; -reg soc_litedramcore_csr_dfi_p3_cs_n = 1'd1; -reg soc_litedramcore_csr_dfi_p3_ras_n = 1'd1; -reg soc_litedramcore_csr_dfi_p3_we_n = 1'd1; -wire soc_litedramcore_csr_dfi_p3_cke; -wire soc_litedramcore_csr_dfi_p3_odt; -wire soc_litedramcore_csr_dfi_p3_reset_n; -reg soc_litedramcore_csr_dfi_p3_act_n = 1'd1; -wire [31:0] soc_litedramcore_csr_dfi_p3_wrdata; -wire soc_litedramcore_csr_dfi_p3_wrdata_en; -wire [3:0] soc_litedramcore_csr_dfi_p3_wrdata_mask; -wire soc_litedramcore_csr_dfi_p3_rddata_en; -reg [31:0] soc_litedramcore_csr_dfi_p3_rddata = 32'd0; -reg soc_litedramcore_csr_dfi_p3_rddata_valid = 1'd0; -reg [13:0] soc_litedramcore_ext_dfi_p0_address = 14'd0; -reg [2:0] soc_litedramcore_ext_dfi_p0_bank = 3'd0; -reg soc_litedramcore_ext_dfi_p0_cas_n = 1'd1; -reg soc_litedramcore_ext_dfi_p0_cs_n = 1'd1; -reg soc_litedramcore_ext_dfi_p0_ras_n = 1'd1; -reg soc_litedramcore_ext_dfi_p0_we_n = 1'd1; -reg soc_litedramcore_ext_dfi_p0_cke = 1'd0; -reg soc_litedramcore_ext_dfi_p0_odt = 1'd0; -reg soc_litedramcore_ext_dfi_p0_reset_n = 1'd0; -reg soc_litedramcore_ext_dfi_p0_act_n = 1'd1; -reg [31:0] soc_litedramcore_ext_dfi_p0_wrdata = 32'd0; -reg soc_litedramcore_ext_dfi_p0_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_ext_dfi_p0_wrdata_mask = 4'd0; -reg soc_litedramcore_ext_dfi_p0_rddata_en = 1'd0; -reg [31:0] soc_litedramcore_ext_dfi_p0_rddata = 32'd0; -reg soc_litedramcore_ext_dfi_p0_rddata_valid = 1'd0; -reg [13:0] soc_litedramcore_ext_dfi_p1_address = 14'd0; -reg [2:0] soc_litedramcore_ext_dfi_p1_bank = 3'd0; -reg soc_litedramcore_ext_dfi_p1_cas_n = 1'd1; -reg soc_litedramcore_ext_dfi_p1_cs_n = 1'd1; -reg soc_litedramcore_ext_dfi_p1_ras_n = 1'd1; -reg soc_litedramcore_ext_dfi_p1_we_n = 1'd1; -reg soc_litedramcore_ext_dfi_p1_cke = 1'd0; -reg soc_litedramcore_ext_dfi_p1_odt = 1'd0; -reg soc_litedramcore_ext_dfi_p1_reset_n = 1'd0; -reg soc_litedramcore_ext_dfi_p1_act_n = 1'd1; -reg [31:0] soc_litedramcore_ext_dfi_p1_wrdata = 32'd0; -reg soc_litedramcore_ext_dfi_p1_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_ext_dfi_p1_wrdata_mask = 4'd0; -reg soc_litedramcore_ext_dfi_p1_rddata_en = 1'd0; -reg [31:0] soc_litedramcore_ext_dfi_p1_rddata = 32'd0; -reg soc_litedramcore_ext_dfi_p1_rddata_valid = 1'd0; -reg [13:0] soc_litedramcore_ext_dfi_p2_address = 14'd0; -reg [2:0] soc_litedramcore_ext_dfi_p2_bank = 3'd0; -reg soc_litedramcore_ext_dfi_p2_cas_n = 1'd1; -reg soc_litedramcore_ext_dfi_p2_cs_n = 1'd1; -reg soc_litedramcore_ext_dfi_p2_ras_n = 1'd1; -reg soc_litedramcore_ext_dfi_p2_we_n = 1'd1; -reg soc_litedramcore_ext_dfi_p2_cke = 1'd0; -reg soc_litedramcore_ext_dfi_p2_odt = 1'd0; -reg soc_litedramcore_ext_dfi_p2_reset_n = 1'd0; -reg soc_litedramcore_ext_dfi_p2_act_n = 1'd1; -reg [31:0] soc_litedramcore_ext_dfi_p2_wrdata = 32'd0; -reg soc_litedramcore_ext_dfi_p2_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_ext_dfi_p2_wrdata_mask = 4'd0; -reg soc_litedramcore_ext_dfi_p2_rddata_en = 1'd0; -reg [31:0] soc_litedramcore_ext_dfi_p2_rddata = 32'd0; -reg soc_litedramcore_ext_dfi_p2_rddata_valid = 1'd0; -reg [13:0] soc_litedramcore_ext_dfi_p3_address = 14'd0; -reg [2:0] soc_litedramcore_ext_dfi_p3_bank = 3'd0; -reg soc_litedramcore_ext_dfi_p3_cas_n = 1'd1; -reg soc_litedramcore_ext_dfi_p3_cs_n = 1'd1; -reg soc_litedramcore_ext_dfi_p3_ras_n = 1'd1; -reg soc_litedramcore_ext_dfi_p3_we_n = 1'd1; -reg soc_litedramcore_ext_dfi_p3_cke = 1'd0; -reg soc_litedramcore_ext_dfi_p3_odt = 1'd0; -reg soc_litedramcore_ext_dfi_p3_reset_n = 1'd0; -reg soc_litedramcore_ext_dfi_p3_act_n = 1'd1; -reg [31:0] soc_litedramcore_ext_dfi_p3_wrdata = 32'd0; -reg soc_litedramcore_ext_dfi_p3_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_ext_dfi_p3_wrdata_mask = 4'd0; -reg soc_litedramcore_ext_dfi_p3_rddata_en = 1'd0; -reg [31:0] soc_litedramcore_ext_dfi_p3_rddata = 32'd0; -reg soc_litedramcore_ext_dfi_p3_rddata_valid = 1'd0; -reg soc_litedramcore_ext_dfi_sel = 1'd0; -wire soc_litedramcore_sel; -wire soc_litedramcore_cke; -wire soc_litedramcore_odt; -wire soc_litedramcore_reset_n; -reg [3:0] soc_litedramcore_storage = 4'd1; -reg soc_litedramcore_re = 1'd0; -wire soc_litedramcore_phaseinjector0_csrfield_cs; -wire soc_litedramcore_phaseinjector0_csrfield_we; -wire soc_litedramcore_phaseinjector0_csrfield_cas; -wire soc_litedramcore_phaseinjector0_csrfield_ras; -wire soc_litedramcore_phaseinjector0_csrfield_wren; -wire soc_litedramcore_phaseinjector0_csrfield_rden; -reg [5:0] soc_litedramcore_phaseinjector0_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector0_command_re = 1'd0; -reg soc_litedramcore_phaseinjector0_command_issue_re = 1'd0; -wire soc_litedramcore_phaseinjector0_command_issue_r; -reg soc_litedramcore_phaseinjector0_command_issue_we = 1'd0; -reg soc_litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [13:0] soc_litedramcore_phaseinjector0_address_storage = 14'd0; -reg soc_litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector0_wrdata_storage = 32'd0; -reg soc_litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector0_rddata_status = 32'd0; -wire soc_litedramcore_phaseinjector0_rddata_we; -reg soc_litedramcore_phaseinjector0_rddata_re = 1'd0; -wire soc_litedramcore_phaseinjector1_csrfield_cs; -wire soc_litedramcore_phaseinjector1_csrfield_we; -wire soc_litedramcore_phaseinjector1_csrfield_cas; -wire soc_litedramcore_phaseinjector1_csrfield_ras; -wire soc_litedramcore_phaseinjector1_csrfield_wren; -wire soc_litedramcore_phaseinjector1_csrfield_rden; -reg [5:0] soc_litedramcore_phaseinjector1_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector1_command_re = 1'd0; -reg soc_litedramcore_phaseinjector1_command_issue_re = 1'd0; -wire soc_litedramcore_phaseinjector1_command_issue_r; -reg soc_litedramcore_phaseinjector1_command_issue_we = 1'd0; -reg soc_litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [13:0] soc_litedramcore_phaseinjector1_address_storage = 14'd0; -reg soc_litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector1_wrdata_storage = 32'd0; -reg soc_litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector1_rddata_status = 32'd0; -wire soc_litedramcore_phaseinjector1_rddata_we; -reg soc_litedramcore_phaseinjector1_rddata_re = 1'd0; -wire soc_litedramcore_phaseinjector2_csrfield_cs; -wire soc_litedramcore_phaseinjector2_csrfield_we; -wire soc_litedramcore_phaseinjector2_csrfield_cas; -wire soc_litedramcore_phaseinjector2_csrfield_ras; -wire soc_litedramcore_phaseinjector2_csrfield_wren; -wire soc_litedramcore_phaseinjector2_csrfield_rden; -reg [5:0] soc_litedramcore_phaseinjector2_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector2_command_re = 1'd0; -reg soc_litedramcore_phaseinjector2_command_issue_re = 1'd0; -wire soc_litedramcore_phaseinjector2_command_issue_r; -reg soc_litedramcore_phaseinjector2_command_issue_we = 1'd0; -reg soc_litedramcore_phaseinjector2_command_issue_w = 1'd0; -reg [13:0] soc_litedramcore_phaseinjector2_address_storage = 14'd0; -reg soc_litedramcore_phaseinjector2_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector2_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector2_baddress_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector2_wrdata_storage = 32'd0; -reg soc_litedramcore_phaseinjector2_wrdata_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector2_rddata_status = 32'd0; -wire soc_litedramcore_phaseinjector2_rddata_we; -reg soc_litedramcore_phaseinjector2_rddata_re = 1'd0; -wire soc_litedramcore_phaseinjector3_csrfield_cs; -wire soc_litedramcore_phaseinjector3_csrfield_we; -wire soc_litedramcore_phaseinjector3_csrfield_cas; -wire soc_litedramcore_phaseinjector3_csrfield_ras; -wire soc_litedramcore_phaseinjector3_csrfield_wren; -wire soc_litedramcore_phaseinjector3_csrfield_rden; -reg [5:0] soc_litedramcore_phaseinjector3_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector3_command_re = 1'd0; -reg soc_litedramcore_phaseinjector3_command_issue_re = 1'd0; -wire soc_litedramcore_phaseinjector3_command_issue_r; -reg soc_litedramcore_phaseinjector3_command_issue_we = 1'd0; -reg soc_litedramcore_phaseinjector3_command_issue_w = 1'd0; -reg [13:0] soc_litedramcore_phaseinjector3_address_storage = 14'd0; -reg soc_litedramcore_phaseinjector3_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector3_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector3_baddress_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector3_wrdata_storage = 32'd0; -reg soc_litedramcore_phaseinjector3_wrdata_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector3_rddata_status = 32'd0; -wire soc_litedramcore_phaseinjector3_rddata_we; -reg soc_litedramcore_phaseinjector3_rddata_re = 1'd0; -wire soc_litedramcore_interface_bank0_valid; -wire soc_litedramcore_interface_bank0_ready; -wire soc_litedramcore_interface_bank0_we; -wire [20:0] soc_litedramcore_interface_bank0_addr; -wire soc_litedramcore_interface_bank0_lock; -wire soc_litedramcore_interface_bank0_wdata_ready; -wire soc_litedramcore_interface_bank0_rdata_valid; -wire soc_litedramcore_interface_bank1_valid; -wire soc_litedramcore_interface_bank1_ready; -wire soc_litedramcore_interface_bank1_we; -wire [20:0] soc_litedramcore_interface_bank1_addr; -wire soc_litedramcore_interface_bank1_lock; -wire soc_litedramcore_interface_bank1_wdata_ready; -wire soc_litedramcore_interface_bank1_rdata_valid; -wire soc_litedramcore_interface_bank2_valid; -wire soc_litedramcore_interface_bank2_ready; -wire soc_litedramcore_interface_bank2_we; -wire [20:0] soc_litedramcore_interface_bank2_addr; -wire soc_litedramcore_interface_bank2_lock; -wire soc_litedramcore_interface_bank2_wdata_ready; -wire soc_litedramcore_interface_bank2_rdata_valid; -wire soc_litedramcore_interface_bank3_valid; -wire soc_litedramcore_interface_bank3_ready; -wire soc_litedramcore_interface_bank3_we; -wire [20:0] soc_litedramcore_interface_bank3_addr; -wire soc_litedramcore_interface_bank3_lock; -wire soc_litedramcore_interface_bank3_wdata_ready; -wire soc_litedramcore_interface_bank3_rdata_valid; -wire soc_litedramcore_interface_bank4_valid; -wire soc_litedramcore_interface_bank4_ready; -wire soc_litedramcore_interface_bank4_we; -wire [20:0] soc_litedramcore_interface_bank4_addr; -wire soc_litedramcore_interface_bank4_lock; -wire soc_litedramcore_interface_bank4_wdata_ready; -wire soc_litedramcore_interface_bank4_rdata_valid; -wire soc_litedramcore_interface_bank5_valid; -wire soc_litedramcore_interface_bank5_ready; -wire soc_litedramcore_interface_bank5_we; -wire [20:0] soc_litedramcore_interface_bank5_addr; -wire soc_litedramcore_interface_bank5_lock; -wire soc_litedramcore_interface_bank5_wdata_ready; -wire soc_litedramcore_interface_bank5_rdata_valid; -wire soc_litedramcore_interface_bank6_valid; -wire soc_litedramcore_interface_bank6_ready; -wire soc_litedramcore_interface_bank6_we; -wire [20:0] soc_litedramcore_interface_bank6_addr; -wire soc_litedramcore_interface_bank6_lock; -wire soc_litedramcore_interface_bank6_wdata_ready; -wire soc_litedramcore_interface_bank6_rdata_valid; -wire soc_litedramcore_interface_bank7_valid; -wire soc_litedramcore_interface_bank7_ready; -wire soc_litedramcore_interface_bank7_we; -wire [20:0] soc_litedramcore_interface_bank7_addr; -wire soc_litedramcore_interface_bank7_lock; -wire soc_litedramcore_interface_bank7_wdata_ready; -wire soc_litedramcore_interface_bank7_rdata_valid; -reg [127:0] soc_litedramcore_interface_wdata = 128'd0; -reg [15:0] soc_litedramcore_interface_wdata_we = 16'd0; -wire [127:0] soc_litedramcore_interface_rdata; -reg [13:0] soc_litedramcore_dfi_p0_address = 14'd0; -reg [2:0] soc_litedramcore_dfi_p0_bank = 3'd0; -reg soc_litedramcore_dfi_p0_cas_n = 1'd1; -reg soc_litedramcore_dfi_p0_cs_n = 1'd1; -reg soc_litedramcore_dfi_p0_ras_n = 1'd1; -reg soc_litedramcore_dfi_p0_we_n = 1'd1; -wire soc_litedramcore_dfi_p0_cke; -wire soc_litedramcore_dfi_p0_odt; -wire soc_litedramcore_dfi_p0_reset_n; -reg soc_litedramcore_dfi_p0_act_n = 1'd1; -wire [31:0] soc_litedramcore_dfi_p0_wrdata; -reg soc_litedramcore_dfi_p0_wrdata_en = 1'd0; -wire [3:0] soc_litedramcore_dfi_p0_wrdata_mask; -reg soc_litedramcore_dfi_p0_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_dfi_p0_rddata; -wire soc_litedramcore_dfi_p0_rddata_valid; -reg [13:0] soc_litedramcore_dfi_p1_address = 14'd0; -reg [2:0] soc_litedramcore_dfi_p1_bank = 3'd0; -reg soc_litedramcore_dfi_p1_cas_n = 1'd1; -reg soc_litedramcore_dfi_p1_cs_n = 1'd1; -reg soc_litedramcore_dfi_p1_ras_n = 1'd1; -reg soc_litedramcore_dfi_p1_we_n = 1'd1; -wire soc_litedramcore_dfi_p1_cke; -wire soc_litedramcore_dfi_p1_odt; -wire soc_litedramcore_dfi_p1_reset_n; -reg soc_litedramcore_dfi_p1_act_n = 1'd1; -wire [31:0] soc_litedramcore_dfi_p1_wrdata; -reg soc_litedramcore_dfi_p1_wrdata_en = 1'd0; -wire [3:0] soc_litedramcore_dfi_p1_wrdata_mask; -reg soc_litedramcore_dfi_p1_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_dfi_p1_rddata; -wire soc_litedramcore_dfi_p1_rddata_valid; -reg [13:0] soc_litedramcore_dfi_p2_address = 14'd0; -reg [2:0] soc_litedramcore_dfi_p2_bank = 3'd0; -reg soc_litedramcore_dfi_p2_cas_n = 1'd1; -reg soc_litedramcore_dfi_p2_cs_n = 1'd1; -reg soc_litedramcore_dfi_p2_ras_n = 1'd1; -reg soc_litedramcore_dfi_p2_we_n = 1'd1; -wire soc_litedramcore_dfi_p2_cke; -wire soc_litedramcore_dfi_p2_odt; -wire soc_litedramcore_dfi_p2_reset_n; -reg soc_litedramcore_dfi_p2_act_n = 1'd1; -wire [31:0] soc_litedramcore_dfi_p2_wrdata; -reg soc_litedramcore_dfi_p2_wrdata_en = 1'd0; -wire [3:0] soc_litedramcore_dfi_p2_wrdata_mask; -reg soc_litedramcore_dfi_p2_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_dfi_p2_rddata; -wire soc_litedramcore_dfi_p2_rddata_valid; -reg [13:0] soc_litedramcore_dfi_p3_address = 14'd0; -reg [2:0] soc_litedramcore_dfi_p3_bank = 3'd0; -reg soc_litedramcore_dfi_p3_cas_n = 1'd1; -reg soc_litedramcore_dfi_p3_cs_n = 1'd1; -reg soc_litedramcore_dfi_p3_ras_n = 1'd1; -reg soc_litedramcore_dfi_p3_we_n = 1'd1; -wire soc_litedramcore_dfi_p3_cke; -wire soc_litedramcore_dfi_p3_odt; -wire soc_litedramcore_dfi_p3_reset_n; -reg soc_litedramcore_dfi_p3_act_n = 1'd1; -wire [31:0] soc_litedramcore_dfi_p3_wrdata; -reg soc_litedramcore_dfi_p3_wrdata_en = 1'd0; -wire [3:0] soc_litedramcore_dfi_p3_wrdata_mask; -reg soc_litedramcore_dfi_p3_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_dfi_p3_rddata; -wire soc_litedramcore_dfi_p3_rddata_valid; -reg soc_litedramcore_cmd_valid = 1'd0; -reg soc_litedramcore_cmd_ready = 1'd0; -reg soc_litedramcore_cmd_last = 1'd0; -reg [13:0] soc_litedramcore_cmd_payload_a = 14'd0; -reg [2:0] soc_litedramcore_cmd_payload_ba = 3'd0; -reg soc_litedramcore_cmd_payload_cas = 1'd0; -reg soc_litedramcore_cmd_payload_ras = 1'd0; -reg soc_litedramcore_cmd_payload_we = 1'd0; -reg soc_litedramcore_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_cmd_payload_is_write = 1'd0; -wire soc_litedramcore_wants_refresh; -wire soc_litedramcore_wants_zqcs; -wire soc_litedramcore_timer_wait; -wire soc_litedramcore_timer_done0; -wire [9:0] soc_litedramcore_timer_count0; -wire soc_litedramcore_timer_done1; -reg [9:0] soc_litedramcore_timer_count1 = 10'd781; -wire soc_litedramcore_postponer_req_i; -reg soc_litedramcore_postponer_req_o = 1'd0; -reg soc_litedramcore_postponer_count = 1'd0; -reg soc_litedramcore_sequencer_start0 = 1'd0; -wire soc_litedramcore_sequencer_done0; -wire soc_litedramcore_sequencer_start1; -reg soc_litedramcore_sequencer_done1 = 1'd0; -reg [5:0] soc_litedramcore_sequencer_counter = 6'd0; -reg soc_litedramcore_sequencer_count = 1'd0; -wire soc_litedramcore_zqcs_timer_wait; -wire soc_litedramcore_zqcs_timer_done0; -wire [26:0] soc_litedramcore_zqcs_timer_count0; -wire soc_litedramcore_zqcs_timer_done1; -reg [26:0] soc_litedramcore_zqcs_timer_count1 = 27'd99999999; -reg soc_litedramcore_zqcs_executer_start = 1'd0; -reg soc_litedramcore_zqcs_executer_done = 1'd0; -reg [4:0] soc_litedramcore_zqcs_executer_counter = 5'd0; -wire soc_litedramcore_bankmachine0_req_valid; -wire soc_litedramcore_bankmachine0_req_ready; -wire soc_litedramcore_bankmachine0_req_we; -wire [20:0] soc_litedramcore_bankmachine0_req_addr; -wire soc_litedramcore_bankmachine0_req_lock; -reg soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine0_refresh_req; -reg soc_litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [3:0] soc_ddrphy_precharges0 = 4'd0; +reg [3:0] soc_ddrphy_precharges1 = 4'd0; +reg [3:0] soc_ddrphy_precharges2 = 4'd0; +reg [3:0] soc_ddrphy_precharges3 = 4'd0; +reg [3:0] soc_ddrphy_precharges4 = 4'd0; +reg [3:0] soc_ddrphy_precharges5 = 4'd0; +reg [3:0] soc_ddrphy_precharges6 = 4'd0; +reg [3:0] soc_ddrphy_precharges7 = 4'd0; +reg [3:0] soc_ddrphy_reads0 = 4'd0; +reg [3:0] soc_ddrphy_reads1 = 4'd0; +reg [3:0] soc_ddrphy_reads2 = 4'd0; +reg [3:0] soc_ddrphy_reads3 = 4'd0; +reg [3:0] soc_ddrphy_reads4 = 4'd0; +reg [3:0] soc_ddrphy_reads5 = 4'd0; +reg [3:0] soc_ddrphy_reads6 = 4'd0; +reg [3:0] soc_ddrphy_reads7 = 4'd0; +reg [3:0] soc_ddrphy_writes0 = 4'd0; +reg [3:0] soc_ddrphy_writes1 = 4'd0; +reg [3:0] soc_ddrphy_writes2 = 4'd0; +reg [3:0] soc_ddrphy_writes3 = 4'd0; +reg [3:0] soc_ddrphy_writes4 = 4'd0; +reg [3:0] soc_ddrphy_writes5 = 4'd0; +reg [3:0] soc_ddrphy_writes6 = 4'd0; +reg [3:0] soc_ddrphy_writes7 = 4'd0; +reg soc_init_done_re = 1'd0; +reg soc_init_done_storage = 1'd0; +reg soc_init_error_re = 1'd0; +reg soc_init_error_storage = 1'd0; +reg soc_int_rst = 1'd1; +reg soc_litedramcore_bankmachine0_auto_precharge = 1'd0; reg [13:0] soc_litedramcore_bankmachine0_cmd_payload_a = 14'd0; wire [2:0] soc_litedramcore_bankmachine0_cmd_payload_ba; reg soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0; reg soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; reg soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; reg soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine0_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine0_sink_valid; -wire soc_litedramcore_bankmachine0_sink_ready; -reg soc_litedramcore_bankmachine0_sink_first = 1'd0; -reg soc_litedramcore_bankmachine0_sink_last = 1'd0; -wire soc_litedramcore_bankmachine0_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine0_sink_payload_addr; -wire soc_litedramcore_bankmachine0_source_valid; -wire soc_litedramcore_bankmachine0_source_ready; -wire soc_litedramcore_bankmachine0_source_first; -wire soc_litedramcore_bankmachine0_source_last; -wire soc_litedramcore_bankmachine0_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine0_source_payload_addr; -wire soc_litedramcore_bankmachine0_syncfifo0_we; -wire soc_litedramcore_bankmachine0_syncfifo0_writable; -wire soc_litedramcore_bankmachine0_syncfifo0_re; -wire soc_litedramcore_bankmachine0_syncfifo0_readable; -wire [23:0] soc_litedramcore_bankmachine0_syncfifo0_din; -wire [23:0] soc_litedramcore_bankmachine0_syncfifo0_dout; -reg [4:0] soc_litedramcore_bankmachine0_level = 5'd0; -reg soc_litedramcore_bankmachine0_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine0_produce = 4'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_ready = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_valid = 1'd0; reg [3:0] soc_litedramcore_bankmachine0_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine0_wrport_adr = 4'd0; -wire [23:0] soc_litedramcore_bankmachine0_wrport_dat_r; -wire soc_litedramcore_bankmachine0_wrport_we; -wire [23:0] soc_litedramcore_bankmachine0_wrport_dat_w; wire soc_litedramcore_bankmachine0_do_read; -wire [3:0] soc_litedramcore_bankmachine0_rdport_adr; -wire [23:0] soc_litedramcore_bankmachine0_rdport_dat_r; -wire soc_litedramcore_bankmachine0_fifo_in_payload_we; -wire [20:0] soc_litedramcore_bankmachine0_fifo_in_payload_addr; wire soc_litedramcore_bankmachine0_fifo_in_first; wire soc_litedramcore_bankmachine0_fifo_in_last; -wire soc_litedramcore_bankmachine0_fifo_out_payload_we; -wire [20:0] soc_litedramcore_bankmachine0_fifo_out_payload_addr; +wire [20:0] soc_litedramcore_bankmachine0_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine0_fifo_in_payload_we; wire soc_litedramcore_bankmachine0_fifo_out_first; wire soc_litedramcore_bankmachine0_fifo_out_last; -wire soc_litedramcore_bankmachine0_sink_sink_valid; -wire soc_litedramcore_bankmachine0_sink_sink_ready; -wire soc_litedramcore_bankmachine0_sink_sink_first; -wire soc_litedramcore_bankmachine0_sink_sink_last; -wire soc_litedramcore_bankmachine0_sink_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine0_sink_sink_payload_addr; -wire soc_litedramcore_bankmachine0_source_source_valid; -wire soc_litedramcore_bankmachine0_source_source_ready; -wire soc_litedramcore_bankmachine0_source_source_first; -wire soc_litedramcore_bankmachine0_source_source_last; -wire soc_litedramcore_bankmachine0_source_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine0_source_source_payload_addr; -wire soc_litedramcore_bankmachine0_pipe_valid_sink_valid; -wire soc_litedramcore_bankmachine0_pipe_valid_sink_ready; +wire [20:0] soc_litedramcore_bankmachine0_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine0_fifo_out_payload_we; +reg [4:0] soc_litedramcore_bankmachine0_level = 5'd0; wire soc_litedramcore_bankmachine0_pipe_valid_sink_first; wire soc_litedramcore_bankmachine0_pipe_valid_sink_last; -wire soc_litedramcore_bankmachine0_pipe_valid_sink_payload_we; wire [20:0] soc_litedramcore_bankmachine0_pipe_valid_sink_payload_addr; -reg soc_litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; -wire soc_litedramcore_bankmachine0_pipe_valid_source_ready; +wire soc_litedramcore_bankmachine0_pipe_valid_sink_payload_we; +wire soc_litedramcore_bankmachine0_pipe_valid_sink_ready; +wire soc_litedramcore_bankmachine0_pipe_valid_sink_valid; reg soc_litedramcore_bankmachine0_pipe_valid_source_first = 1'd0; reg soc_litedramcore_bankmachine0_pipe_valid_source_last = 1'd0; -reg soc_litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; reg [20:0] soc_litedramcore_bankmachine0_pipe_valid_source_payload_addr = 21'd0; +reg soc_litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; +wire soc_litedramcore_bankmachine0_pipe_valid_source_ready; +reg soc_litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; +reg [3:0] soc_litedramcore_bankmachine0_produce = 4'd0; +wire [3:0] soc_litedramcore_bankmachine0_rdport_adr; +wire [23:0] soc_litedramcore_bankmachine0_rdport_dat_r; +reg soc_litedramcore_bankmachine0_refresh_gnt = 1'd0; +wire soc_litedramcore_bankmachine0_refresh_req; +reg soc_litedramcore_bankmachine0_replace = 1'd0; +wire [20:0] soc_litedramcore_bankmachine0_req_addr; +wire soc_litedramcore_bankmachine0_req_lock; +reg soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine0_req_ready; +wire soc_litedramcore_bankmachine0_req_valid; +reg soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0; +wire soc_litedramcore_bankmachine0_req_we; reg [13:0] soc_litedramcore_bankmachine0_row = 14'd0; -reg soc_litedramcore_bankmachine0_row_opened = 1'd0; -wire soc_litedramcore_bankmachine0_row_hit; -reg soc_litedramcore_bankmachine0_row_open = 1'd0; reg soc_litedramcore_bankmachine0_row_close = 1'd0; reg soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine0_twtpcon_valid; -reg soc_litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine0_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine0_trccon_valid; -reg soc_litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine0_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine0_trascon_valid; -reg soc_litedramcore_bankmachine0_trascon_ready = 1'd0; +wire soc_litedramcore_bankmachine0_row_hit; +reg soc_litedramcore_bankmachine0_row_open = 1'd0; +reg soc_litedramcore_bankmachine0_row_opened = 1'd0; +reg soc_litedramcore_bankmachine0_sink_first = 1'd0; +reg soc_litedramcore_bankmachine0_sink_last = 1'd0; +wire [20:0] soc_litedramcore_bankmachine0_sink_payload_addr; +wire soc_litedramcore_bankmachine0_sink_payload_we; +wire soc_litedramcore_bankmachine0_sink_ready; +wire soc_litedramcore_bankmachine0_sink_sink_first; +wire soc_litedramcore_bankmachine0_sink_sink_last; +wire [20:0] soc_litedramcore_bankmachine0_sink_sink_payload_addr; +wire soc_litedramcore_bankmachine0_sink_sink_payload_we; +wire soc_litedramcore_bankmachine0_sink_sink_ready; +wire soc_litedramcore_bankmachine0_sink_sink_valid; +wire soc_litedramcore_bankmachine0_sink_valid; +wire soc_litedramcore_bankmachine0_source_first; +wire soc_litedramcore_bankmachine0_source_last; +wire [20:0] soc_litedramcore_bankmachine0_source_payload_addr; +wire soc_litedramcore_bankmachine0_source_payload_we; +wire soc_litedramcore_bankmachine0_source_ready; +wire soc_litedramcore_bankmachine0_source_source_first; +wire soc_litedramcore_bankmachine0_source_source_last; +wire [20:0] soc_litedramcore_bankmachine0_source_source_payload_addr; +wire soc_litedramcore_bankmachine0_source_source_payload_we; +wire soc_litedramcore_bankmachine0_source_source_ready; +wire soc_litedramcore_bankmachine0_source_source_valid; +wire soc_litedramcore_bankmachine0_source_valid; +wire [23:0] soc_litedramcore_bankmachine0_syncfifo0_din; +wire [23:0] soc_litedramcore_bankmachine0_syncfifo0_dout; +wire soc_litedramcore_bankmachine0_syncfifo0_re; +wire soc_litedramcore_bankmachine0_syncfifo0_readable; +wire soc_litedramcore_bankmachine0_syncfifo0_we; +wire soc_litedramcore_bankmachine0_syncfifo0_writable; reg [2:0] soc_litedramcore_bankmachine0_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine1_req_valid; -wire soc_litedramcore_bankmachine1_req_ready; -wire soc_litedramcore_bankmachine1_req_we; -wire [20:0] soc_litedramcore_bankmachine1_req_addr; -wire soc_litedramcore_bankmachine1_req_lock; -reg soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine1_refresh_req; -reg soc_litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_ready = 1'd0; +reg soc_litedramcore_bankmachine0_trascon_ready = 1'd0; +wire soc_litedramcore_bankmachine0_trascon_valid; +reg [2:0] soc_litedramcore_bankmachine0_trccon_count = 3'd0; +reg soc_litedramcore_bankmachine0_trccon_ready = 1'd0; +wire soc_litedramcore_bankmachine0_trccon_valid; +reg [2:0] soc_litedramcore_bankmachine0_twtpcon_count = 3'd0; +reg soc_litedramcore_bankmachine0_twtpcon_ready = 1'd0; +wire soc_litedramcore_bankmachine0_twtpcon_valid; +reg [3:0] soc_litedramcore_bankmachine0_wrport_adr = 4'd0; +wire [23:0] soc_litedramcore_bankmachine0_wrport_dat_r; +wire [23:0] soc_litedramcore_bankmachine0_wrport_dat_w; +wire soc_litedramcore_bankmachine0_wrport_we; +reg soc_litedramcore_bankmachine1_auto_precharge = 1'd0; reg [13:0] soc_litedramcore_bankmachine1_cmd_payload_a = 14'd0; wire [2:0] soc_litedramcore_bankmachine1_cmd_payload_ba; reg soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0; reg soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; reg soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; reg soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine1_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine1_sink_valid; -wire soc_litedramcore_bankmachine1_sink_ready; -reg soc_litedramcore_bankmachine1_sink_first = 1'd0; -reg soc_litedramcore_bankmachine1_sink_last = 1'd0; -wire soc_litedramcore_bankmachine1_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine1_sink_payload_addr; -wire soc_litedramcore_bankmachine1_source_valid; -wire soc_litedramcore_bankmachine1_source_ready; -wire soc_litedramcore_bankmachine1_source_first; -wire soc_litedramcore_bankmachine1_source_last; -wire soc_litedramcore_bankmachine1_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine1_source_payload_addr; -wire soc_litedramcore_bankmachine1_syncfifo1_we; -wire soc_litedramcore_bankmachine1_syncfifo1_writable; -wire soc_litedramcore_bankmachine1_syncfifo1_re; -wire soc_litedramcore_bankmachine1_syncfifo1_readable; -wire [23:0] soc_litedramcore_bankmachine1_syncfifo1_din; -wire [23:0] soc_litedramcore_bankmachine1_syncfifo1_dout; -reg [4:0] soc_litedramcore_bankmachine1_level = 5'd0; -reg soc_litedramcore_bankmachine1_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine1_produce = 4'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_ready = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_valid = 1'd0; reg [3:0] soc_litedramcore_bankmachine1_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine1_wrport_adr = 4'd0; -wire [23:0] soc_litedramcore_bankmachine1_wrport_dat_r; -wire soc_litedramcore_bankmachine1_wrport_we; -wire [23:0] soc_litedramcore_bankmachine1_wrport_dat_w; wire soc_litedramcore_bankmachine1_do_read; -wire [3:0] soc_litedramcore_bankmachine1_rdport_adr; -wire [23:0] soc_litedramcore_bankmachine1_rdport_dat_r; -wire soc_litedramcore_bankmachine1_fifo_in_payload_we; -wire [20:0] soc_litedramcore_bankmachine1_fifo_in_payload_addr; wire soc_litedramcore_bankmachine1_fifo_in_first; wire soc_litedramcore_bankmachine1_fifo_in_last; -wire soc_litedramcore_bankmachine1_fifo_out_payload_we; -wire [20:0] soc_litedramcore_bankmachine1_fifo_out_payload_addr; +wire [20:0] soc_litedramcore_bankmachine1_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine1_fifo_in_payload_we; wire soc_litedramcore_bankmachine1_fifo_out_first; wire soc_litedramcore_bankmachine1_fifo_out_last; -wire soc_litedramcore_bankmachine1_sink_sink_valid; -wire soc_litedramcore_bankmachine1_sink_sink_ready; -wire soc_litedramcore_bankmachine1_sink_sink_first; -wire soc_litedramcore_bankmachine1_sink_sink_last; -wire soc_litedramcore_bankmachine1_sink_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine1_sink_sink_payload_addr; -wire soc_litedramcore_bankmachine1_source_source_valid; -wire soc_litedramcore_bankmachine1_source_source_ready; -wire soc_litedramcore_bankmachine1_source_source_first; -wire soc_litedramcore_bankmachine1_source_source_last; -wire soc_litedramcore_bankmachine1_source_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine1_source_source_payload_addr; -wire soc_litedramcore_bankmachine1_pipe_valid_sink_valid; -wire soc_litedramcore_bankmachine1_pipe_valid_sink_ready; +wire [20:0] soc_litedramcore_bankmachine1_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine1_fifo_out_payload_we; +reg [4:0] soc_litedramcore_bankmachine1_level = 5'd0; wire soc_litedramcore_bankmachine1_pipe_valid_sink_first; wire soc_litedramcore_bankmachine1_pipe_valid_sink_last; -wire soc_litedramcore_bankmachine1_pipe_valid_sink_payload_we; wire [20:0] soc_litedramcore_bankmachine1_pipe_valid_sink_payload_addr; -reg soc_litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; -wire soc_litedramcore_bankmachine1_pipe_valid_source_ready; +wire soc_litedramcore_bankmachine1_pipe_valid_sink_payload_we; +wire soc_litedramcore_bankmachine1_pipe_valid_sink_ready; +wire soc_litedramcore_bankmachine1_pipe_valid_sink_valid; reg soc_litedramcore_bankmachine1_pipe_valid_source_first = 1'd0; reg soc_litedramcore_bankmachine1_pipe_valid_source_last = 1'd0; -reg soc_litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; reg [20:0] soc_litedramcore_bankmachine1_pipe_valid_source_payload_addr = 21'd0; +reg soc_litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; +wire soc_litedramcore_bankmachine1_pipe_valid_source_ready; +reg soc_litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; +reg [3:0] soc_litedramcore_bankmachine1_produce = 4'd0; +wire [3:0] soc_litedramcore_bankmachine1_rdport_adr; +wire [23:0] soc_litedramcore_bankmachine1_rdport_dat_r; +reg soc_litedramcore_bankmachine1_refresh_gnt = 1'd0; +wire soc_litedramcore_bankmachine1_refresh_req; +reg soc_litedramcore_bankmachine1_replace = 1'd0; +wire [20:0] soc_litedramcore_bankmachine1_req_addr; +wire soc_litedramcore_bankmachine1_req_lock; +reg soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine1_req_ready; +wire soc_litedramcore_bankmachine1_req_valid; +reg soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0; +wire soc_litedramcore_bankmachine1_req_we; reg [13:0] soc_litedramcore_bankmachine1_row = 14'd0; -reg soc_litedramcore_bankmachine1_row_opened = 1'd0; -wire soc_litedramcore_bankmachine1_row_hit; -reg soc_litedramcore_bankmachine1_row_open = 1'd0; reg soc_litedramcore_bankmachine1_row_close = 1'd0; reg soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine1_twtpcon_valid; -reg soc_litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine1_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine1_trccon_valid; -reg soc_litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine1_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine1_trascon_valid; -reg soc_litedramcore_bankmachine1_trascon_ready = 1'd0; +wire soc_litedramcore_bankmachine1_row_hit; +reg soc_litedramcore_bankmachine1_row_open = 1'd0; +reg soc_litedramcore_bankmachine1_row_opened = 1'd0; +reg soc_litedramcore_bankmachine1_sink_first = 1'd0; +reg soc_litedramcore_bankmachine1_sink_last = 1'd0; +wire [20:0] soc_litedramcore_bankmachine1_sink_payload_addr; +wire soc_litedramcore_bankmachine1_sink_payload_we; +wire soc_litedramcore_bankmachine1_sink_ready; +wire soc_litedramcore_bankmachine1_sink_sink_first; +wire soc_litedramcore_bankmachine1_sink_sink_last; +wire [20:0] soc_litedramcore_bankmachine1_sink_sink_payload_addr; +wire soc_litedramcore_bankmachine1_sink_sink_payload_we; +wire soc_litedramcore_bankmachine1_sink_sink_ready; +wire soc_litedramcore_bankmachine1_sink_sink_valid; +wire soc_litedramcore_bankmachine1_sink_valid; +wire soc_litedramcore_bankmachine1_source_first; +wire soc_litedramcore_bankmachine1_source_last; +wire [20:0] soc_litedramcore_bankmachine1_source_payload_addr; +wire soc_litedramcore_bankmachine1_source_payload_we; +wire soc_litedramcore_bankmachine1_source_ready; +wire soc_litedramcore_bankmachine1_source_source_first; +wire soc_litedramcore_bankmachine1_source_source_last; +wire [20:0] soc_litedramcore_bankmachine1_source_source_payload_addr; +wire soc_litedramcore_bankmachine1_source_source_payload_we; +wire soc_litedramcore_bankmachine1_source_source_ready; +wire soc_litedramcore_bankmachine1_source_source_valid; +wire soc_litedramcore_bankmachine1_source_valid; +wire [23:0] soc_litedramcore_bankmachine1_syncfifo1_din; +wire [23:0] soc_litedramcore_bankmachine1_syncfifo1_dout; +wire soc_litedramcore_bankmachine1_syncfifo1_re; +wire soc_litedramcore_bankmachine1_syncfifo1_readable; +wire soc_litedramcore_bankmachine1_syncfifo1_we; +wire soc_litedramcore_bankmachine1_syncfifo1_writable; reg [2:0] soc_litedramcore_bankmachine1_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine2_req_valid; -wire soc_litedramcore_bankmachine2_req_ready; -wire soc_litedramcore_bankmachine2_req_we; -wire [20:0] soc_litedramcore_bankmachine2_req_addr; -wire soc_litedramcore_bankmachine2_req_lock; -reg soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine2_refresh_req; -reg soc_litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_ready = 1'd0; +reg soc_litedramcore_bankmachine1_trascon_ready = 1'd0; +wire soc_litedramcore_bankmachine1_trascon_valid; +reg [2:0] soc_litedramcore_bankmachine1_trccon_count = 3'd0; +reg soc_litedramcore_bankmachine1_trccon_ready = 1'd0; +wire soc_litedramcore_bankmachine1_trccon_valid; +reg [2:0] soc_litedramcore_bankmachine1_twtpcon_count = 3'd0; +reg soc_litedramcore_bankmachine1_twtpcon_ready = 1'd0; +wire soc_litedramcore_bankmachine1_twtpcon_valid; +reg [3:0] soc_litedramcore_bankmachine1_wrport_adr = 4'd0; +wire [23:0] soc_litedramcore_bankmachine1_wrport_dat_r; +wire [23:0] soc_litedramcore_bankmachine1_wrport_dat_w; +wire soc_litedramcore_bankmachine1_wrport_we; +reg soc_litedramcore_bankmachine2_auto_precharge = 1'd0; reg [13:0] soc_litedramcore_bankmachine2_cmd_payload_a = 14'd0; wire [2:0] soc_litedramcore_bankmachine2_cmd_payload_ba; reg soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0; reg soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; reg soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; reg soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine2_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine2_sink_valid; -wire soc_litedramcore_bankmachine2_sink_ready; -reg soc_litedramcore_bankmachine2_sink_first = 1'd0; -reg soc_litedramcore_bankmachine2_sink_last = 1'd0; -wire soc_litedramcore_bankmachine2_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine2_sink_payload_addr; -wire soc_litedramcore_bankmachine2_source_valid; -wire soc_litedramcore_bankmachine2_source_ready; -wire soc_litedramcore_bankmachine2_source_first; -wire soc_litedramcore_bankmachine2_source_last; -wire soc_litedramcore_bankmachine2_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine2_source_payload_addr; -wire soc_litedramcore_bankmachine2_syncfifo2_we; -wire soc_litedramcore_bankmachine2_syncfifo2_writable; -wire soc_litedramcore_bankmachine2_syncfifo2_re; -wire soc_litedramcore_bankmachine2_syncfifo2_readable; -wire [23:0] soc_litedramcore_bankmachine2_syncfifo2_din; -wire [23:0] soc_litedramcore_bankmachine2_syncfifo2_dout; -reg [4:0] soc_litedramcore_bankmachine2_level = 5'd0; -reg soc_litedramcore_bankmachine2_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine2_produce = 4'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_ready = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_valid = 1'd0; reg [3:0] soc_litedramcore_bankmachine2_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine2_wrport_adr = 4'd0; -wire [23:0] soc_litedramcore_bankmachine2_wrport_dat_r; -wire soc_litedramcore_bankmachine2_wrport_we; -wire [23:0] soc_litedramcore_bankmachine2_wrport_dat_w; wire soc_litedramcore_bankmachine2_do_read; -wire [3:0] soc_litedramcore_bankmachine2_rdport_adr; -wire [23:0] soc_litedramcore_bankmachine2_rdport_dat_r; -wire soc_litedramcore_bankmachine2_fifo_in_payload_we; -wire [20:0] soc_litedramcore_bankmachine2_fifo_in_payload_addr; wire soc_litedramcore_bankmachine2_fifo_in_first; wire soc_litedramcore_bankmachine2_fifo_in_last; -wire soc_litedramcore_bankmachine2_fifo_out_payload_we; -wire [20:0] soc_litedramcore_bankmachine2_fifo_out_payload_addr; +wire [20:0] soc_litedramcore_bankmachine2_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine2_fifo_in_payload_we; wire soc_litedramcore_bankmachine2_fifo_out_first; wire soc_litedramcore_bankmachine2_fifo_out_last; -wire soc_litedramcore_bankmachine2_sink_sink_valid; -wire soc_litedramcore_bankmachine2_sink_sink_ready; -wire soc_litedramcore_bankmachine2_sink_sink_first; -wire soc_litedramcore_bankmachine2_sink_sink_last; -wire soc_litedramcore_bankmachine2_sink_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine2_sink_sink_payload_addr; -wire soc_litedramcore_bankmachine2_source_source_valid; -wire soc_litedramcore_bankmachine2_source_source_ready; -wire soc_litedramcore_bankmachine2_source_source_first; -wire soc_litedramcore_bankmachine2_source_source_last; -wire soc_litedramcore_bankmachine2_source_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine2_source_source_payload_addr; -wire soc_litedramcore_bankmachine2_pipe_valid_sink_valid; -wire soc_litedramcore_bankmachine2_pipe_valid_sink_ready; +wire [20:0] soc_litedramcore_bankmachine2_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine2_fifo_out_payload_we; +reg [4:0] soc_litedramcore_bankmachine2_level = 5'd0; wire soc_litedramcore_bankmachine2_pipe_valid_sink_first; wire soc_litedramcore_bankmachine2_pipe_valid_sink_last; -wire soc_litedramcore_bankmachine2_pipe_valid_sink_payload_we; wire [20:0] soc_litedramcore_bankmachine2_pipe_valid_sink_payload_addr; -reg soc_litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; -wire soc_litedramcore_bankmachine2_pipe_valid_source_ready; +wire soc_litedramcore_bankmachine2_pipe_valid_sink_payload_we; +wire soc_litedramcore_bankmachine2_pipe_valid_sink_ready; +wire soc_litedramcore_bankmachine2_pipe_valid_sink_valid; reg soc_litedramcore_bankmachine2_pipe_valid_source_first = 1'd0; reg soc_litedramcore_bankmachine2_pipe_valid_source_last = 1'd0; -reg soc_litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; reg [20:0] soc_litedramcore_bankmachine2_pipe_valid_source_payload_addr = 21'd0; +reg soc_litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; +wire soc_litedramcore_bankmachine2_pipe_valid_source_ready; +reg soc_litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; +reg [3:0] soc_litedramcore_bankmachine2_produce = 4'd0; +wire [3:0] soc_litedramcore_bankmachine2_rdport_adr; +wire [23:0] soc_litedramcore_bankmachine2_rdport_dat_r; +reg soc_litedramcore_bankmachine2_refresh_gnt = 1'd0; +wire soc_litedramcore_bankmachine2_refresh_req; +reg soc_litedramcore_bankmachine2_replace = 1'd0; +wire [20:0] soc_litedramcore_bankmachine2_req_addr; +wire soc_litedramcore_bankmachine2_req_lock; +reg soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine2_req_ready; +wire soc_litedramcore_bankmachine2_req_valid; +reg soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0; +wire soc_litedramcore_bankmachine2_req_we; reg [13:0] soc_litedramcore_bankmachine2_row = 14'd0; -reg soc_litedramcore_bankmachine2_row_opened = 1'd0; -wire soc_litedramcore_bankmachine2_row_hit; -reg soc_litedramcore_bankmachine2_row_open = 1'd0; reg soc_litedramcore_bankmachine2_row_close = 1'd0; reg soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine2_twtpcon_valid; -reg soc_litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine2_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine2_trccon_valid; -reg soc_litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine2_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine2_trascon_valid; -reg soc_litedramcore_bankmachine2_trascon_ready = 1'd0; +wire soc_litedramcore_bankmachine2_row_hit; +reg soc_litedramcore_bankmachine2_row_open = 1'd0; +reg soc_litedramcore_bankmachine2_row_opened = 1'd0; +reg soc_litedramcore_bankmachine2_sink_first = 1'd0; +reg soc_litedramcore_bankmachine2_sink_last = 1'd0; +wire [20:0] soc_litedramcore_bankmachine2_sink_payload_addr; +wire soc_litedramcore_bankmachine2_sink_payload_we; +wire soc_litedramcore_bankmachine2_sink_ready; +wire soc_litedramcore_bankmachine2_sink_sink_first; +wire soc_litedramcore_bankmachine2_sink_sink_last; +wire [20:0] soc_litedramcore_bankmachine2_sink_sink_payload_addr; +wire soc_litedramcore_bankmachine2_sink_sink_payload_we; +wire soc_litedramcore_bankmachine2_sink_sink_ready; +wire soc_litedramcore_bankmachine2_sink_sink_valid; +wire soc_litedramcore_bankmachine2_sink_valid; +wire soc_litedramcore_bankmachine2_source_first; +wire soc_litedramcore_bankmachine2_source_last; +wire [20:0] soc_litedramcore_bankmachine2_source_payload_addr; +wire soc_litedramcore_bankmachine2_source_payload_we; +wire soc_litedramcore_bankmachine2_source_ready; +wire soc_litedramcore_bankmachine2_source_source_first; +wire soc_litedramcore_bankmachine2_source_source_last; +wire [20:0] soc_litedramcore_bankmachine2_source_source_payload_addr; +wire soc_litedramcore_bankmachine2_source_source_payload_we; +wire soc_litedramcore_bankmachine2_source_source_ready; +wire soc_litedramcore_bankmachine2_source_source_valid; +wire soc_litedramcore_bankmachine2_source_valid; +wire [23:0] soc_litedramcore_bankmachine2_syncfifo2_din; +wire [23:0] soc_litedramcore_bankmachine2_syncfifo2_dout; +wire soc_litedramcore_bankmachine2_syncfifo2_re; +wire soc_litedramcore_bankmachine2_syncfifo2_readable; +wire soc_litedramcore_bankmachine2_syncfifo2_we; +wire soc_litedramcore_bankmachine2_syncfifo2_writable; reg [2:0] soc_litedramcore_bankmachine2_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine3_req_valid; -wire soc_litedramcore_bankmachine3_req_ready; -wire soc_litedramcore_bankmachine3_req_we; -wire [20:0] soc_litedramcore_bankmachine3_req_addr; -wire soc_litedramcore_bankmachine3_req_lock; -reg soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine3_refresh_req; -reg soc_litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_ready = 1'd0; +reg soc_litedramcore_bankmachine2_trascon_ready = 1'd0; +wire soc_litedramcore_bankmachine2_trascon_valid; +reg [2:0] soc_litedramcore_bankmachine2_trccon_count = 3'd0; +reg soc_litedramcore_bankmachine2_trccon_ready = 1'd0; +wire soc_litedramcore_bankmachine2_trccon_valid; +reg [2:0] soc_litedramcore_bankmachine2_twtpcon_count = 3'd0; +reg soc_litedramcore_bankmachine2_twtpcon_ready = 1'd0; +wire soc_litedramcore_bankmachine2_twtpcon_valid; +reg [3:0] soc_litedramcore_bankmachine2_wrport_adr = 4'd0; +wire [23:0] soc_litedramcore_bankmachine2_wrport_dat_r; +wire [23:0] soc_litedramcore_bankmachine2_wrport_dat_w; +wire soc_litedramcore_bankmachine2_wrport_we; +reg soc_litedramcore_bankmachine3_auto_precharge = 1'd0; reg [13:0] soc_litedramcore_bankmachine3_cmd_payload_a = 14'd0; wire [2:0] soc_litedramcore_bankmachine3_cmd_payload_ba; reg soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0; reg soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; reg soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; reg soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine3_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine3_sink_valid; -wire soc_litedramcore_bankmachine3_sink_ready; -reg soc_litedramcore_bankmachine3_sink_first = 1'd0; -reg soc_litedramcore_bankmachine3_sink_last = 1'd0; -wire soc_litedramcore_bankmachine3_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine3_sink_payload_addr; -wire soc_litedramcore_bankmachine3_source_valid; -wire soc_litedramcore_bankmachine3_source_ready; -wire soc_litedramcore_bankmachine3_source_first; -wire soc_litedramcore_bankmachine3_source_last; -wire soc_litedramcore_bankmachine3_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine3_source_payload_addr; -wire soc_litedramcore_bankmachine3_syncfifo3_we; -wire soc_litedramcore_bankmachine3_syncfifo3_writable; -wire soc_litedramcore_bankmachine3_syncfifo3_re; -wire soc_litedramcore_bankmachine3_syncfifo3_readable; -wire [23:0] soc_litedramcore_bankmachine3_syncfifo3_din; -wire [23:0] soc_litedramcore_bankmachine3_syncfifo3_dout; -reg [4:0] soc_litedramcore_bankmachine3_level = 5'd0; -reg soc_litedramcore_bankmachine3_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine3_produce = 4'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_ready = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_valid = 1'd0; reg [3:0] soc_litedramcore_bankmachine3_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine3_wrport_adr = 4'd0; -wire [23:0] soc_litedramcore_bankmachine3_wrport_dat_r; -wire soc_litedramcore_bankmachine3_wrport_we; -wire [23:0] soc_litedramcore_bankmachine3_wrport_dat_w; wire soc_litedramcore_bankmachine3_do_read; -wire [3:0] soc_litedramcore_bankmachine3_rdport_adr; -wire [23:0] soc_litedramcore_bankmachine3_rdport_dat_r; -wire soc_litedramcore_bankmachine3_fifo_in_payload_we; -wire [20:0] soc_litedramcore_bankmachine3_fifo_in_payload_addr; wire soc_litedramcore_bankmachine3_fifo_in_first; wire soc_litedramcore_bankmachine3_fifo_in_last; -wire soc_litedramcore_bankmachine3_fifo_out_payload_we; -wire [20:0] soc_litedramcore_bankmachine3_fifo_out_payload_addr; +wire [20:0] soc_litedramcore_bankmachine3_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine3_fifo_in_payload_we; wire soc_litedramcore_bankmachine3_fifo_out_first; wire soc_litedramcore_bankmachine3_fifo_out_last; -wire soc_litedramcore_bankmachine3_sink_sink_valid; -wire soc_litedramcore_bankmachine3_sink_sink_ready; -wire soc_litedramcore_bankmachine3_sink_sink_first; -wire soc_litedramcore_bankmachine3_sink_sink_last; -wire soc_litedramcore_bankmachine3_sink_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine3_sink_sink_payload_addr; -wire soc_litedramcore_bankmachine3_source_source_valid; -wire soc_litedramcore_bankmachine3_source_source_ready; -wire soc_litedramcore_bankmachine3_source_source_first; -wire soc_litedramcore_bankmachine3_source_source_last; -wire soc_litedramcore_bankmachine3_source_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine3_source_source_payload_addr; -wire soc_litedramcore_bankmachine3_pipe_valid_sink_valid; -wire soc_litedramcore_bankmachine3_pipe_valid_sink_ready; +wire [20:0] soc_litedramcore_bankmachine3_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine3_fifo_out_payload_we; +reg [4:0] soc_litedramcore_bankmachine3_level = 5'd0; wire soc_litedramcore_bankmachine3_pipe_valid_sink_first; wire soc_litedramcore_bankmachine3_pipe_valid_sink_last; -wire soc_litedramcore_bankmachine3_pipe_valid_sink_payload_we; wire [20:0] soc_litedramcore_bankmachine3_pipe_valid_sink_payload_addr; -reg soc_litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; -wire soc_litedramcore_bankmachine3_pipe_valid_source_ready; +wire soc_litedramcore_bankmachine3_pipe_valid_sink_payload_we; +wire soc_litedramcore_bankmachine3_pipe_valid_sink_ready; +wire soc_litedramcore_bankmachine3_pipe_valid_sink_valid; reg soc_litedramcore_bankmachine3_pipe_valid_source_first = 1'd0; reg soc_litedramcore_bankmachine3_pipe_valid_source_last = 1'd0; -reg soc_litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; reg [20:0] soc_litedramcore_bankmachine3_pipe_valid_source_payload_addr = 21'd0; +reg soc_litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; +wire soc_litedramcore_bankmachine3_pipe_valid_source_ready; +reg soc_litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; +reg [3:0] soc_litedramcore_bankmachine3_produce = 4'd0; +wire [3:0] soc_litedramcore_bankmachine3_rdport_adr; +wire [23:0] soc_litedramcore_bankmachine3_rdport_dat_r; +reg soc_litedramcore_bankmachine3_refresh_gnt = 1'd0; +wire soc_litedramcore_bankmachine3_refresh_req; +reg soc_litedramcore_bankmachine3_replace = 1'd0; +wire [20:0] soc_litedramcore_bankmachine3_req_addr; +wire soc_litedramcore_bankmachine3_req_lock; +reg soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine3_req_ready; +wire soc_litedramcore_bankmachine3_req_valid; +reg soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0; +wire soc_litedramcore_bankmachine3_req_we; reg [13:0] soc_litedramcore_bankmachine3_row = 14'd0; -reg soc_litedramcore_bankmachine3_row_opened = 1'd0; -wire soc_litedramcore_bankmachine3_row_hit; -reg soc_litedramcore_bankmachine3_row_open = 1'd0; reg soc_litedramcore_bankmachine3_row_close = 1'd0; reg soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine3_twtpcon_valid; -reg soc_litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine3_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine3_trccon_valid; -reg soc_litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine3_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine3_trascon_valid; -reg soc_litedramcore_bankmachine3_trascon_ready = 1'd0; +wire soc_litedramcore_bankmachine3_row_hit; +reg soc_litedramcore_bankmachine3_row_open = 1'd0; +reg soc_litedramcore_bankmachine3_row_opened = 1'd0; +reg soc_litedramcore_bankmachine3_sink_first = 1'd0; +reg soc_litedramcore_bankmachine3_sink_last = 1'd0; +wire [20:0] soc_litedramcore_bankmachine3_sink_payload_addr; +wire soc_litedramcore_bankmachine3_sink_payload_we; +wire soc_litedramcore_bankmachine3_sink_ready; +wire soc_litedramcore_bankmachine3_sink_sink_first; +wire soc_litedramcore_bankmachine3_sink_sink_last; +wire [20:0] soc_litedramcore_bankmachine3_sink_sink_payload_addr; +wire soc_litedramcore_bankmachine3_sink_sink_payload_we; +wire soc_litedramcore_bankmachine3_sink_sink_ready; +wire soc_litedramcore_bankmachine3_sink_sink_valid; +wire soc_litedramcore_bankmachine3_sink_valid; +wire soc_litedramcore_bankmachine3_source_first; +wire soc_litedramcore_bankmachine3_source_last; +wire [20:0] soc_litedramcore_bankmachine3_source_payload_addr; +wire soc_litedramcore_bankmachine3_source_payload_we; +wire soc_litedramcore_bankmachine3_source_ready; +wire soc_litedramcore_bankmachine3_source_source_first; +wire soc_litedramcore_bankmachine3_source_source_last; +wire [20:0] soc_litedramcore_bankmachine3_source_source_payload_addr; +wire soc_litedramcore_bankmachine3_source_source_payload_we; +wire soc_litedramcore_bankmachine3_source_source_ready; +wire soc_litedramcore_bankmachine3_source_source_valid; +wire soc_litedramcore_bankmachine3_source_valid; +wire [23:0] soc_litedramcore_bankmachine3_syncfifo3_din; +wire [23:0] soc_litedramcore_bankmachine3_syncfifo3_dout; +wire soc_litedramcore_bankmachine3_syncfifo3_re; +wire soc_litedramcore_bankmachine3_syncfifo3_readable; +wire soc_litedramcore_bankmachine3_syncfifo3_we; +wire soc_litedramcore_bankmachine3_syncfifo3_writable; reg [2:0] soc_litedramcore_bankmachine3_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine4_req_valid; -wire soc_litedramcore_bankmachine4_req_ready; -wire soc_litedramcore_bankmachine4_req_we; -wire [20:0] soc_litedramcore_bankmachine4_req_addr; -wire soc_litedramcore_bankmachine4_req_lock; -reg soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine4_refresh_req; -reg soc_litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_ready = 1'd0; +reg soc_litedramcore_bankmachine3_trascon_ready = 1'd0; +wire soc_litedramcore_bankmachine3_trascon_valid; +reg [2:0] soc_litedramcore_bankmachine3_trccon_count = 3'd0; +reg soc_litedramcore_bankmachine3_trccon_ready = 1'd0; +wire soc_litedramcore_bankmachine3_trccon_valid; +reg [2:0] soc_litedramcore_bankmachine3_twtpcon_count = 3'd0; +reg soc_litedramcore_bankmachine3_twtpcon_ready = 1'd0; +wire soc_litedramcore_bankmachine3_twtpcon_valid; +reg [3:0] soc_litedramcore_bankmachine3_wrport_adr = 4'd0; +wire [23:0] soc_litedramcore_bankmachine3_wrport_dat_r; +wire [23:0] soc_litedramcore_bankmachine3_wrport_dat_w; +wire soc_litedramcore_bankmachine3_wrport_we; +reg soc_litedramcore_bankmachine4_auto_precharge = 1'd0; reg [13:0] soc_litedramcore_bankmachine4_cmd_payload_a = 14'd0; wire [2:0] soc_litedramcore_bankmachine4_cmd_payload_ba; reg soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0; reg soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; reg soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; reg soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine4_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine4_sink_valid; -wire soc_litedramcore_bankmachine4_sink_ready; -reg soc_litedramcore_bankmachine4_sink_first = 1'd0; -reg soc_litedramcore_bankmachine4_sink_last = 1'd0; -wire soc_litedramcore_bankmachine4_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine4_sink_payload_addr; -wire soc_litedramcore_bankmachine4_source_valid; -wire soc_litedramcore_bankmachine4_source_ready; -wire soc_litedramcore_bankmachine4_source_first; -wire soc_litedramcore_bankmachine4_source_last; -wire soc_litedramcore_bankmachine4_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine4_source_payload_addr; -wire soc_litedramcore_bankmachine4_syncfifo4_we; -wire soc_litedramcore_bankmachine4_syncfifo4_writable; -wire soc_litedramcore_bankmachine4_syncfifo4_re; -wire soc_litedramcore_bankmachine4_syncfifo4_readable; -wire [23:0] soc_litedramcore_bankmachine4_syncfifo4_din; -wire [23:0] soc_litedramcore_bankmachine4_syncfifo4_dout; -reg [4:0] soc_litedramcore_bankmachine4_level = 5'd0; -reg soc_litedramcore_bankmachine4_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine4_produce = 4'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_ready = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_valid = 1'd0; reg [3:0] soc_litedramcore_bankmachine4_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine4_wrport_adr = 4'd0; -wire [23:0] soc_litedramcore_bankmachine4_wrport_dat_r; -wire soc_litedramcore_bankmachine4_wrport_we; -wire [23:0] soc_litedramcore_bankmachine4_wrport_dat_w; wire soc_litedramcore_bankmachine4_do_read; -wire [3:0] soc_litedramcore_bankmachine4_rdport_adr; -wire [23:0] soc_litedramcore_bankmachine4_rdport_dat_r; -wire soc_litedramcore_bankmachine4_fifo_in_payload_we; -wire [20:0] soc_litedramcore_bankmachine4_fifo_in_payload_addr; wire soc_litedramcore_bankmachine4_fifo_in_first; wire soc_litedramcore_bankmachine4_fifo_in_last; -wire soc_litedramcore_bankmachine4_fifo_out_payload_we; -wire [20:0] soc_litedramcore_bankmachine4_fifo_out_payload_addr; +wire [20:0] soc_litedramcore_bankmachine4_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine4_fifo_in_payload_we; wire soc_litedramcore_bankmachine4_fifo_out_first; wire soc_litedramcore_bankmachine4_fifo_out_last; -wire soc_litedramcore_bankmachine4_sink_sink_valid; -wire soc_litedramcore_bankmachine4_sink_sink_ready; -wire soc_litedramcore_bankmachine4_sink_sink_first; -wire soc_litedramcore_bankmachine4_sink_sink_last; -wire soc_litedramcore_bankmachine4_sink_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine4_sink_sink_payload_addr; -wire soc_litedramcore_bankmachine4_source_source_valid; -wire soc_litedramcore_bankmachine4_source_source_ready; -wire soc_litedramcore_bankmachine4_source_source_first; -wire soc_litedramcore_bankmachine4_source_source_last; -wire soc_litedramcore_bankmachine4_source_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine4_source_source_payload_addr; -wire soc_litedramcore_bankmachine4_pipe_valid_sink_valid; -wire soc_litedramcore_bankmachine4_pipe_valid_sink_ready; +wire [20:0] soc_litedramcore_bankmachine4_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine4_fifo_out_payload_we; +reg [4:0] soc_litedramcore_bankmachine4_level = 5'd0; wire soc_litedramcore_bankmachine4_pipe_valid_sink_first; wire soc_litedramcore_bankmachine4_pipe_valid_sink_last; -wire soc_litedramcore_bankmachine4_pipe_valid_sink_payload_we; wire [20:0] soc_litedramcore_bankmachine4_pipe_valid_sink_payload_addr; -reg soc_litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; -wire soc_litedramcore_bankmachine4_pipe_valid_source_ready; +wire soc_litedramcore_bankmachine4_pipe_valid_sink_payload_we; +wire soc_litedramcore_bankmachine4_pipe_valid_sink_ready; +wire soc_litedramcore_bankmachine4_pipe_valid_sink_valid; reg soc_litedramcore_bankmachine4_pipe_valid_source_first = 1'd0; reg soc_litedramcore_bankmachine4_pipe_valid_source_last = 1'd0; -reg soc_litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; reg [20:0] soc_litedramcore_bankmachine4_pipe_valid_source_payload_addr = 21'd0; +reg soc_litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; +wire soc_litedramcore_bankmachine4_pipe_valid_source_ready; +reg soc_litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; +reg [3:0] soc_litedramcore_bankmachine4_produce = 4'd0; +wire [3:0] soc_litedramcore_bankmachine4_rdport_adr; +wire [23:0] soc_litedramcore_bankmachine4_rdport_dat_r; +reg soc_litedramcore_bankmachine4_refresh_gnt = 1'd0; +wire soc_litedramcore_bankmachine4_refresh_req; +reg soc_litedramcore_bankmachine4_replace = 1'd0; +wire [20:0] soc_litedramcore_bankmachine4_req_addr; +wire soc_litedramcore_bankmachine4_req_lock; +reg soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine4_req_ready; +wire soc_litedramcore_bankmachine4_req_valid; +reg soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0; +wire soc_litedramcore_bankmachine4_req_we; reg [13:0] soc_litedramcore_bankmachine4_row = 14'd0; -reg soc_litedramcore_bankmachine4_row_opened = 1'd0; -wire soc_litedramcore_bankmachine4_row_hit; -reg soc_litedramcore_bankmachine4_row_open = 1'd0; reg soc_litedramcore_bankmachine4_row_close = 1'd0; reg soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine4_twtpcon_valid; -reg soc_litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine4_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine4_trccon_valid; -reg soc_litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine4_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine4_trascon_valid; -reg soc_litedramcore_bankmachine4_trascon_ready = 1'd0; +wire soc_litedramcore_bankmachine4_row_hit; +reg soc_litedramcore_bankmachine4_row_open = 1'd0; +reg soc_litedramcore_bankmachine4_row_opened = 1'd0; +reg soc_litedramcore_bankmachine4_sink_first = 1'd0; +reg soc_litedramcore_bankmachine4_sink_last = 1'd0; +wire [20:0] soc_litedramcore_bankmachine4_sink_payload_addr; +wire soc_litedramcore_bankmachine4_sink_payload_we; +wire soc_litedramcore_bankmachine4_sink_ready; +wire soc_litedramcore_bankmachine4_sink_sink_first; +wire soc_litedramcore_bankmachine4_sink_sink_last; +wire [20:0] soc_litedramcore_bankmachine4_sink_sink_payload_addr; +wire soc_litedramcore_bankmachine4_sink_sink_payload_we; +wire soc_litedramcore_bankmachine4_sink_sink_ready; +wire soc_litedramcore_bankmachine4_sink_sink_valid; +wire soc_litedramcore_bankmachine4_sink_valid; +wire soc_litedramcore_bankmachine4_source_first; +wire soc_litedramcore_bankmachine4_source_last; +wire [20:0] soc_litedramcore_bankmachine4_source_payload_addr; +wire soc_litedramcore_bankmachine4_source_payload_we; +wire soc_litedramcore_bankmachine4_source_ready; +wire soc_litedramcore_bankmachine4_source_source_first; +wire soc_litedramcore_bankmachine4_source_source_last; +wire [20:0] soc_litedramcore_bankmachine4_source_source_payload_addr; +wire soc_litedramcore_bankmachine4_source_source_payload_we; +wire soc_litedramcore_bankmachine4_source_source_ready; +wire soc_litedramcore_bankmachine4_source_source_valid; +wire soc_litedramcore_bankmachine4_source_valid; +wire [23:0] soc_litedramcore_bankmachine4_syncfifo4_din; +wire [23:0] soc_litedramcore_bankmachine4_syncfifo4_dout; +wire soc_litedramcore_bankmachine4_syncfifo4_re; +wire soc_litedramcore_bankmachine4_syncfifo4_readable; +wire soc_litedramcore_bankmachine4_syncfifo4_we; +wire soc_litedramcore_bankmachine4_syncfifo4_writable; reg [2:0] soc_litedramcore_bankmachine4_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine5_req_valid; -wire soc_litedramcore_bankmachine5_req_ready; -wire soc_litedramcore_bankmachine5_req_we; -wire [20:0] soc_litedramcore_bankmachine5_req_addr; -wire soc_litedramcore_bankmachine5_req_lock; -reg soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine5_refresh_req; -reg soc_litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_ready = 1'd0; +reg soc_litedramcore_bankmachine4_trascon_ready = 1'd0; +wire soc_litedramcore_bankmachine4_trascon_valid; +reg [2:0] soc_litedramcore_bankmachine4_trccon_count = 3'd0; +reg soc_litedramcore_bankmachine4_trccon_ready = 1'd0; +wire soc_litedramcore_bankmachine4_trccon_valid; +reg [2:0] soc_litedramcore_bankmachine4_twtpcon_count = 3'd0; +reg soc_litedramcore_bankmachine4_twtpcon_ready = 1'd0; +wire soc_litedramcore_bankmachine4_twtpcon_valid; +reg [3:0] soc_litedramcore_bankmachine4_wrport_adr = 4'd0; +wire [23:0] soc_litedramcore_bankmachine4_wrport_dat_r; +wire [23:0] soc_litedramcore_bankmachine4_wrport_dat_w; +wire soc_litedramcore_bankmachine4_wrport_we; +reg soc_litedramcore_bankmachine5_auto_precharge = 1'd0; reg [13:0] soc_litedramcore_bankmachine5_cmd_payload_a = 14'd0; wire [2:0] soc_litedramcore_bankmachine5_cmd_payload_ba; reg soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0; reg soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; reg soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; reg soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine5_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine5_sink_valid; -wire soc_litedramcore_bankmachine5_sink_ready; -reg soc_litedramcore_bankmachine5_sink_first = 1'd0; -reg soc_litedramcore_bankmachine5_sink_last = 1'd0; -wire soc_litedramcore_bankmachine5_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine5_sink_payload_addr; -wire soc_litedramcore_bankmachine5_source_valid; -wire soc_litedramcore_bankmachine5_source_ready; -wire soc_litedramcore_bankmachine5_source_first; -wire soc_litedramcore_bankmachine5_source_last; -wire soc_litedramcore_bankmachine5_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine5_source_payload_addr; -wire soc_litedramcore_bankmachine5_syncfifo5_we; -wire soc_litedramcore_bankmachine5_syncfifo5_writable; -wire soc_litedramcore_bankmachine5_syncfifo5_re; -wire soc_litedramcore_bankmachine5_syncfifo5_readable; -wire [23:0] soc_litedramcore_bankmachine5_syncfifo5_din; -wire [23:0] soc_litedramcore_bankmachine5_syncfifo5_dout; -reg [4:0] soc_litedramcore_bankmachine5_level = 5'd0; -reg soc_litedramcore_bankmachine5_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine5_produce = 4'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_ready = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_valid = 1'd0; reg [3:0] soc_litedramcore_bankmachine5_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine5_wrport_adr = 4'd0; -wire [23:0] soc_litedramcore_bankmachine5_wrport_dat_r; -wire soc_litedramcore_bankmachine5_wrport_we; -wire [23:0] soc_litedramcore_bankmachine5_wrport_dat_w; wire soc_litedramcore_bankmachine5_do_read; -wire [3:0] soc_litedramcore_bankmachine5_rdport_adr; -wire [23:0] soc_litedramcore_bankmachine5_rdport_dat_r; -wire soc_litedramcore_bankmachine5_fifo_in_payload_we; -wire [20:0] soc_litedramcore_bankmachine5_fifo_in_payload_addr; wire soc_litedramcore_bankmachine5_fifo_in_first; wire soc_litedramcore_bankmachine5_fifo_in_last; -wire soc_litedramcore_bankmachine5_fifo_out_payload_we; -wire [20:0] soc_litedramcore_bankmachine5_fifo_out_payload_addr; +wire [20:0] soc_litedramcore_bankmachine5_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine5_fifo_in_payload_we; wire soc_litedramcore_bankmachine5_fifo_out_first; wire soc_litedramcore_bankmachine5_fifo_out_last; -wire soc_litedramcore_bankmachine5_sink_sink_valid; -wire soc_litedramcore_bankmachine5_sink_sink_ready; -wire soc_litedramcore_bankmachine5_sink_sink_first; -wire soc_litedramcore_bankmachine5_sink_sink_last; -wire soc_litedramcore_bankmachine5_sink_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine5_sink_sink_payload_addr; -wire soc_litedramcore_bankmachine5_source_source_valid; -wire soc_litedramcore_bankmachine5_source_source_ready; -wire soc_litedramcore_bankmachine5_source_source_first; -wire soc_litedramcore_bankmachine5_source_source_last; -wire soc_litedramcore_bankmachine5_source_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine5_source_source_payload_addr; -wire soc_litedramcore_bankmachine5_pipe_valid_sink_valid; -wire soc_litedramcore_bankmachine5_pipe_valid_sink_ready; +wire [20:0] soc_litedramcore_bankmachine5_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine5_fifo_out_payload_we; +reg [4:0] soc_litedramcore_bankmachine5_level = 5'd0; wire soc_litedramcore_bankmachine5_pipe_valid_sink_first; wire soc_litedramcore_bankmachine5_pipe_valid_sink_last; -wire soc_litedramcore_bankmachine5_pipe_valid_sink_payload_we; wire [20:0] soc_litedramcore_bankmachine5_pipe_valid_sink_payload_addr; -reg soc_litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; -wire soc_litedramcore_bankmachine5_pipe_valid_source_ready; +wire soc_litedramcore_bankmachine5_pipe_valid_sink_payload_we; +wire soc_litedramcore_bankmachine5_pipe_valid_sink_ready; +wire soc_litedramcore_bankmachine5_pipe_valid_sink_valid; reg soc_litedramcore_bankmachine5_pipe_valid_source_first = 1'd0; reg soc_litedramcore_bankmachine5_pipe_valid_source_last = 1'd0; -reg soc_litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; reg [20:0] soc_litedramcore_bankmachine5_pipe_valid_source_payload_addr = 21'd0; +reg soc_litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; +wire soc_litedramcore_bankmachine5_pipe_valid_source_ready; +reg soc_litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; +reg [3:0] soc_litedramcore_bankmachine5_produce = 4'd0; +wire [3:0] soc_litedramcore_bankmachine5_rdport_adr; +wire [23:0] soc_litedramcore_bankmachine5_rdport_dat_r; +reg soc_litedramcore_bankmachine5_refresh_gnt = 1'd0; +wire soc_litedramcore_bankmachine5_refresh_req; +reg soc_litedramcore_bankmachine5_replace = 1'd0; +wire [20:0] soc_litedramcore_bankmachine5_req_addr; +wire soc_litedramcore_bankmachine5_req_lock; +reg soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine5_req_ready; +wire soc_litedramcore_bankmachine5_req_valid; +reg soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0; +wire soc_litedramcore_bankmachine5_req_we; reg [13:0] soc_litedramcore_bankmachine5_row = 14'd0; -reg soc_litedramcore_bankmachine5_row_opened = 1'd0; -wire soc_litedramcore_bankmachine5_row_hit; -reg soc_litedramcore_bankmachine5_row_open = 1'd0; reg soc_litedramcore_bankmachine5_row_close = 1'd0; reg soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine5_twtpcon_valid; -reg soc_litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine5_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine5_trccon_valid; -reg soc_litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine5_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine5_trascon_valid; -reg soc_litedramcore_bankmachine5_trascon_ready = 1'd0; +wire soc_litedramcore_bankmachine5_row_hit; +reg soc_litedramcore_bankmachine5_row_open = 1'd0; +reg soc_litedramcore_bankmachine5_row_opened = 1'd0; +reg soc_litedramcore_bankmachine5_sink_first = 1'd0; +reg soc_litedramcore_bankmachine5_sink_last = 1'd0; +wire [20:0] soc_litedramcore_bankmachine5_sink_payload_addr; +wire soc_litedramcore_bankmachine5_sink_payload_we; +wire soc_litedramcore_bankmachine5_sink_ready; +wire soc_litedramcore_bankmachine5_sink_sink_first; +wire soc_litedramcore_bankmachine5_sink_sink_last; +wire [20:0] soc_litedramcore_bankmachine5_sink_sink_payload_addr; +wire soc_litedramcore_bankmachine5_sink_sink_payload_we; +wire soc_litedramcore_bankmachine5_sink_sink_ready; +wire soc_litedramcore_bankmachine5_sink_sink_valid; +wire soc_litedramcore_bankmachine5_sink_valid; +wire soc_litedramcore_bankmachine5_source_first; +wire soc_litedramcore_bankmachine5_source_last; +wire [20:0] soc_litedramcore_bankmachine5_source_payload_addr; +wire soc_litedramcore_bankmachine5_source_payload_we; +wire soc_litedramcore_bankmachine5_source_ready; +wire soc_litedramcore_bankmachine5_source_source_first; +wire soc_litedramcore_bankmachine5_source_source_last; +wire [20:0] soc_litedramcore_bankmachine5_source_source_payload_addr; +wire soc_litedramcore_bankmachine5_source_source_payload_we; +wire soc_litedramcore_bankmachine5_source_source_ready; +wire soc_litedramcore_bankmachine5_source_source_valid; +wire soc_litedramcore_bankmachine5_source_valid; +wire [23:0] soc_litedramcore_bankmachine5_syncfifo5_din; +wire [23:0] soc_litedramcore_bankmachine5_syncfifo5_dout; +wire soc_litedramcore_bankmachine5_syncfifo5_re; +wire soc_litedramcore_bankmachine5_syncfifo5_readable; +wire soc_litedramcore_bankmachine5_syncfifo5_we; +wire soc_litedramcore_bankmachine5_syncfifo5_writable; reg [2:0] soc_litedramcore_bankmachine5_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine6_req_valid; -wire soc_litedramcore_bankmachine6_req_ready; -wire soc_litedramcore_bankmachine6_req_we; -wire [20:0] soc_litedramcore_bankmachine6_req_addr; -wire soc_litedramcore_bankmachine6_req_lock; -reg soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine6_refresh_req; -reg soc_litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_ready = 1'd0; +reg soc_litedramcore_bankmachine5_trascon_ready = 1'd0; +wire soc_litedramcore_bankmachine5_trascon_valid; +reg [2:0] soc_litedramcore_bankmachine5_trccon_count = 3'd0; +reg soc_litedramcore_bankmachine5_trccon_ready = 1'd0; +wire soc_litedramcore_bankmachine5_trccon_valid; +reg [2:0] soc_litedramcore_bankmachine5_twtpcon_count = 3'd0; +reg soc_litedramcore_bankmachine5_twtpcon_ready = 1'd0; +wire soc_litedramcore_bankmachine5_twtpcon_valid; +reg [3:0] soc_litedramcore_bankmachine5_wrport_adr = 4'd0; +wire [23:0] soc_litedramcore_bankmachine5_wrport_dat_r; +wire [23:0] soc_litedramcore_bankmachine5_wrport_dat_w; +wire soc_litedramcore_bankmachine5_wrport_we; +reg soc_litedramcore_bankmachine6_auto_precharge = 1'd0; reg [13:0] soc_litedramcore_bankmachine6_cmd_payload_a = 14'd0; wire [2:0] soc_litedramcore_bankmachine6_cmd_payload_ba; reg soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0; reg soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; reg soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; reg soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine6_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine6_sink_valid; -wire soc_litedramcore_bankmachine6_sink_ready; -reg soc_litedramcore_bankmachine6_sink_first = 1'd0; -reg soc_litedramcore_bankmachine6_sink_last = 1'd0; -wire soc_litedramcore_bankmachine6_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine6_sink_payload_addr; -wire soc_litedramcore_bankmachine6_source_valid; -wire soc_litedramcore_bankmachine6_source_ready; -wire soc_litedramcore_bankmachine6_source_first; -wire soc_litedramcore_bankmachine6_source_last; -wire soc_litedramcore_bankmachine6_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine6_source_payload_addr; -wire soc_litedramcore_bankmachine6_syncfifo6_we; -wire soc_litedramcore_bankmachine6_syncfifo6_writable; -wire soc_litedramcore_bankmachine6_syncfifo6_re; -wire soc_litedramcore_bankmachine6_syncfifo6_readable; -wire [23:0] soc_litedramcore_bankmachine6_syncfifo6_din; -wire [23:0] soc_litedramcore_bankmachine6_syncfifo6_dout; -reg [4:0] soc_litedramcore_bankmachine6_level = 5'd0; -reg soc_litedramcore_bankmachine6_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine6_produce = 4'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_ready = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_valid = 1'd0; reg [3:0] soc_litedramcore_bankmachine6_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine6_wrport_adr = 4'd0; -wire [23:0] soc_litedramcore_bankmachine6_wrport_dat_r; -wire soc_litedramcore_bankmachine6_wrport_we; -wire [23:0] soc_litedramcore_bankmachine6_wrport_dat_w; wire soc_litedramcore_bankmachine6_do_read; -wire [3:0] soc_litedramcore_bankmachine6_rdport_adr; -wire [23:0] soc_litedramcore_bankmachine6_rdport_dat_r; -wire soc_litedramcore_bankmachine6_fifo_in_payload_we; -wire [20:0] soc_litedramcore_bankmachine6_fifo_in_payload_addr; wire soc_litedramcore_bankmachine6_fifo_in_first; wire soc_litedramcore_bankmachine6_fifo_in_last; -wire soc_litedramcore_bankmachine6_fifo_out_payload_we; -wire [20:0] soc_litedramcore_bankmachine6_fifo_out_payload_addr; +wire [20:0] soc_litedramcore_bankmachine6_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine6_fifo_in_payload_we; wire soc_litedramcore_bankmachine6_fifo_out_first; wire soc_litedramcore_bankmachine6_fifo_out_last; -wire soc_litedramcore_bankmachine6_sink_sink_valid; -wire soc_litedramcore_bankmachine6_sink_sink_ready; -wire soc_litedramcore_bankmachine6_sink_sink_first; -wire soc_litedramcore_bankmachine6_sink_sink_last; -wire soc_litedramcore_bankmachine6_sink_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine6_sink_sink_payload_addr; -wire soc_litedramcore_bankmachine6_source_source_valid; -wire soc_litedramcore_bankmachine6_source_source_ready; -wire soc_litedramcore_bankmachine6_source_source_first; -wire soc_litedramcore_bankmachine6_source_source_last; -wire soc_litedramcore_bankmachine6_source_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine6_source_source_payload_addr; -wire soc_litedramcore_bankmachine6_pipe_valid_sink_valid; -wire soc_litedramcore_bankmachine6_pipe_valid_sink_ready; +wire [20:0] soc_litedramcore_bankmachine6_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine6_fifo_out_payload_we; +reg [4:0] soc_litedramcore_bankmachine6_level = 5'd0; wire soc_litedramcore_bankmachine6_pipe_valid_sink_first; wire soc_litedramcore_bankmachine6_pipe_valid_sink_last; -wire soc_litedramcore_bankmachine6_pipe_valid_sink_payload_we; wire [20:0] soc_litedramcore_bankmachine6_pipe_valid_sink_payload_addr; -reg soc_litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; -wire soc_litedramcore_bankmachine6_pipe_valid_source_ready; +wire soc_litedramcore_bankmachine6_pipe_valid_sink_payload_we; +wire soc_litedramcore_bankmachine6_pipe_valid_sink_ready; +wire soc_litedramcore_bankmachine6_pipe_valid_sink_valid; reg soc_litedramcore_bankmachine6_pipe_valid_source_first = 1'd0; reg soc_litedramcore_bankmachine6_pipe_valid_source_last = 1'd0; -reg soc_litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; reg [20:0] soc_litedramcore_bankmachine6_pipe_valid_source_payload_addr = 21'd0; +reg soc_litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; +wire soc_litedramcore_bankmachine6_pipe_valid_source_ready; +reg soc_litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; +reg [3:0] soc_litedramcore_bankmachine6_produce = 4'd0; +wire [3:0] soc_litedramcore_bankmachine6_rdport_adr; +wire [23:0] soc_litedramcore_bankmachine6_rdport_dat_r; +reg soc_litedramcore_bankmachine6_refresh_gnt = 1'd0; +wire soc_litedramcore_bankmachine6_refresh_req; +reg soc_litedramcore_bankmachine6_replace = 1'd0; +wire [20:0] soc_litedramcore_bankmachine6_req_addr; +wire soc_litedramcore_bankmachine6_req_lock; +reg soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine6_req_ready; +wire soc_litedramcore_bankmachine6_req_valid; +reg soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0; +wire soc_litedramcore_bankmachine6_req_we; reg [13:0] soc_litedramcore_bankmachine6_row = 14'd0; -reg soc_litedramcore_bankmachine6_row_opened = 1'd0; -wire soc_litedramcore_bankmachine6_row_hit; -reg soc_litedramcore_bankmachine6_row_open = 1'd0; reg soc_litedramcore_bankmachine6_row_close = 1'd0; reg soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine6_twtpcon_valid; -reg soc_litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine6_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine6_trccon_valid; -reg soc_litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine6_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine6_trascon_valid; -reg soc_litedramcore_bankmachine6_trascon_ready = 1'd0; +wire soc_litedramcore_bankmachine6_row_hit; +reg soc_litedramcore_bankmachine6_row_open = 1'd0; +reg soc_litedramcore_bankmachine6_row_opened = 1'd0; +reg soc_litedramcore_bankmachine6_sink_first = 1'd0; +reg soc_litedramcore_bankmachine6_sink_last = 1'd0; +wire [20:0] soc_litedramcore_bankmachine6_sink_payload_addr; +wire soc_litedramcore_bankmachine6_sink_payload_we; +wire soc_litedramcore_bankmachine6_sink_ready; +wire soc_litedramcore_bankmachine6_sink_sink_first; +wire soc_litedramcore_bankmachine6_sink_sink_last; +wire [20:0] soc_litedramcore_bankmachine6_sink_sink_payload_addr; +wire soc_litedramcore_bankmachine6_sink_sink_payload_we; +wire soc_litedramcore_bankmachine6_sink_sink_ready; +wire soc_litedramcore_bankmachine6_sink_sink_valid; +wire soc_litedramcore_bankmachine6_sink_valid; +wire soc_litedramcore_bankmachine6_source_first; +wire soc_litedramcore_bankmachine6_source_last; +wire [20:0] soc_litedramcore_bankmachine6_source_payload_addr; +wire soc_litedramcore_bankmachine6_source_payload_we; +wire soc_litedramcore_bankmachine6_source_ready; +wire soc_litedramcore_bankmachine6_source_source_first; +wire soc_litedramcore_bankmachine6_source_source_last; +wire [20:0] soc_litedramcore_bankmachine6_source_source_payload_addr; +wire soc_litedramcore_bankmachine6_source_source_payload_we; +wire soc_litedramcore_bankmachine6_source_source_ready; +wire soc_litedramcore_bankmachine6_source_source_valid; +wire soc_litedramcore_bankmachine6_source_valid; +wire [23:0] soc_litedramcore_bankmachine6_syncfifo6_din; +wire [23:0] soc_litedramcore_bankmachine6_syncfifo6_dout; +wire soc_litedramcore_bankmachine6_syncfifo6_re; +wire soc_litedramcore_bankmachine6_syncfifo6_readable; +wire soc_litedramcore_bankmachine6_syncfifo6_we; +wire soc_litedramcore_bankmachine6_syncfifo6_writable; reg [2:0] soc_litedramcore_bankmachine6_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine7_req_valid; -wire soc_litedramcore_bankmachine7_req_ready; -wire soc_litedramcore_bankmachine7_req_we; -wire [20:0] soc_litedramcore_bankmachine7_req_addr; -wire soc_litedramcore_bankmachine7_req_lock; -reg soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine7_refresh_req; -reg soc_litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_ready = 1'd0; +reg soc_litedramcore_bankmachine6_trascon_ready = 1'd0; +wire soc_litedramcore_bankmachine6_trascon_valid; +reg [2:0] soc_litedramcore_bankmachine6_trccon_count = 3'd0; +reg soc_litedramcore_bankmachine6_trccon_ready = 1'd0; +wire soc_litedramcore_bankmachine6_trccon_valid; +reg [2:0] soc_litedramcore_bankmachine6_twtpcon_count = 3'd0; +reg soc_litedramcore_bankmachine6_twtpcon_ready = 1'd0; +wire soc_litedramcore_bankmachine6_twtpcon_valid; +reg [3:0] soc_litedramcore_bankmachine6_wrport_adr = 4'd0; +wire [23:0] soc_litedramcore_bankmachine6_wrport_dat_r; +wire [23:0] soc_litedramcore_bankmachine6_wrport_dat_w; +wire soc_litedramcore_bankmachine6_wrport_we; +reg soc_litedramcore_bankmachine7_auto_precharge = 1'd0; reg [13:0] soc_litedramcore_bankmachine7_cmd_payload_a = 14'd0; wire [2:0] soc_litedramcore_bankmachine7_cmd_payload_ba; reg soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0; reg soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; reg soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; reg soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine7_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine7_sink_valid; -wire soc_litedramcore_bankmachine7_sink_ready; -reg soc_litedramcore_bankmachine7_sink_first = 1'd0; -reg soc_litedramcore_bankmachine7_sink_last = 1'd0; -wire soc_litedramcore_bankmachine7_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine7_sink_payload_addr; -wire soc_litedramcore_bankmachine7_source_valid; -wire soc_litedramcore_bankmachine7_source_ready; -wire soc_litedramcore_bankmachine7_source_first; -wire soc_litedramcore_bankmachine7_source_last; -wire soc_litedramcore_bankmachine7_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine7_source_payload_addr; -wire soc_litedramcore_bankmachine7_syncfifo7_we; -wire soc_litedramcore_bankmachine7_syncfifo7_writable; -wire soc_litedramcore_bankmachine7_syncfifo7_re; -wire soc_litedramcore_bankmachine7_syncfifo7_readable; -wire [23:0] soc_litedramcore_bankmachine7_syncfifo7_din; -wire [23:0] soc_litedramcore_bankmachine7_syncfifo7_dout; -reg [4:0] soc_litedramcore_bankmachine7_level = 5'd0; -reg soc_litedramcore_bankmachine7_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine7_produce = 4'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_ready = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_valid = 1'd0; reg [3:0] soc_litedramcore_bankmachine7_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine7_wrport_adr = 4'd0; -wire [23:0] soc_litedramcore_bankmachine7_wrport_dat_r; -wire soc_litedramcore_bankmachine7_wrport_we; -wire [23:0] soc_litedramcore_bankmachine7_wrport_dat_w; wire soc_litedramcore_bankmachine7_do_read; -wire [3:0] soc_litedramcore_bankmachine7_rdport_adr; -wire [23:0] soc_litedramcore_bankmachine7_rdport_dat_r; -wire soc_litedramcore_bankmachine7_fifo_in_payload_we; -wire [20:0] soc_litedramcore_bankmachine7_fifo_in_payload_addr; wire soc_litedramcore_bankmachine7_fifo_in_first; wire soc_litedramcore_bankmachine7_fifo_in_last; -wire soc_litedramcore_bankmachine7_fifo_out_payload_we; -wire [20:0] soc_litedramcore_bankmachine7_fifo_out_payload_addr; +wire [20:0] soc_litedramcore_bankmachine7_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine7_fifo_in_payload_we; wire soc_litedramcore_bankmachine7_fifo_out_first; wire soc_litedramcore_bankmachine7_fifo_out_last; -wire soc_litedramcore_bankmachine7_sink_sink_valid; -wire soc_litedramcore_bankmachine7_sink_sink_ready; -wire soc_litedramcore_bankmachine7_sink_sink_first; -wire soc_litedramcore_bankmachine7_sink_sink_last; -wire soc_litedramcore_bankmachine7_sink_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine7_sink_sink_payload_addr; -wire soc_litedramcore_bankmachine7_source_source_valid; -wire soc_litedramcore_bankmachine7_source_source_ready; -wire soc_litedramcore_bankmachine7_source_source_first; -wire soc_litedramcore_bankmachine7_source_source_last; -wire soc_litedramcore_bankmachine7_source_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine7_source_source_payload_addr; -wire soc_litedramcore_bankmachine7_pipe_valid_sink_valid; -wire soc_litedramcore_bankmachine7_pipe_valid_sink_ready; +wire [20:0] soc_litedramcore_bankmachine7_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine7_fifo_out_payload_we; +reg [4:0] soc_litedramcore_bankmachine7_level = 5'd0; wire soc_litedramcore_bankmachine7_pipe_valid_sink_first; wire soc_litedramcore_bankmachine7_pipe_valid_sink_last; -wire soc_litedramcore_bankmachine7_pipe_valid_sink_payload_we; wire [20:0] soc_litedramcore_bankmachine7_pipe_valid_sink_payload_addr; -reg soc_litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; -wire soc_litedramcore_bankmachine7_pipe_valid_source_ready; +wire soc_litedramcore_bankmachine7_pipe_valid_sink_payload_we; +wire soc_litedramcore_bankmachine7_pipe_valid_sink_ready; +wire soc_litedramcore_bankmachine7_pipe_valid_sink_valid; reg soc_litedramcore_bankmachine7_pipe_valid_source_first = 1'd0; reg soc_litedramcore_bankmachine7_pipe_valid_source_last = 1'd0; -reg soc_litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; reg [20:0] soc_litedramcore_bankmachine7_pipe_valid_source_payload_addr = 21'd0; +reg soc_litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; +wire soc_litedramcore_bankmachine7_pipe_valid_source_ready; +reg soc_litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; +reg [3:0] soc_litedramcore_bankmachine7_produce = 4'd0; +wire [3:0] soc_litedramcore_bankmachine7_rdport_adr; +wire [23:0] soc_litedramcore_bankmachine7_rdport_dat_r; +reg soc_litedramcore_bankmachine7_refresh_gnt = 1'd0; +wire soc_litedramcore_bankmachine7_refresh_req; +reg soc_litedramcore_bankmachine7_replace = 1'd0; +wire [20:0] soc_litedramcore_bankmachine7_req_addr; +wire soc_litedramcore_bankmachine7_req_lock; +reg soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine7_req_ready; +wire soc_litedramcore_bankmachine7_req_valid; +reg soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0; +wire soc_litedramcore_bankmachine7_req_we; reg [13:0] soc_litedramcore_bankmachine7_row = 14'd0; -reg soc_litedramcore_bankmachine7_row_opened = 1'd0; -wire soc_litedramcore_bankmachine7_row_hit; -reg soc_litedramcore_bankmachine7_row_open = 1'd0; reg soc_litedramcore_bankmachine7_row_close = 1'd0; reg soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine7_twtpcon_valid; -reg soc_litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine7_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine7_trccon_valid; -reg soc_litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine7_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine7_trascon_valid; -reg soc_litedramcore_bankmachine7_trascon_ready = 1'd0; +wire soc_litedramcore_bankmachine7_row_hit; +reg soc_litedramcore_bankmachine7_row_open = 1'd0; +reg soc_litedramcore_bankmachine7_row_opened = 1'd0; +reg soc_litedramcore_bankmachine7_sink_first = 1'd0; +reg soc_litedramcore_bankmachine7_sink_last = 1'd0; +wire [20:0] soc_litedramcore_bankmachine7_sink_payload_addr; +wire soc_litedramcore_bankmachine7_sink_payload_we; +wire soc_litedramcore_bankmachine7_sink_ready; +wire soc_litedramcore_bankmachine7_sink_sink_first; +wire soc_litedramcore_bankmachine7_sink_sink_last; +wire [20:0] soc_litedramcore_bankmachine7_sink_sink_payload_addr; +wire soc_litedramcore_bankmachine7_sink_sink_payload_we; +wire soc_litedramcore_bankmachine7_sink_sink_ready; +wire soc_litedramcore_bankmachine7_sink_sink_valid; +wire soc_litedramcore_bankmachine7_sink_valid; +wire soc_litedramcore_bankmachine7_source_first; +wire soc_litedramcore_bankmachine7_source_last; +wire [20:0] soc_litedramcore_bankmachine7_source_payload_addr; +wire soc_litedramcore_bankmachine7_source_payload_we; +wire soc_litedramcore_bankmachine7_source_ready; +wire soc_litedramcore_bankmachine7_source_source_first; +wire soc_litedramcore_bankmachine7_source_source_last; +wire [20:0] soc_litedramcore_bankmachine7_source_source_payload_addr; +wire soc_litedramcore_bankmachine7_source_source_payload_we; +wire soc_litedramcore_bankmachine7_source_source_ready; +wire soc_litedramcore_bankmachine7_source_source_valid; +wire soc_litedramcore_bankmachine7_source_valid; +wire [23:0] soc_litedramcore_bankmachine7_syncfifo7_din; +wire [23:0] soc_litedramcore_bankmachine7_syncfifo7_dout; +wire soc_litedramcore_bankmachine7_syncfifo7_re; +wire soc_litedramcore_bankmachine7_syncfifo7_readable; +wire soc_litedramcore_bankmachine7_syncfifo7_we; +wire soc_litedramcore_bankmachine7_syncfifo7_writable; reg [2:0] soc_litedramcore_bankmachine7_trascon_count = 3'd0; -wire soc_litedramcore_ras_allowed; +reg soc_litedramcore_bankmachine7_trascon_ready = 1'd0; +wire soc_litedramcore_bankmachine7_trascon_valid; +reg [2:0] soc_litedramcore_bankmachine7_trccon_count = 3'd0; +reg soc_litedramcore_bankmachine7_trccon_ready = 1'd0; +wire soc_litedramcore_bankmachine7_trccon_valid; +reg [2:0] soc_litedramcore_bankmachine7_twtpcon_count = 3'd0; +reg soc_litedramcore_bankmachine7_twtpcon_ready = 1'd0; +wire soc_litedramcore_bankmachine7_twtpcon_valid; +reg [3:0] soc_litedramcore_bankmachine7_wrport_adr = 4'd0; +wire [23:0] soc_litedramcore_bankmachine7_wrport_dat_r; +wire [23:0] soc_litedramcore_bankmachine7_wrport_dat_w; +wire soc_litedramcore_bankmachine7_wrport_we; wire soc_litedramcore_cas_allowed; -reg soc_litedramcore_choose_cmd_want_reads = 1'd0; -reg soc_litedramcore_choose_cmd_want_writes = 1'd0; -reg soc_litedramcore_choose_cmd_want_cmds = 1'd0; -reg soc_litedramcore_choose_cmd_want_activates = 1'd0; -wire soc_litedramcore_choose_cmd_cmd_valid; -reg soc_litedramcore_choose_cmd_cmd_ready = 1'd0; +wire soc_litedramcore_choose_cmd_ce; wire [13:0] soc_litedramcore_choose_cmd_cmd_payload_a; wire [2:0] soc_litedramcore_choose_cmd_cmd_payload_ba; reg soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0; wire soc_litedramcore_choose_cmd_cmd_payload_is_cmd; wire soc_litedramcore_choose_cmd_cmd_payload_is_read; wire soc_litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] soc_litedramcore_choose_cmd_valids = 8'd0; -wire [7:0] soc_litedramcore_choose_cmd_request; +reg soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0; +reg soc_litedramcore_choose_cmd_cmd_ready = 1'd0; +wire soc_litedramcore_choose_cmd_cmd_valid; reg [2:0] soc_litedramcore_choose_cmd_grant = 3'd0; -wire soc_litedramcore_choose_cmd_ce; -reg soc_litedramcore_choose_req_want_reads = 1'd0; -reg soc_litedramcore_choose_req_want_writes = 1'd0; -reg soc_litedramcore_choose_req_want_cmds = 1'd0; -reg soc_litedramcore_choose_req_want_activates = 1'd0; -wire soc_litedramcore_choose_req_cmd_valid; -reg soc_litedramcore_choose_req_cmd_ready = 1'd0; +wire [7:0] soc_litedramcore_choose_cmd_request; +reg [7:0] soc_litedramcore_choose_cmd_valids = 8'd0; +reg soc_litedramcore_choose_cmd_want_activates = 1'd0; +reg soc_litedramcore_choose_cmd_want_cmds = 1'd0; +reg soc_litedramcore_choose_cmd_want_reads = 1'd0; +reg soc_litedramcore_choose_cmd_want_writes = 1'd0; +wire soc_litedramcore_choose_req_ce; wire [13:0] soc_litedramcore_choose_req_cmd_payload_a; wire [2:0] soc_litedramcore_choose_req_cmd_payload_ba; reg soc_litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg soc_litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg soc_litedramcore_choose_req_cmd_payload_we = 1'd0; wire soc_litedramcore_choose_req_cmd_payload_is_cmd; wire soc_litedramcore_choose_req_cmd_payload_is_read; wire soc_litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] soc_litedramcore_choose_req_valids = 8'd0; -wire [7:0] soc_litedramcore_choose_req_request; +reg soc_litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg soc_litedramcore_choose_req_cmd_payload_we = 1'd0; +reg soc_litedramcore_choose_req_cmd_ready = 1'd0; +wire soc_litedramcore_choose_req_cmd_valid; reg [2:0] soc_litedramcore_choose_req_grant = 3'd0; -wire soc_litedramcore_choose_req_ce; +wire [7:0] soc_litedramcore_choose_req_request; +reg [7:0] soc_litedramcore_choose_req_valids = 8'd0; +reg soc_litedramcore_choose_req_want_activates = 1'd0; +reg soc_litedramcore_choose_req_want_cmds = 1'd0; +reg soc_litedramcore_choose_req_want_reads = 1'd0; +reg soc_litedramcore_choose_req_want_writes = 1'd0; +wire soc_litedramcore_cke; +reg soc_litedramcore_cmd_last = 1'd0; +reg [13:0] soc_litedramcore_cmd_payload_a = 14'd0; +reg [2:0] soc_litedramcore_cmd_payload_ba = 3'd0; +reg soc_litedramcore_cmd_payload_cas = 1'd0; +reg soc_litedramcore_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_cmd_payload_ras = 1'd0; +reg soc_litedramcore_cmd_payload_we = 1'd0; +reg soc_litedramcore_cmd_ready = 1'd0; +reg soc_litedramcore_cmd_valid = 1'd0; +reg soc_litedramcore_csr_dfi_p0_act_n = 1'd1; +wire [13:0] soc_litedramcore_csr_dfi_p0_address; +wire [2:0] soc_litedramcore_csr_dfi_p0_bank; +reg soc_litedramcore_csr_dfi_p0_cas_n = 1'd1; +reg soc_litedramcore_csr_dfi_p0_cke = 1'd0; +reg soc_litedramcore_csr_dfi_p0_cs_n = 1'd1; +reg soc_litedramcore_csr_dfi_p0_odt = 1'd0; +reg soc_litedramcore_csr_dfi_p0_ras_n = 1'd1; +reg [31:0] soc_litedramcore_csr_dfi_p0_rddata = 32'd0; +wire soc_litedramcore_csr_dfi_p0_rddata_en; +reg soc_litedramcore_csr_dfi_p0_rddata_valid = 1'd0; +wire soc_litedramcore_csr_dfi_p0_reset_n; +reg soc_litedramcore_csr_dfi_p0_we_n = 1'd1; +wire [31:0] soc_litedramcore_csr_dfi_p0_wrdata; +wire soc_litedramcore_csr_dfi_p0_wrdata_en; +wire [3:0] soc_litedramcore_csr_dfi_p0_wrdata_mask; +reg soc_litedramcore_csr_dfi_p1_act_n = 1'd1; +wire [13:0] soc_litedramcore_csr_dfi_p1_address; +wire [2:0] soc_litedramcore_csr_dfi_p1_bank; +reg soc_litedramcore_csr_dfi_p1_cas_n = 1'd1; +reg soc_litedramcore_csr_dfi_p1_cke = 1'd0; +reg soc_litedramcore_csr_dfi_p1_cs_n = 1'd1; +reg soc_litedramcore_csr_dfi_p1_odt = 1'd0; +reg soc_litedramcore_csr_dfi_p1_ras_n = 1'd1; +reg [31:0] soc_litedramcore_csr_dfi_p1_rddata = 32'd0; +wire soc_litedramcore_csr_dfi_p1_rddata_en; +reg soc_litedramcore_csr_dfi_p1_rddata_valid = 1'd0; +wire soc_litedramcore_csr_dfi_p1_reset_n; +reg soc_litedramcore_csr_dfi_p1_we_n = 1'd1; +wire [31:0] soc_litedramcore_csr_dfi_p1_wrdata; +wire soc_litedramcore_csr_dfi_p1_wrdata_en; +wire [3:0] soc_litedramcore_csr_dfi_p1_wrdata_mask; +reg soc_litedramcore_csr_dfi_p2_act_n = 1'd1; +wire [13:0] soc_litedramcore_csr_dfi_p2_address; +wire [2:0] soc_litedramcore_csr_dfi_p2_bank; +reg soc_litedramcore_csr_dfi_p2_cas_n = 1'd1; +reg soc_litedramcore_csr_dfi_p2_cke = 1'd0; +reg soc_litedramcore_csr_dfi_p2_cs_n = 1'd1; +reg soc_litedramcore_csr_dfi_p2_odt = 1'd0; +reg soc_litedramcore_csr_dfi_p2_ras_n = 1'd1; +reg [31:0] soc_litedramcore_csr_dfi_p2_rddata = 32'd0; +wire soc_litedramcore_csr_dfi_p2_rddata_en; +reg soc_litedramcore_csr_dfi_p2_rddata_valid = 1'd0; +wire soc_litedramcore_csr_dfi_p2_reset_n; +reg soc_litedramcore_csr_dfi_p2_we_n = 1'd1; +wire [31:0] soc_litedramcore_csr_dfi_p2_wrdata; +wire soc_litedramcore_csr_dfi_p2_wrdata_en; +wire [3:0] soc_litedramcore_csr_dfi_p2_wrdata_mask; +reg soc_litedramcore_csr_dfi_p3_act_n = 1'd1; +wire [13:0] soc_litedramcore_csr_dfi_p3_address; +wire [2:0] soc_litedramcore_csr_dfi_p3_bank; +reg soc_litedramcore_csr_dfi_p3_cas_n = 1'd1; +reg soc_litedramcore_csr_dfi_p3_cke = 1'd0; +reg soc_litedramcore_csr_dfi_p3_cs_n = 1'd1; +reg soc_litedramcore_csr_dfi_p3_odt = 1'd0; +reg soc_litedramcore_csr_dfi_p3_ras_n = 1'd1; +reg [31:0] soc_litedramcore_csr_dfi_p3_rddata = 32'd0; +wire soc_litedramcore_csr_dfi_p3_rddata_en; +reg soc_litedramcore_csr_dfi_p3_rddata_valid = 1'd0; +wire soc_litedramcore_csr_dfi_p3_reset_n; +reg soc_litedramcore_csr_dfi_p3_we_n = 1'd1; +wire [31:0] soc_litedramcore_csr_dfi_p3_wrdata; +wire soc_litedramcore_csr_dfi_p3_wrdata_en; +wire [3:0] soc_litedramcore_csr_dfi_p3_wrdata_mask; +reg soc_litedramcore_dfi_p0_act_n = 1'd1; +reg [13:0] soc_litedramcore_dfi_p0_address = 14'd0; +reg [2:0] soc_litedramcore_dfi_p0_bank = 3'd0; +reg soc_litedramcore_dfi_p0_cas_n = 1'd1; +wire soc_litedramcore_dfi_p0_cke; +reg soc_litedramcore_dfi_p0_cs_n = 1'd1; +wire soc_litedramcore_dfi_p0_odt; +reg soc_litedramcore_dfi_p0_ras_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p0_rddata; +reg soc_litedramcore_dfi_p0_rddata_en = 1'd0; +wire soc_litedramcore_dfi_p0_rddata_valid; +wire soc_litedramcore_dfi_p0_reset_n; +reg soc_litedramcore_dfi_p0_we_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p0_wrdata; +reg soc_litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [3:0] soc_litedramcore_dfi_p0_wrdata_mask; +reg soc_litedramcore_dfi_p1_act_n = 1'd1; +reg [13:0] soc_litedramcore_dfi_p1_address = 14'd0; +reg [2:0] soc_litedramcore_dfi_p1_bank = 3'd0; +reg soc_litedramcore_dfi_p1_cas_n = 1'd1; +wire soc_litedramcore_dfi_p1_cke; +reg soc_litedramcore_dfi_p1_cs_n = 1'd1; +wire soc_litedramcore_dfi_p1_odt; +reg soc_litedramcore_dfi_p1_ras_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p1_rddata; +reg soc_litedramcore_dfi_p1_rddata_en = 1'd0; +wire soc_litedramcore_dfi_p1_rddata_valid; +wire soc_litedramcore_dfi_p1_reset_n; +reg soc_litedramcore_dfi_p1_we_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p1_wrdata; +reg soc_litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [3:0] soc_litedramcore_dfi_p1_wrdata_mask; +reg soc_litedramcore_dfi_p2_act_n = 1'd1; +reg [13:0] soc_litedramcore_dfi_p2_address = 14'd0; +reg [2:0] soc_litedramcore_dfi_p2_bank = 3'd0; +reg soc_litedramcore_dfi_p2_cas_n = 1'd1; +wire soc_litedramcore_dfi_p2_cke; +reg soc_litedramcore_dfi_p2_cs_n = 1'd1; +wire soc_litedramcore_dfi_p2_odt; +reg soc_litedramcore_dfi_p2_ras_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p2_rddata; +reg soc_litedramcore_dfi_p2_rddata_en = 1'd0; +wire soc_litedramcore_dfi_p2_rddata_valid; +wire soc_litedramcore_dfi_p2_reset_n; +reg soc_litedramcore_dfi_p2_we_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p2_wrdata; +reg soc_litedramcore_dfi_p2_wrdata_en = 1'd0; +wire [3:0] soc_litedramcore_dfi_p2_wrdata_mask; +reg soc_litedramcore_dfi_p3_act_n = 1'd1; +reg [13:0] soc_litedramcore_dfi_p3_address = 14'd0; +reg [2:0] soc_litedramcore_dfi_p3_bank = 3'd0; +reg soc_litedramcore_dfi_p3_cas_n = 1'd1; +wire soc_litedramcore_dfi_p3_cke; +reg soc_litedramcore_dfi_p3_cs_n = 1'd1; +wire soc_litedramcore_dfi_p3_odt; +reg soc_litedramcore_dfi_p3_ras_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p3_rddata; +reg soc_litedramcore_dfi_p3_rddata_en = 1'd0; +wire soc_litedramcore_dfi_p3_rddata_valid; +wire soc_litedramcore_dfi_p3_reset_n; +reg soc_litedramcore_dfi_p3_we_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p3_wrdata; +reg soc_litedramcore_dfi_p3_wrdata_en = 1'd0; +wire [3:0] soc_litedramcore_dfi_p3_wrdata_mask; +reg soc_litedramcore_en0 = 1'd0; +reg soc_litedramcore_en1 = 1'd0; +reg soc_litedramcore_ext_dfi_p0_act_n = 1'd1; +reg [13:0] soc_litedramcore_ext_dfi_p0_address = 14'd0; +reg [2:0] soc_litedramcore_ext_dfi_p0_bank = 3'd0; +reg soc_litedramcore_ext_dfi_p0_cas_n = 1'd1; +reg soc_litedramcore_ext_dfi_p0_cke = 1'd0; +reg soc_litedramcore_ext_dfi_p0_cs_n = 1'd1; +reg soc_litedramcore_ext_dfi_p0_odt = 1'd0; +reg soc_litedramcore_ext_dfi_p0_ras_n = 1'd1; +reg [31:0] soc_litedramcore_ext_dfi_p0_rddata = 32'd0; +reg soc_litedramcore_ext_dfi_p0_rddata_en = 1'd0; +reg soc_litedramcore_ext_dfi_p0_rddata_valid = 1'd0; +reg soc_litedramcore_ext_dfi_p0_reset_n = 1'd0; +reg soc_litedramcore_ext_dfi_p0_we_n = 1'd1; +reg [31:0] soc_litedramcore_ext_dfi_p0_wrdata = 32'd0; +reg soc_litedramcore_ext_dfi_p0_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_ext_dfi_p0_wrdata_mask = 4'd0; +reg soc_litedramcore_ext_dfi_p1_act_n = 1'd1; +reg [13:0] soc_litedramcore_ext_dfi_p1_address = 14'd0; +reg [2:0] soc_litedramcore_ext_dfi_p1_bank = 3'd0; +reg soc_litedramcore_ext_dfi_p1_cas_n = 1'd1; +reg soc_litedramcore_ext_dfi_p1_cke = 1'd0; +reg soc_litedramcore_ext_dfi_p1_cs_n = 1'd1; +reg soc_litedramcore_ext_dfi_p1_odt = 1'd0; +reg soc_litedramcore_ext_dfi_p1_ras_n = 1'd1; +reg [31:0] soc_litedramcore_ext_dfi_p1_rddata = 32'd0; +reg soc_litedramcore_ext_dfi_p1_rddata_en = 1'd0; +reg soc_litedramcore_ext_dfi_p1_rddata_valid = 1'd0; +reg soc_litedramcore_ext_dfi_p1_reset_n = 1'd0; +reg soc_litedramcore_ext_dfi_p1_we_n = 1'd1; +reg [31:0] soc_litedramcore_ext_dfi_p1_wrdata = 32'd0; +reg soc_litedramcore_ext_dfi_p1_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_ext_dfi_p1_wrdata_mask = 4'd0; +reg soc_litedramcore_ext_dfi_p2_act_n = 1'd1; +reg [13:0] soc_litedramcore_ext_dfi_p2_address = 14'd0; +reg [2:0] soc_litedramcore_ext_dfi_p2_bank = 3'd0; +reg soc_litedramcore_ext_dfi_p2_cas_n = 1'd1; +reg soc_litedramcore_ext_dfi_p2_cke = 1'd0; +reg soc_litedramcore_ext_dfi_p2_cs_n = 1'd1; +reg soc_litedramcore_ext_dfi_p2_odt = 1'd0; +reg soc_litedramcore_ext_dfi_p2_ras_n = 1'd1; +reg [31:0] soc_litedramcore_ext_dfi_p2_rddata = 32'd0; +reg soc_litedramcore_ext_dfi_p2_rddata_en = 1'd0; +reg soc_litedramcore_ext_dfi_p2_rddata_valid = 1'd0; +reg soc_litedramcore_ext_dfi_p2_reset_n = 1'd0; +reg soc_litedramcore_ext_dfi_p2_we_n = 1'd1; +reg [31:0] soc_litedramcore_ext_dfi_p2_wrdata = 32'd0; +reg soc_litedramcore_ext_dfi_p2_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_ext_dfi_p2_wrdata_mask = 4'd0; +reg soc_litedramcore_ext_dfi_p3_act_n = 1'd1; +reg [13:0] soc_litedramcore_ext_dfi_p3_address = 14'd0; +reg [2:0] soc_litedramcore_ext_dfi_p3_bank = 3'd0; +reg soc_litedramcore_ext_dfi_p3_cas_n = 1'd1; +reg soc_litedramcore_ext_dfi_p3_cke = 1'd0; +reg soc_litedramcore_ext_dfi_p3_cs_n = 1'd1; +reg soc_litedramcore_ext_dfi_p3_odt = 1'd0; +reg soc_litedramcore_ext_dfi_p3_ras_n = 1'd1; +reg [31:0] soc_litedramcore_ext_dfi_p3_rddata = 32'd0; +reg soc_litedramcore_ext_dfi_p3_rddata_en = 1'd0; +reg soc_litedramcore_ext_dfi_p3_rddata_valid = 1'd0; +reg soc_litedramcore_ext_dfi_p3_reset_n = 1'd0; +reg soc_litedramcore_ext_dfi_p3_we_n = 1'd1; +reg [31:0] soc_litedramcore_ext_dfi_p3_wrdata = 32'd0; +reg soc_litedramcore_ext_dfi_p3_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_ext_dfi_p3_wrdata_mask = 4'd0; +reg soc_litedramcore_ext_dfi_sel = 1'd0; +wire soc_litedramcore_go_to_refresh; +wire [20:0] soc_litedramcore_interface_bank0_addr; +wire soc_litedramcore_interface_bank0_lock; +wire soc_litedramcore_interface_bank0_rdata_valid; +wire soc_litedramcore_interface_bank0_ready; +wire soc_litedramcore_interface_bank0_valid; +wire soc_litedramcore_interface_bank0_wdata_ready; +wire soc_litedramcore_interface_bank0_we; +wire [20:0] soc_litedramcore_interface_bank1_addr; +wire soc_litedramcore_interface_bank1_lock; +wire soc_litedramcore_interface_bank1_rdata_valid; +wire soc_litedramcore_interface_bank1_ready; +wire soc_litedramcore_interface_bank1_valid; +wire soc_litedramcore_interface_bank1_wdata_ready; +wire soc_litedramcore_interface_bank1_we; +wire [20:0] soc_litedramcore_interface_bank2_addr; +wire soc_litedramcore_interface_bank2_lock; +wire soc_litedramcore_interface_bank2_rdata_valid; +wire soc_litedramcore_interface_bank2_ready; +wire soc_litedramcore_interface_bank2_valid; +wire soc_litedramcore_interface_bank2_wdata_ready; +wire soc_litedramcore_interface_bank2_we; +wire [20:0] soc_litedramcore_interface_bank3_addr; +wire soc_litedramcore_interface_bank3_lock; +wire soc_litedramcore_interface_bank3_rdata_valid; +wire soc_litedramcore_interface_bank3_ready; +wire soc_litedramcore_interface_bank3_valid; +wire soc_litedramcore_interface_bank3_wdata_ready; +wire soc_litedramcore_interface_bank3_we; +wire [20:0] soc_litedramcore_interface_bank4_addr; +wire soc_litedramcore_interface_bank4_lock; +wire soc_litedramcore_interface_bank4_rdata_valid; +wire soc_litedramcore_interface_bank4_ready; +wire soc_litedramcore_interface_bank4_valid; +wire soc_litedramcore_interface_bank4_wdata_ready; +wire soc_litedramcore_interface_bank4_we; +wire [20:0] soc_litedramcore_interface_bank5_addr; +wire soc_litedramcore_interface_bank5_lock; +wire soc_litedramcore_interface_bank5_rdata_valid; +wire soc_litedramcore_interface_bank5_ready; +wire soc_litedramcore_interface_bank5_valid; +wire soc_litedramcore_interface_bank5_wdata_ready; +wire soc_litedramcore_interface_bank5_we; +wire [20:0] soc_litedramcore_interface_bank6_addr; +wire soc_litedramcore_interface_bank6_lock; +wire soc_litedramcore_interface_bank6_rdata_valid; +wire soc_litedramcore_interface_bank6_ready; +wire soc_litedramcore_interface_bank6_valid; +wire soc_litedramcore_interface_bank6_wdata_ready; +wire soc_litedramcore_interface_bank6_we; +wire [20:0] soc_litedramcore_interface_bank7_addr; +wire soc_litedramcore_interface_bank7_lock; +wire soc_litedramcore_interface_bank7_rdata_valid; +wire soc_litedramcore_interface_bank7_ready; +wire soc_litedramcore_interface_bank7_valid; +wire soc_litedramcore_interface_bank7_wdata_ready; +wire soc_litedramcore_interface_bank7_we; +wire [127:0] soc_litedramcore_interface_rdata; +reg [127:0] soc_litedramcore_interface_wdata = 128'd0; +reg [15:0] soc_litedramcore_interface_wdata_we = 16'd0; +reg soc_litedramcore_master_p0_act_n = 1'd1; +reg [13:0] soc_litedramcore_master_p0_address = 14'd0; +reg [2:0] soc_litedramcore_master_p0_bank = 3'd0; +reg soc_litedramcore_master_p0_cas_n = 1'd1; +reg soc_litedramcore_master_p0_cke = 1'd0; +reg soc_litedramcore_master_p0_cs_n = 1'd1; +reg soc_litedramcore_master_p0_odt = 1'd0; +reg soc_litedramcore_master_p0_ras_n = 1'd1; +wire [31:0] soc_litedramcore_master_p0_rddata; +reg soc_litedramcore_master_p0_rddata_en = 1'd0; +wire soc_litedramcore_master_p0_rddata_valid; +reg soc_litedramcore_master_p0_reset_n = 1'd0; +reg soc_litedramcore_master_p0_we_n = 1'd1; +reg [31:0] soc_litedramcore_master_p0_wrdata = 32'd0; +reg soc_litedramcore_master_p0_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_master_p0_wrdata_mask = 4'd0; +reg soc_litedramcore_master_p1_act_n = 1'd1; +reg [13:0] soc_litedramcore_master_p1_address = 14'd0; +reg [2:0] soc_litedramcore_master_p1_bank = 3'd0; +reg soc_litedramcore_master_p1_cas_n = 1'd1; +reg soc_litedramcore_master_p1_cke = 1'd0; +reg soc_litedramcore_master_p1_cs_n = 1'd1; +reg soc_litedramcore_master_p1_odt = 1'd0; +reg soc_litedramcore_master_p1_ras_n = 1'd1; +wire [31:0] soc_litedramcore_master_p1_rddata; +reg soc_litedramcore_master_p1_rddata_en = 1'd0; +wire soc_litedramcore_master_p1_rddata_valid; +reg soc_litedramcore_master_p1_reset_n = 1'd0; +reg soc_litedramcore_master_p1_we_n = 1'd1; +reg [31:0] soc_litedramcore_master_p1_wrdata = 32'd0; +reg soc_litedramcore_master_p1_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_master_p1_wrdata_mask = 4'd0; +reg soc_litedramcore_master_p2_act_n = 1'd1; +reg [13:0] soc_litedramcore_master_p2_address = 14'd0; +reg [2:0] soc_litedramcore_master_p2_bank = 3'd0; +reg soc_litedramcore_master_p2_cas_n = 1'd1; +reg soc_litedramcore_master_p2_cke = 1'd0; +reg soc_litedramcore_master_p2_cs_n = 1'd1; +reg soc_litedramcore_master_p2_odt = 1'd0; +reg soc_litedramcore_master_p2_ras_n = 1'd1; +wire [31:0] soc_litedramcore_master_p2_rddata; +reg soc_litedramcore_master_p2_rddata_en = 1'd0; +wire soc_litedramcore_master_p2_rddata_valid; +reg soc_litedramcore_master_p2_reset_n = 1'd0; +reg soc_litedramcore_master_p2_we_n = 1'd1; +reg [31:0] soc_litedramcore_master_p2_wrdata = 32'd0; +reg soc_litedramcore_master_p2_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_master_p2_wrdata_mask = 4'd0; +reg soc_litedramcore_master_p3_act_n = 1'd1; +reg [13:0] soc_litedramcore_master_p3_address = 14'd0; +reg [2:0] soc_litedramcore_master_p3_bank = 3'd0; +reg soc_litedramcore_master_p3_cas_n = 1'd1; +reg soc_litedramcore_master_p3_cke = 1'd0; +reg soc_litedramcore_master_p3_cs_n = 1'd1; +reg soc_litedramcore_master_p3_odt = 1'd0; +reg soc_litedramcore_master_p3_ras_n = 1'd1; +wire [31:0] soc_litedramcore_master_p3_rddata; +reg soc_litedramcore_master_p3_rddata_en = 1'd0; +wire soc_litedramcore_master_p3_rddata_valid; +reg soc_litedramcore_master_p3_reset_n = 1'd0; +reg soc_litedramcore_master_p3_we_n = 1'd1; +reg [31:0] soc_litedramcore_master_p3_wrdata = 32'd0; +reg soc_litedramcore_master_p3_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_master_p3_wrdata_mask = 4'd0; +wire soc_litedramcore_max_time0; +wire soc_litedramcore_max_time1; reg [13:0] soc_litedramcore_nop_a = 14'd0; reg [2:0] soc_litedramcore_nop_ba = 3'd0; -reg [1:0] soc_litedramcore_steerer_sel0 = 2'd0; -reg [1:0] soc_litedramcore_steerer_sel1 = 2'd0; -reg [1:0] soc_litedramcore_steerer_sel2 = 2'd0; -reg [1:0] soc_litedramcore_steerer_sel3 = 2'd0; -reg soc_litedramcore_steerer0 = 1'd1; -reg soc_litedramcore_steerer1 = 1'd1; -reg soc_litedramcore_steerer2 = 1'd1; -reg soc_litedramcore_steerer3 = 1'd1; +wire soc_litedramcore_odt; +reg soc_litedramcore_phaseinjector0_address_re = 1'd0; +reg [13:0] soc_litedramcore_phaseinjector0_address_storage = 14'd0; +reg soc_litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector0_baddress_storage = 3'd0; +wire soc_litedramcore_phaseinjector0_command_issue_r; +reg soc_litedramcore_phaseinjector0_command_issue_re = 1'd0; +reg soc_litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg soc_litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg soc_litedramcore_phaseinjector0_command_re = 1'd0; +reg [7:0] soc_litedramcore_phaseinjector0_command_storage = 8'd0; +wire soc_litedramcore_phaseinjector0_csrfield_cas; +wire soc_litedramcore_phaseinjector0_csrfield_cs; +wire soc_litedramcore_phaseinjector0_csrfield_cs_bottom; +wire soc_litedramcore_phaseinjector0_csrfield_cs_top; +wire soc_litedramcore_phaseinjector0_csrfield_ras; +wire soc_litedramcore_phaseinjector0_csrfield_rden; +wire soc_litedramcore_phaseinjector0_csrfield_we; +wire soc_litedramcore_phaseinjector0_csrfield_wren; +reg soc_litedramcore_phaseinjector0_rddata_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector0_rddata_status = 32'd0; +wire soc_litedramcore_phaseinjector0_rddata_we; +reg soc_litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector0_wrdata_storage = 32'd0; +reg soc_litedramcore_phaseinjector1_address_re = 1'd0; +reg [13:0] soc_litedramcore_phaseinjector1_address_storage = 14'd0; +reg soc_litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector1_baddress_storage = 3'd0; +wire soc_litedramcore_phaseinjector1_command_issue_r; +reg soc_litedramcore_phaseinjector1_command_issue_re = 1'd0; +reg soc_litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg soc_litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg soc_litedramcore_phaseinjector1_command_re = 1'd0; +reg [7:0] soc_litedramcore_phaseinjector1_command_storage = 8'd0; +wire soc_litedramcore_phaseinjector1_csrfield_cas; +wire soc_litedramcore_phaseinjector1_csrfield_cs; +wire soc_litedramcore_phaseinjector1_csrfield_cs_bottom; +wire soc_litedramcore_phaseinjector1_csrfield_cs_top; +wire soc_litedramcore_phaseinjector1_csrfield_ras; +wire soc_litedramcore_phaseinjector1_csrfield_rden; +wire soc_litedramcore_phaseinjector1_csrfield_we; +wire soc_litedramcore_phaseinjector1_csrfield_wren; +reg soc_litedramcore_phaseinjector1_rddata_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector1_rddata_status = 32'd0; +wire soc_litedramcore_phaseinjector1_rddata_we; +reg soc_litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector1_wrdata_storage = 32'd0; +reg soc_litedramcore_phaseinjector2_address_re = 1'd0; +reg [13:0] soc_litedramcore_phaseinjector2_address_storage = 14'd0; +reg soc_litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector2_baddress_storage = 3'd0; +wire soc_litedramcore_phaseinjector2_command_issue_r; +reg soc_litedramcore_phaseinjector2_command_issue_re = 1'd0; +reg soc_litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg soc_litedramcore_phaseinjector2_command_issue_we = 1'd0; +reg soc_litedramcore_phaseinjector2_command_re = 1'd0; +reg [7:0] soc_litedramcore_phaseinjector2_command_storage = 8'd0; +wire soc_litedramcore_phaseinjector2_csrfield_cas; +wire soc_litedramcore_phaseinjector2_csrfield_cs; +wire soc_litedramcore_phaseinjector2_csrfield_cs_bottom; +wire soc_litedramcore_phaseinjector2_csrfield_cs_top; +wire soc_litedramcore_phaseinjector2_csrfield_ras; +wire soc_litedramcore_phaseinjector2_csrfield_rden; +wire soc_litedramcore_phaseinjector2_csrfield_we; +wire soc_litedramcore_phaseinjector2_csrfield_wren; +reg soc_litedramcore_phaseinjector2_rddata_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector2_rddata_status = 32'd0; +wire soc_litedramcore_phaseinjector2_rddata_we; +reg soc_litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector2_wrdata_storage = 32'd0; +reg soc_litedramcore_phaseinjector3_address_re = 1'd0; +reg [13:0] soc_litedramcore_phaseinjector3_address_storage = 14'd0; +reg soc_litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector3_baddress_storage = 3'd0; +wire soc_litedramcore_phaseinjector3_command_issue_r; +reg soc_litedramcore_phaseinjector3_command_issue_re = 1'd0; +reg soc_litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg soc_litedramcore_phaseinjector3_command_issue_we = 1'd0; +reg soc_litedramcore_phaseinjector3_command_re = 1'd0; +reg [7:0] soc_litedramcore_phaseinjector3_command_storage = 8'd0; +wire soc_litedramcore_phaseinjector3_csrfield_cas; +wire soc_litedramcore_phaseinjector3_csrfield_cs; +wire soc_litedramcore_phaseinjector3_csrfield_cs_bottom; +wire soc_litedramcore_phaseinjector3_csrfield_cs_top; +wire soc_litedramcore_phaseinjector3_csrfield_ras; +wire soc_litedramcore_phaseinjector3_csrfield_rden; +wire soc_litedramcore_phaseinjector3_csrfield_we; +wire soc_litedramcore_phaseinjector3_csrfield_wren; +reg soc_litedramcore_phaseinjector3_rddata_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector3_rddata_status = 32'd0; +wire soc_litedramcore_phaseinjector3_rddata_we; +reg soc_litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector3_wrdata_storage = 32'd0; +reg soc_litedramcore_postponer_count = 1'd0; +wire soc_litedramcore_postponer_req_i; +reg soc_litedramcore_postponer_req_o = 1'd0; +wire soc_litedramcore_ras_allowed; +reg soc_litedramcore_re = 1'd0; +wire soc_litedramcore_read_available; +wire soc_litedramcore_reset_n; +wire soc_litedramcore_sel; +reg soc_litedramcore_sequencer_count = 1'd0; +wire soc_litedramcore_sequencer_done0; +reg soc_litedramcore_sequencer_done1 = 1'd0; +reg soc_litedramcore_sequencer_start0 = 1'd0; +wire soc_litedramcore_sequencer_start1; +reg [5:0] soc_litedramcore_sequencer_trigger = 6'd0; +wire soc_litedramcore_slave_p0_act_n; +wire [13:0] soc_litedramcore_slave_p0_address; +wire [2:0] soc_litedramcore_slave_p0_bank; +wire soc_litedramcore_slave_p0_cas_n; +wire soc_litedramcore_slave_p0_cke; +wire soc_litedramcore_slave_p0_cs_n; +wire soc_litedramcore_slave_p0_odt; +wire soc_litedramcore_slave_p0_ras_n; +reg [31:0] soc_litedramcore_slave_p0_rddata = 32'd0; +wire soc_litedramcore_slave_p0_rddata_en; +reg soc_litedramcore_slave_p0_rddata_valid = 1'd0; +wire soc_litedramcore_slave_p0_reset_n; +wire soc_litedramcore_slave_p0_we_n; +wire [31:0] soc_litedramcore_slave_p0_wrdata; +wire soc_litedramcore_slave_p0_wrdata_en; +wire [3:0] soc_litedramcore_slave_p0_wrdata_mask; +wire soc_litedramcore_slave_p1_act_n; +wire [13:0] soc_litedramcore_slave_p1_address; +wire [2:0] soc_litedramcore_slave_p1_bank; +wire soc_litedramcore_slave_p1_cas_n; +wire soc_litedramcore_slave_p1_cke; +wire soc_litedramcore_slave_p1_cs_n; +wire soc_litedramcore_slave_p1_odt; +wire soc_litedramcore_slave_p1_ras_n; +reg [31:0] soc_litedramcore_slave_p1_rddata = 32'd0; +wire soc_litedramcore_slave_p1_rddata_en; +reg soc_litedramcore_slave_p1_rddata_valid = 1'd0; +wire soc_litedramcore_slave_p1_reset_n; +wire soc_litedramcore_slave_p1_we_n; +wire [31:0] soc_litedramcore_slave_p1_wrdata; +wire soc_litedramcore_slave_p1_wrdata_en; +wire [3:0] soc_litedramcore_slave_p1_wrdata_mask; +wire soc_litedramcore_slave_p2_act_n; +wire [13:0] soc_litedramcore_slave_p2_address; +wire [2:0] soc_litedramcore_slave_p2_bank; +wire soc_litedramcore_slave_p2_cas_n; +wire soc_litedramcore_slave_p2_cke; +wire soc_litedramcore_slave_p2_cs_n; +wire soc_litedramcore_slave_p2_odt; +wire soc_litedramcore_slave_p2_ras_n; +reg [31:0] soc_litedramcore_slave_p2_rddata = 32'd0; +wire soc_litedramcore_slave_p2_rddata_en; +reg soc_litedramcore_slave_p2_rddata_valid = 1'd0; +wire soc_litedramcore_slave_p2_reset_n; +wire soc_litedramcore_slave_p2_we_n; +wire [31:0] soc_litedramcore_slave_p2_wrdata; +wire soc_litedramcore_slave_p2_wrdata_en; +wire [3:0] soc_litedramcore_slave_p2_wrdata_mask; +wire soc_litedramcore_slave_p3_act_n; +wire [13:0] soc_litedramcore_slave_p3_address; +wire [2:0] soc_litedramcore_slave_p3_bank; +wire soc_litedramcore_slave_p3_cas_n; +wire soc_litedramcore_slave_p3_cke; +wire soc_litedramcore_slave_p3_cs_n; +wire soc_litedramcore_slave_p3_odt; +wire soc_litedramcore_slave_p3_ras_n; +reg [31:0] soc_litedramcore_slave_p3_rddata = 32'd0; +wire soc_litedramcore_slave_p3_rddata_en; +reg soc_litedramcore_slave_p3_rddata_valid = 1'd0; +wire soc_litedramcore_slave_p3_reset_n; +wire soc_litedramcore_slave_p3_we_n; +wire [31:0] soc_litedramcore_slave_p3_wrdata; +wire soc_litedramcore_slave_p3_wrdata_en; +wire [3:0] soc_litedramcore_slave_p3_wrdata_mask; +reg [1:0] soc_litedramcore_steerer0 = 2'd0; +reg [1:0] soc_litedramcore_steerer1 = 2'd0; +reg soc_litedramcore_steerer10 = 1'd1; +reg soc_litedramcore_steerer11 = 1'd1; +reg [1:0] soc_litedramcore_steerer2 = 2'd0; +reg [1:0] soc_litedramcore_steerer3 = 2'd0; reg soc_litedramcore_steerer4 = 1'd1; reg soc_litedramcore_steerer5 = 1'd1; reg soc_litedramcore_steerer6 = 1'd1; reg soc_litedramcore_steerer7 = 1'd1; -wire soc_litedramcore_trrdcon_valid; -reg soc_litedramcore_trrdcon_ready = 1'd0; -reg soc_litedramcore_trrdcon_count = 1'd0; -wire soc_litedramcore_tfawcon_valid; -reg soc_litedramcore_tfawcon_ready = 1'd1; +reg soc_litedramcore_steerer8 = 1'd1; +reg soc_litedramcore_steerer9 = 1'd1; +reg [3:0] soc_litedramcore_storage = 4'd1; +reg soc_litedramcore_tccdcon_count = 1'd0; +reg soc_litedramcore_tccdcon_ready = 1'd0; +wire soc_litedramcore_tccdcon_valid; wire [2:0] soc_litedramcore_tfawcon_count; +reg soc_litedramcore_tfawcon_ready = 1'd1; +wire soc_litedramcore_tfawcon_valid; reg [4:0] soc_litedramcore_tfawcon_window = 5'd0; -wire soc_litedramcore_tccdcon_valid; -reg soc_litedramcore_tccdcon_ready = 1'd0; -reg soc_litedramcore_tccdcon_count = 1'd0; -wire soc_litedramcore_twtrcon_valid; -reg soc_litedramcore_twtrcon_ready = 1'd0; -reg [2:0] soc_litedramcore_twtrcon_count = 3'd0; -wire soc_litedramcore_read_available; -wire soc_litedramcore_write_available; -reg soc_litedramcore_en0 = 1'd0; -wire soc_litedramcore_max_time0; reg [4:0] soc_litedramcore_time0 = 5'd0; -reg soc_litedramcore_en1 = 1'd0; -wire soc_litedramcore_max_time1; reg [3:0] soc_litedramcore_time1 = 4'd0; -wire soc_litedramcore_go_to_refresh; -reg soc_init_done_storage = 1'd0; -reg soc_init_done_re = 1'd0; -reg soc_init_error_storage = 1'd0; -reg soc_init_error_re = 1'd0; +wire [9:0] soc_litedramcore_timer_count0; +reg [9:0] soc_litedramcore_timer_count1 = 10'd781; +wire soc_litedramcore_timer_done0; +wire soc_litedramcore_timer_done1; +wire soc_litedramcore_timer_wait; +reg soc_litedramcore_trrdcon_count = 1'd0; +reg soc_litedramcore_trrdcon_ready = 1'd0; +wire soc_litedramcore_trrdcon_valid; +reg [2:0] soc_litedramcore_twtrcon_count = 3'd0; +reg soc_litedramcore_twtrcon_ready = 1'd0; +wire soc_litedramcore_twtrcon_valid; +wire soc_litedramcore_wants_refresh; +wire soc_litedramcore_wants_zqcs; +wire soc_litedramcore_write_available; +reg soc_litedramcore_zqcs_executer_done = 1'd0; +reg soc_litedramcore_zqcs_executer_start = 1'd0; +reg [4:0] soc_litedramcore_zqcs_executer_trigger = 5'd0; +wire [26:0] soc_litedramcore_zqcs_timer_count0; +reg [26:0] soc_litedramcore_zqcs_timer_count1 = 27'd99999999; +wire soc_litedramcore_zqcs_timer_done0; +wire soc_litedramcore_zqcs_timer_done1; +wire soc_litedramcore_zqcs_timer_wait; +wire soc_user_enable; +wire [23:0] soc_user_port_cmd_payload_addr; +wire soc_user_port_cmd_payload_we; +wire soc_user_port_cmd_ready; +wire soc_user_port_cmd_valid; +wire [127:0] soc_user_port_rdata_payload_data; +wire soc_user_port_rdata_ready; +wire soc_user_port_rdata_valid; +wire [127:0] soc_user_port_wdata_payload_data; +wire [15:0] soc_user_port_wdata_payload_we; +wire soc_user_port_wdata_ready; +wire soc_user_port_wdata_valid; +wire soc_wb_bus_ack; wire [29:0] soc_wb_bus_adr; -wire [31:0] soc_wb_bus_dat_w; +wire [1:0] soc_wb_bus_bte; +wire [2:0] soc_wb_bus_cti; +wire soc_wb_bus_cyc; wire [31:0] soc_wb_bus_dat_r; +wire [31:0] soc_wb_bus_dat_w; +wire soc_wb_bus_err; wire [3:0] soc_wb_bus_sel; -wire soc_wb_bus_cyc; wire soc_wb_bus_stb; -wire soc_wb_bus_ack; wire soc_wb_bus_we; -wire [2:0] soc_wb_bus_cti; -wire [1:0] soc_wb_bus_bte; -wire soc_wb_bus_err; -wire soc_user_enable; -wire soc_user_port_cmd_valid; -wire soc_user_port_cmd_ready; -wire soc_user_port_cmd_payload_we; -wire [23:0] soc_user_port_cmd_payload_addr; -wire soc_user_port_wdata_valid; -wire soc_user_port_wdata_ready; -wire [127:0] soc_user_port_wdata_payload_data; -wire [15:0] soc_user_port_wdata_payload_we; -wire soc_user_port_rdata_valid; -wire soc_user_port_rdata_ready; -wire [127:0] soc_user_port_rdata_payload_data; -reg [13:0] litedramcore_adr = 14'd0; -reg litedramcore_we = 1'd0; -reg [31:0] litedramcore_dat_w = 32'd0; -wire [31:0] litedramcore_dat_r; -wire [29:0] litedramcore_wishbone_adr; -wire [31:0] litedramcore_wishbone_dat_w; -reg [31:0] litedramcore_wishbone_dat_r = 32'd0; -wire [3:0] litedramcore_wishbone_sel; -wire litedramcore_wishbone_cyc; -wire litedramcore_wishbone_stb; -reg litedramcore_wishbone_ack = 1'd0; -wire litedramcore_wishbone_we; -wire [2:0] litedramcore_wishbone_cti; -wire [1:0] litedramcore_wishbone_bte; -reg litedramcore_wishbone_err = 1'd0; -wire [13:0] interface0_bank_bus_adr; -wire interface0_bank_bus_we; -wire [31:0] interface0_bank_bus_dat_w; -reg [31:0] interface0_bank_bus_dat_r = 32'd0; -reg csrbank0_init_done0_re = 1'd0; -wire csrbank0_init_done0_r; -reg csrbank0_init_done0_we = 1'd0; -wire csrbank0_init_done0_w; -reg csrbank0_init_error0_re = 1'd0; -wire csrbank0_init_error0_r; -reg csrbank0_init_error0_we = 1'd0; -wire csrbank0_init_error0_w; -wire csrbank0_sel; -wire [13:0] interface1_bank_bus_adr; -wire interface1_bank_bus_we; -wire [31:0] interface1_bank_bus_dat_w; -reg [31:0] interface1_bank_bus_dat_r = 32'd0; -reg csrbank1_dfii_control0_re = 1'd0; -wire [3:0] csrbank1_dfii_control0_r; -reg csrbank1_dfii_control0_we = 1'd0; -wire [3:0] csrbank1_dfii_control0_w; -reg csrbank1_dfii_pi0_command0_re = 1'd0; -wire [5:0] csrbank1_dfii_pi0_command0_r; -reg csrbank1_dfii_pi0_command0_we = 1'd0; -wire [5:0] csrbank1_dfii_pi0_command0_w; -reg csrbank1_dfii_pi0_address0_re = 1'd0; -wire [13:0] csrbank1_dfii_pi0_address0_r; -reg csrbank1_dfii_pi0_address0_we = 1'd0; -wire [13:0] csrbank1_dfii_pi0_address0_w; -reg csrbank1_dfii_pi0_baddress0_re = 1'd0; -wire [2:0] csrbank1_dfii_pi0_baddress0_r; -reg csrbank1_dfii_pi0_baddress0_we = 1'd0; -wire [2:0] csrbank1_dfii_pi0_baddress0_w; -reg csrbank1_dfii_pi0_wrdata0_re = 1'd0; -wire [31:0] csrbank1_dfii_pi0_wrdata0_r; -reg csrbank1_dfii_pi0_wrdata0_we = 1'd0; -wire [31:0] csrbank1_dfii_pi0_wrdata0_w; -reg csrbank1_dfii_pi0_rddata_re = 1'd0; -wire [31:0] csrbank1_dfii_pi0_rddata_r; -reg csrbank1_dfii_pi0_rddata_we = 1'd0; -wire [31:0] csrbank1_dfii_pi0_rddata_w; -reg csrbank1_dfii_pi1_command0_re = 1'd0; -wire [5:0] csrbank1_dfii_pi1_command0_r; -reg csrbank1_dfii_pi1_command0_we = 1'd0; -wire [5:0] csrbank1_dfii_pi1_command0_w; -reg csrbank1_dfii_pi1_address0_re = 1'd0; -wire [13:0] csrbank1_dfii_pi1_address0_r; -reg csrbank1_dfii_pi1_address0_we = 1'd0; -wire [13:0] csrbank1_dfii_pi1_address0_w; -reg csrbank1_dfii_pi1_baddress0_re = 1'd0; -wire [2:0] csrbank1_dfii_pi1_baddress0_r; -reg csrbank1_dfii_pi1_baddress0_we = 1'd0; -wire [2:0] csrbank1_dfii_pi1_baddress0_w; -reg csrbank1_dfii_pi1_wrdata0_re = 1'd0; -wire [31:0] csrbank1_dfii_pi1_wrdata0_r; -reg csrbank1_dfii_pi1_wrdata0_we = 1'd0; -wire [31:0] csrbank1_dfii_pi1_wrdata0_w; -reg csrbank1_dfii_pi1_rddata_re = 1'd0; -wire [31:0] csrbank1_dfii_pi1_rddata_r; -reg csrbank1_dfii_pi1_rddata_we = 1'd0; -wire [31:0] csrbank1_dfii_pi1_rddata_w; -reg csrbank1_dfii_pi2_command0_re = 1'd0; -wire [5:0] csrbank1_dfii_pi2_command0_r; -reg csrbank1_dfii_pi2_command0_we = 1'd0; -wire [5:0] csrbank1_dfii_pi2_command0_w; -reg csrbank1_dfii_pi2_address0_re = 1'd0; -wire [13:0] csrbank1_dfii_pi2_address0_r; -reg csrbank1_dfii_pi2_address0_we = 1'd0; -wire [13:0] csrbank1_dfii_pi2_address0_w; -reg csrbank1_dfii_pi2_baddress0_re = 1'd0; -wire [2:0] csrbank1_dfii_pi2_baddress0_r; -reg csrbank1_dfii_pi2_baddress0_we = 1'd0; -wire [2:0] csrbank1_dfii_pi2_baddress0_w; -reg csrbank1_dfii_pi2_wrdata0_re = 1'd0; -wire [31:0] csrbank1_dfii_pi2_wrdata0_r; -reg csrbank1_dfii_pi2_wrdata0_we = 1'd0; -wire [31:0] csrbank1_dfii_pi2_wrdata0_w; -reg csrbank1_dfii_pi2_rddata_re = 1'd0; -wire [31:0] csrbank1_dfii_pi2_rddata_r; -reg csrbank1_dfii_pi2_rddata_we = 1'd0; -wire [31:0] csrbank1_dfii_pi2_rddata_w; -reg csrbank1_dfii_pi3_command0_re = 1'd0; -wire [5:0] csrbank1_dfii_pi3_command0_r; -reg csrbank1_dfii_pi3_command0_we = 1'd0; -wire [5:0] csrbank1_dfii_pi3_command0_w; -reg csrbank1_dfii_pi3_address0_re = 1'd0; -wire [13:0] csrbank1_dfii_pi3_address0_r; -reg csrbank1_dfii_pi3_address0_we = 1'd0; -wire [13:0] csrbank1_dfii_pi3_address0_w; -reg csrbank1_dfii_pi3_baddress0_re = 1'd0; -wire [2:0] csrbank1_dfii_pi3_baddress0_r; -reg csrbank1_dfii_pi3_baddress0_we = 1'd0; -wire [2:0] csrbank1_dfii_pi3_baddress0_w; -reg csrbank1_dfii_pi3_wrdata0_re = 1'd0; -wire [31:0] csrbank1_dfii_pi3_wrdata0_r; -reg csrbank1_dfii_pi3_wrdata0_we = 1'd0; -wire [31:0] csrbank1_dfii_pi3_wrdata0_w; -reg csrbank1_dfii_pi3_rddata_re = 1'd0; -wire [31:0] csrbank1_dfii_pi3_rddata_r; -reg csrbank1_dfii_pi3_rddata_we = 1'd0; -wire [31:0] csrbank1_dfii_pi3_rddata_w; -wire csrbank1_sel; -wire [13:0] csr_interconnect_adr; -wire csr_interconnect_we; -wire [31:0] csr_interconnect_dat_w; -wire [31:0] csr_interconnect_dat_r; -reg [1:0] litedramcore_refresher_state = 2'd0; -reg [1:0] litedramcore_refresher_next_state = 2'd0; -reg [3:0] litedramcore_bankmachine0_state = 4'd0; -reg [3:0] litedramcore_bankmachine0_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine1_state = 4'd0; -reg [3:0] litedramcore_bankmachine1_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine2_state = 4'd0; -reg [3:0] litedramcore_bankmachine2_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine3_state = 4'd0; -reg [3:0] litedramcore_bankmachine3_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine4_state = 4'd0; -reg [3:0] litedramcore_bankmachine4_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine5_state = 4'd0; -reg [3:0] litedramcore_bankmachine5_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine6_state = 4'd0; -reg [3:0] litedramcore_bankmachine6_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine7_state = 4'd0; -reg [3:0] litedramcore_bankmachine7_next_state = 4'd0; -reg [3:0] litedramcore_multiplexer_state = 4'd0; -reg [3:0] litedramcore_multiplexer_next_state = 4'd0; -wire litedramcore_roundrobin0_request; -wire litedramcore_roundrobin0_grant; -wire litedramcore_roundrobin0_ce; -wire litedramcore_roundrobin1_request; -wire litedramcore_roundrobin1_grant; -wire litedramcore_roundrobin1_ce; -wire litedramcore_roundrobin2_request; -wire litedramcore_roundrobin2_grant; -wire litedramcore_roundrobin2_ce; -wire litedramcore_roundrobin3_request; -wire litedramcore_roundrobin3_grant; -wire litedramcore_roundrobin3_ce; -wire litedramcore_roundrobin4_request; -wire litedramcore_roundrobin4_grant; -wire litedramcore_roundrobin4_ce; -wire litedramcore_roundrobin5_request; -wire litedramcore_roundrobin5_grant; -wire litedramcore_roundrobin5_ce; -wire litedramcore_roundrobin6_request; -wire litedramcore_roundrobin6_grant; -wire litedramcore_roundrobin6_ce; -wire litedramcore_roundrobin7_request; -wire litedramcore_roundrobin7_grant; -wire litedramcore_roundrobin7_ce; -reg litedramcore_locked0 = 1'd0; -reg litedramcore_locked1 = 1'd0; -reg litedramcore_locked2 = 1'd0; -reg litedramcore_locked3 = 1'd0; -reg litedramcore_locked4 = 1'd0; -reg litedramcore_locked5 = 1'd0; -reg litedramcore_locked6 = 1'd0; -reg litedramcore_locked7 = 1'd0; -reg litedramcore_new_master_wdata_ready0 = 1'd0; -reg litedramcore_new_master_wdata_ready1 = 1'd0; -reg litedramcore_new_master_rdata_valid0 = 1'd0; -reg litedramcore_new_master_rdata_valid1 = 1'd0; -reg litedramcore_new_master_rdata_valid2 = 1'd0; -reg litedramcore_new_master_rdata_valid3 = 1'd0; -reg litedramcore_new_master_rdata_valid4 = 1'd0; -reg litedramcore_new_master_rdata_valid5 = 1'd0; -reg litedramcore_new_master_rdata_valid6 = 1'd0; -reg litedramcore_new_master_rdata_valid7 = 1'd0; -reg litedramcore_new_master_rdata_valid8 = 1'd0; -reg [1:0] litedramcore_state = 2'd0; -reg [1:0] litedramcore_next_state = 2'd0; -reg [31:0] litedramcore_dat_w_next_value0 = 32'd0; -reg litedramcore_dat_w_next_value_ce0 = 1'd0; -reg [13:0] litedramcore_adr_next_value1 = 14'd0; -reg litedramcore_adr_next_value_ce1 = 1'd0; -reg litedramcore_we_next_value2 = 1'd0; -reg litedramcore_we_next_value_ce2 = 1'd0; -wire [24:0] slice_proxy0; -wire [24:0] slice_proxy1; -wire [24:0] slice_proxy2; -wire [24:0] slice_proxy3; -wire [24:0] slice_proxy4; -wire [24:0] slice_proxy5; -wire [24:0] slice_proxy6; -wire [24:0] slice_proxy7; -wire [24:0] slice_proxy8; -wire [24:0] slice_proxy9; -wire [24:0] slice_proxy10; -wire [24:0] slice_proxy11; -wire [24:0] slice_proxy12; -wire [24:0] slice_proxy13; -wire [24:0] slice_proxy14; -wire [24:0] slice_proxy15; -reg rhs_array_muxed0 = 1'd0; -reg [13:0] rhs_array_muxed1 = 14'd0; -reg [2:0] rhs_array_muxed2 = 3'd0; -reg rhs_array_muxed3 = 1'd0; -reg rhs_array_muxed4 = 1'd0; -reg rhs_array_muxed5 = 1'd0; -reg t_array_muxed0 = 1'd0; -reg t_array_muxed1 = 1'd0; -reg t_array_muxed2 = 1'd0; -reg rhs_array_muxed6 = 1'd0; -reg [13:0] rhs_array_muxed7 = 14'd0; -reg [2:0] rhs_array_muxed8 = 3'd0; -reg rhs_array_muxed9 = 1'd0; -reg rhs_array_muxed10 = 1'd0; -reg rhs_array_muxed11 = 1'd0; -reg t_array_muxed3 = 1'd0; -reg t_array_muxed4 = 1'd0; -reg t_array_muxed5 = 1'd0; -reg [20:0] rhs_array_muxed12 = 21'd0; -reg rhs_array_muxed13 = 1'd0; -reg rhs_array_muxed14 = 1'd0; -reg [20:0] rhs_array_muxed15 = 21'd0; -reg rhs_array_muxed16 = 1'd0; -reg rhs_array_muxed17 = 1'd0; -reg [20:0] rhs_array_muxed18 = 21'd0; -reg rhs_array_muxed19 = 1'd0; -reg rhs_array_muxed20 = 1'd0; -reg [20:0] rhs_array_muxed21 = 21'd0; -reg rhs_array_muxed22 = 1'd0; -reg rhs_array_muxed23 = 1'd0; -reg [20:0] rhs_array_muxed24 = 21'd0; -reg rhs_array_muxed25 = 1'd0; -reg rhs_array_muxed26 = 1'd0; -reg [20:0] rhs_array_muxed27 = 21'd0; -reg rhs_array_muxed28 = 1'd0; -reg rhs_array_muxed29 = 1'd0; -reg [20:0] rhs_array_muxed30 = 21'd0; -reg rhs_array_muxed31 = 1'd0; -reg rhs_array_muxed32 = 1'd0; -reg [20:0] rhs_array_muxed33 = 21'd0; -reg rhs_array_muxed34 = 1'd0; -reg rhs_array_muxed35 = 1'd0; -reg [2:0] array_muxed0 = 3'd0; -reg [13:0] array_muxed1 = 14'd0; -reg array_muxed2 = 1'd0; -reg array_muxed3 = 1'd0; -reg array_muxed4 = 1'd0; -reg array_muxed5 = 1'd0; -reg array_muxed6 = 1'd0; -reg [2:0] array_muxed7 = 3'd0; -reg [13:0] array_muxed8 = 14'd0; -reg array_muxed9 = 1'd0; -reg array_muxed10 = 1'd0; -reg array_muxed11 = 1'd0; -reg array_muxed12 = 1'd0; -reg array_muxed13 = 1'd0; -reg [2:0] array_muxed14 = 3'd0; -reg [13:0] array_muxed15 = 14'd0; -reg array_muxed16 = 1'd0; -reg array_muxed17 = 1'd0; -reg array_muxed18 = 1'd0; -reg array_muxed19 = 1'd0; -reg array_muxed20 = 1'd0; -reg [2:0] array_muxed21 = 3'd0; -reg [13:0] array_muxed22 = 14'd0; -reg array_muxed23 = 1'd0; -reg array_muxed24 = 1'd0; -reg array_muxed25 = 1'd0; -reg array_muxed26 = 1'd0; -reg array_muxed27 = 1'd0; +reg [1:0] state = 2'd0; +wire sys_clk; +wire sys_rst; +reg t_self0 = 1'd0; +reg t_self1 = 1'd0; +reg t_self2 = 1'd0; +reg t_self3 = 1'd0; +reg t_self4 = 1'd0; +reg t_self5 = 1'd0; +wire we; //------------------------------------------------------------------------------ // Combinatorial Logic @@ -2062,6 +2245,17 @@ assign soc_user_port_wdata_payload_data = user_port_native_0_wdata_data; assign user_port_native_0_rdata_valid = (soc_user_port_rdata_valid & soc_user_enable); assign soc_user_port_rdata_ready = (user_port_native_0_rdata_ready & soc_user_enable); assign user_port_native_0_rdata_data = soc_user_port_rdata_payload_data; +assign interface0_adr = soc_wb_bus_adr; +assign interface0_dat_w = soc_wb_bus_dat_w; +assign soc_wb_bus_dat_r = interface0_dat_r; +assign interface0_sel = soc_wb_bus_sel; +assign interface0_cyc = soc_wb_bus_cyc; +assign interface0_stb = soc_wb_bus_stb; +assign soc_wb_bus_ack = interface0_ack; +assign interface0_we = soc_wb_bus_we; +assign interface0_cti = soc_wb_bus_cti; +assign interface0_bte = soc_wb_bus_bte; +assign soc_wb_bus_err = interface0_err; assign sys_clk = clk; assign por_clk = clk; assign sys_rst = soc_int_rst; @@ -3950,6 +4144,9 @@ always @(*) begin soc_litedramcore_master_p0_cs_n <= soc_litedramcore_ext_dfi_p0_cs_n; end else begin soc_litedramcore_master_p0_cs_n <= soc_litedramcore_slave_p0_cs_n; + if (1'd0) begin + soc_litedramcore_master_p0_cs_n <= {2{soc_litedramcore_slave_p0_cs_n}}; + end end end else begin soc_litedramcore_master_p0_cs_n <= soc_litedramcore_csr_dfi_p0_cs_n; @@ -4118,6 +4315,9 @@ always @(*) begin soc_litedramcore_master_p1_cs_n <= soc_litedramcore_ext_dfi_p1_cs_n; end else begin soc_litedramcore_master_p1_cs_n <= soc_litedramcore_slave_p1_cs_n; + if (1'd0) begin + soc_litedramcore_master_p1_cs_n <= {2{soc_litedramcore_slave_p1_cs_n}}; + end end end else begin soc_litedramcore_master_p1_cs_n <= soc_litedramcore_csr_dfi_p1_cs_n; @@ -4286,6 +4486,9 @@ always @(*) begin soc_litedramcore_master_p2_cs_n <= soc_litedramcore_ext_dfi_p2_cs_n; end else begin soc_litedramcore_master_p2_cs_n <= soc_litedramcore_slave_p2_cs_n; + if (1'd0) begin + soc_litedramcore_master_p2_cs_n <= {2{soc_litedramcore_slave_p2_cs_n}}; + end end end else begin soc_litedramcore_master_p2_cs_n <= soc_litedramcore_csr_dfi_p2_cs_n; @@ -4454,6 +4657,9 @@ always @(*) begin soc_litedramcore_master_p3_cs_n <= soc_litedramcore_ext_dfi_p3_cs_n; end else begin soc_litedramcore_master_p3_cs_n <= soc_litedramcore_slave_p3_cs_n; + if (1'd0) begin + soc_litedramcore_master_p3_cs_n <= {2{soc_litedramcore_slave_p3_cs_n}}; + end end end else begin soc_litedramcore_master_p3_cs_n <= soc_litedramcore_csr_dfi_p3_cs_n; @@ -4715,14 +4921,38 @@ always @(*) begin end else begin end end -assign soc_litedramcore_csr_dfi_p0_cke = soc_litedramcore_cke; -assign soc_litedramcore_csr_dfi_p1_cke = soc_litedramcore_cke; -assign soc_litedramcore_csr_dfi_p2_cke = soc_litedramcore_cke; -assign soc_litedramcore_csr_dfi_p3_cke = soc_litedramcore_cke; -assign soc_litedramcore_csr_dfi_p0_odt = soc_litedramcore_odt; -assign soc_litedramcore_csr_dfi_p1_odt = soc_litedramcore_odt; -assign soc_litedramcore_csr_dfi_p2_odt = soc_litedramcore_odt; -assign soc_litedramcore_csr_dfi_p3_odt = soc_litedramcore_odt; +always @(*) begin + soc_litedramcore_csr_dfi_p0_cke <= 1'd0; + soc_litedramcore_csr_dfi_p0_cke <= soc_litedramcore_cke; +end +always @(*) begin + soc_litedramcore_csr_dfi_p1_cke <= 1'd0; + soc_litedramcore_csr_dfi_p1_cke <= soc_litedramcore_cke; +end +always @(*) begin + soc_litedramcore_csr_dfi_p2_cke <= 1'd0; + soc_litedramcore_csr_dfi_p2_cke <= soc_litedramcore_cke; +end +always @(*) begin + soc_litedramcore_csr_dfi_p3_cke <= 1'd0; + soc_litedramcore_csr_dfi_p3_cke <= soc_litedramcore_cke; +end +always @(*) begin + soc_litedramcore_csr_dfi_p0_odt <= 1'd0; + soc_litedramcore_csr_dfi_p0_odt <= soc_litedramcore_odt; +end +always @(*) begin + soc_litedramcore_csr_dfi_p1_odt <= 1'd0; + soc_litedramcore_csr_dfi_p1_odt <= soc_litedramcore_odt; +end +always @(*) begin + soc_litedramcore_csr_dfi_p2_odt <= 1'd0; + soc_litedramcore_csr_dfi_p2_odt <= soc_litedramcore_odt; +end +always @(*) begin + soc_litedramcore_csr_dfi_p3_odt <= 1'd0; + soc_litedramcore_csr_dfi_p3_odt <= soc_litedramcore_odt; +end assign soc_litedramcore_csr_dfi_p0_reset_n = soc_litedramcore_reset_n; assign soc_litedramcore_csr_dfi_p1_reset_n = soc_litedramcore_reset_n; assign soc_litedramcore_csr_dfi_p2_reset_n = soc_litedramcore_reset_n; @@ -4730,7 +4960,15 @@ assign soc_litedramcore_csr_dfi_p3_reset_n = soc_litedramcore_reset_n; always @(*) begin soc_litedramcore_csr_dfi_p0_cs_n <= 1'd1; if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_csr_dfi_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_csrfield_cs)}}; + if (soc_litedramcore_phaseinjector0_csrfield_cs_top) begin + soc_litedramcore_csr_dfi_p0_cs_n <= 2'd2; + end else begin + if (soc_litedramcore_phaseinjector0_csrfield_cs_bottom) begin + soc_litedramcore_csr_dfi_p0_cs_n <= 1'd1; + end else begin + soc_litedramcore_csr_dfi_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_csrfield_cs)}}; + end + end end else begin soc_litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; end @@ -4768,7 +5006,15 @@ assign soc_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; always @(*) begin soc_litedramcore_csr_dfi_p1_cs_n <= 1'd1; if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_csr_dfi_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_csrfield_cs)}}; + if (soc_litedramcore_phaseinjector1_csrfield_cs_top) begin + soc_litedramcore_csr_dfi_p1_cs_n <= 2'd2; + end else begin + if (soc_litedramcore_phaseinjector1_csrfield_cs_bottom) begin + soc_litedramcore_csr_dfi_p1_cs_n <= 1'd1; + end else begin + soc_litedramcore_csr_dfi_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_csrfield_cs)}}; + end + end end else begin soc_litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; end @@ -4806,7 +5052,15 @@ assign soc_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; always @(*) begin soc_litedramcore_csr_dfi_p2_cs_n <= 1'd1; if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_csr_dfi_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_csrfield_cs)}}; + if (soc_litedramcore_phaseinjector2_csrfield_cs_top) begin + soc_litedramcore_csr_dfi_p2_cs_n <= 2'd2; + end else begin + if (soc_litedramcore_phaseinjector2_csrfield_cs_bottom) begin + soc_litedramcore_csr_dfi_p2_cs_n <= 1'd1; + end else begin + soc_litedramcore_csr_dfi_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_csrfield_cs)}}; + end + end end else begin soc_litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; end @@ -4844,7 +5098,15 @@ assign soc_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; always @(*) begin soc_litedramcore_csr_dfi_p3_cs_n <= 1'd1; if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_csr_dfi_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_csrfield_cs)}}; + if (soc_litedramcore_phaseinjector3_csrfield_cs_top) begin + soc_litedramcore_csr_dfi_p3_cs_n <= 2'd2; + end else begin + if (soc_litedramcore_phaseinjector3_csrfield_cs_bottom) begin + soc_litedramcore_csr_dfi_p3_cs_n <= 1'd1; + end else begin + soc_litedramcore_csr_dfi_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_csrfield_cs)}}; + end + end end else begin soc_litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; end @@ -4949,32 +5211,32 @@ assign soc_litedramcore_zqcs_timer_done1 = (soc_litedramcore_zqcs_timer_count1 = assign soc_litedramcore_zqcs_timer_done0 = soc_litedramcore_zqcs_timer_done1; assign soc_litedramcore_zqcs_timer_count0 = soc_litedramcore_zqcs_timer_count1; always @(*) begin - litedramcore_refresher_next_state <= 2'd0; - litedramcore_refresher_next_state <= litedramcore_refresher_state; - case (litedramcore_refresher_state) + refresher_next_state <= 2'd0; + refresher_next_state <= refresher_state; + case (refresher_state) 1'd1: begin if (soc_litedramcore_cmd_ready) begin - litedramcore_refresher_next_state <= 2'd2; + refresher_next_state <= 2'd2; end end 2'd2: begin if (soc_litedramcore_sequencer_done0) begin if (soc_litedramcore_wants_zqcs) begin - litedramcore_refresher_next_state <= 2'd3; + refresher_next_state <= 2'd3; end else begin - litedramcore_refresher_next_state <= 1'd0; + refresher_next_state <= 1'd0; end end end 2'd3: begin if (soc_litedramcore_zqcs_executer_done) begin - litedramcore_refresher_next_state <= 1'd0; + refresher_next_state <= 1'd0; end end default: begin if (1'd1) begin if (soc_litedramcore_wants_refresh) begin - litedramcore_refresher_next_state <= 1'd1; + refresher_next_state <= 1'd1; end end end @@ -4982,7 +5244,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_sequencer_start0 <= 1'd0; - case (litedramcore_refresher_state) + case (refresher_state) 1'd1: begin if (soc_litedramcore_cmd_ready) begin soc_litedramcore_sequencer_start0 <= 1'd1; @@ -4998,7 +5260,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_cmd_valid <= 1'd0; - case (litedramcore_refresher_state) + case (refresher_state) 1'd1: begin soc_litedramcore_cmd_valid <= 1'd1; end @@ -5023,7 +5285,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_zqcs_executer_start <= 1'd0; - case (litedramcore_refresher_state) + case (refresher_state) 1'd1: begin end 2'd2: begin @@ -5042,7 +5304,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_cmd_last <= 1'd0; - case (litedramcore_refresher_state) + case (refresher_state) 1'd1: begin end 2'd2: begin @@ -5141,69 +5403,95 @@ assign soc_litedramcore_bankmachine0_source_source_last = soc_litedramcore_bankm assign soc_litedramcore_bankmachine0_source_source_payload_we = soc_litedramcore_bankmachine0_pipe_valid_source_payload_we; assign soc_litedramcore_bankmachine0_source_source_payload_addr = soc_litedramcore_bankmachine0_pipe_valid_source_payload_addr; always @(*) begin - litedramcore_bankmachine0_next_state <= 4'd0; - litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state; - case (litedramcore_bankmachine0_state) + bankmachine0_next_state <= 4'd0; + bankmachine0_next_state <= bankmachine0_state; + case (bankmachine0_state) 1'd1: begin if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin if (soc_litedramcore_bankmachine0_cmd_ready) begin - litedramcore_bankmachine0_next_state <= 3'd5; + bankmachine0_next_state <= 3'd5; end end end 2'd2: begin if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_next_state <= 3'd5; + bankmachine0_next_state <= 3'd5; end end 2'd3: begin if (soc_litedramcore_bankmachine0_trccon_ready) begin if (soc_litedramcore_bankmachine0_cmd_ready) begin - litedramcore_bankmachine0_next_state <= 3'd7; + bankmachine0_next_state <= 3'd7; end end end 3'd4: begin if ((~soc_litedramcore_bankmachine0_refresh_req)) begin - litedramcore_bankmachine0_next_state <= 1'd0; + bankmachine0_next_state <= 1'd0; end end 3'd5: begin - litedramcore_bankmachine0_next_state <= 3'd6; + bankmachine0_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine0_next_state <= 2'd3; + bankmachine0_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine0_next_state <= 4'd8; + bankmachine0_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine0_next_state <= 1'd0; + bankmachine0_next_state <= 1'd0; end default: begin if (soc_litedramcore_bankmachine0_refresh_req) begin - litedramcore_bankmachine0_next_state <= 3'd4; + bankmachine0_next_state <= 3'd4; end else begin if (soc_litedramcore_bankmachine0_source_source_valid) begin if (soc_litedramcore_bankmachine0_row_opened) begin if (soc_litedramcore_bankmachine0_row_hit) begin if ((soc_litedramcore_bankmachine0_cmd_ready & soc_litedramcore_bankmachine0_auto_precharge)) begin - litedramcore_bankmachine0_next_state <= 2'd2; + bankmachine0_next_state <= 2'd2; end end else begin - litedramcore_bankmachine0_next_state <= 1'd1; + bankmachine0_next_state <= 1'd1; end end else begin - litedramcore_bankmachine0_next_state <= 2'd3; + bankmachine0_next_state <= 2'd3; end end end end endcase end +always @(*) begin + soc_litedramcore_bankmachine0_row_close <= 1'd0; + case (bankmachine0_state) + 1'd1: begin + soc_litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine0_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end always @(*) begin soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine0_state) + case (bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5229,7 +5517,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine0_state) + case (bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5264,7 +5552,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine0_state) + case (bankmachine0_state) 1'd1: begin if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; @@ -5293,7 +5581,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine0_state) + case (bankmachine0_state) 1'd1: begin if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; @@ -5334,7 +5622,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine0_state) + case (bankmachine0_state) 1'd1: begin if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; @@ -5364,7 +5652,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine0_state) + case (bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5402,7 +5690,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine0_state) + case (bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5440,7 +5728,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine0_state) + case (bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5478,7 +5766,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine0_state) + case (bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5516,7 +5804,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine0_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine0_state) + case (bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5542,7 +5830,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine0_row_open <= 1'd0; - case (litedramcore_bankmachine0_state) + case (bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5568,7 +5856,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine0_cmd_valid <= 1'd0; - case (litedramcore_bankmachine0_state) + case (bankmachine0_state) 1'd1: begin if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; @@ -5607,32 +5895,6 @@ always @(*) begin end endcase end -always @(*) begin - soc_litedramcore_bankmachine0_row_close <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - soc_litedramcore_bankmachine0_row_close <= 1'd1; - end - 2'd2: begin - soc_litedramcore_bankmachine0_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - soc_litedramcore_bankmachine0_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end assign soc_litedramcore_bankmachine1_sink_valid = soc_litedramcore_bankmachine1_req_valid; assign soc_litedramcore_bankmachine1_req_ready = soc_litedramcore_bankmachine1_sink_ready; assign soc_litedramcore_bankmachine1_sink_payload_we = soc_litedramcore_bankmachine1_req_we; @@ -5712,60 +5974,95 @@ assign soc_litedramcore_bankmachine1_source_source_last = soc_litedramcore_bankm assign soc_litedramcore_bankmachine1_source_source_payload_we = soc_litedramcore_bankmachine1_pipe_valid_source_payload_we; assign soc_litedramcore_bankmachine1_source_source_payload_addr = soc_litedramcore_bankmachine1_pipe_valid_source_payload_addr; always @(*) begin - litedramcore_bankmachine1_next_state <= 4'd0; - litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state; - case (litedramcore_bankmachine1_state) + bankmachine1_next_state <= 4'd0; + bankmachine1_next_state <= bankmachine1_state; + case (bankmachine1_state) 1'd1: begin if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin if (soc_litedramcore_bankmachine1_cmd_ready) begin - litedramcore_bankmachine1_next_state <= 3'd5; + bankmachine1_next_state <= 3'd5; end end end 2'd2: begin if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_next_state <= 3'd5; + bankmachine1_next_state <= 3'd5; end end 2'd3: begin if (soc_litedramcore_bankmachine1_trccon_ready) begin if (soc_litedramcore_bankmachine1_cmd_ready) begin - litedramcore_bankmachine1_next_state <= 3'd7; + bankmachine1_next_state <= 3'd7; end end end 3'd4: begin if ((~soc_litedramcore_bankmachine1_refresh_req)) begin - litedramcore_bankmachine1_next_state <= 1'd0; + bankmachine1_next_state <= 1'd0; end end 3'd5: begin - litedramcore_bankmachine1_next_state <= 3'd6; + bankmachine1_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine1_next_state <= 2'd3; + bankmachine1_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine1_next_state <= 4'd8; + bankmachine1_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine1_next_state <= 1'd0; + bankmachine1_next_state <= 1'd0; end default: begin if (soc_litedramcore_bankmachine1_refresh_req) begin - litedramcore_bankmachine1_next_state <= 3'd4; + bankmachine1_next_state <= 3'd4; end else begin if (soc_litedramcore_bankmachine1_source_source_valid) begin if (soc_litedramcore_bankmachine1_row_opened) begin if (soc_litedramcore_bankmachine1_row_hit) begin if ((soc_litedramcore_bankmachine1_cmd_ready & soc_litedramcore_bankmachine1_auto_precharge)) begin - litedramcore_bankmachine1_next_state <= 2'd2; + bankmachine1_next_state <= 2'd2; end end else begin - litedramcore_bankmachine1_next_state <= 1'd1; + bankmachine1_next_state <= 1'd1; + end + end else begin + bankmachine1_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_source_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + end else begin end end else begin - litedramcore_bankmachine1_next_state <= 2'd3; end end end @@ -5774,7 +6071,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine1_state) + case (bankmachine1_state) 1'd1: begin if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; @@ -5803,7 +6100,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine1_state) + case (bankmachine1_state) 1'd1: begin if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; @@ -5844,7 +6141,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine1_state) + case (bankmachine1_state) 1'd1: begin if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; @@ -5874,7 +6171,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine1_state) + case (bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -5912,7 +6209,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine1_state) + case (bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -5950,7 +6247,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine1_state) + case (bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -5988,7 +6285,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine1_state) + case (bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -6026,7 +6323,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine1_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine1_state) + case (bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -6052,7 +6349,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine1_row_open <= 1'd0; - case (litedramcore_bankmachine1_state) + case (bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -6078,7 +6375,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine1_cmd_valid <= 1'd0; - case (litedramcore_bankmachine1_state) + case (bankmachine1_state) 1'd1: begin if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; @@ -6119,7 +6416,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine1_row_close <= 1'd0; - case (litedramcore_bankmachine1_state) + case (bankmachine1_state) 1'd1: begin soc_litedramcore_bankmachine1_row_close <= 1'd1; end @@ -6145,7 +6442,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine1_state) + case (bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -6169,41 +6466,6 @@ always @(*) begin end endcase end -always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_source_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end assign soc_litedramcore_bankmachine2_sink_valid = soc_litedramcore_bankmachine2_req_valid; assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_sink_ready; assign soc_litedramcore_bankmachine2_sink_payload_we = soc_litedramcore_bankmachine2_req_we; @@ -6283,60 +6545,128 @@ assign soc_litedramcore_bankmachine2_source_source_last = soc_litedramcore_bankm assign soc_litedramcore_bankmachine2_source_source_payload_we = soc_litedramcore_bankmachine2_pipe_valid_source_payload_we; assign soc_litedramcore_bankmachine2_source_source_payload_addr = soc_litedramcore_bankmachine2_pipe_valid_source_payload_addr; always @(*) begin - litedramcore_bankmachine2_next_state <= 4'd0; - litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state; - case (litedramcore_bankmachine2_state) + bankmachine2_next_state <= 4'd0; + bankmachine2_next_state <= bankmachine2_state; + case (bankmachine2_state) 1'd1: begin if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin if (soc_litedramcore_bankmachine2_cmd_ready) begin - litedramcore_bankmachine2_next_state <= 3'd5; + bankmachine2_next_state <= 3'd5; end end end 2'd2: begin if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_next_state <= 3'd5; + bankmachine2_next_state <= 3'd5; end end 2'd3: begin if (soc_litedramcore_bankmachine2_trccon_ready) begin if (soc_litedramcore_bankmachine2_cmd_ready) begin - litedramcore_bankmachine2_next_state <= 3'd7; + bankmachine2_next_state <= 3'd7; end end end 3'd4: begin if ((~soc_litedramcore_bankmachine2_refresh_req)) begin - litedramcore_bankmachine2_next_state <= 1'd0; + bankmachine2_next_state <= 1'd0; end end 3'd5: begin - litedramcore_bankmachine2_next_state <= 3'd6; + bankmachine2_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine2_next_state <= 2'd3; + bankmachine2_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine2_next_state <= 4'd8; + bankmachine2_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine2_next_state <= 1'd0; + bankmachine2_next_state <= 1'd0; end default: begin if (soc_litedramcore_bankmachine2_refresh_req) begin - litedramcore_bankmachine2_next_state <= 3'd4; + bankmachine2_next_state <= 3'd4; end else begin if (soc_litedramcore_bankmachine2_source_source_valid) begin if (soc_litedramcore_bankmachine2_row_opened) begin if (soc_litedramcore_bankmachine2_row_hit) begin if ((soc_litedramcore_bankmachine2_cmd_ready & soc_litedramcore_bankmachine2_auto_precharge)) begin - litedramcore_bankmachine2_next_state <= 2'd2; + bankmachine2_next_state <= 2'd2; + end + end else begin + bankmachine2_next_state <= 1'd1; + end + end else begin + bankmachine2_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (bankmachine2_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_source_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_source_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; end end else begin - litedramcore_bankmachine2_next_state <= 1'd1; end end else begin - litedramcore_bankmachine2_next_state <= 2'd3; end end end @@ -6345,7 +6675,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine2_state) + case (bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6383,7 +6713,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine2_state) + case (bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6421,7 +6751,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine2_state) + case (bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6459,7 +6789,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine2_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine2_state) + case (bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6485,7 +6815,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine2_row_open <= 1'd0; - case (litedramcore_bankmachine2_state) + case (bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6511,7 +6841,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine2_cmd_valid <= 1'd0; - case (litedramcore_bankmachine2_state) + case (bankmachine2_state) 1'd1: begin if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; @@ -6552,7 +6882,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine2_row_close <= 1'd0; - case (litedramcore_bankmachine2_state) + case (bankmachine2_state) 1'd1: begin soc_litedramcore_bankmachine2_row_close <= 1'd1; end @@ -6578,7 +6908,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine2_state) + case (bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6604,7 +6934,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine2_state) + case (bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6639,7 +6969,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine2_state) + case (bankmachine2_state) 1'd1: begin if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; @@ -6668,7 +6998,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine2_state) + case (bankmachine2_state) 1'd1: begin if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; @@ -6707,74 +7037,6 @@ always @(*) begin end endcase end -always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine2_source_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_source_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end assign soc_litedramcore_bankmachine3_sink_valid = soc_litedramcore_bankmachine3_req_valid; assign soc_litedramcore_bankmachine3_req_ready = soc_litedramcore_bankmachine3_sink_ready; assign soc_litedramcore_bankmachine3_sink_payload_we = soc_litedramcore_bankmachine3_req_we; @@ -6854,60 +7116,60 @@ assign soc_litedramcore_bankmachine3_source_source_last = soc_litedramcore_bankm assign soc_litedramcore_bankmachine3_source_source_payload_we = soc_litedramcore_bankmachine3_pipe_valid_source_payload_we; assign soc_litedramcore_bankmachine3_source_source_payload_addr = soc_litedramcore_bankmachine3_pipe_valid_source_payload_addr; always @(*) begin - litedramcore_bankmachine3_next_state <= 4'd0; - litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state; - case (litedramcore_bankmachine3_state) + bankmachine3_next_state <= 4'd0; + bankmachine3_next_state <= bankmachine3_state; + case (bankmachine3_state) 1'd1: begin if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin if (soc_litedramcore_bankmachine3_cmd_ready) begin - litedramcore_bankmachine3_next_state <= 3'd5; + bankmachine3_next_state <= 3'd5; end end end 2'd2: begin if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_next_state <= 3'd5; + bankmachine3_next_state <= 3'd5; end end 2'd3: begin if (soc_litedramcore_bankmachine3_trccon_ready) begin if (soc_litedramcore_bankmachine3_cmd_ready) begin - litedramcore_bankmachine3_next_state <= 3'd7; + bankmachine3_next_state <= 3'd7; end end end 3'd4: begin if ((~soc_litedramcore_bankmachine3_refresh_req)) begin - litedramcore_bankmachine3_next_state <= 1'd0; + bankmachine3_next_state <= 1'd0; end end 3'd5: begin - litedramcore_bankmachine3_next_state <= 3'd6; + bankmachine3_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine3_next_state <= 2'd3; + bankmachine3_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine3_next_state <= 4'd8; + bankmachine3_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine3_next_state <= 1'd0; + bankmachine3_next_state <= 1'd0; end default: begin if (soc_litedramcore_bankmachine3_refresh_req) begin - litedramcore_bankmachine3_next_state <= 3'd4; + bankmachine3_next_state <= 3'd4; end else begin if (soc_litedramcore_bankmachine3_source_source_valid) begin if (soc_litedramcore_bankmachine3_row_opened) begin if (soc_litedramcore_bankmachine3_row_hit) begin if ((soc_litedramcore_bankmachine3_cmd_ready & soc_litedramcore_bankmachine3_auto_precharge)) begin - litedramcore_bankmachine3_next_state <= 2'd2; + bankmachine3_next_state <= 2'd2; end end else begin - litedramcore_bankmachine3_next_state <= 1'd1; + bankmachine3_next_state <= 1'd1; end end else begin - litedramcore_bankmachine3_next_state <= 2'd3; + bankmachine3_next_state <= 2'd3; end end end @@ -6915,18 +7177,56 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine3_row_open <= 1'd0; - case (litedramcore_bankmachine3_state) + soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_row_open <= 1'd1; + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_source_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_source_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready; + end + end else begin + end + end else begin + end + end end end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end 3'd4: begin + if (soc_litedramcore_bankmachine3_twtpcon_ready) begin + soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -6942,7 +7242,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine3_cmd_valid <= 1'd0; - case (litedramcore_bankmachine3_state) + case (bankmachine3_state) 1'd1: begin if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; @@ -6983,7 +7283,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine3_row_close <= 1'd0; - case (litedramcore_bankmachine3_state) + case (bankmachine3_state) 1'd1: begin soc_litedramcore_bankmachine3_row_close <= 1'd1; end @@ -7008,18 +7308,18 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine3_state) + soc_litedramcore_bankmachine3_row_open <= 1'd0; + case (bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_row_open <= 1'd1; + end end 3'd4: begin - if (soc_litedramcore_bankmachine3_twtpcon_ready) begin - soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7035,7 +7335,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine3_state) + case (bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -7061,7 +7361,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine3_state) + case (bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -7096,7 +7396,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine3_state) + case (bankmachine3_state) 1'd1: begin if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; @@ -7125,7 +7425,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine3_state) + case (bankmachine3_state) 1'd1: begin if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; @@ -7166,7 +7466,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine3_state) + case (bankmachine3_state) 1'd1: begin if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; @@ -7196,7 +7496,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine3_state) + case (bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -7234,7 +7534,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine3_state) + case (bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -7271,46 +7571,8 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine3_source_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_source_source_payload_we) begin - soc_litedramcore_bankmachine3_req_wdata_ready <= soc_litedramcore_bankmachine3_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine3_state) + soc_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + case (bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -7334,8 +7596,8 @@ always @(*) begin if (soc_litedramcore_bankmachine3_row_opened) begin if (soc_litedramcore_bankmachine3_row_hit) begin if (soc_litedramcore_bankmachine3_source_source_payload_we) begin + soc_litedramcore_bankmachine3_req_wdata_ready <= soc_litedramcore_bankmachine3_cmd_ready; end else begin - soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready; end end else begin end @@ -7425,69 +7687,95 @@ assign soc_litedramcore_bankmachine4_source_source_last = soc_litedramcore_bankm assign soc_litedramcore_bankmachine4_source_source_payload_we = soc_litedramcore_bankmachine4_pipe_valid_source_payload_we; assign soc_litedramcore_bankmachine4_source_source_payload_addr = soc_litedramcore_bankmachine4_pipe_valid_source_payload_addr; always @(*) begin - litedramcore_bankmachine4_next_state <= 4'd0; - litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state; - case (litedramcore_bankmachine4_state) + bankmachine4_next_state <= 4'd0; + bankmachine4_next_state <= bankmachine4_state; + case (bankmachine4_state) 1'd1: begin if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin if (soc_litedramcore_bankmachine4_cmd_ready) begin - litedramcore_bankmachine4_next_state <= 3'd5; + bankmachine4_next_state <= 3'd5; end end end 2'd2: begin if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_next_state <= 3'd5; + bankmachine4_next_state <= 3'd5; end end 2'd3: begin if (soc_litedramcore_bankmachine4_trccon_ready) begin if (soc_litedramcore_bankmachine4_cmd_ready) begin - litedramcore_bankmachine4_next_state <= 3'd7; + bankmachine4_next_state <= 3'd7; end end end 3'd4: begin if ((~soc_litedramcore_bankmachine4_refresh_req)) begin - litedramcore_bankmachine4_next_state <= 1'd0; + bankmachine4_next_state <= 1'd0; end end 3'd5: begin - litedramcore_bankmachine4_next_state <= 3'd6; + bankmachine4_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine4_next_state <= 2'd3; + bankmachine4_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine4_next_state <= 4'd8; + bankmachine4_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine4_next_state <= 1'd0; + bankmachine4_next_state <= 1'd0; end default: begin if (soc_litedramcore_bankmachine4_refresh_req) begin - litedramcore_bankmachine4_next_state <= 3'd4; + bankmachine4_next_state <= 3'd4; end else begin if (soc_litedramcore_bankmachine4_source_source_valid) begin if (soc_litedramcore_bankmachine4_row_opened) begin if (soc_litedramcore_bankmachine4_row_hit) begin if ((soc_litedramcore_bankmachine4_cmd_ready & soc_litedramcore_bankmachine4_auto_precharge)) begin - litedramcore_bankmachine4_next_state <= 2'd2; + bankmachine4_next_state <= 2'd2; end end else begin - litedramcore_bankmachine4_next_state <= 1'd1; + bankmachine4_next_state <= 1'd1; end end else begin - litedramcore_bankmachine4_next_state <= 2'd3; + bankmachine4_next_state <= 2'd3; end end end end endcase end +always @(*) begin + soc_litedramcore_bankmachine4_row_close <= 1'd0; + case (bankmachine4_state) + 1'd1: begin + soc_litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine4_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end always @(*) begin soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine4_state) + case (bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7513,7 +7801,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine4_state) + case (bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7548,7 +7836,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine4_state) + case (bankmachine4_state) 1'd1: begin if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; @@ -7577,7 +7865,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine4_state) + case (bankmachine4_state) 1'd1: begin if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; @@ -7618,7 +7906,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine4_state) + case (bankmachine4_state) 1'd1: begin if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; @@ -7648,7 +7936,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine4_state) + case (bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7686,7 +7974,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine4_state) + case (bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7724,7 +8012,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine4_state) + case (bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7762,7 +8050,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine4_state) + case (bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7800,7 +8088,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine4_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine4_state) + case (bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7826,7 +8114,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine4_row_open <= 1'd0; - case (litedramcore_bankmachine4_state) + case (bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7852,7 +8140,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine4_cmd_valid <= 1'd0; - case (litedramcore_bankmachine4_state) + case (bankmachine4_state) 1'd1: begin if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; @@ -7891,32 +8179,6 @@ always @(*) begin end endcase end -always @(*) begin - soc_litedramcore_bankmachine4_row_close <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - soc_litedramcore_bankmachine4_row_close <= 1'd1; - end - 2'd2: begin - soc_litedramcore_bankmachine4_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - soc_litedramcore_bankmachine4_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end assign soc_litedramcore_bankmachine5_sink_valid = soc_litedramcore_bankmachine5_req_valid; assign soc_litedramcore_bankmachine5_req_ready = soc_litedramcore_bankmachine5_sink_ready; assign soc_litedramcore_bankmachine5_sink_payload_we = soc_litedramcore_bankmachine5_req_we; @@ -7996,60 +8258,95 @@ assign soc_litedramcore_bankmachine5_source_source_last = soc_litedramcore_bankm assign soc_litedramcore_bankmachine5_source_source_payload_we = soc_litedramcore_bankmachine5_pipe_valid_source_payload_we; assign soc_litedramcore_bankmachine5_source_source_payload_addr = soc_litedramcore_bankmachine5_pipe_valid_source_payload_addr; always @(*) begin - litedramcore_bankmachine5_next_state <= 4'd0; - litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state; - case (litedramcore_bankmachine5_state) + bankmachine5_next_state <= 4'd0; + bankmachine5_next_state <= bankmachine5_state; + case (bankmachine5_state) 1'd1: begin if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin if (soc_litedramcore_bankmachine5_cmd_ready) begin - litedramcore_bankmachine5_next_state <= 3'd5; + bankmachine5_next_state <= 3'd5; end end end 2'd2: begin if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_next_state <= 3'd5; + bankmachine5_next_state <= 3'd5; end end 2'd3: begin if (soc_litedramcore_bankmachine5_trccon_ready) begin if (soc_litedramcore_bankmachine5_cmd_ready) begin - litedramcore_bankmachine5_next_state <= 3'd7; + bankmachine5_next_state <= 3'd7; end end end 3'd4: begin if ((~soc_litedramcore_bankmachine5_refresh_req)) begin - litedramcore_bankmachine5_next_state <= 1'd0; + bankmachine5_next_state <= 1'd0; end end 3'd5: begin - litedramcore_bankmachine5_next_state <= 3'd6; + bankmachine5_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine5_next_state <= 2'd3; + bankmachine5_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine5_next_state <= 4'd8; + bankmachine5_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine5_next_state <= 1'd0; + bankmachine5_next_state <= 1'd0; end default: begin if (soc_litedramcore_bankmachine5_refresh_req) begin - litedramcore_bankmachine5_next_state <= 3'd4; + bankmachine5_next_state <= 3'd4; end else begin if (soc_litedramcore_bankmachine5_source_source_valid) begin if (soc_litedramcore_bankmachine5_row_opened) begin if (soc_litedramcore_bankmachine5_row_hit) begin if ((soc_litedramcore_bankmachine5_cmd_ready & soc_litedramcore_bankmachine5_auto_precharge)) begin - litedramcore_bankmachine5_next_state <= 2'd2; + bankmachine5_next_state <= 2'd2; end end else begin - litedramcore_bankmachine5_next_state <= 1'd1; + bankmachine5_next_state <= 1'd1; + end + end else begin + bankmachine5_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_source_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + end else begin end end else begin - litedramcore_bankmachine5_next_state <= 2'd3; end end end @@ -8058,7 +8355,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine5_state) + case (bankmachine5_state) 1'd1: begin if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; @@ -8087,7 +8384,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine5_state) + case (bankmachine5_state) 1'd1: begin if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; @@ -8128,7 +8425,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine5_state) + case (bankmachine5_state) 1'd1: begin if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; @@ -8158,7 +8455,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine5_state) + case (bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -8196,7 +8493,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine5_state) + case (bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -8234,7 +8531,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine5_state) + case (bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -8272,7 +8569,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine5_state) + case (bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -8310,7 +8607,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine5_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine5_state) + case (bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -8336,7 +8633,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine5_row_open <= 1'd0; - case (litedramcore_bankmachine5_state) + case (bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -8362,7 +8659,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine5_cmd_valid <= 1'd0; - case (litedramcore_bankmachine5_state) + case (bankmachine5_state) 1'd1: begin if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; @@ -8403,7 +8700,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine5_row_close <= 1'd0; - case (litedramcore_bankmachine5_state) + case (bankmachine5_state) 1'd1: begin soc_litedramcore_bankmachine5_row_close <= 1'd1; end @@ -8429,7 +8726,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine5_state) + case (bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -8453,41 +8750,6 @@ always @(*) begin end endcase end -always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine5_source_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end assign soc_litedramcore_bankmachine6_sink_valid = soc_litedramcore_bankmachine6_req_valid; assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_sink_ready; assign soc_litedramcore_bankmachine6_sink_payload_we = soc_litedramcore_bankmachine6_req_we; @@ -8567,60 +8829,128 @@ assign soc_litedramcore_bankmachine6_source_source_last = soc_litedramcore_bankm assign soc_litedramcore_bankmachine6_source_source_payload_we = soc_litedramcore_bankmachine6_pipe_valid_source_payload_we; assign soc_litedramcore_bankmachine6_source_source_payload_addr = soc_litedramcore_bankmachine6_pipe_valid_source_payload_addr; always @(*) begin - litedramcore_bankmachine6_next_state <= 4'd0; - litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state; - case (litedramcore_bankmachine6_state) + bankmachine6_next_state <= 4'd0; + bankmachine6_next_state <= bankmachine6_state; + case (bankmachine6_state) 1'd1: begin if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin if (soc_litedramcore_bankmachine6_cmd_ready) begin - litedramcore_bankmachine6_next_state <= 3'd5; + bankmachine6_next_state <= 3'd5; end end end 2'd2: begin if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_next_state <= 3'd5; + bankmachine6_next_state <= 3'd5; end end 2'd3: begin if (soc_litedramcore_bankmachine6_trccon_ready) begin if (soc_litedramcore_bankmachine6_cmd_ready) begin - litedramcore_bankmachine6_next_state <= 3'd7; + bankmachine6_next_state <= 3'd7; end end end 3'd4: begin if ((~soc_litedramcore_bankmachine6_refresh_req)) begin - litedramcore_bankmachine6_next_state <= 1'd0; + bankmachine6_next_state <= 1'd0; end end 3'd5: begin - litedramcore_bankmachine6_next_state <= 3'd6; + bankmachine6_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine6_next_state <= 2'd3; + bankmachine6_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine6_next_state <= 4'd8; + bankmachine6_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine6_next_state <= 1'd0; + bankmachine6_next_state <= 1'd0; end default: begin if (soc_litedramcore_bankmachine6_refresh_req) begin - litedramcore_bankmachine6_next_state <= 3'd4; + bankmachine6_next_state <= 3'd4; end else begin if (soc_litedramcore_bankmachine6_source_source_valid) begin if (soc_litedramcore_bankmachine6_row_opened) begin if (soc_litedramcore_bankmachine6_row_hit) begin if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin - litedramcore_bankmachine6_next_state <= 2'd2; + bankmachine6_next_state <= 2'd2; + end + end else begin + bankmachine6_next_state <= 1'd1; + end + end else begin + bankmachine6_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (bankmachine6_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_source_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_source_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; end end else begin - litedramcore_bankmachine6_next_state <= 1'd1; end end else begin - litedramcore_bankmachine6_next_state <= 2'd3; end end end @@ -8629,7 +8959,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine6_state) + case (bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8667,7 +8997,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine6_state) + case (bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8705,7 +9035,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine6_state) + case (bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8743,7 +9073,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine6_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine6_state) + case (bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8769,7 +9099,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine6_row_open <= 1'd0; - case (litedramcore_bankmachine6_state) + case (bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8795,7 +9125,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine6_cmd_valid <= 1'd0; - case (litedramcore_bankmachine6_state) + case (bankmachine6_state) 1'd1: begin if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; @@ -8836,7 +9166,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine6_row_close <= 1'd0; - case (litedramcore_bankmachine6_state) + case (bankmachine6_state) 1'd1: begin soc_litedramcore_bankmachine6_row_close <= 1'd1; end @@ -8862,7 +9192,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine6_state) + case (bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8888,7 +9218,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine6_state) + case (bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8922,92 +9252,21 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine6_source_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_source_source_payload_we) begin - soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine6_state) + soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (bankmachine6_state) 1'd1: begin if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9022,9 +9281,12 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine6_state) + soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + case (bankmachine6_state) 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -9047,8 +9309,8 @@ always @(*) begin if (soc_litedramcore_bankmachine6_row_opened) begin if (soc_litedramcore_bankmachine6_row_hit) begin if (soc_litedramcore_bankmachine6_source_source_payload_we) begin + soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; end else begin - soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9138,60 +9400,60 @@ assign soc_litedramcore_bankmachine7_source_source_last = soc_litedramcore_bankm assign soc_litedramcore_bankmachine7_source_source_payload_we = soc_litedramcore_bankmachine7_pipe_valid_source_payload_we; assign soc_litedramcore_bankmachine7_source_source_payload_addr = soc_litedramcore_bankmachine7_pipe_valid_source_payload_addr; always @(*) begin - litedramcore_bankmachine7_next_state <= 4'd0; - litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state; - case (litedramcore_bankmachine7_state) + bankmachine7_next_state <= 4'd0; + bankmachine7_next_state <= bankmachine7_state; + case (bankmachine7_state) 1'd1: begin if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin if (soc_litedramcore_bankmachine7_cmd_ready) begin - litedramcore_bankmachine7_next_state <= 3'd5; + bankmachine7_next_state <= 3'd5; end end end 2'd2: begin if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_next_state <= 3'd5; + bankmachine7_next_state <= 3'd5; end end 2'd3: begin if (soc_litedramcore_bankmachine7_trccon_ready) begin if (soc_litedramcore_bankmachine7_cmd_ready) begin - litedramcore_bankmachine7_next_state <= 3'd7; + bankmachine7_next_state <= 3'd7; end end end 3'd4: begin if ((~soc_litedramcore_bankmachine7_refresh_req)) begin - litedramcore_bankmachine7_next_state <= 1'd0; + bankmachine7_next_state <= 1'd0; end end 3'd5: begin - litedramcore_bankmachine7_next_state <= 3'd6; + bankmachine7_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine7_next_state <= 2'd3; + bankmachine7_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine7_next_state <= 4'd8; + bankmachine7_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine7_next_state <= 1'd0; + bankmachine7_next_state <= 1'd0; end default: begin if (soc_litedramcore_bankmachine7_refresh_req) begin - litedramcore_bankmachine7_next_state <= 3'd4; + bankmachine7_next_state <= 3'd4; end else begin if (soc_litedramcore_bankmachine7_source_source_valid) begin if (soc_litedramcore_bankmachine7_row_opened) begin if (soc_litedramcore_bankmachine7_row_hit) begin if ((soc_litedramcore_bankmachine7_cmd_ready & soc_litedramcore_bankmachine7_auto_precharge)) begin - litedramcore_bankmachine7_next_state <= 2'd2; + bankmachine7_next_state <= 2'd2; end end else begin - litedramcore_bankmachine7_next_state <= 1'd1; + bankmachine7_next_state <= 1'd1; end end else begin - litedramcore_bankmachine7_next_state <= 2'd3; + bankmachine7_next_state <= 2'd3; end end end @@ -9199,18 +9461,56 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine7_row_open <= 1'd0; - case (litedramcore_bankmachine7_state) + soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_row_open <= 1'd1; + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_source_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_source_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready; + end + end else begin + end + end else begin + end + end end end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end 3'd4: begin + if (soc_litedramcore_bankmachine7_twtpcon_ready) begin + soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9226,7 +9526,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine7_cmd_valid <= 1'd0; - case (litedramcore_bankmachine7_state) + case (bankmachine7_state) 1'd1: begin if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; @@ -9267,7 +9567,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine7_row_close <= 1'd0; - case (litedramcore_bankmachine7_state) + case (bankmachine7_state) 1'd1: begin soc_litedramcore_bankmachine7_row_close <= 1'd1; end @@ -9292,18 +9592,18 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine7_state) + soc_litedramcore_bankmachine7_row_open <= 1'd0; + case (bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_row_open <= 1'd1; + end end 3'd4: begin - if (soc_litedramcore_bankmachine7_twtpcon_ready) begin - soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -9319,7 +9619,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine7_state) + case (bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -9345,7 +9645,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine7_state) + case (bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -9380,7 +9680,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine7_state) + case (bankmachine7_state) 1'd1: begin if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; @@ -9409,7 +9709,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine7_state) + case (bankmachine7_state) 1'd1: begin if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; @@ -9450,7 +9750,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine7_state) + case (bankmachine7_state) 1'd1: begin if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; @@ -9480,7 +9780,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine7_state) + case (bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -9518,7 +9818,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine7_state) + case (bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -9556,7 +9856,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine7_state) + case (bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -9592,44 +9892,6 @@ always @(*) begin end endcase end -always @(*) begin - soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine7_source_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_source_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end assign soc_litedramcore_trrdcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))); assign soc_litedramcore_tfawcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))); assign soc_litedramcore_ras_allowed = (soc_litedramcore_trrdcon_ready & soc_litedramcore_tfawcon_ready); @@ -9670,28 +9932,28 @@ always @(*) begin soc_litedramcore_choose_cmd_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); end assign soc_litedramcore_choose_cmd_request = soc_litedramcore_choose_cmd_valids; -assign soc_litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0; -assign soc_litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1; -assign soc_litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2; -assign soc_litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; -assign soc_litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; -assign soc_litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; +assign soc_litedramcore_choose_cmd_cmd_valid = rhs_self0; +assign soc_litedramcore_choose_cmd_cmd_payload_a = rhs_self1; +assign soc_litedramcore_choose_cmd_cmd_payload_ba = rhs_self2; +assign soc_litedramcore_choose_cmd_cmd_payload_is_read = rhs_self3; +assign soc_litedramcore_choose_cmd_cmd_payload_is_write = rhs_self4; +assign soc_litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_self5; always @(*) begin soc_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; if (soc_litedramcore_choose_cmd_cmd_valid) begin - soc_litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; + soc_litedramcore_choose_cmd_cmd_payload_cas <= t_self0; end end always @(*) begin soc_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; if (soc_litedramcore_choose_cmd_cmd_valid) begin - soc_litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; + soc_litedramcore_choose_cmd_cmd_payload_ras <= t_self1; end end always @(*) begin soc_litedramcore_choose_cmd_cmd_payload_we <= 1'd0; if (soc_litedramcore_choose_cmd_cmd_valid) begin - soc_litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; + soc_litedramcore_choose_cmd_cmd_payload_we <= t_self2; end end always @(*) begin @@ -9779,104 +10041,104 @@ always @(*) begin soc_litedramcore_choose_req_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); end assign soc_litedramcore_choose_req_request = soc_litedramcore_choose_req_valids; -assign soc_litedramcore_choose_req_cmd_valid = rhs_array_muxed6; -assign soc_litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7; -assign soc_litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8; -assign soc_litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9; -assign soc_litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; -assign soc_litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; +assign soc_litedramcore_choose_req_cmd_valid = rhs_self6; +assign soc_litedramcore_choose_req_cmd_payload_a = rhs_self7; +assign soc_litedramcore_choose_req_cmd_payload_ba = rhs_self8; +assign soc_litedramcore_choose_req_cmd_payload_is_read = rhs_self9; +assign soc_litedramcore_choose_req_cmd_payload_is_write = rhs_self10; +assign soc_litedramcore_choose_req_cmd_payload_is_cmd = rhs_self11; always @(*) begin soc_litedramcore_choose_req_cmd_payload_cas <= 1'd0; if (soc_litedramcore_choose_req_cmd_valid) begin - soc_litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; + soc_litedramcore_choose_req_cmd_payload_cas <= t_self3; end end always @(*) begin soc_litedramcore_choose_req_cmd_payload_ras <= 1'd0; if (soc_litedramcore_choose_req_cmd_valid) begin - soc_litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; + soc_litedramcore_choose_req_cmd_payload_ras <= t_self4; end end always @(*) begin soc_litedramcore_choose_req_cmd_payload_we <= 1'd0; if (soc_litedramcore_choose_req_cmd_valid) begin - soc_litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; + soc_litedramcore_choose_req_cmd_payload_we <= t_self5; end end assign soc_litedramcore_choose_req_ce = (soc_litedramcore_choose_req_cmd_ready | (~soc_litedramcore_choose_req_cmd_valid)); assign soc_litedramcore_dfi_p0_reset_n = 1'd1; -assign soc_litedramcore_dfi_p0_cke = {1{soc_litedramcore_steerer0}}; -assign soc_litedramcore_dfi_p0_odt = {1{soc_litedramcore_steerer1}}; +assign soc_litedramcore_dfi_p0_cke = {1{soc_litedramcore_steerer4}}; +assign soc_litedramcore_dfi_p0_odt = {1{soc_litedramcore_steerer5}}; assign soc_litedramcore_dfi_p1_reset_n = 1'd1; -assign soc_litedramcore_dfi_p1_cke = {1{soc_litedramcore_steerer2}}; -assign soc_litedramcore_dfi_p1_odt = {1{soc_litedramcore_steerer3}}; +assign soc_litedramcore_dfi_p1_cke = {1{soc_litedramcore_steerer6}}; +assign soc_litedramcore_dfi_p1_odt = {1{soc_litedramcore_steerer7}}; assign soc_litedramcore_dfi_p2_reset_n = 1'd1; -assign soc_litedramcore_dfi_p2_cke = {1{soc_litedramcore_steerer4}}; -assign soc_litedramcore_dfi_p2_odt = {1{soc_litedramcore_steerer5}}; +assign soc_litedramcore_dfi_p2_cke = {1{soc_litedramcore_steerer8}}; +assign soc_litedramcore_dfi_p2_odt = {1{soc_litedramcore_steerer9}}; assign soc_litedramcore_dfi_p3_reset_n = 1'd1; -assign soc_litedramcore_dfi_p3_cke = {1{soc_litedramcore_steerer6}}; -assign soc_litedramcore_dfi_p3_odt = {1{soc_litedramcore_steerer7}}; +assign soc_litedramcore_dfi_p3_cke = {1{soc_litedramcore_steerer10}}; +assign soc_litedramcore_dfi_p3_odt = {1{soc_litedramcore_steerer11}}; assign soc_litedramcore_tfawcon_count = ((((soc_litedramcore_tfawcon_window[0] + soc_litedramcore_tfawcon_window[1]) + soc_litedramcore_tfawcon_window[2]) + soc_litedramcore_tfawcon_window[3]) + soc_litedramcore_tfawcon_window[4]); always @(*) begin - litedramcore_multiplexer_next_state <= 4'd0; - litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state; - case (litedramcore_multiplexer_state) + multiplexer_next_state <= 4'd0; + multiplexer_next_state <= multiplexer_state; + case (multiplexer_state) 1'd1: begin if (soc_litedramcore_read_available) begin if (((~soc_litedramcore_write_available) | soc_litedramcore_max_time1)) begin - litedramcore_multiplexer_next_state <= 2'd3; + multiplexer_next_state <= 2'd3; end end if (soc_litedramcore_go_to_refresh) begin - litedramcore_multiplexer_next_state <= 2'd2; + multiplexer_next_state <= 2'd2; end end 2'd2: begin if (soc_litedramcore_cmd_last) begin - litedramcore_multiplexer_next_state <= 1'd0; + multiplexer_next_state <= 1'd0; end end 2'd3: begin if (soc_litedramcore_twtrcon_ready) begin - litedramcore_multiplexer_next_state <= 1'd0; + multiplexer_next_state <= 1'd0; end end 3'd4: begin - litedramcore_multiplexer_next_state <= 3'd5; + multiplexer_next_state <= 3'd5; end 3'd5: begin - litedramcore_multiplexer_next_state <= 3'd6; + multiplexer_next_state <= 3'd6; end 3'd6: begin - litedramcore_multiplexer_next_state <= 3'd7; + multiplexer_next_state <= 3'd7; end 3'd7: begin - litedramcore_multiplexer_next_state <= 4'd8; + multiplexer_next_state <= 4'd8; end 4'd8: begin - litedramcore_multiplexer_next_state <= 4'd9; + multiplexer_next_state <= 4'd9; end 4'd9: begin - litedramcore_multiplexer_next_state <= 4'd10; + multiplexer_next_state <= 4'd10; end 4'd10: begin - litedramcore_multiplexer_next_state <= 1'd1; + multiplexer_next_state <= 1'd1; end default: begin if (soc_litedramcore_write_available) begin if (((~soc_litedramcore_read_available) | soc_litedramcore_max_time0)) begin - litedramcore_multiplexer_next_state <= 3'd4; + multiplexer_next_state <= 3'd4; end end if (soc_litedramcore_go_to_refresh) begin - litedramcore_multiplexer_next_state <= 2'd2; + multiplexer_next_state <= 2'd2; end end endcase end always @(*) begin soc_litedramcore_choose_req_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) + case (multiplexer_state) 1'd1: begin if (1'd0) begin soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); @@ -9913,7 +10175,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_en1 <= 1'd0; - case (litedramcore_multiplexer_state) + case (multiplexer_state) 1'd1: begin soc_litedramcore_en1 <= 1'd1; end @@ -9940,19 +10202,18 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_steerer_sel0 <= 2'd0; - case (litedramcore_multiplexer_state) + soc_litedramcore_steerer3 <= 2'd0; + case (multiplexer_state) 1'd1: begin - soc_litedramcore_steerer_sel0 <= 1'd0; - if (1'd0) begin - soc_litedramcore_steerer_sel0 <= 2'd2; + soc_litedramcore_steerer3 <= 1'd0; + if (1'd1) begin + soc_litedramcore_steerer3 <= 2'd2; end if (1'd0) begin - soc_litedramcore_steerer_sel0 <= 1'd1; + soc_litedramcore_steerer3 <= 1'd1; end end 2'd2: begin - soc_litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end @@ -9971,29 +10232,30 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_steerer_sel0 <= 1'd0; + soc_litedramcore_steerer3 <= 1'd0; if (1'd0) begin - soc_litedramcore_steerer_sel0 <= 2'd2; + soc_litedramcore_steerer3 <= 2'd2; end if (1'd0) begin - soc_litedramcore_steerer_sel0 <= 1'd1; + soc_litedramcore_steerer3 <= 1'd1; end end endcase end always @(*) begin - soc_litedramcore_steerer_sel1 <= 2'd0; - case (litedramcore_multiplexer_state) + soc_litedramcore_steerer0 <= 2'd0; + case (multiplexer_state) 1'd1: begin - soc_litedramcore_steerer_sel1 <= 1'd0; + soc_litedramcore_steerer0 <= 1'd0; if (1'd0) begin - soc_litedramcore_steerer_sel1 <= 2'd2; + soc_litedramcore_steerer0 <= 2'd2; end if (1'd0) begin - soc_litedramcore_steerer_sel1 <= 1'd1; + soc_litedramcore_steerer0 <= 1'd1; end end 2'd2: begin + soc_litedramcore_steerer0 <= 2'd3; end 2'd3: begin end @@ -10012,26 +10274,26 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_steerer_sel1 <= 1'd0; + soc_litedramcore_steerer0 <= 1'd0; if (1'd0) begin - soc_litedramcore_steerer_sel1 <= 2'd2; + soc_litedramcore_steerer0 <= 2'd2; end - if (1'd1) begin - soc_litedramcore_steerer_sel1 <= 1'd1; + if (1'd0) begin + soc_litedramcore_steerer0 <= 1'd1; end end endcase end always @(*) begin - soc_litedramcore_steerer_sel2 <= 2'd0; - case (litedramcore_multiplexer_state) + soc_litedramcore_steerer1 <= 2'd0; + case (multiplexer_state) 1'd1: begin - soc_litedramcore_steerer_sel2 <= 1'd0; + soc_litedramcore_steerer1 <= 1'd0; if (1'd0) begin - soc_litedramcore_steerer_sel2 <= 2'd2; + soc_litedramcore_steerer1 <= 2'd2; end - if (1'd1) begin - soc_litedramcore_steerer_sel2 <= 1'd1; + if (1'd0) begin + soc_litedramcore_steerer1 <= 1'd1; end end 2'd2: begin @@ -10053,23 +10315,26 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_steerer_sel2 <= 1'd0; - if (1'd1) begin - soc_litedramcore_steerer_sel2 <= 2'd2; - end + soc_litedramcore_steerer1 <= 1'd0; if (1'd0) begin - soc_litedramcore_steerer_sel2 <= 1'd1; + soc_litedramcore_steerer1 <= 2'd2; + end + if (1'd1) begin + soc_litedramcore_steerer1 <= 1'd1; end end endcase end always @(*) begin - soc_litedramcore_choose_cmd_want_activates <= 1'd0; - case (litedramcore_multiplexer_state) + soc_litedramcore_steerer2 <= 2'd0; + case (multiplexer_state) 1'd1: begin + soc_litedramcore_steerer2 <= 1'd0; if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; + soc_litedramcore_steerer2 <= 2'd2; + end + if (1'd1) begin + soc_litedramcore_steerer2 <= 1'd1; end end 2'd2: begin @@ -10091,23 +10356,23 @@ always @(*) begin 4'd10: begin end default: begin + soc_litedramcore_steerer2 <= 1'd0; + if (1'd1) begin + soc_litedramcore_steerer2 <= 2'd2; + end if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; + soc_litedramcore_steerer2 <= 1'd1; end end endcase end always @(*) begin - soc_litedramcore_steerer_sel3 <= 2'd0; - case (litedramcore_multiplexer_state) + soc_litedramcore_choose_cmd_want_activates <= 1'd0; + case (multiplexer_state) 1'd1: begin - soc_litedramcore_steerer_sel3 <= 1'd0; - if (1'd1) begin - soc_litedramcore_steerer_sel3 <= 2'd2; - end if (1'd0) begin - soc_litedramcore_steerer_sel3 <= 1'd1; + end else begin + soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; end end 2'd2: begin @@ -10129,19 +10394,16 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_steerer_sel3 <= 1'd0; - if (1'd0) begin - soc_litedramcore_steerer_sel3 <= 2'd2; - end if (1'd0) begin - soc_litedramcore_steerer_sel3 <= 1'd1; + end else begin + soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; end end endcase end always @(*) begin soc_litedramcore_en0 <= 1'd0; - case (litedramcore_multiplexer_state) + case (multiplexer_state) 1'd1: begin end 2'd2: begin @@ -10169,7 +10431,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) + case (multiplexer_state) 1'd1: begin end 2'd2: begin @@ -10197,7 +10459,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_choose_cmd_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) + case (multiplexer_state) 1'd1: begin if (1'd0) begin end else begin @@ -10232,7 +10494,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_choose_req_want_reads <= 1'd0; - case (litedramcore_multiplexer_state) + case (multiplexer_state) 1'd1: begin end 2'd2: begin @@ -10260,7 +10522,7 @@ always @(*) begin end always @(*) begin soc_litedramcore_choose_req_want_writes <= 1'd0; - case (litedramcore_multiplexer_state) + case (multiplexer_state) 1'd1: begin soc_litedramcore_choose_req_want_writes <= 1'd1; end @@ -10286,216 +10548,205 @@ always @(*) begin end endcase end -assign litedramcore_roundrobin0_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign litedramcore_roundrobin0_ce = ((~soc_litedramcore_interface_bank0_valid) & (~soc_litedramcore_interface_bank0_lock)); -assign soc_litedramcore_interface_bank0_addr = rhs_array_muxed12; -assign soc_litedramcore_interface_bank0_we = rhs_array_muxed13; -assign soc_litedramcore_interface_bank0_valid = rhs_array_muxed14; -assign litedramcore_roundrobin1_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign litedramcore_roundrobin1_ce = ((~soc_litedramcore_interface_bank1_valid) & (~soc_litedramcore_interface_bank1_lock)); -assign soc_litedramcore_interface_bank1_addr = rhs_array_muxed15; -assign soc_litedramcore_interface_bank1_we = rhs_array_muxed16; -assign soc_litedramcore_interface_bank1_valid = rhs_array_muxed17; -assign litedramcore_roundrobin2_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign litedramcore_roundrobin2_ce = ((~soc_litedramcore_interface_bank2_valid) & (~soc_litedramcore_interface_bank2_lock)); -assign soc_litedramcore_interface_bank2_addr = rhs_array_muxed18; -assign soc_litedramcore_interface_bank2_we = rhs_array_muxed19; -assign soc_litedramcore_interface_bank2_valid = rhs_array_muxed20; -assign litedramcore_roundrobin3_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign litedramcore_roundrobin3_ce = ((~soc_litedramcore_interface_bank3_valid) & (~soc_litedramcore_interface_bank3_lock)); -assign soc_litedramcore_interface_bank3_addr = rhs_array_muxed21; -assign soc_litedramcore_interface_bank3_we = rhs_array_muxed22; -assign soc_litedramcore_interface_bank3_valid = rhs_array_muxed23; -assign litedramcore_roundrobin4_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign litedramcore_roundrobin4_ce = ((~soc_litedramcore_interface_bank4_valid) & (~soc_litedramcore_interface_bank4_lock)); -assign soc_litedramcore_interface_bank4_addr = rhs_array_muxed24; -assign soc_litedramcore_interface_bank4_we = rhs_array_muxed25; -assign soc_litedramcore_interface_bank4_valid = rhs_array_muxed26; -assign litedramcore_roundrobin5_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign litedramcore_roundrobin5_ce = ((~soc_litedramcore_interface_bank5_valid) & (~soc_litedramcore_interface_bank5_lock)); -assign soc_litedramcore_interface_bank5_addr = rhs_array_muxed27; -assign soc_litedramcore_interface_bank5_we = rhs_array_muxed28; -assign soc_litedramcore_interface_bank5_valid = rhs_array_muxed29; -assign litedramcore_roundrobin6_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign litedramcore_roundrobin6_ce = ((~soc_litedramcore_interface_bank6_valid) & (~soc_litedramcore_interface_bank6_lock)); -assign soc_litedramcore_interface_bank6_addr = rhs_array_muxed30; -assign soc_litedramcore_interface_bank6_we = rhs_array_muxed31; -assign soc_litedramcore_interface_bank6_valid = rhs_array_muxed32; -assign litedramcore_roundrobin7_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid)}; -assign litedramcore_roundrobin7_ce = ((~soc_litedramcore_interface_bank7_valid) & (~soc_litedramcore_interface_bank7_lock)); -assign soc_litedramcore_interface_bank7_addr = rhs_array_muxed33; -assign soc_litedramcore_interface_bank7_we = rhs_array_muxed34; -assign soc_litedramcore_interface_bank7_valid = rhs_array_muxed35; -assign soc_user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & soc_litedramcore_interface_bank7_ready)); -assign soc_user_port_wdata_ready = litedramcore_new_master_wdata_ready1; -assign soc_user_port_rdata_valid = litedramcore_new_master_rdata_valid8; +assign roundrobin0_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign roundrobin0_ce = ((~soc_litedramcore_interface_bank0_valid) & (~soc_litedramcore_interface_bank0_lock)); +assign soc_litedramcore_interface_bank0_addr = rhs_self12; +assign soc_litedramcore_interface_bank0_we = rhs_self13; +assign soc_litedramcore_interface_bank0_valid = rhs_self14; +assign roundrobin1_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign roundrobin1_ce = ((~soc_litedramcore_interface_bank1_valid) & (~soc_litedramcore_interface_bank1_lock)); +assign soc_litedramcore_interface_bank1_addr = rhs_self15; +assign soc_litedramcore_interface_bank1_we = rhs_self16; +assign soc_litedramcore_interface_bank1_valid = rhs_self17; +assign roundrobin2_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign roundrobin2_ce = ((~soc_litedramcore_interface_bank2_valid) & (~soc_litedramcore_interface_bank2_lock)); +assign soc_litedramcore_interface_bank2_addr = rhs_self18; +assign soc_litedramcore_interface_bank2_we = rhs_self19; +assign soc_litedramcore_interface_bank2_valid = rhs_self20; +assign roundrobin3_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign roundrobin3_ce = ((~soc_litedramcore_interface_bank3_valid) & (~soc_litedramcore_interface_bank3_lock)); +assign soc_litedramcore_interface_bank3_addr = rhs_self21; +assign soc_litedramcore_interface_bank3_we = rhs_self22; +assign soc_litedramcore_interface_bank3_valid = rhs_self23; +assign roundrobin4_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign roundrobin4_ce = ((~soc_litedramcore_interface_bank4_valid) & (~soc_litedramcore_interface_bank4_lock)); +assign soc_litedramcore_interface_bank4_addr = rhs_self24; +assign soc_litedramcore_interface_bank4_we = rhs_self25; +assign soc_litedramcore_interface_bank4_valid = rhs_self26; +assign roundrobin5_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign roundrobin5_ce = ((~soc_litedramcore_interface_bank5_valid) & (~soc_litedramcore_interface_bank5_lock)); +assign soc_litedramcore_interface_bank5_addr = rhs_self27; +assign soc_litedramcore_interface_bank5_we = rhs_self28; +assign soc_litedramcore_interface_bank5_valid = rhs_self29; +assign roundrobin6_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign roundrobin6_ce = ((~soc_litedramcore_interface_bank6_valid) & (~soc_litedramcore_interface_bank6_lock)); +assign soc_litedramcore_interface_bank6_addr = rhs_self30; +assign soc_litedramcore_interface_bank6_we = rhs_self31; +assign soc_litedramcore_interface_bank6_valid = rhs_self32; +assign roundrobin7_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign roundrobin7_ce = ((~soc_litedramcore_interface_bank7_valid) & (~soc_litedramcore_interface_bank7_lock)); +assign soc_litedramcore_interface_bank7_addr = rhs_self33; +assign soc_litedramcore_interface_bank7_we = rhs_self34; +assign soc_litedramcore_interface_bank7_valid = rhs_self35; +assign soc_user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank0_ready)) | (((roundrobin1_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank1_ready)) | (((roundrobin2_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank2_ready)) | (((roundrobin3_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank3_ready)) | (((roundrobin4_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank4_ready)) | (((roundrobin5_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank5_ready)) | (((roundrobin6_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank6_ready)) | (((roundrobin7_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0)))))) & soc_litedramcore_interface_bank7_ready)); +assign soc_user_port_wdata_ready = new_master_wdata_ready1; +assign soc_user_port_rdata_valid = new_master_rdata_valid8; always @(*) begin - soc_litedramcore_interface_wdata <= 128'd0; - case ({litedramcore_new_master_wdata_ready1}) + soc_litedramcore_interface_wdata_we <= 16'd0; + case ({new_master_wdata_ready1}) 1'd1: begin - soc_litedramcore_interface_wdata <= soc_user_port_wdata_payload_data; + soc_litedramcore_interface_wdata_we <= soc_user_port_wdata_payload_we; end default: begin - soc_litedramcore_interface_wdata <= 1'd0; + soc_litedramcore_interface_wdata_we <= 1'd0; end endcase end always @(*) begin - soc_litedramcore_interface_wdata_we <= 16'd0; - case ({litedramcore_new_master_wdata_ready1}) + soc_litedramcore_interface_wdata <= 128'd0; + case ({new_master_wdata_ready1}) 1'd1: begin - soc_litedramcore_interface_wdata_we <= soc_user_port_wdata_payload_we; + soc_litedramcore_interface_wdata <= soc_user_port_wdata_payload_data; end default: begin - soc_litedramcore_interface_wdata_we <= 1'd0; + soc_litedramcore_interface_wdata <= 1'd0; end endcase end assign soc_user_port_rdata_payload_data = soc_litedramcore_interface_rdata; -assign litedramcore_roundrobin0_grant = 1'd0; -assign litedramcore_roundrobin1_grant = 1'd0; -assign litedramcore_roundrobin2_grant = 1'd0; -assign litedramcore_roundrobin3_grant = 1'd0; -assign litedramcore_roundrobin4_grant = 1'd0; -assign litedramcore_roundrobin5_grant = 1'd0; -assign litedramcore_roundrobin6_grant = 1'd0; -assign litedramcore_roundrobin7_grant = 1'd0; +assign roundrobin0_grant = 1'd0; +assign roundrobin1_grant = 1'd0; +assign roundrobin2_grant = 1'd0; +assign roundrobin3_grant = 1'd0; +assign roundrobin4_grant = 1'd0; +assign roundrobin5_grant = 1'd0; +assign roundrobin6_grant = 1'd0; +assign roundrobin7_grant = 1'd0; always @(*) begin - litedramcore_next_state <= 2'd0; - litedramcore_next_state <= litedramcore_state; - case (litedramcore_state) + next_state <= 2'd0; + next_state <= state; + case (state) 1'd1: begin - litedramcore_next_state <= 2'd2; + next_state <= 2'd2; end 2'd2: begin - litedramcore_next_state <= 1'd0; + next_state <= 1'd0; end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_next_state <= 1'd1; + if ((interface0_cyc & interface0_stb)) begin + next_state <= 1'd1; end end endcase end always @(*) begin - litedramcore_dat_w_next_value0 <= 32'd0; - case (litedramcore_state) + interface1_dat_w_next_value0 <= 32'd0; + case (state) 1'd1: begin end 2'd2: begin end default: begin - litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w; + interface1_dat_w_next_value0 <= interface0_dat_w; end endcase end always @(*) begin - litedramcore_dat_w_next_value_ce0 <= 1'd0; - case (litedramcore_state) + interface1_dat_w_next_value_ce0 <= 1'd0; + case (state) 1'd1: begin end 2'd2: begin end default: begin - litedramcore_dat_w_next_value_ce0 <= 1'd1; + interface1_dat_w_next_value_ce0 <= 1'd1; end endcase end always @(*) begin - litedramcore_wishbone_ack <= 1'd0; - case (litedramcore_state) + interface1_adr_next_value1 <= 14'd0; + case (state) 1'd1: begin + interface1_adr_next_value1 <= 1'd0; end 2'd2: begin - litedramcore_wishbone_ack <= 1'd1; end default: begin + if ((interface0_cyc & interface0_stb)) begin + interface1_adr_next_value1 <= interface0_adr[29:0]; + end end endcase end always @(*) begin - litedramcore_adr_next_value1 <= 14'd0; - case (litedramcore_state) + interface1_adr_next_value_ce1 <= 1'd0; + case (state) 1'd1: begin - litedramcore_adr_next_value1 <= 1'd0; + interface1_adr_next_value_ce1 <= 1'd1; end 2'd2: begin end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value1 <= litedramcore_wishbone_adr; + if ((interface0_cyc & interface0_stb)) begin + interface1_adr_next_value_ce1 <= 1'd1; end end endcase end always @(*) begin - litedramcore_adr_next_value_ce1 <= 1'd0; - case (litedramcore_state) + interface1_we_next_value2 <= 1'd0; + case (state) 1'd1: begin - litedramcore_adr_next_value_ce1 <= 1'd1; + interface1_we_next_value2 <= 1'd0; end 2'd2: begin end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value_ce1 <= 1'd1; + if ((interface0_cyc & interface0_stb)) begin + interface1_we_next_value2 <= (interface0_we & (interface0_sel != 1'd0)); end end endcase end always @(*) begin - litedramcore_we_next_value2 <= 1'd0; - case (litedramcore_state) + interface1_we_next_value_ce2 <= 1'd0; + case (state) 1'd1: begin - litedramcore_we_next_value2 <= 1'd0; + interface1_we_next_value_ce2 <= 1'd1; end 2'd2: begin end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); + if ((interface0_cyc & interface0_stb)) begin + interface1_we_next_value_ce2 <= 1'd1; end end endcase end always @(*) begin - litedramcore_we_next_value_ce2 <= 1'd0; - case (litedramcore_state) + interface0_dat_r <= 32'd0; + case (state) 1'd1: begin - litedramcore_we_next_value_ce2 <= 1'd1; end 2'd2: begin + interface0_dat_r <= interface1_dat_r; end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value_ce2 <= 1'd1; - end end endcase end always @(*) begin - litedramcore_wishbone_dat_r <= 32'd0; - case (litedramcore_state) + interface0_ack <= 1'd0; + case (state) 1'd1: begin end 2'd2: begin - litedramcore_wishbone_dat_r <= litedramcore_dat_r; + interface0_ack <= 1'd1; end default: begin end endcase end -assign litedramcore_wishbone_adr = soc_wb_bus_adr; -assign litedramcore_wishbone_dat_w = soc_wb_bus_dat_w; -assign soc_wb_bus_dat_r = litedramcore_wishbone_dat_r; -assign litedramcore_wishbone_sel = soc_wb_bus_sel; -assign litedramcore_wishbone_cyc = soc_wb_bus_cyc; -assign litedramcore_wishbone_stb = soc_wb_bus_stb; -assign soc_wb_bus_ack = litedramcore_wishbone_ack; -assign litedramcore_wishbone_we = soc_wb_bus_we; -assign litedramcore_wishbone_cti = soc_wb_bus_cti; -assign litedramcore_wishbone_bte = soc_wb_bus_bte; -assign soc_wb_bus_err = litedramcore_wishbone_err; assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; always @(*) begin @@ -10512,15 +10763,15 @@ always @(*) begin end assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_error0_we <= 1'd0; + csrbank0_init_error0_re <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_we <= (~interface0_bank_bus_we); + csrbank0_init_error0_re <= interface0_bank_bus_we; end end always @(*) begin - csrbank0_init_error0_re <= 1'd0; + csrbank0_init_error0_we <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_re <= interface0_bank_bus_we; + csrbank0_init_error0_we <= (~interface0_bank_bus_we); end end assign csrbank0_init_done0_w = soc_init_done_storage; @@ -10528,41 +10779,41 @@ assign csrbank0_init_error0_w = soc_init_error_storage; assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0]; always @(*) begin - csrbank1_dfii_control0_we <= 1'd0; + csrbank1_dfii_control0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_dfii_control0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_control0_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_control0_re <= 1'd0; + csrbank1_dfii_control0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_dfii_control0_re <= interface1_bank_bus_we; + csrbank1_dfii_control0_we <= (~interface1_bank_bus_we); end end -assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0]; +assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[7:0]; always @(*) begin - csrbank1_dfii_pi0_command0_re <= 1'd0; + csrbank1_dfii_pi0_command0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dfii_pi0_command0_re <= interface1_bank_bus_we; + csrbank1_dfii_pi0_command0_we <= (~interface1_bank_bus_we); end end always @(*) begin - csrbank1_dfii_pi0_command0_we <= 1'd0; + csrbank1_dfii_pi0_command0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dfii_pi0_command0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi0_command0_re <= interface1_bank_bus_we; end end assign soc_litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0]; always @(*) begin - soc_litedramcore_phaseinjector0_command_issue_we <= 1'd0; + soc_litedramcore_phaseinjector0_command_issue_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - soc_litedramcore_phaseinjector0_command_issue_we <= (~interface1_bank_bus_we); + soc_litedramcore_phaseinjector0_command_issue_re <= interface1_bank_bus_we; end end always @(*) begin - soc_litedramcore_phaseinjector0_command_issue_re <= 1'd0; + soc_litedramcore_phaseinjector0_command_issue_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - soc_litedramcore_phaseinjector0_command_issue_re <= interface1_bank_bus_we; + soc_litedramcore_phaseinjector0_command_issue_we <= (~interface1_bank_bus_we); end end assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[13:0]; @@ -10593,31 +10844,31 @@ always @(*) begin end assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[31:0]; always @(*) begin - csrbank1_dfii_pi0_wrdata0_re <= 1'd0; + csrbank1_dfii_pi0_wrdata0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - csrbank1_dfii_pi0_wrdata0_re <= interface1_bank_bus_we; + csrbank1_dfii_pi0_wrdata0_we <= (~interface1_bank_bus_we); end end always @(*) begin - csrbank1_dfii_pi0_wrdata0_we <= 1'd0; + csrbank1_dfii_pi0_wrdata0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - csrbank1_dfii_pi0_wrdata0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi0_wrdata0_re <= interface1_bank_bus_we; end end assign csrbank1_dfii_pi0_rddata_r = interface1_bank_bus_dat_w[31:0]; always @(*) begin - csrbank1_dfii_pi0_rddata_we <= 1'd0; + csrbank1_dfii_pi0_rddata_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - csrbank1_dfii_pi0_rddata_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi0_rddata_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi0_rddata_re <= 1'd0; + csrbank1_dfii_pi0_rddata_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - csrbank1_dfii_pi0_rddata_re <= interface1_bank_bus_we; + csrbank1_dfii_pi0_rddata_we <= (~interface1_bank_bus_we); end end -assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0]; +assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[7:0]; always @(*) begin csrbank1_dfii_pi1_command0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin @@ -10632,41 +10883,41 @@ always @(*) begin end assign soc_litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0]; always @(*) begin - soc_litedramcore_phaseinjector1_command_issue_re <= 1'd0; + soc_litedramcore_phaseinjector1_command_issue_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - soc_litedramcore_phaseinjector1_command_issue_re <= interface1_bank_bus_we; + soc_litedramcore_phaseinjector1_command_issue_we <= (~interface1_bank_bus_we); end end always @(*) begin - soc_litedramcore_phaseinjector1_command_issue_we <= 1'd0; + soc_litedramcore_phaseinjector1_command_issue_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - soc_litedramcore_phaseinjector1_command_issue_we <= (~interface1_bank_bus_we); + soc_litedramcore_phaseinjector1_command_issue_re <= interface1_bank_bus_we; end end assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[13:0]; always @(*) begin - csrbank1_dfii_pi1_address0_re <= 1'd0; + csrbank1_dfii_pi1_address0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - csrbank1_dfii_pi1_address0_re <= interface1_bank_bus_we; + csrbank1_dfii_pi1_address0_we <= (~interface1_bank_bus_we); end end always @(*) begin - csrbank1_dfii_pi1_address0_we <= 1'd0; + csrbank1_dfii_pi1_address0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - csrbank1_dfii_pi1_address0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi1_address0_re <= interface1_bank_bus_we; end end assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0]; always @(*) begin - csrbank1_dfii_pi1_baddress0_we <= 1'd0; + csrbank1_dfii_pi1_baddress0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - csrbank1_dfii_pi1_baddress0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi1_baddress0_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi1_baddress0_re <= 1'd0; + csrbank1_dfii_pi1_baddress0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - csrbank1_dfii_pi1_baddress0_re <= interface1_bank_bus_we; + csrbank1_dfii_pi1_baddress0_we <= (~interface1_bank_bus_we); end end assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[31:0]; @@ -10695,17 +10946,17 @@ always @(*) begin csrbank1_dfii_pi1_rddata_we <= (~interface1_bank_bus_we); end end -assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0]; +assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[7:0]; always @(*) begin - csrbank1_dfii_pi2_command0_we <= 1'd0; + csrbank1_dfii_pi2_command0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin - csrbank1_dfii_pi2_command0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi2_command0_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi2_command0_re <= 1'd0; + csrbank1_dfii_pi2_command0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin - csrbank1_dfii_pi2_command0_re <= interface1_bank_bus_we; + csrbank1_dfii_pi2_command0_we <= (~interface1_bank_bus_we); end end assign soc_litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0]; @@ -10749,31 +11000,31 @@ always @(*) begin end assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[31:0]; always @(*) begin - csrbank1_dfii_pi2_wrdata0_we <= 1'd0; + csrbank1_dfii_pi2_wrdata0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin - csrbank1_dfii_pi2_wrdata0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi2_wrdata0_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi2_wrdata0_re <= 1'd0; + csrbank1_dfii_pi2_wrdata0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin - csrbank1_dfii_pi2_wrdata0_re <= interface1_bank_bus_we; + csrbank1_dfii_pi2_wrdata0_we <= (~interface1_bank_bus_we); end end assign csrbank1_dfii_pi2_rddata_r = interface1_bank_bus_dat_w[31:0]; always @(*) begin - csrbank1_dfii_pi2_rddata_re <= 1'd0; + csrbank1_dfii_pi2_rddata_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin - csrbank1_dfii_pi2_rddata_re <= interface1_bank_bus_we; + csrbank1_dfii_pi2_rddata_we <= (~interface1_bank_bus_we); end end always @(*) begin - csrbank1_dfii_pi2_rddata_we <= 1'd0; + csrbank1_dfii_pi2_rddata_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin - csrbank1_dfii_pi2_rddata_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi2_rddata_re <= interface1_bank_bus_we; end end -assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0]; +assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[7:0]; always @(*) begin csrbank1_dfii_pi3_command0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin @@ -10801,28 +11052,28 @@ always @(*) begin end assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[13:0]; always @(*) begin - csrbank1_dfii_pi3_address0_we <= 1'd0; + csrbank1_dfii_pi3_address0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin - csrbank1_dfii_pi3_address0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi3_address0_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi3_address0_re <= 1'd0; + csrbank1_dfii_pi3_address0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin - csrbank1_dfii_pi3_address0_re <= interface1_bank_bus_we; + csrbank1_dfii_pi3_address0_we <= (~interface1_bank_bus_we); end end assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0]; always @(*) begin - csrbank1_dfii_pi3_baddress0_re <= 1'd0; + csrbank1_dfii_pi3_baddress0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin - csrbank1_dfii_pi3_baddress0_re <= interface1_bank_bus_we; + csrbank1_dfii_pi3_baddress0_we <= (~interface1_bank_bus_we); end end always @(*) begin - csrbank1_dfii_pi3_baddress0_we <= 1'd0; + csrbank1_dfii_pi3_baddress0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin - csrbank1_dfii_pi3_baddress0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi3_baddress0_re <= interface1_bank_bus_we; end end assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[31:0]; @@ -10862,7 +11113,9 @@ assign soc_litedramcore_phaseinjector0_csrfield_cas = soc_litedramcore_phaseinje assign soc_litedramcore_phaseinjector0_csrfield_ras = soc_litedramcore_phaseinjector0_command_storage[3]; assign soc_litedramcore_phaseinjector0_csrfield_wren = soc_litedramcore_phaseinjector0_command_storage[4]; assign soc_litedramcore_phaseinjector0_csrfield_rden = soc_litedramcore_phaseinjector0_command_storage[5]; -assign csrbank1_dfii_pi0_command0_w = soc_litedramcore_phaseinjector0_command_storage[5:0]; +assign soc_litedramcore_phaseinjector0_csrfield_cs_top = soc_litedramcore_phaseinjector0_command_storage[6]; +assign soc_litedramcore_phaseinjector0_csrfield_cs_bottom = soc_litedramcore_phaseinjector0_command_storage[7]; +assign csrbank1_dfii_pi0_command0_w = soc_litedramcore_phaseinjector0_command_storage[7:0]; assign csrbank1_dfii_pi0_address0_w = soc_litedramcore_phaseinjector0_address_storage[13:0]; assign csrbank1_dfii_pi0_baddress0_w = soc_litedramcore_phaseinjector0_baddress_storage[2:0]; assign csrbank1_dfii_pi0_wrdata0_w = soc_litedramcore_phaseinjector0_wrdata_storage[31:0]; @@ -10874,7 +11127,9 @@ assign soc_litedramcore_phaseinjector1_csrfield_cas = soc_litedramcore_phaseinje assign soc_litedramcore_phaseinjector1_csrfield_ras = soc_litedramcore_phaseinjector1_command_storage[3]; assign soc_litedramcore_phaseinjector1_csrfield_wren = soc_litedramcore_phaseinjector1_command_storage[4]; assign soc_litedramcore_phaseinjector1_csrfield_rden = soc_litedramcore_phaseinjector1_command_storage[5]; -assign csrbank1_dfii_pi1_command0_w = soc_litedramcore_phaseinjector1_command_storage[5:0]; +assign soc_litedramcore_phaseinjector1_csrfield_cs_top = soc_litedramcore_phaseinjector1_command_storage[6]; +assign soc_litedramcore_phaseinjector1_csrfield_cs_bottom = soc_litedramcore_phaseinjector1_command_storage[7]; +assign csrbank1_dfii_pi1_command0_w = soc_litedramcore_phaseinjector1_command_storage[7:0]; assign csrbank1_dfii_pi1_address0_w = soc_litedramcore_phaseinjector1_address_storage[13:0]; assign csrbank1_dfii_pi1_baddress0_w = soc_litedramcore_phaseinjector1_baddress_storage[2:0]; assign csrbank1_dfii_pi1_wrdata0_w = soc_litedramcore_phaseinjector1_wrdata_storage[31:0]; @@ -10886,7 +11141,9 @@ assign soc_litedramcore_phaseinjector2_csrfield_cas = soc_litedramcore_phaseinje assign soc_litedramcore_phaseinjector2_csrfield_ras = soc_litedramcore_phaseinjector2_command_storage[3]; assign soc_litedramcore_phaseinjector2_csrfield_wren = soc_litedramcore_phaseinjector2_command_storage[4]; assign soc_litedramcore_phaseinjector2_csrfield_rden = soc_litedramcore_phaseinjector2_command_storage[5]; -assign csrbank1_dfii_pi2_command0_w = soc_litedramcore_phaseinjector2_command_storage[5:0]; +assign soc_litedramcore_phaseinjector2_csrfield_cs_top = soc_litedramcore_phaseinjector2_command_storage[6]; +assign soc_litedramcore_phaseinjector2_csrfield_cs_bottom = soc_litedramcore_phaseinjector2_command_storage[7]; +assign csrbank1_dfii_pi2_command0_w = soc_litedramcore_phaseinjector2_command_storage[7:0]; assign csrbank1_dfii_pi2_address0_w = soc_litedramcore_phaseinjector2_address_storage[13:0]; assign csrbank1_dfii_pi2_baddress0_w = soc_litedramcore_phaseinjector2_baddress_storage[2:0]; assign csrbank1_dfii_pi2_wrdata0_w = soc_litedramcore_phaseinjector2_wrdata_storage[31:0]; @@ -10898,23 +11155,25 @@ assign soc_litedramcore_phaseinjector3_csrfield_cas = soc_litedramcore_phaseinje assign soc_litedramcore_phaseinjector3_csrfield_ras = soc_litedramcore_phaseinjector3_command_storage[3]; assign soc_litedramcore_phaseinjector3_csrfield_wren = soc_litedramcore_phaseinjector3_command_storage[4]; assign soc_litedramcore_phaseinjector3_csrfield_rden = soc_litedramcore_phaseinjector3_command_storage[5]; -assign csrbank1_dfii_pi3_command0_w = soc_litedramcore_phaseinjector3_command_storage[5:0]; +assign soc_litedramcore_phaseinjector3_csrfield_cs_top = soc_litedramcore_phaseinjector3_command_storage[6]; +assign soc_litedramcore_phaseinjector3_csrfield_cs_bottom = soc_litedramcore_phaseinjector3_command_storage[7]; +assign csrbank1_dfii_pi3_command0_w = soc_litedramcore_phaseinjector3_command_storage[7:0]; assign csrbank1_dfii_pi3_address0_w = soc_litedramcore_phaseinjector3_address_storage[13:0]; assign csrbank1_dfii_pi3_baddress0_w = soc_litedramcore_phaseinjector3_baddress_storage[2:0]; assign csrbank1_dfii_pi3_wrdata0_w = soc_litedramcore_phaseinjector3_wrdata_storage[31:0]; assign csrbank1_dfii_pi3_rddata_w = soc_litedramcore_phaseinjector3_rddata_status[31:0]; assign soc_litedramcore_phaseinjector3_rddata_we = csrbank1_dfii_pi3_rddata_we; -assign csr_interconnect_adr = litedramcore_adr; -assign csr_interconnect_we = litedramcore_we; -assign csr_interconnect_dat_w = litedramcore_dat_w; -assign litedramcore_dat_r = csr_interconnect_dat_r; -assign interface0_bank_bus_adr = csr_interconnect_adr; -assign interface1_bank_bus_adr = csr_interconnect_adr; -assign interface0_bank_bus_we = csr_interconnect_we; -assign interface1_bank_bus_we = csr_interconnect_we; -assign interface0_bank_bus_dat_w = csr_interconnect_dat_w; -assign interface1_bank_bus_dat_w = csr_interconnect_dat_w; -assign csr_interconnect_dat_r = (interface0_bank_bus_dat_r | interface1_bank_bus_dat_r); +assign adr = interface1_adr; +assign we = interface1_we; +assign dat_w = interface1_dat_w; +assign interface1_dat_r = dat_r; +assign interface0_bank_bus_adr = adr; +assign interface1_bank_bus_adr = adr; +assign interface0_bank_bus_we = we; +assign interface1_bank_bus_we = we; +assign interface0_bank_bus_dat_w = dat_w; +assign interface1_bank_bus_dat_w = dat_w; +assign dat_r = (interface0_bank_bus_dat_r | interface1_bank_bus_dat_r); assign slice_proxy0 = ((soc_ddrphy_bankmodel0_row * 11'd1024) | soc_ddrphy_bankmodel0_write_col); assign slice_proxy1 = ((soc_ddrphy_bankmodel0_row * 11'd1024) | soc_ddrphy_bankmodel0_read_col); assign slice_proxy2 = ((soc_ddrphy_bankmodel1_row * 11'd1024) | soc_ddrphy_bankmodel1_write_col); @@ -10932,1192 +11191,1192 @@ assign slice_proxy13 = ((soc_ddrphy_bankmodel6_row * 11'd1024) | soc_ddrphy_bank assign slice_proxy14 = ((soc_ddrphy_bankmodel7_row * 11'd1024) | soc_ddrphy_bankmodel7_write_col); assign slice_proxy15 = ((soc_ddrphy_bankmodel7_row * 11'd1024) | soc_ddrphy_bankmodel7_read_col); always @(*) begin - rhs_array_muxed0 <= 1'd0; + rhs_self0 <= 1'd0; case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[0]; + rhs_self0 <= soc_litedramcore_choose_cmd_valids[0]; end 1'd1: begin - rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[1]; + rhs_self0 <= soc_litedramcore_choose_cmd_valids[1]; end 2'd2: begin - rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[2]; + rhs_self0 <= soc_litedramcore_choose_cmd_valids[2]; end 2'd3: begin - rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[3]; + rhs_self0 <= soc_litedramcore_choose_cmd_valids[3]; end 3'd4: begin - rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[4]; + rhs_self0 <= soc_litedramcore_choose_cmd_valids[4]; end 3'd5: begin - rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[5]; + rhs_self0 <= soc_litedramcore_choose_cmd_valids[5]; end 3'd6: begin - rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[6]; + rhs_self0 <= soc_litedramcore_choose_cmd_valids[6]; end default: begin - rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[7]; + rhs_self0 <= soc_litedramcore_choose_cmd_valids[7]; end endcase end always @(*) begin - rhs_array_muxed1 <= 14'd0; + rhs_self1 <= 14'd0; case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_a; + rhs_self1 <= soc_litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - rhs_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_a; + rhs_self1 <= soc_litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - rhs_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_a; + rhs_self1 <= soc_litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - rhs_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_a; + rhs_self1 <= soc_litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - rhs_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_a; + rhs_self1 <= soc_litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - rhs_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_a; + rhs_self1 <= soc_litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - rhs_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_a; + rhs_self1 <= soc_litedramcore_bankmachine6_cmd_payload_a; end default: begin - rhs_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_a; + rhs_self1 <= soc_litedramcore_bankmachine7_cmd_payload_a; end endcase end always @(*) begin - rhs_array_muxed2 <= 3'd0; + rhs_self2 <= 3'd0; case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_ba; + rhs_self2 <= soc_litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - rhs_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_ba; + rhs_self2 <= soc_litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - rhs_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_ba; + rhs_self2 <= soc_litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - rhs_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_ba; + rhs_self2 <= soc_litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - rhs_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_ba; + rhs_self2 <= soc_litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - rhs_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_ba; + rhs_self2 <= soc_litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - rhs_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_ba; + rhs_self2 <= soc_litedramcore_bankmachine6_cmd_payload_ba; end default: begin - rhs_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_ba; + rhs_self2 <= soc_litedramcore_bankmachine7_cmd_payload_ba; end endcase end always @(*) begin - rhs_array_muxed3 <= 1'd0; + rhs_self3 <= 1'd0; case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_is_read; + rhs_self3 <= soc_litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - rhs_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_is_read; + rhs_self3 <= soc_litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - rhs_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_is_read; + rhs_self3 <= soc_litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - rhs_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_is_read; + rhs_self3 <= soc_litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - rhs_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_is_read; + rhs_self3 <= soc_litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - rhs_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_is_read; + rhs_self3 <= soc_litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - rhs_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_is_read; + rhs_self3 <= soc_litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - rhs_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_is_read; + rhs_self3 <= soc_litedramcore_bankmachine7_cmd_payload_is_read; end endcase end always @(*) begin - rhs_array_muxed4 <= 1'd0; + rhs_self4 <= 1'd0; case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_is_write; + rhs_self4 <= soc_litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - rhs_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_is_write; + rhs_self4 <= soc_litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - rhs_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_is_write; + rhs_self4 <= soc_litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - rhs_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_is_write; + rhs_self4 <= soc_litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - rhs_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_is_write; + rhs_self4 <= soc_litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - rhs_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_is_write; + rhs_self4 <= soc_litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - rhs_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_is_write; + rhs_self4 <= soc_litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - rhs_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_is_write; + rhs_self4 <= soc_litedramcore_bankmachine7_cmd_payload_is_write; end endcase end always @(*) begin - rhs_array_muxed5 <= 1'd0; + rhs_self5 <= 1'd0; case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd; + rhs_self5 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - rhs_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd; + rhs_self5 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - rhs_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd; + rhs_self5 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - rhs_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd; + rhs_self5 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - rhs_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd; + rhs_self5 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - rhs_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd; + rhs_self5 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - rhs_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd; + rhs_self5 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - rhs_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd; + rhs_self5 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase end always @(*) begin - t_array_muxed0 <= 1'd0; + t_self0 <= 1'd0; case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed0 <= soc_litedramcore_bankmachine0_cmd_payload_cas; + t_self0 <= soc_litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - t_array_muxed0 <= soc_litedramcore_bankmachine1_cmd_payload_cas; + t_self0 <= soc_litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - t_array_muxed0 <= soc_litedramcore_bankmachine2_cmd_payload_cas; + t_self0 <= soc_litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - t_array_muxed0 <= soc_litedramcore_bankmachine3_cmd_payload_cas; + t_self0 <= soc_litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - t_array_muxed0 <= soc_litedramcore_bankmachine4_cmd_payload_cas; + t_self0 <= soc_litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - t_array_muxed0 <= soc_litedramcore_bankmachine5_cmd_payload_cas; + t_self0 <= soc_litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - t_array_muxed0 <= soc_litedramcore_bankmachine6_cmd_payload_cas; + t_self0 <= soc_litedramcore_bankmachine6_cmd_payload_cas; end default: begin - t_array_muxed0 <= soc_litedramcore_bankmachine7_cmd_payload_cas; + t_self0 <= soc_litedramcore_bankmachine7_cmd_payload_cas; end endcase end always @(*) begin - t_array_muxed1 <= 1'd0; + t_self1 <= 1'd0; case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_ras; + t_self1 <= soc_litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - t_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_ras; + t_self1 <= soc_litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - t_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_ras; + t_self1 <= soc_litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - t_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_ras; + t_self1 <= soc_litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - t_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_ras; + t_self1 <= soc_litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - t_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_ras; + t_self1 <= soc_litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - t_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_ras; + t_self1 <= soc_litedramcore_bankmachine6_cmd_payload_ras; end default: begin - t_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_ras; + t_self1 <= soc_litedramcore_bankmachine7_cmd_payload_ras; end endcase end always @(*) begin - t_array_muxed2 <= 1'd0; + t_self2 <= 1'd0; case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_we; + t_self2 <= soc_litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - t_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_we; + t_self2 <= soc_litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - t_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_we; + t_self2 <= soc_litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - t_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_we; + t_self2 <= soc_litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - t_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_we; + t_self2 <= soc_litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - t_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_we; + t_self2 <= soc_litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - t_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_we; + t_self2 <= soc_litedramcore_bankmachine6_cmd_payload_we; end default: begin - t_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_we; + t_self2 <= soc_litedramcore_bankmachine7_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed6 <= 1'd0; + rhs_self6 <= 1'd0; case (soc_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[0]; + rhs_self6 <= soc_litedramcore_choose_req_valids[0]; end 1'd1: begin - rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[1]; + rhs_self6 <= soc_litedramcore_choose_req_valids[1]; end 2'd2: begin - rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[2]; + rhs_self6 <= soc_litedramcore_choose_req_valids[2]; end 2'd3: begin - rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[3]; + rhs_self6 <= soc_litedramcore_choose_req_valids[3]; end 3'd4: begin - rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[4]; + rhs_self6 <= soc_litedramcore_choose_req_valids[4]; end 3'd5: begin - rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[5]; + rhs_self6 <= soc_litedramcore_choose_req_valids[5]; end 3'd6: begin - rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[6]; + rhs_self6 <= soc_litedramcore_choose_req_valids[6]; end default: begin - rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[7]; + rhs_self6 <= soc_litedramcore_choose_req_valids[7]; end endcase end always @(*) begin - rhs_array_muxed7 <= 14'd0; + rhs_self7 <= 14'd0; case (soc_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed7 <= soc_litedramcore_bankmachine0_cmd_payload_a; + rhs_self7 <= soc_litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - rhs_array_muxed7 <= soc_litedramcore_bankmachine1_cmd_payload_a; + rhs_self7 <= soc_litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - rhs_array_muxed7 <= soc_litedramcore_bankmachine2_cmd_payload_a; + rhs_self7 <= soc_litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - rhs_array_muxed7 <= soc_litedramcore_bankmachine3_cmd_payload_a; + rhs_self7 <= soc_litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - rhs_array_muxed7 <= soc_litedramcore_bankmachine4_cmd_payload_a; + rhs_self7 <= soc_litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - rhs_array_muxed7 <= soc_litedramcore_bankmachine5_cmd_payload_a; + rhs_self7 <= soc_litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - rhs_array_muxed7 <= soc_litedramcore_bankmachine6_cmd_payload_a; + rhs_self7 <= soc_litedramcore_bankmachine6_cmd_payload_a; end default: begin - rhs_array_muxed7 <= soc_litedramcore_bankmachine7_cmd_payload_a; + rhs_self7 <= soc_litedramcore_bankmachine7_cmd_payload_a; end endcase end always @(*) begin - rhs_array_muxed8 <= 3'd0; + rhs_self8 <= 3'd0; case (soc_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed8 <= soc_litedramcore_bankmachine0_cmd_payload_ba; + rhs_self8 <= soc_litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - rhs_array_muxed8 <= soc_litedramcore_bankmachine1_cmd_payload_ba; + rhs_self8 <= soc_litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - rhs_array_muxed8 <= soc_litedramcore_bankmachine2_cmd_payload_ba; + rhs_self8 <= soc_litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - rhs_array_muxed8 <= soc_litedramcore_bankmachine3_cmd_payload_ba; + rhs_self8 <= soc_litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - rhs_array_muxed8 <= soc_litedramcore_bankmachine4_cmd_payload_ba; + rhs_self8 <= soc_litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - rhs_array_muxed8 <= soc_litedramcore_bankmachine5_cmd_payload_ba; + rhs_self8 <= soc_litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - rhs_array_muxed8 <= soc_litedramcore_bankmachine6_cmd_payload_ba; + rhs_self8 <= soc_litedramcore_bankmachine6_cmd_payload_ba; end default: begin - rhs_array_muxed8 <= soc_litedramcore_bankmachine7_cmd_payload_ba; + rhs_self8 <= soc_litedramcore_bankmachine7_cmd_payload_ba; end endcase end always @(*) begin - rhs_array_muxed9 <= 1'd0; + rhs_self9 <= 1'd0; case (soc_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed9 <= soc_litedramcore_bankmachine0_cmd_payload_is_read; + rhs_self9 <= soc_litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - rhs_array_muxed9 <= soc_litedramcore_bankmachine1_cmd_payload_is_read; + rhs_self9 <= soc_litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - rhs_array_muxed9 <= soc_litedramcore_bankmachine2_cmd_payload_is_read; + rhs_self9 <= soc_litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - rhs_array_muxed9 <= soc_litedramcore_bankmachine3_cmd_payload_is_read; + rhs_self9 <= soc_litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - rhs_array_muxed9 <= soc_litedramcore_bankmachine4_cmd_payload_is_read; + rhs_self9 <= soc_litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - rhs_array_muxed9 <= soc_litedramcore_bankmachine5_cmd_payload_is_read; + rhs_self9 <= soc_litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - rhs_array_muxed9 <= soc_litedramcore_bankmachine6_cmd_payload_is_read; + rhs_self9 <= soc_litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - rhs_array_muxed9 <= soc_litedramcore_bankmachine7_cmd_payload_is_read; + rhs_self9 <= soc_litedramcore_bankmachine7_cmd_payload_is_read; end endcase end always @(*) begin - rhs_array_muxed10 <= 1'd0; + rhs_self10 <= 1'd0; case (soc_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed10 <= soc_litedramcore_bankmachine0_cmd_payload_is_write; + rhs_self10 <= soc_litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - rhs_array_muxed10 <= soc_litedramcore_bankmachine1_cmd_payload_is_write; + rhs_self10 <= soc_litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - rhs_array_muxed10 <= soc_litedramcore_bankmachine2_cmd_payload_is_write; + rhs_self10 <= soc_litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - rhs_array_muxed10 <= soc_litedramcore_bankmachine3_cmd_payload_is_write; + rhs_self10 <= soc_litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - rhs_array_muxed10 <= soc_litedramcore_bankmachine4_cmd_payload_is_write; + rhs_self10 <= soc_litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - rhs_array_muxed10 <= soc_litedramcore_bankmachine5_cmd_payload_is_write; + rhs_self10 <= soc_litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - rhs_array_muxed10 <= soc_litedramcore_bankmachine6_cmd_payload_is_write; + rhs_self10 <= soc_litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - rhs_array_muxed10 <= soc_litedramcore_bankmachine7_cmd_payload_is_write; + rhs_self10 <= soc_litedramcore_bankmachine7_cmd_payload_is_write; end endcase end always @(*) begin - rhs_array_muxed11 <= 1'd0; + rhs_self11 <= 1'd0; case (soc_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed11 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd; + rhs_self11 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - rhs_array_muxed11 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd; + rhs_self11 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - rhs_array_muxed11 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd; + rhs_self11 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - rhs_array_muxed11 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd; + rhs_self11 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - rhs_array_muxed11 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd; + rhs_self11 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - rhs_array_muxed11 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd; + rhs_self11 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - rhs_array_muxed11 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd; + rhs_self11 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - rhs_array_muxed11 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd; + rhs_self11 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase end always @(*) begin - t_array_muxed3 <= 1'd0; + t_self3 <= 1'd0; case (soc_litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_cas; + t_self3 <= soc_litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - t_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_cas; + t_self3 <= soc_litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - t_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_cas; + t_self3 <= soc_litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - t_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_cas; + t_self3 <= soc_litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - t_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_cas; + t_self3 <= soc_litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - t_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_cas; + t_self3 <= soc_litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - t_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_cas; + t_self3 <= soc_litedramcore_bankmachine6_cmd_payload_cas; end default: begin - t_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_cas; + t_self3 <= soc_litedramcore_bankmachine7_cmd_payload_cas; end endcase end always @(*) begin - t_array_muxed4 <= 1'd0; + t_self4 <= 1'd0; case (soc_litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_ras; + t_self4 <= soc_litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - t_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_ras; + t_self4 <= soc_litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - t_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_ras; + t_self4 <= soc_litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - t_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_ras; + t_self4 <= soc_litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - t_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_ras; + t_self4 <= soc_litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - t_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_ras; + t_self4 <= soc_litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - t_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_ras; + t_self4 <= soc_litedramcore_bankmachine6_cmd_payload_ras; end default: begin - t_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_ras; + t_self4 <= soc_litedramcore_bankmachine7_cmd_payload_ras; end endcase end always @(*) begin - t_array_muxed5 <= 1'd0; + t_self5 <= 1'd0; case (soc_litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_we; + t_self5 <= soc_litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - t_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_we; + t_self5 <= soc_litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - t_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_we; + t_self5 <= soc_litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - t_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_we; + t_self5 <= soc_litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - t_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_we; + t_self5 <= soc_litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - t_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_we; + t_self5 <= soc_litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - t_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_we; + t_self5 <= soc_litedramcore_bankmachine6_cmd_payload_we; end default: begin - t_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_we; + t_self5 <= soc_litedramcore_bankmachine7_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed12 <= 21'd0; - case (litedramcore_roundrobin0_grant) + rhs_self12 <= 21'd0; + case (roundrobin0_grant) default: begin - rhs_array_muxed12 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + rhs_self12 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed13 <= 1'd0; - case (litedramcore_roundrobin0_grant) + rhs_self13 <= 1'd0; + case (roundrobin0_grant) default: begin - rhs_array_muxed13 <= soc_user_port_cmd_payload_we; + rhs_self13 <= soc_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed14 <= 1'd0; - case (litedramcore_roundrobin0_grant) + rhs_self14 <= 1'd0; + case (roundrobin0_grant) default: begin - rhs_array_muxed14 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + rhs_self14 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed15 <= 21'd0; - case (litedramcore_roundrobin1_grant) + rhs_self15 <= 21'd0; + case (roundrobin1_grant) default: begin - rhs_array_muxed15 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + rhs_self15 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed16 <= 1'd0; - case (litedramcore_roundrobin1_grant) + rhs_self16 <= 1'd0; + case (roundrobin1_grant) default: begin - rhs_array_muxed16 <= soc_user_port_cmd_payload_we; + rhs_self16 <= soc_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed17 <= 1'd0; - case (litedramcore_roundrobin1_grant) + rhs_self17 <= 1'd0; + case (roundrobin1_grant) default: begin - rhs_array_muxed17 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + rhs_self17 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed18 <= 21'd0; - case (litedramcore_roundrobin2_grant) + rhs_self18 <= 21'd0; + case (roundrobin2_grant) default: begin - rhs_array_muxed18 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + rhs_self18 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed19 <= 1'd0; - case (litedramcore_roundrobin2_grant) + rhs_self19 <= 1'd0; + case (roundrobin2_grant) default: begin - rhs_array_muxed19 <= soc_user_port_cmd_payload_we; + rhs_self19 <= soc_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed20 <= 1'd0; - case (litedramcore_roundrobin2_grant) + rhs_self20 <= 1'd0; + case (roundrobin2_grant) default: begin - rhs_array_muxed20 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + rhs_self20 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed21 <= 21'd0; - case (litedramcore_roundrobin3_grant) + rhs_self21 <= 21'd0; + case (roundrobin3_grant) default: begin - rhs_array_muxed21 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + rhs_self21 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed22 <= 1'd0; - case (litedramcore_roundrobin3_grant) + rhs_self22 <= 1'd0; + case (roundrobin3_grant) default: begin - rhs_array_muxed22 <= soc_user_port_cmd_payload_we; + rhs_self22 <= soc_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed23 <= 1'd0; - case (litedramcore_roundrobin3_grant) + rhs_self23 <= 1'd0; + case (roundrobin3_grant) default: begin - rhs_array_muxed23 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + rhs_self23 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed24 <= 21'd0; - case (litedramcore_roundrobin4_grant) + rhs_self24 <= 21'd0; + case (roundrobin4_grant) default: begin - rhs_array_muxed24 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + rhs_self24 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed25 <= 1'd0; - case (litedramcore_roundrobin4_grant) + rhs_self25 <= 1'd0; + case (roundrobin4_grant) default: begin - rhs_array_muxed25 <= soc_user_port_cmd_payload_we; + rhs_self25 <= soc_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed26 <= 1'd0; - case (litedramcore_roundrobin4_grant) + rhs_self26 <= 1'd0; + case (roundrobin4_grant) default: begin - rhs_array_muxed26 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + rhs_self26 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed27 <= 21'd0; - case (litedramcore_roundrobin5_grant) + rhs_self27 <= 21'd0; + case (roundrobin5_grant) default: begin - rhs_array_muxed27 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + rhs_self27 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed28 <= 1'd0; - case (litedramcore_roundrobin5_grant) + rhs_self28 <= 1'd0; + case (roundrobin5_grant) default: begin - rhs_array_muxed28 <= soc_user_port_cmd_payload_we; + rhs_self28 <= soc_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed29 <= 1'd0; - case (litedramcore_roundrobin5_grant) + rhs_self29 <= 1'd0; + case (roundrobin5_grant) default: begin - rhs_array_muxed29 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + rhs_self29 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed30 <= 21'd0; - case (litedramcore_roundrobin6_grant) + rhs_self30 <= 21'd0; + case (roundrobin6_grant) default: begin - rhs_array_muxed30 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + rhs_self30 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed31 <= 1'd0; - case (litedramcore_roundrobin6_grant) + rhs_self31 <= 1'd0; + case (roundrobin6_grant) default: begin - rhs_array_muxed31 <= soc_user_port_cmd_payload_we; + rhs_self31 <= soc_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed32 <= 1'd0; - case (litedramcore_roundrobin6_grant) + rhs_self32 <= 1'd0; + case (roundrobin6_grant) default: begin - rhs_array_muxed32 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + rhs_self32 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed33 <= 21'd0; - case (litedramcore_roundrobin7_grant) + rhs_self33 <= 21'd0; + case (roundrobin7_grant) default: begin - rhs_array_muxed33 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + rhs_self33 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed34 <= 1'd0; - case (litedramcore_roundrobin7_grant) + rhs_self34 <= 1'd0; + case (roundrobin7_grant) default: begin - rhs_array_muxed34 <= soc_user_port_cmd_payload_we; + rhs_self34 <= soc_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed35 <= 1'd0; - case (litedramcore_roundrobin7_grant) + rhs_self35 <= 1'd0; + case (roundrobin7_grant) default: begin - rhs_array_muxed35 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid); + rhs_self35 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid); end endcase end always @(*) begin - array_muxed0 <= 3'd0; - case (soc_litedramcore_steerer_sel0) + self0 <= 3'd0; + case (soc_litedramcore_steerer0) 1'd0: begin - array_muxed0 <= soc_litedramcore_nop_ba[2:0]; + self0 <= soc_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed0 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + self0 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed0 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + self0 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed0 <= soc_litedramcore_cmd_payload_ba[2:0]; + self0 <= soc_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed1 <= 14'd0; - case (soc_litedramcore_steerer_sel0) + self1 <= 14'd0; + case (soc_litedramcore_steerer0) 1'd0: begin - array_muxed1 <= soc_litedramcore_nop_a; + self1 <= soc_litedramcore_nop_a; end 1'd1: begin - array_muxed1 <= soc_litedramcore_choose_cmd_cmd_payload_a; + self1 <= soc_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed1 <= soc_litedramcore_choose_req_cmd_payload_a; + self1 <= soc_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed1 <= soc_litedramcore_cmd_payload_a; + self1 <= soc_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed2 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + self2 <= 1'd0; + case (soc_litedramcore_steerer0) 1'd0: begin - array_muxed2 <= 1'd0; + self2 <= 1'd0; end 1'd1: begin - array_muxed2 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + self2 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed2 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + self2 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed2 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + self2 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed3 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + self3 <= 1'd0; + case (soc_litedramcore_steerer0) 1'd0: begin - array_muxed3 <= 1'd0; + self3 <= 1'd0; end 1'd1: begin - array_muxed3 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + self3 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed3 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + self3 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed3 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + self3 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed4 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + self4 <= 1'd0; + case (soc_litedramcore_steerer0) 1'd0: begin - array_muxed4 <= 1'd0; + self4 <= 1'd0; end 1'd1: begin - array_muxed4 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + self4 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed4 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + self4 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed4 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + self4 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed5 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + self5 <= 1'd0; + case (soc_litedramcore_steerer0) 1'd0: begin - array_muxed5 <= 1'd0; + self5 <= 1'd0; end 1'd1: begin - array_muxed5 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + self5 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed5 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + self5 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed5 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + self5 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed6 <= 1'd0; - case (soc_litedramcore_steerer_sel0) + self6 <= 1'd0; + case (soc_litedramcore_steerer0) 1'd0: begin - array_muxed6 <= 1'd0; + self6 <= 1'd0; end 1'd1: begin - array_muxed6 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + self6 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed6 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + self6 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed6 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + self6 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); end endcase end always @(*) begin - array_muxed7 <= 3'd0; - case (soc_litedramcore_steerer_sel1) + self7 <= 3'd0; + case (soc_litedramcore_steerer1) 1'd0: begin - array_muxed7 <= soc_litedramcore_nop_ba[2:0]; + self7 <= soc_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed7 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + self7 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed7 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + self7 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed7 <= soc_litedramcore_cmd_payload_ba[2:0]; + self7 <= soc_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed8 <= 14'd0; - case (soc_litedramcore_steerer_sel1) + self8 <= 14'd0; + case (soc_litedramcore_steerer1) 1'd0: begin - array_muxed8 <= soc_litedramcore_nop_a; + self8 <= soc_litedramcore_nop_a; end 1'd1: begin - array_muxed8 <= soc_litedramcore_choose_cmd_cmd_payload_a; + self8 <= soc_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed8 <= soc_litedramcore_choose_req_cmd_payload_a; + self8 <= soc_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed8 <= soc_litedramcore_cmd_payload_a; + self8 <= soc_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed9 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + self9 <= 1'd0; + case (soc_litedramcore_steerer1) 1'd0: begin - array_muxed9 <= 1'd0; + self9 <= 1'd0; end 1'd1: begin - array_muxed9 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + self9 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed9 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + self9 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed9 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + self9 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed10 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + self10 <= 1'd0; + case (soc_litedramcore_steerer1) 1'd0: begin - array_muxed10 <= 1'd0; + self10 <= 1'd0; end 1'd1: begin - array_muxed10 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + self10 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed10 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + self10 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed10 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + self10 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed11 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + self11 <= 1'd0; + case (soc_litedramcore_steerer1) 1'd0: begin - array_muxed11 <= 1'd0; + self11 <= 1'd0; end 1'd1: begin - array_muxed11 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + self11 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed11 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + self11 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed11 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + self11 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed12 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + self12 <= 1'd0; + case (soc_litedramcore_steerer1) 1'd0: begin - array_muxed12 <= 1'd0; + self12 <= 1'd0; end 1'd1: begin - array_muxed12 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + self12 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed12 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + self12 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed12 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + self12 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed13 <= 1'd0; - case (soc_litedramcore_steerer_sel1) + self13 <= 1'd0; + case (soc_litedramcore_steerer1) 1'd0: begin - array_muxed13 <= 1'd0; + self13 <= 1'd0; end 1'd1: begin - array_muxed13 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + self13 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed13 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + self13 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed13 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + self13 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); end endcase end always @(*) begin - array_muxed14 <= 3'd0; - case (soc_litedramcore_steerer_sel2) + self14 <= 3'd0; + case (soc_litedramcore_steerer2) 1'd0: begin - array_muxed14 <= soc_litedramcore_nop_ba[2:0]; + self14 <= soc_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed14 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + self14 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed14 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + self14 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed14 <= soc_litedramcore_cmd_payload_ba[2:0]; + self14 <= soc_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed15 <= 14'd0; - case (soc_litedramcore_steerer_sel2) + self15 <= 14'd0; + case (soc_litedramcore_steerer2) 1'd0: begin - array_muxed15 <= soc_litedramcore_nop_a; + self15 <= soc_litedramcore_nop_a; end 1'd1: begin - array_muxed15 <= soc_litedramcore_choose_cmd_cmd_payload_a; + self15 <= soc_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed15 <= soc_litedramcore_choose_req_cmd_payload_a; + self15 <= soc_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed15 <= soc_litedramcore_cmd_payload_a; + self15 <= soc_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed16 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + self16 <= 1'd0; + case (soc_litedramcore_steerer2) 1'd0: begin - array_muxed16 <= 1'd0; + self16 <= 1'd0; end 1'd1: begin - array_muxed16 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + self16 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed16 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + self16 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed16 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + self16 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed17 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + self17 <= 1'd0; + case (soc_litedramcore_steerer2) 1'd0: begin - array_muxed17 <= 1'd0; + self17 <= 1'd0; end 1'd1: begin - array_muxed17 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + self17 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed17 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + self17 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed17 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + self17 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed18 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + self18 <= 1'd0; + case (soc_litedramcore_steerer2) 1'd0: begin - array_muxed18 <= 1'd0; + self18 <= 1'd0; end 1'd1: begin - array_muxed18 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + self18 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed18 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + self18 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed18 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + self18 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed19 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + self19 <= 1'd0; + case (soc_litedramcore_steerer2) 1'd0: begin - array_muxed19 <= 1'd0; + self19 <= 1'd0; end 1'd1: begin - array_muxed19 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + self19 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed19 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + self19 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed19 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + self19 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed20 <= 1'd0; - case (soc_litedramcore_steerer_sel2) + self20 <= 1'd0; + case (soc_litedramcore_steerer2) 1'd0: begin - array_muxed20 <= 1'd0; + self20 <= 1'd0; end 1'd1: begin - array_muxed20 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + self20 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed20 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + self20 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed20 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + self20 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); end endcase end always @(*) begin - array_muxed21 <= 3'd0; - case (soc_litedramcore_steerer_sel3) + self21 <= 3'd0; + case (soc_litedramcore_steerer3) 1'd0: begin - array_muxed21 <= soc_litedramcore_nop_ba[2:0]; + self21 <= soc_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed21 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + self21 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed21 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + self21 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed21 <= soc_litedramcore_cmd_payload_ba[2:0]; + self21 <= soc_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed22 <= 14'd0; - case (soc_litedramcore_steerer_sel3) + self22 <= 14'd0; + case (soc_litedramcore_steerer3) 1'd0: begin - array_muxed22 <= soc_litedramcore_nop_a; + self22 <= soc_litedramcore_nop_a; end 1'd1: begin - array_muxed22 <= soc_litedramcore_choose_cmd_cmd_payload_a; + self22 <= soc_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed22 <= soc_litedramcore_choose_req_cmd_payload_a; + self22 <= soc_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed22 <= soc_litedramcore_cmd_payload_a; + self22 <= soc_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed23 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + self23 <= 1'd0; + case (soc_litedramcore_steerer3) 1'd0: begin - array_muxed23 <= 1'd0; + self23 <= 1'd0; end 1'd1: begin - array_muxed23 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + self23 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed23 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + self23 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed23 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + self23 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed24 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + self24 <= 1'd0; + case (soc_litedramcore_steerer3) 1'd0: begin - array_muxed24 <= 1'd0; + self24 <= 1'd0; end 1'd1: begin - array_muxed24 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + self24 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed24 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + self24 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed24 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + self24 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed25 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + self25 <= 1'd0; + case (soc_litedramcore_steerer3) 1'd0: begin - array_muxed25 <= 1'd0; + self25 <= 1'd0; end 1'd1: begin - array_muxed25 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + self25 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed25 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + self25 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed25 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + self25 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed26 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + self26 <= 1'd0; + case (soc_litedramcore_steerer3) 1'd0: begin - array_muxed26 <= 1'd0; + self26 <= 1'd0; end 1'd1: begin - array_muxed26 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + self26 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed26 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + self26 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed26 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + self26 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed27 <= 1'd0; - case (soc_litedramcore_steerer_sel3) + self27 <= 1'd0; + case (soc_litedramcore_steerer3) 1'd0: begin - array_muxed27 <= 1'd0; + self27 <= 1'd0; end 1'd1: begin - array_muxed27 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + self27 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed27 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + self27 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed27 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + self27 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); end endcase end @@ -12268,21 +12527,21 @@ always @(posedge sys_clk) begin soc_litedramcore_cmd_payload_ras <= 1'd0; soc_litedramcore_cmd_payload_we <= 1'd0; soc_litedramcore_sequencer_done1 <= 1'd0; - if ((soc_litedramcore_sequencer_start1 & (soc_litedramcore_sequencer_counter == 1'd0))) begin + if ((soc_litedramcore_sequencer_start1 & (soc_litedramcore_sequencer_trigger == 1'd0))) begin soc_litedramcore_cmd_payload_a <= 11'd1024; soc_litedramcore_cmd_payload_ba <= 1'd0; soc_litedramcore_cmd_payload_cas <= 1'd0; soc_litedramcore_cmd_payload_ras <= 1'd1; soc_litedramcore_cmd_payload_we <= 1'd1; end - if ((soc_litedramcore_sequencer_counter == 2'd3)) begin + if ((soc_litedramcore_sequencer_trigger == 2'd3)) begin soc_litedramcore_cmd_payload_a <= 11'd1024; soc_litedramcore_cmd_payload_ba <= 1'd0; soc_litedramcore_cmd_payload_cas <= 1'd1; soc_litedramcore_cmd_payload_ras <= 1'd1; soc_litedramcore_cmd_payload_we <= 1'd0; end - if ((soc_litedramcore_sequencer_counter == 6'd35)) begin + if ((soc_litedramcore_sequencer_trigger == 6'd35)) begin soc_litedramcore_cmd_payload_a <= 1'd0; soc_litedramcore_cmd_payload_ba <= 1'd0; soc_litedramcore_cmd_payload_cas <= 1'd0; @@ -12290,14 +12549,14 @@ always @(posedge sys_clk) begin soc_litedramcore_cmd_payload_we <= 1'd0; soc_litedramcore_sequencer_done1 <= 1'd1; end - if ((soc_litedramcore_sequencer_counter == 6'd35)) begin - soc_litedramcore_sequencer_counter <= 1'd0; + if ((soc_litedramcore_sequencer_trigger == 6'd35)) begin + soc_litedramcore_sequencer_trigger <= 1'd0; end else begin - if ((soc_litedramcore_sequencer_counter != 1'd0)) begin - soc_litedramcore_sequencer_counter <= (soc_litedramcore_sequencer_counter + 1'd1); + if ((soc_litedramcore_sequencer_trigger != 1'd0)) begin + soc_litedramcore_sequencer_trigger <= (soc_litedramcore_sequencer_trigger + 1'd1); end else begin if (soc_litedramcore_sequencer_start1) begin - soc_litedramcore_sequencer_counter <= 1'd1; + soc_litedramcore_sequencer_trigger <= 1'd1; end end end @@ -12307,21 +12566,21 @@ always @(posedge sys_clk) begin soc_litedramcore_zqcs_timer_count1 <= 27'd99999999; end soc_litedramcore_zqcs_executer_done <= 1'd0; - if ((soc_litedramcore_zqcs_executer_start & (soc_litedramcore_zqcs_executer_counter == 1'd0))) begin + if ((soc_litedramcore_zqcs_executer_start & (soc_litedramcore_zqcs_executer_trigger == 1'd0))) begin soc_litedramcore_cmd_payload_a <= 11'd1024; soc_litedramcore_cmd_payload_ba <= 1'd0; soc_litedramcore_cmd_payload_cas <= 1'd0; soc_litedramcore_cmd_payload_ras <= 1'd1; soc_litedramcore_cmd_payload_we <= 1'd1; end - if ((soc_litedramcore_zqcs_executer_counter == 2'd3)) begin + if ((soc_litedramcore_zqcs_executer_trigger == 2'd3)) begin soc_litedramcore_cmd_payload_a <= 1'd0; soc_litedramcore_cmd_payload_ba <= 1'd0; soc_litedramcore_cmd_payload_cas <= 1'd0; soc_litedramcore_cmd_payload_ras <= 1'd0; soc_litedramcore_cmd_payload_we <= 1'd1; end - if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin + if ((soc_litedramcore_zqcs_executer_trigger == 5'd19)) begin soc_litedramcore_cmd_payload_a <= 1'd0; soc_litedramcore_cmd_payload_ba <= 1'd0; soc_litedramcore_cmd_payload_cas <= 1'd0; @@ -12329,18 +12588,18 @@ always @(posedge sys_clk) begin soc_litedramcore_cmd_payload_we <= 1'd0; soc_litedramcore_zqcs_executer_done <= 1'd1; end - if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin - soc_litedramcore_zqcs_executer_counter <= 1'd0; + if ((soc_litedramcore_zqcs_executer_trigger == 5'd19)) begin + soc_litedramcore_zqcs_executer_trigger <= 1'd0; end else begin - if ((soc_litedramcore_zqcs_executer_counter != 1'd0)) begin - soc_litedramcore_zqcs_executer_counter <= (soc_litedramcore_zqcs_executer_counter + 1'd1); + if ((soc_litedramcore_zqcs_executer_trigger != 1'd0)) begin + soc_litedramcore_zqcs_executer_trigger <= (soc_litedramcore_zqcs_executer_trigger + 1'd1); end else begin if (soc_litedramcore_zqcs_executer_start) begin - soc_litedramcore_zqcs_executer_counter <= 1'd1; + soc_litedramcore_zqcs_executer_trigger <= 1'd1; end end end - litedramcore_refresher_state <= litedramcore_refresher_next_state; + refresher_state <= refresher_next_state; if (soc_litedramcore_bankmachine0_row_close) begin soc_litedramcore_bankmachine0_row_opened <= 1'd0; end else begin @@ -12416,7 +12675,7 @@ always @(posedge sys_clk) begin end end end - litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state; + bankmachine0_state <= bankmachine0_next_state; if (soc_litedramcore_bankmachine1_row_close) begin soc_litedramcore_bankmachine1_row_opened <= 1'd0; end else begin @@ -12492,7 +12751,7 @@ always @(posedge sys_clk) begin end end end - litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state; + bankmachine1_state <= bankmachine1_next_state; if (soc_litedramcore_bankmachine2_row_close) begin soc_litedramcore_bankmachine2_row_opened <= 1'd0; end else begin @@ -12568,7 +12827,7 @@ always @(posedge sys_clk) begin end end end - litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state; + bankmachine2_state <= bankmachine2_next_state; if (soc_litedramcore_bankmachine3_row_close) begin soc_litedramcore_bankmachine3_row_opened <= 1'd0; end else begin @@ -12644,7 +12903,7 @@ always @(posedge sys_clk) begin end end end - litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state; + bankmachine3_state <= bankmachine3_next_state; if (soc_litedramcore_bankmachine4_row_close) begin soc_litedramcore_bankmachine4_row_opened <= 1'd0; end else begin @@ -12720,7 +12979,7 @@ always @(posedge sys_clk) begin end end end - litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state; + bankmachine4_state <= bankmachine4_next_state; if (soc_litedramcore_bankmachine5_row_close) begin soc_litedramcore_bankmachine5_row_opened <= 1'd0; end else begin @@ -12796,7 +13055,7 @@ always @(posedge sys_clk) begin end end end - litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state; + bankmachine5_state <= bankmachine5_next_state; if (soc_litedramcore_bankmachine6_row_close) begin soc_litedramcore_bankmachine6_row_opened <= 1'd0; end else begin @@ -12872,7 +13131,7 @@ always @(posedge sys_clk) begin end end end - litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state; + bankmachine6_state <= bankmachine6_next_state; if (soc_litedramcore_bankmachine7_row_close) begin soc_litedramcore_bankmachine7_row_opened <= 1'd0; end else begin @@ -12948,7 +13207,7 @@ always @(posedge sys_clk) begin end end end - litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state; + bankmachine7_state <= bankmachine7_next_state; if ((~soc_litedramcore_en0)) begin soc_litedramcore_time0 <= 5'd31; end else begin @@ -13436,37 +13695,37 @@ always @(posedge sys_clk) begin endcase end soc_litedramcore_dfi_p0_cs_n <= 1'd0; - soc_litedramcore_dfi_p0_bank <= array_muxed0; - soc_litedramcore_dfi_p0_address <= array_muxed1; - soc_litedramcore_dfi_p0_cas_n <= (~array_muxed2); - soc_litedramcore_dfi_p0_ras_n <= (~array_muxed3); - soc_litedramcore_dfi_p0_we_n <= (~array_muxed4); - soc_litedramcore_dfi_p0_rddata_en <= array_muxed5; - soc_litedramcore_dfi_p0_wrdata_en <= array_muxed6; + soc_litedramcore_dfi_p0_bank <= self0; + soc_litedramcore_dfi_p0_address <= self1; + soc_litedramcore_dfi_p0_cas_n <= (~self2); + soc_litedramcore_dfi_p0_ras_n <= (~self3); + soc_litedramcore_dfi_p0_we_n <= (~self4); + soc_litedramcore_dfi_p0_rddata_en <= self5; + soc_litedramcore_dfi_p0_wrdata_en <= self6; soc_litedramcore_dfi_p1_cs_n <= 1'd0; - soc_litedramcore_dfi_p1_bank <= array_muxed7; - soc_litedramcore_dfi_p1_address <= array_muxed8; - soc_litedramcore_dfi_p1_cas_n <= (~array_muxed9); - soc_litedramcore_dfi_p1_ras_n <= (~array_muxed10); - soc_litedramcore_dfi_p1_we_n <= (~array_muxed11); - soc_litedramcore_dfi_p1_rddata_en <= array_muxed12; - soc_litedramcore_dfi_p1_wrdata_en <= array_muxed13; + soc_litedramcore_dfi_p1_bank <= self7; + soc_litedramcore_dfi_p1_address <= self8; + soc_litedramcore_dfi_p1_cas_n <= (~self9); + soc_litedramcore_dfi_p1_ras_n <= (~self10); + soc_litedramcore_dfi_p1_we_n <= (~self11); + soc_litedramcore_dfi_p1_rddata_en <= self12; + soc_litedramcore_dfi_p1_wrdata_en <= self13; soc_litedramcore_dfi_p2_cs_n <= 1'd0; - soc_litedramcore_dfi_p2_bank <= array_muxed14; - soc_litedramcore_dfi_p2_address <= array_muxed15; - soc_litedramcore_dfi_p2_cas_n <= (~array_muxed16); - soc_litedramcore_dfi_p2_ras_n <= (~array_muxed17); - soc_litedramcore_dfi_p2_we_n <= (~array_muxed18); - soc_litedramcore_dfi_p2_rddata_en <= array_muxed19; - soc_litedramcore_dfi_p2_wrdata_en <= array_muxed20; + soc_litedramcore_dfi_p2_bank <= self14; + soc_litedramcore_dfi_p2_address <= self15; + soc_litedramcore_dfi_p2_cas_n <= (~self16); + soc_litedramcore_dfi_p2_ras_n <= (~self17); + soc_litedramcore_dfi_p2_we_n <= (~self18); + soc_litedramcore_dfi_p2_rddata_en <= self19; + soc_litedramcore_dfi_p2_wrdata_en <= self20; soc_litedramcore_dfi_p3_cs_n <= 1'd0; - soc_litedramcore_dfi_p3_bank <= array_muxed21; - soc_litedramcore_dfi_p3_address <= array_muxed22; - soc_litedramcore_dfi_p3_cas_n <= (~array_muxed23); - soc_litedramcore_dfi_p3_ras_n <= (~array_muxed24); - soc_litedramcore_dfi_p3_we_n <= (~array_muxed25); - soc_litedramcore_dfi_p3_rddata_en <= array_muxed26; - soc_litedramcore_dfi_p3_wrdata_en <= array_muxed27; + soc_litedramcore_dfi_p3_bank <= self21; + soc_litedramcore_dfi_p3_address <= self22; + soc_litedramcore_dfi_p3_cas_n <= (~self23); + soc_litedramcore_dfi_p3_ras_n <= (~self24); + soc_litedramcore_dfi_p3_we_n <= (~self25); + soc_litedramcore_dfi_p3_rddata_en <= self26; + soc_litedramcore_dfi_p3_wrdata_en <= self27; if (soc_litedramcore_trrdcon_valid) begin soc_litedramcore_trrdcon_count <= 1'd1; if (1'd0) begin @@ -13520,27 +13779,27 @@ always @(posedge sys_clk) begin end end end - litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state; - litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_wdata_ready)); - litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0; - litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_rdata_valid)); - litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0; - litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1; - litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2; - litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3; - litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4; - litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5; - litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6; - litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7; - litedramcore_state <= litedramcore_next_state; - if (litedramcore_dat_w_next_value_ce0) begin - litedramcore_dat_w <= litedramcore_dat_w_next_value0; + multiplexer_state <= multiplexer_next_state; + new_master_wdata_ready0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_wdata_ready)) | ((roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_wdata_ready)) | ((roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_wdata_ready)) | ((roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_wdata_ready)) | ((roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_wdata_ready)) | ((roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_wdata_ready)) | ((roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_wdata_ready)) | ((roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_wdata_ready)); + new_master_wdata_ready1 <= new_master_wdata_ready0; + new_master_rdata_valid0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_rdata_valid)) | ((roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_rdata_valid)) | ((roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_rdata_valid)) | ((roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_rdata_valid)) | ((roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_rdata_valid)) | ((roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_rdata_valid)) | ((roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_rdata_valid)) | ((roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_rdata_valid)); + new_master_rdata_valid1 <= new_master_rdata_valid0; + new_master_rdata_valid2 <= new_master_rdata_valid1; + new_master_rdata_valid3 <= new_master_rdata_valid2; + new_master_rdata_valid4 <= new_master_rdata_valid3; + new_master_rdata_valid5 <= new_master_rdata_valid4; + new_master_rdata_valid6 <= new_master_rdata_valid5; + new_master_rdata_valid7 <= new_master_rdata_valid6; + new_master_rdata_valid8 <= new_master_rdata_valid7; + state <= next_state; + if (interface1_dat_w_next_value_ce0) begin + interface1_dat_w <= interface1_dat_w_next_value0; end - if (litedramcore_adr_next_value_ce1) begin - litedramcore_adr <= litedramcore_adr_next_value1; + if (interface1_adr_next_value_ce1) begin + interface1_adr <= interface1_adr_next_value1; end - if (litedramcore_we_next_value_ce2) begin - litedramcore_we <= litedramcore_we_next_value2; + if (interface1_we_next_value_ce2) begin + interface1_we <= interface1_we_next_value2; end interface0_bank_bus_dat_r <= 1'd0; if (csrbank0_sel) begin @@ -13646,7 +13905,7 @@ always @(posedge sys_clk) begin end soc_litedramcore_re <= csrbank1_dfii_control0_re; if (csrbank1_dfii_pi0_command0_re) begin - soc_litedramcore_phaseinjector0_command_storage[5:0] <= csrbank1_dfii_pi0_command0_r; + soc_litedramcore_phaseinjector0_command_storage[7:0] <= csrbank1_dfii_pi0_command0_r; end soc_litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re; if (csrbank1_dfii_pi0_address0_re) begin @@ -13663,7 +13922,7 @@ always @(posedge sys_clk) begin soc_litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re; soc_litedramcore_phaseinjector0_rddata_re <= csrbank1_dfii_pi0_rddata_re; if (csrbank1_dfii_pi1_command0_re) begin - soc_litedramcore_phaseinjector1_command_storage[5:0] <= csrbank1_dfii_pi1_command0_r; + soc_litedramcore_phaseinjector1_command_storage[7:0] <= csrbank1_dfii_pi1_command0_r; end soc_litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re; if (csrbank1_dfii_pi1_address0_re) begin @@ -13680,7 +13939,7 @@ always @(posedge sys_clk) begin soc_litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re; soc_litedramcore_phaseinjector1_rddata_re <= csrbank1_dfii_pi1_rddata_re; if (csrbank1_dfii_pi2_command0_re) begin - soc_litedramcore_phaseinjector2_command_storage[5:0] <= csrbank1_dfii_pi2_command0_r; + soc_litedramcore_phaseinjector2_command_storage[7:0] <= csrbank1_dfii_pi2_command0_r; end soc_litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re; if (csrbank1_dfii_pi2_address0_re) begin @@ -13697,7 +13956,7 @@ always @(posedge sys_clk) begin soc_litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re; soc_litedramcore_phaseinjector2_rddata_re <= csrbank1_dfii_pi2_rddata_re; if (csrbank1_dfii_pi3_command0_re) begin - soc_litedramcore_phaseinjector3_command_storage[5:0] <= csrbank1_dfii_pi3_command0_r; + soc_litedramcore_phaseinjector3_command_storage[7:0] <= csrbank1_dfii_pi3_command0_r; end soc_litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re; if (csrbank1_dfii_pi3_address0_re) begin @@ -13764,28 +14023,28 @@ always @(posedge sys_clk) begin soc_ddrphy_new_banks_read_data7 <= 128'd0; soc_litedramcore_storage <= 4'd1; soc_litedramcore_re <= 1'd0; - soc_litedramcore_phaseinjector0_command_storage <= 6'd0; + soc_litedramcore_phaseinjector0_command_storage <= 8'd0; soc_litedramcore_phaseinjector0_command_re <= 1'd0; soc_litedramcore_phaseinjector0_address_re <= 1'd0; soc_litedramcore_phaseinjector0_baddress_re <= 1'd0; soc_litedramcore_phaseinjector0_wrdata_re <= 1'd0; soc_litedramcore_phaseinjector0_rddata_status <= 32'd0; soc_litedramcore_phaseinjector0_rddata_re <= 1'd0; - soc_litedramcore_phaseinjector1_command_storage <= 6'd0; + soc_litedramcore_phaseinjector1_command_storage <= 8'd0; soc_litedramcore_phaseinjector1_command_re <= 1'd0; soc_litedramcore_phaseinjector1_address_re <= 1'd0; soc_litedramcore_phaseinjector1_baddress_re <= 1'd0; soc_litedramcore_phaseinjector1_wrdata_re <= 1'd0; soc_litedramcore_phaseinjector1_rddata_status <= 32'd0; soc_litedramcore_phaseinjector1_rddata_re <= 1'd0; - soc_litedramcore_phaseinjector2_command_storage <= 6'd0; + soc_litedramcore_phaseinjector2_command_storage <= 8'd0; soc_litedramcore_phaseinjector2_command_re <= 1'd0; soc_litedramcore_phaseinjector2_address_re <= 1'd0; soc_litedramcore_phaseinjector2_baddress_re <= 1'd0; soc_litedramcore_phaseinjector2_wrdata_re <= 1'd0; soc_litedramcore_phaseinjector2_rddata_status <= 32'd0; soc_litedramcore_phaseinjector2_rddata_re <= 1'd0; - soc_litedramcore_phaseinjector3_command_storage <= 6'd0; + soc_litedramcore_phaseinjector3_command_storage <= 8'd0; soc_litedramcore_phaseinjector3_command_re <= 1'd0; soc_litedramcore_phaseinjector3_address_re <= 1'd0; soc_litedramcore_phaseinjector3_baddress_re <= 1'd0; @@ -13833,11 +14092,11 @@ always @(posedge sys_clk) begin soc_litedramcore_postponer_req_o <= 1'd0; soc_litedramcore_postponer_count <= 1'd0; soc_litedramcore_sequencer_done1 <= 1'd0; - soc_litedramcore_sequencer_counter <= 6'd0; + soc_litedramcore_sequencer_trigger <= 6'd0; soc_litedramcore_sequencer_count <= 1'd0; soc_litedramcore_zqcs_timer_count1 <= 27'd99999999; soc_litedramcore_zqcs_executer_done <= 1'd0; - soc_litedramcore_zqcs_executer_counter <= 5'd0; + soc_litedramcore_zqcs_executer_trigger <= 5'd0; soc_litedramcore_bankmachine0_level <= 5'd0; soc_litedramcore_bankmachine0_produce <= 4'd0; soc_litedramcore_bankmachine0_consume <= 4'd0; @@ -13966,29 +14225,29 @@ always @(posedge sys_clk) begin soc_init_done_re <= 1'd0; soc_init_error_storage <= 1'd0; soc_init_error_re <= 1'd0; - litedramcore_we <= 1'd0; - litedramcore_refresher_state <= 2'd0; - litedramcore_bankmachine0_state <= 4'd0; - litedramcore_bankmachine1_state <= 4'd0; - litedramcore_bankmachine2_state <= 4'd0; - litedramcore_bankmachine3_state <= 4'd0; - litedramcore_bankmachine4_state <= 4'd0; - litedramcore_bankmachine5_state <= 4'd0; - litedramcore_bankmachine6_state <= 4'd0; - litedramcore_bankmachine7_state <= 4'd0; - litedramcore_multiplexer_state <= 4'd0; - litedramcore_new_master_wdata_ready0 <= 1'd0; - litedramcore_new_master_wdata_ready1 <= 1'd0; - litedramcore_new_master_rdata_valid0 <= 1'd0; - litedramcore_new_master_rdata_valid1 <= 1'd0; - litedramcore_new_master_rdata_valid2 <= 1'd0; - litedramcore_new_master_rdata_valid3 <= 1'd0; - litedramcore_new_master_rdata_valid4 <= 1'd0; - litedramcore_new_master_rdata_valid5 <= 1'd0; - litedramcore_new_master_rdata_valid6 <= 1'd0; - litedramcore_new_master_rdata_valid7 <= 1'd0; - litedramcore_new_master_rdata_valid8 <= 1'd0; - litedramcore_state <= 2'd0; + interface1_we <= 1'd0; + refresher_state <= 2'd0; + bankmachine0_state <= 4'd0; + bankmachine1_state <= 4'd0; + bankmachine2_state <= 4'd0; + bankmachine3_state <= 4'd0; + bankmachine4_state <= 4'd0; + bankmachine5_state <= 4'd0; + bankmachine6_state <= 4'd0; + bankmachine7_state <= 4'd0; + multiplexer_state <= 4'd0; + new_master_wdata_ready0 <= 1'd0; + new_master_wdata_ready1 <= 1'd0; + new_master_rdata_valid0 <= 1'd0; + new_master_rdata_valid1 <= 1'd0; + new_master_rdata_valid2 <= 1'd0; + new_master_rdata_valid3 <= 1'd0; + new_master_rdata_valid4 <= 1'd0; + new_master_rdata_valid5 <= 1'd0; + new_master_rdata_valid6 <= 1'd0; + new_master_rdata_valid7 <= 1'd0; + new_master_rdata_valid8 <= 1'd0; + state <= 2'd0; end end @@ -14528,5 +14787,5 @@ assign soc_litedramcore_bankmachine7_rdport_dat_r = storage_7[soc_litedramcore_b endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2022-10-28 19:01:27. +// Auto-Generated by LiteX on 2024-04-01 10:12:12. //------------------------------------------------------------------------------ diff --git a/litedram/generated/wukong-v2/litedram_core.init b/litedram/generated/wukong-v2/litedram_core.init index 61e54f3..0573632 100644 --- a/litedram/generated/wukong-v2/litedram_core.init +++ b/litedram/generated/wukong-v2/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ff00782107c6 3d80000060215f00 798c07c6618c0000 -618c10e0658cff00 +618c10d4658cff00 4e8004217d8903a6 4e8004207c6903a6 0000000000000000 @@ -510,677 +510,687 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -392000003d40c000 -794a0020614a6004 -7d2057aa7c0004ac +3920000039406004 +7c0004ac654ac000 +600000007d2057aa 6000000060000000 6000000060000000 -4e80002060000000 +000000004e800020 0000000000000000 -3c4c000100000000 -7c0802a63842adc4 -fbe1fff8fbc1fff0 +3842adc83c4c0001 +fbe1fff87c0802a6 f821ff51f8010010 -f88100d83bc10020 -f8c100e8f8a100e0 -38c100d87c651b78 -f8e100f038800080 -7fc3f378f90100f8 -f9410108f9210100 -6000000048002139 -7fc3f3787c7f1b78 -6000000048001b59 -7fe3fb78382100b0 -000000004800285c -0000028001000000 -000000004e800020 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a/litedram/generated/wukong-v2/litedram_core.v b/litedram/generated/wukong-v2/litedram_core.v index 4196f91..d66961b 100644 --- a/litedram/generated/wukong-v2/litedram_core.v +++ b/litedram/generated/wukong-v2/litedram_core.v @@ -8,10 +8,11 @@ // // Filename : litedram_core.v // Device : -// LiteX sha1 : -------- -// Date : 2022-10-28 19:01:24 +// LiteX sha1 : 87137c30 +// Date : 2024-04-01 10:12:10 //------------------------------------------------------------------------------ +`timescale 1ns / 1ps //------------------------------------------------------------------------------ // Module @@ -19,4868 +20,5285 @@ module litedram_core ( input wire clk, - input wire rst, - output wire pll_locked, output wire [13:0] ddram_a, output wire [2:0] ddram_ba, - output wire ddram_ras_n, output wire ddram_cas_n, - output wire ddram_we_n, + output wire ddram_cke, + output wire ddram_clk_n, + output wire ddram_clk_p, output wire ddram_cs_n, output wire [1:0] ddram_dm, inout wire [15:0] ddram_dq, - inout wire [1:0] ddram_dqs_p, inout wire [1:0] ddram_dqs_n, - output wire ddram_clk_p, - output wire ddram_clk_n, - output wire ddram_cke, + inout wire [1:0] ddram_dqs_p, output wire ddram_odt, + output wire ddram_ras_n, output wire ddram_reset_n, + output wire ddram_we_n, output wire init_done, output wire init_error, - input wire [29:0] wb_ctrl_adr, - input wire [31:0] wb_ctrl_dat_w, - output wire [31:0] wb_ctrl_dat_r, - input wire [3:0] wb_ctrl_sel, - input wire wb_ctrl_cyc, - input wire wb_ctrl_stb, - output wire wb_ctrl_ack, - input wire wb_ctrl_we, - input wire [2:0] wb_ctrl_cti, - input wire [1:0] wb_ctrl_bte, - output wire wb_ctrl_err, + output wire pll_locked, + input wire rst, output wire user_clk, - output wire user_rst, - input wire user_port_native_0_cmd_valid, + input wire [23:0] user_port_native_0_cmd_addr, output wire user_port_native_0_cmd_ready, + input wire user_port_native_0_cmd_valid, input wire user_port_native_0_cmd_we, - input wire [23:0] user_port_native_0_cmd_addr, - input wire user_port_native_0_wdata_valid, + output wire [127:0] user_port_native_0_rdata_data, + input wire user_port_native_0_rdata_ready, + output wire user_port_native_0_rdata_valid, + input wire [127:0] user_port_native_0_wdata_data, output wire user_port_native_0_wdata_ready, + input wire user_port_native_0_wdata_valid, input wire [15:0] user_port_native_0_wdata_we, - input wire [127:0] user_port_native_0_wdata_data, - output wire user_port_native_0_rdata_valid, - input wire user_port_native_0_rdata_ready, - output wire [127:0] user_port_native_0_rdata_data + output wire user_rst, + output wire wb_ctrl_ack, + input wire [29:0] wb_ctrl_adr, + input wire [1:0] wb_ctrl_bte, + input wire [2:0] wb_ctrl_cti, + input wire wb_ctrl_cyc, + output wire [31:0] wb_ctrl_dat_r, + input wire [31:0] wb_ctrl_dat_w, + output wire wb_ctrl_err, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_stb, + input wire wb_ctrl_we ); +//------------------------------------------------------------------------------ +// Hierarchy +//------------------------------------------------------------------------------ + +/* +LiteDRAMCore +└─── bus (SoCBusHandler) +│ └─── _interconnect (InterconnectPointToPoint) +└─── csr (SoCCSRHandler) +└─── irq (SoCIRQHandler) +└─── cpu (CPUNone) +└─── crg (LiteDRAMS7DDRPHYCRG) +│ └─── pll (S7PLL) +│ │ └─── [FDCE] +│ │ └─── [BUFG] +│ │ └─── [FDCE] +│ │ └─── [BUFG] +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [BUFG] +│ │ └─── [BUFG] +│ │ └─── [PLLE2_ADV] +│ └─── idelayctrl (S7IDELAYCTRL) +│ │ └─── [IDELAYCTRL] +└─── ddrphy (A7DDRPHY) +│ └─── tappeddelayline_0* (TappedDelayLine) +│ └─── dqspattern_0* (DQSPattern) +│ └─── bitslip_0* (BitSlip) +│ └─── bitslip_1* (BitSlip) +│ └─── bitslip_2* (BitSlip) +│ └─── bitslip_3* (BitSlip) +│ └─── tappeddelayline_1* (TappedDelayLine) +│ └─── bitslip_4* (BitSlip) +│ └─── bitslip_5* (BitSlip) +│ └─── bitslip_6* (BitSlip) +│ └─── bitslip_7* (BitSlip) +│ └─── bitslip_8* (BitSlip) +│ └─── bitslip_9* (BitSlip) +│ └─── bitslip_10* (BitSlip) +│ └─── bitslip_11* (BitSlip) +│ └─── bitslip_12* (BitSlip) +│ └─── bitslip_13* (BitSlip) +│ └─── bitslip_14* (BitSlip) +│ └─── bitslip_15* (BitSlip) +│ └─── bitslip_16* (BitSlip) +│ └─── bitslip_17* (BitSlip) +│ └─── bitslip_18* (BitSlip) +│ └─── bitslip_19* (BitSlip) +│ └─── bitslip_20* (BitSlip) +│ └─── bitslip_21* (BitSlip) +│ └─── bitslip_22* (BitSlip) +│ └─── bitslip_23* (BitSlip) +│ └─── bitslip_24* (BitSlip) +│ └─── bitslip_25* (BitSlip) +│ └─── bitslip_26* (BitSlip) +│ └─── bitslip_27* (BitSlip) +│ └─── bitslip_28* (BitSlip) +│ └─── bitslip_29* (BitSlip) +│ └─── bitslip_30* (BitSlip) +│ └─── bitslip_31* (BitSlip) +│ └─── bitslip_32* (BitSlip) +│ └─── bitslip_33* (BitSlip) +│ └─── bitslip_34* (BitSlip) +│ └─── bitslip_35* (BitSlip) +│ └─── tappeddelayline_2* (TappedDelayLine) +│ └─── tappeddelayline_3* (TappedDelayLine) +│ └─── [IOBUF] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [OBUFDS] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUFDS] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IOBUFDS] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [ISERDESE2] +│ └─── [IOBUF] +│ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [IDELAYE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [IOBUF] +│ └─── [ISERDESE2] +│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +└─── sdram (LiteDRAMCore) +│ └─── dfii (DFIInjector) +│ │ └─── pi0 (PhaseInjector) +│ │ └─── pi1 (PhaseInjector) +│ │ └─── pi2 (PhaseInjector) +│ │ └─── pi3 (PhaseInjector) +│ └─── controller (LiteDRAMController) +│ │ └─── refresher (Refresher) +│ │ │ └─── timer (RefreshTimer) +│ │ │ └─── postponer (RefreshPostponer) +│ │ │ └─── sequencer (RefreshSequencer) +│ │ │ │ └─── refreshexecuter_0* (RefreshExecuter) +│ │ │ └─── zqcs_timer (RefreshTimer) +│ │ │ └─── zqs_executer (ZQCSExecuter) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_0* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_1* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_2* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_3* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_4* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_5* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_6* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── bankmachine_7* (BankMachine) +│ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── twtpcon (tXXDController) +│ │ │ └─── trccon (tXXDController) +│ │ │ └─── trascon (tXXDController) +│ │ │ └─── fsm (FSM) +│ │ └─── multiplexer (Multiplexer) +│ │ │ └─── choose_cmd (_CommandChooser) +│ │ │ │ └─── roundrobin_0* (RoundRobin) +│ │ │ └─── choose_req (_CommandChooser) +│ │ │ │ └─── roundrobin_0* (RoundRobin) +│ │ │ └─── _steerer_0* (_Steerer) +│ │ │ └─── trrdcon (tXXDController) +│ │ │ └─── tfawcon (tFAWController) +│ │ │ └─── tccdcon (tXXDController) +│ │ │ └─── twtrcon (tXXDController) +│ │ │ └─── fsm (FSM) +│ └─── crossbar (LiteDRAMCrossbar) +│ │ └─── roundrobin_0* (RoundRobin) +│ │ └─── roundrobin_1* (RoundRobin) +│ │ └─── roundrobin_2* (RoundRobin) +│ │ └─── roundrobin_3* (RoundRobin) +│ │ └─── roundrobin_4* (RoundRobin) +│ │ └─── roundrobin_5* (RoundRobin) +│ │ └─── roundrobin_6* (RoundRobin) +│ │ └─── roundrobin_7* (RoundRobin) +└─── ddrctrl (LiteDRAMCoreControl) +└─── csr_bridge (Wishbone2CSR) +│ └─── fsm (FSM) +└─── csr_bankarray (CSRBankArray) +│ └─── csrbank_0* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ └─── csrbank_1* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstorage_4* (CSRStorage) +│ │ └─── csrstorage_5* (CSRStorage) +│ └─── csrbank_2* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstorage_4* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstorage_5* (CSRStorage) +│ │ └─── csrstorage_6* (CSRStorage) +│ │ └─── csrstorage_7* (CSRStorage) +│ │ └─── csrstorage_8* (CSRStorage) +│ │ └─── csrstatus_1* (CSRStatus) +│ │ └─── csrstorage_9* (CSRStorage) +│ │ └─── csrstorage_10* (CSRStorage) +│ │ └─── csrstorage_11* (CSRStorage) +│ │ └─── csrstorage_12* (CSRStorage) +│ │ └─── csrstatus_2* (CSRStatus) +│ │ └─── csrstorage_13* (CSRStorage) +│ │ └─── csrstorage_14* (CSRStorage) +│ │ └─── csrstorage_15* (CSRStorage) +│ │ └─── csrstorage_16* (CSRStorage) +│ │ └─── csrstatus_3* (CSRStatus) +└─── csr_interconnect (InterconnectShared) +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +* : Generated name. +[]: BlackBox. +*/ + //------------------------------------------------------------------------------ // Signals //------------------------------------------------------------------------------ -reg rst_1 = 1'd0; -wire sys_clk; -wire sys_rst; -wire sys4x_clk; -wire sys4x_dqs_clk; +wire [13:0] builder_adr; +reg [3:0] builder_bankmachine0_next_state = 4'd0; +reg [3:0] builder_bankmachine0_state = 4'd0; +reg [3:0] builder_bankmachine1_next_state = 4'd0; +reg [3:0] builder_bankmachine1_state = 4'd0; +reg [3:0] builder_bankmachine2_next_state = 4'd0; +reg [3:0] builder_bankmachine2_state = 4'd0; +reg [3:0] builder_bankmachine3_next_state = 4'd0; +reg [3:0] builder_bankmachine3_state = 4'd0; +reg [3:0] builder_bankmachine4_next_state = 4'd0; +reg [3:0] builder_bankmachine4_state = 4'd0; +reg [3:0] builder_bankmachine5_next_state = 4'd0; +reg [3:0] builder_bankmachine5_state = 4'd0; +reg [3:0] builder_bankmachine6_next_state = 4'd0; +reg [3:0] builder_bankmachine6_state = 4'd0; +reg [3:0] builder_bankmachine7_next_state = 4'd0; +reg [3:0] builder_bankmachine7_state = 4'd0; +wire builder_csrbank0_init_done0_r; +reg builder_csrbank0_init_done0_re = 1'd0; +wire builder_csrbank0_init_done0_w; +reg builder_csrbank0_init_done0_we = 1'd0; +wire builder_csrbank0_init_error0_r; +reg builder_csrbank0_init_error0_re = 1'd0; +wire builder_csrbank0_init_error0_w; +reg builder_csrbank0_init_error0_we = 1'd0; +wire builder_csrbank0_sel; +wire [1:0] builder_csrbank1_dly_sel0_r; +reg builder_csrbank1_dly_sel0_re = 1'd0; +wire [1:0] builder_csrbank1_dly_sel0_w; +reg builder_csrbank1_dly_sel0_we = 1'd0; +wire [4:0] builder_csrbank1_half_sys8x_taps0_r; +reg builder_csrbank1_half_sys8x_taps0_re = 1'd0; +wire [4:0] builder_csrbank1_half_sys8x_taps0_w; +reg builder_csrbank1_half_sys8x_taps0_we = 1'd0; +wire [1:0] builder_csrbank1_rdphase0_r; +reg builder_csrbank1_rdphase0_re = 1'd0; +wire [1:0] builder_csrbank1_rdphase0_w; +reg builder_csrbank1_rdphase0_we = 1'd0; +wire builder_csrbank1_rst0_r; +reg builder_csrbank1_rst0_re = 1'd0; +wire builder_csrbank1_rst0_w; +reg builder_csrbank1_rst0_we = 1'd0; +wire builder_csrbank1_sel; +wire builder_csrbank1_wlevel_en0_r; +reg builder_csrbank1_wlevel_en0_re = 1'd0; +wire builder_csrbank1_wlevel_en0_w; +reg builder_csrbank1_wlevel_en0_we = 1'd0; +wire [1:0] builder_csrbank1_wrphase0_r; +reg builder_csrbank1_wrphase0_re = 1'd0; +wire [1:0] builder_csrbank1_wrphase0_w; +reg builder_csrbank1_wrphase0_we = 1'd0; +wire [3:0] builder_csrbank2_dfii_control0_r; +reg builder_csrbank2_dfii_control0_re = 1'd0; +wire [3:0] builder_csrbank2_dfii_control0_w; +reg builder_csrbank2_dfii_control0_we = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi0_address0_r; +reg builder_csrbank2_dfii_pi0_address0_re = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi0_address0_w; +reg builder_csrbank2_dfii_pi0_address0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r; +reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w; +reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_command0_r; +reg builder_csrbank2_dfii_pi0_command0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi0_command0_w; +reg builder_csrbank2_dfii_pi0_command0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_rddata_r; +reg builder_csrbank2_dfii_pi0_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_rddata_w; +reg builder_csrbank2_dfii_pi0_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_r; +reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_w; +reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi1_address0_r; +reg builder_csrbank2_dfii_pi1_address0_re = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi1_address0_w; +reg builder_csrbank2_dfii_pi1_address0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r; +reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w; +reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_command0_r; +reg builder_csrbank2_dfii_pi1_command0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi1_command0_w; +reg builder_csrbank2_dfii_pi1_command0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_rddata_r; +reg builder_csrbank2_dfii_pi1_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_rddata_w; +reg builder_csrbank2_dfii_pi1_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_r; +reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_w; +reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi2_address0_r; +reg builder_csrbank2_dfii_pi2_address0_re = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi2_address0_w; +reg builder_csrbank2_dfii_pi2_address0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r; +reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w; +reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_command0_r; +reg builder_csrbank2_dfii_pi2_command0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi2_command0_w; +reg builder_csrbank2_dfii_pi2_command0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_rddata_r; +reg builder_csrbank2_dfii_pi2_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_rddata_w; +reg builder_csrbank2_dfii_pi2_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_r; +reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_w; +reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi3_address0_r; +reg builder_csrbank2_dfii_pi3_address0_re = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi3_address0_w; +reg builder_csrbank2_dfii_pi3_address0_we = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r; +reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0; +wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w; +reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_command0_r; +reg builder_csrbank2_dfii_pi3_command0_re = 1'd0; +wire [7:0] builder_csrbank2_dfii_pi3_command0_w; +reg builder_csrbank2_dfii_pi3_command0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_rddata_r; +reg builder_csrbank2_dfii_pi3_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_rddata_w; +reg builder_csrbank2_dfii_pi3_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_r; +reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_w; +reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0; +wire builder_csrbank2_sel; +wire [31:0] builder_dat_r; +wire [31:0] builder_dat_w; +reg builder_interface0_ack = 1'd0; +wire [29:0] builder_interface0_adr; +wire [13:0] builder_interface0_bank_bus_adr; +reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface0_bank_bus_dat_w; +wire builder_interface0_bank_bus_we; +wire [1:0] builder_interface0_bte; +wire [2:0] builder_interface0_cti; +wire builder_interface0_cyc; +reg [31:0] builder_interface0_dat_r = 32'd0; +wire [31:0] builder_interface0_dat_w; +reg builder_interface0_err = 1'd0; +wire [3:0] builder_interface0_sel; +wire builder_interface0_stb; +wire builder_interface0_we; +reg [13:0] builder_interface1_adr = 14'd0; +reg [13:0] builder_interface1_adr_next_value1 = 14'd0; +reg builder_interface1_adr_next_value_ce1 = 1'd0; +wire [13:0] builder_interface1_bank_bus_adr; +reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface1_bank_bus_dat_w; +wire builder_interface1_bank_bus_we; +wire [31:0] builder_interface1_dat_r; +reg [31:0] builder_interface1_dat_w = 32'd0; +reg [31:0] builder_interface1_dat_w_next_value0 = 32'd0; +reg builder_interface1_dat_w_next_value_ce0 = 1'd0; +reg builder_interface1_we = 1'd0; +reg builder_interface1_we_next_value2 = 1'd0; +reg builder_interface1_we_next_value_ce2 = 1'd0; +wire [13:0] builder_interface2_bank_bus_adr; +reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface2_bank_bus_dat_w; +wire builder_interface2_bank_bus_we; +reg builder_locked0 = 1'd0; +reg builder_locked1 = 1'd0; +reg builder_locked2 = 1'd0; +reg builder_locked3 = 1'd0; +reg builder_locked4 = 1'd0; +reg builder_locked5 = 1'd0; +reg builder_locked6 = 1'd0; +reg builder_locked7 = 1'd0; +reg [3:0] builder_multiplexer_next_state = 4'd0; +reg [3:0] builder_multiplexer_state = 4'd0; +reg builder_new_master_rdata_valid0 = 1'd0; +reg builder_new_master_rdata_valid1 = 1'd0; +reg builder_new_master_rdata_valid2 = 1'd0; +reg builder_new_master_rdata_valid3 = 1'd0; +reg builder_new_master_rdata_valid4 = 1'd0; +reg builder_new_master_rdata_valid5 = 1'd0; +reg builder_new_master_rdata_valid6 = 1'd0; +reg builder_new_master_rdata_valid7 = 1'd0; +reg builder_new_master_rdata_valid8 = 1'd0; +reg builder_new_master_wdata_ready0 = 1'd0; +reg builder_new_master_wdata_ready1 = 1'd0; +reg [1:0] builder_next_state = 2'd0; +wire builder_pll_fb; +reg [1:0] builder_refresher_next_state = 2'd0; +reg [1:0] builder_refresher_state = 2'd0; +wire builder_reset0; +wire builder_reset1; +wire builder_reset2; +wire builder_reset3; +wire builder_reset4; +wire builder_reset5; +wire builder_reset6; +wire builder_reset7; +reg builder_rhs_self0 = 1'd0; +reg [13:0] builder_rhs_self1 = 14'd0; +reg builder_rhs_self10 = 1'd0; +reg builder_rhs_self11 = 1'd0; +reg [20:0] builder_rhs_self12 = 21'd0; +reg builder_rhs_self13 = 1'd0; +reg builder_rhs_self14 = 1'd0; +reg [20:0] builder_rhs_self15 = 21'd0; +reg builder_rhs_self16 = 1'd0; +reg builder_rhs_self17 = 1'd0; +reg [20:0] builder_rhs_self18 = 21'd0; +reg builder_rhs_self19 = 1'd0; +reg [2:0] builder_rhs_self2 = 3'd0; +reg builder_rhs_self20 = 1'd0; +reg [20:0] builder_rhs_self21 = 21'd0; +reg builder_rhs_self22 = 1'd0; +reg builder_rhs_self23 = 1'd0; +reg [20:0] builder_rhs_self24 = 21'd0; +reg builder_rhs_self25 = 1'd0; +reg builder_rhs_self26 = 1'd0; +reg [20:0] builder_rhs_self27 = 21'd0; +reg builder_rhs_self28 = 1'd0; +reg builder_rhs_self29 = 1'd0; +reg builder_rhs_self3 = 1'd0; +reg [20:0] builder_rhs_self30 = 21'd0; +reg builder_rhs_self31 = 1'd0; +reg builder_rhs_self32 = 1'd0; +reg [20:0] builder_rhs_self33 = 21'd0; +reg builder_rhs_self34 = 1'd0; +reg builder_rhs_self35 = 1'd0; +reg builder_rhs_self4 = 1'd0; +reg builder_rhs_self5 = 1'd0; +reg builder_rhs_self6 = 1'd0; +reg [13:0] builder_rhs_self7 = 14'd0; +reg [2:0] builder_rhs_self8 = 3'd0; +reg builder_rhs_self9 = 1'd0; +wire builder_roundrobin0_ce; +wire builder_roundrobin0_grant; +wire builder_roundrobin0_request; +wire builder_roundrobin1_ce; +wire builder_roundrobin1_grant; +wire builder_roundrobin1_request; +wire builder_roundrobin2_ce; +wire builder_roundrobin2_grant; +wire builder_roundrobin2_request; +wire builder_roundrobin3_ce; +wire builder_roundrobin3_grant; +wire builder_roundrobin3_request; +wire builder_roundrobin4_ce; +wire builder_roundrobin4_grant; +wire builder_roundrobin4_request; +wire builder_roundrobin5_ce; +wire builder_roundrobin5_grant; +wire builder_roundrobin5_request; +wire builder_roundrobin6_ce; +wire builder_roundrobin6_grant; +wire builder_roundrobin6_request; +wire builder_roundrobin7_ce; +wire builder_roundrobin7_grant; +wire builder_roundrobin7_request; +reg [2:0] builder_self0 = 3'd0; +reg [13:0] builder_self1 = 14'd0; +reg builder_self10 = 1'd0; +reg builder_self11 = 1'd0; +reg builder_self12 = 1'd0; +reg builder_self13 = 1'd0; +reg [2:0] builder_self14 = 3'd0; +reg [13:0] builder_self15 = 14'd0; +reg builder_self16 = 1'd0; +reg builder_self17 = 1'd0; +reg builder_self18 = 1'd0; +reg builder_self19 = 1'd0; +reg builder_self2 = 1'd0; +reg builder_self20 = 1'd0; +reg [2:0] builder_self21 = 3'd0; +reg [13:0] builder_self22 = 14'd0; +reg builder_self23 = 1'd0; +reg builder_self24 = 1'd0; +reg builder_self25 = 1'd0; +reg builder_self26 = 1'd0; +reg builder_self27 = 1'd0; +reg builder_self3 = 1'd0; +reg builder_self4 = 1'd0; +reg builder_self5 = 1'd0; +reg builder_self6 = 1'd0; +reg [2:0] builder_self7 = 3'd0; +reg [13:0] builder_self8 = 14'd0; +reg builder_self9 = 1'd0; +reg [1:0] builder_state = 2'd0; +reg builder_t_self0 = 1'd0; +reg builder_t_self1 = 1'd0; +reg builder_t_self2 = 1'd0; +reg builder_t_self3 = 1'd0; +reg builder_t_self4 = 1'd0; +reg builder_t_self5 = 1'd0; +wire builder_we; +wire builder_xilinxasyncresetsynchronizerimpl0_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl1_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl2_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl2_expr; +wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl3_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl3_expr; +wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta; wire iodelay_clk; wire iodelay_rst; -wire reset; -reg power_down = 1'd0; -wire locked; -wire clkin; -wire clkout0; -wire clkout_buf0; -wire clkout1; -wire clkout_buf1; -wire clkout2; -wire clkout_buf2; -wire clkout3; -wire clkout_buf3; -reg [3:0] reset_counter = 4'd15; -reg ic_reset = 1'd1; -reg a7ddrphy_rst_storage = 1'd0; -reg a7ddrphy_rst_re = 1'd0; -reg [1:0] a7ddrphy_dly_sel_storage = 2'd0; -reg a7ddrphy_dly_sel_re = 1'd0; -reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8; -reg a7ddrphy_half_sys8x_taps_re = 1'd0; -reg a7ddrphy_wlevel_en_storage = 1'd0; -reg a7ddrphy_wlevel_en_re = 1'd0; -reg a7ddrphy_wlevel_strobe_re = 1'd0; -wire a7ddrphy_wlevel_strobe_r; -reg a7ddrphy_wlevel_strobe_we = 1'd0; -reg a7ddrphy_wlevel_strobe_w = 1'd0; -reg a7ddrphy_rdly_dq_rst_re = 1'd0; -wire a7ddrphy_rdly_dq_rst_r; -reg a7ddrphy_rdly_dq_rst_we = 1'd0; -reg a7ddrphy_rdly_dq_rst_w = 1'd0; -reg a7ddrphy_rdly_dq_inc_re = 1'd0; -wire a7ddrphy_rdly_dq_inc_r; -reg a7ddrphy_rdly_dq_inc_we = 1'd0; -reg a7ddrphy_rdly_dq_inc_w = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; -wire a7ddrphy_rdly_dq_bitslip_rst_r; -reg a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_re = 1'd0; -wire a7ddrphy_rdly_dq_bitslip_r; -reg a7ddrphy_rdly_dq_bitslip_we = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_w = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; -wire a7ddrphy_wdly_dq_bitslip_rst_r; -reg a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_re = 1'd0; -wire a7ddrphy_wdly_dq_bitslip_r; -reg a7ddrphy_wdly_dq_bitslip_we = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_w = 1'd0; -reg [1:0] a7ddrphy_rdphase_storage = 2'd2; -reg a7ddrphy_rdphase_re = 1'd0; -reg [1:0] a7ddrphy_wrphase_storage = 2'd3; -reg a7ddrphy_wrphase_re = 1'd0; -wire [13:0] a7ddrphy_dfi_p0_address; -wire [2:0] a7ddrphy_dfi_p0_bank; -wire a7ddrphy_dfi_p0_cas_n; -wire a7ddrphy_dfi_p0_cs_n; -wire a7ddrphy_dfi_p0_ras_n; -wire a7ddrphy_dfi_p0_we_n; -wire a7ddrphy_dfi_p0_cke; -wire a7ddrphy_dfi_p0_odt; -wire a7ddrphy_dfi_p0_reset_n; -wire a7ddrphy_dfi_p0_act_n; -wire [31:0] a7ddrphy_dfi_p0_wrdata; -wire a7ddrphy_dfi_p0_wrdata_en; -wire [3:0] a7ddrphy_dfi_p0_wrdata_mask; -wire a7ddrphy_dfi_p0_rddata_en; -reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0; -wire a7ddrphy_dfi_p0_rddata_valid; -wire [13:0] a7ddrphy_dfi_p1_address; -wire [2:0] a7ddrphy_dfi_p1_bank; -wire a7ddrphy_dfi_p1_cas_n; -wire a7ddrphy_dfi_p1_cs_n; -wire a7ddrphy_dfi_p1_ras_n; -wire a7ddrphy_dfi_p1_we_n; -wire a7ddrphy_dfi_p1_cke; -wire a7ddrphy_dfi_p1_odt; -wire a7ddrphy_dfi_p1_reset_n; -wire a7ddrphy_dfi_p1_act_n; -wire [31:0] a7ddrphy_dfi_p1_wrdata; -wire a7ddrphy_dfi_p1_wrdata_en; -wire [3:0] a7ddrphy_dfi_p1_wrdata_mask; -wire a7ddrphy_dfi_p1_rddata_en; -reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0; -wire a7ddrphy_dfi_p1_rddata_valid; -wire [13:0] a7ddrphy_dfi_p2_address; -wire [2:0] a7ddrphy_dfi_p2_bank; -wire a7ddrphy_dfi_p2_cas_n; -wire a7ddrphy_dfi_p2_cs_n; -wire a7ddrphy_dfi_p2_ras_n; -wire a7ddrphy_dfi_p2_we_n; -wire a7ddrphy_dfi_p2_cke; -wire a7ddrphy_dfi_p2_odt; -wire a7ddrphy_dfi_p2_reset_n; -wire a7ddrphy_dfi_p2_act_n; -wire [31:0] a7ddrphy_dfi_p2_wrdata; -wire a7ddrphy_dfi_p2_wrdata_en; -wire [3:0] a7ddrphy_dfi_p2_wrdata_mask; -wire a7ddrphy_dfi_p2_rddata_en; -reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0; -wire a7ddrphy_dfi_p2_rddata_valid; -wire [13:0] a7ddrphy_dfi_p3_address; -wire [2:0] a7ddrphy_dfi_p3_bank; -wire a7ddrphy_dfi_p3_cas_n; -wire a7ddrphy_dfi_p3_cs_n; -wire a7ddrphy_dfi_p3_ras_n; -wire a7ddrphy_dfi_p3_we_n; -wire a7ddrphy_dfi_p3_cke; -wire a7ddrphy_dfi_p3_odt; -wire a7ddrphy_dfi_p3_reset_n; -wire a7ddrphy_dfi_p3_act_n; -wire [31:0] a7ddrphy_dfi_p3_wrdata; -wire a7ddrphy_dfi_p3_wrdata_en; -wire [3:0] a7ddrphy_dfi_p3_wrdata_mask; -wire a7ddrphy_dfi_p3_rddata_en; -reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0; -wire a7ddrphy_dfi_p3_rddata_valid; -wire a7ddrphy_sd_clk_se_nodelay; -wire [2:0] a7ddrphy_pads_ba; -reg a7ddrphy_dqs_oe = 1'd0; -wire a7ddrphy_dqs_preamble; -wire a7ddrphy_dqs_postamble; -wire a7ddrphy_dqs_oe_delay_tappeddelayline; -reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -reg a7ddrphy_dqspattern0 = 1'd0; -reg a7ddrphy_dqspattern1 = 1'd0; -reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0; -reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0; -wire a7ddrphy_dqs_o_no_delay0; -wire a7ddrphy_dqs_t0; -reg [7:0] a7ddrphy_bitslip00 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r0 = 16'd0; -wire a7ddrphy0; -wire a7ddrphy_dqs_o_no_delay1; -wire a7ddrphy_dqs_t1; -reg [7:0] a7ddrphy_bitslip10 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r0 = 16'd0; -wire a7ddrphy1; -reg [7:0] a7ddrphy_bitslip01 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r1 = 16'd0; -reg [7:0] a7ddrphy_bitslip11 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r1 = 16'd0; -wire a7ddrphy_dq_oe; -wire a7ddrphy_dq_oe_delay_tappeddelayline; -reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -wire a7ddrphy_dq_o_nodelay0; -wire a7ddrphy_dq_i_nodelay0; -wire a7ddrphy_dq_i_delayed0; -wire a7ddrphy_dq_t0; -reg [7:0] a7ddrphy_bitslip02 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value2 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r2 = 16'd0; -wire [7:0] a7ddrphy_bitslip03; -reg [7:0] a7ddrphy_bitslip04 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value3 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r3 = 16'd0; -wire a7ddrphy_dq_o_nodelay1; -wire a7ddrphy_dq_i_nodelay1; -wire a7ddrphy_dq_i_delayed1; -wire a7ddrphy_dq_t1; -reg [7:0] a7ddrphy_bitslip12 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value2 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r2 = 16'd0; -wire [7:0] a7ddrphy_bitslip13; -reg [7:0] a7ddrphy_bitslip14 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value3 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r3 = 16'd0; -wire a7ddrphy_dq_o_nodelay2; -wire a7ddrphy_dq_i_nodelay2; -wire a7ddrphy_dq_i_delayed2; -wire a7ddrphy_dq_t2; -reg [7:0] a7ddrphy_bitslip20 = 8'd0; -reg [2:0] a7ddrphy_bitslip2_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip2_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip21; -reg [7:0] a7ddrphy_bitslip22 = 8'd0; -reg [2:0] a7ddrphy_bitslip2_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip2_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay3; -wire a7ddrphy_dq_i_nodelay3; -wire a7ddrphy_dq_i_delayed3; -wire a7ddrphy_dq_t3; -reg [7:0] a7ddrphy_bitslip30 = 8'd0; -reg [2:0] a7ddrphy_bitslip3_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip3_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip31; -reg [7:0] a7ddrphy_bitslip32 = 8'd0; -reg [2:0] a7ddrphy_bitslip3_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip3_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay4; -wire a7ddrphy_dq_i_nodelay4; -wire a7ddrphy_dq_i_delayed4; -wire a7ddrphy_dq_t4; -reg [7:0] a7ddrphy_bitslip40 = 8'd0; -reg [2:0] a7ddrphy_bitslip4_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip4_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip41; -reg [7:0] a7ddrphy_bitslip42 = 8'd0; -reg [2:0] a7ddrphy_bitslip4_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip4_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay5; -wire a7ddrphy_dq_i_nodelay5; -wire a7ddrphy_dq_i_delayed5; -wire a7ddrphy_dq_t5; -reg [7:0] a7ddrphy_bitslip50 = 8'd0; -reg [2:0] a7ddrphy_bitslip5_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip5_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip51; -reg [7:0] a7ddrphy_bitslip52 = 8'd0; -reg [2:0] a7ddrphy_bitslip5_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip5_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay6; -wire a7ddrphy_dq_i_nodelay6; -wire a7ddrphy_dq_i_delayed6; -wire a7ddrphy_dq_t6; -reg [7:0] a7ddrphy_bitslip60 = 8'd0; -reg [2:0] a7ddrphy_bitslip6_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip6_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip61; -reg [7:0] a7ddrphy_bitslip62 = 8'd0; -reg [2:0] a7ddrphy_bitslip6_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip6_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay7; -wire a7ddrphy_dq_i_nodelay7; -wire a7ddrphy_dq_i_delayed7; -wire a7ddrphy_dq_t7; -reg [7:0] a7ddrphy_bitslip70 = 8'd0; -reg [2:0] a7ddrphy_bitslip7_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip7_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip71; -reg [7:0] a7ddrphy_bitslip72 = 8'd0; -reg [2:0] a7ddrphy_bitslip7_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip7_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay8; -wire a7ddrphy_dq_i_nodelay8; -wire a7ddrphy_dq_i_delayed8; -wire a7ddrphy_dq_t8; -reg [7:0] a7ddrphy_bitslip80 = 8'd0; -reg [2:0] a7ddrphy_bitslip8_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip8_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip81; -reg [7:0] a7ddrphy_bitslip82 = 8'd0; -reg [2:0] a7ddrphy_bitslip8_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip8_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay9; -wire a7ddrphy_dq_i_nodelay9; -wire a7ddrphy_dq_i_delayed9; -wire a7ddrphy_dq_t9; -reg [7:0] a7ddrphy_bitslip90 = 8'd0; -reg [2:0] a7ddrphy_bitslip9_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip9_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip91; -reg [7:0] a7ddrphy_bitslip92 = 8'd0; -reg [2:0] a7ddrphy_bitslip9_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip9_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay10; -wire a7ddrphy_dq_i_nodelay10; -wire a7ddrphy_dq_i_delayed10; -wire a7ddrphy_dq_t10; -reg [7:0] a7ddrphy_bitslip100 = 8'd0; -reg [2:0] a7ddrphy_bitslip10_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip10_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip101; -reg [7:0] a7ddrphy_bitslip102 = 8'd0; -reg [2:0] a7ddrphy_bitslip10_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip10_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay11; -wire a7ddrphy_dq_i_nodelay11; -wire a7ddrphy_dq_i_delayed11; -wire a7ddrphy_dq_t11; -reg [7:0] a7ddrphy_bitslip110 = 8'd0; -reg [2:0] a7ddrphy_bitslip11_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip11_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip111; -reg [7:0] a7ddrphy_bitslip112 = 8'd0; -reg [2:0] a7ddrphy_bitslip11_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip11_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay12; -wire a7ddrphy_dq_i_nodelay12; -wire a7ddrphy_dq_i_delayed12; -wire a7ddrphy_dq_t12; -reg [7:0] a7ddrphy_bitslip120 = 8'd0; -reg [2:0] a7ddrphy_bitslip12_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip12_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip121; -reg [7:0] a7ddrphy_bitslip122 = 8'd0; -reg [2:0] a7ddrphy_bitslip12_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip12_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay13; -wire a7ddrphy_dq_i_nodelay13; -wire a7ddrphy_dq_i_delayed13; -wire a7ddrphy_dq_t13; -reg [7:0] a7ddrphy_bitslip130 = 8'd0; -reg [2:0] a7ddrphy_bitslip13_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip13_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip131; -reg [7:0] a7ddrphy_bitslip132 = 8'd0; -reg [2:0] a7ddrphy_bitslip13_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip13_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay14; -wire a7ddrphy_dq_i_nodelay14; -wire a7ddrphy_dq_i_delayed14; -wire a7ddrphy_dq_t14; -reg [7:0] a7ddrphy_bitslip140 = 8'd0; -reg [2:0] a7ddrphy_bitslip14_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip14_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip141; -reg [7:0] a7ddrphy_bitslip142 = 8'd0; -reg [2:0] a7ddrphy_bitslip14_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip14_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay15; -wire a7ddrphy_dq_i_nodelay15; -wire a7ddrphy_dq_i_delayed15; -wire a7ddrphy_dq_t15; -reg [7:0] a7ddrphy_bitslip150 = 8'd0; -reg [2:0] a7ddrphy_bitslip15_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip15_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip151; -reg [7:0] a7ddrphy_bitslip152 = 8'd0; -reg [2:0] a7ddrphy_bitslip15_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip15_r1 = 16'd0; -reg a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; -reg a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; -reg a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; -reg a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; -wire [13:0] litedramcore_slave_p0_address; -wire [2:0] litedramcore_slave_p0_bank; -wire litedramcore_slave_p0_cas_n; -wire litedramcore_slave_p0_cs_n; -wire litedramcore_slave_p0_ras_n; -wire litedramcore_slave_p0_we_n; -wire litedramcore_slave_p0_cke; -wire litedramcore_slave_p0_odt; -wire litedramcore_slave_p0_reset_n; -wire litedramcore_slave_p0_act_n; -wire [31:0] litedramcore_slave_p0_wrdata; -wire litedramcore_slave_p0_wrdata_en; -wire [3:0] litedramcore_slave_p0_wrdata_mask; -wire litedramcore_slave_p0_rddata_en; -reg [31:0] litedramcore_slave_p0_rddata = 32'd0; -reg litedramcore_slave_p0_rddata_valid = 1'd0; -wire [13:0] litedramcore_slave_p1_address; -wire [2:0] litedramcore_slave_p1_bank; -wire litedramcore_slave_p1_cas_n; -wire litedramcore_slave_p1_cs_n; -wire litedramcore_slave_p1_ras_n; -wire litedramcore_slave_p1_we_n; -wire litedramcore_slave_p1_cke; -wire litedramcore_slave_p1_odt; -wire litedramcore_slave_p1_reset_n; -wire litedramcore_slave_p1_act_n; -wire [31:0] litedramcore_slave_p1_wrdata; -wire litedramcore_slave_p1_wrdata_en; -wire [3:0] litedramcore_slave_p1_wrdata_mask; -wire litedramcore_slave_p1_rddata_en; -reg [31:0] litedramcore_slave_p1_rddata = 32'd0; -reg litedramcore_slave_p1_rddata_valid = 1'd0; -wire [13:0] litedramcore_slave_p2_address; -wire [2:0] litedramcore_slave_p2_bank; -wire litedramcore_slave_p2_cas_n; -wire litedramcore_slave_p2_cs_n; -wire litedramcore_slave_p2_ras_n; -wire litedramcore_slave_p2_we_n; -wire litedramcore_slave_p2_cke; -wire litedramcore_slave_p2_odt; -wire litedramcore_slave_p2_reset_n; -wire litedramcore_slave_p2_act_n; -wire [31:0] litedramcore_slave_p2_wrdata; -wire litedramcore_slave_p2_wrdata_en; -wire [3:0] litedramcore_slave_p2_wrdata_mask; -wire litedramcore_slave_p2_rddata_en; -reg [31:0] litedramcore_slave_p2_rddata = 32'd0; -reg litedramcore_slave_p2_rddata_valid = 1'd0; -wire [13:0] litedramcore_slave_p3_address; -wire [2:0] litedramcore_slave_p3_bank; -wire litedramcore_slave_p3_cas_n; -wire litedramcore_slave_p3_cs_n; -wire litedramcore_slave_p3_ras_n; -wire litedramcore_slave_p3_we_n; -wire litedramcore_slave_p3_cke; -wire litedramcore_slave_p3_odt; -wire litedramcore_slave_p3_reset_n; -wire litedramcore_slave_p3_act_n; -wire [31:0] litedramcore_slave_p3_wrdata; -wire litedramcore_slave_p3_wrdata_en; -wire [3:0] litedramcore_slave_p3_wrdata_mask; -wire litedramcore_slave_p3_rddata_en; -reg [31:0] litedramcore_slave_p3_rddata = 32'd0; -reg litedramcore_slave_p3_rddata_valid = 1'd0; -reg [13:0] litedramcore_master_p0_address = 14'd0; -reg [2:0] litedramcore_master_p0_bank = 3'd0; -reg litedramcore_master_p0_cas_n = 1'd1; -reg litedramcore_master_p0_cs_n = 1'd1; -reg litedramcore_master_p0_ras_n = 1'd1; -reg litedramcore_master_p0_we_n = 1'd1; -reg litedramcore_master_p0_cke = 1'd0; -reg litedramcore_master_p0_odt = 1'd0; -reg litedramcore_master_p0_reset_n = 1'd0; -reg litedramcore_master_p0_act_n = 1'd1; -reg [31:0] litedramcore_master_p0_wrdata = 32'd0; -reg litedramcore_master_p0_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0; -reg litedramcore_master_p0_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p0_rddata; -wire litedramcore_master_p0_rddata_valid; -reg [13:0] litedramcore_master_p1_address = 14'd0; -reg [2:0] litedramcore_master_p1_bank = 3'd0; -reg litedramcore_master_p1_cas_n = 1'd1; -reg litedramcore_master_p1_cs_n = 1'd1; -reg litedramcore_master_p1_ras_n = 1'd1; -reg litedramcore_master_p1_we_n = 1'd1; -reg litedramcore_master_p1_cke = 1'd0; -reg litedramcore_master_p1_odt = 1'd0; -reg litedramcore_master_p1_reset_n = 1'd0; -reg litedramcore_master_p1_act_n = 1'd1; -reg [31:0] litedramcore_master_p1_wrdata = 32'd0; -reg litedramcore_master_p1_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0; -reg litedramcore_master_p1_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p1_rddata; -wire litedramcore_master_p1_rddata_valid; -reg [13:0] litedramcore_master_p2_address = 14'd0; -reg [2:0] litedramcore_master_p2_bank = 3'd0; -reg litedramcore_master_p2_cas_n = 1'd1; -reg litedramcore_master_p2_cs_n = 1'd1; -reg litedramcore_master_p2_ras_n = 1'd1; -reg litedramcore_master_p2_we_n = 1'd1; -reg litedramcore_master_p2_cke = 1'd0; -reg litedramcore_master_p2_odt = 1'd0; -reg litedramcore_master_p2_reset_n = 1'd0; -reg litedramcore_master_p2_act_n = 1'd1; -reg [31:0] litedramcore_master_p2_wrdata = 32'd0; -reg litedramcore_master_p2_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0; -reg litedramcore_master_p2_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p2_rddata; -wire litedramcore_master_p2_rddata_valid; -reg [13:0] litedramcore_master_p3_address = 14'd0; -reg [2:0] litedramcore_master_p3_bank = 3'd0; -reg litedramcore_master_p3_cas_n = 1'd1; -reg litedramcore_master_p3_cs_n = 1'd1; -reg litedramcore_master_p3_ras_n = 1'd1; -reg litedramcore_master_p3_we_n = 1'd1; -reg litedramcore_master_p3_cke = 1'd0; -reg litedramcore_master_p3_odt = 1'd0; -reg litedramcore_master_p3_reset_n = 1'd0; -reg litedramcore_master_p3_act_n = 1'd1; -reg [31:0] litedramcore_master_p3_wrdata = 32'd0; -reg litedramcore_master_p3_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0; -reg litedramcore_master_p3_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p3_rddata; -wire litedramcore_master_p3_rddata_valid; -wire [13:0] litedramcore_csr_dfi_p0_address; -wire [2:0] litedramcore_csr_dfi_p0_bank; -reg litedramcore_csr_dfi_p0_cas_n = 1'd1; -reg litedramcore_csr_dfi_p0_cs_n = 1'd1; -reg litedramcore_csr_dfi_p0_ras_n = 1'd1; -reg litedramcore_csr_dfi_p0_we_n = 1'd1; -wire litedramcore_csr_dfi_p0_cke; -wire litedramcore_csr_dfi_p0_odt; -wire litedramcore_csr_dfi_p0_reset_n; -reg litedramcore_csr_dfi_p0_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p0_wrdata; -wire litedramcore_csr_dfi_p0_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask; -wire litedramcore_csr_dfi_p0_rddata_en; -reg [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0; -reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0; -wire [13:0] litedramcore_csr_dfi_p1_address; -wire [2:0] litedramcore_csr_dfi_p1_bank; -reg litedramcore_csr_dfi_p1_cas_n = 1'd1; -reg litedramcore_csr_dfi_p1_cs_n = 1'd1; -reg litedramcore_csr_dfi_p1_ras_n = 1'd1; -reg litedramcore_csr_dfi_p1_we_n = 1'd1; -wire litedramcore_csr_dfi_p1_cke; -wire litedramcore_csr_dfi_p1_odt; -wire litedramcore_csr_dfi_p1_reset_n; -reg litedramcore_csr_dfi_p1_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p1_wrdata; -wire litedramcore_csr_dfi_p1_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask; -wire litedramcore_csr_dfi_p1_rddata_en; -reg [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0; -reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0; -wire [13:0] litedramcore_csr_dfi_p2_address; -wire [2:0] litedramcore_csr_dfi_p2_bank; -reg litedramcore_csr_dfi_p2_cas_n = 1'd1; -reg litedramcore_csr_dfi_p2_cs_n = 1'd1; -reg litedramcore_csr_dfi_p2_ras_n = 1'd1; -reg litedramcore_csr_dfi_p2_we_n = 1'd1; -wire litedramcore_csr_dfi_p2_cke; -wire litedramcore_csr_dfi_p2_odt; -wire litedramcore_csr_dfi_p2_reset_n; -reg litedramcore_csr_dfi_p2_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p2_wrdata; -wire litedramcore_csr_dfi_p2_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask; -wire litedramcore_csr_dfi_p2_rddata_en; -reg [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0; -reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0; -wire [13:0] litedramcore_csr_dfi_p3_address; -wire [2:0] litedramcore_csr_dfi_p3_bank; -reg litedramcore_csr_dfi_p3_cas_n = 1'd1; -reg litedramcore_csr_dfi_p3_cs_n = 1'd1; -reg litedramcore_csr_dfi_p3_ras_n = 1'd1; -reg litedramcore_csr_dfi_p3_we_n = 1'd1; -wire litedramcore_csr_dfi_p3_cke; -wire litedramcore_csr_dfi_p3_odt; -wire litedramcore_csr_dfi_p3_reset_n; -reg litedramcore_csr_dfi_p3_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p3_wrdata; -wire litedramcore_csr_dfi_p3_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask; -wire litedramcore_csr_dfi_p3_rddata_en; -reg [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0; -reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0; -reg [13:0] litedramcore_ext_dfi_p0_address = 14'd0; -reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0; -reg litedramcore_ext_dfi_p0_cas_n = 1'd1; -reg litedramcore_ext_dfi_p0_cs_n = 1'd1; -reg litedramcore_ext_dfi_p0_ras_n = 1'd1; -reg litedramcore_ext_dfi_p0_we_n = 1'd1; -reg litedramcore_ext_dfi_p0_cke = 1'd0; -reg litedramcore_ext_dfi_p0_odt = 1'd0; -reg litedramcore_ext_dfi_p0_reset_n = 1'd0; -reg litedramcore_ext_dfi_p0_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0; -reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p0_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0; -reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0; -reg [13:0] litedramcore_ext_dfi_p1_address = 14'd0; -reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0; -reg litedramcore_ext_dfi_p1_cas_n = 1'd1; -reg litedramcore_ext_dfi_p1_cs_n = 1'd1; -reg litedramcore_ext_dfi_p1_ras_n = 1'd1; -reg litedramcore_ext_dfi_p1_we_n = 1'd1; -reg litedramcore_ext_dfi_p1_cke = 1'd0; -reg litedramcore_ext_dfi_p1_odt = 1'd0; -reg litedramcore_ext_dfi_p1_reset_n = 1'd0; -reg litedramcore_ext_dfi_p1_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0; -reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p1_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0; -reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0; -reg [13:0] litedramcore_ext_dfi_p2_address = 14'd0; -reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0; -reg litedramcore_ext_dfi_p2_cas_n = 1'd1; -reg litedramcore_ext_dfi_p2_cs_n = 1'd1; -reg litedramcore_ext_dfi_p2_ras_n = 1'd1; -reg litedramcore_ext_dfi_p2_we_n = 1'd1; -reg litedramcore_ext_dfi_p2_cke = 1'd0; -reg litedramcore_ext_dfi_p2_odt = 1'd0; -reg litedramcore_ext_dfi_p2_reset_n = 1'd0; -reg litedramcore_ext_dfi_p2_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0; -reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p2_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0; -reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0; -reg [13:0] litedramcore_ext_dfi_p3_address = 14'd0; -reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0; -reg litedramcore_ext_dfi_p3_cas_n = 1'd1; -reg litedramcore_ext_dfi_p3_cs_n = 1'd1; -reg litedramcore_ext_dfi_p3_ras_n = 1'd1; -reg litedramcore_ext_dfi_p3_we_n = 1'd1; -reg litedramcore_ext_dfi_p3_cke = 1'd0; -reg litedramcore_ext_dfi_p3_odt = 1'd0; -reg litedramcore_ext_dfi_p3_reset_n = 1'd0; -reg litedramcore_ext_dfi_p3_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0; -reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p3_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0; -reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0; -reg litedramcore_ext_dfi_sel = 1'd0; -wire litedramcore_sel; -wire litedramcore_cke; -wire litedramcore_odt; -wire litedramcore_reset_n; -reg [3:0] litedramcore_storage = 4'd1; -reg litedramcore_re = 1'd0; -wire litedramcore_phaseinjector0_csrfield_cs; -wire litedramcore_phaseinjector0_csrfield_we; -wire litedramcore_phaseinjector0_csrfield_cas; -wire litedramcore_phaseinjector0_csrfield_ras; -wire litedramcore_phaseinjector0_csrfield_wren; -wire litedramcore_phaseinjector0_csrfield_rden; -reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; -reg litedramcore_phaseinjector0_command_re = 1'd0; -reg litedramcore_phaseinjector0_command_issue_re = 1'd0; -wire litedramcore_phaseinjector0_command_issue_r; -reg litedramcore_phaseinjector0_command_issue_we = 1'd0; -reg litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [13:0] litedramcore_phaseinjector0_address_storage = 14'd0; -reg litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0; -wire litedramcore_phaseinjector0_rddata_we; -reg litedramcore_phaseinjector0_rddata_re = 1'd0; -wire litedramcore_phaseinjector1_csrfield_cs; -wire litedramcore_phaseinjector1_csrfield_we; -wire litedramcore_phaseinjector1_csrfield_cas; -wire litedramcore_phaseinjector1_csrfield_ras; -wire litedramcore_phaseinjector1_csrfield_wren; -wire litedramcore_phaseinjector1_csrfield_rden; -reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0; -reg litedramcore_phaseinjector1_command_re = 1'd0; -reg litedramcore_phaseinjector1_command_issue_re = 1'd0; -wire litedramcore_phaseinjector1_command_issue_r; -reg litedramcore_phaseinjector1_command_issue_we = 1'd0; -reg litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [13:0] litedramcore_phaseinjector1_address_storage = 14'd0; -reg litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0; -wire litedramcore_phaseinjector1_rddata_we; -reg litedramcore_phaseinjector1_rddata_re = 1'd0; -wire litedramcore_phaseinjector2_csrfield_cs; -wire litedramcore_phaseinjector2_csrfield_we; -wire litedramcore_phaseinjector2_csrfield_cas; -wire litedramcore_phaseinjector2_csrfield_ras; -wire litedramcore_phaseinjector2_csrfield_wren; -wire litedramcore_phaseinjector2_csrfield_rden; -reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0; -reg litedramcore_phaseinjector2_command_re = 1'd0; -reg litedramcore_phaseinjector2_command_issue_re = 1'd0; -wire litedramcore_phaseinjector2_command_issue_r; -reg litedramcore_phaseinjector2_command_issue_we = 1'd0; -reg litedramcore_phaseinjector2_command_issue_w = 1'd0; -reg [13:0] litedramcore_phaseinjector2_address_storage = 14'd0; -reg litedramcore_phaseinjector2_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0; -reg litedramcore_phaseinjector2_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector2_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0; -wire litedramcore_phaseinjector2_rddata_we; -reg litedramcore_phaseinjector2_rddata_re = 1'd0; -wire litedramcore_phaseinjector3_csrfield_cs; -wire litedramcore_phaseinjector3_csrfield_we; -wire litedramcore_phaseinjector3_csrfield_cas; -wire litedramcore_phaseinjector3_csrfield_ras; -wire litedramcore_phaseinjector3_csrfield_wren; -wire litedramcore_phaseinjector3_csrfield_rden; -reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0; -reg litedramcore_phaseinjector3_command_re = 1'd0; -reg litedramcore_phaseinjector3_command_issue_re = 1'd0; -wire litedramcore_phaseinjector3_command_issue_r; -reg litedramcore_phaseinjector3_command_issue_we = 1'd0; -reg litedramcore_phaseinjector3_command_issue_w = 1'd0; -reg [13:0] litedramcore_phaseinjector3_address_storage = 14'd0; -reg litedramcore_phaseinjector3_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0; -reg litedramcore_phaseinjector3_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector3_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0; -wire litedramcore_phaseinjector3_rddata_we; -reg litedramcore_phaseinjector3_rddata_re = 1'd0; -wire litedramcore_interface_bank0_valid; -wire litedramcore_interface_bank0_ready; -wire litedramcore_interface_bank0_we; -wire [20:0] litedramcore_interface_bank0_addr; -wire litedramcore_interface_bank0_lock; -wire litedramcore_interface_bank0_wdata_ready; -wire litedramcore_interface_bank0_rdata_valid; -wire litedramcore_interface_bank1_valid; -wire litedramcore_interface_bank1_ready; -wire litedramcore_interface_bank1_we; -wire [20:0] litedramcore_interface_bank1_addr; -wire litedramcore_interface_bank1_lock; -wire litedramcore_interface_bank1_wdata_ready; -wire litedramcore_interface_bank1_rdata_valid; -wire litedramcore_interface_bank2_valid; -wire litedramcore_interface_bank2_ready; -wire litedramcore_interface_bank2_we; -wire [20:0] litedramcore_interface_bank2_addr; -wire litedramcore_interface_bank2_lock; -wire litedramcore_interface_bank2_wdata_ready; -wire litedramcore_interface_bank2_rdata_valid; -wire litedramcore_interface_bank3_valid; -wire litedramcore_interface_bank3_ready; -wire litedramcore_interface_bank3_we; -wire [20:0] litedramcore_interface_bank3_addr; -wire litedramcore_interface_bank3_lock; -wire litedramcore_interface_bank3_wdata_ready; -wire litedramcore_interface_bank3_rdata_valid; -wire litedramcore_interface_bank4_valid; -wire litedramcore_interface_bank4_ready; -wire litedramcore_interface_bank4_we; -wire [20:0] litedramcore_interface_bank4_addr; -wire litedramcore_interface_bank4_lock; -wire litedramcore_interface_bank4_wdata_ready; -wire litedramcore_interface_bank4_rdata_valid; -wire litedramcore_interface_bank5_valid; -wire litedramcore_interface_bank5_ready; -wire litedramcore_interface_bank5_we; -wire [20:0] litedramcore_interface_bank5_addr; -wire litedramcore_interface_bank5_lock; -wire litedramcore_interface_bank5_wdata_ready; -wire litedramcore_interface_bank5_rdata_valid; -wire litedramcore_interface_bank6_valid; -wire litedramcore_interface_bank6_ready; -wire litedramcore_interface_bank6_we; -wire [20:0] litedramcore_interface_bank6_addr; -wire litedramcore_interface_bank6_lock; -wire litedramcore_interface_bank6_wdata_ready; -wire litedramcore_interface_bank6_rdata_valid; -wire litedramcore_interface_bank7_valid; -wire litedramcore_interface_bank7_ready; -wire litedramcore_interface_bank7_we; -wire [20:0] litedramcore_interface_bank7_addr; -wire litedramcore_interface_bank7_lock; -wire litedramcore_interface_bank7_wdata_ready; -wire litedramcore_interface_bank7_rdata_valid; -reg [127:0] litedramcore_interface_wdata = 128'd0; -reg [15:0] litedramcore_interface_wdata_we = 16'd0; -wire [127:0] litedramcore_interface_rdata; -reg [13:0] litedramcore_dfi_p0_address = 14'd0; -reg [2:0] litedramcore_dfi_p0_bank = 3'd0; -reg litedramcore_dfi_p0_cas_n = 1'd1; -reg litedramcore_dfi_p0_cs_n = 1'd1; -reg litedramcore_dfi_p0_ras_n = 1'd1; -reg litedramcore_dfi_p0_we_n = 1'd1; -wire litedramcore_dfi_p0_cke; -wire litedramcore_dfi_p0_odt; -wire litedramcore_dfi_p0_reset_n; -reg litedramcore_dfi_p0_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p0_wrdata; -reg litedramcore_dfi_p0_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p0_wrdata_mask; -reg litedramcore_dfi_p0_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p0_rddata; -wire litedramcore_dfi_p0_rddata_valid; -reg [13:0] litedramcore_dfi_p1_address = 14'd0; -reg [2:0] litedramcore_dfi_p1_bank = 3'd0; -reg litedramcore_dfi_p1_cas_n = 1'd1; -reg litedramcore_dfi_p1_cs_n = 1'd1; -reg litedramcore_dfi_p1_ras_n = 1'd1; -reg litedramcore_dfi_p1_we_n = 1'd1; -wire litedramcore_dfi_p1_cke; -wire litedramcore_dfi_p1_odt; -wire litedramcore_dfi_p1_reset_n; -reg litedramcore_dfi_p1_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p1_wrdata; -reg litedramcore_dfi_p1_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p1_wrdata_mask; -reg litedramcore_dfi_p1_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p1_rddata; -wire litedramcore_dfi_p1_rddata_valid; -reg [13:0] litedramcore_dfi_p2_address = 14'd0; -reg [2:0] litedramcore_dfi_p2_bank = 3'd0; -reg litedramcore_dfi_p2_cas_n = 1'd1; -reg litedramcore_dfi_p2_cs_n = 1'd1; -reg litedramcore_dfi_p2_ras_n = 1'd1; -reg litedramcore_dfi_p2_we_n = 1'd1; -wire litedramcore_dfi_p2_cke; -wire litedramcore_dfi_p2_odt; -wire litedramcore_dfi_p2_reset_n; -reg litedramcore_dfi_p2_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p2_wrdata; -reg litedramcore_dfi_p2_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p2_wrdata_mask; -reg litedramcore_dfi_p2_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p2_rddata; -wire litedramcore_dfi_p2_rddata_valid; -reg [13:0] litedramcore_dfi_p3_address = 14'd0; -reg [2:0] litedramcore_dfi_p3_bank = 3'd0; -reg litedramcore_dfi_p3_cas_n = 1'd1; -reg litedramcore_dfi_p3_cs_n = 1'd1; -reg litedramcore_dfi_p3_ras_n = 1'd1; -reg litedramcore_dfi_p3_we_n = 1'd1; -wire litedramcore_dfi_p3_cke; -wire litedramcore_dfi_p3_odt; -wire litedramcore_dfi_p3_reset_n; -reg litedramcore_dfi_p3_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p3_wrdata; -reg litedramcore_dfi_p3_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p3_wrdata_mask; -reg litedramcore_dfi_p3_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p3_rddata; -wire litedramcore_dfi_p3_rddata_valid; -reg litedramcore_cmd_valid = 1'd0; -reg litedramcore_cmd_ready = 1'd0; -reg litedramcore_cmd_last = 1'd0; -reg [13:0] litedramcore_cmd_payload_a = 14'd0; -reg [2:0] litedramcore_cmd_payload_ba = 3'd0; -reg litedramcore_cmd_payload_cas = 1'd0; -reg litedramcore_cmd_payload_ras = 1'd0; -reg litedramcore_cmd_payload_we = 1'd0; -reg litedramcore_cmd_payload_is_read = 1'd0; -reg litedramcore_cmd_payload_is_write = 1'd0; -wire litedramcore_wants_refresh; -wire litedramcore_wants_zqcs; -wire litedramcore_timer_wait; -wire litedramcore_timer_done0; -wire [9:0] litedramcore_timer_count0; -wire litedramcore_timer_done1; -reg [9:0] litedramcore_timer_count1 = 10'd781; -wire litedramcore_postponer_req_i; -reg litedramcore_postponer_req_o = 1'd0; -reg litedramcore_postponer_count = 1'd0; -reg litedramcore_sequencer_start0 = 1'd0; -wire litedramcore_sequencer_done0; -wire litedramcore_sequencer_start1; -reg litedramcore_sequencer_done1 = 1'd0; -reg [5:0] litedramcore_sequencer_counter = 6'd0; -reg litedramcore_sequencer_count = 1'd0; -wire litedramcore_zqcs_timer_wait; -wire litedramcore_zqcs_timer_done0; -wire [26:0] litedramcore_zqcs_timer_count0; -wire litedramcore_zqcs_timer_done1; -reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999; -reg litedramcore_zqcs_executer_start = 1'd0; -reg litedramcore_zqcs_executer_done = 1'd0; -reg [4:0] litedramcore_zqcs_executer_counter = 5'd0; -wire litedramcore_bankmachine0_req_valid; -wire litedramcore_bankmachine0_req_ready; -wire litedramcore_bankmachine0_req_we; -wire [20:0] litedramcore_bankmachine0_req_addr; -wire litedramcore_bankmachine0_req_lock; -reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine0_refresh_req; -reg litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg litedramcore_bankmachine0_cmd_valid = 1'd0; -reg litedramcore_bankmachine0_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine0_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; -reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine0_auto_precharge = 1'd0; -wire litedramcore_bankmachine0_sink_valid; -wire litedramcore_bankmachine0_sink_ready; -reg litedramcore_bankmachine0_sink_first = 1'd0; -reg litedramcore_bankmachine0_sink_last = 1'd0; -wire litedramcore_bankmachine0_sink_payload_we; -wire [20:0] litedramcore_bankmachine0_sink_payload_addr; -wire litedramcore_bankmachine0_source_valid; -wire litedramcore_bankmachine0_source_ready; -wire litedramcore_bankmachine0_source_first; -wire litedramcore_bankmachine0_source_last; -wire litedramcore_bankmachine0_source_payload_we; -wire [20:0] litedramcore_bankmachine0_source_payload_addr; -wire litedramcore_bankmachine0_syncfifo0_we; -wire litedramcore_bankmachine0_syncfifo0_writable; -wire litedramcore_bankmachine0_syncfifo0_re; -wire litedramcore_bankmachine0_syncfifo0_readable; -wire [23:0] litedramcore_bankmachine0_syncfifo0_din; -wire [23:0] litedramcore_bankmachine0_syncfifo0_dout; -reg [4:0] litedramcore_bankmachine0_level = 5'd0; -reg litedramcore_bankmachine0_replace = 1'd0; -reg [3:0] litedramcore_bankmachine0_produce = 4'd0; -reg [3:0] litedramcore_bankmachine0_consume = 4'd0; -reg [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine0_wrport_dat_r; -wire litedramcore_bankmachine0_wrport_we; -wire [23:0] litedramcore_bankmachine0_wrport_dat_w; -wire litedramcore_bankmachine0_do_read; -wire [3:0] litedramcore_bankmachine0_rdport_adr; -wire [23:0] litedramcore_bankmachine0_rdport_dat_r; -wire litedramcore_bankmachine0_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine0_fifo_in_payload_addr; -wire litedramcore_bankmachine0_fifo_in_first; -wire litedramcore_bankmachine0_fifo_in_last; -wire litedramcore_bankmachine0_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine0_fifo_out_payload_addr; -wire litedramcore_bankmachine0_fifo_out_first; -wire litedramcore_bankmachine0_fifo_out_last; -wire litedramcore_bankmachine0_sink_sink_valid; -wire litedramcore_bankmachine0_sink_sink_ready; -wire litedramcore_bankmachine0_sink_sink_first; -wire litedramcore_bankmachine0_sink_sink_last; -wire litedramcore_bankmachine0_sink_sink_payload_we; -wire [20:0] litedramcore_bankmachine0_sink_sink_payload_addr; -wire litedramcore_bankmachine0_source_source_valid; -wire litedramcore_bankmachine0_source_source_ready; -wire litedramcore_bankmachine0_source_source_first; -wire litedramcore_bankmachine0_source_source_last; -wire litedramcore_bankmachine0_source_source_payload_we; -wire [20:0] litedramcore_bankmachine0_source_source_payload_addr; -wire litedramcore_bankmachine0_pipe_valid_sink_valid; -wire litedramcore_bankmachine0_pipe_valid_sink_ready; -wire litedramcore_bankmachine0_pipe_valid_sink_first; -wire litedramcore_bankmachine0_pipe_valid_sink_last; -wire litedramcore_bankmachine0_pipe_valid_sink_payload_we; -wire [20:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine0_pipe_valid_source_ready; -reg litedramcore_bankmachine0_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine0_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine0_row = 14'd0; -reg litedramcore_bankmachine0_row_opened = 1'd0; -wire litedramcore_bankmachine0_row_hit; -reg litedramcore_bankmachine0_row_open = 1'd0; -reg litedramcore_bankmachine0_row_close = 1'd0; -reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine0_twtpcon_valid; +wire main_a7ddrphy0; +wire main_a7ddrphy1; +reg [7:0] main_a7ddrphy_bitslip00 = 8'd0; +reg [7:0] main_a7ddrphy_bitslip01 = 8'd0; +reg [7:0] main_a7ddrphy_bitslip02 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip03; +reg [7:0] main_a7ddrphy_bitslip04 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip10 = 8'd0; +reg [7:0] main_a7ddrphy_bitslip100 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip101; +reg [7:0] main_a7ddrphy_bitslip102 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip11 = 8'd0; +reg [7:0] main_a7ddrphy_bitslip110 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip111; +reg [7:0] main_a7ddrphy_bitslip112 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip12 = 8'd0; +reg [7:0] main_a7ddrphy_bitslip120 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip121; +reg [7:0] main_a7ddrphy_bitslip122 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7; +wire [7:0] main_a7ddrphy_bitslip13; +reg [7:0] main_a7ddrphy_bitslip130 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip131; +reg [7:0] main_a7ddrphy_bitslip132 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip14 = 8'd0; +reg [7:0] main_a7ddrphy_bitslip140 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip141; +reg [7:0] main_a7ddrphy_bitslip142 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip150 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip151; +reg [7:0] main_a7ddrphy_bitslip152 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip20 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip21; +reg [7:0] main_a7ddrphy_bitslip22 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip30 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip31; +reg [7:0] main_a7ddrphy_bitslip32 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip40 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip41; +reg [7:0] main_a7ddrphy_bitslip42 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip50 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip51; +reg [7:0] main_a7ddrphy_bitslip52 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip60 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip61; +reg [7:0] main_a7ddrphy_bitslip62 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip70 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip71; +reg [7:0] main_a7ddrphy_bitslip72 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip80 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip81; +reg [7:0] main_a7ddrphy_bitslip82 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7; +reg [7:0] main_a7ddrphy_bitslip90 = 8'd0; +wire [7:0] main_a7ddrphy_bitslip91; +reg [7:0] main_a7ddrphy_bitslip92 = 8'd0; +reg [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0; +reg [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0; +reg [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7; +reg [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7; +wire main_a7ddrphy_dfi_p0_act_n; +wire [13:0] main_a7ddrphy_dfi_p0_address; +wire [2:0] main_a7ddrphy_dfi_p0_bank; +wire main_a7ddrphy_dfi_p0_cas_n; +wire main_a7ddrphy_dfi_p0_cke; +wire main_a7ddrphy_dfi_p0_cs_n; +wire main_a7ddrphy_dfi_p0_odt; +wire main_a7ddrphy_dfi_p0_ras_n; +reg [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0; +wire main_a7ddrphy_dfi_p0_rddata_en; +wire main_a7ddrphy_dfi_p0_rddata_valid; +wire main_a7ddrphy_dfi_p0_reset_n; +wire main_a7ddrphy_dfi_p0_we_n; +wire [31:0] main_a7ddrphy_dfi_p0_wrdata; +wire main_a7ddrphy_dfi_p0_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p0_wrdata_mask; +wire main_a7ddrphy_dfi_p1_act_n; +wire [13:0] main_a7ddrphy_dfi_p1_address; +wire [2:0] main_a7ddrphy_dfi_p1_bank; +wire main_a7ddrphy_dfi_p1_cas_n; +wire main_a7ddrphy_dfi_p1_cke; +wire main_a7ddrphy_dfi_p1_cs_n; +wire main_a7ddrphy_dfi_p1_odt; +wire main_a7ddrphy_dfi_p1_ras_n; +reg [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0; +wire main_a7ddrphy_dfi_p1_rddata_en; +wire main_a7ddrphy_dfi_p1_rddata_valid; +wire main_a7ddrphy_dfi_p1_reset_n; +wire main_a7ddrphy_dfi_p1_we_n; +wire [31:0] main_a7ddrphy_dfi_p1_wrdata; +wire main_a7ddrphy_dfi_p1_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p1_wrdata_mask; +wire main_a7ddrphy_dfi_p2_act_n; +wire [13:0] main_a7ddrphy_dfi_p2_address; +wire [2:0] main_a7ddrphy_dfi_p2_bank; +wire main_a7ddrphy_dfi_p2_cas_n; +wire main_a7ddrphy_dfi_p2_cke; +wire main_a7ddrphy_dfi_p2_cs_n; +wire main_a7ddrphy_dfi_p2_odt; +wire main_a7ddrphy_dfi_p2_ras_n; +reg [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0; +wire main_a7ddrphy_dfi_p2_rddata_en; +wire main_a7ddrphy_dfi_p2_rddata_valid; +wire main_a7ddrphy_dfi_p2_reset_n; +wire main_a7ddrphy_dfi_p2_we_n; +wire [31:0] main_a7ddrphy_dfi_p2_wrdata; +wire main_a7ddrphy_dfi_p2_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p2_wrdata_mask; +wire main_a7ddrphy_dfi_p3_act_n; +wire [13:0] main_a7ddrphy_dfi_p3_address; +wire [2:0] main_a7ddrphy_dfi_p3_bank; +wire main_a7ddrphy_dfi_p3_cas_n; +wire main_a7ddrphy_dfi_p3_cke; +wire main_a7ddrphy_dfi_p3_cs_n; +wire main_a7ddrphy_dfi_p3_odt; +wire main_a7ddrphy_dfi_p3_ras_n; +reg [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0; +wire main_a7ddrphy_dfi_p3_rddata_en; +wire main_a7ddrphy_dfi_p3_rddata_valid; +wire main_a7ddrphy_dfi_p3_reset_n; +wire main_a7ddrphy_dfi_p3_we_n; +wire [31:0] main_a7ddrphy_dfi_p3_wrdata; +wire main_a7ddrphy_dfi_p3_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p3_wrdata_mask; +reg main_a7ddrphy_dly_sel_re = 1'd0; +reg [1:0] main_a7ddrphy_dly_sel_storage = 2'd0; +wire main_a7ddrphy_dq_i_delayed0; +wire main_a7ddrphy_dq_i_delayed1; +wire main_a7ddrphy_dq_i_delayed10; +wire main_a7ddrphy_dq_i_delayed11; +wire main_a7ddrphy_dq_i_delayed12; +wire main_a7ddrphy_dq_i_delayed13; +wire main_a7ddrphy_dq_i_delayed14; +wire main_a7ddrphy_dq_i_delayed15; +wire main_a7ddrphy_dq_i_delayed2; +wire main_a7ddrphy_dq_i_delayed3; +wire main_a7ddrphy_dq_i_delayed4; +wire main_a7ddrphy_dq_i_delayed5; +wire main_a7ddrphy_dq_i_delayed6; +wire main_a7ddrphy_dq_i_delayed7; +wire main_a7ddrphy_dq_i_delayed8; +wire main_a7ddrphy_dq_i_delayed9; +wire main_a7ddrphy_dq_i_nodelay0; +wire main_a7ddrphy_dq_i_nodelay1; +wire main_a7ddrphy_dq_i_nodelay10; +wire main_a7ddrphy_dq_i_nodelay11; +wire main_a7ddrphy_dq_i_nodelay12; +wire main_a7ddrphy_dq_i_nodelay13; +wire main_a7ddrphy_dq_i_nodelay14; +wire main_a7ddrphy_dq_i_nodelay15; +wire main_a7ddrphy_dq_i_nodelay2; +wire main_a7ddrphy_dq_i_nodelay3; +wire main_a7ddrphy_dq_i_nodelay4; +wire main_a7ddrphy_dq_i_nodelay5; +wire main_a7ddrphy_dq_i_nodelay6; +wire main_a7ddrphy_dq_i_nodelay7; +wire main_a7ddrphy_dq_i_nodelay8; +wire main_a7ddrphy_dq_i_nodelay9; +wire main_a7ddrphy_dq_o_nodelay0; +wire main_a7ddrphy_dq_o_nodelay1; +wire main_a7ddrphy_dq_o_nodelay10; +wire main_a7ddrphy_dq_o_nodelay11; +wire main_a7ddrphy_dq_o_nodelay12; +wire main_a7ddrphy_dq_o_nodelay13; +wire main_a7ddrphy_dq_o_nodelay14; +wire main_a7ddrphy_dq_o_nodelay15; +wire main_a7ddrphy_dq_o_nodelay2; +wire main_a7ddrphy_dq_o_nodelay3; +wire main_a7ddrphy_dq_o_nodelay4; +wire main_a7ddrphy_dq_o_nodelay5; +wire main_a7ddrphy_dq_o_nodelay6; +wire main_a7ddrphy_dq_o_nodelay7; +wire main_a7ddrphy_dq_o_nodelay8; +wire main_a7ddrphy_dq_o_nodelay9; +wire main_a7ddrphy_dq_oe; +wire main_a7ddrphy_dq_oe_delay_tappeddelayline; +reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +wire main_a7ddrphy_dq_t0; +wire main_a7ddrphy_dq_t1; +wire main_a7ddrphy_dq_t10; +wire main_a7ddrphy_dq_t11; +wire main_a7ddrphy_dq_t12; +wire main_a7ddrphy_dq_t13; +wire main_a7ddrphy_dq_t14; +wire main_a7ddrphy_dq_t15; +wire main_a7ddrphy_dq_t2; +wire main_a7ddrphy_dq_t3; +wire main_a7ddrphy_dq_t4; +wire main_a7ddrphy_dq_t5; +wire main_a7ddrphy_dq_t6; +wire main_a7ddrphy_dq_t7; +wire main_a7ddrphy_dq_t8; +wire main_a7ddrphy_dq_t9; +wire main_a7ddrphy_dqs_o_no_delay0; +wire main_a7ddrphy_dqs_o_no_delay1; +reg main_a7ddrphy_dqs_oe = 1'd0; +wire main_a7ddrphy_dqs_oe_delay_tappeddelayline; +reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +wire main_a7ddrphy_dqs_postamble; +wire main_a7ddrphy_dqs_preamble; +wire main_a7ddrphy_dqs_t0; +wire main_a7ddrphy_dqs_t1; +reg main_a7ddrphy_dqspattern0 = 1'd0; +reg main_a7ddrphy_dqspattern1 = 1'd0; +reg [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0; +reg [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0; +reg main_a7ddrphy_half_sys8x_taps_re = 1'd0; +reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8; +wire [2:0] main_a7ddrphy_pads_ba; +reg main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; +wire main_a7ddrphy_rdly_dq_bitslip_r; +reg main_a7ddrphy_rdly_dq_bitslip_re = 1'd0; +wire main_a7ddrphy_rdly_dq_bitslip_rst_r; +reg main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_w = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_we = 1'd0; +wire main_a7ddrphy_rdly_dq_inc_r; +reg main_a7ddrphy_rdly_dq_inc_re = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_w = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_we = 1'd0; +wire main_a7ddrphy_rdly_dq_rst_r; +reg main_a7ddrphy_rdly_dq_rst_re = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_w = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_we = 1'd0; +reg main_a7ddrphy_rdphase_re = 1'd0; +reg [1:0] main_a7ddrphy_rdphase_storage = 2'd2; +reg main_a7ddrphy_rst_re = 1'd0; +reg main_a7ddrphy_rst_storage = 1'd0; +wire main_a7ddrphy_sd_clk_se_nodelay; +wire main_a7ddrphy_wdly_dq_bitslip_r; +reg main_a7ddrphy_wdly_dq_bitslip_re = 1'd0; +wire main_a7ddrphy_wdly_dq_bitslip_rst_r; +reg main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_w = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_we = 1'd0; +reg main_a7ddrphy_wlevel_en_re = 1'd0; +reg main_a7ddrphy_wlevel_en_storage = 1'd0; +wire main_a7ddrphy_wlevel_strobe_r; +reg main_a7ddrphy_wlevel_strobe_re = 1'd0; +reg main_a7ddrphy_wlevel_strobe_w = 1'd0; +reg main_a7ddrphy_wlevel_strobe_we = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +reg main_a7ddrphy_wrphase_re = 1'd0; +reg [1:0] main_a7ddrphy_wrphase_storage = 2'd3; +wire main_clkin; +wire main_clkout0; +wire main_clkout1; +wire main_clkout2; +wire main_clkout3; +wire main_clkout_buf0; +wire main_clkout_buf1; +wire main_clkout_buf2; +wire main_clkout_buf3; +reg main_ic_reset = 1'd1; +reg main_init_done_re = 1'd0; +reg main_init_done_storage = 1'd0; +reg main_init_error_re = 1'd0; +reg main_init_error_storage = 1'd0; +reg main_litedramcore_bankmachine0_auto_precharge = 1'd0; +reg [13:0] main_litedramcore_bankmachine0_cmd_payload_a = 14'd0; +wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba; +reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine0_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine0_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine0_consume = 4'd0; +wire main_litedramcore_bankmachine0_do_read; +wire main_litedramcore_bankmachine0_fifo_in_first; +wire main_litedramcore_bankmachine0_fifo_in_last; +wire [20:0] main_litedramcore_bankmachine0_fifo_in_payload_addr; +wire main_litedramcore_bankmachine0_fifo_in_payload_we; +wire main_litedramcore_bankmachine0_fifo_out_first; +wire main_litedramcore_bankmachine0_fifo_out_last; +wire [20:0] main_litedramcore_bankmachine0_fifo_out_payload_addr; +wire main_litedramcore_bankmachine0_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine0_level = 5'd0; +wire main_litedramcore_bankmachine0_pipe_valid_sink_first; +wire main_litedramcore_bankmachine0_pipe_valid_sink_last; +wire [20:0] main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine0_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine0_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine0_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine0_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine0_pipe_valid_source_last = 1'd0; +reg [20:0] main_litedramcore_bankmachine0_pipe_valid_source_payload_addr = 21'd0; +reg main_litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine0_pipe_valid_source_ready; +reg main_litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine0_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine0_rdport_adr; +wire [23:0] main_litedramcore_bankmachine0_rdport_dat_r; +reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine0_refresh_req; +reg main_litedramcore_bankmachine0_replace = 1'd0; +wire [20:0] main_litedramcore_bankmachine0_req_addr; +wire main_litedramcore_bankmachine0_req_lock; +reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine0_req_ready; +wire main_litedramcore_bankmachine0_req_valid; +reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine0_req_we; +reg [13:0] main_litedramcore_bankmachine0_row = 14'd0; +reg main_litedramcore_bankmachine0_row_close = 1'd0; +reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine0_row_hit; +reg main_litedramcore_bankmachine0_row_open = 1'd0; +reg main_litedramcore_bankmachine0_row_opened = 1'd0; +reg main_litedramcore_bankmachine0_sink_first = 1'd0; +reg main_litedramcore_bankmachine0_sink_last = 1'd0; +wire [20:0] main_litedramcore_bankmachine0_sink_payload_addr; +wire main_litedramcore_bankmachine0_sink_payload_we; +wire main_litedramcore_bankmachine0_sink_ready; +wire main_litedramcore_bankmachine0_sink_sink_first; +wire main_litedramcore_bankmachine0_sink_sink_last; +wire [20:0] main_litedramcore_bankmachine0_sink_sink_payload_addr; +wire main_litedramcore_bankmachine0_sink_sink_payload_we; +wire main_litedramcore_bankmachine0_sink_sink_ready; +wire main_litedramcore_bankmachine0_sink_sink_valid; +wire main_litedramcore_bankmachine0_sink_valid; +wire main_litedramcore_bankmachine0_source_first; +wire main_litedramcore_bankmachine0_source_last; +wire [20:0] main_litedramcore_bankmachine0_source_payload_addr; +wire main_litedramcore_bankmachine0_source_payload_we; +wire main_litedramcore_bankmachine0_source_ready; +wire main_litedramcore_bankmachine0_source_source_first; +wire main_litedramcore_bankmachine0_source_source_last; +wire [20:0] main_litedramcore_bankmachine0_source_source_payload_addr; +wire main_litedramcore_bankmachine0_source_source_payload_we; +wire main_litedramcore_bankmachine0_source_source_ready; +wire main_litedramcore_bankmachine0_source_source_valid; +wire main_litedramcore_bankmachine0_source_valid; +wire [23:0] main_litedramcore_bankmachine0_syncfifo0_din; +wire [23:0] main_litedramcore_bankmachine0_syncfifo0_dout; +wire main_litedramcore_bankmachine0_syncfifo0_re; +wire main_litedramcore_bankmachine0_syncfifo0_readable; +wire main_litedramcore_bankmachine0_syncfifo0_we; +wire main_litedramcore_bankmachine0_syncfifo0_writable; +reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; -wire litedramcore_bankmachine0_trccon_valid; +reg main_litedramcore_bankmachine0_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine0_trascon_valid; +reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0; -wire litedramcore_bankmachine0_trascon_valid; +reg main_litedramcore_bankmachine0_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine0_trccon_valid; +reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine0_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0; -wire litedramcore_bankmachine1_req_valid; -wire litedramcore_bankmachine1_req_ready; -wire litedramcore_bankmachine1_req_we; -wire [20:0] litedramcore_bankmachine1_req_addr; -wire litedramcore_bankmachine1_req_lock; -reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine1_refresh_req; -reg litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg litedramcore_bankmachine1_cmd_valid = 1'd0; -reg litedramcore_bankmachine1_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine1_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; -reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine1_auto_precharge = 1'd0; -wire litedramcore_bankmachine1_sink_valid; -wire litedramcore_bankmachine1_sink_ready; -reg litedramcore_bankmachine1_sink_first = 1'd0; -reg litedramcore_bankmachine1_sink_last = 1'd0; -wire litedramcore_bankmachine1_sink_payload_we; -wire [20:0] litedramcore_bankmachine1_sink_payload_addr; -wire litedramcore_bankmachine1_source_valid; -wire litedramcore_bankmachine1_source_ready; -wire litedramcore_bankmachine1_source_first; -wire litedramcore_bankmachine1_source_last; -wire litedramcore_bankmachine1_source_payload_we; -wire [20:0] litedramcore_bankmachine1_source_payload_addr; -wire litedramcore_bankmachine1_syncfifo1_we; -wire litedramcore_bankmachine1_syncfifo1_writable; -wire litedramcore_bankmachine1_syncfifo1_re; -wire litedramcore_bankmachine1_syncfifo1_readable; -wire [23:0] litedramcore_bankmachine1_syncfifo1_din; -wire [23:0] litedramcore_bankmachine1_syncfifo1_dout; -reg [4:0] litedramcore_bankmachine1_level = 5'd0; -reg litedramcore_bankmachine1_replace = 1'd0; -reg [3:0] litedramcore_bankmachine1_produce = 4'd0; -reg [3:0] litedramcore_bankmachine1_consume = 4'd0; -reg [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine1_wrport_dat_r; -wire litedramcore_bankmachine1_wrport_we; -wire [23:0] litedramcore_bankmachine1_wrport_dat_w; -wire litedramcore_bankmachine1_do_read; -wire [3:0] litedramcore_bankmachine1_rdport_adr; -wire [23:0] litedramcore_bankmachine1_rdport_dat_r; -wire litedramcore_bankmachine1_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine1_fifo_in_payload_addr; -wire litedramcore_bankmachine1_fifo_in_first; -wire litedramcore_bankmachine1_fifo_in_last; -wire litedramcore_bankmachine1_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine1_fifo_out_payload_addr; -wire litedramcore_bankmachine1_fifo_out_first; -wire litedramcore_bankmachine1_fifo_out_last; -wire litedramcore_bankmachine1_sink_sink_valid; -wire litedramcore_bankmachine1_sink_sink_ready; -wire litedramcore_bankmachine1_sink_sink_first; -wire litedramcore_bankmachine1_sink_sink_last; -wire litedramcore_bankmachine1_sink_sink_payload_we; -wire [20:0] litedramcore_bankmachine1_sink_sink_payload_addr; -wire litedramcore_bankmachine1_source_source_valid; -wire litedramcore_bankmachine1_source_source_ready; -wire litedramcore_bankmachine1_source_source_first; -wire litedramcore_bankmachine1_source_source_last; -wire litedramcore_bankmachine1_source_source_payload_we; -wire [20:0] litedramcore_bankmachine1_source_source_payload_addr; -wire litedramcore_bankmachine1_pipe_valid_sink_valid; -wire litedramcore_bankmachine1_pipe_valid_sink_ready; -wire litedramcore_bankmachine1_pipe_valid_sink_first; -wire litedramcore_bankmachine1_pipe_valid_sink_last; -wire litedramcore_bankmachine1_pipe_valid_sink_payload_we; -wire [20:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine1_pipe_valid_source_ready; -reg litedramcore_bankmachine1_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine1_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine1_row = 14'd0; -reg litedramcore_bankmachine1_row_opened = 1'd0; -wire litedramcore_bankmachine1_row_hit; -reg litedramcore_bankmachine1_row_open = 1'd0; -reg litedramcore_bankmachine1_row_close = 1'd0; -reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine1_twtpcon_valid; +reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine0_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine0_wrport_adr = 4'd0; +wire [23:0] main_litedramcore_bankmachine0_wrport_dat_r; +wire [23:0] main_litedramcore_bankmachine0_wrport_dat_w; +wire main_litedramcore_bankmachine0_wrport_we; +reg main_litedramcore_bankmachine1_auto_precharge = 1'd0; +reg [13:0] main_litedramcore_bankmachine1_cmd_payload_a = 14'd0; +wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba; +reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine1_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine1_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine1_consume = 4'd0; +wire main_litedramcore_bankmachine1_do_read; +wire main_litedramcore_bankmachine1_fifo_in_first; +wire main_litedramcore_bankmachine1_fifo_in_last; +wire [20:0] main_litedramcore_bankmachine1_fifo_in_payload_addr; +wire main_litedramcore_bankmachine1_fifo_in_payload_we; +wire main_litedramcore_bankmachine1_fifo_out_first; +wire main_litedramcore_bankmachine1_fifo_out_last; +wire [20:0] main_litedramcore_bankmachine1_fifo_out_payload_addr; +wire main_litedramcore_bankmachine1_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine1_level = 5'd0; +wire main_litedramcore_bankmachine1_pipe_valid_sink_first; +wire main_litedramcore_bankmachine1_pipe_valid_sink_last; +wire [20:0] main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine1_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine1_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine1_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine1_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine1_pipe_valid_source_last = 1'd0; +reg [20:0] main_litedramcore_bankmachine1_pipe_valid_source_payload_addr = 21'd0; +reg main_litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine1_pipe_valid_source_ready; +reg main_litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine1_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine1_rdport_adr; +wire [23:0] main_litedramcore_bankmachine1_rdport_dat_r; +reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine1_refresh_req; +reg main_litedramcore_bankmachine1_replace = 1'd0; +wire [20:0] main_litedramcore_bankmachine1_req_addr; +wire main_litedramcore_bankmachine1_req_lock; +reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine1_req_ready; +wire main_litedramcore_bankmachine1_req_valid; +reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine1_req_we; +reg [13:0] main_litedramcore_bankmachine1_row = 14'd0; +reg main_litedramcore_bankmachine1_row_close = 1'd0; +reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine1_row_hit; +reg main_litedramcore_bankmachine1_row_open = 1'd0; +reg main_litedramcore_bankmachine1_row_opened = 1'd0; +reg main_litedramcore_bankmachine1_sink_first = 1'd0; +reg main_litedramcore_bankmachine1_sink_last = 1'd0; +wire [20:0] main_litedramcore_bankmachine1_sink_payload_addr; +wire main_litedramcore_bankmachine1_sink_payload_we; +wire main_litedramcore_bankmachine1_sink_ready; +wire main_litedramcore_bankmachine1_sink_sink_first; +wire main_litedramcore_bankmachine1_sink_sink_last; +wire [20:0] main_litedramcore_bankmachine1_sink_sink_payload_addr; +wire main_litedramcore_bankmachine1_sink_sink_payload_we; +wire main_litedramcore_bankmachine1_sink_sink_ready; +wire main_litedramcore_bankmachine1_sink_sink_valid; +wire main_litedramcore_bankmachine1_sink_valid; +wire main_litedramcore_bankmachine1_source_first; +wire main_litedramcore_bankmachine1_source_last; +wire [20:0] main_litedramcore_bankmachine1_source_payload_addr; +wire main_litedramcore_bankmachine1_source_payload_we; +wire main_litedramcore_bankmachine1_source_ready; +wire main_litedramcore_bankmachine1_source_source_first; +wire main_litedramcore_bankmachine1_source_source_last; +wire [20:0] main_litedramcore_bankmachine1_source_source_payload_addr; +wire main_litedramcore_bankmachine1_source_source_payload_we; +wire main_litedramcore_bankmachine1_source_source_ready; +wire main_litedramcore_bankmachine1_source_source_valid; +wire main_litedramcore_bankmachine1_source_valid; +wire [23:0] main_litedramcore_bankmachine1_syncfifo1_din; +wire [23:0] main_litedramcore_bankmachine1_syncfifo1_dout; +wire main_litedramcore_bankmachine1_syncfifo1_re; +wire main_litedramcore_bankmachine1_syncfifo1_readable; +wire main_litedramcore_bankmachine1_syncfifo1_we; +wire main_litedramcore_bankmachine1_syncfifo1_writable; +reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; -wire litedramcore_bankmachine1_trccon_valid; +reg main_litedramcore_bankmachine1_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine1_trascon_valid; +reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0; -wire litedramcore_bankmachine1_trascon_valid; +reg main_litedramcore_bankmachine1_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine1_trccon_valid; +reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine1_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0; -wire litedramcore_bankmachine2_req_valid; -wire litedramcore_bankmachine2_req_ready; -wire litedramcore_bankmachine2_req_we; -wire [20:0] litedramcore_bankmachine2_req_addr; -wire litedramcore_bankmachine2_req_lock; -reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine2_refresh_req; -reg litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg litedramcore_bankmachine2_cmd_valid = 1'd0; -reg litedramcore_bankmachine2_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine2_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; -reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine2_auto_precharge = 1'd0; -wire litedramcore_bankmachine2_sink_valid; -wire litedramcore_bankmachine2_sink_ready; -reg litedramcore_bankmachine2_sink_first = 1'd0; -reg litedramcore_bankmachine2_sink_last = 1'd0; -wire litedramcore_bankmachine2_sink_payload_we; -wire [20:0] litedramcore_bankmachine2_sink_payload_addr; -wire litedramcore_bankmachine2_source_valid; -wire litedramcore_bankmachine2_source_ready; -wire litedramcore_bankmachine2_source_first; -wire litedramcore_bankmachine2_source_last; -wire litedramcore_bankmachine2_source_payload_we; -wire [20:0] litedramcore_bankmachine2_source_payload_addr; -wire litedramcore_bankmachine2_syncfifo2_we; -wire litedramcore_bankmachine2_syncfifo2_writable; -wire litedramcore_bankmachine2_syncfifo2_re; -wire litedramcore_bankmachine2_syncfifo2_readable; -wire [23:0] litedramcore_bankmachine2_syncfifo2_din; -wire [23:0] litedramcore_bankmachine2_syncfifo2_dout; -reg [4:0] litedramcore_bankmachine2_level = 5'd0; -reg litedramcore_bankmachine2_replace = 1'd0; -reg [3:0] litedramcore_bankmachine2_produce = 4'd0; -reg [3:0] litedramcore_bankmachine2_consume = 4'd0; -reg [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine2_wrport_dat_r; -wire litedramcore_bankmachine2_wrport_we; -wire [23:0] litedramcore_bankmachine2_wrport_dat_w; -wire litedramcore_bankmachine2_do_read; -wire [3:0] litedramcore_bankmachine2_rdport_adr; -wire [23:0] litedramcore_bankmachine2_rdport_dat_r; -wire litedramcore_bankmachine2_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine2_fifo_in_payload_addr; -wire litedramcore_bankmachine2_fifo_in_first; -wire litedramcore_bankmachine2_fifo_in_last; -wire litedramcore_bankmachine2_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine2_fifo_out_payload_addr; -wire litedramcore_bankmachine2_fifo_out_first; -wire litedramcore_bankmachine2_fifo_out_last; -wire litedramcore_bankmachine2_sink_sink_valid; -wire litedramcore_bankmachine2_sink_sink_ready; -wire litedramcore_bankmachine2_sink_sink_first; -wire litedramcore_bankmachine2_sink_sink_last; -wire litedramcore_bankmachine2_sink_sink_payload_we; -wire [20:0] litedramcore_bankmachine2_sink_sink_payload_addr; -wire litedramcore_bankmachine2_source_source_valid; -wire litedramcore_bankmachine2_source_source_ready; -wire litedramcore_bankmachine2_source_source_first; -wire litedramcore_bankmachine2_source_source_last; -wire litedramcore_bankmachine2_source_source_payload_we; -wire [20:0] litedramcore_bankmachine2_source_source_payload_addr; -wire litedramcore_bankmachine2_pipe_valid_sink_valid; -wire litedramcore_bankmachine2_pipe_valid_sink_ready; -wire litedramcore_bankmachine2_pipe_valid_sink_first; -wire litedramcore_bankmachine2_pipe_valid_sink_last; -wire litedramcore_bankmachine2_pipe_valid_sink_payload_we; -wire [20:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine2_pipe_valid_source_ready; -reg litedramcore_bankmachine2_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine2_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine2_row = 14'd0; -reg litedramcore_bankmachine2_row_opened = 1'd0; -wire litedramcore_bankmachine2_row_hit; -reg litedramcore_bankmachine2_row_open = 1'd0; -reg litedramcore_bankmachine2_row_close = 1'd0; -reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine2_twtpcon_valid; +reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine1_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine1_wrport_adr = 4'd0; +wire [23:0] main_litedramcore_bankmachine1_wrport_dat_r; +wire [23:0] main_litedramcore_bankmachine1_wrport_dat_w; +wire main_litedramcore_bankmachine1_wrport_we; +reg main_litedramcore_bankmachine2_auto_precharge = 1'd0; +reg [13:0] main_litedramcore_bankmachine2_cmd_payload_a = 14'd0; +wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba; +reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine2_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine2_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine2_consume = 4'd0; +wire main_litedramcore_bankmachine2_do_read; +wire main_litedramcore_bankmachine2_fifo_in_first; +wire main_litedramcore_bankmachine2_fifo_in_last; +wire [20:0] main_litedramcore_bankmachine2_fifo_in_payload_addr; +wire main_litedramcore_bankmachine2_fifo_in_payload_we; +wire main_litedramcore_bankmachine2_fifo_out_first; +wire main_litedramcore_bankmachine2_fifo_out_last; +wire [20:0] main_litedramcore_bankmachine2_fifo_out_payload_addr; +wire main_litedramcore_bankmachine2_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine2_level = 5'd0; +wire main_litedramcore_bankmachine2_pipe_valid_sink_first; +wire main_litedramcore_bankmachine2_pipe_valid_sink_last; +wire [20:0] main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine2_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine2_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine2_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine2_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine2_pipe_valid_source_last = 1'd0; +reg [20:0] main_litedramcore_bankmachine2_pipe_valid_source_payload_addr = 21'd0; +reg main_litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine2_pipe_valid_source_ready; +reg main_litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine2_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine2_rdport_adr; +wire [23:0] main_litedramcore_bankmachine2_rdport_dat_r; +reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine2_refresh_req; +reg main_litedramcore_bankmachine2_replace = 1'd0; +wire [20:0] main_litedramcore_bankmachine2_req_addr; +wire main_litedramcore_bankmachine2_req_lock; +reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine2_req_ready; +wire main_litedramcore_bankmachine2_req_valid; +reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine2_req_we; +reg [13:0] main_litedramcore_bankmachine2_row = 14'd0; +reg main_litedramcore_bankmachine2_row_close = 1'd0; +reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine2_row_hit; +reg main_litedramcore_bankmachine2_row_open = 1'd0; +reg main_litedramcore_bankmachine2_row_opened = 1'd0; +reg main_litedramcore_bankmachine2_sink_first = 1'd0; +reg main_litedramcore_bankmachine2_sink_last = 1'd0; +wire [20:0] main_litedramcore_bankmachine2_sink_payload_addr; +wire main_litedramcore_bankmachine2_sink_payload_we; +wire main_litedramcore_bankmachine2_sink_ready; +wire main_litedramcore_bankmachine2_sink_sink_first; +wire main_litedramcore_bankmachine2_sink_sink_last; +wire [20:0] main_litedramcore_bankmachine2_sink_sink_payload_addr; +wire main_litedramcore_bankmachine2_sink_sink_payload_we; +wire main_litedramcore_bankmachine2_sink_sink_ready; +wire main_litedramcore_bankmachine2_sink_sink_valid; +wire main_litedramcore_bankmachine2_sink_valid; +wire main_litedramcore_bankmachine2_source_first; +wire main_litedramcore_bankmachine2_source_last; +wire [20:0] main_litedramcore_bankmachine2_source_payload_addr; +wire main_litedramcore_bankmachine2_source_payload_we; +wire main_litedramcore_bankmachine2_source_ready; +wire main_litedramcore_bankmachine2_source_source_first; +wire main_litedramcore_bankmachine2_source_source_last; +wire [20:0] main_litedramcore_bankmachine2_source_source_payload_addr; +wire main_litedramcore_bankmachine2_source_source_payload_we; +wire main_litedramcore_bankmachine2_source_source_ready; +wire main_litedramcore_bankmachine2_source_source_valid; +wire main_litedramcore_bankmachine2_source_valid; +wire [23:0] main_litedramcore_bankmachine2_syncfifo2_din; +wire [23:0] main_litedramcore_bankmachine2_syncfifo2_dout; +wire main_litedramcore_bankmachine2_syncfifo2_re; +wire main_litedramcore_bankmachine2_syncfifo2_readable; +wire main_litedramcore_bankmachine2_syncfifo2_we; +wire main_litedramcore_bankmachine2_syncfifo2_writable; +reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; -wire litedramcore_bankmachine2_trccon_valid; +reg main_litedramcore_bankmachine2_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine2_trascon_valid; +reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0; -wire litedramcore_bankmachine2_trascon_valid; +reg main_litedramcore_bankmachine2_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine2_trccon_valid; +reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine2_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0; -wire litedramcore_bankmachine3_req_valid; -wire litedramcore_bankmachine3_req_ready; -wire litedramcore_bankmachine3_req_we; -wire [20:0] litedramcore_bankmachine3_req_addr; -wire litedramcore_bankmachine3_req_lock; -reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine3_refresh_req; -reg litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg litedramcore_bankmachine3_cmd_valid = 1'd0; -reg litedramcore_bankmachine3_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine3_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; -reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine3_auto_precharge = 1'd0; -wire litedramcore_bankmachine3_sink_valid; -wire litedramcore_bankmachine3_sink_ready; -reg litedramcore_bankmachine3_sink_first = 1'd0; -reg litedramcore_bankmachine3_sink_last = 1'd0; -wire litedramcore_bankmachine3_sink_payload_we; -wire [20:0] litedramcore_bankmachine3_sink_payload_addr; -wire litedramcore_bankmachine3_source_valid; -wire litedramcore_bankmachine3_source_ready; -wire litedramcore_bankmachine3_source_first; -wire litedramcore_bankmachine3_source_last; -wire litedramcore_bankmachine3_source_payload_we; -wire [20:0] litedramcore_bankmachine3_source_payload_addr; -wire litedramcore_bankmachine3_syncfifo3_we; -wire litedramcore_bankmachine3_syncfifo3_writable; -wire litedramcore_bankmachine3_syncfifo3_re; -wire litedramcore_bankmachine3_syncfifo3_readable; -wire [23:0] litedramcore_bankmachine3_syncfifo3_din; -wire [23:0] litedramcore_bankmachine3_syncfifo3_dout; -reg [4:0] litedramcore_bankmachine3_level = 5'd0; -reg litedramcore_bankmachine3_replace = 1'd0; -reg [3:0] litedramcore_bankmachine3_produce = 4'd0; -reg [3:0] litedramcore_bankmachine3_consume = 4'd0; -reg [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine3_wrport_dat_r; -wire litedramcore_bankmachine3_wrport_we; -wire [23:0] litedramcore_bankmachine3_wrport_dat_w; -wire litedramcore_bankmachine3_do_read; -wire [3:0] litedramcore_bankmachine3_rdport_adr; -wire [23:0] litedramcore_bankmachine3_rdport_dat_r; -wire litedramcore_bankmachine3_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine3_fifo_in_payload_addr; -wire litedramcore_bankmachine3_fifo_in_first; -wire litedramcore_bankmachine3_fifo_in_last; -wire litedramcore_bankmachine3_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine3_fifo_out_payload_addr; -wire litedramcore_bankmachine3_fifo_out_first; -wire litedramcore_bankmachine3_fifo_out_last; -wire litedramcore_bankmachine3_sink_sink_valid; -wire litedramcore_bankmachine3_sink_sink_ready; -wire litedramcore_bankmachine3_sink_sink_first; -wire litedramcore_bankmachine3_sink_sink_last; -wire litedramcore_bankmachine3_sink_sink_payload_we; -wire [20:0] litedramcore_bankmachine3_sink_sink_payload_addr; -wire litedramcore_bankmachine3_source_source_valid; -wire litedramcore_bankmachine3_source_source_ready; -wire litedramcore_bankmachine3_source_source_first; -wire litedramcore_bankmachine3_source_source_last; -wire litedramcore_bankmachine3_source_source_payload_we; -wire [20:0] litedramcore_bankmachine3_source_source_payload_addr; -wire litedramcore_bankmachine3_pipe_valid_sink_valid; -wire litedramcore_bankmachine3_pipe_valid_sink_ready; -wire litedramcore_bankmachine3_pipe_valid_sink_first; -wire litedramcore_bankmachine3_pipe_valid_sink_last; -wire litedramcore_bankmachine3_pipe_valid_sink_payload_we; -wire [20:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine3_pipe_valid_source_ready; -reg litedramcore_bankmachine3_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine3_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine3_row = 14'd0; -reg litedramcore_bankmachine3_row_opened = 1'd0; -wire litedramcore_bankmachine3_row_hit; -reg litedramcore_bankmachine3_row_open = 1'd0; -reg litedramcore_bankmachine3_row_close = 1'd0; -reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine3_twtpcon_valid; +reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine2_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine2_wrport_adr = 4'd0; +wire [23:0] main_litedramcore_bankmachine2_wrport_dat_r; +wire [23:0] main_litedramcore_bankmachine2_wrport_dat_w; +wire main_litedramcore_bankmachine2_wrport_we; +reg main_litedramcore_bankmachine3_auto_precharge = 1'd0; +reg [13:0] main_litedramcore_bankmachine3_cmd_payload_a = 14'd0; +wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba; +reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine3_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine3_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine3_consume = 4'd0; +wire main_litedramcore_bankmachine3_do_read; +wire main_litedramcore_bankmachine3_fifo_in_first; +wire main_litedramcore_bankmachine3_fifo_in_last; +wire [20:0] main_litedramcore_bankmachine3_fifo_in_payload_addr; +wire main_litedramcore_bankmachine3_fifo_in_payload_we; +wire main_litedramcore_bankmachine3_fifo_out_first; +wire main_litedramcore_bankmachine3_fifo_out_last; +wire [20:0] main_litedramcore_bankmachine3_fifo_out_payload_addr; +wire main_litedramcore_bankmachine3_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine3_level = 5'd0; +wire main_litedramcore_bankmachine3_pipe_valid_sink_first; +wire main_litedramcore_bankmachine3_pipe_valid_sink_last; +wire [20:0] main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine3_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine3_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine3_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine3_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine3_pipe_valid_source_last = 1'd0; +reg [20:0] main_litedramcore_bankmachine3_pipe_valid_source_payload_addr = 21'd0; +reg main_litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine3_pipe_valid_source_ready; +reg main_litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine3_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine3_rdport_adr; +wire [23:0] main_litedramcore_bankmachine3_rdport_dat_r; +reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine3_refresh_req; +reg main_litedramcore_bankmachine3_replace = 1'd0; +wire [20:0] main_litedramcore_bankmachine3_req_addr; +wire main_litedramcore_bankmachine3_req_lock; +reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine3_req_ready; +wire main_litedramcore_bankmachine3_req_valid; +reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine3_req_we; +reg [13:0] main_litedramcore_bankmachine3_row = 14'd0; +reg main_litedramcore_bankmachine3_row_close = 1'd0; +reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine3_row_hit; +reg main_litedramcore_bankmachine3_row_open = 1'd0; +reg main_litedramcore_bankmachine3_row_opened = 1'd0; +reg main_litedramcore_bankmachine3_sink_first = 1'd0; +reg main_litedramcore_bankmachine3_sink_last = 1'd0; +wire [20:0] main_litedramcore_bankmachine3_sink_payload_addr; +wire main_litedramcore_bankmachine3_sink_payload_we; +wire main_litedramcore_bankmachine3_sink_ready; +wire main_litedramcore_bankmachine3_sink_sink_first; +wire main_litedramcore_bankmachine3_sink_sink_last; +wire [20:0] main_litedramcore_bankmachine3_sink_sink_payload_addr; +wire main_litedramcore_bankmachine3_sink_sink_payload_we; +wire main_litedramcore_bankmachine3_sink_sink_ready; +wire main_litedramcore_bankmachine3_sink_sink_valid; +wire main_litedramcore_bankmachine3_sink_valid; +wire main_litedramcore_bankmachine3_source_first; +wire main_litedramcore_bankmachine3_source_last; +wire [20:0] main_litedramcore_bankmachine3_source_payload_addr; +wire main_litedramcore_bankmachine3_source_payload_we; +wire main_litedramcore_bankmachine3_source_ready; +wire main_litedramcore_bankmachine3_source_source_first; +wire main_litedramcore_bankmachine3_source_source_last; +wire [20:0] main_litedramcore_bankmachine3_source_source_payload_addr; +wire main_litedramcore_bankmachine3_source_source_payload_we; +wire main_litedramcore_bankmachine3_source_source_ready; +wire main_litedramcore_bankmachine3_source_source_valid; +wire main_litedramcore_bankmachine3_source_valid; +wire [23:0] main_litedramcore_bankmachine3_syncfifo3_din; +wire [23:0] main_litedramcore_bankmachine3_syncfifo3_dout; +wire main_litedramcore_bankmachine3_syncfifo3_re; +wire main_litedramcore_bankmachine3_syncfifo3_readable; +wire main_litedramcore_bankmachine3_syncfifo3_we; +wire main_litedramcore_bankmachine3_syncfifo3_writable; +reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; -wire litedramcore_bankmachine3_trccon_valid; +reg main_litedramcore_bankmachine3_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine3_trascon_valid; +reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0; -wire litedramcore_bankmachine3_trascon_valid; +reg main_litedramcore_bankmachine3_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine3_trccon_valid; +reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine3_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0; -wire litedramcore_bankmachine4_req_valid; -wire litedramcore_bankmachine4_req_ready; -wire litedramcore_bankmachine4_req_we; -wire [20:0] litedramcore_bankmachine4_req_addr; -wire litedramcore_bankmachine4_req_lock; -reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine4_refresh_req; -reg litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg litedramcore_bankmachine4_cmd_valid = 1'd0; -reg litedramcore_bankmachine4_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine4_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; -reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine4_auto_precharge = 1'd0; -wire litedramcore_bankmachine4_sink_valid; -wire litedramcore_bankmachine4_sink_ready; -reg litedramcore_bankmachine4_sink_first = 1'd0; -reg litedramcore_bankmachine4_sink_last = 1'd0; -wire litedramcore_bankmachine4_sink_payload_we; -wire [20:0] litedramcore_bankmachine4_sink_payload_addr; -wire litedramcore_bankmachine4_source_valid; -wire litedramcore_bankmachine4_source_ready; -wire litedramcore_bankmachine4_source_first; -wire litedramcore_bankmachine4_source_last; -wire litedramcore_bankmachine4_source_payload_we; -wire [20:0] litedramcore_bankmachine4_source_payload_addr; -wire litedramcore_bankmachine4_syncfifo4_we; -wire litedramcore_bankmachine4_syncfifo4_writable; -wire litedramcore_bankmachine4_syncfifo4_re; -wire litedramcore_bankmachine4_syncfifo4_readable; -wire [23:0] litedramcore_bankmachine4_syncfifo4_din; -wire [23:0] litedramcore_bankmachine4_syncfifo4_dout; -reg [4:0] litedramcore_bankmachine4_level = 5'd0; -reg litedramcore_bankmachine4_replace = 1'd0; -reg [3:0] litedramcore_bankmachine4_produce = 4'd0; -reg [3:0] litedramcore_bankmachine4_consume = 4'd0; -reg [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine4_wrport_dat_r; -wire litedramcore_bankmachine4_wrport_we; -wire [23:0] litedramcore_bankmachine4_wrport_dat_w; -wire litedramcore_bankmachine4_do_read; -wire [3:0] litedramcore_bankmachine4_rdport_adr; -wire [23:0] litedramcore_bankmachine4_rdport_dat_r; -wire litedramcore_bankmachine4_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine4_fifo_in_payload_addr; -wire litedramcore_bankmachine4_fifo_in_first; -wire litedramcore_bankmachine4_fifo_in_last; -wire litedramcore_bankmachine4_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine4_fifo_out_payload_addr; -wire litedramcore_bankmachine4_fifo_out_first; -wire litedramcore_bankmachine4_fifo_out_last; -wire litedramcore_bankmachine4_sink_sink_valid; -wire litedramcore_bankmachine4_sink_sink_ready; -wire litedramcore_bankmachine4_sink_sink_first; -wire litedramcore_bankmachine4_sink_sink_last; -wire litedramcore_bankmachine4_sink_sink_payload_we; -wire [20:0] litedramcore_bankmachine4_sink_sink_payload_addr; -wire litedramcore_bankmachine4_source_source_valid; -wire litedramcore_bankmachine4_source_source_ready; -wire litedramcore_bankmachine4_source_source_first; -wire litedramcore_bankmachine4_source_source_last; -wire litedramcore_bankmachine4_source_source_payload_we; -wire [20:0] litedramcore_bankmachine4_source_source_payload_addr; -wire litedramcore_bankmachine4_pipe_valid_sink_valid; -wire litedramcore_bankmachine4_pipe_valid_sink_ready; -wire litedramcore_bankmachine4_pipe_valid_sink_first; -wire litedramcore_bankmachine4_pipe_valid_sink_last; -wire litedramcore_bankmachine4_pipe_valid_sink_payload_we; -wire [20:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine4_pipe_valid_source_ready; -reg litedramcore_bankmachine4_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine4_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine4_row = 14'd0; -reg litedramcore_bankmachine4_row_opened = 1'd0; -wire litedramcore_bankmachine4_row_hit; -reg litedramcore_bankmachine4_row_open = 1'd0; -reg litedramcore_bankmachine4_row_close = 1'd0; -reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine4_twtpcon_valid; +reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine3_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine3_wrport_adr = 4'd0; +wire [23:0] main_litedramcore_bankmachine3_wrport_dat_r; +wire [23:0] main_litedramcore_bankmachine3_wrport_dat_w; +wire main_litedramcore_bankmachine3_wrport_we; +reg main_litedramcore_bankmachine4_auto_precharge = 1'd0; +reg [13:0] main_litedramcore_bankmachine4_cmd_payload_a = 14'd0; +wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba; +reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine4_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine4_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine4_consume = 4'd0; +wire main_litedramcore_bankmachine4_do_read; +wire main_litedramcore_bankmachine4_fifo_in_first; +wire main_litedramcore_bankmachine4_fifo_in_last; +wire [20:0] main_litedramcore_bankmachine4_fifo_in_payload_addr; +wire main_litedramcore_bankmachine4_fifo_in_payload_we; +wire main_litedramcore_bankmachine4_fifo_out_first; +wire main_litedramcore_bankmachine4_fifo_out_last; +wire [20:0] main_litedramcore_bankmachine4_fifo_out_payload_addr; +wire main_litedramcore_bankmachine4_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine4_level = 5'd0; +wire main_litedramcore_bankmachine4_pipe_valid_sink_first; +wire main_litedramcore_bankmachine4_pipe_valid_sink_last; +wire [20:0] main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine4_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine4_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine4_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine4_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine4_pipe_valid_source_last = 1'd0; +reg [20:0] main_litedramcore_bankmachine4_pipe_valid_source_payload_addr = 21'd0; +reg main_litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine4_pipe_valid_source_ready; +reg main_litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine4_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine4_rdport_adr; +wire [23:0] main_litedramcore_bankmachine4_rdport_dat_r; +reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine4_refresh_req; +reg main_litedramcore_bankmachine4_replace = 1'd0; +wire [20:0] main_litedramcore_bankmachine4_req_addr; +wire main_litedramcore_bankmachine4_req_lock; +reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine4_req_ready; +wire main_litedramcore_bankmachine4_req_valid; +reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine4_req_we; +reg [13:0] main_litedramcore_bankmachine4_row = 14'd0; +reg main_litedramcore_bankmachine4_row_close = 1'd0; +reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine4_row_hit; +reg main_litedramcore_bankmachine4_row_open = 1'd0; +reg main_litedramcore_bankmachine4_row_opened = 1'd0; +reg main_litedramcore_bankmachine4_sink_first = 1'd0; +reg main_litedramcore_bankmachine4_sink_last = 1'd0; +wire [20:0] main_litedramcore_bankmachine4_sink_payload_addr; +wire main_litedramcore_bankmachine4_sink_payload_we; +wire main_litedramcore_bankmachine4_sink_ready; +wire main_litedramcore_bankmachine4_sink_sink_first; +wire main_litedramcore_bankmachine4_sink_sink_last; +wire [20:0] main_litedramcore_bankmachine4_sink_sink_payload_addr; +wire main_litedramcore_bankmachine4_sink_sink_payload_we; +wire main_litedramcore_bankmachine4_sink_sink_ready; +wire main_litedramcore_bankmachine4_sink_sink_valid; +wire main_litedramcore_bankmachine4_sink_valid; +wire main_litedramcore_bankmachine4_source_first; +wire main_litedramcore_bankmachine4_source_last; +wire [20:0] main_litedramcore_bankmachine4_source_payload_addr; +wire main_litedramcore_bankmachine4_source_payload_we; +wire main_litedramcore_bankmachine4_source_ready; +wire main_litedramcore_bankmachine4_source_source_first; +wire main_litedramcore_bankmachine4_source_source_last; +wire [20:0] main_litedramcore_bankmachine4_source_source_payload_addr; +wire main_litedramcore_bankmachine4_source_source_payload_we; +wire main_litedramcore_bankmachine4_source_source_ready; +wire main_litedramcore_bankmachine4_source_source_valid; +wire main_litedramcore_bankmachine4_source_valid; +wire [23:0] main_litedramcore_bankmachine4_syncfifo4_din; +wire [23:0] main_litedramcore_bankmachine4_syncfifo4_dout; +wire main_litedramcore_bankmachine4_syncfifo4_re; +wire main_litedramcore_bankmachine4_syncfifo4_readable; +wire main_litedramcore_bankmachine4_syncfifo4_we; +wire main_litedramcore_bankmachine4_syncfifo4_writable; +reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; -wire litedramcore_bankmachine4_trccon_valid; +reg main_litedramcore_bankmachine4_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine4_trascon_valid; +reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0; -wire litedramcore_bankmachine4_trascon_valid; +reg main_litedramcore_bankmachine4_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine4_trccon_valid; +reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine4_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0; -wire litedramcore_bankmachine5_req_valid; -wire litedramcore_bankmachine5_req_ready; -wire litedramcore_bankmachine5_req_we; -wire [20:0] litedramcore_bankmachine5_req_addr; -wire litedramcore_bankmachine5_req_lock; -reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine5_refresh_req; -reg litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg litedramcore_bankmachine5_cmd_valid = 1'd0; -reg litedramcore_bankmachine5_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine5_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; -reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine5_auto_precharge = 1'd0; -wire litedramcore_bankmachine5_sink_valid; -wire litedramcore_bankmachine5_sink_ready; -reg litedramcore_bankmachine5_sink_first = 1'd0; -reg litedramcore_bankmachine5_sink_last = 1'd0; -wire litedramcore_bankmachine5_sink_payload_we; -wire [20:0] litedramcore_bankmachine5_sink_payload_addr; -wire litedramcore_bankmachine5_source_valid; -wire litedramcore_bankmachine5_source_ready; -wire litedramcore_bankmachine5_source_first; -wire litedramcore_bankmachine5_source_last; -wire litedramcore_bankmachine5_source_payload_we; -wire [20:0] litedramcore_bankmachine5_source_payload_addr; -wire litedramcore_bankmachine5_syncfifo5_we; -wire litedramcore_bankmachine5_syncfifo5_writable; -wire litedramcore_bankmachine5_syncfifo5_re; -wire litedramcore_bankmachine5_syncfifo5_readable; -wire [23:0] litedramcore_bankmachine5_syncfifo5_din; -wire [23:0] litedramcore_bankmachine5_syncfifo5_dout; -reg [4:0] litedramcore_bankmachine5_level = 5'd0; -reg litedramcore_bankmachine5_replace = 1'd0; -reg [3:0] litedramcore_bankmachine5_produce = 4'd0; -reg [3:0] litedramcore_bankmachine5_consume = 4'd0; -reg [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine5_wrport_dat_r; -wire litedramcore_bankmachine5_wrport_we; -wire [23:0] litedramcore_bankmachine5_wrport_dat_w; -wire litedramcore_bankmachine5_do_read; -wire [3:0] litedramcore_bankmachine5_rdport_adr; -wire [23:0] litedramcore_bankmachine5_rdport_dat_r; -wire litedramcore_bankmachine5_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine5_fifo_in_payload_addr; -wire litedramcore_bankmachine5_fifo_in_first; -wire litedramcore_bankmachine5_fifo_in_last; -wire litedramcore_bankmachine5_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine5_fifo_out_payload_addr; -wire litedramcore_bankmachine5_fifo_out_first; -wire litedramcore_bankmachine5_fifo_out_last; -wire litedramcore_bankmachine5_sink_sink_valid; -wire litedramcore_bankmachine5_sink_sink_ready; -wire litedramcore_bankmachine5_sink_sink_first; -wire litedramcore_bankmachine5_sink_sink_last; -wire litedramcore_bankmachine5_sink_sink_payload_we; -wire [20:0] litedramcore_bankmachine5_sink_sink_payload_addr; -wire litedramcore_bankmachine5_source_source_valid; -wire litedramcore_bankmachine5_source_source_ready; -wire litedramcore_bankmachine5_source_source_first; -wire litedramcore_bankmachine5_source_source_last; -wire litedramcore_bankmachine5_source_source_payload_we; -wire [20:0] litedramcore_bankmachine5_source_source_payload_addr; -wire litedramcore_bankmachine5_pipe_valid_sink_valid; -wire litedramcore_bankmachine5_pipe_valid_sink_ready; -wire litedramcore_bankmachine5_pipe_valid_sink_first; -wire litedramcore_bankmachine5_pipe_valid_sink_last; -wire litedramcore_bankmachine5_pipe_valid_sink_payload_we; -wire [20:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine5_pipe_valid_source_ready; -reg litedramcore_bankmachine5_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine5_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine5_row = 14'd0; -reg litedramcore_bankmachine5_row_opened = 1'd0; -wire litedramcore_bankmachine5_row_hit; -reg litedramcore_bankmachine5_row_open = 1'd0; -reg litedramcore_bankmachine5_row_close = 1'd0; -reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine5_twtpcon_valid; +reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine4_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine4_wrport_adr = 4'd0; +wire [23:0] main_litedramcore_bankmachine4_wrport_dat_r; +wire [23:0] main_litedramcore_bankmachine4_wrport_dat_w; +wire main_litedramcore_bankmachine4_wrport_we; +reg main_litedramcore_bankmachine5_auto_precharge = 1'd0; +reg [13:0] main_litedramcore_bankmachine5_cmd_payload_a = 14'd0; +wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba; +reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine5_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine5_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine5_consume = 4'd0; +wire main_litedramcore_bankmachine5_do_read; +wire main_litedramcore_bankmachine5_fifo_in_first; +wire main_litedramcore_bankmachine5_fifo_in_last; +wire [20:0] main_litedramcore_bankmachine5_fifo_in_payload_addr; +wire main_litedramcore_bankmachine5_fifo_in_payload_we; +wire main_litedramcore_bankmachine5_fifo_out_first; +wire main_litedramcore_bankmachine5_fifo_out_last; +wire [20:0] main_litedramcore_bankmachine5_fifo_out_payload_addr; +wire main_litedramcore_bankmachine5_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine5_level = 5'd0; +wire main_litedramcore_bankmachine5_pipe_valid_sink_first; +wire main_litedramcore_bankmachine5_pipe_valid_sink_last; +wire [20:0] main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine5_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine5_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine5_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine5_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine5_pipe_valid_source_last = 1'd0; +reg [20:0] main_litedramcore_bankmachine5_pipe_valid_source_payload_addr = 21'd0; +reg main_litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine5_pipe_valid_source_ready; +reg main_litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine5_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine5_rdport_adr; +wire [23:0] main_litedramcore_bankmachine5_rdport_dat_r; +reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine5_refresh_req; +reg main_litedramcore_bankmachine5_replace = 1'd0; +wire [20:0] main_litedramcore_bankmachine5_req_addr; +wire main_litedramcore_bankmachine5_req_lock; +reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine5_req_ready; +wire main_litedramcore_bankmachine5_req_valid; +reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine5_req_we; +reg [13:0] main_litedramcore_bankmachine5_row = 14'd0; +reg main_litedramcore_bankmachine5_row_close = 1'd0; +reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine5_row_hit; +reg main_litedramcore_bankmachine5_row_open = 1'd0; +reg main_litedramcore_bankmachine5_row_opened = 1'd0; +reg main_litedramcore_bankmachine5_sink_first = 1'd0; +reg main_litedramcore_bankmachine5_sink_last = 1'd0; +wire [20:0] main_litedramcore_bankmachine5_sink_payload_addr; +wire main_litedramcore_bankmachine5_sink_payload_we; +wire main_litedramcore_bankmachine5_sink_ready; +wire main_litedramcore_bankmachine5_sink_sink_first; +wire main_litedramcore_bankmachine5_sink_sink_last; +wire [20:0] main_litedramcore_bankmachine5_sink_sink_payload_addr; +wire main_litedramcore_bankmachine5_sink_sink_payload_we; +wire main_litedramcore_bankmachine5_sink_sink_ready; +wire main_litedramcore_bankmachine5_sink_sink_valid; +wire main_litedramcore_bankmachine5_sink_valid; +wire main_litedramcore_bankmachine5_source_first; +wire main_litedramcore_bankmachine5_source_last; +wire [20:0] main_litedramcore_bankmachine5_source_payload_addr; +wire main_litedramcore_bankmachine5_source_payload_we; +wire main_litedramcore_bankmachine5_source_ready; +wire main_litedramcore_bankmachine5_source_source_first; +wire main_litedramcore_bankmachine5_source_source_last; +wire [20:0] main_litedramcore_bankmachine5_source_source_payload_addr; +wire main_litedramcore_bankmachine5_source_source_payload_we; +wire main_litedramcore_bankmachine5_source_source_ready; +wire main_litedramcore_bankmachine5_source_source_valid; +wire main_litedramcore_bankmachine5_source_valid; +wire [23:0] main_litedramcore_bankmachine5_syncfifo5_din; +wire [23:0] main_litedramcore_bankmachine5_syncfifo5_dout; +wire main_litedramcore_bankmachine5_syncfifo5_re; +wire main_litedramcore_bankmachine5_syncfifo5_readable; +wire main_litedramcore_bankmachine5_syncfifo5_we; +wire main_litedramcore_bankmachine5_syncfifo5_writable; +reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; -wire litedramcore_bankmachine5_trccon_valid; +reg main_litedramcore_bankmachine5_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine5_trascon_valid; +reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0; -wire litedramcore_bankmachine5_trascon_valid; +reg main_litedramcore_bankmachine5_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine5_trccon_valid; +reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine5_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0; -wire litedramcore_bankmachine6_req_valid; -wire litedramcore_bankmachine6_req_ready; -wire litedramcore_bankmachine6_req_we; -wire [20:0] litedramcore_bankmachine6_req_addr; -wire litedramcore_bankmachine6_req_lock; -reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine6_refresh_req; -reg litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg litedramcore_bankmachine6_cmd_valid = 1'd0; -reg litedramcore_bankmachine6_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine6_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; -reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine6_auto_precharge = 1'd0; -wire litedramcore_bankmachine6_sink_valid; -wire litedramcore_bankmachine6_sink_ready; -reg litedramcore_bankmachine6_sink_first = 1'd0; -reg litedramcore_bankmachine6_sink_last = 1'd0; -wire litedramcore_bankmachine6_sink_payload_we; -wire [20:0] litedramcore_bankmachine6_sink_payload_addr; -wire litedramcore_bankmachine6_source_valid; -wire litedramcore_bankmachine6_source_ready; -wire litedramcore_bankmachine6_source_first; -wire litedramcore_bankmachine6_source_last; -wire litedramcore_bankmachine6_source_payload_we; -wire [20:0] litedramcore_bankmachine6_source_payload_addr; -wire litedramcore_bankmachine6_syncfifo6_we; -wire litedramcore_bankmachine6_syncfifo6_writable; -wire litedramcore_bankmachine6_syncfifo6_re; -wire litedramcore_bankmachine6_syncfifo6_readable; -wire [23:0] litedramcore_bankmachine6_syncfifo6_din; -wire [23:0] litedramcore_bankmachine6_syncfifo6_dout; -reg [4:0] litedramcore_bankmachine6_level = 5'd0; -reg litedramcore_bankmachine6_replace = 1'd0; -reg [3:0] litedramcore_bankmachine6_produce = 4'd0; -reg [3:0] litedramcore_bankmachine6_consume = 4'd0; -reg [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine6_wrport_dat_r; -wire litedramcore_bankmachine6_wrport_we; -wire [23:0] litedramcore_bankmachine6_wrport_dat_w; -wire litedramcore_bankmachine6_do_read; -wire [3:0] litedramcore_bankmachine6_rdport_adr; -wire [23:0] litedramcore_bankmachine6_rdport_dat_r; -wire litedramcore_bankmachine6_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine6_fifo_in_payload_addr; -wire litedramcore_bankmachine6_fifo_in_first; -wire litedramcore_bankmachine6_fifo_in_last; -wire litedramcore_bankmachine6_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine6_fifo_out_payload_addr; -wire litedramcore_bankmachine6_fifo_out_first; -wire litedramcore_bankmachine6_fifo_out_last; -wire litedramcore_bankmachine6_sink_sink_valid; -wire litedramcore_bankmachine6_sink_sink_ready; -wire litedramcore_bankmachine6_sink_sink_first; -wire litedramcore_bankmachine6_sink_sink_last; -wire litedramcore_bankmachine6_sink_sink_payload_we; -wire [20:0] litedramcore_bankmachine6_sink_sink_payload_addr; -wire litedramcore_bankmachine6_source_source_valid; -wire litedramcore_bankmachine6_source_source_ready; -wire litedramcore_bankmachine6_source_source_first; -wire litedramcore_bankmachine6_source_source_last; -wire litedramcore_bankmachine6_source_source_payload_we; -wire [20:0] litedramcore_bankmachine6_source_source_payload_addr; -wire litedramcore_bankmachine6_pipe_valid_sink_valid; -wire litedramcore_bankmachine6_pipe_valid_sink_ready; -wire litedramcore_bankmachine6_pipe_valid_sink_first; -wire litedramcore_bankmachine6_pipe_valid_sink_last; -wire litedramcore_bankmachine6_pipe_valid_sink_payload_we; -wire [20:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine6_pipe_valid_source_ready; -reg litedramcore_bankmachine6_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine6_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine6_row = 14'd0; -reg litedramcore_bankmachine6_row_opened = 1'd0; -wire litedramcore_bankmachine6_row_hit; -reg litedramcore_bankmachine6_row_open = 1'd0; -reg litedramcore_bankmachine6_row_close = 1'd0; -reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine6_twtpcon_valid; +reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine5_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine5_wrport_adr = 4'd0; +wire [23:0] main_litedramcore_bankmachine5_wrport_dat_r; +wire [23:0] main_litedramcore_bankmachine5_wrport_dat_w; +wire main_litedramcore_bankmachine5_wrport_we; +reg main_litedramcore_bankmachine6_auto_precharge = 1'd0; +reg [13:0] main_litedramcore_bankmachine6_cmd_payload_a = 14'd0; +wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba; +reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine6_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine6_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine6_consume = 4'd0; +wire main_litedramcore_bankmachine6_do_read; +wire main_litedramcore_bankmachine6_fifo_in_first; +wire main_litedramcore_bankmachine6_fifo_in_last; +wire [20:0] main_litedramcore_bankmachine6_fifo_in_payload_addr; +wire main_litedramcore_bankmachine6_fifo_in_payload_we; +wire main_litedramcore_bankmachine6_fifo_out_first; +wire main_litedramcore_bankmachine6_fifo_out_last; +wire [20:0] main_litedramcore_bankmachine6_fifo_out_payload_addr; +wire main_litedramcore_bankmachine6_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine6_level = 5'd0; +wire main_litedramcore_bankmachine6_pipe_valid_sink_first; +wire main_litedramcore_bankmachine6_pipe_valid_sink_last; +wire [20:0] main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine6_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine6_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine6_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine6_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine6_pipe_valid_source_last = 1'd0; +reg [20:0] main_litedramcore_bankmachine6_pipe_valid_source_payload_addr = 21'd0; +reg main_litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine6_pipe_valid_source_ready; +reg main_litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine6_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine6_rdport_adr; +wire [23:0] main_litedramcore_bankmachine6_rdport_dat_r; +reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine6_refresh_req; +reg main_litedramcore_bankmachine6_replace = 1'd0; +wire [20:0] main_litedramcore_bankmachine6_req_addr; +wire main_litedramcore_bankmachine6_req_lock; +reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine6_req_ready; +wire main_litedramcore_bankmachine6_req_valid; +reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine6_req_we; +reg [13:0] main_litedramcore_bankmachine6_row = 14'd0; +reg main_litedramcore_bankmachine6_row_close = 1'd0; +reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine6_row_hit; +reg main_litedramcore_bankmachine6_row_open = 1'd0; +reg main_litedramcore_bankmachine6_row_opened = 1'd0; +reg main_litedramcore_bankmachine6_sink_first = 1'd0; +reg main_litedramcore_bankmachine6_sink_last = 1'd0; +wire [20:0] main_litedramcore_bankmachine6_sink_payload_addr; +wire main_litedramcore_bankmachine6_sink_payload_we; +wire main_litedramcore_bankmachine6_sink_ready; +wire main_litedramcore_bankmachine6_sink_sink_first; +wire main_litedramcore_bankmachine6_sink_sink_last; +wire [20:0] main_litedramcore_bankmachine6_sink_sink_payload_addr; +wire main_litedramcore_bankmachine6_sink_sink_payload_we; +wire main_litedramcore_bankmachine6_sink_sink_ready; +wire main_litedramcore_bankmachine6_sink_sink_valid; +wire main_litedramcore_bankmachine6_sink_valid; +wire main_litedramcore_bankmachine6_source_first; +wire main_litedramcore_bankmachine6_source_last; +wire [20:0] main_litedramcore_bankmachine6_source_payload_addr; +wire main_litedramcore_bankmachine6_source_payload_we; +wire main_litedramcore_bankmachine6_source_ready; +wire main_litedramcore_bankmachine6_source_source_first; +wire main_litedramcore_bankmachine6_source_source_last; +wire [20:0] main_litedramcore_bankmachine6_source_source_payload_addr; +wire main_litedramcore_bankmachine6_source_source_payload_we; +wire main_litedramcore_bankmachine6_source_source_ready; +wire main_litedramcore_bankmachine6_source_source_valid; +wire main_litedramcore_bankmachine6_source_valid; +wire [23:0] main_litedramcore_bankmachine6_syncfifo6_din; +wire [23:0] main_litedramcore_bankmachine6_syncfifo6_dout; +wire main_litedramcore_bankmachine6_syncfifo6_re; +wire main_litedramcore_bankmachine6_syncfifo6_readable; +wire main_litedramcore_bankmachine6_syncfifo6_we; +wire main_litedramcore_bankmachine6_syncfifo6_writable; +reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; -wire litedramcore_bankmachine6_trccon_valid; +reg main_litedramcore_bankmachine6_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine6_trascon_valid; +reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0; -wire litedramcore_bankmachine6_trascon_valid; +reg main_litedramcore_bankmachine6_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine6_trccon_valid; +reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine6_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0; -wire litedramcore_bankmachine7_req_valid; -wire litedramcore_bankmachine7_req_ready; -wire litedramcore_bankmachine7_req_we; -wire [20:0] litedramcore_bankmachine7_req_addr; -wire litedramcore_bankmachine7_req_lock; -reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine7_refresh_req; -reg litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg litedramcore_bankmachine7_cmd_valid = 1'd0; -reg litedramcore_bankmachine7_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine7_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; -reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine7_auto_precharge = 1'd0; -wire litedramcore_bankmachine7_sink_valid; -wire litedramcore_bankmachine7_sink_ready; -reg litedramcore_bankmachine7_sink_first = 1'd0; -reg litedramcore_bankmachine7_sink_last = 1'd0; -wire litedramcore_bankmachine7_sink_payload_we; -wire [20:0] litedramcore_bankmachine7_sink_payload_addr; -wire litedramcore_bankmachine7_source_valid; -wire litedramcore_bankmachine7_source_ready; -wire litedramcore_bankmachine7_source_first; -wire litedramcore_bankmachine7_source_last; -wire litedramcore_bankmachine7_source_payload_we; -wire [20:0] litedramcore_bankmachine7_source_payload_addr; -wire litedramcore_bankmachine7_syncfifo7_we; -wire litedramcore_bankmachine7_syncfifo7_writable; -wire litedramcore_bankmachine7_syncfifo7_re; -wire litedramcore_bankmachine7_syncfifo7_readable; -wire [23:0] litedramcore_bankmachine7_syncfifo7_din; -wire [23:0] litedramcore_bankmachine7_syncfifo7_dout; -reg [4:0] litedramcore_bankmachine7_level = 5'd0; -reg litedramcore_bankmachine7_replace = 1'd0; -reg [3:0] litedramcore_bankmachine7_produce = 4'd0; -reg [3:0] litedramcore_bankmachine7_consume = 4'd0; -reg [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine7_wrport_dat_r; -wire litedramcore_bankmachine7_wrport_we; -wire [23:0] litedramcore_bankmachine7_wrport_dat_w; -wire litedramcore_bankmachine7_do_read; -wire [3:0] litedramcore_bankmachine7_rdport_adr; -wire [23:0] litedramcore_bankmachine7_rdport_dat_r; -wire litedramcore_bankmachine7_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine7_fifo_in_payload_addr; -wire litedramcore_bankmachine7_fifo_in_first; -wire litedramcore_bankmachine7_fifo_in_last; -wire litedramcore_bankmachine7_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine7_fifo_out_payload_addr; -wire litedramcore_bankmachine7_fifo_out_first; -wire litedramcore_bankmachine7_fifo_out_last; -wire litedramcore_bankmachine7_sink_sink_valid; -wire litedramcore_bankmachine7_sink_sink_ready; -wire litedramcore_bankmachine7_sink_sink_first; -wire litedramcore_bankmachine7_sink_sink_last; -wire litedramcore_bankmachine7_sink_sink_payload_we; -wire [20:0] litedramcore_bankmachine7_sink_sink_payload_addr; -wire litedramcore_bankmachine7_source_source_valid; -wire litedramcore_bankmachine7_source_source_ready; -wire litedramcore_bankmachine7_source_source_first; -wire litedramcore_bankmachine7_source_source_last; -wire litedramcore_bankmachine7_source_source_payload_we; -wire [20:0] litedramcore_bankmachine7_source_source_payload_addr; -wire litedramcore_bankmachine7_pipe_valid_sink_valid; -wire litedramcore_bankmachine7_pipe_valid_sink_ready; -wire litedramcore_bankmachine7_pipe_valid_sink_first; -wire litedramcore_bankmachine7_pipe_valid_sink_last; -wire litedramcore_bankmachine7_pipe_valid_sink_payload_we; -wire [20:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr; -reg litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; -wire litedramcore_bankmachine7_pipe_valid_source_ready; -reg litedramcore_bankmachine7_pipe_valid_source_first = 1'd0; -reg litedramcore_bankmachine7_pipe_valid_source_last = 1'd0; -reg litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine7_row = 14'd0; -reg litedramcore_bankmachine7_row_opened = 1'd0; -wire litedramcore_bankmachine7_row_hit; -reg litedramcore_bankmachine7_row_open = 1'd0; -reg litedramcore_bankmachine7_row_close = 1'd0; -reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine7_twtpcon_valid; +reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine6_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine6_wrport_adr = 4'd0; +wire [23:0] main_litedramcore_bankmachine6_wrport_dat_r; +wire [23:0] main_litedramcore_bankmachine6_wrport_dat_w; +wire main_litedramcore_bankmachine6_wrport_we; +reg main_litedramcore_bankmachine7_auto_precharge = 1'd0; +reg [13:0] main_litedramcore_bankmachine7_cmd_payload_a = 14'd0; +wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba; +reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine7_cmd_ready = 1'd0; +reg main_litedramcore_bankmachine7_cmd_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine7_consume = 4'd0; +wire main_litedramcore_bankmachine7_do_read; +wire main_litedramcore_bankmachine7_fifo_in_first; +wire main_litedramcore_bankmachine7_fifo_in_last; +wire [20:0] main_litedramcore_bankmachine7_fifo_in_payload_addr; +wire main_litedramcore_bankmachine7_fifo_in_payload_we; +wire main_litedramcore_bankmachine7_fifo_out_first; +wire main_litedramcore_bankmachine7_fifo_out_last; +wire [20:0] main_litedramcore_bankmachine7_fifo_out_payload_addr; +wire main_litedramcore_bankmachine7_fifo_out_payload_we; +reg [4:0] main_litedramcore_bankmachine7_level = 5'd0; +wire main_litedramcore_bankmachine7_pipe_valid_sink_first; +wire main_litedramcore_bankmachine7_pipe_valid_sink_last; +wire [20:0] main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr; +wire main_litedramcore_bankmachine7_pipe_valid_sink_payload_we; +wire main_litedramcore_bankmachine7_pipe_valid_sink_ready; +wire main_litedramcore_bankmachine7_pipe_valid_sink_valid; +reg main_litedramcore_bankmachine7_pipe_valid_source_first = 1'd0; +reg main_litedramcore_bankmachine7_pipe_valid_source_last = 1'd0; +reg [20:0] main_litedramcore_bankmachine7_pipe_valid_source_payload_addr = 21'd0; +reg main_litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; +wire main_litedramcore_bankmachine7_pipe_valid_source_ready; +reg main_litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; +reg [3:0] main_litedramcore_bankmachine7_produce = 4'd0; +wire [3:0] main_litedramcore_bankmachine7_rdport_adr; +wire [23:0] main_litedramcore_bankmachine7_rdport_dat_r; +reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0; +wire main_litedramcore_bankmachine7_refresh_req; +reg main_litedramcore_bankmachine7_replace = 1'd0; +wire [20:0] main_litedramcore_bankmachine7_req_addr; +wire main_litedramcore_bankmachine7_req_lock; +reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire main_litedramcore_bankmachine7_req_ready; +wire main_litedramcore_bankmachine7_req_valid; +reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0; +wire main_litedramcore_bankmachine7_req_we; +reg [13:0] main_litedramcore_bankmachine7_row = 14'd0; +reg main_litedramcore_bankmachine7_row_close = 1'd0; +reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire main_litedramcore_bankmachine7_row_hit; +reg main_litedramcore_bankmachine7_row_open = 1'd0; +reg main_litedramcore_bankmachine7_row_opened = 1'd0; +reg main_litedramcore_bankmachine7_sink_first = 1'd0; +reg main_litedramcore_bankmachine7_sink_last = 1'd0; +wire [20:0] main_litedramcore_bankmachine7_sink_payload_addr; +wire main_litedramcore_bankmachine7_sink_payload_we; +wire main_litedramcore_bankmachine7_sink_ready; +wire main_litedramcore_bankmachine7_sink_sink_first; +wire main_litedramcore_bankmachine7_sink_sink_last; +wire [20:0] main_litedramcore_bankmachine7_sink_sink_payload_addr; +wire main_litedramcore_bankmachine7_sink_sink_payload_we; +wire main_litedramcore_bankmachine7_sink_sink_ready; +wire main_litedramcore_bankmachine7_sink_sink_valid; +wire main_litedramcore_bankmachine7_sink_valid; +wire main_litedramcore_bankmachine7_source_first; +wire main_litedramcore_bankmachine7_source_last; +wire [20:0] main_litedramcore_bankmachine7_source_payload_addr; +wire main_litedramcore_bankmachine7_source_payload_we; +wire main_litedramcore_bankmachine7_source_ready; +wire main_litedramcore_bankmachine7_source_source_first; +wire main_litedramcore_bankmachine7_source_source_last; +wire [20:0] main_litedramcore_bankmachine7_source_source_payload_addr; +wire main_litedramcore_bankmachine7_source_source_payload_we; +wire main_litedramcore_bankmachine7_source_source_ready; +wire main_litedramcore_bankmachine7_source_source_valid; +wire main_litedramcore_bankmachine7_source_valid; +wire [23:0] main_litedramcore_bankmachine7_syncfifo7_din; +wire [23:0] main_litedramcore_bankmachine7_syncfifo7_dout; +wire main_litedramcore_bankmachine7_syncfifo7_re; +wire main_litedramcore_bankmachine7_syncfifo7_readable; +wire main_litedramcore_bankmachine7_syncfifo7_we; +wire main_litedramcore_bankmachine7_syncfifo7_writable; +reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; -wire litedramcore_bankmachine7_trccon_valid; +reg main_litedramcore_bankmachine7_trascon_ready = 1'd0; +wire main_litedramcore_bankmachine7_trascon_valid; +reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0; -wire litedramcore_bankmachine7_trascon_valid; +reg main_litedramcore_bankmachine7_trccon_ready = 1'd0; +wire main_litedramcore_bankmachine7_trccon_valid; +reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_bankmachine7_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0; -wire litedramcore_ras_allowed; -wire litedramcore_cas_allowed; -wire [1:0] litedramcore_rdcmdphase; -wire [1:0] litedramcore_wrcmdphase; -reg litedramcore_choose_cmd_want_reads = 1'd0; -reg litedramcore_choose_cmd_want_writes = 1'd0; -reg litedramcore_choose_cmd_want_cmds = 1'd0; -reg litedramcore_choose_cmd_want_activates = 1'd0; -wire litedramcore_choose_cmd_cmd_valid; -reg litedramcore_choose_cmd_cmd_ready = 1'd0; -wire [13:0] litedramcore_choose_cmd_cmd_payload_a; -wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; -reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; -wire litedramcore_choose_cmd_cmd_payload_is_cmd; -wire litedramcore_choose_cmd_cmd_payload_is_read; -wire litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] litedramcore_choose_cmd_valids = 8'd0; -wire [7:0] litedramcore_choose_cmd_request; -reg [2:0] litedramcore_choose_cmd_grant = 3'd0; -wire litedramcore_choose_cmd_ce; -reg litedramcore_choose_req_want_reads = 1'd0; -reg litedramcore_choose_req_want_writes = 1'd0; -reg litedramcore_choose_req_want_cmds = 1'd0; -reg litedramcore_choose_req_want_activates = 1'd0; -wire litedramcore_choose_req_cmd_valid; -reg litedramcore_choose_req_cmd_ready = 1'd0; -wire [13:0] litedramcore_choose_req_cmd_payload_a; -wire [2:0] litedramcore_choose_req_cmd_payload_ba; -reg litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg litedramcore_choose_req_cmd_payload_we = 1'd0; -wire litedramcore_choose_req_cmd_payload_is_cmd; -wire litedramcore_choose_req_cmd_payload_is_read; -wire litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] litedramcore_choose_req_valids = 8'd0; -wire [7:0] litedramcore_choose_req_request; -reg [2:0] litedramcore_choose_req_grant = 3'd0; -wire litedramcore_choose_req_ce; -reg [13:0] litedramcore_nop_a = 14'd0; -reg [2:0] litedramcore_nop_ba = 3'd0; -reg [1:0] litedramcore_steerer_sel0 = 2'd0; -reg [1:0] litedramcore_steerer_sel1 = 2'd0; -reg [1:0] litedramcore_steerer_sel2 = 2'd0; -reg [1:0] litedramcore_steerer_sel3 = 2'd0; -reg litedramcore_steerer0 = 1'd1; -reg litedramcore_steerer1 = 1'd1; -reg litedramcore_steerer2 = 1'd1; -reg litedramcore_steerer3 = 1'd1; -reg litedramcore_steerer4 = 1'd1; -reg litedramcore_steerer5 = 1'd1; -reg litedramcore_steerer6 = 1'd1; -reg litedramcore_steerer7 = 1'd1; -wire litedramcore_trrdcon_valid; +reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0; +wire main_litedramcore_bankmachine7_twtpcon_valid; +reg [3:0] main_litedramcore_bankmachine7_wrport_adr = 4'd0; +wire [23:0] main_litedramcore_bankmachine7_wrport_dat_r; +wire [23:0] main_litedramcore_bankmachine7_wrport_dat_w; +wire main_litedramcore_bankmachine7_wrport_we; +wire main_litedramcore_cas_allowed; +wire main_litedramcore_choose_cmd_ce; +wire [13:0] main_litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba; +reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +wire main_litedramcore_choose_cmd_cmd_payload_is_cmd; +wire main_litedramcore_choose_cmd_cmd_payload_is_read; +wire main_litedramcore_choose_cmd_cmd_payload_is_write; +reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0; +reg main_litedramcore_choose_cmd_cmd_ready = 1'd0; +wire main_litedramcore_choose_cmd_cmd_valid; +reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0; +wire [7:0] main_litedramcore_choose_cmd_request; +reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0; +reg main_litedramcore_choose_cmd_want_activates = 1'd0; +reg main_litedramcore_choose_cmd_want_cmds = 1'd0; +reg main_litedramcore_choose_cmd_want_reads = 1'd0; +reg main_litedramcore_choose_cmd_want_writes = 1'd0; +wire main_litedramcore_choose_req_ce; +wire [13:0] main_litedramcore_choose_req_cmd_payload_a; +wire [2:0] main_litedramcore_choose_req_cmd_payload_ba; +reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0; +wire main_litedramcore_choose_req_cmd_payload_is_cmd; +wire main_litedramcore_choose_req_cmd_payload_is_read; +wire main_litedramcore_choose_req_cmd_payload_is_write; +reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_we = 1'd0; +reg main_litedramcore_choose_req_cmd_ready = 1'd0; +wire main_litedramcore_choose_req_cmd_valid; +reg [2:0] main_litedramcore_choose_req_grant = 3'd0; +wire [7:0] main_litedramcore_choose_req_request; +reg [7:0] main_litedramcore_choose_req_valids = 8'd0; +reg main_litedramcore_choose_req_want_activates = 1'd0; +reg main_litedramcore_choose_req_want_cmds = 1'd0; +reg main_litedramcore_choose_req_want_reads = 1'd0; +reg main_litedramcore_choose_req_want_writes = 1'd0; +wire main_litedramcore_cke; +reg main_litedramcore_cmd_last = 1'd0; +reg [13:0] main_litedramcore_cmd_payload_a = 14'd0; +reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0; +reg main_litedramcore_cmd_payload_cas = 1'd0; +reg main_litedramcore_cmd_payload_is_read = 1'd0; +reg main_litedramcore_cmd_payload_is_write = 1'd0; +reg main_litedramcore_cmd_payload_ras = 1'd0; +reg main_litedramcore_cmd_payload_we = 1'd0; +reg main_litedramcore_cmd_ready = 1'd0; +reg main_litedramcore_cmd_valid = 1'd0; +reg main_litedramcore_csr_dfi_p0_act_n = 1'd1; +wire [13:0] main_litedramcore_csr_dfi_p0_address; +wire [2:0] main_litedramcore_csr_dfi_p0_bank; +reg main_litedramcore_csr_dfi_p0_cas_n = 1'd1; +reg main_litedramcore_csr_dfi_p0_cke = 1'd0; +reg main_litedramcore_csr_dfi_p0_cs_n = 1'd1; +reg main_litedramcore_csr_dfi_p0_odt = 1'd0; +reg main_litedramcore_csr_dfi_p0_ras_n = 1'd1; +reg [31:0] main_litedramcore_csr_dfi_p0_rddata = 32'd0; +wire main_litedramcore_csr_dfi_p0_rddata_en; +reg main_litedramcore_csr_dfi_p0_rddata_valid = 1'd0; +wire main_litedramcore_csr_dfi_p0_reset_n; +reg main_litedramcore_csr_dfi_p0_we_n = 1'd1; +wire [31:0] main_litedramcore_csr_dfi_p0_wrdata; +wire main_litedramcore_csr_dfi_p0_wrdata_en; +wire [3:0] main_litedramcore_csr_dfi_p0_wrdata_mask; +reg main_litedramcore_csr_dfi_p1_act_n = 1'd1; +wire [13:0] main_litedramcore_csr_dfi_p1_address; +wire [2:0] main_litedramcore_csr_dfi_p1_bank; +reg main_litedramcore_csr_dfi_p1_cas_n = 1'd1; +reg main_litedramcore_csr_dfi_p1_cke = 1'd0; +reg main_litedramcore_csr_dfi_p1_cs_n = 1'd1; +reg main_litedramcore_csr_dfi_p1_odt = 1'd0; +reg main_litedramcore_csr_dfi_p1_ras_n = 1'd1; +reg [31:0] main_litedramcore_csr_dfi_p1_rddata = 32'd0; +wire main_litedramcore_csr_dfi_p1_rddata_en; +reg main_litedramcore_csr_dfi_p1_rddata_valid = 1'd0; +wire main_litedramcore_csr_dfi_p1_reset_n; +reg main_litedramcore_csr_dfi_p1_we_n = 1'd1; +wire [31:0] main_litedramcore_csr_dfi_p1_wrdata; +wire main_litedramcore_csr_dfi_p1_wrdata_en; +wire [3:0] main_litedramcore_csr_dfi_p1_wrdata_mask; +reg main_litedramcore_csr_dfi_p2_act_n = 1'd1; +wire [13:0] main_litedramcore_csr_dfi_p2_address; +wire [2:0] main_litedramcore_csr_dfi_p2_bank; +reg main_litedramcore_csr_dfi_p2_cas_n = 1'd1; +reg main_litedramcore_csr_dfi_p2_cke = 1'd0; +reg main_litedramcore_csr_dfi_p2_cs_n = 1'd1; +reg main_litedramcore_csr_dfi_p2_odt = 1'd0; +reg main_litedramcore_csr_dfi_p2_ras_n = 1'd1; +reg [31:0] main_litedramcore_csr_dfi_p2_rddata = 32'd0; +wire main_litedramcore_csr_dfi_p2_rddata_en; +reg main_litedramcore_csr_dfi_p2_rddata_valid = 1'd0; +wire main_litedramcore_csr_dfi_p2_reset_n; +reg main_litedramcore_csr_dfi_p2_we_n = 1'd1; +wire [31:0] main_litedramcore_csr_dfi_p2_wrdata; +wire main_litedramcore_csr_dfi_p2_wrdata_en; +wire [3:0] main_litedramcore_csr_dfi_p2_wrdata_mask; +reg main_litedramcore_csr_dfi_p3_act_n = 1'd1; +wire [13:0] main_litedramcore_csr_dfi_p3_address; +wire [2:0] main_litedramcore_csr_dfi_p3_bank; +reg main_litedramcore_csr_dfi_p3_cas_n = 1'd1; +reg main_litedramcore_csr_dfi_p3_cke = 1'd0; +reg main_litedramcore_csr_dfi_p3_cs_n = 1'd1; +reg main_litedramcore_csr_dfi_p3_odt = 1'd0; +reg main_litedramcore_csr_dfi_p3_ras_n = 1'd1; +reg [31:0] main_litedramcore_csr_dfi_p3_rddata = 32'd0; +wire main_litedramcore_csr_dfi_p3_rddata_en; +reg main_litedramcore_csr_dfi_p3_rddata_valid = 1'd0; +wire main_litedramcore_csr_dfi_p3_reset_n; +reg main_litedramcore_csr_dfi_p3_we_n = 1'd1; +wire [31:0] main_litedramcore_csr_dfi_p3_wrdata; +wire main_litedramcore_csr_dfi_p3_wrdata_en; +wire [3:0] main_litedramcore_csr_dfi_p3_wrdata_mask; +reg main_litedramcore_dfi_p0_act_n = 1'd1; +reg [13:0] main_litedramcore_dfi_p0_address = 14'd0; +reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0; +reg main_litedramcore_dfi_p0_cas_n = 1'd1; +wire main_litedramcore_dfi_p0_cke; +reg main_litedramcore_dfi_p0_cs_n = 1'd1; +wire main_litedramcore_dfi_p0_odt; +reg main_litedramcore_dfi_p0_ras_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p0_rddata; +reg main_litedramcore_dfi_p0_rddata_en = 1'd0; +wire main_litedramcore_dfi_p0_rddata_valid; +wire main_litedramcore_dfi_p0_reset_n; +reg main_litedramcore_dfi_p0_we_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p0_wrdata; +reg main_litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p0_wrdata_mask; +reg main_litedramcore_dfi_p1_act_n = 1'd1; +reg [13:0] main_litedramcore_dfi_p1_address = 14'd0; +reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0; +reg main_litedramcore_dfi_p1_cas_n = 1'd1; +wire main_litedramcore_dfi_p1_cke; +reg main_litedramcore_dfi_p1_cs_n = 1'd1; +wire main_litedramcore_dfi_p1_odt; +reg main_litedramcore_dfi_p1_ras_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p1_rddata; +reg main_litedramcore_dfi_p1_rddata_en = 1'd0; +wire main_litedramcore_dfi_p1_rddata_valid; +wire main_litedramcore_dfi_p1_reset_n; +reg main_litedramcore_dfi_p1_we_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p1_wrdata; +reg main_litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p1_wrdata_mask; +reg main_litedramcore_dfi_p2_act_n = 1'd1; +reg [13:0] main_litedramcore_dfi_p2_address = 14'd0; +reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0; +reg main_litedramcore_dfi_p2_cas_n = 1'd1; +wire main_litedramcore_dfi_p2_cke; +reg main_litedramcore_dfi_p2_cs_n = 1'd1; +wire main_litedramcore_dfi_p2_odt; +reg main_litedramcore_dfi_p2_ras_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p2_rddata; +reg main_litedramcore_dfi_p2_rddata_en = 1'd0; +wire main_litedramcore_dfi_p2_rddata_valid; +wire main_litedramcore_dfi_p2_reset_n; +reg main_litedramcore_dfi_p2_we_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p2_wrdata; +reg main_litedramcore_dfi_p2_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p2_wrdata_mask; +reg main_litedramcore_dfi_p3_act_n = 1'd1; +reg [13:0] main_litedramcore_dfi_p3_address = 14'd0; +reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0; +reg main_litedramcore_dfi_p3_cas_n = 1'd1; +wire main_litedramcore_dfi_p3_cke; +reg main_litedramcore_dfi_p3_cs_n = 1'd1; +wire main_litedramcore_dfi_p3_odt; +reg main_litedramcore_dfi_p3_ras_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p3_rddata; +reg main_litedramcore_dfi_p3_rddata_en = 1'd0; +wire main_litedramcore_dfi_p3_rddata_valid; +wire main_litedramcore_dfi_p3_reset_n; +reg main_litedramcore_dfi_p3_we_n = 1'd1; +wire [31:0] main_litedramcore_dfi_p3_wrdata; +reg main_litedramcore_dfi_p3_wrdata_en = 1'd0; +wire [3:0] main_litedramcore_dfi_p3_wrdata_mask; +reg main_litedramcore_en0 = 1'd0; +reg main_litedramcore_en1 = 1'd0; +reg main_litedramcore_ext_dfi_p0_act_n = 1'd1; +reg [13:0] main_litedramcore_ext_dfi_p0_address = 14'd0; +reg [2:0] main_litedramcore_ext_dfi_p0_bank = 3'd0; +reg main_litedramcore_ext_dfi_p0_cas_n = 1'd1; +reg main_litedramcore_ext_dfi_p0_cke = 1'd0; +reg main_litedramcore_ext_dfi_p0_cs_n = 1'd1; +reg main_litedramcore_ext_dfi_p0_odt = 1'd0; +reg main_litedramcore_ext_dfi_p0_ras_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p0_rddata = 32'd0; +reg main_litedramcore_ext_dfi_p0_rddata_en = 1'd0; +reg main_litedramcore_ext_dfi_p0_rddata_valid = 1'd0; +reg main_litedramcore_ext_dfi_p0_reset_n = 1'd0; +reg main_litedramcore_ext_dfi_p0_we_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p0_wrdata = 32'd0; +reg main_litedramcore_ext_dfi_p0_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_ext_dfi_p0_wrdata_mask = 4'd0; +reg main_litedramcore_ext_dfi_p1_act_n = 1'd1; +reg [13:0] main_litedramcore_ext_dfi_p1_address = 14'd0; +reg [2:0] main_litedramcore_ext_dfi_p1_bank = 3'd0; +reg main_litedramcore_ext_dfi_p1_cas_n = 1'd1; +reg main_litedramcore_ext_dfi_p1_cke = 1'd0; +reg main_litedramcore_ext_dfi_p1_cs_n = 1'd1; +reg main_litedramcore_ext_dfi_p1_odt = 1'd0; +reg main_litedramcore_ext_dfi_p1_ras_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p1_rddata = 32'd0; +reg main_litedramcore_ext_dfi_p1_rddata_en = 1'd0; +reg main_litedramcore_ext_dfi_p1_rddata_valid = 1'd0; +reg main_litedramcore_ext_dfi_p1_reset_n = 1'd0; +reg main_litedramcore_ext_dfi_p1_we_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p1_wrdata = 32'd0; +reg main_litedramcore_ext_dfi_p1_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_ext_dfi_p1_wrdata_mask = 4'd0; +reg main_litedramcore_ext_dfi_p2_act_n = 1'd1; +reg [13:0] main_litedramcore_ext_dfi_p2_address = 14'd0; +reg [2:0] main_litedramcore_ext_dfi_p2_bank = 3'd0; +reg main_litedramcore_ext_dfi_p2_cas_n = 1'd1; +reg main_litedramcore_ext_dfi_p2_cke = 1'd0; +reg main_litedramcore_ext_dfi_p2_cs_n = 1'd1; +reg main_litedramcore_ext_dfi_p2_odt = 1'd0; +reg main_litedramcore_ext_dfi_p2_ras_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p2_rddata = 32'd0; +reg main_litedramcore_ext_dfi_p2_rddata_en = 1'd0; +reg main_litedramcore_ext_dfi_p2_rddata_valid = 1'd0; +reg main_litedramcore_ext_dfi_p2_reset_n = 1'd0; +reg main_litedramcore_ext_dfi_p2_we_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p2_wrdata = 32'd0; +reg main_litedramcore_ext_dfi_p2_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_ext_dfi_p2_wrdata_mask = 4'd0; +reg main_litedramcore_ext_dfi_p3_act_n = 1'd1; +reg [13:0] main_litedramcore_ext_dfi_p3_address = 14'd0; +reg [2:0] main_litedramcore_ext_dfi_p3_bank = 3'd0; +reg main_litedramcore_ext_dfi_p3_cas_n = 1'd1; +reg main_litedramcore_ext_dfi_p3_cke = 1'd0; +reg main_litedramcore_ext_dfi_p3_cs_n = 1'd1; +reg main_litedramcore_ext_dfi_p3_odt = 1'd0; +reg main_litedramcore_ext_dfi_p3_ras_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p3_rddata = 32'd0; +reg main_litedramcore_ext_dfi_p3_rddata_en = 1'd0; +reg main_litedramcore_ext_dfi_p3_rddata_valid = 1'd0; +reg main_litedramcore_ext_dfi_p3_reset_n = 1'd0; +reg main_litedramcore_ext_dfi_p3_we_n = 1'd1; +reg [31:0] main_litedramcore_ext_dfi_p3_wrdata = 32'd0; +reg main_litedramcore_ext_dfi_p3_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_ext_dfi_p3_wrdata_mask = 4'd0; +reg main_litedramcore_ext_dfi_sel = 1'd0; +wire main_litedramcore_go_to_refresh; +wire [20:0] main_litedramcore_interface_bank0_addr; +wire main_litedramcore_interface_bank0_lock; +wire main_litedramcore_interface_bank0_rdata_valid; +wire main_litedramcore_interface_bank0_ready; +wire main_litedramcore_interface_bank0_valid; +wire main_litedramcore_interface_bank0_wdata_ready; +wire main_litedramcore_interface_bank0_we; +wire [20:0] main_litedramcore_interface_bank1_addr; +wire main_litedramcore_interface_bank1_lock; +wire main_litedramcore_interface_bank1_rdata_valid; +wire main_litedramcore_interface_bank1_ready; +wire main_litedramcore_interface_bank1_valid; +wire main_litedramcore_interface_bank1_wdata_ready; +wire main_litedramcore_interface_bank1_we; +wire [20:0] main_litedramcore_interface_bank2_addr; +wire main_litedramcore_interface_bank2_lock; +wire main_litedramcore_interface_bank2_rdata_valid; +wire main_litedramcore_interface_bank2_ready; +wire main_litedramcore_interface_bank2_valid; +wire main_litedramcore_interface_bank2_wdata_ready; +wire main_litedramcore_interface_bank2_we; +wire [20:0] main_litedramcore_interface_bank3_addr; +wire main_litedramcore_interface_bank3_lock; +wire main_litedramcore_interface_bank3_rdata_valid; +wire main_litedramcore_interface_bank3_ready; +wire main_litedramcore_interface_bank3_valid; +wire main_litedramcore_interface_bank3_wdata_ready; +wire main_litedramcore_interface_bank3_we; +wire [20:0] main_litedramcore_interface_bank4_addr; +wire main_litedramcore_interface_bank4_lock; +wire main_litedramcore_interface_bank4_rdata_valid; +wire main_litedramcore_interface_bank4_ready; +wire main_litedramcore_interface_bank4_valid; +wire main_litedramcore_interface_bank4_wdata_ready; +wire main_litedramcore_interface_bank4_we; +wire [20:0] main_litedramcore_interface_bank5_addr; +wire main_litedramcore_interface_bank5_lock; +wire main_litedramcore_interface_bank5_rdata_valid; +wire main_litedramcore_interface_bank5_ready; +wire main_litedramcore_interface_bank5_valid; +wire main_litedramcore_interface_bank5_wdata_ready; +wire main_litedramcore_interface_bank5_we; +wire [20:0] main_litedramcore_interface_bank6_addr; +wire main_litedramcore_interface_bank6_lock; +wire main_litedramcore_interface_bank6_rdata_valid; +wire main_litedramcore_interface_bank6_ready; +wire main_litedramcore_interface_bank6_valid; +wire main_litedramcore_interface_bank6_wdata_ready; +wire main_litedramcore_interface_bank6_we; +wire [20:0] main_litedramcore_interface_bank7_addr; +wire main_litedramcore_interface_bank7_lock; +wire main_litedramcore_interface_bank7_rdata_valid; +wire main_litedramcore_interface_bank7_ready; +wire main_litedramcore_interface_bank7_valid; +wire main_litedramcore_interface_bank7_wdata_ready; +wire main_litedramcore_interface_bank7_we; +wire [127:0] main_litedramcore_interface_rdata; +reg [127:0] main_litedramcore_interface_wdata = 128'd0; +reg [15:0] main_litedramcore_interface_wdata_we = 16'd0; +reg main_litedramcore_master_p0_act_n = 1'd1; +reg [13:0] main_litedramcore_master_p0_address = 14'd0; +reg [2:0] main_litedramcore_master_p0_bank = 3'd0; +reg main_litedramcore_master_p0_cas_n = 1'd1; +reg main_litedramcore_master_p0_cke = 1'd0; +reg main_litedramcore_master_p0_cs_n = 1'd1; +reg main_litedramcore_master_p0_odt = 1'd0; +reg main_litedramcore_master_p0_ras_n = 1'd1; +wire [31:0] main_litedramcore_master_p0_rddata; +reg main_litedramcore_master_p0_rddata_en = 1'd0; +wire main_litedramcore_master_p0_rddata_valid; +reg main_litedramcore_master_p0_reset_n = 1'd0; +reg main_litedramcore_master_p0_we_n = 1'd1; +reg [31:0] main_litedramcore_master_p0_wrdata = 32'd0; +reg main_litedramcore_master_p0_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0; +reg main_litedramcore_master_p1_act_n = 1'd1; +reg [13:0] main_litedramcore_master_p1_address = 14'd0; +reg [2:0] main_litedramcore_master_p1_bank = 3'd0; +reg main_litedramcore_master_p1_cas_n = 1'd1; +reg main_litedramcore_master_p1_cke = 1'd0; +reg main_litedramcore_master_p1_cs_n = 1'd1; +reg main_litedramcore_master_p1_odt = 1'd0; +reg main_litedramcore_master_p1_ras_n = 1'd1; +wire [31:0] main_litedramcore_master_p1_rddata; +reg main_litedramcore_master_p1_rddata_en = 1'd0; +wire main_litedramcore_master_p1_rddata_valid; +reg main_litedramcore_master_p1_reset_n = 1'd0; +reg main_litedramcore_master_p1_we_n = 1'd1; +reg [31:0] main_litedramcore_master_p1_wrdata = 32'd0; +reg main_litedramcore_master_p1_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0; +reg main_litedramcore_master_p2_act_n = 1'd1; +reg [13:0] main_litedramcore_master_p2_address = 14'd0; +reg [2:0] main_litedramcore_master_p2_bank = 3'd0; +reg main_litedramcore_master_p2_cas_n = 1'd1; +reg main_litedramcore_master_p2_cke = 1'd0; +reg main_litedramcore_master_p2_cs_n = 1'd1; +reg main_litedramcore_master_p2_odt = 1'd0; +reg main_litedramcore_master_p2_ras_n = 1'd1; +wire [31:0] main_litedramcore_master_p2_rddata; +reg main_litedramcore_master_p2_rddata_en = 1'd0; +wire main_litedramcore_master_p2_rddata_valid; +reg main_litedramcore_master_p2_reset_n = 1'd0; +reg main_litedramcore_master_p2_we_n = 1'd1; +reg [31:0] main_litedramcore_master_p2_wrdata = 32'd0; +reg main_litedramcore_master_p2_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0; +reg main_litedramcore_master_p3_act_n = 1'd1; +reg [13:0] main_litedramcore_master_p3_address = 14'd0; +reg [2:0] main_litedramcore_master_p3_bank = 3'd0; +reg main_litedramcore_master_p3_cas_n = 1'd1; +reg main_litedramcore_master_p3_cke = 1'd0; +reg main_litedramcore_master_p3_cs_n = 1'd1; +reg main_litedramcore_master_p3_odt = 1'd0; +reg main_litedramcore_master_p3_ras_n = 1'd1; +wire [31:0] main_litedramcore_master_p3_rddata; +reg main_litedramcore_master_p3_rddata_en = 1'd0; +wire main_litedramcore_master_p3_rddata_valid; +reg main_litedramcore_master_p3_reset_n = 1'd0; +reg main_litedramcore_master_p3_we_n = 1'd1; +reg [31:0] main_litedramcore_master_p3_wrdata = 32'd0; +reg main_litedramcore_master_p3_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0; +wire main_litedramcore_max_time0; +wire main_litedramcore_max_time1; +reg [13:0] main_litedramcore_nop_a = 14'd0; +reg [2:0] main_litedramcore_nop_ba = 3'd0; +wire [1:0] main_litedramcore_nphases; +wire main_litedramcore_odt; +reg main_litedramcore_phaseinjector0_address_re = 1'd0; +reg [13:0] main_litedramcore_phaseinjector0_address_storage = 14'd0; +reg main_litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0; +wire main_litedramcore_phaseinjector0_command_issue_r; +reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector0_command_re = 1'd0; +reg [7:0] main_litedramcore_phaseinjector0_command_storage = 8'd0; +wire main_litedramcore_phaseinjector0_csrfield_cas; +wire main_litedramcore_phaseinjector0_csrfield_cs; +wire main_litedramcore_phaseinjector0_csrfield_cs_bottom; +wire main_litedramcore_phaseinjector0_csrfield_cs_top; +wire main_litedramcore_phaseinjector0_csrfield_ras; +wire main_litedramcore_phaseinjector0_csrfield_rden; +wire main_litedramcore_phaseinjector0_csrfield_we; +wire main_litedramcore_phaseinjector0_csrfield_wren; +reg main_litedramcore_phaseinjector0_rddata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector0_rddata_we; +reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector1_address_re = 1'd0; +reg [13:0] main_litedramcore_phaseinjector1_address_storage = 14'd0; +reg main_litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0; +wire main_litedramcore_phaseinjector1_command_issue_r; +reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector1_command_re = 1'd0; +reg [7:0] main_litedramcore_phaseinjector1_command_storage = 8'd0; +wire main_litedramcore_phaseinjector1_csrfield_cas; +wire main_litedramcore_phaseinjector1_csrfield_cs; +wire main_litedramcore_phaseinjector1_csrfield_cs_bottom; +wire main_litedramcore_phaseinjector1_csrfield_cs_top; +wire main_litedramcore_phaseinjector1_csrfield_ras; +wire main_litedramcore_phaseinjector1_csrfield_rden; +wire main_litedramcore_phaseinjector1_csrfield_we; +wire main_litedramcore_phaseinjector1_csrfield_wren; +reg main_litedramcore_phaseinjector1_rddata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector1_rddata_we; +reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector2_address_re = 1'd0; +reg [13:0] main_litedramcore_phaseinjector2_address_storage = 14'd0; +reg main_litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0; +wire main_litedramcore_phaseinjector2_command_issue_r; +reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector2_command_re = 1'd0; +reg [7:0] main_litedramcore_phaseinjector2_command_storage = 8'd0; +wire main_litedramcore_phaseinjector2_csrfield_cas; +wire main_litedramcore_phaseinjector2_csrfield_cs; +wire main_litedramcore_phaseinjector2_csrfield_cs_bottom; +wire main_litedramcore_phaseinjector2_csrfield_cs_top; +wire main_litedramcore_phaseinjector2_csrfield_ras; +wire main_litedramcore_phaseinjector2_csrfield_rden; +wire main_litedramcore_phaseinjector2_csrfield_we; +wire main_litedramcore_phaseinjector2_csrfield_wren; +reg main_litedramcore_phaseinjector2_rddata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector2_rddata_we; +reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector3_address_re = 1'd0; +reg [13:0] main_litedramcore_phaseinjector3_address_storage = 14'd0; +reg main_litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0; +wire main_litedramcore_phaseinjector3_command_issue_r; +reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector3_command_re = 1'd0; +reg [7:0] main_litedramcore_phaseinjector3_command_storage = 8'd0; +wire main_litedramcore_phaseinjector3_csrfield_cas; +wire main_litedramcore_phaseinjector3_csrfield_cs; +wire main_litedramcore_phaseinjector3_csrfield_cs_bottom; +wire main_litedramcore_phaseinjector3_csrfield_cs_top; +wire main_litedramcore_phaseinjector3_csrfield_ras; +wire main_litedramcore_phaseinjector3_csrfield_rden; +wire main_litedramcore_phaseinjector3_csrfield_we; +wire main_litedramcore_phaseinjector3_csrfield_wren; +reg main_litedramcore_phaseinjector3_rddata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0; +wire main_litedramcore_phaseinjector3_rddata_we; +reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0; +reg main_litedramcore_postponer_count = 1'd0; +wire main_litedramcore_postponer_req_i; +reg main_litedramcore_postponer_req_o = 1'd0; +wire main_litedramcore_ras_allowed; +wire [1:0] main_litedramcore_rdphase; +reg main_litedramcore_re = 1'd0; +wire main_litedramcore_read_available; +wire main_litedramcore_reset_n; +wire main_litedramcore_sel; +reg main_litedramcore_sequencer_count = 1'd0; +wire main_litedramcore_sequencer_done0; +reg main_litedramcore_sequencer_done1 = 1'd0; +reg main_litedramcore_sequencer_start0 = 1'd0; +wire main_litedramcore_sequencer_start1; +reg [5:0] main_litedramcore_sequencer_trigger = 6'd0; +wire main_litedramcore_slave_p0_act_n; +wire [13:0] main_litedramcore_slave_p0_address; +wire [2:0] main_litedramcore_slave_p0_bank; +wire main_litedramcore_slave_p0_cas_n; +wire main_litedramcore_slave_p0_cke; +wire main_litedramcore_slave_p0_cs_n; +wire main_litedramcore_slave_p0_odt; +wire main_litedramcore_slave_p0_ras_n; +reg [31:0] main_litedramcore_slave_p0_rddata = 32'd0; +wire main_litedramcore_slave_p0_rddata_en; +reg main_litedramcore_slave_p0_rddata_valid = 1'd0; +wire main_litedramcore_slave_p0_reset_n; +wire main_litedramcore_slave_p0_we_n; +wire [31:0] main_litedramcore_slave_p0_wrdata; +wire main_litedramcore_slave_p0_wrdata_en; +wire [3:0] main_litedramcore_slave_p0_wrdata_mask; +wire main_litedramcore_slave_p1_act_n; +wire [13:0] main_litedramcore_slave_p1_address; +wire [2:0] main_litedramcore_slave_p1_bank; +wire main_litedramcore_slave_p1_cas_n; +wire main_litedramcore_slave_p1_cke; +wire main_litedramcore_slave_p1_cs_n; +wire main_litedramcore_slave_p1_odt; +wire main_litedramcore_slave_p1_ras_n; +reg [31:0] main_litedramcore_slave_p1_rddata = 32'd0; +wire main_litedramcore_slave_p1_rddata_en; +reg main_litedramcore_slave_p1_rddata_valid = 1'd0; +wire main_litedramcore_slave_p1_reset_n; +wire main_litedramcore_slave_p1_we_n; +wire [31:0] main_litedramcore_slave_p1_wrdata; +wire main_litedramcore_slave_p1_wrdata_en; +wire [3:0] main_litedramcore_slave_p1_wrdata_mask; +wire main_litedramcore_slave_p2_act_n; +wire [13:0] main_litedramcore_slave_p2_address; +wire [2:0] main_litedramcore_slave_p2_bank; +wire main_litedramcore_slave_p2_cas_n; +wire main_litedramcore_slave_p2_cke; +wire main_litedramcore_slave_p2_cs_n; +wire main_litedramcore_slave_p2_odt; +wire main_litedramcore_slave_p2_ras_n; +reg [31:0] main_litedramcore_slave_p2_rddata = 32'd0; +wire main_litedramcore_slave_p2_rddata_en; +reg main_litedramcore_slave_p2_rddata_valid = 1'd0; +wire main_litedramcore_slave_p2_reset_n; +wire main_litedramcore_slave_p2_we_n; +wire [31:0] main_litedramcore_slave_p2_wrdata; +wire main_litedramcore_slave_p2_wrdata_en; +wire [3:0] main_litedramcore_slave_p2_wrdata_mask; +wire main_litedramcore_slave_p3_act_n; +wire [13:0] main_litedramcore_slave_p3_address; +wire [2:0] main_litedramcore_slave_p3_bank; +wire main_litedramcore_slave_p3_cas_n; +wire main_litedramcore_slave_p3_cke; +wire main_litedramcore_slave_p3_cs_n; +wire main_litedramcore_slave_p3_odt; +wire main_litedramcore_slave_p3_ras_n; +reg [31:0] main_litedramcore_slave_p3_rddata = 32'd0; +wire main_litedramcore_slave_p3_rddata_en; +reg main_litedramcore_slave_p3_rddata_valid = 1'd0; +wire main_litedramcore_slave_p3_reset_n; +wire main_litedramcore_slave_p3_we_n; +wire [31:0] main_litedramcore_slave_p3_wrdata; +wire main_litedramcore_slave_p3_wrdata_en; +wire [3:0] main_litedramcore_slave_p3_wrdata_mask; +reg [1:0] main_litedramcore_steerer0 = 2'd0; +reg [1:0] main_litedramcore_steerer1 = 2'd0; +reg main_litedramcore_steerer10 = 1'd1; +reg main_litedramcore_steerer11 = 1'd1; +reg [1:0] main_litedramcore_steerer2 = 2'd0; +reg [1:0] main_litedramcore_steerer3 = 2'd0; +reg main_litedramcore_steerer4 = 1'd1; +reg main_litedramcore_steerer5 = 1'd1; +reg main_litedramcore_steerer6 = 1'd1; +reg main_litedramcore_steerer7 = 1'd1; +reg main_litedramcore_steerer8 = 1'd1; +reg main_litedramcore_steerer9 = 1'd1; +reg [3:0] main_litedramcore_storage = 4'd1; +reg main_litedramcore_tccdcon_count = 1'd0; (* dont_touch = "true" *) -reg litedramcore_trrdcon_ready = 1'd0; -reg litedramcore_trrdcon_count = 1'd0; -wire litedramcore_tfawcon_valid; +reg main_litedramcore_tccdcon_ready = 1'd0; +wire main_litedramcore_tccdcon_valid; +wire [2:0] main_litedramcore_tfawcon_count; (* dont_touch = "true" *) -reg litedramcore_tfawcon_ready = 1'd1; -wire [2:0] litedramcore_tfawcon_count; -reg [4:0] litedramcore_tfawcon_window = 5'd0; -wire litedramcore_tccdcon_valid; +reg main_litedramcore_tfawcon_ready = 1'd1; +wire main_litedramcore_tfawcon_valid; +reg [4:0] main_litedramcore_tfawcon_window = 5'd0; +reg [4:0] main_litedramcore_time0 = 5'd0; +reg [3:0] main_litedramcore_time1 = 4'd0; +wire [9:0] main_litedramcore_timer_count0; +reg [9:0] main_litedramcore_timer_count1 = 10'd781; +wire main_litedramcore_timer_done0; +wire main_litedramcore_timer_done1; +wire main_litedramcore_timer_wait; +reg main_litedramcore_trrdcon_count = 1'd0; (* dont_touch = "true" *) -reg litedramcore_tccdcon_ready = 1'd0; -reg litedramcore_tccdcon_count = 1'd0; -wire litedramcore_twtrcon_valid; +reg main_litedramcore_trrdcon_ready = 1'd0; +wire main_litedramcore_trrdcon_valid; +reg [2:0] main_litedramcore_twtrcon_count = 3'd0; (* dont_touch = "true" *) -reg litedramcore_twtrcon_ready = 1'd0; -reg [2:0] litedramcore_twtrcon_count = 3'd0; -wire litedramcore_read_available; -wire litedramcore_write_available; -reg litedramcore_en0 = 1'd0; -wire litedramcore_max_time0; -reg [4:0] litedramcore_time0 = 5'd0; -reg litedramcore_en1 = 1'd0; -wire litedramcore_max_time1; -reg [3:0] litedramcore_time1 = 4'd0; -wire litedramcore_go_to_refresh; -reg init_done_storage = 1'd0; -reg init_done_re = 1'd0; -reg init_error_storage = 1'd0; -reg init_error_re = 1'd0; -wire [29:0] wb_bus_adr; -wire [31:0] wb_bus_dat_w; -wire [31:0] wb_bus_dat_r; -wire [3:0] wb_bus_sel; -wire wb_bus_cyc; -wire wb_bus_stb; -wire wb_bus_ack; -wire wb_bus_we; -wire [2:0] wb_bus_cti; -wire [1:0] wb_bus_bte; -wire wb_bus_err; -wire user_enable; -wire user_port_cmd_valid; -wire user_port_cmd_ready; -wire user_port_cmd_payload_we; -wire [23:0] user_port_cmd_payload_addr; -wire user_port_wdata_valid; -wire user_port_wdata_ready; -wire [127:0] user_port_wdata_payload_data; -wire [15:0] user_port_wdata_payload_we; -wire user_port_rdata_valid; -wire user_port_rdata_ready; -wire [127:0] user_port_rdata_payload_data; -reg [13:0] litedramcore_adr = 14'd0; -reg litedramcore_we = 1'd0; -reg [31:0] litedramcore_dat_w = 32'd0; -wire [31:0] litedramcore_dat_r; -wire [29:0] litedramcore_wishbone_adr; -wire [31:0] litedramcore_wishbone_dat_w; -reg [31:0] litedramcore_wishbone_dat_r = 32'd0; -wire [3:0] litedramcore_wishbone_sel; -wire litedramcore_wishbone_cyc; -wire litedramcore_wishbone_stb; -reg litedramcore_wishbone_ack = 1'd0; -wire litedramcore_wishbone_we; -wire [2:0] litedramcore_wishbone_cti; -wire [1:0] litedramcore_wishbone_bte; -reg litedramcore_wishbone_err = 1'd0; -wire [13:0] interface0_bank_bus_adr; -wire interface0_bank_bus_we; -wire [31:0] interface0_bank_bus_dat_w; -reg [31:0] interface0_bank_bus_dat_r = 32'd0; -reg csrbank0_init_done0_re = 1'd0; -wire csrbank0_init_done0_r; -reg csrbank0_init_done0_we = 1'd0; -wire csrbank0_init_done0_w; -reg csrbank0_init_error0_re = 1'd0; -wire csrbank0_init_error0_r; -reg csrbank0_init_error0_we = 1'd0; -wire csrbank0_init_error0_w; -wire csrbank0_sel; -wire [13:0] interface1_bank_bus_adr; -wire interface1_bank_bus_we; -wire [31:0] interface1_bank_bus_dat_w; -reg [31:0] interface1_bank_bus_dat_r = 32'd0; -reg csrbank1_rst0_re = 1'd0; -wire csrbank1_rst0_r; -reg csrbank1_rst0_we = 1'd0; -wire csrbank1_rst0_w; -reg csrbank1_dly_sel0_re = 1'd0; -wire [1:0] csrbank1_dly_sel0_r; -reg csrbank1_dly_sel0_we = 1'd0; -wire [1:0] csrbank1_dly_sel0_w; -reg csrbank1_half_sys8x_taps0_re = 1'd0; -wire [4:0] csrbank1_half_sys8x_taps0_r; -reg csrbank1_half_sys8x_taps0_we = 1'd0; -wire [4:0] csrbank1_half_sys8x_taps0_w; -reg csrbank1_wlevel_en0_re = 1'd0; -wire csrbank1_wlevel_en0_r; -reg csrbank1_wlevel_en0_we = 1'd0; -wire csrbank1_wlevel_en0_w; -reg csrbank1_rdphase0_re = 1'd0; -wire [1:0] csrbank1_rdphase0_r; -reg csrbank1_rdphase0_we = 1'd0; -wire [1:0] csrbank1_rdphase0_w; -reg csrbank1_wrphase0_re = 1'd0; -wire [1:0] csrbank1_wrphase0_r; -reg csrbank1_wrphase0_we = 1'd0; -wire [1:0] csrbank1_wrphase0_w; -wire csrbank1_sel; -wire [13:0] interface2_bank_bus_adr; -wire interface2_bank_bus_we; -wire [31:0] interface2_bank_bus_dat_w; -reg [31:0] interface2_bank_bus_dat_r = 32'd0; -reg csrbank2_dfii_control0_re = 1'd0; -wire [3:0] csrbank2_dfii_control0_r; -reg csrbank2_dfii_control0_we = 1'd0; -wire [3:0] csrbank2_dfii_control0_w; -reg csrbank2_dfii_pi0_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi0_command0_r; -reg csrbank2_dfii_pi0_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi0_command0_w; -reg csrbank2_dfii_pi0_address0_re = 1'd0; -wire [13:0] csrbank2_dfii_pi0_address0_r; -reg csrbank2_dfii_pi0_address0_we = 1'd0; -wire [13:0] csrbank2_dfii_pi0_address0_w; -reg csrbank2_dfii_pi0_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi0_baddress0_r; -reg csrbank2_dfii_pi0_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi0_baddress0_w; -reg csrbank2_dfii_pi0_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata0_r; -reg csrbank2_dfii_pi0_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata0_w; -reg csrbank2_dfii_pi0_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata_r; -reg csrbank2_dfii_pi0_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata_w; -reg csrbank2_dfii_pi1_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi1_command0_r; -reg csrbank2_dfii_pi1_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi1_command0_w; -reg csrbank2_dfii_pi1_address0_re = 1'd0; -wire [13:0] csrbank2_dfii_pi1_address0_r; -reg csrbank2_dfii_pi1_address0_we = 1'd0; -wire [13:0] csrbank2_dfii_pi1_address0_w; -reg csrbank2_dfii_pi1_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi1_baddress0_r; -reg csrbank2_dfii_pi1_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi1_baddress0_w; -reg csrbank2_dfii_pi1_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata0_r; -reg csrbank2_dfii_pi1_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata0_w; -reg csrbank2_dfii_pi1_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata_r; -reg csrbank2_dfii_pi1_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata_w; -reg csrbank2_dfii_pi2_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi2_command0_r; -reg csrbank2_dfii_pi2_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi2_command0_w; -reg csrbank2_dfii_pi2_address0_re = 1'd0; -wire [13:0] csrbank2_dfii_pi2_address0_r; -reg csrbank2_dfii_pi2_address0_we = 1'd0; -wire [13:0] csrbank2_dfii_pi2_address0_w; -reg csrbank2_dfii_pi2_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi2_baddress0_r; -reg csrbank2_dfii_pi2_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi2_baddress0_w; -reg csrbank2_dfii_pi2_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi2_wrdata0_r; -reg csrbank2_dfii_pi2_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi2_wrdata0_w; -reg csrbank2_dfii_pi2_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi2_rddata_r; -reg csrbank2_dfii_pi2_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi2_rddata_w; -reg csrbank2_dfii_pi3_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi3_command0_r; -reg csrbank2_dfii_pi3_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi3_command0_w; -reg csrbank2_dfii_pi3_address0_re = 1'd0; -wire [13:0] csrbank2_dfii_pi3_address0_r; -reg csrbank2_dfii_pi3_address0_we = 1'd0; -wire [13:0] csrbank2_dfii_pi3_address0_w; -reg csrbank2_dfii_pi3_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi3_baddress0_r; -reg csrbank2_dfii_pi3_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi3_baddress0_w; -reg csrbank2_dfii_pi3_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi3_wrdata0_r; -reg csrbank2_dfii_pi3_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi3_wrdata0_w; -reg csrbank2_dfii_pi3_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi3_rddata_r; -reg csrbank2_dfii_pi3_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi3_rddata_w; -wire csrbank2_sel; -wire [13:0] csr_interconnect_adr; -wire csr_interconnect_we; -wire [31:0] csr_interconnect_dat_w; -wire [31:0] csr_interconnect_dat_r; -wire litedramcore_reset0; -wire litedramcore_reset1; -wire litedramcore_reset2; -wire litedramcore_reset3; -wire litedramcore_reset4; -wire litedramcore_reset5; -wire litedramcore_reset6; -wire litedramcore_reset7; -wire litedramcore_pll_fb; -reg [1:0] litedramcore_refresher_state = 2'd0; -reg [1:0] litedramcore_refresher_next_state = 2'd0; -reg [3:0] litedramcore_bankmachine0_state = 4'd0; -reg [3:0] litedramcore_bankmachine0_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine1_state = 4'd0; -reg [3:0] litedramcore_bankmachine1_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine2_state = 4'd0; -reg [3:0] litedramcore_bankmachine2_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine3_state = 4'd0; -reg [3:0] litedramcore_bankmachine3_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine4_state = 4'd0; -reg [3:0] litedramcore_bankmachine4_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine5_state = 4'd0; -reg [3:0] litedramcore_bankmachine5_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine6_state = 4'd0; -reg [3:0] litedramcore_bankmachine6_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine7_state = 4'd0; -reg [3:0] litedramcore_bankmachine7_next_state = 4'd0; -reg [3:0] litedramcore_multiplexer_state = 4'd0; -reg [3:0] litedramcore_multiplexer_next_state = 4'd0; -wire litedramcore_roundrobin0_request; -wire litedramcore_roundrobin0_grant; -wire litedramcore_roundrobin0_ce; -wire litedramcore_roundrobin1_request; -wire litedramcore_roundrobin1_grant; -wire litedramcore_roundrobin1_ce; -wire litedramcore_roundrobin2_request; -wire litedramcore_roundrobin2_grant; -wire litedramcore_roundrobin2_ce; -wire litedramcore_roundrobin3_request; -wire litedramcore_roundrobin3_grant; -wire litedramcore_roundrobin3_ce; -wire litedramcore_roundrobin4_request; -wire litedramcore_roundrobin4_grant; -wire litedramcore_roundrobin4_ce; -wire litedramcore_roundrobin5_request; -wire litedramcore_roundrobin5_grant; -wire litedramcore_roundrobin5_ce; -wire litedramcore_roundrobin6_request; -wire litedramcore_roundrobin6_grant; -wire litedramcore_roundrobin6_ce; -wire litedramcore_roundrobin7_request; -wire litedramcore_roundrobin7_grant; -wire litedramcore_roundrobin7_ce; -reg litedramcore_locked0 = 1'd0; -reg litedramcore_locked1 = 1'd0; -reg litedramcore_locked2 = 1'd0; -reg litedramcore_locked3 = 1'd0; -reg litedramcore_locked4 = 1'd0; -reg litedramcore_locked5 = 1'd0; -reg litedramcore_locked6 = 1'd0; -reg litedramcore_locked7 = 1'd0; -reg litedramcore_new_master_wdata_ready0 = 1'd0; -reg litedramcore_new_master_wdata_ready1 = 1'd0; -reg litedramcore_new_master_rdata_valid0 = 1'd0; -reg litedramcore_new_master_rdata_valid1 = 1'd0; -reg litedramcore_new_master_rdata_valid2 = 1'd0; -reg litedramcore_new_master_rdata_valid3 = 1'd0; -reg litedramcore_new_master_rdata_valid4 = 1'd0; -reg litedramcore_new_master_rdata_valid5 = 1'd0; -reg litedramcore_new_master_rdata_valid6 = 1'd0; -reg litedramcore_new_master_rdata_valid7 = 1'd0; -reg litedramcore_new_master_rdata_valid8 = 1'd0; -reg [1:0] litedramcore_state = 2'd0; -reg [1:0] litedramcore_next_state = 2'd0; -reg [31:0] litedramcore_dat_w_next_value0 = 32'd0; -reg litedramcore_dat_w_next_value_ce0 = 1'd0; -reg [13:0] litedramcore_adr_next_value1 = 14'd0; -reg litedramcore_adr_next_value_ce1 = 1'd0; -reg litedramcore_we_next_value2 = 1'd0; -reg litedramcore_we_next_value_ce2 = 1'd0; -reg rhs_array_muxed0 = 1'd0; -reg [13:0] rhs_array_muxed1 = 14'd0; -reg [2:0] rhs_array_muxed2 = 3'd0; -reg rhs_array_muxed3 = 1'd0; -reg rhs_array_muxed4 = 1'd0; -reg rhs_array_muxed5 = 1'd0; -reg t_array_muxed0 = 1'd0; -reg t_array_muxed1 = 1'd0; -reg t_array_muxed2 = 1'd0; -reg rhs_array_muxed6 = 1'd0; -reg [13:0] rhs_array_muxed7 = 14'd0; -reg [2:0] rhs_array_muxed8 = 3'd0; -reg rhs_array_muxed9 = 1'd0; -reg rhs_array_muxed10 = 1'd0; -reg rhs_array_muxed11 = 1'd0; -reg t_array_muxed3 = 1'd0; -reg t_array_muxed4 = 1'd0; -reg t_array_muxed5 = 1'd0; -reg [20:0] rhs_array_muxed12 = 21'd0; -reg rhs_array_muxed13 = 1'd0; -reg rhs_array_muxed14 = 1'd0; -reg [20:0] rhs_array_muxed15 = 21'd0; -reg rhs_array_muxed16 = 1'd0; -reg rhs_array_muxed17 = 1'd0; -reg [20:0] rhs_array_muxed18 = 21'd0; -reg rhs_array_muxed19 = 1'd0; -reg rhs_array_muxed20 = 1'd0; -reg [20:0] rhs_array_muxed21 = 21'd0; -reg rhs_array_muxed22 = 1'd0; -reg rhs_array_muxed23 = 1'd0; -reg [20:0] rhs_array_muxed24 = 21'd0; -reg rhs_array_muxed25 = 1'd0; -reg rhs_array_muxed26 = 1'd0; -reg [20:0] rhs_array_muxed27 = 21'd0; -reg rhs_array_muxed28 = 1'd0; -reg rhs_array_muxed29 = 1'd0; -reg [20:0] rhs_array_muxed30 = 21'd0; -reg rhs_array_muxed31 = 1'd0; -reg rhs_array_muxed32 = 1'd0; -reg [20:0] rhs_array_muxed33 = 21'd0; -reg rhs_array_muxed34 = 1'd0; -reg rhs_array_muxed35 = 1'd0; -reg [2:0] array_muxed0 = 3'd0; -reg [13:0] array_muxed1 = 14'd0; -reg array_muxed2 = 1'd0; -reg array_muxed3 = 1'd0; -reg array_muxed4 = 1'd0; -reg array_muxed5 = 1'd0; -reg array_muxed6 = 1'd0; -reg [2:0] array_muxed7 = 3'd0; -reg [13:0] array_muxed8 = 14'd0; -reg array_muxed9 = 1'd0; -reg array_muxed10 = 1'd0; -reg array_muxed11 = 1'd0; -reg array_muxed12 = 1'd0; -reg array_muxed13 = 1'd0; -reg [2:0] array_muxed14 = 3'd0; -reg [13:0] array_muxed15 = 14'd0; -reg array_muxed16 = 1'd0; -reg array_muxed17 = 1'd0; -reg array_muxed18 = 1'd0; -reg array_muxed19 = 1'd0; -reg array_muxed20 = 1'd0; -reg [2:0] array_muxed21 = 3'd0; -reg [13:0] array_muxed22 = 14'd0; -reg array_muxed23 = 1'd0; -reg array_muxed24 = 1'd0; -reg array_muxed25 = 1'd0; -reg array_muxed26 = 1'd0; -reg array_muxed27 = 1'd0; -wire xilinxasyncresetsynchronizerimpl0; -wire xilinxasyncresetsynchronizerimpl0_rst_meta; -wire xilinxasyncresetsynchronizerimpl1; -wire xilinxasyncresetsynchronizerimpl1_rst_meta; -wire xilinxasyncresetsynchronizerimpl2; -wire xilinxasyncresetsynchronizerimpl2_rst_meta; -wire xilinxasyncresetsynchronizerimpl2_expr; -wire xilinxasyncresetsynchronizerimpl3; -wire xilinxasyncresetsynchronizerimpl3_rst_meta; -wire xilinxasyncresetsynchronizerimpl3_expr; +reg main_litedramcore_twtrcon_ready = 1'd0; +wire main_litedramcore_twtrcon_valid; +wire main_litedramcore_wants_refresh; +wire main_litedramcore_wants_zqcs; +wire main_litedramcore_write_available; +reg main_litedramcore_zqcs_executer_done = 1'd0; +reg main_litedramcore_zqcs_executer_start = 1'd0; +reg [4:0] main_litedramcore_zqcs_executer_trigger = 5'd0; +wire [26:0] main_litedramcore_zqcs_timer_count0; +reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999; +wire main_litedramcore_zqcs_timer_done0; +wire main_litedramcore_zqcs_timer_done1; +wire main_litedramcore_zqcs_timer_wait; +wire main_locked; +reg main_power_down = 1'd0; +wire main_reset; +reg [3:0] main_reset_counter = 4'd15; +reg main_rst = 1'd0; +wire main_user_enable; +wire [23:0] main_user_port_cmd_payload_addr; +wire main_user_port_cmd_payload_we; +wire main_user_port_cmd_ready; +wire main_user_port_cmd_valid; +wire [127:0] main_user_port_rdata_payload_data; +wire main_user_port_rdata_ready; +wire main_user_port_rdata_valid; +wire [127:0] main_user_port_wdata_payload_data; +wire [15:0] main_user_port_wdata_payload_we; +wire main_user_port_wdata_ready; +wire main_user_port_wdata_valid; +wire main_wb_bus_ack; +wire [29:0] main_wb_bus_adr; +wire [1:0] main_wb_bus_bte; +wire [2:0] main_wb_bus_cti; +wire main_wb_bus_cyc; +wire [31:0] main_wb_bus_dat_r; +wire [31:0] main_wb_bus_dat_w; +wire main_wb_bus_err; +wire [3:0] main_wb_bus_sel; +wire main_wb_bus_stb; +wire main_wb_bus_we; +wire sys4x_clk; +wire sys4x_dqs_clk; +wire sys_clk; +wire sys_rst; //------------------------------------------------------------------------------ // Combinatorial Logic //------------------------------------------------------------------------------ -assign init_done = init_done_storage; -assign init_error = init_error_storage; -assign wb_bus_adr = wb_ctrl_adr; -assign wb_bus_dat_w = wb_ctrl_dat_w; -assign wb_ctrl_dat_r = wb_bus_dat_r; -assign wb_bus_sel = wb_ctrl_sel; -assign wb_bus_cyc = wb_ctrl_cyc; -assign wb_bus_stb = wb_ctrl_stb; -assign wb_ctrl_ack = wb_bus_ack; -assign wb_bus_we = wb_ctrl_we; -assign wb_bus_cti = wb_ctrl_cti; -assign wb_bus_bte = wb_ctrl_bte; -assign wb_ctrl_err = wb_bus_err; +assign init_done = main_init_done_storage; +assign init_error = main_init_error_storage; +assign main_wb_bus_adr = wb_ctrl_adr; +assign main_wb_bus_dat_w = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = main_wb_bus_dat_r; +assign main_wb_bus_sel = wb_ctrl_sel; +assign main_wb_bus_cyc = wb_ctrl_cyc; +assign main_wb_bus_stb = wb_ctrl_stb; +assign wb_ctrl_ack = main_wb_bus_ack; +assign main_wb_bus_we = wb_ctrl_we; +assign main_wb_bus_cti = wb_ctrl_cti; +assign main_wb_bus_bte = wb_ctrl_bte; +assign wb_ctrl_err = main_wb_bus_err; assign user_clk = sys_clk; assign user_rst = sys_rst; -assign user_enable = 1'd1; -assign user_port_cmd_valid = (user_port_native_0_cmd_valid & user_enable); -assign user_port_native_0_cmd_ready = (user_port_cmd_ready & user_enable); -assign user_port_cmd_payload_we = user_port_native_0_cmd_we; -assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr; -assign user_port_wdata_valid = (user_port_native_0_wdata_valid & user_enable); -assign user_port_native_0_wdata_ready = (user_port_wdata_ready & user_enable); -assign user_port_wdata_payload_we = user_port_native_0_wdata_we; -assign user_port_wdata_payload_data = user_port_native_0_wdata_data; -assign user_port_native_0_rdata_valid = (user_port_rdata_valid & user_enable); -assign user_port_rdata_ready = (user_port_native_0_rdata_ready & user_enable); -assign user_port_native_0_rdata_data = user_port_rdata_payload_data; -assign reset = (rst | rst_1); -assign pll_locked = locked; -assign clkin = clk; -assign iodelay_clk = clkout_buf0; -assign sys_clk = clkout_buf1; -assign sys4x_clk = clkout_buf2; -assign sys4x_dqs_clk = clkout_buf3; -assign ddram_ba = a7ddrphy_pads_ba; -assign a7ddrphy_dqs_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dqs_oe) | a7ddrphy_dqs_postamble); -assign a7ddrphy_dq_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dq_oe) | a7ddrphy_dqs_postamble); -always @(*) begin - a7ddrphy_dfi_p0_rddata <= 32'd0; - a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0]; - a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1]; - a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0]; - a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1]; - a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0]; - a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1]; - a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0]; - a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1]; - a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0]; - a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1]; - a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0]; - a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1]; - a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0]; - a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1]; - a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0]; - a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1]; - a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0]; - a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1]; - a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0]; - a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1]; - a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0]; - a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1]; - a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0]; - a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1]; - a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0]; - a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1]; - a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0]; - a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1]; - a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0]; - a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1]; - a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0]; - a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1]; -end -always @(*) begin - a7ddrphy_dfi_p1_rddata <= 32'd0; - a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2]; - a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3]; - a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2]; - a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3]; - a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2]; - a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3]; - a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2]; - a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3]; - a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2]; - a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3]; - a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2]; - a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3]; - a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2]; - a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3]; - a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2]; - a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3]; - a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2]; - a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3]; - a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2]; - a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3]; - a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2]; - a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3]; - a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2]; - a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3]; - a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2]; - a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3]; - a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2]; - a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3]; - a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2]; - a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3]; - a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2]; - a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3]; -end -always @(*) begin - a7ddrphy_dfi_p2_rddata <= 32'd0; - a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4]; - a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5]; - a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4]; - a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5]; - a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4]; - a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5]; - a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4]; - a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5]; - a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4]; - a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5]; - a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4]; - a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5]; - a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4]; - a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5]; - a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4]; - a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5]; - a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4]; - a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5]; - a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4]; - a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5]; - a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4]; - a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5]; - a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4]; - a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5]; - a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4]; - a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5]; - a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4]; - a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5]; - a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4]; - a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5]; - a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4]; - a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5]; -end -always @(*) begin - a7ddrphy_dfi_p3_rddata <= 32'd0; - a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6]; - a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7]; - a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6]; - a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7]; - a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6]; - a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7]; - a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6]; - a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7]; - a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6]; - a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7]; - a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6]; - a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7]; - a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6]; - a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7]; - a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6]; - a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7]; - a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6]; - a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7]; - a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6]; - a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7]; - a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6]; - a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7]; - a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6]; - a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7]; - a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6]; - a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7]; - a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6]; - a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7]; - a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6]; - a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7]; - a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6]; - a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7]; -end -assign a7ddrphy_dfi_p0_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); -assign a7ddrphy_dfi_p1_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); -assign a7ddrphy_dfi_p2_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); -assign a7ddrphy_dfi_p3_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); -assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en_tappeddelayline1; -always @(*) begin - a7ddrphy_dqs_oe <= 1'd0; - if (a7ddrphy_wlevel_en_storage) begin - a7ddrphy_dqs_oe <= 1'd1; - end else begin - a7ddrphy_dqs_oe <= a7ddrphy_dq_oe; - end -end -assign a7ddrphy_dqs_preamble = (a7ddrphy_wrdata_en_tappeddelayline0 & (~a7ddrphy_wrdata_en_tappeddelayline1)); -assign a7ddrphy_dqs_postamble = (a7ddrphy_wrdata_en_tappeddelayline2 & (~a7ddrphy_wrdata_en_tappeddelayline1)); -always @(*) begin - a7ddrphy_dqspattern_o0 <= 8'd0; - a7ddrphy_dqspattern_o0 <= 7'd85; - if (a7ddrphy_dqspattern0) begin - a7ddrphy_dqspattern_o0 <= 5'd21; - end - if (a7ddrphy_dqspattern1) begin - a7ddrphy_dqspattern_o0 <= 7'd84; - end - if (a7ddrphy_wlevel_en_storage) begin - a7ddrphy_dqspattern_o0 <= 1'd0; - if (a7ddrphy_wlevel_strobe_re) begin - a7ddrphy_dqspattern_o0 <= 1'd1; - end - end -end -always @(*) begin - a7ddrphy_bitslip00 <= 8'd0; - case (a7ddrphy_bitslip0_value0) +assign main_user_enable = 1'd1; +assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable); +assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable); +assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we; +assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr; +assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable); +assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable); +assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we; +assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data; +assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable); +assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable); +assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data; +assign builder_interface0_adr = main_wb_bus_adr; +assign builder_interface0_dat_w = main_wb_bus_dat_w; +assign main_wb_bus_dat_r = builder_interface0_dat_r; +assign builder_interface0_sel = main_wb_bus_sel; +assign builder_interface0_cyc = main_wb_bus_cyc; +assign builder_interface0_stb = main_wb_bus_stb; +assign main_wb_bus_ack = builder_interface0_ack; +assign builder_interface0_we = main_wb_bus_we; +assign builder_interface0_cti = main_wb_bus_cti; +assign builder_interface0_bte = main_wb_bus_bte; +assign main_wb_bus_err = builder_interface0_err; +assign main_reset = (rst | main_rst); +assign pll_locked = main_locked; +assign main_clkin = clk; +assign iodelay_clk = main_clkout_buf0; +assign sys_clk = main_clkout_buf1; +assign sys4x_clk = main_clkout_buf2; +assign sys4x_dqs_clk = main_clkout_buf3; +assign ddram_ba = main_a7ddrphy_pads_ba; +assign main_a7ddrphy_dqs_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_oe) | main_a7ddrphy_dqs_postamble); +assign main_a7ddrphy_dq_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dq_oe) | main_a7ddrphy_dqs_postamble); +always @(*) begin + main_a7ddrphy_dfi_p0_rddata <= 32'd0; + main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip04[0]; + main_a7ddrphy_dfi_p0_rddata[16] <= main_a7ddrphy_bitslip04[1]; + main_a7ddrphy_dfi_p0_rddata[1] <= main_a7ddrphy_bitslip14[0]; + main_a7ddrphy_dfi_p0_rddata[17] <= main_a7ddrphy_bitslip14[1]; + main_a7ddrphy_dfi_p0_rddata[2] <= main_a7ddrphy_bitslip22[0]; + main_a7ddrphy_dfi_p0_rddata[18] <= main_a7ddrphy_bitslip22[1]; + main_a7ddrphy_dfi_p0_rddata[3] <= main_a7ddrphy_bitslip32[0]; + main_a7ddrphy_dfi_p0_rddata[19] <= main_a7ddrphy_bitslip32[1]; + main_a7ddrphy_dfi_p0_rddata[4] <= main_a7ddrphy_bitslip42[0]; + main_a7ddrphy_dfi_p0_rddata[20] <= main_a7ddrphy_bitslip42[1]; + main_a7ddrphy_dfi_p0_rddata[5] <= main_a7ddrphy_bitslip52[0]; + main_a7ddrphy_dfi_p0_rddata[21] <= main_a7ddrphy_bitslip52[1]; + main_a7ddrphy_dfi_p0_rddata[6] <= main_a7ddrphy_bitslip62[0]; + main_a7ddrphy_dfi_p0_rddata[22] <= main_a7ddrphy_bitslip62[1]; + main_a7ddrphy_dfi_p0_rddata[7] <= main_a7ddrphy_bitslip72[0]; + main_a7ddrphy_dfi_p0_rddata[23] <= main_a7ddrphy_bitslip72[1]; + main_a7ddrphy_dfi_p0_rddata[8] <= main_a7ddrphy_bitslip82[0]; + main_a7ddrphy_dfi_p0_rddata[24] <= main_a7ddrphy_bitslip82[1]; + main_a7ddrphy_dfi_p0_rddata[9] <= main_a7ddrphy_bitslip92[0]; + main_a7ddrphy_dfi_p0_rddata[25] <= main_a7ddrphy_bitslip92[1]; + main_a7ddrphy_dfi_p0_rddata[10] <= main_a7ddrphy_bitslip102[0]; + main_a7ddrphy_dfi_p0_rddata[26] <= main_a7ddrphy_bitslip102[1]; + main_a7ddrphy_dfi_p0_rddata[11] <= main_a7ddrphy_bitslip112[0]; + main_a7ddrphy_dfi_p0_rddata[27] <= main_a7ddrphy_bitslip112[1]; + main_a7ddrphy_dfi_p0_rddata[12] <= main_a7ddrphy_bitslip122[0]; + main_a7ddrphy_dfi_p0_rddata[28] <= main_a7ddrphy_bitslip122[1]; + main_a7ddrphy_dfi_p0_rddata[13] <= main_a7ddrphy_bitslip132[0]; + main_a7ddrphy_dfi_p0_rddata[29] <= main_a7ddrphy_bitslip132[1]; + main_a7ddrphy_dfi_p0_rddata[14] <= main_a7ddrphy_bitslip142[0]; + main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip142[1]; + main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip152[0]; + main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip152[1]; +end +always @(*) begin + main_a7ddrphy_dfi_p1_rddata <= 32'd0; + main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip04[2]; + main_a7ddrphy_dfi_p1_rddata[16] <= main_a7ddrphy_bitslip04[3]; + main_a7ddrphy_dfi_p1_rddata[1] <= main_a7ddrphy_bitslip14[2]; + main_a7ddrphy_dfi_p1_rddata[17] <= main_a7ddrphy_bitslip14[3]; + main_a7ddrphy_dfi_p1_rddata[2] <= main_a7ddrphy_bitslip22[2]; + main_a7ddrphy_dfi_p1_rddata[18] <= main_a7ddrphy_bitslip22[3]; + main_a7ddrphy_dfi_p1_rddata[3] <= main_a7ddrphy_bitslip32[2]; + main_a7ddrphy_dfi_p1_rddata[19] <= main_a7ddrphy_bitslip32[3]; + main_a7ddrphy_dfi_p1_rddata[4] <= main_a7ddrphy_bitslip42[2]; + main_a7ddrphy_dfi_p1_rddata[20] <= main_a7ddrphy_bitslip42[3]; + main_a7ddrphy_dfi_p1_rddata[5] <= main_a7ddrphy_bitslip52[2]; + main_a7ddrphy_dfi_p1_rddata[21] <= main_a7ddrphy_bitslip52[3]; + main_a7ddrphy_dfi_p1_rddata[6] <= main_a7ddrphy_bitslip62[2]; + main_a7ddrphy_dfi_p1_rddata[22] <= main_a7ddrphy_bitslip62[3]; + main_a7ddrphy_dfi_p1_rddata[7] <= main_a7ddrphy_bitslip72[2]; + main_a7ddrphy_dfi_p1_rddata[23] <= main_a7ddrphy_bitslip72[3]; + main_a7ddrphy_dfi_p1_rddata[8] <= main_a7ddrphy_bitslip82[2]; + main_a7ddrphy_dfi_p1_rddata[24] <= main_a7ddrphy_bitslip82[3]; + main_a7ddrphy_dfi_p1_rddata[9] <= main_a7ddrphy_bitslip92[2]; + main_a7ddrphy_dfi_p1_rddata[25] <= main_a7ddrphy_bitslip92[3]; + main_a7ddrphy_dfi_p1_rddata[10] <= main_a7ddrphy_bitslip102[2]; + main_a7ddrphy_dfi_p1_rddata[26] <= main_a7ddrphy_bitslip102[3]; + main_a7ddrphy_dfi_p1_rddata[11] <= main_a7ddrphy_bitslip112[2]; + main_a7ddrphy_dfi_p1_rddata[27] <= main_a7ddrphy_bitslip112[3]; + main_a7ddrphy_dfi_p1_rddata[12] <= main_a7ddrphy_bitslip122[2]; + main_a7ddrphy_dfi_p1_rddata[28] <= main_a7ddrphy_bitslip122[3]; + main_a7ddrphy_dfi_p1_rddata[13] <= main_a7ddrphy_bitslip132[2]; + main_a7ddrphy_dfi_p1_rddata[29] <= main_a7ddrphy_bitslip132[3]; + main_a7ddrphy_dfi_p1_rddata[14] <= main_a7ddrphy_bitslip142[2]; + main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip142[3]; + main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip152[2]; + main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip152[3]; +end +always @(*) begin + main_a7ddrphy_dfi_p2_rddata <= 32'd0; + main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip04[4]; + main_a7ddrphy_dfi_p2_rddata[16] <= main_a7ddrphy_bitslip04[5]; + main_a7ddrphy_dfi_p2_rddata[1] <= main_a7ddrphy_bitslip14[4]; + main_a7ddrphy_dfi_p2_rddata[17] <= main_a7ddrphy_bitslip14[5]; + main_a7ddrphy_dfi_p2_rddata[2] <= main_a7ddrphy_bitslip22[4]; + main_a7ddrphy_dfi_p2_rddata[18] <= main_a7ddrphy_bitslip22[5]; + main_a7ddrphy_dfi_p2_rddata[3] <= main_a7ddrphy_bitslip32[4]; + main_a7ddrphy_dfi_p2_rddata[19] <= main_a7ddrphy_bitslip32[5]; + main_a7ddrphy_dfi_p2_rddata[4] <= main_a7ddrphy_bitslip42[4]; + main_a7ddrphy_dfi_p2_rddata[20] <= main_a7ddrphy_bitslip42[5]; + main_a7ddrphy_dfi_p2_rddata[5] <= main_a7ddrphy_bitslip52[4]; + main_a7ddrphy_dfi_p2_rddata[21] <= main_a7ddrphy_bitslip52[5]; + main_a7ddrphy_dfi_p2_rddata[6] <= main_a7ddrphy_bitslip62[4]; + main_a7ddrphy_dfi_p2_rddata[22] <= main_a7ddrphy_bitslip62[5]; + main_a7ddrphy_dfi_p2_rddata[7] <= main_a7ddrphy_bitslip72[4]; + main_a7ddrphy_dfi_p2_rddata[23] <= main_a7ddrphy_bitslip72[5]; + main_a7ddrphy_dfi_p2_rddata[8] <= main_a7ddrphy_bitslip82[4]; + main_a7ddrphy_dfi_p2_rddata[24] <= main_a7ddrphy_bitslip82[5]; + main_a7ddrphy_dfi_p2_rddata[9] <= main_a7ddrphy_bitslip92[4]; + main_a7ddrphy_dfi_p2_rddata[25] <= main_a7ddrphy_bitslip92[5]; + main_a7ddrphy_dfi_p2_rddata[10] <= main_a7ddrphy_bitslip102[4]; + main_a7ddrphy_dfi_p2_rddata[26] <= main_a7ddrphy_bitslip102[5]; + main_a7ddrphy_dfi_p2_rddata[11] <= main_a7ddrphy_bitslip112[4]; + main_a7ddrphy_dfi_p2_rddata[27] <= main_a7ddrphy_bitslip112[5]; + main_a7ddrphy_dfi_p2_rddata[12] <= main_a7ddrphy_bitslip122[4]; + main_a7ddrphy_dfi_p2_rddata[28] <= main_a7ddrphy_bitslip122[5]; + main_a7ddrphy_dfi_p2_rddata[13] <= main_a7ddrphy_bitslip132[4]; + main_a7ddrphy_dfi_p2_rddata[29] <= main_a7ddrphy_bitslip132[5]; + main_a7ddrphy_dfi_p2_rddata[14] <= main_a7ddrphy_bitslip142[4]; + main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip142[5]; + main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip152[4]; + main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip152[5]; +end +always @(*) begin + main_a7ddrphy_dfi_p3_rddata <= 32'd0; + main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip04[6]; + main_a7ddrphy_dfi_p3_rddata[16] <= main_a7ddrphy_bitslip04[7]; + main_a7ddrphy_dfi_p3_rddata[1] <= main_a7ddrphy_bitslip14[6]; + main_a7ddrphy_dfi_p3_rddata[17] <= main_a7ddrphy_bitslip14[7]; + main_a7ddrphy_dfi_p3_rddata[2] <= main_a7ddrphy_bitslip22[6]; + main_a7ddrphy_dfi_p3_rddata[18] <= main_a7ddrphy_bitslip22[7]; + main_a7ddrphy_dfi_p3_rddata[3] <= main_a7ddrphy_bitslip32[6]; + main_a7ddrphy_dfi_p3_rddata[19] <= main_a7ddrphy_bitslip32[7]; + main_a7ddrphy_dfi_p3_rddata[4] <= main_a7ddrphy_bitslip42[6]; + main_a7ddrphy_dfi_p3_rddata[20] <= main_a7ddrphy_bitslip42[7]; + main_a7ddrphy_dfi_p3_rddata[5] <= main_a7ddrphy_bitslip52[6]; + main_a7ddrphy_dfi_p3_rddata[21] <= main_a7ddrphy_bitslip52[7]; + main_a7ddrphy_dfi_p3_rddata[6] <= main_a7ddrphy_bitslip62[6]; + main_a7ddrphy_dfi_p3_rddata[22] <= main_a7ddrphy_bitslip62[7]; + main_a7ddrphy_dfi_p3_rddata[7] <= main_a7ddrphy_bitslip72[6]; + main_a7ddrphy_dfi_p3_rddata[23] <= main_a7ddrphy_bitslip72[7]; + main_a7ddrphy_dfi_p3_rddata[8] <= main_a7ddrphy_bitslip82[6]; + main_a7ddrphy_dfi_p3_rddata[24] <= main_a7ddrphy_bitslip82[7]; + main_a7ddrphy_dfi_p3_rddata[9] <= main_a7ddrphy_bitslip92[6]; + main_a7ddrphy_dfi_p3_rddata[25] <= main_a7ddrphy_bitslip92[7]; + main_a7ddrphy_dfi_p3_rddata[10] <= main_a7ddrphy_bitslip102[6]; + main_a7ddrphy_dfi_p3_rddata[26] <= main_a7ddrphy_bitslip102[7]; + main_a7ddrphy_dfi_p3_rddata[11] <= main_a7ddrphy_bitslip112[6]; + main_a7ddrphy_dfi_p3_rddata[27] <= main_a7ddrphy_bitslip112[7]; + main_a7ddrphy_dfi_p3_rddata[12] <= main_a7ddrphy_bitslip122[6]; + main_a7ddrphy_dfi_p3_rddata[28] <= main_a7ddrphy_bitslip122[7]; + main_a7ddrphy_dfi_p3_rddata[13] <= main_a7ddrphy_bitslip132[6]; + main_a7ddrphy_dfi_p3_rddata[29] <= main_a7ddrphy_bitslip132[7]; + main_a7ddrphy_dfi_p3_rddata[14] <= main_a7ddrphy_bitslip142[6]; + main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip142[7]; + main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip152[6]; + main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip152[7]; +end +assign main_a7ddrphy_dfi_p0_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dfi_p1_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dfi_p2_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dfi_p3_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); +assign main_a7ddrphy_dq_oe = main_a7ddrphy_wrdata_en_tappeddelayline1; +always @(*) begin + main_a7ddrphy_dqs_oe <= 1'd0; + if (main_a7ddrphy_wlevel_en_storage) begin + main_a7ddrphy_dqs_oe <= 1'd1; + end else begin + main_a7ddrphy_dqs_oe <= main_a7ddrphy_dq_oe; + end +end +assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_wrdata_en_tappeddelayline0 & (~main_a7ddrphy_wrdata_en_tappeddelayline1)); +assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_wrdata_en_tappeddelayline2 & (~main_a7ddrphy_wrdata_en_tappeddelayline1)); +always @(*) begin + main_a7ddrphy_dqspattern_o0 <= 8'd0; + main_a7ddrphy_dqspattern_o0 <= 7'd85; + if (main_a7ddrphy_dqspattern0) begin + main_a7ddrphy_dqspattern_o0 <= 5'd21; + end + if (main_a7ddrphy_dqspattern1) begin + main_a7ddrphy_dqspattern_o0 <= 7'd84; + end + if (main_a7ddrphy_wlevel_en_storage) begin + main_a7ddrphy_dqspattern_o0 <= 1'd0; + if (main_a7ddrphy_wlevel_strobe_re) begin + main_a7ddrphy_dqspattern_o0 <= 1'd1; + end + end +end +always @(*) begin + main_a7ddrphy_bitslip00 <= 8'd0; + case (main_a7ddrphy_bitslip0_value0) 1'd0: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8]; + main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip10 <= 8'd0; - case (a7ddrphy_bitslip1_value0) + main_a7ddrphy_bitslip10 <= 8'd0; + case (main_a7ddrphy_bitslip1_value0) 1'd0: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8]; + main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip01 <= 8'd0; - case (a7ddrphy_bitslip0_value1) + main_a7ddrphy_bitslip01 <= 8'd0; + case (main_a7ddrphy_bitslip0_value1) 1'd0: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8]; + main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip11 <= 8'd0; - case (a7ddrphy_bitslip1_value1) + main_a7ddrphy_bitslip11 <= 8'd0; + case (main_a7ddrphy_bitslip1_value1) 1'd0: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8]; + main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip02 <= 8'd0; - case (a7ddrphy_bitslip0_value2) + main_a7ddrphy_bitslip02 <= 8'd0; + case (main_a7ddrphy_bitslip0_value2) 1'd0: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[8:1]; end 1'd1: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[9:2]; end 2'd2: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[10:3]; end 2'd3: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[11:4]; end 3'd4: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[12:5]; end 3'd5: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[13:6]; end 3'd6: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[14:7]; end 3'd7: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8]; + main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip04 <= 8'd0; - case (a7ddrphy_bitslip0_value3) + main_a7ddrphy_bitslip04 <= 8'd0; + case (main_a7ddrphy_bitslip0_value3) 1'd0: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[8:1]; end 1'd1: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[9:2]; end 2'd2: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[10:3]; end 2'd3: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[11:4]; end 3'd4: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[12:5]; end 3'd5: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[13:6]; end 3'd6: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[14:7]; end 3'd7: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8]; + main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip12 <= 8'd0; - case (a7ddrphy_bitslip1_value2) + main_a7ddrphy_bitslip12 <= 8'd0; + case (main_a7ddrphy_bitslip1_value2) 1'd0: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[8:1]; end 1'd1: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[9:2]; end 2'd2: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[10:3]; end 2'd3: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[11:4]; end 3'd4: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[12:5]; end 3'd5: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[13:6]; end 3'd6: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[14:7]; end 3'd7: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8]; + main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip14 <= 8'd0; - case (a7ddrphy_bitslip1_value3) + main_a7ddrphy_bitslip14 <= 8'd0; + case (main_a7ddrphy_bitslip1_value3) 1'd0: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[8:1]; end 1'd1: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[9:2]; end 2'd2: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[10:3]; end 2'd3: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[11:4]; end 3'd4: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[12:5]; end 3'd5: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[13:6]; end 3'd6: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[14:7]; end 3'd7: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8]; + main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip20 <= 8'd0; - case (a7ddrphy_bitslip2_value0) + main_a7ddrphy_bitslip20 <= 8'd0; + case (main_a7ddrphy_bitslip2_value0) 1'd0: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8]; + main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip22 <= 8'd0; - case (a7ddrphy_bitslip2_value1) + main_a7ddrphy_bitslip22 <= 8'd0; + case (main_a7ddrphy_bitslip2_value1) 1'd0: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8]; + main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip30 <= 8'd0; - case (a7ddrphy_bitslip3_value0) + main_a7ddrphy_bitslip30 <= 8'd0; + case (main_a7ddrphy_bitslip3_value0) 1'd0: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8]; + main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip32 <= 8'd0; - case (a7ddrphy_bitslip3_value1) + main_a7ddrphy_bitslip32 <= 8'd0; + case (main_a7ddrphy_bitslip3_value1) 1'd0: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8]; + main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip40 <= 8'd0; - case (a7ddrphy_bitslip4_value0) + main_a7ddrphy_bitslip40 <= 8'd0; + case (main_a7ddrphy_bitslip4_value0) 1'd0: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8]; + main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip42 <= 8'd0; - case (a7ddrphy_bitslip4_value1) + main_a7ddrphy_bitslip42 <= 8'd0; + case (main_a7ddrphy_bitslip4_value1) 1'd0: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8]; + main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip50 <= 8'd0; - case (a7ddrphy_bitslip5_value0) + main_a7ddrphy_bitslip50 <= 8'd0; + case (main_a7ddrphy_bitslip5_value0) 1'd0: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8]; + main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip52 <= 8'd0; - case (a7ddrphy_bitslip5_value1) + main_a7ddrphy_bitslip52 <= 8'd0; + case (main_a7ddrphy_bitslip5_value1) 1'd0: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8]; + main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip60 <= 8'd0; - case (a7ddrphy_bitslip6_value0) + main_a7ddrphy_bitslip60 <= 8'd0; + case (main_a7ddrphy_bitslip6_value0) 1'd0: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8]; + main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip62 <= 8'd0; - case (a7ddrphy_bitslip6_value1) + main_a7ddrphy_bitslip62 <= 8'd0; + case (main_a7ddrphy_bitslip6_value1) 1'd0: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8]; + main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip70 <= 8'd0; - case (a7ddrphy_bitslip7_value0) + main_a7ddrphy_bitslip70 <= 8'd0; + case (main_a7ddrphy_bitslip7_value0) 1'd0: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8]; + main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip72 <= 8'd0; - case (a7ddrphy_bitslip7_value1) + main_a7ddrphy_bitslip72 <= 8'd0; + case (main_a7ddrphy_bitslip7_value1) 1'd0: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8]; + main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip80 <= 8'd0; - case (a7ddrphy_bitslip8_value0) + main_a7ddrphy_bitslip80 <= 8'd0; + case (main_a7ddrphy_bitslip8_value0) 1'd0: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8]; + main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip82 <= 8'd0; - case (a7ddrphy_bitslip8_value1) + main_a7ddrphy_bitslip82 <= 8'd0; + case (main_a7ddrphy_bitslip8_value1) 1'd0: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8]; + main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip90 <= 8'd0; - case (a7ddrphy_bitslip9_value0) + main_a7ddrphy_bitslip90 <= 8'd0; + case (main_a7ddrphy_bitslip9_value0) 1'd0: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8]; + main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip92 <= 8'd0; - case (a7ddrphy_bitslip9_value1) + main_a7ddrphy_bitslip92 <= 8'd0; + case (main_a7ddrphy_bitslip9_value1) 1'd0: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8]; + main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip100 <= 8'd0; - case (a7ddrphy_bitslip10_value0) + main_a7ddrphy_bitslip100 <= 8'd0; + case (main_a7ddrphy_bitslip10_value0) 1'd0: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8]; + main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip102 <= 8'd0; - case (a7ddrphy_bitslip10_value1) + main_a7ddrphy_bitslip102 <= 8'd0; + case (main_a7ddrphy_bitslip10_value1) 1'd0: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8]; + main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip110 <= 8'd0; - case (a7ddrphy_bitslip11_value0) + main_a7ddrphy_bitslip110 <= 8'd0; + case (main_a7ddrphy_bitslip11_value0) 1'd0: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8]; + main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip112 <= 8'd0; - case (a7ddrphy_bitslip11_value1) + main_a7ddrphy_bitslip112 <= 8'd0; + case (main_a7ddrphy_bitslip11_value1) 1'd0: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8]; + main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip120 <= 8'd0; - case (a7ddrphy_bitslip12_value0) + main_a7ddrphy_bitslip120 <= 8'd0; + case (main_a7ddrphy_bitslip12_value0) 1'd0: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8]; + main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip122 <= 8'd0; - case (a7ddrphy_bitslip12_value1) + main_a7ddrphy_bitslip122 <= 8'd0; + case (main_a7ddrphy_bitslip12_value1) 1'd0: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8]; + main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip130 <= 8'd0; - case (a7ddrphy_bitslip13_value0) + main_a7ddrphy_bitslip130 <= 8'd0; + case (main_a7ddrphy_bitslip13_value0) 1'd0: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8]; + main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip132 <= 8'd0; - case (a7ddrphy_bitslip13_value1) + main_a7ddrphy_bitslip132 <= 8'd0; + case (main_a7ddrphy_bitslip13_value1) 1'd0: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8]; + main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip140 <= 8'd0; - case (a7ddrphy_bitslip14_value0) + main_a7ddrphy_bitslip140 <= 8'd0; + case (main_a7ddrphy_bitslip14_value0) 1'd0: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8]; + main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip142 <= 8'd0; - case (a7ddrphy_bitslip14_value1) + main_a7ddrphy_bitslip142 <= 8'd0; + case (main_a7ddrphy_bitslip14_value1) 1'd0: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[8:1]; end 1'd1: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[9:2]; end 2'd2: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[10:3]; end 2'd3: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[11:4]; end 3'd4: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[12:5]; end 3'd5: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[13:6]; end 3'd6: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[14:7]; end 3'd7: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8]; + main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip150 <= 8'd0; - case (a7ddrphy_bitslip15_value0) + main_a7ddrphy_bitslip150 <= 8'd0; + case (main_a7ddrphy_bitslip15_value0) 1'd0: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[8:1]; end 1'd1: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[9:2]; end 2'd2: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[10:3]; end 2'd3: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[11:4]; end 3'd4: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[12:5]; end 3'd5: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[13:6]; end 3'd6: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[14:7]; end 3'd7: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8]; + main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[15:8]; end endcase end always @(*) begin - a7ddrphy_bitslip152 <= 8'd0; - case (a7ddrphy_bitslip15_value1) + main_a7ddrphy_bitslip152 <= 8'd0; + case (main_a7ddrphy_bitslip15_value1) 1'd0: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8]; - end - endcase -end -assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address; -assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank; -assign a7ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n; -assign a7ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n; -assign a7ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n; -assign a7ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n; -assign a7ddrphy_dfi_p0_cke = litedramcore_master_p0_cke; -assign a7ddrphy_dfi_p0_odt = litedramcore_master_p0_odt; -assign a7ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n; -assign a7ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n; -assign a7ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata; -assign a7ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en; -assign a7ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask; -assign a7ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en; -assign litedramcore_master_p0_rddata = a7ddrphy_dfi_p0_rddata; -assign litedramcore_master_p0_rddata_valid = a7ddrphy_dfi_p0_rddata_valid; -assign a7ddrphy_dfi_p1_address = litedramcore_master_p1_address; -assign a7ddrphy_dfi_p1_bank = litedramcore_master_p1_bank; -assign a7ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n; -assign a7ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n; -assign a7ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n; -assign a7ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n; -assign a7ddrphy_dfi_p1_cke = litedramcore_master_p1_cke; -assign a7ddrphy_dfi_p1_odt = litedramcore_master_p1_odt; -assign a7ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n; -assign a7ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n; -assign a7ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata; -assign a7ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en; -assign a7ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask; -assign a7ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en; -assign litedramcore_master_p1_rddata = a7ddrphy_dfi_p1_rddata; -assign litedramcore_master_p1_rddata_valid = a7ddrphy_dfi_p1_rddata_valid; -assign a7ddrphy_dfi_p2_address = litedramcore_master_p2_address; -assign a7ddrphy_dfi_p2_bank = litedramcore_master_p2_bank; -assign a7ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n; -assign a7ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n; -assign a7ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n; -assign a7ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n; -assign a7ddrphy_dfi_p2_cke = litedramcore_master_p2_cke; -assign a7ddrphy_dfi_p2_odt = litedramcore_master_p2_odt; -assign a7ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n; -assign a7ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n; -assign a7ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata; -assign a7ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en; -assign a7ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask; -assign a7ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en; -assign litedramcore_master_p2_rddata = a7ddrphy_dfi_p2_rddata; -assign litedramcore_master_p2_rddata_valid = a7ddrphy_dfi_p2_rddata_valid; -assign a7ddrphy_dfi_p3_address = litedramcore_master_p3_address; -assign a7ddrphy_dfi_p3_bank = litedramcore_master_p3_bank; -assign a7ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n; -assign a7ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n; -assign a7ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n; -assign a7ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n; -assign a7ddrphy_dfi_p3_cke = litedramcore_master_p3_cke; -assign a7ddrphy_dfi_p3_odt = litedramcore_master_p3_odt; -assign a7ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n; -assign a7ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n; -assign a7ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata; -assign a7ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en; -assign a7ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask; -assign a7ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en; -assign litedramcore_master_p3_rddata = a7ddrphy_dfi_p3_rddata; -assign litedramcore_master_p3_rddata_valid = a7ddrphy_dfi_p3_rddata_valid; -assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address; -assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank; -assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n; -assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n; -assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n; -assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n; -assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke; -assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt; -assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n; -assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n; -assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata; -assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en; -assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask; -assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en; -assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata; -assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid; -assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address; -assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank; -assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n; -assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n; -assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n; -assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n; -assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke; -assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt; -assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n; -assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n; -assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata; -assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en; -assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask; -assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en; -assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata; -assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid; -assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address; -assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank; -assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n; -assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n; -assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n; -assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n; -assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke; -assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt; -assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n; -assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n; -assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata; -assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en; -assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask; -assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en; -assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata; -assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid; -assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address; -assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank; -assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n; -assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n; -assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n; -assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n; -assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke; -assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt; -assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n; -assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n; -assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata; -assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en; -assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask; -assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en; -assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata; -assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; -always @(*) begin - litedramcore_csr_dfi_p0_rddata <= 32'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata; - end -end -always @(*) begin - litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; - end -end -always @(*) begin - litedramcore_csr_dfi_p1_rddata <= 32'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata; - end -end -always @(*) begin - litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[8:1]; + end + 1'd1: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[9:2]; + end + 2'd2: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[10:3]; + end + 2'd3: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[11:4]; + end + 3'd4: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[12:5]; + end + 3'd5: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[13:6]; + end + 3'd6: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[14:7]; + end + 3'd7: begin + main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[15:8]; + end + endcase +end +assign main_a7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address; +assign main_a7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank; +assign main_a7ddrphy_dfi_p0_cas_n = main_litedramcore_master_p0_cas_n; +assign main_a7ddrphy_dfi_p0_cs_n = main_litedramcore_master_p0_cs_n; +assign main_a7ddrphy_dfi_p0_ras_n = main_litedramcore_master_p0_ras_n; +assign main_a7ddrphy_dfi_p0_we_n = main_litedramcore_master_p0_we_n; +assign main_a7ddrphy_dfi_p0_cke = main_litedramcore_master_p0_cke; +assign main_a7ddrphy_dfi_p0_odt = main_litedramcore_master_p0_odt; +assign main_a7ddrphy_dfi_p0_reset_n = main_litedramcore_master_p0_reset_n; +assign main_a7ddrphy_dfi_p0_act_n = main_litedramcore_master_p0_act_n; +assign main_a7ddrphy_dfi_p0_wrdata = main_litedramcore_master_p0_wrdata; +assign main_a7ddrphy_dfi_p0_wrdata_en = main_litedramcore_master_p0_wrdata_en; +assign main_a7ddrphy_dfi_p0_wrdata_mask = main_litedramcore_master_p0_wrdata_mask; +assign main_a7ddrphy_dfi_p0_rddata_en = main_litedramcore_master_p0_rddata_en; +assign main_litedramcore_master_p0_rddata = main_a7ddrphy_dfi_p0_rddata; +assign main_litedramcore_master_p0_rddata_valid = main_a7ddrphy_dfi_p0_rddata_valid; +assign main_a7ddrphy_dfi_p1_address = main_litedramcore_master_p1_address; +assign main_a7ddrphy_dfi_p1_bank = main_litedramcore_master_p1_bank; +assign main_a7ddrphy_dfi_p1_cas_n = main_litedramcore_master_p1_cas_n; +assign main_a7ddrphy_dfi_p1_cs_n = main_litedramcore_master_p1_cs_n; +assign main_a7ddrphy_dfi_p1_ras_n = main_litedramcore_master_p1_ras_n; +assign main_a7ddrphy_dfi_p1_we_n = main_litedramcore_master_p1_we_n; +assign main_a7ddrphy_dfi_p1_cke = main_litedramcore_master_p1_cke; +assign main_a7ddrphy_dfi_p1_odt = main_litedramcore_master_p1_odt; +assign main_a7ddrphy_dfi_p1_reset_n = main_litedramcore_master_p1_reset_n; +assign main_a7ddrphy_dfi_p1_act_n = main_litedramcore_master_p1_act_n; +assign main_a7ddrphy_dfi_p1_wrdata = main_litedramcore_master_p1_wrdata; +assign main_a7ddrphy_dfi_p1_wrdata_en = main_litedramcore_master_p1_wrdata_en; +assign main_a7ddrphy_dfi_p1_wrdata_mask = main_litedramcore_master_p1_wrdata_mask; +assign main_a7ddrphy_dfi_p1_rddata_en = main_litedramcore_master_p1_rddata_en; +assign main_litedramcore_master_p1_rddata = main_a7ddrphy_dfi_p1_rddata; +assign main_litedramcore_master_p1_rddata_valid = main_a7ddrphy_dfi_p1_rddata_valid; +assign main_a7ddrphy_dfi_p2_address = main_litedramcore_master_p2_address; +assign main_a7ddrphy_dfi_p2_bank = main_litedramcore_master_p2_bank; +assign main_a7ddrphy_dfi_p2_cas_n = main_litedramcore_master_p2_cas_n; +assign main_a7ddrphy_dfi_p2_cs_n = main_litedramcore_master_p2_cs_n; +assign main_a7ddrphy_dfi_p2_ras_n = main_litedramcore_master_p2_ras_n; +assign main_a7ddrphy_dfi_p2_we_n = main_litedramcore_master_p2_we_n; +assign main_a7ddrphy_dfi_p2_cke = main_litedramcore_master_p2_cke; +assign main_a7ddrphy_dfi_p2_odt = main_litedramcore_master_p2_odt; +assign main_a7ddrphy_dfi_p2_reset_n = main_litedramcore_master_p2_reset_n; +assign main_a7ddrphy_dfi_p2_act_n = main_litedramcore_master_p2_act_n; +assign main_a7ddrphy_dfi_p2_wrdata = main_litedramcore_master_p2_wrdata; +assign main_a7ddrphy_dfi_p2_wrdata_en = main_litedramcore_master_p2_wrdata_en; +assign main_a7ddrphy_dfi_p2_wrdata_mask = main_litedramcore_master_p2_wrdata_mask; +assign main_a7ddrphy_dfi_p2_rddata_en = main_litedramcore_master_p2_rddata_en; +assign main_litedramcore_master_p2_rddata = main_a7ddrphy_dfi_p2_rddata; +assign main_litedramcore_master_p2_rddata_valid = main_a7ddrphy_dfi_p2_rddata_valid; +assign main_a7ddrphy_dfi_p3_address = main_litedramcore_master_p3_address; +assign main_a7ddrphy_dfi_p3_bank = main_litedramcore_master_p3_bank; +assign main_a7ddrphy_dfi_p3_cas_n = main_litedramcore_master_p3_cas_n; +assign main_a7ddrphy_dfi_p3_cs_n = main_litedramcore_master_p3_cs_n; +assign main_a7ddrphy_dfi_p3_ras_n = main_litedramcore_master_p3_ras_n; +assign main_a7ddrphy_dfi_p3_we_n = main_litedramcore_master_p3_we_n; +assign main_a7ddrphy_dfi_p3_cke = main_litedramcore_master_p3_cke; +assign main_a7ddrphy_dfi_p3_odt = main_litedramcore_master_p3_odt; +assign main_a7ddrphy_dfi_p3_reset_n = main_litedramcore_master_p3_reset_n; +assign main_a7ddrphy_dfi_p3_act_n = main_litedramcore_master_p3_act_n; +assign main_a7ddrphy_dfi_p3_wrdata = main_litedramcore_master_p3_wrdata; +assign main_a7ddrphy_dfi_p3_wrdata_en = main_litedramcore_master_p3_wrdata_en; +assign main_a7ddrphy_dfi_p3_wrdata_mask = main_litedramcore_master_p3_wrdata_mask; +assign main_a7ddrphy_dfi_p3_rddata_en = main_litedramcore_master_p3_rddata_en; +assign main_litedramcore_master_p3_rddata = main_a7ddrphy_dfi_p3_rddata; +assign main_litedramcore_master_p3_rddata_valid = main_a7ddrphy_dfi_p3_rddata_valid; +assign main_litedramcore_slave_p0_address = main_litedramcore_dfi_p0_address; +assign main_litedramcore_slave_p0_bank = main_litedramcore_dfi_p0_bank; +assign main_litedramcore_slave_p0_cas_n = main_litedramcore_dfi_p0_cas_n; +assign main_litedramcore_slave_p0_cs_n = main_litedramcore_dfi_p0_cs_n; +assign main_litedramcore_slave_p0_ras_n = main_litedramcore_dfi_p0_ras_n; +assign main_litedramcore_slave_p0_we_n = main_litedramcore_dfi_p0_we_n; +assign main_litedramcore_slave_p0_cke = main_litedramcore_dfi_p0_cke; +assign main_litedramcore_slave_p0_odt = main_litedramcore_dfi_p0_odt; +assign main_litedramcore_slave_p0_reset_n = main_litedramcore_dfi_p0_reset_n; +assign main_litedramcore_slave_p0_act_n = main_litedramcore_dfi_p0_act_n; +assign main_litedramcore_slave_p0_wrdata = main_litedramcore_dfi_p0_wrdata; +assign main_litedramcore_slave_p0_wrdata_en = main_litedramcore_dfi_p0_wrdata_en; +assign main_litedramcore_slave_p0_wrdata_mask = main_litedramcore_dfi_p0_wrdata_mask; +assign main_litedramcore_slave_p0_rddata_en = main_litedramcore_dfi_p0_rddata_en; +assign main_litedramcore_dfi_p0_rddata = main_litedramcore_slave_p0_rddata; +assign main_litedramcore_dfi_p0_rddata_valid = main_litedramcore_slave_p0_rddata_valid; +assign main_litedramcore_slave_p1_address = main_litedramcore_dfi_p1_address; +assign main_litedramcore_slave_p1_bank = main_litedramcore_dfi_p1_bank; +assign main_litedramcore_slave_p1_cas_n = main_litedramcore_dfi_p1_cas_n; +assign main_litedramcore_slave_p1_cs_n = main_litedramcore_dfi_p1_cs_n; +assign main_litedramcore_slave_p1_ras_n = main_litedramcore_dfi_p1_ras_n; +assign main_litedramcore_slave_p1_we_n = main_litedramcore_dfi_p1_we_n; +assign main_litedramcore_slave_p1_cke = main_litedramcore_dfi_p1_cke; +assign main_litedramcore_slave_p1_odt = main_litedramcore_dfi_p1_odt; +assign main_litedramcore_slave_p1_reset_n = main_litedramcore_dfi_p1_reset_n; +assign main_litedramcore_slave_p1_act_n = main_litedramcore_dfi_p1_act_n; +assign main_litedramcore_slave_p1_wrdata = main_litedramcore_dfi_p1_wrdata; +assign main_litedramcore_slave_p1_wrdata_en = main_litedramcore_dfi_p1_wrdata_en; +assign main_litedramcore_slave_p1_wrdata_mask = main_litedramcore_dfi_p1_wrdata_mask; +assign main_litedramcore_slave_p1_rddata_en = main_litedramcore_dfi_p1_rddata_en; +assign main_litedramcore_dfi_p1_rddata = main_litedramcore_slave_p1_rddata; +assign main_litedramcore_dfi_p1_rddata_valid = main_litedramcore_slave_p1_rddata_valid; +assign main_litedramcore_slave_p2_address = main_litedramcore_dfi_p2_address; +assign main_litedramcore_slave_p2_bank = main_litedramcore_dfi_p2_bank; +assign main_litedramcore_slave_p2_cas_n = main_litedramcore_dfi_p2_cas_n; +assign main_litedramcore_slave_p2_cs_n = main_litedramcore_dfi_p2_cs_n; +assign main_litedramcore_slave_p2_ras_n = main_litedramcore_dfi_p2_ras_n; +assign main_litedramcore_slave_p2_we_n = main_litedramcore_dfi_p2_we_n; +assign main_litedramcore_slave_p2_cke = main_litedramcore_dfi_p2_cke; +assign main_litedramcore_slave_p2_odt = main_litedramcore_dfi_p2_odt; +assign main_litedramcore_slave_p2_reset_n = main_litedramcore_dfi_p2_reset_n; +assign main_litedramcore_slave_p2_act_n = main_litedramcore_dfi_p2_act_n; +assign main_litedramcore_slave_p2_wrdata = main_litedramcore_dfi_p2_wrdata; +assign main_litedramcore_slave_p2_wrdata_en = main_litedramcore_dfi_p2_wrdata_en; +assign main_litedramcore_slave_p2_wrdata_mask = main_litedramcore_dfi_p2_wrdata_mask; +assign main_litedramcore_slave_p2_rddata_en = main_litedramcore_dfi_p2_rddata_en; +assign main_litedramcore_dfi_p2_rddata = main_litedramcore_slave_p2_rddata; +assign main_litedramcore_dfi_p2_rddata_valid = main_litedramcore_slave_p2_rddata_valid; +assign main_litedramcore_slave_p3_address = main_litedramcore_dfi_p3_address; +assign main_litedramcore_slave_p3_bank = main_litedramcore_dfi_p3_bank; +assign main_litedramcore_slave_p3_cas_n = main_litedramcore_dfi_p3_cas_n; +assign main_litedramcore_slave_p3_cs_n = main_litedramcore_dfi_p3_cs_n; +assign main_litedramcore_slave_p3_ras_n = main_litedramcore_dfi_p3_ras_n; +assign main_litedramcore_slave_p3_we_n = main_litedramcore_dfi_p3_we_n; +assign main_litedramcore_slave_p3_cke = main_litedramcore_dfi_p3_cke; +assign main_litedramcore_slave_p3_odt = main_litedramcore_dfi_p3_odt; +assign main_litedramcore_slave_p3_reset_n = main_litedramcore_dfi_p3_reset_n; +assign main_litedramcore_slave_p3_act_n = main_litedramcore_dfi_p3_act_n; +assign main_litedramcore_slave_p3_wrdata = main_litedramcore_dfi_p3_wrdata; +assign main_litedramcore_slave_p3_wrdata_en = main_litedramcore_dfi_p3_wrdata_en; +assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_mask; +assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en; +assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata; +assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid; +always @(*) begin + main_litedramcore_csr_dfi_p0_rddata <= 32'd0; + if (main_litedramcore_sel) begin + end else begin + main_litedramcore_csr_dfi_p0_rddata <= main_litedramcore_master_p0_rddata; end end always @(*) begin - litedramcore_csr_dfi_p2_rddata <= 32'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata; + main_litedramcore_csr_dfi_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end end always @(*) begin - litedramcore_csr_dfi_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p1_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + main_litedramcore_csr_dfi_p1_rddata <= main_litedramcore_master_p1_rddata; end end always @(*) begin - litedramcore_csr_dfi_p3_rddata <= 32'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata; + main_litedramcore_csr_dfi_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end end always @(*) begin - litedramcore_csr_dfi_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin + main_litedramcore_csr_dfi_p2_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin - litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + main_litedramcore_csr_dfi_p2_rddata <= main_litedramcore_master_p2_rddata; end end always @(*) begin - litedramcore_ext_dfi_p0_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata; - end else begin - end + main_litedramcore_csr_dfi_p2_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + end else begin + main_litedramcore_csr_dfi_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; + end +end +always @(*) begin + main_litedramcore_csr_dfi_p3_rddata <= 32'd0; + if (main_litedramcore_sel) begin end else begin + main_litedramcore_csr_dfi_p3_rddata <= main_litedramcore_master_p3_rddata; end end always @(*) begin - litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + main_litedramcore_csr_dfi_p3_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + end else begin + main_litedramcore_csr_dfi_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; + end +end +always @(*) begin + main_litedramcore_ext_dfi_p0_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p0_rddata <= main_litedramcore_master_p0_rddata; end else begin end end else begin end end always @(*) begin - litedramcore_ext_dfi_p1_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata; + main_litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end else begin end end else begin end end always @(*) begin - litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + main_litedramcore_ext_dfi_p1_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p1_rddata <= main_litedramcore_master_p1_rddata; end else begin end end else begin end end always @(*) begin - litedramcore_ext_dfi_p2_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata; + main_litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end else begin end end else begin end end always @(*) begin - litedramcore_ext_dfi_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + main_litedramcore_ext_dfi_p2_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p2_rddata <= main_litedramcore_master_p2_rddata; end else begin end end else begin end end always @(*) begin - litedramcore_slave_p0_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p2_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end else begin - litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; end end else begin end end always @(*) begin - litedramcore_slave_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p0_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata; end end else begin end end always @(*) begin - litedramcore_ext_dfi_p3_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata; + main_litedramcore_slave_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin + main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end end else begin end end always @(*) begin - litedramcore_ext_dfi_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + main_litedramcore_ext_dfi_p3_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p3_rddata <= main_litedramcore_master_p3_rddata; end else begin end end else begin end end always @(*) begin - litedramcore_slave_p1_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p3_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_ext_dfi_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end else begin - litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; end end else begin end end always @(*) begin - litedramcore_slave_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p1_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata; end end else begin end end always @(*) begin - litedramcore_slave_p2_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p1_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; + main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end end else begin end end always @(*) begin - litedramcore_slave_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p2_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata; end end else begin end end always @(*) begin - litedramcore_slave_p3_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p2_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; + main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end end else begin end end always @(*) begin - litedramcore_slave_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin + main_litedramcore_slave_p3_rddata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata; end end else begin end end always @(*) begin - litedramcore_master_p0_address <= 14'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address; + main_litedramcore_slave_p3_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin end else begin - litedramcore_master_p0_address <= litedramcore_slave_p0_address; + main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end end else begin - litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address; end end always @(*) begin - litedramcore_master_p0_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank; + main_litedramcore_master_p0_address <= 14'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_address <= main_litedramcore_ext_dfi_p0_address; end else begin - litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; + main_litedramcore_master_p0_address <= main_litedramcore_slave_p0_address; end end else begin - litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank; + main_litedramcore_master_p0_address <= main_litedramcore_csr_dfi_p0_address; end end always @(*) begin - litedramcore_master_p0_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n; + main_litedramcore_master_p0_bank <= 3'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_bank <= main_litedramcore_ext_dfi_p0_bank; end else begin - litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; + main_litedramcore_master_p0_bank <= main_litedramcore_slave_p0_bank; end end else begin - litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n; + main_litedramcore_master_p0_bank <= main_litedramcore_csr_dfi_p0_bank; end end always @(*) begin - litedramcore_master_p0_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n; + main_litedramcore_master_p0_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_cas_n <= main_litedramcore_ext_dfi_p0_cas_n; end else begin - litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; + main_litedramcore_master_p0_cas_n <= main_litedramcore_slave_p0_cas_n; end end else begin - litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n; + main_litedramcore_master_p0_cas_n <= main_litedramcore_csr_dfi_p0_cas_n; end end always @(*) begin - litedramcore_master_p0_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n; + main_litedramcore_master_p0_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_cs_n <= main_litedramcore_ext_dfi_p0_cs_n; end else begin - litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; + main_litedramcore_master_p0_cs_n <= main_litedramcore_slave_p0_cs_n; + if (1'd0) begin + main_litedramcore_master_p0_cs_n <= {2{main_litedramcore_slave_p0_cs_n}}; + end end end else begin - litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n; + main_litedramcore_master_p0_cs_n <= main_litedramcore_csr_dfi_p0_cs_n; end end always @(*) begin - litedramcore_master_p0_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n; + main_litedramcore_master_p0_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_ras_n <= main_litedramcore_ext_dfi_p0_ras_n; end else begin - litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + main_litedramcore_master_p0_ras_n <= main_litedramcore_slave_p0_ras_n; end end else begin - litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n; + main_litedramcore_master_p0_ras_n <= main_litedramcore_csr_dfi_p0_ras_n; end end always @(*) begin - litedramcore_master_p0_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke; + main_litedramcore_master_p0_we_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_we_n <= main_litedramcore_ext_dfi_p0_we_n; end else begin - litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; + main_litedramcore_master_p0_we_n <= main_litedramcore_slave_p0_we_n; end end else begin - litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke; + main_litedramcore_master_p0_we_n <= main_litedramcore_csr_dfi_p0_we_n; end end always @(*) begin - litedramcore_master_p0_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt; + main_litedramcore_master_p0_cke <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_cke <= main_litedramcore_ext_dfi_p0_cke; end else begin - litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; + main_litedramcore_master_p0_cke <= main_litedramcore_slave_p0_cke; end end else begin - litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt; + main_litedramcore_master_p0_cke <= main_litedramcore_csr_dfi_p0_cke; end end always @(*) begin - litedramcore_master_p0_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n; + main_litedramcore_master_p0_odt <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_odt <= main_litedramcore_ext_dfi_p0_odt; end else begin - litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; + main_litedramcore_master_p0_odt <= main_litedramcore_slave_p0_odt; end end else begin - litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n; + main_litedramcore_master_p0_odt <= main_litedramcore_csr_dfi_p0_odt; end end always @(*) begin - litedramcore_master_p0_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n; + main_litedramcore_master_p0_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_reset_n <= main_litedramcore_ext_dfi_p0_reset_n; end else begin - litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; + main_litedramcore_master_p0_reset_n <= main_litedramcore_slave_p0_reset_n; end end else begin - litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n; + main_litedramcore_master_p0_reset_n <= main_litedramcore_csr_dfi_p0_reset_n; end end always @(*) begin - litedramcore_master_p0_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata; + main_litedramcore_master_p0_act_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_act_n <= main_litedramcore_ext_dfi_p0_act_n; end else begin - litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; + main_litedramcore_master_p0_act_n <= main_litedramcore_slave_p0_act_n; end end else begin - litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata; + main_litedramcore_master_p0_act_n <= main_litedramcore_csr_dfi_p0_act_n; end end always @(*) begin - litedramcore_master_p0_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en; + main_litedramcore_master_p0_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_wrdata <= main_litedramcore_ext_dfi_p0_wrdata; end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; + main_litedramcore_master_p0_wrdata <= main_litedramcore_slave_p0_wrdata; end end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en; + main_litedramcore_master_p0_wrdata <= main_litedramcore_csr_dfi_p0_wrdata; end end always @(*) begin - litedramcore_master_p0_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask; + main_litedramcore_master_p0_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_wrdata_en <= main_litedramcore_ext_dfi_p0_wrdata_en; end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; + main_litedramcore_master_p0_wrdata_en <= main_litedramcore_slave_p0_wrdata_en; end end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask; + main_litedramcore_master_p0_wrdata_en <= main_litedramcore_csr_dfi_p0_wrdata_en; end end always @(*) begin - litedramcore_master_p0_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en; + main_litedramcore_master_p0_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_ext_dfi_p0_wrdata_mask; end else begin - litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_slave_p0_wrdata_mask; end end else begin - litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en; + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_csr_dfi_p0_wrdata_mask; end end always @(*) begin - litedramcore_master_p1_address <= 14'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address; + main_litedramcore_master_p0_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p0_rddata_en <= main_litedramcore_ext_dfi_p0_rddata_en; end else begin - litedramcore_master_p1_address <= litedramcore_slave_p1_address; + main_litedramcore_master_p0_rddata_en <= main_litedramcore_slave_p0_rddata_en; end end else begin - litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address; + main_litedramcore_master_p0_rddata_en <= main_litedramcore_csr_dfi_p0_rddata_en; end end always @(*) begin - litedramcore_master_p1_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank; + main_litedramcore_master_p1_address <= 14'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_address <= main_litedramcore_ext_dfi_p1_address; end else begin - litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; + main_litedramcore_master_p1_address <= main_litedramcore_slave_p1_address; end end else begin - litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank; + main_litedramcore_master_p1_address <= main_litedramcore_csr_dfi_p1_address; end end always @(*) begin - litedramcore_master_p1_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n; + main_litedramcore_master_p1_bank <= 3'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_bank <= main_litedramcore_ext_dfi_p1_bank; end else begin - litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; + main_litedramcore_master_p1_bank <= main_litedramcore_slave_p1_bank; end end else begin - litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n; + main_litedramcore_master_p1_bank <= main_litedramcore_csr_dfi_p1_bank; end end always @(*) begin - litedramcore_master_p1_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n; + main_litedramcore_master_p1_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_cas_n <= main_litedramcore_ext_dfi_p1_cas_n; end else begin - litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; + main_litedramcore_master_p1_cas_n <= main_litedramcore_slave_p1_cas_n; end end else begin - litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n; + main_litedramcore_master_p1_cas_n <= main_litedramcore_csr_dfi_p1_cas_n; end end always @(*) begin - litedramcore_master_p1_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n; + main_litedramcore_master_p1_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_cs_n <= main_litedramcore_ext_dfi_p1_cs_n; end else begin - litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; + main_litedramcore_master_p1_cs_n <= main_litedramcore_slave_p1_cs_n; + if (1'd0) begin + main_litedramcore_master_p1_cs_n <= {2{main_litedramcore_slave_p1_cs_n}}; + end end end else begin - litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n; + main_litedramcore_master_p1_cs_n <= main_litedramcore_csr_dfi_p1_cs_n; end end always @(*) begin - litedramcore_master_p1_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n; + main_litedramcore_master_p1_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_ras_n <= main_litedramcore_ext_dfi_p1_ras_n; end else begin - litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; + main_litedramcore_master_p1_ras_n <= main_litedramcore_slave_p1_ras_n; end end else begin - litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n; + main_litedramcore_master_p1_ras_n <= main_litedramcore_csr_dfi_p1_ras_n; end end always @(*) begin - litedramcore_master_p1_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke; + main_litedramcore_master_p1_we_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_we_n <= main_litedramcore_ext_dfi_p1_we_n; end else begin - litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; + main_litedramcore_master_p1_we_n <= main_litedramcore_slave_p1_we_n; end end else begin - litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke; + main_litedramcore_master_p1_we_n <= main_litedramcore_csr_dfi_p1_we_n; end end always @(*) begin - litedramcore_master_p1_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt; + main_litedramcore_master_p1_cke <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_cke <= main_litedramcore_ext_dfi_p1_cke; end else begin - litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; + main_litedramcore_master_p1_cke <= main_litedramcore_slave_p1_cke; end end else begin - litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt; + main_litedramcore_master_p1_cke <= main_litedramcore_csr_dfi_p1_cke; end end always @(*) begin - litedramcore_master_p1_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n; + main_litedramcore_master_p1_odt <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_odt <= main_litedramcore_ext_dfi_p1_odt; end else begin - litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; + main_litedramcore_master_p1_odt <= main_litedramcore_slave_p1_odt; end end else begin - litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n; + main_litedramcore_master_p1_odt <= main_litedramcore_csr_dfi_p1_odt; end end always @(*) begin - litedramcore_master_p1_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n; + main_litedramcore_master_p1_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_reset_n <= main_litedramcore_ext_dfi_p1_reset_n; end else begin - litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; + main_litedramcore_master_p1_reset_n <= main_litedramcore_slave_p1_reset_n; end end else begin - litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n; + main_litedramcore_master_p1_reset_n <= main_litedramcore_csr_dfi_p1_reset_n; end end always @(*) begin - litedramcore_master_p1_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata; + main_litedramcore_master_p1_act_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_act_n <= main_litedramcore_ext_dfi_p1_act_n; end else begin - litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; + main_litedramcore_master_p1_act_n <= main_litedramcore_slave_p1_act_n; end end else begin - litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata; + main_litedramcore_master_p1_act_n <= main_litedramcore_csr_dfi_p1_act_n; end end always @(*) begin - litedramcore_master_p1_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en; + main_litedramcore_master_p1_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_wrdata <= main_litedramcore_ext_dfi_p1_wrdata; end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; + main_litedramcore_master_p1_wrdata <= main_litedramcore_slave_p1_wrdata; end end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en; + main_litedramcore_master_p1_wrdata <= main_litedramcore_csr_dfi_p1_wrdata; end end always @(*) begin - litedramcore_master_p1_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask; + main_litedramcore_master_p1_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_wrdata_en <= main_litedramcore_ext_dfi_p1_wrdata_en; end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; + main_litedramcore_master_p1_wrdata_en <= main_litedramcore_slave_p1_wrdata_en; end end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask; + main_litedramcore_master_p1_wrdata_en <= main_litedramcore_csr_dfi_p1_wrdata_en; end end always @(*) begin - litedramcore_master_p1_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en; + main_litedramcore_master_p1_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_ext_dfi_p1_wrdata_mask; end else begin - litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; + main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_slave_p1_wrdata_mask; end end else begin - litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en; + main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_csr_dfi_p1_wrdata_mask; end end always @(*) begin - litedramcore_master_p2_address <= 14'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address; + main_litedramcore_master_p1_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p1_rddata_en <= main_litedramcore_ext_dfi_p1_rddata_en; end else begin - litedramcore_master_p2_address <= litedramcore_slave_p2_address; + main_litedramcore_master_p1_rddata_en <= main_litedramcore_slave_p1_rddata_en; end end else begin - litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address; + main_litedramcore_master_p1_rddata_en <= main_litedramcore_csr_dfi_p1_rddata_en; end end always @(*) begin - litedramcore_master_p2_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank; + main_litedramcore_master_p2_address <= 14'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_address <= main_litedramcore_ext_dfi_p2_address; end else begin - litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; + main_litedramcore_master_p2_address <= main_litedramcore_slave_p2_address; end end else begin - litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank; + main_litedramcore_master_p2_address <= main_litedramcore_csr_dfi_p2_address; end end always @(*) begin - litedramcore_master_p2_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n; + main_litedramcore_master_p2_bank <= 3'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_bank <= main_litedramcore_ext_dfi_p2_bank; end else begin - litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; + main_litedramcore_master_p2_bank <= main_litedramcore_slave_p2_bank; end end else begin - litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n; + main_litedramcore_master_p2_bank <= main_litedramcore_csr_dfi_p2_bank; end end always @(*) begin - litedramcore_master_p2_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n; + main_litedramcore_master_p2_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_cas_n <= main_litedramcore_ext_dfi_p2_cas_n; end else begin - litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; + main_litedramcore_master_p2_cas_n <= main_litedramcore_slave_p2_cas_n; end end else begin - litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n; + main_litedramcore_master_p2_cas_n <= main_litedramcore_csr_dfi_p2_cas_n; end end always @(*) begin - litedramcore_master_p2_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n; + main_litedramcore_master_p2_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_cs_n <= main_litedramcore_ext_dfi_p2_cs_n; end else begin - litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; + main_litedramcore_master_p2_cs_n <= main_litedramcore_slave_p2_cs_n; + if (1'd0) begin + main_litedramcore_master_p2_cs_n <= {2{main_litedramcore_slave_p2_cs_n}}; + end end end else begin - litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n; + main_litedramcore_master_p2_cs_n <= main_litedramcore_csr_dfi_p2_cs_n; end end always @(*) begin - litedramcore_master_p2_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n; + main_litedramcore_master_p2_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_ras_n <= main_litedramcore_ext_dfi_p2_ras_n; end else begin - litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; + main_litedramcore_master_p2_ras_n <= main_litedramcore_slave_p2_ras_n; end end else begin - litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n; + main_litedramcore_master_p2_ras_n <= main_litedramcore_csr_dfi_p2_ras_n; end end always @(*) begin - litedramcore_master_p2_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke; + main_litedramcore_master_p2_we_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_we_n <= main_litedramcore_ext_dfi_p2_we_n; end else begin - litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; + main_litedramcore_master_p2_we_n <= main_litedramcore_slave_p2_we_n; end end else begin - litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke; + main_litedramcore_master_p2_we_n <= main_litedramcore_csr_dfi_p2_we_n; end end always @(*) begin - litedramcore_master_p2_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt; + main_litedramcore_master_p2_cke <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_cke <= main_litedramcore_ext_dfi_p2_cke; end else begin - litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; + main_litedramcore_master_p2_cke <= main_litedramcore_slave_p2_cke; end end else begin - litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt; + main_litedramcore_master_p2_cke <= main_litedramcore_csr_dfi_p2_cke; end end always @(*) begin - litedramcore_master_p2_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n; + main_litedramcore_master_p2_odt <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_odt <= main_litedramcore_ext_dfi_p2_odt; end else begin - litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; + main_litedramcore_master_p2_odt <= main_litedramcore_slave_p2_odt; end end else begin - litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n; + main_litedramcore_master_p2_odt <= main_litedramcore_csr_dfi_p2_odt; end end always @(*) begin - litedramcore_master_p2_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n; + main_litedramcore_master_p2_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_reset_n <= main_litedramcore_ext_dfi_p2_reset_n; end else begin - litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; + main_litedramcore_master_p2_reset_n <= main_litedramcore_slave_p2_reset_n; end end else begin - litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n; + main_litedramcore_master_p2_reset_n <= main_litedramcore_csr_dfi_p2_reset_n; end end always @(*) begin - litedramcore_master_p2_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata; + main_litedramcore_master_p2_act_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_act_n <= main_litedramcore_ext_dfi_p2_act_n; end else begin - litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; + main_litedramcore_master_p2_act_n <= main_litedramcore_slave_p2_act_n; end end else begin - litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata; + main_litedramcore_master_p2_act_n <= main_litedramcore_csr_dfi_p2_act_n; end end always @(*) begin - litedramcore_master_p2_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en; + main_litedramcore_master_p2_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_wrdata <= main_litedramcore_ext_dfi_p2_wrdata; end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; + main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata; end end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en; + main_litedramcore_master_p2_wrdata <= main_litedramcore_csr_dfi_p2_wrdata; end end always @(*) begin - litedramcore_master_p2_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask; + main_litedramcore_master_p2_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_wrdata_en <= main_litedramcore_ext_dfi_p2_wrdata_en; end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; + main_litedramcore_master_p2_wrdata_en <= main_litedramcore_slave_p2_wrdata_en; end end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask; + main_litedramcore_master_p2_wrdata_en <= main_litedramcore_csr_dfi_p2_wrdata_en; end end always @(*) begin - litedramcore_master_p2_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en; + main_litedramcore_master_p2_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_ext_dfi_p2_wrdata_mask; end else begin - litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; + main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_slave_p2_wrdata_mask; end end else begin - litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en; + main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_csr_dfi_p2_wrdata_mask; end end always @(*) begin - litedramcore_master_p3_address <= 14'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address; + main_litedramcore_master_p2_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p2_rddata_en <= main_litedramcore_ext_dfi_p2_rddata_en; end else begin - litedramcore_master_p3_address <= litedramcore_slave_p3_address; + main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en; end end else begin - litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address; + main_litedramcore_master_p2_rddata_en <= main_litedramcore_csr_dfi_p2_rddata_en; end end always @(*) begin - litedramcore_master_p3_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank; + main_litedramcore_master_p3_address <= 14'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_address <= main_litedramcore_ext_dfi_p3_address; end else begin - litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; + main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address; end end else begin - litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank; + main_litedramcore_master_p3_address <= main_litedramcore_csr_dfi_p3_address; end end always @(*) begin - litedramcore_master_p3_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n; + main_litedramcore_master_p3_bank <= 3'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_bank <= main_litedramcore_ext_dfi_p3_bank; end else begin - litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; + main_litedramcore_master_p3_bank <= main_litedramcore_slave_p3_bank; end end else begin - litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n; + main_litedramcore_master_p3_bank <= main_litedramcore_csr_dfi_p3_bank; end end always @(*) begin - litedramcore_master_p3_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n; + main_litedramcore_master_p3_cas_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_cas_n <= main_litedramcore_ext_dfi_p3_cas_n; end else begin - litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; + main_litedramcore_master_p3_cas_n <= main_litedramcore_slave_p3_cas_n; end end else begin - litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n; + main_litedramcore_master_p3_cas_n <= main_litedramcore_csr_dfi_p3_cas_n; end end always @(*) begin - litedramcore_master_p3_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n; + main_litedramcore_master_p3_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_cs_n <= main_litedramcore_ext_dfi_p3_cs_n; end else begin - litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; + main_litedramcore_master_p3_cs_n <= main_litedramcore_slave_p3_cs_n; + if (1'd0) begin + main_litedramcore_master_p3_cs_n <= {2{main_litedramcore_slave_p3_cs_n}}; + end end end else begin - litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n; + main_litedramcore_master_p3_cs_n <= main_litedramcore_csr_dfi_p3_cs_n; end end always @(*) begin - litedramcore_master_p3_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n; + main_litedramcore_master_p3_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_ras_n <= main_litedramcore_ext_dfi_p3_ras_n; end else begin - litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; + main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n; end end else begin - litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n; + main_litedramcore_master_p3_ras_n <= main_litedramcore_csr_dfi_p3_ras_n; end end always @(*) begin - litedramcore_master_p3_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke; + main_litedramcore_master_p3_we_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_we_n <= main_litedramcore_ext_dfi_p3_we_n; end else begin - litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; + main_litedramcore_master_p3_we_n <= main_litedramcore_slave_p3_we_n; end end else begin - litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke; + main_litedramcore_master_p3_we_n <= main_litedramcore_csr_dfi_p3_we_n; end end always @(*) begin - litedramcore_master_p3_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt; + main_litedramcore_master_p3_cke <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_cke <= main_litedramcore_ext_dfi_p3_cke; end else begin - litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; + main_litedramcore_master_p3_cke <= main_litedramcore_slave_p3_cke; end end else begin - litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt; + main_litedramcore_master_p3_cke <= main_litedramcore_csr_dfi_p3_cke; end end always @(*) begin - litedramcore_master_p3_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n; + main_litedramcore_master_p3_odt <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_odt <= main_litedramcore_ext_dfi_p3_odt; end else begin - litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; + main_litedramcore_master_p3_odt <= main_litedramcore_slave_p3_odt; end end else begin - litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n; + main_litedramcore_master_p3_odt <= main_litedramcore_csr_dfi_p3_odt; end end always @(*) begin - litedramcore_master_p3_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n; + main_litedramcore_master_p3_reset_n <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_reset_n <= main_litedramcore_ext_dfi_p3_reset_n; end else begin - litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; + main_litedramcore_master_p3_reset_n <= main_litedramcore_slave_p3_reset_n; end end else begin - litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n; + main_litedramcore_master_p3_reset_n <= main_litedramcore_csr_dfi_p3_reset_n; end end always @(*) begin - litedramcore_master_p3_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata; + main_litedramcore_master_p3_act_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_act_n <= main_litedramcore_ext_dfi_p3_act_n; end else begin - litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; + main_litedramcore_master_p3_act_n <= main_litedramcore_slave_p3_act_n; end end else begin - litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata; + main_litedramcore_master_p3_act_n <= main_litedramcore_csr_dfi_p3_act_n; end end always @(*) begin - litedramcore_master_p3_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en; + main_litedramcore_master_p3_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_wrdata <= main_litedramcore_ext_dfi_p3_wrdata; end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; + main_litedramcore_master_p3_wrdata <= main_litedramcore_slave_p3_wrdata; end end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en; + main_litedramcore_master_p3_wrdata <= main_litedramcore_csr_dfi_p3_wrdata; end end always @(*) begin - litedramcore_master_p3_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask; + main_litedramcore_master_p3_wrdata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_wrdata_en <= main_litedramcore_ext_dfi_p3_wrdata_en; end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; + main_litedramcore_master_p3_wrdata_en <= main_litedramcore_slave_p3_wrdata_en; end end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask; + main_litedramcore_master_p3_wrdata_en <= main_litedramcore_csr_dfi_p3_wrdata_en; end end always @(*) begin - litedramcore_master_p3_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en; + main_litedramcore_master_p3_wrdata_mask <= 4'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_ext_dfi_p3_wrdata_mask; end else begin - litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; + main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_slave_p3_wrdata_mask; end end else begin - litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en; + main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_csr_dfi_p3_wrdata_mask; end end -assign litedramcore_csr_dfi_p0_cke = litedramcore_cke; -assign litedramcore_csr_dfi_p1_cke = litedramcore_cke; -assign litedramcore_csr_dfi_p2_cke = litedramcore_cke; -assign litedramcore_csr_dfi_p3_cke = litedramcore_cke; -assign litedramcore_csr_dfi_p0_odt = litedramcore_odt; -assign litedramcore_csr_dfi_p1_odt = litedramcore_odt; -assign litedramcore_csr_dfi_p2_odt = litedramcore_odt; -assign litedramcore_csr_dfi_p3_odt = litedramcore_odt; -assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n; -assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n; -assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n; -assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n; always @(*) begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we); + main_litedramcore_master_p3_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_rddata_en <= main_litedramcore_ext_dfi_p3_rddata_en; + end else begin + main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en; + end end else begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; + main_litedramcore_master_p3_rddata_en <= main_litedramcore_csr_dfi_p3_rddata_en; end end always @(*) begin - litedramcore_csr_dfi_p0_cas_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas); + main_litedramcore_csr_dfi_p0_cke <= 1'd0; + main_litedramcore_csr_dfi_p0_cke <= main_litedramcore_cke; +end +always @(*) begin + main_litedramcore_csr_dfi_p1_cke <= 1'd0; + main_litedramcore_csr_dfi_p1_cke <= main_litedramcore_cke; +end +always @(*) begin + main_litedramcore_csr_dfi_p2_cke <= 1'd0; + main_litedramcore_csr_dfi_p2_cke <= main_litedramcore_cke; +end +always @(*) begin + main_litedramcore_csr_dfi_p3_cke <= 1'd0; + main_litedramcore_csr_dfi_p3_cke <= main_litedramcore_cke; +end +always @(*) begin + main_litedramcore_csr_dfi_p0_odt <= 1'd0; + main_litedramcore_csr_dfi_p0_odt <= main_litedramcore_odt; +end +always @(*) begin + main_litedramcore_csr_dfi_p1_odt <= 1'd0; + main_litedramcore_csr_dfi_p1_odt <= main_litedramcore_odt; +end +always @(*) begin + main_litedramcore_csr_dfi_p2_odt <= 1'd0; + main_litedramcore_csr_dfi_p2_odt <= main_litedramcore_odt; +end +always @(*) begin + main_litedramcore_csr_dfi_p3_odt <= 1'd0; + main_litedramcore_csr_dfi_p3_odt <= main_litedramcore_odt; +end +assign main_litedramcore_csr_dfi_p0_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_csr_dfi_p1_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_csr_dfi_p2_reset_n = main_litedramcore_reset_n; +assign main_litedramcore_csr_dfi_p3_reset_n = main_litedramcore_reset_n; +always @(*) begin + main_litedramcore_csr_dfi_p0_we_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_csr_dfi_p0_we_n <= (~main_litedramcore_phaseinjector0_csrfield_we); end else begin - litedramcore_csr_dfi_p0_cas_n <= 1'd1; + main_litedramcore_csr_dfi_p0_we_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p0_cs_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}}; + main_litedramcore_csr_dfi_p0_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_csr_dfi_p0_cas_n <= (~main_litedramcore_phaseinjector0_csrfield_cas); end else begin - litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; + main_litedramcore_csr_dfi_p0_cas_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p0_ras_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras); + main_litedramcore_csr_dfi_p0_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + if (main_litedramcore_phaseinjector0_csrfield_cs_top) begin + main_litedramcore_csr_dfi_p0_cs_n <= 2'd2; + end else begin + if (main_litedramcore_phaseinjector0_csrfield_cs_bottom) begin + main_litedramcore_csr_dfi_p0_cs_n <= 1'd1; + end else begin + main_litedramcore_csr_dfi_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_csrfield_cs)}}; + end + end end else begin - litedramcore_csr_dfi_p0_ras_n <= 1'd1; + main_litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; end end -assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage; -assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage; -assign litedramcore_csr_dfi_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_wren); -assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_rden); -assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; -assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we); + main_litedramcore_csr_dfi_p0_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_csr_dfi_p0_ras_n <= (~main_litedramcore_phaseinjector0_csrfield_ras); end else begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; + main_litedramcore_csr_dfi_p0_ras_n <= 1'd1; end end +assign main_litedramcore_csr_dfi_p0_address = main_litedramcore_phaseinjector0_address_storage; +assign main_litedramcore_csr_dfi_p0_bank = main_litedramcore_phaseinjector0_baddress_storage; +assign main_litedramcore_csr_dfi_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_wren); +assign main_litedramcore_csr_dfi_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_rden); +assign main_litedramcore_csr_dfi_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage; +assign main_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p1_cas_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas); + main_litedramcore_csr_dfi_p1_we_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_csr_dfi_p1_we_n <= (~main_litedramcore_phaseinjector1_csrfield_we); end else begin - litedramcore_csr_dfi_p1_cas_n <= 1'd1; + main_litedramcore_csr_dfi_p1_we_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p1_cs_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}}; + main_litedramcore_csr_dfi_p1_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_csr_dfi_p1_cas_n <= (~main_litedramcore_phaseinjector1_csrfield_cas); end else begin - litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; + main_litedramcore_csr_dfi_p1_cas_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p1_ras_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras); + main_litedramcore_csr_dfi_p1_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + if (main_litedramcore_phaseinjector1_csrfield_cs_top) begin + main_litedramcore_csr_dfi_p1_cs_n <= 2'd2; + end else begin + if (main_litedramcore_phaseinjector1_csrfield_cs_bottom) begin + main_litedramcore_csr_dfi_p1_cs_n <= 1'd1; + end else begin + main_litedramcore_csr_dfi_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_csrfield_cs)}}; + end + end end else begin - litedramcore_csr_dfi_p1_ras_n <= 1'd1; + main_litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; end end -assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage; -assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage; -assign litedramcore_csr_dfi_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_wren); -assign litedramcore_csr_dfi_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_rden); -assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; -assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p2_we_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we); + main_litedramcore_csr_dfi_p1_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_csr_dfi_p1_ras_n <= (~main_litedramcore_phaseinjector1_csrfield_ras); end else begin - litedramcore_csr_dfi_p2_we_n <= 1'd1; + main_litedramcore_csr_dfi_p1_ras_n <= 1'd1; end end +assign main_litedramcore_csr_dfi_p1_address = main_litedramcore_phaseinjector1_address_storage; +assign main_litedramcore_csr_dfi_p1_bank = main_litedramcore_phaseinjector1_baddress_storage; +assign main_litedramcore_csr_dfi_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_wren); +assign main_litedramcore_csr_dfi_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_rden); +assign main_litedramcore_csr_dfi_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage; +assign main_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p2_cas_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas); + main_litedramcore_csr_dfi_p2_we_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_csr_dfi_p2_we_n <= (~main_litedramcore_phaseinjector2_csrfield_we); end else begin - litedramcore_csr_dfi_p2_cas_n <= 1'd1; + main_litedramcore_csr_dfi_p2_we_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p2_cs_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}}; + main_litedramcore_csr_dfi_p2_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_csr_dfi_p2_cas_n <= (~main_litedramcore_phaseinjector2_csrfield_cas); end else begin - litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; + main_litedramcore_csr_dfi_p2_cas_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p2_ras_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras); + main_litedramcore_csr_dfi_p2_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + if (main_litedramcore_phaseinjector2_csrfield_cs_top) begin + main_litedramcore_csr_dfi_p2_cs_n <= 2'd2; + end else begin + if (main_litedramcore_phaseinjector2_csrfield_cs_bottom) begin + main_litedramcore_csr_dfi_p2_cs_n <= 1'd1; + end else begin + main_litedramcore_csr_dfi_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_csrfield_cs)}}; + end + end end else begin - litedramcore_csr_dfi_p2_ras_n <= 1'd1; + main_litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; end end -assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage; -assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage; -assign litedramcore_csr_dfi_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_wren); -assign litedramcore_csr_dfi_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_rden); -assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage; -assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p3_we_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we); + main_litedramcore_csr_dfi_p2_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_csr_dfi_p2_ras_n <= (~main_litedramcore_phaseinjector2_csrfield_ras); end else begin - litedramcore_csr_dfi_p3_we_n <= 1'd1; + main_litedramcore_csr_dfi_p2_ras_n <= 1'd1; end end +assign main_litedramcore_csr_dfi_p2_address = main_litedramcore_phaseinjector2_address_storage; +assign main_litedramcore_csr_dfi_p2_bank = main_litedramcore_phaseinjector2_baddress_storage; +assign main_litedramcore_csr_dfi_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_wren); +assign main_litedramcore_csr_dfi_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_rden); +assign main_litedramcore_csr_dfi_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage; +assign main_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p3_cas_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas); + main_litedramcore_csr_dfi_p3_we_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_csr_dfi_p3_we_n <= (~main_litedramcore_phaseinjector3_csrfield_we); end else begin - litedramcore_csr_dfi_p3_cas_n <= 1'd1; + main_litedramcore_csr_dfi_p3_we_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p3_cs_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}}; + main_litedramcore_csr_dfi_p3_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_csr_dfi_p3_cas_n <= (~main_litedramcore_phaseinjector3_csrfield_cas); end else begin - litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; + main_litedramcore_csr_dfi_p3_cas_n <= 1'd1; end end always @(*) begin - litedramcore_csr_dfi_p3_ras_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras); + main_litedramcore_csr_dfi_p3_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + if (main_litedramcore_phaseinjector3_csrfield_cs_top) begin + main_litedramcore_csr_dfi_p3_cs_n <= 2'd2; + end else begin + if (main_litedramcore_phaseinjector3_csrfield_cs_bottom) begin + main_litedramcore_csr_dfi_p3_cs_n <= 1'd1; + end else begin + main_litedramcore_csr_dfi_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_csrfield_cs)}}; + end + end end else begin - litedramcore_csr_dfi_p3_ras_n <= 1'd1; + main_litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; end end -assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage; -assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage; -assign litedramcore_csr_dfi_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_wren); -assign litedramcore_csr_dfi_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_rden); -assign litedramcore_csr_dfi_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage; -assign litedramcore_csr_dfi_p3_wrdata_mask = 1'd0; -assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid; -assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready; -assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we; -assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr; -assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock; -assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready; -assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid; -assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid; -assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready; -assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we; -assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr; -assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock; -assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready; -assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid; -assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid; -assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready; -assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we; -assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr; -assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock; -assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready; -assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid; -assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid; -assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready; -assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we; -assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr; -assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock; -assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready; -assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid; -assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid; -assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready; -assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we; -assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr; -assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock; -assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready; -assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid; -assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid; -assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready; -assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we; -assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr; -assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock; -assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready; -assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid; -assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid; -assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready; -assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we; -assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr; -assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock; -assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready; -assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid; -assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid; -assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready; -assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we; -assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr; -assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock; -assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready; -assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid; -assign litedramcore_timer_wait = (~litedramcore_timer_done0); -assign litedramcore_postponer_req_i = litedramcore_timer_done0; -assign litedramcore_wants_refresh = litedramcore_postponer_req_o; -assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0; -assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done); -assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0); -assign litedramcore_timer_done0 = litedramcore_timer_done1; -assign litedramcore_timer_count0 = litedramcore_timer_count1; -assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0)); -assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0)); -assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0); -assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1; -assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1; -always @(*) begin - litedramcore_refresher_next_state <= 2'd0; - litedramcore_refresher_next_state <= litedramcore_refresher_state; - case (litedramcore_refresher_state) - 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_refresher_next_state <= 2'd2; - end - end - 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - litedramcore_refresher_next_state <= 2'd3; +always @(*) begin + main_litedramcore_csr_dfi_p3_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_csr_dfi_p3_ras_n <= (~main_litedramcore_phaseinjector3_csrfield_ras); + end else begin + main_litedramcore_csr_dfi_p3_ras_n <= 1'd1; + end +end +assign main_litedramcore_csr_dfi_p3_address = main_litedramcore_phaseinjector3_address_storage; +assign main_litedramcore_csr_dfi_p3_bank = main_litedramcore_phaseinjector3_baddress_storage; +assign main_litedramcore_csr_dfi_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_wren); +assign main_litedramcore_csr_dfi_p3_rddata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_rden); +assign main_litedramcore_csr_dfi_p3_wrdata = main_litedramcore_phaseinjector3_wrdata_storage; +assign main_litedramcore_csr_dfi_p3_wrdata_mask = 1'd0; +assign main_litedramcore_bankmachine0_req_valid = main_litedramcore_interface_bank0_valid; +assign main_litedramcore_interface_bank0_ready = main_litedramcore_bankmachine0_req_ready; +assign main_litedramcore_bankmachine0_req_we = main_litedramcore_interface_bank0_we; +assign main_litedramcore_bankmachine0_req_addr = main_litedramcore_interface_bank0_addr; +assign main_litedramcore_interface_bank0_lock = main_litedramcore_bankmachine0_req_lock; +assign main_litedramcore_interface_bank0_wdata_ready = main_litedramcore_bankmachine0_req_wdata_ready; +assign main_litedramcore_interface_bank0_rdata_valid = main_litedramcore_bankmachine0_req_rdata_valid; +assign main_litedramcore_bankmachine1_req_valid = main_litedramcore_interface_bank1_valid; +assign main_litedramcore_interface_bank1_ready = main_litedramcore_bankmachine1_req_ready; +assign main_litedramcore_bankmachine1_req_we = main_litedramcore_interface_bank1_we; +assign main_litedramcore_bankmachine1_req_addr = main_litedramcore_interface_bank1_addr; +assign main_litedramcore_interface_bank1_lock = main_litedramcore_bankmachine1_req_lock; +assign main_litedramcore_interface_bank1_wdata_ready = main_litedramcore_bankmachine1_req_wdata_ready; +assign main_litedramcore_interface_bank1_rdata_valid = main_litedramcore_bankmachine1_req_rdata_valid; +assign main_litedramcore_bankmachine2_req_valid = main_litedramcore_interface_bank2_valid; +assign main_litedramcore_interface_bank2_ready = main_litedramcore_bankmachine2_req_ready; +assign main_litedramcore_bankmachine2_req_we = main_litedramcore_interface_bank2_we; +assign main_litedramcore_bankmachine2_req_addr = main_litedramcore_interface_bank2_addr; +assign main_litedramcore_interface_bank2_lock = main_litedramcore_bankmachine2_req_lock; +assign main_litedramcore_interface_bank2_wdata_ready = main_litedramcore_bankmachine2_req_wdata_ready; +assign main_litedramcore_interface_bank2_rdata_valid = main_litedramcore_bankmachine2_req_rdata_valid; +assign main_litedramcore_bankmachine3_req_valid = main_litedramcore_interface_bank3_valid; +assign main_litedramcore_interface_bank3_ready = main_litedramcore_bankmachine3_req_ready; +assign main_litedramcore_bankmachine3_req_we = main_litedramcore_interface_bank3_we; +assign main_litedramcore_bankmachine3_req_addr = main_litedramcore_interface_bank3_addr; +assign main_litedramcore_interface_bank3_lock = main_litedramcore_bankmachine3_req_lock; +assign main_litedramcore_interface_bank3_wdata_ready = main_litedramcore_bankmachine3_req_wdata_ready; +assign main_litedramcore_interface_bank3_rdata_valid = main_litedramcore_bankmachine3_req_rdata_valid; +assign main_litedramcore_bankmachine4_req_valid = main_litedramcore_interface_bank4_valid; +assign main_litedramcore_interface_bank4_ready = main_litedramcore_bankmachine4_req_ready; +assign main_litedramcore_bankmachine4_req_we = main_litedramcore_interface_bank4_we; +assign main_litedramcore_bankmachine4_req_addr = main_litedramcore_interface_bank4_addr; +assign main_litedramcore_interface_bank4_lock = main_litedramcore_bankmachine4_req_lock; +assign main_litedramcore_interface_bank4_wdata_ready = main_litedramcore_bankmachine4_req_wdata_ready; +assign main_litedramcore_interface_bank4_rdata_valid = main_litedramcore_bankmachine4_req_rdata_valid; +assign main_litedramcore_bankmachine5_req_valid = main_litedramcore_interface_bank5_valid; +assign main_litedramcore_interface_bank5_ready = main_litedramcore_bankmachine5_req_ready; +assign main_litedramcore_bankmachine5_req_we = main_litedramcore_interface_bank5_we; +assign main_litedramcore_bankmachine5_req_addr = main_litedramcore_interface_bank5_addr; +assign main_litedramcore_interface_bank5_lock = main_litedramcore_bankmachine5_req_lock; +assign main_litedramcore_interface_bank5_wdata_ready = main_litedramcore_bankmachine5_req_wdata_ready; +assign main_litedramcore_interface_bank5_rdata_valid = main_litedramcore_bankmachine5_req_rdata_valid; +assign main_litedramcore_bankmachine6_req_valid = main_litedramcore_interface_bank6_valid; +assign main_litedramcore_interface_bank6_ready = main_litedramcore_bankmachine6_req_ready; +assign main_litedramcore_bankmachine6_req_we = main_litedramcore_interface_bank6_we; +assign main_litedramcore_bankmachine6_req_addr = main_litedramcore_interface_bank6_addr; +assign main_litedramcore_interface_bank6_lock = main_litedramcore_bankmachine6_req_lock; +assign main_litedramcore_interface_bank6_wdata_ready = main_litedramcore_bankmachine6_req_wdata_ready; +assign main_litedramcore_interface_bank6_rdata_valid = main_litedramcore_bankmachine6_req_rdata_valid; +assign main_litedramcore_bankmachine7_req_valid = main_litedramcore_interface_bank7_valid; +assign main_litedramcore_interface_bank7_ready = main_litedramcore_bankmachine7_req_ready; +assign main_litedramcore_bankmachine7_req_we = main_litedramcore_interface_bank7_we; +assign main_litedramcore_bankmachine7_req_addr = main_litedramcore_interface_bank7_addr; +assign main_litedramcore_interface_bank7_lock = main_litedramcore_bankmachine7_req_lock; +assign main_litedramcore_interface_bank7_wdata_ready = main_litedramcore_bankmachine7_req_wdata_ready; +assign main_litedramcore_interface_bank7_rdata_valid = main_litedramcore_bankmachine7_req_rdata_valid; +assign main_litedramcore_timer_wait = (~main_litedramcore_timer_done0); +assign main_litedramcore_postponer_req_i = main_litedramcore_timer_done0; +assign main_litedramcore_wants_refresh = main_litedramcore_postponer_req_o; +assign main_litedramcore_wants_zqcs = main_litedramcore_zqcs_timer_done0; +assign main_litedramcore_zqcs_timer_wait = (~main_litedramcore_zqcs_executer_done); +assign main_litedramcore_timer_done1 = (main_litedramcore_timer_count1 == 1'd0); +assign main_litedramcore_timer_done0 = main_litedramcore_timer_done1; +assign main_litedramcore_timer_count0 = main_litedramcore_timer_count1; +assign main_litedramcore_sequencer_start1 = (main_litedramcore_sequencer_start0 | (main_litedramcore_sequencer_count != 1'd0)); +assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & (main_litedramcore_sequencer_count == 1'd0)); +assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0); +assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1; +assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1; +always @(*) begin + builder_refresher_next_state <= 2'd0; + builder_refresher_next_state <= builder_refresher_state; + case (builder_refresher_state) + 1'd1: begin + if (main_litedramcore_cmd_ready) begin + builder_refresher_next_state <= 2'd2; + end + end + 2'd2: begin + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + builder_refresher_next_state <= 2'd3; end else begin - litedramcore_refresher_next_state <= 1'd0; + builder_refresher_next_state <= 1'd0; end end end 2'd3: begin - if (litedramcore_zqcs_executer_done) begin - litedramcore_refresher_next_state <= 1'd0; + if (main_litedramcore_zqcs_executer_done) begin + builder_refresher_next_state <= 1'd0; end end default: begin if (1'd1) begin - if (litedramcore_wants_refresh) begin - litedramcore_refresher_next_state <= 1'd1; + if (main_litedramcore_wants_refresh) begin + builder_refresher_next_state <= 1'd1; end end end endcase end always @(*) begin - litedramcore_zqcs_executer_start <= 1'd0; - case (litedramcore_refresher_state) + main_litedramcore_cmd_valid <= 1'd0; + case (builder_refresher_state) 1'd1: begin + main_litedramcore_cmd_valid <= 1'd1; end 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - litedramcore_zqcs_executer_start <= 1'd1; + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin end else begin + main_litedramcore_cmd_valid <= 1'd0; end end end 2'd3: begin + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_valid <= 1'd0; + end end default: begin end endcase end always @(*) begin - litedramcore_cmd_last <= 1'd0; - case (litedramcore_refresher_state) + main_litedramcore_zqcs_executer_start <= 1'd0; + case (builder_refresher_state) 1'd1: begin end 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + main_litedramcore_zqcs_executer_start <= 1'd1; end else begin - litedramcore_cmd_last <= 1'd1; end end end 2'd3: begin - if (litedramcore_zqcs_executer_done) begin - litedramcore_cmd_last <= 1'd1; - end end default: begin end endcase end always @(*) begin - litedramcore_sequencer_start0 <= 1'd0; - case (litedramcore_refresher_state) + main_litedramcore_cmd_last <= 1'd0; + case (builder_refresher_state) 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_sequencer_start0 <= 1'd1; - end end 2'd2: begin + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + end else begin + main_litedramcore_cmd_last <= 1'd1; + end + end end 2'd3: begin + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_last <= 1'd1; + end end default: begin end endcase end always @(*) begin - litedramcore_cmd_valid <= 1'd0; - case (litedramcore_refresher_state) + main_litedramcore_sequencer_start0 <= 1'd0; + case (builder_refresher_state) 1'd1: begin - litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_cmd_ready) begin + main_litedramcore_sequencer_start0 <= 1'd1; + end end 2'd2: begin - litedramcore_cmd_valid <= 1'd1; - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - end else begin - litedramcore_cmd_valid <= 1'd0; - end - end end 2'd3: begin - litedramcore_cmd_valid <= 1'd1; - if (litedramcore_zqcs_executer_done) begin - litedramcore_cmd_valid <= 1'd0; - end - end - default: begin - end - endcase -end -assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid; -assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready; -assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we; -assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr; -assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid; -assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready; -assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first; -assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last; -assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we; -assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr; -assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); -assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid); -assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[20:7]); -assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0; -always @(*) begin - litedramcore_bankmachine0_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine0_row_col_n_addr_sel) begin - litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_source_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write); -assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); -assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); -always @(*) begin - litedramcore_bankmachine0_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin - if ((litedramcore_bankmachine0_source_payload_addr[20:7] != litedramcore_bankmachine0_source_source_payload_addr[20:7])) begin - litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we}; -assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; -assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; -assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; -assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; -assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable; -assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid; -assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first; -assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last; -assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we; -assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr; -assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable; -assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first; -assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last; -assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we; -assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr; -assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready; -always @(*) begin - litedramcore_bankmachine0_wrport_adr <= 4'd0; - if (litedramcore_bankmachine0_replace) begin - litedramcore_bankmachine0_wrport_adr <= (litedramcore_bankmachine0_produce - 1'd1); - end else begin - litedramcore_bankmachine0_wrport_adr <= litedramcore_bankmachine0_produce; - end -end -assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din; -assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace)); -assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re); -assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume; -assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r; -assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 5'd16); -assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0); -assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready); -assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid; -assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready; -assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first; -assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last; -assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we; -assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr; -assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid; -assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready; -assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first; -assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last; -assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we; -assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine0_next_state <= 4'd0; - litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - if (litedramcore_bankmachine0_cmd_ready) begin - litedramcore_bankmachine0_next_state <= 3'd5; + end + default: begin + end + endcase +end +assign main_litedramcore_bankmachine0_sink_valid = main_litedramcore_bankmachine0_req_valid; +assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_sink_ready; +assign main_litedramcore_bankmachine0_sink_payload_we = main_litedramcore_bankmachine0_req_we; +assign main_litedramcore_bankmachine0_sink_payload_addr = main_litedramcore_bankmachine0_req_addr; +assign main_litedramcore_bankmachine0_sink_sink_valid = main_litedramcore_bankmachine0_source_valid; +assign main_litedramcore_bankmachine0_source_ready = main_litedramcore_bankmachine0_sink_sink_ready; +assign main_litedramcore_bankmachine0_sink_sink_first = main_litedramcore_bankmachine0_source_first; +assign main_litedramcore_bankmachine0_sink_sink_last = main_litedramcore_bankmachine0_source_last; +assign main_litedramcore_bankmachine0_sink_sink_payload_we = main_litedramcore_bankmachine0_source_payload_we; +assign main_litedramcore_bankmachine0_sink_sink_payload_addr = main_litedramcore_bankmachine0_source_payload_addr; +assign main_litedramcore_bankmachine0_source_source_ready = (main_litedramcore_bankmachine0_req_wdata_ready | main_litedramcore_bankmachine0_req_rdata_valid); +assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_source_valid | main_litedramcore_bankmachine0_source_source_valid); +assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_source_source_payload_addr[20:7]); +assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0; +always @(*) begin + main_litedramcore_bankmachine0_cmd_payload_a <= 14'd0; + if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin + main_litedramcore_bankmachine0_cmd_payload_a <= main_litedramcore_bankmachine0_source_source_payload_addr[20:7]; + end else begin + main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write); +assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); +assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); +always @(*) begin + main_litedramcore_bankmachine0_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine0_source_valid & main_litedramcore_bankmachine0_source_source_valid)) begin + if ((main_litedramcore_bankmachine0_source_payload_addr[20:7] != main_litedramcore_bankmachine0_source_source_payload_addr[20:7])) begin + main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine0_syncfifo0_din = {main_litedramcore_bankmachine0_fifo_in_last, main_litedramcore_bankmachine0_fifo_in_first, main_litedramcore_bankmachine0_fifo_in_payload_addr, main_litedramcore_bankmachine0_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout; +assign {main_litedramcore_bankmachine0_fifo_out_last, main_litedramcore_bankmachine0_fifo_out_first, main_litedramcore_bankmachine0_fifo_out_payload_addr, main_litedramcore_bankmachine0_fifo_out_payload_we} = main_litedramcore_bankmachine0_syncfifo0_dout; +assign main_litedramcore_bankmachine0_sink_ready = main_litedramcore_bankmachine0_syncfifo0_writable; +assign main_litedramcore_bankmachine0_syncfifo0_we = main_litedramcore_bankmachine0_sink_valid; +assign main_litedramcore_bankmachine0_fifo_in_first = main_litedramcore_bankmachine0_sink_first; +assign main_litedramcore_bankmachine0_fifo_in_last = main_litedramcore_bankmachine0_sink_last; +assign main_litedramcore_bankmachine0_fifo_in_payload_we = main_litedramcore_bankmachine0_sink_payload_we; +assign main_litedramcore_bankmachine0_fifo_in_payload_addr = main_litedramcore_bankmachine0_sink_payload_addr; +assign main_litedramcore_bankmachine0_source_valid = main_litedramcore_bankmachine0_syncfifo0_readable; +assign main_litedramcore_bankmachine0_source_first = main_litedramcore_bankmachine0_fifo_out_first; +assign main_litedramcore_bankmachine0_source_last = main_litedramcore_bankmachine0_fifo_out_last; +assign main_litedramcore_bankmachine0_source_payload_we = main_litedramcore_bankmachine0_fifo_out_payload_we; +assign main_litedramcore_bankmachine0_source_payload_addr = main_litedramcore_bankmachine0_fifo_out_payload_addr; +assign main_litedramcore_bankmachine0_syncfifo0_re = main_litedramcore_bankmachine0_source_ready; +always @(*) begin + main_litedramcore_bankmachine0_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine0_replace) begin + main_litedramcore_bankmachine0_wrport_adr <= (main_litedramcore_bankmachine0_produce - 1'd1); + end else begin + main_litedramcore_bankmachine0_wrport_adr <= main_litedramcore_bankmachine0_produce; + end +end +assign main_litedramcore_bankmachine0_wrport_dat_w = main_litedramcore_bankmachine0_syncfifo0_din; +assign main_litedramcore_bankmachine0_wrport_we = (main_litedramcore_bankmachine0_syncfifo0_we & (main_litedramcore_bankmachine0_syncfifo0_writable | main_litedramcore_bankmachine0_replace)); +assign main_litedramcore_bankmachine0_do_read = (main_litedramcore_bankmachine0_syncfifo0_readable & main_litedramcore_bankmachine0_syncfifo0_re); +assign main_litedramcore_bankmachine0_rdport_adr = main_litedramcore_bankmachine0_consume; +assign main_litedramcore_bankmachine0_syncfifo0_dout = main_litedramcore_bankmachine0_rdport_dat_r; +assign main_litedramcore_bankmachine0_syncfifo0_writable = (main_litedramcore_bankmachine0_level != 5'd16); +assign main_litedramcore_bankmachine0_syncfifo0_readable = (main_litedramcore_bankmachine0_level != 1'd0); +assign main_litedramcore_bankmachine0_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine0_pipe_valid_source_valid) | main_litedramcore_bankmachine0_pipe_valid_source_ready); +assign main_litedramcore_bankmachine0_pipe_valid_sink_valid = main_litedramcore_bankmachine0_sink_sink_valid; +assign main_litedramcore_bankmachine0_sink_sink_ready = main_litedramcore_bankmachine0_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine0_pipe_valid_sink_first = main_litedramcore_bankmachine0_sink_sink_first; +assign main_litedramcore_bankmachine0_pipe_valid_sink_last = main_litedramcore_bankmachine0_sink_sink_last; +assign main_litedramcore_bankmachine0_pipe_valid_sink_payload_we = main_litedramcore_bankmachine0_sink_sink_payload_we; +assign main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine0_sink_sink_payload_addr; +assign main_litedramcore_bankmachine0_source_source_valid = main_litedramcore_bankmachine0_pipe_valid_source_valid; +assign main_litedramcore_bankmachine0_pipe_valid_source_ready = main_litedramcore_bankmachine0_source_source_ready; +assign main_litedramcore_bankmachine0_source_source_first = main_litedramcore_bankmachine0_pipe_valid_source_first; +assign main_litedramcore_bankmachine0_source_source_last = main_litedramcore_bankmachine0_pipe_valid_source_last; +assign main_litedramcore_bankmachine0_source_source_payload_we = main_litedramcore_bankmachine0_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine0_source_source_payload_addr = main_litedramcore_bankmachine0_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine0_next_state <= 4'd0; + builder_bankmachine0_next_state <= builder_bankmachine0_state; + case (builder_bankmachine0_state) + 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + if (main_litedramcore_bankmachine0_cmd_ready) begin + builder_bankmachine0_next_state <= 3'd5; end end end 2'd2: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_next_state <= 3'd5; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + builder_bankmachine0_next_state <= 3'd5; end end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - if (litedramcore_bankmachine0_cmd_ready) begin - litedramcore_bankmachine0_next_state <= 3'd7; + if (main_litedramcore_bankmachine0_trccon_ready) begin + if (main_litedramcore_bankmachine0_cmd_ready) begin + builder_bankmachine0_next_state <= 3'd7; end end end 3'd4: begin - if ((~litedramcore_bankmachine0_refresh_req)) begin - litedramcore_bankmachine0_next_state <= 1'd0; + if ((~main_litedramcore_bankmachine0_refresh_req)) begin + builder_bankmachine0_next_state <= 1'd0; end end 3'd5: begin - litedramcore_bankmachine0_next_state <= 3'd6; + builder_bankmachine0_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine0_next_state <= 2'd3; + builder_bankmachine0_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine0_next_state <= 4'd8; + builder_bankmachine0_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine0_next_state <= 1'd0; + builder_bankmachine0_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - litedramcore_bankmachine0_next_state <= 3'd4; + if (main_litedramcore_bankmachine0_refresh_req) begin + builder_bankmachine0_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin - litedramcore_bankmachine0_next_state <= 2'd2; + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if ((main_litedramcore_bankmachine0_cmd_ready & main_litedramcore_bankmachine0_auto_precharge)) begin + builder_bankmachine0_next_state <= 2'd2; end end else begin - litedramcore_bankmachine0_next_state <= 1'd1; + builder_bankmachine0_next_state <= 1'd1; end end else begin - litedramcore_bankmachine0_next_state <= 2'd3; + builder_bankmachine0_next_state <= 2'd3; end end end @@ -4888,8 +5306,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -4907,14 +5325,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; end else begin - litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; end end else begin end @@ -4926,8 +5344,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -4935,9 +5353,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine0_twtpcon_ready) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -4948,20 +5363,32 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin + main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine0_row_open <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_open <= 1'd1; - end end 3'd4: begin end @@ -4974,25 +5401,37 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin + end else begin + main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine0_cmd_valid <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_refresh_gnt <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine0_twtpcon_ready) begin + main_litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -5003,34 +5442,22 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine0_row_close <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_row_open <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - litedramcore_bankmachine0_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_row_open <= 1'd1; + end end 3'd4: begin - litedramcore_bankmachine0_row_close <= 1'd1; end 3'd5: begin end @@ -5045,15 +5472,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; end end 3'd4: begin @@ -5067,19 +5497,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_row_close <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin + main_litedramcore_bankmachine0_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + main_litedramcore_bankmachine0_row_close <= 1'd1; end 3'd5: begin end @@ -5090,34 +5535,19 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -5135,12 +5565,9 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -5157,15 +5584,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end else begin - end + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -5176,22 +5600,21 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5206,9 +5629,12 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -5225,14 +5651,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; end else begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; end end else begin end @@ -5244,15 +5670,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5263,27 +5696,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine0_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine0_state) + main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5301,14 +5719,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin + if (main_litedramcore_bankmachine0_refresh_req) begin end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin - litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin end else begin + main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; end end else begin end @@ -5319,139 +5737,139 @@ always @(*) begin end endcase end -assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid; -assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready; -assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we; -assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr; -assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid; -assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready; -assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first; -assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last; -assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we; -assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr; -assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); -assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid); -assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[20:7]); -assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1; -always @(*) begin - litedramcore_bankmachine1_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine1_row_col_n_addr_sel) begin - litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_source_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write); -assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); -assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); -always @(*) begin - litedramcore_bankmachine1_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin - if ((litedramcore_bankmachine1_source_payload_addr[20:7] != litedramcore_bankmachine1_source_source_payload_addr[20:7])) begin - litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we}; -assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; -assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; -assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; -assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; -assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable; -assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid; -assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first; -assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last; -assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we; -assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr; -assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable; -assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first; -assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last; -assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we; -assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr; -assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready; -always @(*) begin - litedramcore_bankmachine1_wrport_adr <= 4'd0; - if (litedramcore_bankmachine1_replace) begin - litedramcore_bankmachine1_wrport_adr <= (litedramcore_bankmachine1_produce - 1'd1); - end else begin - litedramcore_bankmachine1_wrport_adr <= litedramcore_bankmachine1_produce; - end -end -assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din; -assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace)); -assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re); -assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume; -assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r; -assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 5'd16); -assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0); -assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready); -assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid; -assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready; -assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first; -assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last; -assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we; -assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr; -assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid; -assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready; -assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first; -assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last; -assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we; -assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine1_next_state <= 4'd0; - litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - if (litedramcore_bankmachine1_cmd_ready) begin - litedramcore_bankmachine1_next_state <= 3'd5; +assign main_litedramcore_bankmachine1_sink_valid = main_litedramcore_bankmachine1_req_valid; +assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_sink_ready; +assign main_litedramcore_bankmachine1_sink_payload_we = main_litedramcore_bankmachine1_req_we; +assign main_litedramcore_bankmachine1_sink_payload_addr = main_litedramcore_bankmachine1_req_addr; +assign main_litedramcore_bankmachine1_sink_sink_valid = main_litedramcore_bankmachine1_source_valid; +assign main_litedramcore_bankmachine1_source_ready = main_litedramcore_bankmachine1_sink_sink_ready; +assign main_litedramcore_bankmachine1_sink_sink_first = main_litedramcore_bankmachine1_source_first; +assign main_litedramcore_bankmachine1_sink_sink_last = main_litedramcore_bankmachine1_source_last; +assign main_litedramcore_bankmachine1_sink_sink_payload_we = main_litedramcore_bankmachine1_source_payload_we; +assign main_litedramcore_bankmachine1_sink_sink_payload_addr = main_litedramcore_bankmachine1_source_payload_addr; +assign main_litedramcore_bankmachine1_source_source_ready = (main_litedramcore_bankmachine1_req_wdata_ready | main_litedramcore_bankmachine1_req_rdata_valid); +assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_source_valid | main_litedramcore_bankmachine1_source_source_valid); +assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_source_source_payload_addr[20:7]); +assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; +always @(*) begin + main_litedramcore_bankmachine1_cmd_payload_a <= 14'd0; + if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin + main_litedramcore_bankmachine1_cmd_payload_a <= main_litedramcore_bankmachine1_source_source_payload_addr[20:7]; + end else begin + main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write); +assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); +assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); +always @(*) begin + main_litedramcore_bankmachine1_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine1_source_valid & main_litedramcore_bankmachine1_source_source_valid)) begin + if ((main_litedramcore_bankmachine1_source_payload_addr[20:7] != main_litedramcore_bankmachine1_source_source_payload_addr[20:7])) begin + main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine1_syncfifo1_din = {main_litedramcore_bankmachine1_fifo_in_last, main_litedramcore_bankmachine1_fifo_in_first, main_litedramcore_bankmachine1_fifo_in_payload_addr, main_litedramcore_bankmachine1_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout; +assign {main_litedramcore_bankmachine1_fifo_out_last, main_litedramcore_bankmachine1_fifo_out_first, main_litedramcore_bankmachine1_fifo_out_payload_addr, main_litedramcore_bankmachine1_fifo_out_payload_we} = main_litedramcore_bankmachine1_syncfifo1_dout; +assign main_litedramcore_bankmachine1_sink_ready = main_litedramcore_bankmachine1_syncfifo1_writable; +assign main_litedramcore_bankmachine1_syncfifo1_we = main_litedramcore_bankmachine1_sink_valid; +assign main_litedramcore_bankmachine1_fifo_in_first = main_litedramcore_bankmachine1_sink_first; +assign main_litedramcore_bankmachine1_fifo_in_last = main_litedramcore_bankmachine1_sink_last; +assign main_litedramcore_bankmachine1_fifo_in_payload_we = main_litedramcore_bankmachine1_sink_payload_we; +assign main_litedramcore_bankmachine1_fifo_in_payload_addr = main_litedramcore_bankmachine1_sink_payload_addr; +assign main_litedramcore_bankmachine1_source_valid = main_litedramcore_bankmachine1_syncfifo1_readable; +assign main_litedramcore_bankmachine1_source_first = main_litedramcore_bankmachine1_fifo_out_first; +assign main_litedramcore_bankmachine1_source_last = main_litedramcore_bankmachine1_fifo_out_last; +assign main_litedramcore_bankmachine1_source_payload_we = main_litedramcore_bankmachine1_fifo_out_payload_we; +assign main_litedramcore_bankmachine1_source_payload_addr = main_litedramcore_bankmachine1_fifo_out_payload_addr; +assign main_litedramcore_bankmachine1_syncfifo1_re = main_litedramcore_bankmachine1_source_ready; +always @(*) begin + main_litedramcore_bankmachine1_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine1_replace) begin + main_litedramcore_bankmachine1_wrport_adr <= (main_litedramcore_bankmachine1_produce - 1'd1); + end else begin + main_litedramcore_bankmachine1_wrport_adr <= main_litedramcore_bankmachine1_produce; + end +end +assign main_litedramcore_bankmachine1_wrport_dat_w = main_litedramcore_bankmachine1_syncfifo1_din; +assign main_litedramcore_bankmachine1_wrport_we = (main_litedramcore_bankmachine1_syncfifo1_we & (main_litedramcore_bankmachine1_syncfifo1_writable | main_litedramcore_bankmachine1_replace)); +assign main_litedramcore_bankmachine1_do_read = (main_litedramcore_bankmachine1_syncfifo1_readable & main_litedramcore_bankmachine1_syncfifo1_re); +assign main_litedramcore_bankmachine1_rdport_adr = main_litedramcore_bankmachine1_consume; +assign main_litedramcore_bankmachine1_syncfifo1_dout = main_litedramcore_bankmachine1_rdport_dat_r; +assign main_litedramcore_bankmachine1_syncfifo1_writable = (main_litedramcore_bankmachine1_level != 5'd16); +assign main_litedramcore_bankmachine1_syncfifo1_readable = (main_litedramcore_bankmachine1_level != 1'd0); +assign main_litedramcore_bankmachine1_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine1_pipe_valid_source_valid) | main_litedramcore_bankmachine1_pipe_valid_source_ready); +assign main_litedramcore_bankmachine1_pipe_valid_sink_valid = main_litedramcore_bankmachine1_sink_sink_valid; +assign main_litedramcore_bankmachine1_sink_sink_ready = main_litedramcore_bankmachine1_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine1_pipe_valid_sink_first = main_litedramcore_bankmachine1_sink_sink_first; +assign main_litedramcore_bankmachine1_pipe_valid_sink_last = main_litedramcore_bankmachine1_sink_sink_last; +assign main_litedramcore_bankmachine1_pipe_valid_sink_payload_we = main_litedramcore_bankmachine1_sink_sink_payload_we; +assign main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine1_sink_sink_payload_addr; +assign main_litedramcore_bankmachine1_source_source_valid = main_litedramcore_bankmachine1_pipe_valid_source_valid; +assign main_litedramcore_bankmachine1_pipe_valid_source_ready = main_litedramcore_bankmachine1_source_source_ready; +assign main_litedramcore_bankmachine1_source_source_first = main_litedramcore_bankmachine1_pipe_valid_source_first; +assign main_litedramcore_bankmachine1_source_source_last = main_litedramcore_bankmachine1_pipe_valid_source_last; +assign main_litedramcore_bankmachine1_source_source_payload_we = main_litedramcore_bankmachine1_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine1_source_source_payload_addr = main_litedramcore_bankmachine1_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine1_next_state <= 4'd0; + builder_bankmachine1_next_state <= builder_bankmachine1_state; + case (builder_bankmachine1_state) + 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + if (main_litedramcore_bankmachine1_cmd_ready) begin + builder_bankmachine1_next_state <= 3'd5; end end end 2'd2: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_next_state <= 3'd5; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + builder_bankmachine1_next_state <= 3'd5; end end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - if (litedramcore_bankmachine1_cmd_ready) begin - litedramcore_bankmachine1_next_state <= 3'd7; + if (main_litedramcore_bankmachine1_trccon_ready) begin + if (main_litedramcore_bankmachine1_cmd_ready) begin + builder_bankmachine1_next_state <= 3'd7; end end end 3'd4: begin - if ((~litedramcore_bankmachine1_refresh_req)) begin - litedramcore_bankmachine1_next_state <= 1'd0; + if ((~main_litedramcore_bankmachine1_refresh_req)) begin + builder_bankmachine1_next_state <= 1'd0; end end 3'd5: begin - litedramcore_bankmachine1_next_state <= 3'd6; + builder_bankmachine1_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine1_next_state <= 2'd3; + builder_bankmachine1_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine1_next_state <= 4'd8; + builder_bankmachine1_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine1_next_state <= 1'd0; + builder_bankmachine1_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - litedramcore_bankmachine1_next_state <= 3'd4; + if (main_litedramcore_bankmachine1_refresh_req) begin + builder_bankmachine1_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin - litedramcore_bankmachine1_next_state <= 2'd2; + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if ((main_litedramcore_bankmachine1_cmd_ready & main_litedramcore_bankmachine1_auto_precharge)) begin + builder_bankmachine1_next_state <= 2'd2; end end else begin - litedramcore_bankmachine1_next_state <= 1'd1; + builder_bankmachine1_next_state <= 1'd1; end end else begin - litedramcore_bankmachine1_next_state <= 2'd3; + builder_bankmachine1_next_state <= 2'd3; end end end @@ -5459,18 +5877,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine1_twtpcon_ready) begin + main_litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -5485,13 +5903,16 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_row_open <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_row_open <= 1'd1; + end end 3'd4: begin end @@ -5504,34 +5925,22 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; end end 3'd4: begin @@ -5545,22 +5954,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_row_close <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end + main_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + main_litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -5571,41 +5992,22 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5620,8 +6022,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -5639,15 +6041,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - end else begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; - end + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -5658,13 +6057,19 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -5677,28 +6082,16 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine1_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -5715,13 +6108,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -5734,15 +6127,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5753,27 +6153,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - end else begin - litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -5781,9 +6166,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine1_twtpcon_ready) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -5794,20 +6176,32 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine1_row_open <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_open <= 1'd1; - end end 3'd4: begin end @@ -5820,23 +6214,32 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin + main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine1_cmd_valid <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -5849,12 +6252,15 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin + if (main_litedramcore_bankmachine1_refresh_req) begin end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin + main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready; + end else begin + end end else begin end end else begin @@ -5865,18 +6271,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_row_close <= 1'd0; - case (litedramcore_bankmachine1_state) + main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (builder_bankmachine1_state) 1'd1: begin - litedramcore_bankmachine1_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -5887,142 +6290,157 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase end -assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid; -assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready; -assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we; -assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr; -assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid; -assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready; -assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first; -assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last; -assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we; -assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr; -assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); -assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid); -assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[20:7]); -assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2; -always @(*) begin - litedramcore_bankmachine2_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine2_row_col_n_addr_sel) begin - litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_source_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write); -assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); -assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); -always @(*) begin - litedramcore_bankmachine2_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin - if ((litedramcore_bankmachine2_source_payload_addr[20:7] != litedramcore_bankmachine2_source_source_payload_addr[20:7])) begin - litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we}; -assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; -assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; -assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; -assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; -assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable; -assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid; -assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first; -assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last; -assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we; -assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr; -assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable; -assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first; -assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last; -assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we; -assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr; -assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready; -always @(*) begin - litedramcore_bankmachine2_wrport_adr <= 4'd0; - if (litedramcore_bankmachine2_replace) begin - litedramcore_bankmachine2_wrport_adr <= (litedramcore_bankmachine2_produce - 1'd1); - end else begin - litedramcore_bankmachine2_wrport_adr <= litedramcore_bankmachine2_produce; - end -end -assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din; -assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace)); -assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re); -assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume; -assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r; -assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 5'd16); -assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0); -assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready); -assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid; -assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready; -assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first; -assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last; -assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we; -assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr; -assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid; -assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready; -assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first; -assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last; -assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we; -assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine2_next_state <= 4'd0; - litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - if (litedramcore_bankmachine2_cmd_ready) begin - litedramcore_bankmachine2_next_state <= 3'd5; +assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid; +assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready; +assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we; +assign main_litedramcore_bankmachine2_sink_payload_addr = main_litedramcore_bankmachine2_req_addr; +assign main_litedramcore_bankmachine2_sink_sink_valid = main_litedramcore_bankmachine2_source_valid; +assign main_litedramcore_bankmachine2_source_ready = main_litedramcore_bankmachine2_sink_sink_ready; +assign main_litedramcore_bankmachine2_sink_sink_first = main_litedramcore_bankmachine2_source_first; +assign main_litedramcore_bankmachine2_sink_sink_last = main_litedramcore_bankmachine2_source_last; +assign main_litedramcore_bankmachine2_sink_sink_payload_we = main_litedramcore_bankmachine2_source_payload_we; +assign main_litedramcore_bankmachine2_sink_sink_payload_addr = main_litedramcore_bankmachine2_source_payload_addr; +assign main_litedramcore_bankmachine2_source_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid); +assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_source_valid | main_litedramcore_bankmachine2_source_source_valid); +assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_source_source_payload_addr[20:7]); +assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; +always @(*) begin + main_litedramcore_bankmachine2_cmd_payload_a <= 14'd0; + if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin + main_litedramcore_bankmachine2_cmd_payload_a <= main_litedramcore_bankmachine2_source_source_payload_addr[20:7]; + end else begin + main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write); +assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); +assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); +always @(*) begin + main_litedramcore_bankmachine2_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine2_source_valid & main_litedramcore_bankmachine2_source_source_valid)) begin + if ((main_litedramcore_bankmachine2_source_payload_addr[20:7] != main_litedramcore_bankmachine2_source_source_payload_addr[20:7])) begin + main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine2_syncfifo2_din = {main_litedramcore_bankmachine2_fifo_in_last, main_litedramcore_bankmachine2_fifo_in_first, main_litedramcore_bankmachine2_fifo_in_payload_addr, main_litedramcore_bankmachine2_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; +assign main_litedramcore_bankmachine2_sink_ready = main_litedramcore_bankmachine2_syncfifo2_writable; +assign main_litedramcore_bankmachine2_syncfifo2_we = main_litedramcore_bankmachine2_sink_valid; +assign main_litedramcore_bankmachine2_fifo_in_first = main_litedramcore_bankmachine2_sink_first; +assign main_litedramcore_bankmachine2_fifo_in_last = main_litedramcore_bankmachine2_sink_last; +assign main_litedramcore_bankmachine2_fifo_in_payload_we = main_litedramcore_bankmachine2_sink_payload_we; +assign main_litedramcore_bankmachine2_fifo_in_payload_addr = main_litedramcore_bankmachine2_sink_payload_addr; +assign main_litedramcore_bankmachine2_source_valid = main_litedramcore_bankmachine2_syncfifo2_readable; +assign main_litedramcore_bankmachine2_source_first = main_litedramcore_bankmachine2_fifo_out_first; +assign main_litedramcore_bankmachine2_source_last = main_litedramcore_bankmachine2_fifo_out_last; +assign main_litedramcore_bankmachine2_source_payload_we = main_litedramcore_bankmachine2_fifo_out_payload_we; +assign main_litedramcore_bankmachine2_source_payload_addr = main_litedramcore_bankmachine2_fifo_out_payload_addr; +assign main_litedramcore_bankmachine2_syncfifo2_re = main_litedramcore_bankmachine2_source_ready; +always @(*) begin + main_litedramcore_bankmachine2_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine2_replace) begin + main_litedramcore_bankmachine2_wrport_adr <= (main_litedramcore_bankmachine2_produce - 1'd1); + end else begin + main_litedramcore_bankmachine2_wrport_adr <= main_litedramcore_bankmachine2_produce; + end +end +assign main_litedramcore_bankmachine2_wrport_dat_w = main_litedramcore_bankmachine2_syncfifo2_din; +assign main_litedramcore_bankmachine2_wrport_we = (main_litedramcore_bankmachine2_syncfifo2_we & (main_litedramcore_bankmachine2_syncfifo2_writable | main_litedramcore_bankmachine2_replace)); +assign main_litedramcore_bankmachine2_do_read = (main_litedramcore_bankmachine2_syncfifo2_readable & main_litedramcore_bankmachine2_syncfifo2_re); +assign main_litedramcore_bankmachine2_rdport_adr = main_litedramcore_bankmachine2_consume; +assign main_litedramcore_bankmachine2_syncfifo2_dout = main_litedramcore_bankmachine2_rdport_dat_r; +assign main_litedramcore_bankmachine2_syncfifo2_writable = (main_litedramcore_bankmachine2_level != 5'd16); +assign main_litedramcore_bankmachine2_syncfifo2_readable = (main_litedramcore_bankmachine2_level != 1'd0); +assign main_litedramcore_bankmachine2_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine2_pipe_valid_source_valid) | main_litedramcore_bankmachine2_pipe_valid_source_ready); +assign main_litedramcore_bankmachine2_pipe_valid_sink_valid = main_litedramcore_bankmachine2_sink_sink_valid; +assign main_litedramcore_bankmachine2_sink_sink_ready = main_litedramcore_bankmachine2_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine2_pipe_valid_sink_first = main_litedramcore_bankmachine2_sink_sink_first; +assign main_litedramcore_bankmachine2_pipe_valid_sink_last = main_litedramcore_bankmachine2_sink_sink_last; +assign main_litedramcore_bankmachine2_pipe_valid_sink_payload_we = main_litedramcore_bankmachine2_sink_sink_payload_we; +assign main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine2_sink_sink_payload_addr; +assign main_litedramcore_bankmachine2_source_source_valid = main_litedramcore_bankmachine2_pipe_valid_source_valid; +assign main_litedramcore_bankmachine2_pipe_valid_source_ready = main_litedramcore_bankmachine2_source_source_ready; +assign main_litedramcore_bankmachine2_source_source_first = main_litedramcore_bankmachine2_pipe_valid_source_first; +assign main_litedramcore_bankmachine2_source_source_last = main_litedramcore_bankmachine2_pipe_valid_source_last; +assign main_litedramcore_bankmachine2_source_source_payload_we = main_litedramcore_bankmachine2_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine2_source_source_payload_addr = main_litedramcore_bankmachine2_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine2_next_state <= 4'd0; + builder_bankmachine2_next_state <= builder_bankmachine2_state; + case (builder_bankmachine2_state) + 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + if (main_litedramcore_bankmachine2_cmd_ready) begin + builder_bankmachine2_next_state <= 3'd5; end end end 2'd2: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_next_state <= 3'd5; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + builder_bankmachine2_next_state <= 3'd5; end end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - if (litedramcore_bankmachine2_cmd_ready) begin - litedramcore_bankmachine2_next_state <= 3'd7; + if (main_litedramcore_bankmachine2_trccon_ready) begin + if (main_litedramcore_bankmachine2_cmd_ready) begin + builder_bankmachine2_next_state <= 3'd7; end end end 3'd4: begin - if ((~litedramcore_bankmachine2_refresh_req)) begin - litedramcore_bankmachine2_next_state <= 1'd0; + if ((~main_litedramcore_bankmachine2_refresh_req)) begin + builder_bankmachine2_next_state <= 1'd0; end end 3'd5: begin - litedramcore_bankmachine2_next_state <= 3'd6; + builder_bankmachine2_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine2_next_state <= 2'd3; + builder_bankmachine2_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine2_next_state <= 4'd8; + builder_bankmachine2_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine2_next_state <= 1'd0; + builder_bankmachine2_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - litedramcore_bankmachine2_next_state <= 3'd4; + if (main_litedramcore_bankmachine2_refresh_req) begin + builder_bankmachine2_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin - litedramcore_bankmachine2_next_state <= 2'd2; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if ((main_litedramcore_bankmachine2_cmd_ready & main_litedramcore_bankmachine2_auto_precharge)) begin + builder_bankmachine2_next_state <= 2'd2; end end else begin - litedramcore_bankmachine2_next_state <= 1'd1; + builder_bankmachine2_next_state <= 1'd1; end end else begin - litedramcore_bankmachine2_next_state <= 2'd3; + builder_bankmachine2_next_state <= 2'd3; end end end @@ -6030,8 +6448,34 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6049,12 +6493,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -6065,18 +6509,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -6094,11 +6538,11 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -6116,13 +6560,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -6135,22 +6579,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6165,8 +6609,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6184,14 +6628,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin end else begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6203,8 +6647,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6222,13 +6666,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin + main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -6241,8 +6685,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6260,13 +6704,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin - litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin + main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready; end else begin end end else begin @@ -6279,8 +6723,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6298,14 +6742,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_source_source_payload_we) begin + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin end else begin - litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; + main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready; end end else begin end @@ -6317,8 +6761,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6326,8 +6770,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine2_twtpcon_ready) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd1; + if (main_litedramcore_bankmachine2_twtpcon_ready) begin + main_litedramcore_bankmachine2_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -6343,15 +6787,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_row_open <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_row_open <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_row_open <= 1'd1; end end 3'd4: begin @@ -6369,18 +6813,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_cmd_valid <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_cmd_valid <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; end end 3'd4: begin @@ -6394,12 +6838,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin + if (main_litedramcore_bankmachine2_refresh_req) begin end else begin - if (litedramcore_bankmachine2_source_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; end else begin end end else begin @@ -6410,18 +6854,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine2_row_close <= 1'd0; - case (litedramcore_bankmachine2_state) + main_litedramcore_bankmachine2_row_close <= 1'd0; + case (builder_bankmachine2_state) 1'd1: begin - litedramcore_bankmachine2_row_close <= 1'd1; + main_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine2_row_close <= 1'd1; + main_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine2_row_close <= 1'd1; + main_litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -6435,165 +6879,209 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine2_state) +assign main_litedramcore_bankmachine3_sink_valid = main_litedramcore_bankmachine3_req_valid; +assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_sink_ready; +assign main_litedramcore_bankmachine3_sink_payload_we = main_litedramcore_bankmachine3_req_we; +assign main_litedramcore_bankmachine3_sink_payload_addr = main_litedramcore_bankmachine3_req_addr; +assign main_litedramcore_bankmachine3_sink_sink_valid = main_litedramcore_bankmachine3_source_valid; +assign main_litedramcore_bankmachine3_source_ready = main_litedramcore_bankmachine3_sink_sink_ready; +assign main_litedramcore_bankmachine3_sink_sink_first = main_litedramcore_bankmachine3_source_first; +assign main_litedramcore_bankmachine3_sink_sink_last = main_litedramcore_bankmachine3_source_last; +assign main_litedramcore_bankmachine3_sink_sink_payload_we = main_litedramcore_bankmachine3_source_payload_we; +assign main_litedramcore_bankmachine3_sink_sink_payload_addr = main_litedramcore_bankmachine3_source_payload_addr; +assign main_litedramcore_bankmachine3_source_source_ready = (main_litedramcore_bankmachine3_req_wdata_ready | main_litedramcore_bankmachine3_req_rdata_valid); +assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_source_valid | main_litedramcore_bankmachine3_source_source_valid); +assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_source_source_payload_addr[20:7]); +assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; +always @(*) begin + main_litedramcore_bankmachine3_cmd_payload_a <= 14'd0; + if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin + main_litedramcore_bankmachine3_cmd_payload_a <= main_litedramcore_bankmachine3_source_source_payload_addr[20:7]; + end else begin + main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write); +assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); +assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); +always @(*) begin + main_litedramcore_bankmachine3_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine3_source_valid & main_litedramcore_bankmachine3_source_source_valid)) begin + if ((main_litedramcore_bankmachine3_source_payload_addr[20:7] != main_litedramcore_bankmachine3_source_source_payload_addr[20:7])) begin + main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine3_syncfifo3_din = {main_litedramcore_bankmachine3_fifo_in_last, main_litedramcore_bankmachine3_fifo_in_first, main_litedramcore_bankmachine3_fifo_in_payload_addr, main_litedramcore_bankmachine3_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout; +assign {main_litedramcore_bankmachine3_fifo_out_last, main_litedramcore_bankmachine3_fifo_out_first, main_litedramcore_bankmachine3_fifo_out_payload_addr, main_litedramcore_bankmachine3_fifo_out_payload_we} = main_litedramcore_bankmachine3_syncfifo3_dout; +assign main_litedramcore_bankmachine3_sink_ready = main_litedramcore_bankmachine3_syncfifo3_writable; +assign main_litedramcore_bankmachine3_syncfifo3_we = main_litedramcore_bankmachine3_sink_valid; +assign main_litedramcore_bankmachine3_fifo_in_first = main_litedramcore_bankmachine3_sink_first; +assign main_litedramcore_bankmachine3_fifo_in_last = main_litedramcore_bankmachine3_sink_last; +assign main_litedramcore_bankmachine3_fifo_in_payload_we = main_litedramcore_bankmachine3_sink_payload_we; +assign main_litedramcore_bankmachine3_fifo_in_payload_addr = main_litedramcore_bankmachine3_sink_payload_addr; +assign main_litedramcore_bankmachine3_source_valid = main_litedramcore_bankmachine3_syncfifo3_readable; +assign main_litedramcore_bankmachine3_source_first = main_litedramcore_bankmachine3_fifo_out_first; +assign main_litedramcore_bankmachine3_source_last = main_litedramcore_bankmachine3_fifo_out_last; +assign main_litedramcore_bankmachine3_source_payload_we = main_litedramcore_bankmachine3_fifo_out_payload_we; +assign main_litedramcore_bankmachine3_source_payload_addr = main_litedramcore_bankmachine3_fifo_out_payload_addr; +assign main_litedramcore_bankmachine3_syncfifo3_re = main_litedramcore_bankmachine3_source_ready; +always @(*) begin + main_litedramcore_bankmachine3_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine3_replace) begin + main_litedramcore_bankmachine3_wrport_adr <= (main_litedramcore_bankmachine3_produce - 1'd1); + end else begin + main_litedramcore_bankmachine3_wrport_adr <= main_litedramcore_bankmachine3_produce; + end +end +assign main_litedramcore_bankmachine3_wrport_dat_w = main_litedramcore_bankmachine3_syncfifo3_din; +assign main_litedramcore_bankmachine3_wrport_we = (main_litedramcore_bankmachine3_syncfifo3_we & (main_litedramcore_bankmachine3_syncfifo3_writable | main_litedramcore_bankmachine3_replace)); +assign main_litedramcore_bankmachine3_do_read = (main_litedramcore_bankmachine3_syncfifo3_readable & main_litedramcore_bankmachine3_syncfifo3_re); +assign main_litedramcore_bankmachine3_rdport_adr = main_litedramcore_bankmachine3_consume; +assign main_litedramcore_bankmachine3_syncfifo3_dout = main_litedramcore_bankmachine3_rdport_dat_r; +assign main_litedramcore_bankmachine3_syncfifo3_writable = (main_litedramcore_bankmachine3_level != 5'd16); +assign main_litedramcore_bankmachine3_syncfifo3_readable = (main_litedramcore_bankmachine3_level != 1'd0); +assign main_litedramcore_bankmachine3_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine3_pipe_valid_source_valid) | main_litedramcore_bankmachine3_pipe_valid_source_ready); +assign main_litedramcore_bankmachine3_pipe_valid_sink_valid = main_litedramcore_bankmachine3_sink_sink_valid; +assign main_litedramcore_bankmachine3_sink_sink_ready = main_litedramcore_bankmachine3_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine3_pipe_valid_sink_first = main_litedramcore_bankmachine3_sink_sink_first; +assign main_litedramcore_bankmachine3_pipe_valid_sink_last = main_litedramcore_bankmachine3_sink_sink_last; +assign main_litedramcore_bankmachine3_pipe_valid_sink_payload_we = main_litedramcore_bankmachine3_sink_sink_payload_we; +assign main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine3_sink_sink_payload_addr; +assign main_litedramcore_bankmachine3_source_source_valid = main_litedramcore_bankmachine3_pipe_valid_source_valid; +assign main_litedramcore_bankmachine3_pipe_valid_source_ready = main_litedramcore_bankmachine3_source_source_ready; +assign main_litedramcore_bankmachine3_source_source_first = main_litedramcore_bankmachine3_pipe_valid_source_first; +assign main_litedramcore_bankmachine3_source_source_last = main_litedramcore_bankmachine3_pipe_valid_source_last; +assign main_litedramcore_bankmachine3_source_source_payload_we = main_litedramcore_bankmachine3_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine3_source_source_payload_addr = main_litedramcore_bankmachine3_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine3_next_state <= 4'd0; + builder_bankmachine3_next_state <= builder_bankmachine3_state; + case (builder_bankmachine3_state) 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + if (main_litedramcore_bankmachine3_cmd_ready) begin + builder_bankmachine3_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + builder_bankmachine3_next_state <= 3'd5; + end end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + if (main_litedramcore_bankmachine3_cmd_ready) begin + builder_bankmachine3_next_state <= 3'd7; + end end end 3'd4: begin + if ((~main_litedramcore_bankmachine3_refresh_req)) begin + builder_bankmachine3_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine3_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine3_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine3_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine3_next_state <= 1'd0; end default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + builder_bankmachine3_next_state <= 3'd4; + end else begin + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin + builder_bankmachine3_next_state <= 2'd2; + end + end else begin + builder_bankmachine3_next_state <= 1'd1; + end + end else begin + builder_bankmachine3_next_state <= 2'd3; + end + end + end end endcase end -assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid; -assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready; -assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we; -assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr; -assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid; -assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready; -assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first; -assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last; -assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we; -assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr; -assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); -assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid); -assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[20:7]); -assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3; -always @(*) begin - litedramcore_bankmachine3_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine3_row_col_n_addr_sel) begin - litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_source_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write); -assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); -assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); -always @(*) begin - litedramcore_bankmachine3_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin - if ((litedramcore_bankmachine3_source_payload_addr[20:7] != litedramcore_bankmachine3_source_source_payload_addr[20:7])) begin - litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we}; -assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; -assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; -assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; -assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; -assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable; -assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid; -assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first; -assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last; -assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we; -assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr; -assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable; -assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first; -assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last; -assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we; -assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr; -assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready; -always @(*) begin - litedramcore_bankmachine3_wrport_adr <= 4'd0; - if (litedramcore_bankmachine3_replace) begin - litedramcore_bankmachine3_wrport_adr <= (litedramcore_bankmachine3_produce - 1'd1); - end else begin - litedramcore_bankmachine3_wrport_adr <= litedramcore_bankmachine3_produce; - end -end -assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din; -assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace)); -assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re); -assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume; -assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r; -assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 5'd16); -assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0); -assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready); -assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid; -assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready; -assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first; -assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last; -assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we; -assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr; -assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid; -assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready; -assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first; -assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last; -assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we; -assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine3_next_state <= 4'd0; - litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - if (litedramcore_bankmachine3_cmd_ready) begin - litedramcore_bankmachine3_next_state <= 3'd5; - end +always @(*) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (builder_bankmachine3_state) + 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; end end 2'd2: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - if (litedramcore_bankmachine3_cmd_ready) begin - litedramcore_bankmachine3_next_state <= 3'd7; - end + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; end end 3'd4: begin - if ((~litedramcore_bankmachine3_refresh_req)) begin - litedramcore_bankmachine3_next_state <= 1'd0; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (builder_bankmachine3_state) + 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; end end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end 3'd5: begin - litedramcore_bankmachine3_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine3_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine3_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine3_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - litedramcore_bankmachine3_next_state <= 3'd4; + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin - litedramcore_bankmachine3_next_state <= 2'd2; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end else begin end end else begin - litedramcore_bankmachine3_next_state <= 1'd1; end end else begin - litedramcore_bankmachine3_next_state <= 2'd3; end end end @@ -6601,22 +7089,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6631,8 +7119,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -6650,14 +7138,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin end else begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6669,8 +7157,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -6688,13 +7176,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin + main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -6707,8 +7195,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -6726,13 +7214,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin - litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin + main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready; end else begin end end else begin @@ -6745,8 +7233,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -6764,14 +7252,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin end else begin - litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; + main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready; end end else begin end @@ -6783,8 +7271,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -6792,8 +7280,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine3_twtpcon_ready) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd1; + if (main_litedramcore_bankmachine3_twtpcon_ready) begin + main_litedramcore_bankmachine3_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -6809,15 +7297,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_row_open <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_row_open <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_open <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_open <= 1'd1; end end 3'd4: begin @@ -6835,18 +7323,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_valid <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; end end 3'd4: begin @@ -6860,12 +7348,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; end else begin end end else begin @@ -6876,18 +7364,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_row_close <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_row_close <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin - litedramcore_bankmachine3_row_close <= 1'd1; + main_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine3_row_close <= 1'd1; + main_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine3_row_close <= 1'd1; + main_litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -6902,15 +7390,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -6928,8 +7416,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -6947,12 +7435,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine3_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -6962,42 +7450,149 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine3_state) +assign main_litedramcore_bankmachine4_sink_valid = main_litedramcore_bankmachine4_req_valid; +assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_sink_ready; +assign main_litedramcore_bankmachine4_sink_payload_we = main_litedramcore_bankmachine4_req_we; +assign main_litedramcore_bankmachine4_sink_payload_addr = main_litedramcore_bankmachine4_req_addr; +assign main_litedramcore_bankmachine4_sink_sink_valid = main_litedramcore_bankmachine4_source_valid; +assign main_litedramcore_bankmachine4_source_ready = main_litedramcore_bankmachine4_sink_sink_ready; +assign main_litedramcore_bankmachine4_sink_sink_first = main_litedramcore_bankmachine4_source_first; +assign main_litedramcore_bankmachine4_sink_sink_last = main_litedramcore_bankmachine4_source_last; +assign main_litedramcore_bankmachine4_sink_sink_payload_we = main_litedramcore_bankmachine4_source_payload_we; +assign main_litedramcore_bankmachine4_sink_sink_payload_addr = main_litedramcore_bankmachine4_source_payload_addr; +assign main_litedramcore_bankmachine4_source_source_ready = (main_litedramcore_bankmachine4_req_wdata_ready | main_litedramcore_bankmachine4_req_rdata_valid); +assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_source_valid | main_litedramcore_bankmachine4_source_source_valid); +assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_source_source_payload_addr[20:7]); +assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; +always @(*) begin + main_litedramcore_bankmachine4_cmd_payload_a <= 14'd0; + if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin + main_litedramcore_bankmachine4_cmd_payload_a <= main_litedramcore_bankmachine4_source_source_payload_addr[20:7]; + end else begin + main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write); +assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); +assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); +always @(*) begin + main_litedramcore_bankmachine4_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine4_source_valid & main_litedramcore_bankmachine4_source_source_valid)) begin + if ((main_litedramcore_bankmachine4_source_payload_addr[20:7] != main_litedramcore_bankmachine4_source_source_payload_addr[20:7])) begin + main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine4_syncfifo4_din = {main_litedramcore_bankmachine4_fifo_in_last, main_litedramcore_bankmachine4_fifo_in_first, main_litedramcore_bankmachine4_fifo_in_payload_addr, main_litedramcore_bankmachine4_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout; +assign {main_litedramcore_bankmachine4_fifo_out_last, main_litedramcore_bankmachine4_fifo_out_first, main_litedramcore_bankmachine4_fifo_out_payload_addr, main_litedramcore_bankmachine4_fifo_out_payload_we} = main_litedramcore_bankmachine4_syncfifo4_dout; +assign main_litedramcore_bankmachine4_sink_ready = main_litedramcore_bankmachine4_syncfifo4_writable; +assign main_litedramcore_bankmachine4_syncfifo4_we = main_litedramcore_bankmachine4_sink_valid; +assign main_litedramcore_bankmachine4_fifo_in_first = main_litedramcore_bankmachine4_sink_first; +assign main_litedramcore_bankmachine4_fifo_in_last = main_litedramcore_bankmachine4_sink_last; +assign main_litedramcore_bankmachine4_fifo_in_payload_we = main_litedramcore_bankmachine4_sink_payload_we; +assign main_litedramcore_bankmachine4_fifo_in_payload_addr = main_litedramcore_bankmachine4_sink_payload_addr; +assign main_litedramcore_bankmachine4_source_valid = main_litedramcore_bankmachine4_syncfifo4_readable; +assign main_litedramcore_bankmachine4_source_first = main_litedramcore_bankmachine4_fifo_out_first; +assign main_litedramcore_bankmachine4_source_last = main_litedramcore_bankmachine4_fifo_out_last; +assign main_litedramcore_bankmachine4_source_payload_we = main_litedramcore_bankmachine4_fifo_out_payload_we; +assign main_litedramcore_bankmachine4_source_payload_addr = main_litedramcore_bankmachine4_fifo_out_payload_addr; +assign main_litedramcore_bankmachine4_syncfifo4_re = main_litedramcore_bankmachine4_source_ready; +always @(*) begin + main_litedramcore_bankmachine4_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine4_replace) begin + main_litedramcore_bankmachine4_wrport_adr <= (main_litedramcore_bankmachine4_produce - 1'd1); + end else begin + main_litedramcore_bankmachine4_wrport_adr <= main_litedramcore_bankmachine4_produce; + end +end +assign main_litedramcore_bankmachine4_wrport_dat_w = main_litedramcore_bankmachine4_syncfifo4_din; +assign main_litedramcore_bankmachine4_wrport_we = (main_litedramcore_bankmachine4_syncfifo4_we & (main_litedramcore_bankmachine4_syncfifo4_writable | main_litedramcore_bankmachine4_replace)); +assign main_litedramcore_bankmachine4_do_read = (main_litedramcore_bankmachine4_syncfifo4_readable & main_litedramcore_bankmachine4_syncfifo4_re); +assign main_litedramcore_bankmachine4_rdport_adr = main_litedramcore_bankmachine4_consume; +assign main_litedramcore_bankmachine4_syncfifo4_dout = main_litedramcore_bankmachine4_rdport_dat_r; +assign main_litedramcore_bankmachine4_syncfifo4_writable = (main_litedramcore_bankmachine4_level != 5'd16); +assign main_litedramcore_bankmachine4_syncfifo4_readable = (main_litedramcore_bankmachine4_level != 1'd0); +assign main_litedramcore_bankmachine4_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine4_pipe_valid_source_valid) | main_litedramcore_bankmachine4_pipe_valid_source_ready); +assign main_litedramcore_bankmachine4_pipe_valid_sink_valid = main_litedramcore_bankmachine4_sink_sink_valid; +assign main_litedramcore_bankmachine4_sink_sink_ready = main_litedramcore_bankmachine4_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine4_pipe_valid_sink_first = main_litedramcore_bankmachine4_sink_sink_first; +assign main_litedramcore_bankmachine4_pipe_valid_sink_last = main_litedramcore_bankmachine4_sink_sink_last; +assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_we = main_litedramcore_bankmachine4_sink_sink_payload_we; +assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine4_sink_sink_payload_addr; +assign main_litedramcore_bankmachine4_source_source_valid = main_litedramcore_bankmachine4_pipe_valid_source_valid; +assign main_litedramcore_bankmachine4_pipe_valid_source_ready = main_litedramcore_bankmachine4_source_source_ready; +assign main_litedramcore_bankmachine4_source_source_first = main_litedramcore_bankmachine4_pipe_valid_source_first; +assign main_litedramcore_bankmachine4_source_source_last = main_litedramcore_bankmachine4_pipe_valid_source_last; +assign main_litedramcore_bankmachine4_source_source_payload_we = main_litedramcore_bankmachine4_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine4_source_source_payload_addr = main_litedramcore_bankmachine4_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine4_next_state <= 4'd0; + builder_bankmachine4_next_state <= builder_bankmachine4_state; + case (builder_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + if (main_litedramcore_bankmachine4_cmd_ready) begin + builder_bankmachine4_next_state <= 3'd5; + end end end 2'd2: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + builder_bankmachine4_next_state <= 3'd5; + end end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + if (main_litedramcore_bankmachine4_cmd_ready) begin + builder_bankmachine4_next_state <= 3'd7; + end end end 3'd4: begin + if ((~main_litedramcore_bankmachine4_refresh_req)) begin + builder_bankmachine4_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine4_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine4_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine4_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine4_next_state <= 1'd0; end default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + builder_bankmachine4_next_state <= 3'd4; + end else begin + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if ((main_litedramcore_bankmachine4_cmd_ready & main_litedramcore_bankmachine4_auto_precharge)) begin + builder_bankmachine4_next_state <= 2'd2; + end + end else begin + builder_bankmachine4_next_state <= 1'd1; + end + end else begin + builder_bankmachine4_next_state <= 2'd3; + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine3_state) + main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -7014,13 +7609,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_source_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin + main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -7032,139 +7627,38 @@ always @(*) begin end endcase end -assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid; -assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready; -assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we; -assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr; -assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid; -assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready; -assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first; -assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last; -assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we; -assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr; -assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); -assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid); -assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[20:7]); -assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4; -always @(*) begin - litedramcore_bankmachine4_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine4_row_col_n_addr_sel) begin - litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_source_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write); -assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); -assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); -always @(*) begin - litedramcore_bankmachine4_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin - if ((litedramcore_bankmachine4_source_payload_addr[20:7] != litedramcore_bankmachine4_source_source_payload_addr[20:7])) begin - litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we}; -assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; -assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; -assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; -assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; -assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable; -assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid; -assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first; -assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last; -assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we; -assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr; -assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable; -assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first; -assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last; -assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we; -assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr; -assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready; -always @(*) begin - litedramcore_bankmachine4_wrport_adr <= 4'd0; - if (litedramcore_bankmachine4_replace) begin - litedramcore_bankmachine4_wrport_adr <= (litedramcore_bankmachine4_produce - 1'd1); - end else begin - litedramcore_bankmachine4_wrport_adr <= litedramcore_bankmachine4_produce; - end -end -assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din; -assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace)); -assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re); -assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume; -assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r; -assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 5'd16); -assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0); -assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready); -assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid; -assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready; -assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first; -assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last; -assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we; -assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr; -assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid; -assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready; -assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first; -assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last; -assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we; -assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine4_next_state <= 4'd0; - litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - if (litedramcore_bankmachine4_cmd_ready) begin - litedramcore_bankmachine4_next_state <= 3'd5; - end - end +always @(*) begin + main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (builder_bankmachine4_state) + 1'd1: begin end 2'd2: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - if (litedramcore_bankmachine4_cmd_ready) begin - litedramcore_bankmachine4_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~litedramcore_bankmachine4_refresh_req)) begin - litedramcore_bankmachine4_next_state <= 1'd0; - end end 3'd5: begin - litedramcore_bankmachine4_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine4_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine4_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine4_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - litedramcore_bankmachine4_next_state <= 3'd4; + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin - litedramcore_bankmachine4_next_state <= 2'd2; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin + main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready; + end else begin end end else begin - litedramcore_bankmachine4_next_state <= 1'd1; end end else begin - litedramcore_bankmachine4_next_state <= 2'd3; end end end @@ -7172,8 +7666,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7191,14 +7685,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin end else begin - litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; + main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready; end end else begin end @@ -7210,8 +7704,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7219,8 +7713,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine4_twtpcon_ready) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd1; + if (main_litedramcore_bankmachine4_twtpcon_ready) begin + main_litedramcore_bankmachine4_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -7236,15 +7730,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_row_open <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_row_open <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_open <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_row_open <= 1'd1; end end 3'd4: begin @@ -7262,18 +7756,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_valid <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_valid <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; end end 3'd4: begin @@ -7287,12 +7781,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; end else begin end end else begin @@ -7303,18 +7797,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_row_close <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_row_close <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - litedramcore_bankmachine4_row_close <= 1'd1; + main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine4_row_close <= 1'd1; + main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine4_row_close <= 1'd1; + main_litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -7329,15 +7823,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -7355,8 +7849,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7374,12 +7868,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -7390,18 +7884,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -7419,11 +7913,11 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -7441,13 +7935,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -7460,22 +7954,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7490,8 +7984,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7509,14 +8003,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin end else begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; end end else begin end @@ -7527,38 +8021,139 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine4_state) +assign main_litedramcore_bankmachine5_sink_valid = main_litedramcore_bankmachine5_req_valid; +assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_sink_ready; +assign main_litedramcore_bankmachine5_sink_payload_we = main_litedramcore_bankmachine5_req_we; +assign main_litedramcore_bankmachine5_sink_payload_addr = main_litedramcore_bankmachine5_req_addr; +assign main_litedramcore_bankmachine5_sink_sink_valid = main_litedramcore_bankmachine5_source_valid; +assign main_litedramcore_bankmachine5_source_ready = main_litedramcore_bankmachine5_sink_sink_ready; +assign main_litedramcore_bankmachine5_sink_sink_first = main_litedramcore_bankmachine5_source_first; +assign main_litedramcore_bankmachine5_sink_sink_last = main_litedramcore_bankmachine5_source_last; +assign main_litedramcore_bankmachine5_sink_sink_payload_we = main_litedramcore_bankmachine5_source_payload_we; +assign main_litedramcore_bankmachine5_sink_sink_payload_addr = main_litedramcore_bankmachine5_source_payload_addr; +assign main_litedramcore_bankmachine5_source_source_ready = (main_litedramcore_bankmachine5_req_wdata_ready | main_litedramcore_bankmachine5_req_rdata_valid); +assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_source_valid | main_litedramcore_bankmachine5_source_source_valid); +assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_source_source_payload_addr[20:7]); +assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5; +always @(*) begin + main_litedramcore_bankmachine5_cmd_payload_a <= 14'd0; + if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin + main_litedramcore_bankmachine5_cmd_payload_a <= main_litedramcore_bankmachine5_source_source_payload_addr[20:7]; + end else begin + main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write); +assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); +assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); +always @(*) begin + main_litedramcore_bankmachine5_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine5_source_valid & main_litedramcore_bankmachine5_source_source_valid)) begin + if ((main_litedramcore_bankmachine5_source_payload_addr[20:7] != main_litedramcore_bankmachine5_source_source_payload_addr[20:7])) begin + main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine5_syncfifo5_din = {main_litedramcore_bankmachine5_fifo_in_last, main_litedramcore_bankmachine5_fifo_in_first, main_litedramcore_bankmachine5_fifo_in_payload_addr, main_litedramcore_bankmachine5_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout; +assign {main_litedramcore_bankmachine5_fifo_out_last, main_litedramcore_bankmachine5_fifo_out_first, main_litedramcore_bankmachine5_fifo_out_payload_addr, main_litedramcore_bankmachine5_fifo_out_payload_we} = main_litedramcore_bankmachine5_syncfifo5_dout; +assign main_litedramcore_bankmachine5_sink_ready = main_litedramcore_bankmachine5_syncfifo5_writable; +assign main_litedramcore_bankmachine5_syncfifo5_we = main_litedramcore_bankmachine5_sink_valid; +assign main_litedramcore_bankmachine5_fifo_in_first = main_litedramcore_bankmachine5_sink_first; +assign main_litedramcore_bankmachine5_fifo_in_last = main_litedramcore_bankmachine5_sink_last; +assign main_litedramcore_bankmachine5_fifo_in_payload_we = main_litedramcore_bankmachine5_sink_payload_we; +assign main_litedramcore_bankmachine5_fifo_in_payload_addr = main_litedramcore_bankmachine5_sink_payload_addr; +assign main_litedramcore_bankmachine5_source_valid = main_litedramcore_bankmachine5_syncfifo5_readable; +assign main_litedramcore_bankmachine5_source_first = main_litedramcore_bankmachine5_fifo_out_first; +assign main_litedramcore_bankmachine5_source_last = main_litedramcore_bankmachine5_fifo_out_last; +assign main_litedramcore_bankmachine5_source_payload_we = main_litedramcore_bankmachine5_fifo_out_payload_we; +assign main_litedramcore_bankmachine5_source_payload_addr = main_litedramcore_bankmachine5_fifo_out_payload_addr; +assign main_litedramcore_bankmachine5_syncfifo5_re = main_litedramcore_bankmachine5_source_ready; +always @(*) begin + main_litedramcore_bankmachine5_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine5_replace) begin + main_litedramcore_bankmachine5_wrport_adr <= (main_litedramcore_bankmachine5_produce - 1'd1); + end else begin + main_litedramcore_bankmachine5_wrport_adr <= main_litedramcore_bankmachine5_produce; + end +end +assign main_litedramcore_bankmachine5_wrport_dat_w = main_litedramcore_bankmachine5_syncfifo5_din; +assign main_litedramcore_bankmachine5_wrport_we = (main_litedramcore_bankmachine5_syncfifo5_we & (main_litedramcore_bankmachine5_syncfifo5_writable | main_litedramcore_bankmachine5_replace)); +assign main_litedramcore_bankmachine5_do_read = (main_litedramcore_bankmachine5_syncfifo5_readable & main_litedramcore_bankmachine5_syncfifo5_re); +assign main_litedramcore_bankmachine5_rdport_adr = main_litedramcore_bankmachine5_consume; +assign main_litedramcore_bankmachine5_syncfifo5_dout = main_litedramcore_bankmachine5_rdport_dat_r; +assign main_litedramcore_bankmachine5_syncfifo5_writable = (main_litedramcore_bankmachine5_level != 5'd16); +assign main_litedramcore_bankmachine5_syncfifo5_readable = (main_litedramcore_bankmachine5_level != 1'd0); +assign main_litedramcore_bankmachine5_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine5_pipe_valid_source_valid) | main_litedramcore_bankmachine5_pipe_valid_source_ready); +assign main_litedramcore_bankmachine5_pipe_valid_sink_valid = main_litedramcore_bankmachine5_sink_sink_valid; +assign main_litedramcore_bankmachine5_sink_sink_ready = main_litedramcore_bankmachine5_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine5_pipe_valid_sink_first = main_litedramcore_bankmachine5_sink_sink_first; +assign main_litedramcore_bankmachine5_pipe_valid_sink_last = main_litedramcore_bankmachine5_sink_sink_last; +assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_we = main_litedramcore_bankmachine5_sink_sink_payload_we; +assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine5_sink_sink_payload_addr; +assign main_litedramcore_bankmachine5_source_source_valid = main_litedramcore_bankmachine5_pipe_valid_source_valid; +assign main_litedramcore_bankmachine5_pipe_valid_source_ready = main_litedramcore_bankmachine5_source_source_ready; +assign main_litedramcore_bankmachine5_source_source_first = main_litedramcore_bankmachine5_pipe_valid_source_first; +assign main_litedramcore_bankmachine5_source_source_last = main_litedramcore_bankmachine5_pipe_valid_source_last; +assign main_litedramcore_bankmachine5_source_source_payload_we = main_litedramcore_bankmachine5_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine5_source_source_payload_addr = main_litedramcore_bankmachine5_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine5_next_state <= 4'd0; + builder_bankmachine5_next_state <= builder_bankmachine5_state; + case (builder_bankmachine5_state) 1'd1: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + if (main_litedramcore_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + builder_bankmachine5_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + if (main_litedramcore_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine5_refresh_req)) begin + builder_bankmachine5_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine5_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine5_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine5_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine5_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine4_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin + builder_bankmachine5_next_state <= 3'd4; end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; - end else begin + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin + builder_bankmachine5_next_state <= 2'd2; end end else begin + builder_bankmachine5_next_state <= 1'd1; end end else begin + builder_bankmachine5_next_state <= 2'd3; end end end @@ -7566,8 +8161,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine4_state) + main_litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -7575,6 +8170,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine5_twtpcon_ready) begin + main_litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -7585,157 +8183,70 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin - litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine5_row_open <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_row_open <= 1'd1; end end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end endcase end -assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid; -assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready; -assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we; -assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr; -assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid; -assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready; -assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first; -assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last; -assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we; -assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr; -assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); -assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid); -assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[20:7]); -assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5; -always @(*) begin - litedramcore_bankmachine5_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine5_row_col_n_addr_sel) begin - litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_source_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write); -assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); -assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); -always @(*) begin - litedramcore_bankmachine5_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin - if ((litedramcore_bankmachine5_source_payload_addr[20:7] != litedramcore_bankmachine5_source_source_payload_addr[20:7])) begin - litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we}; -assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; -assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; -assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; -assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; -assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable; -assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid; -assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first; -assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last; -assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we; -assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr; -assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable; -assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first; -assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last; -assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we; -assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr; -assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready; -always @(*) begin - litedramcore_bankmachine5_wrport_adr <= 4'd0; - if (litedramcore_bankmachine5_replace) begin - litedramcore_bankmachine5_wrport_adr <= (litedramcore_bankmachine5_produce - 1'd1); - end else begin - litedramcore_bankmachine5_wrport_adr <= litedramcore_bankmachine5_produce; - end -end -assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din; -assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace)); -assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re); -assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume; -assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r; -assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 5'd16); -assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0); -assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready); -assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid; -assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready; -assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first; -assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last; -assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we; -assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr; -assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid; -assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready; -assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first; -assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last; -assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we; -assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine5_next_state <= 4'd0; - litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - if (litedramcore_bankmachine5_cmd_ready) begin - litedramcore_bankmachine5_next_state <= 3'd5; - end +always @(*) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; end end 2'd2: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - if (litedramcore_bankmachine5_cmd_ready) begin - litedramcore_bankmachine5_next_state <= 3'd7; - end + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; end end 3'd4: begin - if ((~litedramcore_bankmachine5_refresh_req)) begin - litedramcore_bankmachine5_next_state <= 1'd0; - end end 3'd5: begin - litedramcore_bankmachine5_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine5_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine5_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine5_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - litedramcore_bankmachine5_next_state <= 3'd4; + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin - litedramcore_bankmachine5_next_state <= 2'd2; - end + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; end else begin - litedramcore_bankmachine5_next_state <= 1'd1; end end else begin - litedramcore_bankmachine5_next_state <= 2'd3; end end end @@ -7743,15 +8254,41 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_row_close <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + main_litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd2: begin + main_litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + main_litedramcore_bankmachine5_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -7769,8 +8306,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -7788,12 +8325,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -7804,18 +8341,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -7833,11 +8370,11 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -7855,13 +8392,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin + main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -7874,22 +8411,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7904,8 +8441,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -7923,14 +8460,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin end else begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; end end else begin end @@ -7942,8 +8479,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -7961,13 +8498,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin + main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -7980,8 +8517,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -7999,13 +8536,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin - litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin + main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready; end else begin end end else begin @@ -8018,8 +8555,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -8037,14 +8574,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine5_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin end else begin - litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; + main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready; end end else begin end @@ -8055,42 +8592,155 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine5_state) +assign main_litedramcore_bankmachine6_sink_valid = main_litedramcore_bankmachine6_req_valid; +assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_sink_ready; +assign main_litedramcore_bankmachine6_sink_payload_we = main_litedramcore_bankmachine6_req_we; +assign main_litedramcore_bankmachine6_sink_payload_addr = main_litedramcore_bankmachine6_req_addr; +assign main_litedramcore_bankmachine6_sink_sink_valid = main_litedramcore_bankmachine6_source_valid; +assign main_litedramcore_bankmachine6_source_ready = main_litedramcore_bankmachine6_sink_sink_ready; +assign main_litedramcore_bankmachine6_sink_sink_first = main_litedramcore_bankmachine6_source_first; +assign main_litedramcore_bankmachine6_sink_sink_last = main_litedramcore_bankmachine6_source_last; +assign main_litedramcore_bankmachine6_sink_sink_payload_we = main_litedramcore_bankmachine6_source_payload_we; +assign main_litedramcore_bankmachine6_sink_sink_payload_addr = main_litedramcore_bankmachine6_source_payload_addr; +assign main_litedramcore_bankmachine6_source_source_ready = (main_litedramcore_bankmachine6_req_wdata_ready | main_litedramcore_bankmachine6_req_rdata_valid); +assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_source_valid | main_litedramcore_bankmachine6_source_source_valid); +assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_source_source_payload_addr[20:7]); +assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; +always @(*) begin + main_litedramcore_bankmachine6_cmd_payload_a <= 14'd0; + if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin + main_litedramcore_bankmachine6_cmd_payload_a <= main_litedramcore_bankmachine6_source_source_payload_addr[20:7]; + end else begin + main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write); +assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); +assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); +always @(*) begin + main_litedramcore_bankmachine6_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine6_source_valid & main_litedramcore_bankmachine6_source_source_valid)) begin + if ((main_litedramcore_bankmachine6_source_payload_addr[20:7] != main_litedramcore_bankmachine6_source_source_payload_addr[20:7])) begin + main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine6_syncfifo6_din = {main_litedramcore_bankmachine6_fifo_in_last, main_litedramcore_bankmachine6_fifo_in_first, main_litedramcore_bankmachine6_fifo_in_payload_addr, main_litedramcore_bankmachine6_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout; +assign {main_litedramcore_bankmachine6_fifo_out_last, main_litedramcore_bankmachine6_fifo_out_first, main_litedramcore_bankmachine6_fifo_out_payload_addr, main_litedramcore_bankmachine6_fifo_out_payload_we} = main_litedramcore_bankmachine6_syncfifo6_dout; +assign main_litedramcore_bankmachine6_sink_ready = main_litedramcore_bankmachine6_syncfifo6_writable; +assign main_litedramcore_bankmachine6_syncfifo6_we = main_litedramcore_bankmachine6_sink_valid; +assign main_litedramcore_bankmachine6_fifo_in_first = main_litedramcore_bankmachine6_sink_first; +assign main_litedramcore_bankmachine6_fifo_in_last = main_litedramcore_bankmachine6_sink_last; +assign main_litedramcore_bankmachine6_fifo_in_payload_we = main_litedramcore_bankmachine6_sink_payload_we; +assign main_litedramcore_bankmachine6_fifo_in_payload_addr = main_litedramcore_bankmachine6_sink_payload_addr; +assign main_litedramcore_bankmachine6_source_valid = main_litedramcore_bankmachine6_syncfifo6_readable; +assign main_litedramcore_bankmachine6_source_first = main_litedramcore_bankmachine6_fifo_out_first; +assign main_litedramcore_bankmachine6_source_last = main_litedramcore_bankmachine6_fifo_out_last; +assign main_litedramcore_bankmachine6_source_payload_we = main_litedramcore_bankmachine6_fifo_out_payload_we; +assign main_litedramcore_bankmachine6_source_payload_addr = main_litedramcore_bankmachine6_fifo_out_payload_addr; +assign main_litedramcore_bankmachine6_syncfifo6_re = main_litedramcore_bankmachine6_source_ready; +always @(*) begin + main_litedramcore_bankmachine6_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine6_replace) begin + main_litedramcore_bankmachine6_wrport_adr <= (main_litedramcore_bankmachine6_produce - 1'd1); + end else begin + main_litedramcore_bankmachine6_wrport_adr <= main_litedramcore_bankmachine6_produce; + end +end +assign main_litedramcore_bankmachine6_wrport_dat_w = main_litedramcore_bankmachine6_syncfifo6_din; +assign main_litedramcore_bankmachine6_wrport_we = (main_litedramcore_bankmachine6_syncfifo6_we & (main_litedramcore_bankmachine6_syncfifo6_writable | main_litedramcore_bankmachine6_replace)); +assign main_litedramcore_bankmachine6_do_read = (main_litedramcore_bankmachine6_syncfifo6_readable & main_litedramcore_bankmachine6_syncfifo6_re); +assign main_litedramcore_bankmachine6_rdport_adr = main_litedramcore_bankmachine6_consume; +assign main_litedramcore_bankmachine6_syncfifo6_dout = main_litedramcore_bankmachine6_rdport_dat_r; +assign main_litedramcore_bankmachine6_syncfifo6_writable = (main_litedramcore_bankmachine6_level != 5'd16); +assign main_litedramcore_bankmachine6_syncfifo6_readable = (main_litedramcore_bankmachine6_level != 1'd0); +assign main_litedramcore_bankmachine6_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine6_pipe_valid_source_valid) | main_litedramcore_bankmachine6_pipe_valid_source_ready); +assign main_litedramcore_bankmachine6_pipe_valid_sink_valid = main_litedramcore_bankmachine6_sink_sink_valid; +assign main_litedramcore_bankmachine6_sink_sink_ready = main_litedramcore_bankmachine6_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine6_pipe_valid_sink_first = main_litedramcore_bankmachine6_sink_sink_first; +assign main_litedramcore_bankmachine6_pipe_valid_sink_last = main_litedramcore_bankmachine6_sink_sink_last; +assign main_litedramcore_bankmachine6_pipe_valid_sink_payload_we = main_litedramcore_bankmachine6_sink_sink_payload_we; +assign main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine6_sink_sink_payload_addr; +assign main_litedramcore_bankmachine6_source_source_valid = main_litedramcore_bankmachine6_pipe_valid_source_valid; +assign main_litedramcore_bankmachine6_pipe_valid_source_ready = main_litedramcore_bankmachine6_source_source_ready; +assign main_litedramcore_bankmachine6_source_source_first = main_litedramcore_bankmachine6_pipe_valid_source_first; +assign main_litedramcore_bankmachine6_source_source_last = main_litedramcore_bankmachine6_pipe_valid_source_last; +assign main_litedramcore_bankmachine6_source_source_payload_we = main_litedramcore_bankmachine6_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine6_source_source_payload_addr = main_litedramcore_bankmachine6_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine6_next_state <= 4'd0; + builder_bankmachine6_next_state <= builder_bankmachine6_state; + case (builder_bankmachine6_state) 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + if (main_litedramcore_bankmachine6_cmd_ready) begin + builder_bankmachine6_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + builder_bankmachine6_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + if (main_litedramcore_bankmachine6_cmd_ready) begin + builder_bankmachine6_next_state <= 3'd7; + end + end end 3'd4: begin - if (litedramcore_bankmachine5_twtpcon_ready) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd1; + if ((~main_litedramcore_bankmachine6_refresh_req)) begin + builder_bankmachine6_next_state <= 1'd0; end end 3'd5: begin + builder_bankmachine6_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine6_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine6_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine6_next_state <= 1'd0; end default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + builder_bankmachine6_next_state <= 3'd4; + end else begin + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if ((main_litedramcore_bankmachine6_cmd_ready & main_litedramcore_bankmachine6_auto_precharge)) begin + builder_bankmachine6_next_state <= 2'd2; + end + end else begin + builder_bankmachine6_next_state <= 1'd1; + end + end else begin + builder_bankmachine6_next_state <= 2'd3; + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine5_row_open <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_open <= 1'd1; + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -8108,19 +8758,13 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_cmd_valid <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -8133,12 +8777,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -8149,18 +8793,21 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_row_close <= 1'd0; - case (litedramcore_bankmachine5_state) + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - litedramcore_bankmachine5_row_close <= 1'd1; + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 2'd2: begin - litedramcore_bankmachine5_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 3'd4: begin - litedramcore_bankmachine5_row_close <= 1'd1; end 3'd5: begin end @@ -8174,139 +8821,41 @@ always @(*) begin end endcase end -assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid; -assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready; -assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we; -assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr; -assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid; -assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready; -assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first; -assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last; -assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we; -assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr; -assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); -assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid); -assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[20:7]); -assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6; -always @(*) begin - litedramcore_bankmachine6_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine6_row_col_n_addr_sel) begin - litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_source_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write); -assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); -assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); -always @(*) begin - litedramcore_bankmachine6_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin - if ((litedramcore_bankmachine6_source_payload_addr[20:7] != litedramcore_bankmachine6_source_source_payload_addr[20:7])) begin - litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we}; -assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; -assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; -assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; -assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; -assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable; -assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid; -assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first; -assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last; -assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we; -assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr; -assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable; -assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first; -assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last; -assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we; -assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr; -assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready; -always @(*) begin - litedramcore_bankmachine6_wrport_adr <= 4'd0; - if (litedramcore_bankmachine6_replace) begin - litedramcore_bankmachine6_wrport_adr <= (litedramcore_bankmachine6_produce - 1'd1); - end else begin - litedramcore_bankmachine6_wrport_adr <= litedramcore_bankmachine6_produce; - end -end -assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din; -assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace)); -assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re); -assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume; -assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r; -assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 5'd16); -assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0); -assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready); -assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid; -assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready; -assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first; -assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last; -assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we; -assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr; -assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid; -assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready; -assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first; -assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last; -assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we; -assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine6_next_state <= 4'd0; - litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - if (litedramcore_bankmachine6_cmd_ready) begin - litedramcore_bankmachine6_next_state <= 3'd5; - end +always @(*) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; end end 2'd2: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - if (litedramcore_bankmachine6_cmd_ready) begin - litedramcore_bankmachine6_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~litedramcore_bankmachine6_refresh_req)) begin - litedramcore_bankmachine6_next_state <= 1'd0; - end end 3'd5: begin - litedramcore_bankmachine6_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine6_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine6_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine6_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - litedramcore_bankmachine6_next_state <= 3'd4; + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin - litedramcore_bankmachine6_next_state <= 2'd2; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end else begin end end else begin - litedramcore_bankmachine6_next_state <= 1'd1; end end else begin - litedramcore_bankmachine6_next_state <= 2'd3; end end end @@ -8314,56 +8863,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8378,12 +8893,9 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -8400,14 +8912,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin end else begin + main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; end end else begin end @@ -8419,38 +8931,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8468,14 +8950,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin + main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; end else begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; end end else begin end @@ -8487,8 +8969,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8506,13 +8988,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin + main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready; end else begin end end else begin @@ -8525,8 +9007,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8544,14 +9026,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin + if (main_litedramcore_bankmachine6_refresh_req) begin end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin - litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin end else begin + main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready; end end else begin end @@ -8563,8 +9045,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -8572,6 +9054,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine6_twtpcon_ready) begin + main_litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -8582,37 +9067,22 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_source_source_payload_we) begin - end else begin - litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_row_open <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_open <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine6_twtpcon_ready) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -8627,15 +9097,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_row_open <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_cmd_valid <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_open <= 1'd1; + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; end end 3'd4: begin @@ -8649,25 +9122,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine6_cmd_valid <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine6_row_close <= 1'd0; + case (builder_bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end + main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 3'd4: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -8678,57 +9160,161 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_source_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end -always @(*) begin - litedramcore_bankmachine6_row_close <= 1'd0; - case (litedramcore_bankmachine6_state) +assign main_litedramcore_bankmachine7_sink_valid = main_litedramcore_bankmachine7_req_valid; +assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_sink_ready; +assign main_litedramcore_bankmachine7_sink_payload_we = main_litedramcore_bankmachine7_req_we; +assign main_litedramcore_bankmachine7_sink_payload_addr = main_litedramcore_bankmachine7_req_addr; +assign main_litedramcore_bankmachine7_sink_sink_valid = main_litedramcore_bankmachine7_source_valid; +assign main_litedramcore_bankmachine7_source_ready = main_litedramcore_bankmachine7_sink_sink_ready; +assign main_litedramcore_bankmachine7_sink_sink_first = main_litedramcore_bankmachine7_source_first; +assign main_litedramcore_bankmachine7_sink_sink_last = main_litedramcore_bankmachine7_source_last; +assign main_litedramcore_bankmachine7_sink_sink_payload_we = main_litedramcore_bankmachine7_source_payload_we; +assign main_litedramcore_bankmachine7_sink_sink_payload_addr = main_litedramcore_bankmachine7_source_payload_addr; +assign main_litedramcore_bankmachine7_source_source_ready = (main_litedramcore_bankmachine7_req_wdata_ready | main_litedramcore_bankmachine7_req_rdata_valid); +assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_source_valid | main_litedramcore_bankmachine7_source_source_valid); +assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_source_source_payload_addr[20:7]); +assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7; +always @(*) begin + main_litedramcore_bankmachine7_cmd_payload_a <= 14'd0; + if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin + main_litedramcore_bankmachine7_cmd_payload_a <= main_litedramcore_bankmachine7_source_source_payload_addr[20:7]; + end else begin + main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write); +assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); +assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); +always @(*) begin + main_litedramcore_bankmachine7_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine7_source_valid & main_litedramcore_bankmachine7_source_source_valid)) begin + if ((main_litedramcore_bankmachine7_source_payload_addr[20:7] != main_litedramcore_bankmachine7_source_source_payload_addr[20:7])) begin + main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine7_syncfifo7_din = {main_litedramcore_bankmachine7_fifo_in_last, main_litedramcore_bankmachine7_fifo_in_first, main_litedramcore_bankmachine7_fifo_in_payload_addr, main_litedramcore_bankmachine7_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout; +assign {main_litedramcore_bankmachine7_fifo_out_last, main_litedramcore_bankmachine7_fifo_out_first, main_litedramcore_bankmachine7_fifo_out_payload_addr, main_litedramcore_bankmachine7_fifo_out_payload_we} = main_litedramcore_bankmachine7_syncfifo7_dout; +assign main_litedramcore_bankmachine7_sink_ready = main_litedramcore_bankmachine7_syncfifo7_writable; +assign main_litedramcore_bankmachine7_syncfifo7_we = main_litedramcore_bankmachine7_sink_valid; +assign main_litedramcore_bankmachine7_fifo_in_first = main_litedramcore_bankmachine7_sink_first; +assign main_litedramcore_bankmachine7_fifo_in_last = main_litedramcore_bankmachine7_sink_last; +assign main_litedramcore_bankmachine7_fifo_in_payload_we = main_litedramcore_bankmachine7_sink_payload_we; +assign main_litedramcore_bankmachine7_fifo_in_payload_addr = main_litedramcore_bankmachine7_sink_payload_addr; +assign main_litedramcore_bankmachine7_source_valid = main_litedramcore_bankmachine7_syncfifo7_readable; +assign main_litedramcore_bankmachine7_source_first = main_litedramcore_bankmachine7_fifo_out_first; +assign main_litedramcore_bankmachine7_source_last = main_litedramcore_bankmachine7_fifo_out_last; +assign main_litedramcore_bankmachine7_source_payload_we = main_litedramcore_bankmachine7_fifo_out_payload_we; +assign main_litedramcore_bankmachine7_source_payload_addr = main_litedramcore_bankmachine7_fifo_out_payload_addr; +assign main_litedramcore_bankmachine7_syncfifo7_re = main_litedramcore_bankmachine7_source_ready; +always @(*) begin + main_litedramcore_bankmachine7_wrport_adr <= 4'd0; + if (main_litedramcore_bankmachine7_replace) begin + main_litedramcore_bankmachine7_wrport_adr <= (main_litedramcore_bankmachine7_produce - 1'd1); + end else begin + main_litedramcore_bankmachine7_wrport_adr <= main_litedramcore_bankmachine7_produce; + end +end +assign main_litedramcore_bankmachine7_wrport_dat_w = main_litedramcore_bankmachine7_syncfifo7_din; +assign main_litedramcore_bankmachine7_wrport_we = (main_litedramcore_bankmachine7_syncfifo7_we & (main_litedramcore_bankmachine7_syncfifo7_writable | main_litedramcore_bankmachine7_replace)); +assign main_litedramcore_bankmachine7_do_read = (main_litedramcore_bankmachine7_syncfifo7_readable & main_litedramcore_bankmachine7_syncfifo7_re); +assign main_litedramcore_bankmachine7_rdport_adr = main_litedramcore_bankmachine7_consume; +assign main_litedramcore_bankmachine7_syncfifo7_dout = main_litedramcore_bankmachine7_rdport_dat_r; +assign main_litedramcore_bankmachine7_syncfifo7_writable = (main_litedramcore_bankmachine7_level != 5'd16); +assign main_litedramcore_bankmachine7_syncfifo7_readable = (main_litedramcore_bankmachine7_level != 1'd0); +assign main_litedramcore_bankmachine7_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine7_pipe_valid_source_valid) | main_litedramcore_bankmachine7_pipe_valid_source_ready); +assign main_litedramcore_bankmachine7_pipe_valid_sink_valid = main_litedramcore_bankmachine7_sink_sink_valid; +assign main_litedramcore_bankmachine7_sink_sink_ready = main_litedramcore_bankmachine7_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine7_pipe_valid_sink_first = main_litedramcore_bankmachine7_sink_sink_first; +assign main_litedramcore_bankmachine7_pipe_valid_sink_last = main_litedramcore_bankmachine7_sink_sink_last; +assign main_litedramcore_bankmachine7_pipe_valid_sink_payload_we = main_litedramcore_bankmachine7_sink_sink_payload_we; +assign main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine7_sink_sink_payload_addr; +assign main_litedramcore_bankmachine7_source_source_valid = main_litedramcore_bankmachine7_pipe_valid_source_valid; +assign main_litedramcore_bankmachine7_pipe_valid_source_ready = main_litedramcore_bankmachine7_source_source_ready; +assign main_litedramcore_bankmachine7_source_source_first = main_litedramcore_bankmachine7_pipe_valid_source_first; +assign main_litedramcore_bankmachine7_source_source_last = main_litedramcore_bankmachine7_pipe_valid_source_last; +assign main_litedramcore_bankmachine7_source_source_payload_we = main_litedramcore_bankmachine7_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine7_source_source_payload_addr = main_litedramcore_bankmachine7_pipe_valid_source_payload_addr; +always @(*) begin + builder_bankmachine7_next_state <= 4'd0; + builder_bankmachine7_next_state <= builder_bankmachine7_state; + case (builder_bankmachine7_state) 1'd1: begin - litedramcore_bankmachine6_row_close <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + if (main_litedramcore_bankmachine7_cmd_ready) begin + builder_bankmachine7_next_state <= 3'd5; + end + end end 2'd2: begin - litedramcore_bankmachine6_row_close <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + builder_bankmachine7_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + if (main_litedramcore_bankmachine7_cmd_ready) begin + builder_bankmachine7_next_state <= 3'd7; + end + end end 3'd4: begin - litedramcore_bankmachine6_row_close <= 1'd1; + if ((~main_litedramcore_bankmachine7_refresh_req)) begin + builder_bankmachine7_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine7_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine7_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine7_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine7_next_state <= 1'd0; end default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + builder_bankmachine7_next_state <= 3'd4; + end else begin + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if ((main_litedramcore_bankmachine7_cmd_ready & main_litedramcore_bankmachine7_auto_precharge)) begin + builder_bankmachine7_next_state <= 2'd2; + end + end else begin + builder_bankmachine7_next_state <= 1'd1; + end + end else begin + builder_bankmachine7_next_state <= 2'd3; + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine6_state) + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -8745,139 +9331,41 @@ always @(*) begin end endcase end -assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid; -assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready; -assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we; -assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr; -assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid; -assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready; -assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first; -assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last; -assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we; -assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr; -assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); -assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid); -assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[20:7]); -assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7; -always @(*) begin - litedramcore_bankmachine7_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine7_row_col_n_addr_sel) begin - litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_source_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write); -assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); -assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); -always @(*) begin - litedramcore_bankmachine7_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin - if ((litedramcore_bankmachine7_source_payload_addr[20:7] != litedramcore_bankmachine7_source_source_payload_addr[20:7])) begin - litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we}; -assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; -assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; -assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; -assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; -assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable; -assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid; -assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first; -assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last; -assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we; -assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr; -assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable; -assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first; -assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last; -assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we; -assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr; -assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready; -always @(*) begin - litedramcore_bankmachine7_wrport_adr <= 4'd0; - if (litedramcore_bankmachine7_replace) begin - litedramcore_bankmachine7_wrport_adr <= (litedramcore_bankmachine7_produce - 1'd1); - end else begin - litedramcore_bankmachine7_wrport_adr <= litedramcore_bankmachine7_produce; - end -end -assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din; -assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace)); -assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re); -assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume; -assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r; -assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 5'd16); -assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0); -assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready); -assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid; -assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready; -assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first; -assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last; -assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we; -assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr; -assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid; -assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready; -assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first; -assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last; -assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we; -assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr; -always @(*) begin - litedramcore_bankmachine7_next_state <= 4'd0; - litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - if (litedramcore_bankmachine7_cmd_ready) begin - litedramcore_bankmachine7_next_state <= 3'd5; - end +always @(*) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end end 2'd2: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_next_state <= 3'd5; - end end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - if (litedramcore_bankmachine7_cmd_ready) begin - litedramcore_bankmachine7_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~litedramcore_bankmachine7_refresh_req)) begin - litedramcore_bankmachine7_next_state <= 1'd0; - end end 3'd5: begin - litedramcore_bankmachine7_next_state <= 3'd6; end 3'd6: begin - litedramcore_bankmachine7_next_state <= 2'd3; end 3'd7: begin - litedramcore_bankmachine7_next_state <= 4'd8; end 4'd8: begin - litedramcore_bankmachine7_next_state <= 1'd0; end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - litedramcore_bankmachine7_next_state <= 3'd4; + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin - litedramcore_bankmachine7_next_state <= 2'd2; + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin end end else begin - litedramcore_bankmachine7_next_state <= 1'd1; end end else begin - litedramcore_bankmachine7_next_state <= 2'd3; end end end @@ -8885,22 +9373,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8915,8 +9403,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -8934,14 +9422,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin end else begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; end end else begin end @@ -8953,8 +9441,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -8972,13 +9460,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -8991,8 +9479,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -9010,13 +9498,13 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin - litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin + main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready; end else begin end end else begin @@ -9029,8 +9517,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -9048,14 +9536,14 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin end else begin - litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; + main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready; end end else begin end @@ -9067,8 +9555,8 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -9076,8 +9564,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine7_twtpcon_ready) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd1; + if (main_litedramcore_bankmachine7_twtpcon_ready) begin + main_litedramcore_bankmachine7_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -9093,15 +9581,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_row_open <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_row_open <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_open <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_row_open <= 1'd1; end end 3'd4: begin @@ -9119,18 +9607,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_valid <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; end end 3'd4: begin @@ -9144,12 +9632,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; end else begin end end else begin @@ -9160,67 +9648,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_row_close <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_row_close <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -9231,34 +9670,19 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -9276,12 +9700,9 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine7_state) + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (builder_bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -9298,15 +9719,12 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin + if (main_litedramcore_bankmachine7_refresh_req) begin end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_source_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end else begin - end + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -9316,266 +9734,266 @@ always @(*) begin end endcase end -assign litedramcore_rdcmdphase = (a7ddrphy_rdphase_storage - 1'd1); -assign litedramcore_wrcmdphase = (a7ddrphy_wrphase_storage - 1'd1); -assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); -assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); -assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready); -assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read)); -assign litedramcore_cas_allowed = litedramcore_tccdcon_ready; -assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); -assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read)); -assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write)); -assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0); -assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0); -assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid; -assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid; -assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt); -assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata}; -assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; -assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; -assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; -assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; -assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); -assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); -assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); -assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); +assign main_litedramcore_nphases = (main_a7ddrphy_rdphase_storage - 1'd1); +assign main_litedramcore_rdphase = (main_a7ddrphy_wrphase_storage - 1'd1); +assign main_litedramcore_trrdcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))); +assign main_litedramcore_tfawcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))); +assign main_litedramcore_ras_allowed = (main_litedramcore_trrdcon_ready & main_litedramcore_tfawcon_ready); +assign main_litedramcore_tccdcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_cmd_payload_is_write | main_litedramcore_choose_req_cmd_payload_is_read)); +assign main_litedramcore_cas_allowed = main_litedramcore_tccdcon_ready; +assign main_litedramcore_twtrcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); +assign main_litedramcore_read_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_read) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_read)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_read)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_read)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_read)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_read)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_read)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_read)); +assign main_litedramcore_write_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_write) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_write)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_write)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_write)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_write)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_write)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_write)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_write)); +assign main_litedramcore_max_time0 = (main_litedramcore_time0 == 1'd0); +assign main_litedramcore_max_time1 = (main_litedramcore_time1 == 1'd0); +assign main_litedramcore_bankmachine0_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine1_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine2_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine3_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine4_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine5_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine6_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_bankmachine7_refresh_req = main_litedramcore_cmd_valid; +assign main_litedramcore_go_to_refresh = (((((((main_litedramcore_bankmachine0_refresh_gnt & main_litedramcore_bankmachine1_refresh_gnt) & main_litedramcore_bankmachine2_refresh_gnt) & main_litedramcore_bankmachine3_refresh_gnt) & main_litedramcore_bankmachine4_refresh_gnt) & main_litedramcore_bankmachine5_refresh_gnt) & main_litedramcore_bankmachine6_refresh_gnt) & main_litedramcore_bankmachine7_refresh_gnt); +assign main_litedramcore_interface_rdata = {main_litedramcore_dfi_p3_rddata, main_litedramcore_dfi_p2_rddata, main_litedramcore_dfi_p1_rddata, main_litedramcore_dfi_p0_rddata}; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata; +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); +assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); always @(*) begin - litedramcore_choose_cmd_valids <= 8'd0; - litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids <= 8'd0; + main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); + main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); end -assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; -assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0; -assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1; -assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2; -assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; -assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; -assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; +assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids; +assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_self0; +assign main_litedramcore_choose_cmd_cmd_payload_a = builder_rhs_self1; +assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_self2; +assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_self3; +assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_self4; +assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_self5; always @(*) begin - litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; + main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_self0; end end always @(*) begin - litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; + main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_self1; end end always @(*) begin - litedramcore_choose_cmd_cmd_payload_we <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; + main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0; + if (main_litedramcore_choose_cmd_cmd_valid) begin + main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_self2; end end always @(*) begin - litedramcore_bankmachine0_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin - litedramcore_bankmachine0_cmd_ready <= 1'd1; + main_litedramcore_bankmachine0_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin + main_litedramcore_bankmachine0_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin - litedramcore_bankmachine0_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin + main_litedramcore_bankmachine0_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine1_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin - litedramcore_bankmachine1_cmd_ready <= 1'd1; + main_litedramcore_bankmachine1_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin + main_litedramcore_bankmachine1_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin - litedramcore_bankmachine1_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin + main_litedramcore_bankmachine1_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine2_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin - litedramcore_bankmachine2_cmd_ready <= 1'd1; + main_litedramcore_bankmachine2_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin + main_litedramcore_bankmachine2_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin - litedramcore_bankmachine2_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin + main_litedramcore_bankmachine2_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine3_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin - litedramcore_bankmachine3_cmd_ready <= 1'd1; + main_litedramcore_bankmachine3_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin + main_litedramcore_bankmachine3_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin - litedramcore_bankmachine3_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin + main_litedramcore_bankmachine3_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine4_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin - litedramcore_bankmachine4_cmd_ready <= 1'd1; + main_litedramcore_bankmachine4_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin + main_litedramcore_bankmachine4_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin - litedramcore_bankmachine4_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin + main_litedramcore_bankmachine4_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine5_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin - litedramcore_bankmachine5_cmd_ready <= 1'd1; + main_litedramcore_bankmachine5_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin + main_litedramcore_bankmachine5_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin - litedramcore_bankmachine5_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin + main_litedramcore_bankmachine5_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine6_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin - litedramcore_bankmachine6_cmd_ready <= 1'd1; + main_litedramcore_bankmachine6_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin + main_litedramcore_bankmachine6_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin - litedramcore_bankmachine6_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin + main_litedramcore_bankmachine6_cmd_ready <= 1'd1; end end always @(*) begin - litedramcore_bankmachine7_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin - litedramcore_bankmachine7_cmd_ready <= 1'd1; + main_litedramcore_bankmachine7_cmd_ready <= 1'd0; + if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin + main_litedramcore_bankmachine7_cmd_ready <= 1'd1; end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin - litedramcore_bankmachine7_cmd_ready <= 1'd1; + if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin + main_litedramcore_bankmachine7_cmd_ready <= 1'd1; end end -assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid)); +assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid)); always @(*) begin - litedramcore_choose_req_valids <= 8'd0; - litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids <= 8'd0; + main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); + main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); end -assign litedramcore_choose_req_request = litedramcore_choose_req_valids; -assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6; -assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7; -assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8; -assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9; -assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; -assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; +assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids; +assign main_litedramcore_choose_req_cmd_valid = builder_rhs_self6; +assign main_litedramcore_choose_req_cmd_payload_a = builder_rhs_self7; +assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_self8; +assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_self9; +assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_self10; +assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_self11; always @(*) begin - litedramcore_choose_req_cmd_payload_cas <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; + main_litedramcore_choose_req_cmd_payload_cas <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_cas <= builder_t_self3; end end always @(*) begin - litedramcore_choose_req_cmd_payload_ras <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; + main_litedramcore_choose_req_cmd_payload_ras <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_ras <= builder_t_self4; end end always @(*) begin - litedramcore_choose_req_cmd_payload_we <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; + main_litedramcore_choose_req_cmd_payload_we <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_we <= builder_t_self5; end end -assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); -assign litedramcore_dfi_p0_reset_n = 1'd1; -assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}}; -assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}}; -assign litedramcore_dfi_p1_reset_n = 1'd1; -assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}}; -assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}}; -assign litedramcore_dfi_p2_reset_n = 1'd1; -assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}}; -assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}}; -assign litedramcore_dfi_p3_reset_n = 1'd1; -assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}}; -assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}}; -assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]); +assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid)); +assign main_litedramcore_dfi_p0_reset_n = 1'd1; +assign main_litedramcore_dfi_p0_cke = {1{main_litedramcore_steerer4}}; +assign main_litedramcore_dfi_p0_odt = {1{main_litedramcore_steerer5}}; +assign main_litedramcore_dfi_p1_reset_n = 1'd1; +assign main_litedramcore_dfi_p1_cke = {1{main_litedramcore_steerer6}}; +assign main_litedramcore_dfi_p1_odt = {1{main_litedramcore_steerer7}}; +assign main_litedramcore_dfi_p2_reset_n = 1'd1; +assign main_litedramcore_dfi_p2_cke = {1{main_litedramcore_steerer8}}; +assign main_litedramcore_dfi_p2_odt = {1{main_litedramcore_steerer9}}; +assign main_litedramcore_dfi_p3_reset_n = 1'd1; +assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer10}}; +assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer11}}; +assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]); always @(*) begin - litedramcore_multiplexer_next_state <= 4'd0; - litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state; - case (litedramcore_multiplexer_state) + builder_multiplexer_next_state <= 4'd0; + builder_multiplexer_next_state <= builder_multiplexer_state; + case (builder_multiplexer_state) 1'd1: begin - if (litedramcore_read_available) begin - if (((~litedramcore_write_available) | litedramcore_max_time1)) begin - litedramcore_multiplexer_next_state <= 2'd3; + if (main_litedramcore_read_available) begin + if (((~main_litedramcore_write_available) | main_litedramcore_max_time1)) begin + builder_multiplexer_next_state <= 2'd3; end end - if (litedramcore_go_to_refresh) begin - litedramcore_multiplexer_next_state <= 2'd2; + if (main_litedramcore_go_to_refresh) begin + builder_multiplexer_next_state <= 2'd2; end end 2'd2: begin - if (litedramcore_cmd_last) begin - litedramcore_multiplexer_next_state <= 1'd0; + if (main_litedramcore_cmd_last) begin + builder_multiplexer_next_state <= 1'd0; end end 2'd3: begin - if (litedramcore_twtrcon_ready) begin - litedramcore_multiplexer_next_state <= 1'd0; + if (main_litedramcore_twtrcon_ready) begin + builder_multiplexer_next_state <= 1'd0; end end 3'd4: begin - litedramcore_multiplexer_next_state <= 3'd5; + builder_multiplexer_next_state <= 3'd5; end 3'd5: begin - litedramcore_multiplexer_next_state <= 3'd6; + builder_multiplexer_next_state <= 3'd6; end 3'd6: begin - litedramcore_multiplexer_next_state <= 3'd7; + builder_multiplexer_next_state <= 3'd7; end 3'd7: begin - litedramcore_multiplexer_next_state <= 4'd8; + builder_multiplexer_next_state <= 4'd8; end 4'd8: begin - litedramcore_multiplexer_next_state <= 4'd9; + builder_multiplexer_next_state <= 4'd9; end 4'd9: begin - litedramcore_multiplexer_next_state <= 4'd10; + builder_multiplexer_next_state <= 4'd10; end 4'd10: begin - litedramcore_multiplexer_next_state <= 1'd1; + builder_multiplexer_next_state <= 1'd1; end default: begin - if (litedramcore_write_available) begin - if (((~litedramcore_read_available) | litedramcore_max_time0)) begin - litedramcore_multiplexer_next_state <= 3'd4; + if (main_litedramcore_write_available) begin + if (((~main_litedramcore_read_available) | main_litedramcore_max_time0)) begin + builder_multiplexer_next_state <= 3'd4; end end - if (litedramcore_go_to_refresh) begin - litedramcore_multiplexer_next_state <= 2'd2; + if (main_litedramcore_go_to_refresh) begin + builder_multiplexer_next_state <= 2'd2; end end endcase end always @(*) begin - litedramcore_steerer_sel0 <= 2'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_steerer0 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_steerer_sel0 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 1'd0)) begin - litedramcore_steerer_sel0 <= 2'd2; + main_litedramcore_steerer0 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 1'd0)) begin + main_litedramcore_steerer0 <= 2'd2; end - if ((litedramcore_wrcmdphase == 1'd0)) begin - litedramcore_steerer_sel0 <= 1'd1; + if ((main_litedramcore_rdphase == 1'd0)) begin + main_litedramcore_steerer0 <= 1'd1; end end 2'd2: begin - litedramcore_steerer_sel0 <= 2'd3; + main_litedramcore_steerer0 <= 2'd3; end 2'd3: begin end @@ -9594,23 +10012,23 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel0 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 1'd0)) begin - litedramcore_steerer_sel0 <= 2'd2; + main_litedramcore_steerer0 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 1'd0)) begin + main_litedramcore_steerer0 <= 2'd2; end - if ((litedramcore_rdcmdphase == 1'd0)) begin - litedramcore_steerer_sel0 <= 1'd1; + if ((main_litedramcore_nphases == 1'd0)) begin + main_litedramcore_steerer0 <= 1'd1; end end endcase end always @(*) begin - litedramcore_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_cmd_ready <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin end 2'd2: begin - litedramcore_cmd_ready <= 1'd1; + main_litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -9633,15 +10051,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_steerer_sel1 <= 2'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_steerer1 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_steerer_sel1 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 1'd1)) begin - litedramcore_steerer_sel1 <= 2'd2; + main_litedramcore_steerer1 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin + main_litedramcore_steerer1 <= 2'd2; end - if ((litedramcore_wrcmdphase == 1'd1)) begin - litedramcore_steerer_sel1 <= 1'd1; + if ((main_litedramcore_rdphase == 1'd1)) begin + main_litedramcore_steerer1 <= 1'd1; end end 2'd2: begin @@ -9663,26 +10081,26 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel1 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 1'd1)) begin - litedramcore_steerer_sel1 <= 2'd2; + main_litedramcore_steerer1 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin + main_litedramcore_steerer1 <= 2'd2; end - if ((litedramcore_rdcmdphase == 1'd1)) begin - litedramcore_steerer_sel1 <= 1'd1; + if ((main_litedramcore_nphases == 1'd1)) begin + main_litedramcore_steerer1 <= 1'd1; end end endcase end always @(*) begin - litedramcore_steerer_sel2 <= 2'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_steerer2 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_steerer_sel2 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 2'd2)) begin - litedramcore_steerer_sel2 <= 2'd2; + main_litedramcore_steerer2 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 2'd2)) begin + main_litedramcore_steerer2 <= 2'd2; end - if ((litedramcore_wrcmdphase == 2'd2)) begin - litedramcore_steerer_sel2 <= 1'd1; + if ((main_litedramcore_rdphase == 2'd2)) begin + main_litedramcore_steerer2 <= 1'd1; end end 2'd2: begin @@ -9704,23 +10122,23 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel2 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 2'd2)) begin - litedramcore_steerer_sel2 <= 2'd2; + main_litedramcore_steerer2 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 2'd2)) begin + main_litedramcore_steerer2 <= 2'd2; end - if ((litedramcore_rdcmdphase == 2'd2)) begin - litedramcore_steerer_sel2 <= 1'd1; + if ((main_litedramcore_nphases == 2'd2)) begin + main_litedramcore_steerer2 <= 1'd1; end end endcase end always @(*) begin - litedramcore_choose_cmd_want_activates <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_cmd_want_activates <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin if (1'd0) begin end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; end end 2'd2: begin @@ -9744,21 +10162,21 @@ always @(*) begin default: begin if (1'd0) begin end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; end end endcase end always @(*) begin - litedramcore_steerer_sel3 <= 2'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_steerer3 <= 2'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_steerer_sel3 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 2'd3)) begin - litedramcore_steerer_sel3 <= 2'd2; + main_litedramcore_steerer3 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin + main_litedramcore_steerer3 <= 2'd2; end - if ((litedramcore_wrcmdphase == 2'd3)) begin - litedramcore_steerer_sel3 <= 1'd1; + if ((main_litedramcore_rdphase == 2'd3)) begin + main_litedramcore_steerer3 <= 1'd1; end end 2'd2: begin @@ -9780,19 +10198,19 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel3 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 2'd3)) begin - litedramcore_steerer_sel3 <= 2'd2; + main_litedramcore_steerer3 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin + main_litedramcore_steerer3 <= 2'd2; end - if ((litedramcore_rdcmdphase == 2'd3)) begin - litedramcore_steerer_sel3 <= 1'd1; + if ((main_litedramcore_nphases == 2'd3)) begin + main_litedramcore_steerer3 <= 1'd1; end end endcase end always @(*) begin - litedramcore_en0 <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_en0 <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin end 2'd2: begin @@ -9814,17 +10232,17 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_en0 <= 1'd1; + main_litedramcore_en0 <= 1'd1; end endcase end always @(*) begin - litedramcore_choose_cmd_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_cmd_cmd_ready <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin if (1'd0) begin end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); end end 2'd2: begin @@ -9848,14 +10266,14 @@ always @(*) begin default: begin if (1'd0) begin end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); end end endcase end always @(*) begin - litedramcore_choose_req_want_reads <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_req_want_reads <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin end 2'd2: begin @@ -9877,15 +10295,15 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_choose_req_want_reads <= 1'd1; + main_litedramcore_choose_req_want_reads <= 1'd1; end endcase end always @(*) begin - litedramcore_choose_req_want_writes <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_req_want_writes <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_choose_req_want_writes <= 1'd1; + main_litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -9910,14 +10328,10 @@ always @(*) begin endcase end always @(*) begin - litedramcore_choose_req_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_en1 <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end + main_litedramcore_en1 <= 1'd1; end 2'd2: begin end @@ -9938,19 +10352,18 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end end endcase end always @(*) begin - litedramcore_en1 <= 1'd0; - case (litedramcore_multiplexer_state) + main_litedramcore_choose_req_cmd_ready <= 1'd0; + case (builder_multiplexer_state) 1'd1: begin - litedramcore_en1 <= 1'd1; + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; + end end 2'd2: begin end @@ -9971,2011 +10384,2013 @@ always @(*) begin 4'd10: begin end default: begin + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; + end end endcase end -assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock)); -assign litedramcore_interface_bank0_addr = rhs_array_muxed12; -assign litedramcore_interface_bank0_we = rhs_array_muxed13; -assign litedramcore_interface_bank0_valid = rhs_array_muxed14; -assign litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock)); -assign litedramcore_interface_bank1_addr = rhs_array_muxed15; -assign litedramcore_interface_bank1_we = rhs_array_muxed16; -assign litedramcore_interface_bank1_valid = rhs_array_muxed17; -assign litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock)); -assign litedramcore_interface_bank2_addr = rhs_array_muxed18; -assign litedramcore_interface_bank2_we = rhs_array_muxed19; -assign litedramcore_interface_bank2_valid = rhs_array_muxed20; -assign litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock)); -assign litedramcore_interface_bank3_addr = rhs_array_muxed21; -assign litedramcore_interface_bank3_we = rhs_array_muxed22; -assign litedramcore_interface_bank3_valid = rhs_array_muxed23; -assign litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock)); -assign litedramcore_interface_bank4_addr = rhs_array_muxed24; -assign litedramcore_interface_bank4_we = rhs_array_muxed25; -assign litedramcore_interface_bank4_valid = rhs_array_muxed26; -assign litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock)); -assign litedramcore_interface_bank5_addr = rhs_array_muxed27; -assign litedramcore_interface_bank5_we = rhs_array_muxed28; -assign litedramcore_interface_bank5_valid = rhs_array_muxed29; -assign litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock)); -assign litedramcore_interface_bank6_addr = rhs_array_muxed30; -assign litedramcore_interface_bank6_we = rhs_array_muxed31; -assign litedramcore_interface_bank6_valid = rhs_array_muxed32; -assign litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)}; -assign litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock)); -assign litedramcore_interface_bank7_addr = rhs_array_muxed33; -assign litedramcore_interface_bank7_we = rhs_array_muxed34; -assign litedramcore_interface_bank7_valid = rhs_array_muxed35; -assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready)); -assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1; -assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8; -always @(*) begin - litedramcore_interface_wdata <= 128'd0; - case ({litedramcore_new_master_wdata_ready1}) +assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock)); +assign main_litedramcore_interface_bank0_addr = builder_rhs_self12; +assign main_litedramcore_interface_bank0_we = builder_rhs_self13; +assign main_litedramcore_interface_bank0_valid = builder_rhs_self14; +assign builder_roundrobin1_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin1_ce = ((~main_litedramcore_interface_bank1_valid) & (~main_litedramcore_interface_bank1_lock)); +assign main_litedramcore_interface_bank1_addr = builder_rhs_self15; +assign main_litedramcore_interface_bank1_we = builder_rhs_self16; +assign main_litedramcore_interface_bank1_valid = builder_rhs_self17; +assign builder_roundrobin2_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin2_ce = ((~main_litedramcore_interface_bank2_valid) & (~main_litedramcore_interface_bank2_lock)); +assign main_litedramcore_interface_bank2_addr = builder_rhs_self18; +assign main_litedramcore_interface_bank2_we = builder_rhs_self19; +assign main_litedramcore_interface_bank2_valid = builder_rhs_self20; +assign builder_roundrobin3_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin3_ce = ((~main_litedramcore_interface_bank3_valid) & (~main_litedramcore_interface_bank3_lock)); +assign main_litedramcore_interface_bank3_addr = builder_rhs_self21; +assign main_litedramcore_interface_bank3_we = builder_rhs_self22; +assign main_litedramcore_interface_bank3_valid = builder_rhs_self23; +assign builder_roundrobin4_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin4_ce = ((~main_litedramcore_interface_bank4_valid) & (~main_litedramcore_interface_bank4_lock)); +assign main_litedramcore_interface_bank4_addr = builder_rhs_self24; +assign main_litedramcore_interface_bank4_we = builder_rhs_self25; +assign main_litedramcore_interface_bank4_valid = builder_rhs_self26; +assign builder_roundrobin5_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin5_ce = ((~main_litedramcore_interface_bank5_valid) & (~main_litedramcore_interface_bank5_lock)); +assign main_litedramcore_interface_bank5_addr = builder_rhs_self27; +assign main_litedramcore_interface_bank5_we = builder_rhs_self28; +assign main_litedramcore_interface_bank5_valid = builder_rhs_self29; +assign builder_roundrobin6_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin6_ce = ((~main_litedramcore_interface_bank6_valid) & (~main_litedramcore_interface_bank6_lock)); +assign main_litedramcore_interface_bank6_addr = builder_rhs_self30; +assign main_litedramcore_interface_bank6_we = builder_rhs_self31; +assign main_litedramcore_interface_bank6_valid = builder_rhs_self32; +assign builder_roundrobin7_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid)}; +assign builder_roundrobin7_ce = ((~main_litedramcore_interface_bank7_valid) & (~main_litedramcore_interface_bank7_lock)); +assign main_litedramcore_interface_bank7_addr = builder_rhs_self33; +assign main_litedramcore_interface_bank7_we = builder_rhs_self34; +assign main_litedramcore_interface_bank7_valid = builder_rhs_self35; +assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready)); +assign main_user_port_wdata_ready = builder_new_master_wdata_ready1; +assign main_user_port_rdata_valid = builder_new_master_rdata_valid8; +always @(*) begin + main_litedramcore_interface_wdata <= 128'd0; + case ({builder_new_master_wdata_ready1}) 1'd1: begin - litedramcore_interface_wdata <= user_port_wdata_payload_data; + main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data; end default: begin - litedramcore_interface_wdata <= 1'd0; + main_litedramcore_interface_wdata <= 1'd0; end endcase end always @(*) begin - litedramcore_interface_wdata_we <= 16'd0; - case ({litedramcore_new_master_wdata_ready1}) + main_litedramcore_interface_wdata_we <= 16'd0; + case ({builder_new_master_wdata_ready1}) 1'd1: begin - litedramcore_interface_wdata_we <= user_port_wdata_payload_we; + main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we; end default: begin - litedramcore_interface_wdata_we <= 1'd0; + main_litedramcore_interface_wdata_we <= 1'd0; end endcase end -assign user_port_rdata_payload_data = litedramcore_interface_rdata; -assign litedramcore_roundrobin0_grant = 1'd0; -assign litedramcore_roundrobin1_grant = 1'd0; -assign litedramcore_roundrobin2_grant = 1'd0; -assign litedramcore_roundrobin3_grant = 1'd0; -assign litedramcore_roundrobin4_grant = 1'd0; -assign litedramcore_roundrobin5_grant = 1'd0; -assign litedramcore_roundrobin6_grant = 1'd0; -assign litedramcore_roundrobin7_grant = 1'd0; -always @(*) begin - litedramcore_next_state <= 2'd0; - litedramcore_next_state <= litedramcore_state; - case (litedramcore_state) +assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata; +assign builder_roundrobin0_grant = 1'd0; +assign builder_roundrobin1_grant = 1'd0; +assign builder_roundrobin2_grant = 1'd0; +assign builder_roundrobin3_grant = 1'd0; +assign builder_roundrobin4_grant = 1'd0; +assign builder_roundrobin5_grant = 1'd0; +assign builder_roundrobin6_grant = 1'd0; +assign builder_roundrobin7_grant = 1'd0; +always @(*) begin + builder_next_state <= 2'd0; + builder_next_state <= builder_state; + case (builder_state) 1'd1: begin - litedramcore_next_state <= 2'd2; + builder_next_state <= 2'd2; end 2'd2: begin - litedramcore_next_state <= 1'd0; + builder_next_state <= 1'd0; end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_next_state <= 1'd1; + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_next_state <= 1'd1; end end endcase end always @(*) begin - litedramcore_we_next_value2 <= 1'd0; - case (litedramcore_state) + builder_interface1_adr_next_value1 <= 14'd0; + case (builder_state) 1'd1: begin - litedramcore_we_next_value2 <= 1'd0; + builder_interface1_adr_next_value1 <= 1'd0; end 2'd2: begin end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_adr_next_value1 <= builder_interface0_adr[29:0]; end end endcase end always @(*) begin - litedramcore_we_next_value_ce2 <= 1'd0; - case (litedramcore_state) + builder_interface0_ack <= 1'd0; + case (builder_state) 1'd1: begin - litedramcore_we_next_value_ce2 <= 1'd1; end 2'd2: begin + builder_interface0_ack <= 1'd1; end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value_ce2 <= 1'd1; - end end endcase end always @(*) begin - litedramcore_wishbone_ack <= 1'd0; - case (litedramcore_state) + builder_interface1_adr_next_value_ce1 <= 1'd0; + case (builder_state) 1'd1: begin + builder_interface1_adr_next_value_ce1 <= 1'd1; end 2'd2: begin - litedramcore_wishbone_ack <= 1'd1; end default: begin + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_adr_next_value_ce1 <= 1'd1; + end end endcase end always @(*) begin - litedramcore_wishbone_dat_r <= 32'd0; - case (litedramcore_state) + builder_interface1_we_next_value2 <= 1'd0; + case (builder_state) 1'd1: begin + builder_interface1_we_next_value2 <= 1'd0; end 2'd2: begin - litedramcore_wishbone_dat_r <= litedramcore_dat_r; end default: begin + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_we_next_value2 <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); + end end endcase end always @(*) begin - litedramcore_dat_w_next_value0 <= 32'd0; - case (litedramcore_state) + builder_interface1_we_next_value_ce2 <= 1'd0; + case (builder_state) 1'd1: begin + builder_interface1_we_next_value_ce2 <= 1'd1; end 2'd2: begin end default: begin - litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w; + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_we_next_value_ce2 <= 1'd1; + end end endcase end always @(*) begin - litedramcore_dat_w_next_value_ce0 <= 1'd0; - case (litedramcore_state) + builder_interface0_dat_r <= 32'd0; + case (builder_state) 1'd1: begin end 2'd2: begin + builder_interface0_dat_r <= builder_interface1_dat_r; end default: begin - litedramcore_dat_w_next_value_ce0 <= 1'd1; end endcase end always @(*) begin - litedramcore_adr_next_value1 <= 14'd0; - case (litedramcore_state) + builder_interface1_dat_w_next_value0 <= 32'd0; + case (builder_state) 1'd1: begin - litedramcore_adr_next_value1 <= 1'd0; end 2'd2: begin end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value1 <= litedramcore_wishbone_adr; - end + builder_interface1_dat_w_next_value0 <= builder_interface0_dat_w; end endcase end always @(*) begin - litedramcore_adr_next_value_ce1 <= 1'd0; - case (litedramcore_state) + builder_interface1_dat_w_next_value_ce0 <= 1'd0; + case (builder_state) 1'd1: begin - litedramcore_adr_next_value_ce1 <= 1'd1; end 2'd2: begin end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value_ce1 <= 1'd1; - end + builder_interface1_dat_w_next_value_ce0 <= 1'd1; end endcase end -assign litedramcore_wishbone_adr = wb_bus_adr; -assign litedramcore_wishbone_dat_w = wb_bus_dat_w; -assign wb_bus_dat_r = litedramcore_wishbone_dat_r; -assign litedramcore_wishbone_sel = wb_bus_sel; -assign litedramcore_wishbone_cyc = wb_bus_cyc; -assign litedramcore_wishbone_stb = wb_bus_stb; -assign wb_bus_ack = litedramcore_wishbone_ack; -assign litedramcore_wishbone_we = wb_bus_we; -assign litedramcore_wishbone_cti = wb_bus_cti; -assign litedramcore_wishbone_bte = wb_bus_bte; -assign wb_bus_err = litedramcore_wishbone_err; -assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); -assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; +assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); +assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_done0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_we <= (~interface0_bank_bus_we); + builder_csrbank0_init_done0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we); end end always @(*) begin - csrbank0_init_done0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_re <= interface0_bank_bus_we; + builder_csrbank0_init_done0_re <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we; end end -assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; +assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_error0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_re <= interface0_bank_bus_we; + builder_csrbank0_init_error0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we); end end always @(*) begin - csrbank0_init_error0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_we <= (~interface0_bank_bus_we); + builder_csrbank0_init_error0_re <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; end end -assign csrbank0_init_done0_w = init_done_storage; -assign csrbank0_init_error0_w = init_error_storage; -assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); -assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0]; +assign builder_csrbank0_init_done0_w = main_init_done_storage; +assign builder_csrbank0_init_error0_w = main_init_error_storage; +assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1); +assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - csrbank1_rst0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_rst0_re <= interface1_bank_bus_we; + builder_csrbank1_rst0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - csrbank1_rst0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_rst0_we <= (~interface1_bank_bus_we); + builder_csrbank1_rst0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; end end -assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; +assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_dly_sel0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dly_sel0_we <= (~interface1_bank_bus_we); + builder_csrbank1_dly_sel0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - csrbank1_dly_sel0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dly_sel0_re <= interface1_bank_bus_we; + builder_csrbank1_dly_sel0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we); end end -assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; +assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0]; always @(*) begin - csrbank1_half_sys8x_taps0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we); + builder_csrbank1_half_sys8x_taps0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - csrbank1_half_sys8x_taps0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we; + builder_csrbank1_half_sys8x_taps0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; end end -assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0]; +assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - csrbank1_wlevel_en0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_wlevel_en0_re <= interface1_bank_bus_we; + builder_csrbank1_wlevel_en0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - csrbank1_wlevel_en0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we); + builder_csrbank1_wlevel_en0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we); end end -assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_wlevel_strobe_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we; + main_a7ddrphy_wlevel_strobe_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we; end end always @(*) begin - a7ddrphy_wlevel_strobe_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we); + main_a7ddrphy_wlevel_strobe_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we); end end -assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; end end always @(*) begin - a7ddrphy_rdly_dq_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we); end end -assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_inc_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_inc_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; end end always @(*) begin - a7ddrphy_rdly_dq_inc_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_inc_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we); end end -assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end end -assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_bitslip_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - a7ddrphy_rdly_dq_bitslip_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end end -assign a7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end end -assign a7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_wdly_dq_bitslip_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we); + main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - a7ddrphy_wdly_dq_bitslip_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we; + main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end end -assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0]; +assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_rdphase0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - csrbank1_rdphase0_we <= (~interface1_bank_bus_we); + builder_csrbank1_rdphase0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - csrbank1_rdphase0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - csrbank1_rdphase0_re <= interface1_bank_bus_we; + builder_csrbank1_rdphase0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we); end end -assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0]; +assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_wrphase0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - csrbank1_wrphase0_re <= interface1_bank_bus_we; + builder_csrbank1_wrphase0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we); end end always @(*) begin - csrbank1_wrphase0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - csrbank1_wrphase0_we <= (~interface1_bank_bus_we); + builder_csrbank1_wrphase0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; end end -assign csrbank1_rst0_w = a7ddrphy_rst_storage; -assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; -assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0]; -assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage; -assign csrbank1_rdphase0_w = a7ddrphy_rdphase_storage[1:0]; -assign csrbank1_wrphase0_w = a7ddrphy_wrphase_storage[1:0]; -assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); -assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; +assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage; +assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0]; +assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0]; +assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage; +assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0]; +assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0]; +assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2); +assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0]; always @(*) begin - csrbank2_dfii_control0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_control0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_control0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_control0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; +assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi0_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi0_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we; end end -assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; +assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector0_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we; + main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - litedramcore_phaseinjector0_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we); + main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[13:0]; +assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[13:0]; always @(*) begin - csrbank2_dfii_pi0_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi0_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi0_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi0_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi0_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin + builder_csrbank2_dfii_pi0_rddata_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi0_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin + builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; +assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi1_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi1_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we; end end -assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; +assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector1_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we); + main_litedramcore_phaseinjector1_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin + main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we; end end always @(*) begin - litedramcore_phaseinjector1_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we; + main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin + main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[13:0]; +assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[13:0]; always @(*) begin - csrbank2_dfii_pi1_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi1_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi1_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi1_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi1_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi1_rddata_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi1_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0]; +assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi2_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi2_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we); end end -assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; +assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector2_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we); + main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - litedramcore_phaseinjector2_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we; + main_litedramcore_phaseinjector2_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[13:0]; +assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[13:0]; always @(*) begin - csrbank2_dfii_pi2_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi2_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi2_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi2_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi2_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin - csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi2_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin - csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi2_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin - csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi2_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin - csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank2_dfii_pi2_rddata_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0]; +assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi3_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin - csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi3_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin - csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we); end end -assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; +assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector3_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin - litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we; + main_litedramcore_phaseinjector3_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we; end end always @(*) begin - litedramcore_phaseinjector3_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin - litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we); + main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[13:0]; +assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[13:0]; always @(*) begin - csrbank2_dfii_pi3_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin - csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi3_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin - csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi3_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin - csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi3_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin - csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we; end end -assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi3_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin - csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi3_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin - csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we); end end -assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi3_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin - csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we); end end always @(*) begin - csrbank2_dfii_pi3_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin - csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi3_rddata_re <= builder_interface2_bank_bus_we; end end -assign litedramcore_sel = litedramcore_storage[0]; -assign litedramcore_cke = litedramcore_storage[1]; -assign litedramcore_odt = litedramcore_storage[2]; -assign litedramcore_reset_n = litedramcore_storage[3]; -assign csrbank2_dfii_control0_w = litedramcore_storage[3:0]; -assign litedramcore_phaseinjector0_csrfield_cs = litedramcore_phaseinjector0_command_storage[0]; -assign litedramcore_phaseinjector0_csrfield_we = litedramcore_phaseinjector0_command_storage[1]; -assign litedramcore_phaseinjector0_csrfield_cas = litedramcore_phaseinjector0_command_storage[2]; -assign litedramcore_phaseinjector0_csrfield_ras = litedramcore_phaseinjector0_command_storage[3]; -assign litedramcore_phaseinjector0_csrfield_wren = litedramcore_phaseinjector0_command_storage[4]; -assign litedramcore_phaseinjector0_csrfield_rden = litedramcore_phaseinjector0_command_storage[5]; -assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; -assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0]; -assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0]; -assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0]; -assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_rddata_status[31:0]; -assign litedramcore_phaseinjector0_rddata_we = csrbank2_dfii_pi0_rddata_we; -assign litedramcore_phaseinjector1_csrfield_cs = litedramcore_phaseinjector1_command_storage[0]; -assign litedramcore_phaseinjector1_csrfield_we = litedramcore_phaseinjector1_command_storage[1]; -assign litedramcore_phaseinjector1_csrfield_cas = litedramcore_phaseinjector1_command_storage[2]; -assign litedramcore_phaseinjector1_csrfield_ras = litedramcore_phaseinjector1_command_storage[3]; -assign litedramcore_phaseinjector1_csrfield_wren = litedramcore_phaseinjector1_command_storage[4]; -assign litedramcore_phaseinjector1_csrfield_rden = litedramcore_phaseinjector1_command_storage[5]; -assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0]; -assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[13:0]; -assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0]; -assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0]; -assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_rddata_status[31:0]; -assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata_we; -assign litedramcore_phaseinjector2_csrfield_cs = litedramcore_phaseinjector2_command_storage[0]; -assign litedramcore_phaseinjector2_csrfield_we = litedramcore_phaseinjector2_command_storage[1]; -assign litedramcore_phaseinjector2_csrfield_cas = litedramcore_phaseinjector2_command_storage[2]; -assign litedramcore_phaseinjector2_csrfield_ras = litedramcore_phaseinjector2_command_storage[3]; -assign litedramcore_phaseinjector2_csrfield_wren = litedramcore_phaseinjector2_command_storage[4]; -assign litedramcore_phaseinjector2_csrfield_rden = litedramcore_phaseinjector2_command_storage[5]; -assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0]; -assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[13:0]; -assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0]; -assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0]; -assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_rddata_status[31:0]; -assign litedramcore_phaseinjector2_rddata_we = csrbank2_dfii_pi2_rddata_we; -assign litedramcore_phaseinjector3_csrfield_cs = litedramcore_phaseinjector3_command_storage[0]; -assign litedramcore_phaseinjector3_csrfield_we = litedramcore_phaseinjector3_command_storage[1]; -assign litedramcore_phaseinjector3_csrfield_cas = litedramcore_phaseinjector3_command_storage[2]; -assign litedramcore_phaseinjector3_csrfield_ras = litedramcore_phaseinjector3_command_storage[3]; -assign litedramcore_phaseinjector3_csrfield_wren = litedramcore_phaseinjector3_command_storage[4]; -assign litedramcore_phaseinjector3_csrfield_rden = litedramcore_phaseinjector3_command_storage[5]; -assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0]; -assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[13:0]; -assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0]; -assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0]; -assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_rddata_status[31:0]; -assign litedramcore_phaseinjector3_rddata_we = csrbank2_dfii_pi3_rddata_we; -assign csr_interconnect_adr = litedramcore_adr; -assign csr_interconnect_we = litedramcore_we; -assign csr_interconnect_dat_w = litedramcore_dat_w; -assign litedramcore_dat_r = csr_interconnect_dat_r; -assign interface0_bank_bus_adr = csr_interconnect_adr; -assign interface1_bank_bus_adr = csr_interconnect_adr; -assign interface2_bank_bus_adr = csr_interconnect_adr; -assign interface0_bank_bus_we = csr_interconnect_we; -assign interface1_bank_bus_we = csr_interconnect_we; -assign interface2_bank_bus_we = csr_interconnect_we; -assign interface0_bank_bus_dat_w = csr_interconnect_dat_w; -assign interface1_bank_bus_dat_w = csr_interconnect_dat_w; -assign interface2_bank_bus_dat_w = csr_interconnect_dat_w; -assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); -always @(*) begin - rhs_array_muxed0 <= 1'd0; - case (litedramcore_choose_cmd_grant) +assign main_litedramcore_sel = main_litedramcore_storage[0]; +assign main_litedramcore_cke = main_litedramcore_storage[1]; +assign main_litedramcore_odt = main_litedramcore_storage[2]; +assign main_litedramcore_reset_n = main_litedramcore_storage[3]; +assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0]; +assign main_litedramcore_phaseinjector0_csrfield_cs = main_litedramcore_phaseinjector0_command_storage[0]; +assign main_litedramcore_phaseinjector0_csrfield_we = main_litedramcore_phaseinjector0_command_storage[1]; +assign main_litedramcore_phaseinjector0_csrfield_cas = main_litedramcore_phaseinjector0_command_storage[2]; +assign main_litedramcore_phaseinjector0_csrfield_ras = main_litedramcore_phaseinjector0_command_storage[3]; +assign main_litedramcore_phaseinjector0_csrfield_wren = main_litedramcore_phaseinjector0_command_storage[4]; +assign main_litedramcore_phaseinjector0_csrfield_rden = main_litedramcore_phaseinjector0_command_storage[5]; +assign main_litedramcore_phaseinjector0_csrfield_cs_top = main_litedramcore_phaseinjector0_command_storage[6]; +assign main_litedramcore_phaseinjector0_csrfield_cs_bottom = main_litedramcore_phaseinjector0_command_storage[7]; +assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[7:0]; +assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[13:0]; +assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0]; +assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we; +assign main_litedramcore_phaseinjector1_csrfield_cs = main_litedramcore_phaseinjector1_command_storage[0]; +assign main_litedramcore_phaseinjector1_csrfield_we = main_litedramcore_phaseinjector1_command_storage[1]; +assign main_litedramcore_phaseinjector1_csrfield_cas = main_litedramcore_phaseinjector1_command_storage[2]; +assign main_litedramcore_phaseinjector1_csrfield_ras = main_litedramcore_phaseinjector1_command_storage[3]; +assign main_litedramcore_phaseinjector1_csrfield_wren = main_litedramcore_phaseinjector1_command_storage[4]; +assign main_litedramcore_phaseinjector1_csrfield_rden = main_litedramcore_phaseinjector1_command_storage[5]; +assign main_litedramcore_phaseinjector1_csrfield_cs_top = main_litedramcore_phaseinjector1_command_storage[6]; +assign main_litedramcore_phaseinjector1_csrfield_cs_bottom = main_litedramcore_phaseinjector1_command_storage[7]; +assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[7:0]; +assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[13:0]; +assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0]; +assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we; +assign main_litedramcore_phaseinjector2_csrfield_cs = main_litedramcore_phaseinjector2_command_storage[0]; +assign main_litedramcore_phaseinjector2_csrfield_we = main_litedramcore_phaseinjector2_command_storage[1]; +assign main_litedramcore_phaseinjector2_csrfield_cas = main_litedramcore_phaseinjector2_command_storage[2]; +assign main_litedramcore_phaseinjector2_csrfield_ras = main_litedramcore_phaseinjector2_command_storage[3]; +assign main_litedramcore_phaseinjector2_csrfield_wren = main_litedramcore_phaseinjector2_command_storage[4]; +assign main_litedramcore_phaseinjector2_csrfield_rden = main_litedramcore_phaseinjector2_command_storage[5]; +assign main_litedramcore_phaseinjector2_csrfield_cs_top = main_litedramcore_phaseinjector2_command_storage[6]; +assign main_litedramcore_phaseinjector2_csrfield_cs_bottom = main_litedramcore_phaseinjector2_command_storage[7]; +assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[7:0]; +assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[13:0]; +assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0]; +assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we; +assign main_litedramcore_phaseinjector3_csrfield_cs = main_litedramcore_phaseinjector3_command_storage[0]; +assign main_litedramcore_phaseinjector3_csrfield_we = main_litedramcore_phaseinjector3_command_storage[1]; +assign main_litedramcore_phaseinjector3_csrfield_cas = main_litedramcore_phaseinjector3_command_storage[2]; +assign main_litedramcore_phaseinjector3_csrfield_ras = main_litedramcore_phaseinjector3_command_storage[3]; +assign main_litedramcore_phaseinjector3_csrfield_wren = main_litedramcore_phaseinjector3_command_storage[4]; +assign main_litedramcore_phaseinjector3_csrfield_rden = main_litedramcore_phaseinjector3_command_storage[5]; +assign main_litedramcore_phaseinjector3_csrfield_cs_top = main_litedramcore_phaseinjector3_command_storage[6]; +assign main_litedramcore_phaseinjector3_csrfield_cs_bottom = main_litedramcore_phaseinjector3_command_storage[7]; +assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[7:0]; +assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[13:0]; +assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0]; +assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we; +assign builder_adr = builder_interface1_adr; +assign builder_we = builder_interface1_we; +assign builder_dat_w = builder_interface1_dat_w; +assign builder_interface1_dat_r = builder_dat_r; +assign builder_interface0_bank_bus_adr = builder_adr; +assign builder_interface1_bank_bus_adr = builder_adr; +assign builder_interface2_bank_bus_adr = builder_adr; +assign builder_interface0_bank_bus_we = builder_we; +assign builder_interface1_bank_bus_we = builder_we; +assign builder_interface2_bank_bus_we = builder_we; +assign builder_interface0_bank_bus_dat_w = builder_dat_w; +assign builder_interface1_bank_bus_dat_w = builder_dat_w; +assign builder_interface2_bank_bus_dat_w = builder_dat_w; +assign builder_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); +always @(*) begin + builder_rhs_self0 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[0]; end 1'd1: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[1]; end 2'd2: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[2]; end 2'd3: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[3]; end 3'd4: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[4]; end 3'd5: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[5]; end 3'd6: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[6]; end default: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7]; + builder_rhs_self0 <= main_litedramcore_choose_cmd_valids[7]; end endcase end always @(*) begin - rhs_array_muxed1 <= 14'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self1 <= 14'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine6_cmd_payload_a; end default: begin - rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a; + builder_rhs_self1 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase end always @(*) begin - rhs_array_muxed2 <= 3'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self2 <= 3'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine6_cmd_payload_ba; end default: begin - rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba; + builder_rhs_self2 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase end always @(*) begin - rhs_array_muxed3 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self3 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read; + builder_rhs_self3 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase end always @(*) begin - rhs_array_muxed4 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self4 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write; + builder_rhs_self4 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase end always @(*) begin - rhs_array_muxed5 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_rhs_self5 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + builder_rhs_self5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase end always @(*) begin - t_array_muxed0 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_t_self0 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine6_cmd_payload_cas; end default: begin - t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas; + builder_t_self0 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase end always @(*) begin - t_array_muxed1 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_t_self1 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine6_cmd_payload_ras; end default: begin - t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras; + builder_t_self1 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase end always @(*) begin - t_array_muxed2 <= 1'd0; - case (litedramcore_choose_cmd_grant) + builder_t_self2 <= 1'd0; + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine6_cmd_payload_we; end default: begin - t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we; + builder_t_self2 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed6 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self6 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[0]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[0]; end 1'd1: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[1]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[1]; end 2'd2: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[2]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[2]; end 2'd3: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[3]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[3]; end 3'd4: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[4]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[4]; end 3'd5: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[5]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[5]; end 3'd6: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[6]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[6]; end default: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[7]; + builder_rhs_self6 <= main_litedramcore_choose_req_valids[7]; end endcase end always @(*) begin - rhs_array_muxed7 <= 14'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self7 <= 14'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine6_cmd_payload_a; end default: begin - rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a; + builder_rhs_self7 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase end always @(*) begin - rhs_array_muxed8 <= 3'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self8 <= 3'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine6_cmd_payload_ba; end default: begin - rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba; + builder_rhs_self8 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase end always @(*) begin - rhs_array_muxed9 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self9 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read; + builder_rhs_self9 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase end always @(*) begin - rhs_array_muxed10 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self10 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write; + builder_rhs_self10 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase end always @(*) begin - rhs_array_muxed11 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_rhs_self11 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + builder_rhs_self11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase end always @(*) begin - t_array_muxed3 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_t_self3 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine6_cmd_payload_cas; end default: begin - t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas; + builder_t_self3 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase end always @(*) begin - t_array_muxed4 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_t_self4 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine6_cmd_payload_ras; end default: begin - t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras; + builder_t_self4 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase end always @(*) begin - t_array_muxed5 <= 1'd0; - case (litedramcore_choose_req_grant) + builder_t_self5 <= 1'd0; + case (main_litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine6_cmd_payload_we; end default: begin - t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we; + builder_t_self5 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed12 <= 21'd0; - case (litedramcore_roundrobin0_grant) + builder_rhs_self12 <= 21'd0; + case (builder_roundrobin0_grant) default: begin - rhs_array_muxed12 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self12 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed13 <= 1'd0; - case (litedramcore_roundrobin0_grant) + builder_rhs_self13 <= 1'd0; + case (builder_roundrobin0_grant) default: begin - rhs_array_muxed13 <= user_port_cmd_payload_we; + builder_rhs_self13 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed14 <= 1'd0; - case (litedramcore_roundrobin0_grant) + builder_rhs_self14 <= 1'd0; + case (builder_roundrobin0_grant) default: begin - rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed15 <= 21'd0; - case (litedramcore_roundrobin1_grant) + builder_rhs_self15 <= 21'd0; + case (builder_roundrobin1_grant) default: begin - rhs_array_muxed15 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self15 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed16 <= 1'd0; - case (litedramcore_roundrobin1_grant) + builder_rhs_self16 <= 1'd0; + case (builder_roundrobin1_grant) default: begin - rhs_array_muxed16 <= user_port_cmd_payload_we; + builder_rhs_self16 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed17 <= 1'd0; - case (litedramcore_roundrobin1_grant) + builder_rhs_self17 <= 1'd0; + case (builder_roundrobin1_grant) default: begin - rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed18 <= 21'd0; - case (litedramcore_roundrobin2_grant) + builder_rhs_self18 <= 21'd0; + case (builder_roundrobin2_grant) default: begin - rhs_array_muxed18 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self18 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed19 <= 1'd0; - case (litedramcore_roundrobin2_grant) + builder_rhs_self19 <= 1'd0; + case (builder_roundrobin2_grant) default: begin - rhs_array_muxed19 <= user_port_cmd_payload_we; + builder_rhs_self19 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed20 <= 1'd0; - case (litedramcore_roundrobin2_grant) + builder_rhs_self20 <= 1'd0; + case (builder_roundrobin2_grant) default: begin - rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed21 <= 21'd0; - case (litedramcore_roundrobin3_grant) + builder_rhs_self21 <= 21'd0; + case (builder_roundrobin3_grant) default: begin - rhs_array_muxed21 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self21 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed22 <= 1'd0; - case (litedramcore_roundrobin3_grant) + builder_rhs_self22 <= 1'd0; + case (builder_roundrobin3_grant) default: begin - rhs_array_muxed22 <= user_port_cmd_payload_we; + builder_rhs_self22 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed23 <= 1'd0; - case (litedramcore_roundrobin3_grant) + builder_rhs_self23 <= 1'd0; + case (builder_roundrobin3_grant) default: begin - rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed24 <= 21'd0; - case (litedramcore_roundrobin4_grant) + builder_rhs_self24 <= 21'd0; + case (builder_roundrobin4_grant) default: begin - rhs_array_muxed24 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self24 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed25 <= 1'd0; - case (litedramcore_roundrobin4_grant) + builder_rhs_self25 <= 1'd0; + case (builder_roundrobin4_grant) default: begin - rhs_array_muxed25 <= user_port_cmd_payload_we; + builder_rhs_self25 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed26 <= 1'd0; - case (litedramcore_roundrobin4_grant) + builder_rhs_self26 <= 1'd0; + case (builder_roundrobin4_grant) default: begin - rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed27 <= 21'd0; - case (litedramcore_roundrobin5_grant) + builder_rhs_self27 <= 21'd0; + case (builder_roundrobin5_grant) default: begin - rhs_array_muxed27 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self27 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed28 <= 1'd0; - case (litedramcore_roundrobin5_grant) + builder_rhs_self28 <= 1'd0; + case (builder_roundrobin5_grant) default: begin - rhs_array_muxed28 <= user_port_cmd_payload_we; + builder_rhs_self28 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed29 <= 1'd0; - case (litedramcore_roundrobin5_grant) + builder_rhs_self29 <= 1'd0; + case (builder_roundrobin5_grant) default: begin - rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed30 <= 21'd0; - case (litedramcore_roundrobin6_grant) + builder_rhs_self30 <= 21'd0; + case (builder_roundrobin6_grant) default: begin - rhs_array_muxed30 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self30 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed31 <= 1'd0; - case (litedramcore_roundrobin6_grant) + builder_rhs_self31 <= 1'd0; + case (builder_roundrobin6_grant) default: begin - rhs_array_muxed31 <= user_port_cmd_payload_we; + builder_rhs_self31 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed32 <= 1'd0; - case (litedramcore_roundrobin6_grant) + builder_rhs_self32 <= 1'd0; + case (builder_roundrobin6_grant) default: begin - rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed33 <= 21'd0; - case (litedramcore_roundrobin7_grant) + builder_rhs_self33 <= 21'd0; + case (builder_roundrobin7_grant) default: begin - rhs_array_muxed33 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + builder_rhs_self33 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed34 <= 1'd0; - case (litedramcore_roundrobin7_grant) + builder_rhs_self34 <= 1'd0; + case (builder_roundrobin7_grant) default: begin - rhs_array_muxed34 <= user_port_cmd_payload_we; + builder_rhs_self34 <= main_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed35 <= 1'd0; - case (litedramcore_roundrobin7_grant) + builder_rhs_self35 <= 1'd0; + case (builder_roundrobin7_grant) default: begin - rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); + builder_rhs_self35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase end always @(*) begin - array_muxed0 <= 3'd0; - case (litedramcore_steerer_sel0) + builder_self0 <= 3'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed0 <= litedramcore_nop_ba[2:0]; + builder_self0 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed0 <= litedramcore_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed1 <= 14'd0; - case (litedramcore_steerer_sel0) + builder_self1 <= 14'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed1 <= litedramcore_nop_a; + builder_self1 <= main_litedramcore_nop_a; end 1'd1: begin - array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a; + builder_self1 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed1 <= litedramcore_choose_req_cmd_payload_a; + builder_self1 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed1 <= litedramcore_cmd_payload_a; + builder_self1 <= main_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed2 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self2 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed2 <= 1'd0; + builder_self2 <= 1'd0; end 1'd1: begin - array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + builder_self2 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + builder_self2 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + builder_self2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed3 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self3 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed3 <= 1'd0; + builder_self3 <= 1'd0; end 1'd1: begin - array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + builder_self3 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + builder_self3 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + builder_self3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed4 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self4 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed4 <= 1'd0; + builder_self4 <= 1'd0; end 1'd1: begin - array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + builder_self4 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + builder_self4 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + builder_self4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed5 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self5 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed5 <= 1'd0; + builder_self5 <= 1'd0; end 1'd1: begin - array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + builder_self5 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + builder_self5 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + builder_self5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed6 <= 1'd0; - case (litedramcore_steerer_sel0) + builder_self6 <= 1'd0; + case (main_litedramcore_steerer0) 1'd0: begin - array_muxed6 <= 1'd0; + builder_self6 <= 1'd0; end 1'd1: begin - array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + builder_self6 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + builder_self6 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + builder_self6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase end always @(*) begin - array_muxed7 <= 3'd0; - case (litedramcore_steerer_sel1) + builder_self7 <= 3'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed7 <= litedramcore_nop_ba[2:0]; + builder_self7 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed7 <= litedramcore_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed8 <= 14'd0; - case (litedramcore_steerer_sel1) + builder_self8 <= 14'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed8 <= litedramcore_nop_a; + builder_self8 <= main_litedramcore_nop_a; end 1'd1: begin - array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a; + builder_self8 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed8 <= litedramcore_choose_req_cmd_payload_a; + builder_self8 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed8 <= litedramcore_cmd_payload_a; + builder_self8 <= main_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed9 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self9 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed9 <= 1'd0; + builder_self9 <= 1'd0; end 1'd1: begin - array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + builder_self9 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + builder_self9 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + builder_self9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed10 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self10 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed10 <= 1'd0; + builder_self10 <= 1'd0; end 1'd1: begin - array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + builder_self10 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + builder_self10 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + builder_self10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed11 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self11 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed11 <= 1'd0; + builder_self11 <= 1'd0; end 1'd1: begin - array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + builder_self11 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + builder_self11 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + builder_self11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed12 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self12 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed12 <= 1'd0; + builder_self12 <= 1'd0; end 1'd1: begin - array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + builder_self12 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + builder_self12 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + builder_self12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed13 <= 1'd0; - case (litedramcore_steerer_sel1) + builder_self13 <= 1'd0; + case (main_litedramcore_steerer1) 1'd0: begin - array_muxed13 <= 1'd0; + builder_self13 <= 1'd0; end 1'd1: begin - array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + builder_self13 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + builder_self13 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + builder_self13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase end always @(*) begin - array_muxed14 <= 3'd0; - case (litedramcore_steerer_sel2) + builder_self14 <= 3'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed14 <= litedramcore_nop_ba[2:0]; + builder_self14 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed14 <= litedramcore_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed15 <= 14'd0; - case (litedramcore_steerer_sel2) + builder_self15 <= 14'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed15 <= litedramcore_nop_a; + builder_self15 <= main_litedramcore_nop_a; end 1'd1: begin - array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a; + builder_self15 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed15 <= litedramcore_choose_req_cmd_payload_a; + builder_self15 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed15 <= litedramcore_cmd_payload_a; + builder_self15 <= main_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed16 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self16 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed16 <= 1'd0; + builder_self16 <= 1'd0; end 1'd1: begin - array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + builder_self16 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + builder_self16 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + builder_self16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed17 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self17 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed17 <= 1'd0; + builder_self17 <= 1'd0; end 1'd1: begin - array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + builder_self17 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + builder_self17 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + builder_self17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed18 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self18 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed18 <= 1'd0; + builder_self18 <= 1'd0; end 1'd1: begin - array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + builder_self18 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + builder_self18 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + builder_self18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed19 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self19 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed19 <= 1'd0; + builder_self19 <= 1'd0; end 1'd1: begin - array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + builder_self19 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + builder_self19 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + builder_self19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed20 <= 1'd0; - case (litedramcore_steerer_sel2) + builder_self20 <= 1'd0; + case (main_litedramcore_steerer2) 1'd0: begin - array_muxed20 <= 1'd0; + builder_self20 <= 1'd0; end 1'd1: begin - array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + builder_self20 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + builder_self20 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + builder_self20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase end always @(*) begin - array_muxed21 <= 3'd0; - case (litedramcore_steerer_sel3) + builder_self21 <= 3'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed21 <= litedramcore_nop_ba[2:0]; + builder_self21 <= main_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed21 <= litedramcore_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed22 <= 14'd0; - case (litedramcore_steerer_sel3) + builder_self22 <= 14'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed22 <= litedramcore_nop_a; + builder_self22 <= main_litedramcore_nop_a; end 1'd1: begin - array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a; + builder_self22 <= main_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed22 <= litedramcore_choose_req_cmd_payload_a; + builder_self22 <= main_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed22 <= litedramcore_cmd_payload_a; + builder_self22 <= main_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed23 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self23 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed23 <= 1'd0; + builder_self23 <= 1'd0; end 1'd1: begin - array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + builder_self23 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + builder_self23 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + builder_self23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed24 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self24 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed24 <= 1'd0; + builder_self24 <= 1'd0; end 1'd1: begin - array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + builder_self24 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + builder_self24 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + builder_self24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed25 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self25 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed25 <= 1'd0; + builder_self25 <= 1'd0; end 1'd1: begin - array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + builder_self25 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + builder_self25 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + builder_self25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed26 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self26 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed26 <= 1'd0; + builder_self26 <= 1'd0; end 1'd1: begin - array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + builder_self26 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + builder_self26 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + builder_self26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed27 <= 1'd0; - case (litedramcore_steerer_sel3) + builder_self27 <= 1'd0; + case (main_litedramcore_steerer3) 1'd0: begin - array_muxed27 <= 1'd0; + builder_self27 <= 1'd0; end 1'd1: begin - array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + builder_self27 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + builder_self27 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + builder_self27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase end -assign xilinxasyncresetsynchronizerimpl0 = (~locked); -assign xilinxasyncresetsynchronizerimpl1 = (~locked); -assign xilinxasyncresetsynchronizerimpl2 = (~locked); -assign xilinxasyncresetsynchronizerimpl3 = (~locked); +assign builder_xilinxasyncresetsynchronizerimpl0_async_reset = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl1_async_reset = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl2_async_reset = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl3_async_reset = (~main_locked); //------------------------------------------------------------------------------ @@ -11983,1044 +12398,1044 @@ assign xilinxasyncresetsynchronizerimpl3 = (~locked); //------------------------------------------------------------------------------ always @(posedge iodelay_clk) begin - if ((reset_counter != 1'd0)) begin - reset_counter <= (reset_counter - 1'd1); + if ((main_reset_counter != 1'd0)) begin + main_reset_counter <= (main_reset_counter - 1'd1); end else begin - ic_reset <= 1'd0; + main_ic_reset <= 1'd0; end if (iodelay_rst) begin - reset_counter <= 4'd15; - ic_reset <= 1'd1; + main_reset_counter <= 4'd15; + main_ic_reset <= 1'd1; end end always @(posedge sys_clk) begin - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline; - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; - a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1); + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline; + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; + main_a7ddrphy_dqspattern_o1 <= main_a7ddrphy_dqspattern_o0; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value0 <= (main_a7ddrphy_bitslip0_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value0 <= 3'd7; end - a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1); + main_a7ddrphy_bitslip0_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip0_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value0 <= (main_a7ddrphy_bitslip1_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value0 <= 3'd7; end - a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1); + main_a7ddrphy_bitslip1_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip1_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value1 <= (main_a7ddrphy_bitslip0_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value1 <= 3'd7; end - a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1); + main_a7ddrphy_bitslip0_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[2], main_a7ddrphy_dfi_p3_wrdata_mask[0], main_a7ddrphy_dfi_p2_wrdata_mask[2], main_a7ddrphy_dfi_p2_wrdata_mask[0], main_a7ddrphy_dfi_p1_wrdata_mask[2], main_a7ddrphy_dfi_p1_wrdata_mask[0], main_a7ddrphy_dfi_p0_wrdata_mask[2], main_a7ddrphy_dfi_p0_wrdata_mask[0]}, main_a7ddrphy_bitslip0_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value1 <= (main_a7ddrphy_bitslip1_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value1 <= 3'd7; end - a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]}; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1); + main_a7ddrphy_bitslip1_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[3], main_a7ddrphy_dfi_p3_wrdata_mask[1], main_a7ddrphy_dfi_p2_wrdata_mask[3], main_a7ddrphy_dfi_p2_wrdata_mask[1], main_a7ddrphy_dfi_p1_wrdata_mask[3], main_a7ddrphy_dfi_p1_wrdata_mask[1], main_a7ddrphy_dfi_p0_wrdata_mask[3], main_a7ddrphy_dfi_p0_wrdata_mask[1]}, main_a7ddrphy_bitslip1_r1[15:8]}; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dq_oe_delay_tappeddelayline; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value2 <= (main_a7ddrphy_bitslip0_value2 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value2 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value2 <= 3'd7; end - a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1); + main_a7ddrphy_bitslip0_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[16], main_a7ddrphy_dfi_p3_wrdata[0], main_a7ddrphy_dfi_p2_wrdata[16], main_a7ddrphy_dfi_p2_wrdata[0], main_a7ddrphy_dfi_p1_wrdata[16], main_a7ddrphy_dfi_p1_wrdata[0], main_a7ddrphy_dfi_p0_wrdata[16], main_a7ddrphy_dfi_p0_wrdata[0]}, main_a7ddrphy_bitslip0_r2[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip0_value3 <= (main_a7ddrphy_bitslip0_value3 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value3 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip0_value3 <= 3'd7; end - a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1); + main_a7ddrphy_bitslip0_r3 <= {main_a7ddrphy_bitslip03, main_a7ddrphy_bitslip0_r3[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value2 <= (main_a7ddrphy_bitslip1_value2 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value2 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value2 <= 3'd7; end - a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1); + main_a7ddrphy_bitslip1_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[17], main_a7ddrphy_dfi_p3_wrdata[1], main_a7ddrphy_dfi_p2_wrdata[17], main_a7ddrphy_dfi_p2_wrdata[1], main_a7ddrphy_dfi_p1_wrdata[17], main_a7ddrphy_dfi_p1_wrdata[1], main_a7ddrphy_dfi_p0_wrdata[17], main_a7ddrphy_dfi_p0_wrdata[1]}, main_a7ddrphy_bitslip1_r2[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip1_value3 <= (main_a7ddrphy_bitslip1_value3 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value3 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip1_value3 <= 3'd7; end - a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1); + main_a7ddrphy_bitslip1_r3 <= {main_a7ddrphy_bitslip13, main_a7ddrphy_bitslip1_r3[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip2_value0 <= (main_a7ddrphy_bitslip2_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip2_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip2_value0 <= 3'd7; end - a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1); + main_a7ddrphy_bitslip2_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[18], main_a7ddrphy_dfi_p3_wrdata[2], main_a7ddrphy_dfi_p2_wrdata[18], main_a7ddrphy_dfi_p2_wrdata[2], main_a7ddrphy_dfi_p1_wrdata[18], main_a7ddrphy_dfi_p1_wrdata[2], main_a7ddrphy_dfi_p0_wrdata[18], main_a7ddrphy_dfi_p0_wrdata[2]}, main_a7ddrphy_bitslip2_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip2_value1 <= (main_a7ddrphy_bitslip2_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip2_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip2_value1 <= 3'd7; end - a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1); + main_a7ddrphy_bitslip2_r1 <= {main_a7ddrphy_bitslip21, main_a7ddrphy_bitslip2_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip3_value0 <= (main_a7ddrphy_bitslip3_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip3_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip3_value0 <= 3'd7; end - a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1); + main_a7ddrphy_bitslip3_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[19], main_a7ddrphy_dfi_p3_wrdata[3], main_a7ddrphy_dfi_p2_wrdata[19], main_a7ddrphy_dfi_p2_wrdata[3], main_a7ddrphy_dfi_p1_wrdata[19], main_a7ddrphy_dfi_p1_wrdata[3], main_a7ddrphy_dfi_p0_wrdata[19], main_a7ddrphy_dfi_p0_wrdata[3]}, main_a7ddrphy_bitslip3_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip3_value1 <= (main_a7ddrphy_bitslip3_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip3_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip3_value1 <= 3'd7; end - a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1); + main_a7ddrphy_bitslip3_r1 <= {main_a7ddrphy_bitslip31, main_a7ddrphy_bitslip3_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip4_value0 <= (main_a7ddrphy_bitslip4_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip4_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip4_value0 <= 3'd7; end - a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1); + main_a7ddrphy_bitslip4_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[20], main_a7ddrphy_dfi_p3_wrdata[4], main_a7ddrphy_dfi_p2_wrdata[20], main_a7ddrphy_dfi_p2_wrdata[4], main_a7ddrphy_dfi_p1_wrdata[20], main_a7ddrphy_dfi_p1_wrdata[4], main_a7ddrphy_dfi_p0_wrdata[20], main_a7ddrphy_dfi_p0_wrdata[4]}, main_a7ddrphy_bitslip4_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip4_value1 <= (main_a7ddrphy_bitslip4_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip4_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip4_value1 <= 3'd7; end - a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1); + main_a7ddrphy_bitslip4_r1 <= {main_a7ddrphy_bitslip41, main_a7ddrphy_bitslip4_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip5_value0 <= (main_a7ddrphy_bitslip5_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip5_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip5_value0 <= 3'd7; end - a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1); + main_a7ddrphy_bitslip5_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[21], main_a7ddrphy_dfi_p3_wrdata[5], main_a7ddrphy_dfi_p2_wrdata[21], main_a7ddrphy_dfi_p2_wrdata[5], main_a7ddrphy_dfi_p1_wrdata[21], main_a7ddrphy_dfi_p1_wrdata[5], main_a7ddrphy_dfi_p0_wrdata[21], main_a7ddrphy_dfi_p0_wrdata[5]}, main_a7ddrphy_bitslip5_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip5_value1 <= (main_a7ddrphy_bitslip5_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip5_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip5_value1 <= 3'd7; end - a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1); + main_a7ddrphy_bitslip5_r1 <= {main_a7ddrphy_bitslip51, main_a7ddrphy_bitslip5_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip6_value0 <= (main_a7ddrphy_bitslip6_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip6_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip6_value0 <= 3'd7; end - a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1); + main_a7ddrphy_bitslip6_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[22], main_a7ddrphy_dfi_p3_wrdata[6], main_a7ddrphy_dfi_p2_wrdata[22], main_a7ddrphy_dfi_p2_wrdata[6], main_a7ddrphy_dfi_p1_wrdata[22], main_a7ddrphy_dfi_p1_wrdata[6], main_a7ddrphy_dfi_p0_wrdata[22], main_a7ddrphy_dfi_p0_wrdata[6]}, main_a7ddrphy_bitslip6_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip6_value1 <= (main_a7ddrphy_bitslip6_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip6_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip6_value1 <= 3'd7; end - a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1); + main_a7ddrphy_bitslip6_r1 <= {main_a7ddrphy_bitslip61, main_a7ddrphy_bitslip6_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip7_value0 <= (main_a7ddrphy_bitslip7_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip7_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip7_value0 <= 3'd7; end - a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1); + main_a7ddrphy_bitslip7_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[23], main_a7ddrphy_dfi_p3_wrdata[7], main_a7ddrphy_dfi_p2_wrdata[23], main_a7ddrphy_dfi_p2_wrdata[7], main_a7ddrphy_dfi_p1_wrdata[23], main_a7ddrphy_dfi_p1_wrdata[7], main_a7ddrphy_dfi_p0_wrdata[23], main_a7ddrphy_dfi_p0_wrdata[7]}, main_a7ddrphy_bitslip7_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip7_value1 <= (main_a7ddrphy_bitslip7_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip7_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip7_value1 <= 3'd7; end - a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1); + main_a7ddrphy_bitslip7_r1 <= {main_a7ddrphy_bitslip71, main_a7ddrphy_bitslip7_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip8_value0 <= (main_a7ddrphy_bitslip8_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip8_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip8_value0 <= 3'd7; end - a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1); + main_a7ddrphy_bitslip8_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[24], main_a7ddrphy_dfi_p3_wrdata[8], main_a7ddrphy_dfi_p2_wrdata[24], main_a7ddrphy_dfi_p2_wrdata[8], main_a7ddrphy_dfi_p1_wrdata[24], main_a7ddrphy_dfi_p1_wrdata[8], main_a7ddrphy_dfi_p0_wrdata[24], main_a7ddrphy_dfi_p0_wrdata[8]}, main_a7ddrphy_bitslip8_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip8_value1 <= (main_a7ddrphy_bitslip8_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip8_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip8_value1 <= 3'd7; end - a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1); + main_a7ddrphy_bitslip8_r1 <= {main_a7ddrphy_bitslip81, main_a7ddrphy_bitslip8_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip9_value0 <= (main_a7ddrphy_bitslip9_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip9_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip9_value0 <= 3'd7; end - a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1); + main_a7ddrphy_bitslip9_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[25], main_a7ddrphy_dfi_p3_wrdata[9], main_a7ddrphy_dfi_p2_wrdata[25], main_a7ddrphy_dfi_p2_wrdata[9], main_a7ddrphy_dfi_p1_wrdata[25], main_a7ddrphy_dfi_p1_wrdata[9], main_a7ddrphy_dfi_p0_wrdata[25], main_a7ddrphy_dfi_p0_wrdata[9]}, main_a7ddrphy_bitslip9_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip9_value1 <= (main_a7ddrphy_bitslip9_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip9_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip9_value1 <= 3'd7; end - a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1); + main_a7ddrphy_bitslip9_r1 <= {main_a7ddrphy_bitslip91, main_a7ddrphy_bitslip9_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip10_value0 <= (main_a7ddrphy_bitslip10_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip10_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip10_value0 <= 3'd7; end - a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1); + main_a7ddrphy_bitslip10_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[26], main_a7ddrphy_dfi_p3_wrdata[10], main_a7ddrphy_dfi_p2_wrdata[26], main_a7ddrphy_dfi_p2_wrdata[10], main_a7ddrphy_dfi_p1_wrdata[26], main_a7ddrphy_dfi_p1_wrdata[10], main_a7ddrphy_dfi_p0_wrdata[26], main_a7ddrphy_dfi_p0_wrdata[10]}, main_a7ddrphy_bitslip10_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip10_value1 <= (main_a7ddrphy_bitslip10_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip10_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip10_value1 <= 3'd7; end - a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1); + main_a7ddrphy_bitslip10_r1 <= {main_a7ddrphy_bitslip101, main_a7ddrphy_bitslip10_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip11_value0 <= (main_a7ddrphy_bitslip11_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip11_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip11_value0 <= 3'd7; end - a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1); + main_a7ddrphy_bitslip11_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[27], main_a7ddrphy_dfi_p3_wrdata[11], main_a7ddrphy_dfi_p2_wrdata[27], main_a7ddrphy_dfi_p2_wrdata[11], main_a7ddrphy_dfi_p1_wrdata[27], main_a7ddrphy_dfi_p1_wrdata[11], main_a7ddrphy_dfi_p0_wrdata[27], main_a7ddrphy_dfi_p0_wrdata[11]}, main_a7ddrphy_bitslip11_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip11_value1 <= (main_a7ddrphy_bitslip11_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip11_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip11_value1 <= 3'd7; end - a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1); + main_a7ddrphy_bitslip11_r1 <= {main_a7ddrphy_bitslip111, main_a7ddrphy_bitslip11_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip12_value0 <= (main_a7ddrphy_bitslip12_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip12_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip12_value0 <= 3'd7; end - a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1); + main_a7ddrphy_bitslip12_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[28], main_a7ddrphy_dfi_p3_wrdata[12], main_a7ddrphy_dfi_p2_wrdata[28], main_a7ddrphy_dfi_p2_wrdata[12], main_a7ddrphy_dfi_p1_wrdata[28], main_a7ddrphy_dfi_p1_wrdata[12], main_a7ddrphy_dfi_p0_wrdata[28], main_a7ddrphy_dfi_p0_wrdata[12]}, main_a7ddrphy_bitslip12_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip12_value1 <= (main_a7ddrphy_bitslip12_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip12_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip12_value1 <= 3'd7; end - a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1); + main_a7ddrphy_bitslip12_r1 <= {main_a7ddrphy_bitslip121, main_a7ddrphy_bitslip12_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip13_value0 <= (main_a7ddrphy_bitslip13_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip13_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip13_value0 <= 3'd7; end - a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1); + main_a7ddrphy_bitslip13_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[29], main_a7ddrphy_dfi_p3_wrdata[13], main_a7ddrphy_dfi_p2_wrdata[29], main_a7ddrphy_dfi_p2_wrdata[13], main_a7ddrphy_dfi_p1_wrdata[29], main_a7ddrphy_dfi_p1_wrdata[13], main_a7ddrphy_dfi_p0_wrdata[29], main_a7ddrphy_dfi_p0_wrdata[13]}, main_a7ddrphy_bitslip13_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip13_value1 <= (main_a7ddrphy_bitslip13_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip13_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip13_value1 <= 3'd7; end - a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1); + main_a7ddrphy_bitslip13_r1 <= {main_a7ddrphy_bitslip131, main_a7ddrphy_bitslip13_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip14_value0 <= (main_a7ddrphy_bitslip14_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip14_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip14_value0 <= 3'd7; end - a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1); + main_a7ddrphy_bitslip14_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[30], main_a7ddrphy_dfi_p3_wrdata[14], main_a7ddrphy_dfi_p2_wrdata[30], main_a7ddrphy_dfi_p2_wrdata[14], main_a7ddrphy_dfi_p1_wrdata[30], main_a7ddrphy_dfi_p1_wrdata[14], main_a7ddrphy_dfi_p0_wrdata[30], main_a7ddrphy_dfi_p0_wrdata[14]}, main_a7ddrphy_bitslip14_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip14_value1 <= (main_a7ddrphy_bitslip14_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip14_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip14_value1 <= 3'd7; end - a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1); + main_a7ddrphy_bitslip14_r1 <= {main_a7ddrphy_bitslip141, main_a7ddrphy_bitslip14_r1[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip15_value0 <= (main_a7ddrphy_bitslip15_value0 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip15_value0 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip15_value0 <= 3'd7; end - a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1); + main_a7ddrphy_bitslip15_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[31], main_a7ddrphy_dfi_p3_wrdata[15], main_a7ddrphy_dfi_p2_wrdata[31], main_a7ddrphy_dfi_p2_wrdata[15], main_a7ddrphy_dfi_p1_wrdata[31], main_a7ddrphy_dfi_p1_wrdata[15], main_a7ddrphy_dfi_p0_wrdata[31], main_a7ddrphy_dfi_p0_wrdata[15]}, main_a7ddrphy_bitslip15_r0[15:8]}; + if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin + main_a7ddrphy_bitslip15_value1 <= (main_a7ddrphy_bitslip15_value1 + 1'd1); end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip15_value1 <= 3'd7; + if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin + main_a7ddrphy_bitslip15_value1 <= 3'd7; end - a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]}; - a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en); - a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0; - a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1; - a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2; - a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3; - a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4; - a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5; - a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6; - a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en); - a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0; - a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1; - if (litedramcore_csr_dfi_p0_rddata_valid) begin - litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata; + main_a7ddrphy_bitslip15_r1 <= {main_a7ddrphy_bitslip151, main_a7ddrphy_bitslip15_r1[15:8]}; + main_a7ddrphy_rddata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_rddata_en | main_a7ddrphy_dfi_p1_rddata_en) | main_a7ddrphy_dfi_p2_rddata_en) | main_a7ddrphy_dfi_p3_rddata_en); + main_a7ddrphy_rddata_en_tappeddelayline1 <= main_a7ddrphy_rddata_en_tappeddelayline0; + main_a7ddrphy_rddata_en_tappeddelayline2 <= main_a7ddrphy_rddata_en_tappeddelayline1; + main_a7ddrphy_rddata_en_tappeddelayline3 <= main_a7ddrphy_rddata_en_tappeddelayline2; + main_a7ddrphy_rddata_en_tappeddelayline4 <= main_a7ddrphy_rddata_en_tappeddelayline3; + main_a7ddrphy_rddata_en_tappeddelayline5 <= main_a7ddrphy_rddata_en_tappeddelayline4; + main_a7ddrphy_rddata_en_tappeddelayline6 <= main_a7ddrphy_rddata_en_tappeddelayline5; + main_a7ddrphy_rddata_en_tappeddelayline7 <= main_a7ddrphy_rddata_en_tappeddelayline6; + main_a7ddrphy_wrdata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_wrdata_en | main_a7ddrphy_dfi_p1_wrdata_en) | main_a7ddrphy_dfi_p2_wrdata_en) | main_a7ddrphy_dfi_p3_wrdata_en); + main_a7ddrphy_wrdata_en_tappeddelayline1 <= main_a7ddrphy_wrdata_en_tappeddelayline0; + main_a7ddrphy_wrdata_en_tappeddelayline2 <= main_a7ddrphy_wrdata_en_tappeddelayline1; + if (main_litedramcore_csr_dfi_p0_rddata_valid) begin + main_litedramcore_phaseinjector0_rddata_status <= main_litedramcore_csr_dfi_p0_rddata; end - if (litedramcore_csr_dfi_p1_rddata_valid) begin - litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata; + if (main_litedramcore_csr_dfi_p1_rddata_valid) begin + main_litedramcore_phaseinjector1_rddata_status <= main_litedramcore_csr_dfi_p1_rddata; end - if (litedramcore_csr_dfi_p2_rddata_valid) begin - litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata; + if (main_litedramcore_csr_dfi_p2_rddata_valid) begin + main_litedramcore_phaseinjector2_rddata_status <= main_litedramcore_csr_dfi_p2_rddata; end - if (litedramcore_csr_dfi_p3_rddata_valid) begin - litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata; - end - if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin - litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); + if (main_litedramcore_csr_dfi_p3_rddata_valid) begin + main_litedramcore_phaseinjector3_rddata_status <= main_litedramcore_csr_dfi_p3_rddata; + end + if ((main_litedramcore_timer_wait & (~main_litedramcore_timer_done0))) begin + main_litedramcore_timer_count1 <= (main_litedramcore_timer_count1 - 1'd1); end else begin - litedramcore_timer_count1 <= 10'd781; + main_litedramcore_timer_count1 <= 10'd781; end - litedramcore_postponer_req_o <= 1'd0; - if (litedramcore_postponer_req_i) begin - litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); - if ((litedramcore_postponer_count == 1'd0)) begin - litedramcore_postponer_count <= 1'd0; - litedramcore_postponer_req_o <= 1'd1; - end + main_litedramcore_postponer_req_o <= 1'd0; + if (main_litedramcore_postponer_req_i) begin + main_litedramcore_postponer_count <= (main_litedramcore_postponer_count - 1'd1); + if ((main_litedramcore_postponer_count == 1'd0)) begin + main_litedramcore_postponer_count <= 1'd0; + main_litedramcore_postponer_req_o <= 1'd1; + end end - if (litedramcore_sequencer_start0) begin - litedramcore_sequencer_count <= 1'd0; - end else begin - if (litedramcore_sequencer_done1) begin - if ((litedramcore_sequencer_count != 1'd0)) begin - litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); - end - end - end - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_sequencer_done1 <= 1'd0; - if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_sequencer_counter == 2'd3)) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd1; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd0; - end - if ((litedramcore_sequencer_counter == 6'd35)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_sequencer_done1 <= 1'd1; - end - if ((litedramcore_sequencer_counter == 6'd35)) begin - litedramcore_sequencer_counter <= 1'd0; - end else begin - if ((litedramcore_sequencer_counter != 1'd0)) begin - litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1); + if (main_litedramcore_sequencer_start0) begin + main_litedramcore_sequencer_count <= 1'd0; + end else begin + if (main_litedramcore_sequencer_done1) begin + if ((main_litedramcore_sequencer_count != 1'd0)) begin + main_litedramcore_sequencer_count <= (main_litedramcore_sequencer_count - 1'd1); + end + end + end + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd0; + if ((main_litedramcore_sequencer_start1 & (main_litedramcore_sequencer_trigger == 1'd0))) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_sequencer_trigger == 2'd3)) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd1; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd0; + end + if ((main_litedramcore_sequencer_trigger == 6'd35)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd1; + end + if ((main_litedramcore_sequencer_trigger == 6'd35)) begin + main_litedramcore_sequencer_trigger <= 1'd0; + end else begin + if ((main_litedramcore_sequencer_trigger != 1'd0)) begin + main_litedramcore_sequencer_trigger <= (main_litedramcore_sequencer_trigger + 1'd1); end else begin - if (litedramcore_sequencer_start1) begin - litedramcore_sequencer_counter <= 1'd1; + if (main_litedramcore_sequencer_start1) begin + main_litedramcore_sequencer_trigger <= 1'd1; end end end - if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin - litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); + if ((main_litedramcore_zqcs_timer_wait & (~main_litedramcore_zqcs_timer_done0))) begin + main_litedramcore_zqcs_timer_count1 <= (main_litedramcore_zqcs_timer_count1 - 1'd1); end else begin - litedramcore_zqcs_timer_count1 <= 27'd99999999; - end - litedramcore_zqcs_executer_done <= 1'd0; - if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 2'd3)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 5'd19)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_zqcs_executer_done <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 5'd19)) begin - litedramcore_zqcs_executer_counter <= 1'd0; + main_litedramcore_zqcs_timer_count1 <= 27'd99999999; + end + main_litedramcore_zqcs_executer_done <= 1'd0; + if ((main_litedramcore_zqcs_executer_start & (main_litedramcore_zqcs_executer_trigger == 1'd0))) begin + main_litedramcore_cmd_payload_a <= 11'd1024; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd1; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_trigger == 2'd3)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_trigger == 5'd19)) begin + main_litedramcore_cmd_payload_a <= 1'd0; + main_litedramcore_cmd_payload_ba <= 1'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_zqcs_executer_done <= 1'd1; + end + if ((main_litedramcore_zqcs_executer_trigger == 5'd19)) begin + main_litedramcore_zqcs_executer_trigger <= 1'd0; end else begin - if ((litedramcore_zqcs_executer_counter != 1'd0)) begin - litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1); + if ((main_litedramcore_zqcs_executer_trigger != 1'd0)) begin + main_litedramcore_zqcs_executer_trigger <= (main_litedramcore_zqcs_executer_trigger + 1'd1); end else begin - if (litedramcore_zqcs_executer_start) begin - litedramcore_zqcs_executer_counter <= 1'd1; + if (main_litedramcore_zqcs_executer_start) begin + main_litedramcore_zqcs_executer_trigger <= 1'd1; end end end - litedramcore_refresher_state <= litedramcore_refresher_next_state; - if (litedramcore_bankmachine0_row_close) begin - litedramcore_bankmachine0_row_opened <= 1'd0; + builder_refresher_state <= builder_refresher_next_state; + if (main_litedramcore_bankmachine0_row_close) begin + main_litedramcore_bankmachine0_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine0_row_open) begin - litedramcore_bankmachine0_row_opened <= 1'd1; - litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[20:7]; + if (main_litedramcore_bankmachine0_row_open) begin + main_litedramcore_bankmachine0_row_opened <= 1'd1; + main_litedramcore_bankmachine0_row <= main_litedramcore_bankmachine0_source_source_payload_addr[20:7]; end end - if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin - litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1); + if (((main_litedramcore_bankmachine0_syncfifo0_we & main_litedramcore_bankmachine0_syncfifo0_writable) & (~main_litedramcore_bankmachine0_replace))) begin + main_litedramcore_bankmachine0_produce <= (main_litedramcore_bankmachine0_produce + 1'd1); end - if (litedramcore_bankmachine0_do_read) begin - litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1); + if (main_litedramcore_bankmachine0_do_read) begin + main_litedramcore_bankmachine0_consume <= (main_litedramcore_bankmachine0_consume + 1'd1); end - if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin - if ((~litedramcore_bankmachine0_do_read)) begin - litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1); + if (((main_litedramcore_bankmachine0_syncfifo0_we & main_litedramcore_bankmachine0_syncfifo0_writable) & (~main_litedramcore_bankmachine0_replace))) begin + if ((~main_litedramcore_bankmachine0_do_read)) begin + main_litedramcore_bankmachine0_level <= (main_litedramcore_bankmachine0_level + 1'd1); end end else begin - if (litedramcore_bankmachine0_do_read) begin - litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1); + if (main_litedramcore_bankmachine0_do_read) begin + main_litedramcore_bankmachine0_level <= (main_litedramcore_bankmachine0_level - 1'd1); end end - if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin - litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid; - litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first; - litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last; - litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we; - litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine0_pipe_valid_source_valid) | main_litedramcore_bankmachine0_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine0_pipe_valid_source_valid <= main_litedramcore_bankmachine0_pipe_valid_sink_valid; + main_litedramcore_bankmachine0_pipe_valid_source_first <= main_litedramcore_bankmachine0_pipe_valid_sink_first; + main_litedramcore_bankmachine0_pipe_valid_source_last <= main_litedramcore_bankmachine0_pipe_valid_sink_last; + main_litedramcore_bankmachine0_pipe_valid_source_payload_we <= main_litedramcore_bankmachine0_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine0_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine0_twtpcon_valid) begin - litedramcore_bankmachine0_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine0_twtpcon_valid) begin + main_litedramcore_bankmachine0_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine0_twtpcon_ready)) begin - litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_twtpcon_ready)) begin + main_litedramcore_bankmachine0_twtpcon_count <= (main_litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine0_trccon_valid) begin - litedramcore_bankmachine0_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine0_trccon_valid) begin + main_litedramcore_bankmachine0_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine0_trccon_ready <= 1'd1; + main_litedramcore_bankmachine0_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine0_trccon_ready <= 1'd0; + main_litedramcore_bankmachine0_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine0_trccon_ready)) begin - litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); - if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin - litedramcore_bankmachine0_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_trccon_ready)) begin + main_litedramcore_bankmachine0_trccon_count <= (main_litedramcore_bankmachine0_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine0_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine0_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine0_trascon_valid) begin - litedramcore_bankmachine0_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine0_trascon_valid) begin + main_litedramcore_bankmachine0_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine0_trascon_ready <= 1'd1; + main_litedramcore_bankmachine0_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine0_trascon_ready <= 1'd0; + main_litedramcore_bankmachine0_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); - if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin - litedramcore_bankmachine0_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_trascon_count <= (main_litedramcore_bankmachine0_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine0_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine0_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state; - if (litedramcore_bankmachine1_row_close) begin - litedramcore_bankmachine1_row_opened <= 1'd0; + builder_bankmachine0_state <= builder_bankmachine0_next_state; + if (main_litedramcore_bankmachine1_row_close) begin + main_litedramcore_bankmachine1_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine1_row_open) begin - litedramcore_bankmachine1_row_opened <= 1'd1; - litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[20:7]; + if (main_litedramcore_bankmachine1_row_open) begin + main_litedramcore_bankmachine1_row_opened <= 1'd1; + main_litedramcore_bankmachine1_row <= main_litedramcore_bankmachine1_source_source_payload_addr[20:7]; end end - if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin - litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1); + if (((main_litedramcore_bankmachine1_syncfifo1_we & main_litedramcore_bankmachine1_syncfifo1_writable) & (~main_litedramcore_bankmachine1_replace))) begin + main_litedramcore_bankmachine1_produce <= (main_litedramcore_bankmachine1_produce + 1'd1); end - if (litedramcore_bankmachine1_do_read) begin - litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1); + if (main_litedramcore_bankmachine1_do_read) begin + main_litedramcore_bankmachine1_consume <= (main_litedramcore_bankmachine1_consume + 1'd1); end - if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin - if ((~litedramcore_bankmachine1_do_read)) begin - litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1); + if (((main_litedramcore_bankmachine1_syncfifo1_we & main_litedramcore_bankmachine1_syncfifo1_writable) & (~main_litedramcore_bankmachine1_replace))) begin + if ((~main_litedramcore_bankmachine1_do_read)) begin + main_litedramcore_bankmachine1_level <= (main_litedramcore_bankmachine1_level + 1'd1); end end else begin - if (litedramcore_bankmachine1_do_read) begin - litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1); + if (main_litedramcore_bankmachine1_do_read) begin + main_litedramcore_bankmachine1_level <= (main_litedramcore_bankmachine1_level - 1'd1); end end - if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin - litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid; - litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first; - litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last; - litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we; - litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine1_pipe_valid_source_valid) | main_litedramcore_bankmachine1_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine1_pipe_valid_source_valid <= main_litedramcore_bankmachine1_pipe_valid_sink_valid; + main_litedramcore_bankmachine1_pipe_valid_source_first <= main_litedramcore_bankmachine1_pipe_valid_sink_first; + main_litedramcore_bankmachine1_pipe_valid_source_last <= main_litedramcore_bankmachine1_pipe_valid_sink_last; + main_litedramcore_bankmachine1_pipe_valid_source_payload_we <= main_litedramcore_bankmachine1_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine1_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine1_twtpcon_valid) begin - litedramcore_bankmachine1_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine1_twtpcon_valid) begin + main_litedramcore_bankmachine1_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine1_twtpcon_ready)) begin - litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_twtpcon_ready)) begin + main_litedramcore_bankmachine1_twtpcon_count <= (main_litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine1_trccon_valid) begin - litedramcore_bankmachine1_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine1_trccon_valid) begin + main_litedramcore_bankmachine1_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine1_trccon_ready <= 1'd1; + main_litedramcore_bankmachine1_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine1_trccon_ready <= 1'd0; + main_litedramcore_bankmachine1_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine1_trccon_ready)) begin - litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); - if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin - litedramcore_bankmachine1_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_trccon_ready)) begin + main_litedramcore_bankmachine1_trccon_count <= (main_litedramcore_bankmachine1_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine1_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine1_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine1_trascon_valid) begin - litedramcore_bankmachine1_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine1_trascon_valid) begin + main_litedramcore_bankmachine1_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine1_trascon_ready <= 1'd1; + main_litedramcore_bankmachine1_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine1_trascon_ready <= 1'd0; + main_litedramcore_bankmachine1_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); - if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin - litedramcore_bankmachine1_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_trascon_count <= (main_litedramcore_bankmachine1_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine1_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine1_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state; - if (litedramcore_bankmachine2_row_close) begin - litedramcore_bankmachine2_row_opened <= 1'd0; + builder_bankmachine1_state <= builder_bankmachine1_next_state; + if (main_litedramcore_bankmachine2_row_close) begin + main_litedramcore_bankmachine2_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine2_row_open) begin - litedramcore_bankmachine2_row_opened <= 1'd1; - litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[20:7]; + if (main_litedramcore_bankmachine2_row_open) begin + main_litedramcore_bankmachine2_row_opened <= 1'd1; + main_litedramcore_bankmachine2_row <= main_litedramcore_bankmachine2_source_source_payload_addr[20:7]; end end - if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin - litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1); + if (((main_litedramcore_bankmachine2_syncfifo2_we & main_litedramcore_bankmachine2_syncfifo2_writable) & (~main_litedramcore_bankmachine2_replace))) begin + main_litedramcore_bankmachine2_produce <= (main_litedramcore_bankmachine2_produce + 1'd1); end - if (litedramcore_bankmachine2_do_read) begin - litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1); + if (main_litedramcore_bankmachine2_do_read) begin + main_litedramcore_bankmachine2_consume <= (main_litedramcore_bankmachine2_consume + 1'd1); end - if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin - if ((~litedramcore_bankmachine2_do_read)) begin - litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1); + if (((main_litedramcore_bankmachine2_syncfifo2_we & main_litedramcore_bankmachine2_syncfifo2_writable) & (~main_litedramcore_bankmachine2_replace))) begin + if ((~main_litedramcore_bankmachine2_do_read)) begin + main_litedramcore_bankmachine2_level <= (main_litedramcore_bankmachine2_level + 1'd1); end end else begin - if (litedramcore_bankmachine2_do_read) begin - litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1); + if (main_litedramcore_bankmachine2_do_read) begin + main_litedramcore_bankmachine2_level <= (main_litedramcore_bankmachine2_level - 1'd1); end end - if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin - litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid; - litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first; - litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last; - litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we; - litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine2_pipe_valid_source_valid) | main_litedramcore_bankmachine2_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine2_pipe_valid_source_valid <= main_litedramcore_bankmachine2_pipe_valid_sink_valid; + main_litedramcore_bankmachine2_pipe_valid_source_first <= main_litedramcore_bankmachine2_pipe_valid_sink_first; + main_litedramcore_bankmachine2_pipe_valid_source_last <= main_litedramcore_bankmachine2_pipe_valid_sink_last; + main_litedramcore_bankmachine2_pipe_valid_source_payload_we <= main_litedramcore_bankmachine2_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine2_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine2_twtpcon_valid) begin - litedramcore_bankmachine2_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine2_twtpcon_valid) begin + main_litedramcore_bankmachine2_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine2_twtpcon_ready)) begin - litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_twtpcon_ready)) begin + main_litedramcore_bankmachine2_twtpcon_count <= (main_litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine2_trccon_valid) begin - litedramcore_bankmachine2_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine2_trccon_valid) begin + main_litedramcore_bankmachine2_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine2_trccon_ready <= 1'd1; + main_litedramcore_bankmachine2_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine2_trccon_ready <= 1'd0; + main_litedramcore_bankmachine2_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine2_trccon_ready)) begin - litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); - if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin - litedramcore_bankmachine2_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_trccon_ready)) begin + main_litedramcore_bankmachine2_trccon_count <= (main_litedramcore_bankmachine2_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine2_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine2_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine2_trascon_valid) begin - litedramcore_bankmachine2_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine2_trascon_valid) begin + main_litedramcore_bankmachine2_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine2_trascon_ready <= 1'd1; + main_litedramcore_bankmachine2_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine2_trascon_ready <= 1'd0; + main_litedramcore_bankmachine2_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); - if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin - litedramcore_bankmachine2_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_trascon_count <= (main_litedramcore_bankmachine2_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine2_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine2_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state; - if (litedramcore_bankmachine3_row_close) begin - litedramcore_bankmachine3_row_opened <= 1'd0; + builder_bankmachine2_state <= builder_bankmachine2_next_state; + if (main_litedramcore_bankmachine3_row_close) begin + main_litedramcore_bankmachine3_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine3_row_open) begin - litedramcore_bankmachine3_row_opened <= 1'd1; - litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[20:7]; + if (main_litedramcore_bankmachine3_row_open) begin + main_litedramcore_bankmachine3_row_opened <= 1'd1; + main_litedramcore_bankmachine3_row <= main_litedramcore_bankmachine3_source_source_payload_addr[20:7]; end end - if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin - litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1); + if (((main_litedramcore_bankmachine3_syncfifo3_we & main_litedramcore_bankmachine3_syncfifo3_writable) & (~main_litedramcore_bankmachine3_replace))) begin + main_litedramcore_bankmachine3_produce <= (main_litedramcore_bankmachine3_produce + 1'd1); end - if (litedramcore_bankmachine3_do_read) begin - litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1); + if (main_litedramcore_bankmachine3_do_read) begin + main_litedramcore_bankmachine3_consume <= (main_litedramcore_bankmachine3_consume + 1'd1); end - if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin - if ((~litedramcore_bankmachine3_do_read)) begin - litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1); + if (((main_litedramcore_bankmachine3_syncfifo3_we & main_litedramcore_bankmachine3_syncfifo3_writable) & (~main_litedramcore_bankmachine3_replace))) begin + if ((~main_litedramcore_bankmachine3_do_read)) begin + main_litedramcore_bankmachine3_level <= (main_litedramcore_bankmachine3_level + 1'd1); end end else begin - if (litedramcore_bankmachine3_do_read) begin - litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1); + if (main_litedramcore_bankmachine3_do_read) begin + main_litedramcore_bankmachine3_level <= (main_litedramcore_bankmachine3_level - 1'd1); end end - if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin - litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid; - litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first; - litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last; - litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we; - litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine3_pipe_valid_source_valid) | main_litedramcore_bankmachine3_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine3_pipe_valid_source_valid <= main_litedramcore_bankmachine3_pipe_valid_sink_valid; + main_litedramcore_bankmachine3_pipe_valid_source_first <= main_litedramcore_bankmachine3_pipe_valid_sink_first; + main_litedramcore_bankmachine3_pipe_valid_source_last <= main_litedramcore_bankmachine3_pipe_valid_sink_last; + main_litedramcore_bankmachine3_pipe_valid_source_payload_we <= main_litedramcore_bankmachine3_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine3_twtpcon_valid) begin - litedramcore_bankmachine3_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine3_twtpcon_valid) begin + main_litedramcore_bankmachine3_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine3_twtpcon_ready)) begin - litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_twtpcon_ready)) begin + main_litedramcore_bankmachine3_twtpcon_count <= (main_litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine3_trccon_valid) begin - litedramcore_bankmachine3_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine3_trccon_valid) begin + main_litedramcore_bankmachine3_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine3_trccon_ready <= 1'd1; + main_litedramcore_bankmachine3_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine3_trccon_ready <= 1'd0; + main_litedramcore_bankmachine3_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine3_trccon_ready)) begin - litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); - if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin - litedramcore_bankmachine3_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_trccon_ready)) begin + main_litedramcore_bankmachine3_trccon_count <= (main_litedramcore_bankmachine3_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine3_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine3_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine3_trascon_valid) begin - litedramcore_bankmachine3_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine3_trascon_valid) begin + main_litedramcore_bankmachine3_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine3_trascon_ready <= 1'd1; + main_litedramcore_bankmachine3_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine3_trascon_ready <= 1'd0; + main_litedramcore_bankmachine3_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); - if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin - litedramcore_bankmachine3_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_trascon_count <= (main_litedramcore_bankmachine3_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine3_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine3_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state; - if (litedramcore_bankmachine4_row_close) begin - litedramcore_bankmachine4_row_opened <= 1'd0; + builder_bankmachine3_state <= builder_bankmachine3_next_state; + if (main_litedramcore_bankmachine4_row_close) begin + main_litedramcore_bankmachine4_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine4_row_open) begin - litedramcore_bankmachine4_row_opened <= 1'd1; - litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[20:7]; + if (main_litedramcore_bankmachine4_row_open) begin + main_litedramcore_bankmachine4_row_opened <= 1'd1; + main_litedramcore_bankmachine4_row <= main_litedramcore_bankmachine4_source_source_payload_addr[20:7]; end end - if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin - litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1); + if (((main_litedramcore_bankmachine4_syncfifo4_we & main_litedramcore_bankmachine4_syncfifo4_writable) & (~main_litedramcore_bankmachine4_replace))) begin + main_litedramcore_bankmachine4_produce <= (main_litedramcore_bankmachine4_produce + 1'd1); end - if (litedramcore_bankmachine4_do_read) begin - litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1); + if (main_litedramcore_bankmachine4_do_read) begin + main_litedramcore_bankmachine4_consume <= (main_litedramcore_bankmachine4_consume + 1'd1); end - if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin - if ((~litedramcore_bankmachine4_do_read)) begin - litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1); + if (((main_litedramcore_bankmachine4_syncfifo4_we & main_litedramcore_bankmachine4_syncfifo4_writable) & (~main_litedramcore_bankmachine4_replace))) begin + if ((~main_litedramcore_bankmachine4_do_read)) begin + main_litedramcore_bankmachine4_level <= (main_litedramcore_bankmachine4_level + 1'd1); end end else begin - if (litedramcore_bankmachine4_do_read) begin - litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1); + if (main_litedramcore_bankmachine4_do_read) begin + main_litedramcore_bankmachine4_level <= (main_litedramcore_bankmachine4_level - 1'd1); end end - if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin - litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid; - litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first; - litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last; - litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we; - litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine4_pipe_valid_source_valid) | main_litedramcore_bankmachine4_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine4_pipe_valid_source_valid <= main_litedramcore_bankmachine4_pipe_valid_sink_valid; + main_litedramcore_bankmachine4_pipe_valid_source_first <= main_litedramcore_bankmachine4_pipe_valid_sink_first; + main_litedramcore_bankmachine4_pipe_valid_source_last <= main_litedramcore_bankmachine4_pipe_valid_sink_last; + main_litedramcore_bankmachine4_pipe_valid_source_payload_we <= main_litedramcore_bankmachine4_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine4_twtpcon_valid) begin - litedramcore_bankmachine4_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine4_twtpcon_valid) begin + main_litedramcore_bankmachine4_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine4_twtpcon_ready)) begin - litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_twtpcon_ready)) begin + main_litedramcore_bankmachine4_twtpcon_count <= (main_litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine4_trccon_valid) begin - litedramcore_bankmachine4_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine4_trccon_valid) begin + main_litedramcore_bankmachine4_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine4_trccon_ready <= 1'd1; + main_litedramcore_bankmachine4_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine4_trccon_ready <= 1'd0; + main_litedramcore_bankmachine4_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine4_trccon_ready)) begin - litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); - if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin - litedramcore_bankmachine4_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_trccon_ready)) begin + main_litedramcore_bankmachine4_trccon_count <= (main_litedramcore_bankmachine4_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine4_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine4_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine4_trascon_valid) begin - litedramcore_bankmachine4_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine4_trascon_valid) begin + main_litedramcore_bankmachine4_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine4_trascon_ready <= 1'd1; + main_litedramcore_bankmachine4_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine4_trascon_ready <= 1'd0; + main_litedramcore_bankmachine4_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); - if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin - litedramcore_bankmachine4_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_trascon_count <= (main_litedramcore_bankmachine4_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine4_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine4_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state; - if (litedramcore_bankmachine5_row_close) begin - litedramcore_bankmachine5_row_opened <= 1'd0; + builder_bankmachine4_state <= builder_bankmachine4_next_state; + if (main_litedramcore_bankmachine5_row_close) begin + main_litedramcore_bankmachine5_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine5_row_open) begin - litedramcore_bankmachine5_row_opened <= 1'd1; - litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[20:7]; + if (main_litedramcore_bankmachine5_row_open) begin + main_litedramcore_bankmachine5_row_opened <= 1'd1; + main_litedramcore_bankmachine5_row <= main_litedramcore_bankmachine5_source_source_payload_addr[20:7]; end end - if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin - litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1); + if (((main_litedramcore_bankmachine5_syncfifo5_we & main_litedramcore_bankmachine5_syncfifo5_writable) & (~main_litedramcore_bankmachine5_replace))) begin + main_litedramcore_bankmachine5_produce <= (main_litedramcore_bankmachine5_produce + 1'd1); end - if (litedramcore_bankmachine5_do_read) begin - litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1); + if (main_litedramcore_bankmachine5_do_read) begin + main_litedramcore_bankmachine5_consume <= (main_litedramcore_bankmachine5_consume + 1'd1); end - if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin - if ((~litedramcore_bankmachine5_do_read)) begin - litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1); + if (((main_litedramcore_bankmachine5_syncfifo5_we & main_litedramcore_bankmachine5_syncfifo5_writable) & (~main_litedramcore_bankmachine5_replace))) begin + if ((~main_litedramcore_bankmachine5_do_read)) begin + main_litedramcore_bankmachine5_level <= (main_litedramcore_bankmachine5_level + 1'd1); end end else begin - if (litedramcore_bankmachine5_do_read) begin - litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1); + if (main_litedramcore_bankmachine5_do_read) begin + main_litedramcore_bankmachine5_level <= (main_litedramcore_bankmachine5_level - 1'd1); end end - if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin - litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid; - litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first; - litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last; - litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we; - litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine5_pipe_valid_source_valid) | main_litedramcore_bankmachine5_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine5_pipe_valid_source_valid <= main_litedramcore_bankmachine5_pipe_valid_sink_valid; + main_litedramcore_bankmachine5_pipe_valid_source_first <= main_litedramcore_bankmachine5_pipe_valid_sink_first; + main_litedramcore_bankmachine5_pipe_valid_source_last <= main_litedramcore_bankmachine5_pipe_valid_sink_last; + main_litedramcore_bankmachine5_pipe_valid_source_payload_we <= main_litedramcore_bankmachine5_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine5_twtpcon_valid) begin - litedramcore_bankmachine5_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine5_twtpcon_valid) begin + main_litedramcore_bankmachine5_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine5_twtpcon_ready)) begin - litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_twtpcon_ready)) begin + main_litedramcore_bankmachine5_twtpcon_count <= (main_litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine5_trccon_valid) begin - litedramcore_bankmachine5_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine5_trccon_valid) begin + main_litedramcore_bankmachine5_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine5_trccon_ready <= 1'd1; + main_litedramcore_bankmachine5_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine5_trccon_ready <= 1'd0; + main_litedramcore_bankmachine5_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine5_trccon_ready)) begin - litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); - if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin - litedramcore_bankmachine5_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_trccon_ready)) begin + main_litedramcore_bankmachine5_trccon_count <= (main_litedramcore_bankmachine5_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine5_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine5_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine5_trascon_valid) begin - litedramcore_bankmachine5_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine5_trascon_valid) begin + main_litedramcore_bankmachine5_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine5_trascon_ready <= 1'd1; + main_litedramcore_bankmachine5_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine5_trascon_ready <= 1'd0; + main_litedramcore_bankmachine5_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); - if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin - litedramcore_bankmachine5_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_trascon_count <= (main_litedramcore_bankmachine5_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine5_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine5_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state; - if (litedramcore_bankmachine6_row_close) begin - litedramcore_bankmachine6_row_opened <= 1'd0; + builder_bankmachine5_state <= builder_bankmachine5_next_state; + if (main_litedramcore_bankmachine6_row_close) begin + main_litedramcore_bankmachine6_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine6_row_open) begin - litedramcore_bankmachine6_row_opened <= 1'd1; - litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[20:7]; + if (main_litedramcore_bankmachine6_row_open) begin + main_litedramcore_bankmachine6_row_opened <= 1'd1; + main_litedramcore_bankmachine6_row <= main_litedramcore_bankmachine6_source_source_payload_addr[20:7]; end end - if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin - litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1); + if (((main_litedramcore_bankmachine6_syncfifo6_we & main_litedramcore_bankmachine6_syncfifo6_writable) & (~main_litedramcore_bankmachine6_replace))) begin + main_litedramcore_bankmachine6_produce <= (main_litedramcore_bankmachine6_produce + 1'd1); end - if (litedramcore_bankmachine6_do_read) begin - litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1); + if (main_litedramcore_bankmachine6_do_read) begin + main_litedramcore_bankmachine6_consume <= (main_litedramcore_bankmachine6_consume + 1'd1); end - if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin - if ((~litedramcore_bankmachine6_do_read)) begin - litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1); + if (((main_litedramcore_bankmachine6_syncfifo6_we & main_litedramcore_bankmachine6_syncfifo6_writable) & (~main_litedramcore_bankmachine6_replace))) begin + if ((~main_litedramcore_bankmachine6_do_read)) begin + main_litedramcore_bankmachine6_level <= (main_litedramcore_bankmachine6_level + 1'd1); end end else begin - if (litedramcore_bankmachine6_do_read) begin - litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1); + if (main_litedramcore_bankmachine6_do_read) begin + main_litedramcore_bankmachine6_level <= (main_litedramcore_bankmachine6_level - 1'd1); end end - if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin - litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid; - litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first; - litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last; - litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we; - litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine6_pipe_valid_source_valid) | main_litedramcore_bankmachine6_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine6_pipe_valid_source_valid <= main_litedramcore_bankmachine6_pipe_valid_sink_valid; + main_litedramcore_bankmachine6_pipe_valid_source_first <= main_litedramcore_bankmachine6_pipe_valid_sink_first; + main_litedramcore_bankmachine6_pipe_valid_source_last <= main_litedramcore_bankmachine6_pipe_valid_sink_last; + main_litedramcore_bankmachine6_pipe_valid_source_payload_we <= main_litedramcore_bankmachine6_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine6_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine6_twtpcon_valid) begin - litedramcore_bankmachine6_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine6_twtpcon_valid) begin + main_litedramcore_bankmachine6_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine6_twtpcon_ready)) begin - litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_twtpcon_ready)) begin + main_litedramcore_bankmachine6_twtpcon_count <= (main_litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine6_trccon_valid) begin - litedramcore_bankmachine6_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine6_trccon_valid) begin + main_litedramcore_bankmachine6_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine6_trccon_ready <= 1'd1; + main_litedramcore_bankmachine6_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine6_trccon_ready <= 1'd0; + main_litedramcore_bankmachine6_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine6_trccon_ready)) begin - litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); - if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin - litedramcore_bankmachine6_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_trccon_ready)) begin + main_litedramcore_bankmachine6_trccon_count <= (main_litedramcore_bankmachine6_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine6_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine6_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine6_trascon_valid) begin - litedramcore_bankmachine6_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine6_trascon_valid) begin + main_litedramcore_bankmachine6_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine6_trascon_ready <= 1'd1; + main_litedramcore_bankmachine6_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine6_trascon_ready <= 1'd0; + main_litedramcore_bankmachine6_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); - if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin - litedramcore_bankmachine6_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_trascon_count <= (main_litedramcore_bankmachine6_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine6_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine6_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state; - if (litedramcore_bankmachine7_row_close) begin - litedramcore_bankmachine7_row_opened <= 1'd0; + builder_bankmachine6_state <= builder_bankmachine6_next_state; + if (main_litedramcore_bankmachine7_row_close) begin + main_litedramcore_bankmachine7_row_opened <= 1'd0; end else begin - if (litedramcore_bankmachine7_row_open) begin - litedramcore_bankmachine7_row_opened <= 1'd1; - litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[20:7]; + if (main_litedramcore_bankmachine7_row_open) begin + main_litedramcore_bankmachine7_row_opened <= 1'd1; + main_litedramcore_bankmachine7_row <= main_litedramcore_bankmachine7_source_source_payload_addr[20:7]; end end - if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin - litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1); + if (((main_litedramcore_bankmachine7_syncfifo7_we & main_litedramcore_bankmachine7_syncfifo7_writable) & (~main_litedramcore_bankmachine7_replace))) begin + main_litedramcore_bankmachine7_produce <= (main_litedramcore_bankmachine7_produce + 1'd1); end - if (litedramcore_bankmachine7_do_read) begin - litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1); + if (main_litedramcore_bankmachine7_do_read) begin + main_litedramcore_bankmachine7_consume <= (main_litedramcore_bankmachine7_consume + 1'd1); end - if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin - if ((~litedramcore_bankmachine7_do_read)) begin - litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1); + if (((main_litedramcore_bankmachine7_syncfifo7_we & main_litedramcore_bankmachine7_syncfifo7_writable) & (~main_litedramcore_bankmachine7_replace))) begin + if ((~main_litedramcore_bankmachine7_do_read)) begin + main_litedramcore_bankmachine7_level <= (main_litedramcore_bankmachine7_level + 1'd1); end end else begin - if (litedramcore_bankmachine7_do_read) begin - litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1); + if (main_litedramcore_bankmachine7_do_read) begin + main_litedramcore_bankmachine7_level <= (main_litedramcore_bankmachine7_level - 1'd1); end end - if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin - litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid; - litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first; - litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last; - litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we; - litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr; + if (((~main_litedramcore_bankmachine7_pipe_valid_source_valid) | main_litedramcore_bankmachine7_pipe_valid_source_ready)) begin + main_litedramcore_bankmachine7_pipe_valid_source_valid <= main_litedramcore_bankmachine7_pipe_valid_sink_valid; + main_litedramcore_bankmachine7_pipe_valid_source_first <= main_litedramcore_bankmachine7_pipe_valid_sink_first; + main_litedramcore_bankmachine7_pipe_valid_source_last <= main_litedramcore_bankmachine7_pipe_valid_sink_last; + main_litedramcore_bankmachine7_pipe_valid_source_payload_we <= main_litedramcore_bankmachine7_pipe_valid_sink_payload_we; + main_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= main_litedramcore_bankmachine7_pipe_valid_sink_payload_addr; end - if (litedramcore_bankmachine7_twtpcon_valid) begin - litedramcore_bankmachine7_twtpcon_count <= 3'd5; + if (main_litedramcore_bankmachine7_twtpcon_valid) begin + main_litedramcore_bankmachine7_twtpcon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end else begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine7_twtpcon_ready)) begin - litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_twtpcon_ready)) begin + main_litedramcore_bankmachine7_twtpcon_count <= (main_litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((main_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end end end - if (litedramcore_bankmachine7_trccon_valid) begin - litedramcore_bankmachine7_trccon_count <= 3'd5; + if (main_litedramcore_bankmachine7_trccon_valid) begin + main_litedramcore_bankmachine7_trccon_count <= 3'd5; if (1'd0) begin - litedramcore_bankmachine7_trccon_ready <= 1'd1; + main_litedramcore_bankmachine7_trccon_ready <= 1'd1; end else begin - litedramcore_bankmachine7_trccon_ready <= 1'd0; + main_litedramcore_bankmachine7_trccon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine7_trccon_ready)) begin - litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); - if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin - litedramcore_bankmachine7_trccon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_trccon_ready)) begin + main_litedramcore_bankmachine7_trccon_count <= (main_litedramcore_bankmachine7_trccon_count - 1'd1); + if ((main_litedramcore_bankmachine7_trccon_count == 1'd1)) begin + main_litedramcore_bankmachine7_trccon_ready <= 1'd1; end end end - if (litedramcore_bankmachine7_trascon_valid) begin - litedramcore_bankmachine7_trascon_count <= 3'd4; + if (main_litedramcore_bankmachine7_trascon_valid) begin + main_litedramcore_bankmachine7_trascon_count <= 3'd4; if (1'd0) begin - litedramcore_bankmachine7_trascon_ready <= 1'd1; + main_litedramcore_bankmachine7_trascon_ready <= 1'd1; end else begin - litedramcore_bankmachine7_trascon_ready <= 1'd0; + main_litedramcore_bankmachine7_trascon_ready <= 1'd0; end end else begin - if ((~litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); - if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin - litedramcore_bankmachine7_trascon_ready <= 1'd1; + if ((~main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_trascon_count <= (main_litedramcore_bankmachine7_trascon_count - 1'd1); + if ((main_litedramcore_bankmachine7_trascon_count == 1'd1)) begin + main_litedramcore_bankmachine7_trascon_ready <= 1'd1; end end end - litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state; - if ((~litedramcore_en0)) begin - litedramcore_time0 <= 5'd31; + builder_bankmachine7_state <= builder_bankmachine7_next_state; + if ((~main_litedramcore_en0)) begin + main_litedramcore_time0 <= 5'd31; end else begin - if ((~litedramcore_max_time0)) begin - litedramcore_time0 <= (litedramcore_time0 - 1'd1); + if ((~main_litedramcore_max_time0)) begin + main_litedramcore_time0 <= (main_litedramcore_time0 - 1'd1); end end - if ((~litedramcore_en1)) begin - litedramcore_time1 <= 4'd15; + if ((~main_litedramcore_en1)) begin + main_litedramcore_time1 <= 4'd15; end else begin - if ((~litedramcore_max_time1)) begin - litedramcore_time1 <= (litedramcore_time1 - 1'd1); + if ((~main_litedramcore_max_time1)) begin + main_litedramcore_time1 <= (main_litedramcore_time1 - 1'd1); end end - if (litedramcore_choose_cmd_ce) begin - case (litedramcore_choose_cmd_grant) + if (main_litedramcore_choose_cmd_ce) begin + case (main_litedramcore_choose_cmd_grant) 1'd0: begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end end end @@ -13030,26 +13445,26 @@ always @(posedge sys_clk) begin end end 1'd1: begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end end end @@ -13059,26 +13474,26 @@ always @(posedge sys_clk) begin end end 2'd2: begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end end end @@ -13088,26 +13503,26 @@ always @(posedge sys_clk) begin end end 2'd3: begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end end end @@ -13117,26 +13532,26 @@ always @(posedge sys_clk) begin end end 3'd4: begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end end end @@ -13146,26 +13561,26 @@ always @(posedge sys_clk) begin end end 3'd5: begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end end end @@ -13175,26 +13590,26 @@ always @(posedge sys_clk) begin end end 3'd6: begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; + if (main_litedramcore_choose_cmd_request[7]) begin + main_litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end end end @@ -13204,26 +13619,26 @@ always @(posedge sys_clk) begin end end 3'd7: begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; + if (main_litedramcore_choose_cmd_request[0]) begin + main_litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; + if (main_litedramcore_choose_cmd_request[1]) begin + main_litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; + if (main_litedramcore_choose_cmd_request[2]) begin + main_litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; + if (main_litedramcore_choose_cmd_request[3]) begin + main_litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; + if (main_litedramcore_choose_cmd_request[4]) begin + main_litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; + if (main_litedramcore_choose_cmd_request[5]) begin + main_litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; + if (main_litedramcore_choose_cmd_request[6]) begin + main_litedramcore_choose_cmd_grant <= 3'd6; end end end @@ -13234,29 +13649,29 @@ always @(posedge sys_clk) begin end endcase end - if (litedramcore_choose_req_ce) begin - case (litedramcore_choose_req_grant) + if (main_litedramcore_choose_req_ce) begin + case (main_litedramcore_choose_req_grant) 1'd0: begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end end end @@ -13266,26 +13681,26 @@ always @(posedge sys_clk) begin end end 1'd1: begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end end end @@ -13295,26 +13710,26 @@ always @(posedge sys_clk) begin end end 2'd2: begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end end end @@ -13324,26 +13739,26 @@ always @(posedge sys_clk) begin end end 2'd3: begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end end end @@ -13353,26 +13768,26 @@ always @(posedge sys_clk) begin end end 3'd4: begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end end end @@ -13382,26 +13797,26 @@ always @(posedge sys_clk) begin end end 3'd5: begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end end end @@ -13411,26 +13826,26 @@ always @(posedge sys_clk) begin end end 3'd6: begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; + if (main_litedramcore_choose_req_request[7]) begin + main_litedramcore_choose_req_grant <= 3'd7; end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end end end @@ -13440,26 +13855,26 @@ always @(posedge sys_clk) begin end end 3'd7: begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; + if (main_litedramcore_choose_req_request[0]) begin + main_litedramcore_choose_req_grant <= 1'd0; end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; + if (main_litedramcore_choose_req_request[1]) begin + main_litedramcore_choose_req_grant <= 1'd1; end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; + if (main_litedramcore_choose_req_request[2]) begin + main_litedramcore_choose_req_grant <= 2'd2; end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; + if (main_litedramcore_choose_req_request[3]) begin + main_litedramcore_choose_req_grant <= 2'd3; end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; + if (main_litedramcore_choose_req_request[4]) begin + main_litedramcore_choose_req_grant <= 3'd4; end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; + if (main_litedramcore_choose_req_request[5]) begin + main_litedramcore_choose_req_grant <= 3'd5; end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; + if (main_litedramcore_choose_req_request[6]) begin + main_litedramcore_choose_req_grant <= 3'd6; end end end @@ -13470,644 +13885,644 @@ always @(posedge sys_clk) begin end endcase end - litedramcore_dfi_p0_cs_n <= 1'd0; - litedramcore_dfi_p0_bank <= array_muxed0; - litedramcore_dfi_p0_address <= array_muxed1; - litedramcore_dfi_p0_cas_n <= (~array_muxed2); - litedramcore_dfi_p0_ras_n <= (~array_muxed3); - litedramcore_dfi_p0_we_n <= (~array_muxed4); - litedramcore_dfi_p0_rddata_en <= array_muxed5; - litedramcore_dfi_p0_wrdata_en <= array_muxed6; - litedramcore_dfi_p1_cs_n <= 1'd0; - litedramcore_dfi_p1_bank <= array_muxed7; - litedramcore_dfi_p1_address <= array_muxed8; - litedramcore_dfi_p1_cas_n <= (~array_muxed9); - litedramcore_dfi_p1_ras_n <= (~array_muxed10); - litedramcore_dfi_p1_we_n <= (~array_muxed11); - litedramcore_dfi_p1_rddata_en <= array_muxed12; - litedramcore_dfi_p1_wrdata_en <= array_muxed13; - litedramcore_dfi_p2_cs_n <= 1'd0; - litedramcore_dfi_p2_bank <= array_muxed14; - litedramcore_dfi_p2_address <= array_muxed15; - litedramcore_dfi_p2_cas_n <= (~array_muxed16); - litedramcore_dfi_p2_ras_n <= (~array_muxed17); - litedramcore_dfi_p2_we_n <= (~array_muxed18); - litedramcore_dfi_p2_rddata_en <= array_muxed19; - litedramcore_dfi_p2_wrdata_en <= array_muxed20; - litedramcore_dfi_p3_cs_n <= 1'd0; - litedramcore_dfi_p3_bank <= array_muxed21; - litedramcore_dfi_p3_address <= array_muxed22; - litedramcore_dfi_p3_cas_n <= (~array_muxed23); - litedramcore_dfi_p3_ras_n <= (~array_muxed24); - litedramcore_dfi_p3_we_n <= (~array_muxed25); - litedramcore_dfi_p3_rddata_en <= array_muxed26; - litedramcore_dfi_p3_wrdata_en <= array_muxed27; - if (litedramcore_trrdcon_valid) begin - litedramcore_trrdcon_count <= 1'd1; + main_litedramcore_dfi_p0_cs_n <= 1'd0; + main_litedramcore_dfi_p0_bank <= builder_self0; + main_litedramcore_dfi_p0_address <= builder_self1; + main_litedramcore_dfi_p0_cas_n <= (~builder_self2); + main_litedramcore_dfi_p0_ras_n <= (~builder_self3); + main_litedramcore_dfi_p0_we_n <= (~builder_self4); + main_litedramcore_dfi_p0_rddata_en <= builder_self5; + main_litedramcore_dfi_p0_wrdata_en <= builder_self6; + main_litedramcore_dfi_p1_cs_n <= 1'd0; + main_litedramcore_dfi_p1_bank <= builder_self7; + main_litedramcore_dfi_p1_address <= builder_self8; + main_litedramcore_dfi_p1_cas_n <= (~builder_self9); + main_litedramcore_dfi_p1_ras_n <= (~builder_self10); + main_litedramcore_dfi_p1_we_n <= (~builder_self11); + main_litedramcore_dfi_p1_rddata_en <= builder_self12; + main_litedramcore_dfi_p1_wrdata_en <= builder_self13; + main_litedramcore_dfi_p2_cs_n <= 1'd0; + main_litedramcore_dfi_p2_bank <= builder_self14; + main_litedramcore_dfi_p2_address <= builder_self15; + main_litedramcore_dfi_p2_cas_n <= (~builder_self16); + main_litedramcore_dfi_p2_ras_n <= (~builder_self17); + main_litedramcore_dfi_p2_we_n <= (~builder_self18); + main_litedramcore_dfi_p2_rddata_en <= builder_self19; + main_litedramcore_dfi_p2_wrdata_en <= builder_self20; + main_litedramcore_dfi_p3_cs_n <= 1'd0; + main_litedramcore_dfi_p3_bank <= builder_self21; + main_litedramcore_dfi_p3_address <= builder_self22; + main_litedramcore_dfi_p3_cas_n <= (~builder_self23); + main_litedramcore_dfi_p3_ras_n <= (~builder_self24); + main_litedramcore_dfi_p3_we_n <= (~builder_self25); + main_litedramcore_dfi_p3_rddata_en <= builder_self26; + main_litedramcore_dfi_p3_wrdata_en <= builder_self27; + if (main_litedramcore_trrdcon_valid) begin + main_litedramcore_trrdcon_count <= 1'd1; if (1'd0) begin - litedramcore_trrdcon_ready <= 1'd1; + main_litedramcore_trrdcon_ready <= 1'd1; end else begin - litedramcore_trrdcon_ready <= 1'd0; + main_litedramcore_trrdcon_ready <= 1'd0; end end else begin - if ((~litedramcore_trrdcon_ready)) begin - litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); - if ((litedramcore_trrdcon_count == 1'd1)) begin - litedramcore_trrdcon_ready <= 1'd1; + if ((~main_litedramcore_trrdcon_ready)) begin + main_litedramcore_trrdcon_count <= (main_litedramcore_trrdcon_count - 1'd1); + if ((main_litedramcore_trrdcon_count == 1'd1)) begin + main_litedramcore_trrdcon_ready <= 1'd1; end end end - litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; - if ((litedramcore_tfawcon_count < 3'd4)) begin - if ((litedramcore_tfawcon_count == 2'd3)) begin - litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); + main_litedramcore_tfawcon_window <= {main_litedramcore_tfawcon_window, main_litedramcore_tfawcon_valid}; + if ((main_litedramcore_tfawcon_count < 3'd4)) begin + if ((main_litedramcore_tfawcon_count == 2'd3)) begin + main_litedramcore_tfawcon_ready <= (~main_litedramcore_tfawcon_valid); end else begin - litedramcore_tfawcon_ready <= 1'd1; + main_litedramcore_tfawcon_ready <= 1'd1; end end - if (litedramcore_tccdcon_valid) begin - litedramcore_tccdcon_count <= 1'd0; + if (main_litedramcore_tccdcon_valid) begin + main_litedramcore_tccdcon_count <= 1'd0; if (1'd1) begin - litedramcore_tccdcon_ready <= 1'd1; + main_litedramcore_tccdcon_ready <= 1'd1; end else begin - litedramcore_tccdcon_ready <= 1'd0; + main_litedramcore_tccdcon_ready <= 1'd0; end end else begin - if ((~litedramcore_tccdcon_ready)) begin - litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); - if ((litedramcore_tccdcon_count == 1'd1)) begin - litedramcore_tccdcon_ready <= 1'd1; + if ((~main_litedramcore_tccdcon_ready)) begin + main_litedramcore_tccdcon_count <= (main_litedramcore_tccdcon_count - 1'd1); + if ((main_litedramcore_tccdcon_count == 1'd1)) begin + main_litedramcore_tccdcon_ready <= 1'd1; end end end - if (litedramcore_twtrcon_valid) begin - litedramcore_twtrcon_count <= 3'd4; + if (main_litedramcore_twtrcon_valid) begin + main_litedramcore_twtrcon_count <= 3'd4; if (1'd0) begin - litedramcore_twtrcon_ready <= 1'd1; + main_litedramcore_twtrcon_ready <= 1'd1; end else begin - litedramcore_twtrcon_ready <= 1'd0; + main_litedramcore_twtrcon_ready <= 1'd0; end end else begin - if ((~litedramcore_twtrcon_ready)) begin - litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); - if ((litedramcore_twtrcon_count == 1'd1)) begin - litedramcore_twtrcon_ready <= 1'd1; - end - end - end - litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state; - litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); - litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0; - litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); - litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0; - litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1; - litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2; - litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3; - litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4; - litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5; - litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6; - litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7; - litedramcore_state <= litedramcore_next_state; - if (litedramcore_dat_w_next_value_ce0) begin - litedramcore_dat_w <= litedramcore_dat_w_next_value0; - end - if (litedramcore_adr_next_value_ce1) begin - litedramcore_adr <= litedramcore_adr_next_value1; - end - if (litedramcore_we_next_value_ce2) begin - litedramcore_we <= litedramcore_we_next_value2; - end - interface0_bank_bus_dat_r <= 1'd0; - if (csrbank0_sel) begin - case (interface0_bank_bus_adr[8:0]) + if ((~main_litedramcore_twtrcon_ready)) begin + main_litedramcore_twtrcon_count <= (main_litedramcore_twtrcon_count - 1'd1); + if ((main_litedramcore_twtrcon_count == 1'd1)) begin + main_litedramcore_twtrcon_ready <= 1'd1; + end + end + end + builder_multiplexer_state <= builder_multiplexer_next_state; + builder_new_master_wdata_ready0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_wdata_ready)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_wdata_ready)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_wdata_ready)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_wdata_ready)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_wdata_ready)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_wdata_ready)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_wdata_ready)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_wdata_ready)); + builder_new_master_wdata_ready1 <= builder_new_master_wdata_ready0; + builder_new_master_rdata_valid0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_rdata_valid)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_rdata_valid)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_rdata_valid)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_rdata_valid)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_rdata_valid)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_rdata_valid)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_rdata_valid)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_rdata_valid)); + builder_new_master_rdata_valid1 <= builder_new_master_rdata_valid0; + builder_new_master_rdata_valid2 <= builder_new_master_rdata_valid1; + builder_new_master_rdata_valid3 <= builder_new_master_rdata_valid2; + builder_new_master_rdata_valid4 <= builder_new_master_rdata_valid3; + builder_new_master_rdata_valid5 <= builder_new_master_rdata_valid4; + builder_new_master_rdata_valid6 <= builder_new_master_rdata_valid5; + builder_new_master_rdata_valid7 <= builder_new_master_rdata_valid6; + builder_new_master_rdata_valid8 <= builder_new_master_rdata_valid7; + builder_state <= builder_next_state; + if (builder_interface1_dat_w_next_value_ce0) begin + builder_interface1_dat_w <= builder_interface1_dat_w_next_value0; + end + if (builder_interface1_adr_next_value_ce1) begin + builder_interface1_adr <= builder_interface1_adr_next_value1; + end + if (builder_interface1_we_next_value_ce2) begin + builder_interface1_we <= builder_interface1_we_next_value2; + end + builder_interface0_bank_bus_dat_r <= 1'd0; + if (builder_csrbank0_sel) begin + case (builder_interface0_bank_bus_adr[8:0]) 1'd0: begin - interface0_bank_bus_dat_r <= csrbank0_init_done0_w; + builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_done0_w; end 1'd1: begin - interface0_bank_bus_dat_r <= csrbank0_init_error0_w; + builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_error0_w; end endcase end - if (csrbank0_init_done0_re) begin - init_done_storage <= csrbank0_init_done0_r; + if (builder_csrbank0_init_done0_re) begin + main_init_done_storage <= builder_csrbank0_init_done0_r; end - init_done_re <= csrbank0_init_done0_re; - if (csrbank0_init_error0_re) begin - init_error_storage <= csrbank0_init_error0_r; + main_init_done_re <= builder_csrbank0_init_done0_re; + if (builder_csrbank0_init_error0_re) begin + main_init_error_storage <= builder_csrbank0_init_error0_r; end - init_error_re <= csrbank0_init_error0_re; - interface1_bank_bus_dat_r <= 1'd0; - if (csrbank1_sel) begin - case (interface1_bank_bus_adr[8:0]) + main_init_error_re <= builder_csrbank0_init_error0_re; + builder_interface1_bank_bus_dat_r <= 1'd0; + if (builder_csrbank1_sel) begin + case (builder_interface1_bank_bus_adr[8:0]) 1'd0: begin - interface1_bank_bus_dat_r <= csrbank1_rst0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rst0_w; end 1'd1: begin - interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_dly_sel0_w; end 2'd2: begin - interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_half_sys8x_taps0_w; end 2'd3: begin - interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_wlevel_en0_w; end 3'd4: begin - interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wlevel_strobe_w; end 3'd5: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_rst_w; end 3'd6: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_inc_w; end 3'd7: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_rst_w; end 4'd8: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_w; end 4'd9: begin - interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_rst_w; end 4'd10: begin - interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w; + builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_w; end 4'd11: begin - interface1_bank_bus_dat_r <= csrbank1_rdphase0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rdphase0_w; end 4'd12: begin - interface1_bank_bus_dat_r <= csrbank1_wrphase0_w; + builder_interface1_bank_bus_dat_r <= builder_csrbank1_wrphase0_w; end endcase end - if (csrbank1_rst0_re) begin - a7ddrphy_rst_storage <= csrbank1_rst0_r; + if (builder_csrbank1_rst0_re) begin + main_a7ddrphy_rst_storage <= builder_csrbank1_rst0_r; end - a7ddrphy_rst_re <= csrbank1_rst0_re; - if (csrbank1_dly_sel0_re) begin - a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r; + main_a7ddrphy_rst_re <= builder_csrbank1_rst0_re; + if (builder_csrbank1_dly_sel0_re) begin + main_a7ddrphy_dly_sel_storage[1:0] <= builder_csrbank1_dly_sel0_r; end - a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; - if (csrbank1_half_sys8x_taps0_re) begin - a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r; + main_a7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re; + if (builder_csrbank1_half_sys8x_taps0_re) begin + main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r; end - a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re; - if (csrbank1_wlevel_en0_re) begin - a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r; + main_a7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re; + if (builder_csrbank1_wlevel_en0_re) begin + main_a7ddrphy_wlevel_en_storage <= builder_csrbank1_wlevel_en0_r; end - a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re; - if (csrbank1_rdphase0_re) begin - a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r; + main_a7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re; + if (builder_csrbank1_rdphase0_re) begin + main_a7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r; end - a7ddrphy_rdphase_re <= csrbank1_rdphase0_re; - if (csrbank1_wrphase0_re) begin - a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r; + main_a7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re; + if (builder_csrbank1_wrphase0_re) begin + main_a7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r; end - a7ddrphy_wrphase_re <= csrbank1_wrphase0_re; - interface2_bank_bus_dat_r <= 1'd0; - if (csrbank2_sel) begin - case (interface2_bank_bus_adr[8:0]) + main_a7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re; + builder_interface2_bank_bus_dat_r <= 1'd0; + if (builder_csrbank2_sel) begin + case (builder_interface2_bank_bus_adr[8:0]) 1'd0: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_control0_w; end 1'd1: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_command0_w; end 2'd2: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w; end 3'd4: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w; end 3'd5: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w; end 3'd6: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata_w; end 3'd7: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w; end 4'd8: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w; end 4'd9: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w; end 4'd10: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w; end 4'd11: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w; end 4'd12: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata_w; end 4'd13: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w; end 4'd14: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w; end 4'd15: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w; end 5'd16: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w; end 5'd17: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w; end 5'd18: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata_w; end 5'd19: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w; end 5'd20: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w; end 5'd21: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w; end 5'd22: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w; end 5'd23: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w; end 5'd24: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata_w; end endcase end - if (csrbank2_dfii_control0_re) begin - litedramcore_storage[3:0] <= csrbank2_dfii_control0_r; + if (builder_csrbank2_dfii_control0_re) begin + main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r; end - litedramcore_re <= csrbank2_dfii_control0_re; - if (csrbank2_dfii_pi0_command0_re) begin - litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; + main_litedramcore_re <= builder_csrbank2_dfii_control0_re; + if (builder_csrbank2_dfii_pi0_command0_re) begin + main_litedramcore_phaseinjector0_command_storage[7:0] <= builder_csrbank2_dfii_pi0_command0_r; end - litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; - if (csrbank2_dfii_pi0_address0_re) begin - litedramcore_phaseinjector0_address_storage[13:0] <= csrbank2_dfii_pi0_address0_r; + main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re; + if (builder_csrbank2_dfii_pi0_address0_re) begin + main_litedramcore_phaseinjector0_address_storage[13:0] <= builder_csrbank2_dfii_pi0_address0_r; end - litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; - if (csrbank2_dfii_pi0_baddress0_re) begin - litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; + main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re; + if (builder_csrbank2_dfii_pi0_baddress0_re) begin + main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r; end - litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; - if (csrbank2_dfii_pi0_wrdata0_re) begin - litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; + main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re; + if (builder_csrbank2_dfii_pi0_wrdata0_re) begin + main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r; end - litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; - litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re; - if (csrbank2_dfii_pi1_command0_re) begin - litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; + main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re; + main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re; + if (builder_csrbank2_dfii_pi1_command0_re) begin + main_litedramcore_phaseinjector1_command_storage[7:0] <= builder_csrbank2_dfii_pi1_command0_r; end - litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; - if (csrbank2_dfii_pi1_address0_re) begin - litedramcore_phaseinjector1_address_storage[13:0] <= csrbank2_dfii_pi1_address0_r; + main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re; + if (builder_csrbank2_dfii_pi1_address0_re) begin + main_litedramcore_phaseinjector1_address_storage[13:0] <= builder_csrbank2_dfii_pi1_address0_r; end - litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; - if (csrbank2_dfii_pi1_baddress0_re) begin - litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; + main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re; + if (builder_csrbank2_dfii_pi1_baddress0_re) begin + main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r; end - litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; - if (csrbank2_dfii_pi1_wrdata0_re) begin - litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; + main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re; + if (builder_csrbank2_dfii_pi1_wrdata0_re) begin + main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r; end - litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; - litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re; - if (csrbank2_dfii_pi2_command0_re) begin - litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; + main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re; + main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re; + if (builder_csrbank2_dfii_pi2_command0_re) begin + main_litedramcore_phaseinjector2_command_storage[7:0] <= builder_csrbank2_dfii_pi2_command0_r; end - litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; - if (csrbank2_dfii_pi2_address0_re) begin - litedramcore_phaseinjector2_address_storage[13:0] <= csrbank2_dfii_pi2_address0_r; + main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re; + if (builder_csrbank2_dfii_pi2_address0_re) begin + main_litedramcore_phaseinjector2_address_storage[13:0] <= builder_csrbank2_dfii_pi2_address0_r; end - litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; - if (csrbank2_dfii_pi2_baddress0_re) begin - litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; + main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re; + if (builder_csrbank2_dfii_pi2_baddress0_re) begin + main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r; end - litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; - if (csrbank2_dfii_pi2_wrdata0_re) begin - litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r; + main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re; + if (builder_csrbank2_dfii_pi2_wrdata0_re) begin + main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r; end - litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; - litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re; - if (csrbank2_dfii_pi3_command0_re) begin - litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; + main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re; + main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re; + if (builder_csrbank2_dfii_pi3_command0_re) begin + main_litedramcore_phaseinjector3_command_storage[7:0] <= builder_csrbank2_dfii_pi3_command0_r; end - litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; - if (csrbank2_dfii_pi3_address0_re) begin - litedramcore_phaseinjector3_address_storage[13:0] <= csrbank2_dfii_pi3_address0_r; + main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re; + if (builder_csrbank2_dfii_pi3_address0_re) begin + main_litedramcore_phaseinjector3_address_storage[13:0] <= builder_csrbank2_dfii_pi3_address0_r; end - litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; - if (csrbank2_dfii_pi3_baddress0_re) begin - litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; + main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re; + if (builder_csrbank2_dfii_pi3_baddress0_re) begin + main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r; end - litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; - if (csrbank2_dfii_pi3_wrdata0_re) begin - litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r; + main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re; + if (builder_csrbank2_dfii_pi3_wrdata0_re) begin + main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r; end - litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; - litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re; + main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re; + main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re; if (sys_rst) begin - a7ddrphy_rst_storage <= 1'd0; - a7ddrphy_rst_re <= 1'd0; - a7ddrphy_dly_sel_storage <= 2'd0; - a7ddrphy_dly_sel_re <= 1'd0; - a7ddrphy_half_sys8x_taps_storage <= 5'd8; - a7ddrphy_half_sys8x_taps_re <= 1'd0; - a7ddrphy_wlevel_en_storage <= 1'd0; - a7ddrphy_wlevel_en_re <= 1'd0; - a7ddrphy_rdphase_storage <= 2'd2; - a7ddrphy_rdphase_re <= 1'd0; - a7ddrphy_wrphase_storage <= 2'd3; - a7ddrphy_wrphase_re <= 1'd0; - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; - a7ddrphy_dqspattern_o1 <= 8'd0; - a7ddrphy_bitslip0_value0 <= 3'd7; - a7ddrphy_bitslip1_value0 <= 3'd7; - a7ddrphy_bitslip0_value1 <= 3'd7; - a7ddrphy_bitslip1_value1 <= 3'd7; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; - a7ddrphy_bitslip0_value2 <= 3'd7; - a7ddrphy_bitslip0_value3 <= 3'd7; - a7ddrphy_bitslip1_value2 <= 3'd7; - a7ddrphy_bitslip1_value3 <= 3'd7; - a7ddrphy_bitslip2_value0 <= 3'd7; - a7ddrphy_bitslip2_value1 <= 3'd7; - a7ddrphy_bitslip3_value0 <= 3'd7; - a7ddrphy_bitslip3_value1 <= 3'd7; - a7ddrphy_bitslip4_value0 <= 3'd7; - a7ddrphy_bitslip4_value1 <= 3'd7; - a7ddrphy_bitslip5_value0 <= 3'd7; - a7ddrphy_bitslip5_value1 <= 3'd7; - a7ddrphy_bitslip6_value0 <= 3'd7; - a7ddrphy_bitslip6_value1 <= 3'd7; - a7ddrphy_bitslip7_value0 <= 3'd7; - a7ddrphy_bitslip7_value1 <= 3'd7; - a7ddrphy_bitslip8_value0 <= 3'd7; - a7ddrphy_bitslip8_value1 <= 3'd7; - a7ddrphy_bitslip9_value0 <= 3'd7; - a7ddrphy_bitslip9_value1 <= 3'd7; - a7ddrphy_bitslip10_value0 <= 3'd7; - a7ddrphy_bitslip10_value1 <= 3'd7; - a7ddrphy_bitslip11_value0 <= 3'd7; - a7ddrphy_bitslip11_value1 <= 3'd7; - a7ddrphy_bitslip12_value0 <= 3'd7; - a7ddrphy_bitslip12_value1 <= 3'd7; - a7ddrphy_bitslip13_value0 <= 3'd7; - a7ddrphy_bitslip13_value1 <= 3'd7; - a7ddrphy_bitslip14_value0 <= 3'd7; - a7ddrphy_bitslip14_value1 <= 3'd7; - a7ddrphy_bitslip15_value0 <= 3'd7; - a7ddrphy_bitslip15_value1 <= 3'd7; - a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; - a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; - a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; - a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; - litedramcore_storage <= 4'd1; - litedramcore_re <= 1'd0; - litedramcore_phaseinjector0_command_storage <= 6'd0; - litedramcore_phaseinjector0_command_re <= 1'd0; - litedramcore_phaseinjector0_address_re <= 1'd0; - litedramcore_phaseinjector0_baddress_re <= 1'd0; - litedramcore_phaseinjector0_wrdata_re <= 1'd0; - litedramcore_phaseinjector0_rddata_status <= 32'd0; - litedramcore_phaseinjector0_rddata_re <= 1'd0; - litedramcore_phaseinjector1_command_storage <= 6'd0; - litedramcore_phaseinjector1_command_re <= 1'd0; - litedramcore_phaseinjector1_address_re <= 1'd0; - litedramcore_phaseinjector1_baddress_re <= 1'd0; - litedramcore_phaseinjector1_wrdata_re <= 1'd0; - litedramcore_phaseinjector1_rddata_status <= 32'd0; - litedramcore_phaseinjector1_rddata_re <= 1'd0; - litedramcore_phaseinjector2_command_storage <= 6'd0; - litedramcore_phaseinjector2_command_re <= 1'd0; - litedramcore_phaseinjector2_address_re <= 1'd0; - litedramcore_phaseinjector2_baddress_re <= 1'd0; - litedramcore_phaseinjector2_wrdata_re <= 1'd0; - litedramcore_phaseinjector2_rddata_status <= 32'd0; - litedramcore_phaseinjector2_rddata_re <= 1'd0; - litedramcore_phaseinjector3_command_storage <= 6'd0; - litedramcore_phaseinjector3_command_re <= 1'd0; - litedramcore_phaseinjector3_address_re <= 1'd0; - litedramcore_phaseinjector3_baddress_re <= 1'd0; - litedramcore_phaseinjector3_wrdata_re <= 1'd0; - litedramcore_phaseinjector3_rddata_status <= 32'd0; - litedramcore_phaseinjector3_rddata_re <= 1'd0; - litedramcore_dfi_p0_address <= 14'd0; - litedramcore_dfi_p0_bank <= 3'd0; - litedramcore_dfi_p0_cas_n <= 1'd1; - litedramcore_dfi_p0_cs_n <= 1'd1; - litedramcore_dfi_p0_ras_n <= 1'd1; - litedramcore_dfi_p0_we_n <= 1'd1; - litedramcore_dfi_p0_wrdata_en <= 1'd0; - litedramcore_dfi_p0_rddata_en <= 1'd0; - litedramcore_dfi_p1_address <= 14'd0; - litedramcore_dfi_p1_bank <= 3'd0; - litedramcore_dfi_p1_cas_n <= 1'd1; - litedramcore_dfi_p1_cs_n <= 1'd1; - litedramcore_dfi_p1_ras_n <= 1'd1; - litedramcore_dfi_p1_we_n <= 1'd1; - litedramcore_dfi_p1_wrdata_en <= 1'd0; - litedramcore_dfi_p1_rddata_en <= 1'd0; - litedramcore_dfi_p2_address <= 14'd0; - litedramcore_dfi_p2_bank <= 3'd0; - litedramcore_dfi_p2_cas_n <= 1'd1; - litedramcore_dfi_p2_cs_n <= 1'd1; - litedramcore_dfi_p2_ras_n <= 1'd1; - litedramcore_dfi_p2_we_n <= 1'd1; - litedramcore_dfi_p2_wrdata_en <= 1'd0; - litedramcore_dfi_p2_rddata_en <= 1'd0; - litedramcore_dfi_p3_address <= 14'd0; - litedramcore_dfi_p3_bank <= 3'd0; - litedramcore_dfi_p3_cas_n <= 1'd1; - litedramcore_dfi_p3_cs_n <= 1'd1; - litedramcore_dfi_p3_ras_n <= 1'd1; - litedramcore_dfi_p3_we_n <= 1'd1; - litedramcore_dfi_p3_wrdata_en <= 1'd0; - litedramcore_dfi_p3_rddata_en <= 1'd0; - litedramcore_cmd_payload_a <= 14'd0; - litedramcore_cmd_payload_ba <= 3'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_timer_count1 <= 10'd781; - litedramcore_postponer_req_o <= 1'd0; - litedramcore_postponer_count <= 1'd0; - litedramcore_sequencer_done1 <= 1'd0; - litedramcore_sequencer_counter <= 6'd0; - litedramcore_sequencer_count <= 1'd0; - litedramcore_zqcs_timer_count1 <= 27'd99999999; - litedramcore_zqcs_executer_done <= 1'd0; - litedramcore_zqcs_executer_counter <= 5'd0; - litedramcore_bankmachine0_level <= 5'd0; - litedramcore_bankmachine0_produce <= 4'd0; - litedramcore_bankmachine0_consume <= 4'd0; - litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 21'd0; - litedramcore_bankmachine0_row <= 14'd0; - litedramcore_bankmachine0_row_opened <= 1'd0; - litedramcore_bankmachine0_twtpcon_ready <= 1'd0; - litedramcore_bankmachine0_twtpcon_count <= 3'd0; - litedramcore_bankmachine0_trccon_ready <= 1'd0; - litedramcore_bankmachine0_trccon_count <= 3'd0; - litedramcore_bankmachine0_trascon_ready <= 1'd0; - litedramcore_bankmachine0_trascon_count <= 3'd0; - litedramcore_bankmachine1_level <= 5'd0; - litedramcore_bankmachine1_produce <= 4'd0; - litedramcore_bankmachine1_consume <= 4'd0; - litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 21'd0; - litedramcore_bankmachine1_row <= 14'd0; - litedramcore_bankmachine1_row_opened <= 1'd0; - litedramcore_bankmachine1_twtpcon_ready <= 1'd0; - litedramcore_bankmachine1_twtpcon_count <= 3'd0; - litedramcore_bankmachine1_trccon_ready <= 1'd0; - litedramcore_bankmachine1_trccon_count <= 3'd0; - litedramcore_bankmachine1_trascon_ready <= 1'd0; - litedramcore_bankmachine1_trascon_count <= 3'd0; - litedramcore_bankmachine2_level <= 5'd0; - litedramcore_bankmachine2_produce <= 4'd0; - litedramcore_bankmachine2_consume <= 4'd0; - litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 21'd0; - litedramcore_bankmachine2_row <= 14'd0; - litedramcore_bankmachine2_row_opened <= 1'd0; - litedramcore_bankmachine2_twtpcon_ready <= 1'd0; - litedramcore_bankmachine2_twtpcon_count <= 3'd0; - litedramcore_bankmachine2_trccon_ready <= 1'd0; - litedramcore_bankmachine2_trccon_count <= 3'd0; - litedramcore_bankmachine2_trascon_ready <= 1'd0; - litedramcore_bankmachine2_trascon_count <= 3'd0; - litedramcore_bankmachine3_level <= 5'd0; - litedramcore_bankmachine3_produce <= 4'd0; - litedramcore_bankmachine3_consume <= 4'd0; - litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 21'd0; - litedramcore_bankmachine3_row <= 14'd0; - litedramcore_bankmachine3_row_opened <= 1'd0; - litedramcore_bankmachine3_twtpcon_ready <= 1'd0; - litedramcore_bankmachine3_twtpcon_count <= 3'd0; - litedramcore_bankmachine3_trccon_ready <= 1'd0; - litedramcore_bankmachine3_trccon_count <= 3'd0; - litedramcore_bankmachine3_trascon_ready <= 1'd0; - litedramcore_bankmachine3_trascon_count <= 3'd0; - litedramcore_bankmachine4_level <= 5'd0; - litedramcore_bankmachine4_produce <= 4'd0; - litedramcore_bankmachine4_consume <= 4'd0; - litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 21'd0; - litedramcore_bankmachine4_row <= 14'd0; - litedramcore_bankmachine4_row_opened <= 1'd0; - litedramcore_bankmachine4_twtpcon_ready <= 1'd0; - litedramcore_bankmachine4_twtpcon_count <= 3'd0; - litedramcore_bankmachine4_trccon_ready <= 1'd0; - litedramcore_bankmachine4_trccon_count <= 3'd0; - litedramcore_bankmachine4_trascon_ready <= 1'd0; - litedramcore_bankmachine4_trascon_count <= 3'd0; - litedramcore_bankmachine5_level <= 5'd0; - litedramcore_bankmachine5_produce <= 4'd0; - litedramcore_bankmachine5_consume <= 4'd0; - litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 21'd0; - litedramcore_bankmachine5_row <= 14'd0; - litedramcore_bankmachine5_row_opened <= 1'd0; - litedramcore_bankmachine5_twtpcon_ready <= 1'd0; - litedramcore_bankmachine5_twtpcon_count <= 3'd0; - litedramcore_bankmachine5_trccon_ready <= 1'd0; - litedramcore_bankmachine5_trccon_count <= 3'd0; - litedramcore_bankmachine5_trascon_ready <= 1'd0; - litedramcore_bankmachine5_trascon_count <= 3'd0; - litedramcore_bankmachine6_level <= 5'd0; - litedramcore_bankmachine6_produce <= 4'd0; - litedramcore_bankmachine6_consume <= 4'd0; - litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 21'd0; - litedramcore_bankmachine6_row <= 14'd0; - litedramcore_bankmachine6_row_opened <= 1'd0; - litedramcore_bankmachine6_twtpcon_ready <= 1'd0; - litedramcore_bankmachine6_twtpcon_count <= 3'd0; - litedramcore_bankmachine6_trccon_ready <= 1'd0; - litedramcore_bankmachine6_trccon_count <= 3'd0; - litedramcore_bankmachine6_trascon_ready <= 1'd0; - litedramcore_bankmachine6_trascon_count <= 3'd0; - litedramcore_bankmachine7_level <= 5'd0; - litedramcore_bankmachine7_produce <= 4'd0; - litedramcore_bankmachine7_consume <= 4'd0; - litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0; - litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0; - litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 21'd0; - litedramcore_bankmachine7_row <= 14'd0; - litedramcore_bankmachine7_row_opened <= 1'd0; - litedramcore_bankmachine7_twtpcon_ready <= 1'd0; - litedramcore_bankmachine7_twtpcon_count <= 3'd0; - litedramcore_bankmachine7_trccon_ready <= 1'd0; - litedramcore_bankmachine7_trccon_count <= 3'd0; - litedramcore_bankmachine7_trascon_ready <= 1'd0; - litedramcore_bankmachine7_trascon_count <= 3'd0; - litedramcore_choose_cmd_grant <= 3'd0; - litedramcore_choose_req_grant <= 3'd0; - litedramcore_trrdcon_ready <= 1'd0; - litedramcore_trrdcon_count <= 1'd0; - litedramcore_tfawcon_ready <= 1'd1; - litedramcore_tfawcon_window <= 5'd0; - litedramcore_tccdcon_ready <= 1'd0; - litedramcore_tccdcon_count <= 1'd0; - litedramcore_twtrcon_ready <= 1'd0; - litedramcore_twtrcon_count <= 3'd0; - litedramcore_time0 <= 5'd0; - litedramcore_time1 <= 4'd0; - init_done_storage <= 1'd0; - init_done_re <= 1'd0; - init_error_storage <= 1'd0; - init_error_re <= 1'd0; - litedramcore_we <= 1'd0; - litedramcore_refresher_state <= 2'd0; - litedramcore_bankmachine0_state <= 4'd0; - litedramcore_bankmachine1_state <= 4'd0; - litedramcore_bankmachine2_state <= 4'd0; - litedramcore_bankmachine3_state <= 4'd0; - litedramcore_bankmachine4_state <= 4'd0; - litedramcore_bankmachine5_state <= 4'd0; - litedramcore_bankmachine6_state <= 4'd0; - litedramcore_bankmachine7_state <= 4'd0; - litedramcore_multiplexer_state <= 4'd0; - litedramcore_new_master_wdata_ready0 <= 1'd0; - litedramcore_new_master_wdata_ready1 <= 1'd0; - litedramcore_new_master_rdata_valid0 <= 1'd0; - litedramcore_new_master_rdata_valid1 <= 1'd0; - litedramcore_new_master_rdata_valid2 <= 1'd0; - litedramcore_new_master_rdata_valid3 <= 1'd0; - litedramcore_new_master_rdata_valid4 <= 1'd0; - litedramcore_new_master_rdata_valid5 <= 1'd0; - litedramcore_new_master_rdata_valid6 <= 1'd0; - litedramcore_new_master_rdata_valid7 <= 1'd0; - litedramcore_new_master_rdata_valid8 <= 1'd0; - litedramcore_state <= 2'd0; + main_a7ddrphy_rst_storage <= 1'd0; + main_a7ddrphy_rst_re <= 1'd0; + main_a7ddrphy_dly_sel_storage <= 2'd0; + main_a7ddrphy_dly_sel_re <= 1'd0; + main_a7ddrphy_half_sys8x_taps_storage <= 5'd8; + main_a7ddrphy_half_sys8x_taps_re <= 1'd0; + main_a7ddrphy_wlevel_en_storage <= 1'd0; + main_a7ddrphy_wlevel_en_re <= 1'd0; + main_a7ddrphy_rdphase_storage <= 2'd2; + main_a7ddrphy_rdphase_re <= 1'd0; + main_a7ddrphy_wrphase_storage <= 2'd3; + main_a7ddrphy_wrphase_re <= 1'd0; + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + main_a7ddrphy_dqspattern_o1 <= 8'd0; + main_a7ddrphy_bitslip0_value0 <= 3'd7; + main_a7ddrphy_bitslip1_value0 <= 3'd7; + main_a7ddrphy_bitslip0_value1 <= 3'd7; + main_a7ddrphy_bitslip1_value1 <= 3'd7; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + main_a7ddrphy_bitslip0_value2 <= 3'd7; + main_a7ddrphy_bitslip0_value3 <= 3'd7; + main_a7ddrphy_bitslip1_value2 <= 3'd7; + main_a7ddrphy_bitslip1_value3 <= 3'd7; + main_a7ddrphy_bitslip2_value0 <= 3'd7; + main_a7ddrphy_bitslip2_value1 <= 3'd7; + main_a7ddrphy_bitslip3_value0 <= 3'd7; + main_a7ddrphy_bitslip3_value1 <= 3'd7; + main_a7ddrphy_bitslip4_value0 <= 3'd7; + main_a7ddrphy_bitslip4_value1 <= 3'd7; + main_a7ddrphy_bitslip5_value0 <= 3'd7; + main_a7ddrphy_bitslip5_value1 <= 3'd7; + main_a7ddrphy_bitslip6_value0 <= 3'd7; + main_a7ddrphy_bitslip6_value1 <= 3'd7; + main_a7ddrphy_bitslip7_value0 <= 3'd7; + main_a7ddrphy_bitslip7_value1 <= 3'd7; + main_a7ddrphy_bitslip8_value0 <= 3'd7; + main_a7ddrphy_bitslip8_value1 <= 3'd7; + main_a7ddrphy_bitslip9_value0 <= 3'd7; + main_a7ddrphy_bitslip9_value1 <= 3'd7; + main_a7ddrphy_bitslip10_value0 <= 3'd7; + main_a7ddrphy_bitslip10_value1 <= 3'd7; + main_a7ddrphy_bitslip11_value0 <= 3'd7; + main_a7ddrphy_bitslip11_value1 <= 3'd7; + main_a7ddrphy_bitslip12_value0 <= 3'd7; + main_a7ddrphy_bitslip12_value1 <= 3'd7; + main_a7ddrphy_bitslip13_value0 <= 3'd7; + main_a7ddrphy_bitslip13_value1 <= 3'd7; + main_a7ddrphy_bitslip14_value0 <= 3'd7; + main_a7ddrphy_bitslip14_value1 <= 3'd7; + main_a7ddrphy_bitslip15_value0 <= 3'd7; + main_a7ddrphy_bitslip15_value1 <= 3'd7; + main_a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; + main_a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; + main_a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; + main_a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; + main_a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; + main_litedramcore_storage <= 4'd1; + main_litedramcore_re <= 1'd0; + main_litedramcore_phaseinjector0_command_storage <= 8'd0; + main_litedramcore_phaseinjector0_command_re <= 1'd0; + main_litedramcore_phaseinjector0_address_re <= 1'd0; + main_litedramcore_phaseinjector0_baddress_re <= 1'd0; + main_litedramcore_phaseinjector0_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector0_rddata_status <= 32'd0; + main_litedramcore_phaseinjector0_rddata_re <= 1'd0; + main_litedramcore_phaseinjector1_command_storage <= 8'd0; + main_litedramcore_phaseinjector1_command_re <= 1'd0; + main_litedramcore_phaseinjector1_address_re <= 1'd0; + main_litedramcore_phaseinjector1_baddress_re <= 1'd0; + main_litedramcore_phaseinjector1_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector1_rddata_status <= 32'd0; + main_litedramcore_phaseinjector1_rddata_re <= 1'd0; + main_litedramcore_phaseinjector2_command_storage <= 8'd0; + main_litedramcore_phaseinjector2_command_re <= 1'd0; + main_litedramcore_phaseinjector2_address_re <= 1'd0; + main_litedramcore_phaseinjector2_baddress_re <= 1'd0; + main_litedramcore_phaseinjector2_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector2_rddata_status <= 32'd0; + main_litedramcore_phaseinjector2_rddata_re <= 1'd0; + main_litedramcore_phaseinjector3_command_storage <= 8'd0; + main_litedramcore_phaseinjector3_command_re <= 1'd0; + main_litedramcore_phaseinjector3_address_re <= 1'd0; + main_litedramcore_phaseinjector3_baddress_re <= 1'd0; + main_litedramcore_phaseinjector3_wrdata_re <= 1'd0; + main_litedramcore_phaseinjector3_rddata_status <= 32'd0; + main_litedramcore_phaseinjector3_rddata_re <= 1'd0; + main_litedramcore_dfi_p0_address <= 14'd0; + main_litedramcore_dfi_p0_bank <= 3'd0; + main_litedramcore_dfi_p0_cas_n <= 1'd1; + main_litedramcore_dfi_p0_cs_n <= 1'd1; + main_litedramcore_dfi_p0_ras_n <= 1'd1; + main_litedramcore_dfi_p0_we_n <= 1'd1; + main_litedramcore_dfi_p0_wrdata_en <= 1'd0; + main_litedramcore_dfi_p0_rddata_en <= 1'd0; + main_litedramcore_dfi_p1_address <= 14'd0; + main_litedramcore_dfi_p1_bank <= 3'd0; + main_litedramcore_dfi_p1_cas_n <= 1'd1; + main_litedramcore_dfi_p1_cs_n <= 1'd1; + main_litedramcore_dfi_p1_ras_n <= 1'd1; + main_litedramcore_dfi_p1_we_n <= 1'd1; + main_litedramcore_dfi_p1_wrdata_en <= 1'd0; + main_litedramcore_dfi_p1_rddata_en <= 1'd0; + main_litedramcore_dfi_p2_address <= 14'd0; + main_litedramcore_dfi_p2_bank <= 3'd0; + main_litedramcore_dfi_p2_cas_n <= 1'd1; + main_litedramcore_dfi_p2_cs_n <= 1'd1; + main_litedramcore_dfi_p2_ras_n <= 1'd1; + main_litedramcore_dfi_p2_we_n <= 1'd1; + main_litedramcore_dfi_p2_wrdata_en <= 1'd0; + main_litedramcore_dfi_p2_rddata_en <= 1'd0; + main_litedramcore_dfi_p3_address <= 14'd0; + main_litedramcore_dfi_p3_bank <= 3'd0; + main_litedramcore_dfi_p3_cas_n <= 1'd1; + main_litedramcore_dfi_p3_cs_n <= 1'd1; + main_litedramcore_dfi_p3_ras_n <= 1'd1; + main_litedramcore_dfi_p3_we_n <= 1'd1; + main_litedramcore_dfi_p3_wrdata_en <= 1'd0; + main_litedramcore_dfi_p3_rddata_en <= 1'd0; + main_litedramcore_cmd_payload_a <= 14'd0; + main_litedramcore_cmd_payload_ba <= 3'd0; + main_litedramcore_cmd_payload_cas <= 1'd0; + main_litedramcore_cmd_payload_ras <= 1'd0; + main_litedramcore_cmd_payload_we <= 1'd0; + main_litedramcore_timer_count1 <= 10'd781; + main_litedramcore_postponer_req_o <= 1'd0; + main_litedramcore_postponer_count <= 1'd0; + main_litedramcore_sequencer_done1 <= 1'd0; + main_litedramcore_sequencer_trigger <= 6'd0; + main_litedramcore_sequencer_count <= 1'd0; + main_litedramcore_zqcs_timer_count1 <= 27'd99999999; + main_litedramcore_zqcs_executer_done <= 1'd0; + main_litedramcore_zqcs_executer_trigger <= 5'd0; + main_litedramcore_bankmachine0_level <= 5'd0; + main_litedramcore_bankmachine0_produce <= 4'd0; + main_litedramcore_bankmachine0_consume <= 4'd0; + main_litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 21'd0; + main_litedramcore_bankmachine0_row <= 14'd0; + main_litedramcore_bankmachine0_row_opened <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine0_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine0_trccon_ready <= 1'd0; + main_litedramcore_bankmachine0_trccon_count <= 3'd0; + main_litedramcore_bankmachine0_trascon_ready <= 1'd0; + main_litedramcore_bankmachine0_trascon_count <= 3'd0; + main_litedramcore_bankmachine1_level <= 5'd0; + main_litedramcore_bankmachine1_produce <= 4'd0; + main_litedramcore_bankmachine1_consume <= 4'd0; + main_litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 21'd0; + main_litedramcore_bankmachine1_row <= 14'd0; + main_litedramcore_bankmachine1_row_opened <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine1_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine1_trccon_ready <= 1'd0; + main_litedramcore_bankmachine1_trccon_count <= 3'd0; + main_litedramcore_bankmachine1_trascon_ready <= 1'd0; + main_litedramcore_bankmachine1_trascon_count <= 3'd0; + main_litedramcore_bankmachine2_level <= 5'd0; + main_litedramcore_bankmachine2_produce <= 4'd0; + main_litedramcore_bankmachine2_consume <= 4'd0; + main_litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 21'd0; + main_litedramcore_bankmachine2_row <= 14'd0; + main_litedramcore_bankmachine2_row_opened <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine2_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine2_trccon_ready <= 1'd0; + main_litedramcore_bankmachine2_trccon_count <= 3'd0; + main_litedramcore_bankmachine2_trascon_ready <= 1'd0; + main_litedramcore_bankmachine2_trascon_count <= 3'd0; + main_litedramcore_bankmachine3_level <= 5'd0; + main_litedramcore_bankmachine3_produce <= 4'd0; + main_litedramcore_bankmachine3_consume <= 4'd0; + main_litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 21'd0; + main_litedramcore_bankmachine3_row <= 14'd0; + main_litedramcore_bankmachine3_row_opened <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine3_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine3_trccon_ready <= 1'd0; + main_litedramcore_bankmachine3_trccon_count <= 3'd0; + main_litedramcore_bankmachine3_trascon_ready <= 1'd0; + main_litedramcore_bankmachine3_trascon_count <= 3'd0; + main_litedramcore_bankmachine4_level <= 5'd0; + main_litedramcore_bankmachine4_produce <= 4'd0; + main_litedramcore_bankmachine4_consume <= 4'd0; + main_litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 21'd0; + main_litedramcore_bankmachine4_row <= 14'd0; + main_litedramcore_bankmachine4_row_opened <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine4_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine4_trccon_ready <= 1'd0; + main_litedramcore_bankmachine4_trccon_count <= 3'd0; + main_litedramcore_bankmachine4_trascon_ready <= 1'd0; + main_litedramcore_bankmachine4_trascon_count <= 3'd0; + main_litedramcore_bankmachine5_level <= 5'd0; + main_litedramcore_bankmachine5_produce <= 4'd0; + main_litedramcore_bankmachine5_consume <= 4'd0; + main_litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 21'd0; + main_litedramcore_bankmachine5_row <= 14'd0; + main_litedramcore_bankmachine5_row_opened <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine5_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine5_trccon_ready <= 1'd0; + main_litedramcore_bankmachine5_trccon_count <= 3'd0; + main_litedramcore_bankmachine5_trascon_ready <= 1'd0; + main_litedramcore_bankmachine5_trascon_count <= 3'd0; + main_litedramcore_bankmachine6_level <= 5'd0; + main_litedramcore_bankmachine6_produce <= 4'd0; + main_litedramcore_bankmachine6_consume <= 4'd0; + main_litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 21'd0; + main_litedramcore_bankmachine6_row <= 14'd0; + main_litedramcore_bankmachine6_row_opened <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine6_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine6_trccon_ready <= 1'd0; + main_litedramcore_bankmachine6_trccon_count <= 3'd0; + main_litedramcore_bankmachine6_trascon_ready <= 1'd0; + main_litedramcore_bankmachine6_trascon_count <= 3'd0; + main_litedramcore_bankmachine7_level <= 5'd0; + main_litedramcore_bankmachine7_produce <= 4'd0; + main_litedramcore_bankmachine7_consume <= 4'd0; + main_litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0; + main_litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0; + main_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 21'd0; + main_litedramcore_bankmachine7_row <= 14'd0; + main_litedramcore_bankmachine7_row_opened <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + main_litedramcore_bankmachine7_twtpcon_count <= 3'd0; + main_litedramcore_bankmachine7_trccon_ready <= 1'd0; + main_litedramcore_bankmachine7_trccon_count <= 3'd0; + main_litedramcore_bankmachine7_trascon_ready <= 1'd0; + main_litedramcore_bankmachine7_trascon_count <= 3'd0; + main_litedramcore_choose_cmd_grant <= 3'd0; + main_litedramcore_choose_req_grant <= 3'd0; + main_litedramcore_trrdcon_ready <= 1'd0; + main_litedramcore_trrdcon_count <= 1'd0; + main_litedramcore_tfawcon_ready <= 1'd1; + main_litedramcore_tfawcon_window <= 5'd0; + main_litedramcore_tccdcon_ready <= 1'd0; + main_litedramcore_tccdcon_count <= 1'd0; + main_litedramcore_twtrcon_ready <= 1'd0; + main_litedramcore_twtrcon_count <= 3'd0; + main_litedramcore_time0 <= 5'd0; + main_litedramcore_time1 <= 4'd0; + main_init_done_storage <= 1'd0; + main_init_done_re <= 1'd0; + main_init_error_storage <= 1'd0; + main_init_error_re <= 1'd0; + builder_interface1_we <= 1'd0; + builder_refresher_state <= 2'd0; + builder_bankmachine0_state <= 4'd0; + builder_bankmachine1_state <= 4'd0; + builder_bankmachine2_state <= 4'd0; + builder_bankmachine3_state <= 4'd0; + builder_bankmachine4_state <= 4'd0; + builder_bankmachine5_state <= 4'd0; + builder_bankmachine6_state <= 4'd0; + builder_bankmachine7_state <= 4'd0; + builder_multiplexer_state <= 4'd0; + builder_new_master_wdata_ready0 <= 1'd0; + builder_new_master_wdata_ready1 <= 1'd0; + builder_new_master_rdata_valid0 <= 1'd0; + builder_new_master_rdata_valid1 <= 1'd0; + builder_new_master_rdata_valid2 <= 1'd0; + builder_new_master_rdata_valid3 <= 1'd0; + builder_new_master_rdata_valid4 <= 1'd0; + builder_new_master_rdata_valid5 <= 1'd0; + builder_new_master_rdata_valid6 <= 1'd0; + builder_new_master_rdata_valid7 <= 1'd0; + builder_new_master_rdata_valid8 <= 1'd0; + builder_state <= 2'd0; end end @@ -14116,1911 +14531,2624 @@ end // Specialized Logic //------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +// Instance BUFG of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG( - .I(clkout0), - .O(clkout_buf0) + // Inputs. + .I (main_clkout0), + + // Outputs. + .O (main_clkout_buf0) ); +//------------------------------------------------------------------------------ +// Instance BUFG_1 of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG_1( - .I(clkout1), - .O(clkout_buf1) + // Inputs. + .I (main_clkout1), + + // Outputs. + .O (main_clkout_buf1) ); +//------------------------------------------------------------------------------ +// Instance BUFG_2 of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG_2( - .I(clkout2), - .O(clkout_buf2) + // Inputs. + .I (main_clkout2), + + // Outputs. + .O (main_clkout_buf2) ); +//------------------------------------------------------------------------------ +// Instance BUFG_3 of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG_3( - .I(clkout3), - .O(clkout_buf3) + // Inputs. + .I (main_clkout3), + + // Outputs. + .O (main_clkout_buf3) ); +//------------------------------------------------------------------------------ +// Instance IDELAYCTRL of IDELAYCTRL Module. +//------------------------------------------------------------------------------ IDELAYCTRL IDELAYCTRL( - .REFCLK(iodelay_clk), - .RST(ic_reset) + // Inputs. + .REFCLK (iodelay_clk), + .RST (main_ic_reset) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(1'd0), - .D2(1'd1), - .D3(1'd0), - .D4(1'd1), - .D5(1'd0), - .D6(1'd1), - .D7(1'd0), - .D8(1'd1), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(a7ddrphy_sd_clk_se_nodelay) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (1'd0), + .D2 (1'd1), + .D3 (1'd0), + .D4 (1'd1), + .D5 (1'd0), + .D6 (1'd1), + .D7 (1'd0), + .D8 (1'd1), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_a7ddrphy_sd_clk_se_nodelay) ); +//------------------------------------------------------------------------------ +// Instance OBUFDS of OBUFDS Module. +//------------------------------------------------------------------------------ OBUFDS OBUFDS( - .I(a7ddrphy_sd_clk_se_nodelay), - .O(ddram_clk_p), - .OB(ddram_clk_n) + // Inputs. + .I (main_a7ddrphy_sd_clk_se_nodelay), + + // Outputs. + .O (ddram_clk_p), + .OB (ddram_clk_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_1 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_1 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_reset_n), - .D2(a7ddrphy_dfi_p0_reset_n), - .D3(a7ddrphy_dfi_p1_reset_n), - .D4(a7ddrphy_dfi_p1_reset_n), - .D5(a7ddrphy_dfi_p2_reset_n), - .D6(a7ddrphy_dfi_p2_reset_n), - .D7(a7ddrphy_dfi_p3_reset_n), - .D8(a7ddrphy_dfi_p3_reset_n), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_reset_n) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_reset_n), + .D2 (main_a7ddrphy_dfi_p0_reset_n), + .D3 (main_a7ddrphy_dfi_p1_reset_n), + .D4 (main_a7ddrphy_dfi_p1_reset_n), + .D5 (main_a7ddrphy_dfi_p2_reset_n), + .D6 (main_a7ddrphy_dfi_p2_reset_n), + .D7 (main_a7ddrphy_dfi_p3_reset_n), + .D8 (main_a7ddrphy_dfi_p3_reset_n), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_reset_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_2 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_2 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_cs_n), - .D2(a7ddrphy_dfi_p0_cs_n), - .D3(a7ddrphy_dfi_p1_cs_n), - .D4(a7ddrphy_dfi_p1_cs_n), - .D5(a7ddrphy_dfi_p2_cs_n), - .D6(a7ddrphy_dfi_p2_cs_n), - .D7(a7ddrphy_dfi_p3_cs_n), - .D8(a7ddrphy_dfi_p3_cs_n), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_cs_n) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_cs_n), + .D2 (main_a7ddrphy_dfi_p0_cs_n), + .D3 (main_a7ddrphy_dfi_p1_cs_n), + .D4 (main_a7ddrphy_dfi_p1_cs_n), + .D5 (main_a7ddrphy_dfi_p2_cs_n), + .D6 (main_a7ddrphy_dfi_p2_cs_n), + .D7 (main_a7ddrphy_dfi_p3_cs_n), + .D8 (main_a7ddrphy_dfi_p3_cs_n), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_cs_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_3 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_3 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[0]), - .D2(a7ddrphy_dfi_p0_address[0]), - .D3(a7ddrphy_dfi_p1_address[0]), - .D4(a7ddrphy_dfi_p1_address[0]), - .D5(a7ddrphy_dfi_p2_address[0]), - .D6(a7ddrphy_dfi_p2_address[0]), - .D7(a7ddrphy_dfi_p3_address[0]), - .D8(a7ddrphy_dfi_p3_address[0]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[0]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[0]), + .D2 (main_a7ddrphy_dfi_p0_address[0]), + .D3 (main_a7ddrphy_dfi_p1_address[0]), + .D4 (main_a7ddrphy_dfi_p1_address[0]), + .D5 (main_a7ddrphy_dfi_p2_address[0]), + .D6 (main_a7ddrphy_dfi_p2_address[0]), + .D7 (main_a7ddrphy_dfi_p3_address[0]), + .D8 (main_a7ddrphy_dfi_p3_address[0]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[0]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_4 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_4 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[1]), - .D2(a7ddrphy_dfi_p0_address[1]), - .D3(a7ddrphy_dfi_p1_address[1]), - .D4(a7ddrphy_dfi_p1_address[1]), - .D5(a7ddrphy_dfi_p2_address[1]), - .D6(a7ddrphy_dfi_p2_address[1]), - .D7(a7ddrphy_dfi_p3_address[1]), - .D8(a7ddrphy_dfi_p3_address[1]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[1]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[1]), + .D2 (main_a7ddrphy_dfi_p0_address[1]), + .D3 (main_a7ddrphy_dfi_p1_address[1]), + .D4 (main_a7ddrphy_dfi_p1_address[1]), + .D5 (main_a7ddrphy_dfi_p2_address[1]), + .D6 (main_a7ddrphy_dfi_p2_address[1]), + .D7 (main_a7ddrphy_dfi_p3_address[1]), + .D8 (main_a7ddrphy_dfi_p3_address[1]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[1]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_5 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_5 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[2]), - .D2(a7ddrphy_dfi_p0_address[2]), - .D3(a7ddrphy_dfi_p1_address[2]), - .D4(a7ddrphy_dfi_p1_address[2]), - .D5(a7ddrphy_dfi_p2_address[2]), - .D6(a7ddrphy_dfi_p2_address[2]), - .D7(a7ddrphy_dfi_p3_address[2]), - .D8(a7ddrphy_dfi_p3_address[2]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[2]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[2]), + .D2 (main_a7ddrphy_dfi_p0_address[2]), + .D3 (main_a7ddrphy_dfi_p1_address[2]), + .D4 (main_a7ddrphy_dfi_p1_address[2]), + .D5 (main_a7ddrphy_dfi_p2_address[2]), + .D6 (main_a7ddrphy_dfi_p2_address[2]), + .D7 (main_a7ddrphy_dfi_p3_address[2]), + .D8 (main_a7ddrphy_dfi_p3_address[2]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[2]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_6 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_6 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[3]), - .D2(a7ddrphy_dfi_p0_address[3]), - .D3(a7ddrphy_dfi_p1_address[3]), - .D4(a7ddrphy_dfi_p1_address[3]), - .D5(a7ddrphy_dfi_p2_address[3]), - .D6(a7ddrphy_dfi_p2_address[3]), - .D7(a7ddrphy_dfi_p3_address[3]), - .D8(a7ddrphy_dfi_p3_address[3]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[3]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[3]), + .D2 (main_a7ddrphy_dfi_p0_address[3]), + .D3 (main_a7ddrphy_dfi_p1_address[3]), + .D4 (main_a7ddrphy_dfi_p1_address[3]), + .D5 (main_a7ddrphy_dfi_p2_address[3]), + .D6 (main_a7ddrphy_dfi_p2_address[3]), + .D7 (main_a7ddrphy_dfi_p3_address[3]), + .D8 (main_a7ddrphy_dfi_p3_address[3]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[3]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_7 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_7 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[4]), - .D2(a7ddrphy_dfi_p0_address[4]), - .D3(a7ddrphy_dfi_p1_address[4]), - .D4(a7ddrphy_dfi_p1_address[4]), - .D5(a7ddrphy_dfi_p2_address[4]), - .D6(a7ddrphy_dfi_p2_address[4]), - .D7(a7ddrphy_dfi_p3_address[4]), - .D8(a7ddrphy_dfi_p3_address[4]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[4]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[4]), + .D2 (main_a7ddrphy_dfi_p0_address[4]), + .D3 (main_a7ddrphy_dfi_p1_address[4]), + .D4 (main_a7ddrphy_dfi_p1_address[4]), + .D5 (main_a7ddrphy_dfi_p2_address[4]), + .D6 (main_a7ddrphy_dfi_p2_address[4]), + .D7 (main_a7ddrphy_dfi_p3_address[4]), + .D8 (main_a7ddrphy_dfi_p3_address[4]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[4]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_8 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_8 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[5]), - .D2(a7ddrphy_dfi_p0_address[5]), - .D3(a7ddrphy_dfi_p1_address[5]), - .D4(a7ddrphy_dfi_p1_address[5]), - .D5(a7ddrphy_dfi_p2_address[5]), - .D6(a7ddrphy_dfi_p2_address[5]), - .D7(a7ddrphy_dfi_p3_address[5]), - .D8(a7ddrphy_dfi_p3_address[5]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[5]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[5]), + .D2 (main_a7ddrphy_dfi_p0_address[5]), + .D3 (main_a7ddrphy_dfi_p1_address[5]), + .D4 (main_a7ddrphy_dfi_p1_address[5]), + .D5 (main_a7ddrphy_dfi_p2_address[5]), + .D6 (main_a7ddrphy_dfi_p2_address[5]), + .D7 (main_a7ddrphy_dfi_p3_address[5]), + .D8 (main_a7ddrphy_dfi_p3_address[5]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[5]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_9 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_9 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[6]), - .D2(a7ddrphy_dfi_p0_address[6]), - .D3(a7ddrphy_dfi_p1_address[6]), - .D4(a7ddrphy_dfi_p1_address[6]), - .D5(a7ddrphy_dfi_p2_address[6]), - .D6(a7ddrphy_dfi_p2_address[6]), - .D7(a7ddrphy_dfi_p3_address[6]), - .D8(a7ddrphy_dfi_p3_address[6]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[6]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[6]), + .D2 (main_a7ddrphy_dfi_p0_address[6]), + .D3 (main_a7ddrphy_dfi_p1_address[6]), + .D4 (main_a7ddrphy_dfi_p1_address[6]), + .D5 (main_a7ddrphy_dfi_p2_address[6]), + .D6 (main_a7ddrphy_dfi_p2_address[6]), + .D7 (main_a7ddrphy_dfi_p3_address[6]), + .D8 (main_a7ddrphy_dfi_p3_address[6]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[6]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_10 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_10 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[7]), - .D2(a7ddrphy_dfi_p0_address[7]), - .D3(a7ddrphy_dfi_p1_address[7]), - .D4(a7ddrphy_dfi_p1_address[7]), - .D5(a7ddrphy_dfi_p2_address[7]), - .D6(a7ddrphy_dfi_p2_address[7]), - .D7(a7ddrphy_dfi_p3_address[7]), - .D8(a7ddrphy_dfi_p3_address[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[7]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[7]), + .D2 (main_a7ddrphy_dfi_p0_address[7]), + .D3 (main_a7ddrphy_dfi_p1_address[7]), + .D4 (main_a7ddrphy_dfi_p1_address[7]), + .D5 (main_a7ddrphy_dfi_p2_address[7]), + .D6 (main_a7ddrphy_dfi_p2_address[7]), + .D7 (main_a7ddrphy_dfi_p3_address[7]), + .D8 (main_a7ddrphy_dfi_p3_address[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[7]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_11 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_11 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[8]), - .D2(a7ddrphy_dfi_p0_address[8]), - .D3(a7ddrphy_dfi_p1_address[8]), - .D4(a7ddrphy_dfi_p1_address[8]), - .D5(a7ddrphy_dfi_p2_address[8]), - .D6(a7ddrphy_dfi_p2_address[8]), - .D7(a7ddrphy_dfi_p3_address[8]), - .D8(a7ddrphy_dfi_p3_address[8]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[8]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[8]), + .D2 (main_a7ddrphy_dfi_p0_address[8]), + .D3 (main_a7ddrphy_dfi_p1_address[8]), + .D4 (main_a7ddrphy_dfi_p1_address[8]), + .D5 (main_a7ddrphy_dfi_p2_address[8]), + .D6 (main_a7ddrphy_dfi_p2_address[8]), + .D7 (main_a7ddrphy_dfi_p3_address[8]), + .D8 (main_a7ddrphy_dfi_p3_address[8]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[8]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_12 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_12 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[9]), - .D2(a7ddrphy_dfi_p0_address[9]), - .D3(a7ddrphy_dfi_p1_address[9]), - .D4(a7ddrphy_dfi_p1_address[9]), - .D5(a7ddrphy_dfi_p2_address[9]), - .D6(a7ddrphy_dfi_p2_address[9]), - .D7(a7ddrphy_dfi_p3_address[9]), - .D8(a7ddrphy_dfi_p3_address[9]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[9]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[9]), + .D2 (main_a7ddrphy_dfi_p0_address[9]), + .D3 (main_a7ddrphy_dfi_p1_address[9]), + .D4 (main_a7ddrphy_dfi_p1_address[9]), + .D5 (main_a7ddrphy_dfi_p2_address[9]), + .D6 (main_a7ddrphy_dfi_p2_address[9]), + .D7 (main_a7ddrphy_dfi_p3_address[9]), + .D8 (main_a7ddrphy_dfi_p3_address[9]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[9]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_13 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_13 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[10]), - .D2(a7ddrphy_dfi_p0_address[10]), - .D3(a7ddrphy_dfi_p1_address[10]), - .D4(a7ddrphy_dfi_p1_address[10]), - .D5(a7ddrphy_dfi_p2_address[10]), - .D6(a7ddrphy_dfi_p2_address[10]), - .D7(a7ddrphy_dfi_p3_address[10]), - .D8(a7ddrphy_dfi_p3_address[10]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[10]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[10]), + .D2 (main_a7ddrphy_dfi_p0_address[10]), + .D3 (main_a7ddrphy_dfi_p1_address[10]), + .D4 (main_a7ddrphy_dfi_p1_address[10]), + .D5 (main_a7ddrphy_dfi_p2_address[10]), + .D6 (main_a7ddrphy_dfi_p2_address[10]), + .D7 (main_a7ddrphy_dfi_p3_address[10]), + .D8 (main_a7ddrphy_dfi_p3_address[10]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[10]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_14 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_14 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[11]), - .D2(a7ddrphy_dfi_p0_address[11]), - .D3(a7ddrphy_dfi_p1_address[11]), - .D4(a7ddrphy_dfi_p1_address[11]), - .D5(a7ddrphy_dfi_p2_address[11]), - .D6(a7ddrphy_dfi_p2_address[11]), - .D7(a7ddrphy_dfi_p3_address[11]), - .D8(a7ddrphy_dfi_p3_address[11]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[11]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[11]), + .D2 (main_a7ddrphy_dfi_p0_address[11]), + .D3 (main_a7ddrphy_dfi_p1_address[11]), + .D4 (main_a7ddrphy_dfi_p1_address[11]), + .D5 (main_a7ddrphy_dfi_p2_address[11]), + .D6 (main_a7ddrphy_dfi_p2_address[11]), + .D7 (main_a7ddrphy_dfi_p3_address[11]), + .D8 (main_a7ddrphy_dfi_p3_address[11]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[11]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_15 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_15 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[12]), - .D2(a7ddrphy_dfi_p0_address[12]), - .D3(a7ddrphy_dfi_p1_address[12]), - .D4(a7ddrphy_dfi_p1_address[12]), - .D5(a7ddrphy_dfi_p2_address[12]), - .D6(a7ddrphy_dfi_p2_address[12]), - .D7(a7ddrphy_dfi_p3_address[12]), - .D8(a7ddrphy_dfi_p3_address[12]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[12]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[12]), + .D2 (main_a7ddrphy_dfi_p0_address[12]), + .D3 (main_a7ddrphy_dfi_p1_address[12]), + .D4 (main_a7ddrphy_dfi_p1_address[12]), + .D5 (main_a7ddrphy_dfi_p2_address[12]), + .D6 (main_a7ddrphy_dfi_p2_address[12]), + .D7 (main_a7ddrphy_dfi_p3_address[12]), + .D8 (main_a7ddrphy_dfi_p3_address[12]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[12]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_16 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_16 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_address[13]), - .D2(a7ddrphy_dfi_p0_address[13]), - .D3(a7ddrphy_dfi_p1_address[13]), - .D4(a7ddrphy_dfi_p1_address[13]), - .D5(a7ddrphy_dfi_p2_address[13]), - .D6(a7ddrphy_dfi_p2_address[13]), - .D7(a7ddrphy_dfi_p3_address[13]), - .D8(a7ddrphy_dfi_p3_address[13]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_a[13]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_address[13]), + .D2 (main_a7ddrphy_dfi_p0_address[13]), + .D3 (main_a7ddrphy_dfi_p1_address[13]), + .D4 (main_a7ddrphy_dfi_p1_address[13]), + .D5 (main_a7ddrphy_dfi_p2_address[13]), + .D6 (main_a7ddrphy_dfi_p2_address[13]), + .D7 (main_a7ddrphy_dfi_p3_address[13]), + .D8 (main_a7ddrphy_dfi_p3_address[13]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_a[13]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_17 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_17 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_bank[0]), - .D2(a7ddrphy_dfi_p0_bank[0]), - .D3(a7ddrphy_dfi_p1_bank[0]), - .D4(a7ddrphy_dfi_p1_bank[0]), - .D5(a7ddrphy_dfi_p2_bank[0]), - .D6(a7ddrphy_dfi_p2_bank[0]), - .D7(a7ddrphy_dfi_p3_bank[0]), - .D8(a7ddrphy_dfi_p3_bank[0]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(a7ddrphy_pads_ba[0]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_bank[0]), + .D2 (main_a7ddrphy_dfi_p0_bank[0]), + .D3 (main_a7ddrphy_dfi_p1_bank[0]), + .D4 (main_a7ddrphy_dfi_p1_bank[0]), + .D5 (main_a7ddrphy_dfi_p2_bank[0]), + .D6 (main_a7ddrphy_dfi_p2_bank[0]), + .D7 (main_a7ddrphy_dfi_p3_bank[0]), + .D8 (main_a7ddrphy_dfi_p3_bank[0]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_a7ddrphy_pads_ba[0]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_18 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_18 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_bank[1]), - .D2(a7ddrphy_dfi_p0_bank[1]), - .D3(a7ddrphy_dfi_p1_bank[1]), - .D4(a7ddrphy_dfi_p1_bank[1]), - .D5(a7ddrphy_dfi_p2_bank[1]), - .D6(a7ddrphy_dfi_p2_bank[1]), - .D7(a7ddrphy_dfi_p3_bank[1]), - .D8(a7ddrphy_dfi_p3_bank[1]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(a7ddrphy_pads_ba[1]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_bank[1]), + .D2 (main_a7ddrphy_dfi_p0_bank[1]), + .D3 (main_a7ddrphy_dfi_p1_bank[1]), + .D4 (main_a7ddrphy_dfi_p1_bank[1]), + .D5 (main_a7ddrphy_dfi_p2_bank[1]), + .D6 (main_a7ddrphy_dfi_p2_bank[1]), + .D7 (main_a7ddrphy_dfi_p3_bank[1]), + .D8 (main_a7ddrphy_dfi_p3_bank[1]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_a7ddrphy_pads_ba[1]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_19 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_19 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_bank[2]), - .D2(a7ddrphy_dfi_p0_bank[2]), - .D3(a7ddrphy_dfi_p1_bank[2]), - .D4(a7ddrphy_dfi_p1_bank[2]), - .D5(a7ddrphy_dfi_p2_bank[2]), - .D6(a7ddrphy_dfi_p2_bank[2]), - .D7(a7ddrphy_dfi_p3_bank[2]), - .D8(a7ddrphy_dfi_p3_bank[2]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(a7ddrphy_pads_ba[2]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_bank[2]), + .D2 (main_a7ddrphy_dfi_p0_bank[2]), + .D3 (main_a7ddrphy_dfi_p1_bank[2]), + .D4 (main_a7ddrphy_dfi_p1_bank[2]), + .D5 (main_a7ddrphy_dfi_p2_bank[2]), + .D6 (main_a7ddrphy_dfi_p2_bank[2]), + .D7 (main_a7ddrphy_dfi_p3_bank[2]), + .D8 (main_a7ddrphy_dfi_p3_bank[2]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (main_a7ddrphy_pads_ba[2]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_20 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_20 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_ras_n), - .D2(a7ddrphy_dfi_p0_ras_n), - .D3(a7ddrphy_dfi_p1_ras_n), - .D4(a7ddrphy_dfi_p1_ras_n), - .D5(a7ddrphy_dfi_p2_ras_n), - .D6(a7ddrphy_dfi_p2_ras_n), - .D7(a7ddrphy_dfi_p3_ras_n), - .D8(a7ddrphy_dfi_p3_ras_n), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_ras_n) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_ras_n), + .D2 (main_a7ddrphy_dfi_p0_ras_n), + .D3 (main_a7ddrphy_dfi_p1_ras_n), + .D4 (main_a7ddrphy_dfi_p1_ras_n), + .D5 (main_a7ddrphy_dfi_p2_ras_n), + .D6 (main_a7ddrphy_dfi_p2_ras_n), + .D7 (main_a7ddrphy_dfi_p3_ras_n), + .D8 (main_a7ddrphy_dfi_p3_ras_n), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_ras_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_21 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_21 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_cas_n), - .D2(a7ddrphy_dfi_p0_cas_n), - .D3(a7ddrphy_dfi_p1_cas_n), - .D4(a7ddrphy_dfi_p1_cas_n), - .D5(a7ddrphy_dfi_p2_cas_n), - .D6(a7ddrphy_dfi_p2_cas_n), - .D7(a7ddrphy_dfi_p3_cas_n), - .D8(a7ddrphy_dfi_p3_cas_n), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_cas_n) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_cas_n), + .D2 (main_a7ddrphy_dfi_p0_cas_n), + .D3 (main_a7ddrphy_dfi_p1_cas_n), + .D4 (main_a7ddrphy_dfi_p1_cas_n), + .D5 (main_a7ddrphy_dfi_p2_cas_n), + .D6 (main_a7ddrphy_dfi_p2_cas_n), + .D7 (main_a7ddrphy_dfi_p3_cas_n), + .D8 (main_a7ddrphy_dfi_p3_cas_n), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_cas_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_22 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_22 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_we_n), - .D2(a7ddrphy_dfi_p0_we_n), - .D3(a7ddrphy_dfi_p1_we_n), - .D4(a7ddrphy_dfi_p1_we_n), - .D5(a7ddrphy_dfi_p2_we_n), - .D6(a7ddrphy_dfi_p2_we_n), - .D7(a7ddrphy_dfi_p3_we_n), - .D8(a7ddrphy_dfi_p3_we_n), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_we_n) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_we_n), + .D2 (main_a7ddrphy_dfi_p0_we_n), + .D3 (main_a7ddrphy_dfi_p1_we_n), + .D4 (main_a7ddrphy_dfi_p1_we_n), + .D5 (main_a7ddrphy_dfi_p2_we_n), + .D6 (main_a7ddrphy_dfi_p2_we_n), + .D7 (main_a7ddrphy_dfi_p3_we_n), + .D8 (main_a7ddrphy_dfi_p3_we_n), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_we_n) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_23 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_23 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_cke), - .D2(a7ddrphy_dfi_p0_cke), - .D3(a7ddrphy_dfi_p1_cke), - .D4(a7ddrphy_dfi_p1_cke), - .D5(a7ddrphy_dfi_p2_cke), - .D6(a7ddrphy_dfi_p2_cke), - .D7(a7ddrphy_dfi_p3_cke), - .D8(a7ddrphy_dfi_p3_cke), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_cke) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_cke), + .D2 (main_a7ddrphy_dfi_p0_cke), + .D3 (main_a7ddrphy_dfi_p1_cke), + .D4 (main_a7ddrphy_dfi_p1_cke), + .D5 (main_a7ddrphy_dfi_p2_cke), + .D6 (main_a7ddrphy_dfi_p2_cke), + .D7 (main_a7ddrphy_dfi_p3_cke), + .D8 (main_a7ddrphy_dfi_p3_cke), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_cke) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_24 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_24 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_dfi_p0_odt), - .D2(a7ddrphy_dfi_p0_odt), - .D3(a7ddrphy_dfi_p1_odt), - .D4(a7ddrphy_dfi_p1_odt), - .D5(a7ddrphy_dfi_p2_odt), - .D6(a7ddrphy_dfi_p2_odt), - .D7(a7ddrphy_dfi_p3_odt), - .D8(a7ddrphy_dfi_p3_odt), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_odt) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_dfi_p0_odt), + .D2 (main_a7ddrphy_dfi_p0_odt), + .D3 (main_a7ddrphy_dfi_p1_odt), + .D4 (main_a7ddrphy_dfi_p1_odt), + .D5 (main_a7ddrphy_dfi_p2_odt), + .D6 (main_a7ddrphy_dfi_p2_odt), + .D7 (main_a7ddrphy_dfi_p3_odt), + .D8 (main_a7ddrphy_dfi_p3_odt), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_odt) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_25 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_25 ( - .CLK(sys4x_dqs_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip00[0]), - .D2(a7ddrphy_bitslip00[1]), - .D3(a7ddrphy_bitslip00[2]), - .D4(a7ddrphy_bitslip00[3]), - .D5(a7ddrphy_bitslip00[4]), - .D6(a7ddrphy_bitslip00[5]), - .D7(a7ddrphy_bitslip00[6]), - .D8(a7ddrphy_bitslip00[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OFB(a7ddrphy0), - .OQ(a7ddrphy_dqs_o_no_delay0), - .TQ(a7ddrphy_dqs_t0) + // Inputs. + .CLK (sys4x_dqs_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip00[0]), + .D2 (main_a7ddrphy_bitslip00[1]), + .D3 (main_a7ddrphy_bitslip00[2]), + .D4 (main_a7ddrphy_bitslip00[3]), + .D5 (main_a7ddrphy_bitslip00[4]), + .D6 (main_a7ddrphy_bitslip00[5]), + .D7 (main_a7ddrphy_bitslip00[6]), + .D8 (main_a7ddrphy_bitslip00[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OFB (main_a7ddrphy0), + .OQ (main_a7ddrphy_dqs_o_no_delay0), + .TQ (main_a7ddrphy_dqs_t0) ); +//------------------------------------------------------------------------------ +// Instance IOBUFDS of IOBUFDS Module. +//------------------------------------------------------------------------------ IOBUFDS IOBUFDS( - .I(a7ddrphy_dqs_o_no_delay0), - .T(a7ddrphy_dqs_t0), - .IO(ddram_dqs_p[0]), - .IOB(ddram_dqs_n[0]) + // Inputs. + .I (main_a7ddrphy_dqs_o_no_delay0), + .T (main_a7ddrphy_dqs_t0), + + // InOuts. + .IO (ddram_dqs_p[0]), + .IOB (ddram_dqs_n[0]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_26 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_26 ( - .CLK(sys4x_dqs_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip10[0]), - .D2(a7ddrphy_bitslip10[1]), - .D3(a7ddrphy_bitslip10[2]), - .D4(a7ddrphy_bitslip10[3]), - .D5(a7ddrphy_bitslip10[4]), - .D6(a7ddrphy_bitslip10[5]), - .D7(a7ddrphy_bitslip10[6]), - .D8(a7ddrphy_bitslip10[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OFB(a7ddrphy1), - .OQ(a7ddrphy_dqs_o_no_delay1), - .TQ(a7ddrphy_dqs_t1) + // Inputs. + .CLK (sys4x_dqs_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip10[0]), + .D2 (main_a7ddrphy_bitslip10[1]), + .D3 (main_a7ddrphy_bitslip10[2]), + .D4 (main_a7ddrphy_bitslip10[3]), + .D5 (main_a7ddrphy_bitslip10[4]), + .D6 (main_a7ddrphy_bitslip10[5]), + .D7 (main_a7ddrphy_bitslip10[6]), + .D8 (main_a7ddrphy_bitslip10[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OFB (main_a7ddrphy1), + .OQ (main_a7ddrphy_dqs_o_no_delay1), + .TQ (main_a7ddrphy_dqs_t1) ); +//------------------------------------------------------------------------------ +// Instance IOBUFDS_1 of IOBUFDS Module. +//------------------------------------------------------------------------------ IOBUFDS IOBUFDS_1( - .I(a7ddrphy_dqs_o_no_delay1), - .T(a7ddrphy_dqs_t1), - .IO(ddram_dqs_p[1]), - .IOB(ddram_dqs_n[1]) + // Inputs. + .I (main_a7ddrphy_dqs_o_no_delay1), + .T (main_a7ddrphy_dqs_t1), + + // InOuts. + .IO (ddram_dqs_p[1]), + .IOB (ddram_dqs_n[1]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_27 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_27 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip01[0]), - .D2(a7ddrphy_bitslip01[1]), - .D3(a7ddrphy_bitslip01[2]), - .D4(a7ddrphy_bitslip01[3]), - .D5(a7ddrphy_bitslip01[4]), - .D6(a7ddrphy_bitslip01[5]), - .D7(a7ddrphy_bitslip01[6]), - .D8(a7ddrphy_bitslip01[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_dm[0]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip01[0]), + .D2 (main_a7ddrphy_bitslip01[1]), + .D3 (main_a7ddrphy_bitslip01[2]), + .D4 (main_a7ddrphy_bitslip01[3]), + .D5 (main_a7ddrphy_bitslip01[4]), + .D6 (main_a7ddrphy_bitslip01[5]), + .D7 (main_a7ddrphy_bitslip01[6]), + .D8 (main_a7ddrphy_bitslip01[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_dm[0]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_28 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_28 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip11[0]), - .D2(a7ddrphy_bitslip11[1]), - .D3(a7ddrphy_bitslip11[2]), - .D4(a7ddrphy_bitslip11[3]), - .D5(a7ddrphy_bitslip11[4]), - .D6(a7ddrphy_bitslip11[5]), - .D7(a7ddrphy_bitslip11[6]), - .D8(a7ddrphy_bitslip11[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .OQ(ddram_dm[1]) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip11[0]), + .D2 (main_a7ddrphy_bitslip11[1]), + .D3 (main_a7ddrphy_bitslip11[2]), + .D4 (main_a7ddrphy_bitslip11[3]), + .D5 (main_a7ddrphy_bitslip11[4]), + .D6 (main_a7ddrphy_bitslip11[5]), + .D7 (main_a7ddrphy_bitslip11[6]), + .D8 (main_a7ddrphy_bitslip11[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .OQ (ddram_dm[1]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_29 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_29 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip02[0]), - .D2(a7ddrphy_bitslip02[1]), - .D3(a7ddrphy_bitslip02[2]), - .D4(a7ddrphy_bitslip02[3]), - .D5(a7ddrphy_bitslip02[4]), - .D6(a7ddrphy_bitslip02[5]), - .D7(a7ddrphy_bitslip02[6]), - .D8(a7ddrphy_bitslip02[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay0), - .TQ(a7ddrphy_dq_t0) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip02[0]), + .D2 (main_a7ddrphy_bitslip02[1]), + .D3 (main_a7ddrphy_bitslip02[2]), + .D4 (main_a7ddrphy_bitslip02[3]), + .D5 (main_a7ddrphy_bitslip02[4]), + .D6 (main_a7ddrphy_bitslip02[5]), + .D7 (main_a7ddrphy_bitslip02[6]), + .D8 (main_a7ddrphy_bitslip02[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay0), + .TQ (main_a7ddrphy_dq_t0) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed0), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip03[7]), - .Q2(a7ddrphy_bitslip03[6]), - .Q3(a7ddrphy_bitslip03[5]), - .Q4(a7ddrphy_bitslip03[4]), - .Q5(a7ddrphy_bitslip03[3]), - .Q6(a7ddrphy_bitslip03[2]), - .Q7(a7ddrphy_bitslip03[1]), - .Q8(a7ddrphy_bitslip03[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed0), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip03[7]), + .Q2 (main_a7ddrphy_bitslip03[6]), + .Q3 (main_a7ddrphy_bitslip03[5]), + .Q4 (main_a7ddrphy_bitslip03[4]), + .Q5 (main_a7ddrphy_bitslip03[3]), + .Q6 (main_a7ddrphy_bitslip03[2]), + .Q7 (main_a7ddrphy_bitslip03[1]), + .Q8 (main_a7ddrphy_bitslip03[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay0), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed0) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay0), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed0) ); +//------------------------------------------------------------------------------ +// Instance IOBUF of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF( - .I(a7ddrphy_dq_o_nodelay0), - .T(a7ddrphy_dq_t0), - .IO(ddram_dq[0]), - .O(a7ddrphy_dq_i_nodelay0) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay0), + .T (main_a7ddrphy_dq_t0), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay0), + + // InOuts. + .IO (ddram_dq[0]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_30 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_30 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip12[0]), - .D2(a7ddrphy_bitslip12[1]), - .D3(a7ddrphy_bitslip12[2]), - .D4(a7ddrphy_bitslip12[3]), - .D5(a7ddrphy_bitslip12[4]), - .D6(a7ddrphy_bitslip12[5]), - .D7(a7ddrphy_bitslip12[6]), - .D8(a7ddrphy_bitslip12[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay1), - .TQ(a7ddrphy_dq_t1) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip12[0]), + .D2 (main_a7ddrphy_bitslip12[1]), + .D3 (main_a7ddrphy_bitslip12[2]), + .D4 (main_a7ddrphy_bitslip12[3]), + .D5 (main_a7ddrphy_bitslip12[4]), + .D6 (main_a7ddrphy_bitslip12[5]), + .D7 (main_a7ddrphy_bitslip12[6]), + .D8 (main_a7ddrphy_bitslip12[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay1), + .TQ (main_a7ddrphy_dq_t1) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_1 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_1 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip13[7]), - .Q2(a7ddrphy_bitslip13[6]), - .Q3(a7ddrphy_bitslip13[5]), - .Q4(a7ddrphy_bitslip13[4]), - .Q5(a7ddrphy_bitslip13[3]), - .Q6(a7ddrphy_bitslip13[2]), - .Q7(a7ddrphy_bitslip13[1]), - .Q8(a7ddrphy_bitslip13[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip13[7]), + .Q2 (main_a7ddrphy_bitslip13[6]), + .Q3 (main_a7ddrphy_bitslip13[5]), + .Q4 (main_a7ddrphy_bitslip13[4]), + .Q5 (main_a7ddrphy_bitslip13[3]), + .Q6 (main_a7ddrphy_bitslip13[2]), + .Q7 (main_a7ddrphy_bitslip13[1]), + .Q8 (main_a7ddrphy_bitslip13[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_1 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_1 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay1), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed1) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay1), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed1) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_1 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_1( - .I(a7ddrphy_dq_o_nodelay1), - .T(a7ddrphy_dq_t1), - .IO(ddram_dq[1]), - .O(a7ddrphy_dq_i_nodelay1) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay1), + .T (main_a7ddrphy_dq_t1), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay1), + + // InOuts. + .IO (ddram_dq[1]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_31 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_31 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip20[0]), - .D2(a7ddrphy_bitslip20[1]), - .D3(a7ddrphy_bitslip20[2]), - .D4(a7ddrphy_bitslip20[3]), - .D5(a7ddrphy_bitslip20[4]), - .D6(a7ddrphy_bitslip20[5]), - .D7(a7ddrphy_bitslip20[6]), - .D8(a7ddrphy_bitslip20[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay2), - .TQ(a7ddrphy_dq_t2) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip20[0]), + .D2 (main_a7ddrphy_bitslip20[1]), + .D3 (main_a7ddrphy_bitslip20[2]), + .D4 (main_a7ddrphy_bitslip20[3]), + .D5 (main_a7ddrphy_bitslip20[4]), + .D6 (main_a7ddrphy_bitslip20[5]), + .D7 (main_a7ddrphy_bitslip20[6]), + .D8 (main_a7ddrphy_bitslip20[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay2), + .TQ (main_a7ddrphy_dq_t2) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_2 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_2 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed2), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip21[7]), - .Q2(a7ddrphy_bitslip21[6]), - .Q3(a7ddrphy_bitslip21[5]), - .Q4(a7ddrphy_bitslip21[4]), - .Q5(a7ddrphy_bitslip21[3]), - .Q6(a7ddrphy_bitslip21[2]), - .Q7(a7ddrphy_bitslip21[1]), - .Q8(a7ddrphy_bitslip21[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed2), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip21[7]), + .Q2 (main_a7ddrphy_bitslip21[6]), + .Q3 (main_a7ddrphy_bitslip21[5]), + .Q4 (main_a7ddrphy_bitslip21[4]), + .Q5 (main_a7ddrphy_bitslip21[3]), + .Q6 (main_a7ddrphy_bitslip21[2]), + .Q7 (main_a7ddrphy_bitslip21[1]), + .Q8 (main_a7ddrphy_bitslip21[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_2 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_2 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay2), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed2) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay2), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed2) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_2 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_2( - .I(a7ddrphy_dq_o_nodelay2), - .T(a7ddrphy_dq_t2), - .IO(ddram_dq[2]), - .O(a7ddrphy_dq_i_nodelay2) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay2), + .T (main_a7ddrphy_dq_t2), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay2), + + // InOuts. + .IO (ddram_dq[2]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_32 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_32 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip30[0]), - .D2(a7ddrphy_bitslip30[1]), - .D3(a7ddrphy_bitslip30[2]), - .D4(a7ddrphy_bitslip30[3]), - .D5(a7ddrphy_bitslip30[4]), - .D6(a7ddrphy_bitslip30[5]), - .D7(a7ddrphy_bitslip30[6]), - .D8(a7ddrphy_bitslip30[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay3), - .TQ(a7ddrphy_dq_t3) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip30[0]), + .D2 (main_a7ddrphy_bitslip30[1]), + .D3 (main_a7ddrphy_bitslip30[2]), + .D4 (main_a7ddrphy_bitslip30[3]), + .D5 (main_a7ddrphy_bitslip30[4]), + .D6 (main_a7ddrphy_bitslip30[5]), + .D7 (main_a7ddrphy_bitslip30[6]), + .D8 (main_a7ddrphy_bitslip30[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay3), + .TQ (main_a7ddrphy_dq_t3) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_3 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_3 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed3), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip31[7]), - .Q2(a7ddrphy_bitslip31[6]), - .Q3(a7ddrphy_bitslip31[5]), - .Q4(a7ddrphy_bitslip31[4]), - .Q5(a7ddrphy_bitslip31[3]), - .Q6(a7ddrphy_bitslip31[2]), - .Q7(a7ddrphy_bitslip31[1]), - .Q8(a7ddrphy_bitslip31[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed3), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip31[7]), + .Q2 (main_a7ddrphy_bitslip31[6]), + .Q3 (main_a7ddrphy_bitslip31[5]), + .Q4 (main_a7ddrphy_bitslip31[4]), + .Q5 (main_a7ddrphy_bitslip31[3]), + .Q6 (main_a7ddrphy_bitslip31[2]), + .Q7 (main_a7ddrphy_bitslip31[1]), + .Q8 (main_a7ddrphy_bitslip31[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_3 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_3 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay3), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed3) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay3), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed3) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_3 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_3( - .I(a7ddrphy_dq_o_nodelay3), - .T(a7ddrphy_dq_t3), - .IO(ddram_dq[3]), - .O(a7ddrphy_dq_i_nodelay3) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay3), + .T (main_a7ddrphy_dq_t3), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay3), + + // InOuts. + .IO (ddram_dq[3]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_33 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_33 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip40[0]), - .D2(a7ddrphy_bitslip40[1]), - .D3(a7ddrphy_bitslip40[2]), - .D4(a7ddrphy_bitslip40[3]), - .D5(a7ddrphy_bitslip40[4]), - .D6(a7ddrphy_bitslip40[5]), - .D7(a7ddrphy_bitslip40[6]), - .D8(a7ddrphy_bitslip40[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay4), - .TQ(a7ddrphy_dq_t4) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip40[0]), + .D2 (main_a7ddrphy_bitslip40[1]), + .D3 (main_a7ddrphy_bitslip40[2]), + .D4 (main_a7ddrphy_bitslip40[3]), + .D5 (main_a7ddrphy_bitslip40[4]), + .D6 (main_a7ddrphy_bitslip40[5]), + .D7 (main_a7ddrphy_bitslip40[6]), + .D8 (main_a7ddrphy_bitslip40[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay4), + .TQ (main_a7ddrphy_dq_t4) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_4 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_4 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed4), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip41[7]), - .Q2(a7ddrphy_bitslip41[6]), - .Q3(a7ddrphy_bitslip41[5]), - .Q4(a7ddrphy_bitslip41[4]), - .Q5(a7ddrphy_bitslip41[3]), - .Q6(a7ddrphy_bitslip41[2]), - .Q7(a7ddrphy_bitslip41[1]), - .Q8(a7ddrphy_bitslip41[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed4), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip41[7]), + .Q2 (main_a7ddrphy_bitslip41[6]), + .Q3 (main_a7ddrphy_bitslip41[5]), + .Q4 (main_a7ddrphy_bitslip41[4]), + .Q5 (main_a7ddrphy_bitslip41[3]), + .Q6 (main_a7ddrphy_bitslip41[2]), + .Q7 (main_a7ddrphy_bitslip41[1]), + .Q8 (main_a7ddrphy_bitslip41[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_4 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_4 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay4), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed4) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay4), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed4) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_4 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_4( - .I(a7ddrphy_dq_o_nodelay4), - .T(a7ddrphy_dq_t4), - .IO(ddram_dq[4]), - .O(a7ddrphy_dq_i_nodelay4) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay4), + .T (main_a7ddrphy_dq_t4), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay4), + + // InOuts. + .IO (ddram_dq[4]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_34 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_34 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip50[0]), - .D2(a7ddrphy_bitslip50[1]), - .D3(a7ddrphy_bitslip50[2]), - .D4(a7ddrphy_bitslip50[3]), - .D5(a7ddrphy_bitslip50[4]), - .D6(a7ddrphy_bitslip50[5]), - .D7(a7ddrphy_bitslip50[6]), - .D8(a7ddrphy_bitslip50[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay5), - .TQ(a7ddrphy_dq_t5) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip50[0]), + .D2 (main_a7ddrphy_bitslip50[1]), + .D3 (main_a7ddrphy_bitslip50[2]), + .D4 (main_a7ddrphy_bitslip50[3]), + .D5 (main_a7ddrphy_bitslip50[4]), + .D6 (main_a7ddrphy_bitslip50[5]), + .D7 (main_a7ddrphy_bitslip50[6]), + .D8 (main_a7ddrphy_bitslip50[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay5), + .TQ (main_a7ddrphy_dq_t5) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_5 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_5 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed5), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip51[7]), - .Q2(a7ddrphy_bitslip51[6]), - .Q3(a7ddrphy_bitslip51[5]), - .Q4(a7ddrphy_bitslip51[4]), - .Q5(a7ddrphy_bitslip51[3]), - .Q6(a7ddrphy_bitslip51[2]), - .Q7(a7ddrphy_bitslip51[1]), - .Q8(a7ddrphy_bitslip51[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed5), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip51[7]), + .Q2 (main_a7ddrphy_bitslip51[6]), + .Q3 (main_a7ddrphy_bitslip51[5]), + .Q4 (main_a7ddrphy_bitslip51[4]), + .Q5 (main_a7ddrphy_bitslip51[3]), + .Q6 (main_a7ddrphy_bitslip51[2]), + .Q7 (main_a7ddrphy_bitslip51[1]), + .Q8 (main_a7ddrphy_bitslip51[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_5 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_5 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay5), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed5) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay5), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed5) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_5 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_5( - .I(a7ddrphy_dq_o_nodelay5), - .T(a7ddrphy_dq_t5), - .IO(ddram_dq[5]), - .O(a7ddrphy_dq_i_nodelay5) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay5), + .T (main_a7ddrphy_dq_t5), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay5), + + // InOuts. + .IO (ddram_dq[5]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_35 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_35 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip60[0]), - .D2(a7ddrphy_bitslip60[1]), - .D3(a7ddrphy_bitslip60[2]), - .D4(a7ddrphy_bitslip60[3]), - .D5(a7ddrphy_bitslip60[4]), - .D6(a7ddrphy_bitslip60[5]), - .D7(a7ddrphy_bitslip60[6]), - .D8(a7ddrphy_bitslip60[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay6), - .TQ(a7ddrphy_dq_t6) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip60[0]), + .D2 (main_a7ddrphy_bitslip60[1]), + .D3 (main_a7ddrphy_bitslip60[2]), + .D4 (main_a7ddrphy_bitslip60[3]), + .D5 (main_a7ddrphy_bitslip60[4]), + .D6 (main_a7ddrphy_bitslip60[5]), + .D7 (main_a7ddrphy_bitslip60[6]), + .D8 (main_a7ddrphy_bitslip60[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay6), + .TQ (main_a7ddrphy_dq_t6) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_6 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_6 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed6), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip61[7]), - .Q2(a7ddrphy_bitslip61[6]), - .Q3(a7ddrphy_bitslip61[5]), - .Q4(a7ddrphy_bitslip61[4]), - .Q5(a7ddrphy_bitslip61[3]), - .Q6(a7ddrphy_bitslip61[2]), - .Q7(a7ddrphy_bitslip61[1]), - .Q8(a7ddrphy_bitslip61[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed6), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip61[7]), + .Q2 (main_a7ddrphy_bitslip61[6]), + .Q3 (main_a7ddrphy_bitslip61[5]), + .Q4 (main_a7ddrphy_bitslip61[4]), + .Q5 (main_a7ddrphy_bitslip61[3]), + .Q6 (main_a7ddrphy_bitslip61[2]), + .Q7 (main_a7ddrphy_bitslip61[1]), + .Q8 (main_a7ddrphy_bitslip61[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_6 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_6 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay6), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed6) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay6), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed6) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_6 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_6( - .I(a7ddrphy_dq_o_nodelay6), - .T(a7ddrphy_dq_t6), - .IO(ddram_dq[6]), - .O(a7ddrphy_dq_i_nodelay6) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay6), + .T (main_a7ddrphy_dq_t6), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay6), + + // InOuts. + .IO (ddram_dq[6]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_36 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_36 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip70[0]), - .D2(a7ddrphy_bitslip70[1]), - .D3(a7ddrphy_bitslip70[2]), - .D4(a7ddrphy_bitslip70[3]), - .D5(a7ddrphy_bitslip70[4]), - .D6(a7ddrphy_bitslip70[5]), - .D7(a7ddrphy_bitslip70[6]), - .D8(a7ddrphy_bitslip70[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay7), - .TQ(a7ddrphy_dq_t7) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip70[0]), + .D2 (main_a7ddrphy_bitslip70[1]), + .D3 (main_a7ddrphy_bitslip70[2]), + .D4 (main_a7ddrphy_bitslip70[3]), + .D5 (main_a7ddrphy_bitslip70[4]), + .D6 (main_a7ddrphy_bitslip70[5]), + .D7 (main_a7ddrphy_bitslip70[6]), + .D8 (main_a7ddrphy_bitslip70[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay7), + .TQ (main_a7ddrphy_dq_t7) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_7 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_7 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed7), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip71[7]), - .Q2(a7ddrphy_bitslip71[6]), - .Q3(a7ddrphy_bitslip71[5]), - .Q4(a7ddrphy_bitslip71[4]), - .Q5(a7ddrphy_bitslip71[3]), - .Q6(a7ddrphy_bitslip71[2]), - .Q7(a7ddrphy_bitslip71[1]), - .Q8(a7ddrphy_bitslip71[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed7), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip71[7]), + .Q2 (main_a7ddrphy_bitslip71[6]), + .Q3 (main_a7ddrphy_bitslip71[5]), + .Q4 (main_a7ddrphy_bitslip71[4]), + .Q5 (main_a7ddrphy_bitslip71[3]), + .Q6 (main_a7ddrphy_bitslip71[2]), + .Q7 (main_a7ddrphy_bitslip71[1]), + .Q8 (main_a7ddrphy_bitslip71[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_7 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_7 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay7), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed7) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay7), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed7) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_7 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_7( - .I(a7ddrphy_dq_o_nodelay7), - .T(a7ddrphy_dq_t7), - .IO(ddram_dq[7]), - .O(a7ddrphy_dq_i_nodelay7) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay7), + .T (main_a7ddrphy_dq_t7), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay7), + + // InOuts. + .IO (ddram_dq[7]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_37 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_37 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip80[0]), - .D2(a7ddrphy_bitslip80[1]), - .D3(a7ddrphy_bitslip80[2]), - .D4(a7ddrphy_bitslip80[3]), - .D5(a7ddrphy_bitslip80[4]), - .D6(a7ddrphy_bitslip80[5]), - .D7(a7ddrphy_bitslip80[6]), - .D8(a7ddrphy_bitslip80[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay8), - .TQ(a7ddrphy_dq_t8) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip80[0]), + .D2 (main_a7ddrphy_bitslip80[1]), + .D3 (main_a7ddrphy_bitslip80[2]), + .D4 (main_a7ddrphy_bitslip80[3]), + .D5 (main_a7ddrphy_bitslip80[4]), + .D6 (main_a7ddrphy_bitslip80[5]), + .D7 (main_a7ddrphy_bitslip80[6]), + .D8 (main_a7ddrphy_bitslip80[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay8), + .TQ (main_a7ddrphy_dq_t8) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_8 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_8 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed8), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip81[7]), - .Q2(a7ddrphy_bitslip81[6]), - .Q3(a7ddrphy_bitslip81[5]), - .Q4(a7ddrphy_bitslip81[4]), - .Q5(a7ddrphy_bitslip81[3]), - .Q6(a7ddrphy_bitslip81[2]), - .Q7(a7ddrphy_bitslip81[1]), - .Q8(a7ddrphy_bitslip81[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed8), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip81[7]), + .Q2 (main_a7ddrphy_bitslip81[6]), + .Q3 (main_a7ddrphy_bitslip81[5]), + .Q4 (main_a7ddrphy_bitslip81[4]), + .Q5 (main_a7ddrphy_bitslip81[3]), + .Q6 (main_a7ddrphy_bitslip81[2]), + .Q7 (main_a7ddrphy_bitslip81[1]), + .Q8 (main_a7ddrphy_bitslip81[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_8 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_8 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay8), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed8) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay8), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed8) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_8 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_8( - .I(a7ddrphy_dq_o_nodelay8), - .T(a7ddrphy_dq_t8), - .IO(ddram_dq[8]), - .O(a7ddrphy_dq_i_nodelay8) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay8), + .T (main_a7ddrphy_dq_t8), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay8), + + // InOuts. + .IO (ddram_dq[8]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_38 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_38 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip90[0]), - .D2(a7ddrphy_bitslip90[1]), - .D3(a7ddrphy_bitslip90[2]), - .D4(a7ddrphy_bitslip90[3]), - .D5(a7ddrphy_bitslip90[4]), - .D6(a7ddrphy_bitslip90[5]), - .D7(a7ddrphy_bitslip90[6]), - .D8(a7ddrphy_bitslip90[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay9), - .TQ(a7ddrphy_dq_t9) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip90[0]), + .D2 (main_a7ddrphy_bitslip90[1]), + .D3 (main_a7ddrphy_bitslip90[2]), + .D4 (main_a7ddrphy_bitslip90[3]), + .D5 (main_a7ddrphy_bitslip90[4]), + .D6 (main_a7ddrphy_bitslip90[5]), + .D7 (main_a7ddrphy_bitslip90[6]), + .D8 (main_a7ddrphy_bitslip90[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay9), + .TQ (main_a7ddrphy_dq_t9) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_9 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_9 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed9), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip91[7]), - .Q2(a7ddrphy_bitslip91[6]), - .Q3(a7ddrphy_bitslip91[5]), - .Q4(a7ddrphy_bitslip91[4]), - .Q5(a7ddrphy_bitslip91[3]), - .Q6(a7ddrphy_bitslip91[2]), - .Q7(a7ddrphy_bitslip91[1]), - .Q8(a7ddrphy_bitslip91[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed9), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip91[7]), + .Q2 (main_a7ddrphy_bitslip91[6]), + .Q3 (main_a7ddrphy_bitslip91[5]), + .Q4 (main_a7ddrphy_bitslip91[4]), + .Q5 (main_a7ddrphy_bitslip91[3]), + .Q6 (main_a7ddrphy_bitslip91[2]), + .Q7 (main_a7ddrphy_bitslip91[1]), + .Q8 (main_a7ddrphy_bitslip91[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_9 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_9 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay9), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed9) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay9), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed9) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_9 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_9( - .I(a7ddrphy_dq_o_nodelay9), - .T(a7ddrphy_dq_t9), - .IO(ddram_dq[9]), - .O(a7ddrphy_dq_i_nodelay9) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay9), + .T (main_a7ddrphy_dq_t9), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay9), + + // InOuts. + .IO (ddram_dq[9]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_39 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_39 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip100[0]), - .D2(a7ddrphy_bitslip100[1]), - .D3(a7ddrphy_bitslip100[2]), - .D4(a7ddrphy_bitslip100[3]), - .D5(a7ddrphy_bitslip100[4]), - .D6(a7ddrphy_bitslip100[5]), - .D7(a7ddrphy_bitslip100[6]), - .D8(a7ddrphy_bitslip100[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay10), - .TQ(a7ddrphy_dq_t10) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip100[0]), + .D2 (main_a7ddrphy_bitslip100[1]), + .D3 (main_a7ddrphy_bitslip100[2]), + .D4 (main_a7ddrphy_bitslip100[3]), + .D5 (main_a7ddrphy_bitslip100[4]), + .D6 (main_a7ddrphy_bitslip100[5]), + .D7 (main_a7ddrphy_bitslip100[6]), + .D8 (main_a7ddrphy_bitslip100[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay10), + .TQ (main_a7ddrphy_dq_t10) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_10 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_10 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed10), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip101[7]), - .Q2(a7ddrphy_bitslip101[6]), - .Q3(a7ddrphy_bitslip101[5]), - .Q4(a7ddrphy_bitslip101[4]), - .Q5(a7ddrphy_bitslip101[3]), - .Q6(a7ddrphy_bitslip101[2]), - .Q7(a7ddrphy_bitslip101[1]), - .Q8(a7ddrphy_bitslip101[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed10), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip101[7]), + .Q2 (main_a7ddrphy_bitslip101[6]), + .Q3 (main_a7ddrphy_bitslip101[5]), + .Q4 (main_a7ddrphy_bitslip101[4]), + .Q5 (main_a7ddrphy_bitslip101[3]), + .Q6 (main_a7ddrphy_bitslip101[2]), + .Q7 (main_a7ddrphy_bitslip101[1]), + .Q8 (main_a7ddrphy_bitslip101[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_10 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_10 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay10), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed10) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay10), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed10) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_10 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_10( - .I(a7ddrphy_dq_o_nodelay10), - .T(a7ddrphy_dq_t10), - .IO(ddram_dq[10]), - .O(a7ddrphy_dq_i_nodelay10) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay10), + .T (main_a7ddrphy_dq_t10), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay10), + + // InOuts. + .IO (ddram_dq[10]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_40 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_40 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip110[0]), - .D2(a7ddrphy_bitslip110[1]), - .D3(a7ddrphy_bitslip110[2]), - .D4(a7ddrphy_bitslip110[3]), - .D5(a7ddrphy_bitslip110[4]), - .D6(a7ddrphy_bitslip110[5]), - .D7(a7ddrphy_bitslip110[6]), - .D8(a7ddrphy_bitslip110[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay11), - .TQ(a7ddrphy_dq_t11) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip110[0]), + .D2 (main_a7ddrphy_bitslip110[1]), + .D3 (main_a7ddrphy_bitslip110[2]), + .D4 (main_a7ddrphy_bitslip110[3]), + .D5 (main_a7ddrphy_bitslip110[4]), + .D6 (main_a7ddrphy_bitslip110[5]), + .D7 (main_a7ddrphy_bitslip110[6]), + .D8 (main_a7ddrphy_bitslip110[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay11), + .TQ (main_a7ddrphy_dq_t11) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_11 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_11 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed11), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip111[7]), - .Q2(a7ddrphy_bitslip111[6]), - .Q3(a7ddrphy_bitslip111[5]), - .Q4(a7ddrphy_bitslip111[4]), - .Q5(a7ddrphy_bitslip111[3]), - .Q6(a7ddrphy_bitslip111[2]), - .Q7(a7ddrphy_bitslip111[1]), - .Q8(a7ddrphy_bitslip111[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed11), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip111[7]), + .Q2 (main_a7ddrphy_bitslip111[6]), + .Q3 (main_a7ddrphy_bitslip111[5]), + .Q4 (main_a7ddrphy_bitslip111[4]), + .Q5 (main_a7ddrphy_bitslip111[3]), + .Q6 (main_a7ddrphy_bitslip111[2]), + .Q7 (main_a7ddrphy_bitslip111[1]), + .Q8 (main_a7ddrphy_bitslip111[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_11 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_11 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay11), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed11) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay11), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed11) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_11 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_11( - .I(a7ddrphy_dq_o_nodelay11), - .T(a7ddrphy_dq_t11), - .IO(ddram_dq[11]), - .O(a7ddrphy_dq_i_nodelay11) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay11), + .T (main_a7ddrphy_dq_t11), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay11), + + // InOuts. + .IO (ddram_dq[11]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_41 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_41 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip120[0]), - .D2(a7ddrphy_bitslip120[1]), - .D3(a7ddrphy_bitslip120[2]), - .D4(a7ddrphy_bitslip120[3]), - .D5(a7ddrphy_bitslip120[4]), - .D6(a7ddrphy_bitslip120[5]), - .D7(a7ddrphy_bitslip120[6]), - .D8(a7ddrphy_bitslip120[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay12), - .TQ(a7ddrphy_dq_t12) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip120[0]), + .D2 (main_a7ddrphy_bitslip120[1]), + .D3 (main_a7ddrphy_bitslip120[2]), + .D4 (main_a7ddrphy_bitslip120[3]), + .D5 (main_a7ddrphy_bitslip120[4]), + .D6 (main_a7ddrphy_bitslip120[5]), + .D7 (main_a7ddrphy_bitslip120[6]), + .D8 (main_a7ddrphy_bitslip120[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay12), + .TQ (main_a7ddrphy_dq_t12) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_12 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_12 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed12), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip121[7]), - .Q2(a7ddrphy_bitslip121[6]), - .Q3(a7ddrphy_bitslip121[5]), - .Q4(a7ddrphy_bitslip121[4]), - .Q5(a7ddrphy_bitslip121[3]), - .Q6(a7ddrphy_bitslip121[2]), - .Q7(a7ddrphy_bitslip121[1]), - .Q8(a7ddrphy_bitslip121[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed12), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip121[7]), + .Q2 (main_a7ddrphy_bitslip121[6]), + .Q3 (main_a7ddrphy_bitslip121[5]), + .Q4 (main_a7ddrphy_bitslip121[4]), + .Q5 (main_a7ddrphy_bitslip121[3]), + .Q6 (main_a7ddrphy_bitslip121[2]), + .Q7 (main_a7ddrphy_bitslip121[1]), + .Q8 (main_a7ddrphy_bitslip121[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_12 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_12 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay12), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed12) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay12), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed12) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_12 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_12( - .I(a7ddrphy_dq_o_nodelay12), - .T(a7ddrphy_dq_t12), - .IO(ddram_dq[12]), - .O(a7ddrphy_dq_i_nodelay12) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay12), + .T (main_a7ddrphy_dq_t12), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay12), + + // InOuts. + .IO (ddram_dq[12]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_42 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_42 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip130[0]), - .D2(a7ddrphy_bitslip130[1]), - .D3(a7ddrphy_bitslip130[2]), - .D4(a7ddrphy_bitslip130[3]), - .D5(a7ddrphy_bitslip130[4]), - .D6(a7ddrphy_bitslip130[5]), - .D7(a7ddrphy_bitslip130[6]), - .D8(a7ddrphy_bitslip130[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay13), - .TQ(a7ddrphy_dq_t13) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip130[0]), + .D2 (main_a7ddrphy_bitslip130[1]), + .D3 (main_a7ddrphy_bitslip130[2]), + .D4 (main_a7ddrphy_bitslip130[3]), + .D5 (main_a7ddrphy_bitslip130[4]), + .D6 (main_a7ddrphy_bitslip130[5]), + .D7 (main_a7ddrphy_bitslip130[6]), + .D8 (main_a7ddrphy_bitslip130[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay13), + .TQ (main_a7ddrphy_dq_t13) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_13 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_13 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed13), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip131[7]), - .Q2(a7ddrphy_bitslip131[6]), - .Q3(a7ddrphy_bitslip131[5]), - .Q4(a7ddrphy_bitslip131[4]), - .Q5(a7ddrphy_bitslip131[3]), - .Q6(a7ddrphy_bitslip131[2]), - .Q7(a7ddrphy_bitslip131[1]), - .Q8(a7ddrphy_bitslip131[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed13), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip131[7]), + .Q2 (main_a7ddrphy_bitslip131[6]), + .Q3 (main_a7ddrphy_bitslip131[5]), + .Q4 (main_a7ddrphy_bitslip131[4]), + .Q5 (main_a7ddrphy_bitslip131[3]), + .Q6 (main_a7ddrphy_bitslip131[2]), + .Q7 (main_a7ddrphy_bitslip131[1]), + .Q8 (main_a7ddrphy_bitslip131[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_13 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_13 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay13), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed13) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay13), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed13) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_13 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_13( - .I(a7ddrphy_dq_o_nodelay13), - .T(a7ddrphy_dq_t13), - .IO(ddram_dq[13]), - .O(a7ddrphy_dq_i_nodelay13) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay13), + .T (main_a7ddrphy_dq_t13), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay13), + + // InOuts. + .IO (ddram_dq[13]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_43 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_43 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip140[0]), - .D2(a7ddrphy_bitslip140[1]), - .D3(a7ddrphy_bitslip140[2]), - .D4(a7ddrphy_bitslip140[3]), - .D5(a7ddrphy_bitslip140[4]), - .D6(a7ddrphy_bitslip140[5]), - .D7(a7ddrphy_bitslip140[6]), - .D8(a7ddrphy_bitslip140[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay14), - .TQ(a7ddrphy_dq_t14) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip140[0]), + .D2 (main_a7ddrphy_bitslip140[1]), + .D3 (main_a7ddrphy_bitslip140[2]), + .D4 (main_a7ddrphy_bitslip140[3]), + .D5 (main_a7ddrphy_bitslip140[4]), + .D6 (main_a7ddrphy_bitslip140[5]), + .D7 (main_a7ddrphy_bitslip140[6]), + .D8 (main_a7ddrphy_bitslip140[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay14), + .TQ (main_a7ddrphy_dq_t14) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_14 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_14 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed14), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip141[7]), - .Q2(a7ddrphy_bitslip141[6]), - .Q3(a7ddrphy_bitslip141[5]), - .Q4(a7ddrphy_bitslip141[4]), - .Q5(a7ddrphy_bitslip141[3]), - .Q6(a7ddrphy_bitslip141[2]), - .Q7(a7ddrphy_bitslip141[1]), - .Q8(a7ddrphy_bitslip141[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed14), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip141[7]), + .Q2 (main_a7ddrphy_bitslip141[6]), + .Q3 (main_a7ddrphy_bitslip141[5]), + .Q4 (main_a7ddrphy_bitslip141[4]), + .Q5 (main_a7ddrphy_bitslip141[3]), + .Q6 (main_a7ddrphy_bitslip141[2]), + .Q7 (main_a7ddrphy_bitslip141[1]), + .Q8 (main_a7ddrphy_bitslip141[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_14 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_14 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay14), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed14) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay14), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed14) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_14 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_14( - .I(a7ddrphy_dq_o_nodelay14), - .T(a7ddrphy_dq_t14), - .IO(ddram_dq[14]), - .O(a7ddrphy_dq_i_nodelay14) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay14), + .T (main_a7ddrphy_dq_t14), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay14), + + // InOuts. + .IO (ddram_dq[14]) ); +//------------------------------------------------------------------------------ +// Instance OSERDESE2_44 of OSERDESE2 Module. +//------------------------------------------------------------------------------ OSERDESE2 #( - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("BUF"), - .DATA_WIDTH(4'd8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1'd1) + // Parameters. + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("BUF"), + .DATA_WIDTH (4'd8), + .SERDES_MODE ("MASTER"), + .TRISTATE_WIDTH (1'd1) ) OSERDESE2_44 ( - .CLK(sys4x_clk), - .CLKDIV(sys_clk), - .D1(a7ddrphy_bitslip150[0]), - .D2(a7ddrphy_bitslip150[1]), - .D3(a7ddrphy_bitslip150[2]), - .D4(a7ddrphy_bitslip150[3]), - .D5(a7ddrphy_bitslip150[4]), - .D6(a7ddrphy_bitslip150[5]), - .D7(a7ddrphy_bitslip150[6]), - .D8(a7ddrphy_bitslip150[7]), - .OCE(1'd1), - .RST((sys_rst | a7ddrphy_rst_storage)), - .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), - .TCE(1'd1), - .OQ(a7ddrphy_dq_o_nodelay15), - .TQ(a7ddrphy_dq_t15) + // Inputs. + .CLK (sys4x_clk), + .CLKDIV (sys_clk), + .D1 (main_a7ddrphy_bitslip150[0]), + .D2 (main_a7ddrphy_bitslip150[1]), + .D3 (main_a7ddrphy_bitslip150[2]), + .D4 (main_a7ddrphy_bitslip150[3]), + .D5 (main_a7ddrphy_bitslip150[4]), + .D6 (main_a7ddrphy_bitslip150[5]), + .D7 (main_a7ddrphy_bitslip150[6]), + .D8 (main_a7ddrphy_bitslip150[7]), + .OCE (1'd1), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + .T1 ((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE (1'd1), + + // Outputs. + .OQ (main_a7ddrphy_dq_o_nodelay15), + .TQ (main_a7ddrphy_dq_t15) ); +//------------------------------------------------------------------------------ +// Instance ISERDESE2_15 of ISERDESE2 Module. +//------------------------------------------------------------------------------ ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(4'd8), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(1'd1), - .SERDES_MODE("MASTER") + // Parameters. + .DATA_RATE ("DDR"), + .DATA_WIDTH (4'd8), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (1'd1), + .SERDES_MODE ("MASTER") ) ISERDESE2_15 ( - .BITSLIP(1'd0), - .CE1(1'd1), - .CLK(sys4x_clk), - .CLKB((~sys4x_clk)), - .CLKDIV(sys_clk), - .DDLY(a7ddrphy_dq_i_delayed15), - .RST((sys_rst | a7ddrphy_rst_storage)), - .Q1(a7ddrphy_bitslip151[7]), - .Q2(a7ddrphy_bitslip151[6]), - .Q3(a7ddrphy_bitslip151[5]), - .Q4(a7ddrphy_bitslip151[4]), - .Q5(a7ddrphy_bitslip151[3]), - .Q6(a7ddrphy_bitslip151[2]), - .Q7(a7ddrphy_bitslip151[1]), - .Q8(a7ddrphy_bitslip151[0]) + // Inputs. + .BITSLIP (1'd0), + .CE1 (1'd1), + .CLK (sys4x_clk), + .CLKB ((~sys4x_clk)), + .CLKDIV (sys_clk), + .DDLY (main_a7ddrphy_dq_i_delayed15), + .RST ((sys_rst | main_a7ddrphy_rst_storage)), + + // Outputs. + .Q1 (main_a7ddrphy_bitslip151[7]), + .Q2 (main_a7ddrphy_bitslip151[6]), + .Q3 (main_a7ddrphy_bitslip151[5]), + .Q4 (main_a7ddrphy_bitslip151[4]), + .Q5 (main_a7ddrphy_bitslip151[3]), + .Q6 (main_a7ddrphy_bitslip151[2]), + .Q7 (main_a7ddrphy_bitslip151[1]), + .Q8 (main_a7ddrphy_bitslip151[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_15 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC("IDATAIN"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .IDELAY_TYPE("VARIABLE"), - .IDELAY_VALUE(1'd0), - .PIPE_SEL("FALSE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA") + // Parameters. + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VARIABLE"), + .IDELAY_VALUE (1'd0), + .PIPE_SEL ("FALSE"), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA") ) IDELAYE2_15 ( - .C(sys_clk), - .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(a7ddrphy_dq_i_nodelay15), - .INC(1'd1), - .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), - .LDPIPEEN(1'd0), - .DATAOUT(a7ddrphy_dq_i_delayed15) + // Inputs. + .C (sys_clk), + .CE ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN (main_a7ddrphy_dq_i_nodelay15), + .INC (1'd1), + .LD (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_a7ddrphy_dq_i_delayed15) ); +//------------------------------------------------------------------------------ +// Instance IOBUF_15 of IOBUF Module. +//------------------------------------------------------------------------------ IOBUF IOBUF_15( - .I(a7ddrphy_dq_o_nodelay15), - .T(a7ddrphy_dq_t15), - .IO(ddram_dq[15]), - .O(a7ddrphy_dq_i_nodelay15) + // Inputs. + .I (main_a7ddrphy_dq_o_nodelay15), + .T (main_a7ddrphy_dq_t15), + + // Outputs. + .O (main_a7ddrphy_dq_i_nodelay15), + + // InOuts. + .IO (ddram_dq[15]) ); //------------------------------------------------------------------------------ @@ -16031,14 +17159,14 @@ IOBUF IOBUF_15( reg [23:0] storage[0:15]; reg [23:0] storage_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine0_wrport_we) - storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w; - storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr]; + if (main_litedramcore_bankmachine0_wrport_we) + storage[main_litedramcore_bankmachine0_wrport_adr] <= main_litedramcore_bankmachine0_wrport_dat_w; + storage_dat0 <= storage[main_litedramcore_bankmachine0_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0; -assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr]; +assign main_litedramcore_bankmachine0_wrport_dat_r = storage_dat0; +assign main_litedramcore_bankmachine0_rdport_dat_r = storage[main_litedramcore_bankmachine0_rdport_adr]; //------------------------------------------------------------------------------ @@ -16049,14 +17177,14 @@ assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine reg [23:0] storage_1[0:15]; reg [23:0] storage_1_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine1_wrport_we) - storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w; - storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr]; + if (main_litedramcore_bankmachine1_wrport_we) + storage_1[main_litedramcore_bankmachine1_wrport_adr] <= main_litedramcore_bankmachine1_wrport_dat_w; + storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0; -assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr]; +assign main_litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0; +assign main_litedramcore_bankmachine1_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_rdport_adr]; //------------------------------------------------------------------------------ @@ -16067,14 +17195,14 @@ assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachi reg [23:0] storage_2[0:15]; reg [23:0] storage_2_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine2_wrport_we) - storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w; - storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr]; + if (main_litedramcore_bankmachine2_wrport_we) + storage_2[main_litedramcore_bankmachine2_wrport_adr] <= main_litedramcore_bankmachine2_wrport_dat_w; + storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0; -assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr]; +assign main_litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0; +assign main_litedramcore_bankmachine2_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_rdport_adr]; //------------------------------------------------------------------------------ @@ -16085,14 +17213,14 @@ assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachi reg [23:0] storage_3[0:15]; reg [23:0] storage_3_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine3_wrport_we) - storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w; - storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr]; + if (main_litedramcore_bankmachine3_wrport_we) + storage_3[main_litedramcore_bankmachine3_wrport_adr] <= main_litedramcore_bankmachine3_wrport_dat_w; + storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0; -assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr]; +assign main_litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0; +assign main_litedramcore_bankmachine3_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_rdport_adr]; //------------------------------------------------------------------------------ @@ -16103,14 +17231,14 @@ assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachi reg [23:0] storage_4[0:15]; reg [23:0] storage_4_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine4_wrport_we) - storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w; - storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr]; + if (main_litedramcore_bankmachine4_wrport_we) + storage_4[main_litedramcore_bankmachine4_wrport_adr] <= main_litedramcore_bankmachine4_wrport_dat_w; + storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0; -assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr]; +assign main_litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0; +assign main_litedramcore_bankmachine4_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_rdport_adr]; //------------------------------------------------------------------------------ @@ -16121,14 +17249,14 @@ assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachi reg [23:0] storage_5[0:15]; reg [23:0] storage_5_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine5_wrport_we) - storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w; - storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr]; + if (main_litedramcore_bankmachine5_wrport_we) + storage_5[main_litedramcore_bankmachine5_wrport_adr] <= main_litedramcore_bankmachine5_wrport_dat_w; + storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0; -assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr]; +assign main_litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0; +assign main_litedramcore_bankmachine5_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_rdport_adr]; //------------------------------------------------------------------------------ @@ -16139,14 +17267,14 @@ assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachi reg [23:0] storage_6[0:15]; reg [23:0] storage_6_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine6_wrport_we) - storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w; - storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr]; + if (main_litedramcore_bankmachine6_wrport_we) + storage_6[main_litedramcore_bankmachine6_wrport_adr] <= main_litedramcore_bankmachine6_wrport_dat_w; + storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0; -assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr]; +assign main_litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0; +assign main_litedramcore_bankmachine6_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_rdport_adr]; //------------------------------------------------------------------------------ @@ -16157,197 +17285,308 @@ assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachi reg [23:0] storage_7[0:15]; reg [23:0] storage_7_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine7_wrport_we) - storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w; - storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr]; + if (main_litedramcore_bankmachine7_wrport_we) + storage_7[main_litedramcore_bankmachine7_wrport_adr] <= main_litedramcore_bankmachine7_wrport_dat_w; + storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0; -assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr]; +assign main_litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0; +assign main_litedramcore_bankmachine7_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_rdport_adr]; +//------------------------------------------------------------------------------ +// Instance FDCE of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(reset), - .Q(litedramcore_reset0) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (main_reset), + + // Outputs. + .Q (builder_reset0) ); +//------------------------------------------------------------------------------ +// Instance FDCE_1 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_1( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset0), - .Q(litedramcore_reset1) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset0), + + // Outputs. + .Q (builder_reset1) ); +//------------------------------------------------------------------------------ +// Instance FDCE_2 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_2( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset1), - .Q(litedramcore_reset2) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset1), + + // Outputs. + .Q (builder_reset2) ); +//------------------------------------------------------------------------------ +// Instance FDCE_3 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_3( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset2), - .Q(litedramcore_reset3) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset2), + + // Outputs. + .Q (builder_reset3) ); +//------------------------------------------------------------------------------ +// Instance FDCE_4 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_4( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset3), - .Q(litedramcore_reset4) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset3), + + // Outputs. + .Q (builder_reset4) ); +//------------------------------------------------------------------------------ +// Instance FDCE_5 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_5( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset4), - .Q(litedramcore_reset5) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset4), + + // Outputs. + .Q (builder_reset5) ); +//------------------------------------------------------------------------------ +// Instance FDCE_6 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_6( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset5), - .Q(litedramcore_reset6) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset5), + + // Outputs. + .Q (builder_reset6) ); +//------------------------------------------------------------------------------ +// Instance FDCE_7 of FDCE Module. +//------------------------------------------------------------------------------ FDCE FDCE_7( - .C(clkin), - .CE(1'd1), - .CLR(1'd0), - .D(litedramcore_reset6), - .Q(litedramcore_reset7) + // Inputs. + .C (main_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset6), + + // Outputs. + .Q (builder_reset7) ); +//------------------------------------------------------------------------------ +// Instance PLLE2_ADV of PLLE2_ADV Module. +//------------------------------------------------------------------------------ PLLE2_ADV #( - .CLKFBOUT_MULT(6'd32), - .CLKIN1_PERIOD(20.0), - .CLKOUT0_DIVIDE(4'd8), - .CLKOUT0_PHASE(1'd0), - .CLKOUT1_DIVIDE(5'd16), - .CLKOUT1_PHASE(1'd0), - .CLKOUT2_DIVIDE(3'd4), - .CLKOUT2_PHASE(1'd0), - .CLKOUT3_DIVIDE(3'd4), - .CLKOUT3_PHASE(7'd90), - .DIVCLK_DIVIDE(1'd1), - .REF_JITTER1(0.01), - .STARTUP_WAIT("FALSE") + // Parameters. + .CLKFBOUT_MULT (6'd32), + .CLKIN1_PERIOD (20.0), + .CLKOUT0_DIVIDE (4'd8), + .CLKOUT0_PHASE (1'd0), + .CLKOUT1_DIVIDE (5'd16), + .CLKOUT1_PHASE (1'd0), + .CLKOUT2_DIVIDE (3'd4), + .CLKOUT2_PHASE (1'd0), + .CLKOUT3_DIVIDE (3'd4), + .CLKOUT3_PHASE (7'd90), + .DIVCLK_DIVIDE (1'd1), + .REF_JITTER1 (0.01), + .STARTUP_WAIT ("FALSE") ) PLLE2_ADV ( - .CLKFBIN(litedramcore_pll_fb), - .CLKIN1(clkin), - .PWRDWN(power_down), - .RST(litedramcore_reset7), - .CLKFBOUT(litedramcore_pll_fb), - .CLKOUT0(clkout0), - .CLKOUT1(clkout1), - .CLKOUT2(clkout2), - .CLKOUT3(clkout3), - .LOCKED(locked) + // Inputs. + .CLKFBIN (builder_pll_fb), + .CLKIN1 (main_clkin), + .PWRDWN (main_power_down), + .RST (builder_reset7), + + // Outputs. + .CLKFBOUT (builder_pll_fb), + .CLKOUT0 (main_clkout0), + .CLKOUT1 (main_clkout1), + .CLKOUT2 (main_clkout2), + .CLKOUT3 (main_clkout3), + .LOCKED (main_locked) ); (* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE ( - .C(iodelay_clk), - .CE(1'd1), - .D(1'd0), - .PRE(xilinxasyncresetsynchronizerimpl0), - .Q(xilinxasyncresetsynchronizerimpl0_rst_meta) + // Inputs. + .C (iodelay_clk), + .CE (1'd1), + .D (1'd0), + .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl0_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_1 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_1 ( - .C(iodelay_clk), - .CE(1'd1), - .D(xilinxasyncresetsynchronizerimpl0_rst_meta), - .PRE(xilinxasyncresetsynchronizerimpl0), - .Q(iodelay_rst) + // Inputs. + .C (iodelay_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl0_rst_meta), + .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + + // Outputs. + .Q (iodelay_rst) ); (* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_2 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_2 ( - .C(sys_clk), - .CE(1'd1), - .D(1'd0), - .PRE(xilinxasyncresetsynchronizerimpl1), - .Q(xilinxasyncresetsynchronizerimpl1_rst_meta) + // Inputs. + .C (sys_clk), + .CE (1'd1), + .D (1'd0), + .PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl1_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_3 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_3 ( - .C(sys_clk), - .CE(1'd1), - .D(xilinxasyncresetsynchronizerimpl1_rst_meta), - .PRE(xilinxasyncresetsynchronizerimpl1), - .Q(sys_rst) + // Inputs. + .C (sys_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl1_rst_meta), + .PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset), + + // Outputs. + .Q (sys_rst) ); (* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_4 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_4 ( - .C(sys4x_clk), - .CE(1'd1), - .D(1'd0), - .PRE(xilinxasyncresetsynchronizerimpl2), - .Q(xilinxasyncresetsynchronizerimpl2_rst_meta) + // Inputs. + .C (sys4x_clk), + .CE (1'd1), + .D (1'd0), + .PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl2_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_5 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_5 ( - .C(sys4x_clk), - .CE(1'd1), - .D(xilinxasyncresetsynchronizerimpl2_rst_meta), - .PRE(xilinxasyncresetsynchronizerimpl2), - .Q(xilinxasyncresetsynchronizerimpl2_expr) + // Inputs. + .C (sys4x_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl2_rst_meta), + .PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl2_expr) ); (* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_6 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_6 ( - .C(sys4x_dqs_clk), - .CE(1'd1), - .D(1'd0), - .PRE(xilinxasyncresetsynchronizerimpl3), - .Q(xilinxasyncresetsynchronizerimpl3_rst_meta) + // Inputs. + .C (sys4x_dqs_clk), + .CE (1'd1), + .D (1'd0), + .PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl3_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_7 of FDPE Module. +//------------------------------------------------------------------------------ FDPE #( - .INIT(1'd1) + // Parameters. + .INIT (1'd1) ) FDPE_7 ( - .C(sys4x_dqs_clk), - .CE(1'd1), - .D(xilinxasyncresetsynchronizerimpl3_rst_meta), - .PRE(xilinxasyncresetsynchronizerimpl3), - .Q(xilinxasyncresetsynchronizerimpl3_expr) + // Inputs. + .C (sys4x_dqs_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl3_rst_meta), + .PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl3_expr) ); endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2022-10-28 19:01:25. +// Auto-Generated by LiteX on 2024-04-01 10:12:10. //------------------------------------------------------------------------------ diff --git a/liteeth/gen-src/ecpix-5.yml b/liteeth/gen-src/ecpix-5.yml new file mode 100644 index 0000000..9803c4b --- /dev/null +++ b/liteeth/gen-src/ecpix-5.yml @@ -0,0 +1,18 @@ +# This file is derived from nexys_video.yml, which is: +# Copyright (c) 2020 Florent Kermarrec +# License: BSD + +# PHY ---------------------------------------------------------------------- +phy: LiteEthECP5PHYRGMII +vendor: lattice +# Core --------------------------------------------------------------------- +clk_freq: 125e6 +core: wishbone +endianness: little +ntxslots: 2 +nrxslots: 2 +phy_rx_delay: 0 + +soc: + mem_map: + ethmac: 0x00010000 diff --git a/liteeth/gen-src/generate.sh b/liteeth/gen-src/generate.sh index 96203eb..a631b3e 100755 --- a/liteeth/gen-src/generate.sh +++ b/liteeth/gen-src/generate.sh @@ -1,6 +1,6 @@ #!/bin/bash -TARGETS="arty nexys-video wukong-v2" +TARGETS="arty nexys-video wukong-v2 ecpix-5" ME=$(realpath $0) echo ME=$ME diff --git a/liteeth/generated/arty/liteeth_core.v b/liteeth/generated/arty/liteeth_core.v index 3f5ac6c..f363a2f 100644 --- a/liteeth/generated/arty/liteeth_core.v +++ b/liteeth/generated/arty/liteeth_core.v @@ -1,1041 +1,1334 @@ -//-------------------------------------------------------------------------------- -// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:37:00 -//-------------------------------------------------------------------------------- -module liteeth_core( - input wire sys_clock, - input wire sys_reset, - input wire mii_eth_clocks_tx, - input wire mii_eth_clocks_rx, - output wire mii_eth_rst_n, - inout wire mii_eth_mdio, - output wire mii_eth_mdc, - input wire mii_eth_rx_dv, - input wire mii_eth_rx_er, - input wire [3:0] mii_eth_rx_data, - output reg mii_eth_tx_en, - output reg [3:0] mii_eth_tx_data, - input wire mii_eth_col, - input wire mii_eth_crs, - input wire [29:0] wishbone_adr, - input wire [31:0] wishbone_dat_w, - output wire [31:0] wishbone_dat_r, - input wire [3:0] wishbone_sel, - input wire wishbone_cyc, - input wire wishbone_stb, - output wire wishbone_ack, - input wire wishbone_we, - input wire [2:0] wishbone_cti, - input wire [1:0] wishbone_bte, - output wire wishbone_err, - output wire interrupt +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : liteeth_core.v +// Device : +// LiteX sha1 : 87137c30 +// Date : 2024-04-05 17:38:49 +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ps + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module liteeth_core ( + output wire interrupt, + input wire mii_clocks_rx, + input wire mii_clocks_tx, + input wire mii_col, + input wire mii_crs, + output wire mii_mdc, + inout wire mii_mdio, + output wire mii_rst_n, + input wire [3:0] mii_rx_data, + input wire mii_rx_dv, + input wire mii_rx_er, + output reg [3:0] mii_tx_data, + output reg mii_tx_en, + input wire sys_clock, + input wire sys_reset, + output wire wishbone_ack, + input wire [29:0] wishbone_adr, + input wire [1:0] wishbone_bte, + input wire [2:0] wishbone_cti, + input wire wishbone_cyc, + output wire [31:0] wishbone_dat_r, + input wire [31:0] wishbone_dat_w, + output wire wishbone_err, + input wire [3:0] wishbone_sel, + input wire wishbone_stb, + input wire wishbone_we ); -reg main_maccore_maccore_soc_rst = 1'd0; -wire main_maccore_maccore_cpu_rst; -reg [1:0] main_maccore_maccore_reset_storage = 2'd0; -reg main_maccore_maccore_reset_re = 1'd0; -reg [31:0] main_maccore_maccore_scratch_storage = 32'd305419896; -reg main_maccore_maccore_scratch_re = 1'd0; -wire [31:0] main_maccore_maccore_bus_errors_status; -wire main_maccore_maccore_bus_errors_we; -reg main_maccore_maccore_bus_errors_re = 1'd0; -wire main_maccore_maccore_bus_error; -reg [31:0] main_maccore_maccore_bus_errors = 32'd0; -(* dont_touch = "true" *) wire sys_clk; -wire sys_rst; -wire por_clk; -reg main_maccore_int_rst = 1'd1; -reg main_maccore_ethphy_reset_storage = 1'd0; -reg main_maccore_ethphy_reset_re = 1'd0; -(* dont_touch = "true" *) wire eth_rx_clk; -wire eth_rx_rst; -(* dont_touch = "true" *) wire eth_tx_clk; -wire eth_tx_rst; -wire main_maccore_ethphy_reset0; -wire main_maccore_ethphy_reset1; -reg [8:0] main_maccore_ethphy_counter = 9'd0; -wire main_maccore_ethphy_counter_done; -wire main_maccore_ethphy_counter_ce; -wire main_maccore_ethphy_liteethphymiitx_sink_sink_valid; -wire main_maccore_ethphy_liteethphymiitx_sink_sink_ready; -wire main_maccore_ethphy_liteethphymiitx_sink_sink_first; -wire main_maccore_ethphy_liteethphymiitx_sink_sink_last; -wire [7:0] main_maccore_ethphy_liteethphymiitx_sink_sink_payload_data; -wire main_maccore_ethphy_liteethphymiitx_sink_sink_payload_last_be; -wire main_maccore_ethphy_liteethphymiitx_sink_sink_payload_error; -wire main_maccore_ethphy_liteethphymiitx_converter_sink_valid; -wire main_maccore_ethphy_liteethphymiitx_converter_sink_ready; -reg main_maccore_ethphy_liteethphymiitx_converter_sink_first = 1'd0; -reg main_maccore_ethphy_liteethphymiitx_converter_sink_last = 1'd0; -wire [7:0] main_maccore_ethphy_liteethphymiitx_converter_sink_payload_data; -wire main_maccore_ethphy_liteethphymiitx_converter_source_valid; -wire main_maccore_ethphy_liteethphymiitx_converter_source_ready; -wire main_maccore_ethphy_liteethphymiitx_converter_source_first; -wire main_maccore_ethphy_liteethphymiitx_converter_source_last; -wire [3:0] main_maccore_ethphy_liteethphymiitx_converter_source_payload_data; -wire main_maccore_ethphy_liteethphymiitx_converter_converter_sink_valid; -wire main_maccore_ethphy_liteethphymiitx_converter_converter_sink_ready; -wire main_maccore_ethphy_liteethphymiitx_converter_converter_sink_first; -wire main_maccore_ethphy_liteethphymiitx_converter_converter_sink_last; -reg [7:0] main_maccore_ethphy_liteethphymiitx_converter_converter_sink_payload_data = 8'd0; -wire main_maccore_ethphy_liteethphymiitx_converter_converter_source_valid; -wire main_maccore_ethphy_liteethphymiitx_converter_converter_source_ready; -wire main_maccore_ethphy_liteethphymiitx_converter_converter_source_first; -wire main_maccore_ethphy_liteethphymiitx_converter_converter_source_last; -reg [3:0] main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_data = 4'd0; -wire main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_valid_token_count; -reg main_maccore_ethphy_liteethphymiitx_converter_converter_mux = 1'd0; -wire main_maccore_ethphy_liteethphymiitx_converter_converter_first; -wire main_maccore_ethphy_liteethphymiitx_converter_converter_last; -wire main_maccore_ethphy_liteethphymiitx_converter_source_source_valid; -wire main_maccore_ethphy_liteethphymiitx_converter_source_source_ready; -wire main_maccore_ethphy_liteethphymiitx_converter_source_source_first; -wire main_maccore_ethphy_liteethphymiitx_converter_source_source_last; -wire [3:0] main_maccore_ethphy_liteethphymiitx_converter_source_source_payload_data; -wire main_maccore_ethphy_liteethphymiirx_source_source_valid; -wire main_maccore_ethphy_liteethphymiirx_source_source_ready; -wire main_maccore_ethphy_liteethphymiirx_source_source_first; -wire main_maccore_ethphy_liteethphymiirx_source_source_last; -wire [7:0] main_maccore_ethphy_liteethphymiirx_source_source_payload_data; -reg main_maccore_ethphy_liteethphymiirx_source_source_payload_last_be = 1'd0; -reg main_maccore_ethphy_liteethphymiirx_source_source_payload_error = 1'd0; -reg main_maccore_ethphy_liteethphymiirx_converter_sink_valid = 1'd0; -wire main_maccore_ethphy_liteethphymiirx_converter_sink_ready; -reg main_maccore_ethphy_liteethphymiirx_converter_sink_first = 1'd0; -wire main_maccore_ethphy_liteethphymiirx_converter_sink_last; -reg [3:0] main_maccore_ethphy_liteethphymiirx_converter_sink_payload_data = 4'd0; -wire main_maccore_ethphy_liteethphymiirx_converter_source_valid; -wire main_maccore_ethphy_liteethphymiirx_converter_source_ready; -wire main_maccore_ethphy_liteethphymiirx_converter_source_first; -wire main_maccore_ethphy_liteethphymiirx_converter_source_last; -reg [7:0] main_maccore_ethphy_liteethphymiirx_converter_source_payload_data = 8'd0; -wire main_maccore_ethphy_liteethphymiirx_converter_converter_sink_valid; -wire main_maccore_ethphy_liteethphymiirx_converter_converter_sink_ready; -wire main_maccore_ethphy_liteethphymiirx_converter_converter_sink_first; -wire main_maccore_ethphy_liteethphymiirx_converter_converter_sink_last; -wire [3:0] main_maccore_ethphy_liteethphymiirx_converter_converter_sink_payload_data; -wire main_maccore_ethphy_liteethphymiirx_converter_converter_source_valid; -wire main_maccore_ethphy_liteethphymiirx_converter_converter_source_ready; -reg main_maccore_ethphy_liteethphymiirx_converter_converter_source_first = 1'd0; -reg main_maccore_ethphy_liteethphymiirx_converter_converter_source_last = 1'd0; -reg [7:0] main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_data = 8'd0; -reg [1:0] main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_valid_token_count = 2'd0; -reg main_maccore_ethphy_liteethphymiirx_converter_converter_demux = 1'd0; -wire main_maccore_ethphy_liteethphymiirx_converter_converter_load_part; -reg main_maccore_ethphy_liteethphymiirx_converter_converter_strobe_all = 1'd0; -wire main_maccore_ethphy_liteethphymiirx_converter_source_source_valid; -wire main_maccore_ethphy_liteethphymiirx_converter_source_source_ready; -wire main_maccore_ethphy_liteethphymiirx_converter_source_source_first; -wire main_maccore_ethphy_liteethphymiirx_converter_source_source_last; -wire [7:0] main_maccore_ethphy_liteethphymiirx_converter_source_source_payload_data; -reg main_maccore_ethphy_liteethphymiirx_converter_reset = 1'd0; -wire main_maccore_ethphy_mdc; -wire main_maccore_ethphy_oe; -wire main_maccore_ethphy_w; -reg [2:0] main_maccore_ethphy__w_storage = 3'd0; -reg main_maccore_ethphy__w_re = 1'd0; -reg main_maccore_ethphy_r = 1'd0; -reg main_maccore_ethphy__r_status = 1'd0; -wire main_maccore_ethphy__r_we; -reg main_maccore_ethphy__r_re = 1'd0; -wire main_maccore_ethphy_data_w; -wire main_maccore_ethphy_data_oe; -wire main_maccore_ethphy_data_r; -wire main_tx_gap_inserter_sink_valid; -reg main_tx_gap_inserter_sink_ready = 1'd0; -wire main_tx_gap_inserter_sink_first; -wire main_tx_gap_inserter_sink_last; -wire [7:0] main_tx_gap_inserter_sink_payload_data; -wire main_tx_gap_inserter_sink_payload_last_be; -wire main_tx_gap_inserter_sink_payload_error; -reg main_tx_gap_inserter_source_valid = 1'd0; -wire main_tx_gap_inserter_source_ready; -reg main_tx_gap_inserter_source_first = 1'd0; -reg main_tx_gap_inserter_source_last = 1'd0; -reg [7:0] main_tx_gap_inserter_source_payload_data = 8'd0; -reg main_tx_gap_inserter_source_payload_last_be = 1'd0; -reg main_tx_gap_inserter_source_payload_error = 1'd0; -reg [3:0] main_tx_gap_inserter_counter = 4'd0; -reg main_preamble_crc_status = 1'd1; -wire main_preamble_crc_we; -reg main_preamble_crc_re = 1'd0; -reg [31:0] main_preamble_errors_status = 32'd0; -wire main_preamble_errors_we; -reg main_preamble_errors_re = 1'd0; -reg [31:0] main_crc_errors_status = 32'd0; -wire main_crc_errors_we; -reg main_crc_errors_re = 1'd0; -wire main_preamble_inserter_sink_valid; -reg main_preamble_inserter_sink_ready = 1'd0; -wire main_preamble_inserter_sink_first; -wire main_preamble_inserter_sink_last; -wire [7:0] main_preamble_inserter_sink_payload_data; -wire main_preamble_inserter_sink_payload_last_be; -wire main_preamble_inserter_sink_payload_error; -reg main_preamble_inserter_source_valid = 1'd0; -wire main_preamble_inserter_source_ready; -reg main_preamble_inserter_source_first = 1'd0; -reg main_preamble_inserter_source_last = 1'd0; -reg [7:0] main_preamble_inserter_source_payload_data = 8'd0; -wire main_preamble_inserter_source_payload_last_be; -reg main_preamble_inserter_source_payload_error = 1'd0; -reg [63:0] main_preamble_inserter_preamble = 64'd15372286728091293013; -reg [2:0] main_preamble_inserter_count = 3'd0; -wire main_preamble_checker_sink_valid; -reg main_preamble_checker_sink_ready = 1'd0; -wire main_preamble_checker_sink_first; -wire main_preamble_checker_sink_last; -wire [7:0] main_preamble_checker_sink_payload_data; -wire main_preamble_checker_sink_payload_last_be; -wire main_preamble_checker_sink_payload_error; -reg main_preamble_checker_source_valid = 1'd0; -wire main_preamble_checker_source_ready; -reg main_preamble_checker_source_first = 1'd0; -reg main_preamble_checker_source_last = 1'd0; -wire [7:0] main_preamble_checker_source_payload_data; -wire main_preamble_checker_source_payload_last_be; -reg main_preamble_checker_source_payload_error = 1'd0; -reg main_preamble_checker_error = 1'd0; -wire main_liteethmaccrc32inserter_sink_valid; -reg main_liteethmaccrc32inserter_sink_ready = 1'd0; -wire main_liteethmaccrc32inserter_sink_first; -wire main_liteethmaccrc32inserter_sink_last; -wire [7:0] main_liteethmaccrc32inserter_sink_payload_data; -wire main_liteethmaccrc32inserter_sink_payload_last_be; -wire main_liteethmaccrc32inserter_sink_payload_error; -reg main_liteethmaccrc32inserter_source_valid = 1'd0; -wire main_liteethmaccrc32inserter_source_ready; -reg main_liteethmaccrc32inserter_source_first = 1'd0; -reg main_liteethmaccrc32inserter_source_last = 1'd0; -reg [7:0] main_liteethmaccrc32inserter_source_payload_data = 8'd0; -reg main_liteethmaccrc32inserter_source_payload_last_be = 1'd0; -reg main_liteethmaccrc32inserter_source_payload_error = 1'd0; -reg [7:0] main_liteethmaccrc32inserter_data0 = 8'd0; -wire [31:0] main_liteethmaccrc32inserter_value; -wire main_liteethmaccrc32inserter_error; -wire [7:0] main_liteethmaccrc32inserter_data1; -wire [31:0] main_liteethmaccrc32inserter_last; -reg [31:0] main_liteethmaccrc32inserter_next = 32'd0; -reg [31:0] main_liteethmaccrc32inserter_reg = 32'd4294967295; -reg main_liteethmaccrc32inserter_ce = 1'd0; -reg main_liteethmaccrc32inserter_reset = 1'd0; -reg [1:0] main_liteethmaccrc32inserter_cnt = 2'd3; -wire main_liteethmaccrc32inserter_cnt_done; -reg main_liteethmaccrc32inserter_is_ongoing0 = 1'd0; -reg main_liteethmaccrc32inserter_is_ongoing1 = 1'd0; -wire main_crc32_inserter_sink_valid; -wire main_crc32_inserter_sink_ready; -wire main_crc32_inserter_sink_first; -wire main_crc32_inserter_sink_last; -wire [7:0] main_crc32_inserter_sink_payload_data; -wire main_crc32_inserter_sink_payload_last_be; -wire main_crc32_inserter_sink_payload_error; -reg main_crc32_inserter_source_valid = 1'd0; -wire main_crc32_inserter_source_ready; -reg main_crc32_inserter_source_first = 1'd0; -reg main_crc32_inserter_source_last = 1'd0; -reg [7:0] main_crc32_inserter_source_payload_data = 8'd0; -reg main_crc32_inserter_source_payload_last_be = 1'd0; -reg main_crc32_inserter_source_payload_error = 1'd0; -wire main_liteethmaccrc32checker_sink_sink_valid; -reg main_liteethmaccrc32checker_sink_sink_ready = 1'd0; -wire main_liteethmaccrc32checker_sink_sink_first; -wire main_liteethmaccrc32checker_sink_sink_last; -wire [7:0] main_liteethmaccrc32checker_sink_sink_payload_data; -wire main_liteethmaccrc32checker_sink_sink_payload_last_be; -wire main_liteethmaccrc32checker_sink_sink_payload_error; -wire main_liteethmaccrc32checker_source_source_valid; -wire main_liteethmaccrc32checker_source_source_ready; -reg main_liteethmaccrc32checker_source_source_first = 1'd0; -wire main_liteethmaccrc32checker_source_source_last; -wire [7:0] main_liteethmaccrc32checker_source_source_payload_data; -wire main_liteethmaccrc32checker_source_source_payload_last_be; -reg main_liteethmaccrc32checker_source_source_payload_error = 1'd0; -wire main_liteethmaccrc32checker_error; -wire [7:0] main_liteethmaccrc32checker_crc_data0; -wire [31:0] main_liteethmaccrc32checker_crc_value; -wire main_liteethmaccrc32checker_crc_error; -wire [7:0] main_liteethmaccrc32checker_crc_data1; -wire [31:0] main_liteethmaccrc32checker_crc_last; -reg [31:0] main_liteethmaccrc32checker_crc_next = 32'd0; -reg [31:0] main_liteethmaccrc32checker_crc_reg = 32'd4294967295; -reg main_liteethmaccrc32checker_crc_ce = 1'd0; -reg main_liteethmaccrc32checker_crc_reset = 1'd0; -reg main_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; -wire main_liteethmaccrc32checker_syncfifo_sink_ready; -wire main_liteethmaccrc32checker_syncfifo_sink_first; -wire main_liteethmaccrc32checker_syncfifo_sink_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_sink_payload_data; -wire main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; -wire main_liteethmaccrc32checker_syncfifo_sink_payload_error; -wire main_liteethmaccrc32checker_syncfifo_source_valid; -wire main_liteethmaccrc32checker_syncfifo_source_ready; -wire main_liteethmaccrc32checker_syncfifo_source_first; -wire main_liteethmaccrc32checker_syncfifo_source_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_source_payload_data; -wire main_liteethmaccrc32checker_syncfifo_source_payload_last_be; -wire main_liteethmaccrc32checker_syncfifo_source_payload_error; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_we; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_writable; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_re; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_readable; -wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_din; -wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_dout; -reg [2:0] main_liteethmaccrc32checker_syncfifo_level = 3'd0; -reg main_liteethmaccrc32checker_syncfifo_replace = 1'd0; -reg [2:0] main_liteethmaccrc32checker_syncfifo_produce = 3'd0; -reg [2:0] main_liteethmaccrc32checker_syncfifo_consume = 3'd0; -reg [2:0] main_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; -wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_r; -wire main_liteethmaccrc32checker_syncfifo_wrport_we; -wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_w; -wire main_liteethmaccrc32checker_syncfifo_do_read; -wire [2:0] main_liteethmaccrc32checker_syncfifo_rdport_adr; -wire [11:0] main_liteethmaccrc32checker_syncfifo_rdport_dat_r; -wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_first; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_first; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_last; -reg main_liteethmaccrc32checker_fifo_reset = 1'd0; -wire main_liteethmaccrc32checker_fifo_in; -wire main_liteethmaccrc32checker_fifo_out; -wire main_liteethmaccrc32checker_fifo_full; -wire main_crc32_checker_sink_valid; -wire main_crc32_checker_sink_ready; -wire main_crc32_checker_sink_first; -wire main_crc32_checker_sink_last; -wire [7:0] main_crc32_checker_sink_payload_data; -wire main_crc32_checker_sink_payload_last_be; -wire main_crc32_checker_sink_payload_error; -reg main_crc32_checker_source_valid = 1'd0; -wire main_crc32_checker_source_ready; -reg main_crc32_checker_source_first = 1'd0; -reg main_crc32_checker_source_last = 1'd0; -reg [7:0] main_crc32_checker_source_payload_data = 8'd0; -reg main_crc32_checker_source_payload_last_be = 1'd0; -reg main_crc32_checker_source_payload_error = 1'd0; -wire main_ps_preamble_error_i; -wire main_ps_preamble_error_o; -reg main_ps_preamble_error_toggle_i = 1'd0; -wire main_ps_preamble_error_toggle_o; -reg main_ps_preamble_error_toggle_o_r = 1'd0; -wire main_ps_crc_error_i; -wire main_ps_crc_error_o; -reg main_ps_crc_error_toggle_i = 1'd0; -wire main_ps_crc_error_toggle_o; -reg main_ps_crc_error_toggle_o_r = 1'd0; -wire main_padding_inserter_sink_valid; -reg main_padding_inserter_sink_ready = 1'd0; -wire main_padding_inserter_sink_first; -wire main_padding_inserter_sink_last; -wire [7:0] main_padding_inserter_sink_payload_data; -wire main_padding_inserter_sink_payload_last_be; -wire main_padding_inserter_sink_payload_error; -reg main_padding_inserter_source_valid = 1'd0; -wire main_padding_inserter_source_ready; -reg main_padding_inserter_source_first = 1'd0; -reg main_padding_inserter_source_last = 1'd0; -reg [7:0] main_padding_inserter_source_payload_data = 8'd0; -reg main_padding_inserter_source_payload_last_be = 1'd0; -reg main_padding_inserter_source_payload_error = 1'd0; -reg [15:0] main_padding_inserter_counter = 16'd0; -wire main_padding_inserter_counter_done; -wire main_padding_checker_sink_valid; -wire main_padding_checker_sink_ready; -wire main_padding_checker_sink_first; -wire main_padding_checker_sink_last; -wire [7:0] main_padding_checker_sink_payload_data; -wire main_padding_checker_sink_payload_last_be; -wire main_padding_checker_sink_payload_error; -wire main_padding_checker_source_valid; -wire main_padding_checker_source_ready; -wire main_padding_checker_source_first; -wire main_padding_checker_source_last; -wire [7:0] main_padding_checker_source_payload_data; -wire main_padding_checker_source_payload_last_be; -wire main_padding_checker_source_payload_error; -wire main_tx_last_be_sink_valid; -reg main_tx_last_be_sink_ready = 1'd0; -wire main_tx_last_be_sink_first; -wire main_tx_last_be_sink_last; -wire [7:0] main_tx_last_be_sink_payload_data; -wire main_tx_last_be_sink_payload_last_be; -wire main_tx_last_be_sink_payload_error; -reg main_tx_last_be_source_valid = 1'd0; -wire main_tx_last_be_source_ready; -reg main_tx_last_be_source_first = 1'd0; -reg main_tx_last_be_source_last = 1'd0; -reg [7:0] main_tx_last_be_source_payload_data = 8'd0; -reg main_tx_last_be_source_payload_last_be = 1'd0; -reg main_tx_last_be_source_payload_error = 1'd0; -wire main_rx_last_be_sink_valid; -wire main_rx_last_be_sink_ready; -wire main_rx_last_be_sink_first; -wire main_rx_last_be_sink_last; -wire [7:0] main_rx_last_be_sink_payload_data; -wire main_rx_last_be_sink_payload_last_be; -wire main_rx_last_be_sink_payload_error; -wire main_rx_last_be_source_valid; -wire main_rx_last_be_source_ready; -wire main_rx_last_be_source_first; -wire main_rx_last_be_source_last; -wire [7:0] main_rx_last_be_source_payload_data; -reg main_rx_last_be_source_payload_last_be = 1'd0; -wire main_rx_last_be_source_payload_error; -wire main_tx_converter_sink_valid; -wire main_tx_converter_sink_ready; -wire main_tx_converter_sink_first; -wire main_tx_converter_sink_last; -wire [31:0] main_tx_converter_sink_payload_data; -wire [3:0] main_tx_converter_sink_payload_last_be; -wire [3:0] main_tx_converter_sink_payload_error; -wire main_tx_converter_source_valid; -wire main_tx_converter_source_ready; -wire main_tx_converter_source_first; -wire main_tx_converter_source_last; -wire [7:0] main_tx_converter_source_payload_data; -wire main_tx_converter_source_payload_last_be; -wire main_tx_converter_source_payload_error; -wire main_tx_converter_converter_sink_valid; -wire main_tx_converter_converter_sink_ready; -wire main_tx_converter_converter_sink_first; -wire main_tx_converter_converter_sink_last; -reg [39:0] main_tx_converter_converter_sink_payload_data = 40'd0; -wire main_tx_converter_converter_source_valid; -wire main_tx_converter_converter_source_ready; -wire main_tx_converter_converter_source_first; -wire main_tx_converter_converter_source_last; -reg [9:0] main_tx_converter_converter_source_payload_data = 10'd0; -wire main_tx_converter_converter_source_payload_valid_token_count; -reg [1:0] main_tx_converter_converter_mux = 2'd0; -wire main_tx_converter_converter_first; -wire main_tx_converter_converter_last; -wire main_tx_converter_source_source_valid; -wire main_tx_converter_source_source_ready; -wire main_tx_converter_source_source_first; -wire main_tx_converter_source_source_last; -wire [9:0] main_tx_converter_source_source_payload_data; -wire main_rx_converter_sink_valid; -wire main_rx_converter_sink_ready; -wire main_rx_converter_sink_first; -wire main_rx_converter_sink_last; -wire [7:0] main_rx_converter_sink_payload_data; -wire main_rx_converter_sink_payload_last_be; -wire main_rx_converter_sink_payload_error; -wire main_rx_converter_source_valid; -wire main_rx_converter_source_ready; -wire main_rx_converter_source_first; -wire main_rx_converter_source_last; -reg [31:0] main_rx_converter_source_payload_data = 32'd0; -reg [3:0] main_rx_converter_source_payload_last_be = 4'd0; -reg [3:0] main_rx_converter_source_payload_error = 4'd0; -wire main_rx_converter_converter_sink_valid; -wire main_rx_converter_converter_sink_ready; -wire main_rx_converter_converter_sink_first; -wire main_rx_converter_converter_sink_last; -wire [9:0] main_rx_converter_converter_sink_payload_data; -wire main_rx_converter_converter_source_valid; -wire main_rx_converter_converter_source_ready; -reg main_rx_converter_converter_source_first = 1'd0; -reg main_rx_converter_converter_source_last = 1'd0; -reg [39:0] main_rx_converter_converter_source_payload_data = 40'd0; -reg [2:0] main_rx_converter_converter_source_payload_valid_token_count = 3'd0; -reg [1:0] main_rx_converter_converter_demux = 2'd0; -wire main_rx_converter_converter_load_part; -reg main_rx_converter_converter_strobe_all = 1'd0; -wire main_rx_converter_source_source_valid; -wire main_rx_converter_source_source_ready; -wire main_rx_converter_source_source_first; -wire main_rx_converter_source_source_last; -wire [39:0] main_rx_converter_source_source_payload_data; -wire main_tx_cdc_sink_sink_valid; -wire main_tx_cdc_sink_sink_ready; -wire main_tx_cdc_sink_sink_first; -wire main_tx_cdc_sink_sink_last; -wire [31:0] main_tx_cdc_sink_sink_payload_data; -wire [3:0] main_tx_cdc_sink_sink_payload_last_be; -wire [3:0] main_tx_cdc_sink_sink_payload_error; -wire main_tx_cdc_source_source_valid; -wire main_tx_cdc_source_source_ready; -wire main_tx_cdc_source_source_first; -wire main_tx_cdc_source_source_last; -wire [31:0] main_tx_cdc_source_source_payload_data; -wire [3:0] main_tx_cdc_source_source_payload_last_be; -wire [3:0] main_tx_cdc_source_source_payload_error; -wire main_tx_cdc_cdc_sink_valid; -wire main_tx_cdc_cdc_sink_ready; -wire main_tx_cdc_cdc_sink_first; -wire main_tx_cdc_cdc_sink_last; -wire [31:0] main_tx_cdc_cdc_sink_payload_data; -wire [3:0] main_tx_cdc_cdc_sink_payload_last_be; -wire [3:0] main_tx_cdc_cdc_sink_payload_error; -wire main_tx_cdc_cdc_source_valid; -wire main_tx_cdc_cdc_source_ready; -wire main_tx_cdc_cdc_source_first; -wire main_tx_cdc_cdc_source_last; -wire [31:0] main_tx_cdc_cdc_source_payload_data; -wire [3:0] main_tx_cdc_cdc_source_payload_last_be; -wire [3:0] main_tx_cdc_cdc_source_payload_error; -wire main_tx_cdc_cdc_asyncfifo_we; -wire main_tx_cdc_cdc_asyncfifo_writable; -wire main_tx_cdc_cdc_asyncfifo_re; -wire main_tx_cdc_cdc_asyncfifo_readable; -wire [41:0] main_tx_cdc_cdc_asyncfifo_din; -wire [41:0] main_tx_cdc_cdc_asyncfifo_dout; -wire main_tx_cdc_cdc_graycounter0_ce; -(* dont_touch = "true" *) reg [5:0] main_tx_cdc_cdc_graycounter0_q = 6'd0; -wire [5:0] main_tx_cdc_cdc_graycounter0_q_next; -reg [5:0] main_tx_cdc_cdc_graycounter0_q_binary = 6'd0; -reg [5:0] main_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; -wire main_tx_cdc_cdc_graycounter1_ce; -(* dont_touch = "true" *) reg [5:0] main_tx_cdc_cdc_graycounter1_q = 6'd0; -wire [5:0] main_tx_cdc_cdc_graycounter1_q_next; -reg [5:0] main_tx_cdc_cdc_graycounter1_q_binary = 6'd0; -reg [5:0] main_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; -wire [5:0] main_tx_cdc_cdc_produce_rdomain; -wire [5:0] main_tx_cdc_cdc_consume_wdomain; -wire [4:0] main_tx_cdc_cdc_wrport_adr; -wire [41:0] main_tx_cdc_cdc_wrport_dat_r; -wire main_tx_cdc_cdc_wrport_we; -wire [41:0] main_tx_cdc_cdc_wrport_dat_w; -wire [4:0] main_tx_cdc_cdc_rdport_adr; -wire [41:0] main_tx_cdc_cdc_rdport_dat_r; -wire [31:0] main_tx_cdc_cdc_fifo_in_payload_data; -wire [3:0] main_tx_cdc_cdc_fifo_in_payload_last_be; -wire [3:0] main_tx_cdc_cdc_fifo_in_payload_error; -wire main_tx_cdc_cdc_fifo_in_first; -wire main_tx_cdc_cdc_fifo_in_last; -wire [31:0] main_tx_cdc_cdc_fifo_out_payload_data; -wire [3:0] main_tx_cdc_cdc_fifo_out_payload_last_be; -wire [3:0] main_tx_cdc_cdc_fifo_out_payload_error; -wire main_tx_cdc_cdc_fifo_out_first; -wire main_tx_cdc_cdc_fifo_out_last; -wire main_rx_cdc_sink_sink_valid; -wire main_rx_cdc_sink_sink_ready; -wire main_rx_cdc_sink_sink_first; -wire main_rx_cdc_sink_sink_last; -wire [31:0] main_rx_cdc_sink_sink_payload_data; -wire [3:0] main_rx_cdc_sink_sink_payload_last_be; -wire [3:0] main_rx_cdc_sink_sink_payload_error; -wire main_rx_cdc_source_source_valid; -wire main_rx_cdc_source_source_ready; -wire main_rx_cdc_source_source_first; -wire main_rx_cdc_source_source_last; -wire [31:0] main_rx_cdc_source_source_payload_data; -wire [3:0] main_rx_cdc_source_source_payload_last_be; -wire [3:0] main_rx_cdc_source_source_payload_error; -wire main_rx_cdc_cdc_sink_valid; -wire main_rx_cdc_cdc_sink_ready; -wire main_rx_cdc_cdc_sink_first; -wire main_rx_cdc_cdc_sink_last; -wire [31:0] main_rx_cdc_cdc_sink_payload_data; -wire [3:0] main_rx_cdc_cdc_sink_payload_last_be; -wire [3:0] main_rx_cdc_cdc_sink_payload_error; -wire main_rx_cdc_cdc_source_valid; -wire main_rx_cdc_cdc_source_ready; -wire main_rx_cdc_cdc_source_first; -wire main_rx_cdc_cdc_source_last; -wire [31:0] main_rx_cdc_cdc_source_payload_data; -wire [3:0] main_rx_cdc_cdc_source_payload_last_be; -wire [3:0] main_rx_cdc_cdc_source_payload_error; -wire main_rx_cdc_cdc_asyncfifo_we; -wire main_rx_cdc_cdc_asyncfifo_writable; -wire main_rx_cdc_cdc_asyncfifo_re; -wire main_rx_cdc_cdc_asyncfifo_readable; -wire [41:0] main_rx_cdc_cdc_asyncfifo_din; -wire [41:0] main_rx_cdc_cdc_asyncfifo_dout; -wire main_rx_cdc_cdc_graycounter0_ce; -(* dont_touch = "true" *) reg [5:0] main_rx_cdc_cdc_graycounter0_q = 6'd0; -wire [5:0] main_rx_cdc_cdc_graycounter0_q_next; -reg [5:0] main_rx_cdc_cdc_graycounter0_q_binary = 6'd0; -reg [5:0] main_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; -wire main_rx_cdc_cdc_graycounter1_ce; -(* dont_touch = "true" *) reg [5:0] main_rx_cdc_cdc_graycounter1_q = 6'd0; -wire [5:0] main_rx_cdc_cdc_graycounter1_q_next; -reg [5:0] main_rx_cdc_cdc_graycounter1_q_binary = 6'd0; -reg [5:0] main_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; -wire [5:0] main_rx_cdc_cdc_produce_rdomain; -wire [5:0] main_rx_cdc_cdc_consume_wdomain; -wire [4:0] main_rx_cdc_cdc_wrport_adr; -wire [41:0] main_rx_cdc_cdc_wrport_dat_r; -wire main_rx_cdc_cdc_wrport_we; -wire [41:0] main_rx_cdc_cdc_wrport_dat_w; -wire [4:0] main_rx_cdc_cdc_rdport_adr; -wire [41:0] main_rx_cdc_cdc_rdport_dat_r; -wire [31:0] main_rx_cdc_cdc_fifo_in_payload_data; -wire [3:0] main_rx_cdc_cdc_fifo_in_payload_last_be; -wire [3:0] main_rx_cdc_cdc_fifo_in_payload_error; -wire main_rx_cdc_cdc_fifo_in_first; -wire main_rx_cdc_cdc_fifo_in_last; -wire [31:0] main_rx_cdc_cdc_fifo_out_payload_data; -wire [3:0] main_rx_cdc_cdc_fifo_out_payload_last_be; -wire [3:0] main_rx_cdc_cdc_fifo_out_payload_error; -wire main_rx_cdc_cdc_fifo_out_first; -wire main_rx_cdc_cdc_fifo_out_last; -wire main_sink_valid; -wire main_sink_ready; -wire main_sink_first; -wire main_sink_last; -wire [31:0] main_sink_payload_data; -wire [3:0] main_sink_payload_last_be; -wire [3:0] main_sink_payload_error; -wire main_source_valid; -wire main_source_ready; -wire main_source_first; -wire main_source_last; -wire [31:0] main_source_payload_data; -wire [3:0] main_source_payload_last_be; -wire [3:0] main_source_payload_error; -wire [29:0] main_bus_adr; -wire [31:0] main_bus_dat_w; -wire [31:0] main_bus_dat_r; -wire [3:0] main_bus_sel; -wire main_bus_cyc; -wire main_bus_stb; -wire main_bus_ack; -wire main_bus_we; -wire [2:0] main_bus_cti; -wire [1:0] main_bus_bte; -wire main_bus_err; -wire main_writer_sink_sink_valid; -reg main_writer_sink_sink_ready = 1'd1; -wire main_writer_sink_sink_first; -wire main_writer_sink_sink_last; -wire [31:0] main_writer_sink_sink_payload_data; -wire [3:0] main_writer_sink_sink_payload_last_be; -wire [3:0] main_writer_sink_sink_payload_error; -wire main_writer_slot_status; -wire main_writer_slot_we; -reg main_writer_slot_re = 1'd0; -wire [31:0] main_writer_length_status; -wire main_writer_length_we; -reg main_writer_length_re = 1'd0; -reg [31:0] main_writer_errors_status = 32'd0; -wire main_writer_errors_we; -reg main_writer_errors_re = 1'd0; -wire main_writer_irq; -wire main_writer_available_status; -wire main_writer_available_pending; -wire main_writer_available_trigger; -reg main_writer_available_clear = 1'd0; -wire main_writer_available0; -wire main_writer_status_status; -wire main_writer_status_we; -reg main_writer_status_re = 1'd0; -wire main_writer_available1; -wire main_writer_pending_status; -wire main_writer_pending_we; -reg main_writer_pending_re = 1'd0; -reg main_writer_pending_r = 1'd0; -wire main_writer_available2; -reg main_writer_enable_storage = 1'd0; -reg main_writer_enable_re = 1'd0; -reg [2:0] main_writer_inc = 3'd0; -reg [31:0] main_writer_counter = 32'd0; -reg main_writer_slot = 1'd0; -reg main_writer_slot_ce = 1'd0; -reg main_writer_start = 1'd0; -reg main_writer_ongoing = 1'd0; -reg main_writer_stat_fifo_sink_valid = 1'd0; -wire main_writer_stat_fifo_sink_ready; -reg main_writer_stat_fifo_sink_first = 1'd0; -reg main_writer_stat_fifo_sink_last = 1'd0; -wire main_writer_stat_fifo_sink_payload_slot; -wire [31:0] main_writer_stat_fifo_sink_payload_length; -wire main_writer_stat_fifo_source_valid; -wire main_writer_stat_fifo_source_ready; -wire main_writer_stat_fifo_source_first; -wire main_writer_stat_fifo_source_last; -wire main_writer_stat_fifo_source_payload_slot; -wire [31:0] main_writer_stat_fifo_source_payload_length; -wire main_writer_stat_fifo_syncfifo_we; -wire main_writer_stat_fifo_syncfifo_writable; -wire main_writer_stat_fifo_syncfifo_re; -wire main_writer_stat_fifo_syncfifo_readable; -wire [34:0] main_writer_stat_fifo_syncfifo_din; -wire [34:0] main_writer_stat_fifo_syncfifo_dout; -reg [1:0] main_writer_stat_fifo_level = 2'd0; -reg main_writer_stat_fifo_replace = 1'd0; -reg main_writer_stat_fifo_produce = 1'd0; -reg main_writer_stat_fifo_consume = 1'd0; -reg main_writer_stat_fifo_wrport_adr = 1'd0; -wire [34:0] main_writer_stat_fifo_wrport_dat_r; -wire main_writer_stat_fifo_wrport_we; -wire [34:0] main_writer_stat_fifo_wrport_dat_w; -wire main_writer_stat_fifo_do_read; -wire main_writer_stat_fifo_rdport_adr; -wire [34:0] main_writer_stat_fifo_rdport_dat_r; -wire main_writer_stat_fifo_fifo_in_payload_slot; -wire [31:0] main_writer_stat_fifo_fifo_in_payload_length; -wire main_writer_stat_fifo_fifo_in_first; -wire main_writer_stat_fifo_fifo_in_last; -wire main_writer_stat_fifo_fifo_out_payload_slot; -wire [31:0] main_writer_stat_fifo_fifo_out_payload_length; -wire main_writer_stat_fifo_fifo_out_first; -wire main_writer_stat_fifo_fifo_out_last; -reg [8:0] main_writer_memory0_adr = 9'd0; -wire [31:0] main_writer_memory0_dat_r; -reg main_writer_memory0_we = 1'd0; -reg [31:0] main_writer_memory0_dat_w = 32'd0; -reg [8:0] main_writer_memory1_adr = 9'd0; -wire [31:0] main_writer_memory1_dat_r; -reg main_writer_memory1_we = 1'd0; -reg [31:0] main_writer_memory1_dat_w = 32'd0; -reg main_reader_source_source_valid = 1'd0; -wire main_reader_source_source_ready; -reg main_reader_source_source_first = 1'd0; -reg main_reader_source_source_last = 1'd0; -reg [31:0] main_reader_source_source_payload_data = 32'd0; -reg [3:0] main_reader_source_source_payload_last_be = 4'd0; -reg [3:0] main_reader_source_source_payload_error = 4'd0; -reg main_reader_start_start_re = 1'd0; -wire main_reader_start_start_r; -reg main_reader_start_start_we = 1'd0; -reg main_reader_start_start_w = 1'd0; -wire main_reader_ready_status; -wire main_reader_ready_we; -reg main_reader_ready_re = 1'd0; -wire [1:0] main_reader_level_status; -wire main_reader_level_we; -reg main_reader_level_re = 1'd0; -reg main_reader_slot_storage = 1'd0; -reg main_reader_slot_re = 1'd0; -reg [10:0] main_reader_length_storage = 11'd0; -reg main_reader_length_re = 1'd0; -wire main_reader_irq; -wire main_reader_eventsourcepulse_status; -reg main_reader_eventsourcepulse_pending = 1'd0; -reg main_reader_eventsourcepulse_trigger = 1'd0; -reg main_reader_eventsourcepulse_clear = 1'd0; -wire main_reader_event00; -wire main_reader_status_status; -wire main_reader_status_we; -reg main_reader_status_re = 1'd0; -wire main_reader_event01; -wire main_reader_pending_status; -wire main_reader_pending_we; -reg main_reader_pending_re = 1'd0; -reg main_reader_pending_r = 1'd0; -wire main_reader_event02; -reg main_reader_enable_storage = 1'd0; -reg main_reader_enable_re = 1'd0; -reg main_reader_start = 1'd0; -wire main_reader_cmd_fifo_sink_valid; -wire main_reader_cmd_fifo_sink_ready; -reg main_reader_cmd_fifo_sink_first = 1'd0; -reg main_reader_cmd_fifo_sink_last = 1'd0; -wire main_reader_cmd_fifo_sink_payload_slot; -wire [10:0] main_reader_cmd_fifo_sink_payload_length; -wire main_reader_cmd_fifo_source_valid; -reg main_reader_cmd_fifo_source_ready = 1'd0; -wire main_reader_cmd_fifo_source_first; -wire main_reader_cmd_fifo_source_last; -wire main_reader_cmd_fifo_source_payload_slot; -wire [10:0] main_reader_cmd_fifo_source_payload_length; -wire main_reader_cmd_fifo_syncfifo_we; -wire main_reader_cmd_fifo_syncfifo_writable; -wire main_reader_cmd_fifo_syncfifo_re; -wire main_reader_cmd_fifo_syncfifo_readable; -wire [13:0] main_reader_cmd_fifo_syncfifo_din; -wire [13:0] main_reader_cmd_fifo_syncfifo_dout; -reg [1:0] main_reader_cmd_fifo_level = 2'd0; -reg main_reader_cmd_fifo_replace = 1'd0; -reg main_reader_cmd_fifo_produce = 1'd0; -reg main_reader_cmd_fifo_consume = 1'd0; -reg main_reader_cmd_fifo_wrport_adr = 1'd0; -wire [13:0] main_reader_cmd_fifo_wrport_dat_r; -wire main_reader_cmd_fifo_wrport_we; -wire [13:0] main_reader_cmd_fifo_wrport_dat_w; -wire main_reader_cmd_fifo_do_read; -wire main_reader_cmd_fifo_rdport_adr; -wire [13:0] main_reader_cmd_fifo_rdport_dat_r; -wire main_reader_cmd_fifo_fifo_in_payload_slot; -wire [10:0] main_reader_cmd_fifo_fifo_in_payload_length; -wire main_reader_cmd_fifo_fifo_in_first; -wire main_reader_cmd_fifo_fifo_in_last; -wire main_reader_cmd_fifo_fifo_out_payload_slot; -wire [10:0] main_reader_cmd_fifo_fifo_out_payload_length; -wire main_reader_cmd_fifo_fifo_out_first; -wire main_reader_cmd_fifo_fifo_out_last; -reg [10:0] main_reader_read_address = 11'd0; -reg [10:0] main_reader_counter = 11'd0; -wire [8:0] main_reader_memory0_adr; -wire [31:0] main_reader_memory0_dat_r; -wire [8:0] main_reader_memory1_adr; -wire [31:0] main_reader_memory1_dat_r; -wire main_ev_irq; -wire [29:0] main_sram0_bus_adr0; -wire [31:0] main_sram0_bus_dat_w0; -wire [31:0] main_sram0_bus_dat_r0; -wire [3:0] main_sram0_bus_sel0; -wire main_sram0_bus_cyc0; -wire main_sram0_bus_stb0; -reg main_sram0_bus_ack0 = 1'd0; -wire main_sram0_bus_we0; -wire [2:0] main_sram0_bus_cti0; -wire [1:0] main_sram0_bus_bte0; -reg main_sram0_bus_err0 = 1'd0; -wire [8:0] main_sram0_adr0; -wire [31:0] main_sram0_dat_r0; -wire [29:0] main_sram1_bus_adr0; -wire [31:0] main_sram1_bus_dat_w0; -wire [31:0] main_sram1_bus_dat_r0; -wire [3:0] main_sram1_bus_sel0; -wire main_sram1_bus_cyc0; -wire main_sram1_bus_stb0; -reg main_sram1_bus_ack0 = 1'd0; -wire main_sram1_bus_we0; -wire [2:0] main_sram1_bus_cti0; -wire [1:0] main_sram1_bus_bte0; -reg main_sram1_bus_err0 = 1'd0; -wire [8:0] main_sram1_adr0; -wire [31:0] main_sram1_dat_r0; -wire [29:0] main_sram0_bus_adr1; -wire [31:0] main_sram0_bus_dat_w1; -wire [31:0] main_sram0_bus_dat_r1; -wire [3:0] main_sram0_bus_sel1; -wire main_sram0_bus_cyc1; -wire main_sram0_bus_stb1; -reg main_sram0_bus_ack1 = 1'd0; -wire main_sram0_bus_we1; -wire [2:0] main_sram0_bus_cti1; -wire [1:0] main_sram0_bus_bte1; -reg main_sram0_bus_err1 = 1'd0; -wire [8:0] main_sram0_adr1; -wire [31:0] main_sram0_dat_r1; -reg [3:0] main_sram0_we = 4'd0; -wire [31:0] main_sram0_dat_w; -wire [29:0] main_sram1_bus_adr1; -wire [31:0] main_sram1_bus_dat_w1; -wire [31:0] main_sram1_bus_dat_r1; -wire [3:0] main_sram1_bus_sel1; -wire main_sram1_bus_cyc1; -wire main_sram1_bus_stb1; -reg main_sram1_bus_ack1 = 1'd0; -wire main_sram1_bus_we1; -wire [2:0] main_sram1_bus_cti1; -wire [1:0] main_sram1_bus_bte1; -reg main_sram1_bus_err1 = 1'd0; -wire [8:0] main_sram1_adr1; -wire [31:0] main_sram1_dat_r1; -reg [3:0] main_sram1_we = 4'd0; -wire [31:0] main_sram1_dat_w; -reg [3:0] main_slave_sel = 4'd0; -reg [3:0] main_slave_sel_r = 4'd0; -wire [29:0] main_wb_bus_adr; -wire [31:0] main_wb_bus_dat_w; -wire [31:0] main_wb_bus_dat_r; -wire [3:0] main_wb_bus_sel; -wire main_wb_bus_cyc; -wire main_wb_bus_stb; -wire main_wb_bus_ack; -wire main_wb_bus_we; -wire [2:0] main_wb_bus_cti; -wire [1:0] main_wb_bus_bte; -wire main_wb_bus_err; -reg builder_liteethmacgap_state = 1'd0; -reg builder_liteethmacgap_next_state = 1'd0; -reg [3:0] main_tx_gap_inserter_counter_liteethmacgap_next_value = 4'd0; -reg main_tx_gap_inserter_counter_liteethmacgap_next_value_ce = 1'd0; -reg [1:0] builder_liteethmacpreambleinserter_state = 2'd0; -reg [1:0] builder_liteethmacpreambleinserter_next_state = 2'd0; -reg [2:0] main_preamble_inserter_count_liteethmacpreambleinserter_next_value = 3'd0; -reg main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce = 1'd0; -reg builder_liteethmacpreamblechecker_state = 1'd0; -reg builder_liteethmacpreamblechecker_next_state = 1'd0; -reg [1:0] builder_liteethmaccrc32inserter_state = 2'd0; -reg [1:0] builder_liteethmaccrc32inserter_next_state = 2'd0; -reg [1:0] builder_liteethmaccrc32checker_state = 2'd0; -reg [1:0] builder_liteethmaccrc32checker_next_state = 2'd0; -reg builder_liteethmacpaddinginserter_state = 1'd0; -reg builder_liteethmacpaddinginserter_next_state = 1'd0; -reg [15:0] main_padding_inserter_counter_liteethmacpaddinginserter_next_value = 16'd0; -reg main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce = 1'd0; -reg builder_liteethmactxlastbe_state = 1'd0; -reg builder_liteethmactxlastbe_next_state = 1'd0; -reg [2:0] builder_liteethmacsramwriter_state = 3'd0; -reg [2:0] builder_liteethmacsramwriter_next_state = 3'd0; -reg [31:0] main_writer_counter_t_next_value = 32'd0; -reg main_writer_counter_t_next_value_ce = 1'd0; -reg [31:0] main_writer_errors_status_f_next_value = 32'd0; -reg main_writer_errors_status_f_next_value_ce = 1'd0; -reg [1:0] builder_liteethmacsramreader_state = 2'd0; -reg [1:0] builder_liteethmacsramreader_next_state = 2'd0; -reg [10:0] main_reader_counter_next_value = 11'd0; -reg main_reader_counter_next_value_ce = 1'd0; -reg [13:0] builder_maccore_adr = 14'd0; -reg builder_maccore_we = 1'd0; -reg [31:0] builder_maccore_dat_w = 32'd0; -wire [31:0] builder_maccore_dat_r; -wire [29:0] builder_maccore_wishbone_adr; -wire [31:0] builder_maccore_wishbone_dat_w; -reg [31:0] builder_maccore_wishbone_dat_r = 32'd0; -wire [3:0] builder_maccore_wishbone_sel; -wire builder_maccore_wishbone_cyc; -wire builder_maccore_wishbone_stb; -reg builder_maccore_wishbone_ack = 1'd0; -wire builder_maccore_wishbone_we; -wire [2:0] builder_maccore_wishbone_cti; -wire [1:0] builder_maccore_wishbone_bte; -reg builder_maccore_wishbone_err = 1'd0; -wire [29:0] builder_shared_adr; -wire [31:0] builder_shared_dat_w; -reg [31:0] builder_shared_dat_r = 32'd0; -wire [3:0] builder_shared_sel; -wire builder_shared_cyc; -wire builder_shared_stb; -reg builder_shared_ack = 1'd0; -wire builder_shared_we; -wire [2:0] builder_shared_cti; -wire [1:0] builder_shared_bte; -wire builder_shared_err; -wire builder_request; -wire builder_grant; -reg [1:0] builder_slave_sel = 2'd0; -reg [1:0] builder_slave_sel_r = 2'd0; -reg builder_error = 1'd0; -wire builder_wait; -wire builder_done; -reg [19:0] builder_count = 20'd1000000; -wire [13:0] builder_interface0_bank_bus_adr; -wire builder_interface0_bank_bus_we; -wire [31:0] builder_interface0_bank_bus_dat_w; -reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; -reg builder_csrbank0_reset0_re = 1'd0; -wire [1:0] builder_csrbank0_reset0_r; -reg builder_csrbank0_reset0_we = 1'd0; -wire [1:0] builder_csrbank0_reset0_w; -reg builder_csrbank0_scratch0_re = 1'd0; -wire [31:0] builder_csrbank0_scratch0_r; -reg builder_csrbank0_scratch0_we = 1'd0; -wire [31:0] builder_csrbank0_scratch0_w; -reg builder_csrbank0_bus_errors_re = 1'd0; -wire [31:0] builder_csrbank0_bus_errors_r; -reg builder_csrbank0_bus_errors_we = 1'd0; -wire [31:0] builder_csrbank0_bus_errors_w; -wire builder_csrbank0_sel; -wire [13:0] builder_interface1_bank_bus_adr; -wire builder_interface1_bank_bus_we; -wire [31:0] builder_interface1_bank_bus_dat_w; -reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; -reg builder_csrbank1_sram_writer_slot_re = 1'd0; -wire builder_csrbank1_sram_writer_slot_r; -reg builder_csrbank1_sram_writer_slot_we = 1'd0; -wire builder_csrbank1_sram_writer_slot_w; -reg builder_csrbank1_sram_writer_length_re = 1'd0; -wire [31:0] builder_csrbank1_sram_writer_length_r; -reg builder_csrbank1_sram_writer_length_we = 1'd0; -wire [31:0] builder_csrbank1_sram_writer_length_w; -reg builder_csrbank1_sram_writer_errors_re = 1'd0; -wire [31:0] builder_csrbank1_sram_writer_errors_r; -reg builder_csrbank1_sram_writer_errors_we = 1'd0; -wire [31:0] builder_csrbank1_sram_writer_errors_w; -reg builder_csrbank1_sram_writer_ev_status_re = 1'd0; -wire builder_csrbank1_sram_writer_ev_status_r; -reg builder_csrbank1_sram_writer_ev_status_we = 1'd0; -wire builder_csrbank1_sram_writer_ev_status_w; -reg builder_csrbank1_sram_writer_ev_pending_re = 1'd0; -wire builder_csrbank1_sram_writer_ev_pending_r; -reg builder_csrbank1_sram_writer_ev_pending_we = 1'd0; -wire builder_csrbank1_sram_writer_ev_pending_w; -reg builder_csrbank1_sram_writer_ev_enable0_re = 1'd0; -wire builder_csrbank1_sram_writer_ev_enable0_r; -reg builder_csrbank1_sram_writer_ev_enable0_we = 1'd0; -wire builder_csrbank1_sram_writer_ev_enable0_w; -reg builder_csrbank1_sram_reader_ready_re = 1'd0; -wire builder_csrbank1_sram_reader_ready_r; -reg builder_csrbank1_sram_reader_ready_we = 1'd0; -wire builder_csrbank1_sram_reader_ready_w; -reg builder_csrbank1_sram_reader_level_re = 1'd0; -wire [1:0] builder_csrbank1_sram_reader_level_r; -reg builder_csrbank1_sram_reader_level_we = 1'd0; -wire [1:0] builder_csrbank1_sram_reader_level_w; -reg builder_csrbank1_sram_reader_slot0_re = 1'd0; -wire builder_csrbank1_sram_reader_slot0_r; -reg builder_csrbank1_sram_reader_slot0_we = 1'd0; -wire builder_csrbank1_sram_reader_slot0_w; -reg builder_csrbank1_sram_reader_length0_re = 1'd0; -wire [10:0] builder_csrbank1_sram_reader_length0_r; -reg builder_csrbank1_sram_reader_length0_we = 1'd0; -wire [10:0] builder_csrbank1_sram_reader_length0_w; -reg builder_csrbank1_sram_reader_ev_status_re = 1'd0; -wire builder_csrbank1_sram_reader_ev_status_r; -reg builder_csrbank1_sram_reader_ev_status_we = 1'd0; -wire builder_csrbank1_sram_reader_ev_status_w; -reg builder_csrbank1_sram_reader_ev_pending_re = 1'd0; -wire builder_csrbank1_sram_reader_ev_pending_r; -reg builder_csrbank1_sram_reader_ev_pending_we = 1'd0; -wire builder_csrbank1_sram_reader_ev_pending_w; -reg builder_csrbank1_sram_reader_ev_enable0_re = 1'd0; -wire builder_csrbank1_sram_reader_ev_enable0_r; -reg builder_csrbank1_sram_reader_ev_enable0_we = 1'd0; -wire builder_csrbank1_sram_reader_ev_enable0_w; -reg builder_csrbank1_preamble_crc_re = 1'd0; -wire builder_csrbank1_preamble_crc_r; -reg builder_csrbank1_preamble_crc_we = 1'd0; -wire builder_csrbank1_preamble_crc_w; -reg builder_csrbank1_preamble_errors_re = 1'd0; -wire [31:0] builder_csrbank1_preamble_errors_r; -reg builder_csrbank1_preamble_errors_we = 1'd0; -wire [31:0] builder_csrbank1_preamble_errors_w; -reg builder_csrbank1_crc_errors_re = 1'd0; -wire [31:0] builder_csrbank1_crc_errors_r; -reg builder_csrbank1_crc_errors_we = 1'd0; -wire [31:0] builder_csrbank1_crc_errors_w; -wire builder_csrbank1_sel; -wire [13:0] builder_interface2_bank_bus_adr; -wire builder_interface2_bank_bus_we; -wire [31:0] builder_interface2_bank_bus_dat_w; -reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; -reg builder_csrbank2_crg_reset0_re = 1'd0; -wire builder_csrbank2_crg_reset0_r; -reg builder_csrbank2_crg_reset0_we = 1'd0; -wire builder_csrbank2_crg_reset0_w; -reg builder_csrbank2_mdio_w0_re = 1'd0; -wire [2:0] builder_csrbank2_mdio_w0_r; -reg builder_csrbank2_mdio_w0_we = 1'd0; -wire [2:0] builder_csrbank2_mdio_w0_w; -reg builder_csrbank2_mdio_r_re = 1'd0; -wire builder_csrbank2_mdio_r_r; -reg builder_csrbank2_mdio_r_we = 1'd0; -wire builder_csrbank2_mdio_r_w; -wire builder_csrbank2_sel; -wire [13:0] builder_csr_interconnect_adr; -wire builder_csr_interconnect_we; -wire [31:0] builder_csr_interconnect_dat_w; -wire [31:0] builder_csr_interconnect_dat_r; -reg builder_state = 1'd0; -reg builder_next_state = 1'd0; -reg [29:0] builder_array_muxed0 = 30'd0; -reg [31:0] builder_array_muxed1 = 32'd0; -reg [3:0] builder_array_muxed2 = 4'd0; -reg builder_array_muxed3 = 1'd0; -reg builder_array_muxed4 = 1'd0; -reg builder_array_muxed5 = 1'd0; -reg [2:0] builder_array_muxed6 = 3'd0; -reg [1:0] builder_array_muxed7 = 2'd0; -wire builder_rst_meta0; -wire builder_rst_meta1; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl0_regs0 = 1'd0; -(* async_reg = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl0_regs1 = 1'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl1_regs0 = 1'd0; -(* async_reg = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl1_regs1 = 1'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl2_regs0 = 1'd0; -(* async_reg = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl2_regs1 = 1'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl3_regs0 = 6'd0; -(* async_reg = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl3_regs1 = 6'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl4_regs0 = 6'd0; -(* async_reg = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl4_regs1 = 6'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl5_regs0 = 6'd0; -(* async_reg = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl5_regs1 = 6'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl6_regs0 = 6'd0; -(* async_reg = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl6_regs1 = 6'd0; + +//------------------------------------------------------------------------------ +// Hierarchy +//------------------------------------------------------------------------------ + +/* +MACCore +└─── bus (SoCBusHandler) +│ └─── _interconnect (InterconnectShared) +│ │ └─── arbiter (Arbiter) +│ │ │ └─── rr (RoundRobin) +│ │ └─── decoder (Decoder) +│ │ └─── timeout (Timeout) +│ │ │ └─── waittimer_0* (WaitTimer) +└─── csr (SoCCSRHandler) +└─── irq (SoCIRQHandler) +└─── ctrl (SoCController) +└─── cpu (CPUNone) +└─── crg (CRG) +└─── ethphy (LiteEthPHYMII) +│ └─── crg (LiteEthPHYMIICRG) +│ │ └─── hw_reset (LiteEthPHYHWReset) +│ └─── tx (LiteEthPHYMIITX) +│ │ └─── converter (Converter) +│ │ │ └─── _downconverter_0* (_DownConverter) +│ └─── rx (LiteEthPHYMIIRX) +│ │ └─── converter_0* (Converter) +│ │ │ └─── _upconverter_0* (_UpConverter) +│ └─── mdio (LiteEthPHYMDIO) +└─── ethmac (LiteEthMAC) +│ └─── core (LiteEthMACCore) +│ │ └─── tx_datapath (TXDatapath) +│ │ │ └─── clockdomaincrossing_0* (ClockDomainCrossing) +│ │ │ │ └─── asyncfifo_0* (AsyncFIFO) +│ │ │ │ │ └─── fifo (AsyncFIFO) +│ │ │ │ │ │ └─── graycounter_0* (GrayCounter) +│ │ │ │ │ │ └─── graycounter_1* (GrayCounter) +│ │ │ └─── strideconverter_0* (StrideConverter) +│ │ │ │ └─── converter_0* (Converter) +│ │ │ │ │ └─── _downconverter_0* (_DownConverter) +│ │ │ └─── liteethmactxlastbe_0* (LiteEthMACTXLastBE) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── liteethmacpaddinginserter_0* (LiteEthMACPaddingInserter) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── liteethmaccrc32inserter_0* (LiteEthMACCRC32Inserter) +│ │ │ │ └─── crc (LiteEthMACCRC32) +│ │ │ │ │ └─── liteethmaccrcengine_0* (LiteEthMACCRCEngine) +│ │ │ │ └─── fsm (FSM) +│ │ │ │ └─── buffer_0* (Buffer) +│ │ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── liteethmacpreambleinserter_0* (LiteEthMACPreambleInserter) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── liteethmacgap_0* (LiteEthMACGap) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── pipeline_0* (Pipeline) +│ │ └─── rx_datapath (RXDatapath) +│ │ │ └─── liteethmacpreamblechecker_0* (LiteEthMACPreambleChecker) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── pulsesynchronizer_0* (PulseSynchronizer) +│ │ │ └─── liteethmaccrc32checker_0* (LiteEthMACCRC32Checker) +│ │ │ │ └─── crc (LiteEthMACCRC32) +│ │ │ │ │ └─── liteethmaccrcengine_0* (LiteEthMACCRCEngine) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ └─── fsm (FSM) +│ │ │ │ └─── buffer_0* (Buffer) +│ │ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── pulsesynchronizer_1* (PulseSynchronizer) +│ │ │ └─── liteethmacpaddingchecker_0* (LiteEthMACPaddingChecker) +│ │ │ └─── liteethmacrxlastbe_0* (LiteEthMACRXLastBE) +│ │ │ └─── strideconverter_0* (StrideConverter) +│ │ │ │ └─── converter_0* (Converter) +│ │ │ │ │ └─── _upconverter_0* (_UpConverter) +│ │ │ └─── clockdomaincrossing_0* (ClockDomainCrossing) +│ │ │ │ └─── asyncfifo_0* (AsyncFIFO) +│ │ │ │ │ └─── fifo (AsyncFIFO) +│ │ │ │ │ │ └─── graycounter_0* (GrayCounter) +│ │ │ │ │ │ └─── graycounter_1* (GrayCounter) +│ │ │ └─── pipeline_0* (Pipeline) +│ └─── interface (LiteEthMACWishboneInterface) +│ │ └─── sram (LiteEthMACSRAM) +│ │ │ └─── writer (LiteEthMACSRAMWriter) +│ │ │ │ └─── ev (EventManager) +│ │ │ │ │ └─── eventsourcelevel_0* (EventSourceLevel) +│ │ │ │ └─── stat_fifo (SyncFIFO) +│ │ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── reader (LiteEthMACSRAMReader) +│ │ │ │ └─── ev (EventManager) +│ │ │ │ │ └─── eventsourcepulse_0* (EventSourcePulse) +│ │ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── ev (SharedIRQ) +│ │ └─── sram_0* (SRAM) +│ │ └─── sram_1* (SRAM) +│ │ └─── sram_2* (SRAM) +│ │ └─── sram_3* (SRAM) +│ │ └─── decoder_0* (Decoder) +└─── csr_bridge (Wishbone2CSR) +│ └─── fsm (FSM) +└─── csr_bankarray (CSRBankArray) +│ └─── csrbank_0* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ └─── csrbank_1* (CSRBank) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstatus_1* (CSRStatus) +│ │ └─── csrstatus_2* (CSRStatus) +│ │ └─── csrstatus_3* (CSRStatus) +│ │ └─── csrstatus_4* (CSRStatus) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstatus_5* (CSRStatus) +│ │ └─── csrstatus_6* (CSRStatus) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstatus_7* (CSRStatus) +│ │ └─── csrstatus_8* (CSRStatus) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstatus_9* (CSRStatus) +│ │ └─── csrstatus_10* (CSRStatus) +│ │ └─── csrstatus_11* (CSRStatus) +│ └─── csrbank_2* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +└─── csr_interconnect (InterconnectShared) +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +* : Generated name. +[]: BlackBox. +*/ + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +wire [13:0] builder_adr; +wire [39:0] builder_complexslicelowerer_slice_proxy; +reg [19:0] builder_count = 20'd1000000; +wire [31:0] builder_csrbank0_bus_errors_r; +reg builder_csrbank0_bus_errors_re = 1'd0; +wire [31:0] builder_csrbank0_bus_errors_w; +reg builder_csrbank0_bus_errors_we = 1'd0; +wire [1:0] builder_csrbank0_reset0_r; +reg builder_csrbank0_reset0_re = 1'd0; +wire [1:0] builder_csrbank0_reset0_w; +reg builder_csrbank0_reset0_we = 1'd0; +wire [31:0] builder_csrbank0_scratch0_r; +reg builder_csrbank0_scratch0_re = 1'd0; +wire [31:0] builder_csrbank0_scratch0_w; +reg builder_csrbank0_scratch0_we = 1'd0; +wire builder_csrbank0_sel; +wire builder_csrbank1_preamble_crc_r; +reg builder_csrbank1_preamble_crc_re = 1'd0; +wire builder_csrbank1_preamble_crc_w; +reg builder_csrbank1_preamble_crc_we = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_crc_errors_r; +reg builder_csrbank1_rx_datapath_crc_errors_re = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_crc_errors_w; +reg builder_csrbank1_rx_datapath_crc_errors_we = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_r; +reg builder_csrbank1_rx_datapath_preamble_errors_re = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_w; +reg builder_csrbank1_rx_datapath_preamble_errors_we = 1'd0; +wire builder_csrbank1_sel; +wire builder_csrbank1_sram_reader_ev_enable0_r; +reg builder_csrbank1_sram_reader_ev_enable0_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_enable0_w; +reg builder_csrbank1_sram_reader_ev_enable0_we = 1'd0; +wire builder_csrbank1_sram_reader_ev_pending_r; +reg builder_csrbank1_sram_reader_ev_pending_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_pending_w; +reg builder_csrbank1_sram_reader_ev_pending_we = 1'd0; +wire builder_csrbank1_sram_reader_ev_status_r; +reg builder_csrbank1_sram_reader_ev_status_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_status_w; +reg builder_csrbank1_sram_reader_ev_status_we = 1'd0; +wire [10:0] builder_csrbank1_sram_reader_length0_r; +reg builder_csrbank1_sram_reader_length0_re = 1'd0; +wire [10:0] builder_csrbank1_sram_reader_length0_w; +reg builder_csrbank1_sram_reader_length0_we = 1'd0; +wire [1:0] builder_csrbank1_sram_reader_level_r; +reg builder_csrbank1_sram_reader_level_re = 1'd0; +wire [1:0] builder_csrbank1_sram_reader_level_w; +reg builder_csrbank1_sram_reader_level_we = 1'd0; +wire builder_csrbank1_sram_reader_ready_r; +reg builder_csrbank1_sram_reader_ready_re = 1'd0; +wire builder_csrbank1_sram_reader_ready_w; +reg builder_csrbank1_sram_reader_ready_we = 1'd0; +wire builder_csrbank1_sram_reader_slot0_r; +reg builder_csrbank1_sram_reader_slot0_re = 1'd0; +wire builder_csrbank1_sram_reader_slot0_w; +reg builder_csrbank1_sram_reader_slot0_we = 1'd0; +wire [31:0] builder_csrbank1_sram_writer_errors_r; +reg builder_csrbank1_sram_writer_errors_re = 1'd0; +wire [31:0] builder_csrbank1_sram_writer_errors_w; +reg builder_csrbank1_sram_writer_errors_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_enable0_r; +reg builder_csrbank1_sram_writer_ev_enable0_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_enable0_w; +reg builder_csrbank1_sram_writer_ev_enable0_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_pending_r; +reg builder_csrbank1_sram_writer_ev_pending_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_pending_w; +reg builder_csrbank1_sram_writer_ev_pending_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_status_r; +reg builder_csrbank1_sram_writer_ev_status_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_status_w; +reg builder_csrbank1_sram_writer_ev_status_we = 1'd0; +wire [10:0] builder_csrbank1_sram_writer_length_r; +reg builder_csrbank1_sram_writer_length_re = 1'd0; +wire [10:0] builder_csrbank1_sram_writer_length_w; +reg builder_csrbank1_sram_writer_length_we = 1'd0; +wire builder_csrbank1_sram_writer_slot_r; +reg builder_csrbank1_sram_writer_slot_re = 1'd0; +wire builder_csrbank1_sram_writer_slot_w; +reg builder_csrbank1_sram_writer_slot_we = 1'd0; +wire builder_csrbank2_crg_reset0_r; +reg builder_csrbank2_crg_reset0_re = 1'd0; +wire builder_csrbank2_crg_reset0_w; +reg builder_csrbank2_crg_reset0_we = 1'd0; +wire builder_csrbank2_mdio_r_r; +reg builder_csrbank2_mdio_r_re = 1'd0; +wire builder_csrbank2_mdio_r_w; +reg builder_csrbank2_mdio_r_we = 1'd0; +wire [2:0] builder_csrbank2_mdio_w0_r; +reg builder_csrbank2_mdio_w0_re = 1'd0; +wire [2:0] builder_csrbank2_mdio_w0_w; +reg builder_csrbank2_mdio_w0_we = 1'd0; +wire builder_csrbank2_sel; +wire [31:0] builder_dat_r; +wire [31:0] builder_dat_w; +wire builder_done; +reg builder_error = 1'd0; +wire builder_grant; +reg builder_interface0_ack = 1'd0; +wire [29:0] builder_interface0_adr; +wire [13:0] builder_interface0_bank_bus_adr; +reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface0_bank_bus_dat_w; +wire builder_interface0_bank_bus_we; +wire [1:0] builder_interface0_bte; +wire [2:0] builder_interface0_cti; +wire builder_interface0_cyc; +reg [31:0] builder_interface0_dat_r = 32'd0; +wire [31:0] builder_interface0_dat_w; +reg builder_interface0_err = 1'd0; +wire [3:0] builder_interface0_sel; +wire builder_interface0_stb; +wire builder_interface0_we; +reg [13:0] builder_interface1_adr = 14'd0; +wire [13:0] builder_interface1_bank_bus_adr; +reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface1_bank_bus_dat_w; +wire builder_interface1_bank_bus_we; +wire [31:0] builder_interface1_dat_r; +reg [31:0] builder_interface1_dat_w = 32'd0; +reg builder_interface1_we = 1'd0; +wire [13:0] builder_interface2_bank_bus_adr; +reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface2_bank_bus_dat_w; +wire builder_interface2_bank_bus_we; +reg [1:0] builder_liteethmacsramreader_next_state = 2'd0; +reg [1:0] builder_liteethmacsramreader_state = 2'd0; +reg [2:0] builder_liteethmacsramwriter_next_state = 3'd0; +reg [2:0] builder_liteethmacsramwriter_state = 3'd0; +reg builder_next_state = 1'd0; +wire builder_request; +wire builder_rst_meta0; +wire builder_rst_meta1; +reg [1:0] builder_rxdatapath_bufferizeendpoints_next_state = 2'd0; +reg [1:0] builder_rxdatapath_bufferizeendpoints_state = 2'd0; +reg builder_rxdatapath_liteethmacpreamblechecker_next_state = 1'd0; +reg builder_rxdatapath_liteethmacpreamblechecker_state = 1'd0; +reg [29:0] builder_self0 = 30'd0; +reg [31:0] builder_self1 = 32'd0; +reg [3:0] builder_self2 = 4'd0; +reg builder_self3 = 1'd0; +reg builder_self4 = 1'd0; +reg builder_self5 = 1'd0; +reg [2:0] builder_self6 = 3'd0; +reg [1:0] builder_self7 = 2'd0; +reg builder_shared_ack = 1'd0; +wire [29:0] builder_shared_adr; +wire [1:0] builder_shared_bte; +wire [2:0] builder_shared_cti; +wire builder_shared_cyc; +reg [31:0] builder_shared_dat_r = 32'd0; +wire [31:0] builder_shared_dat_w; +wire builder_shared_err; +wire [3:0] builder_shared_sel; +wire builder_shared_stb; +wire builder_shared_we; +reg [1:0] builder_slave_sel = 2'd0; +reg [1:0] builder_slave_sel_r = 2'd0; +reg builder_state = 1'd0; +wire [31:0] builder_t_slice_proxy0; +wire [31:0] builder_t_slice_proxy1; +wire [31:0] builder_t_slice_proxy10; +wire [31:0] builder_t_slice_proxy11; +wire [31:0] builder_t_slice_proxy12; +wire [31:0] builder_t_slice_proxy13; +wire [31:0] builder_t_slice_proxy14; +wire [31:0] builder_t_slice_proxy15; +wire [31:0] builder_t_slice_proxy16; +wire [31:0] builder_t_slice_proxy17; +wire [31:0] builder_t_slice_proxy18; +wire [31:0] builder_t_slice_proxy19; +wire [31:0] builder_t_slice_proxy2; +wire [31:0] builder_t_slice_proxy20; +wire [31:0] builder_t_slice_proxy21; +wire [31:0] builder_t_slice_proxy22; +wire [31:0] builder_t_slice_proxy23; +wire [31:0] builder_t_slice_proxy24; +wire [31:0] builder_t_slice_proxy25; +wire [31:0] builder_t_slice_proxy26; +wire [31:0] builder_t_slice_proxy27; +wire [31:0] builder_t_slice_proxy28; +wire [31:0] builder_t_slice_proxy29; +wire [31:0] builder_t_slice_proxy3; +wire [31:0] builder_t_slice_proxy30; +wire [31:0] builder_t_slice_proxy31; +wire [31:0] builder_t_slice_proxy32; +wire [31:0] builder_t_slice_proxy33; +wire [31:0] builder_t_slice_proxy34; +wire [31:0] builder_t_slice_proxy35; +wire [31:0] builder_t_slice_proxy36; +wire [31:0] builder_t_slice_proxy37; +wire [31:0] builder_t_slice_proxy38; +wire [31:0] builder_t_slice_proxy39; +wire [31:0] builder_t_slice_proxy4; +wire [31:0] builder_t_slice_proxy40; +wire [31:0] builder_t_slice_proxy41; +wire [31:0] builder_t_slice_proxy42; +wire [31:0] builder_t_slice_proxy43; +wire [31:0] builder_t_slice_proxy44; +wire [31:0] builder_t_slice_proxy45; +wire [31:0] builder_t_slice_proxy46; +wire [31:0] builder_t_slice_proxy47; +wire [31:0] builder_t_slice_proxy48; +wire [31:0] builder_t_slice_proxy49; +wire [31:0] builder_t_slice_proxy5; +wire [31:0] builder_t_slice_proxy50; +wire [31:0] builder_t_slice_proxy51; +wire [31:0] builder_t_slice_proxy52; +wire [31:0] builder_t_slice_proxy53; +wire [31:0] builder_t_slice_proxy54; +wire [31:0] builder_t_slice_proxy55; +wire [31:0] builder_t_slice_proxy56; +wire [31:0] builder_t_slice_proxy57; +wire [31:0] builder_t_slice_proxy58; +wire [31:0] builder_t_slice_proxy59; +wire [31:0] builder_t_slice_proxy6; +wire [31:0] builder_t_slice_proxy60; +wire [31:0] builder_t_slice_proxy61; +wire [31:0] builder_t_slice_proxy62; +wire [31:0] builder_t_slice_proxy63; +wire [31:0] builder_t_slice_proxy7; +wire [31:0] builder_t_slice_proxy8; +wire [31:0] builder_t_slice_proxy9; +reg [1:0] builder_txdatapath_bufferizeendpoints_next_state = 2'd0; +reg [1:0] builder_txdatapath_bufferizeendpoints_state = 2'd0; +reg builder_txdatapath_liteethmacgap_next_state = 1'd0; +reg builder_txdatapath_liteethmacgap_state = 1'd0; +reg builder_txdatapath_liteethmacpaddinginserter_next_state = 1'd0; +reg builder_txdatapath_liteethmacpaddinginserter_state = 1'd0; +reg [1:0] builder_txdatapath_liteethmacpreambleinserter_next_state = 2'd0; +reg [1:0] builder_txdatapath_liteethmacpreambleinserter_state = 2'd0; +reg builder_txdatapath_liteethmactxlastbe_next_state = 1'd0; +reg builder_txdatapath_liteethmactxlastbe_state = 1'd0; +wire builder_wait; +wire builder_we; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl00 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl01 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl10 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl11 = 6'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl20 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl21 = 6'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl30 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl31 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl40 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl41 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl50 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl51 = 6'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl60 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl61 = 6'd0; +(* dont_touch = "true" *) +wire eth_rx_clk; +wire eth_rx_rst; +(* dont_touch = "true" *) +wire eth_tx_clk; +wire eth_tx_rst; +wire main_bufferizeendpoints_pipe_valid_sink_first; +wire main_bufferizeendpoints_pipe_valid_sink_last; +wire [7:0] main_bufferizeendpoints_pipe_valid_sink_payload_data; +wire main_bufferizeendpoints_pipe_valid_sink_payload_error; +wire main_bufferizeendpoints_pipe_valid_sink_payload_last_be; +wire main_bufferizeendpoints_pipe_valid_sink_ready; +wire main_bufferizeendpoints_pipe_valid_sink_valid; +reg main_bufferizeendpoints_pipe_valid_source_first = 1'd0; +reg main_bufferizeendpoints_pipe_valid_source_last = 1'd0; +reg [7:0] main_bufferizeendpoints_pipe_valid_source_payload_data = 8'd0; +reg main_bufferizeendpoints_pipe_valid_source_payload_error = 1'd0; +reg main_bufferizeendpoints_pipe_valid_source_payload_last_be = 1'd0; +wire main_bufferizeendpoints_pipe_valid_source_ready; +reg main_bufferizeendpoints_pipe_valid_source_valid = 1'd0; +wire main_bufferizeendpoints_sink_sink_first; +wire main_bufferizeendpoints_sink_sink_last; +wire [7:0] main_bufferizeendpoints_sink_sink_payload_data; +wire main_bufferizeendpoints_sink_sink_payload_error; +wire main_bufferizeendpoints_sink_sink_payload_last_be; +wire main_bufferizeendpoints_sink_sink_ready; +wire main_bufferizeendpoints_sink_sink_valid; +wire main_bufferizeendpoints_source_source_first; +wire main_bufferizeendpoints_source_source_last; +wire [7:0] main_bufferizeendpoints_source_source_payload_data; +wire main_bufferizeendpoints_source_source_payload_error; +wire main_bufferizeendpoints_source_source_payload_last_be; +wire main_bufferizeendpoints_source_source_ready; +wire main_bufferizeendpoints_source_source_valid; +wire main_bus_ack; +wire [29:0] main_bus_adr; +wire [1:0] main_bus_bte; +wire [2:0] main_bus_cti; +wire main_bus_cyc; +wire [31:0] main_bus_dat_r; +wire [31:0] main_bus_dat_w; +wire main_bus_err; +wire [3:0] main_bus_sel; +wire main_bus_stb; +wire main_bus_we; +reg main_crc_errors_re = 1'd0; +reg [31:0] main_crc_errors_status = 32'd0; +wire main_crc_errors_we; +reg main_interface0_ack = 1'd0; +wire [29:0] main_interface0_adr; +wire [1:0] main_interface0_bte; +wire [2:0] main_interface0_cti; +wire main_interface0_cyc; +wire [31:0] main_interface0_dat_r; +wire [31:0] main_interface0_dat_w; +reg main_interface0_err = 1'd0; +wire [3:0] main_interface0_sel; +wire main_interface0_stb; +wire main_interface0_we; +reg main_interface1_ack = 1'd0; +wire [29:0] main_interface1_adr; +wire [1:0] main_interface1_bte; +wire [2:0] main_interface1_cti; +wire main_interface1_cyc; +wire [31:0] main_interface1_dat_r; +wire [31:0] main_interface1_dat_w; +reg main_interface1_err = 1'd0; +wire [3:0] main_interface1_sel; +wire main_interface1_stb; +wire main_interface1_we; +reg main_interface2_ack = 1'd0; +wire [29:0] main_interface2_adr; +wire [1:0] main_interface2_bte; +wire [2:0] main_interface2_cti; +wire main_interface2_cyc; +wire [31:0] main_interface2_dat_r; +wire [31:0] main_interface2_dat_w; +reg main_interface2_err = 1'd0; +wire [3:0] main_interface2_sel; +wire main_interface2_stb; +wire main_interface2_we; +reg main_interface3_ack = 1'd0; +wire [29:0] main_interface3_adr; +wire [1:0] main_interface3_bte; +wire [2:0] main_interface3_cti; +wire main_interface3_cyc; +wire [31:0] main_interface3_dat_r; +wire [31:0] main_interface3_dat_w; +reg main_interface3_err = 1'd0; +wire [3:0] main_interface3_sel; +wire main_interface3_stb; +wire main_interface3_we; +reg [3:0] main_length_inc = 4'd0; +wire main_liteethmaccrc32checker_crc_be; +reg main_liteethmaccrc32checker_crc_ce = 1'd0; +reg [31:0] main_liteethmaccrc32checker_crc_crc_next = 32'd0; +wire [31:0] main_liteethmaccrc32checker_crc_crc_prev; +wire [7:0] main_liteethmaccrc32checker_crc_data0; +wire [7:0] main_liteethmaccrc32checker_crc_data1; +reg main_liteethmaccrc32checker_crc_error0 = 1'd0; +reg main_liteethmaccrc32checker_crc_error1 = 1'd0; +reg main_liteethmaccrc32checker_crc_error1_next_value1 = 1'd0; +reg main_liteethmaccrc32checker_crc_error1_next_value_ce1 = 1'd0; +reg [31:0] main_liteethmaccrc32checker_crc_reg = 32'd4294967295; +reg main_liteethmaccrc32checker_crc_reset = 1'd0; +reg [31:0] main_liteethmaccrc32checker_crc_value = 32'd0; +reg main_liteethmaccrc32checker_error = 1'd0; +wire main_liteethmaccrc32checker_fifo_full; +wire main_liteethmaccrc32checker_fifo_in; +wire main_liteethmaccrc32checker_fifo_out; +reg main_liteethmaccrc32checker_fifo_reset = 1'd0; +reg main_liteethmaccrc32checker_last_be = 1'd0; +reg main_liteethmaccrc32checker_last_be_next_value0 = 1'd0; +reg main_liteethmaccrc32checker_last_be_next_value_ce0 = 1'd0; +wire main_liteethmaccrc32checker_sink_sink_first; +wire main_liteethmaccrc32checker_sink_sink_last; +wire [7:0] main_liteethmaccrc32checker_sink_sink_payload_data; +wire main_liteethmaccrc32checker_sink_sink_payload_error; +wire main_liteethmaccrc32checker_sink_sink_payload_last_be; +reg main_liteethmaccrc32checker_sink_sink_ready = 1'd0; +wire main_liteethmaccrc32checker_sink_sink_valid; +wire main_liteethmaccrc32checker_source_source_first; +reg main_liteethmaccrc32checker_source_source_last = 1'd0; +wire [7:0] main_liteethmaccrc32checker_source_source_payload_data; +reg main_liteethmaccrc32checker_source_source_payload_error = 1'd0; +reg main_liteethmaccrc32checker_source_source_payload_last_be = 1'd0; +wire main_liteethmaccrc32checker_source_source_ready; +reg main_liteethmaccrc32checker_source_source_valid = 1'd0; +reg [2:0] main_liteethmaccrc32checker_syncfifo_consume = 3'd0; +wire main_liteethmaccrc32checker_syncfifo_do_read; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_first; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_first; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; +reg [2:0] main_liteethmaccrc32checker_syncfifo_level = 3'd0; +reg [2:0] main_liteethmaccrc32checker_syncfifo_produce = 3'd0; +wire [2:0] main_liteethmaccrc32checker_syncfifo_rdport_adr; +wire [11:0] main_liteethmaccrc32checker_syncfifo_rdport_dat_r; +reg main_liteethmaccrc32checker_syncfifo_replace = 1'd0; +wire main_liteethmaccrc32checker_syncfifo_sink_first; +wire main_liteethmaccrc32checker_syncfifo_sink_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_sink_payload_data; +wire main_liteethmaccrc32checker_syncfifo_sink_payload_error; +wire main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; +wire main_liteethmaccrc32checker_syncfifo_sink_ready; +reg main_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; +wire main_liteethmaccrc32checker_syncfifo_source_first; +wire main_liteethmaccrc32checker_syncfifo_source_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_source_payload_data; +wire main_liteethmaccrc32checker_syncfifo_source_payload_error; +wire main_liteethmaccrc32checker_syncfifo_source_payload_last_be; +reg main_liteethmaccrc32checker_syncfifo_source_ready = 1'd0; +wire main_liteethmaccrc32checker_syncfifo_source_valid; +wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_din; +wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_dout; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_re; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_readable; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_we; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_writable; +reg [2:0] main_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; +wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_r; +wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_w; +wire main_liteethmaccrc32checker_syncfifo_wrport_we; +reg main_maccore__r_re = 1'd0; +reg main_maccore__r_status = 1'd0; +wire main_maccore__r_we; +reg main_maccore__w_re = 1'd0; +reg [2:0] main_maccore__w_storage = 3'd0; +wire main_maccore_bus_error; +reg [31:0] main_maccore_bus_errors = 32'd0; +reg main_maccore_bus_errors_re = 1'd0; +wire [31:0] main_maccore_bus_errors_status; +wire main_maccore_bus_errors_we; +wire main_maccore_cpu_rst; +reg [8:0] main_maccore_crg_counter = 9'd0; +wire main_maccore_crg_counter_ce; +wire main_maccore_crg_counter_done; +wire main_maccore_crg_reset0; +wire main_maccore_crg_reset1; +reg main_maccore_crg_reset_re = 1'd0; +reg main_maccore_crg_reset_storage = 1'd0; +wire main_maccore_data_oe; +wire main_maccore_data_r; +wire main_maccore_data_w; +reg main_maccore_int_rst = 1'd1; +reg main_maccore_liteethphymiirx_converter_demux = 1'd0; +wire main_maccore_liteethphymiirx_converter_load_part; +reg main_maccore_liteethphymiirx_converter_sink_first = 1'd0; +wire main_maccore_liteethphymiirx_converter_sink_last; +reg [3:0] main_maccore_liteethphymiirx_converter_sink_payload_data = 4'd0; +wire main_maccore_liteethphymiirx_converter_sink_ready; +reg main_maccore_liteethphymiirx_converter_sink_valid = 1'd0; +reg main_maccore_liteethphymiirx_converter_source_first = 1'd0; +reg main_maccore_liteethphymiirx_converter_source_last = 1'd0; +reg [7:0] main_maccore_liteethphymiirx_converter_source_payload_data = 8'd0; +reg [1:0] main_maccore_liteethphymiirx_converter_source_payload_valid_token_count = 2'd0; +wire main_maccore_liteethphymiirx_converter_source_ready; +wire main_maccore_liteethphymiirx_converter_source_valid; +reg main_maccore_liteethphymiirx_converter_strobe_all = 1'd0; +reg main_maccore_liteethphymiirx_reset = 1'd0; +wire main_maccore_liteethphymiirx_source_first; +wire main_maccore_liteethphymiirx_source_last; +wire [7:0] main_maccore_liteethphymiirx_source_payload_data; +reg main_maccore_liteethphymiirx_source_payload_error = 1'd0; +reg main_maccore_liteethphymiirx_source_payload_last_be = 1'd0; +wire main_maccore_liteethphymiirx_source_ready; +wire main_maccore_liteethphymiirx_source_source_first; +wire main_maccore_liteethphymiirx_source_source_last; +wire [7:0] main_maccore_liteethphymiirx_source_source_payload_data; +wire main_maccore_liteethphymiirx_source_source_ready; +wire main_maccore_liteethphymiirx_source_source_valid; +wire main_maccore_liteethphymiirx_source_valid; +wire main_maccore_liteethphymiitx_converter_first; +wire main_maccore_liteethphymiitx_converter_last; +reg main_maccore_liteethphymiitx_converter_mux = 1'd0; +reg main_maccore_liteethphymiitx_converter_sink_first = 1'd0; +reg main_maccore_liteethphymiitx_converter_sink_last = 1'd0; +wire [7:0] main_maccore_liteethphymiitx_converter_sink_payload_data; +wire main_maccore_liteethphymiitx_converter_sink_ready; +wire main_maccore_liteethphymiitx_converter_sink_valid; +wire main_maccore_liteethphymiitx_converter_source_first; +wire main_maccore_liteethphymiitx_converter_source_last; +reg [3:0] main_maccore_liteethphymiitx_converter_source_payload_data = 4'd0; +wire main_maccore_liteethphymiitx_converter_source_payload_valid_token_count; +wire main_maccore_liteethphymiitx_converter_source_ready; +wire main_maccore_liteethphymiitx_converter_source_valid; +wire main_maccore_liteethphymiitx_sink_first; +wire main_maccore_liteethphymiitx_sink_last; +wire [7:0] main_maccore_liteethphymiitx_sink_payload_data; +wire main_maccore_liteethphymiitx_sink_payload_error; +wire main_maccore_liteethphymiitx_sink_payload_last_be; +wire main_maccore_liteethphymiitx_sink_ready; +wire main_maccore_liteethphymiitx_sink_valid; +wire main_maccore_liteethphymiitx_source_source_first; +wire main_maccore_liteethphymiitx_source_source_last; +wire [3:0] main_maccore_liteethphymiitx_source_source_payload_data; +wire main_maccore_liteethphymiitx_source_source_ready; +wire main_maccore_liteethphymiitx_source_source_valid; +wire main_maccore_mdc; +wire main_maccore_oe; +reg main_maccore_r = 1'd0; +reg main_maccore_reset_re = 1'd0; +reg [1:0] main_maccore_reset_storage = 2'd0; +reg main_maccore_scratch_re = 1'd0; +reg [31:0] main_maccore_scratch_storage = 32'd305419896; +reg main_maccore_soc_rst = 1'd0; +wire main_maccore_w; +reg main_preamble_errors_re = 1'd0; +reg [31:0] main_preamble_errors_status = 32'd0; +wire main_preamble_errors_we; +wire main_pulsesynchronizer0_i; +wire main_pulsesynchronizer0_o; +reg main_pulsesynchronizer0_toggle_i = 1'd0; +wire main_pulsesynchronizer0_toggle_o; +reg main_pulsesynchronizer0_toggle_o_r = 1'd0; +wire main_pulsesynchronizer1_i; +wire main_pulsesynchronizer1_o; +reg main_pulsesynchronizer1_toggle_i = 1'd0; +wire main_pulsesynchronizer1_toggle_o; +reg main_pulsesynchronizer1_toggle_o_r = 1'd0; +reg [31:0] main_rd_data = 32'd0; +reg main_re = 1'd0; +reg main_read = 1'd0; +wire [41:0] main_rx_cdc_cdc_asyncfifo_din; +wire [41:0] main_rx_cdc_cdc_asyncfifo_dout; +wire main_rx_cdc_cdc_asyncfifo_re; +wire main_rx_cdc_cdc_asyncfifo_readable; +wire main_rx_cdc_cdc_asyncfifo_we; +wire main_rx_cdc_cdc_asyncfifo_writable; +wire [5:0] main_rx_cdc_cdc_consume_wdomain; +wire main_rx_cdc_cdc_fifo_in_first; +wire main_rx_cdc_cdc_fifo_in_last; +wire [31:0] main_rx_cdc_cdc_fifo_in_payload_data; +wire [3:0] main_rx_cdc_cdc_fifo_in_payload_error; +wire [3:0] main_rx_cdc_cdc_fifo_in_payload_last_be; +wire main_rx_cdc_cdc_fifo_out_first; +wire main_rx_cdc_cdc_fifo_out_last; +wire [31:0] main_rx_cdc_cdc_fifo_out_payload_data; +wire [3:0] main_rx_cdc_cdc_fifo_out_payload_error; +wire [3:0] main_rx_cdc_cdc_fifo_out_payload_last_be; +wire main_rx_cdc_cdc_graycounter0_ce; +(* dont_touch = "true" *) +reg [5:0] main_rx_cdc_cdc_graycounter0_q = 6'd0; +reg [5:0] main_rx_cdc_cdc_graycounter0_q_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_graycounter0_q_next; +reg [5:0] main_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire main_rx_cdc_cdc_graycounter1_ce; +(* dont_touch = "true" *) +reg [5:0] main_rx_cdc_cdc_graycounter1_q = 6'd0; +reg [5:0] main_rx_cdc_cdc_graycounter1_q_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_graycounter1_q_next; +reg [5:0] main_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_produce_rdomain; +wire [4:0] main_rx_cdc_cdc_rdport_adr; +wire [41:0] main_rx_cdc_cdc_rdport_dat_r; +wire main_rx_cdc_cdc_sink_first; +wire main_rx_cdc_cdc_sink_last; +wire [31:0] main_rx_cdc_cdc_sink_payload_data; +wire [3:0] main_rx_cdc_cdc_sink_payload_error; +wire [3:0] main_rx_cdc_cdc_sink_payload_last_be; +wire main_rx_cdc_cdc_sink_ready; +wire main_rx_cdc_cdc_sink_valid; +wire main_rx_cdc_cdc_source_first; +wire main_rx_cdc_cdc_source_last; +wire [31:0] main_rx_cdc_cdc_source_payload_data; +wire [3:0] main_rx_cdc_cdc_source_payload_error; +wire [3:0] main_rx_cdc_cdc_source_payload_last_be; +wire main_rx_cdc_cdc_source_ready; +wire main_rx_cdc_cdc_source_valid; +wire [4:0] main_rx_cdc_cdc_wrport_adr; +wire [41:0] main_rx_cdc_cdc_wrport_dat_r; +wire [41:0] main_rx_cdc_cdc_wrport_dat_w; +wire main_rx_cdc_cdc_wrport_we; +wire main_rx_cdc_sink_sink_first; +wire main_rx_cdc_sink_sink_last; +wire [31:0] main_rx_cdc_sink_sink_payload_data; +wire [3:0] main_rx_cdc_sink_sink_payload_error; +wire [3:0] main_rx_cdc_sink_sink_payload_last_be; +wire main_rx_cdc_sink_sink_ready; +wire main_rx_cdc_sink_sink_valid; +wire main_rx_cdc_source_source_first; +wire main_rx_cdc_source_source_last; +wire [31:0] main_rx_cdc_source_source_payload_data; +wire [3:0] main_rx_cdc_source_source_payload_error; +wire [3:0] main_rx_cdc_source_source_payload_last_be; +wire main_rx_cdc_source_source_ready; +wire main_rx_cdc_source_source_valid; +reg [1:0] main_rx_converter_converter_demux = 2'd0; +wire main_rx_converter_converter_load_part; +wire main_rx_converter_converter_sink_first; +wire main_rx_converter_converter_sink_last; +wire [9:0] main_rx_converter_converter_sink_payload_data; +wire main_rx_converter_converter_sink_ready; +wire main_rx_converter_converter_sink_valid; +reg main_rx_converter_converter_source_first = 1'd0; +reg main_rx_converter_converter_source_last = 1'd0; +reg [39:0] main_rx_converter_converter_source_payload_data = 40'd0; +reg [2:0] main_rx_converter_converter_source_payload_valid_token_count = 3'd0; +wire main_rx_converter_converter_source_ready; +wire main_rx_converter_converter_source_valid; +reg main_rx_converter_converter_strobe_all = 1'd0; +wire main_rx_converter_sink_first; +wire main_rx_converter_sink_last; +wire [7:0] main_rx_converter_sink_payload_data; +wire main_rx_converter_sink_payload_error; +wire main_rx_converter_sink_payload_last_be; +wire main_rx_converter_sink_ready; +wire main_rx_converter_sink_valid; +wire main_rx_converter_source_first; +wire main_rx_converter_source_last; +reg [31:0] main_rx_converter_source_payload_data = 32'd0; +reg [3:0] main_rx_converter_source_payload_error = 4'd0; +reg [3:0] main_rx_converter_source_payload_last_be = 4'd0; +wire main_rx_converter_source_ready; +wire main_rx_converter_source_source_first; +wire main_rx_converter_source_source_last; +wire [39:0] main_rx_converter_source_source_payload_data; +wire main_rx_converter_source_source_ready; +wire main_rx_converter_source_source_valid; +wire main_rx_converter_source_valid; +wire main_rx_last_be_sink_first; +wire main_rx_last_be_sink_last; +wire [7:0] main_rx_last_be_sink_payload_data; +wire main_rx_last_be_sink_payload_error; +wire main_rx_last_be_sink_payload_last_be; +wire main_rx_last_be_sink_ready; +wire main_rx_last_be_sink_valid; +wire main_rx_last_be_source_first; +wire main_rx_last_be_source_last; +wire [7:0] main_rx_last_be_source_payload_data; +wire main_rx_last_be_source_payload_error; +reg main_rx_last_be_source_payload_last_be = 1'd0; +wire main_rx_last_be_source_ready; +wire main_rx_last_be_source_valid; +wire main_rx_padding_sink_first; +wire main_rx_padding_sink_last; +wire [7:0] main_rx_padding_sink_payload_data; +wire main_rx_padding_sink_payload_error; +wire main_rx_padding_sink_payload_last_be; +wire main_rx_padding_sink_ready; +wire main_rx_padding_sink_valid; +wire main_rx_padding_source_first; +wire main_rx_padding_source_last; +wire [7:0] main_rx_padding_source_payload_data; +wire main_rx_padding_source_payload_error; +wire main_rx_padding_source_payload_last_be; +wire main_rx_padding_source_ready; +wire main_rx_padding_source_valid; +reg main_rx_preamble_error = 1'd0; +reg [63:0] main_rx_preamble_preamble = 64'd15372286728091293013; +wire main_rx_preamble_sink_first; +wire main_rx_preamble_sink_last; +wire [7:0] main_rx_preamble_sink_payload_data; +wire main_rx_preamble_sink_payload_error; +wire main_rx_preamble_sink_payload_last_be; +reg main_rx_preamble_sink_ready = 1'd0; +wire main_rx_preamble_sink_valid; +reg main_rx_preamble_source_first = 1'd0; +reg main_rx_preamble_source_last = 1'd0; +wire [7:0] main_rx_preamble_source_payload_data; +reg main_rx_preamble_source_payload_error = 1'd0; +wire main_rx_preamble_source_payload_last_be; +wire main_rx_preamble_source_ready; +reg main_rx_preamble_source_valid = 1'd0; +wire main_sink_first; +wire main_sink_last; +wire [31:0] main_sink_payload_data; +wire [3:0] main_sink_payload_error; +wire [3:0] main_sink_payload_last_be; +wire main_sink_ready; +wire main_sink_sink_first; +wire main_sink_sink_last; +wire [31:0] main_sink_sink_payload_data; +wire [3:0] main_sink_sink_payload_error; +wire [3:0] main_sink_sink_payload_last_be; +wire main_sink_sink_ready; +wire main_sink_sink_valid; +wire main_sink_valid; +reg [3:0] main_slave_sel = 4'd0; +reg [3:0] main_slave_sel_r = 4'd0; +reg main_slot = 1'd0; +reg main_slot_liteethmacsramwriter_next_value = 1'd0; +reg main_slot_liteethmacsramwriter_next_value_ce = 1'd0; +wire main_source_first; +wire main_source_last; +wire [31:0] main_source_payload_data; +wire [3:0] main_source_payload_error; +wire [3:0] main_source_payload_last_be; +wire main_source_ready; +wire main_source_source_first; +wire main_source_source_last; +wire [31:0] main_source_source_payload_data; +wire [3:0] main_source_source_payload_error; +wire [3:0] main_source_source_payload_last_be; +wire main_source_source_ready; +wire main_source_source_valid; +wire main_source_valid; +wire [8:0] main_sram0_adr; +reg main_sram0_adr_burst = 1'd0; +wire [31:0] main_sram0_dat_r; +wire main_sram0_sink_valid; +reg main_sram100_storage = 1'd0; +reg main_sram101_re = 1'd0; +reg [10:0] main_sram102_storage = 11'd0; +reg main_sram103_re = 1'd0; +wire main_sram104_irq; +wire main_sram105_status; +reg main_sram106_pending = 1'd0; +reg main_sram107_trigger = 1'd0; +reg main_sram108_clear = 1'd0; +wire main_sram109_event0; +wire [10:0] main_sram10_status; +reg main_sram110_status = 1'd0; +wire main_sram111_we; +reg main_sram112_re = 1'd0; +wire main_sram113_event0; +reg main_sram114_status = 1'd0; +wire main_sram115_we; +reg main_sram116_re = 1'd0; +reg main_sram117_r = 1'd0; +wire main_sram118_event0; +reg main_sram119_storage = 1'd0; +wire main_sram11_we; +reg main_sram120_re = 1'd0; +reg [10:0] main_sram122_length = 11'd0; +reg [10:0] main_sram122_length_liteethmacsramreader_next_value = 11'd0; +reg main_sram122_length_liteethmacsramreader_next_value_ce = 1'd0; +wire main_sram123_sink_valid; +wire main_sram124_sink_ready; +reg main_sram125_sink_first = 1'd0; +reg main_sram126_sink_last = 1'd0; +wire main_sram127_sink_payload_slot; +wire [10:0] main_sram128_sink_payload_length; +wire main_sram129_source_valid; +reg main_sram12_re = 1'd0; +reg main_sram130_source_ready = 1'd0; +wire main_sram131_source_first; +wire main_sram132_source_last; +wire main_sram133_source_payload_slot; +wire [10:0] main_sram134_source_payload_length; +wire main_sram135_we; +wire main_sram136_writable; +wire main_sram137_re; +wire main_sram138_readable; +wire [13:0] main_sram139_din; +reg [31:0] main_sram13_status = 32'd0; +reg [31:0] main_sram13_status_liteethmacsramwriter_f_next_value = 32'd0; +reg main_sram13_status_liteethmacsramwriter_f_next_value_ce = 1'd0; +wire [13:0] main_sram140_dout; +reg [1:0] main_sram141_level = 2'd0; +reg main_sram142_replace = 1'd0; +reg main_sram143_produce = 1'd0; +reg main_sram144_consume = 1'd0; +reg main_sram145_adr = 1'd0; +wire [13:0] main_sram146_dat_r; +wire main_sram147_we; +wire [13:0] main_sram148_dat_w; +wire main_sram149_do_read; +wire main_sram14_we; +wire main_sram150_adr; +wire [13:0] main_sram151_dat_r; +wire main_sram152_fifo_in_payload_slot; +wire [10:0] main_sram153_fifo_in_payload_length; +wire main_sram154_fifo_in_first; +wire main_sram155_fifo_in_last; +wire main_sram156_fifo_out_payload_slot; +wire [10:0] main_sram157_fifo_out_payload_length; +wire main_sram158_fifo_out_first; +wire main_sram159_fifo_out_last; +reg main_sram15_re = 1'd0; +wire [8:0] main_sram161_adr; +wire [31:0] main_sram162_dat_r; +wire main_sram163_re; +wire [8:0] main_sram164_adr; +wire [31:0] main_sram165_dat_r; +wire main_sram166_re; +wire main_sram167_irq; +wire main_sram16_irq; +wire main_sram17_status; +wire main_sram18_pending; +wire main_sram19_trigger; +wire [8:0] main_sram1_adr; +reg main_sram1_adr_burst = 1'd0; +wire [31:0] main_sram1_dat_r; +reg main_sram1_sink_ready = 1'd1; +reg main_sram20_clear = 1'd0; +wire main_sram21_available; +reg main_sram22_status = 1'd0; +wire main_sram23_we; +reg main_sram24_re = 1'd0; +wire main_sram25_available; +reg main_sram26_status = 1'd0; +wire main_sram27_we; +reg main_sram28_re = 1'd0; +reg main_sram29_r = 1'd0; +wire [8:0] main_sram2_adr; +reg main_sram2_adr_burst = 1'd0; +wire [31:0] main_sram2_dat_r; +wire [31:0] main_sram2_dat_w; +wire main_sram2_sink_first; +reg [3:0] main_sram2_we = 4'd0; +wire main_sram30_available; +reg main_sram31_storage = 1'd0; +reg main_sram32_re = 1'd0; +reg [10:0] main_sram35_length = 11'd0; +reg [10:0] main_sram35_length_liteethmacsramwriter_t_next_value = 11'd0; +reg main_sram35_length_liteethmacsramwriter_t_next_value_ce = 1'd0; +reg main_sram37_sink_valid = 1'd0; +wire main_sram38_sink_ready; +reg main_sram39_sink_first = 1'd0; +wire [8:0] main_sram3_adr; +reg main_sram3_adr_burst = 1'd0; +wire [31:0] main_sram3_dat_r; +wire [31:0] main_sram3_dat_w; +wire main_sram3_sink_last; +reg [3:0] main_sram3_we = 4'd0; +reg main_sram40_sink_last = 1'd0; +reg main_sram41_sink_payload_slot = 1'd0; +reg [10:0] main_sram42_sink_payload_length = 11'd0; +wire main_sram43_source_valid; +wire main_sram44_source_ready; +wire main_sram45_source_first; +wire main_sram46_source_last; +wire main_sram47_source_payload_slot; +wire [10:0] main_sram48_source_payload_length; +wire main_sram49_we; +wire [31:0] main_sram4_sink_payload_data; +wire main_sram50_writable; +wire main_sram51_re; +wire main_sram52_readable; +wire [13:0] main_sram53_din; +wire [13:0] main_sram54_dout; +reg [1:0] main_sram55_level = 2'd0; +reg main_sram56_replace = 1'd0; +reg main_sram57_produce = 1'd0; +reg main_sram58_consume = 1'd0; +reg main_sram59_adr = 1'd0; +wire [3:0] main_sram5_sink_payload_last_be; +wire [13:0] main_sram60_dat_r; +wire main_sram61_we; +wire [13:0] main_sram62_dat_w; +wire main_sram63_do_read; +wire main_sram64_adr; +wire [13:0] main_sram65_dat_r; +wire main_sram66_fifo_in_payload_slot; +wire [10:0] main_sram67_fifo_in_payload_length; +wire main_sram68_fifo_in_first; +wire main_sram69_fifo_in_last; +wire [3:0] main_sram6_sink_payload_error; +wire main_sram70_fifo_out_payload_slot; +wire [10:0] main_sram71_fifo_out_payload_length; +wire main_sram72_fifo_out_first; +wire main_sram73_fifo_out_last; +reg [8:0] main_sram75_adr = 9'd0; +wire [31:0] main_sram76_dat_r; +reg main_sram77_we = 1'd0; +reg [31:0] main_sram78_dat_w = 32'd0; +reg [8:0] main_sram79_adr = 9'd0; +wire main_sram7_status; +wire [31:0] main_sram80_dat_r; +reg main_sram81_we = 1'd0; +reg [31:0] main_sram82_dat_w = 32'd0; +reg main_sram83_source_valid = 1'd0; +wire main_sram84_source_ready; +reg main_sram85_source_first = 1'd0; +reg main_sram86_source_last = 1'd0; +wire [31:0] main_sram87_source_payload_data; +reg [3:0] main_sram88_source_payload_last_be = 4'd0; +reg [3:0] main_sram89_source_payload_error = 4'd0; +wire main_sram8_we; +wire main_sram94_status; +wire main_sram95_we; +reg main_sram96_re = 1'd0; +wire [1:0] main_sram97_status; +wire main_sram98_we; +reg main_sram99_re = 1'd0; +reg main_sram9_re = 1'd0; +wire main_start_r; +reg main_start_re = 1'd0; +reg main_start_w = 1'd0; +reg main_start_we = 1'd0; +reg main_status = 1'd1; +wire [41:0] main_tx_cdc_cdc_asyncfifo_din; +wire [41:0] main_tx_cdc_cdc_asyncfifo_dout; +wire main_tx_cdc_cdc_asyncfifo_re; +wire main_tx_cdc_cdc_asyncfifo_readable; +wire main_tx_cdc_cdc_asyncfifo_we; +wire main_tx_cdc_cdc_asyncfifo_writable; +wire [5:0] main_tx_cdc_cdc_consume_wdomain; +wire main_tx_cdc_cdc_fifo_in_first; +wire main_tx_cdc_cdc_fifo_in_last; +wire [31:0] main_tx_cdc_cdc_fifo_in_payload_data; +wire [3:0] main_tx_cdc_cdc_fifo_in_payload_error; +wire [3:0] main_tx_cdc_cdc_fifo_in_payload_last_be; +wire main_tx_cdc_cdc_fifo_out_first; +wire main_tx_cdc_cdc_fifo_out_last; +wire [31:0] main_tx_cdc_cdc_fifo_out_payload_data; +wire [3:0] main_tx_cdc_cdc_fifo_out_payload_error; +wire [3:0] main_tx_cdc_cdc_fifo_out_payload_last_be; +wire main_tx_cdc_cdc_graycounter0_ce; +(* dont_touch = "true" *) +reg [5:0] main_tx_cdc_cdc_graycounter0_q = 6'd0; +reg [5:0] main_tx_cdc_cdc_graycounter0_q_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_graycounter0_q_next; +reg [5:0] main_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire main_tx_cdc_cdc_graycounter1_ce; +(* dont_touch = "true" *) +reg [5:0] main_tx_cdc_cdc_graycounter1_q = 6'd0; +reg [5:0] main_tx_cdc_cdc_graycounter1_q_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_graycounter1_q_next; +reg [5:0] main_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_produce_rdomain; +wire [4:0] main_tx_cdc_cdc_rdport_adr; +wire [41:0] main_tx_cdc_cdc_rdport_dat_r; +wire main_tx_cdc_cdc_sink_first; +wire main_tx_cdc_cdc_sink_last; +wire [31:0] main_tx_cdc_cdc_sink_payload_data; +wire [3:0] main_tx_cdc_cdc_sink_payload_error; +wire [3:0] main_tx_cdc_cdc_sink_payload_last_be; +wire main_tx_cdc_cdc_sink_ready; +wire main_tx_cdc_cdc_sink_valid; +wire main_tx_cdc_cdc_source_first; +wire main_tx_cdc_cdc_source_last; +wire [31:0] main_tx_cdc_cdc_source_payload_data; +wire [3:0] main_tx_cdc_cdc_source_payload_error; +wire [3:0] main_tx_cdc_cdc_source_payload_last_be; +wire main_tx_cdc_cdc_source_ready; +wire main_tx_cdc_cdc_source_valid; +wire [4:0] main_tx_cdc_cdc_wrport_adr; +wire [41:0] main_tx_cdc_cdc_wrport_dat_r; +wire [41:0] main_tx_cdc_cdc_wrport_dat_w; +wire main_tx_cdc_cdc_wrport_we; +wire main_tx_cdc_sink_sink_first; +wire main_tx_cdc_sink_sink_last; +wire [31:0] main_tx_cdc_sink_sink_payload_data; +wire [3:0] main_tx_cdc_sink_sink_payload_error; +wire [3:0] main_tx_cdc_sink_sink_payload_last_be; +wire main_tx_cdc_sink_sink_ready; +wire main_tx_cdc_sink_sink_valid; +wire main_tx_cdc_source_source_first; +wire main_tx_cdc_source_source_last; +wire [31:0] main_tx_cdc_source_source_payload_data; +wire [3:0] main_tx_cdc_source_source_payload_error; +wire [3:0] main_tx_cdc_source_source_payload_last_be; +wire main_tx_cdc_source_source_ready; +wire main_tx_cdc_source_source_valid; +wire main_tx_converter_converter_first; +wire main_tx_converter_converter_last; +reg [1:0] main_tx_converter_converter_mux = 2'd0; +wire main_tx_converter_converter_sink_first; +wire main_tx_converter_converter_sink_last; +reg [39:0] main_tx_converter_converter_sink_payload_data = 40'd0; +wire main_tx_converter_converter_sink_ready; +wire main_tx_converter_converter_sink_valid; +wire main_tx_converter_converter_source_first; +wire main_tx_converter_converter_source_last; +reg [9:0] main_tx_converter_converter_source_payload_data = 10'd0; +wire main_tx_converter_converter_source_payload_valid_token_count; +wire main_tx_converter_converter_source_ready; +wire main_tx_converter_converter_source_valid; +wire main_tx_converter_sink_first; +wire main_tx_converter_sink_last; +wire [31:0] main_tx_converter_sink_payload_data; +wire [3:0] main_tx_converter_sink_payload_error; +wire [3:0] main_tx_converter_sink_payload_last_be; +wire main_tx_converter_sink_ready; +wire main_tx_converter_sink_valid; +wire main_tx_converter_source_first; +wire main_tx_converter_source_last; +wire [7:0] main_tx_converter_source_payload_data; +wire main_tx_converter_source_payload_error; +wire main_tx_converter_source_payload_last_be; +wire main_tx_converter_source_ready; +wire main_tx_converter_source_source_first; +wire main_tx_converter_source_source_last; +wire [9:0] main_tx_converter_source_source_payload_data; +wire main_tx_converter_source_source_ready; +wire main_tx_converter_source_source_valid; +wire main_tx_converter_source_valid; +wire main_tx_crc_be; +reg main_tx_crc_ce = 1'd0; +reg [1:0] main_tx_crc_cnt = 2'd3; +wire main_tx_crc_cnt_done; +reg [31:0] main_tx_crc_crc_next = 32'd0; +reg [31:0] main_tx_crc_crc_packet = 32'd0; +reg [31:0] main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 = 32'd0; +reg main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 = 1'd0; +wire [31:0] main_tx_crc_crc_prev; +wire [7:0] main_tx_crc_data0; +wire [7:0] main_tx_crc_data1; +reg main_tx_crc_error = 1'd0; +reg main_tx_crc_is_ongoing0 = 1'd0; +reg main_tx_crc_is_ongoing1 = 1'd0; +reg main_tx_crc_last_be = 1'd0; +reg main_tx_crc_last_be_clockdomainsrenamer1_next_value1 = 1'd0; +reg main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 = 1'd0; +wire main_tx_crc_pipe_valid_sink_first; +wire main_tx_crc_pipe_valid_sink_last; +wire [7:0] main_tx_crc_pipe_valid_sink_payload_data; +wire main_tx_crc_pipe_valid_sink_payload_error; +wire main_tx_crc_pipe_valid_sink_payload_last_be; +wire main_tx_crc_pipe_valid_sink_ready; +wire main_tx_crc_pipe_valid_sink_valid; +reg main_tx_crc_pipe_valid_source_first = 1'd0; +reg main_tx_crc_pipe_valid_source_last = 1'd0; +reg [7:0] main_tx_crc_pipe_valid_source_payload_data = 8'd0; +reg main_tx_crc_pipe_valid_source_payload_error = 1'd0; +reg main_tx_crc_pipe_valid_source_payload_last_be = 1'd0; +wire main_tx_crc_pipe_valid_source_ready; +reg main_tx_crc_pipe_valid_source_valid = 1'd0; +reg [31:0] main_tx_crc_reg = 32'd4294967295; +reg main_tx_crc_reset = 1'd0; +wire main_tx_crc_sink_first; +wire main_tx_crc_sink_last; +wire [7:0] main_tx_crc_sink_payload_data; +wire main_tx_crc_sink_payload_error; +wire main_tx_crc_sink_payload_last_be; +reg main_tx_crc_sink_ready = 1'd0; +wire main_tx_crc_sink_sink_first; +wire main_tx_crc_sink_sink_last; +wire [7:0] main_tx_crc_sink_sink_payload_data; +wire main_tx_crc_sink_sink_payload_error; +wire main_tx_crc_sink_sink_payload_last_be; +wire main_tx_crc_sink_sink_ready; +wire main_tx_crc_sink_sink_valid; +wire main_tx_crc_sink_valid; +reg main_tx_crc_source_first = 1'd0; +reg main_tx_crc_source_last = 1'd0; +reg [7:0] main_tx_crc_source_payload_data = 8'd0; +reg main_tx_crc_source_payload_error = 1'd0; +reg main_tx_crc_source_payload_last_be = 1'd0; +wire main_tx_crc_source_ready; +wire main_tx_crc_source_source_first; +wire main_tx_crc_source_source_last; +wire [7:0] main_tx_crc_source_source_payload_data; +wire main_tx_crc_source_source_payload_error; +wire main_tx_crc_source_source_payload_last_be; +wire main_tx_crc_source_source_ready; +wire main_tx_crc_source_source_valid; +reg main_tx_crc_source_valid = 1'd0; +reg [31:0] main_tx_crc_value = 32'd0; +reg [3:0] main_tx_gap_counter = 4'd0; +reg [3:0] main_tx_gap_counter_clockdomainsrenamer3_next_value = 4'd0; +reg main_tx_gap_counter_clockdomainsrenamer3_next_value_ce = 1'd0; +wire main_tx_gap_sink_first; +wire main_tx_gap_sink_last; +wire [7:0] main_tx_gap_sink_payload_data; +wire main_tx_gap_sink_payload_error; +wire main_tx_gap_sink_payload_last_be; +reg main_tx_gap_sink_ready = 1'd0; +wire main_tx_gap_sink_valid; +reg main_tx_gap_source_first = 1'd0; +reg main_tx_gap_source_last = 1'd0; +reg [7:0] main_tx_gap_source_payload_data = 8'd0; +reg main_tx_gap_source_payload_error = 1'd0; +reg main_tx_gap_source_payload_last_be = 1'd0; +wire main_tx_gap_source_ready; +reg main_tx_gap_source_valid = 1'd0; +wire main_tx_last_be_sink_first; +wire main_tx_last_be_sink_last; +wire [7:0] main_tx_last_be_sink_payload_data; +wire main_tx_last_be_sink_payload_error; +wire main_tx_last_be_sink_payload_last_be; +reg main_tx_last_be_sink_ready = 1'd0; +wire main_tx_last_be_sink_valid; +reg main_tx_last_be_source_first = 1'd0; +reg main_tx_last_be_source_last = 1'd0; +reg [7:0] main_tx_last_be_source_payload_data = 8'd0; +reg main_tx_last_be_source_payload_error = 1'd0; +reg main_tx_last_be_source_payload_last_be = 1'd0; +wire main_tx_last_be_source_ready; +reg main_tx_last_be_source_valid = 1'd0; +reg [15:0] main_tx_padding_counter = 16'd0; +reg [15:0] main_tx_padding_counter_clockdomainsrenamer0_next_value = 16'd0; +reg main_tx_padding_counter_clockdomainsrenamer0_next_value_ce = 1'd0; +wire main_tx_padding_counter_done; +wire main_tx_padding_sink_first; +wire main_tx_padding_sink_last; +wire [7:0] main_tx_padding_sink_payload_data; +wire main_tx_padding_sink_payload_error; +wire main_tx_padding_sink_payload_last_be; +reg main_tx_padding_sink_ready = 1'd0; +wire main_tx_padding_sink_valid; +reg main_tx_padding_source_first = 1'd0; +reg main_tx_padding_source_last = 1'd0; +reg [7:0] main_tx_padding_source_payload_data = 8'd0; +reg main_tx_padding_source_payload_error = 1'd0; +reg main_tx_padding_source_payload_last_be = 1'd0; +wire main_tx_padding_source_ready; +reg main_tx_padding_source_valid = 1'd0; +reg [2:0] main_tx_preamble_count = 3'd0; +reg [2:0] main_tx_preamble_count_clockdomainsrenamer2_next_value = 3'd0; +reg main_tx_preamble_count_clockdomainsrenamer2_next_value_ce = 1'd0; +reg [63:0] main_tx_preamble_preamble = 64'd15372286728091293013; +wire main_tx_preamble_sink_first; +wire main_tx_preamble_sink_last; +wire [7:0] main_tx_preamble_sink_payload_data; +wire main_tx_preamble_sink_payload_error; +wire main_tx_preamble_sink_payload_last_be; +reg main_tx_preamble_sink_ready = 1'd0; +wire main_tx_preamble_sink_valid; +reg main_tx_preamble_source_first = 1'd0; +reg main_tx_preamble_source_last = 1'd0; +reg [7:0] main_tx_preamble_source_payload_data = 8'd0; +reg main_tx_preamble_source_payload_error = 1'd0; +wire main_tx_preamble_source_payload_last_be; +wire main_tx_preamble_source_ready; +reg main_tx_preamble_source_valid = 1'd0; +wire main_wb_bus_ack; +wire [29:0] main_wb_bus_adr; +wire [1:0] main_wb_bus_bte; +wire [2:0] main_wb_bus_cti; +wire main_wb_bus_cyc; +wire [31:0] main_wb_bus_dat_r; +wire [31:0] main_wb_bus_dat_w; +wire main_wb_bus_err; +wire [3:0] main_wb_bus_sel; +wire main_wb_bus_stb; +wire main_wb_bus_we; +wire main_we; +wire [31:0] main_wr_data; +reg main_write = 1'd0; +wire por_clk; +(* dont_touch = "true" *) +wire sys_clk; +wire sys_rst; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ assign main_wb_bus_adr = wishbone_adr; assign main_wb_bus_dat_w = wishbone_dat_w; @@ -1048,362 +1341,693 @@ assign main_wb_bus_we = wishbone_we; assign main_wb_bus_cti = wishbone_cti; assign main_wb_bus_bte = wishbone_bte; assign wishbone_err = main_wb_bus_err; -assign interrupt = main_ev_irq; -assign main_maccore_maccore_bus_error = builder_error; -assign main_maccore_maccore_bus_errors_status = main_maccore_maccore_bus_errors; +assign interrupt = main_sram167_irq; +assign main_maccore_bus_error = builder_error; +assign builder_shared_adr = builder_self0; +assign builder_shared_dat_w = builder_self1; +assign builder_shared_sel = builder_self2; +assign builder_shared_cyc = builder_self3; +assign builder_shared_stb = builder_self4; +assign builder_shared_we = builder_self5; +assign builder_shared_cti = builder_self6; +assign builder_shared_bte = builder_self7; +assign main_wb_bus_dat_r = builder_shared_dat_r; +assign main_wb_bus_ack = (builder_shared_ack & (builder_grant == 1'd0)); +assign main_wb_bus_err = (builder_shared_err & (builder_grant == 1'd0)); +assign builder_request = {main_wb_bus_cyc}; +assign builder_grant = 1'd0; +always @(*) begin + builder_slave_sel <= 2'd0; + builder_slave_sel[0] <= (builder_shared_adr[29:11] == 4'd8); + builder_slave_sel[1] <= (builder_shared_adr[29:14] == 1'd0); +end +assign main_bus_adr = builder_shared_adr; +assign main_bus_dat_w = builder_shared_dat_w; +assign main_bus_sel = builder_shared_sel; +assign main_bus_stb = builder_shared_stb; +assign main_bus_we = builder_shared_we; +assign main_bus_cti = builder_shared_cti; +assign main_bus_bte = builder_shared_bte; +assign builder_interface0_adr = builder_shared_adr; +assign builder_interface0_dat_w = builder_shared_dat_w; +assign builder_interface0_sel = builder_shared_sel; +assign builder_interface0_stb = builder_shared_stb; +assign builder_interface0_we = builder_shared_we; +assign builder_interface0_cti = builder_shared_cti; +assign builder_interface0_bte = builder_shared_bte; +assign main_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]); +assign builder_interface0_cyc = (builder_shared_cyc & builder_slave_sel[1]); +assign builder_shared_err = (main_bus_err | builder_interface0_err); +assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack)); +always @(*) begin + builder_error <= 1'd0; + builder_shared_ack <= 1'd0; + builder_shared_dat_r <= 32'd0; + builder_shared_ack <= (main_bus_ack | builder_interface0_ack); + builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & builder_interface0_dat_r)); + if (builder_done) begin + builder_shared_dat_r <= 32'd4294967295; + builder_shared_ack <= 1'd1; + builder_error <= 1'd1; + end +end +assign builder_done = (builder_count == 1'd0); +assign main_maccore_bus_errors_status = main_maccore_bus_errors; assign sys_clk = sys_clock; assign por_clk = sys_clock; assign sys_rst = main_maccore_int_rst; -assign eth_rx_clk = mii_eth_clocks_rx; -assign eth_tx_clk = mii_eth_clocks_tx; -assign main_maccore_ethphy_reset0 = (main_maccore_ethphy_reset_storage | main_maccore_ethphy_reset1); -assign mii_eth_rst_n = (~main_maccore_ethphy_reset0); -assign main_maccore_ethphy_counter_done = (main_maccore_ethphy_counter == 9'd256); -assign main_maccore_ethphy_counter_ce = (~main_maccore_ethphy_counter_done); -assign main_maccore_ethphy_reset1 = (~main_maccore_ethphy_counter_done); -assign main_maccore_ethphy_liteethphymiitx_converter_sink_valid = main_maccore_ethphy_liteethphymiitx_sink_sink_valid; -assign main_maccore_ethphy_liteethphymiitx_converter_sink_payload_data = main_maccore_ethphy_liteethphymiitx_sink_sink_payload_data; -assign main_maccore_ethphy_liteethphymiitx_sink_sink_ready = main_maccore_ethphy_liteethphymiitx_converter_sink_ready; -assign main_maccore_ethphy_liteethphymiitx_converter_source_ready = 1'd1; -assign main_maccore_ethphy_liteethphymiitx_converter_converter_sink_valid = main_maccore_ethphy_liteethphymiitx_converter_sink_valid; -assign main_maccore_ethphy_liteethphymiitx_converter_converter_sink_first = main_maccore_ethphy_liteethphymiitx_converter_sink_first; -assign main_maccore_ethphy_liteethphymiitx_converter_converter_sink_last = main_maccore_ethphy_liteethphymiitx_converter_sink_last; -assign main_maccore_ethphy_liteethphymiitx_converter_sink_ready = main_maccore_ethphy_liteethphymiitx_converter_converter_sink_ready; -always @(*) begin - main_maccore_ethphy_liteethphymiitx_converter_converter_sink_payload_data <= 8'd0; - main_maccore_ethphy_liteethphymiitx_converter_converter_sink_payload_data[3:0] <= main_maccore_ethphy_liteethphymiitx_converter_sink_payload_data[3:0]; - main_maccore_ethphy_liteethphymiitx_converter_converter_sink_payload_data[7:4] <= main_maccore_ethphy_liteethphymiitx_converter_sink_payload_data[7:4]; -end -assign main_maccore_ethphy_liteethphymiitx_converter_source_valid = main_maccore_ethphy_liteethphymiitx_converter_source_source_valid; -assign main_maccore_ethphy_liteethphymiitx_converter_source_first = main_maccore_ethphy_liteethphymiitx_converter_source_source_first; -assign main_maccore_ethphy_liteethphymiitx_converter_source_last = main_maccore_ethphy_liteethphymiitx_converter_source_source_last; -assign main_maccore_ethphy_liteethphymiitx_converter_source_source_ready = main_maccore_ethphy_liteethphymiitx_converter_source_ready; -assign {main_maccore_ethphy_liteethphymiitx_converter_source_payload_data} = main_maccore_ethphy_liteethphymiitx_converter_source_source_payload_data; -assign main_maccore_ethphy_liteethphymiitx_converter_source_source_valid = main_maccore_ethphy_liteethphymiitx_converter_converter_source_valid; -assign main_maccore_ethphy_liteethphymiitx_converter_converter_source_ready = main_maccore_ethphy_liteethphymiitx_converter_source_source_ready; -assign main_maccore_ethphy_liteethphymiitx_converter_source_source_first = main_maccore_ethphy_liteethphymiitx_converter_converter_source_first; -assign main_maccore_ethphy_liteethphymiitx_converter_source_source_last = main_maccore_ethphy_liteethphymiitx_converter_converter_source_last; -assign main_maccore_ethphy_liteethphymiitx_converter_source_source_payload_data = main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_data; -assign main_maccore_ethphy_liteethphymiitx_converter_converter_first = (main_maccore_ethphy_liteethphymiitx_converter_converter_mux == 1'd0); -assign main_maccore_ethphy_liteethphymiitx_converter_converter_last = (main_maccore_ethphy_liteethphymiitx_converter_converter_mux == 1'd1); -assign main_maccore_ethphy_liteethphymiitx_converter_converter_source_valid = main_maccore_ethphy_liteethphymiitx_converter_converter_sink_valid; -assign main_maccore_ethphy_liteethphymiitx_converter_converter_source_first = (main_maccore_ethphy_liteethphymiitx_converter_converter_sink_first & main_maccore_ethphy_liteethphymiitx_converter_converter_first); -assign main_maccore_ethphy_liteethphymiitx_converter_converter_source_last = (main_maccore_ethphy_liteethphymiitx_converter_converter_sink_last & main_maccore_ethphy_liteethphymiitx_converter_converter_last); -assign main_maccore_ethphy_liteethphymiitx_converter_converter_sink_ready = (main_maccore_ethphy_liteethphymiitx_converter_converter_last & main_maccore_ethphy_liteethphymiitx_converter_converter_source_ready); -always @(*) begin - main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_data <= 4'd0; - case (main_maccore_ethphy_liteethphymiitx_converter_converter_mux) - 1'd0: begin - main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_data <= main_maccore_ethphy_liteethphymiitx_converter_converter_sink_payload_data[3:0]; - end - default: begin - main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_data <= main_maccore_ethphy_liteethphymiitx_converter_converter_sink_payload_data[7:4]; - end - endcase -end -assign main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_valid_token_count = main_maccore_ethphy_liteethphymiitx_converter_converter_last; -assign main_maccore_ethphy_liteethphymiirx_converter_sink_last = (~mii_eth_rx_dv); -assign main_maccore_ethphy_liteethphymiirx_source_source_valid = main_maccore_ethphy_liteethphymiirx_converter_source_valid; -assign main_maccore_ethphy_liteethphymiirx_converter_source_ready = main_maccore_ethphy_liteethphymiirx_source_source_ready; -assign main_maccore_ethphy_liteethphymiirx_source_source_first = main_maccore_ethphy_liteethphymiirx_converter_source_first; -assign main_maccore_ethphy_liteethphymiirx_source_source_last = main_maccore_ethphy_liteethphymiirx_converter_source_last; -assign main_maccore_ethphy_liteethphymiirx_source_source_payload_data = main_maccore_ethphy_liteethphymiirx_converter_source_payload_data; -assign main_maccore_ethphy_liteethphymiirx_converter_converter_sink_valid = main_maccore_ethphy_liteethphymiirx_converter_sink_valid; -assign main_maccore_ethphy_liteethphymiirx_converter_converter_sink_first = main_maccore_ethphy_liteethphymiirx_converter_sink_first; -assign main_maccore_ethphy_liteethphymiirx_converter_converter_sink_last = main_maccore_ethphy_liteethphymiirx_converter_sink_last; -assign main_maccore_ethphy_liteethphymiirx_converter_sink_ready = main_maccore_ethphy_liteethphymiirx_converter_converter_sink_ready; -assign main_maccore_ethphy_liteethphymiirx_converter_converter_sink_payload_data = {main_maccore_ethphy_liteethphymiirx_converter_sink_payload_data}; -assign main_maccore_ethphy_liteethphymiirx_converter_source_valid = main_maccore_ethphy_liteethphymiirx_converter_source_source_valid; -assign main_maccore_ethphy_liteethphymiirx_converter_source_first = main_maccore_ethphy_liteethphymiirx_converter_source_source_first; -assign main_maccore_ethphy_liteethphymiirx_converter_source_last = main_maccore_ethphy_liteethphymiirx_converter_source_source_last; -assign main_maccore_ethphy_liteethphymiirx_converter_source_source_ready = main_maccore_ethphy_liteethphymiirx_converter_source_ready; -always @(*) begin - main_maccore_ethphy_liteethphymiirx_converter_source_payload_data <= 8'd0; - main_maccore_ethphy_liteethphymiirx_converter_source_payload_data[3:0] <= main_maccore_ethphy_liteethphymiirx_converter_source_source_payload_data[3:0]; - main_maccore_ethphy_liteethphymiirx_converter_source_payload_data[7:4] <= main_maccore_ethphy_liteethphymiirx_converter_source_source_payload_data[7:4]; -end -assign main_maccore_ethphy_liteethphymiirx_converter_source_source_valid = main_maccore_ethphy_liteethphymiirx_converter_converter_source_valid; -assign main_maccore_ethphy_liteethphymiirx_converter_converter_source_ready = main_maccore_ethphy_liteethphymiirx_converter_source_source_ready; -assign main_maccore_ethphy_liteethphymiirx_converter_source_source_first = main_maccore_ethphy_liteethphymiirx_converter_converter_source_first; -assign main_maccore_ethphy_liteethphymiirx_converter_source_source_last = main_maccore_ethphy_liteethphymiirx_converter_converter_source_last; -assign main_maccore_ethphy_liteethphymiirx_converter_source_source_payload_data = main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_data; -assign main_maccore_ethphy_liteethphymiirx_converter_converter_sink_ready = ((~main_maccore_ethphy_liteethphymiirx_converter_converter_strobe_all) | main_maccore_ethphy_liteethphymiirx_converter_converter_source_ready); -assign main_maccore_ethphy_liteethphymiirx_converter_converter_source_valid = main_maccore_ethphy_liteethphymiirx_converter_converter_strobe_all; -assign main_maccore_ethphy_liteethphymiirx_converter_converter_load_part = (main_maccore_ethphy_liteethphymiirx_converter_converter_sink_valid & main_maccore_ethphy_liteethphymiirx_converter_converter_sink_ready); -assign mii_eth_mdc = main_maccore_ethphy__w_storage[0]; -assign main_maccore_ethphy_data_oe = main_maccore_ethphy__w_storage[1]; -assign main_maccore_ethphy_data_w = main_maccore_ethphy__w_storage[2]; -assign main_tx_cdc_sink_sink_valid = main_source_valid; -assign main_source_ready = main_tx_cdc_sink_sink_ready; -assign main_tx_cdc_sink_sink_first = main_source_first; -assign main_tx_cdc_sink_sink_last = main_source_last; -assign main_tx_cdc_sink_sink_payload_data = main_source_payload_data; -assign main_tx_cdc_sink_sink_payload_last_be = main_source_payload_last_be; -assign main_tx_cdc_sink_sink_payload_error = main_source_payload_error; -assign main_sink_valid = main_rx_cdc_source_source_valid; -assign main_rx_cdc_source_source_ready = main_sink_ready; -assign main_sink_first = main_rx_cdc_source_source_first; -assign main_sink_last = main_rx_cdc_source_source_last; -assign main_sink_payload_data = main_rx_cdc_source_source_payload_data; -assign main_sink_payload_last_be = main_rx_cdc_source_source_payload_last_be; -assign main_sink_payload_error = main_rx_cdc_source_source_payload_error; -assign main_ps_preamble_error_i = main_preamble_checker_error; -assign main_ps_crc_error_i = main_liteethmaccrc32checker_error; -always @(*) begin - main_tx_gap_inserter_source_valid <= 1'd0; - builder_liteethmacgap_next_state <= 1'd0; - main_tx_gap_inserter_counter_liteethmacgap_next_value <= 4'd0; - main_tx_gap_inserter_source_first <= 1'd0; - main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd0; - main_tx_gap_inserter_source_last <= 1'd0; - main_tx_gap_inserter_source_payload_data <= 8'd0; - main_tx_gap_inserter_source_payload_last_be <= 1'd0; - main_tx_gap_inserter_source_payload_error <= 1'd0; - main_tx_gap_inserter_sink_ready <= 1'd0; - builder_liteethmacgap_next_state <= builder_liteethmacgap_state; - case (builder_liteethmacgap_state) - 1'd1: begin - main_tx_gap_inserter_counter_liteethmacgap_next_value <= (main_tx_gap_inserter_counter + 1'd1); - main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1; - if ((main_tx_gap_inserter_counter == 4'd11)) begin - builder_liteethmacgap_next_state <= 1'd0; - end - end - default: begin - main_tx_gap_inserter_counter_liteethmacgap_next_value <= 1'd0; - main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1; - main_tx_gap_inserter_source_valid <= main_tx_gap_inserter_sink_valid; - main_tx_gap_inserter_sink_ready <= main_tx_gap_inserter_source_ready; - main_tx_gap_inserter_source_first <= main_tx_gap_inserter_sink_first; - main_tx_gap_inserter_source_last <= main_tx_gap_inserter_sink_last; - main_tx_gap_inserter_source_payload_data <= main_tx_gap_inserter_sink_payload_data; - main_tx_gap_inserter_source_payload_last_be <= main_tx_gap_inserter_sink_payload_last_be; - main_tx_gap_inserter_source_payload_error <= main_tx_gap_inserter_sink_payload_error; - if (((main_tx_gap_inserter_sink_valid & main_tx_gap_inserter_sink_last) & main_tx_gap_inserter_sink_ready)) begin - builder_liteethmacgap_next_state <= 1'd1; - end - end - endcase -end -assign main_preamble_inserter_source_payload_last_be = main_preamble_inserter_sink_payload_last_be; -always @(*) begin - builder_liteethmacpreambleinserter_next_state <= 2'd0; - main_preamble_inserter_count_liteethmacpreambleinserter_next_value <= 3'd0; - main_preamble_inserter_source_valid <= 1'd0; - main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd0; - main_preamble_inserter_source_first <= 1'd0; - main_preamble_inserter_source_last <= 1'd0; - main_preamble_inserter_source_payload_data <= 8'd0; - main_preamble_inserter_source_payload_error <= 1'd0; - main_preamble_inserter_sink_ready <= 1'd0; - main_preamble_inserter_source_payload_data <= main_preamble_inserter_sink_payload_data; - builder_liteethmacpreambleinserter_next_state <= builder_liteethmacpreambleinserter_state; - case (builder_liteethmacpreambleinserter_state) - 1'd1: begin - main_preamble_inserter_source_valid <= 1'd1; - case (main_preamble_inserter_count) - 1'd0: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[7:0]; - end - 1'd1: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[15:8]; - end - 2'd2: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[23:16]; - end - 2'd3: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[31:24]; - end - 3'd4: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[39:32]; - end - 3'd5: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[47:40]; - end - 3'd6: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[55:48]; - end - default: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[63:56]; - end - endcase - if (main_preamble_inserter_source_ready) begin - if ((main_preamble_inserter_count == 3'd7)) begin - builder_liteethmacpreambleinserter_next_state <= 2'd2; - end else begin - main_preamble_inserter_count_liteethmacpreambleinserter_next_value <= (main_preamble_inserter_count + 1'd1); - main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1; - end - end - end - 2'd2: begin - main_preamble_inserter_source_valid <= main_preamble_inserter_sink_valid; - main_preamble_inserter_sink_ready <= main_preamble_inserter_source_ready; - main_preamble_inserter_source_first <= main_preamble_inserter_sink_first; - main_preamble_inserter_source_last <= main_preamble_inserter_sink_last; - main_preamble_inserter_source_payload_error <= main_preamble_inserter_sink_payload_error; - if (((main_preamble_inserter_sink_valid & main_preamble_inserter_sink_last) & main_preamble_inserter_source_ready)) begin - builder_liteethmacpreambleinserter_next_state <= 1'd0; - end - end - default: begin - main_preamble_inserter_sink_ready <= 1'd1; - main_preamble_inserter_count_liteethmacpreambleinserter_next_value <= 1'd0; - main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1; - if (main_preamble_inserter_sink_valid) begin - main_preamble_inserter_sink_ready <= 1'd0; - builder_liteethmacpreambleinserter_next_state <= 1'd1; - end - end - endcase -end -assign main_preamble_checker_source_payload_data = main_preamble_checker_sink_payload_data; -assign main_preamble_checker_source_payload_last_be = main_preamble_checker_sink_payload_last_be; -always @(*) begin - builder_liteethmacpreamblechecker_next_state <= 1'd0; - main_preamble_checker_source_first <= 1'd0; - main_preamble_checker_sink_ready <= 1'd0; - main_preamble_checker_source_last <= 1'd0; - main_preamble_checker_source_payload_error <= 1'd0; - main_preamble_checker_error <= 1'd0; - main_preamble_checker_source_valid <= 1'd0; - builder_liteethmacpreamblechecker_next_state <= builder_liteethmacpreamblechecker_state; - case (builder_liteethmacpreamblechecker_state) - 1'd1: begin - main_preamble_checker_source_valid <= main_preamble_checker_sink_valid; - main_preamble_checker_sink_ready <= main_preamble_checker_source_ready; - main_preamble_checker_source_first <= main_preamble_checker_sink_first; - main_preamble_checker_source_last <= main_preamble_checker_sink_last; - main_preamble_checker_source_payload_error <= main_preamble_checker_sink_payload_error; - if (((main_preamble_checker_source_valid & main_preamble_checker_source_last) & main_preamble_checker_source_ready)) begin - builder_liteethmacpreamblechecker_next_state <= 1'd0; - end - end - default: begin - main_preamble_checker_sink_ready <= 1'd1; - if (((main_preamble_checker_sink_valid & (~main_preamble_checker_sink_last)) & (main_preamble_checker_sink_payload_data == 8'd213))) begin - builder_liteethmacpreamblechecker_next_state <= 1'd1; - end - if ((main_preamble_checker_sink_valid & main_preamble_checker_sink_last)) begin - main_preamble_checker_error <= 1'd1; - end - end - endcase -end -assign main_liteethmaccrc32inserter_cnt_done = (main_liteethmaccrc32inserter_cnt == 1'd0); -assign main_liteethmaccrc32inserter_sink_valid = main_crc32_inserter_source_valid; -assign main_crc32_inserter_source_ready = main_liteethmaccrc32inserter_sink_ready; -assign main_liteethmaccrc32inserter_sink_first = main_crc32_inserter_source_first; -assign main_liteethmaccrc32inserter_sink_last = main_crc32_inserter_source_last; -assign main_liteethmaccrc32inserter_sink_payload_data = main_crc32_inserter_source_payload_data; -assign main_liteethmaccrc32inserter_sink_payload_last_be = main_crc32_inserter_source_payload_last_be; -assign main_liteethmaccrc32inserter_sink_payload_error = main_crc32_inserter_source_payload_error; -assign main_liteethmaccrc32inserter_data1 = main_liteethmaccrc32inserter_data0; -assign main_liteethmaccrc32inserter_last = main_liteethmaccrc32inserter_reg; -assign main_liteethmaccrc32inserter_value = (~{main_liteethmaccrc32inserter_reg[0], main_liteethmaccrc32inserter_reg[1], main_liteethmaccrc32inserter_reg[2], main_liteethmaccrc32inserter_reg[3], main_liteethmaccrc32inserter_reg[4], main_liteethmaccrc32inserter_reg[5], main_liteethmaccrc32inserter_reg[6], main_liteethmaccrc32inserter_reg[7], main_liteethmaccrc32inserter_reg[8], main_liteethmaccrc32inserter_reg[9], main_liteethmaccrc32inserter_reg[10], main_liteethmaccrc32inserter_reg[11], main_liteethmaccrc32inserter_reg[12], main_liteethmaccrc32inserter_reg[13], main_liteethmaccrc32inserter_reg[14], main_liteethmaccrc32inserter_reg[15], main_liteethmaccrc32inserter_reg[16], main_liteethmaccrc32inserter_reg[17], main_liteethmaccrc32inserter_reg[18], main_liteethmaccrc32inserter_reg[19], main_liteethmaccrc32inserter_reg[20], main_liteethmaccrc32inserter_reg[21], main_liteethmaccrc32inserter_reg[22], main_liteethmaccrc32inserter_reg[23], main_liteethmaccrc32inserter_reg[24], main_liteethmaccrc32inserter_reg[25], main_liteethmaccrc32inserter_reg[26], main_liteethmaccrc32inserter_reg[27], main_liteethmaccrc32inserter_reg[28], main_liteethmaccrc32inserter_reg[29], main_liteethmaccrc32inserter_reg[30], main_liteethmaccrc32inserter_reg[31]}); -assign main_liteethmaccrc32inserter_error = (main_liteethmaccrc32inserter_next != 32'd3338984827); -always @(*) begin - main_liteethmaccrc32inserter_next <= 32'd0; - main_liteethmaccrc32inserter_next[0] <= (((main_liteethmaccrc32inserter_last[24] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[1] <= (((((((main_liteethmaccrc32inserter_last[25] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[2] <= (((((((((main_liteethmaccrc32inserter_last[26] ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[3] <= (((((((main_liteethmaccrc32inserter_last[27] ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[4] <= (((((((((main_liteethmaccrc32inserter_last[28] ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[5] <= (((((((((((((main_liteethmaccrc32inserter_last[29] ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[6] <= (((((((((((main_liteethmaccrc32inserter_last[30] ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[7] <= (((((((((main_liteethmaccrc32inserter_last[31] ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[8] <= ((((((((main_liteethmaccrc32inserter_last[0] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[9] <= ((((((((main_liteethmaccrc32inserter_last[1] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[10] <= ((((((((main_liteethmaccrc32inserter_last[2] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[11] <= ((((((((main_liteethmaccrc32inserter_last[3] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[12] <= ((((((((((((main_liteethmaccrc32inserter_last[4] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[13] <= ((((((((((((main_liteethmaccrc32inserter_last[5] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[14] <= ((((((((((main_liteethmaccrc32inserter_last[6] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]); - main_liteethmaccrc32inserter_next[15] <= ((((((((main_liteethmaccrc32inserter_last[7] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]); - main_liteethmaccrc32inserter_next[16] <= ((((((main_liteethmaccrc32inserter_last[8] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[17] <= ((((((main_liteethmaccrc32inserter_last[9] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[18] <= ((((((main_liteethmaccrc32inserter_last[10] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]); - main_liteethmaccrc32inserter_next[19] <= ((((main_liteethmaccrc32inserter_last[11] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]); - main_liteethmaccrc32inserter_next[20] <= ((main_liteethmaccrc32inserter_last[12] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]); - main_liteethmaccrc32inserter_next[21] <= ((main_liteethmaccrc32inserter_last[13] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]); - main_liteethmaccrc32inserter_next[22] <= ((main_liteethmaccrc32inserter_last[14] ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[23] <= ((((((main_liteethmaccrc32inserter_last[15] ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[24] <= ((((((main_liteethmaccrc32inserter_last[16] ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[25] <= ((((main_liteethmaccrc32inserter_last[17] ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]); - main_liteethmaccrc32inserter_next[26] <= ((((((((main_liteethmaccrc32inserter_last[18] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[27] <= ((((((((main_liteethmaccrc32inserter_last[19] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[28] <= ((((((main_liteethmaccrc32inserter_last[20] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]); - main_liteethmaccrc32inserter_next[29] <= ((((((main_liteethmaccrc32inserter_last[21] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]); - main_liteethmaccrc32inserter_next[30] <= ((((main_liteethmaccrc32inserter_last[22] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]); - main_liteethmaccrc32inserter_next[31] <= ((main_liteethmaccrc32inserter_last[23] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]); -end -always @(*) begin - main_liteethmaccrc32inserter_source_valid <= 1'd0; - main_liteethmaccrc32inserter_source_first <= 1'd0; - main_liteethmaccrc32inserter_source_last <= 1'd0; - main_liteethmaccrc32inserter_source_payload_data <= 8'd0; - main_liteethmaccrc32inserter_source_payload_last_be <= 1'd0; - main_liteethmaccrc32inserter_source_payload_error <= 1'd0; - builder_liteethmaccrc32inserter_next_state <= 2'd0; - main_liteethmaccrc32inserter_data0 <= 8'd0; - main_liteethmaccrc32inserter_is_ongoing0 <= 1'd0; - main_liteethmaccrc32inserter_sink_ready <= 1'd0; - main_liteethmaccrc32inserter_is_ongoing1 <= 1'd0; - main_liteethmaccrc32inserter_ce <= 1'd0; - main_liteethmaccrc32inserter_reset <= 1'd0; - builder_liteethmaccrc32inserter_next_state <= builder_liteethmaccrc32inserter_state; - case (builder_liteethmaccrc32inserter_state) - 1'd1: begin - main_liteethmaccrc32inserter_ce <= (main_liteethmaccrc32inserter_sink_valid & main_liteethmaccrc32inserter_source_ready); - main_liteethmaccrc32inserter_data0 <= main_liteethmaccrc32inserter_sink_payload_data; - main_liteethmaccrc32inserter_source_valid <= main_liteethmaccrc32inserter_sink_valid; - main_liteethmaccrc32inserter_sink_ready <= main_liteethmaccrc32inserter_source_ready; - main_liteethmaccrc32inserter_source_first <= main_liteethmaccrc32inserter_sink_first; - main_liteethmaccrc32inserter_source_last <= main_liteethmaccrc32inserter_sink_last; - main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_sink_payload_data; - main_liteethmaccrc32inserter_source_payload_last_be <= main_liteethmaccrc32inserter_sink_payload_last_be; - main_liteethmaccrc32inserter_source_payload_error <= main_liteethmaccrc32inserter_sink_payload_error; - main_liteethmaccrc32inserter_source_last <= 1'd0; - if (((main_liteethmaccrc32inserter_sink_valid & main_liteethmaccrc32inserter_sink_last) & main_liteethmaccrc32inserter_source_ready)) begin - builder_liteethmaccrc32inserter_next_state <= 2'd2; - end - end - 2'd2: begin - main_liteethmaccrc32inserter_source_valid <= 1'd1; - case (main_liteethmaccrc32inserter_cnt) - 1'd0: begin - main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[31:24]; - end - 1'd1: begin - main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[23:16]; - end - 2'd2: begin - main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[15:8]; - end - default: begin - main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[7:0]; - end - endcase - if (main_liteethmaccrc32inserter_cnt_done) begin - main_liteethmaccrc32inserter_source_last <= 1'd1; - if (main_liteethmaccrc32inserter_source_ready) begin - builder_liteethmaccrc32inserter_next_state <= 1'd0; - end - end - main_liteethmaccrc32inserter_is_ongoing1 <= 1'd1; - end - default: begin - main_liteethmaccrc32inserter_reset <= 1'd1; - main_liteethmaccrc32inserter_sink_ready <= 1'd1; - if (main_liteethmaccrc32inserter_sink_valid) begin - main_liteethmaccrc32inserter_sink_ready <= 1'd0; - builder_liteethmaccrc32inserter_next_state <= 1'd1; - end - main_liteethmaccrc32inserter_is_ongoing0 <= 1'd1; - end - endcase -end -assign main_crc32_inserter_sink_ready = ((~main_crc32_inserter_source_valid) | main_crc32_inserter_source_ready); +assign eth_rx_clk = mii_clocks_rx; +assign eth_tx_clk = mii_clocks_tx; +assign main_maccore_crg_reset0 = (main_maccore_crg_reset_storage | main_maccore_crg_reset1); +assign mii_rst_n = (~main_maccore_crg_reset0); +assign main_maccore_crg_counter_done = (main_maccore_crg_counter == 9'd256); +assign main_maccore_crg_counter_ce = (~main_maccore_crg_counter_done); +assign main_maccore_crg_reset1 = (~main_maccore_crg_counter_done); +assign main_maccore_liteethphymiitx_converter_sink_valid = main_maccore_liteethphymiitx_sink_valid; +assign main_maccore_liteethphymiitx_converter_sink_payload_data = main_maccore_liteethphymiitx_sink_payload_data; +assign main_maccore_liteethphymiitx_sink_ready = main_maccore_liteethphymiitx_converter_sink_ready; +assign main_maccore_liteethphymiitx_source_source_ready = 1'd1; +assign main_maccore_liteethphymiitx_source_source_valid = main_maccore_liteethphymiitx_converter_source_valid; +assign main_maccore_liteethphymiitx_converter_source_ready = main_maccore_liteethphymiitx_source_source_ready; +assign main_maccore_liteethphymiitx_source_source_first = main_maccore_liteethphymiitx_converter_source_first; +assign main_maccore_liteethphymiitx_source_source_last = main_maccore_liteethphymiitx_converter_source_last; +assign main_maccore_liteethphymiitx_source_source_payload_data = main_maccore_liteethphymiitx_converter_source_payload_data; +assign main_maccore_liteethphymiitx_converter_first = (main_maccore_liteethphymiitx_converter_mux == 1'd0); +assign main_maccore_liteethphymiitx_converter_last = (main_maccore_liteethphymiitx_converter_mux == 1'd1); +assign main_maccore_liteethphymiitx_converter_source_valid = main_maccore_liteethphymiitx_converter_sink_valid; +assign main_maccore_liteethphymiitx_converter_source_first = (main_maccore_liteethphymiitx_converter_sink_first & main_maccore_liteethphymiitx_converter_first); +assign main_maccore_liteethphymiitx_converter_source_last = (main_maccore_liteethphymiitx_converter_sink_last & main_maccore_liteethphymiitx_converter_last); +assign main_maccore_liteethphymiitx_converter_sink_ready = (main_maccore_liteethphymiitx_converter_last & main_maccore_liteethphymiitx_converter_source_ready); +always @(*) begin + main_maccore_liteethphymiitx_converter_source_payload_data <= 4'd0; + case (main_maccore_liteethphymiitx_converter_mux) + 1'd0: begin + main_maccore_liteethphymiitx_converter_source_payload_data <= main_maccore_liteethphymiitx_converter_sink_payload_data[3:0]; + end + default: begin + main_maccore_liteethphymiitx_converter_source_payload_data <= main_maccore_liteethphymiitx_converter_sink_payload_data[7:4]; + end + endcase +end +assign main_maccore_liteethphymiitx_converter_source_payload_valid_token_count = main_maccore_liteethphymiitx_converter_last; +assign main_maccore_liteethphymiirx_converter_sink_last = (~mii_rx_dv); +assign main_maccore_liteethphymiirx_source_valid = main_maccore_liteethphymiirx_source_source_valid; +assign main_maccore_liteethphymiirx_source_source_ready = main_maccore_liteethphymiirx_source_ready; +assign main_maccore_liteethphymiirx_source_first = main_maccore_liteethphymiirx_source_source_first; +assign main_maccore_liteethphymiirx_source_last = main_maccore_liteethphymiirx_source_source_last; +assign main_maccore_liteethphymiirx_source_payload_data = main_maccore_liteethphymiirx_source_source_payload_data; +assign main_maccore_liteethphymiirx_source_source_valid = main_maccore_liteethphymiirx_converter_source_valid; +assign main_maccore_liteethphymiirx_converter_source_ready = main_maccore_liteethphymiirx_source_source_ready; +assign main_maccore_liteethphymiirx_source_source_first = main_maccore_liteethphymiirx_converter_source_first; +assign main_maccore_liteethphymiirx_source_source_last = main_maccore_liteethphymiirx_converter_source_last; +assign main_maccore_liteethphymiirx_source_source_payload_data = main_maccore_liteethphymiirx_converter_source_payload_data; +assign main_maccore_liteethphymiirx_converter_sink_ready = ((~main_maccore_liteethphymiirx_converter_strobe_all) | main_maccore_liteethphymiirx_converter_source_ready); +assign main_maccore_liteethphymiirx_converter_source_valid = main_maccore_liteethphymiirx_converter_strobe_all; +assign main_maccore_liteethphymiirx_converter_load_part = (main_maccore_liteethphymiirx_converter_sink_valid & main_maccore_liteethphymiirx_converter_sink_ready); +assign mii_mdc = main_maccore__w_storage[0]; +assign main_maccore_data_oe = main_maccore__w_storage[1]; +assign main_maccore_data_w = main_maccore__w_storage[2]; +assign main_sink_valid = main_source_source_valid; +assign main_source_source_ready = main_sink_ready; +assign main_sink_first = main_source_source_first; +assign main_sink_last = main_source_source_last; +assign main_sink_payload_data = main_source_source_payload_data; +assign main_sink_payload_last_be = main_source_source_payload_last_be; +assign main_sink_payload_error = main_source_source_payload_error; +assign main_sink_sink_valid = main_source_valid; +assign main_source_ready = main_sink_sink_ready; +assign main_sink_sink_first = main_source_first; +assign main_sink_sink_last = main_source_last; +assign main_sink_sink_payload_data = main_source_payload_data; +assign main_sink_sink_payload_last_be = main_source_payload_last_be; +assign main_sink_sink_payload_error = main_source_payload_error; +assign main_tx_cdc_cdc_sink_valid = main_tx_cdc_sink_sink_valid; +assign main_tx_cdc_sink_sink_ready = main_tx_cdc_cdc_sink_ready; +assign main_tx_cdc_cdc_sink_first = main_tx_cdc_sink_sink_first; +assign main_tx_cdc_cdc_sink_last = main_tx_cdc_sink_sink_last; +assign main_tx_cdc_cdc_sink_payload_data = main_tx_cdc_sink_sink_payload_data; +assign main_tx_cdc_cdc_sink_payload_last_be = main_tx_cdc_sink_sink_payload_last_be; +assign main_tx_cdc_cdc_sink_payload_error = main_tx_cdc_sink_sink_payload_error; +assign main_tx_cdc_source_source_valid = main_tx_cdc_cdc_source_valid; +assign main_tx_cdc_cdc_source_ready = main_tx_cdc_source_source_ready; +assign main_tx_cdc_source_source_first = main_tx_cdc_cdc_source_first; +assign main_tx_cdc_source_source_last = main_tx_cdc_cdc_source_last; +assign main_tx_cdc_source_source_payload_data = main_tx_cdc_cdc_source_payload_data; +assign main_tx_cdc_source_source_payload_last_be = main_tx_cdc_cdc_source_payload_last_be; +assign main_tx_cdc_source_source_payload_error = main_tx_cdc_cdc_source_payload_error; +assign main_tx_cdc_cdc_asyncfifo_din = {main_tx_cdc_cdc_fifo_in_last, main_tx_cdc_cdc_fifo_in_first, main_tx_cdc_cdc_fifo_in_payload_error, main_tx_cdc_cdc_fifo_in_payload_last_be, main_tx_cdc_cdc_fifo_in_payload_data}; +assign {main_tx_cdc_cdc_fifo_out_last, main_tx_cdc_cdc_fifo_out_first, main_tx_cdc_cdc_fifo_out_payload_error, main_tx_cdc_cdc_fifo_out_payload_last_be, main_tx_cdc_cdc_fifo_out_payload_data} = main_tx_cdc_cdc_asyncfifo_dout; +assign main_tx_cdc_cdc_sink_ready = main_tx_cdc_cdc_asyncfifo_writable; +assign main_tx_cdc_cdc_asyncfifo_we = main_tx_cdc_cdc_sink_valid; +assign main_tx_cdc_cdc_fifo_in_first = main_tx_cdc_cdc_sink_first; +assign main_tx_cdc_cdc_fifo_in_last = main_tx_cdc_cdc_sink_last; +assign main_tx_cdc_cdc_fifo_in_payload_data = main_tx_cdc_cdc_sink_payload_data; +assign main_tx_cdc_cdc_fifo_in_payload_last_be = main_tx_cdc_cdc_sink_payload_last_be; +assign main_tx_cdc_cdc_fifo_in_payload_error = main_tx_cdc_cdc_sink_payload_error; +assign main_tx_cdc_cdc_source_valid = main_tx_cdc_cdc_asyncfifo_readable; +assign main_tx_cdc_cdc_source_first = main_tx_cdc_cdc_fifo_out_first; +assign main_tx_cdc_cdc_source_last = main_tx_cdc_cdc_fifo_out_last; +assign main_tx_cdc_cdc_source_payload_data = main_tx_cdc_cdc_fifo_out_payload_data; +assign main_tx_cdc_cdc_source_payload_last_be = main_tx_cdc_cdc_fifo_out_payload_last_be; +assign main_tx_cdc_cdc_source_payload_error = main_tx_cdc_cdc_fifo_out_payload_error; +assign main_tx_cdc_cdc_asyncfifo_re = main_tx_cdc_cdc_source_ready; +assign main_tx_cdc_cdc_graycounter0_ce = (main_tx_cdc_cdc_asyncfifo_writable & main_tx_cdc_cdc_asyncfifo_we); +assign main_tx_cdc_cdc_graycounter1_ce = (main_tx_cdc_cdc_asyncfifo_readable & main_tx_cdc_cdc_asyncfifo_re); +assign main_tx_cdc_cdc_asyncfifo_writable = (((main_tx_cdc_cdc_graycounter0_q[5] == main_tx_cdc_cdc_consume_wdomain[5]) | (main_tx_cdc_cdc_graycounter0_q[4] == main_tx_cdc_cdc_consume_wdomain[4])) | (main_tx_cdc_cdc_graycounter0_q[3:0] != main_tx_cdc_cdc_consume_wdomain[3:0])); +assign main_tx_cdc_cdc_asyncfifo_readable = (main_tx_cdc_cdc_graycounter1_q != main_tx_cdc_cdc_produce_rdomain); +assign main_tx_cdc_cdc_wrport_adr = main_tx_cdc_cdc_graycounter0_q_binary[4:0]; +assign main_tx_cdc_cdc_wrport_dat_w = main_tx_cdc_cdc_asyncfifo_din; +assign main_tx_cdc_cdc_wrport_we = main_tx_cdc_cdc_graycounter0_ce; +assign main_tx_cdc_cdc_rdport_adr = main_tx_cdc_cdc_graycounter1_q_next_binary[4:0]; +assign main_tx_cdc_cdc_asyncfifo_dout = main_tx_cdc_cdc_rdport_dat_r; +always @(*) begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (main_tx_cdc_cdc_graycounter0_ce) begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= (main_tx_cdc_cdc_graycounter0_q_binary + 1'd1); + end else begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= main_tx_cdc_cdc_graycounter0_q_binary; + end +end +assign main_tx_cdc_cdc_graycounter0_q_next = (main_tx_cdc_cdc_graycounter0_q_next_binary ^ main_tx_cdc_cdc_graycounter0_q_next_binary[5:1]); +always @(*) begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (main_tx_cdc_cdc_graycounter1_ce) begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= (main_tx_cdc_cdc_graycounter1_q_binary + 1'd1); + end else begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= main_tx_cdc_cdc_graycounter1_q_binary; + end +end +assign main_tx_cdc_cdc_graycounter1_q_next = (main_tx_cdc_cdc_graycounter1_q_next_binary ^ main_tx_cdc_cdc_graycounter1_q_next_binary[5:1]); +assign main_tx_converter_converter_sink_valid = main_tx_converter_sink_valid; +assign main_tx_converter_converter_sink_first = main_tx_converter_sink_first; +assign main_tx_converter_converter_sink_last = main_tx_converter_sink_last; +assign main_tx_converter_sink_ready = main_tx_converter_converter_sink_ready; +always @(*) begin + main_tx_converter_converter_sink_payload_data <= 40'd0; + main_tx_converter_converter_sink_payload_data[7:0] <= main_tx_converter_sink_payload_data[7:0]; + main_tx_converter_converter_sink_payload_data[8] <= main_tx_converter_sink_payload_last_be[0]; + main_tx_converter_converter_sink_payload_data[9] <= main_tx_converter_sink_payload_error[0]; + main_tx_converter_converter_sink_payload_data[17:10] <= main_tx_converter_sink_payload_data[15:8]; + main_tx_converter_converter_sink_payload_data[18] <= main_tx_converter_sink_payload_last_be[1]; + main_tx_converter_converter_sink_payload_data[19] <= main_tx_converter_sink_payload_error[1]; + main_tx_converter_converter_sink_payload_data[27:20] <= main_tx_converter_sink_payload_data[23:16]; + main_tx_converter_converter_sink_payload_data[28] <= main_tx_converter_sink_payload_last_be[2]; + main_tx_converter_converter_sink_payload_data[29] <= main_tx_converter_sink_payload_error[2]; + main_tx_converter_converter_sink_payload_data[37:30] <= main_tx_converter_sink_payload_data[31:24]; + main_tx_converter_converter_sink_payload_data[38] <= main_tx_converter_sink_payload_last_be[3]; + main_tx_converter_converter_sink_payload_data[39] <= main_tx_converter_sink_payload_error[3]; +end +assign main_tx_converter_source_valid = main_tx_converter_source_source_valid; +assign main_tx_converter_source_first = main_tx_converter_source_source_first; +assign main_tx_converter_source_last = main_tx_converter_source_source_last; +assign main_tx_converter_source_source_ready = main_tx_converter_source_ready; +assign {main_tx_converter_source_payload_error, main_tx_converter_source_payload_last_be, main_tx_converter_source_payload_data} = main_tx_converter_source_source_payload_data; +assign main_tx_converter_source_source_valid = main_tx_converter_converter_source_valid; +assign main_tx_converter_converter_source_ready = main_tx_converter_source_source_ready; +assign main_tx_converter_source_source_first = main_tx_converter_converter_source_first; +assign main_tx_converter_source_source_last = main_tx_converter_converter_source_last; +assign main_tx_converter_source_source_payload_data = main_tx_converter_converter_source_payload_data; +assign main_tx_converter_converter_first = (main_tx_converter_converter_mux == 1'd0); +assign main_tx_converter_converter_last = (main_tx_converter_converter_mux == 2'd3); +assign main_tx_converter_converter_source_valid = main_tx_converter_converter_sink_valid; +assign main_tx_converter_converter_source_first = (main_tx_converter_converter_sink_first & main_tx_converter_converter_first); +assign main_tx_converter_converter_source_last = (main_tx_converter_converter_sink_last & main_tx_converter_converter_last); +assign main_tx_converter_converter_sink_ready = (main_tx_converter_converter_last & main_tx_converter_converter_source_ready); +always @(*) begin + main_tx_converter_converter_source_payload_data <= 10'd0; + case (main_tx_converter_converter_mux) + 1'd0: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[9:0]; + end + 1'd1: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[19:10]; + end + 2'd2: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[29:20]; + end + default: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[39:30]; + end + endcase +end +assign main_tx_converter_converter_source_payload_valid_token_count = main_tx_converter_converter_last; +always @(*) begin + builder_txdatapath_liteethmactxlastbe_next_state <= 1'd0; + main_tx_last_be_sink_ready <= 1'd0; + main_tx_last_be_source_first <= 1'd0; + main_tx_last_be_source_last <= 1'd0; + main_tx_last_be_source_payload_data <= 8'd0; + main_tx_last_be_source_payload_error <= 1'd0; + main_tx_last_be_source_payload_last_be <= 1'd0; + main_tx_last_be_source_valid <= 1'd0; + builder_txdatapath_liteethmactxlastbe_next_state <= builder_txdatapath_liteethmactxlastbe_state; + case (builder_txdatapath_liteethmactxlastbe_state) + 1'd1: begin + main_tx_last_be_sink_ready <= 1'd1; + if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_last)) begin + builder_txdatapath_liteethmactxlastbe_next_state <= 1'd0; + end + end + default: begin + main_tx_last_be_source_valid <= main_tx_last_be_sink_valid; + main_tx_last_be_sink_ready <= main_tx_last_be_source_ready; + main_tx_last_be_source_first <= main_tx_last_be_sink_first; + main_tx_last_be_source_last <= main_tx_last_be_sink_last; + main_tx_last_be_source_payload_data <= main_tx_last_be_sink_payload_data; + main_tx_last_be_source_payload_last_be <= main_tx_last_be_sink_payload_last_be; + main_tx_last_be_source_payload_error <= main_tx_last_be_sink_payload_error; + main_tx_last_be_source_last <= (main_tx_last_be_sink_payload_last_be != 1'd0); + if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_ready)) begin + if ((main_tx_last_be_source_last & (~main_tx_last_be_sink_last))) begin + builder_txdatapath_liteethmactxlastbe_next_state <= 1'd1; + end + end + end + endcase +end +assign main_tx_padding_counter_done = (main_tx_padding_counter >= 6'd59); +always @(*) begin + builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 16'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd0; + main_tx_padding_sink_ready <= 1'd0; + main_tx_padding_source_first <= 1'd0; + main_tx_padding_source_last <= 1'd0; + main_tx_padding_source_payload_data <= 8'd0; + main_tx_padding_source_payload_error <= 1'd0; + main_tx_padding_source_payload_last_be <= 1'd0; + main_tx_padding_source_valid <= 1'd0; + builder_txdatapath_liteethmacpaddinginserter_next_state <= builder_txdatapath_liteethmacpaddinginserter_state; + case (builder_txdatapath_liteethmacpaddinginserter_state) + 1'd1: begin + main_tx_padding_source_valid <= 1'd1; + if (main_tx_padding_counter_done) begin + main_tx_padding_source_payload_last_be <= 1'd1; + main_tx_padding_source_last <= 1'd1; + end + main_tx_padding_source_payload_data <= 1'd0; + if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (main_tx_padding_counter_done) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + end + end + end + default: begin + main_tx_padding_source_valid <= main_tx_padding_sink_valid; + main_tx_padding_sink_ready <= main_tx_padding_source_ready; + main_tx_padding_source_first <= main_tx_padding_sink_first; + main_tx_padding_source_last <= main_tx_padding_sink_last; + main_tx_padding_source_payload_data <= main_tx_padding_sink_payload_data; + main_tx_padding_source_payload_last_be <= main_tx_padding_sink_payload_last_be; + main_tx_padding_source_payload_error <= main_tx_padding_sink_payload_error; + if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (main_tx_padding_sink_last) begin + if ((~main_tx_padding_counter_done)) begin + main_tx_padding_source_last <= 1'd0; + main_tx_padding_source_payload_last_be <= 1'd0; + builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd1; + end else begin + if (((main_tx_padding_counter == 6'd59) & (main_tx_padding_sink_payload_last_be < 1'd1))) begin + main_tx_padding_source_payload_last_be <= 1'd1; + end else begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + end + end + end + end + end + endcase +end +assign main_tx_crc_data0 = main_tx_crc_sink_payload_data; +assign main_tx_crc_be = main_tx_crc_sink_payload_last_be; +assign main_tx_crc_cnt_done = (main_tx_crc_cnt == 1'd0); +assign main_tx_crc_sink_valid = main_tx_crc_source_source_valid; +assign main_tx_crc_source_source_ready = main_tx_crc_sink_ready; +assign main_tx_crc_sink_first = main_tx_crc_source_source_first; +assign main_tx_crc_sink_last = main_tx_crc_source_source_last; +assign main_tx_crc_sink_payload_data = main_tx_crc_source_source_payload_data; +assign main_tx_crc_sink_payload_last_be = main_tx_crc_source_source_payload_last_be; +assign main_tx_crc_sink_payload_error = main_tx_crc_source_source_payload_error; +assign main_tx_crc_data1 = main_tx_crc_data0[7:0]; +assign main_tx_crc_crc_prev = main_tx_crc_reg; +always @(*) begin + main_tx_crc_error <= 1'd0; + main_tx_crc_value <= 32'd0; + if (main_tx_crc_be) begin + main_tx_crc_value <= {builder_t_slice_proxy31[0], builder_t_slice_proxy30[1], builder_t_slice_proxy29[2], builder_t_slice_proxy28[3], builder_t_slice_proxy27[4], builder_t_slice_proxy26[5], builder_t_slice_proxy25[6], builder_t_slice_proxy24[7], builder_t_slice_proxy23[8], builder_t_slice_proxy22[9], builder_t_slice_proxy21[10], builder_t_slice_proxy20[11], builder_t_slice_proxy19[12], builder_t_slice_proxy18[13], builder_t_slice_proxy17[14], builder_t_slice_proxy16[15], builder_t_slice_proxy15[16], builder_t_slice_proxy14[17], builder_t_slice_proxy13[18], builder_t_slice_proxy12[19], builder_t_slice_proxy11[20], builder_t_slice_proxy10[21], builder_t_slice_proxy9[22], builder_t_slice_proxy8[23], builder_t_slice_proxy7[24], builder_t_slice_proxy6[25], builder_t_slice_proxy5[26], builder_t_slice_proxy4[27], builder_t_slice_proxy3[28], builder_t_slice_proxy2[29], builder_t_slice_proxy1[30], builder_t_slice_proxy0[31]}; + main_tx_crc_error <= (main_tx_crc_crc_next != 32'd3338984827); + end +end +always @(*) begin + main_tx_crc_crc_next <= 32'd0; + main_tx_crc_crc_next[0] <= (((main_tx_crc_crc_prev[24] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[1] <= (((((((main_tx_crc_crc_prev[25] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[2] <= (((((((((main_tx_crc_crc_prev[26] ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[3] <= (((((((main_tx_crc_crc_prev[27] ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[4] <= (((((((((main_tx_crc_crc_prev[28] ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[5] <= (((((((((((((main_tx_crc_crc_prev[29] ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[6] <= (((((((((((main_tx_crc_crc_prev[30] ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[7] <= (((((((((main_tx_crc_crc_prev[31] ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[8] <= ((((((((main_tx_crc_crc_prev[0] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[9] <= ((((((((main_tx_crc_crc_prev[1] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[10] <= ((((((((main_tx_crc_crc_prev[2] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[11] <= ((((((((main_tx_crc_crc_prev[3] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[12] <= ((((((((((((main_tx_crc_crc_prev[4] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[13] <= ((((((((((((main_tx_crc_crc_prev[5] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[14] <= ((((((((((main_tx_crc_crc_prev[6] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[15] <= ((((((((main_tx_crc_crc_prev[7] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); + main_tx_crc_crc_next[16] <= ((((((main_tx_crc_crc_prev[8] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[17] <= ((((((main_tx_crc_crc_prev[9] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[18] <= ((((((main_tx_crc_crc_prev[10] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[19] <= ((((main_tx_crc_crc_prev[11] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); + main_tx_crc_crc_next[20] <= ((main_tx_crc_crc_prev[12] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]); + main_tx_crc_crc_next[21] <= ((main_tx_crc_crc_prev[13] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]); + main_tx_crc_crc_next[22] <= ((main_tx_crc_crc_prev[14] ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[23] <= ((((((main_tx_crc_crc_prev[15] ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[24] <= ((((((main_tx_crc_crc_prev[16] ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[25] <= ((((main_tx_crc_crc_prev[17] ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[26] <= ((((((((main_tx_crc_crc_prev[18] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[27] <= ((((((((main_tx_crc_crc_prev[19] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[28] <= ((((((main_tx_crc_crc_prev[20] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[29] <= ((((((main_tx_crc_crc_prev[21] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); + main_tx_crc_crc_next[30] <= ((((main_tx_crc_crc_prev[22] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]); + main_tx_crc_crc_next[31] <= ((main_tx_crc_crc_prev[23] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]); +end +always @(*) begin + builder_txdatapath_bufferizeendpoints_next_state <= 2'd0; + main_tx_crc_ce <= 1'd0; + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= 32'd0; + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd0; + main_tx_crc_is_ongoing0 <= 1'd0; + main_tx_crc_is_ongoing1 <= 1'd0; + main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= 1'd0; + main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd0; + main_tx_crc_reset <= 1'd0; + main_tx_crc_sink_ready <= 1'd0; + main_tx_crc_source_first <= 1'd0; + main_tx_crc_source_last <= 1'd0; + main_tx_crc_source_payload_data <= 8'd0; + main_tx_crc_source_payload_error <= 1'd0; + main_tx_crc_source_payload_last_be <= 1'd0; + main_tx_crc_source_valid <= 1'd0; + builder_txdatapath_bufferizeendpoints_next_state <= builder_txdatapath_bufferizeendpoints_state; + case (builder_txdatapath_bufferizeendpoints_state) + 1'd1: begin + main_tx_crc_ce <= (main_tx_crc_sink_valid & main_tx_crc_source_ready); + main_tx_crc_source_valid <= main_tx_crc_sink_valid; + main_tx_crc_sink_ready <= main_tx_crc_source_ready; + main_tx_crc_source_first <= main_tx_crc_sink_first; + main_tx_crc_source_last <= main_tx_crc_sink_last; + main_tx_crc_source_payload_data <= main_tx_crc_sink_payload_data; + main_tx_crc_source_payload_last_be <= main_tx_crc_sink_payload_last_be; + main_tx_crc_source_payload_error <= main_tx_crc_sink_payload_error; + main_tx_crc_source_last <= 1'd0; + main_tx_crc_source_payload_last_be <= 1'd0; + if (main_tx_crc_sink_last) begin + if (main_tx_crc_sink_payload_last_be) begin + main_tx_crc_source_payload_data <= builder_complexslicelowerer_slice_proxy[7:0]; + end + if ((1'd0 & (main_tx_crc_sink_payload_last_be <= 4'd15))) begin + main_tx_crc_source_last <= 1'd1; + main_tx_crc_source_payload_last_be <= (main_tx_crc_sink_payload_last_be <<< -3'd3); + end + end else begin + main_tx_crc_ce <= (main_tx_crc_sink_valid & main_tx_crc_source_ready); + end + if (((main_tx_crc_sink_valid & main_tx_crc_sink_last) & main_tx_crc_source_ready)) begin + if ((1'd0 & (main_tx_crc_sink_payload_last_be <= 4'd15))) begin + builder_txdatapath_bufferizeendpoints_next_state <= 1'd0; + end else begin + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= main_tx_crc_value; + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd1; + if (1'd0) begin + main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= (main_tx_crc_sink_payload_last_be >>> 3'd4); + main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + end else begin + main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= main_tx_crc_sink_payload_last_be; + main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + end + builder_txdatapath_bufferizeendpoints_next_state <= 2'd2; + end + end + end + 2'd2: begin + main_tx_crc_source_valid <= 1'd1; + case (main_tx_crc_cnt) + 1'd0: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[31:24]; + end + 1'd1: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[23:16]; + end + 2'd2: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[15:8]; + end + default: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[7:0]; + end + endcase + if (main_tx_crc_cnt_done) begin + main_tx_crc_source_last <= 1'd1; + if (main_tx_crc_source_ready) begin + builder_txdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + main_tx_crc_is_ongoing1 <= 1'd1; + end + default: begin + main_tx_crc_reset <= 1'd1; + main_tx_crc_sink_ready <= 1'd1; + if (main_tx_crc_sink_valid) begin + main_tx_crc_sink_ready <= 1'd0; + builder_txdatapath_bufferizeendpoints_next_state <= 1'd1; + end + main_tx_crc_is_ongoing0 <= 1'd1; + end + endcase +end +assign main_tx_crc_pipe_valid_sink_ready = ((~main_tx_crc_pipe_valid_source_valid) | main_tx_crc_pipe_valid_source_ready); +assign main_tx_crc_pipe_valid_sink_valid = main_tx_crc_sink_sink_valid; +assign main_tx_crc_sink_sink_ready = main_tx_crc_pipe_valid_sink_ready; +assign main_tx_crc_pipe_valid_sink_first = main_tx_crc_sink_sink_first; +assign main_tx_crc_pipe_valid_sink_last = main_tx_crc_sink_sink_last; +assign main_tx_crc_pipe_valid_sink_payload_data = main_tx_crc_sink_sink_payload_data; +assign main_tx_crc_pipe_valid_sink_payload_last_be = main_tx_crc_sink_sink_payload_last_be; +assign main_tx_crc_pipe_valid_sink_payload_error = main_tx_crc_sink_sink_payload_error; +assign main_tx_crc_source_source_valid = main_tx_crc_pipe_valid_source_valid; +assign main_tx_crc_pipe_valid_source_ready = main_tx_crc_source_source_ready; +assign main_tx_crc_source_source_first = main_tx_crc_pipe_valid_source_first; +assign main_tx_crc_source_source_last = main_tx_crc_pipe_valid_source_last; +assign main_tx_crc_source_source_payload_data = main_tx_crc_pipe_valid_source_payload_data; +assign main_tx_crc_source_source_payload_last_be = main_tx_crc_pipe_valid_source_payload_last_be; +assign main_tx_crc_source_source_payload_error = main_tx_crc_pipe_valid_source_payload_error; +assign main_tx_preamble_source_payload_last_be = main_tx_preamble_sink_payload_last_be; +always @(*) begin + builder_txdatapath_liteethmacpreambleinserter_next_state <= 2'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value <= 3'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd0; + main_tx_preamble_sink_ready <= 1'd0; + main_tx_preamble_source_first <= 1'd0; + main_tx_preamble_source_last <= 1'd0; + main_tx_preamble_source_payload_data <= 8'd0; + main_tx_preamble_source_payload_error <= 1'd0; + main_tx_preamble_source_valid <= 1'd0; + main_tx_preamble_source_payload_data <= main_tx_preamble_sink_payload_data; + builder_txdatapath_liteethmacpreambleinserter_next_state <= builder_txdatapath_liteethmacpreambleinserter_state; + case (builder_txdatapath_liteethmacpreambleinserter_state) + 1'd1: begin + main_tx_preamble_source_valid <= 1'd1; + case (main_tx_preamble_count) + 1'd0: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[7:0]; + end + 1'd1: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[15:8]; + end + 2'd2: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[23:16]; + end + 2'd3: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[31:24]; + end + 3'd4: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[39:32]; + end + 3'd5: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[47:40]; + end + 3'd6: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[55:48]; + end + default: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[63:56]; + end + endcase + if (main_tx_preamble_source_ready) begin + if ((main_tx_preamble_count == 3'd7)) begin + builder_txdatapath_liteethmacpreambleinserter_next_state <= 2'd2; + end else begin + main_tx_preamble_count_clockdomainsrenamer2_next_value <= (main_tx_preamble_count + 1'd1); + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + end + end + end + 2'd2: begin + main_tx_preamble_source_valid <= main_tx_preamble_sink_valid; + main_tx_preamble_sink_ready <= main_tx_preamble_source_ready; + main_tx_preamble_source_first <= main_tx_preamble_sink_first; + main_tx_preamble_source_last <= main_tx_preamble_sink_last; + main_tx_preamble_source_payload_error <= main_tx_preamble_sink_payload_error; + if (((main_tx_preamble_sink_valid & main_tx_preamble_sink_last) & main_tx_preamble_source_ready)) begin + builder_txdatapath_liteethmacpreambleinserter_next_state <= 1'd0; + end + end + default: begin + main_tx_preamble_sink_ready <= 1'd1; + main_tx_preamble_count_clockdomainsrenamer2_next_value <= 1'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + if (main_tx_preamble_sink_valid) begin + main_tx_preamble_sink_ready <= 1'd0; + builder_txdatapath_liteethmacpreambleinserter_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + builder_txdatapath_liteethmacgap_next_state <= 1'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value <= 4'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd0; + main_tx_gap_sink_ready <= 1'd0; + main_tx_gap_source_first <= 1'd0; + main_tx_gap_source_last <= 1'd0; + main_tx_gap_source_payload_data <= 8'd0; + main_tx_gap_source_payload_error <= 1'd0; + main_tx_gap_source_payload_last_be <= 1'd0; + main_tx_gap_source_valid <= 1'd0; + builder_txdatapath_liteethmacgap_next_state <= builder_txdatapath_liteethmacgap_state; + case (builder_txdatapath_liteethmacgap_state) + 1'd1: begin + main_tx_gap_counter_clockdomainsrenamer3_next_value <= (main_tx_gap_counter + 1'd1); + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + if ((main_tx_gap_counter == 4'd11)) begin + builder_txdatapath_liteethmacgap_next_state <= 1'd0; + end + end + default: begin + main_tx_gap_counter_clockdomainsrenamer3_next_value <= 1'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + main_tx_gap_source_valid <= main_tx_gap_sink_valid; + main_tx_gap_sink_ready <= main_tx_gap_source_ready; + main_tx_gap_source_first <= main_tx_gap_sink_first; + main_tx_gap_source_last <= main_tx_gap_sink_last; + main_tx_gap_source_payload_data <= main_tx_gap_sink_payload_data; + main_tx_gap_source_payload_last_be <= main_tx_gap_sink_payload_last_be; + main_tx_gap_source_payload_error <= main_tx_gap_sink_payload_error; + if (((main_tx_gap_sink_valid & main_tx_gap_sink_last) & main_tx_gap_sink_ready)) begin + builder_txdatapath_liteethmacgap_next_state <= 1'd1; + end + end + endcase +end +assign main_tx_cdc_sink_sink_valid = main_sink_valid; +assign main_sink_ready = main_tx_cdc_sink_sink_ready; +assign main_tx_cdc_sink_sink_first = main_sink_first; +assign main_tx_cdc_sink_sink_last = main_sink_last; +assign main_tx_cdc_sink_sink_payload_data = main_sink_payload_data; +assign main_tx_cdc_sink_sink_payload_last_be = main_sink_payload_last_be; +assign main_tx_cdc_sink_sink_payload_error = main_sink_payload_error; +assign main_tx_converter_sink_valid = main_tx_cdc_source_source_valid; +assign main_tx_cdc_source_source_ready = main_tx_converter_sink_ready; +assign main_tx_converter_sink_first = main_tx_cdc_source_source_first; +assign main_tx_converter_sink_last = main_tx_cdc_source_source_last; +assign main_tx_converter_sink_payload_data = main_tx_cdc_source_source_payload_data; +assign main_tx_converter_sink_payload_last_be = main_tx_cdc_source_source_payload_last_be; +assign main_tx_converter_sink_payload_error = main_tx_cdc_source_source_payload_error; +assign main_tx_last_be_sink_valid = main_tx_converter_source_valid; +assign main_tx_converter_source_ready = main_tx_last_be_sink_ready; +assign main_tx_last_be_sink_first = main_tx_converter_source_first; +assign main_tx_last_be_sink_last = main_tx_converter_source_last; +assign main_tx_last_be_sink_payload_data = main_tx_converter_source_payload_data; +assign main_tx_last_be_sink_payload_last_be = main_tx_converter_source_payload_last_be; +assign main_tx_last_be_sink_payload_error = main_tx_converter_source_payload_error; +assign main_tx_padding_sink_valid = main_tx_last_be_source_valid; +assign main_tx_last_be_source_ready = main_tx_padding_sink_ready; +assign main_tx_padding_sink_first = main_tx_last_be_source_first; +assign main_tx_padding_sink_last = main_tx_last_be_source_last; +assign main_tx_padding_sink_payload_data = main_tx_last_be_source_payload_data; +assign main_tx_padding_sink_payload_last_be = main_tx_last_be_source_payload_last_be; +assign main_tx_padding_sink_payload_error = main_tx_last_be_source_payload_error; +assign main_tx_crc_sink_sink_valid = main_tx_padding_source_valid; +assign main_tx_padding_source_ready = main_tx_crc_sink_sink_ready; +assign main_tx_crc_sink_sink_first = main_tx_padding_source_first; +assign main_tx_crc_sink_sink_last = main_tx_padding_source_last; +assign main_tx_crc_sink_sink_payload_data = main_tx_padding_source_payload_data; +assign main_tx_crc_sink_sink_payload_last_be = main_tx_padding_source_payload_last_be; +assign main_tx_crc_sink_sink_payload_error = main_tx_padding_source_payload_error; +assign main_tx_preamble_sink_valid = main_tx_crc_source_valid; +assign main_tx_crc_source_ready = main_tx_preamble_sink_ready; +assign main_tx_preamble_sink_first = main_tx_crc_source_first; +assign main_tx_preamble_sink_last = main_tx_crc_source_last; +assign main_tx_preamble_sink_payload_data = main_tx_crc_source_payload_data; +assign main_tx_preamble_sink_payload_last_be = main_tx_crc_source_payload_last_be; +assign main_tx_preamble_sink_payload_error = main_tx_crc_source_payload_error; +assign main_tx_gap_sink_valid = main_tx_preamble_source_valid; +assign main_tx_preamble_source_ready = main_tx_gap_sink_ready; +assign main_tx_gap_sink_first = main_tx_preamble_source_first; +assign main_tx_gap_sink_last = main_tx_preamble_source_last; +assign main_tx_gap_sink_payload_data = main_tx_preamble_source_payload_data; +assign main_tx_gap_sink_payload_last_be = main_tx_preamble_source_payload_last_be; +assign main_tx_gap_sink_payload_error = main_tx_preamble_source_payload_error; +assign main_maccore_liteethphymiitx_sink_valid = main_tx_gap_source_valid; +assign main_tx_gap_source_ready = main_maccore_liteethphymiitx_sink_ready; +assign main_maccore_liteethphymiitx_sink_first = main_tx_gap_source_first; +assign main_maccore_liteethphymiitx_sink_last = main_tx_gap_source_last; +assign main_maccore_liteethphymiitx_sink_payload_data = main_tx_gap_source_payload_data; +assign main_maccore_liteethphymiitx_sink_payload_last_be = main_tx_gap_source_payload_last_be; +assign main_maccore_liteethphymiitx_sink_payload_error = main_tx_gap_source_payload_error; +assign main_pulsesynchronizer0_i = main_rx_preamble_error; +assign main_pulsesynchronizer1_i = main_liteethmaccrc32checker_error; +assign main_rx_preamble_source_payload_data = main_rx_preamble_sink_payload_data; +assign main_rx_preamble_source_payload_last_be = main_rx_preamble_sink_payload_last_be; +always @(*) begin + builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + main_rx_preamble_error <= 1'd0; + main_rx_preamble_sink_ready <= 1'd0; + main_rx_preamble_source_first <= 1'd0; + main_rx_preamble_source_last <= 1'd0; + main_rx_preamble_source_payload_error <= 1'd0; + main_rx_preamble_source_valid <= 1'd0; + builder_rxdatapath_liteethmacpreamblechecker_next_state <= builder_rxdatapath_liteethmacpreamblechecker_state; + case (builder_rxdatapath_liteethmacpreamblechecker_state) + 1'd1: begin + main_rx_preamble_source_valid <= main_rx_preamble_sink_valid; + main_rx_preamble_sink_ready <= main_rx_preamble_source_ready; + main_rx_preamble_source_first <= main_rx_preamble_sink_first; + main_rx_preamble_source_last <= main_rx_preamble_sink_last; + main_rx_preamble_source_payload_error <= main_rx_preamble_sink_payload_error; + if (((main_rx_preamble_source_valid & main_rx_preamble_source_last) & main_rx_preamble_source_ready)) begin + builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + end + end + default: begin + main_rx_preamble_sink_ready <= 1'd1; + if (((main_rx_preamble_sink_valid & (~main_rx_preamble_sink_last)) & (main_rx_preamble_sink_payload_data == main_rx_preamble_preamble[63:56]))) begin + builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd1; + end + if ((main_rx_preamble_sink_valid & main_rx_preamble_sink_last)) begin + main_rx_preamble_error <= 1'd1; + end + end + endcase +end +assign main_pulsesynchronizer0_o = (main_pulsesynchronizer0_toggle_o ^ main_pulsesynchronizer0_toggle_o_r); assign main_liteethmaccrc32checker_fifo_full = (main_liteethmaccrc32checker_syncfifo_level == 3'd4); assign main_liteethmaccrc32checker_fifo_in = (main_liteethmaccrc32checker_sink_sink_valid & ((~main_liteethmaccrc32checker_fifo_full) | main_liteethmaccrc32checker_fifo_out)); assign main_liteethmaccrc32checker_fifo_out = (main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready); @@ -1413,72 +2037,70 @@ assign main_liteethmaccrc32checker_syncfifo_sink_payload_data = main_liteethmacc assign main_liteethmaccrc32checker_syncfifo_sink_payload_last_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; assign main_liteethmaccrc32checker_syncfifo_sink_payload_error = main_liteethmaccrc32checker_sink_sink_payload_error; always @(*) begin - main_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; - main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_sink_sink_valid; - main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_fifo_in; -end -always @(*) begin - main_liteethmaccrc32checker_sink_sink_ready <= 1'd0; - main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_syncfifo_sink_ready; - main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_fifo_in; + main_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; + main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_sink_sink_valid; + main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_fifo_in; end -assign main_liteethmaccrc32checker_source_source_valid = (main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_fifo_full); -assign main_liteethmaccrc32checker_source_source_last = main_liteethmaccrc32checker_sink_sink_last; -assign main_liteethmaccrc32checker_syncfifo_source_ready = main_liteethmaccrc32checker_fifo_out; -assign main_liteethmaccrc32checker_source_source_payload_data = main_liteethmaccrc32checker_syncfifo_source_payload_data; -assign main_liteethmaccrc32checker_source_source_payload_last_be = main_liteethmaccrc32checker_syncfifo_source_payload_last_be; always @(*) begin - main_liteethmaccrc32checker_source_source_payload_error <= 1'd0; - main_liteethmaccrc32checker_source_source_payload_error <= main_liteethmaccrc32checker_syncfifo_source_payload_error; - main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_sink_sink_payload_error | main_liteethmaccrc32checker_crc_error); + main_liteethmaccrc32checker_sink_sink_ready <= 1'd0; + main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_syncfifo_sink_ready; + main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_fifo_in; end -assign main_liteethmaccrc32checker_error = ((main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_last) & main_liteethmaccrc32checker_crc_error); assign main_liteethmaccrc32checker_crc_data0 = main_liteethmaccrc32checker_sink_sink_payload_data; -assign main_liteethmaccrc32checker_sink_sink_valid = main_crc32_checker_source_valid; -assign main_crc32_checker_source_ready = main_liteethmaccrc32checker_sink_sink_ready; -assign main_liteethmaccrc32checker_sink_sink_first = main_crc32_checker_source_first; -assign main_liteethmaccrc32checker_sink_sink_last = main_crc32_checker_source_last; -assign main_liteethmaccrc32checker_sink_sink_payload_data = main_crc32_checker_source_payload_data; -assign main_liteethmaccrc32checker_sink_sink_payload_last_be = main_crc32_checker_source_payload_last_be; -assign main_liteethmaccrc32checker_sink_sink_payload_error = main_crc32_checker_source_payload_error; -assign main_liteethmaccrc32checker_crc_data1 = main_liteethmaccrc32checker_crc_data0; -assign main_liteethmaccrc32checker_crc_last = main_liteethmaccrc32checker_crc_reg; -assign main_liteethmaccrc32checker_crc_value = (~{main_liteethmaccrc32checker_crc_reg[0], main_liteethmaccrc32checker_crc_reg[1], main_liteethmaccrc32checker_crc_reg[2], main_liteethmaccrc32checker_crc_reg[3], main_liteethmaccrc32checker_crc_reg[4], main_liteethmaccrc32checker_crc_reg[5], main_liteethmaccrc32checker_crc_reg[6], main_liteethmaccrc32checker_crc_reg[7], main_liteethmaccrc32checker_crc_reg[8], main_liteethmaccrc32checker_crc_reg[9], main_liteethmaccrc32checker_crc_reg[10], main_liteethmaccrc32checker_crc_reg[11], main_liteethmaccrc32checker_crc_reg[12], main_liteethmaccrc32checker_crc_reg[13], main_liteethmaccrc32checker_crc_reg[14], main_liteethmaccrc32checker_crc_reg[15], main_liteethmaccrc32checker_crc_reg[16], main_liteethmaccrc32checker_crc_reg[17], main_liteethmaccrc32checker_crc_reg[18], main_liteethmaccrc32checker_crc_reg[19], main_liteethmaccrc32checker_crc_reg[20], main_liteethmaccrc32checker_crc_reg[21], main_liteethmaccrc32checker_crc_reg[22], main_liteethmaccrc32checker_crc_reg[23], main_liteethmaccrc32checker_crc_reg[24], main_liteethmaccrc32checker_crc_reg[25], main_liteethmaccrc32checker_crc_reg[26], main_liteethmaccrc32checker_crc_reg[27], main_liteethmaccrc32checker_crc_reg[28], main_liteethmaccrc32checker_crc_reg[29], main_liteethmaccrc32checker_crc_reg[30], main_liteethmaccrc32checker_crc_reg[31]}); -assign main_liteethmaccrc32checker_crc_error = (main_liteethmaccrc32checker_crc_next != 32'd3338984827); -always @(*) begin - main_liteethmaccrc32checker_crc_next <= 32'd0; - main_liteethmaccrc32checker_crc_next[0] <= (((main_liteethmaccrc32checker_crc_last[24] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[1] <= (((((((main_liteethmaccrc32checker_crc_last[25] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[2] <= (((((((((main_liteethmaccrc32checker_crc_last[26] ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[3] <= (((((((main_liteethmaccrc32checker_crc_last[27] ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[4] <= (((((((((main_liteethmaccrc32checker_crc_last[28] ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[5] <= (((((((((((((main_liteethmaccrc32checker_crc_last[29] ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[6] <= (((((((((((main_liteethmaccrc32checker_crc_last[30] ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[7] <= (((((((((main_liteethmaccrc32checker_crc_last[31] ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[8] <= ((((((((main_liteethmaccrc32checker_crc_last[0] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[9] <= ((((((((main_liteethmaccrc32checker_crc_last[1] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[10] <= ((((((((main_liteethmaccrc32checker_crc_last[2] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[11] <= ((((((((main_liteethmaccrc32checker_crc_last[3] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[12] <= ((((((((((((main_liteethmaccrc32checker_crc_last[4] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[13] <= ((((((((((((main_liteethmaccrc32checker_crc_last[5] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[14] <= ((((((((((main_liteethmaccrc32checker_crc_last[6] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_next[15] <= ((((((((main_liteethmaccrc32checker_crc_last[7] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); - main_liteethmaccrc32checker_crc_next[16] <= ((((((main_liteethmaccrc32checker_crc_last[8] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[17] <= ((((((main_liteethmaccrc32checker_crc_last[9] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[18] <= ((((((main_liteethmaccrc32checker_crc_last[10] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_next[19] <= ((((main_liteethmaccrc32checker_crc_last[11] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); - main_liteethmaccrc32checker_crc_next[20] <= ((main_liteethmaccrc32checker_crc_last[12] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); - main_liteethmaccrc32checker_crc_next[21] <= ((main_liteethmaccrc32checker_crc_last[13] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); - main_liteethmaccrc32checker_crc_next[22] <= ((main_liteethmaccrc32checker_crc_last[14] ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[23] <= ((((((main_liteethmaccrc32checker_crc_last[15] ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[24] <= ((((((main_liteethmaccrc32checker_crc_last[16] ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[25] <= ((((main_liteethmaccrc32checker_crc_last[17] ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_next[26] <= ((((((((main_liteethmaccrc32checker_crc_last[18] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[27] <= ((((((((main_liteethmaccrc32checker_crc_last[19] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[28] <= ((((((main_liteethmaccrc32checker_crc_last[20] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_next[29] <= ((((((main_liteethmaccrc32checker_crc_last[21] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); - main_liteethmaccrc32checker_crc_next[30] <= ((((main_liteethmaccrc32checker_crc_last[22] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); - main_liteethmaccrc32checker_crc_next[31] <= ((main_liteethmaccrc32checker_crc_last[23] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); +assign main_liteethmaccrc32checker_crc_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; +assign main_liteethmaccrc32checker_source_source_first = main_liteethmaccrc32checker_syncfifo_source_first; +assign main_liteethmaccrc32checker_source_source_payload_data = main_liteethmaccrc32checker_syncfifo_source_payload_data; +assign main_liteethmaccrc32checker_sink_sink_valid = main_bufferizeendpoints_source_source_valid; +assign main_bufferizeendpoints_source_source_ready = main_liteethmaccrc32checker_sink_sink_ready; +assign main_liteethmaccrc32checker_sink_sink_first = main_bufferizeendpoints_source_source_first; +assign main_liteethmaccrc32checker_sink_sink_last = main_bufferizeendpoints_source_source_last; +assign main_liteethmaccrc32checker_sink_sink_payload_data = main_bufferizeendpoints_source_source_payload_data; +assign main_liteethmaccrc32checker_sink_sink_payload_last_be = main_bufferizeendpoints_source_source_payload_last_be; +assign main_liteethmaccrc32checker_sink_sink_payload_error = main_bufferizeendpoints_source_source_payload_error; +assign main_liteethmaccrc32checker_crc_data1 = main_liteethmaccrc32checker_crc_data0[7:0]; +assign main_liteethmaccrc32checker_crc_crc_prev = main_liteethmaccrc32checker_crc_reg; +always @(*) begin + main_liteethmaccrc32checker_crc_error0 <= 1'd0; + main_liteethmaccrc32checker_crc_value <= 32'd0; + if (main_liteethmaccrc32checker_crc_be) begin + main_liteethmaccrc32checker_crc_value <= {builder_t_slice_proxy63[0], builder_t_slice_proxy62[1], builder_t_slice_proxy61[2], builder_t_slice_proxy60[3], builder_t_slice_proxy59[4], builder_t_slice_proxy58[5], builder_t_slice_proxy57[6], builder_t_slice_proxy56[7], builder_t_slice_proxy55[8], builder_t_slice_proxy54[9], builder_t_slice_proxy53[10], builder_t_slice_proxy52[11], builder_t_slice_proxy51[12], builder_t_slice_proxy50[13], builder_t_slice_proxy49[14], builder_t_slice_proxy48[15], builder_t_slice_proxy47[16], builder_t_slice_proxy46[17], builder_t_slice_proxy45[18], builder_t_slice_proxy44[19], builder_t_slice_proxy43[20], builder_t_slice_proxy42[21], builder_t_slice_proxy41[22], builder_t_slice_proxy40[23], builder_t_slice_proxy39[24], builder_t_slice_proxy38[25], builder_t_slice_proxy37[26], builder_t_slice_proxy36[27], builder_t_slice_proxy35[28], builder_t_slice_proxy34[29], builder_t_slice_proxy33[30], builder_t_slice_proxy32[31]}; + main_liteethmaccrc32checker_crc_error0 <= (main_liteethmaccrc32checker_crc_crc_next != 32'd3338984827); + end +end +always @(*) begin + main_liteethmaccrc32checker_crc_crc_next <= 32'd0; + main_liteethmaccrc32checker_crc_crc_next[0] <= (((main_liteethmaccrc32checker_crc_crc_prev[24] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[1] <= (((((((main_liteethmaccrc32checker_crc_crc_prev[25] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[2] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[26] ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[3] <= (((((((main_liteethmaccrc32checker_crc_crc_prev[27] ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[4] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[28] ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[5] <= (((((((((((((main_liteethmaccrc32checker_crc_crc_prev[29] ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[6] <= (((((((((((main_liteethmaccrc32checker_crc_crc_prev[30] ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[7] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[31] ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[8] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[0] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[9] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[1] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[10] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[2] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[11] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[3] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[12] <= ((((((((((((main_liteethmaccrc32checker_crc_crc_prev[4] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[13] <= ((((((((((((main_liteethmaccrc32checker_crc_crc_prev[5] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[14] <= ((((((((((main_liteethmaccrc32checker_crc_crc_prev[6] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[15] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[7] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); + main_liteethmaccrc32checker_crc_crc_next[16] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[8] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[17] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[9] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[18] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[10] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[19] <= ((((main_liteethmaccrc32checker_crc_crc_prev[11] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); + main_liteethmaccrc32checker_crc_crc_next[20] <= ((main_liteethmaccrc32checker_crc_crc_prev[12] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); + main_liteethmaccrc32checker_crc_crc_next[21] <= ((main_liteethmaccrc32checker_crc_crc_prev[13] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); + main_liteethmaccrc32checker_crc_crc_next[22] <= ((main_liteethmaccrc32checker_crc_crc_prev[14] ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[23] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[15] ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[24] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[16] ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[25] <= ((((main_liteethmaccrc32checker_crc_crc_prev[17] ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[26] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[18] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[27] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[19] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[28] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[20] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[29] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[21] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); + main_liteethmaccrc32checker_crc_crc_next[30] <= ((((main_liteethmaccrc32checker_crc_crc_prev[22] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); + main_liteethmaccrc32checker_crc_crc_next[31] <= ((main_liteethmaccrc32checker_crc_crc_prev[23] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); end assign main_liteethmaccrc32checker_syncfifo_syncfifo_din = {main_liteethmaccrc32checker_syncfifo_fifo_in_last, main_liteethmaccrc32checker_syncfifo_fifo_in_first, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data}; assign {main_liteethmaccrc32checker_syncfifo_fifo_out_last, main_liteethmaccrc32checker_syncfifo_fifo_out_first, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = main_liteethmaccrc32checker_syncfifo_syncfifo_dout; @@ -1497,12 +2119,12 @@ assign main_liteethmaccrc32checker_syncfifo_source_payload_last_be = main_liteet assign main_liteethmaccrc32checker_syncfifo_source_payload_error = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; assign main_liteethmaccrc32checker_syncfifo_syncfifo_re = main_liteethmaccrc32checker_syncfifo_source_ready; always @(*) begin - main_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; - if (main_liteethmaccrc32checker_syncfifo_replace) begin - main_liteethmaccrc32checker_syncfifo_wrport_adr <= (main_liteethmaccrc32checker_syncfifo_produce - 1'd1); - end else begin - main_liteethmaccrc32checker_syncfifo_wrport_adr <= main_liteethmaccrc32checker_syncfifo_produce; - end + main_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; + if (main_liteethmaccrc32checker_syncfifo_replace) begin + main_liteethmaccrc32checker_syncfifo_wrport_adr <= (main_liteethmaccrc32checker_syncfifo_produce - 1'd1); + end else begin + main_liteethmaccrc32checker_syncfifo_wrport_adr <= main_liteethmaccrc32checker_syncfifo_produce; + end end assign main_liteethmaccrc32checker_syncfifo_wrport_dat_w = main_liteethmaccrc32checker_syncfifo_syncfifo_din; assign main_liteethmaccrc32checker_syncfifo_wrport_we = (main_liteethmaccrc32checker_syncfifo_syncfifo_we & (main_liteethmaccrc32checker_syncfifo_syncfifo_writable | main_liteethmaccrc32checker_syncfifo_replace)); @@ -1512,126 +2134,99 @@ assign main_liteethmaccrc32checker_syncfifo_syncfifo_dout = main_liteethmaccrc32 assign main_liteethmaccrc32checker_syncfifo_syncfifo_writable = (main_liteethmaccrc32checker_syncfifo_level != 3'd5); assign main_liteethmaccrc32checker_syncfifo_syncfifo_readable = (main_liteethmaccrc32checker_syncfifo_level != 1'd0); always @(*) begin - main_liteethmaccrc32checker_fifo_reset <= 1'd0; - builder_liteethmaccrc32checker_next_state <= 2'd0; - main_liteethmaccrc32checker_crc_ce <= 1'd0; - main_liteethmaccrc32checker_crc_reset <= 1'd0; - builder_liteethmaccrc32checker_next_state <= builder_liteethmaccrc32checker_state; - case (builder_liteethmaccrc32checker_state) - 1'd1: begin - if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin - main_liteethmaccrc32checker_crc_ce <= 1'd1; - builder_liteethmaccrc32checker_next_state <= 2'd2; - end - end - 2'd2: begin - if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin - main_liteethmaccrc32checker_crc_ce <= 1'd1; - if (main_liteethmaccrc32checker_sink_sink_last) begin - builder_liteethmaccrc32checker_next_state <= 1'd0; - end - end - end - default: begin - main_liteethmaccrc32checker_crc_reset <= 1'd1; - main_liteethmaccrc32checker_fifo_reset <= 1'd1; - builder_liteethmaccrc32checker_next_state <= 1'd1; - end - endcase -end -assign main_crc32_checker_sink_ready = ((~main_crc32_checker_source_valid) | main_crc32_checker_source_ready); -assign main_ps_preamble_error_o = (main_ps_preamble_error_toggle_o ^ main_ps_preamble_error_toggle_o_r); -assign main_ps_crc_error_o = (main_ps_crc_error_toggle_o ^ main_ps_crc_error_toggle_o_r); -assign main_padding_inserter_counter_done = (main_padding_inserter_counter >= 6'd59); -always @(*) begin - main_padding_inserter_source_valid <= 1'd0; - main_padding_inserter_source_first <= 1'd0; - main_padding_inserter_source_last <= 1'd0; - main_padding_inserter_source_payload_data <= 8'd0; - main_padding_inserter_source_payload_last_be <= 1'd0; - main_padding_inserter_source_payload_error <= 1'd0; - builder_liteethmacpaddinginserter_next_state <= 1'd0; - main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 16'd0; - main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd0; - main_padding_inserter_sink_ready <= 1'd0; - builder_liteethmacpaddinginserter_next_state <= builder_liteethmacpaddinginserter_state; - case (builder_liteethmacpaddinginserter_state) - 1'd1: begin - main_padding_inserter_source_valid <= 1'd1; - main_padding_inserter_source_last <= main_padding_inserter_counter_done; - main_padding_inserter_source_payload_data <= 1'd0; - if ((main_padding_inserter_source_valid & main_padding_inserter_source_ready)) begin - main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= (main_padding_inserter_counter + 1'd1); - main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; - if (main_padding_inserter_counter_done) begin - main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0; - main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; - builder_liteethmacpaddinginserter_next_state <= 1'd0; - end - end - end - default: begin - main_padding_inserter_source_valid <= main_padding_inserter_sink_valid; - main_padding_inserter_sink_ready <= main_padding_inserter_source_ready; - main_padding_inserter_source_first <= main_padding_inserter_sink_first; - main_padding_inserter_source_last <= main_padding_inserter_sink_last; - main_padding_inserter_source_payload_data <= main_padding_inserter_sink_payload_data; - main_padding_inserter_source_payload_last_be <= main_padding_inserter_sink_payload_last_be; - main_padding_inserter_source_payload_error <= main_padding_inserter_sink_payload_error; - if ((main_padding_inserter_source_valid & main_padding_inserter_source_ready)) begin - main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= (main_padding_inserter_counter + 1'd1); - main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; - if (main_padding_inserter_sink_last) begin - if ((~main_padding_inserter_counter_done)) begin - main_padding_inserter_source_last <= 1'd0; - builder_liteethmacpaddinginserter_next_state <= 1'd1; - end else begin - main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0; - main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; - end - end - end - end - endcase -end -assign main_padding_checker_source_valid = main_padding_checker_sink_valid; -assign main_padding_checker_sink_ready = main_padding_checker_source_ready; -assign main_padding_checker_source_first = main_padding_checker_sink_first; -assign main_padding_checker_source_last = main_padding_checker_sink_last; -assign main_padding_checker_source_payload_data = main_padding_checker_sink_payload_data; -assign main_padding_checker_source_payload_last_be = main_padding_checker_sink_payload_last_be; -assign main_padding_checker_source_payload_error = main_padding_checker_sink_payload_error; -always @(*) begin - main_tx_last_be_source_valid <= 1'd0; - main_tx_last_be_sink_ready <= 1'd0; - main_tx_last_be_source_first <= 1'd0; - main_tx_last_be_source_last <= 1'd0; - main_tx_last_be_source_payload_data <= 8'd0; - main_tx_last_be_source_payload_error <= 1'd0; - builder_liteethmactxlastbe_next_state <= 1'd0; - builder_liteethmactxlastbe_next_state <= builder_liteethmactxlastbe_state; - case (builder_liteethmactxlastbe_state) - 1'd1: begin - main_tx_last_be_sink_ready <= 1'd1; - if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_last)) begin - builder_liteethmactxlastbe_next_state <= 1'd0; - end - end - default: begin - main_tx_last_be_source_valid <= main_tx_last_be_sink_valid; - main_tx_last_be_sink_ready <= main_tx_last_be_source_ready; - main_tx_last_be_source_first <= main_tx_last_be_sink_first; - main_tx_last_be_source_payload_data <= main_tx_last_be_sink_payload_data; - main_tx_last_be_source_payload_error <= main_tx_last_be_sink_payload_error; - main_tx_last_be_source_last <= main_tx_last_be_sink_payload_last_be; - if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_ready)) begin - if ((main_tx_last_be_sink_payload_last_be & (~main_tx_last_be_sink_last))) begin - builder_liteethmactxlastbe_next_state <= 1'd1; - end - end - end - endcase -end + builder_rxdatapath_bufferizeendpoints_next_state <= 2'd0; + main_liteethmaccrc32checker_crc_ce <= 1'd0; + main_liteethmaccrc32checker_crc_error1_next_value1 <= 1'd0; + main_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd0; + main_liteethmaccrc32checker_crc_reset <= 1'd0; + main_liteethmaccrc32checker_error <= 1'd0; + main_liteethmaccrc32checker_fifo_reset <= 1'd0; + main_liteethmaccrc32checker_last_be_next_value0 <= 1'd0; + main_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd0; + main_liteethmaccrc32checker_source_source_last <= 1'd0; + main_liteethmaccrc32checker_source_source_payload_error <= 1'd0; + main_liteethmaccrc32checker_source_source_payload_last_be <= 1'd0; + main_liteethmaccrc32checker_source_source_valid <= 1'd0; + main_liteethmaccrc32checker_syncfifo_source_ready <= 1'd0; + main_liteethmaccrc32checker_source_source_payload_error <= main_liteethmaccrc32checker_syncfifo_source_payload_error; + builder_rxdatapath_bufferizeendpoints_next_state <= builder_rxdatapath_bufferizeendpoints_state; + case (builder_rxdatapath_bufferizeendpoints_state) + 1'd1: begin + if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin + main_liteethmaccrc32checker_crc_ce <= 1'd1; + builder_rxdatapath_bufferizeendpoints_next_state <= 2'd2; + end + end + 2'd2: begin + main_liteethmaccrc32checker_syncfifo_source_ready <= main_liteethmaccrc32checker_fifo_out; + main_liteethmaccrc32checker_source_source_valid <= (main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_fifo_full); + if (1'd1) begin + main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_sink_sink_last; + main_liteethmaccrc32checker_source_source_payload_last_be <= main_liteethmaccrc32checker_sink_sink_payload_last_be; + end else begin + if ((main_liteethmaccrc32checker_sink_sink_payload_last_be & 4'd15)) begin + main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_sink_sink_last; + main_liteethmaccrc32checker_source_source_payload_last_be <= (main_liteethmaccrc32checker_sink_sink_payload_last_be <<< -3'd3); + end else begin + main_liteethmaccrc32checker_last_be_next_value0 <= (main_liteethmaccrc32checker_sink_sink_payload_last_be >>> 3'd4); + main_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd1; + main_liteethmaccrc32checker_crc_error1_next_value1 <= main_liteethmaccrc32checker_crc_error0; + main_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd1; + end + end + main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_sink_sink_payload_error | {1{(main_liteethmaccrc32checker_crc_error0 & main_liteethmaccrc32checker_sink_sink_last)}}); + main_liteethmaccrc32checker_error <= ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_last) & main_liteethmaccrc32checker_crc_error0); + if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin + main_liteethmaccrc32checker_crc_ce <= 1'd1; + if ((main_liteethmaccrc32checker_sink_sink_last & (main_liteethmaccrc32checker_sink_sink_payload_last_be > 4'd15))) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 2'd3; + end else begin + if (main_liteethmaccrc32checker_sink_sink_last) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + end + end + 2'd3: begin + main_liteethmaccrc32checker_source_source_valid <= main_liteethmaccrc32checker_syncfifo_source_valid; + main_liteethmaccrc32checker_syncfifo_source_ready <= main_liteethmaccrc32checker_source_source_ready; + main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_syncfifo_source_last; + main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_syncfifo_source_payload_error | {1{main_liteethmaccrc32checker_crc_error1}}); + main_liteethmaccrc32checker_source_source_payload_last_be <= main_liteethmaccrc32checker_last_be; + if ((main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready)) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + default: begin + main_liteethmaccrc32checker_crc_reset <= 1'd1; + main_liteethmaccrc32checker_fifo_reset <= 1'd1; + builder_rxdatapath_bufferizeendpoints_next_state <= 1'd1; + end + endcase +end +assign main_bufferizeendpoints_pipe_valid_sink_ready = ((~main_bufferizeendpoints_pipe_valid_source_valid) | main_bufferizeendpoints_pipe_valid_source_ready); +assign main_bufferizeendpoints_pipe_valid_sink_valid = main_bufferizeendpoints_sink_sink_valid; +assign main_bufferizeendpoints_sink_sink_ready = main_bufferizeendpoints_pipe_valid_sink_ready; +assign main_bufferizeendpoints_pipe_valid_sink_first = main_bufferizeendpoints_sink_sink_first; +assign main_bufferizeendpoints_pipe_valid_sink_last = main_bufferizeendpoints_sink_sink_last; +assign main_bufferizeendpoints_pipe_valid_sink_payload_data = main_bufferizeendpoints_sink_sink_payload_data; +assign main_bufferizeendpoints_pipe_valid_sink_payload_last_be = main_bufferizeendpoints_sink_sink_payload_last_be; +assign main_bufferizeendpoints_pipe_valid_sink_payload_error = main_bufferizeendpoints_sink_sink_payload_error; +assign main_bufferizeendpoints_source_source_valid = main_bufferizeendpoints_pipe_valid_source_valid; +assign main_bufferizeendpoints_pipe_valid_source_ready = main_bufferizeendpoints_source_source_ready; +assign main_bufferizeendpoints_source_source_first = main_bufferizeendpoints_pipe_valid_source_first; +assign main_bufferizeendpoints_source_source_last = main_bufferizeendpoints_pipe_valid_source_last; +assign main_bufferizeendpoints_source_source_payload_data = main_bufferizeendpoints_pipe_valid_source_payload_data; +assign main_bufferizeendpoints_source_source_payload_last_be = main_bufferizeendpoints_pipe_valid_source_payload_last_be; +assign main_bufferizeendpoints_source_source_payload_error = main_bufferizeendpoints_pipe_valid_source_payload_error; +assign main_pulsesynchronizer1_o = (main_pulsesynchronizer1_toggle_o ^ main_pulsesynchronizer1_toggle_o_r); +assign main_rx_padding_source_valid = main_rx_padding_sink_valid; +assign main_rx_padding_sink_ready = main_rx_padding_source_ready; +assign main_rx_padding_source_first = main_rx_padding_sink_first; +assign main_rx_padding_source_last = main_rx_padding_sink_last; +assign main_rx_padding_source_payload_data = main_rx_padding_sink_payload_data; +assign main_rx_padding_source_payload_last_be = main_rx_padding_sink_payload_last_be; +assign main_rx_padding_source_payload_error = main_rx_padding_sink_payload_error; assign main_rx_last_be_source_valid = main_rx_last_be_sink_valid; assign main_rx_last_be_sink_ready = main_rx_last_be_source_ready; assign main_rx_last_be_source_first = main_rx_last_be_sink_first; @@ -1639,63 +2234,12 @@ assign main_rx_last_be_source_last = main_rx_last_be_sink_last; assign main_rx_last_be_source_payload_data = main_rx_last_be_sink_payload_data; assign main_rx_last_be_source_payload_error = main_rx_last_be_sink_payload_error; always @(*) begin - main_rx_last_be_source_payload_last_be <= 1'd0; - main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_payload_last_be; - main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_last; + main_rx_last_be_source_payload_last_be <= 1'd0; + main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_payload_last_be; + if (1'd1) begin + main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_last; + end end -assign main_tx_converter_converter_sink_valid = main_tx_converter_sink_valid; -assign main_tx_converter_converter_sink_first = main_tx_converter_sink_first; -assign main_tx_converter_converter_sink_last = main_tx_converter_sink_last; -assign main_tx_converter_sink_ready = main_tx_converter_converter_sink_ready; -always @(*) begin - main_tx_converter_converter_sink_payload_data <= 40'd0; - main_tx_converter_converter_sink_payload_data[7:0] <= main_tx_converter_sink_payload_data[7:0]; - main_tx_converter_converter_sink_payload_data[8] <= main_tx_converter_sink_payload_last_be[0]; - main_tx_converter_converter_sink_payload_data[9] <= main_tx_converter_sink_payload_error[0]; - main_tx_converter_converter_sink_payload_data[17:10] <= main_tx_converter_sink_payload_data[15:8]; - main_tx_converter_converter_sink_payload_data[18] <= main_tx_converter_sink_payload_last_be[1]; - main_tx_converter_converter_sink_payload_data[19] <= main_tx_converter_sink_payload_error[1]; - main_tx_converter_converter_sink_payload_data[27:20] <= main_tx_converter_sink_payload_data[23:16]; - main_tx_converter_converter_sink_payload_data[28] <= main_tx_converter_sink_payload_last_be[2]; - main_tx_converter_converter_sink_payload_data[29] <= main_tx_converter_sink_payload_error[2]; - main_tx_converter_converter_sink_payload_data[37:30] <= main_tx_converter_sink_payload_data[31:24]; - main_tx_converter_converter_sink_payload_data[38] <= main_tx_converter_sink_payload_last_be[3]; - main_tx_converter_converter_sink_payload_data[39] <= main_tx_converter_sink_payload_error[3]; -end -assign main_tx_converter_source_valid = main_tx_converter_source_source_valid; -assign main_tx_converter_source_first = main_tx_converter_source_source_first; -assign main_tx_converter_source_last = main_tx_converter_source_source_last; -assign main_tx_converter_source_source_ready = main_tx_converter_source_ready; -assign {main_tx_converter_source_payload_error, main_tx_converter_source_payload_last_be, main_tx_converter_source_payload_data} = main_tx_converter_source_source_payload_data; -assign main_tx_converter_source_source_valid = main_tx_converter_converter_source_valid; -assign main_tx_converter_converter_source_ready = main_tx_converter_source_source_ready; -assign main_tx_converter_source_source_first = main_tx_converter_converter_source_first; -assign main_tx_converter_source_source_last = main_tx_converter_converter_source_last; -assign main_tx_converter_source_source_payload_data = main_tx_converter_converter_source_payload_data; -assign main_tx_converter_converter_first = (main_tx_converter_converter_mux == 1'd0); -assign main_tx_converter_converter_last = (main_tx_converter_converter_mux == 2'd3); -assign main_tx_converter_converter_source_valid = main_tx_converter_converter_sink_valid; -assign main_tx_converter_converter_source_first = (main_tx_converter_converter_sink_first & main_tx_converter_converter_first); -assign main_tx_converter_converter_source_last = (main_tx_converter_converter_sink_last & main_tx_converter_converter_last); -assign main_tx_converter_converter_sink_ready = (main_tx_converter_converter_last & main_tx_converter_converter_source_ready); -always @(*) begin - main_tx_converter_converter_source_payload_data <= 10'd0; - case (main_tx_converter_converter_mux) - 1'd0: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[9:0]; - end - 1'd1: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[19:10]; - end - 2'd2: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[29:20]; - end - default: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[39:30]; - end - endcase -end -assign main_tx_converter_converter_source_payload_valid_token_count = main_tx_converter_converter_last; assign main_rx_converter_converter_sink_valid = main_rx_converter_sink_valid; assign main_rx_converter_converter_sink_first = main_rx_converter_sink_first; assign main_rx_converter_converter_sink_last = main_rx_converter_sink_last; @@ -1706,25 +2250,25 @@ assign main_rx_converter_source_first = main_rx_converter_source_source_first; assign main_rx_converter_source_last = main_rx_converter_source_source_last; assign main_rx_converter_source_source_ready = main_rx_converter_source_ready; always @(*) begin - main_rx_converter_source_payload_data <= 32'd0; - main_rx_converter_source_payload_data[7:0] <= main_rx_converter_source_source_payload_data[7:0]; - main_rx_converter_source_payload_data[15:8] <= main_rx_converter_source_source_payload_data[17:10]; - main_rx_converter_source_payload_data[23:16] <= main_rx_converter_source_source_payload_data[27:20]; - main_rx_converter_source_payload_data[31:24] <= main_rx_converter_source_source_payload_data[37:30]; + main_rx_converter_source_payload_data <= 32'd0; + main_rx_converter_source_payload_data[7:0] <= main_rx_converter_source_source_payload_data[7:0]; + main_rx_converter_source_payload_data[15:8] <= main_rx_converter_source_source_payload_data[17:10]; + main_rx_converter_source_payload_data[23:16] <= main_rx_converter_source_source_payload_data[27:20]; + main_rx_converter_source_payload_data[31:24] <= main_rx_converter_source_source_payload_data[37:30]; end always @(*) begin - main_rx_converter_source_payload_last_be <= 4'd0; - main_rx_converter_source_payload_last_be[0] <= main_rx_converter_source_source_payload_data[8]; - main_rx_converter_source_payload_last_be[1] <= main_rx_converter_source_source_payload_data[18]; - main_rx_converter_source_payload_last_be[2] <= main_rx_converter_source_source_payload_data[28]; - main_rx_converter_source_payload_last_be[3] <= main_rx_converter_source_source_payload_data[38]; + main_rx_converter_source_payload_last_be <= 4'd0; + main_rx_converter_source_payload_last_be[0] <= main_rx_converter_source_source_payload_data[8]; + main_rx_converter_source_payload_last_be[1] <= main_rx_converter_source_source_payload_data[18]; + main_rx_converter_source_payload_last_be[2] <= main_rx_converter_source_source_payload_data[28]; + main_rx_converter_source_payload_last_be[3] <= main_rx_converter_source_source_payload_data[38]; end always @(*) begin - main_rx_converter_source_payload_error <= 4'd0; - main_rx_converter_source_payload_error[0] <= main_rx_converter_source_source_payload_data[9]; - main_rx_converter_source_payload_error[1] <= main_rx_converter_source_source_payload_data[19]; - main_rx_converter_source_payload_error[2] <= main_rx_converter_source_source_payload_data[29]; - main_rx_converter_source_payload_error[3] <= main_rx_converter_source_source_payload_data[39]; + main_rx_converter_source_payload_error <= 4'd0; + main_rx_converter_source_payload_error[0] <= main_rx_converter_source_source_payload_data[9]; + main_rx_converter_source_payload_error[1] <= main_rx_converter_source_source_payload_data[19]; + main_rx_converter_source_payload_error[2] <= main_rx_converter_source_source_payload_data[29]; + main_rx_converter_source_payload_error[3] <= main_rx_converter_source_source_payload_data[39]; end assign main_rx_converter_source_source_valid = main_rx_converter_converter_source_valid; assign main_rx_converter_converter_source_ready = main_rx_converter_source_source_ready; @@ -1734,63 +2278,6 @@ assign main_rx_converter_source_source_payload_data = main_rx_converter_converte assign main_rx_converter_converter_sink_ready = ((~main_rx_converter_converter_strobe_all) | main_rx_converter_converter_source_ready); assign main_rx_converter_converter_source_valid = main_rx_converter_converter_strobe_all; assign main_rx_converter_converter_load_part = (main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready); -assign main_tx_cdc_cdc_sink_valid = main_tx_cdc_sink_sink_valid; -assign main_tx_cdc_sink_sink_ready = main_tx_cdc_cdc_sink_ready; -assign main_tx_cdc_cdc_sink_first = main_tx_cdc_sink_sink_first; -assign main_tx_cdc_cdc_sink_last = main_tx_cdc_sink_sink_last; -assign main_tx_cdc_cdc_sink_payload_data = main_tx_cdc_sink_sink_payload_data; -assign main_tx_cdc_cdc_sink_payload_last_be = main_tx_cdc_sink_sink_payload_last_be; -assign main_tx_cdc_cdc_sink_payload_error = main_tx_cdc_sink_sink_payload_error; -assign main_tx_cdc_source_source_valid = main_tx_cdc_cdc_source_valid; -assign main_tx_cdc_cdc_source_ready = main_tx_cdc_source_source_ready; -assign main_tx_cdc_source_source_first = main_tx_cdc_cdc_source_first; -assign main_tx_cdc_source_source_last = main_tx_cdc_cdc_source_last; -assign main_tx_cdc_source_source_payload_data = main_tx_cdc_cdc_source_payload_data; -assign main_tx_cdc_source_source_payload_last_be = main_tx_cdc_cdc_source_payload_last_be; -assign main_tx_cdc_source_source_payload_error = main_tx_cdc_cdc_source_payload_error; -assign main_tx_cdc_cdc_asyncfifo_din = {main_tx_cdc_cdc_fifo_in_last, main_tx_cdc_cdc_fifo_in_first, main_tx_cdc_cdc_fifo_in_payload_error, main_tx_cdc_cdc_fifo_in_payload_last_be, main_tx_cdc_cdc_fifo_in_payload_data}; -assign {main_tx_cdc_cdc_fifo_out_last, main_tx_cdc_cdc_fifo_out_first, main_tx_cdc_cdc_fifo_out_payload_error, main_tx_cdc_cdc_fifo_out_payload_last_be, main_tx_cdc_cdc_fifo_out_payload_data} = main_tx_cdc_cdc_asyncfifo_dout; -assign main_tx_cdc_cdc_sink_ready = main_tx_cdc_cdc_asyncfifo_writable; -assign main_tx_cdc_cdc_asyncfifo_we = main_tx_cdc_cdc_sink_valid; -assign main_tx_cdc_cdc_fifo_in_first = main_tx_cdc_cdc_sink_first; -assign main_tx_cdc_cdc_fifo_in_last = main_tx_cdc_cdc_sink_last; -assign main_tx_cdc_cdc_fifo_in_payload_data = main_tx_cdc_cdc_sink_payload_data; -assign main_tx_cdc_cdc_fifo_in_payload_last_be = main_tx_cdc_cdc_sink_payload_last_be; -assign main_tx_cdc_cdc_fifo_in_payload_error = main_tx_cdc_cdc_sink_payload_error; -assign main_tx_cdc_cdc_source_valid = main_tx_cdc_cdc_asyncfifo_readable; -assign main_tx_cdc_cdc_source_first = main_tx_cdc_cdc_fifo_out_first; -assign main_tx_cdc_cdc_source_last = main_tx_cdc_cdc_fifo_out_last; -assign main_tx_cdc_cdc_source_payload_data = main_tx_cdc_cdc_fifo_out_payload_data; -assign main_tx_cdc_cdc_source_payload_last_be = main_tx_cdc_cdc_fifo_out_payload_last_be; -assign main_tx_cdc_cdc_source_payload_error = main_tx_cdc_cdc_fifo_out_payload_error; -assign main_tx_cdc_cdc_asyncfifo_re = main_tx_cdc_cdc_source_ready; -assign main_tx_cdc_cdc_graycounter0_ce = (main_tx_cdc_cdc_asyncfifo_writable & main_tx_cdc_cdc_asyncfifo_we); -assign main_tx_cdc_cdc_graycounter1_ce = (main_tx_cdc_cdc_asyncfifo_readable & main_tx_cdc_cdc_asyncfifo_re); -assign main_tx_cdc_cdc_asyncfifo_writable = (((main_tx_cdc_cdc_graycounter0_q[5] == main_tx_cdc_cdc_consume_wdomain[5]) | (main_tx_cdc_cdc_graycounter0_q[4] == main_tx_cdc_cdc_consume_wdomain[4])) | (main_tx_cdc_cdc_graycounter0_q[3:0] != main_tx_cdc_cdc_consume_wdomain[3:0])); -assign main_tx_cdc_cdc_asyncfifo_readable = (main_tx_cdc_cdc_graycounter1_q != main_tx_cdc_cdc_produce_rdomain); -assign main_tx_cdc_cdc_wrport_adr = main_tx_cdc_cdc_graycounter0_q_binary[4:0]; -assign main_tx_cdc_cdc_wrport_dat_w = main_tx_cdc_cdc_asyncfifo_din; -assign main_tx_cdc_cdc_wrport_we = main_tx_cdc_cdc_graycounter0_ce; -assign main_tx_cdc_cdc_rdport_adr = main_tx_cdc_cdc_graycounter1_q_next_binary[4:0]; -assign main_tx_cdc_cdc_asyncfifo_dout = main_tx_cdc_cdc_rdport_dat_r; -always @(*) begin - main_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; - if (main_tx_cdc_cdc_graycounter0_ce) begin - main_tx_cdc_cdc_graycounter0_q_next_binary <= (main_tx_cdc_cdc_graycounter0_q_binary + 1'd1); - end else begin - main_tx_cdc_cdc_graycounter0_q_next_binary <= main_tx_cdc_cdc_graycounter0_q_binary; - end -end -assign main_tx_cdc_cdc_graycounter0_q_next = (main_tx_cdc_cdc_graycounter0_q_next_binary ^ main_tx_cdc_cdc_graycounter0_q_next_binary[5:1]); -always @(*) begin - main_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; - if (main_tx_cdc_cdc_graycounter1_ce) begin - main_tx_cdc_cdc_graycounter1_q_next_binary <= (main_tx_cdc_cdc_graycounter1_q_binary + 1'd1); - end else begin - main_tx_cdc_cdc_graycounter1_q_next_binary <= main_tx_cdc_cdc_graycounter1_q_binary; - end -end -assign main_tx_cdc_cdc_graycounter1_q_next = (main_tx_cdc_cdc_graycounter1_q_next_binary ^ main_tx_cdc_cdc_graycounter1_q_next_binary[5:1]); assign main_rx_cdc_cdc_sink_valid = main_rx_cdc_sink_sink_valid; assign main_rx_cdc_sink_sink_ready = main_rx_cdc_cdc_sink_ready; assign main_rx_cdc_cdc_sink_first = main_rx_cdc_sink_sink_first; @@ -1831,100 +2318,51 @@ assign main_rx_cdc_cdc_wrport_we = main_rx_cdc_cdc_graycounter0_ce; assign main_rx_cdc_cdc_rdport_adr = main_rx_cdc_cdc_graycounter1_q_next_binary[4:0]; assign main_rx_cdc_cdc_asyncfifo_dout = main_rx_cdc_cdc_rdport_dat_r; always @(*) begin - main_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; - if (main_rx_cdc_cdc_graycounter0_ce) begin - main_rx_cdc_cdc_graycounter0_q_next_binary <= (main_rx_cdc_cdc_graycounter0_q_binary + 1'd1); - end else begin - main_rx_cdc_cdc_graycounter0_q_next_binary <= main_rx_cdc_cdc_graycounter0_q_binary; - end + main_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (main_rx_cdc_cdc_graycounter0_ce) begin + main_rx_cdc_cdc_graycounter0_q_next_binary <= (main_rx_cdc_cdc_graycounter0_q_binary + 1'd1); + end else begin + main_rx_cdc_cdc_graycounter0_q_next_binary <= main_rx_cdc_cdc_graycounter0_q_binary; + end end assign main_rx_cdc_cdc_graycounter0_q_next = (main_rx_cdc_cdc_graycounter0_q_next_binary ^ main_rx_cdc_cdc_graycounter0_q_next_binary[5:1]); always @(*) begin - main_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; - if (main_rx_cdc_cdc_graycounter1_ce) begin - main_rx_cdc_cdc_graycounter1_q_next_binary <= (main_rx_cdc_cdc_graycounter1_q_binary + 1'd1); - end else begin - main_rx_cdc_cdc_graycounter1_q_next_binary <= main_rx_cdc_cdc_graycounter1_q_binary; - end + main_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (main_rx_cdc_cdc_graycounter1_ce) begin + main_rx_cdc_cdc_graycounter1_q_next_binary <= (main_rx_cdc_cdc_graycounter1_q_binary + 1'd1); + end else begin + main_rx_cdc_cdc_graycounter1_q_next_binary <= main_rx_cdc_cdc_graycounter1_q_binary; + end end assign main_rx_cdc_cdc_graycounter1_q_next = (main_rx_cdc_cdc_graycounter1_q_next_binary ^ main_rx_cdc_cdc_graycounter1_q_next_binary[5:1]); -assign main_tx_converter_sink_valid = main_tx_cdc_source_source_valid; -assign main_tx_cdc_source_source_ready = main_tx_converter_sink_ready; -assign main_tx_converter_sink_first = main_tx_cdc_source_source_first; -assign main_tx_converter_sink_last = main_tx_cdc_source_source_last; -assign main_tx_converter_sink_payload_data = main_tx_cdc_source_source_payload_data; -assign main_tx_converter_sink_payload_last_be = main_tx_cdc_source_source_payload_last_be; -assign main_tx_converter_sink_payload_error = main_tx_cdc_source_source_payload_error; -assign main_tx_last_be_sink_valid = main_tx_converter_source_valid; -assign main_tx_converter_source_ready = main_tx_last_be_sink_ready; -assign main_tx_last_be_sink_first = main_tx_converter_source_first; -assign main_tx_last_be_sink_last = main_tx_converter_source_last; -assign main_tx_last_be_sink_payload_data = main_tx_converter_source_payload_data; -assign main_tx_last_be_sink_payload_last_be = main_tx_converter_source_payload_last_be; -assign main_tx_last_be_sink_payload_error = main_tx_converter_source_payload_error; -assign main_padding_inserter_sink_valid = main_tx_last_be_source_valid; -assign main_tx_last_be_source_ready = main_padding_inserter_sink_ready; -assign main_padding_inserter_sink_first = main_tx_last_be_source_first; -assign main_padding_inserter_sink_last = main_tx_last_be_source_last; -assign main_padding_inserter_sink_payload_data = main_tx_last_be_source_payload_data; -assign main_padding_inserter_sink_payload_last_be = main_tx_last_be_source_payload_last_be; -assign main_padding_inserter_sink_payload_error = main_tx_last_be_source_payload_error; -assign main_crc32_inserter_sink_valid = main_padding_inserter_source_valid; -assign main_padding_inserter_source_ready = main_crc32_inserter_sink_ready; -assign main_crc32_inserter_sink_first = main_padding_inserter_source_first; -assign main_crc32_inserter_sink_last = main_padding_inserter_source_last; -assign main_crc32_inserter_sink_payload_data = main_padding_inserter_source_payload_data; -assign main_crc32_inserter_sink_payload_last_be = main_padding_inserter_source_payload_last_be; -assign main_crc32_inserter_sink_payload_error = main_padding_inserter_source_payload_error; -assign main_preamble_inserter_sink_valid = main_liteethmaccrc32inserter_source_valid; -assign main_liteethmaccrc32inserter_source_ready = main_preamble_inserter_sink_ready; -assign main_preamble_inserter_sink_first = main_liteethmaccrc32inserter_source_first; -assign main_preamble_inserter_sink_last = main_liteethmaccrc32inserter_source_last; -assign main_preamble_inserter_sink_payload_data = main_liteethmaccrc32inserter_source_payload_data; -assign main_preamble_inserter_sink_payload_last_be = main_liteethmaccrc32inserter_source_payload_last_be; -assign main_preamble_inserter_sink_payload_error = main_liteethmaccrc32inserter_source_payload_error; -assign main_tx_gap_inserter_sink_valid = main_preamble_inserter_source_valid; -assign main_preamble_inserter_source_ready = main_tx_gap_inserter_sink_ready; -assign main_tx_gap_inserter_sink_first = main_preamble_inserter_source_first; -assign main_tx_gap_inserter_sink_last = main_preamble_inserter_source_last; -assign main_tx_gap_inserter_sink_payload_data = main_preamble_inserter_source_payload_data; -assign main_tx_gap_inserter_sink_payload_last_be = main_preamble_inserter_source_payload_last_be; -assign main_tx_gap_inserter_sink_payload_error = main_preamble_inserter_source_payload_error; -assign main_maccore_ethphy_liteethphymiitx_sink_sink_valid = main_tx_gap_inserter_source_valid; -assign main_tx_gap_inserter_source_ready = main_maccore_ethphy_liteethphymiitx_sink_sink_ready; -assign main_maccore_ethphy_liteethphymiitx_sink_sink_first = main_tx_gap_inserter_source_first; -assign main_maccore_ethphy_liteethphymiitx_sink_sink_last = main_tx_gap_inserter_source_last; -assign main_maccore_ethphy_liteethphymiitx_sink_sink_payload_data = main_tx_gap_inserter_source_payload_data; -assign main_maccore_ethphy_liteethphymiitx_sink_sink_payload_last_be = main_tx_gap_inserter_source_payload_last_be; -assign main_maccore_ethphy_liteethphymiitx_sink_sink_payload_error = main_tx_gap_inserter_source_payload_error; -assign main_preamble_checker_sink_valid = main_maccore_ethphy_liteethphymiirx_source_source_valid; -assign main_maccore_ethphy_liteethphymiirx_source_source_ready = main_preamble_checker_sink_ready; -assign main_preamble_checker_sink_first = main_maccore_ethphy_liteethphymiirx_source_source_first; -assign main_preamble_checker_sink_last = main_maccore_ethphy_liteethphymiirx_source_source_last; -assign main_preamble_checker_sink_payload_data = main_maccore_ethphy_liteethphymiirx_source_source_payload_data; -assign main_preamble_checker_sink_payload_last_be = main_maccore_ethphy_liteethphymiirx_source_source_payload_last_be; -assign main_preamble_checker_sink_payload_error = main_maccore_ethphy_liteethphymiirx_source_source_payload_error; -assign main_crc32_checker_sink_valid = main_preamble_checker_source_valid; -assign main_preamble_checker_source_ready = main_crc32_checker_sink_ready; -assign main_crc32_checker_sink_first = main_preamble_checker_source_first; -assign main_crc32_checker_sink_last = main_preamble_checker_source_last; -assign main_crc32_checker_sink_payload_data = main_preamble_checker_source_payload_data; -assign main_crc32_checker_sink_payload_last_be = main_preamble_checker_source_payload_last_be; -assign main_crc32_checker_sink_payload_error = main_preamble_checker_source_payload_error; -assign main_padding_checker_sink_valid = main_liteethmaccrc32checker_source_source_valid; -assign main_liteethmaccrc32checker_source_source_ready = main_padding_checker_sink_ready; -assign main_padding_checker_sink_first = main_liteethmaccrc32checker_source_source_first; -assign main_padding_checker_sink_last = main_liteethmaccrc32checker_source_source_last; -assign main_padding_checker_sink_payload_data = main_liteethmaccrc32checker_source_source_payload_data; -assign main_padding_checker_sink_payload_last_be = main_liteethmaccrc32checker_source_source_payload_last_be; -assign main_padding_checker_sink_payload_error = main_liteethmaccrc32checker_source_source_payload_error; -assign main_rx_last_be_sink_valid = main_padding_checker_source_valid; -assign main_padding_checker_source_ready = main_rx_last_be_sink_ready; -assign main_rx_last_be_sink_first = main_padding_checker_source_first; -assign main_rx_last_be_sink_last = main_padding_checker_source_last; -assign main_rx_last_be_sink_payload_data = main_padding_checker_source_payload_data; -assign main_rx_last_be_sink_payload_last_be = main_padding_checker_source_payload_last_be; -assign main_rx_last_be_sink_payload_error = main_padding_checker_source_payload_error; +assign main_rx_preamble_sink_valid = main_maccore_liteethphymiirx_source_valid; +assign main_maccore_liteethphymiirx_source_ready = main_rx_preamble_sink_ready; +assign main_rx_preamble_sink_first = main_maccore_liteethphymiirx_source_first; +assign main_rx_preamble_sink_last = main_maccore_liteethphymiirx_source_last; +assign main_rx_preamble_sink_payload_data = main_maccore_liteethphymiirx_source_payload_data; +assign main_rx_preamble_sink_payload_last_be = main_maccore_liteethphymiirx_source_payload_last_be; +assign main_rx_preamble_sink_payload_error = main_maccore_liteethphymiirx_source_payload_error; +assign main_bufferizeendpoints_sink_sink_valid = main_rx_preamble_source_valid; +assign main_rx_preamble_source_ready = main_bufferizeendpoints_sink_sink_ready; +assign main_bufferizeendpoints_sink_sink_first = main_rx_preamble_source_first; +assign main_bufferizeendpoints_sink_sink_last = main_rx_preamble_source_last; +assign main_bufferizeendpoints_sink_sink_payload_data = main_rx_preamble_source_payload_data; +assign main_bufferizeendpoints_sink_sink_payload_last_be = main_rx_preamble_source_payload_last_be; +assign main_bufferizeendpoints_sink_sink_payload_error = main_rx_preamble_source_payload_error; +assign main_rx_padding_sink_valid = main_liteethmaccrc32checker_source_source_valid; +assign main_liteethmaccrc32checker_source_source_ready = main_rx_padding_sink_ready; +assign main_rx_padding_sink_first = main_liteethmaccrc32checker_source_source_first; +assign main_rx_padding_sink_last = main_liteethmaccrc32checker_source_source_last; +assign main_rx_padding_sink_payload_data = main_liteethmaccrc32checker_source_source_payload_data; +assign main_rx_padding_sink_payload_last_be = main_liteethmaccrc32checker_source_source_payload_last_be; +assign main_rx_padding_sink_payload_error = main_liteethmaccrc32checker_source_source_payload_error; +assign main_rx_last_be_sink_valid = main_rx_padding_source_valid; +assign main_rx_padding_source_ready = main_rx_last_be_sink_ready; +assign main_rx_last_be_sink_first = main_rx_padding_source_first; +assign main_rx_last_be_sink_last = main_rx_padding_source_last; +assign main_rx_last_be_sink_payload_data = main_rx_padding_source_payload_data; +assign main_rx_last_be_sink_payload_last_be = main_rx_padding_source_payload_last_be; +assign main_rx_last_be_sink_payload_error = main_rx_padding_source_payload_error; assign main_rx_converter_sink_valid = main_rx_last_be_source_valid; assign main_rx_last_be_source_ready = main_rx_converter_sink_ready; assign main_rx_converter_sink_first = main_rx_last_be_source_first; @@ -1939,1529 +2377,1700 @@ assign main_rx_cdc_sink_sink_last = main_rx_converter_source_last; assign main_rx_cdc_sink_sink_payload_data = main_rx_converter_source_payload_data; assign main_rx_cdc_sink_sink_payload_last_be = main_rx_converter_source_payload_last_be; assign main_rx_cdc_sink_sink_payload_error = main_rx_converter_source_payload_error; -assign main_writer_sink_sink_valid = main_sink_valid; -assign main_sink_ready = main_writer_sink_sink_ready; -assign main_writer_sink_sink_first = main_sink_first; -assign main_writer_sink_sink_last = main_sink_last; -assign main_writer_sink_sink_payload_data = main_sink_payload_data; -assign main_writer_sink_sink_payload_last_be = main_sink_payload_last_be; -assign main_writer_sink_sink_payload_error = main_sink_payload_error; -assign main_source_valid = main_reader_source_source_valid; -assign main_reader_source_source_ready = main_source_ready; -assign main_source_first = main_reader_source_source_first; -assign main_source_last = main_reader_source_source_last; -assign main_source_payload_data = main_reader_source_source_payload_data; -assign main_source_payload_last_be = main_reader_source_source_payload_last_be; -assign main_source_payload_error = main_reader_source_source_payload_error; -always @(*) begin - main_writer_inc <= 3'd0; - case (main_writer_sink_sink_payload_last_be) - 1'd1: begin - main_writer_inc <= 1'd1; - end - 2'd2: begin - main_writer_inc <= 2'd2; - end - 3'd4: begin - main_writer_inc <= 2'd3; - end - default: begin - main_writer_inc <= 3'd4; - end - endcase -end -assign main_writer_stat_fifo_sink_payload_slot = main_writer_slot; -assign main_writer_stat_fifo_sink_payload_length = main_writer_counter; -assign main_writer_stat_fifo_source_ready = main_writer_available_clear; -assign main_writer_available_trigger = main_writer_stat_fifo_source_valid; -assign main_writer_slot_status = main_writer_stat_fifo_source_payload_slot; -assign main_writer_length_status = main_writer_stat_fifo_source_payload_length; -always @(*) begin - main_writer_memory0_we <= 1'd0; - main_writer_memory0_dat_w <= 32'd0; - main_writer_memory1_adr <= 9'd0; - main_writer_memory1_we <= 1'd0; - main_writer_memory0_adr <= 9'd0; - main_writer_memory1_dat_w <= 32'd0; - case (main_writer_slot) - 1'd0: begin - main_writer_memory0_adr <= main_writer_counter[31:2]; - main_writer_memory0_dat_w <= main_writer_sink_sink_payload_data; - if ((main_writer_sink_sink_valid & main_writer_ongoing)) begin - main_writer_memory0_we <= 4'd15; - end - end - 1'd1: begin - main_writer_memory1_adr <= main_writer_counter[31:2]; - main_writer_memory1_dat_w <= main_writer_sink_sink_payload_data; - if ((main_writer_sink_sink_valid & main_writer_ongoing)) begin - main_writer_memory1_we <= 4'd15; - end - end - endcase -end -assign main_writer_available0 = main_writer_available_status; -assign main_writer_available1 = main_writer_available_pending; -always @(*) begin - main_writer_available_clear <= 1'd0; - if ((main_writer_pending_re & main_writer_pending_r)) begin - main_writer_available_clear <= 1'd1; - end -end -assign main_writer_irq = (main_writer_pending_status & main_writer_enable_storage); -assign main_writer_available_status = main_writer_available_trigger; -assign main_writer_available_pending = main_writer_available_trigger; -assign main_writer_stat_fifo_syncfifo_din = {main_writer_stat_fifo_fifo_in_last, main_writer_stat_fifo_fifo_in_first, main_writer_stat_fifo_fifo_in_payload_length, main_writer_stat_fifo_fifo_in_payload_slot}; -assign {main_writer_stat_fifo_fifo_out_last, main_writer_stat_fifo_fifo_out_first, main_writer_stat_fifo_fifo_out_payload_length, main_writer_stat_fifo_fifo_out_payload_slot} = main_writer_stat_fifo_syncfifo_dout; -assign main_writer_stat_fifo_sink_ready = main_writer_stat_fifo_syncfifo_writable; -assign main_writer_stat_fifo_syncfifo_we = main_writer_stat_fifo_sink_valid; -assign main_writer_stat_fifo_fifo_in_first = main_writer_stat_fifo_sink_first; -assign main_writer_stat_fifo_fifo_in_last = main_writer_stat_fifo_sink_last; -assign main_writer_stat_fifo_fifo_in_payload_slot = main_writer_stat_fifo_sink_payload_slot; -assign main_writer_stat_fifo_fifo_in_payload_length = main_writer_stat_fifo_sink_payload_length; -assign main_writer_stat_fifo_source_valid = main_writer_stat_fifo_syncfifo_readable; -assign main_writer_stat_fifo_source_first = main_writer_stat_fifo_fifo_out_first; -assign main_writer_stat_fifo_source_last = main_writer_stat_fifo_fifo_out_last; -assign main_writer_stat_fifo_source_payload_slot = main_writer_stat_fifo_fifo_out_payload_slot; -assign main_writer_stat_fifo_source_payload_length = main_writer_stat_fifo_fifo_out_payload_length; -assign main_writer_stat_fifo_syncfifo_re = main_writer_stat_fifo_source_ready; -always @(*) begin - main_writer_stat_fifo_wrport_adr <= 1'd0; - if (main_writer_stat_fifo_replace) begin - main_writer_stat_fifo_wrport_adr <= (main_writer_stat_fifo_produce - 1'd1); - end else begin - main_writer_stat_fifo_wrport_adr <= main_writer_stat_fifo_produce; - end -end -assign main_writer_stat_fifo_wrport_dat_w = main_writer_stat_fifo_syncfifo_din; -assign main_writer_stat_fifo_wrport_we = (main_writer_stat_fifo_syncfifo_we & (main_writer_stat_fifo_syncfifo_writable | main_writer_stat_fifo_replace)); -assign main_writer_stat_fifo_do_read = (main_writer_stat_fifo_syncfifo_readable & main_writer_stat_fifo_syncfifo_re); -assign main_writer_stat_fifo_rdport_adr = main_writer_stat_fifo_consume; -assign main_writer_stat_fifo_syncfifo_dout = main_writer_stat_fifo_rdport_dat_r; -assign main_writer_stat_fifo_syncfifo_writable = (main_writer_stat_fifo_level != 2'd2); -assign main_writer_stat_fifo_syncfifo_readable = (main_writer_stat_fifo_level != 1'd0); -always @(*) begin - main_writer_start <= 1'd0; - main_writer_counter_t_next_value_ce <= 1'd0; - main_writer_ongoing <= 1'd0; - main_writer_slot_ce <= 1'd0; - main_writer_errors_status_f_next_value <= 32'd0; - main_writer_stat_fifo_sink_valid <= 1'd0; - main_writer_errors_status_f_next_value_ce <= 1'd0; - builder_liteethmacsramwriter_next_state <= 3'd0; - main_writer_counter_t_next_value <= 32'd0; - builder_liteethmacsramwriter_next_state <= builder_liteethmacsramwriter_state; - case (builder_liteethmacsramwriter_state) - 1'd1: begin - if (main_writer_sink_sink_valid) begin - if ((main_writer_counter == 11'd1530)) begin - builder_liteethmacsramwriter_next_state <= 2'd3; - end else begin - main_writer_counter_t_next_value <= (main_writer_counter + main_writer_inc); - main_writer_counter_t_next_value_ce <= 1'd1; - main_writer_ongoing <= 1'd1; - end - if (main_writer_sink_sink_last) begin - if (((main_writer_sink_sink_payload_error & main_writer_sink_sink_payload_last_be) != 1'd0)) begin - builder_liteethmacsramwriter_next_state <= 2'd2; - end else begin - builder_liteethmacsramwriter_next_state <= 3'd4; - end - end - end - end - 2'd2: begin - main_writer_counter_t_next_value <= 1'd0; - main_writer_counter_t_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 1'd0; - end - 2'd3: begin - if ((main_writer_sink_sink_valid & main_writer_sink_sink_last)) begin - builder_liteethmacsramwriter_next_state <= 3'd4; - end - end - 3'd4: begin - main_writer_counter_t_next_value <= 1'd0; - main_writer_counter_t_next_value_ce <= 1'd1; - main_writer_slot_ce <= 1'd1; - main_writer_stat_fifo_sink_valid <= 1'd1; - builder_liteethmacsramwriter_next_state <= 1'd0; - end - default: begin - if (main_writer_sink_sink_valid) begin - if (main_writer_stat_fifo_sink_ready) begin - main_writer_start <= 1'd1; - main_writer_ongoing <= 1'd1; - main_writer_counter_t_next_value <= (main_writer_counter + main_writer_inc); - main_writer_counter_t_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 1'd1; - end else begin - main_writer_errors_status_f_next_value <= (main_writer_errors_status + 1'd1); - main_writer_errors_status_f_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 2'd3; - end - end - end - endcase -end -assign main_reader_cmd_fifo_sink_valid = main_reader_start_start_re; -assign main_reader_cmd_fifo_sink_payload_slot = main_reader_slot_storage; -assign main_reader_cmd_fifo_sink_payload_length = main_reader_length_storage; -assign main_reader_ready_status = main_reader_cmd_fifo_sink_ready; -assign main_reader_level_status = main_reader_cmd_fifo_level; -always @(*) begin - main_reader_source_source_payload_last_be <= 4'd0; - if (main_reader_source_source_last) begin - case (main_reader_cmd_fifo_source_payload_length[1:0]) - 1'd0: begin - main_reader_source_source_payload_last_be <= 4'd8; - end - 1'd1: begin - main_reader_source_source_payload_last_be <= 1'd1; - end - 2'd2: begin - main_reader_source_source_payload_last_be <= 2'd2; - end - 2'd3: begin - main_reader_source_source_payload_last_be <= 3'd4; - end - endcase - end -end -assign main_reader_memory0_adr = main_reader_read_address[10:2]; -assign main_reader_memory1_adr = main_reader_read_address[10:2]; -always @(*) begin - main_reader_source_source_payload_data <= 32'd0; - case (main_reader_cmd_fifo_source_payload_slot) - 1'd0: begin - main_reader_source_source_payload_data <= main_reader_memory0_dat_r; - end - 1'd1: begin - main_reader_source_source_payload_data <= main_reader_memory1_dat_r; - end - endcase -end -assign main_reader_event00 = main_reader_eventsourcepulse_status; -assign main_reader_event01 = main_reader_eventsourcepulse_pending; -always @(*) begin - main_reader_eventsourcepulse_clear <= 1'd0; - if ((main_reader_pending_re & main_reader_pending_r)) begin - main_reader_eventsourcepulse_clear <= 1'd1; - end -end -assign main_reader_irq = (main_reader_pending_status & main_reader_enable_storage); -assign main_reader_eventsourcepulse_status = 1'd0; -assign main_reader_cmd_fifo_syncfifo_din = {main_reader_cmd_fifo_fifo_in_last, main_reader_cmd_fifo_fifo_in_first, main_reader_cmd_fifo_fifo_in_payload_length, main_reader_cmd_fifo_fifo_in_payload_slot}; -assign {main_reader_cmd_fifo_fifo_out_last, main_reader_cmd_fifo_fifo_out_first, main_reader_cmd_fifo_fifo_out_payload_length, main_reader_cmd_fifo_fifo_out_payload_slot} = main_reader_cmd_fifo_syncfifo_dout; -assign main_reader_cmd_fifo_sink_ready = main_reader_cmd_fifo_syncfifo_writable; -assign main_reader_cmd_fifo_syncfifo_we = main_reader_cmd_fifo_sink_valid; -assign main_reader_cmd_fifo_fifo_in_first = main_reader_cmd_fifo_sink_first; -assign main_reader_cmd_fifo_fifo_in_last = main_reader_cmd_fifo_sink_last; -assign main_reader_cmd_fifo_fifo_in_payload_slot = main_reader_cmd_fifo_sink_payload_slot; -assign main_reader_cmd_fifo_fifo_in_payload_length = main_reader_cmd_fifo_sink_payload_length; -assign main_reader_cmd_fifo_source_valid = main_reader_cmd_fifo_syncfifo_readable; -assign main_reader_cmd_fifo_source_first = main_reader_cmd_fifo_fifo_out_first; -assign main_reader_cmd_fifo_source_last = main_reader_cmd_fifo_fifo_out_last; -assign main_reader_cmd_fifo_source_payload_slot = main_reader_cmd_fifo_fifo_out_payload_slot; -assign main_reader_cmd_fifo_source_payload_length = main_reader_cmd_fifo_fifo_out_payload_length; -assign main_reader_cmd_fifo_syncfifo_re = main_reader_cmd_fifo_source_ready; -always @(*) begin - main_reader_cmd_fifo_wrport_adr <= 1'd0; - if (main_reader_cmd_fifo_replace) begin - main_reader_cmd_fifo_wrport_adr <= (main_reader_cmd_fifo_produce - 1'd1); - end else begin - main_reader_cmd_fifo_wrport_adr <= main_reader_cmd_fifo_produce; - end -end -assign main_reader_cmd_fifo_wrport_dat_w = main_reader_cmd_fifo_syncfifo_din; -assign main_reader_cmd_fifo_wrport_we = (main_reader_cmd_fifo_syncfifo_we & (main_reader_cmd_fifo_syncfifo_writable | main_reader_cmd_fifo_replace)); -assign main_reader_cmd_fifo_do_read = (main_reader_cmd_fifo_syncfifo_readable & main_reader_cmd_fifo_syncfifo_re); -assign main_reader_cmd_fifo_rdport_adr = main_reader_cmd_fifo_consume; -assign main_reader_cmd_fifo_syncfifo_dout = main_reader_cmd_fifo_rdport_dat_r; -assign main_reader_cmd_fifo_syncfifo_writable = (main_reader_cmd_fifo_level != 2'd2); -assign main_reader_cmd_fifo_syncfifo_readable = (main_reader_cmd_fifo_level != 1'd0); -always @(*) begin - main_reader_source_source_last <= 1'd0; - builder_liteethmacsramreader_next_state <= 2'd0; - main_reader_counter_next_value <= 11'd0; - main_reader_read_address <= 11'd0; - main_reader_counter_next_value_ce <= 1'd0; - main_reader_cmd_fifo_source_ready <= 1'd0; - main_reader_eventsourcepulse_trigger <= 1'd0; - main_reader_source_source_valid <= 1'd0; - main_reader_start <= 1'd0; - builder_liteethmacsramreader_next_state <= builder_liteethmacsramreader_state; - case (builder_liteethmacsramreader_state) - 1'd1: begin - main_reader_source_source_valid <= 1'd1; - main_reader_source_source_last <= (main_reader_counter >= (main_reader_cmd_fifo_source_payload_length - 3'd4)); - main_reader_read_address <= main_reader_counter; - if (main_reader_source_source_ready) begin - main_reader_read_address <= (main_reader_counter + 3'd4); - main_reader_counter_next_value <= (main_reader_counter + 3'd4); - main_reader_counter_next_value_ce <= 1'd1; - if (main_reader_source_source_last) begin - builder_liteethmacsramreader_next_state <= 2'd2; - end - end - end - 2'd2: begin - main_reader_eventsourcepulse_trigger <= 1'd1; - main_reader_cmd_fifo_source_ready <= 1'd1; - builder_liteethmacsramreader_next_state <= 1'd0; - end - default: begin - main_reader_counter_next_value <= 1'd0; - main_reader_counter_next_value_ce <= 1'd1; - if (main_reader_cmd_fifo_source_valid) begin - main_reader_start <= 1'd1; - builder_liteethmacsramreader_next_state <= 1'd1; - end - end - endcase -end -assign main_ev_irq = (main_writer_irq | main_reader_irq); -assign main_sram0_adr0 = main_sram0_bus_adr0[8:0]; -assign main_sram0_bus_dat_r0 = main_sram0_dat_r0; -assign main_sram1_adr0 = main_sram1_bus_adr0[8:0]; -assign main_sram1_bus_dat_r0 = main_sram1_dat_r0; -always @(*) begin - main_sram0_we <= 4'd0; - main_sram0_we[0] <= (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & main_sram0_bus_we1) & main_sram0_bus_sel1[0]); - main_sram0_we[1] <= (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & main_sram0_bus_we1) & main_sram0_bus_sel1[1]); - main_sram0_we[2] <= (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & main_sram0_bus_we1) & main_sram0_bus_sel1[2]); - main_sram0_we[3] <= (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & main_sram0_bus_we1) & main_sram0_bus_sel1[3]); -end -assign main_sram0_adr1 = main_sram0_bus_adr1[8:0]; -assign main_sram0_bus_dat_r1 = main_sram0_dat_r1; -assign main_sram0_dat_w = main_sram0_bus_dat_w1; -always @(*) begin - main_sram1_we <= 4'd0; - main_sram1_we[0] <= (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & main_sram1_bus_we1) & main_sram1_bus_sel1[0]); - main_sram1_we[1] <= (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & main_sram1_bus_we1) & main_sram1_bus_sel1[1]); - main_sram1_we[2] <= (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & main_sram1_bus_we1) & main_sram1_bus_sel1[2]); - main_sram1_we[3] <= (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & main_sram1_bus_we1) & main_sram1_bus_sel1[3]); -end -assign main_sram1_adr1 = main_sram1_bus_adr1[8:0]; -assign main_sram1_bus_dat_r1 = main_sram1_dat_r1; -assign main_sram1_dat_w = main_sram1_bus_dat_w1; -always @(*) begin - main_slave_sel <= 4'd0; - main_slave_sel[0] <= (main_bus_adr[10:9] == 1'd0); - main_slave_sel[1] <= (main_bus_adr[10:9] == 1'd1); - main_slave_sel[2] <= (main_bus_adr[10:9] == 2'd2); - main_slave_sel[3] <= (main_bus_adr[10:9] == 2'd3); -end -assign main_sram0_bus_adr0 = main_bus_adr; -assign main_sram0_bus_dat_w0 = main_bus_dat_w; -assign main_sram0_bus_sel0 = main_bus_sel; -assign main_sram0_bus_stb0 = main_bus_stb; -assign main_sram0_bus_we0 = main_bus_we; -assign main_sram0_bus_cti0 = main_bus_cti; -assign main_sram0_bus_bte0 = main_bus_bte; -assign main_sram1_bus_adr0 = main_bus_adr; -assign main_sram1_bus_dat_w0 = main_bus_dat_w; -assign main_sram1_bus_sel0 = main_bus_sel; -assign main_sram1_bus_stb0 = main_bus_stb; -assign main_sram1_bus_we0 = main_bus_we; -assign main_sram1_bus_cti0 = main_bus_cti; -assign main_sram1_bus_bte0 = main_bus_bte; -assign main_sram0_bus_adr1 = main_bus_adr; -assign main_sram0_bus_dat_w1 = main_bus_dat_w; -assign main_sram0_bus_sel1 = main_bus_sel; -assign main_sram0_bus_stb1 = main_bus_stb; -assign main_sram0_bus_we1 = main_bus_we; -assign main_sram0_bus_cti1 = main_bus_cti; -assign main_sram0_bus_bte1 = main_bus_bte; -assign main_sram1_bus_adr1 = main_bus_adr; -assign main_sram1_bus_dat_w1 = main_bus_dat_w; -assign main_sram1_bus_sel1 = main_bus_sel; -assign main_sram1_bus_stb1 = main_bus_stb; -assign main_sram1_bus_we1 = main_bus_we; -assign main_sram1_bus_cti1 = main_bus_cti; -assign main_sram1_bus_bte1 = main_bus_bte; -assign main_sram0_bus_cyc0 = (main_bus_cyc & main_slave_sel[0]); -assign main_sram1_bus_cyc0 = (main_bus_cyc & main_slave_sel[1]); -assign main_sram0_bus_cyc1 = (main_bus_cyc & main_slave_sel[2]); -assign main_sram1_bus_cyc1 = (main_bus_cyc & main_slave_sel[3]); -assign main_bus_ack = (((main_sram0_bus_ack0 | main_sram1_bus_ack0) | main_sram0_bus_ack1) | main_sram1_bus_ack1); -assign main_bus_err = (((main_sram0_bus_err0 | main_sram1_bus_err0) | main_sram0_bus_err1) | main_sram1_bus_err1); -assign main_bus_dat_r = (((({32{main_slave_sel_r[0]}} & main_sram0_bus_dat_r0) | ({32{main_slave_sel_r[1]}} & main_sram1_bus_dat_r0)) | ({32{main_slave_sel_r[2]}} & main_sram0_bus_dat_r1)) | ({32{main_slave_sel_r[3]}} & main_sram1_bus_dat_r1)); -always @(*) begin - builder_next_state <= 1'd0; - builder_maccore_wishbone_dat_r <= 32'd0; - builder_maccore_adr <= 14'd0; - builder_maccore_we <= 1'd0; - builder_maccore_wishbone_ack <= 1'd0; - builder_maccore_dat_w <= 32'd0; - builder_next_state <= builder_state; - case (builder_state) - 1'd1: begin - builder_maccore_wishbone_ack <= 1'd1; - builder_maccore_wishbone_dat_r <= builder_maccore_dat_r; - builder_next_state <= 1'd0; - end - default: begin - builder_maccore_dat_w <= builder_maccore_wishbone_dat_w; - if ((builder_maccore_wishbone_cyc & builder_maccore_wishbone_stb)) begin - builder_maccore_adr <= builder_maccore_wishbone_adr; - builder_maccore_we <= (builder_maccore_wishbone_we & (builder_maccore_wishbone_sel != 1'd0)); - builder_next_state <= 1'd1; - end - end - endcase -end -assign builder_shared_adr = builder_array_muxed0; -assign builder_shared_dat_w = builder_array_muxed1; -assign builder_shared_sel = builder_array_muxed2; -assign builder_shared_cyc = builder_array_muxed3; -assign builder_shared_stb = builder_array_muxed4; -assign builder_shared_we = builder_array_muxed5; -assign builder_shared_cti = builder_array_muxed6; -assign builder_shared_bte = builder_array_muxed7; -assign main_wb_bus_dat_r = builder_shared_dat_r; -assign main_wb_bus_ack = (builder_shared_ack & (builder_grant == 1'd0)); -assign main_wb_bus_err = (builder_shared_err & (builder_grant == 1'd0)); -assign builder_request = {main_wb_bus_cyc}; -assign builder_grant = 1'd0; -always @(*) begin - builder_slave_sel <= 2'd0; - builder_slave_sel[0] <= (builder_shared_adr[29:11] == 4'd8); - builder_slave_sel[1] <= (builder_shared_adr[29:14] == 1'd0); -end -assign main_bus_adr = builder_shared_adr; -assign main_bus_dat_w = builder_shared_dat_w; -assign main_bus_sel = builder_shared_sel; -assign main_bus_stb = builder_shared_stb; -assign main_bus_we = builder_shared_we; -assign main_bus_cti = builder_shared_cti; -assign main_bus_bte = builder_shared_bte; -assign builder_maccore_wishbone_adr = builder_shared_adr; -assign builder_maccore_wishbone_dat_w = builder_shared_dat_w; -assign builder_maccore_wishbone_sel = builder_shared_sel; -assign builder_maccore_wishbone_stb = builder_shared_stb; -assign builder_maccore_wishbone_we = builder_shared_we; -assign builder_maccore_wishbone_cti = builder_shared_cti; -assign builder_maccore_wishbone_bte = builder_shared_bte; -assign main_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]); -assign builder_maccore_wishbone_cyc = (builder_shared_cyc & builder_slave_sel[1]); -assign builder_shared_err = (main_bus_err | builder_maccore_wishbone_err); -assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack)); -always @(*) begin - builder_shared_ack <= 1'd0; - builder_error <= 1'd0; - builder_shared_dat_r <= 32'd0; - builder_shared_ack <= (main_bus_ack | builder_maccore_wishbone_ack); - builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & builder_maccore_wishbone_dat_r)); - if (builder_done) begin - builder_shared_dat_r <= 32'd4294967295; - builder_shared_ack <= 1'd1; - builder_error <= 1'd1; - end +assign main_source_valid = main_rx_cdc_source_source_valid; +assign main_rx_cdc_source_source_ready = main_source_ready; +assign main_source_first = main_rx_cdc_source_source_first; +assign main_source_last = main_rx_cdc_source_source_last; +assign main_source_payload_data = main_rx_cdc_source_source_payload_data; +assign main_source_payload_last_be = main_rx_cdc_source_source_payload_last_be; +assign main_source_payload_error = main_rx_cdc_source_source_payload_error; +assign main_sram0_sink_valid = main_sink_sink_valid; +assign main_sink_sink_ready = main_sram1_sink_ready; +assign main_sram2_sink_first = main_sink_sink_first; +assign main_sram3_sink_last = main_sink_sink_last; +assign main_sram4_sink_payload_data = main_sink_sink_payload_data; +assign main_sram5_sink_payload_last_be = main_sink_sink_payload_last_be; +assign main_sram6_sink_payload_error = main_sink_sink_payload_error; +assign main_source_source_valid = main_sram83_source_valid; +assign main_sram84_source_ready = main_source_source_ready; +assign main_source_source_first = main_sram85_source_first; +assign main_source_source_last = main_sram86_source_last; +assign main_source_source_payload_data = main_sram87_source_payload_data; +assign main_source_source_payload_last_be = main_sram88_source_payload_last_be; +assign main_source_source_payload_error = main_sram89_source_payload_error; +always @(*) begin + main_length_inc <= 4'd0; + case (main_sram5_sink_payload_last_be) + 1'd1: begin + main_length_inc <= 1'd1; + end + 2'd2: begin + main_length_inc <= 2'd2; + end + 3'd4: begin + main_length_inc <= 2'd3; + end + 4'd8: begin + main_length_inc <= 3'd4; + end + 5'd16: begin + main_length_inc <= 3'd5; + end + 6'd32: begin + main_length_inc <= 3'd6; + end + 7'd64: begin + main_length_inc <= 3'd7; + end + default: begin + main_length_inc <= 3'd4; + end + endcase +end +assign main_sram44_source_ready = main_sram20_clear; +assign main_sram19_trigger = main_sram43_source_valid; +assign main_sram7_status = main_sram47_source_payload_slot; +assign main_sram10_status = main_sram48_source_payload_length; +assign main_wr_data = main_sram4_sink_payload_data; +always @(*) begin + main_sram75_adr <= 9'd0; + main_sram77_we <= 1'd0; + main_sram78_dat_w <= 32'd0; + main_sram79_adr <= 9'd0; + main_sram81_we <= 1'd0; + main_sram82_dat_w <= 32'd0; + case (main_slot) + 1'd0: begin + main_sram75_adr <= main_sram35_length[10:2]; + main_sram78_dat_w <= main_wr_data; + if ((main_sram0_sink_valid & main_write)) begin + main_sram77_we <= 1'd1; + end + end + 1'd1: begin + main_sram79_adr <= main_sram35_length[10:2]; + main_sram82_dat_w <= main_wr_data; + if ((main_sram0_sink_valid & main_write)) begin + main_sram81_we <= 1'd1; + end + end + endcase +end +assign main_sram21_available = main_sram17_status; +assign main_sram25_available = main_sram18_pending; +always @(*) begin + main_sram20_clear <= 1'd0; + if ((main_sram28_re & main_sram29_r)) begin + main_sram20_clear <= 1'd1; + end +end +assign main_sram16_irq = (main_sram26_status & main_sram31_storage); +assign main_sram17_status = main_sram19_trigger; +assign main_sram18_pending = main_sram19_trigger; +assign main_sram53_din = {main_sram69_fifo_in_last, main_sram68_fifo_in_first, main_sram67_fifo_in_payload_length, main_sram66_fifo_in_payload_slot}; +assign {main_sram73_fifo_out_last, main_sram72_fifo_out_first, main_sram71_fifo_out_payload_length, main_sram70_fifo_out_payload_slot} = main_sram54_dout; +assign main_sram38_sink_ready = main_sram50_writable; +assign main_sram49_we = main_sram37_sink_valid; +assign main_sram68_fifo_in_first = main_sram39_sink_first; +assign main_sram69_fifo_in_last = main_sram40_sink_last; +assign main_sram66_fifo_in_payload_slot = main_sram41_sink_payload_slot; +assign main_sram67_fifo_in_payload_length = main_sram42_sink_payload_length; +assign main_sram43_source_valid = main_sram52_readable; +assign main_sram45_source_first = main_sram72_fifo_out_first; +assign main_sram46_source_last = main_sram73_fifo_out_last; +assign main_sram47_source_payload_slot = main_sram70_fifo_out_payload_slot; +assign main_sram48_source_payload_length = main_sram71_fifo_out_payload_length; +assign main_sram51_re = main_sram44_source_ready; +always @(*) begin + main_sram59_adr <= 1'd0; + if (main_sram56_replace) begin + main_sram59_adr <= (main_sram57_produce - 1'd1); + end else begin + main_sram59_adr <= main_sram57_produce; + end +end +assign main_sram62_dat_w = main_sram53_din; +assign main_sram61_we = (main_sram49_we & (main_sram50_writable | main_sram56_replace)); +assign main_sram63_do_read = (main_sram52_readable & main_sram51_re); +assign main_sram64_adr = main_sram58_consume; +assign main_sram54_dout = main_sram65_dat_r; +assign main_sram50_writable = (main_sram55_level != 2'd2); +assign main_sram52_readable = (main_sram55_level != 1'd0); +always @(*) begin + builder_liteethmacsramwriter_next_state <= 3'd0; + main_slot_liteethmacsramwriter_next_value <= 1'd0; + main_slot_liteethmacsramwriter_next_value_ce <= 1'd0; + main_sram13_status_liteethmacsramwriter_f_next_value <= 32'd0; + main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value <= 11'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd0; + main_sram37_sink_valid <= 1'd0; + main_sram41_sink_payload_slot <= 1'd0; + main_sram42_sink_payload_length <= 11'd0; + main_write <= 1'd0; + builder_liteethmacsramwriter_next_state <= builder_liteethmacsramwriter_state; + case (builder_liteethmacsramwriter_state) + 1'd1: begin + if ((main_sram0_sink_valid & main_sram3_sink_last)) begin + if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + builder_liteethmacsramwriter_next_state <= 3'd4; + end + end + end + 2'd2: begin + if ((main_sram0_sink_valid & main_sram3_sink_last)) begin + if ((main_sram5_sink_payload_last_be != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + end + end + 2'd3: begin + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + 3'd4: begin + main_sram37_sink_valid <= 1'd1; + main_sram41_sink_payload_slot <= main_slot; + main_sram42_sink_payload_length <= main_sram35_length; + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + main_slot_liteethmacsramwriter_next_value <= (main_slot + 1'd1); + main_slot_liteethmacsramwriter_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + default: begin + if (main_sram0_sink_valid) begin + if (main_sram38_sink_ready) begin + main_write <= 1'd1; + main_sram35_length_liteethmacsramwriter_t_next_value <= (main_sram35_length + main_length_inc); + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + if ((main_sram35_length >= 11'd1530)) begin + builder_liteethmacsramwriter_next_state <= 1'd1; + end + if (main_sram3_sink_last) begin + if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + builder_liteethmacsramwriter_next_state <= 3'd4; + end + end + end else begin + main_sram13_status_liteethmacsramwriter_f_next_value <= (main_sram13_status + 1'd1); + main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 2'd2; + end + end + end + endcase +end +assign main_sram123_sink_valid = main_start_re; +assign main_sram127_sink_payload_slot = main_sram100_storage; +assign main_sram128_sink_payload_length = main_sram102_storage; +assign main_sram94_status = main_sram124_sink_ready; +assign main_sram97_status = main_sram141_level; +always @(*) begin + main_sram88_source_payload_last_be <= 4'd0; + if (main_sram86_source_last) begin + case (main_sram134_source_payload_length[1:0]) + 1'd1: begin + main_sram88_source_payload_last_be <= 1'd1; + end + 2'd2: begin + main_sram88_source_payload_last_be <= 2'd2; + end + 2'd3: begin + main_sram88_source_payload_last_be <= 3'd4; + end + 3'd4: begin + main_sram88_source_payload_last_be <= 4'd8; + end + 3'd5: begin + main_sram88_source_payload_last_be <= 5'd16; + end + 3'd6: begin + main_sram88_source_payload_last_be <= 6'd32; + end + 3'd7: begin + main_sram88_source_payload_last_be <= 7'd64; + end + default: begin + main_sram88_source_payload_last_be <= 4'd8; + end + endcase + end +end +assign main_sram163_re = main_read; +assign main_sram161_adr = main_sram122_length[10:2]; +assign main_sram166_re = main_read; +assign main_sram164_adr = main_sram122_length[10:2]; +always @(*) begin + main_rd_data <= 32'd0; + case (main_sram133_source_payload_slot) + 1'd0: begin + main_rd_data <= main_sram162_dat_r; + end + 1'd1: begin + main_rd_data <= main_sram165_dat_r; + end + endcase +end +assign main_sram87_source_payload_data = main_rd_data; +assign main_sram109_event0 = main_sram105_status; +assign main_sram113_event0 = main_sram106_pending; +always @(*) begin + main_sram108_clear <= 1'd0; + if ((main_sram116_re & main_sram117_r)) begin + main_sram108_clear <= 1'd1; + end +end +assign main_sram104_irq = (main_sram114_status & main_sram119_storage); +assign main_sram105_status = 1'd0; +assign main_sram139_din = {main_sram155_fifo_in_last, main_sram154_fifo_in_first, main_sram153_fifo_in_payload_length, main_sram152_fifo_in_payload_slot}; +assign {main_sram159_fifo_out_last, main_sram158_fifo_out_first, main_sram157_fifo_out_payload_length, main_sram156_fifo_out_payload_slot} = main_sram140_dout; +assign main_sram124_sink_ready = main_sram136_writable; +assign main_sram135_we = main_sram123_sink_valid; +assign main_sram154_fifo_in_first = main_sram125_sink_first; +assign main_sram155_fifo_in_last = main_sram126_sink_last; +assign main_sram152_fifo_in_payload_slot = main_sram127_sink_payload_slot; +assign main_sram153_fifo_in_payload_length = main_sram128_sink_payload_length; +assign main_sram129_source_valid = main_sram138_readable; +assign main_sram131_source_first = main_sram158_fifo_out_first; +assign main_sram132_source_last = main_sram159_fifo_out_last; +assign main_sram133_source_payload_slot = main_sram156_fifo_out_payload_slot; +assign main_sram134_source_payload_length = main_sram157_fifo_out_payload_length; +assign main_sram137_re = main_sram130_source_ready; +always @(*) begin + main_sram145_adr <= 1'd0; + if (main_sram142_replace) begin + main_sram145_adr <= (main_sram143_produce - 1'd1); + end else begin + main_sram145_adr <= main_sram143_produce; + end +end +assign main_sram148_dat_w = main_sram139_din; +assign main_sram147_we = (main_sram135_we & (main_sram136_writable | main_sram142_replace)); +assign main_sram149_do_read = (main_sram138_readable & main_sram137_re); +assign main_sram150_adr = main_sram144_consume; +assign main_sram140_dout = main_sram151_dat_r; +assign main_sram136_writable = (main_sram141_level != 2'd2); +assign main_sram138_readable = (main_sram141_level != 1'd0); +always @(*) begin + builder_liteethmacsramreader_next_state <= 2'd0; + main_read <= 1'd0; + main_sram107_trigger <= 1'd0; + main_sram122_length_liteethmacsramreader_next_value <= 11'd0; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd0; + main_sram130_source_ready <= 1'd0; + main_sram83_source_valid <= 1'd0; + main_sram86_source_last <= 1'd0; + builder_liteethmacsramreader_next_state <= builder_liteethmacsramreader_state; + case (builder_liteethmacsramreader_state) + 1'd1: begin + main_sram83_source_valid <= 1'd1; + main_sram86_source_last <= (main_sram122_length >= main_sram134_source_payload_length); + if (main_sram84_source_ready) begin + main_read <= 1'd1; + main_sram122_length_liteethmacsramreader_next_value <= (main_sram122_length + 3'd4); + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + if (main_sram86_source_last) begin + builder_liteethmacsramreader_next_state <= 2'd2; + end + end + end + 2'd2: begin + main_sram122_length_liteethmacsramreader_next_value <= 1'd0; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + main_sram107_trigger <= 1'd1; + main_sram130_source_ready <= 1'd1; + builder_liteethmacsramreader_next_state <= 1'd0; + end + default: begin + if (main_sram129_source_valid) begin + main_read <= 1'd1; + main_sram122_length_liteethmacsramreader_next_value <= 3'd4; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + builder_liteethmacsramreader_next_state <= 1'd1; + end + end + endcase +end +assign main_sram167_irq = (main_sram16_irq | main_sram104_irq); +assign main_sram0_adr = main_interface0_adr[8:0]; +assign main_interface0_dat_r = main_sram0_dat_r; +assign main_sram1_adr = main_interface1_adr[8:0]; +assign main_interface1_dat_r = main_sram1_dat_r; +always @(*) begin + main_sram2_we <= 4'd0; + main_sram2_we[0] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[0]); + main_sram2_we[1] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[1]); + main_sram2_we[2] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[2]); + main_sram2_we[3] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[3]); +end +assign main_sram2_adr = main_interface2_adr[8:0]; +assign main_interface2_dat_r = main_sram2_dat_r; +assign main_sram2_dat_w = main_interface2_dat_w; +always @(*) begin + main_sram3_we <= 4'd0; + main_sram3_we[0] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[0]); + main_sram3_we[1] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[1]); + main_sram3_we[2] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[2]); + main_sram3_we[3] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[3]); +end +assign main_sram3_adr = main_interface3_adr[8:0]; +assign main_interface3_dat_r = main_sram3_dat_r; +assign main_sram3_dat_w = main_interface3_dat_w; +always @(*) begin + main_slave_sel <= 4'd0; + main_slave_sel[0] <= (main_bus_adr[10:9] == 1'd0); + main_slave_sel[1] <= (main_bus_adr[10:9] == 1'd1); + main_slave_sel[2] <= (main_bus_adr[10:9] == 2'd2); + main_slave_sel[3] <= (main_bus_adr[10:9] == 2'd3); +end +assign main_interface0_adr = main_bus_adr; +assign main_interface0_dat_w = main_bus_dat_w; +assign main_interface0_sel = main_bus_sel; +assign main_interface0_stb = main_bus_stb; +assign main_interface0_we = main_bus_we; +assign main_interface0_cti = main_bus_cti; +assign main_interface0_bte = main_bus_bte; +assign main_interface1_adr = main_bus_adr; +assign main_interface1_dat_w = main_bus_dat_w; +assign main_interface1_sel = main_bus_sel; +assign main_interface1_stb = main_bus_stb; +assign main_interface1_we = main_bus_we; +assign main_interface1_cti = main_bus_cti; +assign main_interface1_bte = main_bus_bte; +assign main_interface2_adr = main_bus_adr; +assign main_interface2_dat_w = main_bus_dat_w; +assign main_interface2_sel = main_bus_sel; +assign main_interface2_stb = main_bus_stb; +assign main_interface2_we = main_bus_we; +assign main_interface2_cti = main_bus_cti; +assign main_interface2_bte = main_bus_bte; +assign main_interface3_adr = main_bus_adr; +assign main_interface3_dat_w = main_bus_dat_w; +assign main_interface3_sel = main_bus_sel; +assign main_interface3_stb = main_bus_stb; +assign main_interface3_we = main_bus_we; +assign main_interface3_cti = main_bus_cti; +assign main_interface3_bte = main_bus_bte; +assign main_interface0_cyc = (main_bus_cyc & main_slave_sel[0]); +assign main_interface1_cyc = (main_bus_cyc & main_slave_sel[1]); +assign main_interface2_cyc = (main_bus_cyc & main_slave_sel[2]); +assign main_interface3_cyc = (main_bus_cyc & main_slave_sel[3]); +assign main_bus_ack = (((main_interface0_ack | main_interface1_ack) | main_interface2_ack) | main_interface3_ack); +assign main_bus_err = (((main_interface0_err | main_interface1_err) | main_interface2_err) | main_interface3_err); +assign main_bus_dat_r = (((({32{main_slave_sel_r[0]}} & main_interface0_dat_r) | ({32{main_slave_sel_r[1]}} & main_interface1_dat_r)) | ({32{main_slave_sel_r[2]}} & main_interface2_dat_r)) | ({32{main_slave_sel_r[3]}} & main_interface3_dat_r)); +always @(*) begin + builder_interface0_ack <= 1'd0; + builder_interface0_dat_r <= 32'd0; + builder_interface1_adr <= 14'd0; + builder_interface1_dat_w <= 32'd0; + builder_interface1_we <= 1'd0; + builder_next_state <= 1'd0; + builder_next_state <= builder_state; + case (builder_state) + 1'd1: begin + builder_interface0_ack <= 1'd1; + builder_interface0_dat_r <= builder_interface1_dat_r; + builder_next_state <= 1'd0; + end + default: begin + builder_interface1_dat_w <= builder_interface0_dat_w; + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_adr <= builder_interface0_adr[29:0]; + builder_interface1_we <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); + builder_next_state <= 1'd1; + end + end + endcase end -assign builder_done = (builder_count == 1'd0); assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); assign builder_csrbank0_reset0_r = builder_interface0_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank0_reset0_re <= 1'd0; - builder_csrbank0_reset0_we <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank0_reset0_re <= builder_interface0_bank_bus_we; - builder_csrbank0_reset0_we <= (~builder_interface0_bank_bus_we); - end + builder_csrbank0_reset0_re <= 1'd0; + builder_csrbank0_reset0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_reset0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_reset0_we <= (~builder_interface0_bank_bus_we); + end end assign builder_csrbank0_scratch0_r = builder_interface0_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank0_scratch0_we <= 1'd0; - builder_csrbank0_scratch0_re <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_scratch0_re <= builder_interface0_bank_bus_we; - builder_csrbank0_scratch0_we <= (~builder_interface0_bank_bus_we); - end + builder_csrbank0_scratch0_re <= 1'd0; + builder_csrbank0_scratch0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_scratch0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_scratch0_we <= (~builder_interface0_bank_bus_we); + end end assign builder_csrbank0_bus_errors_r = builder_interface0_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank0_bus_errors_re <= 1'd0; - builder_csrbank0_bus_errors_we <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank0_bus_errors_re <= builder_interface0_bank_bus_we; - builder_csrbank0_bus_errors_we <= (~builder_interface0_bank_bus_we); - end + builder_csrbank0_bus_errors_re <= 1'd0; + builder_csrbank0_bus_errors_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank0_bus_errors_re <= builder_interface0_bank_bus_we; + builder_csrbank0_bus_errors_we <= (~builder_interface0_bank_bus_we); + end end always @(*) begin - main_maccore_maccore_soc_rst <= 1'd0; - if (main_maccore_maccore_reset_re) begin - main_maccore_maccore_soc_rst <= main_maccore_maccore_reset_storage[0]; - end + main_maccore_soc_rst <= 1'd0; + if (main_maccore_reset_re) begin + main_maccore_soc_rst <= main_maccore_reset_storage[0]; + end end -assign main_maccore_maccore_cpu_rst = main_maccore_maccore_reset_storage[1]; -assign builder_csrbank0_reset0_w = main_maccore_maccore_reset_storage[1:0]; -assign builder_csrbank0_scratch0_w = main_maccore_maccore_scratch_storage[31:0]; -assign builder_csrbank0_bus_errors_w = main_maccore_maccore_bus_errors_status[31:0]; -assign main_maccore_maccore_bus_errors_we = builder_csrbank0_bus_errors_we; +assign main_maccore_cpu_rst = main_maccore_reset_storage[1]; +assign builder_csrbank0_reset0_w = main_maccore_reset_storage[1:0]; +assign builder_csrbank0_scratch0_w = main_maccore_scratch_storage[31:0]; +assign builder_csrbank0_bus_errors_w = main_maccore_bus_errors_status[31:0]; +assign main_maccore_bus_errors_we = builder_csrbank0_bus_errors_we; assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2); assign builder_csrbank1_sram_writer_slot_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_slot_we <= 1'd0; - builder_csrbank1_sram_writer_slot_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_sram_writer_slot_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_slot_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_writer_slot_re <= 1'd0; + builder_csrbank1_sram_writer_slot_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_sram_writer_slot_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_slot_we <= (~builder_interface1_bank_bus_we); + end end -assign builder_csrbank1_sram_writer_length_r = builder_interface1_bank_bus_dat_w[31:0]; +assign builder_csrbank1_sram_writer_length_r = builder_interface1_bank_bus_dat_w[10:0]; always @(*) begin - builder_csrbank1_sram_writer_length_re <= 1'd0; - builder_csrbank1_sram_writer_length_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_sram_writer_length_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_length_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_writer_length_re <= 1'd0; + builder_csrbank1_sram_writer_length_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_sram_writer_length_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_length_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_writer_errors_r = builder_interface1_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank1_sram_writer_errors_re <= 1'd0; - builder_csrbank1_sram_writer_errors_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_sram_writer_errors_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_errors_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_writer_errors_re <= 1'd0; + builder_csrbank1_sram_writer_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_sram_writer_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_errors_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_writer_ev_status_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_ev_status_we <= 1'd0; - builder_csrbank1_sram_writer_ev_status_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank1_sram_writer_ev_status_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_ev_status_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_writer_ev_status_re <= 1'd0; + builder_csrbank1_sram_writer_ev_status_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank1_sram_writer_ev_status_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_status_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_writer_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_ev_pending_we <= 1'd0; - builder_csrbank1_sram_writer_ev_pending_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank1_sram_writer_ev_pending_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_ev_pending_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_writer_ev_pending_re <= 1'd0; + builder_csrbank1_sram_writer_ev_pending_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank1_sram_writer_ev_pending_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_pending_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_writer_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_ev_enable0_re <= 1'd0; - builder_csrbank1_sram_writer_ev_enable0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - builder_csrbank1_sram_writer_ev_enable0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_ev_enable0_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_writer_ev_enable0_re <= 1'd0; + builder_csrbank1_sram_writer_ev_enable0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank1_sram_writer_ev_enable0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_enable0_we <= (~builder_interface1_bank_bus_we); + end end -assign main_reader_start_start_r = builder_interface1_bank_bus_dat_w[0]; +assign main_start_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_reader_start_start_re <= 1'd0; - main_reader_start_start_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_reader_start_start_re <= builder_interface1_bank_bus_we; - main_reader_start_start_we <= (~builder_interface1_bank_bus_we); - end + main_start_re <= 1'd0; + main_start_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_start_re <= builder_interface1_bank_bus_we; + main_start_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_ready_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ready_we <= 1'd0; - builder_csrbank1_sram_reader_ready_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin - builder_csrbank1_sram_reader_ready_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ready_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_ready_re <= 1'd0; + builder_csrbank1_sram_reader_ready_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank1_sram_reader_ready_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ready_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_level_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank1_sram_reader_level_we <= 1'd0; - builder_csrbank1_sram_reader_level_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - builder_csrbank1_sram_reader_level_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_level_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_level_re <= 1'd0; + builder_csrbank1_sram_reader_level_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + builder_csrbank1_sram_reader_level_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_level_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_slot0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_slot0_re <= 1'd0; - builder_csrbank1_sram_reader_slot0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - builder_csrbank1_sram_reader_slot0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_slot0_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_slot0_re <= 1'd0; + builder_csrbank1_sram_reader_slot0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank1_sram_reader_slot0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_slot0_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_length0_r = builder_interface1_bank_bus_dat_w[10:0]; always @(*) begin - builder_csrbank1_sram_reader_length0_re <= 1'd0; - builder_csrbank1_sram_reader_length0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - builder_csrbank1_sram_reader_length0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_length0_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_length0_re <= 1'd0; + builder_csrbank1_sram_reader_length0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank1_sram_reader_length0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_length0_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_ev_status_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ev_status_we <= 1'd0; - builder_csrbank1_sram_reader_ev_status_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank1_sram_reader_ev_status_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ev_status_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_ev_status_re <= 1'd0; + builder_csrbank1_sram_reader_ev_status_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank1_sram_reader_ev_status_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_status_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ev_pending_re <= 1'd0; - builder_csrbank1_sram_reader_ev_pending_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank1_sram_reader_ev_pending_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ev_pending_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_ev_pending_re <= 1'd0; + builder_csrbank1_sram_reader_ev_pending_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank1_sram_reader_ev_pending_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_pending_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ev_enable0_re <= 1'd0; - builder_csrbank1_sram_reader_ev_enable0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin - builder_csrbank1_sram_reader_ev_enable0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ev_enable0_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_ev_enable0_re <= 1'd0; + builder_csrbank1_sram_reader_ev_enable0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank1_sram_reader_ev_enable0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_enable0_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_preamble_crc_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_preamble_crc_we <= 1'd0; - builder_csrbank1_preamble_crc_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin - builder_csrbank1_preamble_crc_re <= builder_interface1_bank_bus_we; - builder_csrbank1_preamble_crc_we <= (~builder_interface1_bank_bus_we); - end -end -assign builder_csrbank1_preamble_errors_r = builder_interface1_bank_bus_dat_w[31:0]; -always @(*) begin - builder_csrbank1_preamble_errors_re <= 1'd0; - builder_csrbank1_preamble_errors_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin - builder_csrbank1_preamble_errors_re <= builder_interface1_bank_bus_we; - builder_csrbank1_preamble_errors_we <= (~builder_interface1_bank_bus_we); - end -end -assign builder_csrbank1_crc_errors_r = builder_interface1_bank_bus_dat_w[31:0]; -always @(*) begin - builder_csrbank1_crc_errors_re <= 1'd0; - builder_csrbank1_crc_errors_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin - builder_csrbank1_crc_errors_re <= builder_interface1_bank_bus_we; - builder_csrbank1_crc_errors_we <= (~builder_interface1_bank_bus_we); - end -end -assign builder_csrbank1_sram_writer_slot_w = main_writer_slot_status; -assign main_writer_slot_we = builder_csrbank1_sram_writer_slot_we; -assign builder_csrbank1_sram_writer_length_w = main_writer_length_status[31:0]; -assign main_writer_length_we = builder_csrbank1_sram_writer_length_we; -assign builder_csrbank1_sram_writer_errors_w = main_writer_errors_status[31:0]; -assign main_writer_errors_we = builder_csrbank1_sram_writer_errors_we; -assign main_writer_status_status = main_writer_available0; -assign builder_csrbank1_sram_writer_ev_status_w = main_writer_status_status; -assign main_writer_status_we = builder_csrbank1_sram_writer_ev_status_we; -assign main_writer_pending_status = main_writer_available1; -assign builder_csrbank1_sram_writer_ev_pending_w = main_writer_pending_status; -assign main_writer_pending_we = builder_csrbank1_sram_writer_ev_pending_we; -assign main_writer_available2 = main_writer_enable_storage; -assign builder_csrbank1_sram_writer_ev_enable0_w = main_writer_enable_storage; -assign builder_csrbank1_sram_reader_ready_w = main_reader_ready_status; -assign main_reader_ready_we = builder_csrbank1_sram_reader_ready_we; -assign builder_csrbank1_sram_reader_level_w = main_reader_level_status[1:0]; -assign main_reader_level_we = builder_csrbank1_sram_reader_level_we; -assign builder_csrbank1_sram_reader_slot0_w = main_reader_slot_storage; -assign builder_csrbank1_sram_reader_length0_w = main_reader_length_storage[10:0]; -assign main_reader_status_status = main_reader_event00; -assign builder_csrbank1_sram_reader_ev_status_w = main_reader_status_status; -assign main_reader_status_we = builder_csrbank1_sram_reader_ev_status_we; -assign main_reader_pending_status = main_reader_event01; -assign builder_csrbank1_sram_reader_ev_pending_w = main_reader_pending_status; -assign main_reader_pending_we = builder_csrbank1_sram_reader_ev_pending_we; -assign main_reader_event02 = main_reader_enable_storage; -assign builder_csrbank1_sram_reader_ev_enable0_w = main_reader_enable_storage; -assign builder_csrbank1_preamble_crc_w = main_preamble_crc_status; -assign main_preamble_crc_we = builder_csrbank1_preamble_crc_we; -assign builder_csrbank1_preamble_errors_w = main_preamble_errors_status[31:0]; -assign main_preamble_errors_we = builder_csrbank1_preamble_errors_we; -assign builder_csrbank1_crc_errors_w = main_crc_errors_status[31:0]; -assign main_crc_errors_we = builder_csrbank1_crc_errors_we; + builder_csrbank1_preamble_crc_re <= 1'd0; + builder_csrbank1_preamble_crc_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin + builder_csrbank1_preamble_crc_re <= builder_interface1_bank_bus_we; + builder_csrbank1_preamble_crc_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_rx_datapath_preamble_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank1_rx_datapath_preamble_errors_re <= 1'd0; + builder_csrbank1_rx_datapath_preamble_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin + builder_csrbank1_rx_datapath_preamble_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rx_datapath_preamble_errors_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_rx_datapath_crc_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank1_rx_datapath_crc_errors_re <= 1'd0; + builder_csrbank1_rx_datapath_crc_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank1_rx_datapath_crc_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rx_datapath_crc_errors_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_slot_w = main_sram7_status; +assign main_sram8_we = builder_csrbank1_sram_writer_slot_we; +assign builder_csrbank1_sram_writer_length_w = main_sram10_status[10:0]; +assign main_sram11_we = builder_csrbank1_sram_writer_length_we; +assign builder_csrbank1_sram_writer_errors_w = main_sram13_status[31:0]; +assign main_sram14_we = builder_csrbank1_sram_writer_errors_we; +always @(*) begin + main_sram22_status <= 1'd0; + main_sram22_status <= main_sram21_available; +end +assign builder_csrbank1_sram_writer_ev_status_w = main_sram22_status; +assign main_sram23_we = builder_csrbank1_sram_writer_ev_status_we; +always @(*) begin + main_sram26_status <= 1'd0; + main_sram26_status <= main_sram25_available; +end +assign builder_csrbank1_sram_writer_ev_pending_w = main_sram26_status; +assign main_sram27_we = builder_csrbank1_sram_writer_ev_pending_we; +assign main_sram30_available = main_sram31_storage; +assign builder_csrbank1_sram_writer_ev_enable0_w = main_sram31_storage; +assign builder_csrbank1_sram_reader_ready_w = main_sram94_status; +assign main_sram95_we = builder_csrbank1_sram_reader_ready_we; +assign builder_csrbank1_sram_reader_level_w = main_sram97_status[1:0]; +assign main_sram98_we = builder_csrbank1_sram_reader_level_we; +assign builder_csrbank1_sram_reader_slot0_w = main_sram100_storage; +assign builder_csrbank1_sram_reader_length0_w = main_sram102_storage[10:0]; +always @(*) begin + main_sram110_status <= 1'd0; + main_sram110_status <= main_sram109_event0; +end +assign builder_csrbank1_sram_reader_ev_status_w = main_sram110_status; +assign main_sram111_we = builder_csrbank1_sram_reader_ev_status_we; +always @(*) begin + main_sram114_status <= 1'd0; + main_sram114_status <= main_sram113_event0; +end +assign builder_csrbank1_sram_reader_ev_pending_w = main_sram114_status; +assign main_sram115_we = builder_csrbank1_sram_reader_ev_pending_we; +assign main_sram118_event0 = main_sram119_storage; +assign builder_csrbank1_sram_reader_ev_enable0_w = main_sram119_storage; +assign builder_csrbank1_preamble_crc_w = main_status; +assign main_we = builder_csrbank1_preamble_crc_we; +assign builder_csrbank1_rx_datapath_preamble_errors_w = main_preamble_errors_status[31:0]; +assign main_preamble_errors_we = builder_csrbank1_rx_datapath_preamble_errors_we; +assign builder_csrbank1_rx_datapath_crc_errors_w = main_crc_errors_status[31:0]; +assign main_crc_errors_we = builder_csrbank1_rx_datapath_crc_errors_we; assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd1); assign builder_csrbank2_crg_reset0_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank2_crg_reset0_re <= 1'd0; - builder_csrbank2_crg_reset0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank2_crg_reset0_re <= builder_interface2_bank_bus_we; - builder_csrbank2_crg_reset0_we <= (~builder_interface2_bank_bus_we); - end + builder_csrbank2_crg_reset0_re <= 1'd0; + builder_csrbank2_crg_reset0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_crg_reset0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_crg_reset0_we <= (~builder_interface2_bank_bus_we); + end end assign builder_csrbank2_mdio_w0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - builder_csrbank2_mdio_w0_we <= 1'd0; - builder_csrbank2_mdio_w0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank2_mdio_w0_re <= builder_interface2_bank_bus_we; - builder_csrbank2_mdio_w0_we <= (~builder_interface2_bank_bus_we); - end + builder_csrbank2_mdio_w0_re <= 1'd0; + builder_csrbank2_mdio_w0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_mdio_w0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_mdio_w0_we <= (~builder_interface2_bank_bus_we); + end end assign builder_csrbank2_mdio_r_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank2_mdio_r_re <= 1'd0; - builder_csrbank2_mdio_r_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank2_mdio_r_re <= builder_interface2_bank_bus_we; - builder_csrbank2_mdio_r_we <= (~builder_interface2_bank_bus_we); - end -end -assign builder_csrbank2_crg_reset0_w = main_maccore_ethphy_reset_storage; -assign main_maccore_ethphy_mdc = main_maccore_ethphy__w_storage[0]; -assign main_maccore_ethphy_oe = main_maccore_ethphy__w_storage[1]; -assign main_maccore_ethphy_w = main_maccore_ethphy__w_storage[2]; -assign builder_csrbank2_mdio_w0_w = main_maccore_ethphy__w_storage[2:0]; -assign builder_csrbank2_mdio_r_w = main_maccore_ethphy__r_status; -assign main_maccore_ethphy__r_we = builder_csrbank2_mdio_r_we; -assign builder_csr_interconnect_adr = builder_maccore_adr; -assign builder_csr_interconnect_we = builder_maccore_we; -assign builder_csr_interconnect_dat_w = builder_maccore_dat_w; -assign builder_maccore_dat_r = builder_csr_interconnect_dat_r; -assign builder_interface0_bank_bus_adr = builder_csr_interconnect_adr; -assign builder_interface1_bank_bus_adr = builder_csr_interconnect_adr; -assign builder_interface2_bank_bus_adr = builder_csr_interconnect_adr; -assign builder_interface0_bank_bus_we = builder_csr_interconnect_we; -assign builder_interface1_bank_bus_we = builder_csr_interconnect_we; -assign builder_interface2_bank_bus_we = builder_csr_interconnect_we; -assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w; -assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w; -assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w; -assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); -always @(*) begin - builder_array_muxed0 <= 30'd0; - case (builder_grant) - default: begin - builder_array_muxed0 <= main_wb_bus_adr; - end - endcase -end -always @(*) begin - builder_array_muxed1 <= 32'd0; - case (builder_grant) - default: begin - builder_array_muxed1 <= main_wb_bus_dat_w; - end - endcase -end -always @(*) begin - builder_array_muxed2 <= 4'd0; - case (builder_grant) - default: begin - builder_array_muxed2 <= main_wb_bus_sel; - end - endcase -end -always @(*) begin - builder_array_muxed3 <= 1'd0; - case (builder_grant) - default: begin - builder_array_muxed3 <= main_wb_bus_cyc; - end - endcase -end -always @(*) begin - builder_array_muxed4 <= 1'd0; - case (builder_grant) - default: begin - builder_array_muxed4 <= main_wb_bus_stb; - end - endcase -end -always @(*) begin - builder_array_muxed5 <= 1'd0; - case (builder_grant) - default: begin - builder_array_muxed5 <= main_wb_bus_we; - end - endcase -end -always @(*) begin - builder_array_muxed6 <= 3'd0; - case (builder_grant) - default: begin - builder_array_muxed6 <= main_wb_bus_cti; - end - endcase -end -always @(*) begin - builder_array_muxed7 <= 2'd0; - case (builder_grant) - default: begin - builder_array_muxed7 <= main_wb_bus_bte; - end - endcase -end -always @(*) begin - main_maccore_ethphy__r_status <= 1'd0; - main_maccore_ethphy__r_status <= main_maccore_ethphy_r; - main_maccore_ethphy__r_status <= builder_xilinxmultiregimpl0_regs1; -end -assign main_ps_preamble_error_toggle_o = builder_xilinxmultiregimpl1_regs1; -assign main_ps_crc_error_toggle_o = builder_xilinxmultiregimpl2_regs1; -assign main_tx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl3_regs1; -assign main_tx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl4_regs1; -assign main_rx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl5_regs1; -assign main_rx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl6_regs1; + builder_csrbank2_mdio_r_re <= 1'd0; + builder_csrbank2_mdio_r_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank2_mdio_r_re <= builder_interface2_bank_bus_we; + builder_csrbank2_mdio_r_we <= (~builder_interface2_bank_bus_we); + end +end +assign builder_csrbank2_crg_reset0_w = main_maccore_crg_reset_storage; +assign main_maccore_mdc = main_maccore__w_storage[0]; +assign main_maccore_oe = main_maccore__w_storage[1]; +assign main_maccore_w = main_maccore__w_storage[2]; +assign builder_csrbank2_mdio_w0_w = main_maccore__w_storage[2:0]; +assign builder_csrbank2_mdio_r_w = main_maccore__r_status; +assign main_maccore__r_we = builder_csrbank2_mdio_r_we; +assign builder_adr = builder_interface1_adr; +assign builder_we = builder_interface1_we; +assign builder_dat_w = builder_interface1_dat_w; +assign builder_interface1_dat_r = builder_dat_r; +assign builder_interface0_bank_bus_adr = builder_adr; +assign builder_interface1_bank_bus_adr = builder_adr; +assign builder_interface2_bank_bus_adr = builder_adr; +assign builder_interface0_bank_bus_we = builder_we; +assign builder_interface1_bank_bus_we = builder_we; +assign builder_interface2_bank_bus_we = builder_we; +assign builder_interface0_bank_bus_dat_w = builder_dat_w; +assign builder_interface1_bank_bus_dat_w = builder_dat_w; +assign builder_interface2_bank_bus_dat_w = builder_dat_w; +assign builder_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); +assign builder_t_slice_proxy0 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy1 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy2 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy3 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy4 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy5 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy6 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy7 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy8 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy9 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy10 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy11 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy12 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy13 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy14 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy15 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy16 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy17 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy18 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy19 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy20 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy21 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy22 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy23 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy24 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy25 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy26 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy27 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy28 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy29 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy30 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy31 = (~main_tx_crc_crc_next); +assign builder_complexslicelowerer_slice_proxy = {main_tx_crc_value, main_tx_crc_sink_payload_data[7:0]}; +assign builder_t_slice_proxy32 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy33 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy34 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy35 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy36 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy37 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy38 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy39 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy40 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy41 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy42 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy43 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy44 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy45 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy46 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy47 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy48 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy49 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy50 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy51 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy52 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy53 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy54 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy55 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy56 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy57 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy58 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy59 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy60 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy61 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy62 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy63 = (~main_liteethmaccrc32checker_crc_crc_next); +always @(*) begin + builder_self0 <= 30'd0; + case (builder_grant) + default: begin + builder_self0 <= main_wb_bus_adr; + end + endcase +end +always @(*) begin + builder_self1 <= 32'd0; + case (builder_grant) + default: begin + builder_self1 <= main_wb_bus_dat_w; + end + endcase +end +always @(*) begin + builder_self2 <= 4'd0; + case (builder_grant) + default: begin + builder_self2 <= main_wb_bus_sel; + end + endcase +end +always @(*) begin + builder_self3 <= 1'd0; + case (builder_grant) + default: begin + builder_self3 <= main_wb_bus_cyc; + end + endcase +end +always @(*) begin + builder_self4 <= 1'd0; + case (builder_grant) + default: begin + builder_self4 <= main_wb_bus_stb; + end + endcase +end +always @(*) begin + builder_self5 <= 1'd0; + case (builder_grant) + default: begin + builder_self5 <= main_wb_bus_we; + end + endcase +end +always @(*) begin + builder_self6 <= 3'd0; + case (builder_grant) + default: begin + builder_self6 <= main_wb_bus_cti; + end + endcase +end +always @(*) begin + builder_self7 <= 2'd0; + case (builder_grant) + default: begin + builder_self7 <= main_wb_bus_bte; + end + endcase +end +always @(*) begin + main_maccore__r_status <= 1'd0; + main_maccore__r_status <= main_maccore_r; + main_maccore__r_status <= builder_xilinxmultiregimpl01; +end +assign main_tx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl11; +assign main_tx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl21; +assign main_pulsesynchronizer0_toggle_o = builder_xilinxmultiregimpl31; +assign main_pulsesynchronizer1_toggle_o = builder_xilinxmultiregimpl41; +assign main_rx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl51; +assign main_rx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl61; + + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ always @(posedge eth_rx_clk) begin - main_maccore_ethphy_liteethphymiirx_converter_reset <= (~mii_eth_rx_dv); - main_maccore_ethphy_liteethphymiirx_converter_sink_valid <= 1'd1; - main_maccore_ethphy_liteethphymiirx_converter_sink_payload_data <= mii_eth_rx_data; - if (main_maccore_ethphy_liteethphymiirx_converter_converter_source_ready) begin - main_maccore_ethphy_liteethphymiirx_converter_converter_strobe_all <= 1'd0; - end - if (main_maccore_ethphy_liteethphymiirx_converter_converter_load_part) begin - if (((main_maccore_ethphy_liteethphymiirx_converter_converter_demux == 1'd1) | main_maccore_ethphy_liteethphymiirx_converter_converter_sink_last)) begin - main_maccore_ethphy_liteethphymiirx_converter_converter_demux <= 1'd0; - main_maccore_ethphy_liteethphymiirx_converter_converter_strobe_all <= 1'd1; - end else begin - main_maccore_ethphy_liteethphymiirx_converter_converter_demux <= (main_maccore_ethphy_liteethphymiirx_converter_converter_demux + 1'd1); - end - end - if ((main_maccore_ethphy_liteethphymiirx_converter_converter_source_valid & main_maccore_ethphy_liteethphymiirx_converter_converter_source_ready)) begin - if ((main_maccore_ethphy_liteethphymiirx_converter_converter_sink_valid & main_maccore_ethphy_liteethphymiirx_converter_converter_sink_ready)) begin - main_maccore_ethphy_liteethphymiirx_converter_converter_source_first <= main_maccore_ethphy_liteethphymiirx_converter_converter_sink_first; - main_maccore_ethphy_liteethphymiirx_converter_converter_source_last <= main_maccore_ethphy_liteethphymiirx_converter_converter_sink_last; - end else begin - main_maccore_ethphy_liteethphymiirx_converter_converter_source_first <= 1'd0; - main_maccore_ethphy_liteethphymiirx_converter_converter_source_last <= 1'd0; - end - end else begin - if ((main_maccore_ethphy_liteethphymiirx_converter_converter_sink_valid & main_maccore_ethphy_liteethphymiirx_converter_converter_sink_ready)) begin - main_maccore_ethphy_liteethphymiirx_converter_converter_source_first <= (main_maccore_ethphy_liteethphymiirx_converter_converter_sink_first | main_maccore_ethphy_liteethphymiirx_converter_converter_source_first); - main_maccore_ethphy_liteethphymiirx_converter_converter_source_last <= (main_maccore_ethphy_liteethphymiirx_converter_converter_sink_last | main_maccore_ethphy_liteethphymiirx_converter_converter_source_last); - end - end - if (main_maccore_ethphy_liteethphymiirx_converter_converter_load_part) begin - case (main_maccore_ethphy_liteethphymiirx_converter_converter_demux) - 1'd0: begin - main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_data[3:0] <= main_maccore_ethphy_liteethphymiirx_converter_converter_sink_payload_data; - end - 1'd1: begin - main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_data[7:4] <= main_maccore_ethphy_liteethphymiirx_converter_converter_sink_payload_data; - end - endcase - end - if (main_maccore_ethphy_liteethphymiirx_converter_converter_load_part) begin - main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_valid_token_count <= (main_maccore_ethphy_liteethphymiirx_converter_converter_demux + 1'd1); - end - if (main_maccore_ethphy_liteethphymiirx_converter_reset) begin - main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_data <= 8'd0; - main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_valid_token_count <= 2'd0; - main_maccore_ethphy_liteethphymiirx_converter_converter_demux <= 1'd0; - main_maccore_ethphy_liteethphymiirx_converter_converter_strobe_all <= 1'd0; - end - builder_liteethmacpreamblechecker_state <= builder_liteethmacpreamblechecker_next_state; - if (main_liteethmaccrc32checker_crc_ce) begin - main_liteethmaccrc32checker_crc_reg <= main_liteethmaccrc32checker_crc_next; - end - if (main_liteethmaccrc32checker_crc_reset) begin - main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; - end - if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin - if ((main_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin - main_liteethmaccrc32checker_syncfifo_produce <= 1'd0; - end else begin - main_liteethmaccrc32checker_syncfifo_produce <= (main_liteethmaccrc32checker_syncfifo_produce + 1'd1); - end - end - if (main_liteethmaccrc32checker_syncfifo_do_read) begin - if ((main_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin - main_liteethmaccrc32checker_syncfifo_consume <= 1'd0; - end else begin - main_liteethmaccrc32checker_syncfifo_consume <= (main_liteethmaccrc32checker_syncfifo_consume + 1'd1); - end - end - if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin - if ((~main_liteethmaccrc32checker_syncfifo_do_read)) begin - main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level + 1'd1); - end - end else begin - if (main_liteethmaccrc32checker_syncfifo_do_read) begin - main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level - 1'd1); - end - end - if (main_liteethmaccrc32checker_fifo_reset) begin - main_liteethmaccrc32checker_syncfifo_level <= 3'd0; - main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; - main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; - end - builder_liteethmaccrc32checker_state <= builder_liteethmaccrc32checker_next_state; - if (((~main_crc32_checker_source_valid) | main_crc32_checker_source_ready)) begin - main_crc32_checker_source_valid <= main_crc32_checker_sink_valid; - main_crc32_checker_source_first <= main_crc32_checker_sink_first; - main_crc32_checker_source_last <= main_crc32_checker_sink_last; - main_crc32_checker_source_payload_data <= main_crc32_checker_sink_payload_data; - main_crc32_checker_source_payload_last_be <= main_crc32_checker_sink_payload_last_be; - main_crc32_checker_source_payload_error <= main_crc32_checker_sink_payload_error; - end - if (main_ps_preamble_error_i) begin - main_ps_preamble_error_toggle_i <= (~main_ps_preamble_error_toggle_i); - end - if (main_ps_crc_error_i) begin - main_ps_crc_error_toggle_i <= (~main_ps_crc_error_toggle_i); - end - if (main_rx_converter_converter_source_ready) begin - main_rx_converter_converter_strobe_all <= 1'd0; - end - if (main_rx_converter_converter_load_part) begin - if (((main_rx_converter_converter_demux == 2'd3) | main_rx_converter_converter_sink_last)) begin - main_rx_converter_converter_demux <= 1'd0; - main_rx_converter_converter_strobe_all <= 1'd1; - end else begin - main_rx_converter_converter_demux <= (main_rx_converter_converter_demux + 1'd1); - end - end - if ((main_rx_converter_converter_source_valid & main_rx_converter_converter_source_ready)) begin - if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin - main_rx_converter_converter_source_first <= main_rx_converter_converter_sink_first; - main_rx_converter_converter_source_last <= main_rx_converter_converter_sink_last; - end else begin - main_rx_converter_converter_source_first <= 1'd0; - main_rx_converter_converter_source_last <= 1'd0; - end - end else begin - if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin - main_rx_converter_converter_source_first <= (main_rx_converter_converter_sink_first | main_rx_converter_converter_source_first); - main_rx_converter_converter_source_last <= (main_rx_converter_converter_sink_last | main_rx_converter_converter_source_last); - end - end - if (main_rx_converter_converter_load_part) begin - case (main_rx_converter_converter_demux) - 1'd0: begin - main_rx_converter_converter_source_payload_data[9:0] <= main_rx_converter_converter_sink_payload_data; - end - 1'd1: begin - main_rx_converter_converter_source_payload_data[19:10] <= main_rx_converter_converter_sink_payload_data; - end - 2'd2: begin - main_rx_converter_converter_source_payload_data[29:20] <= main_rx_converter_converter_sink_payload_data; - end - 2'd3: begin - main_rx_converter_converter_source_payload_data[39:30] <= main_rx_converter_converter_sink_payload_data; - end - endcase - end - if (main_rx_converter_converter_load_part) begin - main_rx_converter_converter_source_payload_valid_token_count <= (main_rx_converter_converter_demux + 1'd1); - end - main_rx_cdc_cdc_graycounter0_q_binary <= main_rx_cdc_cdc_graycounter0_q_next_binary; - main_rx_cdc_cdc_graycounter0_q <= main_rx_cdc_cdc_graycounter0_q_next; - if (eth_rx_rst) begin - main_maccore_ethphy_liteethphymiirx_converter_sink_valid <= 1'd0; - main_maccore_ethphy_liteethphymiirx_converter_sink_payload_data <= 4'd0; - main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_data <= 8'd0; - main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_valid_token_count <= 2'd0; - main_maccore_ethphy_liteethphymiirx_converter_converter_demux <= 1'd0; - main_maccore_ethphy_liteethphymiirx_converter_converter_strobe_all <= 1'd0; - main_maccore_ethphy_liteethphymiirx_converter_reset <= 1'd0; - main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; - main_liteethmaccrc32checker_syncfifo_level <= 3'd0; - main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; - main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; - main_crc32_checker_source_valid <= 1'd0; - main_crc32_checker_source_payload_data <= 8'd0; - main_crc32_checker_source_payload_last_be <= 1'd0; - main_crc32_checker_source_payload_error <= 1'd0; - main_rx_converter_converter_source_payload_data <= 40'd0; - main_rx_converter_converter_source_payload_valid_token_count <= 3'd0; - main_rx_converter_converter_demux <= 2'd0; - main_rx_converter_converter_strobe_all <= 1'd0; - main_rx_cdc_cdc_graycounter0_q <= 6'd0; - main_rx_cdc_cdc_graycounter0_q_binary <= 6'd0; - builder_liteethmacpreamblechecker_state <= 1'd0; - builder_liteethmaccrc32checker_state <= 2'd0; - end - builder_xilinxmultiregimpl6_regs0 <= main_rx_cdc_cdc_graycounter1_q; - builder_xilinxmultiregimpl6_regs1 <= builder_xilinxmultiregimpl6_regs0; + main_maccore_liteethphymiirx_reset <= (~mii_rx_dv); + main_maccore_liteethphymiirx_converter_sink_valid <= 1'd1; + main_maccore_liteethphymiirx_converter_sink_payload_data <= mii_rx_data; + if (main_maccore_liteethphymiirx_converter_source_ready) begin + main_maccore_liteethphymiirx_converter_strobe_all <= 1'd0; + end + if (main_maccore_liteethphymiirx_converter_load_part) begin + if (((main_maccore_liteethphymiirx_converter_demux == 1'd1) | main_maccore_liteethphymiirx_converter_sink_last)) begin + main_maccore_liteethphymiirx_converter_demux <= 1'd0; + main_maccore_liteethphymiirx_converter_strobe_all <= 1'd1; + end else begin + main_maccore_liteethphymiirx_converter_demux <= (main_maccore_liteethphymiirx_converter_demux + 1'd1); + end + end + if ((main_maccore_liteethphymiirx_converter_source_valid & main_maccore_liteethphymiirx_converter_source_ready)) begin + if ((main_maccore_liteethphymiirx_converter_sink_valid & main_maccore_liteethphymiirx_converter_sink_ready)) begin + main_maccore_liteethphymiirx_converter_source_first <= main_maccore_liteethphymiirx_converter_sink_first; + main_maccore_liteethphymiirx_converter_source_last <= main_maccore_liteethphymiirx_converter_sink_last; + end else begin + main_maccore_liteethphymiirx_converter_source_first <= 1'd0; + main_maccore_liteethphymiirx_converter_source_last <= 1'd0; + end + end else begin + if ((main_maccore_liteethphymiirx_converter_sink_valid & main_maccore_liteethphymiirx_converter_sink_ready)) begin + main_maccore_liteethphymiirx_converter_source_first <= (main_maccore_liteethphymiirx_converter_sink_first | main_maccore_liteethphymiirx_converter_source_first); + main_maccore_liteethphymiirx_converter_source_last <= (main_maccore_liteethphymiirx_converter_sink_last | main_maccore_liteethphymiirx_converter_source_last); + end + end + if (main_maccore_liteethphymiirx_converter_load_part) begin + case (main_maccore_liteethphymiirx_converter_demux) + 1'd0: begin + main_maccore_liteethphymiirx_converter_source_payload_data[3:0] <= main_maccore_liteethphymiirx_converter_sink_payload_data; + end + 1'd1: begin + main_maccore_liteethphymiirx_converter_source_payload_data[7:4] <= main_maccore_liteethphymiirx_converter_sink_payload_data; + end + endcase + end + if (main_maccore_liteethphymiirx_converter_load_part) begin + main_maccore_liteethphymiirx_converter_source_payload_valid_token_count <= (main_maccore_liteethphymiirx_converter_demux + 1'd1); + end + if (main_maccore_liteethphymiirx_reset) begin + main_maccore_liteethphymiirx_converter_source_payload_data <= 8'd0; + main_maccore_liteethphymiirx_converter_source_payload_valid_token_count <= 2'd0; + main_maccore_liteethphymiirx_converter_demux <= 1'd0; + main_maccore_liteethphymiirx_converter_strobe_all <= 1'd0; + end + builder_rxdatapath_liteethmacpreamblechecker_state <= builder_rxdatapath_liteethmacpreamblechecker_next_state; + if (main_pulsesynchronizer0_i) begin + main_pulsesynchronizer0_toggle_i <= (~main_pulsesynchronizer0_toggle_i); + end + if (main_liteethmaccrc32checker_crc_ce) begin + main_liteethmaccrc32checker_crc_reg <= main_liteethmaccrc32checker_crc_crc_next; + end + if (main_liteethmaccrc32checker_crc_reset) begin + main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + end + if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin + if ((main_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin + main_liteethmaccrc32checker_syncfifo_produce <= 1'd0; + end else begin + main_liteethmaccrc32checker_syncfifo_produce <= (main_liteethmaccrc32checker_syncfifo_produce + 1'd1); + end + end + if (main_liteethmaccrc32checker_syncfifo_do_read) begin + if ((main_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin + main_liteethmaccrc32checker_syncfifo_consume <= 1'd0; + end else begin + main_liteethmaccrc32checker_syncfifo_consume <= (main_liteethmaccrc32checker_syncfifo_consume + 1'd1); + end + end + if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin + if ((~main_liteethmaccrc32checker_syncfifo_do_read)) begin + main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level + 1'd1); + end + end else begin + if (main_liteethmaccrc32checker_syncfifo_do_read) begin + main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level - 1'd1); + end + end + if (main_liteethmaccrc32checker_fifo_reset) begin + main_liteethmaccrc32checker_syncfifo_level <= 3'd0; + main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + end + builder_rxdatapath_bufferizeendpoints_state <= builder_rxdatapath_bufferizeendpoints_next_state; + if (main_liteethmaccrc32checker_last_be_next_value_ce0) begin + main_liteethmaccrc32checker_last_be <= main_liteethmaccrc32checker_last_be_next_value0; + end + if (main_liteethmaccrc32checker_crc_error1_next_value_ce1) begin + main_liteethmaccrc32checker_crc_error1 <= main_liteethmaccrc32checker_crc_error1_next_value1; + end + if (((~main_bufferizeendpoints_pipe_valid_source_valid) | main_bufferizeendpoints_pipe_valid_source_ready)) begin + main_bufferizeendpoints_pipe_valid_source_valid <= main_bufferizeendpoints_pipe_valid_sink_valid; + main_bufferizeendpoints_pipe_valid_source_first <= main_bufferizeendpoints_pipe_valid_sink_first; + main_bufferizeendpoints_pipe_valid_source_last <= main_bufferizeendpoints_pipe_valid_sink_last; + main_bufferizeendpoints_pipe_valid_source_payload_data <= main_bufferizeendpoints_pipe_valid_sink_payload_data; + main_bufferizeendpoints_pipe_valid_source_payload_last_be <= main_bufferizeendpoints_pipe_valid_sink_payload_last_be; + main_bufferizeendpoints_pipe_valid_source_payload_error <= main_bufferizeendpoints_pipe_valid_sink_payload_error; + end + if (main_pulsesynchronizer1_i) begin + main_pulsesynchronizer1_toggle_i <= (~main_pulsesynchronizer1_toggle_i); + end + if (main_rx_converter_converter_source_ready) begin + main_rx_converter_converter_strobe_all <= 1'd0; + end + if (main_rx_converter_converter_load_part) begin + if (((main_rx_converter_converter_demux == 2'd3) | main_rx_converter_converter_sink_last)) begin + main_rx_converter_converter_demux <= 1'd0; + main_rx_converter_converter_strobe_all <= 1'd1; + end else begin + main_rx_converter_converter_demux <= (main_rx_converter_converter_demux + 1'd1); + end + end + if ((main_rx_converter_converter_source_valid & main_rx_converter_converter_source_ready)) begin + if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin + main_rx_converter_converter_source_first <= main_rx_converter_converter_sink_first; + main_rx_converter_converter_source_last <= main_rx_converter_converter_sink_last; + end else begin + main_rx_converter_converter_source_first <= 1'd0; + main_rx_converter_converter_source_last <= 1'd0; + end + end else begin + if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin + main_rx_converter_converter_source_first <= (main_rx_converter_converter_sink_first | main_rx_converter_converter_source_first); + main_rx_converter_converter_source_last <= (main_rx_converter_converter_sink_last | main_rx_converter_converter_source_last); + end + end + if (main_rx_converter_converter_load_part) begin + case (main_rx_converter_converter_demux) + 1'd0: begin + main_rx_converter_converter_source_payload_data[9:0] <= main_rx_converter_converter_sink_payload_data; + end + 1'd1: begin + main_rx_converter_converter_source_payload_data[19:10] <= main_rx_converter_converter_sink_payload_data; + end + 2'd2: begin + main_rx_converter_converter_source_payload_data[29:20] <= main_rx_converter_converter_sink_payload_data; + end + 2'd3: begin + main_rx_converter_converter_source_payload_data[39:30] <= main_rx_converter_converter_sink_payload_data; + end + endcase + end + if (main_rx_converter_converter_load_part) begin + main_rx_converter_converter_source_payload_valid_token_count <= (main_rx_converter_converter_demux + 1'd1); + end + main_rx_cdc_cdc_graycounter0_q_binary <= main_rx_cdc_cdc_graycounter0_q_next_binary; + main_rx_cdc_cdc_graycounter0_q <= main_rx_cdc_cdc_graycounter0_q_next; + if (eth_rx_rst) begin + main_maccore_liteethphymiirx_converter_sink_valid <= 1'd0; + main_maccore_liteethphymiirx_converter_sink_payload_data <= 4'd0; + main_maccore_liteethphymiirx_converter_source_payload_data <= 8'd0; + main_maccore_liteethphymiirx_converter_source_payload_valid_token_count <= 2'd0; + main_maccore_liteethphymiirx_converter_demux <= 1'd0; + main_maccore_liteethphymiirx_converter_strobe_all <= 1'd0; + main_maccore_liteethphymiirx_reset <= 1'd0; + main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + main_liteethmaccrc32checker_syncfifo_level <= 3'd0; + main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + main_liteethmaccrc32checker_last_be <= 1'd0; + main_liteethmaccrc32checker_crc_error1 <= 1'd0; + main_bufferizeendpoints_pipe_valid_source_valid <= 1'd0; + main_bufferizeendpoints_pipe_valid_source_payload_data <= 8'd0; + main_bufferizeendpoints_pipe_valid_source_payload_last_be <= 1'd0; + main_bufferizeendpoints_pipe_valid_source_payload_error <= 1'd0; + main_rx_converter_converter_source_payload_data <= 40'd0; + main_rx_converter_converter_source_payload_valid_token_count <= 3'd0; + main_rx_converter_converter_demux <= 2'd0; + main_rx_converter_converter_strobe_all <= 1'd0; + main_rx_cdc_cdc_graycounter0_q <= 6'd0; + main_rx_cdc_cdc_graycounter0_q_binary <= 6'd0; + builder_rxdatapath_liteethmacpreamblechecker_state <= 1'd0; + builder_rxdatapath_bufferizeendpoints_state <= 2'd0; + end + builder_xilinxmultiregimpl60 <= main_rx_cdc_cdc_graycounter1_q; + builder_xilinxmultiregimpl61 <= builder_xilinxmultiregimpl60; end always @(posedge eth_tx_clk) begin - mii_eth_tx_en <= main_maccore_ethphy_liteethphymiitx_converter_source_valid; - mii_eth_tx_data <= main_maccore_ethphy_liteethphymiitx_converter_source_payload_data; - if ((main_maccore_ethphy_liteethphymiitx_converter_converter_source_valid & main_maccore_ethphy_liteethphymiitx_converter_converter_source_ready)) begin - if (main_maccore_ethphy_liteethphymiitx_converter_converter_last) begin - main_maccore_ethphy_liteethphymiitx_converter_converter_mux <= 1'd0; - end else begin - main_maccore_ethphy_liteethphymiitx_converter_converter_mux <= (main_maccore_ethphy_liteethphymiitx_converter_converter_mux + 1'd1); - end - end - builder_liteethmacgap_state <= builder_liteethmacgap_next_state; - if (main_tx_gap_inserter_counter_liteethmacgap_next_value_ce) begin - main_tx_gap_inserter_counter <= main_tx_gap_inserter_counter_liteethmacgap_next_value; - end - builder_liteethmacpreambleinserter_state <= builder_liteethmacpreambleinserter_next_state; - if (main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce) begin - main_preamble_inserter_count <= main_preamble_inserter_count_liteethmacpreambleinserter_next_value; - end - if (main_liteethmaccrc32inserter_is_ongoing0) begin - main_liteethmaccrc32inserter_cnt <= 2'd3; - end else begin - if ((main_liteethmaccrc32inserter_is_ongoing1 & (~main_liteethmaccrc32inserter_cnt_done))) begin - main_liteethmaccrc32inserter_cnt <= (main_liteethmaccrc32inserter_cnt - main_liteethmaccrc32inserter_source_ready); - end - end - if (main_liteethmaccrc32inserter_ce) begin - main_liteethmaccrc32inserter_reg <= main_liteethmaccrc32inserter_next; - end - if (main_liteethmaccrc32inserter_reset) begin - main_liteethmaccrc32inserter_reg <= 32'd4294967295; - end - builder_liteethmaccrc32inserter_state <= builder_liteethmaccrc32inserter_next_state; - if (((~main_crc32_inserter_source_valid) | main_crc32_inserter_source_ready)) begin - main_crc32_inserter_source_valid <= main_crc32_inserter_sink_valid; - main_crc32_inserter_source_first <= main_crc32_inserter_sink_first; - main_crc32_inserter_source_last <= main_crc32_inserter_sink_last; - main_crc32_inserter_source_payload_data <= main_crc32_inserter_sink_payload_data; - main_crc32_inserter_source_payload_last_be <= main_crc32_inserter_sink_payload_last_be; - main_crc32_inserter_source_payload_error <= main_crc32_inserter_sink_payload_error; - end - builder_liteethmacpaddinginserter_state <= builder_liteethmacpaddinginserter_next_state; - if (main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce) begin - main_padding_inserter_counter <= main_padding_inserter_counter_liteethmacpaddinginserter_next_value; - end - builder_liteethmactxlastbe_state <= builder_liteethmactxlastbe_next_state; - if ((main_tx_converter_converter_source_valid & main_tx_converter_converter_source_ready)) begin - if (main_tx_converter_converter_last) begin - main_tx_converter_converter_mux <= 1'd0; - end else begin - main_tx_converter_converter_mux <= (main_tx_converter_converter_mux + 1'd1); - end - end - main_tx_cdc_cdc_graycounter1_q_binary <= main_tx_cdc_cdc_graycounter1_q_next_binary; - main_tx_cdc_cdc_graycounter1_q <= main_tx_cdc_cdc_graycounter1_q_next; - if (eth_tx_rst) begin - main_maccore_ethphy_liteethphymiitx_converter_converter_mux <= 1'd0; - main_liteethmaccrc32inserter_reg <= 32'd4294967295; - main_liteethmaccrc32inserter_cnt <= 2'd3; - main_crc32_inserter_source_valid <= 1'd0; - main_crc32_inserter_source_payload_data <= 8'd0; - main_crc32_inserter_source_payload_last_be <= 1'd0; - main_crc32_inserter_source_payload_error <= 1'd0; - main_padding_inserter_counter <= 16'd0; - main_tx_converter_converter_mux <= 2'd0; - main_tx_cdc_cdc_graycounter1_q <= 6'd0; - main_tx_cdc_cdc_graycounter1_q_binary <= 6'd0; - builder_liteethmacgap_state <= 1'd0; - builder_liteethmacpreambleinserter_state <= 2'd0; - builder_liteethmaccrc32inserter_state <= 2'd0; - builder_liteethmacpaddinginserter_state <= 1'd0; - builder_liteethmactxlastbe_state <= 1'd0; - end - builder_xilinxmultiregimpl3_regs0 <= main_tx_cdc_cdc_graycounter0_q; - builder_xilinxmultiregimpl3_regs1 <= builder_xilinxmultiregimpl3_regs0; + mii_tx_en <= main_maccore_liteethphymiitx_source_source_valid; + mii_tx_data <= main_maccore_liteethphymiitx_source_source_payload_data; + if ((main_maccore_liteethphymiitx_converter_source_valid & main_maccore_liteethphymiitx_converter_source_ready)) begin + if (main_maccore_liteethphymiitx_converter_last) begin + main_maccore_liteethphymiitx_converter_mux <= 1'd0; + end else begin + main_maccore_liteethphymiitx_converter_mux <= (main_maccore_liteethphymiitx_converter_mux + 1'd1); + end + end + main_tx_cdc_cdc_graycounter1_q_binary <= main_tx_cdc_cdc_graycounter1_q_next_binary; + main_tx_cdc_cdc_graycounter1_q <= main_tx_cdc_cdc_graycounter1_q_next; + if ((main_tx_converter_converter_source_valid & main_tx_converter_converter_source_ready)) begin + if (main_tx_converter_converter_last) begin + main_tx_converter_converter_mux <= 1'd0; + end else begin + main_tx_converter_converter_mux <= (main_tx_converter_converter_mux + 1'd1); + end + end + builder_txdatapath_liteethmactxlastbe_state <= builder_txdatapath_liteethmactxlastbe_next_state; + builder_txdatapath_liteethmacpaddinginserter_state <= builder_txdatapath_liteethmacpaddinginserter_next_state; + if (main_tx_padding_counter_clockdomainsrenamer0_next_value_ce) begin + main_tx_padding_counter <= main_tx_padding_counter_clockdomainsrenamer0_next_value; + end + if (main_tx_crc_is_ongoing0) begin + main_tx_crc_cnt <= 2'd3; + end else begin + if ((main_tx_crc_is_ongoing1 & (~main_tx_crc_cnt_done))) begin + main_tx_crc_cnt <= (main_tx_crc_cnt - main_tx_crc_source_ready); + end + end + if (main_tx_crc_ce) begin + main_tx_crc_reg <= main_tx_crc_crc_next; + end + if (main_tx_crc_reset) begin + main_tx_crc_reg <= 32'd4294967295; + end + builder_txdatapath_bufferizeendpoints_state <= builder_txdatapath_bufferizeendpoints_next_state; + if (main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0) begin + main_tx_crc_crc_packet <= main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0; + end + if (main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1) begin + main_tx_crc_last_be <= main_tx_crc_last_be_clockdomainsrenamer1_next_value1; + end + if (((~main_tx_crc_pipe_valid_source_valid) | main_tx_crc_pipe_valid_source_ready)) begin + main_tx_crc_pipe_valid_source_valid <= main_tx_crc_pipe_valid_sink_valid; + main_tx_crc_pipe_valid_source_first <= main_tx_crc_pipe_valid_sink_first; + main_tx_crc_pipe_valid_source_last <= main_tx_crc_pipe_valid_sink_last; + main_tx_crc_pipe_valid_source_payload_data <= main_tx_crc_pipe_valid_sink_payload_data; + main_tx_crc_pipe_valid_source_payload_last_be <= main_tx_crc_pipe_valid_sink_payload_last_be; + main_tx_crc_pipe_valid_source_payload_error <= main_tx_crc_pipe_valid_sink_payload_error; + end + builder_txdatapath_liteethmacpreambleinserter_state <= builder_txdatapath_liteethmacpreambleinserter_next_state; + if (main_tx_preamble_count_clockdomainsrenamer2_next_value_ce) begin + main_tx_preamble_count <= main_tx_preamble_count_clockdomainsrenamer2_next_value; + end + builder_txdatapath_liteethmacgap_state <= builder_txdatapath_liteethmacgap_next_state; + if (main_tx_gap_counter_clockdomainsrenamer3_next_value_ce) begin + main_tx_gap_counter <= main_tx_gap_counter_clockdomainsrenamer3_next_value; + end + if (eth_tx_rst) begin + main_maccore_liteethphymiitx_converter_mux <= 1'd0; + main_tx_cdc_cdc_graycounter1_q <= 6'd0; + main_tx_cdc_cdc_graycounter1_q_binary <= 6'd0; + main_tx_converter_converter_mux <= 2'd0; + main_tx_padding_counter <= 16'd0; + main_tx_crc_crc_packet <= 32'd0; + main_tx_crc_last_be <= 1'd0; + main_tx_crc_reg <= 32'd4294967295; + main_tx_crc_cnt <= 2'd3; + main_tx_crc_pipe_valid_source_valid <= 1'd0; + main_tx_crc_pipe_valid_source_payload_data <= 8'd0; + main_tx_crc_pipe_valid_source_payload_last_be <= 1'd0; + main_tx_crc_pipe_valid_source_payload_error <= 1'd0; + builder_txdatapath_liteethmactxlastbe_state <= 1'd0; + builder_txdatapath_liteethmacpaddinginserter_state <= 1'd0; + builder_txdatapath_bufferizeendpoints_state <= 2'd0; + builder_txdatapath_liteethmacpreambleinserter_state <= 2'd0; + builder_txdatapath_liteethmacgap_state <= 1'd0; + end + builder_xilinxmultiregimpl10 <= main_tx_cdc_cdc_graycounter0_q; + builder_xilinxmultiregimpl11 <= builder_xilinxmultiregimpl10; end always @(posedge por_clk) begin - main_maccore_int_rst <= sys_reset; + main_maccore_int_rst <= sys_reset; end always @(posedge sys_clk) begin - if ((main_maccore_maccore_bus_errors != 32'd4294967295)) begin - if (main_maccore_maccore_bus_error) begin - main_maccore_maccore_bus_errors <= (main_maccore_maccore_bus_errors + 1'd1); - end - end - if (main_maccore_ethphy_counter_ce) begin - main_maccore_ethphy_counter <= (main_maccore_ethphy_counter + 1'd1); - end - if (main_ps_preamble_error_o) begin - main_preamble_errors_status <= (main_preamble_errors_status + 1'd1); - end - if (main_ps_crc_error_o) begin - main_crc_errors_status <= (main_crc_errors_status + 1'd1); - end - main_ps_preamble_error_toggle_o_r <= main_ps_preamble_error_toggle_o; - main_ps_crc_error_toggle_o_r <= main_ps_crc_error_toggle_o; - main_tx_cdc_cdc_graycounter0_q_binary <= main_tx_cdc_cdc_graycounter0_q_next_binary; - main_tx_cdc_cdc_graycounter0_q <= main_tx_cdc_cdc_graycounter0_q_next; - main_rx_cdc_cdc_graycounter1_q_binary <= main_rx_cdc_cdc_graycounter1_q_next_binary; - main_rx_cdc_cdc_graycounter1_q <= main_rx_cdc_cdc_graycounter1_q_next; - if (main_writer_slot_ce) begin - main_writer_slot <= (main_writer_slot + 1'd1); - end - if (((main_writer_stat_fifo_syncfifo_we & main_writer_stat_fifo_syncfifo_writable) & (~main_writer_stat_fifo_replace))) begin - main_writer_stat_fifo_produce <= (main_writer_stat_fifo_produce + 1'd1); - end - if (main_writer_stat_fifo_do_read) begin - main_writer_stat_fifo_consume <= (main_writer_stat_fifo_consume + 1'd1); - end - if (((main_writer_stat_fifo_syncfifo_we & main_writer_stat_fifo_syncfifo_writable) & (~main_writer_stat_fifo_replace))) begin - if ((~main_writer_stat_fifo_do_read)) begin - main_writer_stat_fifo_level <= (main_writer_stat_fifo_level + 1'd1); - end - end else begin - if (main_writer_stat_fifo_do_read) begin - main_writer_stat_fifo_level <= (main_writer_stat_fifo_level - 1'd1); - end - end - builder_liteethmacsramwriter_state <= builder_liteethmacsramwriter_next_state; - if (main_writer_counter_t_next_value_ce) begin - main_writer_counter <= main_writer_counter_t_next_value; - end - if (main_writer_errors_status_f_next_value_ce) begin - main_writer_errors_status <= main_writer_errors_status_f_next_value; - end - if (main_reader_eventsourcepulse_clear) begin - main_reader_eventsourcepulse_pending <= 1'd0; - end - if (main_reader_eventsourcepulse_trigger) begin - main_reader_eventsourcepulse_pending <= 1'd1; - end - if (((main_reader_cmd_fifo_syncfifo_we & main_reader_cmd_fifo_syncfifo_writable) & (~main_reader_cmd_fifo_replace))) begin - main_reader_cmd_fifo_produce <= (main_reader_cmd_fifo_produce + 1'd1); - end - if (main_reader_cmd_fifo_do_read) begin - main_reader_cmd_fifo_consume <= (main_reader_cmd_fifo_consume + 1'd1); - end - if (((main_reader_cmd_fifo_syncfifo_we & main_reader_cmd_fifo_syncfifo_writable) & (~main_reader_cmd_fifo_replace))) begin - if ((~main_reader_cmd_fifo_do_read)) begin - main_reader_cmd_fifo_level <= (main_reader_cmd_fifo_level + 1'd1); - end - end else begin - if (main_reader_cmd_fifo_do_read) begin - main_reader_cmd_fifo_level <= (main_reader_cmd_fifo_level - 1'd1); - end - end - builder_liteethmacsramreader_state <= builder_liteethmacsramreader_next_state; - if (main_reader_counter_next_value_ce) begin - main_reader_counter <= main_reader_counter_next_value; - end - main_sram0_bus_ack0 <= 1'd0; - if (((main_sram0_bus_cyc0 & main_sram0_bus_stb0) & (~main_sram0_bus_ack0))) begin - main_sram0_bus_ack0 <= 1'd1; - end - main_sram1_bus_ack0 <= 1'd0; - if (((main_sram1_bus_cyc0 & main_sram1_bus_stb0) & (~main_sram1_bus_ack0))) begin - main_sram1_bus_ack0 <= 1'd1; - end - main_sram0_bus_ack1 <= 1'd0; - if (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & (~main_sram0_bus_ack1))) begin - main_sram0_bus_ack1 <= 1'd1; - end - main_sram1_bus_ack1 <= 1'd0; - if (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & (~main_sram1_bus_ack1))) begin - main_sram1_bus_ack1 <= 1'd1; - end - main_slave_sel_r <= main_slave_sel; - builder_state <= builder_next_state; - builder_slave_sel_r <= builder_slave_sel; - if (builder_wait) begin - if ((~builder_done)) begin - builder_count <= (builder_count - 1'd1); - end - end else begin - builder_count <= 20'd1000000; - end - builder_interface0_bank_bus_dat_r <= 1'd0; - if (builder_csrbank0_sel) begin - case (builder_interface0_bank_bus_adr[8:0]) - 1'd0: begin - builder_interface0_bank_bus_dat_r <= builder_csrbank0_reset0_w; - end - 1'd1: begin - builder_interface0_bank_bus_dat_r <= builder_csrbank0_scratch0_w; - end - 2'd2: begin - builder_interface0_bank_bus_dat_r <= builder_csrbank0_bus_errors_w; - end - endcase - end - if (builder_csrbank0_reset0_re) begin - main_maccore_maccore_reset_storage[1:0] <= builder_csrbank0_reset0_r; - end - main_maccore_maccore_reset_re <= builder_csrbank0_reset0_re; - if (builder_csrbank0_scratch0_re) begin - main_maccore_maccore_scratch_storage[31:0] <= builder_csrbank0_scratch0_r; - end - main_maccore_maccore_scratch_re <= builder_csrbank0_scratch0_re; - main_maccore_maccore_bus_errors_re <= builder_csrbank0_bus_errors_re; - builder_interface1_bank_bus_dat_r <= 1'd0; - if (builder_csrbank1_sel) begin - case (builder_interface1_bank_bus_adr[8:0]) - 1'd0: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_slot_w; - end - 1'd1: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_length_w; - end - 2'd2: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_errors_w; - end - 2'd3: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_status_w; - end - 3'd4: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_pending_w; - end - 3'd5: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_enable0_w; - end - 3'd6: begin - builder_interface1_bank_bus_dat_r <= main_reader_start_start_w; - end - 3'd7: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ready_w; - end - 4'd8: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_level_w; - end - 4'd9: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_slot0_w; - end - 4'd10: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_length0_w; - end - 4'd11: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_status_w; - end - 4'd12: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_pending_w; - end - 4'd13: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_enable0_w; - end - 4'd14: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_crc_w; - end - 4'd15: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_errors_w; - end - 5'd16: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_crc_errors_w; - end - endcase - end - main_writer_slot_re <= builder_csrbank1_sram_writer_slot_re; - main_writer_length_re <= builder_csrbank1_sram_writer_length_re; - main_writer_errors_re <= builder_csrbank1_sram_writer_errors_re; - main_writer_status_re <= builder_csrbank1_sram_writer_ev_status_re; - if (builder_csrbank1_sram_writer_ev_pending_re) begin - main_writer_pending_r <= builder_csrbank1_sram_writer_ev_pending_r; - end - main_writer_pending_re <= builder_csrbank1_sram_writer_ev_pending_re; - if (builder_csrbank1_sram_writer_ev_enable0_re) begin - main_writer_enable_storage <= builder_csrbank1_sram_writer_ev_enable0_r; - end - main_writer_enable_re <= builder_csrbank1_sram_writer_ev_enable0_re; - main_reader_ready_re <= builder_csrbank1_sram_reader_ready_re; - main_reader_level_re <= builder_csrbank1_sram_reader_level_re; - if (builder_csrbank1_sram_reader_slot0_re) begin - main_reader_slot_storage <= builder_csrbank1_sram_reader_slot0_r; - end - main_reader_slot_re <= builder_csrbank1_sram_reader_slot0_re; - if (builder_csrbank1_sram_reader_length0_re) begin - main_reader_length_storage[10:0] <= builder_csrbank1_sram_reader_length0_r; - end - main_reader_length_re <= builder_csrbank1_sram_reader_length0_re; - main_reader_status_re <= builder_csrbank1_sram_reader_ev_status_re; - if (builder_csrbank1_sram_reader_ev_pending_re) begin - main_reader_pending_r <= builder_csrbank1_sram_reader_ev_pending_r; - end - main_reader_pending_re <= builder_csrbank1_sram_reader_ev_pending_re; - if (builder_csrbank1_sram_reader_ev_enable0_re) begin - main_reader_enable_storage <= builder_csrbank1_sram_reader_ev_enable0_r; - end - main_reader_enable_re <= builder_csrbank1_sram_reader_ev_enable0_re; - main_preamble_crc_re <= builder_csrbank1_preamble_crc_re; - main_preamble_errors_re <= builder_csrbank1_preamble_errors_re; - main_crc_errors_re <= builder_csrbank1_crc_errors_re; - builder_interface2_bank_bus_dat_r <= 1'd0; - if (builder_csrbank2_sel) begin - case (builder_interface2_bank_bus_adr[8:0]) - 1'd0: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_crg_reset0_w; - end - 1'd1: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_w0_w; - end - 2'd2: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_r_w; - end - endcase - end - if (builder_csrbank2_crg_reset0_re) begin - main_maccore_ethphy_reset_storage <= builder_csrbank2_crg_reset0_r; - end - main_maccore_ethphy_reset_re <= builder_csrbank2_crg_reset0_re; - if (builder_csrbank2_mdio_w0_re) begin - main_maccore_ethphy__w_storage[2:0] <= builder_csrbank2_mdio_w0_r; - end - main_maccore_ethphy__w_re <= builder_csrbank2_mdio_w0_re; - main_maccore_ethphy__r_re <= builder_csrbank2_mdio_r_re; - if (sys_rst) begin - main_maccore_maccore_reset_storage <= 2'd0; - main_maccore_maccore_reset_re <= 1'd0; - main_maccore_maccore_scratch_storage <= 32'd305419896; - main_maccore_maccore_scratch_re <= 1'd0; - main_maccore_maccore_bus_errors_re <= 1'd0; - main_maccore_maccore_bus_errors <= 32'd0; - main_maccore_ethphy_reset_storage <= 1'd0; - main_maccore_ethphy_reset_re <= 1'd0; - main_maccore_ethphy_counter <= 9'd0; - main_maccore_ethphy__w_storage <= 3'd0; - main_maccore_ethphy__w_re <= 1'd0; - main_maccore_ethphy__r_re <= 1'd0; - main_preamble_crc_re <= 1'd0; - main_preamble_errors_status <= 32'd0; - main_preamble_errors_re <= 1'd0; - main_crc_errors_status <= 32'd0; - main_crc_errors_re <= 1'd0; - main_tx_cdc_cdc_graycounter0_q <= 6'd0; - main_tx_cdc_cdc_graycounter0_q_binary <= 6'd0; - main_rx_cdc_cdc_graycounter1_q <= 6'd0; - main_rx_cdc_cdc_graycounter1_q_binary <= 6'd0; - main_writer_slot_re <= 1'd0; - main_writer_length_re <= 1'd0; - main_writer_errors_status <= 32'd0; - main_writer_errors_re <= 1'd0; - main_writer_status_re <= 1'd0; - main_writer_pending_re <= 1'd0; - main_writer_pending_r <= 1'd0; - main_writer_enable_storage <= 1'd0; - main_writer_enable_re <= 1'd0; - main_writer_counter <= 32'd0; - main_writer_slot <= 1'd0; - main_writer_stat_fifo_level <= 2'd0; - main_writer_stat_fifo_produce <= 1'd0; - main_writer_stat_fifo_consume <= 1'd0; - main_reader_ready_re <= 1'd0; - main_reader_level_re <= 1'd0; - main_reader_slot_re <= 1'd0; - main_reader_length_re <= 1'd0; - main_reader_eventsourcepulse_pending <= 1'd0; - main_reader_status_re <= 1'd0; - main_reader_pending_re <= 1'd0; - main_reader_pending_r <= 1'd0; - main_reader_enable_storage <= 1'd0; - main_reader_enable_re <= 1'd0; - main_reader_cmd_fifo_level <= 2'd0; - main_reader_cmd_fifo_produce <= 1'd0; - main_reader_cmd_fifo_consume <= 1'd0; - main_reader_counter <= 11'd0; - main_sram0_bus_ack0 <= 1'd0; - main_sram1_bus_ack0 <= 1'd0; - main_sram0_bus_ack1 <= 1'd0; - main_sram1_bus_ack1 <= 1'd0; - main_slave_sel_r <= 4'd0; - builder_liteethmacsramwriter_state <= 3'd0; - builder_liteethmacsramreader_state <= 2'd0; - builder_slave_sel_r <= 2'd0; - builder_count <= 20'd1000000; - builder_state <= 1'd0; - end - builder_xilinxmultiregimpl0_regs0 <= main_maccore_ethphy_data_r; - builder_xilinxmultiregimpl0_regs1 <= builder_xilinxmultiregimpl0_regs0; - builder_xilinxmultiregimpl1_regs0 <= main_ps_preamble_error_toggle_i; - builder_xilinxmultiregimpl1_regs1 <= builder_xilinxmultiregimpl1_regs0; - builder_xilinxmultiregimpl2_regs0 <= main_ps_crc_error_toggle_i; - builder_xilinxmultiregimpl2_regs1 <= builder_xilinxmultiregimpl2_regs0; - builder_xilinxmultiregimpl4_regs0 <= main_tx_cdc_cdc_graycounter1_q; - builder_xilinxmultiregimpl4_regs1 <= builder_xilinxmultiregimpl4_regs0; - builder_xilinxmultiregimpl5_regs0 <= main_rx_cdc_cdc_graycounter0_q; - builder_xilinxmultiregimpl5_regs1 <= builder_xilinxmultiregimpl5_regs0; + builder_slave_sel_r <= builder_slave_sel; + if (builder_wait) begin + if ((~builder_done)) begin + builder_count <= (builder_count - 1'd1); + end + end else begin + builder_count <= 20'd1000000; + end + if ((main_maccore_bus_errors != 32'd4294967295)) begin + if (main_maccore_bus_error) begin + main_maccore_bus_errors <= (main_maccore_bus_errors + 1'd1); + end + end + if (main_maccore_crg_counter_ce) begin + main_maccore_crg_counter <= (main_maccore_crg_counter + 1'd1); + end + main_tx_cdc_cdc_graycounter0_q_binary <= main_tx_cdc_cdc_graycounter0_q_next_binary; + main_tx_cdc_cdc_graycounter0_q <= main_tx_cdc_cdc_graycounter0_q_next; + if (main_pulsesynchronizer0_o) begin + main_preamble_errors_status <= (main_preamble_errors_status + 1'd1); + end + if (main_pulsesynchronizer1_o) begin + main_crc_errors_status <= (main_crc_errors_status + 1'd1); + end + main_pulsesynchronizer0_toggle_o_r <= main_pulsesynchronizer0_toggle_o; + main_pulsesynchronizer1_toggle_o_r <= main_pulsesynchronizer1_toggle_o; + main_rx_cdc_cdc_graycounter1_q_binary <= main_rx_cdc_cdc_graycounter1_q_next_binary; + main_rx_cdc_cdc_graycounter1_q <= main_rx_cdc_cdc_graycounter1_q_next; + if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin + main_sram57_produce <= (main_sram57_produce + 1'd1); + end + if (main_sram63_do_read) begin + main_sram58_consume <= (main_sram58_consume + 1'd1); + end + if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin + if ((~main_sram63_do_read)) begin + main_sram55_level <= (main_sram55_level + 1'd1); + end + end else begin + if (main_sram63_do_read) begin + main_sram55_level <= (main_sram55_level - 1'd1); + end + end + builder_liteethmacsramwriter_state <= builder_liteethmacsramwriter_next_state; + if (main_sram35_length_liteethmacsramwriter_t_next_value_ce) begin + main_sram35_length <= main_sram35_length_liteethmacsramwriter_t_next_value; + end + if (main_sram13_status_liteethmacsramwriter_f_next_value_ce) begin + main_sram13_status <= main_sram13_status_liteethmacsramwriter_f_next_value; + end + if (main_slot_liteethmacsramwriter_next_value_ce) begin + main_slot <= main_slot_liteethmacsramwriter_next_value; + end + if (main_sram108_clear) begin + main_sram106_pending <= 1'd0; + end + if (main_sram107_trigger) begin + main_sram106_pending <= 1'd1; + end + if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin + main_sram143_produce <= (main_sram143_produce + 1'd1); + end + if (main_sram149_do_read) begin + main_sram144_consume <= (main_sram144_consume + 1'd1); + end + if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin + if ((~main_sram149_do_read)) begin + main_sram141_level <= (main_sram141_level + 1'd1); + end + end else begin + if (main_sram149_do_read) begin + main_sram141_level <= (main_sram141_level - 1'd1); + end + end + builder_liteethmacsramreader_state <= builder_liteethmacsramreader_next_state; + if (main_sram122_length_liteethmacsramreader_next_value_ce) begin + main_sram122_length <= main_sram122_length_liteethmacsramreader_next_value; + end + main_interface0_ack <= 1'd0; + if (((main_interface0_cyc & main_interface0_stb) & ((~main_interface0_ack) | main_sram0_adr_burst))) begin + main_interface0_ack <= 1'd1; + end + main_interface1_ack <= 1'd0; + if (((main_interface1_cyc & main_interface1_stb) & ((~main_interface1_ack) | main_sram1_adr_burst))) begin + main_interface1_ack <= 1'd1; + end + main_interface2_ack <= 1'd0; + if (((main_interface2_cyc & main_interface2_stb) & ((~main_interface2_ack) | main_sram2_adr_burst))) begin + main_interface2_ack <= 1'd1; + end + main_interface3_ack <= 1'd0; + if (((main_interface3_cyc & main_interface3_stb) & ((~main_interface3_ack) | main_sram3_adr_burst))) begin + main_interface3_ack <= 1'd1; + end + main_slave_sel_r <= main_slave_sel; + builder_state <= builder_next_state; + builder_interface0_bank_bus_dat_r <= 1'd0; + if (builder_csrbank0_sel) begin + case (builder_interface0_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_reset0_w; + end + 1'd1: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_scratch0_w; + end + 2'd2: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_bus_errors_w; + end + endcase + end + if (builder_csrbank0_reset0_re) begin + main_maccore_reset_storage[1:0] <= builder_csrbank0_reset0_r; + end + main_maccore_reset_re <= builder_csrbank0_reset0_re; + if (builder_csrbank0_scratch0_re) begin + main_maccore_scratch_storage[31:0] <= builder_csrbank0_scratch0_r; + end + main_maccore_scratch_re <= builder_csrbank0_scratch0_re; + main_maccore_bus_errors_re <= builder_csrbank0_bus_errors_re; + builder_interface1_bank_bus_dat_r <= 1'd0; + if (builder_csrbank1_sel) begin + case (builder_interface1_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_slot_w; + end + 1'd1: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_length_w; + end + 2'd2: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_errors_w; + end + 2'd3: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_status_w; + end + 3'd4: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_pending_w; + end + 3'd5: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_enable0_w; + end + 3'd6: begin + builder_interface1_bank_bus_dat_r <= main_start_w; + end + 3'd7: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ready_w; + end + 4'd8: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_level_w; + end + 4'd9: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_slot0_w; + end + 4'd10: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_length0_w; + end + 4'd11: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_status_w; + end + 4'd12: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_pending_w; + end + 4'd13: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_enable0_w; + end + 4'd14: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_crc_w; + end + 4'd15: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_preamble_errors_w; + end + 5'd16: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_crc_errors_w; + end + endcase + end + main_sram9_re <= builder_csrbank1_sram_writer_slot_re; + main_sram12_re <= builder_csrbank1_sram_writer_length_re; + main_sram15_re <= builder_csrbank1_sram_writer_errors_re; + main_sram24_re <= builder_csrbank1_sram_writer_ev_status_re; + if (builder_csrbank1_sram_writer_ev_pending_re) begin + main_sram29_r <= builder_csrbank1_sram_writer_ev_pending_r; + end + main_sram28_re <= builder_csrbank1_sram_writer_ev_pending_re; + if (builder_csrbank1_sram_writer_ev_enable0_re) begin + main_sram31_storage <= builder_csrbank1_sram_writer_ev_enable0_r; + end + main_sram32_re <= builder_csrbank1_sram_writer_ev_enable0_re; + main_sram96_re <= builder_csrbank1_sram_reader_ready_re; + main_sram99_re <= builder_csrbank1_sram_reader_level_re; + if (builder_csrbank1_sram_reader_slot0_re) begin + main_sram100_storage <= builder_csrbank1_sram_reader_slot0_r; + end + main_sram101_re <= builder_csrbank1_sram_reader_slot0_re; + if (builder_csrbank1_sram_reader_length0_re) begin + main_sram102_storage[10:0] <= builder_csrbank1_sram_reader_length0_r; + end + main_sram103_re <= builder_csrbank1_sram_reader_length0_re; + main_sram112_re <= builder_csrbank1_sram_reader_ev_status_re; + if (builder_csrbank1_sram_reader_ev_pending_re) begin + main_sram117_r <= builder_csrbank1_sram_reader_ev_pending_r; + end + main_sram116_re <= builder_csrbank1_sram_reader_ev_pending_re; + if (builder_csrbank1_sram_reader_ev_enable0_re) begin + main_sram119_storage <= builder_csrbank1_sram_reader_ev_enable0_r; + end + main_sram120_re <= builder_csrbank1_sram_reader_ev_enable0_re; + main_re <= builder_csrbank1_preamble_crc_re; + main_preamble_errors_re <= builder_csrbank1_rx_datapath_preamble_errors_re; + main_crc_errors_re <= builder_csrbank1_rx_datapath_crc_errors_re; + builder_interface2_bank_bus_dat_r <= 1'd0; + if (builder_csrbank2_sel) begin + case (builder_interface2_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_crg_reset0_w; + end + 1'd1: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_w0_w; + end + 2'd2: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_r_w; + end + endcase + end + if (builder_csrbank2_crg_reset0_re) begin + main_maccore_crg_reset_storage <= builder_csrbank2_crg_reset0_r; + end + main_maccore_crg_reset_re <= builder_csrbank2_crg_reset0_re; + if (builder_csrbank2_mdio_w0_re) begin + main_maccore__w_storage[2:0] <= builder_csrbank2_mdio_w0_r; + end + main_maccore__w_re <= builder_csrbank2_mdio_w0_re; + main_maccore__r_re <= builder_csrbank2_mdio_r_re; + if (sys_rst) begin + main_maccore_reset_storage <= 2'd0; + main_maccore_reset_re <= 1'd0; + main_maccore_scratch_storage <= 32'd305419896; + main_maccore_scratch_re <= 1'd0; + main_maccore_bus_errors_re <= 1'd0; + main_maccore_bus_errors <= 32'd0; + main_maccore_crg_reset_storage <= 1'd0; + main_maccore_crg_reset_re <= 1'd0; + main_maccore_crg_counter <= 9'd0; + main_maccore__w_storage <= 3'd0; + main_maccore__w_re <= 1'd0; + main_maccore__r_re <= 1'd0; + main_re <= 1'd0; + main_tx_cdc_cdc_graycounter0_q <= 6'd0; + main_tx_cdc_cdc_graycounter0_q_binary <= 6'd0; + main_preamble_errors_status <= 32'd0; + main_preamble_errors_re <= 1'd0; + main_crc_errors_status <= 32'd0; + main_crc_errors_re <= 1'd0; + main_rx_cdc_cdc_graycounter1_q <= 6'd0; + main_rx_cdc_cdc_graycounter1_q_binary <= 6'd0; + main_sram9_re <= 1'd0; + main_sram12_re <= 1'd0; + main_sram13_status <= 32'd0; + main_sram15_re <= 1'd0; + main_sram24_re <= 1'd0; + main_sram28_re <= 1'd0; + main_sram29_r <= 1'd0; + main_sram31_storage <= 1'd0; + main_sram32_re <= 1'd0; + main_slot <= 1'd0; + main_sram35_length <= 11'd0; + main_sram55_level <= 2'd0; + main_sram57_produce <= 1'd0; + main_sram58_consume <= 1'd0; + main_sram96_re <= 1'd0; + main_sram99_re <= 1'd0; + main_sram101_re <= 1'd0; + main_sram103_re <= 1'd0; + main_sram106_pending <= 1'd0; + main_sram112_re <= 1'd0; + main_sram116_re <= 1'd0; + main_sram117_r <= 1'd0; + main_sram119_storage <= 1'd0; + main_sram120_re <= 1'd0; + main_sram122_length <= 11'd0; + main_sram141_level <= 2'd0; + main_sram143_produce <= 1'd0; + main_sram144_consume <= 1'd0; + main_interface0_ack <= 1'd0; + main_interface1_ack <= 1'd0; + main_interface2_ack <= 1'd0; + main_interface3_ack <= 1'd0; + main_slave_sel_r <= 4'd0; + builder_slave_sel_r <= 2'd0; + builder_count <= 20'd1000000; + builder_liteethmacsramwriter_state <= 3'd0; + builder_liteethmacsramreader_state <= 2'd0; + builder_state <= 1'd0; + end + builder_xilinxmultiregimpl00 <= main_maccore_data_r; + builder_xilinxmultiregimpl01 <= builder_xilinxmultiregimpl00; + builder_xilinxmultiregimpl20 <= main_tx_cdc_cdc_graycounter1_q; + builder_xilinxmultiregimpl21 <= builder_xilinxmultiregimpl20; + builder_xilinxmultiregimpl30 <= main_pulsesynchronizer0_toggle_i; + builder_xilinxmultiregimpl31 <= builder_xilinxmultiregimpl30; + builder_xilinxmultiregimpl40 <= main_pulsesynchronizer1_toggle_i; + builder_xilinxmultiregimpl41 <= builder_xilinxmultiregimpl40; + builder_xilinxmultiregimpl50 <= main_rx_cdc_cdc_graycounter0_q; + builder_xilinxmultiregimpl51 <= builder_xilinxmultiregimpl50; end -assign mii_eth_mdio = main_maccore_ethphy_data_oe ? main_maccore_ethphy_data_w : 1'bz; -assign main_maccore_ethphy_data_r = mii_eth_mdio; - -reg [11:0] storage[0:4]; -reg [11:0] memdat; -always @(posedge eth_rx_clk) begin - if (main_liteethmaccrc32checker_syncfifo_wrport_we) - storage[main_liteethmaccrc32checker_syncfifo_wrport_adr] <= main_liteethmaccrc32checker_syncfifo_wrport_dat_w; - memdat <= storage[main_liteethmaccrc32checker_syncfifo_wrport_adr]; -end -always @(posedge eth_rx_clk) begin -end +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ -assign main_liteethmaccrc32checker_syncfifo_wrport_dat_r = memdat; -assign main_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage[main_liteethmaccrc32checker_syncfifo_rdport_adr]; +assign mii_mdio = main_maccore_data_oe ? main_maccore_data_w : 1'bz; +assign main_maccore_data_r = mii_mdio; -reg [41:0] storage_1[0:31]; -reg [4:0] memadr; -reg [4:0] memadr_1; +//------------------------------------------------------------------------------ +// Memory storage: 32-words x 42-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 42 +// Port 1 | Read: Sync | Write: ---- | +reg [41:0] storage[0:31]; +reg [41:0] storage_dat0; +reg [41:0] storage_dat1; always @(posedge sys_clk) begin if (main_tx_cdc_cdc_wrport_we) - storage_1[main_tx_cdc_cdc_wrport_adr] <= main_tx_cdc_cdc_wrport_dat_w; - memadr <= main_tx_cdc_cdc_wrport_adr; + storage[main_tx_cdc_cdc_wrport_adr] <= main_tx_cdc_cdc_wrport_dat_w; + storage_dat0 <= storage[main_tx_cdc_cdc_wrport_adr]; end - always @(posedge eth_tx_clk) begin - memadr_1 <= main_tx_cdc_cdc_rdport_adr; + storage_dat1 <= storage[main_tx_cdc_cdc_rdport_adr]; end +assign main_tx_cdc_cdc_wrport_dat_r = storage_dat0; +assign main_tx_cdc_cdc_rdport_dat_r = storage_dat1; -assign main_tx_cdc_cdc_wrport_dat_r = storage_1[memadr]; -assign main_tx_cdc_cdc_rdport_dat_r = storage_1[memadr_1]; +//------------------------------------------------------------------------------ +// Memory storage_1: 5-words x 12-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 12 +// Port 1 | Read: Async | Write: ---- | +reg [11:0] storage_1[0:4]; +reg [11:0] storage_1_dat0; +always @(posedge eth_rx_clk) begin + if (main_liteethmaccrc32checker_syncfifo_wrport_we) + storage_1[main_liteethmaccrc32checker_syncfifo_wrport_adr] <= main_liteethmaccrc32checker_syncfifo_wrport_dat_w; + storage_1_dat0 <= storage_1[main_liteethmaccrc32checker_syncfifo_wrport_adr]; +end +always @(posedge eth_rx_clk) begin +end +assign main_liteethmaccrc32checker_syncfifo_wrport_dat_r = storage_1_dat0; +assign main_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage_1[main_liteethmaccrc32checker_syncfifo_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_2: 32-words x 42-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 42 +// Port 1 | Read: Sync | Write: ---- | reg [41:0] storage_2[0:31]; -reg [4:0] memadr_2; -reg [4:0] memadr_3; +reg [41:0] storage_2_dat0; +reg [41:0] storage_2_dat1; always @(posedge eth_rx_clk) begin if (main_rx_cdc_cdc_wrport_we) storage_2[main_rx_cdc_cdc_wrport_adr] <= main_rx_cdc_cdc_wrport_dat_w; - memadr_2 <= main_rx_cdc_cdc_wrport_adr; + storage_2_dat0 <= storage_2[main_rx_cdc_cdc_wrport_adr]; end - always @(posedge sys_clk) begin - memadr_3 <= main_rx_cdc_cdc_rdport_adr; + storage_2_dat1 <= storage_2[main_rx_cdc_cdc_rdport_adr]; end +assign main_rx_cdc_cdc_wrport_dat_r = storage_2_dat0; +assign main_rx_cdc_cdc_rdport_dat_r = storage_2_dat1; -assign main_rx_cdc_cdc_wrport_dat_r = storage_2[memadr_2]; -assign main_rx_cdc_cdc_rdport_dat_r = storage_2[memadr_3]; -reg [34:0] storage_3[0:1]; -reg [34:0] memdat_1; +//------------------------------------------------------------------------------ +// Memory storage_3: 2-words x 14-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 14 +// Port 1 | Read: Async | Write: ---- | +reg [13:0] storage_3[0:1]; +reg [13:0] storage_3_dat0; always @(posedge sys_clk) begin - if (main_writer_stat_fifo_wrport_we) - storage_3[main_writer_stat_fifo_wrport_adr] <= main_writer_stat_fifo_wrport_dat_w; - memdat_1 <= storage_3[main_writer_stat_fifo_wrport_adr]; + if (main_sram61_we) + storage_3[main_sram59_adr] <= main_sram62_dat_w; + storage_3_dat0 <= storage_3[main_sram59_adr]; end - always @(posedge sys_clk) begin end +assign main_sram60_dat_r = storage_3_dat0; +assign main_sram65_dat_r = storage_3[main_sram64_adr]; -assign main_writer_stat_fifo_wrport_dat_r = memdat_1; -assign main_writer_stat_fifo_rdport_dat_r = storage_3[main_writer_stat_fifo_rdport_adr]; -reg [31:0] mem[0:381]; -reg [8:0] memadr_4; -reg [31:0] memdat_2; +//------------------------------------------------------------------------------ +// Memory mem: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 32 +// Port 1 | Read: Sync | Write: ---- | +reg [31:0] mem[0:382]; +reg [8:0] mem_adr0; +reg [31:0] mem_dat1; always @(posedge sys_clk) begin - if (main_writer_memory0_we) - mem[main_writer_memory0_adr] <= main_writer_memory0_dat_w; - memadr_4 <= main_writer_memory0_adr; + if (main_sram77_we) + mem[main_sram75_adr] <= main_sram78_dat_w; + mem_adr0 <= main_sram75_adr; end - always @(posedge sys_clk) begin - memdat_2 <= mem[main_sram0_adr0]; + mem_dat1 <= mem[main_sram0_adr]; end +assign main_sram76_dat_r = mem[mem_adr0]; +assign main_sram0_dat_r = mem_dat1; -assign main_writer_memory0_dat_r = mem[memadr_4]; -assign main_sram0_dat_r0 = memdat_2; -reg [31:0] mem_1[0:381]; -reg [8:0] memadr_5; -reg [31:0] memdat_3; +//------------------------------------------------------------------------------ +// Memory mem_1: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 32 +// Port 1 | Read: Sync | Write: ---- | +reg [31:0] mem_1[0:382]; +reg [8:0] mem_1_adr0; +reg [31:0] mem_1_dat1; always @(posedge sys_clk) begin - if (main_writer_memory1_we) - mem_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w; - memadr_5 <= main_writer_memory1_adr; + if (main_sram81_we) + mem_1[main_sram79_adr] <= main_sram82_dat_w; + mem_1_adr0 <= main_sram79_adr; end - always @(posedge sys_clk) begin - memdat_3 <= mem_1[main_sram1_adr0]; + mem_1_dat1 <= mem_1[main_sram1_adr]; end +assign main_sram80_dat_r = mem_1[mem_1_adr0]; +assign main_sram1_dat_r = mem_1_dat1; -assign main_writer_memory1_dat_r = mem_1[memadr_5]; -assign main_sram1_dat_r0 = memdat_3; +//------------------------------------------------------------------------------ +// Memory storage_4: 2-words x 14-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 14 +// Port 1 | Read: Async | Write: ---- | reg [13:0] storage_4[0:1]; -reg [13:0] memdat_4; +reg [13:0] storage_4_dat0; always @(posedge sys_clk) begin - if (main_reader_cmd_fifo_wrport_we) - storage_4[main_reader_cmd_fifo_wrport_adr] <= main_reader_cmd_fifo_wrport_dat_w; - memdat_4 <= storage_4[main_reader_cmd_fifo_wrport_adr]; + if (main_sram147_we) + storage_4[main_sram145_adr] <= main_sram148_dat_w; + storage_4_dat0 <= storage_4[main_sram145_adr]; end - always @(posedge sys_clk) begin end +assign main_sram146_dat_r = storage_4_dat0; +assign main_sram151_dat_r = storage_4[main_sram150_adr]; -assign main_reader_cmd_fifo_wrport_dat_r = memdat_4; -assign main_reader_cmd_fifo_rdport_dat_r = storage_4[main_reader_cmd_fifo_rdport_adr]; -reg [31:0] mem_2[0:381]; -reg [8:0] memadr_6; -reg [8:0] memadr_7; +//------------------------------------------------------------------------------ +// Memory mem_2: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +reg [31:0] mem_2[0:382]; +reg [31:0] mem_2_dat0; +reg [8:0] mem_2_adr1; always @(posedge sys_clk) begin - memadr_6 <= main_reader_memory0_adr; + if (main_sram163_re) + mem_2_dat0 <= mem_2[main_sram161_adr]; end - always @(posedge sys_clk) begin - if (main_sram0_we[0]) - mem_2[main_sram0_adr1][7:0] <= main_sram0_dat_w[7:0]; - if (main_sram0_we[1]) - mem_2[main_sram0_adr1][15:8] <= main_sram0_dat_w[15:8]; - if (main_sram0_we[2]) - mem_2[main_sram0_adr1][23:16] <= main_sram0_dat_w[23:16]; - if (main_sram0_we[3]) - mem_2[main_sram0_adr1][31:24] <= main_sram0_dat_w[31:24]; - memadr_7 <= main_sram0_adr1; -end + if (main_sram2_we[0]) + mem_2[main_sram2_adr][7:0] <= main_sram2_dat_w[7:0]; + if (main_sram2_we[1]) + mem_2[main_sram2_adr][15:8] <= main_sram2_dat_w[15:8]; + if (main_sram2_we[2]) + mem_2[main_sram2_adr][23:16] <= main_sram2_dat_w[23:16]; + if (main_sram2_we[3]) + mem_2[main_sram2_adr][31:24] <= main_sram2_dat_w[31:24]; + mem_2_adr1 <= main_sram2_adr; +end +assign main_sram162_dat_r = mem_2_dat0; +assign main_sram2_dat_r = mem_2[mem_2_adr1]; -assign main_reader_memory0_dat_r = mem_2[memadr_6]; -assign main_sram0_dat_r1 = mem_2[memadr_7]; -reg [31:0] mem_3[0:381]; -reg [8:0] memadr_8; -reg [8:0] memadr_9; +//------------------------------------------------------------------------------ +// Memory mem_3: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +reg [31:0] mem_3[0:382]; +reg [31:0] mem_3_dat0; +reg [8:0] mem_3_adr1; always @(posedge sys_clk) begin - memadr_8 <= main_reader_memory1_adr; + if (main_sram166_re) + mem_3_dat0 <= mem_3[main_sram164_adr]; end - always @(posedge sys_clk) begin - if (main_sram1_we[0]) - mem_3[main_sram1_adr1][7:0] <= main_sram1_dat_w[7:0]; - if (main_sram1_we[1]) - mem_3[main_sram1_adr1][15:8] <= main_sram1_dat_w[15:8]; - if (main_sram1_we[2]) - mem_3[main_sram1_adr1][23:16] <= main_sram1_dat_w[23:16]; - if (main_sram1_we[3]) - mem_3[main_sram1_adr1][31:24] <= main_sram1_dat_w[31:24]; - memadr_9 <= main_sram1_adr1; -end + if (main_sram3_we[0]) + mem_3[main_sram3_adr][7:0] <= main_sram3_dat_w[7:0]; + if (main_sram3_we[1]) + mem_3[main_sram3_adr][15:8] <= main_sram3_dat_w[15:8]; + if (main_sram3_we[2]) + mem_3[main_sram3_adr][23:16] <= main_sram3_dat_w[23:16]; + if (main_sram3_we[3]) + mem_3[main_sram3_adr][31:24] <= main_sram3_dat_w[31:24]; + mem_3_adr1 <= main_sram3_adr; +end +assign main_sram165_dat_r = mem_3_dat0; +assign main_sram3_dat_r = mem_3[mem_3_adr1]; -assign main_reader_memory1_dat_r = mem_3[memadr_8]; -assign main_sram1_dat_r1 = mem_3[memadr_9]; -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE ( - .C(eth_tx_clk), - .CE(1'd1), - .D(1'd0), - .PRE(main_maccore_ethphy_reset0), - .Q(builder_rst_meta0) + // Inputs. + .C (eth_tx_clk), + .CE (1'd1), + .D (1'd0), + .PRE (main_maccore_crg_reset0), + + // Outputs. + .Q (builder_rst_meta0) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_1 of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE_1 ( - .C(eth_tx_clk), - .CE(1'd1), - .D(builder_rst_meta0), - .PRE(main_maccore_ethphy_reset0), - .Q(eth_tx_rst) + // Inputs. + .C (eth_tx_clk), + .CE (1'd1), + .D (builder_rst_meta0), + .PRE (main_maccore_crg_reset0), + + // Outputs. + .Q (eth_tx_rst) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_2 of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE_2 ( - .C(eth_rx_clk), - .CE(1'd1), - .D(1'd0), - .PRE(main_maccore_ethphy_reset0), - .Q(builder_rst_meta1) + // Inputs. + .C (eth_rx_clk), + .CE (1'd1), + .D (1'd0), + .PRE (main_maccore_crg_reset0), + + // Outputs. + .Q (builder_rst_meta1) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_3 of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE_3 ( - .C(eth_rx_clk), - .CE(1'd1), - .D(builder_rst_meta1), - .PRE(main_maccore_ethphy_reset0), - .Q(eth_rx_rst) + // Inputs. + .C (eth_rx_clk), + .CE (1'd1), + .D (builder_rst_meta1), + .PRE (main_maccore_crg_reset0), + + // Outputs. + .Q (eth_rx_rst) ); endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2024-04-05 17:38:49. +//------------------------------------------------------------------------------ diff --git a/liteeth/generated/ecpix-5/liteeth_core.v b/liteeth/generated/ecpix-5/liteeth_core.v new file mode 100644 index 0000000..50fde14 --- /dev/null +++ b/liteeth/generated/ecpix-5/liteeth_core.v @@ -0,0 +1,4289 @@ +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : liteeth_core.v +// Device : +// LiteX sha1 : 87137c30 +// Date : 2024-04-09 14:20:58 +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ps + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module liteeth_core ( + output wire interrupt, + input wire rgmii_clocks_rx, + output wire rgmii_clocks_tx, + input wire rgmii_int_n, + output wire rgmii_mdc, + inout wire rgmii_mdio, + output wire rgmii_rst_n, + input wire rgmii_rx_ctl, + input wire [3:0] rgmii_rx_data, + output wire rgmii_tx_ctl, + output wire [3:0] rgmii_tx_data, + input wire sys_clock, + input wire sys_reset, + output wire wishbone_ack, + input wire [29:0] wishbone_adr, + input wire [1:0] wishbone_bte, + input wire [2:0] wishbone_cti, + input wire wishbone_cyc, + output wire [31:0] wishbone_dat_r, + input wire [31:0] wishbone_dat_w, + output wire wishbone_err, + input wire [3:0] wishbone_sel, + input wire wishbone_stb, + input wire wishbone_we +); + + +//------------------------------------------------------------------------------ +// Hierarchy +//------------------------------------------------------------------------------ + +/* +MACCore +└─── bus (SoCBusHandler) +│ └─── _interconnect (InterconnectShared) +│ │ └─── arbiter (Arbiter) +│ │ │ └─── rr (RoundRobin) +│ │ └─── decoder (Decoder) +│ │ └─── timeout (Timeout) +│ │ │ └─── waittimer_0* (WaitTimer) +└─── csr (SoCCSRHandler) +└─── irq (SoCIRQHandler) +└─── ctrl (SoCController) +└─── cpu (CPUNone) +└─── crg (CRG) +└─── ethphy (LiteEthPHYRGMII) +│ └─── crg (LiteEthPHYRGMIICRG) +│ │ └─── [DELAYG] +│ └─── tx (LiteEthPHYRGMIITX) +│ │ └─── [DELAYG] +│ │ └─── [DELAYG] +│ │ └─── [DELAYG] +│ │ └─── [DELAYG] +│ │ └─── [DELAYG] +│ └─── rx (LiteEthPHYRGMIIRX) +│ │ └─── [DELAYG] +│ │ └─── [DELAYG] +│ │ └─── [DELAYG] +│ │ └─── [DELAYG] +│ │ └─── [DELAYG] +│ └─── mdio (LiteEthPHYMDIO) +└─── ethmac (LiteEthMAC) +│ └─── core (LiteEthMACCore) +│ │ └─── tx_datapath (TXDatapath) +│ │ │ └─── clockdomaincrossing_0* (ClockDomainCrossing) +│ │ │ │ └─── asyncfifo_0* (AsyncFIFO) +│ │ │ │ │ └─── fifo (AsyncFIFO) +│ │ │ │ │ │ └─── graycounter_0* (GrayCounter) +│ │ │ │ │ │ └─── graycounter_1* (GrayCounter) +│ │ │ └─── strideconverter_0* (StrideConverter) +│ │ │ │ └─── converter_0* (Converter) +│ │ │ │ │ └─── _downconverter_0* (_DownConverter) +│ │ │ └─── liteethmactxlastbe_0* (LiteEthMACTXLastBE) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── liteethmacpaddinginserter_0* (LiteEthMACPaddingInserter) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── liteethmaccrc32inserter_0* (LiteEthMACCRC32Inserter) +│ │ │ │ └─── crc (LiteEthMACCRC32) +│ │ │ │ │ └─── liteethmaccrcengine_0* (LiteEthMACCRCEngine) +│ │ │ │ └─── fsm (FSM) +│ │ │ │ └─── buffer_0* (Buffer) +│ │ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── liteethmacpreambleinserter_0* (LiteEthMACPreambleInserter) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── liteethmacgap_0* (LiteEthMACGap) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── pipeline_0* (Pipeline) +│ │ └─── rx_datapath (RXDatapath) +│ │ │ └─── liteethmacpreamblechecker_0* (LiteEthMACPreambleChecker) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── pulsesynchronizer_0* (PulseSynchronizer) +│ │ │ └─── liteethmaccrc32checker_0* (LiteEthMACCRC32Checker) +│ │ │ │ └─── crc (LiteEthMACCRC32) +│ │ │ │ │ └─── liteethmaccrcengine_0* (LiteEthMACCRCEngine) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ └─── fsm (FSM) +│ │ │ │ └─── buffer_0* (Buffer) +│ │ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── pulsesynchronizer_1* (PulseSynchronizer) +│ │ │ └─── liteethmacpaddingchecker_0* (LiteEthMACPaddingChecker) +│ │ │ └─── liteethmacrxlastbe_0* (LiteEthMACRXLastBE) +│ │ │ └─── strideconverter_0* (StrideConverter) +│ │ │ │ └─── converter_0* (Converter) +│ │ │ │ │ └─── _upconverter_0* (_UpConverter) +│ │ │ └─── clockdomaincrossing_0* (ClockDomainCrossing) +│ │ │ │ └─── asyncfifo_0* (AsyncFIFO) +│ │ │ │ │ └─── fifo (AsyncFIFO) +│ │ │ │ │ │ └─── graycounter_0* (GrayCounter) +│ │ │ │ │ │ └─── graycounter_1* (GrayCounter) +│ │ │ └─── pipeline_0* (Pipeline) +│ └─── interface (LiteEthMACWishboneInterface) +│ │ └─── sram (LiteEthMACSRAM) +│ │ │ └─── writer (LiteEthMACSRAMWriter) +│ │ │ │ └─── ev (EventManager) +│ │ │ │ │ └─── eventsourcelevel_0* (EventSourceLevel) +│ │ │ │ └─── stat_fifo (SyncFIFO) +│ │ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── reader (LiteEthMACSRAMReader) +│ │ │ │ └─── ev (EventManager) +│ │ │ │ │ └─── eventsourcepulse_0* (EventSourcePulse) +│ │ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── ev (SharedIRQ) +│ │ └─── sram_0* (SRAM) +│ │ └─── sram_1* (SRAM) +│ │ └─── sram_2* (SRAM) +│ │ └─── sram_3* (SRAM) +│ │ └─── decoder_0* (Decoder) +└─── csr_bridge (Wishbone2CSR) +│ └─── fsm (FSM) +└─── csr_bankarray (CSRBankArray) +│ └─── csrbank_0* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ └─── csrbank_1* (CSRBank) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstatus_1* (CSRStatus) +│ │ └─── csrstatus_2* (CSRStatus) +│ │ └─── csrstatus_3* (CSRStatus) +│ │ └─── csrstatus_4* (CSRStatus) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstatus_5* (CSRStatus) +│ │ └─── csrstatus_6* (CSRStatus) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstatus_7* (CSRStatus) +│ │ └─── csrstatus_8* (CSRStatus) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstatus_9* (CSRStatus) +│ │ └─── csrstatus_10* (CSRStatus) +│ │ └─── csrstatus_11* (CSRStatus) +│ └─── csrbank_2* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstatus_1* (CSRStatus) +└─── csr_interconnect (InterconnectShared) +└─── [ODDRX1F] +└─── [IDDRX1F] +└─── [ODDRX1F] +└─── [ODDRX1F] +└─── [FD1S3BX] +└─── [FD1S3BX] +└─── [ODDRX1F] +└─── [IDDRX1F] +└─── [IDDRX1F] +└─── [FD1S3BX] +└─── [ODDRX1F] +└─── [ODDRX1F] +└─── [FD1S3BX] +└─── [IDDRX1F] +└─── [IDDRX1F] +* : Generated name. +[]: BlackBox. +*/ + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +wire [13:0] builder_adr; +wire [39:0] builder_complexslicelowerer_slice_proxy; +reg [19:0] builder_count = 20'd1000000; +wire [31:0] builder_csrbank0_bus_errors_r; +reg builder_csrbank0_bus_errors_re = 1'd0; +wire [31:0] builder_csrbank0_bus_errors_w; +reg builder_csrbank0_bus_errors_we = 1'd0; +wire [1:0] builder_csrbank0_reset0_r; +reg builder_csrbank0_reset0_re = 1'd0; +wire [1:0] builder_csrbank0_reset0_w; +reg builder_csrbank0_reset0_we = 1'd0; +wire [31:0] builder_csrbank0_scratch0_r; +reg builder_csrbank0_scratch0_re = 1'd0; +wire [31:0] builder_csrbank0_scratch0_w; +reg builder_csrbank0_scratch0_we = 1'd0; +wire builder_csrbank0_sel; +wire builder_csrbank1_preamble_crc_r; +reg builder_csrbank1_preamble_crc_re = 1'd0; +wire builder_csrbank1_preamble_crc_w; +reg builder_csrbank1_preamble_crc_we = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_crc_errors_r; +reg builder_csrbank1_rx_datapath_crc_errors_re = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_crc_errors_w; +reg builder_csrbank1_rx_datapath_crc_errors_we = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_r; +reg builder_csrbank1_rx_datapath_preamble_errors_re = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_w; +reg builder_csrbank1_rx_datapath_preamble_errors_we = 1'd0; +wire builder_csrbank1_sel; +wire builder_csrbank1_sram_reader_ev_enable0_r; +reg builder_csrbank1_sram_reader_ev_enable0_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_enable0_w; +reg builder_csrbank1_sram_reader_ev_enable0_we = 1'd0; +wire builder_csrbank1_sram_reader_ev_pending_r; +reg builder_csrbank1_sram_reader_ev_pending_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_pending_w; +reg builder_csrbank1_sram_reader_ev_pending_we = 1'd0; +wire builder_csrbank1_sram_reader_ev_status_r; +reg builder_csrbank1_sram_reader_ev_status_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_status_w; +reg builder_csrbank1_sram_reader_ev_status_we = 1'd0; +wire [10:0] builder_csrbank1_sram_reader_length0_r; +reg builder_csrbank1_sram_reader_length0_re = 1'd0; +wire [10:0] builder_csrbank1_sram_reader_length0_w; +reg builder_csrbank1_sram_reader_length0_we = 1'd0; +wire [1:0] builder_csrbank1_sram_reader_level_r; +reg builder_csrbank1_sram_reader_level_re = 1'd0; +wire [1:0] builder_csrbank1_sram_reader_level_w; +reg builder_csrbank1_sram_reader_level_we = 1'd0; +wire builder_csrbank1_sram_reader_ready_r; +reg builder_csrbank1_sram_reader_ready_re = 1'd0; +wire builder_csrbank1_sram_reader_ready_w; +reg builder_csrbank1_sram_reader_ready_we = 1'd0; +wire builder_csrbank1_sram_reader_slot0_r; +reg builder_csrbank1_sram_reader_slot0_re = 1'd0; +wire builder_csrbank1_sram_reader_slot0_w; +reg builder_csrbank1_sram_reader_slot0_we = 1'd0; +wire [31:0] builder_csrbank1_sram_writer_errors_r; +reg builder_csrbank1_sram_writer_errors_re = 1'd0; +wire [31:0] builder_csrbank1_sram_writer_errors_w; +reg builder_csrbank1_sram_writer_errors_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_enable0_r; +reg builder_csrbank1_sram_writer_ev_enable0_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_enable0_w; +reg builder_csrbank1_sram_writer_ev_enable0_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_pending_r; +reg builder_csrbank1_sram_writer_ev_pending_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_pending_w; +reg builder_csrbank1_sram_writer_ev_pending_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_status_r; +reg builder_csrbank1_sram_writer_ev_status_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_status_w; +reg builder_csrbank1_sram_writer_ev_status_we = 1'd0; +wire [10:0] builder_csrbank1_sram_writer_length_r; +reg builder_csrbank1_sram_writer_length_re = 1'd0; +wire [10:0] builder_csrbank1_sram_writer_length_w; +reg builder_csrbank1_sram_writer_length_we = 1'd0; +wire builder_csrbank1_sram_writer_slot_r; +reg builder_csrbank1_sram_writer_slot_re = 1'd0; +wire builder_csrbank1_sram_writer_slot_w; +reg builder_csrbank1_sram_writer_slot_we = 1'd0; +wire builder_csrbank2_crg_reset0_r; +reg builder_csrbank2_crg_reset0_re = 1'd0; +wire builder_csrbank2_crg_reset0_w; +reg builder_csrbank2_crg_reset0_we = 1'd0; +wire builder_csrbank2_mdio_r_r; +reg builder_csrbank2_mdio_r_re = 1'd0; +wire builder_csrbank2_mdio_r_w; +reg builder_csrbank2_mdio_r_we = 1'd0; +wire [2:0] builder_csrbank2_mdio_w0_r; +reg builder_csrbank2_mdio_w0_re = 1'd0; +wire [2:0] builder_csrbank2_mdio_w0_w; +reg builder_csrbank2_mdio_w0_we = 1'd0; +wire [2:0] builder_csrbank2_rx_inband_status_r; +reg builder_csrbank2_rx_inband_status_re = 1'd0; +wire [2:0] builder_csrbank2_rx_inband_status_w; +reg builder_csrbank2_rx_inband_status_we = 1'd0; +wire builder_csrbank2_sel; +wire [31:0] builder_dat_r; +wire [31:0] builder_dat_w; +wire builder_done; +reg builder_error = 1'd0; +wire builder_grant; +reg builder_interface0_ack = 1'd0; +wire [29:0] builder_interface0_adr; +wire [13:0] builder_interface0_bank_bus_adr; +reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface0_bank_bus_dat_w; +wire builder_interface0_bank_bus_we; +wire [1:0] builder_interface0_bte; +wire [2:0] builder_interface0_cti; +wire builder_interface0_cyc; +reg [31:0] builder_interface0_dat_r = 32'd0; +wire [31:0] builder_interface0_dat_w; +reg builder_interface0_err = 1'd0; +wire [3:0] builder_interface0_sel; +wire builder_interface0_stb; +wire builder_interface0_we; +reg [13:0] builder_interface1_adr = 14'd0; +wire [13:0] builder_interface1_bank_bus_adr; +reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface1_bank_bus_dat_w; +wire builder_interface1_bank_bus_we; +wire [31:0] builder_interface1_dat_r; +reg [31:0] builder_interface1_dat_w = 32'd0; +reg builder_interface1_we = 1'd0; +wire [13:0] builder_interface2_bank_bus_adr; +reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface2_bank_bus_dat_w; +wire builder_interface2_bank_bus_we; +reg [1:0] builder_liteethmacsramreader_next_state = 2'd0; +reg [1:0] builder_liteethmacsramreader_state = 2'd0; +reg [2:0] builder_liteethmacsramwriter_next_state = 3'd0; +reg [2:0] builder_liteethmacsramwriter_state = 3'd0; +(* syn_no_retiming = "true" *) +reg builder_multiregimpl00 = 1'd0; +(* syn_no_retiming = "true" *) +reg builder_multiregimpl01 = 1'd0; +(* syn_no_retiming = "true" *) +reg [5:0] builder_multiregimpl10 = 6'd0; +(* syn_no_retiming = "true" *) +reg [5:0] builder_multiregimpl11 = 6'd0; +(* syn_no_retiming = "true" *) +reg [5:0] builder_multiregimpl20 = 6'd0; +(* syn_no_retiming = "true" *) +reg [5:0] builder_multiregimpl21 = 6'd0; +(* syn_no_retiming = "true" *) +reg builder_multiregimpl30 = 1'd0; +(* syn_no_retiming = "true" *) +reg builder_multiregimpl31 = 1'd0; +(* syn_no_retiming = "true" *) +reg builder_multiregimpl40 = 1'd0; +(* syn_no_retiming = "true" *) +reg builder_multiregimpl41 = 1'd0; +(* syn_no_retiming = "true" *) +reg [5:0] builder_multiregimpl50 = 6'd0; +(* syn_no_retiming = "true" *) +reg [5:0] builder_multiregimpl51 = 6'd0; +(* syn_no_retiming = "true" *) +reg [5:0] builder_multiregimpl60 = 6'd0; +(* syn_no_retiming = "true" *) +reg [5:0] builder_multiregimpl61 = 6'd0; +reg builder_next_state = 1'd0; +wire builder_request; +wire builder_rst10; +wire builder_rst11; +reg [1:0] builder_rxdatapath_bufferizeendpoints_next_state = 2'd0; +reg [1:0] builder_rxdatapath_bufferizeendpoints_state = 2'd0; +reg builder_rxdatapath_liteethmacpreamblechecker_next_state = 1'd0; +reg builder_rxdatapath_liteethmacpreamblechecker_state = 1'd0; +reg [29:0] builder_self0 = 30'd0; +reg [31:0] builder_self1 = 32'd0; +reg [3:0] builder_self2 = 4'd0; +reg builder_self3 = 1'd0; +reg builder_self4 = 1'd0; +reg builder_self5 = 1'd0; +reg [2:0] builder_self6 = 3'd0; +reg [1:0] builder_self7 = 2'd0; +reg builder_shared_ack = 1'd0; +wire [29:0] builder_shared_adr; +wire [1:0] builder_shared_bte; +wire [2:0] builder_shared_cti; +wire builder_shared_cyc; +reg [31:0] builder_shared_dat_r = 32'd0; +wire [31:0] builder_shared_dat_w; +wire builder_shared_err; +wire [3:0] builder_shared_sel; +wire builder_shared_stb; +wire builder_shared_we; +reg [1:0] builder_slave_sel = 2'd0; +reg [1:0] builder_slave_sel_r = 2'd0; +reg builder_state = 1'd0; +wire [31:0] builder_t_slice_proxy0; +wire [31:0] builder_t_slice_proxy1; +wire [31:0] builder_t_slice_proxy10; +wire [31:0] builder_t_slice_proxy11; +wire [31:0] builder_t_slice_proxy12; +wire [31:0] builder_t_slice_proxy13; +wire [31:0] builder_t_slice_proxy14; +wire [31:0] builder_t_slice_proxy15; +wire [31:0] builder_t_slice_proxy16; +wire [31:0] builder_t_slice_proxy17; +wire [31:0] builder_t_slice_proxy18; +wire [31:0] builder_t_slice_proxy19; +wire [31:0] builder_t_slice_proxy2; +wire [31:0] builder_t_slice_proxy20; +wire [31:0] builder_t_slice_proxy21; +wire [31:0] builder_t_slice_proxy22; +wire [31:0] builder_t_slice_proxy23; +wire [31:0] builder_t_slice_proxy24; +wire [31:0] builder_t_slice_proxy25; +wire [31:0] builder_t_slice_proxy26; +wire [31:0] builder_t_slice_proxy27; +wire [31:0] builder_t_slice_proxy28; +wire [31:0] builder_t_slice_proxy29; +wire [31:0] builder_t_slice_proxy3; +wire [31:0] builder_t_slice_proxy30; +wire [31:0] builder_t_slice_proxy31; +wire [31:0] builder_t_slice_proxy32; +wire [31:0] builder_t_slice_proxy33; +wire [31:0] builder_t_slice_proxy34; +wire [31:0] builder_t_slice_proxy35; +wire [31:0] builder_t_slice_proxy36; +wire [31:0] builder_t_slice_proxy37; +wire [31:0] builder_t_slice_proxy38; +wire [31:0] builder_t_slice_proxy39; +wire [31:0] builder_t_slice_proxy4; +wire [31:0] builder_t_slice_proxy40; +wire [31:0] builder_t_slice_proxy41; +wire [31:0] builder_t_slice_proxy42; +wire [31:0] builder_t_slice_proxy43; +wire [31:0] builder_t_slice_proxy44; +wire [31:0] builder_t_slice_proxy45; +wire [31:0] builder_t_slice_proxy46; +wire [31:0] builder_t_slice_proxy47; +wire [31:0] builder_t_slice_proxy48; +wire [31:0] builder_t_slice_proxy49; +wire [31:0] builder_t_slice_proxy5; +wire [31:0] builder_t_slice_proxy50; +wire [31:0] builder_t_slice_proxy51; +wire [31:0] builder_t_slice_proxy52; +wire [31:0] builder_t_slice_proxy53; +wire [31:0] builder_t_slice_proxy54; +wire [31:0] builder_t_slice_proxy55; +wire [31:0] builder_t_slice_proxy56; +wire [31:0] builder_t_slice_proxy57; +wire [31:0] builder_t_slice_proxy58; +wire [31:0] builder_t_slice_proxy59; +wire [31:0] builder_t_slice_proxy6; +wire [31:0] builder_t_slice_proxy60; +wire [31:0] builder_t_slice_proxy61; +wire [31:0] builder_t_slice_proxy62; +wire [31:0] builder_t_slice_proxy63; +wire [31:0] builder_t_slice_proxy7; +wire [31:0] builder_t_slice_proxy8; +wire [31:0] builder_t_slice_proxy9; +reg [1:0] builder_txdatapath_bufferizeendpoints_next_state = 2'd0; +reg [1:0] builder_txdatapath_bufferizeendpoints_state = 2'd0; +reg builder_txdatapath_liteethmacgap_next_state = 1'd0; +reg builder_txdatapath_liteethmacgap_state = 1'd0; +reg builder_txdatapath_liteethmacpaddinginserter_next_state = 1'd0; +reg builder_txdatapath_liteethmacpaddinginserter_state = 1'd0; +reg [1:0] builder_txdatapath_liteethmacpreambleinserter_next_state = 2'd0; +reg [1:0] builder_txdatapath_liteethmacpreambleinserter_state = 2'd0; +reg builder_txdatapath_liteethmactxlastbe_next_state = 1'd0; +reg builder_txdatapath_liteethmactxlastbe_state = 1'd0; +wire builder_wait; +wire builder_we; +(* syn_keep = "true" *) +wire eth_rx_clk; +wire eth_rx_rst; +(* syn_keep = "true" *) +wire eth_tx_clk; +wire eth_tx_rst; +wire main_bufferizeendpoints_pipe_valid_sink_first; +wire main_bufferizeendpoints_pipe_valid_sink_last; +wire [7:0] main_bufferizeendpoints_pipe_valid_sink_payload_data; +wire main_bufferizeendpoints_pipe_valid_sink_payload_error; +wire main_bufferizeendpoints_pipe_valid_sink_payload_last_be; +wire main_bufferizeendpoints_pipe_valid_sink_ready; +wire main_bufferizeendpoints_pipe_valid_sink_valid; +reg main_bufferizeendpoints_pipe_valid_source_first = 1'd0; +reg main_bufferizeendpoints_pipe_valid_source_last = 1'd0; +reg [7:0] main_bufferizeendpoints_pipe_valid_source_payload_data = 8'd0; +reg main_bufferizeendpoints_pipe_valid_source_payload_error = 1'd0; +reg main_bufferizeendpoints_pipe_valid_source_payload_last_be = 1'd0; +wire main_bufferizeendpoints_pipe_valid_source_ready; +reg main_bufferizeendpoints_pipe_valid_source_valid = 1'd0; +wire main_bufferizeendpoints_sink_sink_first; +wire main_bufferizeendpoints_sink_sink_last; +wire [7:0] main_bufferizeendpoints_sink_sink_payload_data; +wire main_bufferizeendpoints_sink_sink_payload_error; +wire main_bufferizeendpoints_sink_sink_payload_last_be; +wire main_bufferizeendpoints_sink_sink_ready; +wire main_bufferizeendpoints_sink_sink_valid; +wire main_bufferizeendpoints_source_source_first; +wire main_bufferizeendpoints_source_source_last; +wire [7:0] main_bufferizeendpoints_source_source_payload_data; +wire main_bufferizeendpoints_source_source_payload_error; +wire main_bufferizeendpoints_source_source_payload_last_be; +wire main_bufferizeendpoints_source_source_ready; +wire main_bufferizeendpoints_source_source_valid; +wire main_bus_ack; +wire [29:0] main_bus_adr; +wire [1:0] main_bus_bte; +wire [2:0] main_bus_cti; +wire main_bus_cyc; +wire [31:0] main_bus_dat_r; +wire [31:0] main_bus_dat_w; +wire main_bus_err; +wire [3:0] main_bus_sel; +wire main_bus_stb; +wire main_bus_we; +reg main_crc_errors_re = 1'd0; +reg [31:0] main_crc_errors_status = 32'd0; +wire main_crc_errors_we; +reg main_interface0_ack = 1'd0; +wire [29:0] main_interface0_adr; +wire [1:0] main_interface0_bte; +wire [2:0] main_interface0_cti; +wire main_interface0_cyc; +wire [31:0] main_interface0_dat_r; +wire [31:0] main_interface0_dat_w; +reg main_interface0_err = 1'd0; +wire [3:0] main_interface0_sel; +wire main_interface0_stb; +wire main_interface0_we; +reg main_interface1_ack = 1'd0; +wire [29:0] main_interface1_adr; +wire [1:0] main_interface1_bte; +wire [2:0] main_interface1_cti; +wire main_interface1_cyc; +wire [31:0] main_interface1_dat_r; +wire [31:0] main_interface1_dat_w; +reg main_interface1_err = 1'd0; +wire [3:0] main_interface1_sel; +wire main_interface1_stb; +wire main_interface1_we; +reg main_interface2_ack = 1'd0; +wire [29:0] main_interface2_adr; +wire [1:0] main_interface2_bte; +wire [2:0] main_interface2_cti; +wire main_interface2_cyc; +wire [31:0] main_interface2_dat_r; +wire [31:0] main_interface2_dat_w; +reg main_interface2_err = 1'd0; +wire [3:0] main_interface2_sel; +wire main_interface2_stb; +wire main_interface2_we; +reg main_interface3_ack = 1'd0; +wire [29:0] main_interface3_adr; +wire [1:0] main_interface3_bte; +wire [2:0] main_interface3_cti; +wire main_interface3_cyc; +wire [31:0] main_interface3_dat_r; +wire [31:0] main_interface3_dat_w; +reg main_interface3_err = 1'd0; +wire [3:0] main_interface3_sel; +wire main_interface3_stb; +wire main_interface3_we; +reg [3:0] main_length_inc = 4'd0; +wire main_liteethmaccrc32checker_crc_be; +reg main_liteethmaccrc32checker_crc_ce = 1'd0; +reg [31:0] main_liteethmaccrc32checker_crc_crc_next = 32'd0; +wire [31:0] main_liteethmaccrc32checker_crc_crc_prev; +wire [7:0] main_liteethmaccrc32checker_crc_data0; +wire [7:0] main_liteethmaccrc32checker_crc_data1; +reg main_liteethmaccrc32checker_crc_error0 = 1'd0; +reg main_liteethmaccrc32checker_crc_error1 = 1'd0; +reg main_liteethmaccrc32checker_crc_error1_next_value1 = 1'd0; +reg main_liteethmaccrc32checker_crc_error1_next_value_ce1 = 1'd0; +reg [31:0] main_liteethmaccrc32checker_crc_reg = 32'd4294967295; +reg main_liteethmaccrc32checker_crc_reset = 1'd0; +reg [31:0] main_liteethmaccrc32checker_crc_value = 32'd0; +reg main_liteethmaccrc32checker_error = 1'd0; +wire main_liteethmaccrc32checker_fifo_full; +wire main_liteethmaccrc32checker_fifo_in; +wire main_liteethmaccrc32checker_fifo_out; +reg main_liteethmaccrc32checker_fifo_reset = 1'd0; +reg main_liteethmaccrc32checker_last_be = 1'd0; +reg main_liteethmaccrc32checker_last_be_next_value0 = 1'd0; +reg main_liteethmaccrc32checker_last_be_next_value_ce0 = 1'd0; +wire main_liteethmaccrc32checker_sink_sink_first; +wire main_liteethmaccrc32checker_sink_sink_last; +wire [7:0] main_liteethmaccrc32checker_sink_sink_payload_data; +wire main_liteethmaccrc32checker_sink_sink_payload_error; +wire main_liteethmaccrc32checker_sink_sink_payload_last_be; +reg main_liteethmaccrc32checker_sink_sink_ready = 1'd0; +wire main_liteethmaccrc32checker_sink_sink_valid; +wire main_liteethmaccrc32checker_source_source_first; +reg main_liteethmaccrc32checker_source_source_last = 1'd0; +wire [7:0] main_liteethmaccrc32checker_source_source_payload_data; +reg main_liteethmaccrc32checker_source_source_payload_error = 1'd0; +reg main_liteethmaccrc32checker_source_source_payload_last_be = 1'd0; +wire main_liteethmaccrc32checker_source_source_ready; +reg main_liteethmaccrc32checker_source_source_valid = 1'd0; +reg [2:0] main_liteethmaccrc32checker_syncfifo_consume = 3'd0; +wire main_liteethmaccrc32checker_syncfifo_do_read; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_first; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_first; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; +reg [2:0] main_liteethmaccrc32checker_syncfifo_level = 3'd0; +reg [2:0] main_liteethmaccrc32checker_syncfifo_produce = 3'd0; +wire [2:0] main_liteethmaccrc32checker_syncfifo_rdport_adr; +wire [11:0] main_liteethmaccrc32checker_syncfifo_rdport_dat_r; +reg main_liteethmaccrc32checker_syncfifo_replace = 1'd0; +wire main_liteethmaccrc32checker_syncfifo_sink_first; +wire main_liteethmaccrc32checker_syncfifo_sink_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_sink_payload_data; +wire main_liteethmaccrc32checker_syncfifo_sink_payload_error; +wire main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; +wire main_liteethmaccrc32checker_syncfifo_sink_ready; +reg main_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; +wire main_liteethmaccrc32checker_syncfifo_source_first; +wire main_liteethmaccrc32checker_syncfifo_source_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_source_payload_data; +wire main_liteethmaccrc32checker_syncfifo_source_payload_error; +wire main_liteethmaccrc32checker_syncfifo_source_payload_last_be; +reg main_liteethmaccrc32checker_syncfifo_source_ready = 1'd0; +wire main_liteethmaccrc32checker_syncfifo_source_valid; +wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_din; +wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_dout; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_re; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_readable; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_we; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_writable; +reg [2:0] main_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; +wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_r; +wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_w; +wire main_liteethmaccrc32checker_syncfifo_wrport_we; +reg main_maccore_ethphy__r_re = 1'd0; +reg main_maccore_ethphy__r_status = 1'd0; +wire main_maccore_ethphy__r_we; +reg main_maccore_ethphy__w_re = 1'd0; +reg [2:0] main_maccore_ethphy__w_storage = 3'd0; +reg main_maccore_ethphy_clock_speed = 1'd0; +wire main_maccore_ethphy_data_oe; +wire main_maccore_ethphy_data_r; +wire main_maccore_ethphy_data_w; +reg main_maccore_ethphy_duplex_status = 1'd0; +wire main_maccore_ethphy_eth_tx_clk_o; +wire main_maccore_ethphy_last; +reg main_maccore_ethphy_link_status = 1'd0; +wire main_maccore_ethphy_mdc; +wire main_maccore_ethphy_oe; +reg main_maccore_ethphy_r = 1'd0; +reg main_maccore_ethphy_re = 1'd0; +wire main_maccore_ethphy_reset; +reg main_maccore_ethphy_reset_re = 1'd0; +reg main_maccore_ethphy_reset_storage = 1'd0; +wire [1:0] main_maccore_ethphy_rx_ctl; +wire main_maccore_ethphy_rx_ctl_delayf; +reg [1:0] main_maccore_ethphy_rx_ctl_reg = 2'd0; +reg [1:0] main_maccore_ethphy_rx_ctl_reg_d = 2'd0; +wire [7:0] main_maccore_ethphy_rx_data; +wire [3:0] main_maccore_ethphy_rx_data_delayf; +reg [7:0] main_maccore_ethphy_rx_data_reg = 8'd0; +wire main_maccore_ethphy_sink_first; +wire main_maccore_ethphy_sink_last; +wire [7:0] main_maccore_ethphy_sink_payload_data; +wire main_maccore_ethphy_sink_payload_error; +wire main_maccore_ethphy_sink_payload_last_be; +wire main_maccore_ethphy_sink_ready; +wire main_maccore_ethphy_sink_valid; +reg main_maccore_ethphy_source_first = 1'd0; +wire main_maccore_ethphy_source_last; +reg [7:0] main_maccore_ethphy_source_payload_data = 8'd0; +reg main_maccore_ethphy_source_payload_error = 1'd0; +reg main_maccore_ethphy_source_payload_last_be = 1'd0; +wire main_maccore_ethphy_source_ready; +reg main_maccore_ethphy_source_valid = 1'd0; +reg [2:0] main_maccore_ethphy_status = 3'd0; +wire main_maccore_ethphy_tx_ctl_oddrx1f; +wire [3:0] main_maccore_ethphy_tx_data_oddrx1f; +wire main_maccore_ethphy_w; +wire main_maccore_ethphy_we; +reg main_maccore_int_rst = 1'd1; +wire main_maccore_maccore_bus_error; +reg [31:0] main_maccore_maccore_bus_errors = 32'd0; +reg main_maccore_maccore_bus_errors_re = 1'd0; +wire [31:0] main_maccore_maccore_bus_errors_status; +wire main_maccore_maccore_bus_errors_we; +wire main_maccore_maccore_cpu_rst; +reg main_maccore_maccore_reset_re = 1'd0; +reg [1:0] main_maccore_maccore_reset_storage = 2'd0; +reg main_maccore_maccore_scratch_re = 1'd0; +reg [31:0] main_maccore_maccore_scratch_storage = 32'd305419896; +reg main_maccore_maccore_soc_rst = 1'd0; +reg main_preamble_errors_re = 1'd0; +reg [31:0] main_preamble_errors_status = 32'd0; +wire main_preamble_errors_we; +wire main_pulsesynchronizer0_i; +wire main_pulsesynchronizer0_o; +reg main_pulsesynchronizer0_toggle_i = 1'd0; +wire main_pulsesynchronizer0_toggle_o; +reg main_pulsesynchronizer0_toggle_o_r = 1'd0; +wire main_pulsesynchronizer1_i; +wire main_pulsesynchronizer1_o; +reg main_pulsesynchronizer1_toggle_i = 1'd0; +wire main_pulsesynchronizer1_toggle_o; +reg main_pulsesynchronizer1_toggle_o_r = 1'd0; +reg [31:0] main_rd_data = 32'd0; +reg main_re = 1'd0; +reg main_read = 1'd0; +wire [41:0] main_rx_cdc_cdc_asyncfifo_din; +wire [41:0] main_rx_cdc_cdc_asyncfifo_dout; +wire main_rx_cdc_cdc_asyncfifo_re; +wire main_rx_cdc_cdc_asyncfifo_readable; +wire main_rx_cdc_cdc_asyncfifo_we; +wire main_rx_cdc_cdc_asyncfifo_writable; +wire [5:0] main_rx_cdc_cdc_consume_wdomain; +wire main_rx_cdc_cdc_fifo_in_first; +wire main_rx_cdc_cdc_fifo_in_last; +wire [31:0] main_rx_cdc_cdc_fifo_in_payload_data; +wire [3:0] main_rx_cdc_cdc_fifo_in_payload_error; +wire [3:0] main_rx_cdc_cdc_fifo_in_payload_last_be; +wire main_rx_cdc_cdc_fifo_out_first; +wire main_rx_cdc_cdc_fifo_out_last; +wire [31:0] main_rx_cdc_cdc_fifo_out_payload_data; +wire [3:0] main_rx_cdc_cdc_fifo_out_payload_error; +wire [3:0] main_rx_cdc_cdc_fifo_out_payload_last_be; +wire main_rx_cdc_cdc_graycounter0_ce; +(* syn_no_retiming = "true" *) +reg [5:0] main_rx_cdc_cdc_graycounter0_q = 6'd0; +reg [5:0] main_rx_cdc_cdc_graycounter0_q_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_graycounter0_q_next; +reg [5:0] main_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire main_rx_cdc_cdc_graycounter1_ce; +(* syn_no_retiming = "true" *) +reg [5:0] main_rx_cdc_cdc_graycounter1_q = 6'd0; +reg [5:0] main_rx_cdc_cdc_graycounter1_q_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_graycounter1_q_next; +reg [5:0] main_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_produce_rdomain; +wire [4:0] main_rx_cdc_cdc_rdport_adr; +wire [41:0] main_rx_cdc_cdc_rdport_dat_r; +wire main_rx_cdc_cdc_sink_first; +wire main_rx_cdc_cdc_sink_last; +wire [31:0] main_rx_cdc_cdc_sink_payload_data; +wire [3:0] main_rx_cdc_cdc_sink_payload_error; +wire [3:0] main_rx_cdc_cdc_sink_payload_last_be; +wire main_rx_cdc_cdc_sink_ready; +wire main_rx_cdc_cdc_sink_valid; +wire main_rx_cdc_cdc_source_first; +wire main_rx_cdc_cdc_source_last; +wire [31:0] main_rx_cdc_cdc_source_payload_data; +wire [3:0] main_rx_cdc_cdc_source_payload_error; +wire [3:0] main_rx_cdc_cdc_source_payload_last_be; +wire main_rx_cdc_cdc_source_ready; +wire main_rx_cdc_cdc_source_valid; +wire [4:0] main_rx_cdc_cdc_wrport_adr; +wire [41:0] main_rx_cdc_cdc_wrport_dat_r; +wire [41:0] main_rx_cdc_cdc_wrport_dat_w; +wire main_rx_cdc_cdc_wrport_we; +wire main_rx_cdc_sink_sink_first; +wire main_rx_cdc_sink_sink_last; +wire [31:0] main_rx_cdc_sink_sink_payload_data; +wire [3:0] main_rx_cdc_sink_sink_payload_error; +wire [3:0] main_rx_cdc_sink_sink_payload_last_be; +wire main_rx_cdc_sink_sink_ready; +wire main_rx_cdc_sink_sink_valid; +wire main_rx_cdc_source_source_first; +wire main_rx_cdc_source_source_last; +wire [31:0] main_rx_cdc_source_source_payload_data; +wire [3:0] main_rx_cdc_source_source_payload_error; +wire [3:0] main_rx_cdc_source_source_payload_last_be; +wire main_rx_cdc_source_source_ready; +wire main_rx_cdc_source_source_valid; +reg [1:0] main_rx_converter_converter_demux = 2'd0; +wire main_rx_converter_converter_load_part; +wire main_rx_converter_converter_sink_first; +wire main_rx_converter_converter_sink_last; +wire [9:0] main_rx_converter_converter_sink_payload_data; +wire main_rx_converter_converter_sink_ready; +wire main_rx_converter_converter_sink_valid; +reg main_rx_converter_converter_source_first = 1'd0; +reg main_rx_converter_converter_source_last = 1'd0; +reg [39:0] main_rx_converter_converter_source_payload_data = 40'd0; +reg [2:0] main_rx_converter_converter_source_payload_valid_token_count = 3'd0; +wire main_rx_converter_converter_source_ready; +wire main_rx_converter_converter_source_valid; +reg main_rx_converter_converter_strobe_all = 1'd0; +wire main_rx_converter_sink_first; +wire main_rx_converter_sink_last; +wire [7:0] main_rx_converter_sink_payload_data; +wire main_rx_converter_sink_payload_error; +wire main_rx_converter_sink_payload_last_be; +wire main_rx_converter_sink_ready; +wire main_rx_converter_sink_valid; +wire main_rx_converter_source_first; +wire main_rx_converter_source_last; +reg [31:0] main_rx_converter_source_payload_data = 32'd0; +reg [3:0] main_rx_converter_source_payload_error = 4'd0; +reg [3:0] main_rx_converter_source_payload_last_be = 4'd0; +wire main_rx_converter_source_ready; +wire main_rx_converter_source_source_first; +wire main_rx_converter_source_source_last; +wire [39:0] main_rx_converter_source_source_payload_data; +wire main_rx_converter_source_source_ready; +wire main_rx_converter_source_source_valid; +wire main_rx_converter_source_valid; +wire main_rx_last_be_sink_first; +wire main_rx_last_be_sink_last; +wire [7:0] main_rx_last_be_sink_payload_data; +wire main_rx_last_be_sink_payload_error; +wire main_rx_last_be_sink_payload_last_be; +wire main_rx_last_be_sink_ready; +wire main_rx_last_be_sink_valid; +wire main_rx_last_be_source_first; +wire main_rx_last_be_source_last; +wire [7:0] main_rx_last_be_source_payload_data; +wire main_rx_last_be_source_payload_error; +reg main_rx_last_be_source_payload_last_be = 1'd0; +wire main_rx_last_be_source_ready; +wire main_rx_last_be_source_valid; +wire main_rx_padding_sink_first; +wire main_rx_padding_sink_last; +wire [7:0] main_rx_padding_sink_payload_data; +wire main_rx_padding_sink_payload_error; +wire main_rx_padding_sink_payload_last_be; +wire main_rx_padding_sink_ready; +wire main_rx_padding_sink_valid; +wire main_rx_padding_source_first; +wire main_rx_padding_source_last; +wire [7:0] main_rx_padding_source_payload_data; +wire main_rx_padding_source_payload_error; +wire main_rx_padding_source_payload_last_be; +wire main_rx_padding_source_ready; +wire main_rx_padding_source_valid; +reg main_rx_preamble_error = 1'd0; +reg [63:0] main_rx_preamble_preamble = 64'd15372286728091293013; +wire main_rx_preamble_sink_first; +wire main_rx_preamble_sink_last; +wire [7:0] main_rx_preamble_sink_payload_data; +wire main_rx_preamble_sink_payload_error; +wire main_rx_preamble_sink_payload_last_be; +reg main_rx_preamble_sink_ready = 1'd0; +wire main_rx_preamble_sink_valid; +reg main_rx_preamble_source_first = 1'd0; +reg main_rx_preamble_source_last = 1'd0; +wire [7:0] main_rx_preamble_source_payload_data; +reg main_rx_preamble_source_payload_error = 1'd0; +wire main_rx_preamble_source_payload_last_be; +wire main_rx_preamble_source_ready; +reg main_rx_preamble_source_valid = 1'd0; +wire main_sink_first; +wire main_sink_last; +wire [31:0] main_sink_payload_data; +wire [3:0] main_sink_payload_error; +wire [3:0] main_sink_payload_last_be; +wire main_sink_ready; +wire main_sink_sink_first; +wire main_sink_sink_last; +wire [31:0] main_sink_sink_payload_data; +wire [3:0] main_sink_sink_payload_error; +wire [3:0] main_sink_sink_payload_last_be; +wire main_sink_sink_ready; +wire main_sink_sink_valid; +wire main_sink_valid; +reg [3:0] main_slave_sel = 4'd0; +reg [3:0] main_slave_sel_r = 4'd0; +reg main_slot = 1'd0; +reg main_slot_liteethmacsramwriter_next_value = 1'd0; +reg main_slot_liteethmacsramwriter_next_value_ce = 1'd0; +wire main_source_first; +wire main_source_last; +wire [31:0] main_source_payload_data; +wire [3:0] main_source_payload_error; +wire [3:0] main_source_payload_last_be; +wire main_source_ready; +wire main_source_source_first; +wire main_source_source_last; +wire [31:0] main_source_source_payload_data; +wire [3:0] main_source_source_payload_error; +wire [3:0] main_source_source_payload_last_be; +wire main_source_source_ready; +wire main_source_source_valid; +wire main_source_valid; +wire [8:0] main_sram0_adr; +reg main_sram0_adr_burst = 1'd0; +wire [31:0] main_sram0_dat_r; +wire main_sram0_sink_valid; +reg main_sram100_storage = 1'd0; +reg main_sram101_re = 1'd0; +reg [10:0] main_sram102_storage = 11'd0; +reg main_sram103_re = 1'd0; +wire main_sram104_irq; +wire main_sram105_status; +reg main_sram106_pending = 1'd0; +reg main_sram107_trigger = 1'd0; +reg main_sram108_clear = 1'd0; +wire main_sram109_event0; +wire [10:0] main_sram10_status; +reg main_sram110_status = 1'd0; +wire main_sram111_we; +reg main_sram112_re = 1'd0; +wire main_sram113_event0; +reg main_sram114_status = 1'd0; +wire main_sram115_we; +reg main_sram116_re = 1'd0; +reg main_sram117_r = 1'd0; +wire main_sram118_event0; +reg main_sram119_storage = 1'd0; +wire main_sram11_we; +reg main_sram120_re = 1'd0; +reg [10:0] main_sram122_length = 11'd0; +reg [10:0] main_sram122_length_liteethmacsramreader_next_value = 11'd0; +reg main_sram122_length_liteethmacsramreader_next_value_ce = 1'd0; +wire main_sram123_sink_valid; +wire main_sram124_sink_ready; +reg main_sram125_sink_first = 1'd0; +reg main_sram126_sink_last = 1'd0; +wire main_sram127_sink_payload_slot; +wire [10:0] main_sram128_sink_payload_length; +wire main_sram129_source_valid; +reg main_sram12_re = 1'd0; +reg main_sram130_source_ready = 1'd0; +wire main_sram131_source_first; +wire main_sram132_source_last; +wire main_sram133_source_payload_slot; +wire [10:0] main_sram134_source_payload_length; +wire main_sram135_we; +wire main_sram136_writable; +wire main_sram137_re; +wire main_sram138_readable; +wire [13:0] main_sram139_din; +reg [31:0] main_sram13_status = 32'd0; +reg [31:0] main_sram13_status_liteethmacsramwriter_f_next_value = 32'd0; +reg main_sram13_status_liteethmacsramwriter_f_next_value_ce = 1'd0; +wire [13:0] main_sram140_dout; +reg [1:0] main_sram141_level = 2'd0; +reg main_sram142_replace = 1'd0; +reg main_sram143_produce = 1'd0; +reg main_sram144_consume = 1'd0; +reg main_sram145_adr = 1'd0; +wire [13:0] main_sram146_dat_r; +wire main_sram147_we; +wire [13:0] main_sram148_dat_w; +wire main_sram149_do_read; +wire main_sram14_we; +wire main_sram150_adr; +wire [13:0] main_sram151_dat_r; +wire main_sram152_fifo_in_payload_slot; +wire [10:0] main_sram153_fifo_in_payload_length; +wire main_sram154_fifo_in_first; +wire main_sram155_fifo_in_last; +wire main_sram156_fifo_out_payload_slot; +wire [10:0] main_sram157_fifo_out_payload_length; +wire main_sram158_fifo_out_first; +wire main_sram159_fifo_out_last; +reg main_sram15_re = 1'd0; +wire [8:0] main_sram161_adr; +wire [31:0] main_sram162_dat_r; +wire main_sram163_re; +wire [8:0] main_sram164_adr; +wire [31:0] main_sram165_dat_r; +wire main_sram166_re; +wire main_sram167_irq; +wire main_sram16_irq; +wire main_sram17_status; +wire main_sram18_pending; +wire main_sram19_trigger; +wire [8:0] main_sram1_adr; +reg main_sram1_adr_burst = 1'd0; +wire [31:0] main_sram1_dat_r; +reg main_sram1_sink_ready = 1'd1; +reg main_sram20_clear = 1'd0; +wire main_sram21_available; +reg main_sram22_status = 1'd0; +wire main_sram23_we; +reg main_sram24_re = 1'd0; +wire main_sram25_available; +reg main_sram26_status = 1'd0; +wire main_sram27_we; +reg main_sram28_re = 1'd0; +reg main_sram29_r = 1'd0; +wire [8:0] main_sram2_adr; +reg main_sram2_adr_burst = 1'd0; +wire [31:0] main_sram2_dat_r; +wire [31:0] main_sram2_dat_w; +wire main_sram2_sink_first; +reg [3:0] main_sram2_we = 4'd0; +wire main_sram30_available; +reg main_sram31_storage = 1'd0; +reg main_sram32_re = 1'd0; +reg [10:0] main_sram35_length = 11'd0; +reg [10:0] main_sram35_length_liteethmacsramwriter_t_next_value = 11'd0; +reg main_sram35_length_liteethmacsramwriter_t_next_value_ce = 1'd0; +reg main_sram37_sink_valid = 1'd0; +wire main_sram38_sink_ready; +reg main_sram39_sink_first = 1'd0; +wire [8:0] main_sram3_adr; +reg main_sram3_adr_burst = 1'd0; +wire [31:0] main_sram3_dat_r; +wire [31:0] main_sram3_dat_w; +wire main_sram3_sink_last; +reg [3:0] main_sram3_we = 4'd0; +reg main_sram40_sink_last = 1'd0; +reg main_sram41_sink_payload_slot = 1'd0; +reg [10:0] main_sram42_sink_payload_length = 11'd0; +wire main_sram43_source_valid; +wire main_sram44_source_ready; +wire main_sram45_source_first; +wire main_sram46_source_last; +wire main_sram47_source_payload_slot; +wire [10:0] main_sram48_source_payload_length; +wire main_sram49_we; +wire [31:0] main_sram4_sink_payload_data; +wire main_sram50_writable; +wire main_sram51_re; +wire main_sram52_readable; +wire [13:0] main_sram53_din; +wire [13:0] main_sram54_dout; +reg [1:0] main_sram55_level = 2'd0; +reg main_sram56_replace = 1'd0; +reg main_sram57_produce = 1'd0; +reg main_sram58_consume = 1'd0; +reg main_sram59_adr = 1'd0; +wire [3:0] main_sram5_sink_payload_last_be; +wire [13:0] main_sram60_dat_r; +wire main_sram61_we; +wire [13:0] main_sram62_dat_w; +wire main_sram63_do_read; +wire main_sram64_adr; +wire [13:0] main_sram65_dat_r; +wire main_sram66_fifo_in_payload_slot; +wire [10:0] main_sram67_fifo_in_payload_length; +wire main_sram68_fifo_in_first; +wire main_sram69_fifo_in_last; +wire [3:0] main_sram6_sink_payload_error; +wire main_sram70_fifo_out_payload_slot; +wire [10:0] main_sram71_fifo_out_payload_length; +wire main_sram72_fifo_out_first; +wire main_sram73_fifo_out_last; +reg [8:0] main_sram75_adr = 9'd0; +wire [31:0] main_sram76_dat_r; +reg main_sram77_we = 1'd0; +reg [31:0] main_sram78_dat_w = 32'd0; +reg [8:0] main_sram79_adr = 9'd0; +wire main_sram7_status; +wire [31:0] main_sram80_dat_r; +reg main_sram81_we = 1'd0; +reg [31:0] main_sram82_dat_w = 32'd0; +reg main_sram83_source_valid = 1'd0; +wire main_sram84_source_ready; +reg main_sram85_source_first = 1'd0; +reg main_sram86_source_last = 1'd0; +wire [31:0] main_sram87_source_payload_data; +reg [3:0] main_sram88_source_payload_last_be = 4'd0; +reg [3:0] main_sram89_source_payload_error = 4'd0; +wire main_sram8_we; +wire main_sram94_status; +wire main_sram95_we; +reg main_sram96_re = 1'd0; +wire [1:0] main_sram97_status; +wire main_sram98_we; +reg main_sram99_re = 1'd0; +reg main_sram9_re = 1'd0; +wire main_start_r; +reg main_start_re = 1'd0; +reg main_start_w = 1'd0; +reg main_start_we = 1'd0; +reg main_status = 1'd1; +wire [41:0] main_tx_cdc_cdc_asyncfifo_din; +wire [41:0] main_tx_cdc_cdc_asyncfifo_dout; +wire main_tx_cdc_cdc_asyncfifo_re; +wire main_tx_cdc_cdc_asyncfifo_readable; +wire main_tx_cdc_cdc_asyncfifo_we; +wire main_tx_cdc_cdc_asyncfifo_writable; +wire [5:0] main_tx_cdc_cdc_consume_wdomain; +wire main_tx_cdc_cdc_fifo_in_first; +wire main_tx_cdc_cdc_fifo_in_last; +wire [31:0] main_tx_cdc_cdc_fifo_in_payload_data; +wire [3:0] main_tx_cdc_cdc_fifo_in_payload_error; +wire [3:0] main_tx_cdc_cdc_fifo_in_payload_last_be; +wire main_tx_cdc_cdc_fifo_out_first; +wire main_tx_cdc_cdc_fifo_out_last; +wire [31:0] main_tx_cdc_cdc_fifo_out_payload_data; +wire [3:0] main_tx_cdc_cdc_fifo_out_payload_error; +wire [3:0] main_tx_cdc_cdc_fifo_out_payload_last_be; +wire main_tx_cdc_cdc_graycounter0_ce; +(* syn_no_retiming = "true" *) +reg [5:0] main_tx_cdc_cdc_graycounter0_q = 6'd0; +reg [5:0] main_tx_cdc_cdc_graycounter0_q_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_graycounter0_q_next; +reg [5:0] main_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire main_tx_cdc_cdc_graycounter1_ce; +(* syn_no_retiming = "true" *) +reg [5:0] main_tx_cdc_cdc_graycounter1_q = 6'd0; +reg [5:0] main_tx_cdc_cdc_graycounter1_q_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_graycounter1_q_next; +reg [5:0] main_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_produce_rdomain; +wire [4:0] main_tx_cdc_cdc_rdport_adr; +wire [41:0] main_tx_cdc_cdc_rdport_dat_r; +wire main_tx_cdc_cdc_sink_first; +wire main_tx_cdc_cdc_sink_last; +wire [31:0] main_tx_cdc_cdc_sink_payload_data; +wire [3:0] main_tx_cdc_cdc_sink_payload_error; +wire [3:0] main_tx_cdc_cdc_sink_payload_last_be; +wire main_tx_cdc_cdc_sink_ready; +wire main_tx_cdc_cdc_sink_valid; +wire main_tx_cdc_cdc_source_first; +wire main_tx_cdc_cdc_source_last; +wire [31:0] main_tx_cdc_cdc_source_payload_data; +wire [3:0] main_tx_cdc_cdc_source_payload_error; +wire [3:0] main_tx_cdc_cdc_source_payload_last_be; +wire main_tx_cdc_cdc_source_ready; +wire main_tx_cdc_cdc_source_valid; +wire [4:0] main_tx_cdc_cdc_wrport_adr; +wire [41:0] main_tx_cdc_cdc_wrport_dat_r; +wire [41:0] main_tx_cdc_cdc_wrport_dat_w; +wire main_tx_cdc_cdc_wrport_we; +wire main_tx_cdc_sink_sink_first; +wire main_tx_cdc_sink_sink_last; +wire [31:0] main_tx_cdc_sink_sink_payload_data; +wire [3:0] main_tx_cdc_sink_sink_payload_error; +wire [3:0] main_tx_cdc_sink_sink_payload_last_be; +wire main_tx_cdc_sink_sink_ready; +wire main_tx_cdc_sink_sink_valid; +wire main_tx_cdc_source_source_first; +wire main_tx_cdc_source_source_last; +wire [31:0] main_tx_cdc_source_source_payload_data; +wire [3:0] main_tx_cdc_source_source_payload_error; +wire [3:0] main_tx_cdc_source_source_payload_last_be; +wire main_tx_cdc_source_source_ready; +wire main_tx_cdc_source_source_valid; +wire main_tx_converter_converter_first; +wire main_tx_converter_converter_last; +reg [1:0] main_tx_converter_converter_mux = 2'd0; +wire main_tx_converter_converter_sink_first; +wire main_tx_converter_converter_sink_last; +reg [39:0] main_tx_converter_converter_sink_payload_data = 40'd0; +wire main_tx_converter_converter_sink_ready; +wire main_tx_converter_converter_sink_valid; +wire main_tx_converter_converter_source_first; +wire main_tx_converter_converter_source_last; +reg [9:0] main_tx_converter_converter_source_payload_data = 10'd0; +wire main_tx_converter_converter_source_payload_valid_token_count; +wire main_tx_converter_converter_source_ready; +wire main_tx_converter_converter_source_valid; +wire main_tx_converter_sink_first; +wire main_tx_converter_sink_last; +wire [31:0] main_tx_converter_sink_payload_data; +wire [3:0] main_tx_converter_sink_payload_error; +wire [3:0] main_tx_converter_sink_payload_last_be; +wire main_tx_converter_sink_ready; +wire main_tx_converter_sink_valid; +wire main_tx_converter_source_first; +wire main_tx_converter_source_last; +wire [7:0] main_tx_converter_source_payload_data; +wire main_tx_converter_source_payload_error; +wire main_tx_converter_source_payload_last_be; +wire main_tx_converter_source_ready; +wire main_tx_converter_source_source_first; +wire main_tx_converter_source_source_last; +wire [9:0] main_tx_converter_source_source_payload_data; +wire main_tx_converter_source_source_ready; +wire main_tx_converter_source_source_valid; +wire main_tx_converter_source_valid; +wire main_tx_crc_be; +reg main_tx_crc_ce = 1'd0; +reg [1:0] main_tx_crc_cnt = 2'd3; +wire main_tx_crc_cnt_done; +reg [31:0] main_tx_crc_crc_next = 32'd0; +reg [31:0] main_tx_crc_crc_packet = 32'd0; +reg [31:0] main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 = 32'd0; +reg main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 = 1'd0; +wire [31:0] main_tx_crc_crc_prev; +wire [7:0] main_tx_crc_data0; +wire [7:0] main_tx_crc_data1; +reg main_tx_crc_error = 1'd0; +reg main_tx_crc_is_ongoing0 = 1'd0; +reg main_tx_crc_is_ongoing1 = 1'd0; +reg main_tx_crc_last_be = 1'd0; +reg main_tx_crc_last_be_clockdomainsrenamer1_next_value1 = 1'd0; +reg main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 = 1'd0; +wire main_tx_crc_pipe_valid_sink_first; +wire main_tx_crc_pipe_valid_sink_last; +wire [7:0] main_tx_crc_pipe_valid_sink_payload_data; +wire main_tx_crc_pipe_valid_sink_payload_error; +wire main_tx_crc_pipe_valid_sink_payload_last_be; +wire main_tx_crc_pipe_valid_sink_ready; +wire main_tx_crc_pipe_valid_sink_valid; +reg main_tx_crc_pipe_valid_source_first = 1'd0; +reg main_tx_crc_pipe_valid_source_last = 1'd0; +reg [7:0] main_tx_crc_pipe_valid_source_payload_data = 8'd0; +reg main_tx_crc_pipe_valid_source_payload_error = 1'd0; +reg main_tx_crc_pipe_valid_source_payload_last_be = 1'd0; +wire main_tx_crc_pipe_valid_source_ready; +reg main_tx_crc_pipe_valid_source_valid = 1'd0; +reg [31:0] main_tx_crc_reg = 32'd4294967295; +reg main_tx_crc_reset = 1'd0; +wire main_tx_crc_sink_first; +wire main_tx_crc_sink_last; +wire [7:0] main_tx_crc_sink_payload_data; +wire main_tx_crc_sink_payload_error; +wire main_tx_crc_sink_payload_last_be; +reg main_tx_crc_sink_ready = 1'd0; +wire main_tx_crc_sink_sink_first; +wire main_tx_crc_sink_sink_last; +wire [7:0] main_tx_crc_sink_sink_payload_data; +wire main_tx_crc_sink_sink_payload_error; +wire main_tx_crc_sink_sink_payload_last_be; +wire main_tx_crc_sink_sink_ready; +wire main_tx_crc_sink_sink_valid; +wire main_tx_crc_sink_valid; +reg main_tx_crc_source_first = 1'd0; +reg main_tx_crc_source_last = 1'd0; +reg [7:0] main_tx_crc_source_payload_data = 8'd0; +reg main_tx_crc_source_payload_error = 1'd0; +reg main_tx_crc_source_payload_last_be = 1'd0; +wire main_tx_crc_source_ready; +wire main_tx_crc_source_source_first; +wire main_tx_crc_source_source_last; +wire [7:0] main_tx_crc_source_source_payload_data; +wire main_tx_crc_source_source_payload_error; +wire main_tx_crc_source_source_payload_last_be; +wire main_tx_crc_source_source_ready; +wire main_tx_crc_source_source_valid; +reg main_tx_crc_source_valid = 1'd0; +reg [31:0] main_tx_crc_value = 32'd0; +reg [3:0] main_tx_gap_counter = 4'd0; +reg [3:0] main_tx_gap_counter_clockdomainsrenamer3_next_value = 4'd0; +reg main_tx_gap_counter_clockdomainsrenamer3_next_value_ce = 1'd0; +wire main_tx_gap_sink_first; +wire main_tx_gap_sink_last; +wire [7:0] main_tx_gap_sink_payload_data; +wire main_tx_gap_sink_payload_error; +wire main_tx_gap_sink_payload_last_be; +reg main_tx_gap_sink_ready = 1'd0; +wire main_tx_gap_sink_valid; +reg main_tx_gap_source_first = 1'd0; +reg main_tx_gap_source_last = 1'd0; +reg [7:0] main_tx_gap_source_payload_data = 8'd0; +reg main_tx_gap_source_payload_error = 1'd0; +reg main_tx_gap_source_payload_last_be = 1'd0; +wire main_tx_gap_source_ready; +reg main_tx_gap_source_valid = 1'd0; +wire main_tx_last_be_sink_first; +wire main_tx_last_be_sink_last; +wire [7:0] main_tx_last_be_sink_payload_data; +wire main_tx_last_be_sink_payload_error; +wire main_tx_last_be_sink_payload_last_be; +reg main_tx_last_be_sink_ready = 1'd0; +wire main_tx_last_be_sink_valid; +reg main_tx_last_be_source_first = 1'd0; +reg main_tx_last_be_source_last = 1'd0; +reg [7:0] main_tx_last_be_source_payload_data = 8'd0; +reg main_tx_last_be_source_payload_error = 1'd0; +reg main_tx_last_be_source_payload_last_be = 1'd0; +wire main_tx_last_be_source_ready; +reg main_tx_last_be_source_valid = 1'd0; +reg [15:0] main_tx_padding_counter = 16'd0; +reg [15:0] main_tx_padding_counter_clockdomainsrenamer0_next_value = 16'd0; +reg main_tx_padding_counter_clockdomainsrenamer0_next_value_ce = 1'd0; +wire main_tx_padding_counter_done; +wire main_tx_padding_sink_first; +wire main_tx_padding_sink_last; +wire [7:0] main_tx_padding_sink_payload_data; +wire main_tx_padding_sink_payload_error; +wire main_tx_padding_sink_payload_last_be; +reg main_tx_padding_sink_ready = 1'd0; +wire main_tx_padding_sink_valid; +reg main_tx_padding_source_first = 1'd0; +reg main_tx_padding_source_last = 1'd0; +reg [7:0] main_tx_padding_source_payload_data = 8'd0; +reg main_tx_padding_source_payload_error = 1'd0; +reg main_tx_padding_source_payload_last_be = 1'd0; +wire main_tx_padding_source_ready; +reg main_tx_padding_source_valid = 1'd0; +reg [2:0] main_tx_preamble_count = 3'd0; +reg [2:0] main_tx_preamble_count_clockdomainsrenamer2_next_value = 3'd0; +reg main_tx_preamble_count_clockdomainsrenamer2_next_value_ce = 1'd0; +reg [63:0] main_tx_preamble_preamble = 64'd15372286728091293013; +wire main_tx_preamble_sink_first; +wire main_tx_preamble_sink_last; +wire [7:0] main_tx_preamble_sink_payload_data; +wire main_tx_preamble_sink_payload_error; +wire main_tx_preamble_sink_payload_last_be; +reg main_tx_preamble_sink_ready = 1'd0; +wire main_tx_preamble_sink_valid; +reg main_tx_preamble_source_first = 1'd0; +reg main_tx_preamble_source_last = 1'd0; +reg [7:0] main_tx_preamble_source_payload_data = 8'd0; +reg main_tx_preamble_source_payload_error = 1'd0; +wire main_tx_preamble_source_payload_last_be; +wire main_tx_preamble_source_ready; +reg main_tx_preamble_source_valid = 1'd0; +wire main_wb_bus_ack; +wire [29:0] main_wb_bus_adr; +wire [1:0] main_wb_bus_bte; +wire [2:0] main_wb_bus_cti; +wire main_wb_bus_cyc; +wire [31:0] main_wb_bus_dat_r; +wire [31:0] main_wb_bus_dat_w; +wire main_wb_bus_err; +wire [3:0] main_wb_bus_sel; +wire main_wb_bus_stb; +wire main_wb_bus_we; +wire main_we; +wire [31:0] main_wr_data; +reg main_write = 1'd0; +wire por_clk; +(* syn_keep = "true" *) +wire sys_clk; +wire sys_rst; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + +assign main_wb_bus_adr = wishbone_adr; +assign main_wb_bus_dat_w = wishbone_dat_w; +assign wishbone_dat_r = main_wb_bus_dat_r; +assign main_wb_bus_sel = wishbone_sel; +assign main_wb_bus_cyc = wishbone_cyc; +assign main_wb_bus_stb = wishbone_stb; +assign wishbone_ack = main_wb_bus_ack; +assign main_wb_bus_we = wishbone_we; +assign main_wb_bus_cti = wishbone_cti; +assign main_wb_bus_bte = wishbone_bte; +assign wishbone_err = main_wb_bus_err; +assign interrupt = main_sram167_irq; +assign main_maccore_maccore_bus_error = builder_error; +assign builder_shared_adr = builder_self0; +assign builder_shared_dat_w = builder_self1; +assign builder_shared_sel = builder_self2; +assign builder_shared_cyc = builder_self3; +assign builder_shared_stb = builder_self4; +assign builder_shared_we = builder_self5; +assign builder_shared_cti = builder_self6; +assign builder_shared_bte = builder_self7; +assign main_wb_bus_dat_r = builder_shared_dat_r; +assign main_wb_bus_ack = (builder_shared_ack & (builder_grant == 1'd0)); +assign main_wb_bus_err = (builder_shared_err & (builder_grant == 1'd0)); +assign builder_request = {main_wb_bus_cyc}; +assign builder_grant = 1'd0; +always @(*) begin + builder_slave_sel <= 2'd0; + builder_slave_sel[0] <= (builder_shared_adr[29:11] == 4'd8); + builder_slave_sel[1] <= (builder_shared_adr[29:14] == 1'd0); +end +assign main_bus_adr = builder_shared_adr; +assign main_bus_dat_w = builder_shared_dat_w; +assign main_bus_sel = builder_shared_sel; +assign main_bus_stb = builder_shared_stb; +assign main_bus_we = builder_shared_we; +assign main_bus_cti = builder_shared_cti; +assign main_bus_bte = builder_shared_bte; +assign builder_interface0_adr = builder_shared_adr; +assign builder_interface0_dat_w = builder_shared_dat_w; +assign builder_interface0_sel = builder_shared_sel; +assign builder_interface0_stb = builder_shared_stb; +assign builder_interface0_we = builder_shared_we; +assign builder_interface0_cti = builder_shared_cti; +assign builder_interface0_bte = builder_shared_bte; +assign main_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]); +assign builder_interface0_cyc = (builder_shared_cyc & builder_slave_sel[1]); +assign builder_shared_err = (main_bus_err | builder_interface0_err); +assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack)); +always @(*) begin + builder_error <= 1'd0; + builder_shared_ack <= 1'd0; + builder_shared_dat_r <= 32'd0; + builder_shared_ack <= (main_bus_ack | builder_interface0_ack); + builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & builder_interface0_dat_r)); + if (builder_done) begin + builder_shared_dat_r <= 32'd4294967295; + builder_shared_ack <= 1'd1; + builder_error <= 1'd1; + end +end +assign builder_done = (builder_count == 1'd0); +assign main_maccore_maccore_bus_errors_status = main_maccore_maccore_bus_errors; +assign sys_clk = sys_clock; +assign por_clk = sys_clock; +assign sys_rst = main_maccore_int_rst; +assign eth_rx_clk = rgmii_clocks_rx; +assign eth_tx_clk = eth_rx_clk; +assign main_maccore_ethphy_reset = main_maccore_ethphy_reset_storage; +assign rgmii_rst_n = (~main_maccore_ethphy_reset); +assign main_maccore_ethphy_sink_ready = 1'd1; +assign main_maccore_ethphy_last = ((~main_maccore_ethphy_rx_ctl_reg[0]) & main_maccore_ethphy_rx_ctl_reg_d[0]); +assign main_maccore_ethphy_source_last = main_maccore_ethphy_last; +assign rgmii_mdc = main_maccore_ethphy__w_storage[0]; +assign main_maccore_ethphy_data_oe = main_maccore_ethphy__w_storage[1]; +assign main_maccore_ethphy_data_w = main_maccore_ethphy__w_storage[2]; +assign main_sink_valid = main_source_source_valid; +assign main_source_source_ready = main_sink_ready; +assign main_sink_first = main_source_source_first; +assign main_sink_last = main_source_source_last; +assign main_sink_payload_data = main_source_source_payload_data; +assign main_sink_payload_last_be = main_source_source_payload_last_be; +assign main_sink_payload_error = main_source_source_payload_error; +assign main_sink_sink_valid = main_source_valid; +assign main_source_ready = main_sink_sink_ready; +assign main_sink_sink_first = main_source_first; +assign main_sink_sink_last = main_source_last; +assign main_sink_sink_payload_data = main_source_payload_data; +assign main_sink_sink_payload_last_be = main_source_payload_last_be; +assign main_sink_sink_payload_error = main_source_payload_error; +assign main_tx_cdc_cdc_sink_valid = main_tx_cdc_sink_sink_valid; +assign main_tx_cdc_sink_sink_ready = main_tx_cdc_cdc_sink_ready; +assign main_tx_cdc_cdc_sink_first = main_tx_cdc_sink_sink_first; +assign main_tx_cdc_cdc_sink_last = main_tx_cdc_sink_sink_last; +assign main_tx_cdc_cdc_sink_payload_data = main_tx_cdc_sink_sink_payload_data; +assign main_tx_cdc_cdc_sink_payload_last_be = main_tx_cdc_sink_sink_payload_last_be; +assign main_tx_cdc_cdc_sink_payload_error = main_tx_cdc_sink_sink_payload_error; +assign main_tx_cdc_source_source_valid = main_tx_cdc_cdc_source_valid; +assign main_tx_cdc_cdc_source_ready = main_tx_cdc_source_source_ready; +assign main_tx_cdc_source_source_first = main_tx_cdc_cdc_source_first; +assign main_tx_cdc_source_source_last = main_tx_cdc_cdc_source_last; +assign main_tx_cdc_source_source_payload_data = main_tx_cdc_cdc_source_payload_data; +assign main_tx_cdc_source_source_payload_last_be = main_tx_cdc_cdc_source_payload_last_be; +assign main_tx_cdc_source_source_payload_error = main_tx_cdc_cdc_source_payload_error; +assign main_tx_cdc_cdc_asyncfifo_din = {main_tx_cdc_cdc_fifo_in_last, main_tx_cdc_cdc_fifo_in_first, main_tx_cdc_cdc_fifo_in_payload_error, main_tx_cdc_cdc_fifo_in_payload_last_be, main_tx_cdc_cdc_fifo_in_payload_data}; +assign {main_tx_cdc_cdc_fifo_out_last, main_tx_cdc_cdc_fifo_out_first, main_tx_cdc_cdc_fifo_out_payload_error, main_tx_cdc_cdc_fifo_out_payload_last_be, main_tx_cdc_cdc_fifo_out_payload_data} = main_tx_cdc_cdc_asyncfifo_dout; +assign main_tx_cdc_cdc_sink_ready = main_tx_cdc_cdc_asyncfifo_writable; +assign main_tx_cdc_cdc_asyncfifo_we = main_tx_cdc_cdc_sink_valid; +assign main_tx_cdc_cdc_fifo_in_first = main_tx_cdc_cdc_sink_first; +assign main_tx_cdc_cdc_fifo_in_last = main_tx_cdc_cdc_sink_last; +assign main_tx_cdc_cdc_fifo_in_payload_data = main_tx_cdc_cdc_sink_payload_data; +assign main_tx_cdc_cdc_fifo_in_payload_last_be = main_tx_cdc_cdc_sink_payload_last_be; +assign main_tx_cdc_cdc_fifo_in_payload_error = main_tx_cdc_cdc_sink_payload_error; +assign main_tx_cdc_cdc_source_valid = main_tx_cdc_cdc_asyncfifo_readable; +assign main_tx_cdc_cdc_source_first = main_tx_cdc_cdc_fifo_out_first; +assign main_tx_cdc_cdc_source_last = main_tx_cdc_cdc_fifo_out_last; +assign main_tx_cdc_cdc_source_payload_data = main_tx_cdc_cdc_fifo_out_payload_data; +assign main_tx_cdc_cdc_source_payload_last_be = main_tx_cdc_cdc_fifo_out_payload_last_be; +assign main_tx_cdc_cdc_source_payload_error = main_tx_cdc_cdc_fifo_out_payload_error; +assign main_tx_cdc_cdc_asyncfifo_re = main_tx_cdc_cdc_source_ready; +assign main_tx_cdc_cdc_graycounter0_ce = (main_tx_cdc_cdc_asyncfifo_writable & main_tx_cdc_cdc_asyncfifo_we); +assign main_tx_cdc_cdc_graycounter1_ce = (main_tx_cdc_cdc_asyncfifo_readable & main_tx_cdc_cdc_asyncfifo_re); +assign main_tx_cdc_cdc_asyncfifo_writable = (((main_tx_cdc_cdc_graycounter0_q[5] == main_tx_cdc_cdc_consume_wdomain[5]) | (main_tx_cdc_cdc_graycounter0_q[4] == main_tx_cdc_cdc_consume_wdomain[4])) | (main_tx_cdc_cdc_graycounter0_q[3:0] != main_tx_cdc_cdc_consume_wdomain[3:0])); +assign main_tx_cdc_cdc_asyncfifo_readable = (main_tx_cdc_cdc_graycounter1_q != main_tx_cdc_cdc_produce_rdomain); +assign main_tx_cdc_cdc_wrport_adr = main_tx_cdc_cdc_graycounter0_q_binary[4:0]; +assign main_tx_cdc_cdc_wrport_dat_w = main_tx_cdc_cdc_asyncfifo_din; +assign main_tx_cdc_cdc_wrport_we = main_tx_cdc_cdc_graycounter0_ce; +assign main_tx_cdc_cdc_rdport_adr = main_tx_cdc_cdc_graycounter1_q_next_binary[4:0]; +assign main_tx_cdc_cdc_asyncfifo_dout = main_tx_cdc_cdc_rdport_dat_r; +always @(*) begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (main_tx_cdc_cdc_graycounter0_ce) begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= (main_tx_cdc_cdc_graycounter0_q_binary + 1'd1); + end else begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= main_tx_cdc_cdc_graycounter0_q_binary; + end +end +assign main_tx_cdc_cdc_graycounter0_q_next = (main_tx_cdc_cdc_graycounter0_q_next_binary ^ main_tx_cdc_cdc_graycounter0_q_next_binary[5:1]); +always @(*) begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (main_tx_cdc_cdc_graycounter1_ce) begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= (main_tx_cdc_cdc_graycounter1_q_binary + 1'd1); + end else begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= main_tx_cdc_cdc_graycounter1_q_binary; + end +end +assign main_tx_cdc_cdc_graycounter1_q_next = (main_tx_cdc_cdc_graycounter1_q_next_binary ^ main_tx_cdc_cdc_graycounter1_q_next_binary[5:1]); +assign main_tx_converter_converter_sink_valid = main_tx_converter_sink_valid; +assign main_tx_converter_converter_sink_first = main_tx_converter_sink_first; +assign main_tx_converter_converter_sink_last = main_tx_converter_sink_last; +assign main_tx_converter_sink_ready = main_tx_converter_converter_sink_ready; +always @(*) begin + main_tx_converter_converter_sink_payload_data <= 40'd0; + main_tx_converter_converter_sink_payload_data[7:0] <= main_tx_converter_sink_payload_data[7:0]; + main_tx_converter_converter_sink_payload_data[8] <= main_tx_converter_sink_payload_last_be[0]; + main_tx_converter_converter_sink_payload_data[9] <= main_tx_converter_sink_payload_error[0]; + main_tx_converter_converter_sink_payload_data[17:10] <= main_tx_converter_sink_payload_data[15:8]; + main_tx_converter_converter_sink_payload_data[18] <= main_tx_converter_sink_payload_last_be[1]; + main_tx_converter_converter_sink_payload_data[19] <= main_tx_converter_sink_payload_error[1]; + main_tx_converter_converter_sink_payload_data[27:20] <= main_tx_converter_sink_payload_data[23:16]; + main_tx_converter_converter_sink_payload_data[28] <= main_tx_converter_sink_payload_last_be[2]; + main_tx_converter_converter_sink_payload_data[29] <= main_tx_converter_sink_payload_error[2]; + main_tx_converter_converter_sink_payload_data[37:30] <= main_tx_converter_sink_payload_data[31:24]; + main_tx_converter_converter_sink_payload_data[38] <= main_tx_converter_sink_payload_last_be[3]; + main_tx_converter_converter_sink_payload_data[39] <= main_tx_converter_sink_payload_error[3]; +end +assign main_tx_converter_source_valid = main_tx_converter_source_source_valid; +assign main_tx_converter_source_first = main_tx_converter_source_source_first; +assign main_tx_converter_source_last = main_tx_converter_source_source_last; +assign main_tx_converter_source_source_ready = main_tx_converter_source_ready; +assign {main_tx_converter_source_payload_error, main_tx_converter_source_payload_last_be, main_tx_converter_source_payload_data} = main_tx_converter_source_source_payload_data; +assign main_tx_converter_source_source_valid = main_tx_converter_converter_source_valid; +assign main_tx_converter_converter_source_ready = main_tx_converter_source_source_ready; +assign main_tx_converter_source_source_first = main_tx_converter_converter_source_first; +assign main_tx_converter_source_source_last = main_tx_converter_converter_source_last; +assign main_tx_converter_source_source_payload_data = main_tx_converter_converter_source_payload_data; +assign main_tx_converter_converter_first = (main_tx_converter_converter_mux == 1'd0); +assign main_tx_converter_converter_last = (main_tx_converter_converter_mux == 2'd3); +assign main_tx_converter_converter_source_valid = main_tx_converter_converter_sink_valid; +assign main_tx_converter_converter_source_first = (main_tx_converter_converter_sink_first & main_tx_converter_converter_first); +assign main_tx_converter_converter_source_last = (main_tx_converter_converter_sink_last & main_tx_converter_converter_last); +assign main_tx_converter_converter_sink_ready = (main_tx_converter_converter_last & main_tx_converter_converter_source_ready); +always @(*) begin + main_tx_converter_converter_source_payload_data <= 10'd0; + case (main_tx_converter_converter_mux) + 1'd0: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[9:0]; + end + 1'd1: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[19:10]; + end + 2'd2: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[29:20]; + end + default: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[39:30]; + end + endcase +end +assign main_tx_converter_converter_source_payload_valid_token_count = main_tx_converter_converter_last; +always @(*) begin + builder_txdatapath_liteethmactxlastbe_next_state <= 1'd0; + main_tx_last_be_sink_ready <= 1'd0; + main_tx_last_be_source_first <= 1'd0; + main_tx_last_be_source_last <= 1'd0; + main_tx_last_be_source_payload_data <= 8'd0; + main_tx_last_be_source_payload_error <= 1'd0; + main_tx_last_be_source_payload_last_be <= 1'd0; + main_tx_last_be_source_valid <= 1'd0; + builder_txdatapath_liteethmactxlastbe_next_state <= builder_txdatapath_liteethmactxlastbe_state; + case (builder_txdatapath_liteethmactxlastbe_state) + 1'd1: begin + main_tx_last_be_sink_ready <= 1'd1; + if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_last)) begin + builder_txdatapath_liteethmactxlastbe_next_state <= 1'd0; + end + end + default: begin + main_tx_last_be_source_valid <= main_tx_last_be_sink_valid; + main_tx_last_be_sink_ready <= main_tx_last_be_source_ready; + main_tx_last_be_source_first <= main_tx_last_be_sink_first; + main_tx_last_be_source_last <= main_tx_last_be_sink_last; + main_tx_last_be_source_payload_data <= main_tx_last_be_sink_payload_data; + main_tx_last_be_source_payload_last_be <= main_tx_last_be_sink_payload_last_be; + main_tx_last_be_source_payload_error <= main_tx_last_be_sink_payload_error; + main_tx_last_be_source_last <= (main_tx_last_be_sink_payload_last_be != 1'd0); + if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_ready)) begin + if ((main_tx_last_be_source_last & (~main_tx_last_be_sink_last))) begin + builder_txdatapath_liteethmactxlastbe_next_state <= 1'd1; + end + end + end + endcase +end +assign main_tx_padding_counter_done = (main_tx_padding_counter >= 6'd59); +always @(*) begin + builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 16'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd0; + main_tx_padding_sink_ready <= 1'd0; + main_tx_padding_source_first <= 1'd0; + main_tx_padding_source_last <= 1'd0; + main_tx_padding_source_payload_data <= 8'd0; + main_tx_padding_source_payload_error <= 1'd0; + main_tx_padding_source_payload_last_be <= 1'd0; + main_tx_padding_source_valid <= 1'd0; + builder_txdatapath_liteethmacpaddinginserter_next_state <= builder_txdatapath_liteethmacpaddinginserter_state; + case (builder_txdatapath_liteethmacpaddinginserter_state) + 1'd1: begin + main_tx_padding_source_valid <= 1'd1; + if (main_tx_padding_counter_done) begin + main_tx_padding_source_payload_last_be <= 1'd1; + main_tx_padding_source_last <= 1'd1; + end + main_tx_padding_source_payload_data <= 1'd0; + if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (main_tx_padding_counter_done) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + end + end + end + default: begin + main_tx_padding_source_valid <= main_tx_padding_sink_valid; + main_tx_padding_sink_ready <= main_tx_padding_source_ready; + main_tx_padding_source_first <= main_tx_padding_sink_first; + main_tx_padding_source_last <= main_tx_padding_sink_last; + main_tx_padding_source_payload_data <= main_tx_padding_sink_payload_data; + main_tx_padding_source_payload_last_be <= main_tx_padding_sink_payload_last_be; + main_tx_padding_source_payload_error <= main_tx_padding_sink_payload_error; + if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (main_tx_padding_sink_last) begin + if ((~main_tx_padding_counter_done)) begin + main_tx_padding_source_last <= 1'd0; + main_tx_padding_source_payload_last_be <= 1'd0; + builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd1; + end else begin + if (((main_tx_padding_counter == 6'd59) & (main_tx_padding_sink_payload_last_be < 1'd1))) begin + main_tx_padding_source_payload_last_be <= 1'd1; + end else begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + end + end + end + end + end + endcase +end +assign main_tx_crc_data0 = main_tx_crc_sink_payload_data; +assign main_tx_crc_be = main_tx_crc_sink_payload_last_be; +assign main_tx_crc_cnt_done = (main_tx_crc_cnt == 1'd0); +assign main_tx_crc_sink_valid = main_tx_crc_source_source_valid; +assign main_tx_crc_source_source_ready = main_tx_crc_sink_ready; +assign main_tx_crc_sink_first = main_tx_crc_source_source_first; +assign main_tx_crc_sink_last = main_tx_crc_source_source_last; +assign main_tx_crc_sink_payload_data = main_tx_crc_source_source_payload_data; +assign main_tx_crc_sink_payload_last_be = main_tx_crc_source_source_payload_last_be; +assign main_tx_crc_sink_payload_error = main_tx_crc_source_source_payload_error; +assign main_tx_crc_data1 = main_tx_crc_data0[7:0]; +assign main_tx_crc_crc_prev = main_tx_crc_reg; +always @(*) begin + main_tx_crc_error <= 1'd0; + main_tx_crc_value <= 32'd0; + if (main_tx_crc_be) begin + main_tx_crc_value <= {builder_t_slice_proxy31[0], builder_t_slice_proxy30[1], builder_t_slice_proxy29[2], builder_t_slice_proxy28[3], builder_t_slice_proxy27[4], builder_t_slice_proxy26[5], builder_t_slice_proxy25[6], builder_t_slice_proxy24[7], builder_t_slice_proxy23[8], builder_t_slice_proxy22[9], builder_t_slice_proxy21[10], builder_t_slice_proxy20[11], builder_t_slice_proxy19[12], builder_t_slice_proxy18[13], builder_t_slice_proxy17[14], builder_t_slice_proxy16[15], builder_t_slice_proxy15[16], builder_t_slice_proxy14[17], builder_t_slice_proxy13[18], builder_t_slice_proxy12[19], builder_t_slice_proxy11[20], builder_t_slice_proxy10[21], builder_t_slice_proxy9[22], builder_t_slice_proxy8[23], builder_t_slice_proxy7[24], builder_t_slice_proxy6[25], builder_t_slice_proxy5[26], builder_t_slice_proxy4[27], builder_t_slice_proxy3[28], builder_t_slice_proxy2[29], builder_t_slice_proxy1[30], builder_t_slice_proxy0[31]}; + main_tx_crc_error <= (main_tx_crc_crc_next != 32'd3338984827); + end +end +always @(*) begin + main_tx_crc_crc_next <= 32'd0; + main_tx_crc_crc_next[0] <= (((main_tx_crc_crc_prev[24] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[1] <= (((((((main_tx_crc_crc_prev[25] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[2] <= (((((((((main_tx_crc_crc_prev[26] ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[3] <= (((((((main_tx_crc_crc_prev[27] ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[4] <= (((((((((main_tx_crc_crc_prev[28] ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[5] <= (((((((((((((main_tx_crc_crc_prev[29] ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[6] <= (((((((((((main_tx_crc_crc_prev[30] ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[7] <= (((((((((main_tx_crc_crc_prev[31] ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[8] <= ((((((((main_tx_crc_crc_prev[0] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[9] <= ((((((((main_tx_crc_crc_prev[1] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[10] <= ((((((((main_tx_crc_crc_prev[2] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[11] <= ((((((((main_tx_crc_crc_prev[3] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[12] <= ((((((((((((main_tx_crc_crc_prev[4] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[13] <= ((((((((((((main_tx_crc_crc_prev[5] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[14] <= ((((((((((main_tx_crc_crc_prev[6] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[15] <= ((((((((main_tx_crc_crc_prev[7] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); + main_tx_crc_crc_next[16] <= ((((((main_tx_crc_crc_prev[8] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[17] <= ((((((main_tx_crc_crc_prev[9] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[18] <= ((((((main_tx_crc_crc_prev[10] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[19] <= ((((main_tx_crc_crc_prev[11] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); + main_tx_crc_crc_next[20] <= ((main_tx_crc_crc_prev[12] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]); + main_tx_crc_crc_next[21] <= ((main_tx_crc_crc_prev[13] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]); + main_tx_crc_crc_next[22] <= ((main_tx_crc_crc_prev[14] ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[23] <= ((((((main_tx_crc_crc_prev[15] ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[24] <= ((((((main_tx_crc_crc_prev[16] ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[25] <= ((((main_tx_crc_crc_prev[17] ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[26] <= ((((((((main_tx_crc_crc_prev[18] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[27] <= ((((((((main_tx_crc_crc_prev[19] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[28] <= ((((((main_tx_crc_crc_prev[20] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[29] <= ((((((main_tx_crc_crc_prev[21] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); + main_tx_crc_crc_next[30] <= ((((main_tx_crc_crc_prev[22] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]); + main_tx_crc_crc_next[31] <= ((main_tx_crc_crc_prev[23] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]); +end +always @(*) begin + builder_txdatapath_bufferizeendpoints_next_state <= 2'd0; + main_tx_crc_ce <= 1'd0; + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= 32'd0; + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd0; + main_tx_crc_is_ongoing0 <= 1'd0; + main_tx_crc_is_ongoing1 <= 1'd0; + main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= 1'd0; + main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd0; + main_tx_crc_reset <= 1'd0; + main_tx_crc_sink_ready <= 1'd0; + main_tx_crc_source_first <= 1'd0; + main_tx_crc_source_last <= 1'd0; + main_tx_crc_source_payload_data <= 8'd0; + main_tx_crc_source_payload_error <= 1'd0; + main_tx_crc_source_payload_last_be <= 1'd0; + main_tx_crc_source_valid <= 1'd0; + builder_txdatapath_bufferizeendpoints_next_state <= builder_txdatapath_bufferizeendpoints_state; + case (builder_txdatapath_bufferizeendpoints_state) + 1'd1: begin + main_tx_crc_ce <= (main_tx_crc_sink_valid & main_tx_crc_source_ready); + main_tx_crc_source_valid <= main_tx_crc_sink_valid; + main_tx_crc_sink_ready <= main_tx_crc_source_ready; + main_tx_crc_source_first <= main_tx_crc_sink_first; + main_tx_crc_source_last <= main_tx_crc_sink_last; + main_tx_crc_source_payload_data <= main_tx_crc_sink_payload_data; + main_tx_crc_source_payload_last_be <= main_tx_crc_sink_payload_last_be; + main_tx_crc_source_payload_error <= main_tx_crc_sink_payload_error; + main_tx_crc_source_last <= 1'd0; + main_tx_crc_source_payload_last_be <= 1'd0; + if (main_tx_crc_sink_last) begin + if (main_tx_crc_sink_payload_last_be) begin + main_tx_crc_source_payload_data <= builder_complexslicelowerer_slice_proxy[7:0]; + end + if ((1'd0 & (main_tx_crc_sink_payload_last_be <= 4'd15))) begin + main_tx_crc_source_last <= 1'd1; + main_tx_crc_source_payload_last_be <= (main_tx_crc_sink_payload_last_be <<< -3'd3); + end + end else begin + main_tx_crc_ce <= (main_tx_crc_sink_valid & main_tx_crc_source_ready); + end + if (((main_tx_crc_sink_valid & main_tx_crc_sink_last) & main_tx_crc_source_ready)) begin + if ((1'd0 & (main_tx_crc_sink_payload_last_be <= 4'd15))) begin + builder_txdatapath_bufferizeendpoints_next_state <= 1'd0; + end else begin + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= main_tx_crc_value; + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd1; + if (1'd0) begin + main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= (main_tx_crc_sink_payload_last_be >>> 3'd4); + main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + end else begin + main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= main_tx_crc_sink_payload_last_be; + main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + end + builder_txdatapath_bufferizeendpoints_next_state <= 2'd2; + end + end + end + 2'd2: begin + main_tx_crc_source_valid <= 1'd1; + case (main_tx_crc_cnt) + 1'd0: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[31:24]; + end + 1'd1: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[23:16]; + end + 2'd2: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[15:8]; + end + default: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[7:0]; + end + endcase + if (main_tx_crc_cnt_done) begin + main_tx_crc_source_last <= 1'd1; + if (main_tx_crc_source_ready) begin + builder_txdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + main_tx_crc_is_ongoing1 <= 1'd1; + end + default: begin + main_tx_crc_reset <= 1'd1; + main_tx_crc_sink_ready <= 1'd1; + if (main_tx_crc_sink_valid) begin + main_tx_crc_sink_ready <= 1'd0; + builder_txdatapath_bufferizeendpoints_next_state <= 1'd1; + end + main_tx_crc_is_ongoing0 <= 1'd1; + end + endcase +end +assign main_tx_crc_pipe_valid_sink_ready = ((~main_tx_crc_pipe_valid_source_valid) | main_tx_crc_pipe_valid_source_ready); +assign main_tx_crc_pipe_valid_sink_valid = main_tx_crc_sink_sink_valid; +assign main_tx_crc_sink_sink_ready = main_tx_crc_pipe_valid_sink_ready; +assign main_tx_crc_pipe_valid_sink_first = main_tx_crc_sink_sink_first; +assign main_tx_crc_pipe_valid_sink_last = main_tx_crc_sink_sink_last; +assign main_tx_crc_pipe_valid_sink_payload_data = main_tx_crc_sink_sink_payload_data; +assign main_tx_crc_pipe_valid_sink_payload_last_be = main_tx_crc_sink_sink_payload_last_be; +assign main_tx_crc_pipe_valid_sink_payload_error = main_tx_crc_sink_sink_payload_error; +assign main_tx_crc_source_source_valid = main_tx_crc_pipe_valid_source_valid; +assign main_tx_crc_pipe_valid_source_ready = main_tx_crc_source_source_ready; +assign main_tx_crc_source_source_first = main_tx_crc_pipe_valid_source_first; +assign main_tx_crc_source_source_last = main_tx_crc_pipe_valid_source_last; +assign main_tx_crc_source_source_payload_data = main_tx_crc_pipe_valid_source_payload_data; +assign main_tx_crc_source_source_payload_last_be = main_tx_crc_pipe_valid_source_payload_last_be; +assign main_tx_crc_source_source_payload_error = main_tx_crc_pipe_valid_source_payload_error; +assign main_tx_preamble_source_payload_last_be = main_tx_preamble_sink_payload_last_be; +always @(*) begin + builder_txdatapath_liteethmacpreambleinserter_next_state <= 2'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value <= 3'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd0; + main_tx_preamble_sink_ready <= 1'd0; + main_tx_preamble_source_first <= 1'd0; + main_tx_preamble_source_last <= 1'd0; + main_tx_preamble_source_payload_data <= 8'd0; + main_tx_preamble_source_payload_error <= 1'd0; + main_tx_preamble_source_valid <= 1'd0; + main_tx_preamble_source_payload_data <= main_tx_preamble_sink_payload_data; + builder_txdatapath_liteethmacpreambleinserter_next_state <= builder_txdatapath_liteethmacpreambleinserter_state; + case (builder_txdatapath_liteethmacpreambleinserter_state) + 1'd1: begin + main_tx_preamble_source_valid <= 1'd1; + case (main_tx_preamble_count) + 1'd0: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[7:0]; + end + 1'd1: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[15:8]; + end + 2'd2: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[23:16]; + end + 2'd3: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[31:24]; + end + 3'd4: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[39:32]; + end + 3'd5: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[47:40]; + end + 3'd6: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[55:48]; + end + default: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[63:56]; + end + endcase + if (main_tx_preamble_source_ready) begin + if ((main_tx_preamble_count == 3'd7)) begin + builder_txdatapath_liteethmacpreambleinserter_next_state <= 2'd2; + end else begin + main_tx_preamble_count_clockdomainsrenamer2_next_value <= (main_tx_preamble_count + 1'd1); + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + end + end + end + 2'd2: begin + main_tx_preamble_source_valid <= main_tx_preamble_sink_valid; + main_tx_preamble_sink_ready <= main_tx_preamble_source_ready; + main_tx_preamble_source_first <= main_tx_preamble_sink_first; + main_tx_preamble_source_last <= main_tx_preamble_sink_last; + main_tx_preamble_source_payload_error <= main_tx_preamble_sink_payload_error; + if (((main_tx_preamble_sink_valid & main_tx_preamble_sink_last) & main_tx_preamble_source_ready)) begin + builder_txdatapath_liteethmacpreambleinserter_next_state <= 1'd0; + end + end + default: begin + main_tx_preamble_sink_ready <= 1'd1; + main_tx_preamble_count_clockdomainsrenamer2_next_value <= 1'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + if (main_tx_preamble_sink_valid) begin + main_tx_preamble_sink_ready <= 1'd0; + builder_txdatapath_liteethmacpreambleinserter_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + builder_txdatapath_liteethmacgap_next_state <= 1'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value <= 4'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd0; + main_tx_gap_sink_ready <= 1'd0; + main_tx_gap_source_first <= 1'd0; + main_tx_gap_source_last <= 1'd0; + main_tx_gap_source_payload_data <= 8'd0; + main_tx_gap_source_payload_error <= 1'd0; + main_tx_gap_source_payload_last_be <= 1'd0; + main_tx_gap_source_valid <= 1'd0; + builder_txdatapath_liteethmacgap_next_state <= builder_txdatapath_liteethmacgap_state; + case (builder_txdatapath_liteethmacgap_state) + 1'd1: begin + main_tx_gap_counter_clockdomainsrenamer3_next_value <= (main_tx_gap_counter + 1'd1); + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + if ((main_tx_gap_counter == 4'd11)) begin + builder_txdatapath_liteethmacgap_next_state <= 1'd0; + end + end + default: begin + main_tx_gap_counter_clockdomainsrenamer3_next_value <= 1'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + main_tx_gap_source_valid <= main_tx_gap_sink_valid; + main_tx_gap_sink_ready <= main_tx_gap_source_ready; + main_tx_gap_source_first <= main_tx_gap_sink_first; + main_tx_gap_source_last <= main_tx_gap_sink_last; + main_tx_gap_source_payload_data <= main_tx_gap_sink_payload_data; + main_tx_gap_source_payload_last_be <= main_tx_gap_sink_payload_last_be; + main_tx_gap_source_payload_error <= main_tx_gap_sink_payload_error; + if (((main_tx_gap_sink_valid & main_tx_gap_sink_last) & main_tx_gap_sink_ready)) begin + builder_txdatapath_liteethmacgap_next_state <= 1'd1; + end + end + endcase +end +assign main_tx_cdc_sink_sink_valid = main_sink_valid; +assign main_sink_ready = main_tx_cdc_sink_sink_ready; +assign main_tx_cdc_sink_sink_first = main_sink_first; +assign main_tx_cdc_sink_sink_last = main_sink_last; +assign main_tx_cdc_sink_sink_payload_data = main_sink_payload_data; +assign main_tx_cdc_sink_sink_payload_last_be = main_sink_payload_last_be; +assign main_tx_cdc_sink_sink_payload_error = main_sink_payload_error; +assign main_tx_converter_sink_valid = main_tx_cdc_source_source_valid; +assign main_tx_cdc_source_source_ready = main_tx_converter_sink_ready; +assign main_tx_converter_sink_first = main_tx_cdc_source_source_first; +assign main_tx_converter_sink_last = main_tx_cdc_source_source_last; +assign main_tx_converter_sink_payload_data = main_tx_cdc_source_source_payload_data; +assign main_tx_converter_sink_payload_last_be = main_tx_cdc_source_source_payload_last_be; +assign main_tx_converter_sink_payload_error = main_tx_cdc_source_source_payload_error; +assign main_tx_last_be_sink_valid = main_tx_converter_source_valid; +assign main_tx_converter_source_ready = main_tx_last_be_sink_ready; +assign main_tx_last_be_sink_first = main_tx_converter_source_first; +assign main_tx_last_be_sink_last = main_tx_converter_source_last; +assign main_tx_last_be_sink_payload_data = main_tx_converter_source_payload_data; +assign main_tx_last_be_sink_payload_last_be = main_tx_converter_source_payload_last_be; +assign main_tx_last_be_sink_payload_error = main_tx_converter_source_payload_error; +assign main_tx_padding_sink_valid = main_tx_last_be_source_valid; +assign main_tx_last_be_source_ready = main_tx_padding_sink_ready; +assign main_tx_padding_sink_first = main_tx_last_be_source_first; +assign main_tx_padding_sink_last = main_tx_last_be_source_last; +assign main_tx_padding_sink_payload_data = main_tx_last_be_source_payload_data; +assign main_tx_padding_sink_payload_last_be = main_tx_last_be_source_payload_last_be; +assign main_tx_padding_sink_payload_error = main_tx_last_be_source_payload_error; +assign main_tx_crc_sink_sink_valid = main_tx_padding_source_valid; +assign main_tx_padding_source_ready = main_tx_crc_sink_sink_ready; +assign main_tx_crc_sink_sink_first = main_tx_padding_source_first; +assign main_tx_crc_sink_sink_last = main_tx_padding_source_last; +assign main_tx_crc_sink_sink_payload_data = main_tx_padding_source_payload_data; +assign main_tx_crc_sink_sink_payload_last_be = main_tx_padding_source_payload_last_be; +assign main_tx_crc_sink_sink_payload_error = main_tx_padding_source_payload_error; +assign main_tx_preamble_sink_valid = main_tx_crc_source_valid; +assign main_tx_crc_source_ready = main_tx_preamble_sink_ready; +assign main_tx_preamble_sink_first = main_tx_crc_source_first; +assign main_tx_preamble_sink_last = main_tx_crc_source_last; +assign main_tx_preamble_sink_payload_data = main_tx_crc_source_payload_data; +assign main_tx_preamble_sink_payload_last_be = main_tx_crc_source_payload_last_be; +assign main_tx_preamble_sink_payload_error = main_tx_crc_source_payload_error; +assign main_tx_gap_sink_valid = main_tx_preamble_source_valid; +assign main_tx_preamble_source_ready = main_tx_gap_sink_ready; +assign main_tx_gap_sink_first = main_tx_preamble_source_first; +assign main_tx_gap_sink_last = main_tx_preamble_source_last; +assign main_tx_gap_sink_payload_data = main_tx_preamble_source_payload_data; +assign main_tx_gap_sink_payload_last_be = main_tx_preamble_source_payload_last_be; +assign main_tx_gap_sink_payload_error = main_tx_preamble_source_payload_error; +assign main_maccore_ethphy_sink_valid = main_tx_gap_source_valid; +assign main_tx_gap_source_ready = main_maccore_ethphy_sink_ready; +assign main_maccore_ethphy_sink_first = main_tx_gap_source_first; +assign main_maccore_ethphy_sink_last = main_tx_gap_source_last; +assign main_maccore_ethphy_sink_payload_data = main_tx_gap_source_payload_data; +assign main_maccore_ethphy_sink_payload_last_be = main_tx_gap_source_payload_last_be; +assign main_maccore_ethphy_sink_payload_error = main_tx_gap_source_payload_error; +assign main_pulsesynchronizer0_i = main_rx_preamble_error; +assign main_pulsesynchronizer1_i = main_liteethmaccrc32checker_error; +assign main_rx_preamble_source_payload_data = main_rx_preamble_sink_payload_data; +assign main_rx_preamble_source_payload_last_be = main_rx_preamble_sink_payload_last_be; +always @(*) begin + builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + main_rx_preamble_error <= 1'd0; + main_rx_preamble_sink_ready <= 1'd0; + main_rx_preamble_source_first <= 1'd0; + main_rx_preamble_source_last <= 1'd0; + main_rx_preamble_source_payload_error <= 1'd0; + main_rx_preamble_source_valid <= 1'd0; + builder_rxdatapath_liteethmacpreamblechecker_next_state <= builder_rxdatapath_liteethmacpreamblechecker_state; + case (builder_rxdatapath_liteethmacpreamblechecker_state) + 1'd1: begin + main_rx_preamble_source_valid <= main_rx_preamble_sink_valid; + main_rx_preamble_sink_ready <= main_rx_preamble_source_ready; + main_rx_preamble_source_first <= main_rx_preamble_sink_first; + main_rx_preamble_source_last <= main_rx_preamble_sink_last; + main_rx_preamble_source_payload_error <= main_rx_preamble_sink_payload_error; + if (((main_rx_preamble_source_valid & main_rx_preamble_source_last) & main_rx_preamble_source_ready)) begin + builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + end + end + default: begin + main_rx_preamble_sink_ready <= 1'd1; + if (((main_rx_preamble_sink_valid & (~main_rx_preamble_sink_last)) & (main_rx_preamble_sink_payload_data == main_rx_preamble_preamble[63:56]))) begin + builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd1; + end + if ((main_rx_preamble_sink_valid & main_rx_preamble_sink_last)) begin + main_rx_preamble_error <= 1'd1; + end + end + endcase +end +assign main_pulsesynchronizer0_o = (main_pulsesynchronizer0_toggle_o ^ main_pulsesynchronizer0_toggle_o_r); +assign main_liteethmaccrc32checker_fifo_full = (main_liteethmaccrc32checker_syncfifo_level == 3'd4); +assign main_liteethmaccrc32checker_fifo_in = (main_liteethmaccrc32checker_sink_sink_valid & ((~main_liteethmaccrc32checker_fifo_full) | main_liteethmaccrc32checker_fifo_out)); +assign main_liteethmaccrc32checker_fifo_out = (main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready); +assign main_liteethmaccrc32checker_syncfifo_sink_first = main_liteethmaccrc32checker_sink_sink_first; +assign main_liteethmaccrc32checker_syncfifo_sink_last = main_liteethmaccrc32checker_sink_sink_last; +assign main_liteethmaccrc32checker_syncfifo_sink_payload_data = main_liteethmaccrc32checker_sink_sink_payload_data; +assign main_liteethmaccrc32checker_syncfifo_sink_payload_last_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; +assign main_liteethmaccrc32checker_syncfifo_sink_payload_error = main_liteethmaccrc32checker_sink_sink_payload_error; +always @(*) begin + main_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; + main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_sink_sink_valid; + main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_fifo_in; +end +always @(*) begin + main_liteethmaccrc32checker_sink_sink_ready <= 1'd0; + main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_syncfifo_sink_ready; + main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_fifo_in; +end +assign main_liteethmaccrc32checker_crc_data0 = main_liteethmaccrc32checker_sink_sink_payload_data; +assign main_liteethmaccrc32checker_crc_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; +assign main_liteethmaccrc32checker_source_source_first = main_liteethmaccrc32checker_syncfifo_source_first; +assign main_liteethmaccrc32checker_source_source_payload_data = main_liteethmaccrc32checker_syncfifo_source_payload_data; +assign main_liteethmaccrc32checker_sink_sink_valid = main_bufferizeendpoints_source_source_valid; +assign main_bufferizeendpoints_source_source_ready = main_liteethmaccrc32checker_sink_sink_ready; +assign main_liteethmaccrc32checker_sink_sink_first = main_bufferizeendpoints_source_source_first; +assign main_liteethmaccrc32checker_sink_sink_last = main_bufferizeendpoints_source_source_last; +assign main_liteethmaccrc32checker_sink_sink_payload_data = main_bufferizeendpoints_source_source_payload_data; +assign main_liteethmaccrc32checker_sink_sink_payload_last_be = main_bufferizeendpoints_source_source_payload_last_be; +assign main_liteethmaccrc32checker_sink_sink_payload_error = main_bufferizeendpoints_source_source_payload_error; +assign main_liteethmaccrc32checker_crc_data1 = main_liteethmaccrc32checker_crc_data0[7:0]; +assign main_liteethmaccrc32checker_crc_crc_prev = main_liteethmaccrc32checker_crc_reg; +always @(*) begin + main_liteethmaccrc32checker_crc_error0 <= 1'd0; + main_liteethmaccrc32checker_crc_value <= 32'd0; + if (main_liteethmaccrc32checker_crc_be) begin + main_liteethmaccrc32checker_crc_value <= {builder_t_slice_proxy63[0], builder_t_slice_proxy62[1], builder_t_slice_proxy61[2], builder_t_slice_proxy60[3], builder_t_slice_proxy59[4], builder_t_slice_proxy58[5], builder_t_slice_proxy57[6], builder_t_slice_proxy56[7], builder_t_slice_proxy55[8], builder_t_slice_proxy54[9], builder_t_slice_proxy53[10], builder_t_slice_proxy52[11], builder_t_slice_proxy51[12], builder_t_slice_proxy50[13], builder_t_slice_proxy49[14], builder_t_slice_proxy48[15], builder_t_slice_proxy47[16], builder_t_slice_proxy46[17], builder_t_slice_proxy45[18], builder_t_slice_proxy44[19], builder_t_slice_proxy43[20], builder_t_slice_proxy42[21], builder_t_slice_proxy41[22], builder_t_slice_proxy40[23], builder_t_slice_proxy39[24], builder_t_slice_proxy38[25], builder_t_slice_proxy37[26], builder_t_slice_proxy36[27], builder_t_slice_proxy35[28], builder_t_slice_proxy34[29], builder_t_slice_proxy33[30], builder_t_slice_proxy32[31]}; + main_liteethmaccrc32checker_crc_error0 <= (main_liteethmaccrc32checker_crc_crc_next != 32'd3338984827); + end +end +always @(*) begin + main_liteethmaccrc32checker_crc_crc_next <= 32'd0; + main_liteethmaccrc32checker_crc_crc_next[0] <= (((main_liteethmaccrc32checker_crc_crc_prev[24] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[1] <= (((((((main_liteethmaccrc32checker_crc_crc_prev[25] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[2] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[26] ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[3] <= (((((((main_liteethmaccrc32checker_crc_crc_prev[27] ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[4] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[28] ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[5] <= (((((((((((((main_liteethmaccrc32checker_crc_crc_prev[29] ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[6] <= (((((((((((main_liteethmaccrc32checker_crc_crc_prev[30] ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[7] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[31] ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[8] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[0] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[9] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[1] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[10] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[2] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[11] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[3] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[12] <= ((((((((((((main_liteethmaccrc32checker_crc_crc_prev[4] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[13] <= ((((((((((((main_liteethmaccrc32checker_crc_crc_prev[5] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[14] <= ((((((((((main_liteethmaccrc32checker_crc_crc_prev[6] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[15] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[7] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); + main_liteethmaccrc32checker_crc_crc_next[16] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[8] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[17] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[9] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[18] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[10] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[19] <= ((((main_liteethmaccrc32checker_crc_crc_prev[11] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); + main_liteethmaccrc32checker_crc_crc_next[20] <= ((main_liteethmaccrc32checker_crc_crc_prev[12] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); + main_liteethmaccrc32checker_crc_crc_next[21] <= ((main_liteethmaccrc32checker_crc_crc_prev[13] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); + main_liteethmaccrc32checker_crc_crc_next[22] <= ((main_liteethmaccrc32checker_crc_crc_prev[14] ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[23] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[15] ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[24] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[16] ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[25] <= ((((main_liteethmaccrc32checker_crc_crc_prev[17] ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[26] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[18] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[27] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[19] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[28] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[20] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[29] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[21] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); + main_liteethmaccrc32checker_crc_crc_next[30] <= ((((main_liteethmaccrc32checker_crc_crc_prev[22] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); + main_liteethmaccrc32checker_crc_crc_next[31] <= ((main_liteethmaccrc32checker_crc_crc_prev[23] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); +end +assign main_liteethmaccrc32checker_syncfifo_syncfifo_din = {main_liteethmaccrc32checker_syncfifo_fifo_in_last, main_liteethmaccrc32checker_syncfifo_fifo_in_first, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data}; +assign {main_liteethmaccrc32checker_syncfifo_fifo_out_last, main_liteethmaccrc32checker_syncfifo_fifo_out_first, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = main_liteethmaccrc32checker_syncfifo_syncfifo_dout; +assign main_liteethmaccrc32checker_syncfifo_sink_ready = main_liteethmaccrc32checker_syncfifo_syncfifo_writable; +assign main_liteethmaccrc32checker_syncfifo_syncfifo_we = main_liteethmaccrc32checker_syncfifo_sink_valid; +assign main_liteethmaccrc32checker_syncfifo_fifo_in_first = main_liteethmaccrc32checker_syncfifo_sink_first; +assign main_liteethmaccrc32checker_syncfifo_fifo_in_last = main_liteethmaccrc32checker_syncfifo_sink_last; +assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data = main_liteethmaccrc32checker_syncfifo_sink_payload_data; +assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be = main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; +assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error = main_liteethmaccrc32checker_syncfifo_sink_payload_error; +assign main_liteethmaccrc32checker_syncfifo_source_valid = main_liteethmaccrc32checker_syncfifo_syncfifo_readable; +assign main_liteethmaccrc32checker_syncfifo_source_first = main_liteethmaccrc32checker_syncfifo_fifo_out_first; +assign main_liteethmaccrc32checker_syncfifo_source_last = main_liteethmaccrc32checker_syncfifo_fifo_out_last; +assign main_liteethmaccrc32checker_syncfifo_source_payload_data = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; +assign main_liteethmaccrc32checker_syncfifo_source_payload_last_be = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; +assign main_liteethmaccrc32checker_syncfifo_source_payload_error = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; +assign main_liteethmaccrc32checker_syncfifo_syncfifo_re = main_liteethmaccrc32checker_syncfifo_source_ready; +always @(*) begin + main_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; + if (main_liteethmaccrc32checker_syncfifo_replace) begin + main_liteethmaccrc32checker_syncfifo_wrport_adr <= (main_liteethmaccrc32checker_syncfifo_produce - 1'd1); + end else begin + main_liteethmaccrc32checker_syncfifo_wrport_adr <= main_liteethmaccrc32checker_syncfifo_produce; + end +end +assign main_liteethmaccrc32checker_syncfifo_wrport_dat_w = main_liteethmaccrc32checker_syncfifo_syncfifo_din; +assign main_liteethmaccrc32checker_syncfifo_wrport_we = (main_liteethmaccrc32checker_syncfifo_syncfifo_we & (main_liteethmaccrc32checker_syncfifo_syncfifo_writable | main_liteethmaccrc32checker_syncfifo_replace)); +assign main_liteethmaccrc32checker_syncfifo_do_read = (main_liteethmaccrc32checker_syncfifo_syncfifo_readable & main_liteethmaccrc32checker_syncfifo_syncfifo_re); +assign main_liteethmaccrc32checker_syncfifo_rdport_adr = main_liteethmaccrc32checker_syncfifo_consume; +assign main_liteethmaccrc32checker_syncfifo_syncfifo_dout = main_liteethmaccrc32checker_syncfifo_rdport_dat_r; +assign main_liteethmaccrc32checker_syncfifo_syncfifo_writable = (main_liteethmaccrc32checker_syncfifo_level != 3'd5); +assign main_liteethmaccrc32checker_syncfifo_syncfifo_readable = (main_liteethmaccrc32checker_syncfifo_level != 1'd0); +always @(*) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 2'd0; + main_liteethmaccrc32checker_crc_ce <= 1'd0; + main_liteethmaccrc32checker_crc_error1_next_value1 <= 1'd0; + main_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd0; + main_liteethmaccrc32checker_crc_reset <= 1'd0; + main_liteethmaccrc32checker_error <= 1'd0; + main_liteethmaccrc32checker_fifo_reset <= 1'd0; + main_liteethmaccrc32checker_last_be_next_value0 <= 1'd0; + main_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd0; + main_liteethmaccrc32checker_source_source_last <= 1'd0; + main_liteethmaccrc32checker_source_source_payload_error <= 1'd0; + main_liteethmaccrc32checker_source_source_payload_last_be <= 1'd0; + main_liteethmaccrc32checker_source_source_valid <= 1'd0; + main_liteethmaccrc32checker_syncfifo_source_ready <= 1'd0; + main_liteethmaccrc32checker_source_source_payload_error <= main_liteethmaccrc32checker_syncfifo_source_payload_error; + builder_rxdatapath_bufferizeendpoints_next_state <= builder_rxdatapath_bufferizeendpoints_state; + case (builder_rxdatapath_bufferizeendpoints_state) + 1'd1: begin + if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin + main_liteethmaccrc32checker_crc_ce <= 1'd1; + builder_rxdatapath_bufferizeendpoints_next_state <= 2'd2; + end + end + 2'd2: begin + main_liteethmaccrc32checker_syncfifo_source_ready <= main_liteethmaccrc32checker_fifo_out; + main_liteethmaccrc32checker_source_source_valid <= (main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_fifo_full); + if (1'd1) begin + main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_sink_sink_last; + main_liteethmaccrc32checker_source_source_payload_last_be <= main_liteethmaccrc32checker_sink_sink_payload_last_be; + end else begin + if ((main_liteethmaccrc32checker_sink_sink_payload_last_be & 4'd15)) begin + main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_sink_sink_last; + main_liteethmaccrc32checker_source_source_payload_last_be <= (main_liteethmaccrc32checker_sink_sink_payload_last_be <<< -3'd3); + end else begin + main_liteethmaccrc32checker_last_be_next_value0 <= (main_liteethmaccrc32checker_sink_sink_payload_last_be >>> 3'd4); + main_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd1; + main_liteethmaccrc32checker_crc_error1_next_value1 <= main_liteethmaccrc32checker_crc_error0; + main_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd1; + end + end + main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_sink_sink_payload_error | {1{(main_liteethmaccrc32checker_crc_error0 & main_liteethmaccrc32checker_sink_sink_last)}}); + main_liteethmaccrc32checker_error <= ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_last) & main_liteethmaccrc32checker_crc_error0); + if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin + main_liteethmaccrc32checker_crc_ce <= 1'd1; + if ((main_liteethmaccrc32checker_sink_sink_last & (main_liteethmaccrc32checker_sink_sink_payload_last_be > 4'd15))) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 2'd3; + end else begin + if (main_liteethmaccrc32checker_sink_sink_last) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + end + end + 2'd3: begin + main_liteethmaccrc32checker_source_source_valid <= main_liteethmaccrc32checker_syncfifo_source_valid; + main_liteethmaccrc32checker_syncfifo_source_ready <= main_liteethmaccrc32checker_source_source_ready; + main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_syncfifo_source_last; + main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_syncfifo_source_payload_error | {1{main_liteethmaccrc32checker_crc_error1}}); + main_liteethmaccrc32checker_source_source_payload_last_be <= main_liteethmaccrc32checker_last_be; + if ((main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready)) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + default: begin + main_liteethmaccrc32checker_crc_reset <= 1'd1; + main_liteethmaccrc32checker_fifo_reset <= 1'd1; + builder_rxdatapath_bufferizeendpoints_next_state <= 1'd1; + end + endcase +end +assign main_bufferizeendpoints_pipe_valid_sink_ready = ((~main_bufferizeendpoints_pipe_valid_source_valid) | main_bufferizeendpoints_pipe_valid_source_ready); +assign main_bufferizeendpoints_pipe_valid_sink_valid = main_bufferizeendpoints_sink_sink_valid; +assign main_bufferizeendpoints_sink_sink_ready = main_bufferizeendpoints_pipe_valid_sink_ready; +assign main_bufferizeendpoints_pipe_valid_sink_first = main_bufferizeendpoints_sink_sink_first; +assign main_bufferizeendpoints_pipe_valid_sink_last = main_bufferizeendpoints_sink_sink_last; +assign main_bufferizeendpoints_pipe_valid_sink_payload_data = main_bufferizeendpoints_sink_sink_payload_data; +assign main_bufferizeendpoints_pipe_valid_sink_payload_last_be = main_bufferizeendpoints_sink_sink_payload_last_be; +assign main_bufferizeendpoints_pipe_valid_sink_payload_error = main_bufferizeendpoints_sink_sink_payload_error; +assign main_bufferizeendpoints_source_source_valid = main_bufferizeendpoints_pipe_valid_source_valid; +assign main_bufferizeendpoints_pipe_valid_source_ready = main_bufferizeendpoints_source_source_ready; +assign main_bufferizeendpoints_source_source_first = main_bufferizeendpoints_pipe_valid_source_first; +assign main_bufferizeendpoints_source_source_last = main_bufferizeendpoints_pipe_valid_source_last; +assign main_bufferizeendpoints_source_source_payload_data = main_bufferizeendpoints_pipe_valid_source_payload_data; +assign main_bufferizeendpoints_source_source_payload_last_be = main_bufferizeendpoints_pipe_valid_source_payload_last_be; +assign main_bufferizeendpoints_source_source_payload_error = main_bufferizeendpoints_pipe_valid_source_payload_error; +assign main_pulsesynchronizer1_o = (main_pulsesynchronizer1_toggle_o ^ main_pulsesynchronizer1_toggle_o_r); +assign main_rx_padding_source_valid = main_rx_padding_sink_valid; +assign main_rx_padding_sink_ready = main_rx_padding_source_ready; +assign main_rx_padding_source_first = main_rx_padding_sink_first; +assign main_rx_padding_source_last = main_rx_padding_sink_last; +assign main_rx_padding_source_payload_data = main_rx_padding_sink_payload_data; +assign main_rx_padding_source_payload_last_be = main_rx_padding_sink_payload_last_be; +assign main_rx_padding_source_payload_error = main_rx_padding_sink_payload_error; +assign main_rx_last_be_source_valid = main_rx_last_be_sink_valid; +assign main_rx_last_be_sink_ready = main_rx_last_be_source_ready; +assign main_rx_last_be_source_first = main_rx_last_be_sink_first; +assign main_rx_last_be_source_last = main_rx_last_be_sink_last; +assign main_rx_last_be_source_payload_data = main_rx_last_be_sink_payload_data; +assign main_rx_last_be_source_payload_error = main_rx_last_be_sink_payload_error; +always @(*) begin + main_rx_last_be_source_payload_last_be <= 1'd0; + main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_payload_last_be; + if (1'd1) begin + main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_last; + end +end +assign main_rx_converter_converter_sink_valid = main_rx_converter_sink_valid; +assign main_rx_converter_converter_sink_first = main_rx_converter_sink_first; +assign main_rx_converter_converter_sink_last = main_rx_converter_sink_last; +assign main_rx_converter_sink_ready = main_rx_converter_converter_sink_ready; +assign main_rx_converter_converter_sink_payload_data = {main_rx_converter_sink_payload_error, main_rx_converter_sink_payload_last_be, main_rx_converter_sink_payload_data}; +assign main_rx_converter_source_valid = main_rx_converter_source_source_valid; +assign main_rx_converter_source_first = main_rx_converter_source_source_first; +assign main_rx_converter_source_last = main_rx_converter_source_source_last; +assign main_rx_converter_source_source_ready = main_rx_converter_source_ready; +always @(*) begin + main_rx_converter_source_payload_data <= 32'd0; + main_rx_converter_source_payload_data[7:0] <= main_rx_converter_source_source_payload_data[7:0]; + main_rx_converter_source_payload_data[15:8] <= main_rx_converter_source_source_payload_data[17:10]; + main_rx_converter_source_payload_data[23:16] <= main_rx_converter_source_source_payload_data[27:20]; + main_rx_converter_source_payload_data[31:24] <= main_rx_converter_source_source_payload_data[37:30]; +end +always @(*) begin + main_rx_converter_source_payload_last_be <= 4'd0; + main_rx_converter_source_payload_last_be[0] <= main_rx_converter_source_source_payload_data[8]; + main_rx_converter_source_payload_last_be[1] <= main_rx_converter_source_source_payload_data[18]; + main_rx_converter_source_payload_last_be[2] <= main_rx_converter_source_source_payload_data[28]; + main_rx_converter_source_payload_last_be[3] <= main_rx_converter_source_source_payload_data[38]; +end +always @(*) begin + main_rx_converter_source_payload_error <= 4'd0; + main_rx_converter_source_payload_error[0] <= main_rx_converter_source_source_payload_data[9]; + main_rx_converter_source_payload_error[1] <= main_rx_converter_source_source_payload_data[19]; + main_rx_converter_source_payload_error[2] <= main_rx_converter_source_source_payload_data[29]; + main_rx_converter_source_payload_error[3] <= main_rx_converter_source_source_payload_data[39]; +end +assign main_rx_converter_source_source_valid = main_rx_converter_converter_source_valid; +assign main_rx_converter_converter_source_ready = main_rx_converter_source_source_ready; +assign main_rx_converter_source_source_first = main_rx_converter_converter_source_first; +assign main_rx_converter_source_source_last = main_rx_converter_converter_source_last; +assign main_rx_converter_source_source_payload_data = main_rx_converter_converter_source_payload_data; +assign main_rx_converter_converter_sink_ready = ((~main_rx_converter_converter_strobe_all) | main_rx_converter_converter_source_ready); +assign main_rx_converter_converter_source_valid = main_rx_converter_converter_strobe_all; +assign main_rx_converter_converter_load_part = (main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready); +assign main_rx_cdc_cdc_sink_valid = main_rx_cdc_sink_sink_valid; +assign main_rx_cdc_sink_sink_ready = main_rx_cdc_cdc_sink_ready; +assign main_rx_cdc_cdc_sink_first = main_rx_cdc_sink_sink_first; +assign main_rx_cdc_cdc_sink_last = main_rx_cdc_sink_sink_last; +assign main_rx_cdc_cdc_sink_payload_data = main_rx_cdc_sink_sink_payload_data; +assign main_rx_cdc_cdc_sink_payload_last_be = main_rx_cdc_sink_sink_payload_last_be; +assign main_rx_cdc_cdc_sink_payload_error = main_rx_cdc_sink_sink_payload_error; +assign main_rx_cdc_source_source_valid = main_rx_cdc_cdc_source_valid; +assign main_rx_cdc_cdc_source_ready = main_rx_cdc_source_source_ready; +assign main_rx_cdc_source_source_first = main_rx_cdc_cdc_source_first; +assign main_rx_cdc_source_source_last = main_rx_cdc_cdc_source_last; +assign main_rx_cdc_source_source_payload_data = main_rx_cdc_cdc_source_payload_data; +assign main_rx_cdc_source_source_payload_last_be = main_rx_cdc_cdc_source_payload_last_be; +assign main_rx_cdc_source_source_payload_error = main_rx_cdc_cdc_source_payload_error; +assign main_rx_cdc_cdc_asyncfifo_din = {main_rx_cdc_cdc_fifo_in_last, main_rx_cdc_cdc_fifo_in_first, main_rx_cdc_cdc_fifo_in_payload_error, main_rx_cdc_cdc_fifo_in_payload_last_be, main_rx_cdc_cdc_fifo_in_payload_data}; +assign {main_rx_cdc_cdc_fifo_out_last, main_rx_cdc_cdc_fifo_out_first, main_rx_cdc_cdc_fifo_out_payload_error, main_rx_cdc_cdc_fifo_out_payload_last_be, main_rx_cdc_cdc_fifo_out_payload_data} = main_rx_cdc_cdc_asyncfifo_dout; +assign main_rx_cdc_cdc_sink_ready = main_rx_cdc_cdc_asyncfifo_writable; +assign main_rx_cdc_cdc_asyncfifo_we = main_rx_cdc_cdc_sink_valid; +assign main_rx_cdc_cdc_fifo_in_first = main_rx_cdc_cdc_sink_first; +assign main_rx_cdc_cdc_fifo_in_last = main_rx_cdc_cdc_sink_last; +assign main_rx_cdc_cdc_fifo_in_payload_data = main_rx_cdc_cdc_sink_payload_data; +assign main_rx_cdc_cdc_fifo_in_payload_last_be = main_rx_cdc_cdc_sink_payload_last_be; +assign main_rx_cdc_cdc_fifo_in_payload_error = main_rx_cdc_cdc_sink_payload_error; +assign main_rx_cdc_cdc_source_valid = main_rx_cdc_cdc_asyncfifo_readable; +assign main_rx_cdc_cdc_source_first = main_rx_cdc_cdc_fifo_out_first; +assign main_rx_cdc_cdc_source_last = main_rx_cdc_cdc_fifo_out_last; +assign main_rx_cdc_cdc_source_payload_data = main_rx_cdc_cdc_fifo_out_payload_data; +assign main_rx_cdc_cdc_source_payload_last_be = main_rx_cdc_cdc_fifo_out_payload_last_be; +assign main_rx_cdc_cdc_source_payload_error = main_rx_cdc_cdc_fifo_out_payload_error; +assign main_rx_cdc_cdc_asyncfifo_re = main_rx_cdc_cdc_source_ready; +assign main_rx_cdc_cdc_graycounter0_ce = (main_rx_cdc_cdc_asyncfifo_writable & main_rx_cdc_cdc_asyncfifo_we); +assign main_rx_cdc_cdc_graycounter1_ce = (main_rx_cdc_cdc_asyncfifo_readable & main_rx_cdc_cdc_asyncfifo_re); +assign main_rx_cdc_cdc_asyncfifo_writable = (((main_rx_cdc_cdc_graycounter0_q[5] == main_rx_cdc_cdc_consume_wdomain[5]) | (main_rx_cdc_cdc_graycounter0_q[4] == main_rx_cdc_cdc_consume_wdomain[4])) | (main_rx_cdc_cdc_graycounter0_q[3:0] != main_rx_cdc_cdc_consume_wdomain[3:0])); +assign main_rx_cdc_cdc_asyncfifo_readable = (main_rx_cdc_cdc_graycounter1_q != main_rx_cdc_cdc_produce_rdomain); +assign main_rx_cdc_cdc_wrport_adr = main_rx_cdc_cdc_graycounter0_q_binary[4:0]; +assign main_rx_cdc_cdc_wrport_dat_w = main_rx_cdc_cdc_asyncfifo_din; +assign main_rx_cdc_cdc_wrport_we = main_rx_cdc_cdc_graycounter0_ce; +assign main_rx_cdc_cdc_rdport_adr = main_rx_cdc_cdc_graycounter1_q_next_binary[4:0]; +assign main_rx_cdc_cdc_asyncfifo_dout = main_rx_cdc_cdc_rdport_dat_r; +always @(*) begin + main_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (main_rx_cdc_cdc_graycounter0_ce) begin + main_rx_cdc_cdc_graycounter0_q_next_binary <= (main_rx_cdc_cdc_graycounter0_q_binary + 1'd1); + end else begin + main_rx_cdc_cdc_graycounter0_q_next_binary <= main_rx_cdc_cdc_graycounter0_q_binary; + end +end +assign main_rx_cdc_cdc_graycounter0_q_next = (main_rx_cdc_cdc_graycounter0_q_next_binary ^ main_rx_cdc_cdc_graycounter0_q_next_binary[5:1]); +always @(*) begin + main_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (main_rx_cdc_cdc_graycounter1_ce) begin + main_rx_cdc_cdc_graycounter1_q_next_binary <= (main_rx_cdc_cdc_graycounter1_q_binary + 1'd1); + end else begin + main_rx_cdc_cdc_graycounter1_q_next_binary <= main_rx_cdc_cdc_graycounter1_q_binary; + end +end +assign main_rx_cdc_cdc_graycounter1_q_next = (main_rx_cdc_cdc_graycounter1_q_next_binary ^ main_rx_cdc_cdc_graycounter1_q_next_binary[5:1]); +assign main_rx_preamble_sink_valid = main_maccore_ethphy_source_valid; +assign main_maccore_ethphy_source_ready = main_rx_preamble_sink_ready; +assign main_rx_preamble_sink_first = main_maccore_ethphy_source_first; +assign main_rx_preamble_sink_last = main_maccore_ethphy_source_last; +assign main_rx_preamble_sink_payload_data = main_maccore_ethphy_source_payload_data; +assign main_rx_preamble_sink_payload_last_be = main_maccore_ethphy_source_payload_last_be; +assign main_rx_preamble_sink_payload_error = main_maccore_ethphy_source_payload_error; +assign main_bufferizeendpoints_sink_sink_valid = main_rx_preamble_source_valid; +assign main_rx_preamble_source_ready = main_bufferizeendpoints_sink_sink_ready; +assign main_bufferizeendpoints_sink_sink_first = main_rx_preamble_source_first; +assign main_bufferizeendpoints_sink_sink_last = main_rx_preamble_source_last; +assign main_bufferizeendpoints_sink_sink_payload_data = main_rx_preamble_source_payload_data; +assign main_bufferizeendpoints_sink_sink_payload_last_be = main_rx_preamble_source_payload_last_be; +assign main_bufferizeendpoints_sink_sink_payload_error = main_rx_preamble_source_payload_error; +assign main_rx_padding_sink_valid = main_liteethmaccrc32checker_source_source_valid; +assign main_liteethmaccrc32checker_source_source_ready = main_rx_padding_sink_ready; +assign main_rx_padding_sink_first = main_liteethmaccrc32checker_source_source_first; +assign main_rx_padding_sink_last = main_liteethmaccrc32checker_source_source_last; +assign main_rx_padding_sink_payload_data = main_liteethmaccrc32checker_source_source_payload_data; +assign main_rx_padding_sink_payload_last_be = main_liteethmaccrc32checker_source_source_payload_last_be; +assign main_rx_padding_sink_payload_error = main_liteethmaccrc32checker_source_source_payload_error; +assign main_rx_last_be_sink_valid = main_rx_padding_source_valid; +assign main_rx_padding_source_ready = main_rx_last_be_sink_ready; +assign main_rx_last_be_sink_first = main_rx_padding_source_first; +assign main_rx_last_be_sink_last = main_rx_padding_source_last; +assign main_rx_last_be_sink_payload_data = main_rx_padding_source_payload_data; +assign main_rx_last_be_sink_payload_last_be = main_rx_padding_source_payload_last_be; +assign main_rx_last_be_sink_payload_error = main_rx_padding_source_payload_error; +assign main_rx_converter_sink_valid = main_rx_last_be_source_valid; +assign main_rx_last_be_source_ready = main_rx_converter_sink_ready; +assign main_rx_converter_sink_first = main_rx_last_be_source_first; +assign main_rx_converter_sink_last = main_rx_last_be_source_last; +assign main_rx_converter_sink_payload_data = main_rx_last_be_source_payload_data; +assign main_rx_converter_sink_payload_last_be = main_rx_last_be_source_payload_last_be; +assign main_rx_converter_sink_payload_error = main_rx_last_be_source_payload_error; +assign main_rx_cdc_sink_sink_valid = main_rx_converter_source_valid; +assign main_rx_converter_source_ready = main_rx_cdc_sink_sink_ready; +assign main_rx_cdc_sink_sink_first = main_rx_converter_source_first; +assign main_rx_cdc_sink_sink_last = main_rx_converter_source_last; +assign main_rx_cdc_sink_sink_payload_data = main_rx_converter_source_payload_data; +assign main_rx_cdc_sink_sink_payload_last_be = main_rx_converter_source_payload_last_be; +assign main_rx_cdc_sink_sink_payload_error = main_rx_converter_source_payload_error; +assign main_source_valid = main_rx_cdc_source_source_valid; +assign main_rx_cdc_source_source_ready = main_source_ready; +assign main_source_first = main_rx_cdc_source_source_first; +assign main_source_last = main_rx_cdc_source_source_last; +assign main_source_payload_data = main_rx_cdc_source_source_payload_data; +assign main_source_payload_last_be = main_rx_cdc_source_source_payload_last_be; +assign main_source_payload_error = main_rx_cdc_source_source_payload_error; +assign main_sram0_sink_valid = main_sink_sink_valid; +assign main_sink_sink_ready = main_sram1_sink_ready; +assign main_sram2_sink_first = main_sink_sink_first; +assign main_sram3_sink_last = main_sink_sink_last; +assign main_sram4_sink_payload_data = main_sink_sink_payload_data; +assign main_sram5_sink_payload_last_be = main_sink_sink_payload_last_be; +assign main_sram6_sink_payload_error = main_sink_sink_payload_error; +assign main_source_source_valid = main_sram83_source_valid; +assign main_sram84_source_ready = main_source_source_ready; +assign main_source_source_first = main_sram85_source_first; +assign main_source_source_last = main_sram86_source_last; +assign main_source_source_payload_data = main_sram87_source_payload_data; +assign main_source_source_payload_last_be = main_sram88_source_payload_last_be; +assign main_source_source_payload_error = main_sram89_source_payload_error; +always @(*) begin + main_length_inc <= 4'd0; + case (main_sram5_sink_payload_last_be) + 1'd1: begin + main_length_inc <= 1'd1; + end + 2'd2: begin + main_length_inc <= 2'd2; + end + 3'd4: begin + main_length_inc <= 2'd3; + end + 4'd8: begin + main_length_inc <= 3'd4; + end + 5'd16: begin + main_length_inc <= 3'd5; + end + 6'd32: begin + main_length_inc <= 3'd6; + end + 7'd64: begin + main_length_inc <= 3'd7; + end + default: begin + main_length_inc <= 3'd4; + end + endcase +end +assign main_sram44_source_ready = main_sram20_clear; +assign main_sram19_trigger = main_sram43_source_valid; +assign main_sram7_status = main_sram47_source_payload_slot; +assign main_sram10_status = main_sram48_source_payload_length; +assign main_wr_data = main_sram4_sink_payload_data; +always @(*) begin + main_sram75_adr <= 9'd0; + main_sram77_we <= 1'd0; + main_sram78_dat_w <= 32'd0; + main_sram79_adr <= 9'd0; + main_sram81_we <= 1'd0; + main_sram82_dat_w <= 32'd0; + case (main_slot) + 1'd0: begin + main_sram75_adr <= main_sram35_length[10:2]; + main_sram78_dat_w <= main_wr_data; + if ((main_sram0_sink_valid & main_write)) begin + main_sram77_we <= 1'd1; + end + end + 1'd1: begin + main_sram79_adr <= main_sram35_length[10:2]; + main_sram82_dat_w <= main_wr_data; + if ((main_sram0_sink_valid & main_write)) begin + main_sram81_we <= 1'd1; + end + end + endcase +end +assign main_sram21_available = main_sram17_status; +assign main_sram25_available = main_sram18_pending; +always @(*) begin + main_sram20_clear <= 1'd0; + if ((main_sram28_re & main_sram29_r)) begin + main_sram20_clear <= 1'd1; + end +end +assign main_sram16_irq = (main_sram26_status & main_sram31_storage); +assign main_sram17_status = main_sram19_trigger; +assign main_sram18_pending = main_sram19_trigger; +assign main_sram53_din = {main_sram69_fifo_in_last, main_sram68_fifo_in_first, main_sram67_fifo_in_payload_length, main_sram66_fifo_in_payload_slot}; +assign {main_sram73_fifo_out_last, main_sram72_fifo_out_first, main_sram71_fifo_out_payload_length, main_sram70_fifo_out_payload_slot} = main_sram54_dout; +assign main_sram38_sink_ready = main_sram50_writable; +assign main_sram49_we = main_sram37_sink_valid; +assign main_sram68_fifo_in_first = main_sram39_sink_first; +assign main_sram69_fifo_in_last = main_sram40_sink_last; +assign main_sram66_fifo_in_payload_slot = main_sram41_sink_payload_slot; +assign main_sram67_fifo_in_payload_length = main_sram42_sink_payload_length; +assign main_sram43_source_valid = main_sram52_readable; +assign main_sram45_source_first = main_sram72_fifo_out_first; +assign main_sram46_source_last = main_sram73_fifo_out_last; +assign main_sram47_source_payload_slot = main_sram70_fifo_out_payload_slot; +assign main_sram48_source_payload_length = main_sram71_fifo_out_payload_length; +assign main_sram51_re = main_sram44_source_ready; +always @(*) begin + main_sram59_adr <= 1'd0; + if (main_sram56_replace) begin + main_sram59_adr <= (main_sram57_produce - 1'd1); + end else begin + main_sram59_adr <= main_sram57_produce; + end +end +assign main_sram62_dat_w = main_sram53_din; +assign main_sram61_we = (main_sram49_we & (main_sram50_writable | main_sram56_replace)); +assign main_sram63_do_read = (main_sram52_readable & main_sram51_re); +assign main_sram64_adr = main_sram58_consume; +assign main_sram54_dout = main_sram65_dat_r; +assign main_sram50_writable = (main_sram55_level != 2'd2); +assign main_sram52_readable = (main_sram55_level != 1'd0); +always @(*) begin + builder_liteethmacsramwriter_next_state <= 3'd0; + main_slot_liteethmacsramwriter_next_value <= 1'd0; + main_slot_liteethmacsramwriter_next_value_ce <= 1'd0; + main_sram13_status_liteethmacsramwriter_f_next_value <= 32'd0; + main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value <= 11'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd0; + main_sram37_sink_valid <= 1'd0; + main_sram41_sink_payload_slot <= 1'd0; + main_sram42_sink_payload_length <= 11'd0; + main_write <= 1'd0; + builder_liteethmacsramwriter_next_state <= builder_liteethmacsramwriter_state; + case (builder_liteethmacsramwriter_state) + 1'd1: begin + if ((main_sram0_sink_valid & main_sram3_sink_last)) begin + if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + builder_liteethmacsramwriter_next_state <= 3'd4; + end + end + end + 2'd2: begin + if ((main_sram0_sink_valid & main_sram3_sink_last)) begin + if ((main_sram5_sink_payload_last_be != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + end + end + 2'd3: begin + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + 3'd4: begin + main_sram37_sink_valid <= 1'd1; + main_sram41_sink_payload_slot <= main_slot; + main_sram42_sink_payload_length <= main_sram35_length; + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + main_slot_liteethmacsramwriter_next_value <= (main_slot + 1'd1); + main_slot_liteethmacsramwriter_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + default: begin + if (main_sram0_sink_valid) begin + if (main_sram38_sink_ready) begin + main_write <= 1'd1; + main_sram35_length_liteethmacsramwriter_t_next_value <= (main_sram35_length + main_length_inc); + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + if ((main_sram35_length >= 11'd1530)) begin + builder_liteethmacsramwriter_next_state <= 1'd1; + end + if (main_sram3_sink_last) begin + if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + builder_liteethmacsramwriter_next_state <= 3'd4; + end + end + end else begin + main_sram13_status_liteethmacsramwriter_f_next_value <= (main_sram13_status + 1'd1); + main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 2'd2; + end + end + end + endcase +end +assign main_sram123_sink_valid = main_start_re; +assign main_sram127_sink_payload_slot = main_sram100_storage; +assign main_sram128_sink_payload_length = main_sram102_storage; +assign main_sram94_status = main_sram124_sink_ready; +assign main_sram97_status = main_sram141_level; +always @(*) begin + main_sram88_source_payload_last_be <= 4'd0; + if (main_sram86_source_last) begin + case (main_sram134_source_payload_length[1:0]) + 1'd1: begin + main_sram88_source_payload_last_be <= 1'd1; + end + 2'd2: begin + main_sram88_source_payload_last_be <= 2'd2; + end + 2'd3: begin + main_sram88_source_payload_last_be <= 3'd4; + end + 3'd4: begin + main_sram88_source_payload_last_be <= 4'd8; + end + 3'd5: begin + main_sram88_source_payload_last_be <= 5'd16; + end + 3'd6: begin + main_sram88_source_payload_last_be <= 6'd32; + end + 3'd7: begin + main_sram88_source_payload_last_be <= 7'd64; + end + default: begin + main_sram88_source_payload_last_be <= 4'd8; + end + endcase + end +end +assign main_sram163_re = main_read; +assign main_sram161_adr = main_sram122_length[10:2]; +assign main_sram166_re = main_read; +assign main_sram164_adr = main_sram122_length[10:2]; +always @(*) begin + main_rd_data <= 32'd0; + case (main_sram133_source_payload_slot) + 1'd0: begin + main_rd_data <= main_sram162_dat_r; + end + 1'd1: begin + main_rd_data <= main_sram165_dat_r; + end + endcase +end +assign main_sram87_source_payload_data = main_rd_data; +assign main_sram109_event0 = main_sram105_status; +assign main_sram113_event0 = main_sram106_pending; +always @(*) begin + main_sram108_clear <= 1'd0; + if ((main_sram116_re & main_sram117_r)) begin + main_sram108_clear <= 1'd1; + end +end +assign main_sram104_irq = (main_sram114_status & main_sram119_storage); +assign main_sram105_status = 1'd0; +assign main_sram139_din = {main_sram155_fifo_in_last, main_sram154_fifo_in_first, main_sram153_fifo_in_payload_length, main_sram152_fifo_in_payload_slot}; +assign {main_sram159_fifo_out_last, main_sram158_fifo_out_first, main_sram157_fifo_out_payload_length, main_sram156_fifo_out_payload_slot} = main_sram140_dout; +assign main_sram124_sink_ready = main_sram136_writable; +assign main_sram135_we = main_sram123_sink_valid; +assign main_sram154_fifo_in_first = main_sram125_sink_first; +assign main_sram155_fifo_in_last = main_sram126_sink_last; +assign main_sram152_fifo_in_payload_slot = main_sram127_sink_payload_slot; +assign main_sram153_fifo_in_payload_length = main_sram128_sink_payload_length; +assign main_sram129_source_valid = main_sram138_readable; +assign main_sram131_source_first = main_sram158_fifo_out_first; +assign main_sram132_source_last = main_sram159_fifo_out_last; +assign main_sram133_source_payload_slot = main_sram156_fifo_out_payload_slot; +assign main_sram134_source_payload_length = main_sram157_fifo_out_payload_length; +assign main_sram137_re = main_sram130_source_ready; +always @(*) begin + main_sram145_adr <= 1'd0; + if (main_sram142_replace) begin + main_sram145_adr <= (main_sram143_produce - 1'd1); + end else begin + main_sram145_adr <= main_sram143_produce; + end +end +assign main_sram148_dat_w = main_sram139_din; +assign main_sram147_we = (main_sram135_we & (main_sram136_writable | main_sram142_replace)); +assign main_sram149_do_read = (main_sram138_readable & main_sram137_re); +assign main_sram150_adr = main_sram144_consume; +assign main_sram140_dout = main_sram151_dat_r; +assign main_sram136_writable = (main_sram141_level != 2'd2); +assign main_sram138_readable = (main_sram141_level != 1'd0); +always @(*) begin + builder_liteethmacsramreader_next_state <= 2'd0; + main_read <= 1'd0; + main_sram107_trigger <= 1'd0; + main_sram122_length_liteethmacsramreader_next_value <= 11'd0; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd0; + main_sram130_source_ready <= 1'd0; + main_sram83_source_valid <= 1'd0; + main_sram86_source_last <= 1'd0; + builder_liteethmacsramreader_next_state <= builder_liteethmacsramreader_state; + case (builder_liteethmacsramreader_state) + 1'd1: begin + main_sram83_source_valid <= 1'd1; + main_sram86_source_last <= (main_sram122_length >= main_sram134_source_payload_length); + if (main_sram84_source_ready) begin + main_read <= 1'd1; + main_sram122_length_liteethmacsramreader_next_value <= (main_sram122_length + 3'd4); + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + if (main_sram86_source_last) begin + builder_liteethmacsramreader_next_state <= 2'd2; + end + end + end + 2'd2: begin + main_sram122_length_liteethmacsramreader_next_value <= 1'd0; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + main_sram107_trigger <= 1'd1; + main_sram130_source_ready <= 1'd1; + builder_liteethmacsramreader_next_state <= 1'd0; + end + default: begin + if (main_sram129_source_valid) begin + main_read <= 1'd1; + main_sram122_length_liteethmacsramreader_next_value <= 3'd4; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + builder_liteethmacsramreader_next_state <= 1'd1; + end + end + endcase +end +assign main_sram167_irq = (main_sram16_irq | main_sram104_irq); +assign main_sram0_adr = main_interface0_adr[8:0]; +assign main_interface0_dat_r = main_sram0_dat_r; +assign main_sram1_adr = main_interface1_adr[8:0]; +assign main_interface1_dat_r = main_sram1_dat_r; +always @(*) begin + main_sram2_we <= 4'd0; + main_sram2_we[0] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[0]); + main_sram2_we[1] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[1]); + main_sram2_we[2] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[2]); + main_sram2_we[3] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[3]); +end +assign main_sram2_adr = main_interface2_adr[8:0]; +assign main_interface2_dat_r = main_sram2_dat_r; +assign main_sram2_dat_w = main_interface2_dat_w; +always @(*) begin + main_sram3_we <= 4'd0; + main_sram3_we[0] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[0]); + main_sram3_we[1] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[1]); + main_sram3_we[2] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[2]); + main_sram3_we[3] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[3]); +end +assign main_sram3_adr = main_interface3_adr[8:0]; +assign main_interface3_dat_r = main_sram3_dat_r; +assign main_sram3_dat_w = main_interface3_dat_w; +always @(*) begin + main_slave_sel <= 4'd0; + main_slave_sel[0] <= (main_bus_adr[10:9] == 1'd0); + main_slave_sel[1] <= (main_bus_adr[10:9] == 1'd1); + main_slave_sel[2] <= (main_bus_adr[10:9] == 2'd2); + main_slave_sel[3] <= (main_bus_adr[10:9] == 2'd3); +end +assign main_interface0_adr = main_bus_adr; +assign main_interface0_dat_w = main_bus_dat_w; +assign main_interface0_sel = main_bus_sel; +assign main_interface0_stb = main_bus_stb; +assign main_interface0_we = main_bus_we; +assign main_interface0_cti = main_bus_cti; +assign main_interface0_bte = main_bus_bte; +assign main_interface1_adr = main_bus_adr; +assign main_interface1_dat_w = main_bus_dat_w; +assign main_interface1_sel = main_bus_sel; +assign main_interface1_stb = main_bus_stb; +assign main_interface1_we = main_bus_we; +assign main_interface1_cti = main_bus_cti; +assign main_interface1_bte = main_bus_bte; +assign main_interface2_adr = main_bus_adr; +assign main_interface2_dat_w = main_bus_dat_w; +assign main_interface2_sel = main_bus_sel; +assign main_interface2_stb = main_bus_stb; +assign main_interface2_we = main_bus_we; +assign main_interface2_cti = main_bus_cti; +assign main_interface2_bte = main_bus_bte; +assign main_interface3_adr = main_bus_adr; +assign main_interface3_dat_w = main_bus_dat_w; +assign main_interface3_sel = main_bus_sel; +assign main_interface3_stb = main_bus_stb; +assign main_interface3_we = main_bus_we; +assign main_interface3_cti = main_bus_cti; +assign main_interface3_bte = main_bus_bte; +assign main_interface0_cyc = (main_bus_cyc & main_slave_sel[0]); +assign main_interface1_cyc = (main_bus_cyc & main_slave_sel[1]); +assign main_interface2_cyc = (main_bus_cyc & main_slave_sel[2]); +assign main_interface3_cyc = (main_bus_cyc & main_slave_sel[3]); +assign main_bus_ack = (((main_interface0_ack | main_interface1_ack) | main_interface2_ack) | main_interface3_ack); +assign main_bus_err = (((main_interface0_err | main_interface1_err) | main_interface2_err) | main_interface3_err); +assign main_bus_dat_r = (((({32{main_slave_sel_r[0]}} & main_interface0_dat_r) | ({32{main_slave_sel_r[1]}} & main_interface1_dat_r)) | ({32{main_slave_sel_r[2]}} & main_interface2_dat_r)) | ({32{main_slave_sel_r[3]}} & main_interface3_dat_r)); +always @(*) begin + builder_interface0_ack <= 1'd0; + builder_interface0_dat_r <= 32'd0; + builder_interface1_adr <= 14'd0; + builder_interface1_dat_w <= 32'd0; + builder_interface1_we <= 1'd0; + builder_next_state <= 1'd0; + builder_next_state <= builder_state; + case (builder_state) + 1'd1: begin + builder_interface0_ack <= 1'd1; + builder_interface0_dat_r <= builder_interface1_dat_r; + builder_next_state <= 1'd0; + end + default: begin + builder_interface1_dat_w <= builder_interface0_dat_w; + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_adr <= builder_interface0_adr[29:0]; + builder_interface1_we <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); + builder_next_state <= 1'd1; + end + end + endcase +end +assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); +assign builder_csrbank0_reset0_r = builder_interface0_bank_bus_dat_w[1:0]; +always @(*) begin + builder_csrbank0_reset0_re <= 1'd0; + builder_csrbank0_reset0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_reset0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_reset0_we <= (~builder_interface0_bank_bus_we); + end +end +assign builder_csrbank0_scratch0_r = builder_interface0_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank0_scratch0_re <= 1'd0; + builder_csrbank0_scratch0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_scratch0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_scratch0_we <= (~builder_interface0_bank_bus_we); + end +end +assign builder_csrbank0_bus_errors_r = builder_interface0_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank0_bus_errors_re <= 1'd0; + builder_csrbank0_bus_errors_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank0_bus_errors_re <= builder_interface0_bank_bus_we; + builder_csrbank0_bus_errors_we <= (~builder_interface0_bank_bus_we); + end +end +always @(*) begin + main_maccore_maccore_soc_rst <= 1'd0; + if (main_maccore_maccore_reset_re) begin + main_maccore_maccore_soc_rst <= main_maccore_maccore_reset_storage[0]; + end +end +assign main_maccore_maccore_cpu_rst = main_maccore_maccore_reset_storage[1]; +assign builder_csrbank0_reset0_w = main_maccore_maccore_reset_storage[1:0]; +assign builder_csrbank0_scratch0_w = main_maccore_maccore_scratch_storage[31:0]; +assign builder_csrbank0_bus_errors_w = main_maccore_maccore_bus_errors_status[31:0]; +assign main_maccore_maccore_bus_errors_we = builder_csrbank0_bus_errors_we; +assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2); +assign builder_csrbank1_sram_writer_slot_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_writer_slot_re <= 1'd0; + builder_csrbank1_sram_writer_slot_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_sram_writer_slot_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_slot_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_length_r = builder_interface1_bank_bus_dat_w[10:0]; +always @(*) begin + builder_csrbank1_sram_writer_length_re <= 1'd0; + builder_csrbank1_sram_writer_length_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_sram_writer_length_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_length_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank1_sram_writer_errors_re <= 1'd0; + builder_csrbank1_sram_writer_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_sram_writer_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_errors_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_ev_status_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_writer_ev_status_re <= 1'd0; + builder_csrbank1_sram_writer_ev_status_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank1_sram_writer_ev_status_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_status_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_writer_ev_pending_re <= 1'd0; + builder_csrbank1_sram_writer_ev_pending_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank1_sram_writer_ev_pending_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_pending_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_writer_ev_enable0_re <= 1'd0; + builder_csrbank1_sram_writer_ev_enable0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank1_sram_writer_ev_enable0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_enable0_we <= (~builder_interface1_bank_bus_we); + end +end +assign main_start_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + main_start_re <= 1'd0; + main_start_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_start_re <= builder_interface1_bank_bus_we; + main_start_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_ready_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_ready_re <= 1'd0; + builder_csrbank1_sram_reader_ready_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank1_sram_reader_ready_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ready_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_level_r = builder_interface1_bank_bus_dat_w[1:0]; +always @(*) begin + builder_csrbank1_sram_reader_level_re <= 1'd0; + builder_csrbank1_sram_reader_level_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + builder_csrbank1_sram_reader_level_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_level_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_slot0_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_slot0_re <= 1'd0; + builder_csrbank1_sram_reader_slot0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank1_sram_reader_slot0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_slot0_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_length0_r = builder_interface1_bank_bus_dat_w[10:0]; +always @(*) begin + builder_csrbank1_sram_reader_length0_re <= 1'd0; + builder_csrbank1_sram_reader_length0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank1_sram_reader_length0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_length0_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_ev_status_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_ev_status_re <= 1'd0; + builder_csrbank1_sram_reader_ev_status_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank1_sram_reader_ev_status_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_status_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_ev_pending_re <= 1'd0; + builder_csrbank1_sram_reader_ev_pending_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank1_sram_reader_ev_pending_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_pending_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_ev_enable0_re <= 1'd0; + builder_csrbank1_sram_reader_ev_enable0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank1_sram_reader_ev_enable0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_enable0_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_preamble_crc_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_preamble_crc_re <= 1'd0; + builder_csrbank1_preamble_crc_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin + builder_csrbank1_preamble_crc_re <= builder_interface1_bank_bus_we; + builder_csrbank1_preamble_crc_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_rx_datapath_preamble_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank1_rx_datapath_preamble_errors_re <= 1'd0; + builder_csrbank1_rx_datapath_preamble_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin + builder_csrbank1_rx_datapath_preamble_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rx_datapath_preamble_errors_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_rx_datapath_crc_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank1_rx_datapath_crc_errors_re <= 1'd0; + builder_csrbank1_rx_datapath_crc_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank1_rx_datapath_crc_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rx_datapath_crc_errors_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_slot_w = main_sram7_status; +assign main_sram8_we = builder_csrbank1_sram_writer_slot_we; +assign builder_csrbank1_sram_writer_length_w = main_sram10_status[10:0]; +assign main_sram11_we = builder_csrbank1_sram_writer_length_we; +assign builder_csrbank1_sram_writer_errors_w = main_sram13_status[31:0]; +assign main_sram14_we = builder_csrbank1_sram_writer_errors_we; +always @(*) begin + main_sram22_status <= 1'd0; + main_sram22_status <= main_sram21_available; +end +assign builder_csrbank1_sram_writer_ev_status_w = main_sram22_status; +assign main_sram23_we = builder_csrbank1_sram_writer_ev_status_we; +always @(*) begin + main_sram26_status <= 1'd0; + main_sram26_status <= main_sram25_available; +end +assign builder_csrbank1_sram_writer_ev_pending_w = main_sram26_status; +assign main_sram27_we = builder_csrbank1_sram_writer_ev_pending_we; +assign main_sram30_available = main_sram31_storage; +assign builder_csrbank1_sram_writer_ev_enable0_w = main_sram31_storage; +assign builder_csrbank1_sram_reader_ready_w = main_sram94_status; +assign main_sram95_we = builder_csrbank1_sram_reader_ready_we; +assign builder_csrbank1_sram_reader_level_w = main_sram97_status[1:0]; +assign main_sram98_we = builder_csrbank1_sram_reader_level_we; +assign builder_csrbank1_sram_reader_slot0_w = main_sram100_storage; +assign builder_csrbank1_sram_reader_length0_w = main_sram102_storage[10:0]; +always @(*) begin + main_sram110_status <= 1'd0; + main_sram110_status <= main_sram109_event0; +end +assign builder_csrbank1_sram_reader_ev_status_w = main_sram110_status; +assign main_sram111_we = builder_csrbank1_sram_reader_ev_status_we; +always @(*) begin + main_sram114_status <= 1'd0; + main_sram114_status <= main_sram113_event0; +end +assign builder_csrbank1_sram_reader_ev_pending_w = main_sram114_status; +assign main_sram115_we = builder_csrbank1_sram_reader_ev_pending_we; +assign main_sram118_event0 = main_sram119_storage; +assign builder_csrbank1_sram_reader_ev_enable0_w = main_sram119_storage; +assign builder_csrbank1_preamble_crc_w = main_status; +assign main_we = builder_csrbank1_preamble_crc_we; +assign builder_csrbank1_rx_datapath_preamble_errors_w = main_preamble_errors_status[31:0]; +assign main_preamble_errors_we = builder_csrbank1_rx_datapath_preamble_errors_we; +assign builder_csrbank1_rx_datapath_crc_errors_w = main_crc_errors_status[31:0]; +assign main_crc_errors_we = builder_csrbank1_rx_datapath_crc_errors_we; +assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd1); +assign builder_csrbank2_crg_reset0_r = builder_interface2_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank2_crg_reset0_re <= 1'd0; + builder_csrbank2_crg_reset0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_crg_reset0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_crg_reset0_we <= (~builder_interface2_bank_bus_we); + end +end +assign builder_csrbank2_rx_inband_status_r = builder_interface2_bank_bus_dat_w[2:0]; +always @(*) begin + builder_csrbank2_rx_inband_status_re <= 1'd0; + builder_csrbank2_rx_inband_status_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_rx_inband_status_re <= builder_interface2_bank_bus_we; + builder_csrbank2_rx_inband_status_we <= (~builder_interface2_bank_bus_we); + end +end +assign builder_csrbank2_mdio_w0_r = builder_interface2_bank_bus_dat_w[2:0]; +always @(*) begin + builder_csrbank2_mdio_w0_re <= 1'd0; + builder_csrbank2_mdio_w0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank2_mdio_w0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_mdio_w0_we <= (~builder_interface2_bank_bus_we); + end +end +assign builder_csrbank2_mdio_r_r = builder_interface2_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank2_mdio_r_re <= 1'd0; + builder_csrbank2_mdio_r_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank2_mdio_r_re <= builder_interface2_bank_bus_we; + builder_csrbank2_mdio_r_we <= (~builder_interface2_bank_bus_we); + end +end +assign builder_csrbank2_crg_reset0_w = main_maccore_ethphy_reset_storage; +always @(*) begin + main_maccore_ethphy_status <= 3'd0; + main_maccore_ethphy_status[0] <= main_maccore_ethphy_link_status; + main_maccore_ethphy_status[1] <= main_maccore_ethphy_clock_speed; + main_maccore_ethphy_status[2] <= main_maccore_ethphy_duplex_status; +end +assign builder_csrbank2_rx_inband_status_w = main_maccore_ethphy_status[2:0]; +assign main_maccore_ethphy_we = builder_csrbank2_rx_inband_status_we; +assign main_maccore_ethphy_mdc = main_maccore_ethphy__w_storage[0]; +assign main_maccore_ethphy_oe = main_maccore_ethphy__w_storage[1]; +assign main_maccore_ethphy_w = main_maccore_ethphy__w_storage[2]; +assign builder_csrbank2_mdio_w0_w = main_maccore_ethphy__w_storage[2:0]; +assign builder_csrbank2_mdio_r_w = main_maccore_ethphy__r_status; +assign main_maccore_ethphy__r_we = builder_csrbank2_mdio_r_we; +assign builder_adr = builder_interface1_adr; +assign builder_we = builder_interface1_we; +assign builder_dat_w = builder_interface1_dat_w; +assign builder_interface1_dat_r = builder_dat_r; +assign builder_interface0_bank_bus_adr = builder_adr; +assign builder_interface1_bank_bus_adr = builder_adr; +assign builder_interface2_bank_bus_adr = builder_adr; +assign builder_interface0_bank_bus_we = builder_we; +assign builder_interface1_bank_bus_we = builder_we; +assign builder_interface2_bank_bus_we = builder_we; +assign builder_interface0_bank_bus_dat_w = builder_dat_w; +assign builder_interface1_bank_bus_dat_w = builder_dat_w; +assign builder_interface2_bank_bus_dat_w = builder_dat_w; +assign builder_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); +assign builder_t_slice_proxy0 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy1 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy2 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy3 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy4 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy5 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy6 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy7 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy8 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy9 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy10 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy11 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy12 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy13 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy14 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy15 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy16 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy17 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy18 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy19 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy20 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy21 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy22 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy23 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy24 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy25 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy26 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy27 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy28 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy29 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy30 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy31 = (~main_tx_crc_crc_next); +assign builder_complexslicelowerer_slice_proxy = {main_tx_crc_value, main_tx_crc_sink_payload_data[7:0]}; +assign builder_t_slice_proxy32 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy33 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy34 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy35 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy36 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy37 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy38 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy39 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy40 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy41 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy42 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy43 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy44 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy45 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy46 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy47 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy48 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy49 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy50 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy51 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy52 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy53 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy54 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy55 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy56 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy57 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy58 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy59 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy60 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy61 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy62 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy63 = (~main_liteethmaccrc32checker_crc_crc_next); +always @(*) begin + builder_self0 <= 30'd0; + case (builder_grant) + default: begin + builder_self0 <= main_wb_bus_adr; + end + endcase +end +always @(*) begin + builder_self1 <= 32'd0; + case (builder_grant) + default: begin + builder_self1 <= main_wb_bus_dat_w; + end + endcase +end +always @(*) begin + builder_self2 <= 4'd0; + case (builder_grant) + default: begin + builder_self2 <= main_wb_bus_sel; + end + endcase +end +always @(*) begin + builder_self3 <= 1'd0; + case (builder_grant) + default: begin + builder_self3 <= main_wb_bus_cyc; + end + endcase +end +always @(*) begin + builder_self4 <= 1'd0; + case (builder_grant) + default: begin + builder_self4 <= main_wb_bus_stb; + end + endcase +end +always @(*) begin + builder_self5 <= 1'd0; + case (builder_grant) + default: begin + builder_self5 <= main_wb_bus_we; + end + endcase +end +always @(*) begin + builder_self6 <= 3'd0; + case (builder_grant) + default: begin + builder_self6 <= main_wb_bus_cti; + end + endcase +end +always @(*) begin + builder_self7 <= 2'd0; + case (builder_grant) + default: begin + builder_self7 <= main_wb_bus_bte; + end + endcase +end +always @(*) begin + main_maccore_ethphy__r_status <= 1'd0; + main_maccore_ethphy__r_status <= main_maccore_ethphy_r; + main_maccore_ethphy__r_status <= builder_multiregimpl01; +end +assign main_tx_cdc_cdc_produce_rdomain = builder_multiregimpl11; +assign main_tx_cdc_cdc_consume_wdomain = builder_multiregimpl21; +assign main_pulsesynchronizer0_toggle_o = builder_multiregimpl31; +assign main_pulsesynchronizer1_toggle_o = builder_multiregimpl41; +assign main_rx_cdc_cdc_produce_rdomain = builder_multiregimpl51; +assign main_rx_cdc_cdc_consume_wdomain = builder_multiregimpl61; + + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + +always @(posedge eth_rx_clk) begin + main_maccore_ethphy_rx_ctl_reg <= main_maccore_ethphy_rx_ctl; + main_maccore_ethphy_rx_data_reg <= main_maccore_ethphy_rx_data; + main_maccore_ethphy_rx_ctl_reg_d <= main_maccore_ethphy_rx_ctl_reg; + main_maccore_ethphy_source_valid <= main_maccore_ethphy_rx_ctl_reg[0]; + main_maccore_ethphy_source_payload_data <= main_maccore_ethphy_rx_data_reg; + if ((main_maccore_ethphy_rx_ctl == 1'd0)) begin + main_maccore_ethphy_link_status <= main_maccore_ethphy_rx_data[0]; + main_maccore_ethphy_clock_speed <= main_maccore_ethphy_rx_data[2:1]; + main_maccore_ethphy_duplex_status <= main_maccore_ethphy_rx_data[3]; + end + builder_rxdatapath_liteethmacpreamblechecker_state <= builder_rxdatapath_liteethmacpreamblechecker_next_state; + if (main_pulsesynchronizer0_i) begin + main_pulsesynchronizer0_toggle_i <= (~main_pulsesynchronizer0_toggle_i); + end + if (main_liteethmaccrc32checker_crc_ce) begin + main_liteethmaccrc32checker_crc_reg <= main_liteethmaccrc32checker_crc_crc_next; + end + if (main_liteethmaccrc32checker_crc_reset) begin + main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + end + if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin + if ((main_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin + main_liteethmaccrc32checker_syncfifo_produce <= 1'd0; + end else begin + main_liteethmaccrc32checker_syncfifo_produce <= (main_liteethmaccrc32checker_syncfifo_produce + 1'd1); + end + end + if (main_liteethmaccrc32checker_syncfifo_do_read) begin + if ((main_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin + main_liteethmaccrc32checker_syncfifo_consume <= 1'd0; + end else begin + main_liteethmaccrc32checker_syncfifo_consume <= (main_liteethmaccrc32checker_syncfifo_consume + 1'd1); + end + end + if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin + if ((~main_liteethmaccrc32checker_syncfifo_do_read)) begin + main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level + 1'd1); + end + end else begin + if (main_liteethmaccrc32checker_syncfifo_do_read) begin + main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level - 1'd1); + end + end + if (main_liteethmaccrc32checker_fifo_reset) begin + main_liteethmaccrc32checker_syncfifo_level <= 3'd0; + main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + end + builder_rxdatapath_bufferizeendpoints_state <= builder_rxdatapath_bufferizeendpoints_next_state; + if (main_liteethmaccrc32checker_last_be_next_value_ce0) begin + main_liteethmaccrc32checker_last_be <= main_liteethmaccrc32checker_last_be_next_value0; + end + if (main_liteethmaccrc32checker_crc_error1_next_value_ce1) begin + main_liteethmaccrc32checker_crc_error1 <= main_liteethmaccrc32checker_crc_error1_next_value1; + end + if (((~main_bufferizeendpoints_pipe_valid_source_valid) | main_bufferizeendpoints_pipe_valid_source_ready)) begin + main_bufferizeendpoints_pipe_valid_source_valid <= main_bufferizeendpoints_pipe_valid_sink_valid; + main_bufferizeendpoints_pipe_valid_source_first <= main_bufferizeendpoints_pipe_valid_sink_first; + main_bufferizeendpoints_pipe_valid_source_last <= main_bufferizeendpoints_pipe_valid_sink_last; + main_bufferizeendpoints_pipe_valid_source_payload_data <= main_bufferizeendpoints_pipe_valid_sink_payload_data; + main_bufferizeendpoints_pipe_valid_source_payload_last_be <= main_bufferizeendpoints_pipe_valid_sink_payload_last_be; + main_bufferizeendpoints_pipe_valid_source_payload_error <= main_bufferizeendpoints_pipe_valid_sink_payload_error; + end + if (main_pulsesynchronizer1_i) begin + main_pulsesynchronizer1_toggle_i <= (~main_pulsesynchronizer1_toggle_i); + end + if (main_rx_converter_converter_source_ready) begin + main_rx_converter_converter_strobe_all <= 1'd0; + end + if (main_rx_converter_converter_load_part) begin + if (((main_rx_converter_converter_demux == 2'd3) | main_rx_converter_converter_sink_last)) begin + main_rx_converter_converter_demux <= 1'd0; + main_rx_converter_converter_strobe_all <= 1'd1; + end else begin + main_rx_converter_converter_demux <= (main_rx_converter_converter_demux + 1'd1); + end + end + if ((main_rx_converter_converter_source_valid & main_rx_converter_converter_source_ready)) begin + if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin + main_rx_converter_converter_source_first <= main_rx_converter_converter_sink_first; + main_rx_converter_converter_source_last <= main_rx_converter_converter_sink_last; + end else begin + main_rx_converter_converter_source_first <= 1'd0; + main_rx_converter_converter_source_last <= 1'd0; + end + end else begin + if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin + main_rx_converter_converter_source_first <= (main_rx_converter_converter_sink_first | main_rx_converter_converter_source_first); + main_rx_converter_converter_source_last <= (main_rx_converter_converter_sink_last | main_rx_converter_converter_source_last); + end + end + if (main_rx_converter_converter_load_part) begin + case (main_rx_converter_converter_demux) + 1'd0: begin + main_rx_converter_converter_source_payload_data[9:0] <= main_rx_converter_converter_sink_payload_data; + end + 1'd1: begin + main_rx_converter_converter_source_payload_data[19:10] <= main_rx_converter_converter_sink_payload_data; + end + 2'd2: begin + main_rx_converter_converter_source_payload_data[29:20] <= main_rx_converter_converter_sink_payload_data; + end + 2'd3: begin + main_rx_converter_converter_source_payload_data[39:30] <= main_rx_converter_converter_sink_payload_data; + end + endcase + end + if (main_rx_converter_converter_load_part) begin + main_rx_converter_converter_source_payload_valid_token_count <= (main_rx_converter_converter_demux + 1'd1); + end + main_rx_cdc_cdc_graycounter0_q_binary <= main_rx_cdc_cdc_graycounter0_q_next_binary; + main_rx_cdc_cdc_graycounter0_q <= main_rx_cdc_cdc_graycounter0_q_next; + if (eth_rx_rst) begin + main_maccore_ethphy_source_valid <= 1'd0; + main_maccore_ethphy_source_payload_data <= 8'd0; + main_maccore_ethphy_link_status <= 1'd0; + main_maccore_ethphy_clock_speed <= 1'd0; + main_maccore_ethphy_duplex_status <= 1'd0; + main_maccore_ethphy_rx_ctl_reg <= 2'd0; + main_maccore_ethphy_rx_data_reg <= 8'd0; + main_maccore_ethphy_rx_ctl_reg_d <= 2'd0; + main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + main_liteethmaccrc32checker_syncfifo_level <= 3'd0; + main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + main_liteethmaccrc32checker_last_be <= 1'd0; + main_liteethmaccrc32checker_crc_error1 <= 1'd0; + main_bufferizeendpoints_pipe_valid_source_valid <= 1'd0; + main_bufferizeendpoints_pipe_valid_source_payload_data <= 8'd0; + main_bufferizeendpoints_pipe_valid_source_payload_last_be <= 1'd0; + main_bufferizeendpoints_pipe_valid_source_payload_error <= 1'd0; + main_rx_converter_converter_source_payload_data <= 40'd0; + main_rx_converter_converter_source_payload_valid_token_count <= 3'd0; + main_rx_converter_converter_demux <= 2'd0; + main_rx_converter_converter_strobe_all <= 1'd0; + main_rx_cdc_cdc_graycounter0_q <= 6'd0; + main_rx_cdc_cdc_graycounter0_q_binary <= 6'd0; + builder_rxdatapath_liteethmacpreamblechecker_state <= 1'd0; + builder_rxdatapath_bufferizeendpoints_state <= 2'd0; + end + builder_multiregimpl60 <= main_rx_cdc_cdc_graycounter1_q; + builder_multiregimpl61 <= builder_multiregimpl60; +end + +always @(posedge eth_tx_clk) begin + main_tx_cdc_cdc_graycounter1_q_binary <= main_tx_cdc_cdc_graycounter1_q_next_binary; + main_tx_cdc_cdc_graycounter1_q <= main_tx_cdc_cdc_graycounter1_q_next; + if ((main_tx_converter_converter_source_valid & main_tx_converter_converter_source_ready)) begin + if (main_tx_converter_converter_last) begin + main_tx_converter_converter_mux <= 1'd0; + end else begin + main_tx_converter_converter_mux <= (main_tx_converter_converter_mux + 1'd1); + end + end + builder_txdatapath_liteethmactxlastbe_state <= builder_txdatapath_liteethmactxlastbe_next_state; + builder_txdatapath_liteethmacpaddinginserter_state <= builder_txdatapath_liteethmacpaddinginserter_next_state; + if (main_tx_padding_counter_clockdomainsrenamer0_next_value_ce) begin + main_tx_padding_counter <= main_tx_padding_counter_clockdomainsrenamer0_next_value; + end + if (main_tx_crc_is_ongoing0) begin + main_tx_crc_cnt <= 2'd3; + end else begin + if ((main_tx_crc_is_ongoing1 & (~main_tx_crc_cnt_done))) begin + main_tx_crc_cnt <= (main_tx_crc_cnt - main_tx_crc_source_ready); + end + end + if (main_tx_crc_ce) begin + main_tx_crc_reg <= main_tx_crc_crc_next; + end + if (main_tx_crc_reset) begin + main_tx_crc_reg <= 32'd4294967295; + end + builder_txdatapath_bufferizeendpoints_state <= builder_txdatapath_bufferizeendpoints_next_state; + if (main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0) begin + main_tx_crc_crc_packet <= main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0; + end + if (main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1) begin + main_tx_crc_last_be <= main_tx_crc_last_be_clockdomainsrenamer1_next_value1; + end + if (((~main_tx_crc_pipe_valid_source_valid) | main_tx_crc_pipe_valid_source_ready)) begin + main_tx_crc_pipe_valid_source_valid <= main_tx_crc_pipe_valid_sink_valid; + main_tx_crc_pipe_valid_source_first <= main_tx_crc_pipe_valid_sink_first; + main_tx_crc_pipe_valid_source_last <= main_tx_crc_pipe_valid_sink_last; + main_tx_crc_pipe_valid_source_payload_data <= main_tx_crc_pipe_valid_sink_payload_data; + main_tx_crc_pipe_valid_source_payload_last_be <= main_tx_crc_pipe_valid_sink_payload_last_be; + main_tx_crc_pipe_valid_source_payload_error <= main_tx_crc_pipe_valid_sink_payload_error; + end + builder_txdatapath_liteethmacpreambleinserter_state <= builder_txdatapath_liteethmacpreambleinserter_next_state; + if (main_tx_preamble_count_clockdomainsrenamer2_next_value_ce) begin + main_tx_preamble_count <= main_tx_preamble_count_clockdomainsrenamer2_next_value; + end + builder_txdatapath_liteethmacgap_state <= builder_txdatapath_liteethmacgap_next_state; + if (main_tx_gap_counter_clockdomainsrenamer3_next_value_ce) begin + main_tx_gap_counter <= main_tx_gap_counter_clockdomainsrenamer3_next_value; + end + if (eth_tx_rst) begin + main_tx_cdc_cdc_graycounter1_q <= 6'd0; + main_tx_cdc_cdc_graycounter1_q_binary <= 6'd0; + main_tx_converter_converter_mux <= 2'd0; + main_tx_padding_counter <= 16'd0; + main_tx_crc_crc_packet <= 32'd0; + main_tx_crc_last_be <= 1'd0; + main_tx_crc_reg <= 32'd4294967295; + main_tx_crc_cnt <= 2'd3; + main_tx_crc_pipe_valid_source_valid <= 1'd0; + main_tx_crc_pipe_valid_source_payload_data <= 8'd0; + main_tx_crc_pipe_valid_source_payload_last_be <= 1'd0; + main_tx_crc_pipe_valid_source_payload_error <= 1'd0; + builder_txdatapath_liteethmactxlastbe_state <= 1'd0; + builder_txdatapath_liteethmacpaddinginserter_state <= 1'd0; + builder_txdatapath_bufferizeendpoints_state <= 2'd0; + builder_txdatapath_liteethmacpreambleinserter_state <= 2'd0; + builder_txdatapath_liteethmacgap_state <= 1'd0; + end + builder_multiregimpl10 <= main_tx_cdc_cdc_graycounter0_q; + builder_multiregimpl11 <= builder_multiregimpl10; +end + +always @(posedge por_clk) begin + main_maccore_int_rst <= sys_reset; +end + +always @(posedge sys_clk) begin + builder_slave_sel_r <= builder_slave_sel; + if (builder_wait) begin + if ((~builder_done)) begin + builder_count <= (builder_count - 1'd1); + end + end else begin + builder_count <= 20'd1000000; + end + if ((main_maccore_maccore_bus_errors != 32'd4294967295)) begin + if (main_maccore_maccore_bus_error) begin + main_maccore_maccore_bus_errors <= (main_maccore_maccore_bus_errors + 1'd1); + end + end + main_tx_cdc_cdc_graycounter0_q_binary <= main_tx_cdc_cdc_graycounter0_q_next_binary; + main_tx_cdc_cdc_graycounter0_q <= main_tx_cdc_cdc_graycounter0_q_next; + if (main_pulsesynchronizer0_o) begin + main_preamble_errors_status <= (main_preamble_errors_status + 1'd1); + end + if (main_pulsesynchronizer1_o) begin + main_crc_errors_status <= (main_crc_errors_status + 1'd1); + end + main_pulsesynchronizer0_toggle_o_r <= main_pulsesynchronizer0_toggle_o; + main_pulsesynchronizer1_toggle_o_r <= main_pulsesynchronizer1_toggle_o; + main_rx_cdc_cdc_graycounter1_q_binary <= main_rx_cdc_cdc_graycounter1_q_next_binary; + main_rx_cdc_cdc_graycounter1_q <= main_rx_cdc_cdc_graycounter1_q_next; + if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin + main_sram57_produce <= (main_sram57_produce + 1'd1); + end + if (main_sram63_do_read) begin + main_sram58_consume <= (main_sram58_consume + 1'd1); + end + if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin + if ((~main_sram63_do_read)) begin + main_sram55_level <= (main_sram55_level + 1'd1); + end + end else begin + if (main_sram63_do_read) begin + main_sram55_level <= (main_sram55_level - 1'd1); + end + end + builder_liteethmacsramwriter_state <= builder_liteethmacsramwriter_next_state; + if (main_sram35_length_liteethmacsramwriter_t_next_value_ce) begin + main_sram35_length <= main_sram35_length_liteethmacsramwriter_t_next_value; + end + if (main_sram13_status_liteethmacsramwriter_f_next_value_ce) begin + main_sram13_status <= main_sram13_status_liteethmacsramwriter_f_next_value; + end + if (main_slot_liteethmacsramwriter_next_value_ce) begin + main_slot <= main_slot_liteethmacsramwriter_next_value; + end + if (main_sram108_clear) begin + main_sram106_pending <= 1'd0; + end + if (main_sram107_trigger) begin + main_sram106_pending <= 1'd1; + end + if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin + main_sram143_produce <= (main_sram143_produce + 1'd1); + end + if (main_sram149_do_read) begin + main_sram144_consume <= (main_sram144_consume + 1'd1); + end + if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin + if ((~main_sram149_do_read)) begin + main_sram141_level <= (main_sram141_level + 1'd1); + end + end else begin + if (main_sram149_do_read) begin + main_sram141_level <= (main_sram141_level - 1'd1); + end + end + builder_liteethmacsramreader_state <= builder_liteethmacsramreader_next_state; + if (main_sram122_length_liteethmacsramreader_next_value_ce) begin + main_sram122_length <= main_sram122_length_liteethmacsramreader_next_value; + end + main_interface0_ack <= 1'd0; + if (((main_interface0_cyc & main_interface0_stb) & ((~main_interface0_ack) | main_sram0_adr_burst))) begin + main_interface0_ack <= 1'd1; + end + main_interface1_ack <= 1'd0; + if (((main_interface1_cyc & main_interface1_stb) & ((~main_interface1_ack) | main_sram1_adr_burst))) begin + main_interface1_ack <= 1'd1; + end + main_interface2_ack <= 1'd0; + if (((main_interface2_cyc & main_interface2_stb) & ((~main_interface2_ack) | main_sram2_adr_burst))) begin + main_interface2_ack <= 1'd1; + end + main_interface3_ack <= 1'd0; + if (((main_interface3_cyc & main_interface3_stb) & ((~main_interface3_ack) | main_sram3_adr_burst))) begin + main_interface3_ack <= 1'd1; + end + main_slave_sel_r <= main_slave_sel; + builder_state <= builder_next_state; + builder_interface0_bank_bus_dat_r <= 1'd0; + if (builder_csrbank0_sel) begin + case (builder_interface0_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_reset0_w; + end + 1'd1: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_scratch0_w; + end + 2'd2: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_bus_errors_w; + end + endcase + end + if (builder_csrbank0_reset0_re) begin + main_maccore_maccore_reset_storage[1:0] <= builder_csrbank0_reset0_r; + end + main_maccore_maccore_reset_re <= builder_csrbank0_reset0_re; + if (builder_csrbank0_scratch0_re) begin + main_maccore_maccore_scratch_storage[31:0] <= builder_csrbank0_scratch0_r; + end + main_maccore_maccore_scratch_re <= builder_csrbank0_scratch0_re; + main_maccore_maccore_bus_errors_re <= builder_csrbank0_bus_errors_re; + builder_interface1_bank_bus_dat_r <= 1'd0; + if (builder_csrbank1_sel) begin + case (builder_interface1_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_slot_w; + end + 1'd1: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_length_w; + end + 2'd2: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_errors_w; + end + 2'd3: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_status_w; + end + 3'd4: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_pending_w; + end + 3'd5: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_enable0_w; + end + 3'd6: begin + builder_interface1_bank_bus_dat_r <= main_start_w; + end + 3'd7: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ready_w; + end + 4'd8: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_level_w; + end + 4'd9: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_slot0_w; + end + 4'd10: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_length0_w; + end + 4'd11: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_status_w; + end + 4'd12: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_pending_w; + end + 4'd13: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_enable0_w; + end + 4'd14: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_crc_w; + end + 4'd15: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_preamble_errors_w; + end + 5'd16: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_crc_errors_w; + end + endcase + end + main_sram9_re <= builder_csrbank1_sram_writer_slot_re; + main_sram12_re <= builder_csrbank1_sram_writer_length_re; + main_sram15_re <= builder_csrbank1_sram_writer_errors_re; + main_sram24_re <= builder_csrbank1_sram_writer_ev_status_re; + if (builder_csrbank1_sram_writer_ev_pending_re) begin + main_sram29_r <= builder_csrbank1_sram_writer_ev_pending_r; + end + main_sram28_re <= builder_csrbank1_sram_writer_ev_pending_re; + if (builder_csrbank1_sram_writer_ev_enable0_re) begin + main_sram31_storage <= builder_csrbank1_sram_writer_ev_enable0_r; + end + main_sram32_re <= builder_csrbank1_sram_writer_ev_enable0_re; + main_sram96_re <= builder_csrbank1_sram_reader_ready_re; + main_sram99_re <= builder_csrbank1_sram_reader_level_re; + if (builder_csrbank1_sram_reader_slot0_re) begin + main_sram100_storage <= builder_csrbank1_sram_reader_slot0_r; + end + main_sram101_re <= builder_csrbank1_sram_reader_slot0_re; + if (builder_csrbank1_sram_reader_length0_re) begin + main_sram102_storage[10:0] <= builder_csrbank1_sram_reader_length0_r; + end + main_sram103_re <= builder_csrbank1_sram_reader_length0_re; + main_sram112_re <= builder_csrbank1_sram_reader_ev_status_re; + if (builder_csrbank1_sram_reader_ev_pending_re) begin + main_sram117_r <= builder_csrbank1_sram_reader_ev_pending_r; + end + main_sram116_re <= builder_csrbank1_sram_reader_ev_pending_re; + if (builder_csrbank1_sram_reader_ev_enable0_re) begin + main_sram119_storage <= builder_csrbank1_sram_reader_ev_enable0_r; + end + main_sram120_re <= builder_csrbank1_sram_reader_ev_enable0_re; + main_re <= builder_csrbank1_preamble_crc_re; + main_preamble_errors_re <= builder_csrbank1_rx_datapath_preamble_errors_re; + main_crc_errors_re <= builder_csrbank1_rx_datapath_crc_errors_re; + builder_interface2_bank_bus_dat_r <= 1'd0; + if (builder_csrbank2_sel) begin + case (builder_interface2_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_crg_reset0_w; + end + 1'd1: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_rx_inband_status_w; + end + 2'd2: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_w0_w; + end + 2'd3: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_r_w; + end + endcase + end + if (builder_csrbank2_crg_reset0_re) begin + main_maccore_ethphy_reset_storage <= builder_csrbank2_crg_reset0_r; + end + main_maccore_ethphy_reset_re <= builder_csrbank2_crg_reset0_re; + main_maccore_ethphy_re <= builder_csrbank2_rx_inband_status_re; + if (builder_csrbank2_mdio_w0_re) begin + main_maccore_ethphy__w_storage[2:0] <= builder_csrbank2_mdio_w0_r; + end + main_maccore_ethphy__w_re <= builder_csrbank2_mdio_w0_re; + main_maccore_ethphy__r_re <= builder_csrbank2_mdio_r_re; + if (sys_rst) begin + main_maccore_maccore_reset_storage <= 2'd0; + main_maccore_maccore_reset_re <= 1'd0; + main_maccore_maccore_scratch_storage <= 32'd305419896; + main_maccore_maccore_scratch_re <= 1'd0; + main_maccore_maccore_bus_errors_re <= 1'd0; + main_maccore_maccore_bus_errors <= 32'd0; + main_maccore_ethphy_reset_storage <= 1'd0; + main_maccore_ethphy_reset_re <= 1'd0; + main_maccore_ethphy_re <= 1'd0; + main_maccore_ethphy__w_storage <= 3'd0; + main_maccore_ethphy__w_re <= 1'd0; + main_maccore_ethphy__r_re <= 1'd0; + main_re <= 1'd0; + main_tx_cdc_cdc_graycounter0_q <= 6'd0; + main_tx_cdc_cdc_graycounter0_q_binary <= 6'd0; + main_preamble_errors_status <= 32'd0; + main_preamble_errors_re <= 1'd0; + main_crc_errors_status <= 32'd0; + main_crc_errors_re <= 1'd0; + main_rx_cdc_cdc_graycounter1_q <= 6'd0; + main_rx_cdc_cdc_graycounter1_q_binary <= 6'd0; + main_sram9_re <= 1'd0; + main_sram12_re <= 1'd0; + main_sram13_status <= 32'd0; + main_sram15_re <= 1'd0; + main_sram24_re <= 1'd0; + main_sram28_re <= 1'd0; + main_sram29_r <= 1'd0; + main_sram31_storage <= 1'd0; + main_sram32_re <= 1'd0; + main_slot <= 1'd0; + main_sram35_length <= 11'd0; + main_sram55_level <= 2'd0; + main_sram57_produce <= 1'd0; + main_sram58_consume <= 1'd0; + main_sram96_re <= 1'd0; + main_sram99_re <= 1'd0; + main_sram101_re <= 1'd0; + main_sram103_re <= 1'd0; + main_sram106_pending <= 1'd0; + main_sram112_re <= 1'd0; + main_sram116_re <= 1'd0; + main_sram117_r <= 1'd0; + main_sram119_storage <= 1'd0; + main_sram120_re <= 1'd0; + main_sram122_length <= 11'd0; + main_sram141_level <= 2'd0; + main_sram143_produce <= 1'd0; + main_sram144_consume <= 1'd0; + main_interface0_ack <= 1'd0; + main_interface1_ack <= 1'd0; + main_interface2_ack <= 1'd0; + main_interface3_ack <= 1'd0; + main_slave_sel_r <= 4'd0; + builder_slave_sel_r <= 2'd0; + builder_count <= 20'd1000000; + builder_liteethmacsramwriter_state <= 3'd0; + builder_liteethmacsramreader_state <= 2'd0; + builder_state <= 1'd0; + end + builder_multiregimpl00 <= main_maccore_ethphy_data_r; + builder_multiregimpl01 <= builder_multiregimpl00; + builder_multiregimpl20 <= main_tx_cdc_cdc_graycounter1_q; + builder_multiregimpl21 <= builder_multiregimpl20; + builder_multiregimpl30 <= main_pulsesynchronizer0_toggle_i; + builder_multiregimpl31 <= builder_multiregimpl30; + builder_multiregimpl40 <= main_pulsesynchronizer1_toggle_i; + builder_multiregimpl41 <= builder_multiregimpl40; + builder_multiregimpl50 <= main_rx_cdc_cdc_graycounter0_q; + builder_multiregimpl51 <= builder_multiregimpl50; +end + + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Instance DELAYG of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("SCLK_ALIGNED"), + .DEL_VALUE (7'd80) +) DELAYG ( + // Inputs. + .A (main_maccore_ethphy_eth_tx_clk_o), + + // Outputs. + .Z (rgmii_clocks_tx) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_1 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("SCLK_ALIGNED"), + .DEL_VALUE (1'd0) +) DELAYG_1 ( + // Inputs. + .A (main_maccore_ethphy_tx_ctl_oddrx1f), + + // Outputs. + .Z (rgmii_tx_ctl) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_2 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("SCLK_ALIGNED"), + .DEL_VALUE (1'd0) +) DELAYG_2 ( + // Inputs. + .A (main_maccore_ethphy_tx_data_oddrx1f[0]), + + // Outputs. + .Z (rgmii_tx_data[0]) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_3 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("SCLK_ALIGNED"), + .DEL_VALUE (1'd0) +) DELAYG_3 ( + // Inputs. + .A (main_maccore_ethphy_tx_data_oddrx1f[1]), + + // Outputs. + .Z (rgmii_tx_data[1]) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_4 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("SCLK_ALIGNED"), + .DEL_VALUE (1'd0) +) DELAYG_4 ( + // Inputs. + .A (main_maccore_ethphy_tx_data_oddrx1f[2]), + + // Outputs. + .Z (rgmii_tx_data[2]) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_5 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("SCLK_ALIGNED"), + .DEL_VALUE (1'd0) +) DELAYG_5 ( + // Inputs. + .A (main_maccore_ethphy_tx_data_oddrx1f[3]), + + // Outputs. + .Z (rgmii_tx_data[3]) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_6 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("SCLK_ALIGNED"), + .DEL_VALUE (1'd0) +) DELAYG_6 ( + // Inputs. + .A (rgmii_rx_ctl), + + // Outputs. + .Z (main_maccore_ethphy_rx_ctl_delayf) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_7 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("SCLK_ALIGNED"), + .DEL_VALUE (1'd0) +) DELAYG_7 ( + // Inputs. + .A (rgmii_rx_data[0]), + + // Outputs. + .Z (main_maccore_ethphy_rx_data_delayf[0]) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_8 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("SCLK_ALIGNED"), + .DEL_VALUE (1'd0) +) DELAYG_8 ( + // Inputs. + .A (rgmii_rx_data[1]), + + // Outputs. + .Z (main_maccore_ethphy_rx_data_delayf[1]) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_9 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("SCLK_ALIGNED"), + .DEL_VALUE (1'd0) +) DELAYG_9 ( + // Inputs. + .A (rgmii_rx_data[2]), + + // Outputs. + .Z (main_maccore_ethphy_rx_data_delayf[2]) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_10 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("SCLK_ALIGNED"), + .DEL_VALUE (1'd0) +) DELAYG_10 ( + // Inputs. + .A (rgmii_rx_data[3]), + + // Outputs. + .Z (main_maccore_ethphy_rx_data_delayf[3]) +); + +assign rgmii_mdio = main_maccore_ethphy_data_oe ? main_maccore_ethphy_data_w : 1'bz; +assign main_maccore_ethphy_data_r = rgmii_mdio; + +//------------------------------------------------------------------------------ +// Memory storage: 32-words x 42-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 42 +// Port 1 | Read: Sync | Write: ---- | +reg [41:0] storage[0:31]; +reg [41:0] storage_dat0; +reg [41:0] storage_dat1; +always @(posedge sys_clk) begin + if (main_tx_cdc_cdc_wrport_we) + storage[main_tx_cdc_cdc_wrport_adr] <= main_tx_cdc_cdc_wrport_dat_w; + storage_dat0 <= storage[main_tx_cdc_cdc_wrport_adr]; +end +always @(posedge eth_tx_clk) begin + storage_dat1 <= storage[main_tx_cdc_cdc_rdport_adr]; +end +assign main_tx_cdc_cdc_wrport_dat_r = storage_dat0; +assign main_tx_cdc_cdc_rdport_dat_r = storage_dat1; + + +//------------------------------------------------------------------------------ +// Memory storage_1: 5-words x 12-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 12 +// Port 1 | Read: Async | Write: ---- | +reg [11:0] storage_1[0:4]; +reg [11:0] storage_1_dat0; +always @(posedge eth_rx_clk) begin + if (main_liteethmaccrc32checker_syncfifo_wrport_we) + storage_1[main_liteethmaccrc32checker_syncfifo_wrport_adr] <= main_liteethmaccrc32checker_syncfifo_wrport_dat_w; + storage_1_dat0 <= storage_1[main_liteethmaccrc32checker_syncfifo_wrport_adr]; +end +always @(posedge eth_rx_clk) begin +end +assign main_liteethmaccrc32checker_syncfifo_wrport_dat_r = storage_1_dat0; +assign main_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage_1[main_liteethmaccrc32checker_syncfifo_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_2: 32-words x 42-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 42 +// Port 1 | Read: Sync | Write: ---- | +reg [41:0] storage_2[0:31]; +reg [41:0] storage_2_dat0; +reg [41:0] storage_2_dat1; +always @(posedge eth_rx_clk) begin + if (main_rx_cdc_cdc_wrport_we) + storage_2[main_rx_cdc_cdc_wrport_adr] <= main_rx_cdc_cdc_wrport_dat_w; + storage_2_dat0 <= storage_2[main_rx_cdc_cdc_wrport_adr]; +end +always @(posedge sys_clk) begin + storage_2_dat1 <= storage_2[main_rx_cdc_cdc_rdport_adr]; +end +assign main_rx_cdc_cdc_wrport_dat_r = storage_2_dat0; +assign main_rx_cdc_cdc_rdport_dat_r = storage_2_dat1; + + +//------------------------------------------------------------------------------ +// Memory storage_3: 2-words x 14-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 14 +// Port 1 | Read: Async | Write: ---- | +reg [13:0] storage_3[0:1]; +reg [13:0] storage_3_dat0; +always @(posedge sys_clk) begin + if (main_sram61_we) + storage_3[main_sram59_adr] <= main_sram62_dat_w; + storage_3_dat0 <= storage_3[main_sram59_adr]; +end +always @(posedge sys_clk) begin +end +assign main_sram60_dat_r = storage_3_dat0; +assign main_sram65_dat_r = storage_3[main_sram64_adr]; + + +//------------------------------------------------------------------------------ +// Memory mem: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 32 +// Port 1 | Read: Sync | Write: ---- | +reg [31:0] mem[0:382]; +reg [8:0] mem_adr0; +reg [31:0] mem_dat1; +always @(posedge sys_clk) begin + if (main_sram77_we) + mem[main_sram75_adr] <= main_sram78_dat_w; + mem_adr0 <= main_sram75_adr; +end +always @(posedge sys_clk) begin + mem_dat1 <= mem[main_sram0_adr]; +end +assign main_sram76_dat_r = mem[mem_adr0]; +assign main_sram0_dat_r = mem_dat1; + + +//------------------------------------------------------------------------------ +// Memory mem_1: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 32 +// Port 1 | Read: Sync | Write: ---- | +reg [31:0] mem_1[0:382]; +reg [8:0] mem_1_adr0; +reg [31:0] mem_1_dat1; +always @(posedge sys_clk) begin + if (main_sram81_we) + mem_1[main_sram79_adr] <= main_sram82_dat_w; + mem_1_adr0 <= main_sram79_adr; +end +always @(posedge sys_clk) begin + mem_1_dat1 <= mem_1[main_sram1_adr]; +end +assign main_sram80_dat_r = mem_1[mem_1_adr0]; +assign main_sram1_dat_r = mem_1_dat1; + + +//------------------------------------------------------------------------------ +// Memory storage_4: 2-words x 14-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 14 +// Port 1 | Read: Async | Write: ---- | +reg [13:0] storage_4[0:1]; +reg [13:0] storage_4_dat0; +always @(posedge sys_clk) begin + if (main_sram147_we) + storage_4[main_sram145_adr] <= main_sram148_dat_w; + storage_4_dat0 <= storage_4[main_sram145_adr]; +end +always @(posedge sys_clk) begin +end +assign main_sram146_dat_r = storage_4_dat0; +assign main_sram151_dat_r = storage_4[main_sram150_adr]; + + +//------------------------------------------------------------------------------ +// Memory mem_2: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +reg [31:0] mem_2[0:382]; +reg [31:0] mem_2_dat0; +reg [8:0] mem_2_adr1; +always @(posedge sys_clk) begin + if (main_sram163_re) + mem_2_dat0 <= mem_2[main_sram161_adr]; +end +always @(posedge sys_clk) begin + if (main_sram2_we[0]) + mem_2[main_sram2_adr][7:0] <= main_sram2_dat_w[7:0]; + if (main_sram2_we[1]) + mem_2[main_sram2_adr][15:8] <= main_sram2_dat_w[15:8]; + if (main_sram2_we[2]) + mem_2[main_sram2_adr][23:16] <= main_sram2_dat_w[23:16]; + if (main_sram2_we[3]) + mem_2[main_sram2_adr][31:24] <= main_sram2_dat_w[31:24]; + mem_2_adr1 <= main_sram2_adr; +end +assign main_sram162_dat_r = mem_2_dat0; +assign main_sram2_dat_r = mem_2[mem_2_adr1]; + + +//------------------------------------------------------------------------------ +// Memory mem_3: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +reg [31:0] mem_3[0:382]; +reg [31:0] mem_3_dat0; +reg [8:0] mem_3_adr1; +always @(posedge sys_clk) begin + if (main_sram166_re) + mem_3_dat0 <= mem_3[main_sram164_adr]; +end +always @(posedge sys_clk) begin + if (main_sram3_we[0]) + mem_3[main_sram3_adr][7:0] <= main_sram3_dat_w[7:0]; + if (main_sram3_we[1]) + mem_3[main_sram3_adr][15:8] <= main_sram3_dat_w[15:8]; + if (main_sram3_we[2]) + mem_3[main_sram3_adr][23:16] <= main_sram3_dat_w[23:16]; + if (main_sram3_we[3]) + mem_3[main_sram3_adr][31:24] <= main_sram3_dat_w[31:24]; + mem_3_adr1 <= main_sram3_adr; +end +assign main_sram165_dat_r = mem_3_dat0; +assign main_sram3_dat_r = mem_3[mem_3_adr1]; + + +//------------------------------------------------------------------------------ +// Instance ODDRX1F of ODDRX1F Module. +//------------------------------------------------------------------------------ +ODDRX1F ODDRX1F( + // Inputs. + .D0 (1'd1), + .D1 (1'd0), + .SCLK (eth_tx_clk), + + // Outputs. + .Q (main_maccore_ethphy_eth_tx_clk_o) +); + +//------------------------------------------------------------------------------ +// Instance FD1S3BX of FD1S3BX Module. +//------------------------------------------------------------------------------ +FD1S3BX FD1S3BX( + // Inputs. + .CK (eth_tx_clk), + .D (1'd0), + .PD (main_maccore_ethphy_reset), + + // Outputs. + .Q (builder_rst10) +); + +//------------------------------------------------------------------------------ +// Instance FD1S3BX_1 of FD1S3BX Module. +//------------------------------------------------------------------------------ +FD1S3BX FD1S3BX_1( + // Inputs. + .CK (eth_tx_clk), + .D (builder_rst10), + .PD (main_maccore_ethphy_reset), + + // Outputs. + .Q (eth_tx_rst) +); + +//------------------------------------------------------------------------------ +// Instance FD1S3BX_2 of FD1S3BX Module. +//------------------------------------------------------------------------------ +FD1S3BX FD1S3BX_2( + // Inputs. + .CK (eth_rx_clk), + .D (1'd0), + .PD (main_maccore_ethphy_reset), + + // Outputs. + .Q (builder_rst11) +); + +//------------------------------------------------------------------------------ +// Instance FD1S3BX_3 of FD1S3BX Module. +//------------------------------------------------------------------------------ +FD1S3BX FD1S3BX_3( + // Inputs. + .CK (eth_rx_clk), + .D (builder_rst11), + .PD (main_maccore_ethphy_reset), + + // Outputs. + .Q (eth_rx_rst) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX1F_1 of ODDRX1F Module. +//------------------------------------------------------------------------------ +ODDRX1F ODDRX1F_1( + // Inputs. + .D0 (main_maccore_ethphy_sink_valid), + .D1 (main_maccore_ethphy_sink_valid), + .SCLK (eth_tx_clk), + + // Outputs. + .Q (main_maccore_ethphy_tx_ctl_oddrx1f) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX1F_2 of ODDRX1F Module. +//------------------------------------------------------------------------------ +ODDRX1F ODDRX1F_2( + // Inputs. + .D0 (main_maccore_ethphy_sink_payload_data[0]), + .D1 (main_maccore_ethphy_sink_payload_data[4]), + .SCLK (eth_tx_clk), + + // Outputs. + .Q (main_maccore_ethphy_tx_data_oddrx1f[0]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX1F_3 of ODDRX1F Module. +//------------------------------------------------------------------------------ +ODDRX1F ODDRX1F_3( + // Inputs. + .D0 (main_maccore_ethphy_sink_payload_data[1]), + .D1 (main_maccore_ethphy_sink_payload_data[5]), + .SCLK (eth_tx_clk), + + // Outputs. + .Q (main_maccore_ethphy_tx_data_oddrx1f[1]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX1F_4 of ODDRX1F Module. +//------------------------------------------------------------------------------ +ODDRX1F ODDRX1F_4( + // Inputs. + .D0 (main_maccore_ethphy_sink_payload_data[2]), + .D1 (main_maccore_ethphy_sink_payload_data[6]), + .SCLK (eth_tx_clk), + + // Outputs. + .Q (main_maccore_ethphy_tx_data_oddrx1f[2]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX1F_5 of ODDRX1F Module. +//------------------------------------------------------------------------------ +ODDRX1F ODDRX1F_5( + // Inputs. + .D0 (main_maccore_ethphy_sink_payload_data[3]), + .D1 (main_maccore_ethphy_sink_payload_data[7]), + .SCLK (eth_tx_clk), + + // Outputs. + .Q (main_maccore_ethphy_tx_data_oddrx1f[3]) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX1F of IDDRX1F Module. +//------------------------------------------------------------------------------ +IDDRX1F IDDRX1F( + // Inputs. + .D (main_maccore_ethphy_rx_ctl_delayf), + .SCLK (eth_rx_clk), + + // Outputs. + .Q0 (main_maccore_ethphy_rx_ctl[0]), + .Q1 (main_maccore_ethphy_rx_ctl[1]) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX1F_1 of IDDRX1F Module. +//------------------------------------------------------------------------------ +IDDRX1F IDDRX1F_1( + // Inputs. + .D (main_maccore_ethphy_rx_data_delayf[0]), + .SCLK (eth_rx_clk), + + // Outputs. + .Q0 (main_maccore_ethphy_rx_data[0]), + .Q1 (main_maccore_ethphy_rx_data[4]) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX1F_2 of IDDRX1F Module. +//------------------------------------------------------------------------------ +IDDRX1F IDDRX1F_2( + // Inputs. + .D (main_maccore_ethphy_rx_data_delayf[1]), + .SCLK (eth_rx_clk), + + // Outputs. + .Q0 (main_maccore_ethphy_rx_data[1]), + .Q1 (main_maccore_ethphy_rx_data[5]) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX1F_3 of IDDRX1F Module. +//------------------------------------------------------------------------------ +IDDRX1F IDDRX1F_3( + // Inputs. + .D (main_maccore_ethphy_rx_data_delayf[2]), + .SCLK (eth_rx_clk), + + // Outputs. + .Q0 (main_maccore_ethphy_rx_data[2]), + .Q1 (main_maccore_ethphy_rx_data[6]) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX1F_4 of IDDRX1F Module. +//------------------------------------------------------------------------------ +IDDRX1F IDDRX1F_4( + // Inputs. + .D (main_maccore_ethphy_rx_data_delayf[3]), + .SCLK (eth_rx_clk), + + // Outputs. + .Q0 (main_maccore_ethphy_rx_data[3]), + .Q1 (main_maccore_ethphy_rx_data[7]) +); + +endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2024-04-09 14:20:59. +//------------------------------------------------------------------------------ diff --git a/liteeth/generated/nexys-video/liteeth_core.v b/liteeth/generated/nexys-video/liteeth_core.v index 6fd6fb3..1d780a9 100644 --- a/liteeth/generated/nexys-video/liteeth_core.v +++ b/liteeth/generated/nexys-video/liteeth_core.v @@ -1,1010 +1,1361 @@ -//-------------------------------------------------------------------------------- -// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:37:01 -//-------------------------------------------------------------------------------- -module liteeth_core( - input wire sys_clock, - input wire sys_reset, - output wire rgmii_eth_clocks_tx, - input wire rgmii_eth_clocks_rx, - output wire rgmii_eth_rst_n, - input wire rgmii_eth_int_n, - inout wire rgmii_eth_mdio, - output wire rgmii_eth_mdc, - input wire rgmii_eth_rx_ctl, - input wire [3:0] rgmii_eth_rx_data, - output wire rgmii_eth_tx_ctl, - output wire [3:0] rgmii_eth_tx_data, - input wire [29:0] wishbone_adr, - input wire [31:0] wishbone_dat_w, - output wire [31:0] wishbone_dat_r, - input wire [3:0] wishbone_sel, - input wire wishbone_cyc, - input wire wishbone_stb, - output wire wishbone_ack, - input wire wishbone_we, - input wire [2:0] wishbone_cti, - input wire [1:0] wishbone_bte, - output wire wishbone_err, - output wire interrupt +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : liteeth_core.v +// Device : +// LiteX sha1 : 87137c30 +// Date : 2024-04-05 17:38:49 +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ps + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module liteeth_core ( + output wire interrupt, + input wire rgmii_clocks_rx, + output wire rgmii_clocks_tx, + input wire rgmii_int_n, + output wire rgmii_mdc, + inout wire rgmii_mdio, + output wire rgmii_rst_n, + input wire rgmii_rx_ctl, + input wire [3:0] rgmii_rx_data, + output wire rgmii_tx_ctl, + output wire [3:0] rgmii_tx_data, + input wire sys_clock, + input wire sys_reset, + output wire wishbone_ack, + input wire [29:0] wishbone_adr, + input wire [1:0] wishbone_bte, + input wire [2:0] wishbone_cti, + input wire wishbone_cyc, + output wire [31:0] wishbone_dat_r, + input wire [31:0] wishbone_dat_w, + output wire wishbone_err, + input wire [3:0] wishbone_sel, + input wire wishbone_stb, + input wire wishbone_we ); -reg main_maccore_maccore_soc_rst = 1'd0; -wire main_maccore_maccore_cpu_rst; -reg [1:0] main_maccore_maccore_reset_storage = 2'd0; -reg main_maccore_maccore_reset_re = 1'd0; -reg [31:0] main_maccore_maccore_scratch_storage = 32'd305419896; -reg main_maccore_maccore_scratch_re = 1'd0; -wire [31:0] main_maccore_maccore_bus_errors_status; -wire main_maccore_maccore_bus_errors_we; -reg main_maccore_maccore_bus_errors_re = 1'd0; -wire main_maccore_maccore_bus_error; -reg [31:0] main_maccore_maccore_bus_errors = 32'd0; -(* dont_touch = "true" *) wire sys_clk; -wire sys_rst; -wire por_clk; -reg main_maccore_int_rst = 1'd1; -reg main_maccore_ethphy_reset_storage = 1'd0; -reg main_maccore_ethphy_reset_re = 1'd0; -(* dont_touch = "true" *) wire eth_rx_clk; -wire eth_rx_rst; -wire main_maccore_ethphy_eth_rx_clk_ibuf; -(* dont_touch = "true" *) wire eth_tx_clk; -wire eth_tx_rst; -wire eth_tx_delayed_clk; -reg main_maccore_ethphy_reset0 = 1'd0; -reg main_maccore_ethphy_power_down = 1'd0; -wire main_maccore_ethphy_locked; -wire main_maccore_ethphy_clkin; -wire main_maccore_ethphy_clkout0; -wire main_maccore_ethphy_clkout_buf0; -wire main_maccore_ethphy_clkout1; -wire main_maccore_ethphy_clkout_buf1; -wire main_maccore_ethphy_eth_tx_clk_obuf; -wire main_maccore_ethphy_reset1; -wire main_maccore_ethphy_sink_valid; -wire main_maccore_ethphy_sink_ready; -wire main_maccore_ethphy_sink_first; -wire main_maccore_ethphy_sink_last; -wire [7:0] main_maccore_ethphy_sink_payload_data; -wire main_maccore_ethphy_sink_payload_last_be; -wire main_maccore_ethphy_sink_payload_error; -wire main_maccore_ethphy_tx_ctl_obuf; -wire [3:0] main_maccore_ethphy_tx_data_obuf; -reg main_maccore_ethphy_liteethphyrgmiirx_source_valid = 1'd0; -wire main_maccore_ethphy_liteethphyrgmiirx_source_ready; -reg main_maccore_ethphy_liteethphyrgmiirx_source_first = 1'd0; -wire main_maccore_ethphy_liteethphyrgmiirx_source_last; -reg [7:0] main_maccore_ethphy_liteethphyrgmiirx_source_payload_data = 8'd0; -reg main_maccore_ethphy_liteethphyrgmiirx_source_payload_last_be = 1'd0; -reg main_maccore_ethphy_liteethphyrgmiirx_source_payload_error = 1'd0; -wire main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_ibuf; -wire main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_idelay; -wire main_maccore_ethphy_liteethphyrgmiirx_rx_ctl; -wire [3:0] main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf; -wire [3:0] main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay; -wire [7:0] main_maccore_ethphy_liteethphyrgmiirx_rx_data; -wire main_maccore_ethphy_liteethphyrgmiirx; -reg main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_d = 1'd0; -wire main_maccore_ethphy_liteethphyrgmiirx_last; -wire main_maccore_ethphy_mdc; -wire main_maccore_ethphy_oe; -wire main_maccore_ethphy_w; -reg [2:0] main_maccore_ethphy__w_storage = 3'd0; -reg main_maccore_ethphy__w_re = 1'd0; -reg main_maccore_ethphy_r = 1'd0; -reg main_maccore_ethphy__r_status = 1'd0; -wire main_maccore_ethphy__r_we; -reg main_maccore_ethphy__r_re = 1'd0; -wire main_maccore_ethphy_data_w; -wire main_maccore_ethphy_data_oe; -wire main_maccore_ethphy_data_r; -wire main_tx_gap_inserter_sink_valid; -reg main_tx_gap_inserter_sink_ready = 1'd0; -wire main_tx_gap_inserter_sink_first; -wire main_tx_gap_inserter_sink_last; -wire [7:0] main_tx_gap_inserter_sink_payload_data; -wire main_tx_gap_inserter_sink_payload_last_be; -wire main_tx_gap_inserter_sink_payload_error; -reg main_tx_gap_inserter_source_valid = 1'd0; -wire main_tx_gap_inserter_source_ready; -reg main_tx_gap_inserter_source_first = 1'd0; -reg main_tx_gap_inserter_source_last = 1'd0; -reg [7:0] main_tx_gap_inserter_source_payload_data = 8'd0; -reg main_tx_gap_inserter_source_payload_last_be = 1'd0; -reg main_tx_gap_inserter_source_payload_error = 1'd0; -reg [3:0] main_tx_gap_inserter_counter = 4'd0; -reg main_preamble_crc_status = 1'd1; -wire main_preamble_crc_we; -reg main_preamble_crc_re = 1'd0; -reg [31:0] main_preamble_errors_status = 32'd0; -wire main_preamble_errors_we; -reg main_preamble_errors_re = 1'd0; -reg [31:0] main_crc_errors_status = 32'd0; -wire main_crc_errors_we; -reg main_crc_errors_re = 1'd0; -wire main_preamble_inserter_sink_valid; -reg main_preamble_inserter_sink_ready = 1'd0; -wire main_preamble_inserter_sink_first; -wire main_preamble_inserter_sink_last; -wire [7:0] main_preamble_inserter_sink_payload_data; -wire main_preamble_inserter_sink_payload_last_be; -wire main_preamble_inserter_sink_payload_error; -reg main_preamble_inserter_source_valid = 1'd0; -wire main_preamble_inserter_source_ready; -reg main_preamble_inserter_source_first = 1'd0; -reg main_preamble_inserter_source_last = 1'd0; -reg [7:0] main_preamble_inserter_source_payload_data = 8'd0; -wire main_preamble_inserter_source_payload_last_be; -reg main_preamble_inserter_source_payload_error = 1'd0; -reg [63:0] main_preamble_inserter_preamble = 64'd15372286728091293013; -reg [2:0] main_preamble_inserter_count = 3'd0; -wire main_preamble_checker_sink_valid; -reg main_preamble_checker_sink_ready = 1'd0; -wire main_preamble_checker_sink_first; -wire main_preamble_checker_sink_last; -wire [7:0] main_preamble_checker_sink_payload_data; -wire main_preamble_checker_sink_payload_last_be; -wire main_preamble_checker_sink_payload_error; -reg main_preamble_checker_source_valid = 1'd0; -wire main_preamble_checker_source_ready; -reg main_preamble_checker_source_first = 1'd0; -reg main_preamble_checker_source_last = 1'd0; -wire [7:0] main_preamble_checker_source_payload_data; -wire main_preamble_checker_source_payload_last_be; -reg main_preamble_checker_source_payload_error = 1'd0; -reg main_preamble_checker_error = 1'd0; -wire main_liteethmaccrc32inserter_sink_valid; -reg main_liteethmaccrc32inserter_sink_ready = 1'd0; -wire main_liteethmaccrc32inserter_sink_first; -wire main_liteethmaccrc32inserter_sink_last; -wire [7:0] main_liteethmaccrc32inserter_sink_payload_data; -wire main_liteethmaccrc32inserter_sink_payload_last_be; -wire main_liteethmaccrc32inserter_sink_payload_error; -reg main_liteethmaccrc32inserter_source_valid = 1'd0; -wire main_liteethmaccrc32inserter_source_ready; -reg main_liteethmaccrc32inserter_source_first = 1'd0; -reg main_liteethmaccrc32inserter_source_last = 1'd0; -reg [7:0] main_liteethmaccrc32inserter_source_payload_data = 8'd0; -reg main_liteethmaccrc32inserter_source_payload_last_be = 1'd0; -reg main_liteethmaccrc32inserter_source_payload_error = 1'd0; -reg [7:0] main_liteethmaccrc32inserter_data0 = 8'd0; -wire [31:0] main_liteethmaccrc32inserter_value; -wire main_liteethmaccrc32inserter_error; -wire [7:0] main_liteethmaccrc32inserter_data1; -wire [31:0] main_liteethmaccrc32inserter_last; -reg [31:0] main_liteethmaccrc32inserter_next = 32'd0; -reg [31:0] main_liteethmaccrc32inserter_reg = 32'd4294967295; -reg main_liteethmaccrc32inserter_ce = 1'd0; -reg main_liteethmaccrc32inserter_reset = 1'd0; -reg [1:0] main_liteethmaccrc32inserter_cnt = 2'd3; -wire main_liteethmaccrc32inserter_cnt_done; -reg main_liteethmaccrc32inserter_is_ongoing0 = 1'd0; -reg main_liteethmaccrc32inserter_is_ongoing1 = 1'd0; -wire main_crc32_inserter_sink_valid; -wire main_crc32_inserter_sink_ready; -wire main_crc32_inserter_sink_first; -wire main_crc32_inserter_sink_last; -wire [7:0] main_crc32_inserter_sink_payload_data; -wire main_crc32_inserter_sink_payload_last_be; -wire main_crc32_inserter_sink_payload_error; -reg main_crc32_inserter_source_valid = 1'd0; -wire main_crc32_inserter_source_ready; -reg main_crc32_inserter_source_first = 1'd0; -reg main_crc32_inserter_source_last = 1'd0; -reg [7:0] main_crc32_inserter_source_payload_data = 8'd0; -reg main_crc32_inserter_source_payload_last_be = 1'd0; -reg main_crc32_inserter_source_payload_error = 1'd0; -wire main_liteethmaccrc32checker_sink_sink_valid; -reg main_liteethmaccrc32checker_sink_sink_ready = 1'd0; -wire main_liteethmaccrc32checker_sink_sink_first; -wire main_liteethmaccrc32checker_sink_sink_last; -wire [7:0] main_liteethmaccrc32checker_sink_sink_payload_data; -wire main_liteethmaccrc32checker_sink_sink_payload_last_be; -wire main_liteethmaccrc32checker_sink_sink_payload_error; -wire main_liteethmaccrc32checker_source_source_valid; -wire main_liteethmaccrc32checker_source_source_ready; -reg main_liteethmaccrc32checker_source_source_first = 1'd0; -wire main_liteethmaccrc32checker_source_source_last; -wire [7:0] main_liteethmaccrc32checker_source_source_payload_data; -wire main_liteethmaccrc32checker_source_source_payload_last_be; -reg main_liteethmaccrc32checker_source_source_payload_error = 1'd0; -wire main_liteethmaccrc32checker_error; -wire [7:0] main_liteethmaccrc32checker_crc_data0; -wire [31:0] main_liteethmaccrc32checker_crc_value; -wire main_liteethmaccrc32checker_crc_error; -wire [7:0] main_liteethmaccrc32checker_crc_data1; -wire [31:0] main_liteethmaccrc32checker_crc_last; -reg [31:0] main_liteethmaccrc32checker_crc_next = 32'd0; -reg [31:0] main_liteethmaccrc32checker_crc_reg = 32'd4294967295; -reg main_liteethmaccrc32checker_crc_ce = 1'd0; -reg main_liteethmaccrc32checker_crc_reset = 1'd0; -reg main_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; -wire main_liteethmaccrc32checker_syncfifo_sink_ready; -wire main_liteethmaccrc32checker_syncfifo_sink_first; -wire main_liteethmaccrc32checker_syncfifo_sink_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_sink_payload_data; -wire main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; -wire main_liteethmaccrc32checker_syncfifo_sink_payload_error; -wire main_liteethmaccrc32checker_syncfifo_source_valid; -wire main_liteethmaccrc32checker_syncfifo_source_ready; -wire main_liteethmaccrc32checker_syncfifo_source_first; -wire main_liteethmaccrc32checker_syncfifo_source_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_source_payload_data; -wire main_liteethmaccrc32checker_syncfifo_source_payload_last_be; -wire main_liteethmaccrc32checker_syncfifo_source_payload_error; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_we; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_writable; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_re; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_readable; -wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_din; -wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_dout; -reg [2:0] main_liteethmaccrc32checker_syncfifo_level = 3'd0; -reg main_liteethmaccrc32checker_syncfifo_replace = 1'd0; -reg [2:0] main_liteethmaccrc32checker_syncfifo_produce = 3'd0; -reg [2:0] main_liteethmaccrc32checker_syncfifo_consume = 3'd0; -reg [2:0] main_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; -wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_r; -wire main_liteethmaccrc32checker_syncfifo_wrport_we; -wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_w; -wire main_liteethmaccrc32checker_syncfifo_do_read; -wire [2:0] main_liteethmaccrc32checker_syncfifo_rdport_adr; -wire [11:0] main_liteethmaccrc32checker_syncfifo_rdport_dat_r; -wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_first; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_first; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_last; -reg main_liteethmaccrc32checker_fifo_reset = 1'd0; -wire main_liteethmaccrc32checker_fifo_in; -wire main_liteethmaccrc32checker_fifo_out; -wire main_liteethmaccrc32checker_fifo_full; -wire main_crc32_checker_sink_valid; -wire main_crc32_checker_sink_ready; -wire main_crc32_checker_sink_first; -wire main_crc32_checker_sink_last; -wire [7:0] main_crc32_checker_sink_payload_data; -wire main_crc32_checker_sink_payload_last_be; -wire main_crc32_checker_sink_payload_error; -reg main_crc32_checker_source_valid = 1'd0; -wire main_crc32_checker_source_ready; -reg main_crc32_checker_source_first = 1'd0; -reg main_crc32_checker_source_last = 1'd0; -reg [7:0] main_crc32_checker_source_payload_data = 8'd0; -reg main_crc32_checker_source_payload_last_be = 1'd0; -reg main_crc32_checker_source_payload_error = 1'd0; -wire main_ps_preamble_error_i; -wire main_ps_preamble_error_o; -reg main_ps_preamble_error_toggle_i = 1'd0; -wire main_ps_preamble_error_toggle_o; -reg main_ps_preamble_error_toggle_o_r = 1'd0; -wire main_ps_crc_error_i; -wire main_ps_crc_error_o; -reg main_ps_crc_error_toggle_i = 1'd0; -wire main_ps_crc_error_toggle_o; -reg main_ps_crc_error_toggle_o_r = 1'd0; -wire main_padding_inserter_sink_valid; -reg main_padding_inserter_sink_ready = 1'd0; -wire main_padding_inserter_sink_first; -wire main_padding_inserter_sink_last; -wire [7:0] main_padding_inserter_sink_payload_data; -wire main_padding_inserter_sink_payload_last_be; -wire main_padding_inserter_sink_payload_error; -reg main_padding_inserter_source_valid = 1'd0; -wire main_padding_inserter_source_ready; -reg main_padding_inserter_source_first = 1'd0; -reg main_padding_inserter_source_last = 1'd0; -reg [7:0] main_padding_inserter_source_payload_data = 8'd0; -reg main_padding_inserter_source_payload_last_be = 1'd0; -reg main_padding_inserter_source_payload_error = 1'd0; -reg [15:0] main_padding_inserter_counter = 16'd0; -wire main_padding_inserter_counter_done; -wire main_padding_checker_sink_valid; -wire main_padding_checker_sink_ready; -wire main_padding_checker_sink_first; -wire main_padding_checker_sink_last; -wire [7:0] main_padding_checker_sink_payload_data; -wire main_padding_checker_sink_payload_last_be; -wire main_padding_checker_sink_payload_error; -wire main_padding_checker_source_valid; -wire main_padding_checker_source_ready; -wire main_padding_checker_source_first; -wire main_padding_checker_source_last; -wire [7:0] main_padding_checker_source_payload_data; -wire main_padding_checker_source_payload_last_be; -wire main_padding_checker_source_payload_error; -wire main_tx_last_be_sink_valid; -reg main_tx_last_be_sink_ready = 1'd0; -wire main_tx_last_be_sink_first; -wire main_tx_last_be_sink_last; -wire [7:0] main_tx_last_be_sink_payload_data; -wire main_tx_last_be_sink_payload_last_be; -wire main_tx_last_be_sink_payload_error; -reg main_tx_last_be_source_valid = 1'd0; -wire main_tx_last_be_source_ready; -reg main_tx_last_be_source_first = 1'd0; -reg main_tx_last_be_source_last = 1'd0; -reg [7:0] main_tx_last_be_source_payload_data = 8'd0; -reg main_tx_last_be_source_payload_last_be = 1'd0; -reg main_tx_last_be_source_payload_error = 1'd0; -wire main_rx_last_be_sink_valid; -wire main_rx_last_be_sink_ready; -wire main_rx_last_be_sink_first; -wire main_rx_last_be_sink_last; -wire [7:0] main_rx_last_be_sink_payload_data; -wire main_rx_last_be_sink_payload_last_be; -wire main_rx_last_be_sink_payload_error; -wire main_rx_last_be_source_valid; -wire main_rx_last_be_source_ready; -wire main_rx_last_be_source_first; -wire main_rx_last_be_source_last; -wire [7:0] main_rx_last_be_source_payload_data; -reg main_rx_last_be_source_payload_last_be = 1'd0; -wire main_rx_last_be_source_payload_error; -wire main_tx_converter_sink_valid; -wire main_tx_converter_sink_ready; -wire main_tx_converter_sink_first; -wire main_tx_converter_sink_last; -wire [31:0] main_tx_converter_sink_payload_data; -wire [3:0] main_tx_converter_sink_payload_last_be; -wire [3:0] main_tx_converter_sink_payload_error; -wire main_tx_converter_source_valid; -wire main_tx_converter_source_ready; -wire main_tx_converter_source_first; -wire main_tx_converter_source_last; -wire [7:0] main_tx_converter_source_payload_data; -wire main_tx_converter_source_payload_last_be; -wire main_tx_converter_source_payload_error; -wire main_tx_converter_converter_sink_valid; -wire main_tx_converter_converter_sink_ready; -wire main_tx_converter_converter_sink_first; -wire main_tx_converter_converter_sink_last; -reg [39:0] main_tx_converter_converter_sink_payload_data = 40'd0; -wire main_tx_converter_converter_source_valid; -wire main_tx_converter_converter_source_ready; -wire main_tx_converter_converter_source_first; -wire main_tx_converter_converter_source_last; -reg [9:0] main_tx_converter_converter_source_payload_data = 10'd0; -wire main_tx_converter_converter_source_payload_valid_token_count; -reg [1:0] main_tx_converter_converter_mux = 2'd0; -wire main_tx_converter_converter_first; -wire main_tx_converter_converter_last; -wire main_tx_converter_source_source_valid; -wire main_tx_converter_source_source_ready; -wire main_tx_converter_source_source_first; -wire main_tx_converter_source_source_last; -wire [9:0] main_tx_converter_source_source_payload_data; -wire main_rx_converter_sink_valid; -wire main_rx_converter_sink_ready; -wire main_rx_converter_sink_first; -wire main_rx_converter_sink_last; -wire [7:0] main_rx_converter_sink_payload_data; -wire main_rx_converter_sink_payload_last_be; -wire main_rx_converter_sink_payload_error; -wire main_rx_converter_source_valid; -wire main_rx_converter_source_ready; -wire main_rx_converter_source_first; -wire main_rx_converter_source_last; -reg [31:0] main_rx_converter_source_payload_data = 32'd0; -reg [3:0] main_rx_converter_source_payload_last_be = 4'd0; -reg [3:0] main_rx_converter_source_payload_error = 4'd0; -wire main_rx_converter_converter_sink_valid; -wire main_rx_converter_converter_sink_ready; -wire main_rx_converter_converter_sink_first; -wire main_rx_converter_converter_sink_last; -wire [9:0] main_rx_converter_converter_sink_payload_data; -wire main_rx_converter_converter_source_valid; -wire main_rx_converter_converter_source_ready; -reg main_rx_converter_converter_source_first = 1'd0; -reg main_rx_converter_converter_source_last = 1'd0; -reg [39:0] main_rx_converter_converter_source_payload_data = 40'd0; -reg [2:0] main_rx_converter_converter_source_payload_valid_token_count = 3'd0; -reg [1:0] main_rx_converter_converter_demux = 2'd0; -wire main_rx_converter_converter_load_part; -reg main_rx_converter_converter_strobe_all = 1'd0; -wire main_rx_converter_source_source_valid; -wire main_rx_converter_source_source_ready; -wire main_rx_converter_source_source_first; -wire main_rx_converter_source_source_last; -wire [39:0] main_rx_converter_source_source_payload_data; -wire main_tx_cdc_sink_sink_valid; -wire main_tx_cdc_sink_sink_ready; -wire main_tx_cdc_sink_sink_first; -wire main_tx_cdc_sink_sink_last; -wire [31:0] main_tx_cdc_sink_sink_payload_data; -wire [3:0] main_tx_cdc_sink_sink_payload_last_be; -wire [3:0] main_tx_cdc_sink_sink_payload_error; -wire main_tx_cdc_source_source_valid; -wire main_tx_cdc_source_source_ready; -wire main_tx_cdc_source_source_first; -wire main_tx_cdc_source_source_last; -wire [31:0] main_tx_cdc_source_source_payload_data; -wire [3:0] main_tx_cdc_source_source_payload_last_be; -wire [3:0] main_tx_cdc_source_source_payload_error; -wire main_tx_cdc_cdc_sink_valid; -wire main_tx_cdc_cdc_sink_ready; -wire main_tx_cdc_cdc_sink_first; -wire main_tx_cdc_cdc_sink_last; -wire [31:0] main_tx_cdc_cdc_sink_payload_data; -wire [3:0] main_tx_cdc_cdc_sink_payload_last_be; -wire [3:0] main_tx_cdc_cdc_sink_payload_error; -wire main_tx_cdc_cdc_source_valid; -wire main_tx_cdc_cdc_source_ready; -wire main_tx_cdc_cdc_source_first; -wire main_tx_cdc_cdc_source_last; -wire [31:0] main_tx_cdc_cdc_source_payload_data; -wire [3:0] main_tx_cdc_cdc_source_payload_last_be; -wire [3:0] main_tx_cdc_cdc_source_payload_error; -wire main_tx_cdc_cdc_asyncfifo_we; -wire main_tx_cdc_cdc_asyncfifo_writable; -wire main_tx_cdc_cdc_asyncfifo_re; -wire main_tx_cdc_cdc_asyncfifo_readable; -wire [41:0] main_tx_cdc_cdc_asyncfifo_din; -wire [41:0] main_tx_cdc_cdc_asyncfifo_dout; -wire main_tx_cdc_cdc_graycounter0_ce; -(* dont_touch = "true" *) reg [5:0] main_tx_cdc_cdc_graycounter0_q = 6'd0; -wire [5:0] main_tx_cdc_cdc_graycounter0_q_next; -reg [5:0] main_tx_cdc_cdc_graycounter0_q_binary = 6'd0; -reg [5:0] main_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; -wire main_tx_cdc_cdc_graycounter1_ce; -(* dont_touch = "true" *) reg [5:0] main_tx_cdc_cdc_graycounter1_q = 6'd0; -wire [5:0] main_tx_cdc_cdc_graycounter1_q_next; -reg [5:0] main_tx_cdc_cdc_graycounter1_q_binary = 6'd0; -reg [5:0] main_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; -wire [5:0] main_tx_cdc_cdc_produce_rdomain; -wire [5:0] main_tx_cdc_cdc_consume_wdomain; -wire [4:0] main_tx_cdc_cdc_wrport_adr; -wire [41:0] main_tx_cdc_cdc_wrport_dat_r; -wire main_tx_cdc_cdc_wrport_we; -wire [41:0] main_tx_cdc_cdc_wrport_dat_w; -wire [4:0] main_tx_cdc_cdc_rdport_adr; -wire [41:0] main_tx_cdc_cdc_rdport_dat_r; -wire [31:0] main_tx_cdc_cdc_fifo_in_payload_data; -wire [3:0] main_tx_cdc_cdc_fifo_in_payload_last_be; -wire [3:0] main_tx_cdc_cdc_fifo_in_payload_error; -wire main_tx_cdc_cdc_fifo_in_first; -wire main_tx_cdc_cdc_fifo_in_last; -wire [31:0] main_tx_cdc_cdc_fifo_out_payload_data; -wire [3:0] main_tx_cdc_cdc_fifo_out_payload_last_be; -wire [3:0] main_tx_cdc_cdc_fifo_out_payload_error; -wire main_tx_cdc_cdc_fifo_out_first; -wire main_tx_cdc_cdc_fifo_out_last; -wire main_rx_cdc_sink_sink_valid; -wire main_rx_cdc_sink_sink_ready; -wire main_rx_cdc_sink_sink_first; -wire main_rx_cdc_sink_sink_last; -wire [31:0] main_rx_cdc_sink_sink_payload_data; -wire [3:0] main_rx_cdc_sink_sink_payload_last_be; -wire [3:0] main_rx_cdc_sink_sink_payload_error; -wire main_rx_cdc_source_source_valid; -wire main_rx_cdc_source_source_ready; -wire main_rx_cdc_source_source_first; -wire main_rx_cdc_source_source_last; -wire [31:0] main_rx_cdc_source_source_payload_data; -wire [3:0] main_rx_cdc_source_source_payload_last_be; -wire [3:0] main_rx_cdc_source_source_payload_error; -wire main_rx_cdc_cdc_sink_valid; -wire main_rx_cdc_cdc_sink_ready; -wire main_rx_cdc_cdc_sink_first; -wire main_rx_cdc_cdc_sink_last; -wire [31:0] main_rx_cdc_cdc_sink_payload_data; -wire [3:0] main_rx_cdc_cdc_sink_payload_last_be; -wire [3:0] main_rx_cdc_cdc_sink_payload_error; -wire main_rx_cdc_cdc_source_valid; -wire main_rx_cdc_cdc_source_ready; -wire main_rx_cdc_cdc_source_first; -wire main_rx_cdc_cdc_source_last; -wire [31:0] main_rx_cdc_cdc_source_payload_data; -wire [3:0] main_rx_cdc_cdc_source_payload_last_be; -wire [3:0] main_rx_cdc_cdc_source_payload_error; -wire main_rx_cdc_cdc_asyncfifo_we; -wire main_rx_cdc_cdc_asyncfifo_writable; -wire main_rx_cdc_cdc_asyncfifo_re; -wire main_rx_cdc_cdc_asyncfifo_readable; -wire [41:0] main_rx_cdc_cdc_asyncfifo_din; -wire [41:0] main_rx_cdc_cdc_asyncfifo_dout; -wire main_rx_cdc_cdc_graycounter0_ce; -(* dont_touch = "true" *) reg [5:0] main_rx_cdc_cdc_graycounter0_q = 6'd0; -wire [5:0] main_rx_cdc_cdc_graycounter0_q_next; -reg [5:0] main_rx_cdc_cdc_graycounter0_q_binary = 6'd0; -reg [5:0] main_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; -wire main_rx_cdc_cdc_graycounter1_ce; -(* dont_touch = "true" *) reg [5:0] main_rx_cdc_cdc_graycounter1_q = 6'd0; -wire [5:0] main_rx_cdc_cdc_graycounter1_q_next; -reg [5:0] main_rx_cdc_cdc_graycounter1_q_binary = 6'd0; -reg [5:0] main_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; -wire [5:0] main_rx_cdc_cdc_produce_rdomain; -wire [5:0] main_rx_cdc_cdc_consume_wdomain; -wire [4:0] main_rx_cdc_cdc_wrport_adr; -wire [41:0] main_rx_cdc_cdc_wrport_dat_r; -wire main_rx_cdc_cdc_wrport_we; -wire [41:0] main_rx_cdc_cdc_wrport_dat_w; -wire [4:0] main_rx_cdc_cdc_rdport_adr; -wire [41:0] main_rx_cdc_cdc_rdport_dat_r; -wire [31:0] main_rx_cdc_cdc_fifo_in_payload_data; -wire [3:0] main_rx_cdc_cdc_fifo_in_payload_last_be; -wire [3:0] main_rx_cdc_cdc_fifo_in_payload_error; -wire main_rx_cdc_cdc_fifo_in_first; -wire main_rx_cdc_cdc_fifo_in_last; -wire [31:0] main_rx_cdc_cdc_fifo_out_payload_data; -wire [3:0] main_rx_cdc_cdc_fifo_out_payload_last_be; -wire [3:0] main_rx_cdc_cdc_fifo_out_payload_error; -wire main_rx_cdc_cdc_fifo_out_first; -wire main_rx_cdc_cdc_fifo_out_last; -wire main_sink_valid; -wire main_sink_ready; -wire main_sink_first; -wire main_sink_last; -wire [31:0] main_sink_payload_data; -wire [3:0] main_sink_payload_last_be; -wire [3:0] main_sink_payload_error; -wire main_source_valid; -wire main_source_ready; -wire main_source_first; -wire main_source_last; -wire [31:0] main_source_payload_data; -wire [3:0] main_source_payload_last_be; -wire [3:0] main_source_payload_error; -wire [29:0] main_bus_adr; -wire [31:0] main_bus_dat_w; -wire [31:0] main_bus_dat_r; -wire [3:0] main_bus_sel; -wire main_bus_cyc; -wire main_bus_stb; -wire main_bus_ack; -wire main_bus_we; -wire [2:0] main_bus_cti; -wire [1:0] main_bus_bte; -wire main_bus_err; -wire main_writer_sink_sink_valid; -reg main_writer_sink_sink_ready = 1'd1; -wire main_writer_sink_sink_first; -wire main_writer_sink_sink_last; -wire [31:0] main_writer_sink_sink_payload_data; -wire [3:0] main_writer_sink_sink_payload_last_be; -wire [3:0] main_writer_sink_sink_payload_error; -wire main_writer_slot_status; -wire main_writer_slot_we; -reg main_writer_slot_re = 1'd0; -wire [31:0] main_writer_length_status; -wire main_writer_length_we; -reg main_writer_length_re = 1'd0; -reg [31:0] main_writer_errors_status = 32'd0; -wire main_writer_errors_we; -reg main_writer_errors_re = 1'd0; -wire main_writer_irq; -wire main_writer_available_status; -wire main_writer_available_pending; -wire main_writer_available_trigger; -reg main_writer_available_clear = 1'd0; -wire main_writer_available0; -wire main_writer_status_status; -wire main_writer_status_we; -reg main_writer_status_re = 1'd0; -wire main_writer_available1; -wire main_writer_pending_status; -wire main_writer_pending_we; -reg main_writer_pending_re = 1'd0; -reg main_writer_pending_r = 1'd0; -wire main_writer_available2; -reg main_writer_enable_storage = 1'd0; -reg main_writer_enable_re = 1'd0; -reg [2:0] main_writer_inc = 3'd0; -reg [31:0] main_writer_counter = 32'd0; -reg main_writer_slot = 1'd0; -reg main_writer_slot_ce = 1'd0; -reg main_writer_start = 1'd0; -reg main_writer_ongoing = 1'd0; -reg main_writer_stat_fifo_sink_valid = 1'd0; -wire main_writer_stat_fifo_sink_ready; -reg main_writer_stat_fifo_sink_first = 1'd0; -reg main_writer_stat_fifo_sink_last = 1'd0; -wire main_writer_stat_fifo_sink_payload_slot; -wire [31:0] main_writer_stat_fifo_sink_payload_length; -wire main_writer_stat_fifo_source_valid; -wire main_writer_stat_fifo_source_ready; -wire main_writer_stat_fifo_source_first; -wire main_writer_stat_fifo_source_last; -wire main_writer_stat_fifo_source_payload_slot; -wire [31:0] main_writer_stat_fifo_source_payload_length; -wire main_writer_stat_fifo_syncfifo_we; -wire main_writer_stat_fifo_syncfifo_writable; -wire main_writer_stat_fifo_syncfifo_re; -wire main_writer_stat_fifo_syncfifo_readable; -wire [34:0] main_writer_stat_fifo_syncfifo_din; -wire [34:0] main_writer_stat_fifo_syncfifo_dout; -reg [1:0] main_writer_stat_fifo_level = 2'd0; -reg main_writer_stat_fifo_replace = 1'd0; -reg main_writer_stat_fifo_produce = 1'd0; -reg main_writer_stat_fifo_consume = 1'd0; -reg main_writer_stat_fifo_wrport_adr = 1'd0; -wire [34:0] main_writer_stat_fifo_wrport_dat_r; -wire main_writer_stat_fifo_wrport_we; -wire [34:0] main_writer_stat_fifo_wrport_dat_w; -wire main_writer_stat_fifo_do_read; -wire main_writer_stat_fifo_rdport_adr; -wire [34:0] main_writer_stat_fifo_rdport_dat_r; -wire main_writer_stat_fifo_fifo_in_payload_slot; -wire [31:0] main_writer_stat_fifo_fifo_in_payload_length; -wire main_writer_stat_fifo_fifo_in_first; -wire main_writer_stat_fifo_fifo_in_last; -wire main_writer_stat_fifo_fifo_out_payload_slot; -wire [31:0] main_writer_stat_fifo_fifo_out_payload_length; -wire main_writer_stat_fifo_fifo_out_first; -wire main_writer_stat_fifo_fifo_out_last; -reg [8:0] main_writer_memory0_adr = 9'd0; -wire [31:0] main_writer_memory0_dat_r; -reg main_writer_memory0_we = 1'd0; -reg [31:0] main_writer_memory0_dat_w = 32'd0; -reg [8:0] main_writer_memory1_adr = 9'd0; -wire [31:0] main_writer_memory1_dat_r; -reg main_writer_memory1_we = 1'd0; -reg [31:0] main_writer_memory1_dat_w = 32'd0; -reg main_reader_source_source_valid = 1'd0; -wire main_reader_source_source_ready; -reg main_reader_source_source_first = 1'd0; -reg main_reader_source_source_last = 1'd0; -reg [31:0] main_reader_source_source_payload_data = 32'd0; -reg [3:0] main_reader_source_source_payload_last_be = 4'd0; -reg [3:0] main_reader_source_source_payload_error = 4'd0; -reg main_reader_start_start_re = 1'd0; -wire main_reader_start_start_r; -reg main_reader_start_start_we = 1'd0; -reg main_reader_start_start_w = 1'd0; -wire main_reader_ready_status; -wire main_reader_ready_we; -reg main_reader_ready_re = 1'd0; -wire [1:0] main_reader_level_status; -wire main_reader_level_we; -reg main_reader_level_re = 1'd0; -reg main_reader_slot_storage = 1'd0; -reg main_reader_slot_re = 1'd0; -reg [10:0] main_reader_length_storage = 11'd0; -reg main_reader_length_re = 1'd0; -wire main_reader_irq; -wire main_reader_eventsourcepulse_status; -reg main_reader_eventsourcepulse_pending = 1'd0; -reg main_reader_eventsourcepulse_trigger = 1'd0; -reg main_reader_eventsourcepulse_clear = 1'd0; -wire main_reader_event00; -wire main_reader_status_status; -wire main_reader_status_we; -reg main_reader_status_re = 1'd0; -wire main_reader_event01; -wire main_reader_pending_status; -wire main_reader_pending_we; -reg main_reader_pending_re = 1'd0; -reg main_reader_pending_r = 1'd0; -wire main_reader_event02; -reg main_reader_enable_storage = 1'd0; -reg main_reader_enable_re = 1'd0; -reg main_reader_start = 1'd0; -wire main_reader_cmd_fifo_sink_valid; -wire main_reader_cmd_fifo_sink_ready; -reg main_reader_cmd_fifo_sink_first = 1'd0; -reg main_reader_cmd_fifo_sink_last = 1'd0; -wire main_reader_cmd_fifo_sink_payload_slot; -wire [10:0] main_reader_cmd_fifo_sink_payload_length; -wire main_reader_cmd_fifo_source_valid; -reg main_reader_cmd_fifo_source_ready = 1'd0; -wire main_reader_cmd_fifo_source_first; -wire main_reader_cmd_fifo_source_last; -wire main_reader_cmd_fifo_source_payload_slot; -wire [10:0] main_reader_cmd_fifo_source_payload_length; -wire main_reader_cmd_fifo_syncfifo_we; -wire main_reader_cmd_fifo_syncfifo_writable; -wire main_reader_cmd_fifo_syncfifo_re; -wire main_reader_cmd_fifo_syncfifo_readable; -wire [13:0] main_reader_cmd_fifo_syncfifo_din; -wire [13:0] main_reader_cmd_fifo_syncfifo_dout; -reg [1:0] main_reader_cmd_fifo_level = 2'd0; -reg main_reader_cmd_fifo_replace = 1'd0; -reg main_reader_cmd_fifo_produce = 1'd0; -reg main_reader_cmd_fifo_consume = 1'd0; -reg main_reader_cmd_fifo_wrport_adr = 1'd0; -wire [13:0] main_reader_cmd_fifo_wrport_dat_r; -wire main_reader_cmd_fifo_wrport_we; -wire [13:0] main_reader_cmd_fifo_wrport_dat_w; -wire main_reader_cmd_fifo_do_read; -wire main_reader_cmd_fifo_rdport_adr; -wire [13:0] main_reader_cmd_fifo_rdport_dat_r; -wire main_reader_cmd_fifo_fifo_in_payload_slot; -wire [10:0] main_reader_cmd_fifo_fifo_in_payload_length; -wire main_reader_cmd_fifo_fifo_in_first; -wire main_reader_cmd_fifo_fifo_in_last; -wire main_reader_cmd_fifo_fifo_out_payload_slot; -wire [10:0] main_reader_cmd_fifo_fifo_out_payload_length; -wire main_reader_cmd_fifo_fifo_out_first; -wire main_reader_cmd_fifo_fifo_out_last; -reg [10:0] main_reader_read_address = 11'd0; -reg [10:0] main_reader_counter = 11'd0; -wire [8:0] main_reader_memory0_adr; -wire [31:0] main_reader_memory0_dat_r; -wire [8:0] main_reader_memory1_adr; -wire [31:0] main_reader_memory1_dat_r; -wire main_ev_irq; -wire [29:0] main_sram0_bus_adr0; -wire [31:0] main_sram0_bus_dat_w0; -wire [31:0] main_sram0_bus_dat_r0; -wire [3:0] main_sram0_bus_sel0; -wire main_sram0_bus_cyc0; -wire main_sram0_bus_stb0; -reg main_sram0_bus_ack0 = 1'd0; -wire main_sram0_bus_we0; -wire [2:0] main_sram0_bus_cti0; -wire [1:0] main_sram0_bus_bte0; -reg main_sram0_bus_err0 = 1'd0; -wire [8:0] main_sram0_adr0; -wire [31:0] main_sram0_dat_r0; -wire [29:0] main_sram1_bus_adr0; -wire [31:0] main_sram1_bus_dat_w0; -wire [31:0] main_sram1_bus_dat_r0; -wire [3:0] main_sram1_bus_sel0; -wire main_sram1_bus_cyc0; -wire main_sram1_bus_stb0; -reg main_sram1_bus_ack0 = 1'd0; -wire main_sram1_bus_we0; -wire [2:0] main_sram1_bus_cti0; -wire [1:0] main_sram1_bus_bte0; -reg main_sram1_bus_err0 = 1'd0; -wire [8:0] main_sram1_adr0; -wire [31:0] main_sram1_dat_r0; -wire [29:0] main_sram0_bus_adr1; -wire [31:0] main_sram0_bus_dat_w1; -wire [31:0] main_sram0_bus_dat_r1; -wire [3:0] main_sram0_bus_sel1; -wire main_sram0_bus_cyc1; -wire main_sram0_bus_stb1; -reg main_sram0_bus_ack1 = 1'd0; -wire main_sram0_bus_we1; -wire [2:0] main_sram0_bus_cti1; -wire [1:0] main_sram0_bus_bte1; -reg main_sram0_bus_err1 = 1'd0; -wire [8:0] main_sram0_adr1; -wire [31:0] main_sram0_dat_r1; -reg [3:0] main_sram0_we = 4'd0; -wire [31:0] main_sram0_dat_w; -wire [29:0] main_sram1_bus_adr1; -wire [31:0] main_sram1_bus_dat_w1; -wire [31:0] main_sram1_bus_dat_r1; -wire [3:0] main_sram1_bus_sel1; -wire main_sram1_bus_cyc1; -wire main_sram1_bus_stb1; -reg main_sram1_bus_ack1 = 1'd0; -wire main_sram1_bus_we1; -wire [2:0] main_sram1_bus_cti1; -wire [1:0] main_sram1_bus_bte1; -reg main_sram1_bus_err1 = 1'd0; -wire [8:0] main_sram1_adr1; -wire [31:0] main_sram1_dat_r1; -reg [3:0] main_sram1_we = 4'd0; -wire [31:0] main_sram1_dat_w; -reg [3:0] main_slave_sel = 4'd0; -reg [3:0] main_slave_sel_r = 4'd0; -wire [29:0] main_wb_bus_adr; -wire [31:0] main_wb_bus_dat_w; -wire [31:0] main_wb_bus_dat_r; -wire [3:0] main_wb_bus_sel; -wire main_wb_bus_cyc; -wire main_wb_bus_stb; -wire main_wb_bus_ack; -wire main_wb_bus_we; -wire [2:0] main_wb_bus_cti; -wire [1:0] main_wb_bus_bte; -wire main_wb_bus_err; -wire builder_reset0; -wire builder_reset1; -wire builder_reset2; -wire builder_reset3; -wire builder_reset4; -wire builder_reset5; -wire builder_reset6; -wire builder_reset7; -wire builder_pll_fb; -reg builder_liteethmacgap_state = 1'd0; -reg builder_liteethmacgap_next_state = 1'd0; -reg [3:0] main_tx_gap_inserter_counter_liteethmacgap_next_value = 4'd0; -reg main_tx_gap_inserter_counter_liteethmacgap_next_value_ce = 1'd0; -reg [1:0] builder_liteethmacpreambleinserter_state = 2'd0; -reg [1:0] builder_liteethmacpreambleinserter_next_state = 2'd0; -reg [2:0] main_preamble_inserter_count_liteethmacpreambleinserter_next_value = 3'd0; -reg main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce = 1'd0; -reg builder_liteethmacpreamblechecker_state = 1'd0; -reg builder_liteethmacpreamblechecker_next_state = 1'd0; -reg [1:0] builder_liteethmaccrc32inserter_state = 2'd0; -reg [1:0] builder_liteethmaccrc32inserter_next_state = 2'd0; -reg [1:0] builder_liteethmaccrc32checker_state = 2'd0; -reg [1:0] builder_liteethmaccrc32checker_next_state = 2'd0; -reg builder_liteethmacpaddinginserter_state = 1'd0; -reg builder_liteethmacpaddinginserter_next_state = 1'd0; -reg [15:0] main_padding_inserter_counter_liteethmacpaddinginserter_next_value = 16'd0; -reg main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce = 1'd0; -reg builder_liteethmactxlastbe_state = 1'd0; -reg builder_liteethmactxlastbe_next_state = 1'd0; -reg [2:0] builder_liteethmacsramwriter_state = 3'd0; -reg [2:0] builder_liteethmacsramwriter_next_state = 3'd0; -reg [31:0] main_writer_counter_t_next_value = 32'd0; -reg main_writer_counter_t_next_value_ce = 1'd0; -reg [31:0] main_writer_errors_status_f_next_value = 32'd0; -reg main_writer_errors_status_f_next_value_ce = 1'd0; -reg [1:0] builder_liteethmacsramreader_state = 2'd0; -reg [1:0] builder_liteethmacsramreader_next_state = 2'd0; -reg [10:0] main_reader_counter_next_value = 11'd0; -reg main_reader_counter_next_value_ce = 1'd0; -reg [13:0] builder_maccore_adr = 14'd0; -reg builder_maccore_we = 1'd0; -reg [31:0] builder_maccore_dat_w = 32'd0; -wire [31:0] builder_maccore_dat_r; -wire [29:0] builder_maccore_wishbone_adr; -wire [31:0] builder_maccore_wishbone_dat_w; -reg [31:0] builder_maccore_wishbone_dat_r = 32'd0; -wire [3:0] builder_maccore_wishbone_sel; -wire builder_maccore_wishbone_cyc; -wire builder_maccore_wishbone_stb; -reg builder_maccore_wishbone_ack = 1'd0; -wire builder_maccore_wishbone_we; -wire [2:0] builder_maccore_wishbone_cti; -wire [1:0] builder_maccore_wishbone_bte; -reg builder_maccore_wishbone_err = 1'd0; -wire [29:0] builder_shared_adr; -wire [31:0] builder_shared_dat_w; -reg [31:0] builder_shared_dat_r = 32'd0; -wire [3:0] builder_shared_sel; -wire builder_shared_cyc; -wire builder_shared_stb; -reg builder_shared_ack = 1'd0; -wire builder_shared_we; -wire [2:0] builder_shared_cti; -wire [1:0] builder_shared_bte; -wire builder_shared_err; -wire builder_request; -wire builder_grant; -reg [1:0] builder_slave_sel = 2'd0; -reg [1:0] builder_slave_sel_r = 2'd0; -reg builder_error = 1'd0; -wire builder_wait; -wire builder_done; -reg [19:0] builder_count = 20'd1000000; -wire [13:0] builder_interface0_bank_bus_adr; -wire builder_interface0_bank_bus_we; -wire [31:0] builder_interface0_bank_bus_dat_w; -reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; -reg builder_csrbank0_reset0_re = 1'd0; -wire [1:0] builder_csrbank0_reset0_r; -reg builder_csrbank0_reset0_we = 1'd0; -wire [1:0] builder_csrbank0_reset0_w; -reg builder_csrbank0_scratch0_re = 1'd0; -wire [31:0] builder_csrbank0_scratch0_r; -reg builder_csrbank0_scratch0_we = 1'd0; -wire [31:0] builder_csrbank0_scratch0_w; -reg builder_csrbank0_bus_errors_re = 1'd0; -wire [31:0] builder_csrbank0_bus_errors_r; -reg builder_csrbank0_bus_errors_we = 1'd0; -wire [31:0] builder_csrbank0_bus_errors_w; -wire builder_csrbank0_sel; -wire [13:0] builder_interface1_bank_bus_adr; -wire builder_interface1_bank_bus_we; -wire [31:0] builder_interface1_bank_bus_dat_w; -reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; -reg builder_csrbank1_sram_writer_slot_re = 1'd0; -wire builder_csrbank1_sram_writer_slot_r; -reg builder_csrbank1_sram_writer_slot_we = 1'd0; -wire builder_csrbank1_sram_writer_slot_w; -reg builder_csrbank1_sram_writer_length_re = 1'd0; -wire [31:0] builder_csrbank1_sram_writer_length_r; -reg builder_csrbank1_sram_writer_length_we = 1'd0; -wire [31:0] builder_csrbank1_sram_writer_length_w; -reg builder_csrbank1_sram_writer_errors_re = 1'd0; -wire [31:0] builder_csrbank1_sram_writer_errors_r; -reg builder_csrbank1_sram_writer_errors_we = 1'd0; -wire [31:0] builder_csrbank1_sram_writer_errors_w; -reg builder_csrbank1_sram_writer_ev_status_re = 1'd0; -wire builder_csrbank1_sram_writer_ev_status_r; -reg builder_csrbank1_sram_writer_ev_status_we = 1'd0; -wire builder_csrbank1_sram_writer_ev_status_w; -reg builder_csrbank1_sram_writer_ev_pending_re = 1'd0; -wire builder_csrbank1_sram_writer_ev_pending_r; -reg builder_csrbank1_sram_writer_ev_pending_we = 1'd0; -wire builder_csrbank1_sram_writer_ev_pending_w; -reg builder_csrbank1_sram_writer_ev_enable0_re = 1'd0; -wire builder_csrbank1_sram_writer_ev_enable0_r; -reg builder_csrbank1_sram_writer_ev_enable0_we = 1'd0; -wire builder_csrbank1_sram_writer_ev_enable0_w; -reg builder_csrbank1_sram_reader_ready_re = 1'd0; -wire builder_csrbank1_sram_reader_ready_r; -reg builder_csrbank1_sram_reader_ready_we = 1'd0; -wire builder_csrbank1_sram_reader_ready_w; -reg builder_csrbank1_sram_reader_level_re = 1'd0; -wire [1:0] builder_csrbank1_sram_reader_level_r; -reg builder_csrbank1_sram_reader_level_we = 1'd0; -wire [1:0] builder_csrbank1_sram_reader_level_w; -reg builder_csrbank1_sram_reader_slot0_re = 1'd0; -wire builder_csrbank1_sram_reader_slot0_r; -reg builder_csrbank1_sram_reader_slot0_we = 1'd0; -wire builder_csrbank1_sram_reader_slot0_w; -reg builder_csrbank1_sram_reader_length0_re = 1'd0; -wire [10:0] builder_csrbank1_sram_reader_length0_r; -reg builder_csrbank1_sram_reader_length0_we = 1'd0; -wire [10:0] builder_csrbank1_sram_reader_length0_w; -reg builder_csrbank1_sram_reader_ev_status_re = 1'd0; -wire builder_csrbank1_sram_reader_ev_status_r; -reg builder_csrbank1_sram_reader_ev_status_we = 1'd0; -wire builder_csrbank1_sram_reader_ev_status_w; -reg builder_csrbank1_sram_reader_ev_pending_re = 1'd0; -wire builder_csrbank1_sram_reader_ev_pending_r; -reg builder_csrbank1_sram_reader_ev_pending_we = 1'd0; -wire builder_csrbank1_sram_reader_ev_pending_w; -reg builder_csrbank1_sram_reader_ev_enable0_re = 1'd0; -wire builder_csrbank1_sram_reader_ev_enable0_r; -reg builder_csrbank1_sram_reader_ev_enable0_we = 1'd0; -wire builder_csrbank1_sram_reader_ev_enable0_w; -reg builder_csrbank1_preamble_crc_re = 1'd0; -wire builder_csrbank1_preamble_crc_r; -reg builder_csrbank1_preamble_crc_we = 1'd0; -wire builder_csrbank1_preamble_crc_w; -reg builder_csrbank1_preamble_errors_re = 1'd0; -wire [31:0] builder_csrbank1_preamble_errors_r; -reg builder_csrbank1_preamble_errors_we = 1'd0; -wire [31:0] builder_csrbank1_preamble_errors_w; -reg builder_csrbank1_crc_errors_re = 1'd0; -wire [31:0] builder_csrbank1_crc_errors_r; -reg builder_csrbank1_crc_errors_we = 1'd0; -wire [31:0] builder_csrbank1_crc_errors_w; -wire builder_csrbank1_sel; -wire [13:0] builder_interface2_bank_bus_adr; -wire builder_interface2_bank_bus_we; -wire [31:0] builder_interface2_bank_bus_dat_w; -reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; -reg builder_csrbank2_crg_reset0_re = 1'd0; -wire builder_csrbank2_crg_reset0_r; -reg builder_csrbank2_crg_reset0_we = 1'd0; -wire builder_csrbank2_crg_reset0_w; -reg builder_csrbank2_mdio_w0_re = 1'd0; -wire [2:0] builder_csrbank2_mdio_w0_r; -reg builder_csrbank2_mdio_w0_we = 1'd0; -wire [2:0] builder_csrbank2_mdio_w0_w; -reg builder_csrbank2_mdio_r_re = 1'd0; -wire builder_csrbank2_mdio_r_r; -reg builder_csrbank2_mdio_r_we = 1'd0; -wire builder_csrbank2_mdio_r_w; -wire builder_csrbank2_sel; -wire [13:0] builder_csr_interconnect_adr; -wire builder_csr_interconnect_we; -wire [31:0] builder_csr_interconnect_dat_w; -wire [31:0] builder_csr_interconnect_dat_r; -reg builder_state = 1'd0; -reg builder_next_state = 1'd0; -reg [29:0] builder_array_muxed0 = 30'd0; -reg [31:0] builder_array_muxed1 = 32'd0; -reg [3:0] builder_array_muxed2 = 4'd0; -reg builder_array_muxed3 = 1'd0; -reg builder_array_muxed4 = 1'd0; -reg builder_array_muxed5 = 1'd0; -reg [2:0] builder_array_muxed6 = 3'd0; -reg [1:0] builder_array_muxed7 = 2'd0; -wire builder_xilinxasyncresetsynchronizerimpl0; -wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; -wire builder_xilinxasyncresetsynchronizerimpl0_expr; -wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta; -wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl0_regs0 = 1'd0; -(* async_reg = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl0_regs1 = 1'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl1_regs0 = 1'd0; -(* async_reg = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl1_regs1 = 1'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl2_regs0 = 1'd0; -(* async_reg = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl2_regs1 = 1'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl3_regs0 = 6'd0; -(* async_reg = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl3_regs1 = 6'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl4_regs0 = 6'd0; -(* async_reg = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl4_regs1 = 6'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl5_regs0 = 6'd0; -(* async_reg = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl5_regs1 = 6'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl6_regs0 = 6'd0; -(* async_reg = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl6_regs1 = 6'd0; + +//------------------------------------------------------------------------------ +// Hierarchy +//------------------------------------------------------------------------------ + +/* +MACCore +└─── bus (SoCBusHandler) +│ └─── _interconnect (InterconnectShared) +│ │ └─── arbiter (Arbiter) +│ │ │ └─── rr (RoundRobin) +│ │ └─── decoder (Decoder) +│ │ └─── timeout (Timeout) +│ │ │ └─── waittimer_0* (WaitTimer) +└─── csr (SoCCSRHandler) +└─── irq (SoCIRQHandler) +└─── ctrl (SoCController) +└─── cpu (CPUNone) +└─── crg (CRG) +└─── ethphy (LiteEthPHYRGMII) +│ └─── crg (LiteEthPHYRGMIICRG) +│ │ └─── pll (S7PLL) +│ │ │ └─── [FDCE] +│ │ │ └─── [FDCE] +│ │ │ └─── [FDCE] +│ │ │ └─── [FDCE] +│ │ │ └─── [FDCE] +│ │ │ └─── [BUFG] +│ │ │ └─── [FDCE] +│ │ │ └─── [FDCE] +│ │ │ └─── [FDCE] +│ │ │ └─── [PLLE2_ADV] +│ │ │ └─── [BUFG] +│ │ └─── [BUFG] +│ │ └─── [ODDR] +│ │ └─── [IBUF] +│ │ └─── [OBUF] +│ └─── tx (LiteEthPHYRGMIITX) +│ │ └─── [OBUF] +│ │ └─── [ODDR] +│ │ └─── [OBUF] +│ │ └─── [OBUF] +│ │ └─── [OBUF] +│ │ └─── [ODDR] +│ │ └─── [ODDR] +│ │ └─── [ODDR] +│ │ └─── [OBUF] +│ │ └─── [ODDR] +│ └─── rx (LiteEthPHYRGMIIRX) +│ │ └─── [IDDR] +│ │ └─── [IBUF] +│ │ └─── [IBUF] +│ │ └─── [IDDR] +│ │ └─── [IBUF] +│ │ └─── [IDELAYE2] +│ │ └─── [IDDR] +│ │ └─── [IDDR] +│ │ └─── [IBUF] +│ │ └─── [IDELAYE2] +│ │ └─── [IDELAYE2] +│ │ └─── [IDELAYE2] +│ │ └─── [IBUF] +│ │ └─── [IDDR] +│ │ └─── [IDELAYE2] +│ └─── mdio (LiteEthPHYMDIO) +└─── ethmac (LiteEthMAC) +│ └─── core (LiteEthMACCore) +│ │ └─── tx_datapath (TXDatapath) +│ │ │ └─── clockdomaincrossing_0* (ClockDomainCrossing) +│ │ │ │ └─── asyncfifo_0* (AsyncFIFO) +│ │ │ │ │ └─── fifo (AsyncFIFO) +│ │ │ │ │ │ └─── graycounter_0* (GrayCounter) +│ │ │ │ │ │ └─── graycounter_1* (GrayCounter) +│ │ │ └─── strideconverter_0* (StrideConverter) +│ │ │ │ └─── converter_0* (Converter) +│ │ │ │ │ └─── _downconverter_0* (_DownConverter) +│ │ │ └─── liteethmactxlastbe_0* (LiteEthMACTXLastBE) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── liteethmacpaddinginserter_0* (LiteEthMACPaddingInserter) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── liteethmaccrc32inserter_0* (LiteEthMACCRC32Inserter) +│ │ │ │ └─── crc (LiteEthMACCRC32) +│ │ │ │ │ └─── liteethmaccrcengine_0* (LiteEthMACCRCEngine) +│ │ │ │ └─── fsm (FSM) +│ │ │ │ └─── buffer_0* (Buffer) +│ │ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── liteethmacpreambleinserter_0* (LiteEthMACPreambleInserter) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── liteethmacgap_0* (LiteEthMACGap) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── pipeline_0* (Pipeline) +│ │ └─── rx_datapath (RXDatapath) +│ │ │ └─── liteethmacpreamblechecker_0* (LiteEthMACPreambleChecker) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── pulsesynchronizer_0* (PulseSynchronizer) +│ │ │ └─── liteethmaccrc32checker_0* (LiteEthMACCRC32Checker) +│ │ │ │ └─── crc (LiteEthMACCRC32) +│ │ │ │ │ └─── liteethmaccrcengine_0* (LiteEthMACCRCEngine) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ └─── fsm (FSM) +│ │ │ │ └─── buffer_0* (Buffer) +│ │ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── pulsesynchronizer_1* (PulseSynchronizer) +│ │ │ └─── liteethmacpaddingchecker_0* (LiteEthMACPaddingChecker) +│ │ │ └─── liteethmacrxlastbe_0* (LiteEthMACRXLastBE) +│ │ │ └─── strideconverter_0* (StrideConverter) +│ │ │ │ └─── converter_0* (Converter) +│ │ │ │ │ └─── _upconverter_0* (_UpConverter) +│ │ │ └─── clockdomaincrossing_0* (ClockDomainCrossing) +│ │ │ │ └─── asyncfifo_0* (AsyncFIFO) +│ │ │ │ │ └─── fifo (AsyncFIFO) +│ │ │ │ │ │ └─── graycounter_0* (GrayCounter) +│ │ │ │ │ │ └─── graycounter_1* (GrayCounter) +│ │ │ └─── pipeline_0* (Pipeline) +│ └─── interface (LiteEthMACWishboneInterface) +│ │ └─── sram (LiteEthMACSRAM) +│ │ │ └─── writer (LiteEthMACSRAMWriter) +│ │ │ │ └─── ev (EventManager) +│ │ │ │ │ └─── eventsourcelevel_0* (EventSourceLevel) +│ │ │ │ └─── stat_fifo (SyncFIFO) +│ │ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── reader (LiteEthMACSRAMReader) +│ │ │ │ └─── ev (EventManager) +│ │ │ │ │ └─── eventsourcepulse_0* (EventSourcePulse) +│ │ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── ev (SharedIRQ) +│ │ └─── sram_0* (SRAM) +│ │ └─── sram_1* (SRAM) +│ │ └─── sram_2* (SRAM) +│ │ └─── sram_3* (SRAM) +│ │ └─── decoder_0* (Decoder) +└─── csr_bridge (Wishbone2CSR) +│ └─── fsm (FSM) +└─── csr_bankarray (CSRBankArray) +│ └─── csrbank_0* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ └─── csrbank_1* (CSRBank) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstatus_1* (CSRStatus) +│ │ └─── csrstatus_2* (CSRStatus) +│ │ └─── csrstatus_3* (CSRStatus) +│ │ └─── csrstatus_4* (CSRStatus) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstatus_5* (CSRStatus) +│ │ └─── csrstatus_6* (CSRStatus) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstatus_7* (CSRStatus) +│ │ └─── csrstatus_8* (CSRStatus) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstatus_9* (CSRStatus) +│ │ └─── csrstatus_10* (CSRStatus) +│ │ └─── csrstatus_11* (CSRStatus) +│ └─── csrbank_2* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +└─── csr_interconnect (InterconnectShared) +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +* : Generated name. +[]: BlackBox. +*/ + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +wire [13:0] builder_adr; +wire [39:0] builder_complexslicelowerer_slice_proxy; +reg [19:0] builder_count = 20'd1000000; +wire [31:0] builder_csrbank0_bus_errors_r; +reg builder_csrbank0_bus_errors_re = 1'd0; +wire [31:0] builder_csrbank0_bus_errors_w; +reg builder_csrbank0_bus_errors_we = 1'd0; +wire [1:0] builder_csrbank0_reset0_r; +reg builder_csrbank0_reset0_re = 1'd0; +wire [1:0] builder_csrbank0_reset0_w; +reg builder_csrbank0_reset0_we = 1'd0; +wire [31:0] builder_csrbank0_scratch0_r; +reg builder_csrbank0_scratch0_re = 1'd0; +wire [31:0] builder_csrbank0_scratch0_w; +reg builder_csrbank0_scratch0_we = 1'd0; +wire builder_csrbank0_sel; +wire builder_csrbank1_preamble_crc_r; +reg builder_csrbank1_preamble_crc_re = 1'd0; +wire builder_csrbank1_preamble_crc_w; +reg builder_csrbank1_preamble_crc_we = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_crc_errors_r; +reg builder_csrbank1_rx_datapath_crc_errors_re = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_crc_errors_w; +reg builder_csrbank1_rx_datapath_crc_errors_we = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_r; +reg builder_csrbank1_rx_datapath_preamble_errors_re = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_w; +reg builder_csrbank1_rx_datapath_preamble_errors_we = 1'd0; +wire builder_csrbank1_sel; +wire builder_csrbank1_sram_reader_ev_enable0_r; +reg builder_csrbank1_sram_reader_ev_enable0_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_enable0_w; +reg builder_csrbank1_sram_reader_ev_enable0_we = 1'd0; +wire builder_csrbank1_sram_reader_ev_pending_r; +reg builder_csrbank1_sram_reader_ev_pending_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_pending_w; +reg builder_csrbank1_sram_reader_ev_pending_we = 1'd0; +wire builder_csrbank1_sram_reader_ev_status_r; +reg builder_csrbank1_sram_reader_ev_status_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_status_w; +reg builder_csrbank1_sram_reader_ev_status_we = 1'd0; +wire [10:0] builder_csrbank1_sram_reader_length0_r; +reg builder_csrbank1_sram_reader_length0_re = 1'd0; +wire [10:0] builder_csrbank1_sram_reader_length0_w; +reg builder_csrbank1_sram_reader_length0_we = 1'd0; +wire [1:0] builder_csrbank1_sram_reader_level_r; +reg builder_csrbank1_sram_reader_level_re = 1'd0; +wire [1:0] builder_csrbank1_sram_reader_level_w; +reg builder_csrbank1_sram_reader_level_we = 1'd0; +wire builder_csrbank1_sram_reader_ready_r; +reg builder_csrbank1_sram_reader_ready_re = 1'd0; +wire builder_csrbank1_sram_reader_ready_w; +reg builder_csrbank1_sram_reader_ready_we = 1'd0; +wire builder_csrbank1_sram_reader_slot0_r; +reg builder_csrbank1_sram_reader_slot0_re = 1'd0; +wire builder_csrbank1_sram_reader_slot0_w; +reg builder_csrbank1_sram_reader_slot0_we = 1'd0; +wire [31:0] builder_csrbank1_sram_writer_errors_r; +reg builder_csrbank1_sram_writer_errors_re = 1'd0; +wire [31:0] builder_csrbank1_sram_writer_errors_w; +reg builder_csrbank1_sram_writer_errors_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_enable0_r; +reg builder_csrbank1_sram_writer_ev_enable0_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_enable0_w; +reg builder_csrbank1_sram_writer_ev_enable0_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_pending_r; +reg builder_csrbank1_sram_writer_ev_pending_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_pending_w; +reg builder_csrbank1_sram_writer_ev_pending_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_status_r; +reg builder_csrbank1_sram_writer_ev_status_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_status_w; +reg builder_csrbank1_sram_writer_ev_status_we = 1'd0; +wire [10:0] builder_csrbank1_sram_writer_length_r; +reg builder_csrbank1_sram_writer_length_re = 1'd0; +wire [10:0] builder_csrbank1_sram_writer_length_w; +reg builder_csrbank1_sram_writer_length_we = 1'd0; +wire builder_csrbank1_sram_writer_slot_r; +reg builder_csrbank1_sram_writer_slot_re = 1'd0; +wire builder_csrbank1_sram_writer_slot_w; +reg builder_csrbank1_sram_writer_slot_we = 1'd0; +wire builder_csrbank2_crg_reset0_r; +reg builder_csrbank2_crg_reset0_re = 1'd0; +wire builder_csrbank2_crg_reset0_w; +reg builder_csrbank2_crg_reset0_we = 1'd0; +wire builder_csrbank2_mdio_r_r; +reg builder_csrbank2_mdio_r_re = 1'd0; +wire builder_csrbank2_mdio_r_w; +reg builder_csrbank2_mdio_r_we = 1'd0; +wire [2:0] builder_csrbank2_mdio_w0_r; +reg builder_csrbank2_mdio_w0_re = 1'd0; +wire [2:0] builder_csrbank2_mdio_w0_w; +reg builder_csrbank2_mdio_w0_we = 1'd0; +wire builder_csrbank2_sel; +wire [31:0] builder_dat_r; +wire [31:0] builder_dat_w; +wire builder_done; +reg builder_error = 1'd0; +wire builder_grant; +reg builder_interface0_ack = 1'd0; +wire [29:0] builder_interface0_adr; +wire [13:0] builder_interface0_bank_bus_adr; +reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface0_bank_bus_dat_w; +wire builder_interface0_bank_bus_we; +wire [1:0] builder_interface0_bte; +wire [2:0] builder_interface0_cti; +wire builder_interface0_cyc; +reg [31:0] builder_interface0_dat_r = 32'd0; +wire [31:0] builder_interface0_dat_w; +reg builder_interface0_err = 1'd0; +wire [3:0] builder_interface0_sel; +wire builder_interface0_stb; +wire builder_interface0_we; +reg [13:0] builder_interface1_adr = 14'd0; +wire [13:0] builder_interface1_bank_bus_adr; +reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface1_bank_bus_dat_w; +wire builder_interface1_bank_bus_we; +wire [31:0] builder_interface1_dat_r; +reg [31:0] builder_interface1_dat_w = 32'd0; +reg builder_interface1_we = 1'd0; +wire [13:0] builder_interface2_bank_bus_adr; +reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface2_bank_bus_dat_w; +wire builder_interface2_bank_bus_we; +reg [1:0] builder_liteethmacsramreader_next_state = 2'd0; +reg [1:0] builder_liteethmacsramreader_state = 2'd0; +reg [2:0] builder_liteethmacsramwriter_next_state = 3'd0; +reg [2:0] builder_liteethmacsramwriter_state = 3'd0; +reg builder_next_state = 1'd0; +wire builder_pll_fb; +wire builder_request; +wire builder_reset0; +wire builder_reset1; +wire builder_reset2; +wire builder_reset3; +wire builder_reset4; +wire builder_reset5; +wire builder_reset6; +wire builder_reset7; +reg [1:0] builder_rxdatapath_bufferizeendpoints_next_state = 2'd0; +reg [1:0] builder_rxdatapath_bufferizeendpoints_state = 2'd0; +reg builder_rxdatapath_liteethmacpreamblechecker_next_state = 1'd0; +reg builder_rxdatapath_liteethmacpreamblechecker_state = 1'd0; +reg [29:0] builder_self0 = 30'd0; +reg [31:0] builder_self1 = 32'd0; +reg [3:0] builder_self2 = 4'd0; +reg builder_self3 = 1'd0; +reg builder_self4 = 1'd0; +reg builder_self5 = 1'd0; +reg [2:0] builder_self6 = 3'd0; +reg [1:0] builder_self7 = 2'd0; +reg builder_shared_ack = 1'd0; +wire [29:0] builder_shared_adr; +wire [1:0] builder_shared_bte; +wire [2:0] builder_shared_cti; +wire builder_shared_cyc; +reg [31:0] builder_shared_dat_r = 32'd0; +wire [31:0] builder_shared_dat_w; +wire builder_shared_err; +wire [3:0] builder_shared_sel; +wire builder_shared_stb; +wire builder_shared_we; +reg [1:0] builder_slave_sel = 2'd0; +reg [1:0] builder_slave_sel_r = 2'd0; +reg builder_state = 1'd0; +wire [31:0] builder_t_slice_proxy0; +wire [31:0] builder_t_slice_proxy1; +wire [31:0] builder_t_slice_proxy10; +wire [31:0] builder_t_slice_proxy11; +wire [31:0] builder_t_slice_proxy12; +wire [31:0] builder_t_slice_proxy13; +wire [31:0] builder_t_slice_proxy14; +wire [31:0] builder_t_slice_proxy15; +wire [31:0] builder_t_slice_proxy16; +wire [31:0] builder_t_slice_proxy17; +wire [31:0] builder_t_slice_proxy18; +wire [31:0] builder_t_slice_proxy19; +wire [31:0] builder_t_slice_proxy2; +wire [31:0] builder_t_slice_proxy20; +wire [31:0] builder_t_slice_proxy21; +wire [31:0] builder_t_slice_proxy22; +wire [31:0] builder_t_slice_proxy23; +wire [31:0] builder_t_slice_proxy24; +wire [31:0] builder_t_slice_proxy25; +wire [31:0] builder_t_slice_proxy26; +wire [31:0] builder_t_slice_proxy27; +wire [31:0] builder_t_slice_proxy28; +wire [31:0] builder_t_slice_proxy29; +wire [31:0] builder_t_slice_proxy3; +wire [31:0] builder_t_slice_proxy30; +wire [31:0] builder_t_slice_proxy31; +wire [31:0] builder_t_slice_proxy32; +wire [31:0] builder_t_slice_proxy33; +wire [31:0] builder_t_slice_proxy34; +wire [31:0] builder_t_slice_proxy35; +wire [31:0] builder_t_slice_proxy36; +wire [31:0] builder_t_slice_proxy37; +wire [31:0] builder_t_slice_proxy38; +wire [31:0] builder_t_slice_proxy39; +wire [31:0] builder_t_slice_proxy4; +wire [31:0] builder_t_slice_proxy40; +wire [31:0] builder_t_slice_proxy41; +wire [31:0] builder_t_slice_proxy42; +wire [31:0] builder_t_slice_proxy43; +wire [31:0] builder_t_slice_proxy44; +wire [31:0] builder_t_slice_proxy45; +wire [31:0] builder_t_slice_proxy46; +wire [31:0] builder_t_slice_proxy47; +wire [31:0] builder_t_slice_proxy48; +wire [31:0] builder_t_slice_proxy49; +wire [31:0] builder_t_slice_proxy5; +wire [31:0] builder_t_slice_proxy50; +wire [31:0] builder_t_slice_proxy51; +wire [31:0] builder_t_slice_proxy52; +wire [31:0] builder_t_slice_proxy53; +wire [31:0] builder_t_slice_proxy54; +wire [31:0] builder_t_slice_proxy55; +wire [31:0] builder_t_slice_proxy56; +wire [31:0] builder_t_slice_proxy57; +wire [31:0] builder_t_slice_proxy58; +wire [31:0] builder_t_slice_proxy59; +wire [31:0] builder_t_slice_proxy6; +wire [31:0] builder_t_slice_proxy60; +wire [31:0] builder_t_slice_proxy61; +wire [31:0] builder_t_slice_proxy62; +wire [31:0] builder_t_slice_proxy63; +wire [31:0] builder_t_slice_proxy7; +wire [31:0] builder_t_slice_proxy8; +wire [31:0] builder_t_slice_proxy9; +reg [1:0] builder_txdatapath_bufferizeendpoints_next_state = 2'd0; +reg [1:0] builder_txdatapath_bufferizeendpoints_state = 2'd0; +reg builder_txdatapath_liteethmacgap_next_state = 1'd0; +reg builder_txdatapath_liteethmacgap_state = 1'd0; +reg builder_txdatapath_liteethmacpaddinginserter_next_state = 1'd0; +reg builder_txdatapath_liteethmacpaddinginserter_state = 1'd0; +reg [1:0] builder_txdatapath_liteethmacpreambleinserter_next_state = 2'd0; +reg [1:0] builder_txdatapath_liteethmacpreambleinserter_state = 2'd0; +reg builder_txdatapath_liteethmactxlastbe_next_state = 1'd0; +reg builder_txdatapath_liteethmactxlastbe_state = 1'd0; +wire builder_wait; +wire builder_we; +wire builder_xilinxasyncresetsynchronizerimpl0_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl0_expr; +wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl00 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl01 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl10 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl11 = 6'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl20 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl21 = 6'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl30 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl31 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl40 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl41 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl50 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl51 = 6'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl60 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl61 = 6'd0; +(* dont_touch = "true" *) +wire eth_rx_clk; +wire eth_rx_rst; +(* dont_touch = "true" *) +wire eth_tx_clk; +wire eth_tx_delayed_clk; +wire eth_tx_rst; +wire main_bufferizeendpoints_pipe_valid_sink_first; +wire main_bufferizeendpoints_pipe_valid_sink_last; +wire [7:0] main_bufferizeendpoints_pipe_valid_sink_payload_data; +wire main_bufferizeendpoints_pipe_valid_sink_payload_error; +wire main_bufferizeendpoints_pipe_valid_sink_payload_last_be; +wire main_bufferizeendpoints_pipe_valid_sink_ready; +wire main_bufferizeendpoints_pipe_valid_sink_valid; +reg main_bufferizeendpoints_pipe_valid_source_first = 1'd0; +reg main_bufferizeendpoints_pipe_valid_source_last = 1'd0; +reg [7:0] main_bufferizeendpoints_pipe_valid_source_payload_data = 8'd0; +reg main_bufferizeendpoints_pipe_valid_source_payload_error = 1'd0; +reg main_bufferizeendpoints_pipe_valid_source_payload_last_be = 1'd0; +wire main_bufferizeendpoints_pipe_valid_source_ready; +reg main_bufferizeendpoints_pipe_valid_source_valid = 1'd0; +wire main_bufferizeendpoints_sink_sink_first; +wire main_bufferizeendpoints_sink_sink_last; +wire [7:0] main_bufferizeendpoints_sink_sink_payload_data; +wire main_bufferizeendpoints_sink_sink_payload_error; +wire main_bufferizeendpoints_sink_sink_payload_last_be; +wire main_bufferizeendpoints_sink_sink_ready; +wire main_bufferizeendpoints_sink_sink_valid; +wire main_bufferizeendpoints_source_source_first; +wire main_bufferizeendpoints_source_source_last; +wire [7:0] main_bufferizeendpoints_source_source_payload_data; +wire main_bufferizeendpoints_source_source_payload_error; +wire main_bufferizeendpoints_source_source_payload_last_be; +wire main_bufferizeendpoints_source_source_ready; +wire main_bufferizeendpoints_source_source_valid; +wire main_bus_ack; +wire [29:0] main_bus_adr; +wire [1:0] main_bus_bte; +wire [2:0] main_bus_cti; +wire main_bus_cyc; +wire [31:0] main_bus_dat_r; +wire [31:0] main_bus_dat_w; +wire main_bus_err; +wire [3:0] main_bus_sel; +wire main_bus_stb; +wire main_bus_we; +reg main_crc_errors_re = 1'd0; +reg [31:0] main_crc_errors_status = 32'd0; +wire main_crc_errors_we; +reg main_interface0_ack = 1'd0; +wire [29:0] main_interface0_adr; +wire [1:0] main_interface0_bte; +wire [2:0] main_interface0_cti; +wire main_interface0_cyc; +wire [31:0] main_interface0_dat_r; +wire [31:0] main_interface0_dat_w; +reg main_interface0_err = 1'd0; +wire [3:0] main_interface0_sel; +wire main_interface0_stb; +wire main_interface0_we; +reg main_interface1_ack = 1'd0; +wire [29:0] main_interface1_adr; +wire [1:0] main_interface1_bte; +wire [2:0] main_interface1_cti; +wire main_interface1_cyc; +wire [31:0] main_interface1_dat_r; +wire [31:0] main_interface1_dat_w; +reg main_interface1_err = 1'd0; +wire [3:0] main_interface1_sel; +wire main_interface1_stb; +wire main_interface1_we; +reg main_interface2_ack = 1'd0; +wire [29:0] main_interface2_adr; +wire [1:0] main_interface2_bte; +wire [2:0] main_interface2_cti; +wire main_interface2_cyc; +wire [31:0] main_interface2_dat_r; +wire [31:0] main_interface2_dat_w; +reg main_interface2_err = 1'd0; +wire [3:0] main_interface2_sel; +wire main_interface2_stb; +wire main_interface2_we; +reg main_interface3_ack = 1'd0; +wire [29:0] main_interface3_adr; +wire [1:0] main_interface3_bte; +wire [2:0] main_interface3_cti; +wire main_interface3_cyc; +wire [31:0] main_interface3_dat_r; +wire [31:0] main_interface3_dat_w; +reg main_interface3_err = 1'd0; +wire [3:0] main_interface3_sel; +wire main_interface3_stb; +wire main_interface3_we; +reg [3:0] main_length_inc = 4'd0; +wire main_liteethmaccrc32checker_crc_be; +reg main_liteethmaccrc32checker_crc_ce = 1'd0; +reg [31:0] main_liteethmaccrc32checker_crc_crc_next = 32'd0; +wire [31:0] main_liteethmaccrc32checker_crc_crc_prev; +wire [7:0] main_liteethmaccrc32checker_crc_data0; +wire [7:0] main_liteethmaccrc32checker_crc_data1; +reg main_liteethmaccrc32checker_crc_error0 = 1'd0; +reg main_liteethmaccrc32checker_crc_error1 = 1'd0; +reg main_liteethmaccrc32checker_crc_error1_next_value1 = 1'd0; +reg main_liteethmaccrc32checker_crc_error1_next_value_ce1 = 1'd0; +reg [31:0] main_liteethmaccrc32checker_crc_reg = 32'd4294967295; +reg main_liteethmaccrc32checker_crc_reset = 1'd0; +reg [31:0] main_liteethmaccrc32checker_crc_value = 32'd0; +reg main_liteethmaccrc32checker_error = 1'd0; +wire main_liteethmaccrc32checker_fifo_full; +wire main_liteethmaccrc32checker_fifo_in; +wire main_liteethmaccrc32checker_fifo_out; +reg main_liteethmaccrc32checker_fifo_reset = 1'd0; +reg main_liteethmaccrc32checker_last_be = 1'd0; +reg main_liteethmaccrc32checker_last_be_next_value0 = 1'd0; +reg main_liteethmaccrc32checker_last_be_next_value_ce0 = 1'd0; +wire main_liteethmaccrc32checker_sink_sink_first; +wire main_liteethmaccrc32checker_sink_sink_last; +wire [7:0] main_liteethmaccrc32checker_sink_sink_payload_data; +wire main_liteethmaccrc32checker_sink_sink_payload_error; +wire main_liteethmaccrc32checker_sink_sink_payload_last_be; +reg main_liteethmaccrc32checker_sink_sink_ready = 1'd0; +wire main_liteethmaccrc32checker_sink_sink_valid; +wire main_liteethmaccrc32checker_source_source_first; +reg main_liteethmaccrc32checker_source_source_last = 1'd0; +wire [7:0] main_liteethmaccrc32checker_source_source_payload_data; +reg main_liteethmaccrc32checker_source_source_payload_error = 1'd0; +reg main_liteethmaccrc32checker_source_source_payload_last_be = 1'd0; +wire main_liteethmaccrc32checker_source_source_ready; +reg main_liteethmaccrc32checker_source_source_valid = 1'd0; +reg [2:0] main_liteethmaccrc32checker_syncfifo_consume = 3'd0; +wire main_liteethmaccrc32checker_syncfifo_do_read; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_first; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_first; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; +reg [2:0] main_liteethmaccrc32checker_syncfifo_level = 3'd0; +reg [2:0] main_liteethmaccrc32checker_syncfifo_produce = 3'd0; +wire [2:0] main_liteethmaccrc32checker_syncfifo_rdport_adr; +wire [11:0] main_liteethmaccrc32checker_syncfifo_rdport_dat_r; +reg main_liteethmaccrc32checker_syncfifo_replace = 1'd0; +wire main_liteethmaccrc32checker_syncfifo_sink_first; +wire main_liteethmaccrc32checker_syncfifo_sink_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_sink_payload_data; +wire main_liteethmaccrc32checker_syncfifo_sink_payload_error; +wire main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; +wire main_liteethmaccrc32checker_syncfifo_sink_ready; +reg main_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; +wire main_liteethmaccrc32checker_syncfifo_source_first; +wire main_liteethmaccrc32checker_syncfifo_source_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_source_payload_data; +wire main_liteethmaccrc32checker_syncfifo_source_payload_error; +wire main_liteethmaccrc32checker_syncfifo_source_payload_last_be; +reg main_liteethmaccrc32checker_syncfifo_source_ready = 1'd0; +wire main_liteethmaccrc32checker_syncfifo_source_valid; +wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_din; +wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_dout; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_re; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_readable; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_we; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_writable; +reg [2:0] main_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; +wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_r; +wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_w; +wire main_liteethmaccrc32checker_syncfifo_wrport_we; +reg main_maccore_ethphy__r_re = 1'd0; +reg main_maccore_ethphy__r_status = 1'd0; +wire main_maccore_ethphy__r_we; +reg main_maccore_ethphy__w_re = 1'd0; +reg [2:0] main_maccore_ethphy__w_storage = 3'd0; +wire main_maccore_ethphy_clkin; +wire main_maccore_ethphy_clkout0; +wire main_maccore_ethphy_clkout1; +wire main_maccore_ethphy_clkout_buf0; +wire main_maccore_ethphy_clkout_buf1; +wire main_maccore_ethphy_data_oe; +wire main_maccore_ethphy_data_r; +wire main_maccore_ethphy_data_w; +wire main_maccore_ethphy_eth_rx_clk_ibuf; +wire main_maccore_ethphy_eth_tx_clk_obuf; +wire main_maccore_ethphy_liteethphyrgmiirx; +wire main_maccore_ethphy_liteethphyrgmiirx_last; +wire main_maccore_ethphy_liteethphyrgmiirx_rx_ctl; +reg main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_d = 1'd0; +wire main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_ibuf; +wire main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_idelay; +wire [7:0] main_maccore_ethphy_liteethphyrgmiirx_rx_data; +wire [3:0] main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf; +wire [3:0] main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay; +reg main_maccore_ethphy_liteethphyrgmiirx_source_first = 1'd0; +wire main_maccore_ethphy_liteethphyrgmiirx_source_last; +reg [7:0] main_maccore_ethphy_liteethphyrgmiirx_source_payload_data = 8'd0; +reg main_maccore_ethphy_liteethphyrgmiirx_source_payload_error = 1'd0; +reg main_maccore_ethphy_liteethphyrgmiirx_source_payload_last_be = 1'd0; +wire main_maccore_ethphy_liteethphyrgmiirx_source_ready; +reg main_maccore_ethphy_liteethphyrgmiirx_source_valid = 1'd0; +wire main_maccore_ethphy_locked; +wire main_maccore_ethphy_mdc; +wire main_maccore_ethphy_oe; +reg main_maccore_ethphy_power_down = 1'd0; +reg main_maccore_ethphy_r = 1'd0; +reg main_maccore_ethphy_reset0 = 1'd0; +wire main_maccore_ethphy_reset1; +reg main_maccore_ethphy_reset_re = 1'd0; +reg main_maccore_ethphy_reset_storage = 1'd0; +wire main_maccore_ethphy_sink_first; +wire main_maccore_ethphy_sink_last; +wire [7:0] main_maccore_ethphy_sink_payload_data; +wire main_maccore_ethphy_sink_payload_error; +wire main_maccore_ethphy_sink_payload_last_be; +wire main_maccore_ethphy_sink_ready; +wire main_maccore_ethphy_sink_valid; +wire main_maccore_ethphy_tx_ctl_obuf; +wire [3:0] main_maccore_ethphy_tx_data_obuf; +wire main_maccore_ethphy_w; +reg main_maccore_int_rst = 1'd1; +wire main_maccore_maccore_bus_error; +reg [31:0] main_maccore_maccore_bus_errors = 32'd0; +reg main_maccore_maccore_bus_errors_re = 1'd0; +wire [31:0] main_maccore_maccore_bus_errors_status; +wire main_maccore_maccore_bus_errors_we; +wire main_maccore_maccore_cpu_rst; +reg main_maccore_maccore_reset_re = 1'd0; +reg [1:0] main_maccore_maccore_reset_storage = 2'd0; +reg main_maccore_maccore_scratch_re = 1'd0; +reg [31:0] main_maccore_maccore_scratch_storage = 32'd305419896; +reg main_maccore_maccore_soc_rst = 1'd0; +reg main_preamble_errors_re = 1'd0; +reg [31:0] main_preamble_errors_status = 32'd0; +wire main_preamble_errors_we; +wire main_pulsesynchronizer0_i; +wire main_pulsesynchronizer0_o; +reg main_pulsesynchronizer0_toggle_i = 1'd0; +wire main_pulsesynchronizer0_toggle_o; +reg main_pulsesynchronizer0_toggle_o_r = 1'd0; +wire main_pulsesynchronizer1_i; +wire main_pulsesynchronizer1_o; +reg main_pulsesynchronizer1_toggle_i = 1'd0; +wire main_pulsesynchronizer1_toggle_o; +reg main_pulsesynchronizer1_toggle_o_r = 1'd0; +reg [31:0] main_rd_data = 32'd0; +reg main_re = 1'd0; +reg main_read = 1'd0; +wire [41:0] main_rx_cdc_cdc_asyncfifo_din; +wire [41:0] main_rx_cdc_cdc_asyncfifo_dout; +wire main_rx_cdc_cdc_asyncfifo_re; +wire main_rx_cdc_cdc_asyncfifo_readable; +wire main_rx_cdc_cdc_asyncfifo_we; +wire main_rx_cdc_cdc_asyncfifo_writable; +wire [5:0] main_rx_cdc_cdc_consume_wdomain; +wire main_rx_cdc_cdc_fifo_in_first; +wire main_rx_cdc_cdc_fifo_in_last; +wire [31:0] main_rx_cdc_cdc_fifo_in_payload_data; +wire [3:0] main_rx_cdc_cdc_fifo_in_payload_error; +wire [3:0] main_rx_cdc_cdc_fifo_in_payload_last_be; +wire main_rx_cdc_cdc_fifo_out_first; +wire main_rx_cdc_cdc_fifo_out_last; +wire [31:0] main_rx_cdc_cdc_fifo_out_payload_data; +wire [3:0] main_rx_cdc_cdc_fifo_out_payload_error; +wire [3:0] main_rx_cdc_cdc_fifo_out_payload_last_be; +wire main_rx_cdc_cdc_graycounter0_ce; +(* dont_touch = "true" *) +reg [5:0] main_rx_cdc_cdc_graycounter0_q = 6'd0; +reg [5:0] main_rx_cdc_cdc_graycounter0_q_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_graycounter0_q_next; +reg [5:0] main_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire main_rx_cdc_cdc_graycounter1_ce; +(* dont_touch = "true" *) +reg [5:0] main_rx_cdc_cdc_graycounter1_q = 6'd0; +reg [5:0] main_rx_cdc_cdc_graycounter1_q_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_graycounter1_q_next; +reg [5:0] main_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_produce_rdomain; +wire [4:0] main_rx_cdc_cdc_rdport_adr; +wire [41:0] main_rx_cdc_cdc_rdport_dat_r; +wire main_rx_cdc_cdc_sink_first; +wire main_rx_cdc_cdc_sink_last; +wire [31:0] main_rx_cdc_cdc_sink_payload_data; +wire [3:0] main_rx_cdc_cdc_sink_payload_error; +wire [3:0] main_rx_cdc_cdc_sink_payload_last_be; +wire main_rx_cdc_cdc_sink_ready; +wire main_rx_cdc_cdc_sink_valid; +wire main_rx_cdc_cdc_source_first; +wire main_rx_cdc_cdc_source_last; +wire [31:0] main_rx_cdc_cdc_source_payload_data; +wire [3:0] main_rx_cdc_cdc_source_payload_error; +wire [3:0] main_rx_cdc_cdc_source_payload_last_be; +wire main_rx_cdc_cdc_source_ready; +wire main_rx_cdc_cdc_source_valid; +wire [4:0] main_rx_cdc_cdc_wrport_adr; +wire [41:0] main_rx_cdc_cdc_wrport_dat_r; +wire [41:0] main_rx_cdc_cdc_wrport_dat_w; +wire main_rx_cdc_cdc_wrport_we; +wire main_rx_cdc_sink_sink_first; +wire main_rx_cdc_sink_sink_last; +wire [31:0] main_rx_cdc_sink_sink_payload_data; +wire [3:0] main_rx_cdc_sink_sink_payload_error; +wire [3:0] main_rx_cdc_sink_sink_payload_last_be; +wire main_rx_cdc_sink_sink_ready; +wire main_rx_cdc_sink_sink_valid; +wire main_rx_cdc_source_source_first; +wire main_rx_cdc_source_source_last; +wire [31:0] main_rx_cdc_source_source_payload_data; +wire [3:0] main_rx_cdc_source_source_payload_error; +wire [3:0] main_rx_cdc_source_source_payload_last_be; +wire main_rx_cdc_source_source_ready; +wire main_rx_cdc_source_source_valid; +reg [1:0] main_rx_converter_converter_demux = 2'd0; +wire main_rx_converter_converter_load_part; +wire main_rx_converter_converter_sink_first; +wire main_rx_converter_converter_sink_last; +wire [9:0] main_rx_converter_converter_sink_payload_data; +wire main_rx_converter_converter_sink_ready; +wire main_rx_converter_converter_sink_valid; +reg main_rx_converter_converter_source_first = 1'd0; +reg main_rx_converter_converter_source_last = 1'd0; +reg [39:0] main_rx_converter_converter_source_payload_data = 40'd0; +reg [2:0] main_rx_converter_converter_source_payload_valid_token_count = 3'd0; +wire main_rx_converter_converter_source_ready; +wire main_rx_converter_converter_source_valid; +reg main_rx_converter_converter_strobe_all = 1'd0; +wire main_rx_converter_sink_first; +wire main_rx_converter_sink_last; +wire [7:0] main_rx_converter_sink_payload_data; +wire main_rx_converter_sink_payload_error; +wire main_rx_converter_sink_payload_last_be; +wire main_rx_converter_sink_ready; +wire main_rx_converter_sink_valid; +wire main_rx_converter_source_first; +wire main_rx_converter_source_last; +reg [31:0] main_rx_converter_source_payload_data = 32'd0; +reg [3:0] main_rx_converter_source_payload_error = 4'd0; +reg [3:0] main_rx_converter_source_payload_last_be = 4'd0; +wire main_rx_converter_source_ready; +wire main_rx_converter_source_source_first; +wire main_rx_converter_source_source_last; +wire [39:0] main_rx_converter_source_source_payload_data; +wire main_rx_converter_source_source_ready; +wire main_rx_converter_source_source_valid; +wire main_rx_converter_source_valid; +wire main_rx_last_be_sink_first; +wire main_rx_last_be_sink_last; +wire [7:0] main_rx_last_be_sink_payload_data; +wire main_rx_last_be_sink_payload_error; +wire main_rx_last_be_sink_payload_last_be; +wire main_rx_last_be_sink_ready; +wire main_rx_last_be_sink_valid; +wire main_rx_last_be_source_first; +wire main_rx_last_be_source_last; +wire [7:0] main_rx_last_be_source_payload_data; +wire main_rx_last_be_source_payload_error; +reg main_rx_last_be_source_payload_last_be = 1'd0; +wire main_rx_last_be_source_ready; +wire main_rx_last_be_source_valid; +wire main_rx_padding_sink_first; +wire main_rx_padding_sink_last; +wire [7:0] main_rx_padding_sink_payload_data; +wire main_rx_padding_sink_payload_error; +wire main_rx_padding_sink_payload_last_be; +wire main_rx_padding_sink_ready; +wire main_rx_padding_sink_valid; +wire main_rx_padding_source_first; +wire main_rx_padding_source_last; +wire [7:0] main_rx_padding_source_payload_data; +wire main_rx_padding_source_payload_error; +wire main_rx_padding_source_payload_last_be; +wire main_rx_padding_source_ready; +wire main_rx_padding_source_valid; +reg main_rx_preamble_error = 1'd0; +reg [63:0] main_rx_preamble_preamble = 64'd15372286728091293013; +wire main_rx_preamble_sink_first; +wire main_rx_preamble_sink_last; +wire [7:0] main_rx_preamble_sink_payload_data; +wire main_rx_preamble_sink_payload_error; +wire main_rx_preamble_sink_payload_last_be; +reg main_rx_preamble_sink_ready = 1'd0; +wire main_rx_preamble_sink_valid; +reg main_rx_preamble_source_first = 1'd0; +reg main_rx_preamble_source_last = 1'd0; +wire [7:0] main_rx_preamble_source_payload_data; +reg main_rx_preamble_source_payload_error = 1'd0; +wire main_rx_preamble_source_payload_last_be; +wire main_rx_preamble_source_ready; +reg main_rx_preamble_source_valid = 1'd0; +wire main_sink_first; +wire main_sink_last; +wire [31:0] main_sink_payload_data; +wire [3:0] main_sink_payload_error; +wire [3:0] main_sink_payload_last_be; +wire main_sink_ready; +wire main_sink_sink_first; +wire main_sink_sink_last; +wire [31:0] main_sink_sink_payload_data; +wire [3:0] main_sink_sink_payload_error; +wire [3:0] main_sink_sink_payload_last_be; +wire main_sink_sink_ready; +wire main_sink_sink_valid; +wire main_sink_valid; +reg [3:0] main_slave_sel = 4'd0; +reg [3:0] main_slave_sel_r = 4'd0; +reg main_slot = 1'd0; +reg main_slot_liteethmacsramwriter_next_value = 1'd0; +reg main_slot_liteethmacsramwriter_next_value_ce = 1'd0; +wire main_source_first; +wire main_source_last; +wire [31:0] main_source_payload_data; +wire [3:0] main_source_payload_error; +wire [3:0] main_source_payload_last_be; +wire main_source_ready; +wire main_source_source_first; +wire main_source_source_last; +wire [31:0] main_source_source_payload_data; +wire [3:0] main_source_source_payload_error; +wire [3:0] main_source_source_payload_last_be; +wire main_source_source_ready; +wire main_source_source_valid; +wire main_source_valid; +wire [8:0] main_sram0_adr; +reg main_sram0_adr_burst = 1'd0; +wire [31:0] main_sram0_dat_r; +wire main_sram0_sink_valid; +reg main_sram100_storage = 1'd0; +reg main_sram101_re = 1'd0; +reg [10:0] main_sram102_storage = 11'd0; +reg main_sram103_re = 1'd0; +wire main_sram104_irq; +wire main_sram105_status; +reg main_sram106_pending = 1'd0; +reg main_sram107_trigger = 1'd0; +reg main_sram108_clear = 1'd0; +wire main_sram109_event0; +wire [10:0] main_sram10_status; +reg main_sram110_status = 1'd0; +wire main_sram111_we; +reg main_sram112_re = 1'd0; +wire main_sram113_event0; +reg main_sram114_status = 1'd0; +wire main_sram115_we; +reg main_sram116_re = 1'd0; +reg main_sram117_r = 1'd0; +wire main_sram118_event0; +reg main_sram119_storage = 1'd0; +wire main_sram11_we; +reg main_sram120_re = 1'd0; +reg [10:0] main_sram122_length = 11'd0; +reg [10:0] main_sram122_length_liteethmacsramreader_next_value = 11'd0; +reg main_sram122_length_liteethmacsramreader_next_value_ce = 1'd0; +wire main_sram123_sink_valid; +wire main_sram124_sink_ready; +reg main_sram125_sink_first = 1'd0; +reg main_sram126_sink_last = 1'd0; +wire main_sram127_sink_payload_slot; +wire [10:0] main_sram128_sink_payload_length; +wire main_sram129_source_valid; +reg main_sram12_re = 1'd0; +reg main_sram130_source_ready = 1'd0; +wire main_sram131_source_first; +wire main_sram132_source_last; +wire main_sram133_source_payload_slot; +wire [10:0] main_sram134_source_payload_length; +wire main_sram135_we; +wire main_sram136_writable; +wire main_sram137_re; +wire main_sram138_readable; +wire [13:0] main_sram139_din; +reg [31:0] main_sram13_status = 32'd0; +reg [31:0] main_sram13_status_liteethmacsramwriter_f_next_value = 32'd0; +reg main_sram13_status_liteethmacsramwriter_f_next_value_ce = 1'd0; +wire [13:0] main_sram140_dout; +reg [1:0] main_sram141_level = 2'd0; +reg main_sram142_replace = 1'd0; +reg main_sram143_produce = 1'd0; +reg main_sram144_consume = 1'd0; +reg main_sram145_adr = 1'd0; +wire [13:0] main_sram146_dat_r; +wire main_sram147_we; +wire [13:0] main_sram148_dat_w; +wire main_sram149_do_read; +wire main_sram14_we; +wire main_sram150_adr; +wire [13:0] main_sram151_dat_r; +wire main_sram152_fifo_in_payload_slot; +wire [10:0] main_sram153_fifo_in_payload_length; +wire main_sram154_fifo_in_first; +wire main_sram155_fifo_in_last; +wire main_sram156_fifo_out_payload_slot; +wire [10:0] main_sram157_fifo_out_payload_length; +wire main_sram158_fifo_out_first; +wire main_sram159_fifo_out_last; +reg main_sram15_re = 1'd0; +wire [8:0] main_sram161_adr; +wire [31:0] main_sram162_dat_r; +wire main_sram163_re; +wire [8:0] main_sram164_adr; +wire [31:0] main_sram165_dat_r; +wire main_sram166_re; +wire main_sram167_irq; +wire main_sram16_irq; +wire main_sram17_status; +wire main_sram18_pending; +wire main_sram19_trigger; +wire [8:0] main_sram1_adr; +reg main_sram1_adr_burst = 1'd0; +wire [31:0] main_sram1_dat_r; +reg main_sram1_sink_ready = 1'd1; +reg main_sram20_clear = 1'd0; +wire main_sram21_available; +reg main_sram22_status = 1'd0; +wire main_sram23_we; +reg main_sram24_re = 1'd0; +wire main_sram25_available; +reg main_sram26_status = 1'd0; +wire main_sram27_we; +reg main_sram28_re = 1'd0; +reg main_sram29_r = 1'd0; +wire [8:0] main_sram2_adr; +reg main_sram2_adr_burst = 1'd0; +wire [31:0] main_sram2_dat_r; +wire [31:0] main_sram2_dat_w; +wire main_sram2_sink_first; +reg [3:0] main_sram2_we = 4'd0; +wire main_sram30_available; +reg main_sram31_storage = 1'd0; +reg main_sram32_re = 1'd0; +reg [10:0] main_sram35_length = 11'd0; +reg [10:0] main_sram35_length_liteethmacsramwriter_t_next_value = 11'd0; +reg main_sram35_length_liteethmacsramwriter_t_next_value_ce = 1'd0; +reg main_sram37_sink_valid = 1'd0; +wire main_sram38_sink_ready; +reg main_sram39_sink_first = 1'd0; +wire [8:0] main_sram3_adr; +reg main_sram3_adr_burst = 1'd0; +wire [31:0] main_sram3_dat_r; +wire [31:0] main_sram3_dat_w; +wire main_sram3_sink_last; +reg [3:0] main_sram3_we = 4'd0; +reg main_sram40_sink_last = 1'd0; +reg main_sram41_sink_payload_slot = 1'd0; +reg [10:0] main_sram42_sink_payload_length = 11'd0; +wire main_sram43_source_valid; +wire main_sram44_source_ready; +wire main_sram45_source_first; +wire main_sram46_source_last; +wire main_sram47_source_payload_slot; +wire [10:0] main_sram48_source_payload_length; +wire main_sram49_we; +wire [31:0] main_sram4_sink_payload_data; +wire main_sram50_writable; +wire main_sram51_re; +wire main_sram52_readable; +wire [13:0] main_sram53_din; +wire [13:0] main_sram54_dout; +reg [1:0] main_sram55_level = 2'd0; +reg main_sram56_replace = 1'd0; +reg main_sram57_produce = 1'd0; +reg main_sram58_consume = 1'd0; +reg main_sram59_adr = 1'd0; +wire [3:0] main_sram5_sink_payload_last_be; +wire [13:0] main_sram60_dat_r; +wire main_sram61_we; +wire [13:0] main_sram62_dat_w; +wire main_sram63_do_read; +wire main_sram64_adr; +wire [13:0] main_sram65_dat_r; +wire main_sram66_fifo_in_payload_slot; +wire [10:0] main_sram67_fifo_in_payload_length; +wire main_sram68_fifo_in_first; +wire main_sram69_fifo_in_last; +wire [3:0] main_sram6_sink_payload_error; +wire main_sram70_fifo_out_payload_slot; +wire [10:0] main_sram71_fifo_out_payload_length; +wire main_sram72_fifo_out_first; +wire main_sram73_fifo_out_last; +reg [8:0] main_sram75_adr = 9'd0; +wire [31:0] main_sram76_dat_r; +reg main_sram77_we = 1'd0; +reg [31:0] main_sram78_dat_w = 32'd0; +reg [8:0] main_sram79_adr = 9'd0; +wire main_sram7_status; +wire [31:0] main_sram80_dat_r; +reg main_sram81_we = 1'd0; +reg [31:0] main_sram82_dat_w = 32'd0; +reg main_sram83_source_valid = 1'd0; +wire main_sram84_source_ready; +reg main_sram85_source_first = 1'd0; +reg main_sram86_source_last = 1'd0; +wire [31:0] main_sram87_source_payload_data; +reg [3:0] main_sram88_source_payload_last_be = 4'd0; +reg [3:0] main_sram89_source_payload_error = 4'd0; +wire main_sram8_we; +wire main_sram94_status; +wire main_sram95_we; +reg main_sram96_re = 1'd0; +wire [1:0] main_sram97_status; +wire main_sram98_we; +reg main_sram99_re = 1'd0; +reg main_sram9_re = 1'd0; +wire main_start_r; +reg main_start_re = 1'd0; +reg main_start_w = 1'd0; +reg main_start_we = 1'd0; +reg main_status = 1'd1; +wire [41:0] main_tx_cdc_cdc_asyncfifo_din; +wire [41:0] main_tx_cdc_cdc_asyncfifo_dout; +wire main_tx_cdc_cdc_asyncfifo_re; +wire main_tx_cdc_cdc_asyncfifo_readable; +wire main_tx_cdc_cdc_asyncfifo_we; +wire main_tx_cdc_cdc_asyncfifo_writable; +wire [5:0] main_tx_cdc_cdc_consume_wdomain; +wire main_tx_cdc_cdc_fifo_in_first; +wire main_tx_cdc_cdc_fifo_in_last; +wire [31:0] main_tx_cdc_cdc_fifo_in_payload_data; +wire [3:0] main_tx_cdc_cdc_fifo_in_payload_error; +wire [3:0] main_tx_cdc_cdc_fifo_in_payload_last_be; +wire main_tx_cdc_cdc_fifo_out_first; +wire main_tx_cdc_cdc_fifo_out_last; +wire [31:0] main_tx_cdc_cdc_fifo_out_payload_data; +wire [3:0] main_tx_cdc_cdc_fifo_out_payload_error; +wire [3:0] main_tx_cdc_cdc_fifo_out_payload_last_be; +wire main_tx_cdc_cdc_graycounter0_ce; +(* dont_touch = "true" *) +reg [5:0] main_tx_cdc_cdc_graycounter0_q = 6'd0; +reg [5:0] main_tx_cdc_cdc_graycounter0_q_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_graycounter0_q_next; +reg [5:0] main_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire main_tx_cdc_cdc_graycounter1_ce; +(* dont_touch = "true" *) +reg [5:0] main_tx_cdc_cdc_graycounter1_q = 6'd0; +reg [5:0] main_tx_cdc_cdc_graycounter1_q_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_graycounter1_q_next; +reg [5:0] main_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_produce_rdomain; +wire [4:0] main_tx_cdc_cdc_rdport_adr; +wire [41:0] main_tx_cdc_cdc_rdport_dat_r; +wire main_tx_cdc_cdc_sink_first; +wire main_tx_cdc_cdc_sink_last; +wire [31:0] main_tx_cdc_cdc_sink_payload_data; +wire [3:0] main_tx_cdc_cdc_sink_payload_error; +wire [3:0] main_tx_cdc_cdc_sink_payload_last_be; +wire main_tx_cdc_cdc_sink_ready; +wire main_tx_cdc_cdc_sink_valid; +wire main_tx_cdc_cdc_source_first; +wire main_tx_cdc_cdc_source_last; +wire [31:0] main_tx_cdc_cdc_source_payload_data; +wire [3:0] main_tx_cdc_cdc_source_payload_error; +wire [3:0] main_tx_cdc_cdc_source_payload_last_be; +wire main_tx_cdc_cdc_source_ready; +wire main_tx_cdc_cdc_source_valid; +wire [4:0] main_tx_cdc_cdc_wrport_adr; +wire [41:0] main_tx_cdc_cdc_wrport_dat_r; +wire [41:0] main_tx_cdc_cdc_wrport_dat_w; +wire main_tx_cdc_cdc_wrport_we; +wire main_tx_cdc_sink_sink_first; +wire main_tx_cdc_sink_sink_last; +wire [31:0] main_tx_cdc_sink_sink_payload_data; +wire [3:0] main_tx_cdc_sink_sink_payload_error; +wire [3:0] main_tx_cdc_sink_sink_payload_last_be; +wire main_tx_cdc_sink_sink_ready; +wire main_tx_cdc_sink_sink_valid; +wire main_tx_cdc_source_source_first; +wire main_tx_cdc_source_source_last; +wire [31:0] main_tx_cdc_source_source_payload_data; +wire [3:0] main_tx_cdc_source_source_payload_error; +wire [3:0] main_tx_cdc_source_source_payload_last_be; +wire main_tx_cdc_source_source_ready; +wire main_tx_cdc_source_source_valid; +wire main_tx_converter_converter_first; +wire main_tx_converter_converter_last; +reg [1:0] main_tx_converter_converter_mux = 2'd0; +wire main_tx_converter_converter_sink_first; +wire main_tx_converter_converter_sink_last; +reg [39:0] main_tx_converter_converter_sink_payload_data = 40'd0; +wire main_tx_converter_converter_sink_ready; +wire main_tx_converter_converter_sink_valid; +wire main_tx_converter_converter_source_first; +wire main_tx_converter_converter_source_last; +reg [9:0] main_tx_converter_converter_source_payload_data = 10'd0; +wire main_tx_converter_converter_source_payload_valid_token_count; +wire main_tx_converter_converter_source_ready; +wire main_tx_converter_converter_source_valid; +wire main_tx_converter_sink_first; +wire main_tx_converter_sink_last; +wire [31:0] main_tx_converter_sink_payload_data; +wire [3:0] main_tx_converter_sink_payload_error; +wire [3:0] main_tx_converter_sink_payload_last_be; +wire main_tx_converter_sink_ready; +wire main_tx_converter_sink_valid; +wire main_tx_converter_source_first; +wire main_tx_converter_source_last; +wire [7:0] main_tx_converter_source_payload_data; +wire main_tx_converter_source_payload_error; +wire main_tx_converter_source_payload_last_be; +wire main_tx_converter_source_ready; +wire main_tx_converter_source_source_first; +wire main_tx_converter_source_source_last; +wire [9:0] main_tx_converter_source_source_payload_data; +wire main_tx_converter_source_source_ready; +wire main_tx_converter_source_source_valid; +wire main_tx_converter_source_valid; +wire main_tx_crc_be; +reg main_tx_crc_ce = 1'd0; +reg [1:0] main_tx_crc_cnt = 2'd3; +wire main_tx_crc_cnt_done; +reg [31:0] main_tx_crc_crc_next = 32'd0; +reg [31:0] main_tx_crc_crc_packet = 32'd0; +reg [31:0] main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 = 32'd0; +reg main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 = 1'd0; +wire [31:0] main_tx_crc_crc_prev; +wire [7:0] main_tx_crc_data0; +wire [7:0] main_tx_crc_data1; +reg main_tx_crc_error = 1'd0; +reg main_tx_crc_is_ongoing0 = 1'd0; +reg main_tx_crc_is_ongoing1 = 1'd0; +reg main_tx_crc_last_be = 1'd0; +reg main_tx_crc_last_be_clockdomainsrenamer1_next_value1 = 1'd0; +reg main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 = 1'd0; +wire main_tx_crc_pipe_valid_sink_first; +wire main_tx_crc_pipe_valid_sink_last; +wire [7:0] main_tx_crc_pipe_valid_sink_payload_data; +wire main_tx_crc_pipe_valid_sink_payload_error; +wire main_tx_crc_pipe_valid_sink_payload_last_be; +wire main_tx_crc_pipe_valid_sink_ready; +wire main_tx_crc_pipe_valid_sink_valid; +reg main_tx_crc_pipe_valid_source_first = 1'd0; +reg main_tx_crc_pipe_valid_source_last = 1'd0; +reg [7:0] main_tx_crc_pipe_valid_source_payload_data = 8'd0; +reg main_tx_crc_pipe_valid_source_payload_error = 1'd0; +reg main_tx_crc_pipe_valid_source_payload_last_be = 1'd0; +wire main_tx_crc_pipe_valid_source_ready; +reg main_tx_crc_pipe_valid_source_valid = 1'd0; +reg [31:0] main_tx_crc_reg = 32'd4294967295; +reg main_tx_crc_reset = 1'd0; +wire main_tx_crc_sink_first; +wire main_tx_crc_sink_last; +wire [7:0] main_tx_crc_sink_payload_data; +wire main_tx_crc_sink_payload_error; +wire main_tx_crc_sink_payload_last_be; +reg main_tx_crc_sink_ready = 1'd0; +wire main_tx_crc_sink_sink_first; +wire main_tx_crc_sink_sink_last; +wire [7:0] main_tx_crc_sink_sink_payload_data; +wire main_tx_crc_sink_sink_payload_error; +wire main_tx_crc_sink_sink_payload_last_be; +wire main_tx_crc_sink_sink_ready; +wire main_tx_crc_sink_sink_valid; +wire main_tx_crc_sink_valid; +reg main_tx_crc_source_first = 1'd0; +reg main_tx_crc_source_last = 1'd0; +reg [7:0] main_tx_crc_source_payload_data = 8'd0; +reg main_tx_crc_source_payload_error = 1'd0; +reg main_tx_crc_source_payload_last_be = 1'd0; +wire main_tx_crc_source_ready; +wire main_tx_crc_source_source_first; +wire main_tx_crc_source_source_last; +wire [7:0] main_tx_crc_source_source_payload_data; +wire main_tx_crc_source_source_payload_error; +wire main_tx_crc_source_source_payload_last_be; +wire main_tx_crc_source_source_ready; +wire main_tx_crc_source_source_valid; +reg main_tx_crc_source_valid = 1'd0; +reg [31:0] main_tx_crc_value = 32'd0; +reg [3:0] main_tx_gap_counter = 4'd0; +reg [3:0] main_tx_gap_counter_clockdomainsrenamer3_next_value = 4'd0; +reg main_tx_gap_counter_clockdomainsrenamer3_next_value_ce = 1'd0; +wire main_tx_gap_sink_first; +wire main_tx_gap_sink_last; +wire [7:0] main_tx_gap_sink_payload_data; +wire main_tx_gap_sink_payload_error; +wire main_tx_gap_sink_payload_last_be; +reg main_tx_gap_sink_ready = 1'd0; +wire main_tx_gap_sink_valid; +reg main_tx_gap_source_first = 1'd0; +reg main_tx_gap_source_last = 1'd0; +reg [7:0] main_tx_gap_source_payload_data = 8'd0; +reg main_tx_gap_source_payload_error = 1'd0; +reg main_tx_gap_source_payload_last_be = 1'd0; +wire main_tx_gap_source_ready; +reg main_tx_gap_source_valid = 1'd0; +wire main_tx_last_be_sink_first; +wire main_tx_last_be_sink_last; +wire [7:0] main_tx_last_be_sink_payload_data; +wire main_tx_last_be_sink_payload_error; +wire main_tx_last_be_sink_payload_last_be; +reg main_tx_last_be_sink_ready = 1'd0; +wire main_tx_last_be_sink_valid; +reg main_tx_last_be_source_first = 1'd0; +reg main_tx_last_be_source_last = 1'd0; +reg [7:0] main_tx_last_be_source_payload_data = 8'd0; +reg main_tx_last_be_source_payload_error = 1'd0; +reg main_tx_last_be_source_payload_last_be = 1'd0; +wire main_tx_last_be_source_ready; +reg main_tx_last_be_source_valid = 1'd0; +reg [15:0] main_tx_padding_counter = 16'd0; +reg [15:0] main_tx_padding_counter_clockdomainsrenamer0_next_value = 16'd0; +reg main_tx_padding_counter_clockdomainsrenamer0_next_value_ce = 1'd0; +wire main_tx_padding_counter_done; +wire main_tx_padding_sink_first; +wire main_tx_padding_sink_last; +wire [7:0] main_tx_padding_sink_payload_data; +wire main_tx_padding_sink_payload_error; +wire main_tx_padding_sink_payload_last_be; +reg main_tx_padding_sink_ready = 1'd0; +wire main_tx_padding_sink_valid; +reg main_tx_padding_source_first = 1'd0; +reg main_tx_padding_source_last = 1'd0; +reg [7:0] main_tx_padding_source_payload_data = 8'd0; +reg main_tx_padding_source_payload_error = 1'd0; +reg main_tx_padding_source_payload_last_be = 1'd0; +wire main_tx_padding_source_ready; +reg main_tx_padding_source_valid = 1'd0; +reg [2:0] main_tx_preamble_count = 3'd0; +reg [2:0] main_tx_preamble_count_clockdomainsrenamer2_next_value = 3'd0; +reg main_tx_preamble_count_clockdomainsrenamer2_next_value_ce = 1'd0; +reg [63:0] main_tx_preamble_preamble = 64'd15372286728091293013; +wire main_tx_preamble_sink_first; +wire main_tx_preamble_sink_last; +wire [7:0] main_tx_preamble_sink_payload_data; +wire main_tx_preamble_sink_payload_error; +wire main_tx_preamble_sink_payload_last_be; +reg main_tx_preamble_sink_ready = 1'd0; +wire main_tx_preamble_sink_valid; +reg main_tx_preamble_source_first = 1'd0; +reg main_tx_preamble_source_last = 1'd0; +reg [7:0] main_tx_preamble_source_payload_data = 8'd0; +reg main_tx_preamble_source_payload_error = 1'd0; +wire main_tx_preamble_source_payload_last_be; +wire main_tx_preamble_source_ready; +reg main_tx_preamble_source_valid = 1'd0; +wire main_wb_bus_ack; +wire [29:0] main_wb_bus_adr; +wire [1:0] main_wb_bus_bte; +wire [2:0] main_wb_bus_cti; +wire main_wb_bus_cyc; +wire [31:0] main_wb_bus_dat_r; +wire [31:0] main_wb_bus_dat_w; +wire main_wb_bus_err; +wire [3:0] main_wb_bus_sel; +wire main_wb_bus_stb; +wire main_wb_bus_we; +wire main_we; +wire [31:0] main_wr_data; +reg main_write = 1'd0; +wire por_clk; +(* dont_touch = "true" *) +wire sys_clk; +wire sys_rst; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ assign main_wb_bus_adr = wishbone_adr; assign main_wb_bus_dat_w = wishbone_dat_w; @@ -1017,294 +1368,653 @@ assign main_wb_bus_we = wishbone_we; assign main_wb_bus_cti = wishbone_cti; assign main_wb_bus_bte = wishbone_bte; assign wishbone_err = main_wb_bus_err; -assign interrupt = main_ev_irq; +assign interrupt = main_sram167_irq; assign main_maccore_maccore_bus_error = builder_error; +assign builder_shared_adr = builder_self0; +assign builder_shared_dat_w = builder_self1; +assign builder_shared_sel = builder_self2; +assign builder_shared_cyc = builder_self3; +assign builder_shared_stb = builder_self4; +assign builder_shared_we = builder_self5; +assign builder_shared_cti = builder_self6; +assign builder_shared_bte = builder_self7; +assign main_wb_bus_dat_r = builder_shared_dat_r; +assign main_wb_bus_ack = (builder_shared_ack & (builder_grant == 1'd0)); +assign main_wb_bus_err = (builder_shared_err & (builder_grant == 1'd0)); +assign builder_request = {main_wb_bus_cyc}; +assign builder_grant = 1'd0; +always @(*) begin + builder_slave_sel <= 2'd0; + builder_slave_sel[0] <= (builder_shared_adr[29:11] == 4'd8); + builder_slave_sel[1] <= (builder_shared_adr[29:14] == 1'd0); +end +assign main_bus_adr = builder_shared_adr; +assign main_bus_dat_w = builder_shared_dat_w; +assign main_bus_sel = builder_shared_sel; +assign main_bus_stb = builder_shared_stb; +assign main_bus_we = builder_shared_we; +assign main_bus_cti = builder_shared_cti; +assign main_bus_bte = builder_shared_bte; +assign builder_interface0_adr = builder_shared_adr; +assign builder_interface0_dat_w = builder_shared_dat_w; +assign builder_interface0_sel = builder_shared_sel; +assign builder_interface0_stb = builder_shared_stb; +assign builder_interface0_we = builder_shared_we; +assign builder_interface0_cti = builder_shared_cti; +assign builder_interface0_bte = builder_shared_bte; +assign main_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]); +assign builder_interface0_cyc = (builder_shared_cyc & builder_slave_sel[1]); +assign builder_shared_err = (main_bus_err | builder_interface0_err); +assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack)); +always @(*) begin + builder_error <= 1'd0; + builder_shared_ack <= 1'd0; + builder_shared_dat_r <= 32'd0; + builder_shared_ack <= (main_bus_ack | builder_interface0_ack); + builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & builder_interface0_dat_r)); + if (builder_done) begin + builder_shared_dat_r <= 32'd4294967295; + builder_shared_ack <= 1'd1; + builder_error <= 1'd1; + end +end +assign builder_done = (builder_count == 1'd0); assign main_maccore_maccore_bus_errors_status = main_maccore_maccore_bus_errors; assign sys_clk = sys_clock; assign por_clk = sys_clock; assign sys_rst = main_maccore_int_rst; assign main_maccore_ethphy_reset1 = main_maccore_ethphy_reset_storage; -assign rgmii_eth_rst_n = (~main_maccore_ethphy_reset1); +assign rgmii_rst_n = (~main_maccore_ethphy_reset1); assign main_maccore_ethphy_clkin = eth_rx_clk; assign eth_tx_clk = main_maccore_ethphy_clkout_buf0; assign eth_tx_delayed_clk = main_maccore_ethphy_clkout_buf1; assign main_maccore_ethphy_sink_ready = 1'd1; assign main_maccore_ethphy_liteethphyrgmiirx_last = ((~main_maccore_ethphy_liteethphyrgmiirx_rx_ctl) & main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_d); assign main_maccore_ethphy_liteethphyrgmiirx_source_last = main_maccore_ethphy_liteethphyrgmiirx_last; -assign rgmii_eth_mdc = main_maccore_ethphy__w_storage[0]; +assign rgmii_mdc = main_maccore_ethphy__w_storage[0]; assign main_maccore_ethphy_data_oe = main_maccore_ethphy__w_storage[1]; assign main_maccore_ethphy_data_w = main_maccore_ethphy__w_storage[2]; -assign main_tx_cdc_sink_sink_valid = main_source_valid; -assign main_source_ready = main_tx_cdc_sink_sink_ready; -assign main_tx_cdc_sink_sink_first = main_source_first; -assign main_tx_cdc_sink_sink_last = main_source_last; -assign main_tx_cdc_sink_sink_payload_data = main_source_payload_data; -assign main_tx_cdc_sink_sink_payload_last_be = main_source_payload_last_be; -assign main_tx_cdc_sink_sink_payload_error = main_source_payload_error; -assign main_sink_valid = main_rx_cdc_source_source_valid; -assign main_rx_cdc_source_source_ready = main_sink_ready; -assign main_sink_first = main_rx_cdc_source_source_first; -assign main_sink_last = main_rx_cdc_source_source_last; -assign main_sink_payload_data = main_rx_cdc_source_source_payload_data; -assign main_sink_payload_last_be = main_rx_cdc_source_source_payload_last_be; -assign main_sink_payload_error = main_rx_cdc_source_source_payload_error; -assign main_ps_preamble_error_i = main_preamble_checker_error; -assign main_ps_crc_error_i = main_liteethmaccrc32checker_error; -always @(*) begin - main_tx_gap_inserter_source_payload_last_be <= 1'd0; - main_tx_gap_inserter_source_payload_error <= 1'd0; - main_tx_gap_inserter_sink_ready <= 1'd0; - main_tx_gap_inserter_source_valid <= 1'd0; - builder_liteethmacgap_next_state <= 1'd0; - main_tx_gap_inserter_counter_liteethmacgap_next_value <= 4'd0; - main_tx_gap_inserter_source_first <= 1'd0; - main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd0; - main_tx_gap_inserter_source_last <= 1'd0; - main_tx_gap_inserter_source_payload_data <= 8'd0; - builder_liteethmacgap_next_state <= builder_liteethmacgap_state; - case (builder_liteethmacgap_state) - 1'd1: begin - main_tx_gap_inserter_counter_liteethmacgap_next_value <= (main_tx_gap_inserter_counter + 1'd1); - main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1; - if ((main_tx_gap_inserter_counter == 4'd11)) begin - builder_liteethmacgap_next_state <= 1'd0; - end - end - default: begin - main_tx_gap_inserter_counter_liteethmacgap_next_value <= 1'd0; - main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1; - main_tx_gap_inserter_source_valid <= main_tx_gap_inserter_sink_valid; - main_tx_gap_inserter_sink_ready <= main_tx_gap_inserter_source_ready; - main_tx_gap_inserter_source_first <= main_tx_gap_inserter_sink_first; - main_tx_gap_inserter_source_last <= main_tx_gap_inserter_sink_last; - main_tx_gap_inserter_source_payload_data <= main_tx_gap_inserter_sink_payload_data; - main_tx_gap_inserter_source_payload_last_be <= main_tx_gap_inserter_sink_payload_last_be; - main_tx_gap_inserter_source_payload_error <= main_tx_gap_inserter_sink_payload_error; - if (((main_tx_gap_inserter_sink_valid & main_tx_gap_inserter_sink_last) & main_tx_gap_inserter_sink_ready)) begin - builder_liteethmacgap_next_state <= 1'd1; - end - end - endcase -end -assign main_preamble_inserter_source_payload_last_be = main_preamble_inserter_sink_payload_last_be; -always @(*) begin - main_preamble_inserter_sink_ready <= 1'd0; - builder_liteethmacpreambleinserter_next_state <= 2'd0; - main_preamble_inserter_count_liteethmacpreambleinserter_next_value <= 3'd0; - main_preamble_inserter_source_valid <= 1'd0; - main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd0; - main_preamble_inserter_source_first <= 1'd0; - main_preamble_inserter_source_last <= 1'd0; - main_preamble_inserter_source_payload_data <= 8'd0; - main_preamble_inserter_source_payload_error <= 1'd0; - main_preamble_inserter_source_payload_data <= main_preamble_inserter_sink_payload_data; - builder_liteethmacpreambleinserter_next_state <= builder_liteethmacpreambleinserter_state; - case (builder_liteethmacpreambleinserter_state) - 1'd1: begin - main_preamble_inserter_source_valid <= 1'd1; - case (main_preamble_inserter_count) - 1'd0: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[7:0]; - end - 1'd1: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[15:8]; - end - 2'd2: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[23:16]; - end - 2'd3: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[31:24]; - end - 3'd4: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[39:32]; - end - 3'd5: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[47:40]; - end - 3'd6: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[55:48]; - end - default: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[63:56]; - end - endcase - if (main_preamble_inserter_source_ready) begin - if ((main_preamble_inserter_count == 3'd7)) begin - builder_liteethmacpreambleinserter_next_state <= 2'd2; - end else begin - main_preamble_inserter_count_liteethmacpreambleinserter_next_value <= (main_preamble_inserter_count + 1'd1); - main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1; - end - end - end - 2'd2: begin - main_preamble_inserter_source_valid <= main_preamble_inserter_sink_valid; - main_preamble_inserter_sink_ready <= main_preamble_inserter_source_ready; - main_preamble_inserter_source_first <= main_preamble_inserter_sink_first; - main_preamble_inserter_source_last <= main_preamble_inserter_sink_last; - main_preamble_inserter_source_payload_error <= main_preamble_inserter_sink_payload_error; - if (((main_preamble_inserter_sink_valid & main_preamble_inserter_sink_last) & main_preamble_inserter_source_ready)) begin - builder_liteethmacpreambleinserter_next_state <= 1'd0; - end - end - default: begin - main_preamble_inserter_sink_ready <= 1'd1; - main_preamble_inserter_count_liteethmacpreambleinserter_next_value <= 1'd0; - main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1; - if (main_preamble_inserter_sink_valid) begin - main_preamble_inserter_sink_ready <= 1'd0; - builder_liteethmacpreambleinserter_next_state <= 1'd1; - end - end - endcase -end -assign main_preamble_checker_source_payload_data = main_preamble_checker_sink_payload_data; -assign main_preamble_checker_source_payload_last_be = main_preamble_checker_sink_payload_last_be; -always @(*) begin - main_preamble_checker_source_payload_error <= 1'd0; - main_preamble_checker_error <= 1'd0; - main_preamble_checker_source_valid <= 1'd0; - main_preamble_checker_sink_ready <= 1'd0; - builder_liteethmacpreamblechecker_next_state <= 1'd0; - main_preamble_checker_source_first <= 1'd0; - main_preamble_checker_source_last <= 1'd0; - builder_liteethmacpreamblechecker_next_state <= builder_liteethmacpreamblechecker_state; - case (builder_liteethmacpreamblechecker_state) - 1'd1: begin - main_preamble_checker_source_valid <= main_preamble_checker_sink_valid; - main_preamble_checker_sink_ready <= main_preamble_checker_source_ready; - main_preamble_checker_source_first <= main_preamble_checker_sink_first; - main_preamble_checker_source_last <= main_preamble_checker_sink_last; - main_preamble_checker_source_payload_error <= main_preamble_checker_sink_payload_error; - if (((main_preamble_checker_source_valid & main_preamble_checker_source_last) & main_preamble_checker_source_ready)) begin - builder_liteethmacpreamblechecker_next_state <= 1'd0; - end - end - default: begin - main_preamble_checker_sink_ready <= 1'd1; - if (((main_preamble_checker_sink_valid & (~main_preamble_checker_sink_last)) & (main_preamble_checker_sink_payload_data == 8'd213))) begin - builder_liteethmacpreamblechecker_next_state <= 1'd1; - end - if ((main_preamble_checker_sink_valid & main_preamble_checker_sink_last)) begin - main_preamble_checker_error <= 1'd1; - end - end - endcase -end -assign main_liteethmaccrc32inserter_cnt_done = (main_liteethmaccrc32inserter_cnt == 1'd0); -assign main_liteethmaccrc32inserter_sink_valid = main_crc32_inserter_source_valid; -assign main_crc32_inserter_source_ready = main_liteethmaccrc32inserter_sink_ready; -assign main_liteethmaccrc32inserter_sink_first = main_crc32_inserter_source_first; -assign main_liteethmaccrc32inserter_sink_last = main_crc32_inserter_source_last; -assign main_liteethmaccrc32inserter_sink_payload_data = main_crc32_inserter_source_payload_data; -assign main_liteethmaccrc32inserter_sink_payload_last_be = main_crc32_inserter_source_payload_last_be; -assign main_liteethmaccrc32inserter_sink_payload_error = main_crc32_inserter_source_payload_error; -assign main_liteethmaccrc32inserter_data1 = main_liteethmaccrc32inserter_data0; -assign main_liteethmaccrc32inserter_last = main_liteethmaccrc32inserter_reg; -assign main_liteethmaccrc32inserter_value = (~{main_liteethmaccrc32inserter_reg[0], main_liteethmaccrc32inserter_reg[1], main_liteethmaccrc32inserter_reg[2], main_liteethmaccrc32inserter_reg[3], main_liteethmaccrc32inserter_reg[4], main_liteethmaccrc32inserter_reg[5], main_liteethmaccrc32inserter_reg[6], main_liteethmaccrc32inserter_reg[7], main_liteethmaccrc32inserter_reg[8], main_liteethmaccrc32inserter_reg[9], main_liteethmaccrc32inserter_reg[10], main_liteethmaccrc32inserter_reg[11], main_liteethmaccrc32inserter_reg[12], main_liteethmaccrc32inserter_reg[13], main_liteethmaccrc32inserter_reg[14], main_liteethmaccrc32inserter_reg[15], main_liteethmaccrc32inserter_reg[16], main_liteethmaccrc32inserter_reg[17], main_liteethmaccrc32inserter_reg[18], main_liteethmaccrc32inserter_reg[19], main_liteethmaccrc32inserter_reg[20], main_liteethmaccrc32inserter_reg[21], main_liteethmaccrc32inserter_reg[22], main_liteethmaccrc32inserter_reg[23], main_liteethmaccrc32inserter_reg[24], main_liteethmaccrc32inserter_reg[25], main_liteethmaccrc32inserter_reg[26], main_liteethmaccrc32inserter_reg[27], main_liteethmaccrc32inserter_reg[28], main_liteethmaccrc32inserter_reg[29], main_liteethmaccrc32inserter_reg[30], main_liteethmaccrc32inserter_reg[31]}); -assign main_liteethmaccrc32inserter_error = (main_liteethmaccrc32inserter_next != 32'd3338984827); -always @(*) begin - main_liteethmaccrc32inserter_next <= 32'd0; - main_liteethmaccrc32inserter_next[0] <= (((main_liteethmaccrc32inserter_last[24] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[1] <= (((((((main_liteethmaccrc32inserter_last[25] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[2] <= (((((((((main_liteethmaccrc32inserter_last[26] ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[3] <= (((((((main_liteethmaccrc32inserter_last[27] ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[4] <= (((((((((main_liteethmaccrc32inserter_last[28] ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[5] <= (((((((((((((main_liteethmaccrc32inserter_last[29] ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[6] <= (((((((((((main_liteethmaccrc32inserter_last[30] ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[7] <= (((((((((main_liteethmaccrc32inserter_last[31] ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[8] <= ((((((((main_liteethmaccrc32inserter_last[0] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[9] <= ((((((((main_liteethmaccrc32inserter_last[1] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[10] <= ((((((((main_liteethmaccrc32inserter_last[2] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[11] <= ((((((((main_liteethmaccrc32inserter_last[3] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[12] <= ((((((((((((main_liteethmaccrc32inserter_last[4] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[13] <= ((((((((((((main_liteethmaccrc32inserter_last[5] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[14] <= ((((((((((main_liteethmaccrc32inserter_last[6] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]); - main_liteethmaccrc32inserter_next[15] <= ((((((((main_liteethmaccrc32inserter_last[7] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]); - main_liteethmaccrc32inserter_next[16] <= ((((((main_liteethmaccrc32inserter_last[8] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[17] <= ((((((main_liteethmaccrc32inserter_last[9] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[18] <= ((((((main_liteethmaccrc32inserter_last[10] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]); - main_liteethmaccrc32inserter_next[19] <= ((((main_liteethmaccrc32inserter_last[11] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]); - main_liteethmaccrc32inserter_next[20] <= ((main_liteethmaccrc32inserter_last[12] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]); - main_liteethmaccrc32inserter_next[21] <= ((main_liteethmaccrc32inserter_last[13] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]); - main_liteethmaccrc32inserter_next[22] <= ((main_liteethmaccrc32inserter_last[14] ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[23] <= ((((((main_liteethmaccrc32inserter_last[15] ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[24] <= ((((((main_liteethmaccrc32inserter_last[16] ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[25] <= ((((main_liteethmaccrc32inserter_last[17] ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]); - main_liteethmaccrc32inserter_next[26] <= ((((((((main_liteethmaccrc32inserter_last[18] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[27] <= ((((((((main_liteethmaccrc32inserter_last[19] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[28] <= ((((((main_liteethmaccrc32inserter_last[20] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]); - main_liteethmaccrc32inserter_next[29] <= ((((((main_liteethmaccrc32inserter_last[21] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]); - main_liteethmaccrc32inserter_next[30] <= ((((main_liteethmaccrc32inserter_last[22] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]); - main_liteethmaccrc32inserter_next[31] <= ((main_liteethmaccrc32inserter_last[23] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]); -end -always @(*) begin - main_liteethmaccrc32inserter_is_ongoing0 <= 1'd0; - main_liteethmaccrc32inserter_sink_ready <= 1'd0; - main_liteethmaccrc32inserter_is_ongoing1 <= 1'd0; - main_liteethmaccrc32inserter_ce <= 1'd0; - main_liteethmaccrc32inserter_reset <= 1'd0; - main_liteethmaccrc32inserter_source_valid <= 1'd0; - main_liteethmaccrc32inserter_source_first <= 1'd0; - main_liteethmaccrc32inserter_source_last <= 1'd0; - main_liteethmaccrc32inserter_source_payload_data <= 8'd0; - main_liteethmaccrc32inserter_source_payload_last_be <= 1'd0; - main_liteethmaccrc32inserter_source_payload_error <= 1'd0; - builder_liteethmaccrc32inserter_next_state <= 2'd0; - main_liteethmaccrc32inserter_data0 <= 8'd0; - builder_liteethmaccrc32inserter_next_state <= builder_liteethmaccrc32inserter_state; - case (builder_liteethmaccrc32inserter_state) - 1'd1: begin - main_liteethmaccrc32inserter_ce <= (main_liteethmaccrc32inserter_sink_valid & main_liteethmaccrc32inserter_source_ready); - main_liteethmaccrc32inserter_data0 <= main_liteethmaccrc32inserter_sink_payload_data; - main_liteethmaccrc32inserter_source_valid <= main_liteethmaccrc32inserter_sink_valid; - main_liteethmaccrc32inserter_sink_ready <= main_liteethmaccrc32inserter_source_ready; - main_liteethmaccrc32inserter_source_first <= main_liteethmaccrc32inserter_sink_first; - main_liteethmaccrc32inserter_source_last <= main_liteethmaccrc32inserter_sink_last; - main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_sink_payload_data; - main_liteethmaccrc32inserter_source_payload_last_be <= main_liteethmaccrc32inserter_sink_payload_last_be; - main_liteethmaccrc32inserter_source_payload_error <= main_liteethmaccrc32inserter_sink_payload_error; - main_liteethmaccrc32inserter_source_last <= 1'd0; - if (((main_liteethmaccrc32inserter_sink_valid & main_liteethmaccrc32inserter_sink_last) & main_liteethmaccrc32inserter_source_ready)) begin - builder_liteethmaccrc32inserter_next_state <= 2'd2; - end - end - 2'd2: begin - main_liteethmaccrc32inserter_source_valid <= 1'd1; - case (main_liteethmaccrc32inserter_cnt) - 1'd0: begin - main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[31:24]; - end - 1'd1: begin - main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[23:16]; - end - 2'd2: begin - main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[15:8]; - end - default: begin - main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[7:0]; - end - endcase - if (main_liteethmaccrc32inserter_cnt_done) begin - main_liteethmaccrc32inserter_source_last <= 1'd1; - if (main_liteethmaccrc32inserter_source_ready) begin - builder_liteethmaccrc32inserter_next_state <= 1'd0; - end - end - main_liteethmaccrc32inserter_is_ongoing1 <= 1'd1; - end - default: begin - main_liteethmaccrc32inserter_reset <= 1'd1; - main_liteethmaccrc32inserter_sink_ready <= 1'd1; - if (main_liteethmaccrc32inserter_sink_valid) begin - main_liteethmaccrc32inserter_sink_ready <= 1'd0; - builder_liteethmaccrc32inserter_next_state <= 1'd1; - end - main_liteethmaccrc32inserter_is_ongoing0 <= 1'd1; - end - endcase -end -assign main_crc32_inserter_sink_ready = ((~main_crc32_inserter_source_valid) | main_crc32_inserter_source_ready); +assign main_sink_valid = main_source_source_valid; +assign main_source_source_ready = main_sink_ready; +assign main_sink_first = main_source_source_first; +assign main_sink_last = main_source_source_last; +assign main_sink_payload_data = main_source_source_payload_data; +assign main_sink_payload_last_be = main_source_source_payload_last_be; +assign main_sink_payload_error = main_source_source_payload_error; +assign main_sink_sink_valid = main_source_valid; +assign main_source_ready = main_sink_sink_ready; +assign main_sink_sink_first = main_source_first; +assign main_sink_sink_last = main_source_last; +assign main_sink_sink_payload_data = main_source_payload_data; +assign main_sink_sink_payload_last_be = main_source_payload_last_be; +assign main_sink_sink_payload_error = main_source_payload_error; +assign main_tx_cdc_cdc_sink_valid = main_tx_cdc_sink_sink_valid; +assign main_tx_cdc_sink_sink_ready = main_tx_cdc_cdc_sink_ready; +assign main_tx_cdc_cdc_sink_first = main_tx_cdc_sink_sink_first; +assign main_tx_cdc_cdc_sink_last = main_tx_cdc_sink_sink_last; +assign main_tx_cdc_cdc_sink_payload_data = main_tx_cdc_sink_sink_payload_data; +assign main_tx_cdc_cdc_sink_payload_last_be = main_tx_cdc_sink_sink_payload_last_be; +assign main_tx_cdc_cdc_sink_payload_error = main_tx_cdc_sink_sink_payload_error; +assign main_tx_cdc_source_source_valid = main_tx_cdc_cdc_source_valid; +assign main_tx_cdc_cdc_source_ready = main_tx_cdc_source_source_ready; +assign main_tx_cdc_source_source_first = main_tx_cdc_cdc_source_first; +assign main_tx_cdc_source_source_last = main_tx_cdc_cdc_source_last; +assign main_tx_cdc_source_source_payload_data = main_tx_cdc_cdc_source_payload_data; +assign main_tx_cdc_source_source_payload_last_be = main_tx_cdc_cdc_source_payload_last_be; +assign main_tx_cdc_source_source_payload_error = main_tx_cdc_cdc_source_payload_error; +assign main_tx_cdc_cdc_asyncfifo_din = {main_tx_cdc_cdc_fifo_in_last, main_tx_cdc_cdc_fifo_in_first, main_tx_cdc_cdc_fifo_in_payload_error, main_tx_cdc_cdc_fifo_in_payload_last_be, main_tx_cdc_cdc_fifo_in_payload_data}; +assign {main_tx_cdc_cdc_fifo_out_last, main_tx_cdc_cdc_fifo_out_first, main_tx_cdc_cdc_fifo_out_payload_error, main_tx_cdc_cdc_fifo_out_payload_last_be, main_tx_cdc_cdc_fifo_out_payload_data} = main_tx_cdc_cdc_asyncfifo_dout; +assign main_tx_cdc_cdc_sink_ready = main_tx_cdc_cdc_asyncfifo_writable; +assign main_tx_cdc_cdc_asyncfifo_we = main_tx_cdc_cdc_sink_valid; +assign main_tx_cdc_cdc_fifo_in_first = main_tx_cdc_cdc_sink_first; +assign main_tx_cdc_cdc_fifo_in_last = main_tx_cdc_cdc_sink_last; +assign main_tx_cdc_cdc_fifo_in_payload_data = main_tx_cdc_cdc_sink_payload_data; +assign main_tx_cdc_cdc_fifo_in_payload_last_be = main_tx_cdc_cdc_sink_payload_last_be; +assign main_tx_cdc_cdc_fifo_in_payload_error = main_tx_cdc_cdc_sink_payload_error; +assign main_tx_cdc_cdc_source_valid = main_tx_cdc_cdc_asyncfifo_readable; +assign main_tx_cdc_cdc_source_first = main_tx_cdc_cdc_fifo_out_first; +assign main_tx_cdc_cdc_source_last = main_tx_cdc_cdc_fifo_out_last; +assign main_tx_cdc_cdc_source_payload_data = main_tx_cdc_cdc_fifo_out_payload_data; +assign main_tx_cdc_cdc_source_payload_last_be = main_tx_cdc_cdc_fifo_out_payload_last_be; +assign main_tx_cdc_cdc_source_payload_error = main_tx_cdc_cdc_fifo_out_payload_error; +assign main_tx_cdc_cdc_asyncfifo_re = main_tx_cdc_cdc_source_ready; +assign main_tx_cdc_cdc_graycounter0_ce = (main_tx_cdc_cdc_asyncfifo_writable & main_tx_cdc_cdc_asyncfifo_we); +assign main_tx_cdc_cdc_graycounter1_ce = (main_tx_cdc_cdc_asyncfifo_readable & main_tx_cdc_cdc_asyncfifo_re); +assign main_tx_cdc_cdc_asyncfifo_writable = (((main_tx_cdc_cdc_graycounter0_q[5] == main_tx_cdc_cdc_consume_wdomain[5]) | (main_tx_cdc_cdc_graycounter0_q[4] == main_tx_cdc_cdc_consume_wdomain[4])) | (main_tx_cdc_cdc_graycounter0_q[3:0] != main_tx_cdc_cdc_consume_wdomain[3:0])); +assign main_tx_cdc_cdc_asyncfifo_readable = (main_tx_cdc_cdc_graycounter1_q != main_tx_cdc_cdc_produce_rdomain); +assign main_tx_cdc_cdc_wrport_adr = main_tx_cdc_cdc_graycounter0_q_binary[4:0]; +assign main_tx_cdc_cdc_wrport_dat_w = main_tx_cdc_cdc_asyncfifo_din; +assign main_tx_cdc_cdc_wrport_we = main_tx_cdc_cdc_graycounter0_ce; +assign main_tx_cdc_cdc_rdport_adr = main_tx_cdc_cdc_graycounter1_q_next_binary[4:0]; +assign main_tx_cdc_cdc_asyncfifo_dout = main_tx_cdc_cdc_rdport_dat_r; +always @(*) begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (main_tx_cdc_cdc_graycounter0_ce) begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= (main_tx_cdc_cdc_graycounter0_q_binary + 1'd1); + end else begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= main_tx_cdc_cdc_graycounter0_q_binary; + end +end +assign main_tx_cdc_cdc_graycounter0_q_next = (main_tx_cdc_cdc_graycounter0_q_next_binary ^ main_tx_cdc_cdc_graycounter0_q_next_binary[5:1]); +always @(*) begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (main_tx_cdc_cdc_graycounter1_ce) begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= (main_tx_cdc_cdc_graycounter1_q_binary + 1'd1); + end else begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= main_tx_cdc_cdc_graycounter1_q_binary; + end +end +assign main_tx_cdc_cdc_graycounter1_q_next = (main_tx_cdc_cdc_graycounter1_q_next_binary ^ main_tx_cdc_cdc_graycounter1_q_next_binary[5:1]); +assign main_tx_converter_converter_sink_valid = main_tx_converter_sink_valid; +assign main_tx_converter_converter_sink_first = main_tx_converter_sink_first; +assign main_tx_converter_converter_sink_last = main_tx_converter_sink_last; +assign main_tx_converter_sink_ready = main_tx_converter_converter_sink_ready; +always @(*) begin + main_tx_converter_converter_sink_payload_data <= 40'd0; + main_tx_converter_converter_sink_payload_data[7:0] <= main_tx_converter_sink_payload_data[7:0]; + main_tx_converter_converter_sink_payload_data[8] <= main_tx_converter_sink_payload_last_be[0]; + main_tx_converter_converter_sink_payload_data[9] <= main_tx_converter_sink_payload_error[0]; + main_tx_converter_converter_sink_payload_data[17:10] <= main_tx_converter_sink_payload_data[15:8]; + main_tx_converter_converter_sink_payload_data[18] <= main_tx_converter_sink_payload_last_be[1]; + main_tx_converter_converter_sink_payload_data[19] <= main_tx_converter_sink_payload_error[1]; + main_tx_converter_converter_sink_payload_data[27:20] <= main_tx_converter_sink_payload_data[23:16]; + main_tx_converter_converter_sink_payload_data[28] <= main_tx_converter_sink_payload_last_be[2]; + main_tx_converter_converter_sink_payload_data[29] <= main_tx_converter_sink_payload_error[2]; + main_tx_converter_converter_sink_payload_data[37:30] <= main_tx_converter_sink_payload_data[31:24]; + main_tx_converter_converter_sink_payload_data[38] <= main_tx_converter_sink_payload_last_be[3]; + main_tx_converter_converter_sink_payload_data[39] <= main_tx_converter_sink_payload_error[3]; +end +assign main_tx_converter_source_valid = main_tx_converter_source_source_valid; +assign main_tx_converter_source_first = main_tx_converter_source_source_first; +assign main_tx_converter_source_last = main_tx_converter_source_source_last; +assign main_tx_converter_source_source_ready = main_tx_converter_source_ready; +assign {main_tx_converter_source_payload_error, main_tx_converter_source_payload_last_be, main_tx_converter_source_payload_data} = main_tx_converter_source_source_payload_data; +assign main_tx_converter_source_source_valid = main_tx_converter_converter_source_valid; +assign main_tx_converter_converter_source_ready = main_tx_converter_source_source_ready; +assign main_tx_converter_source_source_first = main_tx_converter_converter_source_first; +assign main_tx_converter_source_source_last = main_tx_converter_converter_source_last; +assign main_tx_converter_source_source_payload_data = main_tx_converter_converter_source_payload_data; +assign main_tx_converter_converter_first = (main_tx_converter_converter_mux == 1'd0); +assign main_tx_converter_converter_last = (main_tx_converter_converter_mux == 2'd3); +assign main_tx_converter_converter_source_valid = main_tx_converter_converter_sink_valid; +assign main_tx_converter_converter_source_first = (main_tx_converter_converter_sink_first & main_tx_converter_converter_first); +assign main_tx_converter_converter_source_last = (main_tx_converter_converter_sink_last & main_tx_converter_converter_last); +assign main_tx_converter_converter_sink_ready = (main_tx_converter_converter_last & main_tx_converter_converter_source_ready); +always @(*) begin + main_tx_converter_converter_source_payload_data <= 10'd0; + case (main_tx_converter_converter_mux) + 1'd0: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[9:0]; + end + 1'd1: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[19:10]; + end + 2'd2: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[29:20]; + end + default: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[39:30]; + end + endcase +end +assign main_tx_converter_converter_source_payload_valid_token_count = main_tx_converter_converter_last; +always @(*) begin + builder_txdatapath_liteethmactxlastbe_next_state <= 1'd0; + main_tx_last_be_sink_ready <= 1'd0; + main_tx_last_be_source_first <= 1'd0; + main_tx_last_be_source_last <= 1'd0; + main_tx_last_be_source_payload_data <= 8'd0; + main_tx_last_be_source_payload_error <= 1'd0; + main_tx_last_be_source_payload_last_be <= 1'd0; + main_tx_last_be_source_valid <= 1'd0; + builder_txdatapath_liteethmactxlastbe_next_state <= builder_txdatapath_liteethmactxlastbe_state; + case (builder_txdatapath_liteethmactxlastbe_state) + 1'd1: begin + main_tx_last_be_sink_ready <= 1'd1; + if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_last)) begin + builder_txdatapath_liteethmactxlastbe_next_state <= 1'd0; + end + end + default: begin + main_tx_last_be_source_valid <= main_tx_last_be_sink_valid; + main_tx_last_be_sink_ready <= main_tx_last_be_source_ready; + main_tx_last_be_source_first <= main_tx_last_be_sink_first; + main_tx_last_be_source_last <= main_tx_last_be_sink_last; + main_tx_last_be_source_payload_data <= main_tx_last_be_sink_payload_data; + main_tx_last_be_source_payload_last_be <= main_tx_last_be_sink_payload_last_be; + main_tx_last_be_source_payload_error <= main_tx_last_be_sink_payload_error; + main_tx_last_be_source_last <= (main_tx_last_be_sink_payload_last_be != 1'd0); + if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_ready)) begin + if ((main_tx_last_be_source_last & (~main_tx_last_be_sink_last))) begin + builder_txdatapath_liteethmactxlastbe_next_state <= 1'd1; + end + end + end + endcase +end +assign main_tx_padding_counter_done = (main_tx_padding_counter >= 6'd59); +always @(*) begin + builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 16'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd0; + main_tx_padding_sink_ready <= 1'd0; + main_tx_padding_source_first <= 1'd0; + main_tx_padding_source_last <= 1'd0; + main_tx_padding_source_payload_data <= 8'd0; + main_tx_padding_source_payload_error <= 1'd0; + main_tx_padding_source_payload_last_be <= 1'd0; + main_tx_padding_source_valid <= 1'd0; + builder_txdatapath_liteethmacpaddinginserter_next_state <= builder_txdatapath_liteethmacpaddinginserter_state; + case (builder_txdatapath_liteethmacpaddinginserter_state) + 1'd1: begin + main_tx_padding_source_valid <= 1'd1; + if (main_tx_padding_counter_done) begin + main_tx_padding_source_payload_last_be <= 1'd1; + main_tx_padding_source_last <= 1'd1; + end + main_tx_padding_source_payload_data <= 1'd0; + if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (main_tx_padding_counter_done) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + end + end + end + default: begin + main_tx_padding_source_valid <= main_tx_padding_sink_valid; + main_tx_padding_sink_ready <= main_tx_padding_source_ready; + main_tx_padding_source_first <= main_tx_padding_sink_first; + main_tx_padding_source_last <= main_tx_padding_sink_last; + main_tx_padding_source_payload_data <= main_tx_padding_sink_payload_data; + main_tx_padding_source_payload_last_be <= main_tx_padding_sink_payload_last_be; + main_tx_padding_source_payload_error <= main_tx_padding_sink_payload_error; + if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (main_tx_padding_sink_last) begin + if ((~main_tx_padding_counter_done)) begin + main_tx_padding_source_last <= 1'd0; + main_tx_padding_source_payload_last_be <= 1'd0; + builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd1; + end else begin + if (((main_tx_padding_counter == 6'd59) & (main_tx_padding_sink_payload_last_be < 1'd1))) begin + main_tx_padding_source_payload_last_be <= 1'd1; + end else begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + end + end + end + end + end + endcase +end +assign main_tx_crc_data0 = main_tx_crc_sink_payload_data; +assign main_tx_crc_be = main_tx_crc_sink_payload_last_be; +assign main_tx_crc_cnt_done = (main_tx_crc_cnt == 1'd0); +assign main_tx_crc_sink_valid = main_tx_crc_source_source_valid; +assign main_tx_crc_source_source_ready = main_tx_crc_sink_ready; +assign main_tx_crc_sink_first = main_tx_crc_source_source_first; +assign main_tx_crc_sink_last = main_tx_crc_source_source_last; +assign main_tx_crc_sink_payload_data = main_tx_crc_source_source_payload_data; +assign main_tx_crc_sink_payload_last_be = main_tx_crc_source_source_payload_last_be; +assign main_tx_crc_sink_payload_error = main_tx_crc_source_source_payload_error; +assign main_tx_crc_data1 = main_tx_crc_data0[7:0]; +assign main_tx_crc_crc_prev = main_tx_crc_reg; +always @(*) begin + main_tx_crc_error <= 1'd0; + main_tx_crc_value <= 32'd0; + if (main_tx_crc_be) begin + main_tx_crc_value <= {builder_t_slice_proxy31[0], builder_t_slice_proxy30[1], builder_t_slice_proxy29[2], builder_t_slice_proxy28[3], builder_t_slice_proxy27[4], builder_t_slice_proxy26[5], builder_t_slice_proxy25[6], builder_t_slice_proxy24[7], builder_t_slice_proxy23[8], builder_t_slice_proxy22[9], builder_t_slice_proxy21[10], builder_t_slice_proxy20[11], builder_t_slice_proxy19[12], builder_t_slice_proxy18[13], builder_t_slice_proxy17[14], builder_t_slice_proxy16[15], builder_t_slice_proxy15[16], builder_t_slice_proxy14[17], builder_t_slice_proxy13[18], builder_t_slice_proxy12[19], builder_t_slice_proxy11[20], builder_t_slice_proxy10[21], builder_t_slice_proxy9[22], builder_t_slice_proxy8[23], builder_t_slice_proxy7[24], builder_t_slice_proxy6[25], builder_t_slice_proxy5[26], builder_t_slice_proxy4[27], builder_t_slice_proxy3[28], builder_t_slice_proxy2[29], builder_t_slice_proxy1[30], builder_t_slice_proxy0[31]}; + main_tx_crc_error <= (main_tx_crc_crc_next != 32'd3338984827); + end +end +always @(*) begin + main_tx_crc_crc_next <= 32'd0; + main_tx_crc_crc_next[0] <= (((main_tx_crc_crc_prev[24] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[1] <= (((((((main_tx_crc_crc_prev[25] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[2] <= (((((((((main_tx_crc_crc_prev[26] ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[3] <= (((((((main_tx_crc_crc_prev[27] ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[4] <= (((((((((main_tx_crc_crc_prev[28] ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[5] <= (((((((((((((main_tx_crc_crc_prev[29] ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[6] <= (((((((((((main_tx_crc_crc_prev[30] ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[7] <= (((((((((main_tx_crc_crc_prev[31] ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[8] <= ((((((((main_tx_crc_crc_prev[0] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[9] <= ((((((((main_tx_crc_crc_prev[1] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[10] <= ((((((((main_tx_crc_crc_prev[2] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[11] <= ((((((((main_tx_crc_crc_prev[3] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[12] <= ((((((((((((main_tx_crc_crc_prev[4] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[13] <= ((((((((((((main_tx_crc_crc_prev[5] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[14] <= ((((((((((main_tx_crc_crc_prev[6] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[15] <= ((((((((main_tx_crc_crc_prev[7] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); + main_tx_crc_crc_next[16] <= ((((((main_tx_crc_crc_prev[8] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[17] <= ((((((main_tx_crc_crc_prev[9] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[18] <= ((((((main_tx_crc_crc_prev[10] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[19] <= ((((main_tx_crc_crc_prev[11] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); + main_tx_crc_crc_next[20] <= ((main_tx_crc_crc_prev[12] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]); + main_tx_crc_crc_next[21] <= ((main_tx_crc_crc_prev[13] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]); + main_tx_crc_crc_next[22] <= ((main_tx_crc_crc_prev[14] ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[23] <= ((((((main_tx_crc_crc_prev[15] ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[24] <= ((((((main_tx_crc_crc_prev[16] ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[25] <= ((((main_tx_crc_crc_prev[17] ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[26] <= ((((((((main_tx_crc_crc_prev[18] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[27] <= ((((((((main_tx_crc_crc_prev[19] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[28] <= ((((((main_tx_crc_crc_prev[20] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[29] <= ((((((main_tx_crc_crc_prev[21] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); + main_tx_crc_crc_next[30] <= ((((main_tx_crc_crc_prev[22] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]); + main_tx_crc_crc_next[31] <= ((main_tx_crc_crc_prev[23] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]); +end +always @(*) begin + builder_txdatapath_bufferizeendpoints_next_state <= 2'd0; + main_tx_crc_ce <= 1'd0; + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= 32'd0; + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd0; + main_tx_crc_is_ongoing0 <= 1'd0; + main_tx_crc_is_ongoing1 <= 1'd0; + main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= 1'd0; + main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd0; + main_tx_crc_reset <= 1'd0; + main_tx_crc_sink_ready <= 1'd0; + main_tx_crc_source_first <= 1'd0; + main_tx_crc_source_last <= 1'd0; + main_tx_crc_source_payload_data <= 8'd0; + main_tx_crc_source_payload_error <= 1'd0; + main_tx_crc_source_payload_last_be <= 1'd0; + main_tx_crc_source_valid <= 1'd0; + builder_txdatapath_bufferizeendpoints_next_state <= builder_txdatapath_bufferizeendpoints_state; + case (builder_txdatapath_bufferizeendpoints_state) + 1'd1: begin + main_tx_crc_ce <= (main_tx_crc_sink_valid & main_tx_crc_source_ready); + main_tx_crc_source_valid <= main_tx_crc_sink_valid; + main_tx_crc_sink_ready <= main_tx_crc_source_ready; + main_tx_crc_source_first <= main_tx_crc_sink_first; + main_tx_crc_source_last <= main_tx_crc_sink_last; + main_tx_crc_source_payload_data <= main_tx_crc_sink_payload_data; + main_tx_crc_source_payload_last_be <= main_tx_crc_sink_payload_last_be; + main_tx_crc_source_payload_error <= main_tx_crc_sink_payload_error; + main_tx_crc_source_last <= 1'd0; + main_tx_crc_source_payload_last_be <= 1'd0; + if (main_tx_crc_sink_last) begin + if (main_tx_crc_sink_payload_last_be) begin + main_tx_crc_source_payload_data <= builder_complexslicelowerer_slice_proxy[7:0]; + end + if ((1'd0 & (main_tx_crc_sink_payload_last_be <= 4'd15))) begin + main_tx_crc_source_last <= 1'd1; + main_tx_crc_source_payload_last_be <= (main_tx_crc_sink_payload_last_be <<< -3'd3); + end + end else begin + main_tx_crc_ce <= (main_tx_crc_sink_valid & main_tx_crc_source_ready); + end + if (((main_tx_crc_sink_valid & main_tx_crc_sink_last) & main_tx_crc_source_ready)) begin + if ((1'd0 & (main_tx_crc_sink_payload_last_be <= 4'd15))) begin + builder_txdatapath_bufferizeendpoints_next_state <= 1'd0; + end else begin + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= main_tx_crc_value; + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd1; + if (1'd0) begin + main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= (main_tx_crc_sink_payload_last_be >>> 3'd4); + main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + end else begin + main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= main_tx_crc_sink_payload_last_be; + main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + end + builder_txdatapath_bufferizeendpoints_next_state <= 2'd2; + end + end + end + 2'd2: begin + main_tx_crc_source_valid <= 1'd1; + case (main_tx_crc_cnt) + 1'd0: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[31:24]; + end + 1'd1: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[23:16]; + end + 2'd2: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[15:8]; + end + default: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[7:0]; + end + endcase + if (main_tx_crc_cnt_done) begin + main_tx_crc_source_last <= 1'd1; + if (main_tx_crc_source_ready) begin + builder_txdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + main_tx_crc_is_ongoing1 <= 1'd1; + end + default: begin + main_tx_crc_reset <= 1'd1; + main_tx_crc_sink_ready <= 1'd1; + if (main_tx_crc_sink_valid) begin + main_tx_crc_sink_ready <= 1'd0; + builder_txdatapath_bufferizeendpoints_next_state <= 1'd1; + end + main_tx_crc_is_ongoing0 <= 1'd1; + end + endcase +end +assign main_tx_crc_pipe_valid_sink_ready = ((~main_tx_crc_pipe_valid_source_valid) | main_tx_crc_pipe_valid_source_ready); +assign main_tx_crc_pipe_valid_sink_valid = main_tx_crc_sink_sink_valid; +assign main_tx_crc_sink_sink_ready = main_tx_crc_pipe_valid_sink_ready; +assign main_tx_crc_pipe_valid_sink_first = main_tx_crc_sink_sink_first; +assign main_tx_crc_pipe_valid_sink_last = main_tx_crc_sink_sink_last; +assign main_tx_crc_pipe_valid_sink_payload_data = main_tx_crc_sink_sink_payload_data; +assign main_tx_crc_pipe_valid_sink_payload_last_be = main_tx_crc_sink_sink_payload_last_be; +assign main_tx_crc_pipe_valid_sink_payload_error = main_tx_crc_sink_sink_payload_error; +assign main_tx_crc_source_source_valid = main_tx_crc_pipe_valid_source_valid; +assign main_tx_crc_pipe_valid_source_ready = main_tx_crc_source_source_ready; +assign main_tx_crc_source_source_first = main_tx_crc_pipe_valid_source_first; +assign main_tx_crc_source_source_last = main_tx_crc_pipe_valid_source_last; +assign main_tx_crc_source_source_payload_data = main_tx_crc_pipe_valid_source_payload_data; +assign main_tx_crc_source_source_payload_last_be = main_tx_crc_pipe_valid_source_payload_last_be; +assign main_tx_crc_source_source_payload_error = main_tx_crc_pipe_valid_source_payload_error; +assign main_tx_preamble_source_payload_last_be = main_tx_preamble_sink_payload_last_be; +always @(*) begin + builder_txdatapath_liteethmacpreambleinserter_next_state <= 2'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value <= 3'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd0; + main_tx_preamble_sink_ready <= 1'd0; + main_tx_preamble_source_first <= 1'd0; + main_tx_preamble_source_last <= 1'd0; + main_tx_preamble_source_payload_data <= 8'd0; + main_tx_preamble_source_payload_error <= 1'd0; + main_tx_preamble_source_valid <= 1'd0; + main_tx_preamble_source_payload_data <= main_tx_preamble_sink_payload_data; + builder_txdatapath_liteethmacpreambleinserter_next_state <= builder_txdatapath_liteethmacpreambleinserter_state; + case (builder_txdatapath_liteethmacpreambleinserter_state) + 1'd1: begin + main_tx_preamble_source_valid <= 1'd1; + case (main_tx_preamble_count) + 1'd0: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[7:0]; + end + 1'd1: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[15:8]; + end + 2'd2: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[23:16]; + end + 2'd3: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[31:24]; + end + 3'd4: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[39:32]; + end + 3'd5: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[47:40]; + end + 3'd6: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[55:48]; + end + default: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[63:56]; + end + endcase + if (main_tx_preamble_source_ready) begin + if ((main_tx_preamble_count == 3'd7)) begin + builder_txdatapath_liteethmacpreambleinserter_next_state <= 2'd2; + end else begin + main_tx_preamble_count_clockdomainsrenamer2_next_value <= (main_tx_preamble_count + 1'd1); + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + end + end + end + 2'd2: begin + main_tx_preamble_source_valid <= main_tx_preamble_sink_valid; + main_tx_preamble_sink_ready <= main_tx_preamble_source_ready; + main_tx_preamble_source_first <= main_tx_preamble_sink_first; + main_tx_preamble_source_last <= main_tx_preamble_sink_last; + main_tx_preamble_source_payload_error <= main_tx_preamble_sink_payload_error; + if (((main_tx_preamble_sink_valid & main_tx_preamble_sink_last) & main_tx_preamble_source_ready)) begin + builder_txdatapath_liteethmacpreambleinserter_next_state <= 1'd0; + end + end + default: begin + main_tx_preamble_sink_ready <= 1'd1; + main_tx_preamble_count_clockdomainsrenamer2_next_value <= 1'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + if (main_tx_preamble_sink_valid) begin + main_tx_preamble_sink_ready <= 1'd0; + builder_txdatapath_liteethmacpreambleinserter_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + builder_txdatapath_liteethmacgap_next_state <= 1'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value <= 4'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd0; + main_tx_gap_sink_ready <= 1'd0; + main_tx_gap_source_first <= 1'd0; + main_tx_gap_source_last <= 1'd0; + main_tx_gap_source_payload_data <= 8'd0; + main_tx_gap_source_payload_error <= 1'd0; + main_tx_gap_source_payload_last_be <= 1'd0; + main_tx_gap_source_valid <= 1'd0; + builder_txdatapath_liteethmacgap_next_state <= builder_txdatapath_liteethmacgap_state; + case (builder_txdatapath_liteethmacgap_state) + 1'd1: begin + main_tx_gap_counter_clockdomainsrenamer3_next_value <= (main_tx_gap_counter + 1'd1); + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + if ((main_tx_gap_counter == 4'd11)) begin + builder_txdatapath_liteethmacgap_next_state <= 1'd0; + end + end + default: begin + main_tx_gap_counter_clockdomainsrenamer3_next_value <= 1'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + main_tx_gap_source_valid <= main_tx_gap_sink_valid; + main_tx_gap_sink_ready <= main_tx_gap_source_ready; + main_tx_gap_source_first <= main_tx_gap_sink_first; + main_tx_gap_source_last <= main_tx_gap_sink_last; + main_tx_gap_source_payload_data <= main_tx_gap_sink_payload_data; + main_tx_gap_source_payload_last_be <= main_tx_gap_sink_payload_last_be; + main_tx_gap_source_payload_error <= main_tx_gap_sink_payload_error; + if (((main_tx_gap_sink_valid & main_tx_gap_sink_last) & main_tx_gap_sink_ready)) begin + builder_txdatapath_liteethmacgap_next_state <= 1'd1; + end + end + endcase +end +assign main_tx_cdc_sink_sink_valid = main_sink_valid; +assign main_sink_ready = main_tx_cdc_sink_sink_ready; +assign main_tx_cdc_sink_sink_first = main_sink_first; +assign main_tx_cdc_sink_sink_last = main_sink_last; +assign main_tx_cdc_sink_sink_payload_data = main_sink_payload_data; +assign main_tx_cdc_sink_sink_payload_last_be = main_sink_payload_last_be; +assign main_tx_cdc_sink_sink_payload_error = main_sink_payload_error; +assign main_tx_converter_sink_valid = main_tx_cdc_source_source_valid; +assign main_tx_cdc_source_source_ready = main_tx_converter_sink_ready; +assign main_tx_converter_sink_first = main_tx_cdc_source_source_first; +assign main_tx_converter_sink_last = main_tx_cdc_source_source_last; +assign main_tx_converter_sink_payload_data = main_tx_cdc_source_source_payload_data; +assign main_tx_converter_sink_payload_last_be = main_tx_cdc_source_source_payload_last_be; +assign main_tx_converter_sink_payload_error = main_tx_cdc_source_source_payload_error; +assign main_tx_last_be_sink_valid = main_tx_converter_source_valid; +assign main_tx_converter_source_ready = main_tx_last_be_sink_ready; +assign main_tx_last_be_sink_first = main_tx_converter_source_first; +assign main_tx_last_be_sink_last = main_tx_converter_source_last; +assign main_tx_last_be_sink_payload_data = main_tx_converter_source_payload_data; +assign main_tx_last_be_sink_payload_last_be = main_tx_converter_source_payload_last_be; +assign main_tx_last_be_sink_payload_error = main_tx_converter_source_payload_error; +assign main_tx_padding_sink_valid = main_tx_last_be_source_valid; +assign main_tx_last_be_source_ready = main_tx_padding_sink_ready; +assign main_tx_padding_sink_first = main_tx_last_be_source_first; +assign main_tx_padding_sink_last = main_tx_last_be_source_last; +assign main_tx_padding_sink_payload_data = main_tx_last_be_source_payload_data; +assign main_tx_padding_sink_payload_last_be = main_tx_last_be_source_payload_last_be; +assign main_tx_padding_sink_payload_error = main_tx_last_be_source_payload_error; +assign main_tx_crc_sink_sink_valid = main_tx_padding_source_valid; +assign main_tx_padding_source_ready = main_tx_crc_sink_sink_ready; +assign main_tx_crc_sink_sink_first = main_tx_padding_source_first; +assign main_tx_crc_sink_sink_last = main_tx_padding_source_last; +assign main_tx_crc_sink_sink_payload_data = main_tx_padding_source_payload_data; +assign main_tx_crc_sink_sink_payload_last_be = main_tx_padding_source_payload_last_be; +assign main_tx_crc_sink_sink_payload_error = main_tx_padding_source_payload_error; +assign main_tx_preamble_sink_valid = main_tx_crc_source_valid; +assign main_tx_crc_source_ready = main_tx_preamble_sink_ready; +assign main_tx_preamble_sink_first = main_tx_crc_source_first; +assign main_tx_preamble_sink_last = main_tx_crc_source_last; +assign main_tx_preamble_sink_payload_data = main_tx_crc_source_payload_data; +assign main_tx_preamble_sink_payload_last_be = main_tx_crc_source_payload_last_be; +assign main_tx_preamble_sink_payload_error = main_tx_crc_source_payload_error; +assign main_tx_gap_sink_valid = main_tx_preamble_source_valid; +assign main_tx_preamble_source_ready = main_tx_gap_sink_ready; +assign main_tx_gap_sink_first = main_tx_preamble_source_first; +assign main_tx_gap_sink_last = main_tx_preamble_source_last; +assign main_tx_gap_sink_payload_data = main_tx_preamble_source_payload_data; +assign main_tx_gap_sink_payload_last_be = main_tx_preamble_source_payload_last_be; +assign main_tx_gap_sink_payload_error = main_tx_preamble_source_payload_error; +assign main_maccore_ethphy_sink_valid = main_tx_gap_source_valid; +assign main_tx_gap_source_ready = main_maccore_ethphy_sink_ready; +assign main_maccore_ethphy_sink_first = main_tx_gap_source_first; +assign main_maccore_ethphy_sink_last = main_tx_gap_source_last; +assign main_maccore_ethphy_sink_payload_data = main_tx_gap_source_payload_data; +assign main_maccore_ethphy_sink_payload_last_be = main_tx_gap_source_payload_last_be; +assign main_maccore_ethphy_sink_payload_error = main_tx_gap_source_payload_error; +assign main_pulsesynchronizer0_i = main_rx_preamble_error; +assign main_pulsesynchronizer1_i = main_liteethmaccrc32checker_error; +assign main_rx_preamble_source_payload_data = main_rx_preamble_sink_payload_data; +assign main_rx_preamble_source_payload_last_be = main_rx_preamble_sink_payload_last_be; +always @(*) begin + builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + main_rx_preamble_error <= 1'd0; + main_rx_preamble_sink_ready <= 1'd0; + main_rx_preamble_source_first <= 1'd0; + main_rx_preamble_source_last <= 1'd0; + main_rx_preamble_source_payload_error <= 1'd0; + main_rx_preamble_source_valid <= 1'd0; + builder_rxdatapath_liteethmacpreamblechecker_next_state <= builder_rxdatapath_liteethmacpreamblechecker_state; + case (builder_rxdatapath_liteethmacpreamblechecker_state) + 1'd1: begin + main_rx_preamble_source_valid <= main_rx_preamble_sink_valid; + main_rx_preamble_sink_ready <= main_rx_preamble_source_ready; + main_rx_preamble_source_first <= main_rx_preamble_sink_first; + main_rx_preamble_source_last <= main_rx_preamble_sink_last; + main_rx_preamble_source_payload_error <= main_rx_preamble_sink_payload_error; + if (((main_rx_preamble_source_valid & main_rx_preamble_source_last) & main_rx_preamble_source_ready)) begin + builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + end + end + default: begin + main_rx_preamble_sink_ready <= 1'd1; + if (((main_rx_preamble_sink_valid & (~main_rx_preamble_sink_last)) & (main_rx_preamble_sink_payload_data == main_rx_preamble_preamble[63:56]))) begin + builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd1; + end + if ((main_rx_preamble_sink_valid & main_rx_preamble_sink_last)) begin + main_rx_preamble_error <= 1'd1; + end + end + endcase +end +assign main_pulsesynchronizer0_o = (main_pulsesynchronizer0_toggle_o ^ main_pulsesynchronizer0_toggle_o_r); assign main_liteethmaccrc32checker_fifo_full = (main_liteethmaccrc32checker_syncfifo_level == 3'd4); assign main_liteethmaccrc32checker_fifo_in = (main_liteethmaccrc32checker_sink_sink_valid & ((~main_liteethmaccrc32checker_fifo_full) | main_liteethmaccrc32checker_fifo_out)); assign main_liteethmaccrc32checker_fifo_out = (main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready); @@ -1314,72 +2024,70 @@ assign main_liteethmaccrc32checker_syncfifo_sink_payload_data = main_liteethmacc assign main_liteethmaccrc32checker_syncfifo_sink_payload_last_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; assign main_liteethmaccrc32checker_syncfifo_sink_payload_error = main_liteethmaccrc32checker_sink_sink_payload_error; always @(*) begin - main_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; - main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_sink_sink_valid; - main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_fifo_in; + main_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; + main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_sink_sink_valid; + main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_fifo_in; end always @(*) begin - main_liteethmaccrc32checker_sink_sink_ready <= 1'd0; - main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_syncfifo_sink_ready; - main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_fifo_in; + main_liteethmaccrc32checker_sink_sink_ready <= 1'd0; + main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_syncfifo_sink_ready; + main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_fifo_in; end -assign main_liteethmaccrc32checker_source_source_valid = (main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_fifo_full); -assign main_liteethmaccrc32checker_source_source_last = main_liteethmaccrc32checker_sink_sink_last; -assign main_liteethmaccrc32checker_syncfifo_source_ready = main_liteethmaccrc32checker_fifo_out; +assign main_liteethmaccrc32checker_crc_data0 = main_liteethmaccrc32checker_sink_sink_payload_data; +assign main_liteethmaccrc32checker_crc_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; +assign main_liteethmaccrc32checker_source_source_first = main_liteethmaccrc32checker_syncfifo_source_first; assign main_liteethmaccrc32checker_source_source_payload_data = main_liteethmaccrc32checker_syncfifo_source_payload_data; -assign main_liteethmaccrc32checker_source_source_payload_last_be = main_liteethmaccrc32checker_syncfifo_source_payload_last_be; +assign main_liteethmaccrc32checker_sink_sink_valid = main_bufferizeendpoints_source_source_valid; +assign main_bufferizeendpoints_source_source_ready = main_liteethmaccrc32checker_sink_sink_ready; +assign main_liteethmaccrc32checker_sink_sink_first = main_bufferizeendpoints_source_source_first; +assign main_liteethmaccrc32checker_sink_sink_last = main_bufferizeendpoints_source_source_last; +assign main_liteethmaccrc32checker_sink_sink_payload_data = main_bufferizeendpoints_source_source_payload_data; +assign main_liteethmaccrc32checker_sink_sink_payload_last_be = main_bufferizeendpoints_source_source_payload_last_be; +assign main_liteethmaccrc32checker_sink_sink_payload_error = main_bufferizeendpoints_source_source_payload_error; +assign main_liteethmaccrc32checker_crc_data1 = main_liteethmaccrc32checker_crc_data0[7:0]; +assign main_liteethmaccrc32checker_crc_crc_prev = main_liteethmaccrc32checker_crc_reg; always @(*) begin - main_liteethmaccrc32checker_source_source_payload_error <= 1'd0; - main_liteethmaccrc32checker_source_source_payload_error <= main_liteethmaccrc32checker_syncfifo_source_payload_error; - main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_sink_sink_payload_error | main_liteethmaccrc32checker_crc_error); + main_liteethmaccrc32checker_crc_error0 <= 1'd0; + main_liteethmaccrc32checker_crc_value <= 32'd0; + if (main_liteethmaccrc32checker_crc_be) begin + main_liteethmaccrc32checker_crc_value <= {builder_t_slice_proxy63[0], builder_t_slice_proxy62[1], builder_t_slice_proxy61[2], builder_t_slice_proxy60[3], builder_t_slice_proxy59[4], builder_t_slice_proxy58[5], builder_t_slice_proxy57[6], builder_t_slice_proxy56[7], builder_t_slice_proxy55[8], builder_t_slice_proxy54[9], builder_t_slice_proxy53[10], builder_t_slice_proxy52[11], builder_t_slice_proxy51[12], builder_t_slice_proxy50[13], builder_t_slice_proxy49[14], builder_t_slice_proxy48[15], builder_t_slice_proxy47[16], builder_t_slice_proxy46[17], builder_t_slice_proxy45[18], builder_t_slice_proxy44[19], builder_t_slice_proxy43[20], builder_t_slice_proxy42[21], builder_t_slice_proxy41[22], builder_t_slice_proxy40[23], builder_t_slice_proxy39[24], builder_t_slice_proxy38[25], builder_t_slice_proxy37[26], builder_t_slice_proxy36[27], builder_t_slice_proxy35[28], builder_t_slice_proxy34[29], builder_t_slice_proxy33[30], builder_t_slice_proxy32[31]}; + main_liteethmaccrc32checker_crc_error0 <= (main_liteethmaccrc32checker_crc_crc_next != 32'd3338984827); + end end -assign main_liteethmaccrc32checker_error = ((main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_last) & main_liteethmaccrc32checker_crc_error); -assign main_liteethmaccrc32checker_crc_data0 = main_liteethmaccrc32checker_sink_sink_payload_data; -assign main_liteethmaccrc32checker_sink_sink_valid = main_crc32_checker_source_valid; -assign main_crc32_checker_source_ready = main_liteethmaccrc32checker_sink_sink_ready; -assign main_liteethmaccrc32checker_sink_sink_first = main_crc32_checker_source_first; -assign main_liteethmaccrc32checker_sink_sink_last = main_crc32_checker_source_last; -assign main_liteethmaccrc32checker_sink_sink_payload_data = main_crc32_checker_source_payload_data; -assign main_liteethmaccrc32checker_sink_sink_payload_last_be = main_crc32_checker_source_payload_last_be; -assign main_liteethmaccrc32checker_sink_sink_payload_error = main_crc32_checker_source_payload_error; -assign main_liteethmaccrc32checker_crc_data1 = main_liteethmaccrc32checker_crc_data0; -assign main_liteethmaccrc32checker_crc_last = main_liteethmaccrc32checker_crc_reg; -assign main_liteethmaccrc32checker_crc_value = (~{main_liteethmaccrc32checker_crc_reg[0], main_liteethmaccrc32checker_crc_reg[1], main_liteethmaccrc32checker_crc_reg[2], main_liteethmaccrc32checker_crc_reg[3], main_liteethmaccrc32checker_crc_reg[4], main_liteethmaccrc32checker_crc_reg[5], main_liteethmaccrc32checker_crc_reg[6], main_liteethmaccrc32checker_crc_reg[7], main_liteethmaccrc32checker_crc_reg[8], main_liteethmaccrc32checker_crc_reg[9], main_liteethmaccrc32checker_crc_reg[10], main_liteethmaccrc32checker_crc_reg[11], main_liteethmaccrc32checker_crc_reg[12], main_liteethmaccrc32checker_crc_reg[13], main_liteethmaccrc32checker_crc_reg[14], main_liteethmaccrc32checker_crc_reg[15], main_liteethmaccrc32checker_crc_reg[16], main_liteethmaccrc32checker_crc_reg[17], main_liteethmaccrc32checker_crc_reg[18], main_liteethmaccrc32checker_crc_reg[19], main_liteethmaccrc32checker_crc_reg[20], main_liteethmaccrc32checker_crc_reg[21], main_liteethmaccrc32checker_crc_reg[22], main_liteethmaccrc32checker_crc_reg[23], main_liteethmaccrc32checker_crc_reg[24], main_liteethmaccrc32checker_crc_reg[25], main_liteethmaccrc32checker_crc_reg[26], main_liteethmaccrc32checker_crc_reg[27], main_liteethmaccrc32checker_crc_reg[28], main_liteethmaccrc32checker_crc_reg[29], main_liteethmaccrc32checker_crc_reg[30], main_liteethmaccrc32checker_crc_reg[31]}); -assign main_liteethmaccrc32checker_crc_error = (main_liteethmaccrc32checker_crc_next != 32'd3338984827); -always @(*) begin - main_liteethmaccrc32checker_crc_next <= 32'd0; - main_liteethmaccrc32checker_crc_next[0] <= (((main_liteethmaccrc32checker_crc_last[24] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[1] <= (((((((main_liteethmaccrc32checker_crc_last[25] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[2] <= (((((((((main_liteethmaccrc32checker_crc_last[26] ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[3] <= (((((((main_liteethmaccrc32checker_crc_last[27] ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[4] <= (((((((((main_liteethmaccrc32checker_crc_last[28] ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[5] <= (((((((((((((main_liteethmaccrc32checker_crc_last[29] ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[6] <= (((((((((((main_liteethmaccrc32checker_crc_last[30] ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[7] <= (((((((((main_liteethmaccrc32checker_crc_last[31] ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[8] <= ((((((((main_liteethmaccrc32checker_crc_last[0] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[9] <= ((((((((main_liteethmaccrc32checker_crc_last[1] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[10] <= ((((((((main_liteethmaccrc32checker_crc_last[2] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[11] <= ((((((((main_liteethmaccrc32checker_crc_last[3] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[12] <= ((((((((((((main_liteethmaccrc32checker_crc_last[4] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[13] <= ((((((((((((main_liteethmaccrc32checker_crc_last[5] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[14] <= ((((((((((main_liteethmaccrc32checker_crc_last[6] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_next[15] <= ((((((((main_liteethmaccrc32checker_crc_last[7] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); - main_liteethmaccrc32checker_crc_next[16] <= ((((((main_liteethmaccrc32checker_crc_last[8] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[17] <= ((((((main_liteethmaccrc32checker_crc_last[9] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[18] <= ((((((main_liteethmaccrc32checker_crc_last[10] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_next[19] <= ((((main_liteethmaccrc32checker_crc_last[11] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); - main_liteethmaccrc32checker_crc_next[20] <= ((main_liteethmaccrc32checker_crc_last[12] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); - main_liteethmaccrc32checker_crc_next[21] <= ((main_liteethmaccrc32checker_crc_last[13] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); - main_liteethmaccrc32checker_crc_next[22] <= ((main_liteethmaccrc32checker_crc_last[14] ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[23] <= ((((((main_liteethmaccrc32checker_crc_last[15] ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[24] <= ((((((main_liteethmaccrc32checker_crc_last[16] ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[25] <= ((((main_liteethmaccrc32checker_crc_last[17] ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_next[26] <= ((((((((main_liteethmaccrc32checker_crc_last[18] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[27] <= ((((((((main_liteethmaccrc32checker_crc_last[19] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[28] <= ((((((main_liteethmaccrc32checker_crc_last[20] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_next[29] <= ((((((main_liteethmaccrc32checker_crc_last[21] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); - main_liteethmaccrc32checker_crc_next[30] <= ((((main_liteethmaccrc32checker_crc_last[22] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); - main_liteethmaccrc32checker_crc_next[31] <= ((main_liteethmaccrc32checker_crc_last[23] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); +always @(*) begin + main_liteethmaccrc32checker_crc_crc_next <= 32'd0; + main_liteethmaccrc32checker_crc_crc_next[0] <= (((main_liteethmaccrc32checker_crc_crc_prev[24] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[1] <= (((((((main_liteethmaccrc32checker_crc_crc_prev[25] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[2] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[26] ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[3] <= (((((((main_liteethmaccrc32checker_crc_crc_prev[27] ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[4] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[28] ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[5] <= (((((((((((((main_liteethmaccrc32checker_crc_crc_prev[29] ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[6] <= (((((((((((main_liteethmaccrc32checker_crc_crc_prev[30] ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[7] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[31] ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[8] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[0] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[9] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[1] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[10] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[2] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[11] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[3] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[12] <= ((((((((((((main_liteethmaccrc32checker_crc_crc_prev[4] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[13] <= ((((((((((((main_liteethmaccrc32checker_crc_crc_prev[5] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[14] <= ((((((((((main_liteethmaccrc32checker_crc_crc_prev[6] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[15] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[7] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); + main_liteethmaccrc32checker_crc_crc_next[16] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[8] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[17] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[9] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[18] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[10] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[19] <= ((((main_liteethmaccrc32checker_crc_crc_prev[11] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); + main_liteethmaccrc32checker_crc_crc_next[20] <= ((main_liteethmaccrc32checker_crc_crc_prev[12] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); + main_liteethmaccrc32checker_crc_crc_next[21] <= ((main_liteethmaccrc32checker_crc_crc_prev[13] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); + main_liteethmaccrc32checker_crc_crc_next[22] <= ((main_liteethmaccrc32checker_crc_crc_prev[14] ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[23] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[15] ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[24] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[16] ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[25] <= ((((main_liteethmaccrc32checker_crc_crc_prev[17] ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[26] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[18] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[27] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[19] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[28] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[20] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[29] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[21] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); + main_liteethmaccrc32checker_crc_crc_next[30] <= ((((main_liteethmaccrc32checker_crc_crc_prev[22] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); + main_liteethmaccrc32checker_crc_crc_next[31] <= ((main_liteethmaccrc32checker_crc_crc_prev[23] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); end assign main_liteethmaccrc32checker_syncfifo_syncfifo_din = {main_liteethmaccrc32checker_syncfifo_fifo_in_last, main_liteethmaccrc32checker_syncfifo_fifo_in_first, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data}; assign {main_liteethmaccrc32checker_syncfifo_fifo_out_last, main_liteethmaccrc32checker_syncfifo_fifo_out_first, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = main_liteethmaccrc32checker_syncfifo_syncfifo_dout; @@ -1398,12 +2106,12 @@ assign main_liteethmaccrc32checker_syncfifo_source_payload_last_be = main_liteet assign main_liteethmaccrc32checker_syncfifo_source_payload_error = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; assign main_liteethmaccrc32checker_syncfifo_syncfifo_re = main_liteethmaccrc32checker_syncfifo_source_ready; always @(*) begin - main_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; - if (main_liteethmaccrc32checker_syncfifo_replace) begin - main_liteethmaccrc32checker_syncfifo_wrport_adr <= (main_liteethmaccrc32checker_syncfifo_produce - 1'd1); - end else begin - main_liteethmaccrc32checker_syncfifo_wrport_adr <= main_liteethmaccrc32checker_syncfifo_produce; - end + main_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; + if (main_liteethmaccrc32checker_syncfifo_replace) begin + main_liteethmaccrc32checker_syncfifo_wrport_adr <= (main_liteethmaccrc32checker_syncfifo_produce - 1'd1); + end else begin + main_liteethmaccrc32checker_syncfifo_wrport_adr <= main_liteethmaccrc32checker_syncfifo_produce; + end end assign main_liteethmaccrc32checker_syncfifo_wrport_dat_w = main_liteethmaccrc32checker_syncfifo_syncfifo_din; assign main_liteethmaccrc32checker_syncfifo_wrport_we = (main_liteethmaccrc32checker_syncfifo_syncfifo_we & (main_liteethmaccrc32checker_syncfifo_syncfifo_writable | main_liteethmaccrc32checker_syncfifo_replace)); @@ -1413,126 +2121,99 @@ assign main_liteethmaccrc32checker_syncfifo_syncfifo_dout = main_liteethmaccrc32 assign main_liteethmaccrc32checker_syncfifo_syncfifo_writable = (main_liteethmaccrc32checker_syncfifo_level != 3'd5); assign main_liteethmaccrc32checker_syncfifo_syncfifo_readable = (main_liteethmaccrc32checker_syncfifo_level != 1'd0); always @(*) begin - builder_liteethmaccrc32checker_next_state <= 2'd0; - main_liteethmaccrc32checker_crc_ce <= 1'd0; - main_liteethmaccrc32checker_crc_reset <= 1'd0; - main_liteethmaccrc32checker_fifo_reset <= 1'd0; - builder_liteethmaccrc32checker_next_state <= builder_liteethmaccrc32checker_state; - case (builder_liteethmaccrc32checker_state) - 1'd1: begin - if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin - main_liteethmaccrc32checker_crc_ce <= 1'd1; - builder_liteethmaccrc32checker_next_state <= 2'd2; - end - end - 2'd2: begin - if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin - main_liteethmaccrc32checker_crc_ce <= 1'd1; - if (main_liteethmaccrc32checker_sink_sink_last) begin - builder_liteethmaccrc32checker_next_state <= 1'd0; - end - end - end - default: begin - main_liteethmaccrc32checker_crc_reset <= 1'd1; - main_liteethmaccrc32checker_fifo_reset <= 1'd1; - builder_liteethmaccrc32checker_next_state <= 1'd1; - end - endcase -end -assign main_crc32_checker_sink_ready = ((~main_crc32_checker_source_valid) | main_crc32_checker_source_ready); -assign main_ps_preamble_error_o = (main_ps_preamble_error_toggle_o ^ main_ps_preamble_error_toggle_o_r); -assign main_ps_crc_error_o = (main_ps_crc_error_toggle_o ^ main_ps_crc_error_toggle_o_r); -assign main_padding_inserter_counter_done = (main_padding_inserter_counter >= 6'd59); -always @(*) begin - builder_liteethmacpaddinginserter_next_state <= 1'd0; - main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 16'd0; - main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd0; - main_padding_inserter_sink_ready <= 1'd0; - main_padding_inserter_source_valid <= 1'd0; - main_padding_inserter_source_first <= 1'd0; - main_padding_inserter_source_last <= 1'd0; - main_padding_inserter_source_payload_data <= 8'd0; - main_padding_inserter_source_payload_last_be <= 1'd0; - main_padding_inserter_source_payload_error <= 1'd0; - builder_liteethmacpaddinginserter_next_state <= builder_liteethmacpaddinginserter_state; - case (builder_liteethmacpaddinginserter_state) - 1'd1: begin - main_padding_inserter_source_valid <= 1'd1; - main_padding_inserter_source_last <= main_padding_inserter_counter_done; - main_padding_inserter_source_payload_data <= 1'd0; - if ((main_padding_inserter_source_valid & main_padding_inserter_source_ready)) begin - main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= (main_padding_inserter_counter + 1'd1); - main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; - if (main_padding_inserter_counter_done) begin - main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0; - main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; - builder_liteethmacpaddinginserter_next_state <= 1'd0; - end - end - end - default: begin - main_padding_inserter_source_valid <= main_padding_inserter_sink_valid; - main_padding_inserter_sink_ready <= main_padding_inserter_source_ready; - main_padding_inserter_source_first <= main_padding_inserter_sink_first; - main_padding_inserter_source_last <= main_padding_inserter_sink_last; - main_padding_inserter_source_payload_data <= main_padding_inserter_sink_payload_data; - main_padding_inserter_source_payload_last_be <= main_padding_inserter_sink_payload_last_be; - main_padding_inserter_source_payload_error <= main_padding_inserter_sink_payload_error; - if ((main_padding_inserter_source_valid & main_padding_inserter_source_ready)) begin - main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= (main_padding_inserter_counter + 1'd1); - main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; - if (main_padding_inserter_sink_last) begin - if ((~main_padding_inserter_counter_done)) begin - main_padding_inserter_source_last <= 1'd0; - builder_liteethmacpaddinginserter_next_state <= 1'd1; - end else begin - main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0; - main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; - end - end - end - end - endcase -end -assign main_padding_checker_source_valid = main_padding_checker_sink_valid; -assign main_padding_checker_sink_ready = main_padding_checker_source_ready; -assign main_padding_checker_source_first = main_padding_checker_sink_first; -assign main_padding_checker_source_last = main_padding_checker_sink_last; -assign main_padding_checker_source_payload_data = main_padding_checker_sink_payload_data; -assign main_padding_checker_source_payload_last_be = main_padding_checker_sink_payload_last_be; -assign main_padding_checker_source_payload_error = main_padding_checker_sink_payload_error; -always @(*) begin - main_tx_last_be_source_last <= 1'd0; - main_tx_last_be_source_payload_data <= 8'd0; - main_tx_last_be_source_payload_error <= 1'd0; - builder_liteethmactxlastbe_next_state <= 1'd0; - main_tx_last_be_source_first <= 1'd0; - main_tx_last_be_source_valid <= 1'd0; - main_tx_last_be_sink_ready <= 1'd0; - builder_liteethmactxlastbe_next_state <= builder_liteethmactxlastbe_state; - case (builder_liteethmactxlastbe_state) - 1'd1: begin - main_tx_last_be_sink_ready <= 1'd1; - if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_last)) begin - builder_liteethmactxlastbe_next_state <= 1'd0; - end - end - default: begin - main_tx_last_be_source_valid <= main_tx_last_be_sink_valid; - main_tx_last_be_sink_ready <= main_tx_last_be_source_ready; - main_tx_last_be_source_first <= main_tx_last_be_sink_first; - main_tx_last_be_source_payload_data <= main_tx_last_be_sink_payload_data; - main_tx_last_be_source_payload_error <= main_tx_last_be_sink_payload_error; - main_tx_last_be_source_last <= main_tx_last_be_sink_payload_last_be; - if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_ready)) begin - if ((main_tx_last_be_sink_payload_last_be & (~main_tx_last_be_sink_last))) begin - builder_liteethmactxlastbe_next_state <= 1'd1; - end - end - end - endcase + builder_rxdatapath_bufferizeendpoints_next_state <= 2'd0; + main_liteethmaccrc32checker_crc_ce <= 1'd0; + main_liteethmaccrc32checker_crc_error1_next_value1 <= 1'd0; + main_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd0; + main_liteethmaccrc32checker_crc_reset <= 1'd0; + main_liteethmaccrc32checker_error <= 1'd0; + main_liteethmaccrc32checker_fifo_reset <= 1'd0; + main_liteethmaccrc32checker_last_be_next_value0 <= 1'd0; + main_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd0; + main_liteethmaccrc32checker_source_source_last <= 1'd0; + main_liteethmaccrc32checker_source_source_payload_error <= 1'd0; + main_liteethmaccrc32checker_source_source_payload_last_be <= 1'd0; + main_liteethmaccrc32checker_source_source_valid <= 1'd0; + main_liteethmaccrc32checker_syncfifo_source_ready <= 1'd0; + main_liteethmaccrc32checker_source_source_payload_error <= main_liteethmaccrc32checker_syncfifo_source_payload_error; + builder_rxdatapath_bufferizeendpoints_next_state <= builder_rxdatapath_bufferizeendpoints_state; + case (builder_rxdatapath_bufferizeendpoints_state) + 1'd1: begin + if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin + main_liteethmaccrc32checker_crc_ce <= 1'd1; + builder_rxdatapath_bufferizeendpoints_next_state <= 2'd2; + end + end + 2'd2: begin + main_liteethmaccrc32checker_syncfifo_source_ready <= main_liteethmaccrc32checker_fifo_out; + main_liteethmaccrc32checker_source_source_valid <= (main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_fifo_full); + if (1'd1) begin + main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_sink_sink_last; + main_liteethmaccrc32checker_source_source_payload_last_be <= main_liteethmaccrc32checker_sink_sink_payload_last_be; + end else begin + if ((main_liteethmaccrc32checker_sink_sink_payload_last_be & 4'd15)) begin + main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_sink_sink_last; + main_liteethmaccrc32checker_source_source_payload_last_be <= (main_liteethmaccrc32checker_sink_sink_payload_last_be <<< -3'd3); + end else begin + main_liteethmaccrc32checker_last_be_next_value0 <= (main_liteethmaccrc32checker_sink_sink_payload_last_be >>> 3'd4); + main_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd1; + main_liteethmaccrc32checker_crc_error1_next_value1 <= main_liteethmaccrc32checker_crc_error0; + main_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd1; + end + end + main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_sink_sink_payload_error | {1{(main_liteethmaccrc32checker_crc_error0 & main_liteethmaccrc32checker_sink_sink_last)}}); + main_liteethmaccrc32checker_error <= ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_last) & main_liteethmaccrc32checker_crc_error0); + if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin + main_liteethmaccrc32checker_crc_ce <= 1'd1; + if ((main_liteethmaccrc32checker_sink_sink_last & (main_liteethmaccrc32checker_sink_sink_payload_last_be > 4'd15))) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 2'd3; + end else begin + if (main_liteethmaccrc32checker_sink_sink_last) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + end + end + 2'd3: begin + main_liteethmaccrc32checker_source_source_valid <= main_liteethmaccrc32checker_syncfifo_source_valid; + main_liteethmaccrc32checker_syncfifo_source_ready <= main_liteethmaccrc32checker_source_source_ready; + main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_syncfifo_source_last; + main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_syncfifo_source_payload_error | {1{main_liteethmaccrc32checker_crc_error1}}); + main_liteethmaccrc32checker_source_source_payload_last_be <= main_liteethmaccrc32checker_last_be; + if ((main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready)) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + default: begin + main_liteethmaccrc32checker_crc_reset <= 1'd1; + main_liteethmaccrc32checker_fifo_reset <= 1'd1; + builder_rxdatapath_bufferizeendpoints_next_state <= 1'd1; + end + endcase end +assign main_bufferizeendpoints_pipe_valid_sink_ready = ((~main_bufferizeendpoints_pipe_valid_source_valid) | main_bufferizeendpoints_pipe_valid_source_ready); +assign main_bufferizeendpoints_pipe_valid_sink_valid = main_bufferizeendpoints_sink_sink_valid; +assign main_bufferizeendpoints_sink_sink_ready = main_bufferizeendpoints_pipe_valid_sink_ready; +assign main_bufferizeendpoints_pipe_valid_sink_first = main_bufferizeendpoints_sink_sink_first; +assign main_bufferizeendpoints_pipe_valid_sink_last = main_bufferizeendpoints_sink_sink_last; +assign main_bufferizeendpoints_pipe_valid_sink_payload_data = main_bufferizeendpoints_sink_sink_payload_data; +assign main_bufferizeendpoints_pipe_valid_sink_payload_last_be = main_bufferizeendpoints_sink_sink_payload_last_be; +assign main_bufferizeendpoints_pipe_valid_sink_payload_error = main_bufferizeendpoints_sink_sink_payload_error; +assign main_bufferizeendpoints_source_source_valid = main_bufferizeendpoints_pipe_valid_source_valid; +assign main_bufferizeendpoints_pipe_valid_source_ready = main_bufferizeendpoints_source_source_ready; +assign main_bufferizeendpoints_source_source_first = main_bufferizeendpoints_pipe_valid_source_first; +assign main_bufferizeendpoints_source_source_last = main_bufferizeendpoints_pipe_valid_source_last; +assign main_bufferizeendpoints_source_source_payload_data = main_bufferizeendpoints_pipe_valid_source_payload_data; +assign main_bufferizeendpoints_source_source_payload_last_be = main_bufferizeendpoints_pipe_valid_source_payload_last_be; +assign main_bufferizeendpoints_source_source_payload_error = main_bufferizeendpoints_pipe_valid_source_payload_error; +assign main_pulsesynchronizer1_o = (main_pulsesynchronizer1_toggle_o ^ main_pulsesynchronizer1_toggle_o_r); +assign main_rx_padding_source_valid = main_rx_padding_sink_valid; +assign main_rx_padding_sink_ready = main_rx_padding_source_ready; +assign main_rx_padding_source_first = main_rx_padding_sink_first; +assign main_rx_padding_source_last = main_rx_padding_sink_last; +assign main_rx_padding_source_payload_data = main_rx_padding_sink_payload_data; +assign main_rx_padding_source_payload_last_be = main_rx_padding_sink_payload_last_be; +assign main_rx_padding_source_payload_error = main_rx_padding_sink_payload_error; assign main_rx_last_be_source_valid = main_rx_last_be_sink_valid; assign main_rx_last_be_sink_ready = main_rx_last_be_source_ready; assign main_rx_last_be_source_first = main_rx_last_be_sink_first; @@ -1540,63 +2221,12 @@ assign main_rx_last_be_source_last = main_rx_last_be_sink_last; assign main_rx_last_be_source_payload_data = main_rx_last_be_sink_payload_data; assign main_rx_last_be_source_payload_error = main_rx_last_be_sink_payload_error; always @(*) begin - main_rx_last_be_source_payload_last_be <= 1'd0; - main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_payload_last_be; - main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_last; -end -assign main_tx_converter_converter_sink_valid = main_tx_converter_sink_valid; -assign main_tx_converter_converter_sink_first = main_tx_converter_sink_first; -assign main_tx_converter_converter_sink_last = main_tx_converter_sink_last; -assign main_tx_converter_sink_ready = main_tx_converter_converter_sink_ready; -always @(*) begin - main_tx_converter_converter_sink_payload_data <= 40'd0; - main_tx_converter_converter_sink_payload_data[7:0] <= main_tx_converter_sink_payload_data[7:0]; - main_tx_converter_converter_sink_payload_data[8] <= main_tx_converter_sink_payload_last_be[0]; - main_tx_converter_converter_sink_payload_data[9] <= main_tx_converter_sink_payload_error[0]; - main_tx_converter_converter_sink_payload_data[17:10] <= main_tx_converter_sink_payload_data[15:8]; - main_tx_converter_converter_sink_payload_data[18] <= main_tx_converter_sink_payload_last_be[1]; - main_tx_converter_converter_sink_payload_data[19] <= main_tx_converter_sink_payload_error[1]; - main_tx_converter_converter_sink_payload_data[27:20] <= main_tx_converter_sink_payload_data[23:16]; - main_tx_converter_converter_sink_payload_data[28] <= main_tx_converter_sink_payload_last_be[2]; - main_tx_converter_converter_sink_payload_data[29] <= main_tx_converter_sink_payload_error[2]; - main_tx_converter_converter_sink_payload_data[37:30] <= main_tx_converter_sink_payload_data[31:24]; - main_tx_converter_converter_sink_payload_data[38] <= main_tx_converter_sink_payload_last_be[3]; - main_tx_converter_converter_sink_payload_data[39] <= main_tx_converter_sink_payload_error[3]; + main_rx_last_be_source_payload_last_be <= 1'd0; + main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_payload_last_be; + if (1'd1) begin + main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_last; + end end -assign main_tx_converter_source_valid = main_tx_converter_source_source_valid; -assign main_tx_converter_source_first = main_tx_converter_source_source_first; -assign main_tx_converter_source_last = main_tx_converter_source_source_last; -assign main_tx_converter_source_source_ready = main_tx_converter_source_ready; -assign {main_tx_converter_source_payload_error, main_tx_converter_source_payload_last_be, main_tx_converter_source_payload_data} = main_tx_converter_source_source_payload_data; -assign main_tx_converter_source_source_valid = main_tx_converter_converter_source_valid; -assign main_tx_converter_converter_source_ready = main_tx_converter_source_source_ready; -assign main_tx_converter_source_source_first = main_tx_converter_converter_source_first; -assign main_tx_converter_source_source_last = main_tx_converter_converter_source_last; -assign main_tx_converter_source_source_payload_data = main_tx_converter_converter_source_payload_data; -assign main_tx_converter_converter_first = (main_tx_converter_converter_mux == 1'd0); -assign main_tx_converter_converter_last = (main_tx_converter_converter_mux == 2'd3); -assign main_tx_converter_converter_source_valid = main_tx_converter_converter_sink_valid; -assign main_tx_converter_converter_source_first = (main_tx_converter_converter_sink_first & main_tx_converter_converter_first); -assign main_tx_converter_converter_source_last = (main_tx_converter_converter_sink_last & main_tx_converter_converter_last); -assign main_tx_converter_converter_sink_ready = (main_tx_converter_converter_last & main_tx_converter_converter_source_ready); -always @(*) begin - main_tx_converter_converter_source_payload_data <= 10'd0; - case (main_tx_converter_converter_mux) - 1'd0: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[9:0]; - end - 1'd1: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[19:10]; - end - 2'd2: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[29:20]; - end - default: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[39:30]; - end - endcase -end -assign main_tx_converter_converter_source_payload_valid_token_count = main_tx_converter_converter_last; assign main_rx_converter_converter_sink_valid = main_rx_converter_sink_valid; assign main_rx_converter_converter_sink_first = main_rx_converter_sink_first; assign main_rx_converter_converter_sink_last = main_rx_converter_sink_last; @@ -1607,25 +2237,25 @@ assign main_rx_converter_source_first = main_rx_converter_source_source_first; assign main_rx_converter_source_last = main_rx_converter_source_source_last; assign main_rx_converter_source_source_ready = main_rx_converter_source_ready; always @(*) begin - main_rx_converter_source_payload_data <= 32'd0; - main_rx_converter_source_payload_data[7:0] <= main_rx_converter_source_source_payload_data[7:0]; - main_rx_converter_source_payload_data[15:8] <= main_rx_converter_source_source_payload_data[17:10]; - main_rx_converter_source_payload_data[23:16] <= main_rx_converter_source_source_payload_data[27:20]; - main_rx_converter_source_payload_data[31:24] <= main_rx_converter_source_source_payload_data[37:30]; + main_rx_converter_source_payload_data <= 32'd0; + main_rx_converter_source_payload_data[7:0] <= main_rx_converter_source_source_payload_data[7:0]; + main_rx_converter_source_payload_data[15:8] <= main_rx_converter_source_source_payload_data[17:10]; + main_rx_converter_source_payload_data[23:16] <= main_rx_converter_source_source_payload_data[27:20]; + main_rx_converter_source_payload_data[31:24] <= main_rx_converter_source_source_payload_data[37:30]; end always @(*) begin - main_rx_converter_source_payload_last_be <= 4'd0; - main_rx_converter_source_payload_last_be[0] <= main_rx_converter_source_source_payload_data[8]; - main_rx_converter_source_payload_last_be[1] <= main_rx_converter_source_source_payload_data[18]; - main_rx_converter_source_payload_last_be[2] <= main_rx_converter_source_source_payload_data[28]; - main_rx_converter_source_payload_last_be[3] <= main_rx_converter_source_source_payload_data[38]; + main_rx_converter_source_payload_last_be <= 4'd0; + main_rx_converter_source_payload_last_be[0] <= main_rx_converter_source_source_payload_data[8]; + main_rx_converter_source_payload_last_be[1] <= main_rx_converter_source_source_payload_data[18]; + main_rx_converter_source_payload_last_be[2] <= main_rx_converter_source_source_payload_data[28]; + main_rx_converter_source_payload_last_be[3] <= main_rx_converter_source_source_payload_data[38]; end always @(*) begin - main_rx_converter_source_payload_error <= 4'd0; - main_rx_converter_source_payload_error[0] <= main_rx_converter_source_source_payload_data[9]; - main_rx_converter_source_payload_error[1] <= main_rx_converter_source_source_payload_data[19]; - main_rx_converter_source_payload_error[2] <= main_rx_converter_source_source_payload_data[29]; - main_rx_converter_source_payload_error[3] <= main_rx_converter_source_source_payload_data[39]; + main_rx_converter_source_payload_error <= 4'd0; + main_rx_converter_source_payload_error[0] <= main_rx_converter_source_source_payload_data[9]; + main_rx_converter_source_payload_error[1] <= main_rx_converter_source_source_payload_data[19]; + main_rx_converter_source_payload_error[2] <= main_rx_converter_source_source_payload_data[29]; + main_rx_converter_source_payload_error[3] <= main_rx_converter_source_source_payload_data[39]; end assign main_rx_converter_source_source_valid = main_rx_converter_converter_source_valid; assign main_rx_converter_converter_source_ready = main_rx_converter_source_source_ready; @@ -1635,63 +2265,6 @@ assign main_rx_converter_source_source_payload_data = main_rx_converter_converte assign main_rx_converter_converter_sink_ready = ((~main_rx_converter_converter_strobe_all) | main_rx_converter_converter_source_ready); assign main_rx_converter_converter_source_valid = main_rx_converter_converter_strobe_all; assign main_rx_converter_converter_load_part = (main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready); -assign main_tx_cdc_cdc_sink_valid = main_tx_cdc_sink_sink_valid; -assign main_tx_cdc_sink_sink_ready = main_tx_cdc_cdc_sink_ready; -assign main_tx_cdc_cdc_sink_first = main_tx_cdc_sink_sink_first; -assign main_tx_cdc_cdc_sink_last = main_tx_cdc_sink_sink_last; -assign main_tx_cdc_cdc_sink_payload_data = main_tx_cdc_sink_sink_payload_data; -assign main_tx_cdc_cdc_sink_payload_last_be = main_tx_cdc_sink_sink_payload_last_be; -assign main_tx_cdc_cdc_sink_payload_error = main_tx_cdc_sink_sink_payload_error; -assign main_tx_cdc_source_source_valid = main_tx_cdc_cdc_source_valid; -assign main_tx_cdc_cdc_source_ready = main_tx_cdc_source_source_ready; -assign main_tx_cdc_source_source_first = main_tx_cdc_cdc_source_first; -assign main_tx_cdc_source_source_last = main_tx_cdc_cdc_source_last; -assign main_tx_cdc_source_source_payload_data = main_tx_cdc_cdc_source_payload_data; -assign main_tx_cdc_source_source_payload_last_be = main_tx_cdc_cdc_source_payload_last_be; -assign main_tx_cdc_source_source_payload_error = main_tx_cdc_cdc_source_payload_error; -assign main_tx_cdc_cdc_asyncfifo_din = {main_tx_cdc_cdc_fifo_in_last, main_tx_cdc_cdc_fifo_in_first, main_tx_cdc_cdc_fifo_in_payload_error, main_tx_cdc_cdc_fifo_in_payload_last_be, main_tx_cdc_cdc_fifo_in_payload_data}; -assign {main_tx_cdc_cdc_fifo_out_last, main_tx_cdc_cdc_fifo_out_first, main_tx_cdc_cdc_fifo_out_payload_error, main_tx_cdc_cdc_fifo_out_payload_last_be, main_tx_cdc_cdc_fifo_out_payload_data} = main_tx_cdc_cdc_asyncfifo_dout; -assign main_tx_cdc_cdc_sink_ready = main_tx_cdc_cdc_asyncfifo_writable; -assign main_tx_cdc_cdc_asyncfifo_we = main_tx_cdc_cdc_sink_valid; -assign main_tx_cdc_cdc_fifo_in_first = main_tx_cdc_cdc_sink_first; -assign main_tx_cdc_cdc_fifo_in_last = main_tx_cdc_cdc_sink_last; -assign main_tx_cdc_cdc_fifo_in_payload_data = main_tx_cdc_cdc_sink_payload_data; -assign main_tx_cdc_cdc_fifo_in_payload_last_be = main_tx_cdc_cdc_sink_payload_last_be; -assign main_tx_cdc_cdc_fifo_in_payload_error = main_tx_cdc_cdc_sink_payload_error; -assign main_tx_cdc_cdc_source_valid = main_tx_cdc_cdc_asyncfifo_readable; -assign main_tx_cdc_cdc_source_first = main_tx_cdc_cdc_fifo_out_first; -assign main_tx_cdc_cdc_source_last = main_tx_cdc_cdc_fifo_out_last; -assign main_tx_cdc_cdc_source_payload_data = main_tx_cdc_cdc_fifo_out_payload_data; -assign main_tx_cdc_cdc_source_payload_last_be = main_tx_cdc_cdc_fifo_out_payload_last_be; -assign main_tx_cdc_cdc_source_payload_error = main_tx_cdc_cdc_fifo_out_payload_error; -assign main_tx_cdc_cdc_asyncfifo_re = main_tx_cdc_cdc_source_ready; -assign main_tx_cdc_cdc_graycounter0_ce = (main_tx_cdc_cdc_asyncfifo_writable & main_tx_cdc_cdc_asyncfifo_we); -assign main_tx_cdc_cdc_graycounter1_ce = (main_tx_cdc_cdc_asyncfifo_readable & main_tx_cdc_cdc_asyncfifo_re); -assign main_tx_cdc_cdc_asyncfifo_writable = (((main_tx_cdc_cdc_graycounter0_q[5] == main_tx_cdc_cdc_consume_wdomain[5]) | (main_tx_cdc_cdc_graycounter0_q[4] == main_tx_cdc_cdc_consume_wdomain[4])) | (main_tx_cdc_cdc_graycounter0_q[3:0] != main_tx_cdc_cdc_consume_wdomain[3:0])); -assign main_tx_cdc_cdc_asyncfifo_readable = (main_tx_cdc_cdc_graycounter1_q != main_tx_cdc_cdc_produce_rdomain); -assign main_tx_cdc_cdc_wrport_adr = main_tx_cdc_cdc_graycounter0_q_binary[4:0]; -assign main_tx_cdc_cdc_wrport_dat_w = main_tx_cdc_cdc_asyncfifo_din; -assign main_tx_cdc_cdc_wrport_we = main_tx_cdc_cdc_graycounter0_ce; -assign main_tx_cdc_cdc_rdport_adr = main_tx_cdc_cdc_graycounter1_q_next_binary[4:0]; -assign main_tx_cdc_cdc_asyncfifo_dout = main_tx_cdc_cdc_rdport_dat_r; -always @(*) begin - main_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; - if (main_tx_cdc_cdc_graycounter0_ce) begin - main_tx_cdc_cdc_graycounter0_q_next_binary <= (main_tx_cdc_cdc_graycounter0_q_binary + 1'd1); - end else begin - main_tx_cdc_cdc_graycounter0_q_next_binary <= main_tx_cdc_cdc_graycounter0_q_binary; - end -end -assign main_tx_cdc_cdc_graycounter0_q_next = (main_tx_cdc_cdc_graycounter0_q_next_binary ^ main_tx_cdc_cdc_graycounter0_q_next_binary[5:1]); -always @(*) begin - main_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; - if (main_tx_cdc_cdc_graycounter1_ce) begin - main_tx_cdc_cdc_graycounter1_q_next_binary <= (main_tx_cdc_cdc_graycounter1_q_binary + 1'd1); - end else begin - main_tx_cdc_cdc_graycounter1_q_next_binary <= main_tx_cdc_cdc_graycounter1_q_binary; - end -end -assign main_tx_cdc_cdc_graycounter1_q_next = (main_tx_cdc_cdc_graycounter1_q_next_binary ^ main_tx_cdc_cdc_graycounter1_q_next_binary[5:1]); assign main_rx_cdc_cdc_sink_valid = main_rx_cdc_sink_sink_valid; assign main_rx_cdc_sink_sink_ready = main_rx_cdc_cdc_sink_ready; assign main_rx_cdc_cdc_sink_first = main_rx_cdc_sink_sink_first; @@ -1732,100 +2305,51 @@ assign main_rx_cdc_cdc_wrport_we = main_rx_cdc_cdc_graycounter0_ce; assign main_rx_cdc_cdc_rdport_adr = main_rx_cdc_cdc_graycounter1_q_next_binary[4:0]; assign main_rx_cdc_cdc_asyncfifo_dout = main_rx_cdc_cdc_rdport_dat_r; always @(*) begin - main_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; - if (main_rx_cdc_cdc_graycounter0_ce) begin - main_rx_cdc_cdc_graycounter0_q_next_binary <= (main_rx_cdc_cdc_graycounter0_q_binary + 1'd1); - end else begin - main_rx_cdc_cdc_graycounter0_q_next_binary <= main_rx_cdc_cdc_graycounter0_q_binary; - end + main_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (main_rx_cdc_cdc_graycounter0_ce) begin + main_rx_cdc_cdc_graycounter0_q_next_binary <= (main_rx_cdc_cdc_graycounter0_q_binary + 1'd1); + end else begin + main_rx_cdc_cdc_graycounter0_q_next_binary <= main_rx_cdc_cdc_graycounter0_q_binary; + end end assign main_rx_cdc_cdc_graycounter0_q_next = (main_rx_cdc_cdc_graycounter0_q_next_binary ^ main_rx_cdc_cdc_graycounter0_q_next_binary[5:1]); always @(*) begin - main_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; - if (main_rx_cdc_cdc_graycounter1_ce) begin - main_rx_cdc_cdc_graycounter1_q_next_binary <= (main_rx_cdc_cdc_graycounter1_q_binary + 1'd1); - end else begin - main_rx_cdc_cdc_graycounter1_q_next_binary <= main_rx_cdc_cdc_graycounter1_q_binary; - end + main_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (main_rx_cdc_cdc_graycounter1_ce) begin + main_rx_cdc_cdc_graycounter1_q_next_binary <= (main_rx_cdc_cdc_graycounter1_q_binary + 1'd1); + end else begin + main_rx_cdc_cdc_graycounter1_q_next_binary <= main_rx_cdc_cdc_graycounter1_q_binary; + end end assign main_rx_cdc_cdc_graycounter1_q_next = (main_rx_cdc_cdc_graycounter1_q_next_binary ^ main_rx_cdc_cdc_graycounter1_q_next_binary[5:1]); -assign main_tx_converter_sink_valid = main_tx_cdc_source_source_valid; -assign main_tx_cdc_source_source_ready = main_tx_converter_sink_ready; -assign main_tx_converter_sink_first = main_tx_cdc_source_source_first; -assign main_tx_converter_sink_last = main_tx_cdc_source_source_last; -assign main_tx_converter_sink_payload_data = main_tx_cdc_source_source_payload_data; -assign main_tx_converter_sink_payload_last_be = main_tx_cdc_source_source_payload_last_be; -assign main_tx_converter_sink_payload_error = main_tx_cdc_source_source_payload_error; -assign main_tx_last_be_sink_valid = main_tx_converter_source_valid; -assign main_tx_converter_source_ready = main_tx_last_be_sink_ready; -assign main_tx_last_be_sink_first = main_tx_converter_source_first; -assign main_tx_last_be_sink_last = main_tx_converter_source_last; -assign main_tx_last_be_sink_payload_data = main_tx_converter_source_payload_data; -assign main_tx_last_be_sink_payload_last_be = main_tx_converter_source_payload_last_be; -assign main_tx_last_be_sink_payload_error = main_tx_converter_source_payload_error; -assign main_padding_inserter_sink_valid = main_tx_last_be_source_valid; -assign main_tx_last_be_source_ready = main_padding_inserter_sink_ready; -assign main_padding_inserter_sink_first = main_tx_last_be_source_first; -assign main_padding_inserter_sink_last = main_tx_last_be_source_last; -assign main_padding_inserter_sink_payload_data = main_tx_last_be_source_payload_data; -assign main_padding_inserter_sink_payload_last_be = main_tx_last_be_source_payload_last_be; -assign main_padding_inserter_sink_payload_error = main_tx_last_be_source_payload_error; -assign main_crc32_inserter_sink_valid = main_padding_inserter_source_valid; -assign main_padding_inserter_source_ready = main_crc32_inserter_sink_ready; -assign main_crc32_inserter_sink_first = main_padding_inserter_source_first; -assign main_crc32_inserter_sink_last = main_padding_inserter_source_last; -assign main_crc32_inserter_sink_payload_data = main_padding_inserter_source_payload_data; -assign main_crc32_inserter_sink_payload_last_be = main_padding_inserter_source_payload_last_be; -assign main_crc32_inserter_sink_payload_error = main_padding_inserter_source_payload_error; -assign main_preamble_inserter_sink_valid = main_liteethmaccrc32inserter_source_valid; -assign main_liteethmaccrc32inserter_source_ready = main_preamble_inserter_sink_ready; -assign main_preamble_inserter_sink_first = main_liteethmaccrc32inserter_source_first; -assign main_preamble_inserter_sink_last = main_liteethmaccrc32inserter_source_last; -assign main_preamble_inserter_sink_payload_data = main_liteethmaccrc32inserter_source_payload_data; -assign main_preamble_inserter_sink_payload_last_be = main_liteethmaccrc32inserter_source_payload_last_be; -assign main_preamble_inserter_sink_payload_error = main_liteethmaccrc32inserter_source_payload_error; -assign main_tx_gap_inserter_sink_valid = main_preamble_inserter_source_valid; -assign main_preamble_inserter_source_ready = main_tx_gap_inserter_sink_ready; -assign main_tx_gap_inserter_sink_first = main_preamble_inserter_source_first; -assign main_tx_gap_inserter_sink_last = main_preamble_inserter_source_last; -assign main_tx_gap_inserter_sink_payload_data = main_preamble_inserter_source_payload_data; -assign main_tx_gap_inserter_sink_payload_last_be = main_preamble_inserter_source_payload_last_be; -assign main_tx_gap_inserter_sink_payload_error = main_preamble_inserter_source_payload_error; -assign main_maccore_ethphy_sink_valid = main_tx_gap_inserter_source_valid; -assign main_tx_gap_inserter_source_ready = main_maccore_ethphy_sink_ready; -assign main_maccore_ethphy_sink_first = main_tx_gap_inserter_source_first; -assign main_maccore_ethphy_sink_last = main_tx_gap_inserter_source_last; -assign main_maccore_ethphy_sink_payload_data = main_tx_gap_inserter_source_payload_data; -assign main_maccore_ethphy_sink_payload_last_be = main_tx_gap_inserter_source_payload_last_be; -assign main_maccore_ethphy_sink_payload_error = main_tx_gap_inserter_source_payload_error; -assign main_preamble_checker_sink_valid = main_maccore_ethphy_liteethphyrgmiirx_source_valid; -assign main_maccore_ethphy_liteethphyrgmiirx_source_ready = main_preamble_checker_sink_ready; -assign main_preamble_checker_sink_first = main_maccore_ethphy_liteethphyrgmiirx_source_first; -assign main_preamble_checker_sink_last = main_maccore_ethphy_liteethphyrgmiirx_source_last; -assign main_preamble_checker_sink_payload_data = main_maccore_ethphy_liteethphyrgmiirx_source_payload_data; -assign main_preamble_checker_sink_payload_last_be = main_maccore_ethphy_liteethphyrgmiirx_source_payload_last_be; -assign main_preamble_checker_sink_payload_error = main_maccore_ethphy_liteethphyrgmiirx_source_payload_error; -assign main_crc32_checker_sink_valid = main_preamble_checker_source_valid; -assign main_preamble_checker_source_ready = main_crc32_checker_sink_ready; -assign main_crc32_checker_sink_first = main_preamble_checker_source_first; -assign main_crc32_checker_sink_last = main_preamble_checker_source_last; -assign main_crc32_checker_sink_payload_data = main_preamble_checker_source_payload_data; -assign main_crc32_checker_sink_payload_last_be = main_preamble_checker_source_payload_last_be; -assign main_crc32_checker_sink_payload_error = main_preamble_checker_source_payload_error; -assign main_padding_checker_sink_valid = main_liteethmaccrc32checker_source_source_valid; -assign main_liteethmaccrc32checker_source_source_ready = main_padding_checker_sink_ready; -assign main_padding_checker_sink_first = main_liteethmaccrc32checker_source_source_first; -assign main_padding_checker_sink_last = main_liteethmaccrc32checker_source_source_last; -assign main_padding_checker_sink_payload_data = main_liteethmaccrc32checker_source_source_payload_data; -assign main_padding_checker_sink_payload_last_be = main_liteethmaccrc32checker_source_source_payload_last_be; -assign main_padding_checker_sink_payload_error = main_liteethmaccrc32checker_source_source_payload_error; -assign main_rx_last_be_sink_valid = main_padding_checker_source_valid; -assign main_padding_checker_source_ready = main_rx_last_be_sink_ready; -assign main_rx_last_be_sink_first = main_padding_checker_source_first; -assign main_rx_last_be_sink_last = main_padding_checker_source_last; -assign main_rx_last_be_sink_payload_data = main_padding_checker_source_payload_data; -assign main_rx_last_be_sink_payload_last_be = main_padding_checker_source_payload_last_be; -assign main_rx_last_be_sink_payload_error = main_padding_checker_source_payload_error; +assign main_rx_preamble_sink_valid = main_maccore_ethphy_liteethphyrgmiirx_source_valid; +assign main_maccore_ethphy_liteethphyrgmiirx_source_ready = main_rx_preamble_sink_ready; +assign main_rx_preamble_sink_first = main_maccore_ethphy_liteethphyrgmiirx_source_first; +assign main_rx_preamble_sink_last = main_maccore_ethphy_liteethphyrgmiirx_source_last; +assign main_rx_preamble_sink_payload_data = main_maccore_ethphy_liteethphyrgmiirx_source_payload_data; +assign main_rx_preamble_sink_payload_last_be = main_maccore_ethphy_liteethphyrgmiirx_source_payload_last_be; +assign main_rx_preamble_sink_payload_error = main_maccore_ethphy_liteethphyrgmiirx_source_payload_error; +assign main_bufferizeendpoints_sink_sink_valid = main_rx_preamble_source_valid; +assign main_rx_preamble_source_ready = main_bufferizeendpoints_sink_sink_ready; +assign main_bufferizeendpoints_sink_sink_first = main_rx_preamble_source_first; +assign main_bufferizeendpoints_sink_sink_last = main_rx_preamble_source_last; +assign main_bufferizeendpoints_sink_sink_payload_data = main_rx_preamble_source_payload_data; +assign main_bufferizeendpoints_sink_sink_payload_last_be = main_rx_preamble_source_payload_last_be; +assign main_bufferizeendpoints_sink_sink_payload_error = main_rx_preamble_source_payload_error; +assign main_rx_padding_sink_valid = main_liteethmaccrc32checker_source_source_valid; +assign main_liteethmaccrc32checker_source_source_ready = main_rx_padding_sink_ready; +assign main_rx_padding_sink_first = main_liteethmaccrc32checker_source_source_first; +assign main_rx_padding_sink_last = main_liteethmaccrc32checker_source_source_last; +assign main_rx_padding_sink_payload_data = main_liteethmaccrc32checker_source_source_payload_data; +assign main_rx_padding_sink_payload_last_be = main_liteethmaccrc32checker_source_source_payload_last_be; +assign main_rx_padding_sink_payload_error = main_liteethmaccrc32checker_source_source_payload_error; +assign main_rx_last_be_sink_valid = main_rx_padding_source_valid; +assign main_rx_padding_source_ready = main_rx_last_be_sink_ready; +assign main_rx_last_be_sink_first = main_rx_padding_source_first; +assign main_rx_last_be_sink_last = main_rx_padding_source_last; +assign main_rx_last_be_sink_payload_data = main_rx_padding_source_payload_data; +assign main_rx_last_be_sink_payload_last_be = main_rx_padding_source_payload_last_be; +assign main_rx_last_be_sink_payload_error = main_rx_padding_source_payload_error; assign main_rx_converter_sink_valid = main_rx_last_be_source_valid; assign main_rx_last_be_source_ready = main_rx_converter_sink_ready; assign main_rx_converter_sink_first = main_rx_last_be_source_first; @@ -1840,460 +2364,454 @@ assign main_rx_cdc_sink_sink_last = main_rx_converter_source_last; assign main_rx_cdc_sink_sink_payload_data = main_rx_converter_source_payload_data; assign main_rx_cdc_sink_sink_payload_last_be = main_rx_converter_source_payload_last_be; assign main_rx_cdc_sink_sink_payload_error = main_rx_converter_source_payload_error; -assign main_writer_sink_sink_valid = main_sink_valid; -assign main_sink_ready = main_writer_sink_sink_ready; -assign main_writer_sink_sink_first = main_sink_first; -assign main_writer_sink_sink_last = main_sink_last; -assign main_writer_sink_sink_payload_data = main_sink_payload_data; -assign main_writer_sink_sink_payload_last_be = main_sink_payload_last_be; -assign main_writer_sink_sink_payload_error = main_sink_payload_error; -assign main_source_valid = main_reader_source_source_valid; -assign main_reader_source_source_ready = main_source_ready; -assign main_source_first = main_reader_source_source_first; -assign main_source_last = main_reader_source_source_last; -assign main_source_payload_data = main_reader_source_source_payload_data; -assign main_source_payload_last_be = main_reader_source_source_payload_last_be; -assign main_source_payload_error = main_reader_source_source_payload_error; -always @(*) begin - main_writer_inc <= 3'd0; - case (main_writer_sink_sink_payload_last_be) - 1'd1: begin - main_writer_inc <= 1'd1; - end - 2'd2: begin - main_writer_inc <= 2'd2; - end - 3'd4: begin - main_writer_inc <= 2'd3; - end - default: begin - main_writer_inc <= 3'd4; - end - endcase -end -assign main_writer_stat_fifo_sink_payload_slot = main_writer_slot; -assign main_writer_stat_fifo_sink_payload_length = main_writer_counter; -assign main_writer_stat_fifo_source_ready = main_writer_available_clear; -assign main_writer_available_trigger = main_writer_stat_fifo_source_valid; -assign main_writer_slot_status = main_writer_stat_fifo_source_payload_slot; -assign main_writer_length_status = main_writer_stat_fifo_source_payload_length; -always @(*) begin - main_writer_memory1_adr <= 9'd0; - main_writer_memory1_we <= 1'd0; - main_writer_memory0_adr <= 9'd0; - main_writer_memory1_dat_w <= 32'd0; - main_writer_memory0_we <= 1'd0; - main_writer_memory0_dat_w <= 32'd0; - case (main_writer_slot) - 1'd0: begin - main_writer_memory0_adr <= main_writer_counter[31:2]; - main_writer_memory0_dat_w <= main_writer_sink_sink_payload_data; - if ((main_writer_sink_sink_valid & main_writer_ongoing)) begin - main_writer_memory0_we <= 4'd15; - end - end - 1'd1: begin - main_writer_memory1_adr <= main_writer_counter[31:2]; - main_writer_memory1_dat_w <= main_writer_sink_sink_payload_data; - if ((main_writer_sink_sink_valid & main_writer_ongoing)) begin - main_writer_memory1_we <= 4'd15; - end - end - endcase -end -assign main_writer_available0 = main_writer_available_status; -assign main_writer_available1 = main_writer_available_pending; -always @(*) begin - main_writer_available_clear <= 1'd0; - if ((main_writer_pending_re & main_writer_pending_r)) begin - main_writer_available_clear <= 1'd1; - end -end -assign main_writer_irq = (main_writer_pending_status & main_writer_enable_storage); -assign main_writer_available_status = main_writer_available_trigger; -assign main_writer_available_pending = main_writer_available_trigger; -assign main_writer_stat_fifo_syncfifo_din = {main_writer_stat_fifo_fifo_in_last, main_writer_stat_fifo_fifo_in_first, main_writer_stat_fifo_fifo_in_payload_length, main_writer_stat_fifo_fifo_in_payload_slot}; -assign {main_writer_stat_fifo_fifo_out_last, main_writer_stat_fifo_fifo_out_first, main_writer_stat_fifo_fifo_out_payload_length, main_writer_stat_fifo_fifo_out_payload_slot} = main_writer_stat_fifo_syncfifo_dout; -assign main_writer_stat_fifo_sink_ready = main_writer_stat_fifo_syncfifo_writable; -assign main_writer_stat_fifo_syncfifo_we = main_writer_stat_fifo_sink_valid; -assign main_writer_stat_fifo_fifo_in_first = main_writer_stat_fifo_sink_first; -assign main_writer_stat_fifo_fifo_in_last = main_writer_stat_fifo_sink_last; -assign main_writer_stat_fifo_fifo_in_payload_slot = main_writer_stat_fifo_sink_payload_slot; -assign main_writer_stat_fifo_fifo_in_payload_length = main_writer_stat_fifo_sink_payload_length; -assign main_writer_stat_fifo_source_valid = main_writer_stat_fifo_syncfifo_readable; -assign main_writer_stat_fifo_source_first = main_writer_stat_fifo_fifo_out_first; -assign main_writer_stat_fifo_source_last = main_writer_stat_fifo_fifo_out_last; -assign main_writer_stat_fifo_source_payload_slot = main_writer_stat_fifo_fifo_out_payload_slot; -assign main_writer_stat_fifo_source_payload_length = main_writer_stat_fifo_fifo_out_payload_length; -assign main_writer_stat_fifo_syncfifo_re = main_writer_stat_fifo_source_ready; -always @(*) begin - main_writer_stat_fifo_wrport_adr <= 1'd0; - if (main_writer_stat_fifo_replace) begin - main_writer_stat_fifo_wrport_adr <= (main_writer_stat_fifo_produce - 1'd1); - end else begin - main_writer_stat_fifo_wrport_adr <= main_writer_stat_fifo_produce; - end -end -assign main_writer_stat_fifo_wrport_dat_w = main_writer_stat_fifo_syncfifo_din; -assign main_writer_stat_fifo_wrport_we = (main_writer_stat_fifo_syncfifo_we & (main_writer_stat_fifo_syncfifo_writable | main_writer_stat_fifo_replace)); -assign main_writer_stat_fifo_do_read = (main_writer_stat_fifo_syncfifo_readable & main_writer_stat_fifo_syncfifo_re); -assign main_writer_stat_fifo_rdport_adr = main_writer_stat_fifo_consume; -assign main_writer_stat_fifo_syncfifo_dout = main_writer_stat_fifo_rdport_dat_r; -assign main_writer_stat_fifo_syncfifo_writable = (main_writer_stat_fifo_level != 2'd2); -assign main_writer_stat_fifo_syncfifo_readable = (main_writer_stat_fifo_level != 1'd0); -always @(*) begin - builder_liteethmacsramwriter_next_state <= 3'd0; - main_writer_slot_ce <= 1'd0; - main_writer_counter_t_next_value <= 32'd0; - main_writer_counter_t_next_value_ce <= 1'd0; - main_writer_start <= 1'd0; - main_writer_ongoing <= 1'd0; - main_writer_errors_status_f_next_value <= 32'd0; - main_writer_stat_fifo_sink_valid <= 1'd0; - main_writer_errors_status_f_next_value_ce <= 1'd0; - builder_liteethmacsramwriter_next_state <= builder_liteethmacsramwriter_state; - case (builder_liteethmacsramwriter_state) - 1'd1: begin - if (main_writer_sink_sink_valid) begin - if ((main_writer_counter == 11'd1530)) begin - builder_liteethmacsramwriter_next_state <= 2'd3; - end else begin - main_writer_counter_t_next_value <= (main_writer_counter + main_writer_inc); - main_writer_counter_t_next_value_ce <= 1'd1; - main_writer_ongoing <= 1'd1; - end - if (main_writer_sink_sink_last) begin - if (((main_writer_sink_sink_payload_error & main_writer_sink_sink_payload_last_be) != 1'd0)) begin - builder_liteethmacsramwriter_next_state <= 2'd2; - end else begin - builder_liteethmacsramwriter_next_state <= 3'd4; - end - end - end - end - 2'd2: begin - main_writer_counter_t_next_value <= 1'd0; - main_writer_counter_t_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 1'd0; - end - 2'd3: begin - if ((main_writer_sink_sink_valid & main_writer_sink_sink_last)) begin - builder_liteethmacsramwriter_next_state <= 3'd4; - end - end - 3'd4: begin - main_writer_counter_t_next_value <= 1'd0; - main_writer_counter_t_next_value_ce <= 1'd1; - main_writer_slot_ce <= 1'd1; - main_writer_stat_fifo_sink_valid <= 1'd1; - builder_liteethmacsramwriter_next_state <= 1'd0; - end - default: begin - if (main_writer_sink_sink_valid) begin - if (main_writer_stat_fifo_sink_ready) begin - main_writer_start <= 1'd1; - main_writer_ongoing <= 1'd1; - main_writer_counter_t_next_value <= (main_writer_counter + main_writer_inc); - main_writer_counter_t_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 1'd1; - end else begin - main_writer_errors_status_f_next_value <= (main_writer_errors_status + 1'd1); - main_writer_errors_status_f_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 2'd3; - end - end - end - endcase -end -assign main_reader_cmd_fifo_sink_valid = main_reader_start_start_re; -assign main_reader_cmd_fifo_sink_payload_slot = main_reader_slot_storage; -assign main_reader_cmd_fifo_sink_payload_length = main_reader_length_storage; -assign main_reader_ready_status = main_reader_cmd_fifo_sink_ready; -assign main_reader_level_status = main_reader_cmd_fifo_level; -always @(*) begin - main_reader_source_source_payload_last_be <= 4'd0; - if (main_reader_source_source_last) begin - case (main_reader_cmd_fifo_source_payload_length[1:0]) - 1'd0: begin - main_reader_source_source_payload_last_be <= 4'd8; - end - 1'd1: begin - main_reader_source_source_payload_last_be <= 1'd1; - end - 2'd2: begin - main_reader_source_source_payload_last_be <= 2'd2; - end - 2'd3: begin - main_reader_source_source_payload_last_be <= 3'd4; - end - endcase - end -end -assign main_reader_memory0_adr = main_reader_read_address[10:2]; -assign main_reader_memory1_adr = main_reader_read_address[10:2]; -always @(*) begin - main_reader_source_source_payload_data <= 32'd0; - case (main_reader_cmd_fifo_source_payload_slot) - 1'd0: begin - main_reader_source_source_payload_data <= main_reader_memory0_dat_r; - end - 1'd1: begin - main_reader_source_source_payload_data <= main_reader_memory1_dat_r; - end - endcase -end -assign main_reader_event00 = main_reader_eventsourcepulse_status; -assign main_reader_event01 = main_reader_eventsourcepulse_pending; -always @(*) begin - main_reader_eventsourcepulse_clear <= 1'd0; - if ((main_reader_pending_re & main_reader_pending_r)) begin - main_reader_eventsourcepulse_clear <= 1'd1; - end -end -assign main_reader_irq = (main_reader_pending_status & main_reader_enable_storage); -assign main_reader_eventsourcepulse_status = 1'd0; -assign main_reader_cmd_fifo_syncfifo_din = {main_reader_cmd_fifo_fifo_in_last, main_reader_cmd_fifo_fifo_in_first, main_reader_cmd_fifo_fifo_in_payload_length, main_reader_cmd_fifo_fifo_in_payload_slot}; -assign {main_reader_cmd_fifo_fifo_out_last, main_reader_cmd_fifo_fifo_out_first, main_reader_cmd_fifo_fifo_out_payload_length, main_reader_cmd_fifo_fifo_out_payload_slot} = main_reader_cmd_fifo_syncfifo_dout; -assign main_reader_cmd_fifo_sink_ready = main_reader_cmd_fifo_syncfifo_writable; -assign main_reader_cmd_fifo_syncfifo_we = main_reader_cmd_fifo_sink_valid; -assign main_reader_cmd_fifo_fifo_in_first = main_reader_cmd_fifo_sink_first; -assign main_reader_cmd_fifo_fifo_in_last = main_reader_cmd_fifo_sink_last; -assign main_reader_cmd_fifo_fifo_in_payload_slot = main_reader_cmd_fifo_sink_payload_slot; -assign main_reader_cmd_fifo_fifo_in_payload_length = main_reader_cmd_fifo_sink_payload_length; -assign main_reader_cmd_fifo_source_valid = main_reader_cmd_fifo_syncfifo_readable; -assign main_reader_cmd_fifo_source_first = main_reader_cmd_fifo_fifo_out_first; -assign main_reader_cmd_fifo_source_last = main_reader_cmd_fifo_fifo_out_last; -assign main_reader_cmd_fifo_source_payload_slot = main_reader_cmd_fifo_fifo_out_payload_slot; -assign main_reader_cmd_fifo_source_payload_length = main_reader_cmd_fifo_fifo_out_payload_length; -assign main_reader_cmd_fifo_syncfifo_re = main_reader_cmd_fifo_source_ready; -always @(*) begin - main_reader_cmd_fifo_wrport_adr <= 1'd0; - if (main_reader_cmd_fifo_replace) begin - main_reader_cmd_fifo_wrport_adr <= (main_reader_cmd_fifo_produce - 1'd1); - end else begin - main_reader_cmd_fifo_wrport_adr <= main_reader_cmd_fifo_produce; - end -end -assign main_reader_cmd_fifo_wrport_dat_w = main_reader_cmd_fifo_syncfifo_din; -assign main_reader_cmd_fifo_wrport_we = (main_reader_cmd_fifo_syncfifo_we & (main_reader_cmd_fifo_syncfifo_writable | main_reader_cmd_fifo_replace)); -assign main_reader_cmd_fifo_do_read = (main_reader_cmd_fifo_syncfifo_readable & main_reader_cmd_fifo_syncfifo_re); -assign main_reader_cmd_fifo_rdport_adr = main_reader_cmd_fifo_consume; -assign main_reader_cmd_fifo_syncfifo_dout = main_reader_cmd_fifo_rdport_dat_r; -assign main_reader_cmd_fifo_syncfifo_writable = (main_reader_cmd_fifo_level != 2'd2); -assign main_reader_cmd_fifo_syncfifo_readable = (main_reader_cmd_fifo_level != 1'd0); -always @(*) begin - main_reader_source_source_valid <= 1'd0; - main_reader_start <= 1'd0; - main_reader_source_source_last <= 1'd0; - builder_liteethmacsramreader_next_state <= 2'd0; - main_reader_counter_next_value <= 11'd0; - main_reader_read_address <= 11'd0; - main_reader_counter_next_value_ce <= 1'd0; - main_reader_cmd_fifo_source_ready <= 1'd0; - main_reader_eventsourcepulse_trigger <= 1'd0; - builder_liteethmacsramreader_next_state <= builder_liteethmacsramreader_state; - case (builder_liteethmacsramreader_state) - 1'd1: begin - main_reader_source_source_valid <= 1'd1; - main_reader_source_source_last <= (main_reader_counter >= (main_reader_cmd_fifo_source_payload_length - 3'd4)); - main_reader_read_address <= main_reader_counter; - if (main_reader_source_source_ready) begin - main_reader_read_address <= (main_reader_counter + 3'd4); - main_reader_counter_next_value <= (main_reader_counter + 3'd4); - main_reader_counter_next_value_ce <= 1'd1; - if (main_reader_source_source_last) begin - builder_liteethmacsramreader_next_state <= 2'd2; - end - end - end - 2'd2: begin - main_reader_eventsourcepulse_trigger <= 1'd1; - main_reader_cmd_fifo_source_ready <= 1'd1; - builder_liteethmacsramreader_next_state <= 1'd0; - end - default: begin - main_reader_counter_next_value <= 1'd0; - main_reader_counter_next_value_ce <= 1'd1; - if (main_reader_cmd_fifo_source_valid) begin - main_reader_start <= 1'd1; - builder_liteethmacsramreader_next_state <= 1'd1; - end - end - endcase -end -assign main_ev_irq = (main_writer_irq | main_reader_irq); -assign main_sram0_adr0 = main_sram0_bus_adr0[8:0]; -assign main_sram0_bus_dat_r0 = main_sram0_dat_r0; -assign main_sram1_adr0 = main_sram1_bus_adr0[8:0]; -assign main_sram1_bus_dat_r0 = main_sram1_dat_r0; -always @(*) begin - main_sram0_we <= 4'd0; - main_sram0_we[0] <= (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & main_sram0_bus_we1) & main_sram0_bus_sel1[0]); - main_sram0_we[1] <= (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & main_sram0_bus_we1) & main_sram0_bus_sel1[1]); - main_sram0_we[2] <= (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & main_sram0_bus_we1) & main_sram0_bus_sel1[2]); - main_sram0_we[3] <= (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & main_sram0_bus_we1) & main_sram0_bus_sel1[3]); -end -assign main_sram0_adr1 = main_sram0_bus_adr1[8:0]; -assign main_sram0_bus_dat_r1 = main_sram0_dat_r1; -assign main_sram0_dat_w = main_sram0_bus_dat_w1; -always @(*) begin - main_sram1_we <= 4'd0; - main_sram1_we[0] <= (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & main_sram1_bus_we1) & main_sram1_bus_sel1[0]); - main_sram1_we[1] <= (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & main_sram1_bus_we1) & main_sram1_bus_sel1[1]); - main_sram1_we[2] <= (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & main_sram1_bus_we1) & main_sram1_bus_sel1[2]); - main_sram1_we[3] <= (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & main_sram1_bus_we1) & main_sram1_bus_sel1[3]); -end -assign main_sram1_adr1 = main_sram1_bus_adr1[8:0]; -assign main_sram1_bus_dat_r1 = main_sram1_dat_r1; -assign main_sram1_dat_w = main_sram1_bus_dat_w1; -always @(*) begin - main_slave_sel <= 4'd0; - main_slave_sel[0] <= (main_bus_adr[10:9] == 1'd0); - main_slave_sel[1] <= (main_bus_adr[10:9] == 1'd1); - main_slave_sel[2] <= (main_bus_adr[10:9] == 2'd2); - main_slave_sel[3] <= (main_bus_adr[10:9] == 2'd3); -end -assign main_sram0_bus_adr0 = main_bus_adr; -assign main_sram0_bus_dat_w0 = main_bus_dat_w; -assign main_sram0_bus_sel0 = main_bus_sel; -assign main_sram0_bus_stb0 = main_bus_stb; -assign main_sram0_bus_we0 = main_bus_we; -assign main_sram0_bus_cti0 = main_bus_cti; -assign main_sram0_bus_bte0 = main_bus_bte; -assign main_sram1_bus_adr0 = main_bus_adr; -assign main_sram1_bus_dat_w0 = main_bus_dat_w; -assign main_sram1_bus_sel0 = main_bus_sel; -assign main_sram1_bus_stb0 = main_bus_stb; -assign main_sram1_bus_we0 = main_bus_we; -assign main_sram1_bus_cti0 = main_bus_cti; -assign main_sram1_bus_bte0 = main_bus_bte; -assign main_sram0_bus_adr1 = main_bus_adr; -assign main_sram0_bus_dat_w1 = main_bus_dat_w; -assign main_sram0_bus_sel1 = main_bus_sel; -assign main_sram0_bus_stb1 = main_bus_stb; -assign main_sram0_bus_we1 = main_bus_we; -assign main_sram0_bus_cti1 = main_bus_cti; -assign main_sram0_bus_bte1 = main_bus_bte; -assign main_sram1_bus_adr1 = main_bus_adr; -assign main_sram1_bus_dat_w1 = main_bus_dat_w; -assign main_sram1_bus_sel1 = main_bus_sel; -assign main_sram1_bus_stb1 = main_bus_stb; -assign main_sram1_bus_we1 = main_bus_we; -assign main_sram1_bus_cti1 = main_bus_cti; -assign main_sram1_bus_bte1 = main_bus_bte; -assign main_sram0_bus_cyc0 = (main_bus_cyc & main_slave_sel[0]); -assign main_sram1_bus_cyc0 = (main_bus_cyc & main_slave_sel[1]); -assign main_sram0_bus_cyc1 = (main_bus_cyc & main_slave_sel[2]); -assign main_sram1_bus_cyc1 = (main_bus_cyc & main_slave_sel[3]); -assign main_bus_ack = (((main_sram0_bus_ack0 | main_sram1_bus_ack0) | main_sram0_bus_ack1) | main_sram1_bus_ack1); -assign main_bus_err = (((main_sram0_bus_err0 | main_sram1_bus_err0) | main_sram0_bus_err1) | main_sram1_bus_err1); -assign main_bus_dat_r = (((({32{main_slave_sel_r[0]}} & main_sram0_bus_dat_r0) | ({32{main_slave_sel_r[1]}} & main_sram1_bus_dat_r0)) | ({32{main_slave_sel_r[2]}} & main_sram0_bus_dat_r1)) | ({32{main_slave_sel_r[3]}} & main_sram1_bus_dat_r1)); -always @(*) begin - builder_maccore_adr <= 14'd0; - builder_maccore_we <= 1'd0; - builder_maccore_dat_w <= 32'd0; - builder_maccore_wishbone_ack <= 1'd0; - builder_next_state <= 1'd0; - builder_maccore_wishbone_dat_r <= 32'd0; - builder_next_state <= builder_state; - case (builder_state) - 1'd1: begin - builder_maccore_wishbone_ack <= 1'd1; - builder_maccore_wishbone_dat_r <= builder_maccore_dat_r; - builder_next_state <= 1'd0; - end - default: begin - builder_maccore_dat_w <= builder_maccore_wishbone_dat_w; - if ((builder_maccore_wishbone_cyc & builder_maccore_wishbone_stb)) begin - builder_maccore_adr <= builder_maccore_wishbone_adr; - builder_maccore_we <= (builder_maccore_wishbone_we & (builder_maccore_wishbone_sel != 1'd0)); - builder_next_state <= 1'd1; - end - end - endcase -end -assign builder_shared_adr = builder_array_muxed0; -assign builder_shared_dat_w = builder_array_muxed1; -assign builder_shared_sel = builder_array_muxed2; -assign builder_shared_cyc = builder_array_muxed3; -assign builder_shared_stb = builder_array_muxed4; -assign builder_shared_we = builder_array_muxed5; -assign builder_shared_cti = builder_array_muxed6; -assign builder_shared_bte = builder_array_muxed7; -assign main_wb_bus_dat_r = builder_shared_dat_r; -assign main_wb_bus_ack = (builder_shared_ack & (builder_grant == 1'd0)); -assign main_wb_bus_err = (builder_shared_err & (builder_grant == 1'd0)); -assign builder_request = {main_wb_bus_cyc}; -assign builder_grant = 1'd0; +assign main_source_valid = main_rx_cdc_source_source_valid; +assign main_rx_cdc_source_source_ready = main_source_ready; +assign main_source_first = main_rx_cdc_source_source_first; +assign main_source_last = main_rx_cdc_source_source_last; +assign main_source_payload_data = main_rx_cdc_source_source_payload_data; +assign main_source_payload_last_be = main_rx_cdc_source_source_payload_last_be; +assign main_source_payload_error = main_rx_cdc_source_source_payload_error; +assign main_sram0_sink_valid = main_sink_sink_valid; +assign main_sink_sink_ready = main_sram1_sink_ready; +assign main_sram2_sink_first = main_sink_sink_first; +assign main_sram3_sink_last = main_sink_sink_last; +assign main_sram4_sink_payload_data = main_sink_sink_payload_data; +assign main_sram5_sink_payload_last_be = main_sink_sink_payload_last_be; +assign main_sram6_sink_payload_error = main_sink_sink_payload_error; +assign main_source_source_valid = main_sram83_source_valid; +assign main_sram84_source_ready = main_source_source_ready; +assign main_source_source_first = main_sram85_source_first; +assign main_source_source_last = main_sram86_source_last; +assign main_source_source_payload_data = main_sram87_source_payload_data; +assign main_source_source_payload_last_be = main_sram88_source_payload_last_be; +assign main_source_source_payload_error = main_sram89_source_payload_error; always @(*) begin - builder_slave_sel <= 2'd0; - builder_slave_sel[0] <= (builder_shared_adr[29:11] == 4'd8); - builder_slave_sel[1] <= (builder_shared_adr[29:14] == 1'd0); + main_length_inc <= 4'd0; + case (main_sram5_sink_payload_last_be) + 1'd1: begin + main_length_inc <= 1'd1; + end + 2'd2: begin + main_length_inc <= 2'd2; + end + 3'd4: begin + main_length_inc <= 2'd3; + end + 4'd8: begin + main_length_inc <= 3'd4; + end + 5'd16: begin + main_length_inc <= 3'd5; + end + 6'd32: begin + main_length_inc <= 3'd6; + end + 7'd64: begin + main_length_inc <= 3'd7; + end + default: begin + main_length_inc <= 3'd4; + end + endcase end -assign main_bus_adr = builder_shared_adr; -assign main_bus_dat_w = builder_shared_dat_w; -assign main_bus_sel = builder_shared_sel; -assign main_bus_stb = builder_shared_stb; -assign main_bus_we = builder_shared_we; -assign main_bus_cti = builder_shared_cti; -assign main_bus_bte = builder_shared_bte; -assign builder_maccore_wishbone_adr = builder_shared_adr; -assign builder_maccore_wishbone_dat_w = builder_shared_dat_w; -assign builder_maccore_wishbone_sel = builder_shared_sel; -assign builder_maccore_wishbone_stb = builder_shared_stb; -assign builder_maccore_wishbone_we = builder_shared_we; -assign builder_maccore_wishbone_cti = builder_shared_cti; -assign builder_maccore_wishbone_bte = builder_shared_bte; -assign main_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]); -assign builder_maccore_wishbone_cyc = (builder_shared_cyc & builder_slave_sel[1]); -assign builder_shared_err = (main_bus_err | builder_maccore_wishbone_err); -assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack)); +assign main_sram44_source_ready = main_sram20_clear; +assign main_sram19_trigger = main_sram43_source_valid; +assign main_sram7_status = main_sram47_source_payload_slot; +assign main_sram10_status = main_sram48_source_payload_length; +assign main_wr_data = main_sram4_sink_payload_data; always @(*) begin - builder_shared_ack <= 1'd0; - builder_error <= 1'd0; - builder_shared_dat_r <= 32'd0; - builder_shared_ack <= (main_bus_ack | builder_maccore_wishbone_ack); - builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & builder_maccore_wishbone_dat_r)); - if (builder_done) begin - builder_shared_dat_r <= 32'd4294967295; - builder_shared_ack <= 1'd1; - builder_error <= 1'd1; - end + main_sram75_adr <= 9'd0; + main_sram77_we <= 1'd0; + main_sram78_dat_w <= 32'd0; + main_sram79_adr <= 9'd0; + main_sram81_we <= 1'd0; + main_sram82_dat_w <= 32'd0; + case (main_slot) + 1'd0: begin + main_sram75_adr <= main_sram35_length[10:2]; + main_sram78_dat_w <= main_wr_data; + if ((main_sram0_sink_valid & main_write)) begin + main_sram77_we <= 1'd1; + end + end + 1'd1: begin + main_sram79_adr <= main_sram35_length[10:2]; + main_sram82_dat_w <= main_wr_data; + if ((main_sram0_sink_valid & main_write)) begin + main_sram81_we <= 1'd1; + end + end + endcase +end +assign main_sram21_available = main_sram17_status; +assign main_sram25_available = main_sram18_pending; +always @(*) begin + main_sram20_clear <= 1'd0; + if ((main_sram28_re & main_sram29_r)) begin + main_sram20_clear <= 1'd1; + end +end +assign main_sram16_irq = (main_sram26_status & main_sram31_storage); +assign main_sram17_status = main_sram19_trigger; +assign main_sram18_pending = main_sram19_trigger; +assign main_sram53_din = {main_sram69_fifo_in_last, main_sram68_fifo_in_first, main_sram67_fifo_in_payload_length, main_sram66_fifo_in_payload_slot}; +assign {main_sram73_fifo_out_last, main_sram72_fifo_out_first, main_sram71_fifo_out_payload_length, main_sram70_fifo_out_payload_slot} = main_sram54_dout; +assign main_sram38_sink_ready = main_sram50_writable; +assign main_sram49_we = main_sram37_sink_valid; +assign main_sram68_fifo_in_first = main_sram39_sink_first; +assign main_sram69_fifo_in_last = main_sram40_sink_last; +assign main_sram66_fifo_in_payload_slot = main_sram41_sink_payload_slot; +assign main_sram67_fifo_in_payload_length = main_sram42_sink_payload_length; +assign main_sram43_source_valid = main_sram52_readable; +assign main_sram45_source_first = main_sram72_fifo_out_first; +assign main_sram46_source_last = main_sram73_fifo_out_last; +assign main_sram47_source_payload_slot = main_sram70_fifo_out_payload_slot; +assign main_sram48_source_payload_length = main_sram71_fifo_out_payload_length; +assign main_sram51_re = main_sram44_source_ready; +always @(*) begin + main_sram59_adr <= 1'd0; + if (main_sram56_replace) begin + main_sram59_adr <= (main_sram57_produce - 1'd1); + end else begin + main_sram59_adr <= main_sram57_produce; + end +end +assign main_sram62_dat_w = main_sram53_din; +assign main_sram61_we = (main_sram49_we & (main_sram50_writable | main_sram56_replace)); +assign main_sram63_do_read = (main_sram52_readable & main_sram51_re); +assign main_sram64_adr = main_sram58_consume; +assign main_sram54_dout = main_sram65_dat_r; +assign main_sram50_writable = (main_sram55_level != 2'd2); +assign main_sram52_readable = (main_sram55_level != 1'd0); +always @(*) begin + builder_liteethmacsramwriter_next_state <= 3'd0; + main_slot_liteethmacsramwriter_next_value <= 1'd0; + main_slot_liteethmacsramwriter_next_value_ce <= 1'd0; + main_sram13_status_liteethmacsramwriter_f_next_value <= 32'd0; + main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value <= 11'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd0; + main_sram37_sink_valid <= 1'd0; + main_sram41_sink_payload_slot <= 1'd0; + main_sram42_sink_payload_length <= 11'd0; + main_write <= 1'd0; + builder_liteethmacsramwriter_next_state <= builder_liteethmacsramwriter_state; + case (builder_liteethmacsramwriter_state) + 1'd1: begin + if ((main_sram0_sink_valid & main_sram3_sink_last)) begin + if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + builder_liteethmacsramwriter_next_state <= 3'd4; + end + end + end + 2'd2: begin + if ((main_sram0_sink_valid & main_sram3_sink_last)) begin + if ((main_sram5_sink_payload_last_be != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + end + end + 2'd3: begin + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + 3'd4: begin + main_sram37_sink_valid <= 1'd1; + main_sram41_sink_payload_slot <= main_slot; + main_sram42_sink_payload_length <= main_sram35_length; + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + main_slot_liteethmacsramwriter_next_value <= (main_slot + 1'd1); + main_slot_liteethmacsramwriter_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + default: begin + if (main_sram0_sink_valid) begin + if (main_sram38_sink_ready) begin + main_write <= 1'd1; + main_sram35_length_liteethmacsramwriter_t_next_value <= (main_sram35_length + main_length_inc); + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + if ((main_sram35_length >= 11'd1530)) begin + builder_liteethmacsramwriter_next_state <= 1'd1; + end + if (main_sram3_sink_last) begin + if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + builder_liteethmacsramwriter_next_state <= 3'd4; + end + end + end else begin + main_sram13_status_liteethmacsramwriter_f_next_value <= (main_sram13_status + 1'd1); + main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 2'd2; + end + end + end + endcase +end +assign main_sram123_sink_valid = main_start_re; +assign main_sram127_sink_payload_slot = main_sram100_storage; +assign main_sram128_sink_payload_length = main_sram102_storage; +assign main_sram94_status = main_sram124_sink_ready; +assign main_sram97_status = main_sram141_level; +always @(*) begin + main_sram88_source_payload_last_be <= 4'd0; + if (main_sram86_source_last) begin + case (main_sram134_source_payload_length[1:0]) + 1'd1: begin + main_sram88_source_payload_last_be <= 1'd1; + end + 2'd2: begin + main_sram88_source_payload_last_be <= 2'd2; + end + 2'd3: begin + main_sram88_source_payload_last_be <= 3'd4; + end + 3'd4: begin + main_sram88_source_payload_last_be <= 4'd8; + end + 3'd5: begin + main_sram88_source_payload_last_be <= 5'd16; + end + 3'd6: begin + main_sram88_source_payload_last_be <= 6'd32; + end + 3'd7: begin + main_sram88_source_payload_last_be <= 7'd64; + end + default: begin + main_sram88_source_payload_last_be <= 4'd8; + end + endcase + end +end +assign main_sram163_re = main_read; +assign main_sram161_adr = main_sram122_length[10:2]; +assign main_sram166_re = main_read; +assign main_sram164_adr = main_sram122_length[10:2]; +always @(*) begin + main_rd_data <= 32'd0; + case (main_sram133_source_payload_slot) + 1'd0: begin + main_rd_data <= main_sram162_dat_r; + end + 1'd1: begin + main_rd_data <= main_sram165_dat_r; + end + endcase +end +assign main_sram87_source_payload_data = main_rd_data; +assign main_sram109_event0 = main_sram105_status; +assign main_sram113_event0 = main_sram106_pending; +always @(*) begin + main_sram108_clear <= 1'd0; + if ((main_sram116_re & main_sram117_r)) begin + main_sram108_clear <= 1'd1; + end +end +assign main_sram104_irq = (main_sram114_status & main_sram119_storage); +assign main_sram105_status = 1'd0; +assign main_sram139_din = {main_sram155_fifo_in_last, main_sram154_fifo_in_first, main_sram153_fifo_in_payload_length, main_sram152_fifo_in_payload_slot}; +assign {main_sram159_fifo_out_last, main_sram158_fifo_out_first, main_sram157_fifo_out_payload_length, main_sram156_fifo_out_payload_slot} = main_sram140_dout; +assign main_sram124_sink_ready = main_sram136_writable; +assign main_sram135_we = main_sram123_sink_valid; +assign main_sram154_fifo_in_first = main_sram125_sink_first; +assign main_sram155_fifo_in_last = main_sram126_sink_last; +assign main_sram152_fifo_in_payload_slot = main_sram127_sink_payload_slot; +assign main_sram153_fifo_in_payload_length = main_sram128_sink_payload_length; +assign main_sram129_source_valid = main_sram138_readable; +assign main_sram131_source_first = main_sram158_fifo_out_first; +assign main_sram132_source_last = main_sram159_fifo_out_last; +assign main_sram133_source_payload_slot = main_sram156_fifo_out_payload_slot; +assign main_sram134_source_payload_length = main_sram157_fifo_out_payload_length; +assign main_sram137_re = main_sram130_source_ready; +always @(*) begin + main_sram145_adr <= 1'd0; + if (main_sram142_replace) begin + main_sram145_adr <= (main_sram143_produce - 1'd1); + end else begin + main_sram145_adr <= main_sram143_produce; + end +end +assign main_sram148_dat_w = main_sram139_din; +assign main_sram147_we = (main_sram135_we & (main_sram136_writable | main_sram142_replace)); +assign main_sram149_do_read = (main_sram138_readable & main_sram137_re); +assign main_sram150_adr = main_sram144_consume; +assign main_sram140_dout = main_sram151_dat_r; +assign main_sram136_writable = (main_sram141_level != 2'd2); +assign main_sram138_readable = (main_sram141_level != 1'd0); +always @(*) begin + builder_liteethmacsramreader_next_state <= 2'd0; + main_read <= 1'd0; + main_sram107_trigger <= 1'd0; + main_sram122_length_liteethmacsramreader_next_value <= 11'd0; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd0; + main_sram130_source_ready <= 1'd0; + main_sram83_source_valid <= 1'd0; + main_sram86_source_last <= 1'd0; + builder_liteethmacsramreader_next_state <= builder_liteethmacsramreader_state; + case (builder_liteethmacsramreader_state) + 1'd1: begin + main_sram83_source_valid <= 1'd1; + main_sram86_source_last <= (main_sram122_length >= main_sram134_source_payload_length); + if (main_sram84_source_ready) begin + main_read <= 1'd1; + main_sram122_length_liteethmacsramreader_next_value <= (main_sram122_length + 3'd4); + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + if (main_sram86_source_last) begin + builder_liteethmacsramreader_next_state <= 2'd2; + end + end + end + 2'd2: begin + main_sram122_length_liteethmacsramreader_next_value <= 1'd0; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + main_sram107_trigger <= 1'd1; + main_sram130_source_ready <= 1'd1; + builder_liteethmacsramreader_next_state <= 1'd0; + end + default: begin + if (main_sram129_source_valid) begin + main_read <= 1'd1; + main_sram122_length_liteethmacsramreader_next_value <= 3'd4; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + builder_liteethmacsramreader_next_state <= 1'd1; + end + end + endcase +end +assign main_sram167_irq = (main_sram16_irq | main_sram104_irq); +assign main_sram0_adr = main_interface0_adr[8:0]; +assign main_interface0_dat_r = main_sram0_dat_r; +assign main_sram1_adr = main_interface1_adr[8:0]; +assign main_interface1_dat_r = main_sram1_dat_r; +always @(*) begin + main_sram2_we <= 4'd0; + main_sram2_we[0] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[0]); + main_sram2_we[1] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[1]); + main_sram2_we[2] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[2]); + main_sram2_we[3] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[3]); +end +assign main_sram2_adr = main_interface2_adr[8:0]; +assign main_interface2_dat_r = main_sram2_dat_r; +assign main_sram2_dat_w = main_interface2_dat_w; +always @(*) begin + main_sram3_we <= 4'd0; + main_sram3_we[0] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[0]); + main_sram3_we[1] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[1]); + main_sram3_we[2] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[2]); + main_sram3_we[3] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[3]); +end +assign main_sram3_adr = main_interface3_adr[8:0]; +assign main_interface3_dat_r = main_sram3_dat_r; +assign main_sram3_dat_w = main_interface3_dat_w; +always @(*) begin + main_slave_sel <= 4'd0; + main_slave_sel[0] <= (main_bus_adr[10:9] == 1'd0); + main_slave_sel[1] <= (main_bus_adr[10:9] == 1'd1); + main_slave_sel[2] <= (main_bus_adr[10:9] == 2'd2); + main_slave_sel[3] <= (main_bus_adr[10:9] == 2'd3); +end +assign main_interface0_adr = main_bus_adr; +assign main_interface0_dat_w = main_bus_dat_w; +assign main_interface0_sel = main_bus_sel; +assign main_interface0_stb = main_bus_stb; +assign main_interface0_we = main_bus_we; +assign main_interface0_cti = main_bus_cti; +assign main_interface0_bte = main_bus_bte; +assign main_interface1_adr = main_bus_adr; +assign main_interface1_dat_w = main_bus_dat_w; +assign main_interface1_sel = main_bus_sel; +assign main_interface1_stb = main_bus_stb; +assign main_interface1_we = main_bus_we; +assign main_interface1_cti = main_bus_cti; +assign main_interface1_bte = main_bus_bte; +assign main_interface2_adr = main_bus_adr; +assign main_interface2_dat_w = main_bus_dat_w; +assign main_interface2_sel = main_bus_sel; +assign main_interface2_stb = main_bus_stb; +assign main_interface2_we = main_bus_we; +assign main_interface2_cti = main_bus_cti; +assign main_interface2_bte = main_bus_bte; +assign main_interface3_adr = main_bus_adr; +assign main_interface3_dat_w = main_bus_dat_w; +assign main_interface3_sel = main_bus_sel; +assign main_interface3_stb = main_bus_stb; +assign main_interface3_we = main_bus_we; +assign main_interface3_cti = main_bus_cti; +assign main_interface3_bte = main_bus_bte; +assign main_interface0_cyc = (main_bus_cyc & main_slave_sel[0]); +assign main_interface1_cyc = (main_bus_cyc & main_slave_sel[1]); +assign main_interface2_cyc = (main_bus_cyc & main_slave_sel[2]); +assign main_interface3_cyc = (main_bus_cyc & main_slave_sel[3]); +assign main_bus_ack = (((main_interface0_ack | main_interface1_ack) | main_interface2_ack) | main_interface3_ack); +assign main_bus_err = (((main_interface0_err | main_interface1_err) | main_interface2_err) | main_interface3_err); +assign main_bus_dat_r = (((({32{main_slave_sel_r[0]}} & main_interface0_dat_r) | ({32{main_slave_sel_r[1]}} & main_interface1_dat_r)) | ({32{main_slave_sel_r[2]}} & main_interface2_dat_r)) | ({32{main_slave_sel_r[3]}} & main_interface3_dat_r)); +always @(*) begin + builder_interface0_ack <= 1'd0; + builder_interface0_dat_r <= 32'd0; + builder_interface1_adr <= 14'd0; + builder_interface1_dat_w <= 32'd0; + builder_interface1_we <= 1'd0; + builder_next_state <= 1'd0; + builder_next_state <= builder_state; + case (builder_state) + 1'd1: begin + builder_interface0_ack <= 1'd1; + builder_interface0_dat_r <= builder_interface1_dat_r; + builder_next_state <= 1'd0; + end + default: begin + builder_interface1_dat_w <= builder_interface0_dat_w; + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_adr <= builder_interface0_adr[29:0]; + builder_interface1_we <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); + builder_next_state <= 1'd1; + end + end + endcase end -assign builder_done = (builder_count == 1'd0); assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); assign builder_csrbank0_reset0_r = builder_interface0_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank0_reset0_we <= 1'd0; - builder_csrbank0_reset0_re <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank0_reset0_re <= builder_interface0_bank_bus_we; - builder_csrbank0_reset0_we <= (~builder_interface0_bank_bus_we); - end + builder_csrbank0_reset0_re <= 1'd0; + builder_csrbank0_reset0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_reset0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_reset0_we <= (~builder_interface0_bank_bus_we); + end end assign builder_csrbank0_scratch0_r = builder_interface0_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank0_scratch0_re <= 1'd0; - builder_csrbank0_scratch0_we <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_scratch0_re <= builder_interface0_bank_bus_we; - builder_csrbank0_scratch0_we <= (~builder_interface0_bank_bus_we); - end + builder_csrbank0_scratch0_re <= 1'd0; + builder_csrbank0_scratch0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_scratch0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_scratch0_we <= (~builder_interface0_bank_bus_we); + end end assign builder_csrbank0_bus_errors_r = builder_interface0_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank0_bus_errors_re <= 1'd0; - builder_csrbank0_bus_errors_we <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank0_bus_errors_re <= builder_interface0_bank_bus_we; - builder_csrbank0_bus_errors_we <= (~builder_interface0_bank_bus_we); - end + builder_csrbank0_bus_errors_re <= 1'd0; + builder_csrbank0_bus_errors_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank0_bus_errors_re <= builder_interface0_bank_bus_we; + builder_csrbank0_bus_errors_we <= (~builder_interface0_bank_bus_we); + end end always @(*) begin - main_maccore_maccore_soc_rst <= 1'd0; - if (main_maccore_maccore_reset_re) begin - main_maccore_maccore_soc_rst <= main_maccore_maccore_reset_storage[0]; - end + main_maccore_maccore_soc_rst <= 1'd0; + if (main_maccore_maccore_reset_re) begin + main_maccore_maccore_soc_rst <= main_maccore_maccore_reset_storage[0]; + end end assign main_maccore_maccore_cpu_rst = main_maccore_maccore_reset_storage[1]; assign builder_csrbank0_reset0_w = main_maccore_maccore_reset_storage[1:0]; @@ -2303,218 +2821,230 @@ assign main_maccore_maccore_bus_errors_we = builder_csrbank0_bus_errors_we; assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2); assign builder_csrbank1_sram_writer_slot_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_slot_re <= 1'd0; - builder_csrbank1_sram_writer_slot_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_sram_writer_slot_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_slot_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_writer_slot_re <= 1'd0; + builder_csrbank1_sram_writer_slot_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_sram_writer_slot_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_slot_we <= (~builder_interface1_bank_bus_we); + end end -assign builder_csrbank1_sram_writer_length_r = builder_interface1_bank_bus_dat_w[31:0]; +assign builder_csrbank1_sram_writer_length_r = builder_interface1_bank_bus_dat_w[10:0]; always @(*) begin - builder_csrbank1_sram_writer_length_re <= 1'd0; - builder_csrbank1_sram_writer_length_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_sram_writer_length_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_length_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_writer_length_re <= 1'd0; + builder_csrbank1_sram_writer_length_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_sram_writer_length_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_length_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_writer_errors_r = builder_interface1_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank1_sram_writer_errors_we <= 1'd0; - builder_csrbank1_sram_writer_errors_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_sram_writer_errors_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_errors_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_writer_errors_re <= 1'd0; + builder_csrbank1_sram_writer_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_sram_writer_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_errors_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_writer_ev_status_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_ev_status_we <= 1'd0; - builder_csrbank1_sram_writer_ev_status_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank1_sram_writer_ev_status_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_ev_status_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_writer_ev_status_re <= 1'd0; + builder_csrbank1_sram_writer_ev_status_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank1_sram_writer_ev_status_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_status_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_writer_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_ev_pending_re <= 1'd0; - builder_csrbank1_sram_writer_ev_pending_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank1_sram_writer_ev_pending_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_ev_pending_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_writer_ev_pending_re <= 1'd0; + builder_csrbank1_sram_writer_ev_pending_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank1_sram_writer_ev_pending_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_pending_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_writer_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_ev_enable0_we <= 1'd0; - builder_csrbank1_sram_writer_ev_enable0_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - builder_csrbank1_sram_writer_ev_enable0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_ev_enable0_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_writer_ev_enable0_re <= 1'd0; + builder_csrbank1_sram_writer_ev_enable0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank1_sram_writer_ev_enable0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_enable0_we <= (~builder_interface1_bank_bus_we); + end end -assign main_reader_start_start_r = builder_interface1_bank_bus_dat_w[0]; +assign main_start_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_reader_start_start_we <= 1'd0; - main_reader_start_start_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_reader_start_start_re <= builder_interface1_bank_bus_we; - main_reader_start_start_we <= (~builder_interface1_bank_bus_we); - end + main_start_re <= 1'd0; + main_start_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_start_re <= builder_interface1_bank_bus_we; + main_start_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_ready_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ready_we <= 1'd0; - builder_csrbank1_sram_reader_ready_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin - builder_csrbank1_sram_reader_ready_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ready_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_ready_re <= 1'd0; + builder_csrbank1_sram_reader_ready_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank1_sram_reader_ready_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ready_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_level_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank1_sram_reader_level_re <= 1'd0; - builder_csrbank1_sram_reader_level_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - builder_csrbank1_sram_reader_level_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_level_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_level_re <= 1'd0; + builder_csrbank1_sram_reader_level_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + builder_csrbank1_sram_reader_level_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_level_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_slot0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_slot0_re <= 1'd0; - builder_csrbank1_sram_reader_slot0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - builder_csrbank1_sram_reader_slot0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_slot0_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_slot0_re <= 1'd0; + builder_csrbank1_sram_reader_slot0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank1_sram_reader_slot0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_slot0_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_length0_r = builder_interface1_bank_bus_dat_w[10:0]; always @(*) begin - builder_csrbank1_sram_reader_length0_we <= 1'd0; - builder_csrbank1_sram_reader_length0_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - builder_csrbank1_sram_reader_length0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_length0_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_length0_re <= 1'd0; + builder_csrbank1_sram_reader_length0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank1_sram_reader_length0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_length0_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_ev_status_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ev_status_re <= 1'd0; - builder_csrbank1_sram_reader_ev_status_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank1_sram_reader_ev_status_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ev_status_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_ev_status_re <= 1'd0; + builder_csrbank1_sram_reader_ev_status_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank1_sram_reader_ev_status_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_status_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ev_pending_re <= 1'd0; - builder_csrbank1_sram_reader_ev_pending_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank1_sram_reader_ev_pending_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ev_pending_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_ev_pending_re <= 1'd0; + builder_csrbank1_sram_reader_ev_pending_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank1_sram_reader_ev_pending_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_pending_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ev_enable0_we <= 1'd0; - builder_csrbank1_sram_reader_ev_enable0_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin - builder_csrbank1_sram_reader_ev_enable0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ev_enable0_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_ev_enable0_re <= 1'd0; + builder_csrbank1_sram_reader_ev_enable0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank1_sram_reader_ev_enable0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_enable0_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_preamble_crc_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_preamble_crc_re <= 1'd0; - builder_csrbank1_preamble_crc_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin - builder_csrbank1_preamble_crc_re <= builder_interface1_bank_bus_we; - builder_csrbank1_preamble_crc_we <= (~builder_interface1_bank_bus_we); - end -end -assign builder_csrbank1_preamble_errors_r = builder_interface1_bank_bus_dat_w[31:0]; -always @(*) begin - builder_csrbank1_preamble_errors_re <= 1'd0; - builder_csrbank1_preamble_errors_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin - builder_csrbank1_preamble_errors_re <= builder_interface1_bank_bus_we; - builder_csrbank1_preamble_errors_we <= (~builder_interface1_bank_bus_we); - end -end -assign builder_csrbank1_crc_errors_r = builder_interface1_bank_bus_dat_w[31:0]; -always @(*) begin - builder_csrbank1_crc_errors_we <= 1'd0; - builder_csrbank1_crc_errors_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin - builder_csrbank1_crc_errors_re <= builder_interface1_bank_bus_we; - builder_csrbank1_crc_errors_we <= (~builder_interface1_bank_bus_we); - end -end -assign builder_csrbank1_sram_writer_slot_w = main_writer_slot_status; -assign main_writer_slot_we = builder_csrbank1_sram_writer_slot_we; -assign builder_csrbank1_sram_writer_length_w = main_writer_length_status[31:0]; -assign main_writer_length_we = builder_csrbank1_sram_writer_length_we; -assign builder_csrbank1_sram_writer_errors_w = main_writer_errors_status[31:0]; -assign main_writer_errors_we = builder_csrbank1_sram_writer_errors_we; -assign main_writer_status_status = main_writer_available0; -assign builder_csrbank1_sram_writer_ev_status_w = main_writer_status_status; -assign main_writer_status_we = builder_csrbank1_sram_writer_ev_status_we; -assign main_writer_pending_status = main_writer_available1; -assign builder_csrbank1_sram_writer_ev_pending_w = main_writer_pending_status; -assign main_writer_pending_we = builder_csrbank1_sram_writer_ev_pending_we; -assign main_writer_available2 = main_writer_enable_storage; -assign builder_csrbank1_sram_writer_ev_enable0_w = main_writer_enable_storage; -assign builder_csrbank1_sram_reader_ready_w = main_reader_ready_status; -assign main_reader_ready_we = builder_csrbank1_sram_reader_ready_we; -assign builder_csrbank1_sram_reader_level_w = main_reader_level_status[1:0]; -assign main_reader_level_we = builder_csrbank1_sram_reader_level_we; -assign builder_csrbank1_sram_reader_slot0_w = main_reader_slot_storage; -assign builder_csrbank1_sram_reader_length0_w = main_reader_length_storage[10:0]; -assign main_reader_status_status = main_reader_event00; -assign builder_csrbank1_sram_reader_ev_status_w = main_reader_status_status; -assign main_reader_status_we = builder_csrbank1_sram_reader_ev_status_we; -assign main_reader_pending_status = main_reader_event01; -assign builder_csrbank1_sram_reader_ev_pending_w = main_reader_pending_status; -assign main_reader_pending_we = builder_csrbank1_sram_reader_ev_pending_we; -assign main_reader_event02 = main_reader_enable_storage; -assign builder_csrbank1_sram_reader_ev_enable0_w = main_reader_enable_storage; -assign builder_csrbank1_preamble_crc_w = main_preamble_crc_status; -assign main_preamble_crc_we = builder_csrbank1_preamble_crc_we; -assign builder_csrbank1_preamble_errors_w = main_preamble_errors_status[31:0]; -assign main_preamble_errors_we = builder_csrbank1_preamble_errors_we; -assign builder_csrbank1_crc_errors_w = main_crc_errors_status[31:0]; -assign main_crc_errors_we = builder_csrbank1_crc_errors_we; + builder_csrbank1_preamble_crc_re <= 1'd0; + builder_csrbank1_preamble_crc_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin + builder_csrbank1_preamble_crc_re <= builder_interface1_bank_bus_we; + builder_csrbank1_preamble_crc_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_rx_datapath_preamble_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank1_rx_datapath_preamble_errors_re <= 1'd0; + builder_csrbank1_rx_datapath_preamble_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin + builder_csrbank1_rx_datapath_preamble_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rx_datapath_preamble_errors_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_rx_datapath_crc_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank1_rx_datapath_crc_errors_re <= 1'd0; + builder_csrbank1_rx_datapath_crc_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank1_rx_datapath_crc_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rx_datapath_crc_errors_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_slot_w = main_sram7_status; +assign main_sram8_we = builder_csrbank1_sram_writer_slot_we; +assign builder_csrbank1_sram_writer_length_w = main_sram10_status[10:0]; +assign main_sram11_we = builder_csrbank1_sram_writer_length_we; +assign builder_csrbank1_sram_writer_errors_w = main_sram13_status[31:0]; +assign main_sram14_we = builder_csrbank1_sram_writer_errors_we; +always @(*) begin + main_sram22_status <= 1'd0; + main_sram22_status <= main_sram21_available; +end +assign builder_csrbank1_sram_writer_ev_status_w = main_sram22_status; +assign main_sram23_we = builder_csrbank1_sram_writer_ev_status_we; +always @(*) begin + main_sram26_status <= 1'd0; + main_sram26_status <= main_sram25_available; +end +assign builder_csrbank1_sram_writer_ev_pending_w = main_sram26_status; +assign main_sram27_we = builder_csrbank1_sram_writer_ev_pending_we; +assign main_sram30_available = main_sram31_storage; +assign builder_csrbank1_sram_writer_ev_enable0_w = main_sram31_storage; +assign builder_csrbank1_sram_reader_ready_w = main_sram94_status; +assign main_sram95_we = builder_csrbank1_sram_reader_ready_we; +assign builder_csrbank1_sram_reader_level_w = main_sram97_status[1:0]; +assign main_sram98_we = builder_csrbank1_sram_reader_level_we; +assign builder_csrbank1_sram_reader_slot0_w = main_sram100_storage; +assign builder_csrbank1_sram_reader_length0_w = main_sram102_storage[10:0]; +always @(*) begin + main_sram110_status <= 1'd0; + main_sram110_status <= main_sram109_event0; +end +assign builder_csrbank1_sram_reader_ev_status_w = main_sram110_status; +assign main_sram111_we = builder_csrbank1_sram_reader_ev_status_we; +always @(*) begin + main_sram114_status <= 1'd0; + main_sram114_status <= main_sram113_event0; +end +assign builder_csrbank1_sram_reader_ev_pending_w = main_sram114_status; +assign main_sram115_we = builder_csrbank1_sram_reader_ev_pending_we; +assign main_sram118_event0 = main_sram119_storage; +assign builder_csrbank1_sram_reader_ev_enable0_w = main_sram119_storage; +assign builder_csrbank1_preamble_crc_w = main_status; +assign main_we = builder_csrbank1_preamble_crc_we; +assign builder_csrbank1_rx_datapath_preamble_errors_w = main_preamble_errors_status[31:0]; +assign main_preamble_errors_we = builder_csrbank1_rx_datapath_preamble_errors_we; +assign builder_csrbank1_rx_datapath_crc_errors_w = main_crc_errors_status[31:0]; +assign main_crc_errors_we = builder_csrbank1_rx_datapath_crc_errors_we; assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd1); assign builder_csrbank2_crg_reset0_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank2_crg_reset0_we <= 1'd0; - builder_csrbank2_crg_reset0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank2_crg_reset0_re <= builder_interface2_bank_bus_we; - builder_csrbank2_crg_reset0_we <= (~builder_interface2_bank_bus_we); - end + builder_csrbank2_crg_reset0_re <= 1'd0; + builder_csrbank2_crg_reset0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_crg_reset0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_crg_reset0_we <= (~builder_interface2_bank_bus_we); + end end assign builder_csrbank2_mdio_w0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - builder_csrbank2_mdio_w0_re <= 1'd0; - builder_csrbank2_mdio_w0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank2_mdio_w0_re <= builder_interface2_bank_bus_we; - builder_csrbank2_mdio_w0_we <= (~builder_interface2_bank_bus_we); - end + builder_csrbank2_mdio_w0_re <= 1'd0; + builder_csrbank2_mdio_w0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_mdio_w0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_mdio_w0_we <= (~builder_interface2_bank_bus_we); + end end assign builder_csrbank2_mdio_r_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank2_mdio_r_re <= 1'd0; - builder_csrbank2_mdio_r_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank2_mdio_r_re <= builder_interface2_bank_bus_we; - builder_csrbank2_mdio_r_we <= (~builder_interface2_bank_bus_we); - end + builder_csrbank2_mdio_r_re <= 1'd0; + builder_csrbank2_mdio_r_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank2_mdio_r_re <= builder_interface2_bank_bus_we; + builder_csrbank2_mdio_r_we <= (~builder_interface2_bank_bus_we); + end end assign builder_csrbank2_crg_reset0_w = main_maccore_ethphy_reset_storage; assign main_maccore_ethphy_mdc = main_maccore_ethphy__w_storage[0]; @@ -2523,1151 +3053,1605 @@ assign main_maccore_ethphy_w = main_maccore_ethphy__w_storage[2]; assign builder_csrbank2_mdio_w0_w = main_maccore_ethphy__w_storage[2:0]; assign builder_csrbank2_mdio_r_w = main_maccore_ethphy__r_status; assign main_maccore_ethphy__r_we = builder_csrbank2_mdio_r_we; -assign builder_csr_interconnect_adr = builder_maccore_adr; -assign builder_csr_interconnect_we = builder_maccore_we; -assign builder_csr_interconnect_dat_w = builder_maccore_dat_w; -assign builder_maccore_dat_r = builder_csr_interconnect_dat_r; -assign builder_interface0_bank_bus_adr = builder_csr_interconnect_adr; -assign builder_interface1_bank_bus_adr = builder_csr_interconnect_adr; -assign builder_interface2_bank_bus_adr = builder_csr_interconnect_adr; -assign builder_interface0_bank_bus_we = builder_csr_interconnect_we; -assign builder_interface1_bank_bus_we = builder_csr_interconnect_we; -assign builder_interface2_bank_bus_we = builder_csr_interconnect_we; -assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w; -assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w; -assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w; -assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); -always @(*) begin - builder_array_muxed0 <= 30'd0; - case (builder_grant) - default: begin - builder_array_muxed0 <= main_wb_bus_adr; - end - endcase -end -always @(*) begin - builder_array_muxed1 <= 32'd0; - case (builder_grant) - default: begin - builder_array_muxed1 <= main_wb_bus_dat_w; - end - endcase -end -always @(*) begin - builder_array_muxed2 <= 4'd0; - case (builder_grant) - default: begin - builder_array_muxed2 <= main_wb_bus_sel; - end - endcase -end -always @(*) begin - builder_array_muxed3 <= 1'd0; - case (builder_grant) - default: begin - builder_array_muxed3 <= main_wb_bus_cyc; - end - endcase -end -always @(*) begin - builder_array_muxed4 <= 1'd0; - case (builder_grant) - default: begin - builder_array_muxed4 <= main_wb_bus_stb; - end - endcase -end -always @(*) begin - builder_array_muxed5 <= 1'd0; - case (builder_grant) - default: begin - builder_array_muxed5 <= main_wb_bus_we; - end - endcase -end -always @(*) begin - builder_array_muxed6 <= 3'd0; - case (builder_grant) - default: begin - builder_array_muxed6 <= main_wb_bus_cti; - end - endcase -end -always @(*) begin - builder_array_muxed7 <= 2'd0; - case (builder_grant) - default: begin - builder_array_muxed7 <= main_wb_bus_bte; - end - endcase -end -assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_maccore_ethphy_locked); -always @(*) begin - main_maccore_ethphy__r_status <= 1'd0; - main_maccore_ethphy__r_status <= main_maccore_ethphy_r; - main_maccore_ethphy__r_status <= builder_xilinxmultiregimpl0_regs1; -end -assign main_ps_preamble_error_toggle_o = builder_xilinxmultiregimpl1_regs1; -assign main_ps_crc_error_toggle_o = builder_xilinxmultiregimpl2_regs1; -assign main_tx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl3_regs1; -assign main_tx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl4_regs1; -assign main_rx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl5_regs1; -assign main_rx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl6_regs1; +assign builder_adr = builder_interface1_adr; +assign builder_we = builder_interface1_we; +assign builder_dat_w = builder_interface1_dat_w; +assign builder_interface1_dat_r = builder_dat_r; +assign builder_interface0_bank_bus_adr = builder_adr; +assign builder_interface1_bank_bus_adr = builder_adr; +assign builder_interface2_bank_bus_adr = builder_adr; +assign builder_interface0_bank_bus_we = builder_we; +assign builder_interface1_bank_bus_we = builder_we; +assign builder_interface2_bank_bus_we = builder_we; +assign builder_interface0_bank_bus_dat_w = builder_dat_w; +assign builder_interface1_bank_bus_dat_w = builder_dat_w; +assign builder_interface2_bank_bus_dat_w = builder_dat_w; +assign builder_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); +assign builder_t_slice_proxy0 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy1 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy2 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy3 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy4 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy5 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy6 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy7 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy8 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy9 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy10 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy11 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy12 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy13 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy14 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy15 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy16 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy17 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy18 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy19 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy20 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy21 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy22 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy23 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy24 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy25 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy26 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy27 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy28 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy29 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy30 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy31 = (~main_tx_crc_crc_next); +assign builder_complexslicelowerer_slice_proxy = {main_tx_crc_value, main_tx_crc_sink_payload_data[7:0]}; +assign builder_t_slice_proxy32 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy33 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy34 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy35 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy36 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy37 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy38 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy39 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy40 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy41 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy42 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy43 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy44 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy45 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy46 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy47 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy48 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy49 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy50 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy51 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy52 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy53 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy54 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy55 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy56 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy57 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy58 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy59 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy60 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy61 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy62 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy63 = (~main_liteethmaccrc32checker_crc_crc_next); +always @(*) begin + builder_self0 <= 30'd0; + case (builder_grant) + default: begin + builder_self0 <= main_wb_bus_adr; + end + endcase +end +always @(*) begin + builder_self1 <= 32'd0; + case (builder_grant) + default: begin + builder_self1 <= main_wb_bus_dat_w; + end + endcase +end +always @(*) begin + builder_self2 <= 4'd0; + case (builder_grant) + default: begin + builder_self2 <= main_wb_bus_sel; + end + endcase +end +always @(*) begin + builder_self3 <= 1'd0; + case (builder_grant) + default: begin + builder_self3 <= main_wb_bus_cyc; + end + endcase +end +always @(*) begin + builder_self4 <= 1'd0; + case (builder_grant) + default: begin + builder_self4 <= main_wb_bus_stb; + end + endcase +end +always @(*) begin + builder_self5 <= 1'd0; + case (builder_grant) + default: begin + builder_self5 <= main_wb_bus_we; + end + endcase +end +always @(*) begin + builder_self6 <= 3'd0; + case (builder_grant) + default: begin + builder_self6 <= main_wb_bus_cti; + end + endcase +end +always @(*) begin + builder_self7 <= 2'd0; + case (builder_grant) + default: begin + builder_self7 <= main_wb_bus_bte; + end + endcase +end +assign builder_xilinxasyncresetsynchronizerimpl0_async_reset = (~main_maccore_ethphy_locked); +always @(*) begin + main_maccore_ethphy__r_status <= 1'd0; + main_maccore_ethphy__r_status <= main_maccore_ethphy_r; + main_maccore_ethphy__r_status <= builder_xilinxmultiregimpl01; +end +assign main_tx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl11; +assign main_tx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl21; +assign main_pulsesynchronizer0_toggle_o = builder_xilinxmultiregimpl31; +assign main_pulsesynchronizer1_toggle_o = builder_xilinxmultiregimpl41; +assign main_rx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl51; +assign main_rx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl61; + + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ always @(posedge eth_rx_clk) begin - main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_d <= main_maccore_ethphy_liteethphyrgmiirx_rx_ctl; - main_maccore_ethphy_liteethphyrgmiirx_source_valid <= main_maccore_ethphy_liteethphyrgmiirx_rx_ctl; - main_maccore_ethphy_liteethphyrgmiirx_source_payload_data <= main_maccore_ethphy_liteethphyrgmiirx_rx_data; - builder_liteethmacpreamblechecker_state <= builder_liteethmacpreamblechecker_next_state; - if (main_liteethmaccrc32checker_crc_ce) begin - main_liteethmaccrc32checker_crc_reg <= main_liteethmaccrc32checker_crc_next; - end - if (main_liteethmaccrc32checker_crc_reset) begin - main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; - end - if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin - if ((main_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin - main_liteethmaccrc32checker_syncfifo_produce <= 1'd0; - end else begin - main_liteethmaccrc32checker_syncfifo_produce <= (main_liteethmaccrc32checker_syncfifo_produce + 1'd1); - end - end - if (main_liteethmaccrc32checker_syncfifo_do_read) begin - if ((main_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin - main_liteethmaccrc32checker_syncfifo_consume <= 1'd0; - end else begin - main_liteethmaccrc32checker_syncfifo_consume <= (main_liteethmaccrc32checker_syncfifo_consume + 1'd1); - end - end - if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin - if ((~main_liteethmaccrc32checker_syncfifo_do_read)) begin - main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level + 1'd1); - end - end else begin - if (main_liteethmaccrc32checker_syncfifo_do_read) begin - main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level - 1'd1); - end - end - if (main_liteethmaccrc32checker_fifo_reset) begin - main_liteethmaccrc32checker_syncfifo_level <= 3'd0; - main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; - main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; - end - builder_liteethmaccrc32checker_state <= builder_liteethmaccrc32checker_next_state; - if (((~main_crc32_checker_source_valid) | main_crc32_checker_source_ready)) begin - main_crc32_checker_source_valid <= main_crc32_checker_sink_valid; - main_crc32_checker_source_first <= main_crc32_checker_sink_first; - main_crc32_checker_source_last <= main_crc32_checker_sink_last; - main_crc32_checker_source_payload_data <= main_crc32_checker_sink_payload_data; - main_crc32_checker_source_payload_last_be <= main_crc32_checker_sink_payload_last_be; - main_crc32_checker_source_payload_error <= main_crc32_checker_sink_payload_error; - end - if (main_ps_preamble_error_i) begin - main_ps_preamble_error_toggle_i <= (~main_ps_preamble_error_toggle_i); - end - if (main_ps_crc_error_i) begin - main_ps_crc_error_toggle_i <= (~main_ps_crc_error_toggle_i); - end - if (main_rx_converter_converter_source_ready) begin - main_rx_converter_converter_strobe_all <= 1'd0; - end - if (main_rx_converter_converter_load_part) begin - if (((main_rx_converter_converter_demux == 2'd3) | main_rx_converter_converter_sink_last)) begin - main_rx_converter_converter_demux <= 1'd0; - main_rx_converter_converter_strobe_all <= 1'd1; - end else begin - main_rx_converter_converter_demux <= (main_rx_converter_converter_demux + 1'd1); - end - end - if ((main_rx_converter_converter_source_valid & main_rx_converter_converter_source_ready)) begin - if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin - main_rx_converter_converter_source_first <= main_rx_converter_converter_sink_first; - main_rx_converter_converter_source_last <= main_rx_converter_converter_sink_last; - end else begin - main_rx_converter_converter_source_first <= 1'd0; - main_rx_converter_converter_source_last <= 1'd0; - end - end else begin - if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin - main_rx_converter_converter_source_first <= (main_rx_converter_converter_sink_first | main_rx_converter_converter_source_first); - main_rx_converter_converter_source_last <= (main_rx_converter_converter_sink_last | main_rx_converter_converter_source_last); - end - end - if (main_rx_converter_converter_load_part) begin - case (main_rx_converter_converter_demux) - 1'd0: begin - main_rx_converter_converter_source_payload_data[9:0] <= main_rx_converter_converter_sink_payload_data; - end - 1'd1: begin - main_rx_converter_converter_source_payload_data[19:10] <= main_rx_converter_converter_sink_payload_data; - end - 2'd2: begin - main_rx_converter_converter_source_payload_data[29:20] <= main_rx_converter_converter_sink_payload_data; - end - 2'd3: begin - main_rx_converter_converter_source_payload_data[39:30] <= main_rx_converter_converter_sink_payload_data; - end - endcase - end - if (main_rx_converter_converter_load_part) begin - main_rx_converter_converter_source_payload_valid_token_count <= (main_rx_converter_converter_demux + 1'd1); - end - main_rx_cdc_cdc_graycounter0_q_binary <= main_rx_cdc_cdc_graycounter0_q_next_binary; - main_rx_cdc_cdc_graycounter0_q <= main_rx_cdc_cdc_graycounter0_q_next; - if (eth_rx_rst) begin - main_maccore_ethphy_liteethphyrgmiirx_source_valid <= 1'd0; - main_maccore_ethphy_liteethphyrgmiirx_source_payload_data <= 8'd0; - main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_d <= 1'd0; - main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; - main_liteethmaccrc32checker_syncfifo_level <= 3'd0; - main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; - main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; - main_crc32_checker_source_valid <= 1'd0; - main_crc32_checker_source_payload_data <= 8'd0; - main_crc32_checker_source_payload_last_be <= 1'd0; - main_crc32_checker_source_payload_error <= 1'd0; - main_rx_converter_converter_source_payload_data <= 40'd0; - main_rx_converter_converter_source_payload_valid_token_count <= 3'd0; - main_rx_converter_converter_demux <= 2'd0; - main_rx_converter_converter_strobe_all <= 1'd0; - main_rx_cdc_cdc_graycounter0_q <= 6'd0; - main_rx_cdc_cdc_graycounter0_q_binary <= 6'd0; - builder_liteethmacpreamblechecker_state <= 1'd0; - builder_liteethmaccrc32checker_state <= 2'd0; - end - builder_xilinxmultiregimpl6_regs0 <= main_rx_cdc_cdc_graycounter1_q; - builder_xilinxmultiregimpl6_regs1 <= builder_xilinxmultiregimpl6_regs0; + main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_d <= main_maccore_ethphy_liteethphyrgmiirx_rx_ctl; + main_maccore_ethphy_liteethphyrgmiirx_source_valid <= main_maccore_ethphy_liteethphyrgmiirx_rx_ctl; + main_maccore_ethphy_liteethphyrgmiirx_source_payload_data <= main_maccore_ethphy_liteethphyrgmiirx_rx_data; + builder_rxdatapath_liteethmacpreamblechecker_state <= builder_rxdatapath_liteethmacpreamblechecker_next_state; + if (main_pulsesynchronizer0_i) begin + main_pulsesynchronizer0_toggle_i <= (~main_pulsesynchronizer0_toggle_i); + end + if (main_liteethmaccrc32checker_crc_ce) begin + main_liteethmaccrc32checker_crc_reg <= main_liteethmaccrc32checker_crc_crc_next; + end + if (main_liteethmaccrc32checker_crc_reset) begin + main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + end + if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin + if ((main_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin + main_liteethmaccrc32checker_syncfifo_produce <= 1'd0; + end else begin + main_liteethmaccrc32checker_syncfifo_produce <= (main_liteethmaccrc32checker_syncfifo_produce + 1'd1); + end + end + if (main_liteethmaccrc32checker_syncfifo_do_read) begin + if ((main_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin + main_liteethmaccrc32checker_syncfifo_consume <= 1'd0; + end else begin + main_liteethmaccrc32checker_syncfifo_consume <= (main_liteethmaccrc32checker_syncfifo_consume + 1'd1); + end + end + if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin + if ((~main_liteethmaccrc32checker_syncfifo_do_read)) begin + main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level + 1'd1); + end + end else begin + if (main_liteethmaccrc32checker_syncfifo_do_read) begin + main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level - 1'd1); + end + end + if (main_liteethmaccrc32checker_fifo_reset) begin + main_liteethmaccrc32checker_syncfifo_level <= 3'd0; + main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + end + builder_rxdatapath_bufferizeendpoints_state <= builder_rxdatapath_bufferizeendpoints_next_state; + if (main_liteethmaccrc32checker_last_be_next_value_ce0) begin + main_liteethmaccrc32checker_last_be <= main_liteethmaccrc32checker_last_be_next_value0; + end + if (main_liteethmaccrc32checker_crc_error1_next_value_ce1) begin + main_liteethmaccrc32checker_crc_error1 <= main_liteethmaccrc32checker_crc_error1_next_value1; + end + if (((~main_bufferizeendpoints_pipe_valid_source_valid) | main_bufferizeendpoints_pipe_valid_source_ready)) begin + main_bufferizeendpoints_pipe_valid_source_valid <= main_bufferizeendpoints_pipe_valid_sink_valid; + main_bufferizeendpoints_pipe_valid_source_first <= main_bufferizeendpoints_pipe_valid_sink_first; + main_bufferizeendpoints_pipe_valid_source_last <= main_bufferizeendpoints_pipe_valid_sink_last; + main_bufferizeendpoints_pipe_valid_source_payload_data <= main_bufferizeendpoints_pipe_valid_sink_payload_data; + main_bufferizeendpoints_pipe_valid_source_payload_last_be <= main_bufferizeendpoints_pipe_valid_sink_payload_last_be; + main_bufferizeendpoints_pipe_valid_source_payload_error <= main_bufferizeendpoints_pipe_valid_sink_payload_error; + end + if (main_pulsesynchronizer1_i) begin + main_pulsesynchronizer1_toggle_i <= (~main_pulsesynchronizer1_toggle_i); + end + if (main_rx_converter_converter_source_ready) begin + main_rx_converter_converter_strobe_all <= 1'd0; + end + if (main_rx_converter_converter_load_part) begin + if (((main_rx_converter_converter_demux == 2'd3) | main_rx_converter_converter_sink_last)) begin + main_rx_converter_converter_demux <= 1'd0; + main_rx_converter_converter_strobe_all <= 1'd1; + end else begin + main_rx_converter_converter_demux <= (main_rx_converter_converter_demux + 1'd1); + end + end + if ((main_rx_converter_converter_source_valid & main_rx_converter_converter_source_ready)) begin + if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin + main_rx_converter_converter_source_first <= main_rx_converter_converter_sink_first; + main_rx_converter_converter_source_last <= main_rx_converter_converter_sink_last; + end else begin + main_rx_converter_converter_source_first <= 1'd0; + main_rx_converter_converter_source_last <= 1'd0; + end + end else begin + if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin + main_rx_converter_converter_source_first <= (main_rx_converter_converter_sink_first | main_rx_converter_converter_source_first); + main_rx_converter_converter_source_last <= (main_rx_converter_converter_sink_last | main_rx_converter_converter_source_last); + end + end + if (main_rx_converter_converter_load_part) begin + case (main_rx_converter_converter_demux) + 1'd0: begin + main_rx_converter_converter_source_payload_data[9:0] <= main_rx_converter_converter_sink_payload_data; + end + 1'd1: begin + main_rx_converter_converter_source_payload_data[19:10] <= main_rx_converter_converter_sink_payload_data; + end + 2'd2: begin + main_rx_converter_converter_source_payload_data[29:20] <= main_rx_converter_converter_sink_payload_data; + end + 2'd3: begin + main_rx_converter_converter_source_payload_data[39:30] <= main_rx_converter_converter_sink_payload_data; + end + endcase + end + if (main_rx_converter_converter_load_part) begin + main_rx_converter_converter_source_payload_valid_token_count <= (main_rx_converter_converter_demux + 1'd1); + end + main_rx_cdc_cdc_graycounter0_q_binary <= main_rx_cdc_cdc_graycounter0_q_next_binary; + main_rx_cdc_cdc_graycounter0_q <= main_rx_cdc_cdc_graycounter0_q_next; + if (eth_rx_rst) begin + main_maccore_ethphy_liteethphyrgmiirx_source_valid <= 1'd0; + main_maccore_ethphy_liteethphyrgmiirx_source_payload_data <= 8'd0; + main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_d <= 1'd0; + main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + main_liteethmaccrc32checker_syncfifo_level <= 3'd0; + main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + main_liteethmaccrc32checker_last_be <= 1'd0; + main_liteethmaccrc32checker_crc_error1 <= 1'd0; + main_bufferizeendpoints_pipe_valid_source_valid <= 1'd0; + main_bufferizeendpoints_pipe_valid_source_payload_data <= 8'd0; + main_bufferizeendpoints_pipe_valid_source_payload_last_be <= 1'd0; + main_bufferizeendpoints_pipe_valid_source_payload_error <= 1'd0; + main_rx_converter_converter_source_payload_data <= 40'd0; + main_rx_converter_converter_source_payload_valid_token_count <= 3'd0; + main_rx_converter_converter_demux <= 2'd0; + main_rx_converter_converter_strobe_all <= 1'd0; + main_rx_cdc_cdc_graycounter0_q <= 6'd0; + main_rx_cdc_cdc_graycounter0_q_binary <= 6'd0; + builder_rxdatapath_liteethmacpreamblechecker_state <= 1'd0; + builder_rxdatapath_bufferizeendpoints_state <= 2'd0; + end + builder_xilinxmultiregimpl60 <= main_rx_cdc_cdc_graycounter1_q; + builder_xilinxmultiregimpl61 <= builder_xilinxmultiregimpl60; end always @(posedge eth_tx_clk) begin - builder_liteethmacgap_state <= builder_liteethmacgap_next_state; - if (main_tx_gap_inserter_counter_liteethmacgap_next_value_ce) begin - main_tx_gap_inserter_counter <= main_tx_gap_inserter_counter_liteethmacgap_next_value; - end - builder_liteethmacpreambleinserter_state <= builder_liteethmacpreambleinserter_next_state; - if (main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce) begin - main_preamble_inserter_count <= main_preamble_inserter_count_liteethmacpreambleinserter_next_value; - end - if (main_liteethmaccrc32inserter_is_ongoing0) begin - main_liteethmaccrc32inserter_cnt <= 2'd3; - end else begin - if ((main_liteethmaccrc32inserter_is_ongoing1 & (~main_liteethmaccrc32inserter_cnt_done))) begin - main_liteethmaccrc32inserter_cnt <= (main_liteethmaccrc32inserter_cnt - main_liteethmaccrc32inserter_source_ready); - end - end - if (main_liteethmaccrc32inserter_ce) begin - main_liteethmaccrc32inserter_reg <= main_liteethmaccrc32inserter_next; - end - if (main_liteethmaccrc32inserter_reset) begin - main_liteethmaccrc32inserter_reg <= 32'd4294967295; - end - builder_liteethmaccrc32inserter_state <= builder_liteethmaccrc32inserter_next_state; - if (((~main_crc32_inserter_source_valid) | main_crc32_inserter_source_ready)) begin - main_crc32_inserter_source_valid <= main_crc32_inserter_sink_valid; - main_crc32_inserter_source_first <= main_crc32_inserter_sink_first; - main_crc32_inserter_source_last <= main_crc32_inserter_sink_last; - main_crc32_inserter_source_payload_data <= main_crc32_inserter_sink_payload_data; - main_crc32_inserter_source_payload_last_be <= main_crc32_inserter_sink_payload_last_be; - main_crc32_inserter_source_payload_error <= main_crc32_inserter_sink_payload_error; - end - builder_liteethmacpaddinginserter_state <= builder_liteethmacpaddinginserter_next_state; - if (main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce) begin - main_padding_inserter_counter <= main_padding_inserter_counter_liteethmacpaddinginserter_next_value; - end - builder_liteethmactxlastbe_state <= builder_liteethmactxlastbe_next_state; - if ((main_tx_converter_converter_source_valid & main_tx_converter_converter_source_ready)) begin - if (main_tx_converter_converter_last) begin - main_tx_converter_converter_mux <= 1'd0; - end else begin - main_tx_converter_converter_mux <= (main_tx_converter_converter_mux + 1'd1); - end - end - main_tx_cdc_cdc_graycounter1_q_binary <= main_tx_cdc_cdc_graycounter1_q_next_binary; - main_tx_cdc_cdc_graycounter1_q <= main_tx_cdc_cdc_graycounter1_q_next; - if (eth_tx_rst) begin - main_liteethmaccrc32inserter_reg <= 32'd4294967295; - main_liteethmaccrc32inserter_cnt <= 2'd3; - main_crc32_inserter_source_valid <= 1'd0; - main_crc32_inserter_source_payload_data <= 8'd0; - main_crc32_inserter_source_payload_last_be <= 1'd0; - main_crc32_inserter_source_payload_error <= 1'd0; - main_padding_inserter_counter <= 16'd0; - main_tx_converter_converter_mux <= 2'd0; - main_tx_cdc_cdc_graycounter1_q <= 6'd0; - main_tx_cdc_cdc_graycounter1_q_binary <= 6'd0; - builder_liteethmacgap_state <= 1'd0; - builder_liteethmacpreambleinserter_state <= 2'd0; - builder_liteethmaccrc32inserter_state <= 2'd0; - builder_liteethmacpaddinginserter_state <= 1'd0; - builder_liteethmactxlastbe_state <= 1'd0; - end - builder_xilinxmultiregimpl3_regs0 <= main_tx_cdc_cdc_graycounter0_q; - builder_xilinxmultiregimpl3_regs1 <= builder_xilinxmultiregimpl3_regs0; + main_tx_cdc_cdc_graycounter1_q_binary <= main_tx_cdc_cdc_graycounter1_q_next_binary; + main_tx_cdc_cdc_graycounter1_q <= main_tx_cdc_cdc_graycounter1_q_next; + if ((main_tx_converter_converter_source_valid & main_tx_converter_converter_source_ready)) begin + if (main_tx_converter_converter_last) begin + main_tx_converter_converter_mux <= 1'd0; + end else begin + main_tx_converter_converter_mux <= (main_tx_converter_converter_mux + 1'd1); + end + end + builder_txdatapath_liteethmactxlastbe_state <= builder_txdatapath_liteethmactxlastbe_next_state; + builder_txdatapath_liteethmacpaddinginserter_state <= builder_txdatapath_liteethmacpaddinginserter_next_state; + if (main_tx_padding_counter_clockdomainsrenamer0_next_value_ce) begin + main_tx_padding_counter <= main_tx_padding_counter_clockdomainsrenamer0_next_value; + end + if (main_tx_crc_is_ongoing0) begin + main_tx_crc_cnt <= 2'd3; + end else begin + if ((main_tx_crc_is_ongoing1 & (~main_tx_crc_cnt_done))) begin + main_tx_crc_cnt <= (main_tx_crc_cnt - main_tx_crc_source_ready); + end + end + if (main_tx_crc_ce) begin + main_tx_crc_reg <= main_tx_crc_crc_next; + end + if (main_tx_crc_reset) begin + main_tx_crc_reg <= 32'd4294967295; + end + builder_txdatapath_bufferizeendpoints_state <= builder_txdatapath_bufferizeendpoints_next_state; + if (main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0) begin + main_tx_crc_crc_packet <= main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0; + end + if (main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1) begin + main_tx_crc_last_be <= main_tx_crc_last_be_clockdomainsrenamer1_next_value1; + end + if (((~main_tx_crc_pipe_valid_source_valid) | main_tx_crc_pipe_valid_source_ready)) begin + main_tx_crc_pipe_valid_source_valid <= main_tx_crc_pipe_valid_sink_valid; + main_tx_crc_pipe_valid_source_first <= main_tx_crc_pipe_valid_sink_first; + main_tx_crc_pipe_valid_source_last <= main_tx_crc_pipe_valid_sink_last; + main_tx_crc_pipe_valid_source_payload_data <= main_tx_crc_pipe_valid_sink_payload_data; + main_tx_crc_pipe_valid_source_payload_last_be <= main_tx_crc_pipe_valid_sink_payload_last_be; + main_tx_crc_pipe_valid_source_payload_error <= main_tx_crc_pipe_valid_sink_payload_error; + end + builder_txdatapath_liteethmacpreambleinserter_state <= builder_txdatapath_liteethmacpreambleinserter_next_state; + if (main_tx_preamble_count_clockdomainsrenamer2_next_value_ce) begin + main_tx_preamble_count <= main_tx_preamble_count_clockdomainsrenamer2_next_value; + end + builder_txdatapath_liteethmacgap_state <= builder_txdatapath_liteethmacgap_next_state; + if (main_tx_gap_counter_clockdomainsrenamer3_next_value_ce) begin + main_tx_gap_counter <= main_tx_gap_counter_clockdomainsrenamer3_next_value; + end + if (eth_tx_rst) begin + main_tx_cdc_cdc_graycounter1_q <= 6'd0; + main_tx_cdc_cdc_graycounter1_q_binary <= 6'd0; + main_tx_converter_converter_mux <= 2'd0; + main_tx_padding_counter <= 16'd0; + main_tx_crc_crc_packet <= 32'd0; + main_tx_crc_last_be <= 1'd0; + main_tx_crc_reg <= 32'd4294967295; + main_tx_crc_cnt <= 2'd3; + main_tx_crc_pipe_valid_source_valid <= 1'd0; + main_tx_crc_pipe_valid_source_payload_data <= 8'd0; + main_tx_crc_pipe_valid_source_payload_last_be <= 1'd0; + main_tx_crc_pipe_valid_source_payload_error <= 1'd0; + builder_txdatapath_liteethmactxlastbe_state <= 1'd0; + builder_txdatapath_liteethmacpaddinginserter_state <= 1'd0; + builder_txdatapath_bufferizeendpoints_state <= 2'd0; + builder_txdatapath_liteethmacpreambleinserter_state <= 2'd0; + builder_txdatapath_liteethmacgap_state <= 1'd0; + end + builder_xilinxmultiregimpl10 <= main_tx_cdc_cdc_graycounter0_q; + builder_xilinxmultiregimpl11 <= builder_xilinxmultiregimpl10; end always @(posedge por_clk) begin - main_maccore_int_rst <= sys_reset; + main_maccore_int_rst <= sys_reset; end always @(posedge sys_clk) begin - if ((main_maccore_maccore_bus_errors != 32'd4294967295)) begin - if (main_maccore_maccore_bus_error) begin - main_maccore_maccore_bus_errors <= (main_maccore_maccore_bus_errors + 1'd1); - end - end - if (main_ps_preamble_error_o) begin - main_preamble_errors_status <= (main_preamble_errors_status + 1'd1); - end - if (main_ps_crc_error_o) begin - main_crc_errors_status <= (main_crc_errors_status + 1'd1); - end - main_ps_preamble_error_toggle_o_r <= main_ps_preamble_error_toggle_o; - main_ps_crc_error_toggle_o_r <= main_ps_crc_error_toggle_o; - main_tx_cdc_cdc_graycounter0_q_binary <= main_tx_cdc_cdc_graycounter0_q_next_binary; - main_tx_cdc_cdc_graycounter0_q <= main_tx_cdc_cdc_graycounter0_q_next; - main_rx_cdc_cdc_graycounter1_q_binary <= main_rx_cdc_cdc_graycounter1_q_next_binary; - main_rx_cdc_cdc_graycounter1_q <= main_rx_cdc_cdc_graycounter1_q_next; - if (main_writer_slot_ce) begin - main_writer_slot <= (main_writer_slot + 1'd1); - end - if (((main_writer_stat_fifo_syncfifo_we & main_writer_stat_fifo_syncfifo_writable) & (~main_writer_stat_fifo_replace))) begin - main_writer_stat_fifo_produce <= (main_writer_stat_fifo_produce + 1'd1); - end - if (main_writer_stat_fifo_do_read) begin - main_writer_stat_fifo_consume <= (main_writer_stat_fifo_consume + 1'd1); - end - if (((main_writer_stat_fifo_syncfifo_we & main_writer_stat_fifo_syncfifo_writable) & (~main_writer_stat_fifo_replace))) begin - if ((~main_writer_stat_fifo_do_read)) begin - main_writer_stat_fifo_level <= (main_writer_stat_fifo_level + 1'd1); - end - end else begin - if (main_writer_stat_fifo_do_read) begin - main_writer_stat_fifo_level <= (main_writer_stat_fifo_level - 1'd1); - end - end - builder_liteethmacsramwriter_state <= builder_liteethmacsramwriter_next_state; - if (main_writer_counter_t_next_value_ce) begin - main_writer_counter <= main_writer_counter_t_next_value; - end - if (main_writer_errors_status_f_next_value_ce) begin - main_writer_errors_status <= main_writer_errors_status_f_next_value; - end - if (main_reader_eventsourcepulse_clear) begin - main_reader_eventsourcepulse_pending <= 1'd0; - end - if (main_reader_eventsourcepulse_trigger) begin - main_reader_eventsourcepulse_pending <= 1'd1; - end - if (((main_reader_cmd_fifo_syncfifo_we & main_reader_cmd_fifo_syncfifo_writable) & (~main_reader_cmd_fifo_replace))) begin - main_reader_cmd_fifo_produce <= (main_reader_cmd_fifo_produce + 1'd1); - end - if (main_reader_cmd_fifo_do_read) begin - main_reader_cmd_fifo_consume <= (main_reader_cmd_fifo_consume + 1'd1); - end - if (((main_reader_cmd_fifo_syncfifo_we & main_reader_cmd_fifo_syncfifo_writable) & (~main_reader_cmd_fifo_replace))) begin - if ((~main_reader_cmd_fifo_do_read)) begin - main_reader_cmd_fifo_level <= (main_reader_cmd_fifo_level + 1'd1); - end - end else begin - if (main_reader_cmd_fifo_do_read) begin - main_reader_cmd_fifo_level <= (main_reader_cmd_fifo_level - 1'd1); - end - end - builder_liteethmacsramreader_state <= builder_liteethmacsramreader_next_state; - if (main_reader_counter_next_value_ce) begin - main_reader_counter <= main_reader_counter_next_value; - end - main_sram0_bus_ack0 <= 1'd0; - if (((main_sram0_bus_cyc0 & main_sram0_bus_stb0) & (~main_sram0_bus_ack0))) begin - main_sram0_bus_ack0 <= 1'd1; - end - main_sram1_bus_ack0 <= 1'd0; - if (((main_sram1_bus_cyc0 & main_sram1_bus_stb0) & (~main_sram1_bus_ack0))) begin - main_sram1_bus_ack0 <= 1'd1; - end - main_sram0_bus_ack1 <= 1'd0; - if (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & (~main_sram0_bus_ack1))) begin - main_sram0_bus_ack1 <= 1'd1; - end - main_sram1_bus_ack1 <= 1'd0; - if (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & (~main_sram1_bus_ack1))) begin - main_sram1_bus_ack1 <= 1'd1; - end - main_slave_sel_r <= main_slave_sel; - builder_state <= builder_next_state; - builder_slave_sel_r <= builder_slave_sel; - if (builder_wait) begin - if ((~builder_done)) begin - builder_count <= (builder_count - 1'd1); - end - end else begin - builder_count <= 20'd1000000; - end - builder_interface0_bank_bus_dat_r <= 1'd0; - if (builder_csrbank0_sel) begin - case (builder_interface0_bank_bus_adr[8:0]) - 1'd0: begin - builder_interface0_bank_bus_dat_r <= builder_csrbank0_reset0_w; - end - 1'd1: begin - builder_interface0_bank_bus_dat_r <= builder_csrbank0_scratch0_w; - end - 2'd2: begin - builder_interface0_bank_bus_dat_r <= builder_csrbank0_bus_errors_w; - end - endcase - end - if (builder_csrbank0_reset0_re) begin - main_maccore_maccore_reset_storage[1:0] <= builder_csrbank0_reset0_r; - end - main_maccore_maccore_reset_re <= builder_csrbank0_reset0_re; - if (builder_csrbank0_scratch0_re) begin - main_maccore_maccore_scratch_storage[31:0] <= builder_csrbank0_scratch0_r; - end - main_maccore_maccore_scratch_re <= builder_csrbank0_scratch0_re; - main_maccore_maccore_bus_errors_re <= builder_csrbank0_bus_errors_re; - builder_interface1_bank_bus_dat_r <= 1'd0; - if (builder_csrbank1_sel) begin - case (builder_interface1_bank_bus_adr[8:0]) - 1'd0: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_slot_w; - end - 1'd1: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_length_w; - end - 2'd2: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_errors_w; - end - 2'd3: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_status_w; - end - 3'd4: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_pending_w; - end - 3'd5: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_enable0_w; - end - 3'd6: begin - builder_interface1_bank_bus_dat_r <= main_reader_start_start_w; - end - 3'd7: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ready_w; - end - 4'd8: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_level_w; - end - 4'd9: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_slot0_w; - end - 4'd10: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_length0_w; - end - 4'd11: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_status_w; - end - 4'd12: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_pending_w; - end - 4'd13: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_enable0_w; - end - 4'd14: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_crc_w; - end - 4'd15: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_errors_w; - end - 5'd16: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_crc_errors_w; - end - endcase - end - main_writer_slot_re <= builder_csrbank1_sram_writer_slot_re; - main_writer_length_re <= builder_csrbank1_sram_writer_length_re; - main_writer_errors_re <= builder_csrbank1_sram_writer_errors_re; - main_writer_status_re <= builder_csrbank1_sram_writer_ev_status_re; - if (builder_csrbank1_sram_writer_ev_pending_re) begin - main_writer_pending_r <= builder_csrbank1_sram_writer_ev_pending_r; - end - main_writer_pending_re <= builder_csrbank1_sram_writer_ev_pending_re; - if (builder_csrbank1_sram_writer_ev_enable0_re) begin - main_writer_enable_storage <= builder_csrbank1_sram_writer_ev_enable0_r; - end - main_writer_enable_re <= builder_csrbank1_sram_writer_ev_enable0_re; - main_reader_ready_re <= builder_csrbank1_sram_reader_ready_re; - main_reader_level_re <= builder_csrbank1_sram_reader_level_re; - if (builder_csrbank1_sram_reader_slot0_re) begin - main_reader_slot_storage <= builder_csrbank1_sram_reader_slot0_r; - end - main_reader_slot_re <= builder_csrbank1_sram_reader_slot0_re; - if (builder_csrbank1_sram_reader_length0_re) begin - main_reader_length_storage[10:0] <= builder_csrbank1_sram_reader_length0_r; - end - main_reader_length_re <= builder_csrbank1_sram_reader_length0_re; - main_reader_status_re <= builder_csrbank1_sram_reader_ev_status_re; - if (builder_csrbank1_sram_reader_ev_pending_re) begin - main_reader_pending_r <= builder_csrbank1_sram_reader_ev_pending_r; - end - main_reader_pending_re <= builder_csrbank1_sram_reader_ev_pending_re; - if (builder_csrbank1_sram_reader_ev_enable0_re) begin - main_reader_enable_storage <= builder_csrbank1_sram_reader_ev_enable0_r; - end - main_reader_enable_re <= builder_csrbank1_sram_reader_ev_enable0_re; - main_preamble_crc_re <= builder_csrbank1_preamble_crc_re; - main_preamble_errors_re <= builder_csrbank1_preamble_errors_re; - main_crc_errors_re <= builder_csrbank1_crc_errors_re; - builder_interface2_bank_bus_dat_r <= 1'd0; - if (builder_csrbank2_sel) begin - case (builder_interface2_bank_bus_adr[8:0]) - 1'd0: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_crg_reset0_w; - end - 1'd1: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_w0_w; - end - 2'd2: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_r_w; - end - endcase - end - if (builder_csrbank2_crg_reset0_re) begin - main_maccore_ethphy_reset_storage <= builder_csrbank2_crg_reset0_r; - end - main_maccore_ethphy_reset_re <= builder_csrbank2_crg_reset0_re; - if (builder_csrbank2_mdio_w0_re) begin - main_maccore_ethphy__w_storage[2:0] <= builder_csrbank2_mdio_w0_r; - end - main_maccore_ethphy__w_re <= builder_csrbank2_mdio_w0_re; - main_maccore_ethphy__r_re <= builder_csrbank2_mdio_r_re; - if (sys_rst) begin - main_maccore_maccore_reset_storage <= 2'd0; - main_maccore_maccore_reset_re <= 1'd0; - main_maccore_maccore_scratch_storage <= 32'd305419896; - main_maccore_maccore_scratch_re <= 1'd0; - main_maccore_maccore_bus_errors_re <= 1'd0; - main_maccore_maccore_bus_errors <= 32'd0; - main_maccore_ethphy_reset_storage <= 1'd0; - main_maccore_ethphy_reset_re <= 1'd0; - main_maccore_ethphy__w_storage <= 3'd0; - main_maccore_ethphy__w_re <= 1'd0; - main_maccore_ethphy__r_re <= 1'd0; - main_preamble_crc_re <= 1'd0; - main_preamble_errors_status <= 32'd0; - main_preamble_errors_re <= 1'd0; - main_crc_errors_status <= 32'd0; - main_crc_errors_re <= 1'd0; - main_tx_cdc_cdc_graycounter0_q <= 6'd0; - main_tx_cdc_cdc_graycounter0_q_binary <= 6'd0; - main_rx_cdc_cdc_graycounter1_q <= 6'd0; - main_rx_cdc_cdc_graycounter1_q_binary <= 6'd0; - main_writer_slot_re <= 1'd0; - main_writer_length_re <= 1'd0; - main_writer_errors_status <= 32'd0; - main_writer_errors_re <= 1'd0; - main_writer_status_re <= 1'd0; - main_writer_pending_re <= 1'd0; - main_writer_pending_r <= 1'd0; - main_writer_enable_storage <= 1'd0; - main_writer_enable_re <= 1'd0; - main_writer_counter <= 32'd0; - main_writer_slot <= 1'd0; - main_writer_stat_fifo_level <= 2'd0; - main_writer_stat_fifo_produce <= 1'd0; - main_writer_stat_fifo_consume <= 1'd0; - main_reader_ready_re <= 1'd0; - main_reader_level_re <= 1'd0; - main_reader_slot_re <= 1'd0; - main_reader_length_re <= 1'd0; - main_reader_eventsourcepulse_pending <= 1'd0; - main_reader_status_re <= 1'd0; - main_reader_pending_re <= 1'd0; - main_reader_pending_r <= 1'd0; - main_reader_enable_storage <= 1'd0; - main_reader_enable_re <= 1'd0; - main_reader_cmd_fifo_level <= 2'd0; - main_reader_cmd_fifo_produce <= 1'd0; - main_reader_cmd_fifo_consume <= 1'd0; - main_reader_counter <= 11'd0; - main_sram0_bus_ack0 <= 1'd0; - main_sram1_bus_ack0 <= 1'd0; - main_sram0_bus_ack1 <= 1'd0; - main_sram1_bus_ack1 <= 1'd0; - main_slave_sel_r <= 4'd0; - builder_liteethmacsramwriter_state <= 3'd0; - builder_liteethmacsramreader_state <= 2'd0; - builder_slave_sel_r <= 2'd0; - builder_count <= 20'd1000000; - builder_state <= 1'd0; - end - builder_xilinxmultiregimpl0_regs0 <= main_maccore_ethphy_data_r; - builder_xilinxmultiregimpl0_regs1 <= builder_xilinxmultiregimpl0_regs0; - builder_xilinxmultiregimpl1_regs0 <= main_ps_preamble_error_toggle_i; - builder_xilinxmultiregimpl1_regs1 <= builder_xilinxmultiregimpl1_regs0; - builder_xilinxmultiregimpl2_regs0 <= main_ps_crc_error_toggle_i; - builder_xilinxmultiregimpl2_regs1 <= builder_xilinxmultiregimpl2_regs0; - builder_xilinxmultiregimpl4_regs0 <= main_tx_cdc_cdc_graycounter1_q; - builder_xilinxmultiregimpl4_regs1 <= builder_xilinxmultiregimpl4_regs0; - builder_xilinxmultiregimpl5_regs0 <= main_rx_cdc_cdc_graycounter0_q; - builder_xilinxmultiregimpl5_regs1 <= builder_xilinxmultiregimpl5_regs0; + builder_slave_sel_r <= builder_slave_sel; + if (builder_wait) begin + if ((~builder_done)) begin + builder_count <= (builder_count - 1'd1); + end + end else begin + builder_count <= 20'd1000000; + end + if ((main_maccore_maccore_bus_errors != 32'd4294967295)) begin + if (main_maccore_maccore_bus_error) begin + main_maccore_maccore_bus_errors <= (main_maccore_maccore_bus_errors + 1'd1); + end + end + main_tx_cdc_cdc_graycounter0_q_binary <= main_tx_cdc_cdc_graycounter0_q_next_binary; + main_tx_cdc_cdc_graycounter0_q <= main_tx_cdc_cdc_graycounter0_q_next; + if (main_pulsesynchronizer0_o) begin + main_preamble_errors_status <= (main_preamble_errors_status + 1'd1); + end + if (main_pulsesynchronizer1_o) begin + main_crc_errors_status <= (main_crc_errors_status + 1'd1); + end + main_pulsesynchronizer0_toggle_o_r <= main_pulsesynchronizer0_toggle_o; + main_pulsesynchronizer1_toggle_o_r <= main_pulsesynchronizer1_toggle_o; + main_rx_cdc_cdc_graycounter1_q_binary <= main_rx_cdc_cdc_graycounter1_q_next_binary; + main_rx_cdc_cdc_graycounter1_q <= main_rx_cdc_cdc_graycounter1_q_next; + if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin + main_sram57_produce <= (main_sram57_produce + 1'd1); + end + if (main_sram63_do_read) begin + main_sram58_consume <= (main_sram58_consume + 1'd1); + end + if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin + if ((~main_sram63_do_read)) begin + main_sram55_level <= (main_sram55_level + 1'd1); + end + end else begin + if (main_sram63_do_read) begin + main_sram55_level <= (main_sram55_level - 1'd1); + end + end + builder_liteethmacsramwriter_state <= builder_liteethmacsramwriter_next_state; + if (main_sram35_length_liteethmacsramwriter_t_next_value_ce) begin + main_sram35_length <= main_sram35_length_liteethmacsramwriter_t_next_value; + end + if (main_sram13_status_liteethmacsramwriter_f_next_value_ce) begin + main_sram13_status <= main_sram13_status_liteethmacsramwriter_f_next_value; + end + if (main_slot_liteethmacsramwriter_next_value_ce) begin + main_slot <= main_slot_liteethmacsramwriter_next_value; + end + if (main_sram108_clear) begin + main_sram106_pending <= 1'd0; + end + if (main_sram107_trigger) begin + main_sram106_pending <= 1'd1; + end + if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin + main_sram143_produce <= (main_sram143_produce + 1'd1); + end + if (main_sram149_do_read) begin + main_sram144_consume <= (main_sram144_consume + 1'd1); + end + if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin + if ((~main_sram149_do_read)) begin + main_sram141_level <= (main_sram141_level + 1'd1); + end + end else begin + if (main_sram149_do_read) begin + main_sram141_level <= (main_sram141_level - 1'd1); + end + end + builder_liteethmacsramreader_state <= builder_liteethmacsramreader_next_state; + if (main_sram122_length_liteethmacsramreader_next_value_ce) begin + main_sram122_length <= main_sram122_length_liteethmacsramreader_next_value; + end + main_interface0_ack <= 1'd0; + if (((main_interface0_cyc & main_interface0_stb) & ((~main_interface0_ack) | main_sram0_adr_burst))) begin + main_interface0_ack <= 1'd1; + end + main_interface1_ack <= 1'd0; + if (((main_interface1_cyc & main_interface1_stb) & ((~main_interface1_ack) | main_sram1_adr_burst))) begin + main_interface1_ack <= 1'd1; + end + main_interface2_ack <= 1'd0; + if (((main_interface2_cyc & main_interface2_stb) & ((~main_interface2_ack) | main_sram2_adr_burst))) begin + main_interface2_ack <= 1'd1; + end + main_interface3_ack <= 1'd0; + if (((main_interface3_cyc & main_interface3_stb) & ((~main_interface3_ack) | main_sram3_adr_burst))) begin + main_interface3_ack <= 1'd1; + end + main_slave_sel_r <= main_slave_sel; + builder_state <= builder_next_state; + builder_interface0_bank_bus_dat_r <= 1'd0; + if (builder_csrbank0_sel) begin + case (builder_interface0_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_reset0_w; + end + 1'd1: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_scratch0_w; + end + 2'd2: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_bus_errors_w; + end + endcase + end + if (builder_csrbank0_reset0_re) begin + main_maccore_maccore_reset_storage[1:0] <= builder_csrbank0_reset0_r; + end + main_maccore_maccore_reset_re <= builder_csrbank0_reset0_re; + if (builder_csrbank0_scratch0_re) begin + main_maccore_maccore_scratch_storage[31:0] <= builder_csrbank0_scratch0_r; + end + main_maccore_maccore_scratch_re <= builder_csrbank0_scratch0_re; + main_maccore_maccore_bus_errors_re <= builder_csrbank0_bus_errors_re; + builder_interface1_bank_bus_dat_r <= 1'd0; + if (builder_csrbank1_sel) begin + case (builder_interface1_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_slot_w; + end + 1'd1: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_length_w; + end + 2'd2: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_errors_w; + end + 2'd3: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_status_w; + end + 3'd4: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_pending_w; + end + 3'd5: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_enable0_w; + end + 3'd6: begin + builder_interface1_bank_bus_dat_r <= main_start_w; + end + 3'd7: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ready_w; + end + 4'd8: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_level_w; + end + 4'd9: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_slot0_w; + end + 4'd10: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_length0_w; + end + 4'd11: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_status_w; + end + 4'd12: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_pending_w; + end + 4'd13: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_enable0_w; + end + 4'd14: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_crc_w; + end + 4'd15: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_preamble_errors_w; + end + 5'd16: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_crc_errors_w; + end + endcase + end + main_sram9_re <= builder_csrbank1_sram_writer_slot_re; + main_sram12_re <= builder_csrbank1_sram_writer_length_re; + main_sram15_re <= builder_csrbank1_sram_writer_errors_re; + main_sram24_re <= builder_csrbank1_sram_writer_ev_status_re; + if (builder_csrbank1_sram_writer_ev_pending_re) begin + main_sram29_r <= builder_csrbank1_sram_writer_ev_pending_r; + end + main_sram28_re <= builder_csrbank1_sram_writer_ev_pending_re; + if (builder_csrbank1_sram_writer_ev_enable0_re) begin + main_sram31_storage <= builder_csrbank1_sram_writer_ev_enable0_r; + end + main_sram32_re <= builder_csrbank1_sram_writer_ev_enable0_re; + main_sram96_re <= builder_csrbank1_sram_reader_ready_re; + main_sram99_re <= builder_csrbank1_sram_reader_level_re; + if (builder_csrbank1_sram_reader_slot0_re) begin + main_sram100_storage <= builder_csrbank1_sram_reader_slot0_r; + end + main_sram101_re <= builder_csrbank1_sram_reader_slot0_re; + if (builder_csrbank1_sram_reader_length0_re) begin + main_sram102_storage[10:0] <= builder_csrbank1_sram_reader_length0_r; + end + main_sram103_re <= builder_csrbank1_sram_reader_length0_re; + main_sram112_re <= builder_csrbank1_sram_reader_ev_status_re; + if (builder_csrbank1_sram_reader_ev_pending_re) begin + main_sram117_r <= builder_csrbank1_sram_reader_ev_pending_r; + end + main_sram116_re <= builder_csrbank1_sram_reader_ev_pending_re; + if (builder_csrbank1_sram_reader_ev_enable0_re) begin + main_sram119_storage <= builder_csrbank1_sram_reader_ev_enable0_r; + end + main_sram120_re <= builder_csrbank1_sram_reader_ev_enable0_re; + main_re <= builder_csrbank1_preamble_crc_re; + main_preamble_errors_re <= builder_csrbank1_rx_datapath_preamble_errors_re; + main_crc_errors_re <= builder_csrbank1_rx_datapath_crc_errors_re; + builder_interface2_bank_bus_dat_r <= 1'd0; + if (builder_csrbank2_sel) begin + case (builder_interface2_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_crg_reset0_w; + end + 1'd1: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_w0_w; + end + 2'd2: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_r_w; + end + endcase + end + if (builder_csrbank2_crg_reset0_re) begin + main_maccore_ethphy_reset_storage <= builder_csrbank2_crg_reset0_r; + end + main_maccore_ethphy_reset_re <= builder_csrbank2_crg_reset0_re; + if (builder_csrbank2_mdio_w0_re) begin + main_maccore_ethphy__w_storage[2:0] <= builder_csrbank2_mdio_w0_r; + end + main_maccore_ethphy__w_re <= builder_csrbank2_mdio_w0_re; + main_maccore_ethphy__r_re <= builder_csrbank2_mdio_r_re; + if (sys_rst) begin + main_maccore_maccore_reset_storage <= 2'd0; + main_maccore_maccore_reset_re <= 1'd0; + main_maccore_maccore_scratch_storage <= 32'd305419896; + main_maccore_maccore_scratch_re <= 1'd0; + main_maccore_maccore_bus_errors_re <= 1'd0; + main_maccore_maccore_bus_errors <= 32'd0; + main_maccore_ethphy_reset_storage <= 1'd0; + main_maccore_ethphy_reset_re <= 1'd0; + main_maccore_ethphy__w_storage <= 3'd0; + main_maccore_ethphy__w_re <= 1'd0; + main_maccore_ethphy__r_re <= 1'd0; + main_re <= 1'd0; + main_tx_cdc_cdc_graycounter0_q <= 6'd0; + main_tx_cdc_cdc_graycounter0_q_binary <= 6'd0; + main_preamble_errors_status <= 32'd0; + main_preamble_errors_re <= 1'd0; + main_crc_errors_status <= 32'd0; + main_crc_errors_re <= 1'd0; + main_rx_cdc_cdc_graycounter1_q <= 6'd0; + main_rx_cdc_cdc_graycounter1_q_binary <= 6'd0; + main_sram9_re <= 1'd0; + main_sram12_re <= 1'd0; + main_sram13_status <= 32'd0; + main_sram15_re <= 1'd0; + main_sram24_re <= 1'd0; + main_sram28_re <= 1'd0; + main_sram29_r <= 1'd0; + main_sram31_storage <= 1'd0; + main_sram32_re <= 1'd0; + main_slot <= 1'd0; + main_sram35_length <= 11'd0; + main_sram55_level <= 2'd0; + main_sram57_produce <= 1'd0; + main_sram58_consume <= 1'd0; + main_sram96_re <= 1'd0; + main_sram99_re <= 1'd0; + main_sram101_re <= 1'd0; + main_sram103_re <= 1'd0; + main_sram106_pending <= 1'd0; + main_sram112_re <= 1'd0; + main_sram116_re <= 1'd0; + main_sram117_r <= 1'd0; + main_sram119_storage <= 1'd0; + main_sram120_re <= 1'd0; + main_sram122_length <= 11'd0; + main_sram141_level <= 2'd0; + main_sram143_produce <= 1'd0; + main_sram144_consume <= 1'd0; + main_interface0_ack <= 1'd0; + main_interface1_ack <= 1'd0; + main_interface2_ack <= 1'd0; + main_interface3_ack <= 1'd0; + main_slave_sel_r <= 4'd0; + builder_slave_sel_r <= 2'd0; + builder_count <= 20'd1000000; + builder_liteethmacsramwriter_state <= 3'd0; + builder_liteethmacsramreader_state <= 2'd0; + builder_state <= 1'd0; + end + builder_xilinxmultiregimpl00 <= main_maccore_ethphy_data_r; + builder_xilinxmultiregimpl01 <= builder_xilinxmultiregimpl00; + builder_xilinxmultiregimpl20 <= main_tx_cdc_cdc_graycounter1_q; + builder_xilinxmultiregimpl21 <= builder_xilinxmultiregimpl20; + builder_xilinxmultiregimpl30 <= main_pulsesynchronizer0_toggle_i; + builder_xilinxmultiregimpl31 <= builder_xilinxmultiregimpl30; + builder_xilinxmultiregimpl40 <= main_pulsesynchronizer1_toggle_i; + builder_xilinxmultiregimpl41 <= builder_xilinxmultiregimpl40; + builder_xilinxmultiregimpl50 <= main_rx_cdc_cdc_graycounter0_q; + builder_xilinxmultiregimpl51 <= builder_xilinxmultiregimpl50; end + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Instance IBUF of IBUF Module. +//------------------------------------------------------------------------------ IBUF IBUF( - .I(rgmii_eth_clocks_rx), - .O(main_maccore_ethphy_eth_rx_clk_ibuf) + // Inputs. + .I (rgmii_clocks_rx), + + // Outputs. + .O (main_maccore_ethphy_eth_rx_clk_ibuf) ); +//------------------------------------------------------------------------------ +// Instance BUFG of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG( - .I(main_maccore_ethphy_eth_rx_clk_ibuf), - .O(eth_rx_clk) + // Inputs. + .I (main_maccore_ethphy_eth_rx_clk_ibuf), + + // Outputs. + .O (eth_rx_clk) ); +//------------------------------------------------------------------------------ +// Instance BUFG_1 of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG_1( - .I(main_maccore_ethphy_clkout0), - .O(main_maccore_ethphy_clkout_buf0) + // Inputs. + .I (main_maccore_ethphy_clkout0), + + // Outputs. + .O (main_maccore_ethphy_clkout_buf0) ); +//------------------------------------------------------------------------------ +// Instance BUFG_2 of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG_2( - .I(main_maccore_ethphy_clkout1), - .O(main_maccore_ethphy_clkout_buf1) + // Inputs. + .I (main_maccore_ethphy_clkout1), + + // Outputs. + .O (main_maccore_ethphy_clkout_buf1) ); +//------------------------------------------------------------------------------ +// Instance ODDR of ODDR Module. +//------------------------------------------------------------------------------ ODDR #( - .DDR_CLK_EDGE("SAME_EDGE") + // Parameters. + .DDR_CLK_EDGE ("SAME_EDGE") ) ODDR ( - .C(eth_tx_delayed_clk), - .CE(1'd1), - .D1(1'd1), - .D2(1'd0), - .R(1'd0), - .S(1'd0), - .Q(main_maccore_ethphy_eth_tx_clk_obuf) + // Inputs. + .C (eth_tx_delayed_clk), + .CE (1'd1), + .D1 (1'd1), + .D2 (1'd0), + .R (1'd0), + .S (1'd0), + + // Outputs. + .Q (main_maccore_ethphy_eth_tx_clk_obuf) ); +//------------------------------------------------------------------------------ +// Instance OBUF of OBUF Module. +//------------------------------------------------------------------------------ OBUF OBUF( - .I(main_maccore_ethphy_eth_tx_clk_obuf), - .O(rgmii_eth_clocks_tx) + // Inputs. + .I (main_maccore_ethphy_eth_tx_clk_obuf), + + // Outputs. + .O (rgmii_clocks_tx) ); +//------------------------------------------------------------------------------ +// Instance ODDR_1 of ODDR Module. +//------------------------------------------------------------------------------ ODDR #( - .DDR_CLK_EDGE("SAME_EDGE") + // Parameters. + .DDR_CLK_EDGE ("SAME_EDGE") ) ODDR_1 ( - .C(eth_tx_clk), - .CE(1'd1), - .D1(main_maccore_ethphy_sink_valid), - .D2(main_maccore_ethphy_sink_valid), - .R(1'd0), - .S(1'd0), - .Q(main_maccore_ethphy_tx_ctl_obuf) + // Inputs. + .C (eth_tx_clk), + .CE (1'd1), + .D1 (main_maccore_ethphy_sink_valid), + .D2 (main_maccore_ethphy_sink_valid), + .R (1'd0), + .S (1'd0), + + // Outputs. + .Q (main_maccore_ethphy_tx_ctl_obuf) ); +//------------------------------------------------------------------------------ +// Instance OBUF_1 of OBUF Module. +//------------------------------------------------------------------------------ OBUF OBUF_1( - .I(main_maccore_ethphy_tx_ctl_obuf), - .O(rgmii_eth_tx_ctl) + // Inputs. + .I (main_maccore_ethphy_tx_ctl_obuf), + + // Outputs. + .O (rgmii_tx_ctl) ); +//------------------------------------------------------------------------------ +// Instance ODDR_2 of ODDR Module. +//------------------------------------------------------------------------------ ODDR #( - .DDR_CLK_EDGE("SAME_EDGE") + // Parameters. + .DDR_CLK_EDGE ("SAME_EDGE") ) ODDR_2 ( - .C(eth_tx_clk), - .CE(1'd1), - .D1(main_maccore_ethphy_sink_payload_data[0]), - .D2(main_maccore_ethphy_sink_payload_data[4]), - .R(1'd0), - .S(1'd0), - .Q(main_maccore_ethphy_tx_data_obuf[0]) + // Inputs. + .C (eth_tx_clk), + .CE (1'd1), + .D1 (main_maccore_ethphy_sink_payload_data[0]), + .D2 (main_maccore_ethphy_sink_payload_data[4]), + .R (1'd0), + .S (1'd0), + + // Outputs. + .Q (main_maccore_ethphy_tx_data_obuf[0]) ); +//------------------------------------------------------------------------------ +// Instance OBUF_2 of OBUF Module. +//------------------------------------------------------------------------------ OBUF OBUF_2( - .I(main_maccore_ethphy_tx_data_obuf[0]), - .O(rgmii_eth_tx_data[0]) + // Inputs. + .I (main_maccore_ethphy_tx_data_obuf[0]), + + // Outputs. + .O (rgmii_tx_data[0]) ); +//------------------------------------------------------------------------------ +// Instance ODDR_3 of ODDR Module. +//------------------------------------------------------------------------------ ODDR #( - .DDR_CLK_EDGE("SAME_EDGE") + // Parameters. + .DDR_CLK_EDGE ("SAME_EDGE") ) ODDR_3 ( - .C(eth_tx_clk), - .CE(1'd1), - .D1(main_maccore_ethphy_sink_payload_data[1]), - .D2(main_maccore_ethphy_sink_payload_data[5]), - .R(1'd0), - .S(1'd0), - .Q(main_maccore_ethphy_tx_data_obuf[1]) + // Inputs. + .C (eth_tx_clk), + .CE (1'd1), + .D1 (main_maccore_ethphy_sink_payload_data[1]), + .D2 (main_maccore_ethphy_sink_payload_data[5]), + .R (1'd0), + .S (1'd0), + + // Outputs. + .Q (main_maccore_ethphy_tx_data_obuf[1]) ); +//------------------------------------------------------------------------------ +// Instance OBUF_3 of OBUF Module. +//------------------------------------------------------------------------------ OBUF OBUF_3( - .I(main_maccore_ethphy_tx_data_obuf[1]), - .O(rgmii_eth_tx_data[1]) + // Inputs. + .I (main_maccore_ethphy_tx_data_obuf[1]), + + // Outputs. + .O (rgmii_tx_data[1]) ); +//------------------------------------------------------------------------------ +// Instance ODDR_4 of ODDR Module. +//------------------------------------------------------------------------------ ODDR #( - .DDR_CLK_EDGE("SAME_EDGE") + // Parameters. + .DDR_CLK_EDGE ("SAME_EDGE") ) ODDR_4 ( - .C(eth_tx_clk), - .CE(1'd1), - .D1(main_maccore_ethphy_sink_payload_data[2]), - .D2(main_maccore_ethphy_sink_payload_data[6]), - .R(1'd0), - .S(1'd0), - .Q(main_maccore_ethphy_tx_data_obuf[2]) + // Inputs. + .C (eth_tx_clk), + .CE (1'd1), + .D1 (main_maccore_ethphy_sink_payload_data[2]), + .D2 (main_maccore_ethphy_sink_payload_data[6]), + .R (1'd0), + .S (1'd0), + + // Outputs. + .Q (main_maccore_ethphy_tx_data_obuf[2]) ); +//------------------------------------------------------------------------------ +// Instance OBUF_4 of OBUF Module. +//------------------------------------------------------------------------------ OBUF OBUF_4( - .I(main_maccore_ethphy_tx_data_obuf[2]), - .O(rgmii_eth_tx_data[2]) + // Inputs. + .I (main_maccore_ethphy_tx_data_obuf[2]), + + // Outputs. + .O (rgmii_tx_data[2]) ); +//------------------------------------------------------------------------------ +// Instance ODDR_5 of ODDR Module. +//------------------------------------------------------------------------------ ODDR #( - .DDR_CLK_EDGE("SAME_EDGE") + // Parameters. + .DDR_CLK_EDGE ("SAME_EDGE") ) ODDR_5 ( - .C(eth_tx_clk), - .CE(1'd1), - .D1(main_maccore_ethphy_sink_payload_data[3]), - .D2(main_maccore_ethphy_sink_payload_data[7]), - .R(1'd0), - .S(1'd0), - .Q(main_maccore_ethphy_tx_data_obuf[3]) + // Inputs. + .C (eth_tx_clk), + .CE (1'd1), + .D1 (main_maccore_ethphy_sink_payload_data[3]), + .D2 (main_maccore_ethphy_sink_payload_data[7]), + .R (1'd0), + .S (1'd0), + + // Outputs. + .Q (main_maccore_ethphy_tx_data_obuf[3]) ); +//------------------------------------------------------------------------------ +// Instance OBUF_5 of OBUF Module. +//------------------------------------------------------------------------------ OBUF OBUF_5( - .I(main_maccore_ethphy_tx_data_obuf[3]), - .O(rgmii_eth_tx_data[3]) + // Inputs. + .I (main_maccore_ethphy_tx_data_obuf[3]), + + // Outputs. + .O (rgmii_tx_data[3]) ); +//------------------------------------------------------------------------------ +// Instance IBUF_1 of IBUF Module. +//------------------------------------------------------------------------------ IBUF IBUF_1( - .I(rgmii_eth_rx_ctl), - .O(main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_ibuf) + // Inputs. + .I (rgmii_rx_ctl), + + // Outputs. + .O (main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_ibuf) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .IDELAY_TYPE("FIXED"), - .IDELAY_VALUE(5'd26), - .REFCLK_FREQUENCY(200.0) + // Parameters. + .IDELAY_TYPE ("FIXED"), + .IDELAY_VALUE (5'd26), + .REFCLK_FREQUENCY (200.0) ) IDELAYE2 ( - .C(1'd0), - .CE(1'd0), - .IDATAIN(main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_ibuf), - .INC(1'd0), - .LD(1'd0), - .LDPIPEEN(1'd0), - .DATAOUT(main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_idelay) + // Inputs. + .C (1'd0), + .CE (1'd0), + .IDATAIN (main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_ibuf), + .INC (1'd0), + .LD (1'd0), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_idelay) ); +//------------------------------------------------------------------------------ +// Instance IDDR of IDDR Module. +//------------------------------------------------------------------------------ IDDR #( - .DDR_CLK_EDGE("SAME_EDGE_PIPELINED") + // Parameters. + .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED") ) IDDR ( - .C(eth_rx_clk), - .CE(1'd1), - .D(main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_idelay), - .R(1'd0), - .S(1'd0), - .Q1(main_maccore_ethphy_liteethphyrgmiirx_rx_ctl), - .Q2(main_maccore_ethphy_liteethphyrgmiirx) + // Inputs. + .C (eth_rx_clk), + .CE (1'd1), + .D (main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_idelay), + .R (1'd0), + .S (1'd0), + + // Outputs. + .Q1 (main_maccore_ethphy_liteethphyrgmiirx_rx_ctl), + .Q2 (main_maccore_ethphy_liteethphyrgmiirx) ); +//------------------------------------------------------------------------------ +// Instance IBUF_2 of IBUF Module. +//------------------------------------------------------------------------------ IBUF IBUF_2( - .I(rgmii_eth_rx_data[0]), - .O(main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[0]) + // Inputs. + .I (rgmii_rx_data[0]), + + // Outputs. + .O (main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_1 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .IDELAY_TYPE("FIXED"), - .IDELAY_VALUE(5'd26), - .REFCLK_FREQUENCY(200.0) + // Parameters. + .IDELAY_TYPE ("FIXED"), + .IDELAY_VALUE (5'd26), + .REFCLK_FREQUENCY (200.0) ) IDELAYE2_1 ( - .C(1'd0), - .CE(1'd0), - .IDATAIN(main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[0]), - .INC(1'd0), - .LD(1'd0), - .LDPIPEEN(1'd0), - .DATAOUT(main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[0]) + // Inputs. + .C (1'd0), + .CE (1'd0), + .IDATAIN (main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[0]), + .INC (1'd0), + .LD (1'd0), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[0]) ); +//------------------------------------------------------------------------------ +// Instance IDDR_1 of IDDR Module. +//------------------------------------------------------------------------------ IDDR #( - .DDR_CLK_EDGE("SAME_EDGE_PIPELINED") + // Parameters. + .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED") ) IDDR_1 ( - .C(eth_rx_clk), - .CE(1'd1), - .D(main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[0]), - .R(1'd0), - .S(1'd0), - .Q1(main_maccore_ethphy_liteethphyrgmiirx_rx_data[0]), - .Q2(main_maccore_ethphy_liteethphyrgmiirx_rx_data[4]) + // Inputs. + .C (eth_rx_clk), + .CE (1'd1), + .D (main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[0]), + .R (1'd0), + .S (1'd0), + + // Outputs. + .Q1 (main_maccore_ethphy_liteethphyrgmiirx_rx_data[0]), + .Q2 (main_maccore_ethphy_liteethphyrgmiirx_rx_data[4]) ); +//------------------------------------------------------------------------------ +// Instance IBUF_3 of IBUF Module. +//------------------------------------------------------------------------------ IBUF IBUF_3( - .I(rgmii_eth_rx_data[1]), - .O(main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[1]) + // Inputs. + .I (rgmii_rx_data[1]), + + // Outputs. + .O (main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[1]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_2 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .IDELAY_TYPE("FIXED"), - .IDELAY_VALUE(5'd26), - .REFCLK_FREQUENCY(200.0) + // Parameters. + .IDELAY_TYPE ("FIXED"), + .IDELAY_VALUE (5'd26), + .REFCLK_FREQUENCY (200.0) ) IDELAYE2_2 ( - .C(1'd0), - .CE(1'd0), - .IDATAIN(main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[1]), - .INC(1'd0), - .LD(1'd0), - .LDPIPEEN(1'd0), - .DATAOUT(main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[1]) + // Inputs. + .C (1'd0), + .CE (1'd0), + .IDATAIN (main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[1]), + .INC (1'd0), + .LD (1'd0), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[1]) ); +//------------------------------------------------------------------------------ +// Instance IDDR_2 of IDDR Module. +//------------------------------------------------------------------------------ IDDR #( - .DDR_CLK_EDGE("SAME_EDGE_PIPELINED") + // Parameters. + .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED") ) IDDR_2 ( - .C(eth_rx_clk), - .CE(1'd1), - .D(main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[1]), - .R(1'd0), - .S(1'd0), - .Q1(main_maccore_ethphy_liteethphyrgmiirx_rx_data[1]), - .Q2(main_maccore_ethphy_liteethphyrgmiirx_rx_data[5]) + // Inputs. + .C (eth_rx_clk), + .CE (1'd1), + .D (main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[1]), + .R (1'd0), + .S (1'd0), + + // Outputs. + .Q1 (main_maccore_ethphy_liteethphyrgmiirx_rx_data[1]), + .Q2 (main_maccore_ethphy_liteethphyrgmiirx_rx_data[5]) ); +//------------------------------------------------------------------------------ +// Instance IBUF_4 of IBUF Module. +//------------------------------------------------------------------------------ IBUF IBUF_4( - .I(rgmii_eth_rx_data[2]), - .O(main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[2]) + // Inputs. + .I (rgmii_rx_data[2]), + + // Outputs. + .O (main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[2]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_3 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .IDELAY_TYPE("FIXED"), - .IDELAY_VALUE(5'd26), - .REFCLK_FREQUENCY(200.0) + // Parameters. + .IDELAY_TYPE ("FIXED"), + .IDELAY_VALUE (5'd26), + .REFCLK_FREQUENCY (200.0) ) IDELAYE2_3 ( - .C(1'd0), - .CE(1'd0), - .IDATAIN(main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[2]), - .INC(1'd0), - .LD(1'd0), - .LDPIPEEN(1'd0), - .DATAOUT(main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[2]) + // Inputs. + .C (1'd0), + .CE (1'd0), + .IDATAIN (main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[2]), + .INC (1'd0), + .LD (1'd0), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[2]) ); +//------------------------------------------------------------------------------ +// Instance IDDR_3 of IDDR Module. +//------------------------------------------------------------------------------ IDDR #( - .DDR_CLK_EDGE("SAME_EDGE_PIPELINED") + // Parameters. + .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED") ) IDDR_3 ( - .C(eth_rx_clk), - .CE(1'd1), - .D(main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[2]), - .R(1'd0), - .S(1'd0), - .Q1(main_maccore_ethphy_liteethphyrgmiirx_rx_data[2]), - .Q2(main_maccore_ethphy_liteethphyrgmiirx_rx_data[6]) + // Inputs. + .C (eth_rx_clk), + .CE (1'd1), + .D (main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[2]), + .R (1'd0), + .S (1'd0), + + // Outputs. + .Q1 (main_maccore_ethphy_liteethphyrgmiirx_rx_data[2]), + .Q2 (main_maccore_ethphy_liteethphyrgmiirx_rx_data[6]) ); +//------------------------------------------------------------------------------ +// Instance IBUF_5 of IBUF Module. +//------------------------------------------------------------------------------ IBUF IBUF_5( - .I(rgmii_eth_rx_data[3]), - .O(main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[3]) + // Inputs. + .I (rgmii_rx_data[3]), + + // Outputs. + .O (main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[3]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_4 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .IDELAY_TYPE("FIXED"), - .IDELAY_VALUE(5'd26), - .REFCLK_FREQUENCY(200.0) + // Parameters. + .IDELAY_TYPE ("FIXED"), + .IDELAY_VALUE (5'd26), + .REFCLK_FREQUENCY (200.0) ) IDELAYE2_4 ( - .C(1'd0), - .CE(1'd0), - .IDATAIN(main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[3]), - .INC(1'd0), - .LD(1'd0), - .LDPIPEEN(1'd0), - .DATAOUT(main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[3]) + // Inputs. + .C (1'd0), + .CE (1'd0), + .IDATAIN (main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[3]), + .INC (1'd0), + .LD (1'd0), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[3]) ); +//------------------------------------------------------------------------------ +// Instance IDDR_4 of IDDR Module. +//------------------------------------------------------------------------------ IDDR #( - .DDR_CLK_EDGE("SAME_EDGE_PIPELINED") + // Parameters. + .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED") ) IDDR_4 ( - .C(eth_rx_clk), - .CE(1'd1), - .D(main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[3]), - .R(1'd0), - .S(1'd0), - .Q1(main_maccore_ethphy_liteethphyrgmiirx_rx_data[3]), - .Q2(main_maccore_ethphy_liteethphyrgmiirx_rx_data[7]) + // Inputs. + .C (eth_rx_clk), + .CE (1'd1), + .D (main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[3]), + .R (1'd0), + .S (1'd0), + + // Outputs. + .Q1 (main_maccore_ethphy_liteethphyrgmiirx_rx_data[3]), + .Q2 (main_maccore_ethphy_liteethphyrgmiirx_rx_data[7]) ); -assign rgmii_eth_mdio = main_maccore_ethphy_data_oe ? main_maccore_ethphy_data_w : 1'bz; -assign main_maccore_ethphy_data_r = rgmii_eth_mdio; +assign rgmii_mdio = main_maccore_ethphy_data_oe ? main_maccore_ethphy_data_w : 1'bz; +assign main_maccore_ethphy_data_r = rgmii_mdio; -reg [11:0] storage[0:4]; -reg [11:0] memdat; -always @(posedge eth_rx_clk) begin - if (main_liteethmaccrc32checker_syncfifo_wrport_we) - storage[main_liteethmaccrc32checker_syncfifo_wrport_adr] <= main_liteethmaccrc32checker_syncfifo_wrport_dat_w; - memdat <= storage[main_liteethmaccrc32checker_syncfifo_wrport_adr]; +//------------------------------------------------------------------------------ +// Memory storage: 32-words x 42-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 42 +// Port 1 | Read: Sync | Write: ---- | +reg [41:0] storage[0:31]; +reg [41:0] storage_dat0; +reg [41:0] storage_dat1; +always @(posedge sys_clk) begin + if (main_tx_cdc_cdc_wrport_we) + storage[main_tx_cdc_cdc_wrport_adr] <= main_tx_cdc_cdc_wrport_dat_w; + storage_dat0 <= storage[main_tx_cdc_cdc_wrport_adr]; end - -always @(posedge eth_rx_clk) begin +always @(posedge eth_tx_clk) begin + storage_dat1 <= storage[main_tx_cdc_cdc_rdport_adr]; end +assign main_tx_cdc_cdc_wrport_dat_r = storage_dat0; +assign main_tx_cdc_cdc_rdport_dat_r = storage_dat1; -assign main_liteethmaccrc32checker_syncfifo_wrport_dat_r = memdat; -assign main_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage[main_liteethmaccrc32checker_syncfifo_rdport_adr]; -reg [41:0] storage_1[0:31]; -reg [4:0] memadr; -reg [4:0] memadr_1; -always @(posedge sys_clk) begin - if (main_tx_cdc_cdc_wrport_we) - storage_1[main_tx_cdc_cdc_wrport_adr] <= main_tx_cdc_cdc_wrport_dat_w; - memadr <= main_tx_cdc_cdc_wrport_adr; +//------------------------------------------------------------------------------ +// Memory storage_1: 5-words x 12-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 12 +// Port 1 | Read: Async | Write: ---- | +reg [11:0] storage_1[0:4]; +reg [11:0] storage_1_dat0; +always @(posedge eth_rx_clk) begin + if (main_liteethmaccrc32checker_syncfifo_wrport_we) + storage_1[main_liteethmaccrc32checker_syncfifo_wrport_adr] <= main_liteethmaccrc32checker_syncfifo_wrport_dat_w; + storage_1_dat0 <= storage_1[main_liteethmaccrc32checker_syncfifo_wrport_adr]; end - -always @(posedge eth_tx_clk) begin - memadr_1 <= main_tx_cdc_cdc_rdport_adr; +always @(posedge eth_rx_clk) begin end +assign main_liteethmaccrc32checker_syncfifo_wrport_dat_r = storage_1_dat0; +assign main_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage_1[main_liteethmaccrc32checker_syncfifo_rdport_adr]; -assign main_tx_cdc_cdc_wrport_dat_r = storage_1[memadr]; -assign main_tx_cdc_cdc_rdport_dat_r = storage_1[memadr_1]; +//------------------------------------------------------------------------------ +// Memory storage_2: 32-words x 42-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 42 +// Port 1 | Read: Sync | Write: ---- | reg [41:0] storage_2[0:31]; -reg [4:0] memadr_2; -reg [4:0] memadr_3; +reg [41:0] storage_2_dat0; +reg [41:0] storage_2_dat1; always @(posedge eth_rx_clk) begin if (main_rx_cdc_cdc_wrport_we) storage_2[main_rx_cdc_cdc_wrport_adr] <= main_rx_cdc_cdc_wrport_dat_w; - memadr_2 <= main_rx_cdc_cdc_wrport_adr; + storage_2_dat0 <= storage_2[main_rx_cdc_cdc_wrport_adr]; end - always @(posedge sys_clk) begin - memadr_3 <= main_rx_cdc_cdc_rdport_adr; + storage_2_dat1 <= storage_2[main_rx_cdc_cdc_rdport_adr]; end +assign main_rx_cdc_cdc_wrport_dat_r = storage_2_dat0; +assign main_rx_cdc_cdc_rdport_dat_r = storage_2_dat1; -assign main_rx_cdc_cdc_wrport_dat_r = storage_2[memadr_2]; -assign main_rx_cdc_cdc_rdport_dat_r = storage_2[memadr_3]; -reg [34:0] storage_3[0:1]; -reg [34:0] memdat_1; +//------------------------------------------------------------------------------ +// Memory storage_3: 2-words x 14-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 14 +// Port 1 | Read: Async | Write: ---- | +reg [13:0] storage_3[0:1]; +reg [13:0] storage_3_dat0; always @(posedge sys_clk) begin - if (main_writer_stat_fifo_wrport_we) - storage_3[main_writer_stat_fifo_wrport_adr] <= main_writer_stat_fifo_wrport_dat_w; - memdat_1 <= storage_3[main_writer_stat_fifo_wrport_adr]; + if (main_sram61_we) + storage_3[main_sram59_adr] <= main_sram62_dat_w; + storage_3_dat0 <= storage_3[main_sram59_adr]; end - always @(posedge sys_clk) begin end +assign main_sram60_dat_r = storage_3_dat0; +assign main_sram65_dat_r = storage_3[main_sram64_adr]; -assign main_writer_stat_fifo_wrport_dat_r = memdat_1; -assign main_writer_stat_fifo_rdport_dat_r = storage_3[main_writer_stat_fifo_rdport_adr]; -reg [31:0] mem[0:381]; -reg [8:0] memadr_4; -reg [31:0] memdat_2; +//------------------------------------------------------------------------------ +// Memory mem: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 32 +// Port 1 | Read: Sync | Write: ---- | +reg [31:0] mem[0:382]; +reg [8:0] mem_adr0; +reg [31:0] mem_dat1; always @(posedge sys_clk) begin - if (main_writer_memory0_we) - mem[main_writer_memory0_adr] <= main_writer_memory0_dat_w; - memadr_4 <= main_writer_memory0_adr; + if (main_sram77_we) + mem[main_sram75_adr] <= main_sram78_dat_w; + mem_adr0 <= main_sram75_adr; end - always @(posedge sys_clk) begin - memdat_2 <= mem[main_sram0_adr0]; + mem_dat1 <= mem[main_sram0_adr]; end +assign main_sram76_dat_r = mem[mem_adr0]; +assign main_sram0_dat_r = mem_dat1; -assign main_writer_memory0_dat_r = mem[memadr_4]; -assign main_sram0_dat_r0 = memdat_2; -reg [31:0] mem_1[0:381]; -reg [8:0] memadr_5; -reg [31:0] memdat_3; +//------------------------------------------------------------------------------ +// Memory mem_1: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 32 +// Port 1 | Read: Sync | Write: ---- | +reg [31:0] mem_1[0:382]; +reg [8:0] mem_1_adr0; +reg [31:0] mem_1_dat1; always @(posedge sys_clk) begin - if (main_writer_memory1_we) - mem_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w; - memadr_5 <= main_writer_memory1_adr; + if (main_sram81_we) + mem_1[main_sram79_adr] <= main_sram82_dat_w; + mem_1_adr0 <= main_sram79_adr; end - always @(posedge sys_clk) begin - memdat_3 <= mem_1[main_sram1_adr0]; + mem_1_dat1 <= mem_1[main_sram1_adr]; end +assign main_sram80_dat_r = mem_1[mem_1_adr0]; +assign main_sram1_dat_r = mem_1_dat1; -assign main_writer_memory1_dat_r = mem_1[memadr_5]; -assign main_sram1_dat_r0 = memdat_3; +//------------------------------------------------------------------------------ +// Memory storage_4: 2-words x 14-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 14 +// Port 1 | Read: Async | Write: ---- | reg [13:0] storage_4[0:1]; -reg [13:0] memdat_4; +reg [13:0] storage_4_dat0; always @(posedge sys_clk) begin - if (main_reader_cmd_fifo_wrport_we) - storage_4[main_reader_cmd_fifo_wrport_adr] <= main_reader_cmd_fifo_wrport_dat_w; - memdat_4 <= storage_4[main_reader_cmd_fifo_wrport_adr]; + if (main_sram147_we) + storage_4[main_sram145_adr] <= main_sram148_dat_w; + storage_4_dat0 <= storage_4[main_sram145_adr]; end - always @(posedge sys_clk) begin end +assign main_sram146_dat_r = storage_4_dat0; +assign main_sram151_dat_r = storage_4[main_sram150_adr]; -assign main_reader_cmd_fifo_wrport_dat_r = memdat_4; -assign main_reader_cmd_fifo_rdport_dat_r = storage_4[main_reader_cmd_fifo_rdport_adr]; -reg [31:0] mem_2[0:381]; -reg [8:0] memadr_6; -reg [8:0] memadr_7; +//------------------------------------------------------------------------------ +// Memory mem_2: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +reg [31:0] mem_2[0:382]; +reg [31:0] mem_2_dat0; +reg [8:0] mem_2_adr1; always @(posedge sys_clk) begin - memadr_6 <= main_reader_memory0_adr; + if (main_sram163_re) + mem_2_dat0 <= mem_2[main_sram161_adr]; end +always @(posedge sys_clk) begin + if (main_sram2_we[0]) + mem_2[main_sram2_adr][7:0] <= main_sram2_dat_w[7:0]; + if (main_sram2_we[1]) + mem_2[main_sram2_adr][15:8] <= main_sram2_dat_w[15:8]; + if (main_sram2_we[2]) + mem_2[main_sram2_adr][23:16] <= main_sram2_dat_w[23:16]; + if (main_sram2_we[3]) + mem_2[main_sram2_adr][31:24] <= main_sram2_dat_w[31:24]; + mem_2_adr1 <= main_sram2_adr; +end +assign main_sram162_dat_r = mem_2_dat0; +assign main_sram2_dat_r = mem_2[mem_2_adr1]; + +//------------------------------------------------------------------------------ +// Memory mem_3: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +reg [31:0] mem_3[0:382]; +reg [31:0] mem_3_dat0; +reg [8:0] mem_3_adr1; always @(posedge sys_clk) begin - if (main_sram0_we[0]) - mem_2[main_sram0_adr1][7:0] <= main_sram0_dat_w[7:0]; - if (main_sram0_we[1]) - mem_2[main_sram0_adr1][15:8] <= main_sram0_dat_w[15:8]; - if (main_sram0_we[2]) - mem_2[main_sram0_adr1][23:16] <= main_sram0_dat_w[23:16]; - if (main_sram0_we[3]) - mem_2[main_sram0_adr1][31:24] <= main_sram0_dat_w[31:24]; - memadr_7 <= main_sram0_adr1; -end - -assign main_reader_memory0_dat_r = mem_2[memadr_6]; -assign main_sram0_dat_r1 = mem_2[memadr_7]; - -reg [31:0] mem_3[0:381]; -reg [8:0] memadr_8; -reg [8:0] memadr_9; + if (main_sram166_re) + mem_3_dat0 <= mem_3[main_sram164_adr]; +end always @(posedge sys_clk) begin - memadr_8 <= main_reader_memory1_adr; + if (main_sram3_we[0]) + mem_3[main_sram3_adr][7:0] <= main_sram3_dat_w[7:0]; + if (main_sram3_we[1]) + mem_3[main_sram3_adr][15:8] <= main_sram3_dat_w[15:8]; + if (main_sram3_we[2]) + mem_3[main_sram3_adr][23:16] <= main_sram3_dat_w[23:16]; + if (main_sram3_we[3]) + mem_3[main_sram3_adr][31:24] <= main_sram3_dat_w[31:24]; + mem_3_adr1 <= main_sram3_adr; end +assign main_sram165_dat_r = mem_3_dat0; +assign main_sram3_dat_r = mem_3[mem_3_adr1]; -always @(posedge sys_clk) begin - if (main_sram1_we[0]) - mem_3[main_sram1_adr1][7:0] <= main_sram1_dat_w[7:0]; - if (main_sram1_we[1]) - mem_3[main_sram1_adr1][15:8] <= main_sram1_dat_w[15:8]; - if (main_sram1_we[2]) - mem_3[main_sram1_adr1][23:16] <= main_sram1_dat_w[23:16]; - if (main_sram1_we[3]) - mem_3[main_sram1_adr1][31:24] <= main_sram1_dat_w[31:24]; - memadr_9 <= main_sram1_adr1; -end - -assign main_reader_memory1_dat_r = mem_3[memadr_8]; -assign main_sram1_dat_r1 = mem_3[memadr_9]; - -FD FD( - .C(main_maccore_ethphy_clkin), - .D(main_maccore_ethphy_reset0), - .Q(builder_reset0) + +//------------------------------------------------------------------------------ +// Instance FDCE of FDCE Module. +//------------------------------------------------------------------------------ +FDCE FDCE( + // Inputs. + .C (main_maccore_ethphy_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (main_maccore_ethphy_reset0), + + // Outputs. + .Q (builder_reset0) ); -FD FD_1( - .C(main_maccore_ethphy_clkin), - .D(builder_reset0), - .Q(builder_reset1) +//------------------------------------------------------------------------------ +// Instance FDCE_1 of FDCE Module. +//------------------------------------------------------------------------------ +FDCE FDCE_1( + // Inputs. + .C (main_maccore_ethphy_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset0), + + // Outputs. + .Q (builder_reset1) ); -FD FD_2( - .C(main_maccore_ethphy_clkin), - .D(builder_reset1), - .Q(builder_reset2) +//------------------------------------------------------------------------------ +// Instance FDCE_2 of FDCE Module. +//------------------------------------------------------------------------------ +FDCE FDCE_2( + // Inputs. + .C (main_maccore_ethphy_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset1), + + // Outputs. + .Q (builder_reset2) ); -FD FD_3( - .C(main_maccore_ethphy_clkin), - .D(builder_reset2), - .Q(builder_reset3) +//------------------------------------------------------------------------------ +// Instance FDCE_3 of FDCE Module. +//------------------------------------------------------------------------------ +FDCE FDCE_3( + // Inputs. + .C (main_maccore_ethphy_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset2), + + // Outputs. + .Q (builder_reset3) ); -FD FD_4( - .C(main_maccore_ethphy_clkin), - .D(builder_reset3), - .Q(builder_reset4) +//------------------------------------------------------------------------------ +// Instance FDCE_4 of FDCE Module. +//------------------------------------------------------------------------------ +FDCE FDCE_4( + // Inputs. + .C (main_maccore_ethphy_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset3), + + // Outputs. + .Q (builder_reset4) ); -FD FD_5( - .C(main_maccore_ethphy_clkin), - .D(builder_reset4), - .Q(builder_reset5) +//------------------------------------------------------------------------------ +// Instance FDCE_5 of FDCE Module. +//------------------------------------------------------------------------------ +FDCE FDCE_5( + // Inputs. + .C (main_maccore_ethphy_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset4), + + // Outputs. + .Q (builder_reset5) ); -FD FD_6( - .C(main_maccore_ethphy_clkin), - .D(builder_reset5), - .Q(builder_reset6) +//------------------------------------------------------------------------------ +// Instance FDCE_6 of FDCE Module. +//------------------------------------------------------------------------------ +FDCE FDCE_6( + // Inputs. + .C (main_maccore_ethphy_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset5), + + // Outputs. + .Q (builder_reset6) ); -FD FD_7( - .C(main_maccore_ethphy_clkin), - .D(builder_reset6), - .Q(builder_reset7) +//------------------------------------------------------------------------------ +// Instance FDCE_7 of FDCE Module. +//------------------------------------------------------------------------------ +FDCE FDCE_7( + // Inputs. + .C (main_maccore_ethphy_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset6), + + // Outputs. + .Q (builder_reset7) ); +//------------------------------------------------------------------------------ +// Instance PLLE2_ADV of PLLE2_ADV Module. +//------------------------------------------------------------------------------ PLLE2_ADV #( - .CLKFBOUT_MULT(4'd12), - .CLKIN1_PERIOD(8.0), - .CLKOUT0_DIVIDE(4'd12), - .CLKOUT0_PHASE(1'd0), - .CLKOUT1_DIVIDE(4'd12), - .CLKOUT1_PHASE(90.0), - .DIVCLK_DIVIDE(1'd1), - .REF_JITTER1(0.01), - .STARTUP_WAIT("FALSE") + // Parameters. + .CLKFBOUT_MULT (4'd12), + .CLKIN1_PERIOD (8.0), + .CLKOUT0_DIVIDE (4'd12), + .CLKOUT0_PHASE (1'd0), + .CLKOUT1_DIVIDE (4'd12), + .CLKOUT1_PHASE (90.0), + .DIVCLK_DIVIDE (1'd1), + .REF_JITTER1 (0.01), + .STARTUP_WAIT ("FALSE") ) PLLE2_ADV ( - .CLKFBIN(builder_pll_fb), - .CLKIN1(main_maccore_ethphy_clkin), - .PWRDWN(main_maccore_ethphy_power_down), - .RST(builder_reset7), - .CLKFBOUT(builder_pll_fb), - .CLKOUT0(main_maccore_ethphy_clkout0), - .CLKOUT1(main_maccore_ethphy_clkout1), - .LOCKED(main_maccore_ethphy_locked) + // Inputs. + .CLKFBIN (builder_pll_fb), + .CLKIN1 (main_maccore_ethphy_clkin), + .PWRDWN (main_maccore_ethphy_power_down), + .RST (builder_reset7), + + // Outputs. + .CLKFBOUT (builder_pll_fb), + .CLKOUT0 (main_maccore_ethphy_clkout0), + .CLKOUT1 (main_maccore_ethphy_clkout1), + .LOCKED (main_maccore_ethphy_locked) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE ( - .C(eth_tx_delayed_clk), - .CE(1'd1), - .D(1'd0), - .PRE(builder_xilinxasyncresetsynchronizerimpl0), - .Q(builder_xilinxasyncresetsynchronizerimpl0_rst_meta) + // Inputs. + .C (eth_tx_delayed_clk), + .CE (1'd1), + .D (1'd0), + .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl0_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_1 of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE_1 ( - .C(eth_tx_delayed_clk), - .CE(1'd1), - .D(builder_xilinxasyncresetsynchronizerimpl0_rst_meta), - .PRE(builder_xilinxasyncresetsynchronizerimpl0), - .Q(builder_xilinxasyncresetsynchronizerimpl0_expr) + // Inputs. + .C (eth_tx_delayed_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl0_rst_meta), + .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl0_expr) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_2 of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE_2 ( - .C(eth_tx_clk), - .CE(1'd1), - .D(1'd0), - .PRE(main_maccore_ethphy_reset1), - .Q(builder_xilinxasyncresetsynchronizerimpl1_rst_meta) + // Inputs. + .C (eth_tx_clk), + .CE (1'd1), + .D (1'd0), + .PRE (main_maccore_ethphy_reset1), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl1_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_3 of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE_3 ( - .C(eth_tx_clk), - .CE(1'd1), - .D(builder_xilinxasyncresetsynchronizerimpl1_rst_meta), - .PRE(main_maccore_ethphy_reset1), - .Q(eth_tx_rst) + // Inputs. + .C (eth_tx_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl1_rst_meta), + .PRE (main_maccore_ethphy_reset1), + + // Outputs. + .Q (eth_tx_rst) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_4 of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE_4 ( - .C(eth_rx_clk), - .CE(1'd1), - .D(1'd0), - .PRE(main_maccore_ethphy_reset1), - .Q(builder_xilinxasyncresetsynchronizerimpl2_rst_meta) + // Inputs. + .C (eth_rx_clk), + .CE (1'd1), + .D (1'd0), + .PRE (main_maccore_ethphy_reset1), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl2_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_5 of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE_5 ( - .C(eth_rx_clk), - .CE(1'd1), - .D(builder_xilinxasyncresetsynchronizerimpl2_rst_meta), - .PRE(main_maccore_ethphy_reset1), - .Q(eth_rx_rst) + // Inputs. + .C (eth_rx_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl2_rst_meta), + .PRE (main_maccore_ethphy_reset1), + + // Outputs. + .Q (eth_rx_rst) ); endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2024-04-05 17:38:49. +//------------------------------------------------------------------------------ diff --git a/liteeth/generated/wukong-v2/liteeth_core.v b/liteeth/generated/wukong-v2/liteeth_core.v index ba65299..9a2da5a 100644 --- a/liteeth/generated/wukong-v2/liteeth_core.v +++ b/liteeth/generated/wukong-v2/liteeth_core.v @@ -1,3810 +1,4453 @@ -//-------------------------------------------------------------------------------- -// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:37:01 -//-------------------------------------------------------------------------------- -module liteeth_core( - input wire sys_clock, - input wire sys_reset, - input wire gmii_eth_clocks_tx, - output wire gmii_eth_clocks_gtx, - input wire gmii_eth_clocks_rx, - output wire gmii_eth_rst_n, - input wire gmii_eth_int_n, - inout wire gmii_eth_mdio, - output wire gmii_eth_mdc, - input wire gmii_eth_rx_dv, - input wire gmii_eth_rx_er, - input wire [7:0] gmii_eth_rx_data, - output reg gmii_eth_tx_en, - output wire gmii_eth_tx_er, - output reg [7:0] gmii_eth_tx_data, - input wire gmii_eth_col, - input wire gmii_eth_crs, - input wire [29:0] wishbone_adr, - input wire [31:0] wishbone_dat_w, - output wire [31:0] wishbone_dat_r, - input wire [3:0] wishbone_sel, - input wire wishbone_cyc, - input wire wishbone_stb, - output wire wishbone_ack, - input wire wishbone_we, - input wire [2:0] wishbone_cti, - input wire [1:0] wishbone_bte, - output wire wishbone_err, - output wire interrupt +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : liteeth_core.v +// Device : xc7 +// LiteX sha1 : 87137c30 +// Date : 2024-04-05 17:38:50 +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ps + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module liteeth_core ( + output wire gmii_clocks_gtx, + input wire gmii_clocks_rx, + input wire gmii_clocks_tx, + input wire gmii_col, + input wire gmii_crs, + input wire gmii_int_n, + output wire gmii_mdc, + inout wire gmii_mdio, + output wire gmii_rst_n, + input wire [7:0] gmii_rx_data, + input wire gmii_rx_dv, + input wire gmii_rx_er, + output reg [7:0] gmii_tx_data, + output reg gmii_tx_en, + output wire gmii_tx_er, + output wire interrupt, + input wire sys_clock, + input wire sys_reset, + output wire wishbone_ack, + input wire [29:0] wishbone_adr, + input wire [1:0] wishbone_bte, + input wire [2:0] wishbone_cti, + input wire wishbone_cyc, + output wire [31:0] wishbone_dat_r, + input wire [31:0] wishbone_dat_w, + output wire wishbone_err, + input wire [3:0] wishbone_sel, + input wire wishbone_stb, + input wire wishbone_we ); -reg maccore_maccore_soc_rst = 1'd0; -wire maccore_maccore_cpu_rst; -reg [1:0] maccore_maccore_reset_storage = 2'd0; -reg maccore_maccore_reset_re = 1'd0; -reg [31:0] maccore_maccore_scratch_storage = 32'd305419896; -reg maccore_maccore_scratch_re = 1'd0; -wire [31:0] maccore_maccore_bus_errors_status; -wire maccore_maccore_bus_errors_we; -reg maccore_maccore_bus_errors_re = 1'd0; -wire maccore_maccore_bus_error; -reg [31:0] maccore_maccore_bus_errors = 32'd0; -(* dont_touch = "true" *) wire sys_clk; -wire sys_rst; -wire por_clk; -reg maccore_int_rst = 1'd1; -reg maccore_ethphy_mode0 = 1'd0; -wire maccore_ethphy_mode_status; -wire maccore_ethphy_mode_we; -reg maccore_ethphy_mode_re = 1'd0; -reg maccore_ethphy_mode1 = 1'd0; -reg maccore_ethphy_update_mode = 1'd0; -wire maccore_ethphy_eth_tick; -reg [9:0] maccore_ethphy_eth_counter = 10'd0; -wire maccore_ethphy_sys_tick; -wire maccore_ethphy_i; -wire maccore_ethphy_o; -reg maccore_ethphy_toggle_i = 1'd0; -wire maccore_ethphy_toggle_o; -reg maccore_ethphy_toggle_o_r = 1'd0; -reg [23:0] maccore_ethphy_sys_counter = 24'd0; -reg maccore_ethphy_sys_counter_reset = 1'd0; -reg maccore_ethphy_sys_counter_ce = 1'd0; -reg maccore_ethphy_reset_storage = 1'd0; -reg maccore_ethphy_reset_re = 1'd0; -(* dont_touch = "true" *) wire eth_rx_clk; -wire eth_rx_rst; -(* dont_touch = "true" *) wire eth_tx_clk; -wire eth_tx_rst; -reg maccore_ethphy_eth_tx_clk = 1'd0; -wire maccore_ethphy_reset0; -wire maccore_ethphy_reset1; -reg [8:0] maccore_ethphy_counter = 9'd0; -wire maccore_ethphy_counter_done; -wire maccore_ethphy_counter_ce; -wire maccore_ethphy_liteethphygmiimiitx_sink_sink_valid0; -wire maccore_ethphy_liteethphygmiimiitx_sink_sink_ready0; -wire maccore_ethphy_liteethphygmiimiitx_sink_sink_first0; -wire maccore_ethphy_liteethphygmiimiitx_sink_sink_last0; -wire [7:0] maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_data0; -wire maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_last_be0; -wire maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_error0; -reg maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_er = 1'd0; -reg maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_en = 1'd0; -reg [7:0] maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_data = 8'd0; -wire maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_valid; -reg maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_ready = 1'd0; -wire maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_first; -wire maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_last; -wire [7:0] maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_data; -wire maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_last_be; -wire maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_error; -reg maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_er = 1'd0; -reg maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_en = 1'd0; -reg [7:0] maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_data = 8'd0; -wire maccore_ethphy_liteethphygmiimiitx_sink_sink_valid1; -wire maccore_ethphy_liteethphygmiimiitx_sink_sink_ready1; -wire maccore_ethphy_liteethphygmiimiitx_sink_sink_first1; -wire maccore_ethphy_liteethphygmiimiitx_sink_sink_last1; -wire [7:0] maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_data1; -wire maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_last_be1; -wire maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_error1; -wire maccore_ethphy_liteethphygmiimiitx_converter_sink_valid; -wire maccore_ethphy_liteethphygmiimiitx_converter_sink_ready; -reg maccore_ethphy_liteethphygmiimiitx_converter_sink_first = 1'd0; -reg maccore_ethphy_liteethphygmiimiitx_converter_sink_last = 1'd0; -wire [7:0] maccore_ethphy_liteethphygmiimiitx_converter_sink_payload_data; -wire maccore_ethphy_liteethphygmiimiitx_converter_source_valid; -wire maccore_ethphy_liteethphygmiimiitx_converter_source_ready; -wire maccore_ethphy_liteethphygmiimiitx_converter_source_first; -wire maccore_ethphy_liteethphygmiimiitx_converter_source_last; -wire [3:0] maccore_ethphy_liteethphygmiimiitx_converter_source_payload_data; -wire maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_valid; -wire maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_ready; -wire maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_first; -wire maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_last; -reg [7:0] maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_payload_data = 8'd0; -wire maccore_ethphy_liteethphygmiimiitx_converter_converter_source_valid; -wire maccore_ethphy_liteethphygmiimiitx_converter_converter_source_ready; -wire maccore_ethphy_liteethphygmiimiitx_converter_converter_source_first; -wire maccore_ethphy_liteethphygmiimiitx_converter_converter_source_last; -reg [3:0] maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_data = 4'd0; -wire maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_valid_token_count; -reg maccore_ethphy_liteethphygmiimiitx_converter_converter_mux = 1'd0; -wire maccore_ethphy_liteethphygmiimiitx_converter_converter_first; -wire maccore_ethphy_liteethphygmiimiitx_converter_converter_last; -wire maccore_ethphy_liteethphygmiimiitx_converter_source_source_valid; -wire maccore_ethphy_liteethphygmiimiitx_converter_source_source_ready; -wire maccore_ethphy_liteethphygmiimiitx_converter_source_source_first; -wire maccore_ethphy_liteethphygmiimiitx_converter_source_source_last; -wire [3:0] maccore_ethphy_liteethphygmiimiitx_converter_source_source_payload_data; -wire maccore_ethphy_liteethphygmiimiitx_demux_sink_valid; -reg maccore_ethphy_liteethphygmiimiitx_demux_sink_ready = 1'd0; -wire maccore_ethphy_liteethphygmiimiitx_demux_sink_first; -wire maccore_ethphy_liteethphygmiimiitx_demux_sink_last; -wire [7:0] maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_data; -wire maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_last_be; -wire maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_error; -reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_valid = 1'd0; -wire maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_ready; -reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_first = 1'd0; -reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_last = 1'd0; -reg [7:0] maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_data = 8'd0; -reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_last_be = 1'd0; -reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_error = 1'd0; -reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_valid = 1'd0; -wire maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_ready; -reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_first = 1'd0; -reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_last = 1'd0; -reg [7:0] maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_data = 8'd0; -reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_last_be = 1'd0; -reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_error = 1'd0; -wire maccore_ethphy_liteethphygmiimiitx_demux_sel; -wire maccore_ethphy_liteethphygmiimiirx_source_source_valid0; -wire maccore_ethphy_liteethphygmiimiirx_source_source_ready0; -wire maccore_ethphy_liteethphygmiimiirx_source_source_first0; -wire maccore_ethphy_liteethphygmiimiirx_source_source_last0; -wire [7:0] maccore_ethphy_liteethphygmiimiirx_source_source_payload_data0; -wire maccore_ethphy_liteethphygmiimiirx_source_source_payload_last_be0; -wire maccore_ethphy_liteethphygmiimiirx_source_source_payload_error0; -reg maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv = 1'd0; -reg [7:0] maccore_ethphy_liteethphygmiimiirx_pads_d_rx_data = 8'd0; -reg maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_valid = 1'd0; -wire maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_ready; -reg maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_first = 1'd0; -wire maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_last; -reg [7:0] maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_data = 8'd0; -reg maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_last_be = 1'd0; -reg maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_error = 1'd0; -reg maccore_ethphy_liteethphygmiimiirx_gmii_rx_dv_d = 1'd0; -wire maccore_ethphy_liteethphygmiimiirx_source_source_valid1; -wire maccore_ethphy_liteethphygmiimiirx_source_source_ready1; -wire maccore_ethphy_liteethphygmiimiirx_source_source_first1; -wire maccore_ethphy_liteethphygmiimiirx_source_source_last1; -wire [7:0] maccore_ethphy_liteethphygmiimiirx_source_source_payload_data1; -reg maccore_ethphy_liteethphygmiimiirx_source_source_payload_last_be1 = 1'd0; -reg maccore_ethphy_liteethphygmiimiirx_source_source_payload_error1 = 1'd0; -reg maccore_ethphy_liteethphygmiimiirx_converter_sink_valid = 1'd0; -wire maccore_ethphy_liteethphygmiimiirx_converter_sink_ready; -reg maccore_ethphy_liteethphygmiimiirx_converter_sink_first = 1'd0; -wire maccore_ethphy_liteethphygmiimiirx_converter_sink_last; -reg [3:0] maccore_ethphy_liteethphygmiimiirx_converter_sink_payload_data = 4'd0; -wire maccore_ethphy_liteethphygmiimiirx_converter_source_valid; -wire maccore_ethphy_liteethphygmiimiirx_converter_source_ready; -wire maccore_ethphy_liteethphygmiimiirx_converter_source_first; -wire maccore_ethphy_liteethphygmiimiirx_converter_source_last; -reg [7:0] maccore_ethphy_liteethphygmiimiirx_converter_source_payload_data = 8'd0; -wire maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_valid; -wire maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_ready; -wire maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_first; -wire maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_last; -wire [3:0] maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_payload_data; -wire maccore_ethphy_liteethphygmiimiirx_converter_converter_source_valid; -wire maccore_ethphy_liteethphygmiimiirx_converter_converter_source_ready; -reg maccore_ethphy_liteethphygmiimiirx_converter_converter_source_first = 1'd0; -reg maccore_ethphy_liteethphygmiimiirx_converter_converter_source_last = 1'd0; -reg [7:0] maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_data = 8'd0; -reg [1:0] maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_valid_token_count = 2'd0; -reg maccore_ethphy_liteethphygmiimiirx_converter_converter_demux = 1'd0; -wire maccore_ethphy_liteethphygmiimiirx_converter_converter_load_part; -reg maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all = 1'd0; -wire maccore_ethphy_liteethphygmiimiirx_converter_source_source_valid; -wire maccore_ethphy_liteethphygmiimiirx_converter_source_source_ready; -wire maccore_ethphy_liteethphygmiimiirx_converter_source_source_first; -wire maccore_ethphy_liteethphygmiimiirx_converter_source_source_last; -wire [7:0] maccore_ethphy_liteethphygmiimiirx_converter_source_source_payload_data; -reg maccore_ethphy_liteethphygmiimiirx_converter_reset = 1'd0; -reg maccore_ethphy_liteethphygmiimiirx_mux_source_valid = 1'd0; -wire maccore_ethphy_liteethphygmiimiirx_mux_source_ready; -reg maccore_ethphy_liteethphygmiimiirx_mux_source_first = 1'd0; -reg maccore_ethphy_liteethphygmiimiirx_mux_source_last = 1'd0; -reg [7:0] maccore_ethphy_liteethphygmiimiirx_mux_source_payload_data = 8'd0; -reg maccore_ethphy_liteethphygmiimiirx_mux_source_payload_last_be = 1'd0; -reg maccore_ethphy_liteethphygmiimiirx_mux_source_payload_error = 1'd0; -wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_valid; -reg maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_ready = 1'd0; -wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_first; -wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_last; -wire [7:0] maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_data; -wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_last_be; -wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_error; -wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_valid; -reg maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_ready = 1'd0; -wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_first; -wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_last; -wire [7:0] maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_data; -wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_last_be; -wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_error; -wire maccore_ethphy_liteethphygmiimiirx_mux_sel; -wire maccore_ethphy_mdc; -wire maccore_ethphy_oe; -wire maccore_ethphy_w; -reg [2:0] maccore_ethphy__w_storage = 3'd0; -reg maccore_ethphy__w_re = 1'd0; -reg maccore_ethphy_r = 1'd0; -reg maccore_ethphy__r_status = 1'd0; -wire maccore_ethphy__r_we; -reg maccore_ethphy__r_re = 1'd0; -wire maccore_ethphy_data_w; -wire maccore_ethphy_data_oe; -wire maccore_ethphy_data_r; -wire tx_gap_inserter_sink_valid; -reg tx_gap_inserter_sink_ready = 1'd0; -wire tx_gap_inserter_sink_first; -wire tx_gap_inserter_sink_last; -wire [7:0] tx_gap_inserter_sink_payload_data; -wire tx_gap_inserter_sink_payload_last_be; -wire tx_gap_inserter_sink_payload_error; -reg tx_gap_inserter_source_valid = 1'd0; -wire tx_gap_inserter_source_ready; -reg tx_gap_inserter_source_first = 1'd0; -reg tx_gap_inserter_source_last = 1'd0; -reg [7:0] tx_gap_inserter_source_payload_data = 8'd0; -reg tx_gap_inserter_source_payload_last_be = 1'd0; -reg tx_gap_inserter_source_payload_error = 1'd0; -reg [3:0] tx_gap_inserter_counter = 4'd0; -reg preamble_crc_status = 1'd1; -wire preamble_crc_we; -reg preamble_crc_re = 1'd0; -reg [31:0] preamble_errors_status = 32'd0; -wire preamble_errors_we; -reg preamble_errors_re = 1'd0; -reg [31:0] crc_errors_status = 32'd0; -wire crc_errors_we; -reg crc_errors_re = 1'd0; -wire preamble_inserter_sink_valid; -reg preamble_inserter_sink_ready = 1'd0; -wire preamble_inserter_sink_first; -wire preamble_inserter_sink_last; -wire [7:0] preamble_inserter_sink_payload_data; -wire preamble_inserter_sink_payload_last_be; -wire preamble_inserter_sink_payload_error; -reg preamble_inserter_source_valid = 1'd0; -wire preamble_inserter_source_ready; -reg preamble_inserter_source_first = 1'd0; -reg preamble_inserter_source_last = 1'd0; -reg [7:0] preamble_inserter_source_payload_data = 8'd0; -wire preamble_inserter_source_payload_last_be; -reg preamble_inserter_source_payload_error = 1'd0; -reg [63:0] preamble_inserter_preamble = 64'd15372286728091293013; -reg [2:0] preamble_inserter_count = 3'd0; -wire preamble_checker_sink_valid; -reg preamble_checker_sink_ready = 1'd0; -wire preamble_checker_sink_first; -wire preamble_checker_sink_last; -wire [7:0] preamble_checker_sink_payload_data; -wire preamble_checker_sink_payload_last_be; -wire preamble_checker_sink_payload_error; -reg preamble_checker_source_valid = 1'd0; -wire preamble_checker_source_ready; -reg preamble_checker_source_first = 1'd0; -reg preamble_checker_source_last = 1'd0; -wire [7:0] preamble_checker_source_payload_data; -wire preamble_checker_source_payload_last_be; -reg preamble_checker_source_payload_error = 1'd0; -reg preamble_checker_error = 1'd0; -wire liteethmaccrc32inserter_sink_valid; -reg liteethmaccrc32inserter_sink_ready = 1'd0; -wire liteethmaccrc32inserter_sink_first; -wire liteethmaccrc32inserter_sink_last; -wire [7:0] liteethmaccrc32inserter_sink_payload_data; -wire liteethmaccrc32inserter_sink_payload_last_be; -wire liteethmaccrc32inserter_sink_payload_error; -reg liteethmaccrc32inserter_source_valid = 1'd0; -wire liteethmaccrc32inserter_source_ready; -reg liteethmaccrc32inserter_source_first = 1'd0; -reg liteethmaccrc32inserter_source_last = 1'd0; -reg [7:0] liteethmaccrc32inserter_source_payload_data = 8'd0; -reg liteethmaccrc32inserter_source_payload_last_be = 1'd0; -reg liteethmaccrc32inserter_source_payload_error = 1'd0; -reg [7:0] liteethmaccrc32inserter_data0 = 8'd0; -wire [31:0] liteethmaccrc32inserter_value; -wire liteethmaccrc32inserter_error; -wire [7:0] liteethmaccrc32inserter_data1; -wire [31:0] liteethmaccrc32inserter_last; -reg [31:0] liteethmaccrc32inserter_next = 32'd0; -reg [31:0] liteethmaccrc32inserter_reg = 32'd4294967295; -reg liteethmaccrc32inserter_ce = 1'd0; -reg liteethmaccrc32inserter_reset = 1'd0; -reg [1:0] liteethmaccrc32inserter_cnt = 2'd3; -wire liteethmaccrc32inserter_cnt_done; -reg liteethmaccrc32inserter_is_ongoing0 = 1'd0; -reg liteethmaccrc32inserter_is_ongoing1 = 1'd0; -wire crc32_inserter_sink_valid; -wire crc32_inserter_sink_ready; -wire crc32_inserter_sink_first; -wire crc32_inserter_sink_last; -wire [7:0] crc32_inserter_sink_payload_data; -wire crc32_inserter_sink_payload_last_be; -wire crc32_inserter_sink_payload_error; -reg crc32_inserter_source_valid = 1'd0; -wire crc32_inserter_source_ready; -reg crc32_inserter_source_first = 1'd0; -reg crc32_inserter_source_last = 1'd0; -reg [7:0] crc32_inserter_source_payload_data = 8'd0; -reg crc32_inserter_source_payload_last_be = 1'd0; -reg crc32_inserter_source_payload_error = 1'd0; -wire liteethmaccrc32checker_sink_sink_valid; -reg liteethmaccrc32checker_sink_sink_ready = 1'd0; -wire liteethmaccrc32checker_sink_sink_first; -wire liteethmaccrc32checker_sink_sink_last; -wire [7:0] liteethmaccrc32checker_sink_sink_payload_data; -wire liteethmaccrc32checker_sink_sink_payload_last_be; -wire liteethmaccrc32checker_sink_sink_payload_error; -wire liteethmaccrc32checker_source_source_valid; -wire liteethmaccrc32checker_source_source_ready; -reg liteethmaccrc32checker_source_source_first = 1'd0; -wire liteethmaccrc32checker_source_source_last; -wire [7:0] liteethmaccrc32checker_source_source_payload_data; -wire liteethmaccrc32checker_source_source_payload_last_be; -reg liteethmaccrc32checker_source_source_payload_error = 1'd0; -wire liteethmaccrc32checker_error; -wire [7:0] liteethmaccrc32checker_crc_data0; -wire [31:0] liteethmaccrc32checker_crc_value; -wire liteethmaccrc32checker_crc_error; -wire [7:0] liteethmaccrc32checker_crc_data1; -wire [31:0] liteethmaccrc32checker_crc_last; -reg [31:0] liteethmaccrc32checker_crc_next = 32'd0; -reg [31:0] liteethmaccrc32checker_crc_reg = 32'd4294967295; -reg liteethmaccrc32checker_crc_ce = 1'd0; -reg liteethmaccrc32checker_crc_reset = 1'd0; -reg liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; -wire liteethmaccrc32checker_syncfifo_sink_ready; -wire liteethmaccrc32checker_syncfifo_sink_first; -wire liteethmaccrc32checker_syncfifo_sink_last; -wire [7:0] liteethmaccrc32checker_syncfifo_sink_payload_data; -wire liteethmaccrc32checker_syncfifo_sink_payload_last_be; -wire liteethmaccrc32checker_syncfifo_sink_payload_error; -wire liteethmaccrc32checker_syncfifo_source_valid; -wire liteethmaccrc32checker_syncfifo_source_ready; -wire liteethmaccrc32checker_syncfifo_source_first; -wire liteethmaccrc32checker_syncfifo_source_last; -wire [7:0] liteethmaccrc32checker_syncfifo_source_payload_data; -wire liteethmaccrc32checker_syncfifo_source_payload_last_be; -wire liteethmaccrc32checker_syncfifo_source_payload_error; -wire liteethmaccrc32checker_syncfifo_syncfifo_we; -wire liteethmaccrc32checker_syncfifo_syncfifo_writable; -wire liteethmaccrc32checker_syncfifo_syncfifo_re; -wire liteethmaccrc32checker_syncfifo_syncfifo_readable; -wire [11:0] liteethmaccrc32checker_syncfifo_syncfifo_din; -wire [11:0] liteethmaccrc32checker_syncfifo_syncfifo_dout; -reg [2:0] liteethmaccrc32checker_syncfifo_level = 3'd0; -reg liteethmaccrc32checker_syncfifo_replace = 1'd0; -reg [2:0] liteethmaccrc32checker_syncfifo_produce = 3'd0; -reg [2:0] liteethmaccrc32checker_syncfifo_consume = 3'd0; -reg [2:0] liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; -wire [11:0] liteethmaccrc32checker_syncfifo_wrport_dat_r; -wire liteethmaccrc32checker_syncfifo_wrport_we; -wire [11:0] liteethmaccrc32checker_syncfifo_wrport_dat_w; -wire liteethmaccrc32checker_syncfifo_do_read; -wire [2:0] liteethmaccrc32checker_syncfifo_rdport_adr; -wire [11:0] liteethmaccrc32checker_syncfifo_rdport_dat_r; -wire [7:0] liteethmaccrc32checker_syncfifo_fifo_in_payload_data; -wire liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; -wire liteethmaccrc32checker_syncfifo_fifo_in_payload_error; -wire liteethmaccrc32checker_syncfifo_fifo_in_first; -wire liteethmaccrc32checker_syncfifo_fifo_in_last; -wire [7:0] liteethmaccrc32checker_syncfifo_fifo_out_payload_data; -wire liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; -wire liteethmaccrc32checker_syncfifo_fifo_out_payload_error; -wire liteethmaccrc32checker_syncfifo_fifo_out_first; -wire liteethmaccrc32checker_syncfifo_fifo_out_last; -reg liteethmaccrc32checker_fifo_reset = 1'd0; -wire liteethmaccrc32checker_fifo_in; -wire liteethmaccrc32checker_fifo_out; -wire liteethmaccrc32checker_fifo_full; -wire crc32_checker_sink_valid; -wire crc32_checker_sink_ready; -wire crc32_checker_sink_first; -wire crc32_checker_sink_last; -wire [7:0] crc32_checker_sink_payload_data; -wire crc32_checker_sink_payload_last_be; -wire crc32_checker_sink_payload_error; -reg crc32_checker_source_valid = 1'd0; -wire crc32_checker_source_ready; -reg crc32_checker_source_first = 1'd0; -reg crc32_checker_source_last = 1'd0; -reg [7:0] crc32_checker_source_payload_data = 8'd0; -reg crc32_checker_source_payload_last_be = 1'd0; -reg crc32_checker_source_payload_error = 1'd0; -wire ps_preamble_error_i; -wire ps_preamble_error_o; -reg ps_preamble_error_toggle_i = 1'd0; -wire ps_preamble_error_toggle_o; -reg ps_preamble_error_toggle_o_r = 1'd0; -wire ps_crc_error_i; -wire ps_crc_error_o; -reg ps_crc_error_toggle_i = 1'd0; -wire ps_crc_error_toggle_o; -reg ps_crc_error_toggle_o_r = 1'd0; -wire padding_inserter_sink_valid; -reg padding_inserter_sink_ready = 1'd0; -wire padding_inserter_sink_first; -wire padding_inserter_sink_last; -wire [7:0] padding_inserter_sink_payload_data; -wire padding_inserter_sink_payload_last_be; -wire padding_inserter_sink_payload_error; -reg padding_inserter_source_valid = 1'd0; -wire padding_inserter_source_ready; -reg padding_inserter_source_first = 1'd0; -reg padding_inserter_source_last = 1'd0; -reg [7:0] padding_inserter_source_payload_data = 8'd0; -reg padding_inserter_source_payload_last_be = 1'd0; -reg padding_inserter_source_payload_error = 1'd0; -reg [15:0] padding_inserter_counter = 16'd0; -wire padding_inserter_counter_done; -wire padding_checker_sink_valid; -wire padding_checker_sink_ready; -wire padding_checker_sink_first; -wire padding_checker_sink_last; -wire [7:0] padding_checker_sink_payload_data; -wire padding_checker_sink_payload_last_be; -wire padding_checker_sink_payload_error; -wire padding_checker_source_valid; -wire padding_checker_source_ready; -wire padding_checker_source_first; -wire padding_checker_source_last; -wire [7:0] padding_checker_source_payload_data; -wire padding_checker_source_payload_last_be; -wire padding_checker_source_payload_error; -wire tx_last_be_sink_valid; -reg tx_last_be_sink_ready = 1'd0; -wire tx_last_be_sink_first; -wire tx_last_be_sink_last; -wire [7:0] tx_last_be_sink_payload_data; -wire tx_last_be_sink_payload_last_be; -wire tx_last_be_sink_payload_error; -reg tx_last_be_source_valid = 1'd0; -wire tx_last_be_source_ready; -reg tx_last_be_source_first = 1'd0; -reg tx_last_be_source_last = 1'd0; -reg [7:0] tx_last_be_source_payload_data = 8'd0; -reg tx_last_be_source_payload_last_be = 1'd0; -reg tx_last_be_source_payload_error = 1'd0; -wire rx_last_be_sink_valid; -wire rx_last_be_sink_ready; -wire rx_last_be_sink_first; -wire rx_last_be_sink_last; -wire [7:0] rx_last_be_sink_payload_data; -wire rx_last_be_sink_payload_last_be; -wire rx_last_be_sink_payload_error; -wire rx_last_be_source_valid; -wire rx_last_be_source_ready; -wire rx_last_be_source_first; -wire rx_last_be_source_last; -wire [7:0] rx_last_be_source_payload_data; -reg rx_last_be_source_payload_last_be = 1'd0; -wire rx_last_be_source_payload_error; -wire tx_converter_sink_valid; -wire tx_converter_sink_ready; -wire tx_converter_sink_first; -wire tx_converter_sink_last; -wire [31:0] tx_converter_sink_payload_data; -wire [3:0] tx_converter_sink_payload_last_be; -wire [3:0] tx_converter_sink_payload_error; -wire tx_converter_source_valid; -wire tx_converter_source_ready; -wire tx_converter_source_first; -wire tx_converter_source_last; -wire [7:0] tx_converter_source_payload_data; -wire tx_converter_source_payload_last_be; -wire tx_converter_source_payload_error; -wire tx_converter_converter_sink_valid; -wire tx_converter_converter_sink_ready; -wire tx_converter_converter_sink_first; -wire tx_converter_converter_sink_last; -reg [39:0] tx_converter_converter_sink_payload_data = 40'd0; -wire tx_converter_converter_source_valid; -wire tx_converter_converter_source_ready; -wire tx_converter_converter_source_first; -wire tx_converter_converter_source_last; -reg [9:0] tx_converter_converter_source_payload_data = 10'd0; -wire tx_converter_converter_source_payload_valid_token_count; -reg [1:0] tx_converter_converter_mux = 2'd0; -wire tx_converter_converter_first; -wire tx_converter_converter_last; -wire tx_converter_source_source_valid; -wire tx_converter_source_source_ready; -wire tx_converter_source_source_first; -wire tx_converter_source_source_last; -wire [9:0] tx_converter_source_source_payload_data; -wire rx_converter_sink_valid; -wire rx_converter_sink_ready; -wire rx_converter_sink_first; -wire rx_converter_sink_last; -wire [7:0] rx_converter_sink_payload_data; -wire rx_converter_sink_payload_last_be; -wire rx_converter_sink_payload_error; -wire rx_converter_source_valid; -wire rx_converter_source_ready; -wire rx_converter_source_first; -wire rx_converter_source_last; -reg [31:0] rx_converter_source_payload_data = 32'd0; -reg [3:0] rx_converter_source_payload_last_be = 4'd0; -reg [3:0] rx_converter_source_payload_error = 4'd0; -wire rx_converter_converter_sink_valid; -wire rx_converter_converter_sink_ready; -wire rx_converter_converter_sink_first; -wire rx_converter_converter_sink_last; -wire [9:0] rx_converter_converter_sink_payload_data; -wire rx_converter_converter_source_valid; -wire rx_converter_converter_source_ready; -reg rx_converter_converter_source_first = 1'd0; -reg rx_converter_converter_source_last = 1'd0; -reg [39:0] rx_converter_converter_source_payload_data = 40'd0; -reg [2:0] rx_converter_converter_source_payload_valid_token_count = 3'd0; -reg [1:0] rx_converter_converter_demux = 2'd0; -wire rx_converter_converter_load_part; -reg rx_converter_converter_strobe_all = 1'd0; -wire rx_converter_source_source_valid; -wire rx_converter_source_source_ready; -wire rx_converter_source_source_first; -wire rx_converter_source_source_last; -wire [39:0] rx_converter_source_source_payload_data; -wire tx_cdc_sink_sink_valid; -wire tx_cdc_sink_sink_ready; -wire tx_cdc_sink_sink_first; -wire tx_cdc_sink_sink_last; -wire [31:0] tx_cdc_sink_sink_payload_data; -wire [3:0] tx_cdc_sink_sink_payload_last_be; -wire [3:0] tx_cdc_sink_sink_payload_error; -wire tx_cdc_source_source_valid; -wire tx_cdc_source_source_ready; -wire tx_cdc_source_source_first; -wire tx_cdc_source_source_last; -wire [31:0] tx_cdc_source_source_payload_data; -wire [3:0] tx_cdc_source_source_payload_last_be; -wire [3:0] tx_cdc_source_source_payload_error; -wire tx_cdc_cdc_sink_valid; -wire tx_cdc_cdc_sink_ready; -wire tx_cdc_cdc_sink_first; -wire tx_cdc_cdc_sink_last; -wire [31:0] tx_cdc_cdc_sink_payload_data; -wire [3:0] tx_cdc_cdc_sink_payload_last_be; -wire [3:0] tx_cdc_cdc_sink_payload_error; -wire tx_cdc_cdc_source_valid; -wire tx_cdc_cdc_source_ready; -wire tx_cdc_cdc_source_first; -wire tx_cdc_cdc_source_last; -wire [31:0] tx_cdc_cdc_source_payload_data; -wire [3:0] tx_cdc_cdc_source_payload_last_be; -wire [3:0] tx_cdc_cdc_source_payload_error; -wire tx_cdc_cdc_asyncfifo_we; -wire tx_cdc_cdc_asyncfifo_writable; -wire tx_cdc_cdc_asyncfifo_re; -wire tx_cdc_cdc_asyncfifo_readable; -wire [41:0] tx_cdc_cdc_asyncfifo_din; -wire [41:0] tx_cdc_cdc_asyncfifo_dout; -wire tx_cdc_cdc_graycounter0_ce; -(* dont_touch = "true" *) reg [5:0] tx_cdc_cdc_graycounter0_q = 6'd0; -wire [5:0] tx_cdc_cdc_graycounter0_q_next; -reg [5:0] tx_cdc_cdc_graycounter0_q_binary = 6'd0; -reg [5:0] tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; -wire tx_cdc_cdc_graycounter1_ce; -(* dont_touch = "true" *) reg [5:0] tx_cdc_cdc_graycounter1_q = 6'd0; -wire [5:0] tx_cdc_cdc_graycounter1_q_next; -reg [5:0] tx_cdc_cdc_graycounter1_q_binary = 6'd0; -reg [5:0] tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; -wire [5:0] tx_cdc_cdc_produce_rdomain; -wire [5:0] tx_cdc_cdc_consume_wdomain; -wire [4:0] tx_cdc_cdc_wrport_adr; -wire [41:0] tx_cdc_cdc_wrport_dat_r; -wire tx_cdc_cdc_wrport_we; -wire [41:0] tx_cdc_cdc_wrport_dat_w; -wire [4:0] tx_cdc_cdc_rdport_adr; -wire [41:0] tx_cdc_cdc_rdport_dat_r; -wire [31:0] tx_cdc_cdc_fifo_in_payload_data; -wire [3:0] tx_cdc_cdc_fifo_in_payload_last_be; -wire [3:0] tx_cdc_cdc_fifo_in_payload_error; -wire tx_cdc_cdc_fifo_in_first; -wire tx_cdc_cdc_fifo_in_last; -wire [31:0] tx_cdc_cdc_fifo_out_payload_data; -wire [3:0] tx_cdc_cdc_fifo_out_payload_last_be; -wire [3:0] tx_cdc_cdc_fifo_out_payload_error; -wire tx_cdc_cdc_fifo_out_first; -wire tx_cdc_cdc_fifo_out_last; -wire rx_cdc_sink_sink_valid; -wire rx_cdc_sink_sink_ready; -wire rx_cdc_sink_sink_first; -wire rx_cdc_sink_sink_last; -wire [31:0] rx_cdc_sink_sink_payload_data; -wire [3:0] rx_cdc_sink_sink_payload_last_be; -wire [3:0] rx_cdc_sink_sink_payload_error; -wire rx_cdc_source_source_valid; -wire rx_cdc_source_source_ready; -wire rx_cdc_source_source_first; -wire rx_cdc_source_source_last; -wire [31:0] rx_cdc_source_source_payload_data; -wire [3:0] rx_cdc_source_source_payload_last_be; -wire [3:0] rx_cdc_source_source_payload_error; -wire rx_cdc_cdc_sink_valid; -wire rx_cdc_cdc_sink_ready; -wire rx_cdc_cdc_sink_first; -wire rx_cdc_cdc_sink_last; -wire [31:0] rx_cdc_cdc_sink_payload_data; -wire [3:0] rx_cdc_cdc_sink_payload_last_be; -wire [3:0] rx_cdc_cdc_sink_payload_error; -wire rx_cdc_cdc_source_valid; -wire rx_cdc_cdc_source_ready; -wire rx_cdc_cdc_source_first; -wire rx_cdc_cdc_source_last; -wire [31:0] rx_cdc_cdc_source_payload_data; -wire [3:0] rx_cdc_cdc_source_payload_last_be; -wire [3:0] rx_cdc_cdc_source_payload_error; -wire rx_cdc_cdc_asyncfifo_we; -wire rx_cdc_cdc_asyncfifo_writable; -wire rx_cdc_cdc_asyncfifo_re; -wire rx_cdc_cdc_asyncfifo_readable; -wire [41:0] rx_cdc_cdc_asyncfifo_din; -wire [41:0] rx_cdc_cdc_asyncfifo_dout; -wire rx_cdc_cdc_graycounter0_ce; -(* dont_touch = "true" *) reg [5:0] rx_cdc_cdc_graycounter0_q = 6'd0; -wire [5:0] rx_cdc_cdc_graycounter0_q_next; -reg [5:0] rx_cdc_cdc_graycounter0_q_binary = 6'd0; -reg [5:0] rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; -wire rx_cdc_cdc_graycounter1_ce; -(* dont_touch = "true" *) reg [5:0] rx_cdc_cdc_graycounter1_q = 6'd0; -wire [5:0] rx_cdc_cdc_graycounter1_q_next; -reg [5:0] rx_cdc_cdc_graycounter1_q_binary = 6'd0; -reg [5:0] rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; -wire [5:0] rx_cdc_cdc_produce_rdomain; -wire [5:0] rx_cdc_cdc_consume_wdomain; -wire [4:0] rx_cdc_cdc_wrport_adr; -wire [41:0] rx_cdc_cdc_wrport_dat_r; -wire rx_cdc_cdc_wrport_we; -wire [41:0] rx_cdc_cdc_wrport_dat_w; -wire [4:0] rx_cdc_cdc_rdport_adr; -wire [41:0] rx_cdc_cdc_rdport_dat_r; -wire [31:0] rx_cdc_cdc_fifo_in_payload_data; -wire [3:0] rx_cdc_cdc_fifo_in_payload_last_be; -wire [3:0] rx_cdc_cdc_fifo_in_payload_error; -wire rx_cdc_cdc_fifo_in_first; -wire rx_cdc_cdc_fifo_in_last; -wire [31:0] rx_cdc_cdc_fifo_out_payload_data; -wire [3:0] rx_cdc_cdc_fifo_out_payload_last_be; -wire [3:0] rx_cdc_cdc_fifo_out_payload_error; -wire rx_cdc_cdc_fifo_out_first; -wire rx_cdc_cdc_fifo_out_last; -wire sink_valid; -wire sink_ready; -wire sink_first; -wire sink_last; -wire [31:0] sink_payload_data; -wire [3:0] sink_payload_last_be; -wire [3:0] sink_payload_error; -wire source_valid; -wire source_ready; -wire source_first; -wire source_last; -wire [31:0] source_payload_data; -wire [3:0] source_payload_last_be; -wire [3:0] source_payload_error; -wire [29:0] bus_adr; -wire [31:0] bus_dat_w; -wire [31:0] bus_dat_r; -wire [3:0] bus_sel; -wire bus_cyc; -wire bus_stb; -wire bus_ack; -wire bus_we; -wire [2:0] bus_cti; -wire [1:0] bus_bte; -wire bus_err; -wire writer_sink_sink_valid; -reg writer_sink_sink_ready = 1'd1; -wire writer_sink_sink_first; -wire writer_sink_sink_last; -wire [31:0] writer_sink_sink_payload_data; -wire [3:0] writer_sink_sink_payload_last_be; -wire [3:0] writer_sink_sink_payload_error; -wire writer_slot_status; -wire writer_slot_we; -reg writer_slot_re = 1'd0; -wire [31:0] writer_length_status; -wire writer_length_we; -reg writer_length_re = 1'd0; -reg [31:0] writer_errors_status = 32'd0; -wire writer_errors_we; -reg writer_errors_re = 1'd0; -wire writer_irq; -wire writer_available_status; -wire writer_available_pending; -wire writer_available_trigger; -reg writer_available_clear = 1'd0; -wire writer_available0; -wire writer_status_status; -wire writer_status_we; -reg writer_status_re = 1'd0; -wire writer_available1; -wire writer_pending_status; -wire writer_pending_we; -reg writer_pending_re = 1'd0; -reg writer_pending_r = 1'd0; -wire writer_available2; -reg writer_enable_storage = 1'd0; -reg writer_enable_re = 1'd0; -reg [2:0] writer_inc = 3'd0; -reg [31:0] writer_counter = 32'd0; -reg writer_slot = 1'd0; -reg writer_slot_ce = 1'd0; -reg writer_start = 1'd0; -reg writer_ongoing = 1'd0; -reg writer_stat_fifo_sink_valid = 1'd0; -wire writer_stat_fifo_sink_ready; -reg writer_stat_fifo_sink_first = 1'd0; -reg writer_stat_fifo_sink_last = 1'd0; -wire writer_stat_fifo_sink_payload_slot; -wire [31:0] writer_stat_fifo_sink_payload_length; -wire writer_stat_fifo_source_valid; -wire writer_stat_fifo_source_ready; -wire writer_stat_fifo_source_first; -wire writer_stat_fifo_source_last; -wire writer_stat_fifo_source_payload_slot; -wire [31:0] writer_stat_fifo_source_payload_length; -wire writer_stat_fifo_syncfifo_we; -wire writer_stat_fifo_syncfifo_writable; -wire writer_stat_fifo_syncfifo_re; -wire writer_stat_fifo_syncfifo_readable; -wire [34:0] writer_stat_fifo_syncfifo_din; -wire [34:0] writer_stat_fifo_syncfifo_dout; -reg [1:0] writer_stat_fifo_level = 2'd0; -reg writer_stat_fifo_replace = 1'd0; -reg writer_stat_fifo_produce = 1'd0; -reg writer_stat_fifo_consume = 1'd0; -reg writer_stat_fifo_wrport_adr = 1'd0; -wire [34:0] writer_stat_fifo_wrport_dat_r; -wire writer_stat_fifo_wrport_we; -wire [34:0] writer_stat_fifo_wrport_dat_w; -wire writer_stat_fifo_do_read; -wire writer_stat_fifo_rdport_adr; -wire [34:0] writer_stat_fifo_rdport_dat_r; -wire writer_stat_fifo_fifo_in_payload_slot; -wire [31:0] writer_stat_fifo_fifo_in_payload_length; -wire writer_stat_fifo_fifo_in_first; -wire writer_stat_fifo_fifo_in_last; -wire writer_stat_fifo_fifo_out_payload_slot; -wire [31:0] writer_stat_fifo_fifo_out_payload_length; -wire writer_stat_fifo_fifo_out_first; -wire writer_stat_fifo_fifo_out_last; -reg [8:0] writer_memory0_adr = 9'd0; -wire [31:0] writer_memory0_dat_r; -reg writer_memory0_we = 1'd0; -reg [31:0] writer_memory0_dat_w = 32'd0; -reg [8:0] writer_memory1_adr = 9'd0; -wire [31:0] writer_memory1_dat_r; -reg writer_memory1_we = 1'd0; -reg [31:0] writer_memory1_dat_w = 32'd0; -reg reader_source_source_valid = 1'd0; -wire reader_source_source_ready; -reg reader_source_source_first = 1'd0; -reg reader_source_source_last = 1'd0; -reg [31:0] reader_source_source_payload_data = 32'd0; -reg [3:0] reader_source_source_payload_last_be = 4'd0; -reg [3:0] reader_source_source_payload_error = 4'd0; -reg reader_start_start_re = 1'd0; -wire reader_start_start_r; -reg reader_start_start_we = 1'd0; -reg reader_start_start_w = 1'd0; -wire reader_ready_status; -wire reader_ready_we; -reg reader_ready_re = 1'd0; -wire [1:0] reader_level_status; -wire reader_level_we; -reg reader_level_re = 1'd0; -reg reader_slot_storage = 1'd0; -reg reader_slot_re = 1'd0; -reg [10:0] reader_length_storage = 11'd0; -reg reader_length_re = 1'd0; -wire reader_irq; -wire reader_eventsourcepulse_status; -reg reader_eventsourcepulse_pending = 1'd0; -reg reader_eventsourcepulse_trigger = 1'd0; -reg reader_eventsourcepulse_clear = 1'd0; -wire reader_event00; -wire reader_status_status; -wire reader_status_we; -reg reader_status_re = 1'd0; -wire reader_event01; -wire reader_pending_status; -wire reader_pending_we; -reg reader_pending_re = 1'd0; -reg reader_pending_r = 1'd0; -wire reader_event02; -reg reader_enable_storage = 1'd0; -reg reader_enable_re = 1'd0; -reg reader_start = 1'd0; -wire reader_cmd_fifo_sink_valid; -wire reader_cmd_fifo_sink_ready; -reg reader_cmd_fifo_sink_first = 1'd0; -reg reader_cmd_fifo_sink_last = 1'd0; -wire reader_cmd_fifo_sink_payload_slot; -wire [10:0] reader_cmd_fifo_sink_payload_length; -wire reader_cmd_fifo_source_valid; -reg reader_cmd_fifo_source_ready = 1'd0; -wire reader_cmd_fifo_source_first; -wire reader_cmd_fifo_source_last; -wire reader_cmd_fifo_source_payload_slot; -wire [10:0] reader_cmd_fifo_source_payload_length; -wire reader_cmd_fifo_syncfifo_we; -wire reader_cmd_fifo_syncfifo_writable; -wire reader_cmd_fifo_syncfifo_re; -wire reader_cmd_fifo_syncfifo_readable; -wire [13:0] reader_cmd_fifo_syncfifo_din; -wire [13:0] reader_cmd_fifo_syncfifo_dout; -reg [1:0] reader_cmd_fifo_level = 2'd0; -reg reader_cmd_fifo_replace = 1'd0; -reg reader_cmd_fifo_produce = 1'd0; -reg reader_cmd_fifo_consume = 1'd0; -reg reader_cmd_fifo_wrport_adr = 1'd0; -wire [13:0] reader_cmd_fifo_wrport_dat_r; -wire reader_cmd_fifo_wrport_we; -wire [13:0] reader_cmd_fifo_wrport_dat_w; -wire reader_cmd_fifo_do_read; -wire reader_cmd_fifo_rdport_adr; -wire [13:0] reader_cmd_fifo_rdport_dat_r; -wire reader_cmd_fifo_fifo_in_payload_slot; -wire [10:0] reader_cmd_fifo_fifo_in_payload_length; -wire reader_cmd_fifo_fifo_in_first; -wire reader_cmd_fifo_fifo_in_last; -wire reader_cmd_fifo_fifo_out_payload_slot; -wire [10:0] reader_cmd_fifo_fifo_out_payload_length; -wire reader_cmd_fifo_fifo_out_first; -wire reader_cmd_fifo_fifo_out_last; -reg [10:0] reader_read_address = 11'd0; -reg [10:0] reader_counter = 11'd0; -wire [8:0] reader_memory0_adr; -wire [31:0] reader_memory0_dat_r; -wire [8:0] reader_memory1_adr; -wire [31:0] reader_memory1_dat_r; -wire ev_irq; -wire [29:0] sram0_bus_adr0; -wire [31:0] sram0_bus_dat_w0; -wire [31:0] sram0_bus_dat_r0; -wire [3:0] sram0_bus_sel0; -wire sram0_bus_cyc0; -wire sram0_bus_stb0; -reg sram0_bus_ack0 = 1'd0; -wire sram0_bus_we0; -wire [2:0] sram0_bus_cti0; -wire [1:0] sram0_bus_bte0; -reg sram0_bus_err0 = 1'd0; -wire [8:0] sram0_adr0; -wire [31:0] sram0_dat_r0; -wire [29:0] sram1_bus_adr0; -wire [31:0] sram1_bus_dat_w0; -wire [31:0] sram1_bus_dat_r0; -wire [3:0] sram1_bus_sel0; -wire sram1_bus_cyc0; -wire sram1_bus_stb0; -reg sram1_bus_ack0 = 1'd0; -wire sram1_bus_we0; -wire [2:0] sram1_bus_cti0; -wire [1:0] sram1_bus_bte0; -reg sram1_bus_err0 = 1'd0; -wire [8:0] sram1_adr0; -wire [31:0] sram1_dat_r0; -wire [29:0] sram0_bus_adr1; -wire [31:0] sram0_bus_dat_w1; -wire [31:0] sram0_bus_dat_r1; -wire [3:0] sram0_bus_sel1; -wire sram0_bus_cyc1; -wire sram0_bus_stb1; -reg sram0_bus_ack1 = 1'd0; -wire sram0_bus_we1; -wire [2:0] sram0_bus_cti1; -wire [1:0] sram0_bus_bte1; -reg sram0_bus_err1 = 1'd0; -wire [8:0] sram0_adr1; -wire [31:0] sram0_dat_r1; -reg [3:0] sram0_we = 4'd0; -wire [31:0] sram0_dat_w; -wire [29:0] sram1_bus_adr1; -wire [31:0] sram1_bus_dat_w1; -wire [31:0] sram1_bus_dat_r1; -wire [3:0] sram1_bus_sel1; -wire sram1_bus_cyc1; -wire sram1_bus_stb1; -reg sram1_bus_ack1 = 1'd0; -wire sram1_bus_we1; -wire [2:0] sram1_bus_cti1; -wire [1:0] sram1_bus_bte1; -reg sram1_bus_err1 = 1'd0; -wire [8:0] sram1_adr1; -wire [31:0] sram1_dat_r1; -reg [3:0] sram1_we = 4'd0; -wire [31:0] sram1_dat_w; -reg [3:0] slave_sel = 4'd0; -reg [3:0] slave_sel_r = 4'd0; -wire [29:0] wb_bus_adr; -wire [31:0] wb_bus_dat_w; -wire [31:0] wb_bus_dat_r; -wire [3:0] wb_bus_sel; -wire wb_bus_cyc; -wire wb_bus_stb; -wire wb_bus_ack; -wire wb_bus_we; -wire [2:0] wb_bus_cti; -wire [1:0] wb_bus_bte; -wire wb_bus_err; -reg [1:0] subfragments_state = 2'd0; -reg [1:0] subfragments_next_state = 2'd0; -reg subfragments_liteethmacgap_state = 1'd0; -reg subfragments_liteethmacgap_next_state = 1'd0; -reg [3:0] tx_gap_inserter_counter_liteethmacgap_next_value = 4'd0; -reg tx_gap_inserter_counter_liteethmacgap_next_value_ce = 1'd0; -reg [1:0] subfragments_liteethmacpreambleinserter_state = 2'd0; -reg [1:0] subfragments_liteethmacpreambleinserter_next_state = 2'd0; -reg [2:0] preamble_inserter_count_liteethmacpreambleinserter_next_value = 3'd0; -reg preamble_inserter_count_liteethmacpreambleinserter_next_value_ce = 1'd0; -reg subfragments_liteethmacpreamblechecker_state = 1'd0; -reg subfragments_liteethmacpreamblechecker_next_state = 1'd0; -reg [1:0] subfragments_liteethmaccrc32inserter_state = 2'd0; -reg [1:0] subfragments_liteethmaccrc32inserter_next_state = 2'd0; -reg [1:0] subfragments_liteethmaccrc32checker_state = 2'd0; -reg [1:0] subfragments_liteethmaccrc32checker_next_state = 2'd0; -reg subfragments_liteethmacpaddinginserter_state = 1'd0; -reg subfragments_liteethmacpaddinginserter_next_state = 1'd0; -reg [15:0] padding_inserter_counter_liteethmacpaddinginserter_next_value = 16'd0; -reg padding_inserter_counter_liteethmacpaddinginserter_next_value_ce = 1'd0; -reg subfragments_liteethmactxlastbe_state = 1'd0; -reg subfragments_liteethmactxlastbe_next_state = 1'd0; -reg [2:0] subfragments_liteethmacsramwriter_state = 3'd0; -reg [2:0] subfragments_liteethmacsramwriter_next_state = 3'd0; -reg [31:0] writer_counter_t_next_value = 32'd0; -reg writer_counter_t_next_value_ce = 1'd0; -reg [31:0] writer_errors_status_f_next_value = 32'd0; -reg writer_errors_status_f_next_value_ce = 1'd0; -reg [1:0] subfragments_liteethmacsramreader_state = 2'd0; -reg [1:0] subfragments_liteethmacsramreader_next_state = 2'd0; -reg [10:0] reader_counter_next_value = 11'd0; -reg reader_counter_next_value_ce = 1'd0; -reg [13:0] maccore_maccore_adr = 14'd0; -reg maccore_maccore_we = 1'd0; -reg [31:0] maccore_maccore_dat_w = 32'd0; -wire [31:0] maccore_maccore_dat_r; -wire [29:0] maccore_maccore_wishbone_adr; -wire [31:0] maccore_maccore_wishbone_dat_w; -reg [31:0] maccore_maccore_wishbone_dat_r = 32'd0; -wire [3:0] maccore_maccore_wishbone_sel; -wire maccore_maccore_wishbone_cyc; -wire maccore_maccore_wishbone_stb; -reg maccore_maccore_wishbone_ack = 1'd0; -wire maccore_maccore_wishbone_we; -wire [2:0] maccore_maccore_wishbone_cti; -wire [1:0] maccore_maccore_wishbone_bte; -reg maccore_maccore_wishbone_err = 1'd0; -wire [29:0] maccore_shared_adr; -wire [31:0] maccore_shared_dat_w; -reg [31:0] maccore_shared_dat_r = 32'd0; -wire [3:0] maccore_shared_sel; -wire maccore_shared_cyc; -wire maccore_shared_stb; -reg maccore_shared_ack = 1'd0; -wire maccore_shared_we; -wire [2:0] maccore_shared_cti; -wire [1:0] maccore_shared_bte; -wire maccore_shared_err; -wire maccore_request; -wire maccore_grant; -reg [1:0] maccore_slave_sel = 2'd0; -reg [1:0] maccore_slave_sel_r = 2'd0; -reg maccore_error = 1'd0; -wire maccore_wait; -wire maccore_done; -reg [19:0] maccore_count = 20'd1000000; -wire [13:0] maccore_interface0_bank_bus_adr; -wire maccore_interface0_bank_bus_we; -wire [31:0] maccore_interface0_bank_bus_dat_w; -reg [31:0] maccore_interface0_bank_bus_dat_r = 32'd0; -reg maccore_csrbank0_reset0_re = 1'd0; -wire [1:0] maccore_csrbank0_reset0_r; -reg maccore_csrbank0_reset0_we = 1'd0; -wire [1:0] maccore_csrbank0_reset0_w; -reg maccore_csrbank0_scratch0_re = 1'd0; -wire [31:0] maccore_csrbank0_scratch0_r; -reg maccore_csrbank0_scratch0_we = 1'd0; -wire [31:0] maccore_csrbank0_scratch0_w; -reg maccore_csrbank0_bus_errors_re = 1'd0; -wire [31:0] maccore_csrbank0_bus_errors_r; -reg maccore_csrbank0_bus_errors_we = 1'd0; -wire [31:0] maccore_csrbank0_bus_errors_w; -wire maccore_csrbank0_sel; -wire [13:0] maccore_interface1_bank_bus_adr; -wire maccore_interface1_bank_bus_we; -wire [31:0] maccore_interface1_bank_bus_dat_w; -reg [31:0] maccore_interface1_bank_bus_dat_r = 32'd0; -reg maccore_csrbank1_sram_writer_slot_re = 1'd0; -wire maccore_csrbank1_sram_writer_slot_r; -reg maccore_csrbank1_sram_writer_slot_we = 1'd0; -wire maccore_csrbank1_sram_writer_slot_w; -reg maccore_csrbank1_sram_writer_length_re = 1'd0; -wire [31:0] maccore_csrbank1_sram_writer_length_r; -reg maccore_csrbank1_sram_writer_length_we = 1'd0; -wire [31:0] maccore_csrbank1_sram_writer_length_w; -reg maccore_csrbank1_sram_writer_errors_re = 1'd0; -wire [31:0] maccore_csrbank1_sram_writer_errors_r; -reg maccore_csrbank1_sram_writer_errors_we = 1'd0; -wire [31:0] maccore_csrbank1_sram_writer_errors_w; -reg maccore_csrbank1_sram_writer_ev_status_re = 1'd0; -wire maccore_csrbank1_sram_writer_ev_status_r; -reg maccore_csrbank1_sram_writer_ev_status_we = 1'd0; -wire maccore_csrbank1_sram_writer_ev_status_w; -reg maccore_csrbank1_sram_writer_ev_pending_re = 1'd0; -wire maccore_csrbank1_sram_writer_ev_pending_r; -reg maccore_csrbank1_sram_writer_ev_pending_we = 1'd0; -wire maccore_csrbank1_sram_writer_ev_pending_w; -reg maccore_csrbank1_sram_writer_ev_enable0_re = 1'd0; -wire maccore_csrbank1_sram_writer_ev_enable0_r; -reg maccore_csrbank1_sram_writer_ev_enable0_we = 1'd0; -wire maccore_csrbank1_sram_writer_ev_enable0_w; -reg maccore_csrbank1_sram_reader_ready_re = 1'd0; -wire maccore_csrbank1_sram_reader_ready_r; -reg maccore_csrbank1_sram_reader_ready_we = 1'd0; -wire maccore_csrbank1_sram_reader_ready_w; -reg maccore_csrbank1_sram_reader_level_re = 1'd0; -wire [1:0] maccore_csrbank1_sram_reader_level_r; -reg maccore_csrbank1_sram_reader_level_we = 1'd0; -wire [1:0] maccore_csrbank1_sram_reader_level_w; -reg maccore_csrbank1_sram_reader_slot0_re = 1'd0; -wire maccore_csrbank1_sram_reader_slot0_r; -reg maccore_csrbank1_sram_reader_slot0_we = 1'd0; -wire maccore_csrbank1_sram_reader_slot0_w; -reg maccore_csrbank1_sram_reader_length0_re = 1'd0; -wire [10:0] maccore_csrbank1_sram_reader_length0_r; -reg maccore_csrbank1_sram_reader_length0_we = 1'd0; -wire [10:0] maccore_csrbank1_sram_reader_length0_w; -reg maccore_csrbank1_sram_reader_ev_status_re = 1'd0; -wire maccore_csrbank1_sram_reader_ev_status_r; -reg maccore_csrbank1_sram_reader_ev_status_we = 1'd0; -wire maccore_csrbank1_sram_reader_ev_status_w; -reg maccore_csrbank1_sram_reader_ev_pending_re = 1'd0; -wire maccore_csrbank1_sram_reader_ev_pending_r; -reg maccore_csrbank1_sram_reader_ev_pending_we = 1'd0; -wire maccore_csrbank1_sram_reader_ev_pending_w; -reg maccore_csrbank1_sram_reader_ev_enable0_re = 1'd0; -wire maccore_csrbank1_sram_reader_ev_enable0_r; -reg maccore_csrbank1_sram_reader_ev_enable0_we = 1'd0; -wire maccore_csrbank1_sram_reader_ev_enable0_w; -reg maccore_csrbank1_preamble_crc_re = 1'd0; -wire maccore_csrbank1_preamble_crc_r; -reg maccore_csrbank1_preamble_crc_we = 1'd0; -wire maccore_csrbank1_preamble_crc_w; -reg maccore_csrbank1_preamble_errors_re = 1'd0; -wire [31:0] maccore_csrbank1_preamble_errors_r; -reg maccore_csrbank1_preamble_errors_we = 1'd0; -wire [31:0] maccore_csrbank1_preamble_errors_w; -reg maccore_csrbank1_crc_errors_re = 1'd0; -wire [31:0] maccore_csrbank1_crc_errors_r; -reg maccore_csrbank1_crc_errors_we = 1'd0; -wire [31:0] maccore_csrbank1_crc_errors_w; -wire maccore_csrbank1_sel; -wire [13:0] maccore_interface2_bank_bus_adr; -wire maccore_interface2_bank_bus_we; -wire [31:0] maccore_interface2_bank_bus_dat_w; -reg [31:0] maccore_interface2_bank_bus_dat_r = 32'd0; -reg maccore_csrbank2_mode_detection_mode_re = 1'd0; -wire maccore_csrbank2_mode_detection_mode_r; -reg maccore_csrbank2_mode_detection_mode_we = 1'd0; -wire maccore_csrbank2_mode_detection_mode_w; -reg maccore_csrbank2_crg_reset0_re = 1'd0; -wire maccore_csrbank2_crg_reset0_r; -reg maccore_csrbank2_crg_reset0_we = 1'd0; -wire maccore_csrbank2_crg_reset0_w; -reg maccore_csrbank2_mdio_w0_re = 1'd0; -wire [2:0] maccore_csrbank2_mdio_w0_r; -reg maccore_csrbank2_mdio_w0_we = 1'd0; -wire [2:0] maccore_csrbank2_mdio_w0_w; -reg maccore_csrbank2_mdio_r_re = 1'd0; -wire maccore_csrbank2_mdio_r_r; -reg maccore_csrbank2_mdio_r_we = 1'd0; -wire maccore_csrbank2_mdio_r_w; -wire maccore_csrbank2_sel; -wire [13:0] maccore_csr_interconnect_adr; -wire maccore_csr_interconnect_we; -wire [31:0] maccore_csr_interconnect_dat_w; -wire [31:0] maccore_csr_interconnect_dat_r; -reg maccore_state = 1'd0; -reg maccore_next_state = 1'd0; -reg [29:0] array_muxed0 = 30'd0; -reg [31:0] array_muxed1 = 32'd0; -reg [3:0] array_muxed2 = 4'd0; -reg array_muxed3 = 1'd0; -reg array_muxed4 = 1'd0; -reg array_muxed5 = 1'd0; -reg [2:0] array_muxed6 = 3'd0; -reg [1:0] array_muxed7 = 2'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl0_regs0 = 1'd0; -(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl0_regs1 = 1'd0; -wire rst_meta0; -wire rst_meta1; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl1_regs0 = 1'd0; -(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl1_regs1 = 1'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl2_regs0 = 1'd0; -(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl2_regs1 = 1'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl3_regs0 = 1'd0; -(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl3_regs1 = 1'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl4_regs0 = 6'd0; -(* async_reg = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl4_regs1 = 6'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl5_regs0 = 6'd0; -(* async_reg = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl5_regs1 = 6'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl6_regs0 = 6'd0; -(* async_reg = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl6_regs1 = 6'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl7_regs0 = 6'd0; -(* async_reg = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl7_regs1 = 6'd0; -assign wb_bus_adr = wishbone_adr; -assign wb_bus_dat_w = wishbone_dat_w; -assign wishbone_dat_r = wb_bus_dat_r; -assign wb_bus_sel = wishbone_sel; -assign wb_bus_cyc = wishbone_cyc; -assign wb_bus_stb = wishbone_stb; -assign wishbone_ack = wb_bus_ack; -assign wb_bus_we = wishbone_we; -assign wb_bus_cti = wishbone_cti; -assign wb_bus_bte = wishbone_bte; -assign wishbone_err = wb_bus_err; -assign interrupt = ev_irq; -assign maccore_maccore_bus_error = maccore_error; -assign maccore_maccore_bus_errors_status = maccore_maccore_bus_errors; +//------------------------------------------------------------------------------ +// Hierarchy +//------------------------------------------------------------------------------ + +/* +MACCore +└─── bus (SoCBusHandler) +│ └─── _interconnect (InterconnectShared) +│ │ └─── arbiter (Arbiter) +│ │ │ └─── rr (RoundRobin) +│ │ └─── decoder (Decoder) +│ │ └─── timeout (Timeout) +│ │ │ └─── waittimer_0* (WaitTimer) +└─── csr (SoCCSRHandler) +└─── irq (SoCIRQHandler) +└─── ctrl (SoCController) +└─── cpu (CPUNone) +└─── crg (CRG) +└─── ethphy (LiteEthPHYGMIIMII) +│ └─── mode_detection (LiteEthGMIIMIIModeDetection) +│ │ └─── eth_ps (PulseSynchronizer) +│ │ └─── fsm (FSM) +│ └─── crg (LiteEthPHYGMIICRG) +│ │ └─── hw_reset (LiteEthPHYHWReset) +│ │ └─── [BUFG] +│ │ └─── [BUFG] +│ └─── tx (LiteEthPHYGMIIMIITX) +│ │ └─── liteethphygmiitx_0* (LiteEthPHYGMIITX) +│ │ └─── liteethphymiitx_0* (LiteEthPHYMIITX) +│ │ │ └─── converter (Converter) +│ │ │ │ └─── _downconverter_0* (_DownConverter) +│ │ └─── demultiplexer_0* (Demultiplexer) +│ └─── rx (LiteEthPHYGMIIMIIRX) +│ │ └─── gmii_rx (LiteEthPHYGMIIRX) +│ │ └─── mii_rx (LiteEthPHYMIIRX) +│ │ │ └─── converter_0* (Converter) +│ │ │ │ └─── _upconverter_0* (_UpConverter) +│ │ └─── mux (Multiplexer) +│ └─── mdio (LiteEthPHYMDIO) +└─── ethmac (LiteEthMAC) +│ └─── core (LiteEthMACCore) +│ │ └─── tx_datapath (TXDatapath) +│ │ │ └─── clockdomaincrossing_0* (ClockDomainCrossing) +│ │ │ │ └─── asyncfifo_0* (AsyncFIFO) +│ │ │ │ │ └─── fifo (AsyncFIFO) +│ │ │ │ │ │ └─── graycounter_0* (GrayCounter) +│ │ │ │ │ │ └─── graycounter_1* (GrayCounter) +│ │ │ └─── strideconverter_0* (StrideConverter) +│ │ │ │ └─── converter_0* (Converter) +│ │ │ │ │ └─── _downconverter_0* (_DownConverter) +│ │ │ └─── liteethmactxlastbe_0* (LiteEthMACTXLastBE) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── liteethmacpaddinginserter_0* (LiteEthMACPaddingInserter) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── liteethmaccrc32inserter_0* (LiteEthMACCRC32Inserter) +│ │ │ │ └─── crc (LiteEthMACCRC32) +│ │ │ │ │ └─── liteethmaccrcengine_0* (LiteEthMACCRCEngine) +│ │ │ │ └─── fsm (FSM) +│ │ │ │ └─── buffer_0* (Buffer) +│ │ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── liteethmacpreambleinserter_0* (LiteEthMACPreambleInserter) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── liteethmacgap_0* (LiteEthMACGap) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── pipeline_0* (Pipeline) +│ │ └─── rx_datapath (RXDatapath) +│ │ │ └─── liteethmacpreamblechecker_0* (LiteEthMACPreambleChecker) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── pulsesynchronizer_0* (PulseSynchronizer) +│ │ │ └─── liteethmaccrc32checker_0* (LiteEthMACCRC32Checker) +│ │ │ │ └─── crc (LiteEthMACCRC32) +│ │ │ │ │ └─── liteethmaccrcengine_0* (LiteEthMACCRCEngine) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ └─── fsm (FSM) +│ │ │ │ └─── buffer_0* (Buffer) +│ │ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── pulsesynchronizer_1* (PulseSynchronizer) +│ │ │ └─── liteethmacpaddingchecker_0* (LiteEthMACPaddingChecker) +│ │ │ └─── liteethmacrxlastbe_0* (LiteEthMACRXLastBE) +│ │ │ └─── strideconverter_0* (StrideConverter) +│ │ │ │ └─── converter_0* (Converter) +│ │ │ │ │ └─── _upconverter_0* (_UpConverter) +│ │ │ └─── clockdomaincrossing_0* (ClockDomainCrossing) +│ │ │ │ └─── asyncfifo_0* (AsyncFIFO) +│ │ │ │ │ └─── fifo (AsyncFIFO) +│ │ │ │ │ │ └─── graycounter_0* (GrayCounter) +│ │ │ │ │ │ └─── graycounter_1* (GrayCounter) +│ │ │ └─── pipeline_0* (Pipeline) +│ └─── interface (LiteEthMACWishboneInterface) +│ │ └─── sram (LiteEthMACSRAM) +│ │ │ └─── writer (LiteEthMACSRAMWriter) +│ │ │ │ └─── ev (EventManager) +│ │ │ │ │ └─── eventsourcelevel_0* (EventSourceLevel) +│ │ │ │ └─── stat_fifo (SyncFIFO) +│ │ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── reader (LiteEthMACSRAMReader) +│ │ │ │ └─── ev (EventManager) +│ │ │ │ │ └─── eventsourcepulse_0* (EventSourcePulse) +│ │ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── ev (SharedIRQ) +│ │ └─── sram_0* (SRAM) +│ │ └─── sram_1* (SRAM) +│ │ └─── sram_2* (SRAM) +│ │ └─── sram_3* (SRAM) +│ │ └─── decoder_0* (Decoder) +└─── csr_bridge (Wishbone2CSR) +│ └─── fsm (FSM) +└─── csr_bankarray (CSRBankArray) +│ └─── csrbank_0* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ └─── csrbank_1* (CSRBank) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstatus_1* (CSRStatus) +│ │ └─── csrstatus_2* (CSRStatus) +│ │ └─── csrstatus_3* (CSRStatus) +│ │ └─── csrstatus_4* (CSRStatus) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstatus_5* (CSRStatus) +│ │ └─── csrstatus_6* (CSRStatus) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstatus_7* (CSRStatus) +│ │ └─── csrstatus_8* (CSRStatus) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstatus_9* (CSRStatus) +│ │ └─── csrstatus_10* (CSRStatus) +│ │ └─── csrstatus_11* (CSRStatus) +│ └─── csrbank_2* (CSRBank) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstatus_1* (CSRStatus) +└─── csr_interconnect (InterconnectShared) +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [ODDR] +* : Generated name. +[]: BlackBox. +*/ + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +wire [13:0] builder_adr; +wire [39:0] builder_complexslicelowerer_slice_proxy; +reg [19:0] builder_count = 20'd1000000; +wire [31:0] builder_csrbank0_bus_errors_r; +reg builder_csrbank0_bus_errors_re = 1'd0; +wire [31:0] builder_csrbank0_bus_errors_w; +reg builder_csrbank0_bus_errors_we = 1'd0; +wire [1:0] builder_csrbank0_reset0_r; +reg builder_csrbank0_reset0_re = 1'd0; +wire [1:0] builder_csrbank0_reset0_w; +reg builder_csrbank0_reset0_we = 1'd0; +wire [31:0] builder_csrbank0_scratch0_r; +reg builder_csrbank0_scratch0_re = 1'd0; +wire [31:0] builder_csrbank0_scratch0_w; +reg builder_csrbank0_scratch0_we = 1'd0; +wire builder_csrbank0_sel; +wire builder_csrbank1_preamble_crc_r; +reg builder_csrbank1_preamble_crc_re = 1'd0; +wire builder_csrbank1_preamble_crc_w; +reg builder_csrbank1_preamble_crc_we = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_crc_errors_r; +reg builder_csrbank1_rx_datapath_crc_errors_re = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_crc_errors_w; +reg builder_csrbank1_rx_datapath_crc_errors_we = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_r; +reg builder_csrbank1_rx_datapath_preamble_errors_re = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_w; +reg builder_csrbank1_rx_datapath_preamble_errors_we = 1'd0; +wire builder_csrbank1_sel; +wire builder_csrbank1_sram_reader_ev_enable0_r; +reg builder_csrbank1_sram_reader_ev_enable0_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_enable0_w; +reg builder_csrbank1_sram_reader_ev_enable0_we = 1'd0; +wire builder_csrbank1_sram_reader_ev_pending_r; +reg builder_csrbank1_sram_reader_ev_pending_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_pending_w; +reg builder_csrbank1_sram_reader_ev_pending_we = 1'd0; +wire builder_csrbank1_sram_reader_ev_status_r; +reg builder_csrbank1_sram_reader_ev_status_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_status_w; +reg builder_csrbank1_sram_reader_ev_status_we = 1'd0; +wire [10:0] builder_csrbank1_sram_reader_length0_r; +reg builder_csrbank1_sram_reader_length0_re = 1'd0; +wire [10:0] builder_csrbank1_sram_reader_length0_w; +reg builder_csrbank1_sram_reader_length0_we = 1'd0; +wire [1:0] builder_csrbank1_sram_reader_level_r; +reg builder_csrbank1_sram_reader_level_re = 1'd0; +wire [1:0] builder_csrbank1_sram_reader_level_w; +reg builder_csrbank1_sram_reader_level_we = 1'd0; +wire builder_csrbank1_sram_reader_ready_r; +reg builder_csrbank1_sram_reader_ready_re = 1'd0; +wire builder_csrbank1_sram_reader_ready_w; +reg builder_csrbank1_sram_reader_ready_we = 1'd0; +wire builder_csrbank1_sram_reader_slot0_r; +reg builder_csrbank1_sram_reader_slot0_re = 1'd0; +wire builder_csrbank1_sram_reader_slot0_w; +reg builder_csrbank1_sram_reader_slot0_we = 1'd0; +wire [31:0] builder_csrbank1_sram_writer_errors_r; +reg builder_csrbank1_sram_writer_errors_re = 1'd0; +wire [31:0] builder_csrbank1_sram_writer_errors_w; +reg builder_csrbank1_sram_writer_errors_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_enable0_r; +reg builder_csrbank1_sram_writer_ev_enable0_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_enable0_w; +reg builder_csrbank1_sram_writer_ev_enable0_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_pending_r; +reg builder_csrbank1_sram_writer_ev_pending_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_pending_w; +reg builder_csrbank1_sram_writer_ev_pending_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_status_r; +reg builder_csrbank1_sram_writer_ev_status_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_status_w; +reg builder_csrbank1_sram_writer_ev_status_we = 1'd0; +wire [10:0] builder_csrbank1_sram_writer_length_r; +reg builder_csrbank1_sram_writer_length_re = 1'd0; +wire [10:0] builder_csrbank1_sram_writer_length_w; +reg builder_csrbank1_sram_writer_length_we = 1'd0; +wire builder_csrbank1_sram_writer_slot_r; +reg builder_csrbank1_sram_writer_slot_re = 1'd0; +wire builder_csrbank1_sram_writer_slot_w; +reg builder_csrbank1_sram_writer_slot_we = 1'd0; +wire builder_csrbank2_crg_reset0_r; +reg builder_csrbank2_crg_reset0_re = 1'd0; +wire builder_csrbank2_crg_reset0_w; +reg builder_csrbank2_crg_reset0_we = 1'd0; +wire builder_csrbank2_mdio_r_r; +reg builder_csrbank2_mdio_r_re = 1'd0; +wire builder_csrbank2_mdio_r_w; +reg builder_csrbank2_mdio_r_we = 1'd0; +wire [2:0] builder_csrbank2_mdio_w0_r; +reg builder_csrbank2_mdio_w0_re = 1'd0; +wire [2:0] builder_csrbank2_mdio_w0_w; +reg builder_csrbank2_mdio_w0_we = 1'd0; +wire builder_csrbank2_mode_detection_mode_r; +reg builder_csrbank2_mode_detection_mode_re = 1'd0; +wire builder_csrbank2_mode_detection_mode_w; +reg builder_csrbank2_mode_detection_mode_we = 1'd0; +wire builder_csrbank2_sel; +wire [31:0] builder_dat_r; +wire [31:0] builder_dat_w; +wire builder_done; +reg builder_error = 1'd0; +wire builder_grant; +reg builder_interface0_ack = 1'd0; +wire [29:0] builder_interface0_adr; +wire [13:0] builder_interface0_bank_bus_adr; +reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface0_bank_bus_dat_w; +wire builder_interface0_bank_bus_we; +wire [1:0] builder_interface0_bte; +wire [2:0] builder_interface0_cti; +wire builder_interface0_cyc; +reg [31:0] builder_interface0_dat_r = 32'd0; +wire [31:0] builder_interface0_dat_w; +reg builder_interface0_err = 1'd0; +wire [3:0] builder_interface0_sel; +wire builder_interface0_stb; +wire builder_interface0_we; +reg [13:0] builder_interface1_adr = 14'd0; +wire [13:0] builder_interface1_bank_bus_adr; +reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface1_bank_bus_dat_w; +wire builder_interface1_bank_bus_we; +wire [31:0] builder_interface1_dat_r; +reg [31:0] builder_interface1_dat_w = 32'd0; +reg builder_interface1_we = 1'd0; +wire [13:0] builder_interface2_bank_bus_adr; +reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface2_bank_bus_dat_w; +wire builder_interface2_bank_bus_we; +reg [1:0] builder_liteethmacsramreader_next_state = 2'd0; +reg [1:0] builder_liteethmacsramreader_state = 2'd0; +reg [2:0] builder_liteethmacsramwriter_next_state = 3'd0; +reg [2:0] builder_liteethmacsramwriter_state = 3'd0; +reg [1:0] builder_liteethphygmiimii_next_state = 2'd0; +reg [1:0] builder_liteethphygmiimii_state = 2'd0; +wire builder_request; +wire builder_rst_meta0; +wire builder_rst_meta1; +reg [1:0] builder_rxdatapath_bufferizeendpoints_next_state = 2'd0; +reg [1:0] builder_rxdatapath_bufferizeendpoints_state = 2'd0; +reg builder_rxdatapath_liteethmacpreamblechecker_next_state = 1'd0; +reg builder_rxdatapath_liteethmacpreamblechecker_state = 1'd0; +reg [29:0] builder_self0 = 30'd0; +reg [31:0] builder_self1 = 32'd0; +reg [3:0] builder_self2 = 4'd0; +reg builder_self3 = 1'd0; +reg builder_self4 = 1'd0; +reg builder_self5 = 1'd0; +reg [2:0] builder_self6 = 3'd0; +reg [1:0] builder_self7 = 2'd0; +reg builder_shared_ack = 1'd0; +wire [29:0] builder_shared_adr; +wire [1:0] builder_shared_bte; +wire [2:0] builder_shared_cti; +wire builder_shared_cyc; +reg [31:0] builder_shared_dat_r = 32'd0; +wire [31:0] builder_shared_dat_w; +wire builder_shared_err; +wire [3:0] builder_shared_sel; +wire builder_shared_stb; +wire builder_shared_we; +reg [1:0] builder_slave_sel = 2'd0; +reg [1:0] builder_slave_sel_r = 2'd0; +wire [31:0] builder_t_slice_proxy0; +wire [31:0] builder_t_slice_proxy1; +wire [31:0] builder_t_slice_proxy10; +wire [31:0] builder_t_slice_proxy11; +wire [31:0] builder_t_slice_proxy12; +wire [31:0] builder_t_slice_proxy13; +wire [31:0] builder_t_slice_proxy14; +wire [31:0] builder_t_slice_proxy15; +wire [31:0] builder_t_slice_proxy16; +wire [31:0] builder_t_slice_proxy17; +wire [31:0] builder_t_slice_proxy18; +wire [31:0] builder_t_slice_proxy19; +wire [31:0] builder_t_slice_proxy2; +wire [31:0] builder_t_slice_proxy20; +wire [31:0] builder_t_slice_proxy21; +wire [31:0] builder_t_slice_proxy22; +wire [31:0] builder_t_slice_proxy23; +wire [31:0] builder_t_slice_proxy24; +wire [31:0] builder_t_slice_proxy25; +wire [31:0] builder_t_slice_proxy26; +wire [31:0] builder_t_slice_proxy27; +wire [31:0] builder_t_slice_proxy28; +wire [31:0] builder_t_slice_proxy29; +wire [31:0] builder_t_slice_proxy3; +wire [31:0] builder_t_slice_proxy30; +wire [31:0] builder_t_slice_proxy31; +wire [31:0] builder_t_slice_proxy32; +wire [31:0] builder_t_slice_proxy33; +wire [31:0] builder_t_slice_proxy34; +wire [31:0] builder_t_slice_proxy35; +wire [31:0] builder_t_slice_proxy36; +wire [31:0] builder_t_slice_proxy37; +wire [31:0] builder_t_slice_proxy38; +wire [31:0] builder_t_slice_proxy39; +wire [31:0] builder_t_slice_proxy4; +wire [31:0] builder_t_slice_proxy40; +wire [31:0] builder_t_slice_proxy41; +wire [31:0] builder_t_slice_proxy42; +wire [31:0] builder_t_slice_proxy43; +wire [31:0] builder_t_slice_proxy44; +wire [31:0] builder_t_slice_proxy45; +wire [31:0] builder_t_slice_proxy46; +wire [31:0] builder_t_slice_proxy47; +wire [31:0] builder_t_slice_proxy48; +wire [31:0] builder_t_slice_proxy49; +wire [31:0] builder_t_slice_proxy5; +wire [31:0] builder_t_slice_proxy50; +wire [31:0] builder_t_slice_proxy51; +wire [31:0] builder_t_slice_proxy52; +wire [31:0] builder_t_slice_proxy53; +wire [31:0] builder_t_slice_proxy54; +wire [31:0] builder_t_slice_proxy55; +wire [31:0] builder_t_slice_proxy56; +wire [31:0] builder_t_slice_proxy57; +wire [31:0] builder_t_slice_proxy58; +wire [31:0] builder_t_slice_proxy59; +wire [31:0] builder_t_slice_proxy6; +wire [31:0] builder_t_slice_proxy60; +wire [31:0] builder_t_slice_proxy61; +wire [31:0] builder_t_slice_proxy62; +wire [31:0] builder_t_slice_proxy63; +wire [31:0] builder_t_slice_proxy7; +wire [31:0] builder_t_slice_proxy8; +wire [31:0] builder_t_slice_proxy9; +reg [1:0] builder_txdatapath_bufferizeendpoints_next_state = 2'd0; +reg [1:0] builder_txdatapath_bufferizeendpoints_state = 2'd0; +reg builder_txdatapath_liteethmacgap_next_state = 1'd0; +reg builder_txdatapath_liteethmacgap_state = 1'd0; +reg builder_txdatapath_liteethmacpaddinginserter_next_state = 1'd0; +reg builder_txdatapath_liteethmacpaddinginserter_state = 1'd0; +reg [1:0] builder_txdatapath_liteethmacpreambleinserter_next_state = 2'd0; +reg [1:0] builder_txdatapath_liteethmacpreambleinserter_state = 2'd0; +reg builder_txdatapath_liteethmactxlastbe_next_state = 1'd0; +reg builder_txdatapath_liteethmactxlastbe_state = 1'd0; +wire builder_wait; +wire builder_we; +reg builder_wishbone2csr_next_state = 1'd0; +reg builder_wishbone2csr_state = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl00 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl01 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl10 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl11 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl20 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl21 = 6'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl30 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl31 = 6'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl40 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl41 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl50 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl51 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl60 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl61 = 6'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl70 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl71 = 6'd0; +(* dont_touch = "true" *) +wire eth_rx_clk; +wire eth_rx_rst; +(* dont_touch = "true" *) +wire eth_tx_clk; +wire eth_tx_rst; +wire main_bufferizeendpoints_pipe_valid_sink_first; +wire main_bufferizeendpoints_pipe_valid_sink_last; +wire [7:0] main_bufferizeendpoints_pipe_valid_sink_payload_data; +wire main_bufferizeendpoints_pipe_valid_sink_payload_error; +wire main_bufferizeendpoints_pipe_valid_sink_payload_last_be; +wire main_bufferizeendpoints_pipe_valid_sink_ready; +wire main_bufferizeendpoints_pipe_valid_sink_valid; +reg main_bufferizeendpoints_pipe_valid_source_first = 1'd0; +reg main_bufferizeendpoints_pipe_valid_source_last = 1'd0; +reg [7:0] main_bufferizeendpoints_pipe_valid_source_payload_data = 8'd0; +reg main_bufferizeendpoints_pipe_valid_source_payload_error = 1'd0; +reg main_bufferizeendpoints_pipe_valid_source_payload_last_be = 1'd0; +wire main_bufferizeendpoints_pipe_valid_source_ready; +reg main_bufferizeendpoints_pipe_valid_source_valid = 1'd0; +wire main_bufferizeendpoints_sink_sink_first; +wire main_bufferizeendpoints_sink_sink_last; +wire [7:0] main_bufferizeendpoints_sink_sink_payload_data; +wire main_bufferizeendpoints_sink_sink_payload_error; +wire main_bufferizeendpoints_sink_sink_payload_last_be; +wire main_bufferizeendpoints_sink_sink_ready; +wire main_bufferizeendpoints_sink_sink_valid; +wire main_bufferizeendpoints_source_source_first; +wire main_bufferizeendpoints_source_source_last; +wire [7:0] main_bufferizeendpoints_source_source_payload_data; +wire main_bufferizeendpoints_source_source_payload_error; +wire main_bufferizeendpoints_source_source_payload_last_be; +wire main_bufferizeendpoints_source_source_ready; +wire main_bufferizeendpoints_source_source_valid; +wire main_bus_ack; +wire [29:0] main_bus_adr; +wire [1:0] main_bus_bte; +wire [2:0] main_bus_cti; +wire main_bus_cyc; +wire [31:0] main_bus_dat_r; +wire [31:0] main_bus_dat_w; +wire main_bus_err; +wire [3:0] main_bus_sel; +wire main_bus_stb; +wire main_bus_we; +reg main_crc_errors_re = 1'd0; +reg [31:0] main_crc_errors_status = 32'd0; +wire main_crc_errors_we; +reg main_interface0_ack = 1'd0; +wire [29:0] main_interface0_adr; +wire [1:0] main_interface0_bte; +wire [2:0] main_interface0_cti; +wire main_interface0_cyc; +wire [31:0] main_interface0_dat_r; +wire [31:0] main_interface0_dat_w; +reg main_interface0_err = 1'd0; +wire [3:0] main_interface0_sel; +wire main_interface0_stb; +wire main_interface0_we; +reg main_interface1_ack = 1'd0; +wire [29:0] main_interface1_adr; +wire [1:0] main_interface1_bte; +wire [2:0] main_interface1_cti; +wire main_interface1_cyc; +wire [31:0] main_interface1_dat_r; +wire [31:0] main_interface1_dat_w; +reg main_interface1_err = 1'd0; +wire [3:0] main_interface1_sel; +wire main_interface1_stb; +wire main_interface1_we; +reg main_interface2_ack = 1'd0; +wire [29:0] main_interface2_adr; +wire [1:0] main_interface2_bte; +wire [2:0] main_interface2_cti; +wire main_interface2_cyc; +wire [31:0] main_interface2_dat_r; +wire [31:0] main_interface2_dat_w; +reg main_interface2_err = 1'd0; +wire [3:0] main_interface2_sel; +wire main_interface2_stb; +wire main_interface2_we; +reg main_interface3_ack = 1'd0; +wire [29:0] main_interface3_adr; +wire [1:0] main_interface3_bte; +wire [2:0] main_interface3_cti; +wire main_interface3_cyc; +wire [31:0] main_interface3_dat_r; +wire [31:0] main_interface3_dat_w; +reg main_interface3_err = 1'd0; +wire [3:0] main_interface3_sel; +wire main_interface3_stb; +wire main_interface3_we; +reg [3:0] main_length_inc = 4'd0; +wire main_liteethmaccrc32checker_crc_be; +reg main_liteethmaccrc32checker_crc_ce = 1'd0; +reg [31:0] main_liteethmaccrc32checker_crc_crc_next = 32'd0; +wire [31:0] main_liteethmaccrc32checker_crc_crc_prev; +wire [7:0] main_liteethmaccrc32checker_crc_data0; +wire [7:0] main_liteethmaccrc32checker_crc_data1; +reg main_liteethmaccrc32checker_crc_error0 = 1'd0; +reg main_liteethmaccrc32checker_crc_error1 = 1'd0; +reg main_liteethmaccrc32checker_crc_error1_next_value1 = 1'd0; +reg main_liteethmaccrc32checker_crc_error1_next_value_ce1 = 1'd0; +reg [31:0] main_liteethmaccrc32checker_crc_reg = 32'd4294967295; +reg main_liteethmaccrc32checker_crc_reset = 1'd0; +reg [31:0] main_liteethmaccrc32checker_crc_value = 32'd0; +reg main_liteethmaccrc32checker_error = 1'd0; +wire main_liteethmaccrc32checker_fifo_full; +wire main_liteethmaccrc32checker_fifo_in; +wire main_liteethmaccrc32checker_fifo_out; +reg main_liteethmaccrc32checker_fifo_reset = 1'd0; +reg main_liteethmaccrc32checker_last_be = 1'd0; +reg main_liteethmaccrc32checker_last_be_next_value0 = 1'd0; +reg main_liteethmaccrc32checker_last_be_next_value_ce0 = 1'd0; +wire main_liteethmaccrc32checker_sink_sink_first; +wire main_liteethmaccrc32checker_sink_sink_last; +wire [7:0] main_liteethmaccrc32checker_sink_sink_payload_data; +wire main_liteethmaccrc32checker_sink_sink_payload_error; +wire main_liteethmaccrc32checker_sink_sink_payload_last_be; +reg main_liteethmaccrc32checker_sink_sink_ready = 1'd0; +wire main_liteethmaccrc32checker_sink_sink_valid; +wire main_liteethmaccrc32checker_source_source_first; +reg main_liteethmaccrc32checker_source_source_last = 1'd0; +wire [7:0] main_liteethmaccrc32checker_source_source_payload_data; +reg main_liteethmaccrc32checker_source_source_payload_error = 1'd0; +reg main_liteethmaccrc32checker_source_source_payload_last_be = 1'd0; +wire main_liteethmaccrc32checker_source_source_ready; +reg main_liteethmaccrc32checker_source_source_valid = 1'd0; +reg [2:0] main_liteethmaccrc32checker_syncfifo_consume = 3'd0; +wire main_liteethmaccrc32checker_syncfifo_do_read; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_first; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_first; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; +reg [2:0] main_liteethmaccrc32checker_syncfifo_level = 3'd0; +reg [2:0] main_liteethmaccrc32checker_syncfifo_produce = 3'd0; +wire [2:0] main_liteethmaccrc32checker_syncfifo_rdport_adr; +wire [11:0] main_liteethmaccrc32checker_syncfifo_rdport_dat_r; +reg main_liteethmaccrc32checker_syncfifo_replace = 1'd0; +wire main_liteethmaccrc32checker_syncfifo_sink_first; +wire main_liteethmaccrc32checker_syncfifo_sink_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_sink_payload_data; +wire main_liteethmaccrc32checker_syncfifo_sink_payload_error; +wire main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; +wire main_liteethmaccrc32checker_syncfifo_sink_ready; +reg main_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; +wire main_liteethmaccrc32checker_syncfifo_source_first; +wire main_liteethmaccrc32checker_syncfifo_source_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_source_payload_data; +wire main_liteethmaccrc32checker_syncfifo_source_payload_error; +wire main_liteethmaccrc32checker_syncfifo_source_payload_last_be; +reg main_liteethmaccrc32checker_syncfifo_source_ready = 1'd0; +wire main_liteethmaccrc32checker_syncfifo_source_valid; +wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_din; +wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_dout; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_re; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_readable; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_we; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_writable; +reg [2:0] main_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; +wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_r; +wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_w; +wire main_liteethmaccrc32checker_syncfifo_wrport_we; +reg main_maccore_ethphy__r_re = 1'd0; +reg main_maccore_ethphy__r_status = 1'd0; +wire main_maccore_ethphy__r_we; +reg main_maccore_ethphy__w_re = 1'd0; +reg [2:0] main_maccore_ethphy__w_storage = 3'd0; +reg [8:0] main_maccore_ethphy_counter = 9'd0; +wire main_maccore_ethphy_counter_ce; +wire main_maccore_ethphy_counter_done; +wire main_maccore_ethphy_data_oe; +wire main_maccore_ethphy_data_r; +wire main_maccore_ethphy_data_w; +reg main_maccore_ethphy_demux_endpoint0_source_first = 1'd0; +reg main_maccore_ethphy_demux_endpoint0_source_last = 1'd0; +reg [7:0] main_maccore_ethphy_demux_endpoint0_source_payload_data = 8'd0; +reg main_maccore_ethphy_demux_endpoint0_source_payload_error = 1'd0; +reg main_maccore_ethphy_demux_endpoint0_source_payload_last_be = 1'd0; +wire main_maccore_ethphy_demux_endpoint0_source_ready; +reg main_maccore_ethphy_demux_endpoint0_source_valid = 1'd0; +reg main_maccore_ethphy_demux_endpoint1_source_first = 1'd0; +reg main_maccore_ethphy_demux_endpoint1_source_last = 1'd0; +reg [7:0] main_maccore_ethphy_demux_endpoint1_source_payload_data = 8'd0; +reg main_maccore_ethphy_demux_endpoint1_source_payload_error = 1'd0; +reg main_maccore_ethphy_demux_endpoint1_source_payload_last_be = 1'd0; +wire main_maccore_ethphy_demux_endpoint1_source_ready; +reg main_maccore_ethphy_demux_endpoint1_source_valid = 1'd0; +wire main_maccore_ethphy_demux_sel; +wire main_maccore_ethphy_demux_sink_first; +wire main_maccore_ethphy_demux_sink_last; +wire [7:0] main_maccore_ethphy_demux_sink_payload_data; +wire main_maccore_ethphy_demux_sink_payload_error; +wire main_maccore_ethphy_demux_sink_payload_last_be; +reg main_maccore_ethphy_demux_sink_ready = 1'd0; +wire main_maccore_ethphy_demux_sink_valid; +reg [9:0] main_maccore_ethphy_eth_counter = 10'd0; +wire main_maccore_ethphy_eth_tick; +reg main_maccore_ethphy_eth_tx_clk = 1'd0; +reg main_maccore_ethphy_gmii_rx_dv_d = 1'd0; +reg main_maccore_ethphy_gmii_rx_source_first = 1'd0; +wire main_maccore_ethphy_gmii_rx_source_last; +reg [7:0] main_maccore_ethphy_gmii_rx_source_payload_data = 8'd0; +reg main_maccore_ethphy_gmii_rx_source_payload_error = 1'd0; +reg main_maccore_ethphy_gmii_rx_source_payload_last_be = 1'd0; +wire main_maccore_ethphy_gmii_rx_source_ready; +reg main_maccore_ethphy_gmii_rx_source_valid = 1'd0; +reg [7:0] main_maccore_ethphy_gmii_tx_pads_tx_data = 8'd0; +reg main_maccore_ethphy_gmii_tx_pads_tx_en = 1'd0; +reg main_maccore_ethphy_gmii_tx_pads_tx_er = 1'd0; +wire main_maccore_ethphy_gmii_tx_sink_first; +wire main_maccore_ethphy_gmii_tx_sink_last; +wire [7:0] main_maccore_ethphy_gmii_tx_sink_payload_data; +wire main_maccore_ethphy_gmii_tx_sink_payload_error; +wire main_maccore_ethphy_gmii_tx_sink_payload_last_be; +reg main_maccore_ethphy_gmii_tx_sink_ready = 1'd0; +wire main_maccore_ethphy_gmii_tx_sink_valid; +wire main_maccore_ethphy_i; +wire main_maccore_ethphy_mdc; +reg main_maccore_ethphy_mii_rx_converter_demux = 1'd0; +wire main_maccore_ethphy_mii_rx_converter_load_part; +reg main_maccore_ethphy_mii_rx_converter_sink_first = 1'd0; +wire main_maccore_ethphy_mii_rx_converter_sink_last; +reg [3:0] main_maccore_ethphy_mii_rx_converter_sink_payload_data = 4'd0; +wire main_maccore_ethphy_mii_rx_converter_sink_ready; +reg main_maccore_ethphy_mii_rx_converter_sink_valid = 1'd0; +reg main_maccore_ethphy_mii_rx_converter_source_first = 1'd0; +reg main_maccore_ethphy_mii_rx_converter_source_last = 1'd0; +reg [7:0] main_maccore_ethphy_mii_rx_converter_source_payload_data = 8'd0; +reg [1:0] main_maccore_ethphy_mii_rx_converter_source_payload_valid_token_count = 2'd0; +wire main_maccore_ethphy_mii_rx_converter_source_ready; +wire main_maccore_ethphy_mii_rx_converter_source_valid; +reg main_maccore_ethphy_mii_rx_converter_strobe_all = 1'd0; +reg main_maccore_ethphy_mii_rx_reset = 1'd0; +wire main_maccore_ethphy_mii_rx_source_first; +wire main_maccore_ethphy_mii_rx_source_last; +wire [7:0] main_maccore_ethphy_mii_rx_source_payload_data; +reg main_maccore_ethphy_mii_rx_source_payload_error = 1'd0; +reg main_maccore_ethphy_mii_rx_source_payload_last_be = 1'd0; +wire main_maccore_ethphy_mii_rx_source_ready; +wire main_maccore_ethphy_mii_rx_source_source_first; +wire main_maccore_ethphy_mii_rx_source_source_last; +wire [7:0] main_maccore_ethphy_mii_rx_source_source_payload_data; +wire main_maccore_ethphy_mii_rx_source_source_ready; +wire main_maccore_ethphy_mii_rx_source_source_valid; +wire main_maccore_ethphy_mii_rx_source_valid; +wire main_maccore_ethphy_mii_tx_converter_first; +wire main_maccore_ethphy_mii_tx_converter_last; +reg main_maccore_ethphy_mii_tx_converter_mux = 1'd0; +reg main_maccore_ethphy_mii_tx_converter_sink_first = 1'd0; +reg main_maccore_ethphy_mii_tx_converter_sink_last = 1'd0; +wire [7:0] main_maccore_ethphy_mii_tx_converter_sink_payload_data; +wire main_maccore_ethphy_mii_tx_converter_sink_ready; +wire main_maccore_ethphy_mii_tx_converter_sink_valid; +wire main_maccore_ethphy_mii_tx_converter_source_first; +wire main_maccore_ethphy_mii_tx_converter_source_last; +reg [3:0] main_maccore_ethphy_mii_tx_converter_source_payload_data = 4'd0; +wire main_maccore_ethphy_mii_tx_converter_source_payload_valid_token_count; +wire main_maccore_ethphy_mii_tx_converter_source_ready; +wire main_maccore_ethphy_mii_tx_converter_source_valid; +reg [7:0] main_maccore_ethphy_mii_tx_pads_tx_data = 8'd0; +reg main_maccore_ethphy_mii_tx_pads_tx_en = 1'd0; +reg main_maccore_ethphy_mii_tx_pads_tx_er = 1'd0; +wire main_maccore_ethphy_mii_tx_sink_first; +wire main_maccore_ethphy_mii_tx_sink_last; +wire [7:0] main_maccore_ethphy_mii_tx_sink_payload_data; +wire main_maccore_ethphy_mii_tx_sink_payload_error; +wire main_maccore_ethphy_mii_tx_sink_payload_last_be; +wire main_maccore_ethphy_mii_tx_sink_ready; +wire main_maccore_ethphy_mii_tx_sink_valid; +wire main_maccore_ethphy_mii_tx_source_source_first; +wire main_maccore_ethphy_mii_tx_source_source_last; +wire [3:0] main_maccore_ethphy_mii_tx_source_source_payload_data; +wire main_maccore_ethphy_mii_tx_source_source_ready; +wire main_maccore_ethphy_mii_tx_source_source_valid; +reg main_maccore_ethphy_mode0 = 1'd0; +reg main_maccore_ethphy_mode1 = 1'd0; +reg main_maccore_ethphy_mode_re = 1'd0; +wire main_maccore_ethphy_mode_status; +wire main_maccore_ethphy_mode_we; +wire main_maccore_ethphy_mux_endpoint0_sink_first; +wire main_maccore_ethphy_mux_endpoint0_sink_last; +wire [7:0] main_maccore_ethphy_mux_endpoint0_sink_payload_data; +wire main_maccore_ethphy_mux_endpoint0_sink_payload_error; +wire main_maccore_ethphy_mux_endpoint0_sink_payload_last_be; +reg main_maccore_ethphy_mux_endpoint0_sink_ready = 1'd0; +wire main_maccore_ethphy_mux_endpoint0_sink_valid; +wire main_maccore_ethphy_mux_endpoint1_sink_first; +wire main_maccore_ethphy_mux_endpoint1_sink_last; +wire [7:0] main_maccore_ethphy_mux_endpoint1_sink_payload_data; +wire main_maccore_ethphy_mux_endpoint1_sink_payload_error; +wire main_maccore_ethphy_mux_endpoint1_sink_payload_last_be; +reg main_maccore_ethphy_mux_endpoint1_sink_ready = 1'd0; +wire main_maccore_ethphy_mux_endpoint1_sink_valid; +wire main_maccore_ethphy_mux_sel; +reg main_maccore_ethphy_mux_source_first = 1'd0; +reg main_maccore_ethphy_mux_source_last = 1'd0; +reg [7:0] main_maccore_ethphy_mux_source_payload_data = 8'd0; +reg main_maccore_ethphy_mux_source_payload_error = 1'd0; +reg main_maccore_ethphy_mux_source_payload_last_be = 1'd0; +wire main_maccore_ethphy_mux_source_ready; +reg main_maccore_ethphy_mux_source_valid = 1'd0; +wire main_maccore_ethphy_o; +wire main_maccore_ethphy_oe; +reg [7:0] main_maccore_ethphy_pads_d_rx_data = 8'd0; +reg main_maccore_ethphy_pads_d_rx_dv = 1'd0; +reg main_maccore_ethphy_r = 1'd0; +wire main_maccore_ethphy_reset0; +wire main_maccore_ethphy_reset1; +reg main_maccore_ethphy_reset_re = 1'd0; +reg main_maccore_ethphy_reset_storage = 1'd0; +wire main_maccore_ethphy_sink_sink_first; +wire main_maccore_ethphy_sink_sink_last; +wire [7:0] main_maccore_ethphy_sink_sink_payload_data; +wire main_maccore_ethphy_sink_sink_payload_error; +wire main_maccore_ethphy_sink_sink_payload_last_be; +wire main_maccore_ethphy_sink_sink_ready; +wire main_maccore_ethphy_sink_sink_valid; +wire main_maccore_ethphy_source_source_first; +wire main_maccore_ethphy_source_source_last; +wire [7:0] main_maccore_ethphy_source_source_payload_data; +wire main_maccore_ethphy_source_source_payload_error; +wire main_maccore_ethphy_source_source_payload_last_be; +wire main_maccore_ethphy_source_source_ready; +wire main_maccore_ethphy_source_source_valid; +reg [23:0] main_maccore_ethphy_sys_counter = 24'd0; +reg main_maccore_ethphy_sys_counter_ce = 1'd0; +reg main_maccore_ethphy_sys_counter_reset = 1'd0; +wire main_maccore_ethphy_sys_tick; +reg main_maccore_ethphy_toggle_i = 1'd0; +wire main_maccore_ethphy_toggle_o; +reg main_maccore_ethphy_toggle_o_r = 1'd0; +reg main_maccore_ethphy_update_mode = 1'd0; +wire main_maccore_ethphy_w; +reg main_maccore_int_rst = 1'd1; +wire main_maccore_maccore_bus_error; +reg [31:0] main_maccore_maccore_bus_errors = 32'd0; +reg main_maccore_maccore_bus_errors_re = 1'd0; +wire [31:0] main_maccore_maccore_bus_errors_status; +wire main_maccore_maccore_bus_errors_we; +wire main_maccore_maccore_cpu_rst; +reg main_maccore_maccore_reset_re = 1'd0; +reg [1:0] main_maccore_maccore_reset_storage = 2'd0; +reg main_maccore_maccore_scratch_re = 1'd0; +reg [31:0] main_maccore_maccore_scratch_storage = 32'd305419896; +reg main_maccore_maccore_soc_rst = 1'd0; +reg main_preamble_errors_re = 1'd0; +reg [31:0] main_preamble_errors_status = 32'd0; +wire main_preamble_errors_we; +wire main_pulsesynchronizer0_i; +wire main_pulsesynchronizer0_o; +reg main_pulsesynchronizer0_toggle_i = 1'd0; +wire main_pulsesynchronizer0_toggle_o; +reg main_pulsesynchronizer0_toggle_o_r = 1'd0; +wire main_pulsesynchronizer1_i; +wire main_pulsesynchronizer1_o; +reg main_pulsesynchronizer1_toggle_i = 1'd0; +wire main_pulsesynchronizer1_toggle_o; +reg main_pulsesynchronizer1_toggle_o_r = 1'd0; +reg [31:0] main_rd_data = 32'd0; +reg main_re = 1'd0; +reg main_read = 1'd0; +wire [41:0] main_rx_cdc_cdc_asyncfifo_din; +wire [41:0] main_rx_cdc_cdc_asyncfifo_dout; +wire main_rx_cdc_cdc_asyncfifo_re; +wire main_rx_cdc_cdc_asyncfifo_readable; +wire main_rx_cdc_cdc_asyncfifo_we; +wire main_rx_cdc_cdc_asyncfifo_writable; +wire [5:0] main_rx_cdc_cdc_consume_wdomain; +wire main_rx_cdc_cdc_fifo_in_first; +wire main_rx_cdc_cdc_fifo_in_last; +wire [31:0] main_rx_cdc_cdc_fifo_in_payload_data; +wire [3:0] main_rx_cdc_cdc_fifo_in_payload_error; +wire [3:0] main_rx_cdc_cdc_fifo_in_payload_last_be; +wire main_rx_cdc_cdc_fifo_out_first; +wire main_rx_cdc_cdc_fifo_out_last; +wire [31:0] main_rx_cdc_cdc_fifo_out_payload_data; +wire [3:0] main_rx_cdc_cdc_fifo_out_payload_error; +wire [3:0] main_rx_cdc_cdc_fifo_out_payload_last_be; +wire main_rx_cdc_cdc_graycounter0_ce; +(* dont_touch = "true" *) +reg [5:0] main_rx_cdc_cdc_graycounter0_q = 6'd0; +reg [5:0] main_rx_cdc_cdc_graycounter0_q_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_graycounter0_q_next; +reg [5:0] main_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire main_rx_cdc_cdc_graycounter1_ce; +(* dont_touch = "true" *) +reg [5:0] main_rx_cdc_cdc_graycounter1_q = 6'd0; +reg [5:0] main_rx_cdc_cdc_graycounter1_q_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_graycounter1_q_next; +reg [5:0] main_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_produce_rdomain; +wire [4:0] main_rx_cdc_cdc_rdport_adr; +wire [41:0] main_rx_cdc_cdc_rdport_dat_r; +wire main_rx_cdc_cdc_sink_first; +wire main_rx_cdc_cdc_sink_last; +wire [31:0] main_rx_cdc_cdc_sink_payload_data; +wire [3:0] main_rx_cdc_cdc_sink_payload_error; +wire [3:0] main_rx_cdc_cdc_sink_payload_last_be; +wire main_rx_cdc_cdc_sink_ready; +wire main_rx_cdc_cdc_sink_valid; +wire main_rx_cdc_cdc_source_first; +wire main_rx_cdc_cdc_source_last; +wire [31:0] main_rx_cdc_cdc_source_payload_data; +wire [3:0] main_rx_cdc_cdc_source_payload_error; +wire [3:0] main_rx_cdc_cdc_source_payload_last_be; +wire main_rx_cdc_cdc_source_ready; +wire main_rx_cdc_cdc_source_valid; +wire [4:0] main_rx_cdc_cdc_wrport_adr; +wire [41:0] main_rx_cdc_cdc_wrport_dat_r; +wire [41:0] main_rx_cdc_cdc_wrport_dat_w; +wire main_rx_cdc_cdc_wrport_we; +wire main_rx_cdc_sink_sink_first; +wire main_rx_cdc_sink_sink_last; +wire [31:0] main_rx_cdc_sink_sink_payload_data; +wire [3:0] main_rx_cdc_sink_sink_payload_error; +wire [3:0] main_rx_cdc_sink_sink_payload_last_be; +wire main_rx_cdc_sink_sink_ready; +wire main_rx_cdc_sink_sink_valid; +wire main_rx_cdc_source_source_first; +wire main_rx_cdc_source_source_last; +wire [31:0] main_rx_cdc_source_source_payload_data; +wire [3:0] main_rx_cdc_source_source_payload_error; +wire [3:0] main_rx_cdc_source_source_payload_last_be; +wire main_rx_cdc_source_source_ready; +wire main_rx_cdc_source_source_valid; +reg [1:0] main_rx_converter_converter_demux = 2'd0; +wire main_rx_converter_converter_load_part; +wire main_rx_converter_converter_sink_first; +wire main_rx_converter_converter_sink_last; +wire [9:0] main_rx_converter_converter_sink_payload_data; +wire main_rx_converter_converter_sink_ready; +wire main_rx_converter_converter_sink_valid; +reg main_rx_converter_converter_source_first = 1'd0; +reg main_rx_converter_converter_source_last = 1'd0; +reg [39:0] main_rx_converter_converter_source_payload_data = 40'd0; +reg [2:0] main_rx_converter_converter_source_payload_valid_token_count = 3'd0; +wire main_rx_converter_converter_source_ready; +wire main_rx_converter_converter_source_valid; +reg main_rx_converter_converter_strobe_all = 1'd0; +wire main_rx_converter_sink_first; +wire main_rx_converter_sink_last; +wire [7:0] main_rx_converter_sink_payload_data; +wire main_rx_converter_sink_payload_error; +wire main_rx_converter_sink_payload_last_be; +wire main_rx_converter_sink_ready; +wire main_rx_converter_sink_valid; +wire main_rx_converter_source_first; +wire main_rx_converter_source_last; +reg [31:0] main_rx_converter_source_payload_data = 32'd0; +reg [3:0] main_rx_converter_source_payload_error = 4'd0; +reg [3:0] main_rx_converter_source_payload_last_be = 4'd0; +wire main_rx_converter_source_ready; +wire main_rx_converter_source_source_first; +wire main_rx_converter_source_source_last; +wire [39:0] main_rx_converter_source_source_payload_data; +wire main_rx_converter_source_source_ready; +wire main_rx_converter_source_source_valid; +wire main_rx_converter_source_valid; +wire main_rx_last_be_sink_first; +wire main_rx_last_be_sink_last; +wire [7:0] main_rx_last_be_sink_payload_data; +wire main_rx_last_be_sink_payload_error; +wire main_rx_last_be_sink_payload_last_be; +wire main_rx_last_be_sink_ready; +wire main_rx_last_be_sink_valid; +wire main_rx_last_be_source_first; +wire main_rx_last_be_source_last; +wire [7:0] main_rx_last_be_source_payload_data; +wire main_rx_last_be_source_payload_error; +reg main_rx_last_be_source_payload_last_be = 1'd0; +wire main_rx_last_be_source_ready; +wire main_rx_last_be_source_valid; +wire main_rx_padding_sink_first; +wire main_rx_padding_sink_last; +wire [7:0] main_rx_padding_sink_payload_data; +wire main_rx_padding_sink_payload_error; +wire main_rx_padding_sink_payload_last_be; +wire main_rx_padding_sink_ready; +wire main_rx_padding_sink_valid; +wire main_rx_padding_source_first; +wire main_rx_padding_source_last; +wire [7:0] main_rx_padding_source_payload_data; +wire main_rx_padding_source_payload_error; +wire main_rx_padding_source_payload_last_be; +wire main_rx_padding_source_ready; +wire main_rx_padding_source_valid; +reg main_rx_preamble_error = 1'd0; +reg [63:0] main_rx_preamble_preamble = 64'd15372286728091293013; +wire main_rx_preamble_sink_first; +wire main_rx_preamble_sink_last; +wire [7:0] main_rx_preamble_sink_payload_data; +wire main_rx_preamble_sink_payload_error; +wire main_rx_preamble_sink_payload_last_be; +reg main_rx_preamble_sink_ready = 1'd0; +wire main_rx_preamble_sink_valid; +reg main_rx_preamble_source_first = 1'd0; +reg main_rx_preamble_source_last = 1'd0; +wire [7:0] main_rx_preamble_source_payload_data; +reg main_rx_preamble_source_payload_error = 1'd0; +wire main_rx_preamble_source_payload_last_be; +wire main_rx_preamble_source_ready; +reg main_rx_preamble_source_valid = 1'd0; +wire main_sink_first; +wire main_sink_last; +wire [31:0] main_sink_payload_data; +wire [3:0] main_sink_payload_error; +wire [3:0] main_sink_payload_last_be; +wire main_sink_ready; +wire main_sink_sink_first; +wire main_sink_sink_last; +wire [31:0] main_sink_sink_payload_data; +wire [3:0] main_sink_sink_payload_error; +wire [3:0] main_sink_sink_payload_last_be; +wire main_sink_sink_ready; +wire main_sink_sink_valid; +wire main_sink_valid; +reg [3:0] main_slave_sel = 4'd0; +reg [3:0] main_slave_sel_r = 4'd0; +reg main_slot = 1'd0; +reg main_slot_liteethmacsramwriter_next_value = 1'd0; +reg main_slot_liteethmacsramwriter_next_value_ce = 1'd0; +wire main_source_first; +wire main_source_last; +wire [31:0] main_source_payload_data; +wire [3:0] main_source_payload_error; +wire [3:0] main_source_payload_last_be; +wire main_source_ready; +wire main_source_source_first; +wire main_source_source_last; +wire [31:0] main_source_source_payload_data; +wire [3:0] main_source_source_payload_error; +wire [3:0] main_source_source_payload_last_be; +wire main_source_source_ready; +wire main_source_source_valid; +wire main_source_valid; +wire [8:0] main_sram0_adr; +reg main_sram0_adr_burst = 1'd0; +wire [31:0] main_sram0_dat_r; +wire main_sram0_sink_valid; +reg main_sram100_storage = 1'd0; +reg main_sram101_re = 1'd0; +reg [10:0] main_sram102_storage = 11'd0; +reg main_sram103_re = 1'd0; +wire main_sram104_irq; +wire main_sram105_status; +reg main_sram106_pending = 1'd0; +reg main_sram107_trigger = 1'd0; +reg main_sram108_clear = 1'd0; +wire main_sram109_event0; +wire [10:0] main_sram10_status; +reg main_sram110_status = 1'd0; +wire main_sram111_we; +reg main_sram112_re = 1'd0; +wire main_sram113_event0; +reg main_sram114_status = 1'd0; +wire main_sram115_we; +reg main_sram116_re = 1'd0; +reg main_sram117_r = 1'd0; +wire main_sram118_event0; +reg main_sram119_storage = 1'd0; +wire main_sram11_we; +reg main_sram120_re = 1'd0; +reg [10:0] main_sram122_length = 11'd0; +reg [10:0] main_sram122_length_liteethmacsramreader_next_value = 11'd0; +reg main_sram122_length_liteethmacsramreader_next_value_ce = 1'd0; +wire main_sram123_sink_valid; +wire main_sram124_sink_ready; +reg main_sram125_sink_first = 1'd0; +reg main_sram126_sink_last = 1'd0; +wire main_sram127_sink_payload_slot; +wire [10:0] main_sram128_sink_payload_length; +wire main_sram129_source_valid; +reg main_sram12_re = 1'd0; +reg main_sram130_source_ready = 1'd0; +wire main_sram131_source_first; +wire main_sram132_source_last; +wire main_sram133_source_payload_slot; +wire [10:0] main_sram134_source_payload_length; +wire main_sram135_we; +wire main_sram136_writable; +wire main_sram137_re; +wire main_sram138_readable; +wire [13:0] main_sram139_din; +reg [31:0] main_sram13_status = 32'd0; +reg [31:0] main_sram13_status_liteethmacsramwriter_f_next_value = 32'd0; +reg main_sram13_status_liteethmacsramwriter_f_next_value_ce = 1'd0; +wire [13:0] main_sram140_dout; +reg [1:0] main_sram141_level = 2'd0; +reg main_sram142_replace = 1'd0; +reg main_sram143_produce = 1'd0; +reg main_sram144_consume = 1'd0; +reg main_sram145_adr = 1'd0; +wire [13:0] main_sram146_dat_r; +wire main_sram147_we; +wire [13:0] main_sram148_dat_w; +wire main_sram149_do_read; +wire main_sram14_we; +wire main_sram150_adr; +wire [13:0] main_sram151_dat_r; +wire main_sram152_fifo_in_payload_slot; +wire [10:0] main_sram153_fifo_in_payload_length; +wire main_sram154_fifo_in_first; +wire main_sram155_fifo_in_last; +wire main_sram156_fifo_out_payload_slot; +wire [10:0] main_sram157_fifo_out_payload_length; +wire main_sram158_fifo_out_first; +wire main_sram159_fifo_out_last; +reg main_sram15_re = 1'd0; +wire [8:0] main_sram161_adr; +wire [31:0] main_sram162_dat_r; +wire main_sram163_re; +wire [8:0] main_sram164_adr; +wire [31:0] main_sram165_dat_r; +wire main_sram166_re; +wire main_sram167_irq; +wire main_sram16_irq; +wire main_sram17_status; +wire main_sram18_pending; +wire main_sram19_trigger; +wire [8:0] main_sram1_adr; +reg main_sram1_adr_burst = 1'd0; +wire [31:0] main_sram1_dat_r; +reg main_sram1_sink_ready = 1'd1; +reg main_sram20_clear = 1'd0; +wire main_sram21_available; +reg main_sram22_status = 1'd0; +wire main_sram23_we; +reg main_sram24_re = 1'd0; +wire main_sram25_available; +reg main_sram26_status = 1'd0; +wire main_sram27_we; +reg main_sram28_re = 1'd0; +reg main_sram29_r = 1'd0; +wire [8:0] main_sram2_adr; +reg main_sram2_adr_burst = 1'd0; +wire [31:0] main_sram2_dat_r; +wire [31:0] main_sram2_dat_w; +wire main_sram2_sink_first; +reg [3:0] main_sram2_we = 4'd0; +wire main_sram30_available; +reg main_sram31_storage = 1'd0; +reg main_sram32_re = 1'd0; +reg [10:0] main_sram35_length = 11'd0; +reg [10:0] main_sram35_length_liteethmacsramwriter_t_next_value = 11'd0; +reg main_sram35_length_liteethmacsramwriter_t_next_value_ce = 1'd0; +reg main_sram37_sink_valid = 1'd0; +wire main_sram38_sink_ready; +reg main_sram39_sink_first = 1'd0; +wire [8:0] main_sram3_adr; +reg main_sram3_adr_burst = 1'd0; +wire [31:0] main_sram3_dat_r; +wire [31:0] main_sram3_dat_w; +wire main_sram3_sink_last; +reg [3:0] main_sram3_we = 4'd0; +reg main_sram40_sink_last = 1'd0; +reg main_sram41_sink_payload_slot = 1'd0; +reg [10:0] main_sram42_sink_payload_length = 11'd0; +wire main_sram43_source_valid; +wire main_sram44_source_ready; +wire main_sram45_source_first; +wire main_sram46_source_last; +wire main_sram47_source_payload_slot; +wire [10:0] main_sram48_source_payload_length; +wire main_sram49_we; +wire [31:0] main_sram4_sink_payload_data; +wire main_sram50_writable; +wire main_sram51_re; +wire main_sram52_readable; +wire [13:0] main_sram53_din; +wire [13:0] main_sram54_dout; +reg [1:0] main_sram55_level = 2'd0; +reg main_sram56_replace = 1'd0; +reg main_sram57_produce = 1'd0; +reg main_sram58_consume = 1'd0; +reg main_sram59_adr = 1'd0; +wire [3:0] main_sram5_sink_payload_last_be; +wire [13:0] main_sram60_dat_r; +wire main_sram61_we; +wire [13:0] main_sram62_dat_w; +wire main_sram63_do_read; +wire main_sram64_adr; +wire [13:0] main_sram65_dat_r; +wire main_sram66_fifo_in_payload_slot; +wire [10:0] main_sram67_fifo_in_payload_length; +wire main_sram68_fifo_in_first; +wire main_sram69_fifo_in_last; +wire [3:0] main_sram6_sink_payload_error; +wire main_sram70_fifo_out_payload_slot; +wire [10:0] main_sram71_fifo_out_payload_length; +wire main_sram72_fifo_out_first; +wire main_sram73_fifo_out_last; +reg [8:0] main_sram75_adr = 9'd0; +wire [31:0] main_sram76_dat_r; +reg main_sram77_we = 1'd0; +reg [31:0] main_sram78_dat_w = 32'd0; +reg [8:0] main_sram79_adr = 9'd0; +wire main_sram7_status; +wire [31:0] main_sram80_dat_r; +reg main_sram81_we = 1'd0; +reg [31:0] main_sram82_dat_w = 32'd0; +reg main_sram83_source_valid = 1'd0; +wire main_sram84_source_ready; +reg main_sram85_source_first = 1'd0; +reg main_sram86_source_last = 1'd0; +wire [31:0] main_sram87_source_payload_data; +reg [3:0] main_sram88_source_payload_last_be = 4'd0; +reg [3:0] main_sram89_source_payload_error = 4'd0; +wire main_sram8_we; +wire main_sram94_status; +wire main_sram95_we; +reg main_sram96_re = 1'd0; +wire [1:0] main_sram97_status; +wire main_sram98_we; +reg main_sram99_re = 1'd0; +reg main_sram9_re = 1'd0; +wire main_start_r; +reg main_start_re = 1'd0; +reg main_start_w = 1'd0; +reg main_start_we = 1'd0; +reg main_status = 1'd1; +wire [41:0] main_tx_cdc_cdc_asyncfifo_din; +wire [41:0] main_tx_cdc_cdc_asyncfifo_dout; +wire main_tx_cdc_cdc_asyncfifo_re; +wire main_tx_cdc_cdc_asyncfifo_readable; +wire main_tx_cdc_cdc_asyncfifo_we; +wire main_tx_cdc_cdc_asyncfifo_writable; +wire [5:0] main_tx_cdc_cdc_consume_wdomain; +wire main_tx_cdc_cdc_fifo_in_first; +wire main_tx_cdc_cdc_fifo_in_last; +wire [31:0] main_tx_cdc_cdc_fifo_in_payload_data; +wire [3:0] main_tx_cdc_cdc_fifo_in_payload_error; +wire [3:0] main_tx_cdc_cdc_fifo_in_payload_last_be; +wire main_tx_cdc_cdc_fifo_out_first; +wire main_tx_cdc_cdc_fifo_out_last; +wire [31:0] main_tx_cdc_cdc_fifo_out_payload_data; +wire [3:0] main_tx_cdc_cdc_fifo_out_payload_error; +wire [3:0] main_tx_cdc_cdc_fifo_out_payload_last_be; +wire main_tx_cdc_cdc_graycounter0_ce; +(* dont_touch = "true" *) +reg [5:0] main_tx_cdc_cdc_graycounter0_q = 6'd0; +reg [5:0] main_tx_cdc_cdc_graycounter0_q_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_graycounter0_q_next; +reg [5:0] main_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire main_tx_cdc_cdc_graycounter1_ce; +(* dont_touch = "true" *) +reg [5:0] main_tx_cdc_cdc_graycounter1_q = 6'd0; +reg [5:0] main_tx_cdc_cdc_graycounter1_q_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_graycounter1_q_next; +reg [5:0] main_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_produce_rdomain; +wire [4:0] main_tx_cdc_cdc_rdport_adr; +wire [41:0] main_tx_cdc_cdc_rdport_dat_r; +wire main_tx_cdc_cdc_sink_first; +wire main_tx_cdc_cdc_sink_last; +wire [31:0] main_tx_cdc_cdc_sink_payload_data; +wire [3:0] main_tx_cdc_cdc_sink_payload_error; +wire [3:0] main_tx_cdc_cdc_sink_payload_last_be; +wire main_tx_cdc_cdc_sink_ready; +wire main_tx_cdc_cdc_sink_valid; +wire main_tx_cdc_cdc_source_first; +wire main_tx_cdc_cdc_source_last; +wire [31:0] main_tx_cdc_cdc_source_payload_data; +wire [3:0] main_tx_cdc_cdc_source_payload_error; +wire [3:0] main_tx_cdc_cdc_source_payload_last_be; +wire main_tx_cdc_cdc_source_ready; +wire main_tx_cdc_cdc_source_valid; +wire [4:0] main_tx_cdc_cdc_wrport_adr; +wire [41:0] main_tx_cdc_cdc_wrport_dat_r; +wire [41:0] main_tx_cdc_cdc_wrport_dat_w; +wire main_tx_cdc_cdc_wrport_we; +wire main_tx_cdc_sink_sink_first; +wire main_tx_cdc_sink_sink_last; +wire [31:0] main_tx_cdc_sink_sink_payload_data; +wire [3:0] main_tx_cdc_sink_sink_payload_error; +wire [3:0] main_tx_cdc_sink_sink_payload_last_be; +wire main_tx_cdc_sink_sink_ready; +wire main_tx_cdc_sink_sink_valid; +wire main_tx_cdc_source_source_first; +wire main_tx_cdc_source_source_last; +wire [31:0] main_tx_cdc_source_source_payload_data; +wire [3:0] main_tx_cdc_source_source_payload_error; +wire [3:0] main_tx_cdc_source_source_payload_last_be; +wire main_tx_cdc_source_source_ready; +wire main_tx_cdc_source_source_valid; +wire main_tx_converter_converter_first; +wire main_tx_converter_converter_last; +reg [1:0] main_tx_converter_converter_mux = 2'd0; +wire main_tx_converter_converter_sink_first; +wire main_tx_converter_converter_sink_last; +reg [39:0] main_tx_converter_converter_sink_payload_data = 40'd0; +wire main_tx_converter_converter_sink_ready; +wire main_tx_converter_converter_sink_valid; +wire main_tx_converter_converter_source_first; +wire main_tx_converter_converter_source_last; +reg [9:0] main_tx_converter_converter_source_payload_data = 10'd0; +wire main_tx_converter_converter_source_payload_valid_token_count; +wire main_tx_converter_converter_source_ready; +wire main_tx_converter_converter_source_valid; +wire main_tx_converter_sink_first; +wire main_tx_converter_sink_last; +wire [31:0] main_tx_converter_sink_payload_data; +wire [3:0] main_tx_converter_sink_payload_error; +wire [3:0] main_tx_converter_sink_payload_last_be; +wire main_tx_converter_sink_ready; +wire main_tx_converter_sink_valid; +wire main_tx_converter_source_first; +wire main_tx_converter_source_last; +wire [7:0] main_tx_converter_source_payload_data; +wire main_tx_converter_source_payload_error; +wire main_tx_converter_source_payload_last_be; +wire main_tx_converter_source_ready; +wire main_tx_converter_source_source_first; +wire main_tx_converter_source_source_last; +wire [9:0] main_tx_converter_source_source_payload_data; +wire main_tx_converter_source_source_ready; +wire main_tx_converter_source_source_valid; +wire main_tx_converter_source_valid; +wire main_tx_crc_be; +reg main_tx_crc_ce = 1'd0; +reg [1:0] main_tx_crc_cnt = 2'd3; +wire main_tx_crc_cnt_done; +reg [31:0] main_tx_crc_crc_next = 32'd0; +reg [31:0] main_tx_crc_crc_packet = 32'd0; +reg [31:0] main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 = 32'd0; +reg main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 = 1'd0; +wire [31:0] main_tx_crc_crc_prev; +wire [7:0] main_tx_crc_data0; +wire [7:0] main_tx_crc_data1; +reg main_tx_crc_error = 1'd0; +reg main_tx_crc_is_ongoing0 = 1'd0; +reg main_tx_crc_is_ongoing1 = 1'd0; +reg main_tx_crc_last_be = 1'd0; +reg main_tx_crc_last_be_clockdomainsrenamer1_next_value1 = 1'd0; +reg main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 = 1'd0; +wire main_tx_crc_pipe_valid_sink_first; +wire main_tx_crc_pipe_valid_sink_last; +wire [7:0] main_tx_crc_pipe_valid_sink_payload_data; +wire main_tx_crc_pipe_valid_sink_payload_error; +wire main_tx_crc_pipe_valid_sink_payload_last_be; +wire main_tx_crc_pipe_valid_sink_ready; +wire main_tx_crc_pipe_valid_sink_valid; +reg main_tx_crc_pipe_valid_source_first = 1'd0; +reg main_tx_crc_pipe_valid_source_last = 1'd0; +reg [7:0] main_tx_crc_pipe_valid_source_payload_data = 8'd0; +reg main_tx_crc_pipe_valid_source_payload_error = 1'd0; +reg main_tx_crc_pipe_valid_source_payload_last_be = 1'd0; +wire main_tx_crc_pipe_valid_source_ready; +reg main_tx_crc_pipe_valid_source_valid = 1'd0; +reg [31:0] main_tx_crc_reg = 32'd4294967295; +reg main_tx_crc_reset = 1'd0; +wire main_tx_crc_sink_first; +wire main_tx_crc_sink_last; +wire [7:0] main_tx_crc_sink_payload_data; +wire main_tx_crc_sink_payload_error; +wire main_tx_crc_sink_payload_last_be; +reg main_tx_crc_sink_ready = 1'd0; +wire main_tx_crc_sink_sink_first; +wire main_tx_crc_sink_sink_last; +wire [7:0] main_tx_crc_sink_sink_payload_data; +wire main_tx_crc_sink_sink_payload_error; +wire main_tx_crc_sink_sink_payload_last_be; +wire main_tx_crc_sink_sink_ready; +wire main_tx_crc_sink_sink_valid; +wire main_tx_crc_sink_valid; +reg main_tx_crc_source_first = 1'd0; +reg main_tx_crc_source_last = 1'd0; +reg [7:0] main_tx_crc_source_payload_data = 8'd0; +reg main_tx_crc_source_payload_error = 1'd0; +reg main_tx_crc_source_payload_last_be = 1'd0; +wire main_tx_crc_source_ready; +wire main_tx_crc_source_source_first; +wire main_tx_crc_source_source_last; +wire [7:0] main_tx_crc_source_source_payload_data; +wire main_tx_crc_source_source_payload_error; +wire main_tx_crc_source_source_payload_last_be; +wire main_tx_crc_source_source_ready; +wire main_tx_crc_source_source_valid; +reg main_tx_crc_source_valid = 1'd0; +reg [31:0] main_tx_crc_value = 32'd0; +reg [3:0] main_tx_gap_counter = 4'd0; +reg [3:0] main_tx_gap_counter_clockdomainsrenamer3_next_value = 4'd0; +reg main_tx_gap_counter_clockdomainsrenamer3_next_value_ce = 1'd0; +wire main_tx_gap_sink_first; +wire main_tx_gap_sink_last; +wire [7:0] main_tx_gap_sink_payload_data; +wire main_tx_gap_sink_payload_error; +wire main_tx_gap_sink_payload_last_be; +reg main_tx_gap_sink_ready = 1'd0; +wire main_tx_gap_sink_valid; +reg main_tx_gap_source_first = 1'd0; +reg main_tx_gap_source_last = 1'd0; +reg [7:0] main_tx_gap_source_payload_data = 8'd0; +reg main_tx_gap_source_payload_error = 1'd0; +reg main_tx_gap_source_payload_last_be = 1'd0; +wire main_tx_gap_source_ready; +reg main_tx_gap_source_valid = 1'd0; +wire main_tx_last_be_sink_first; +wire main_tx_last_be_sink_last; +wire [7:0] main_tx_last_be_sink_payload_data; +wire main_tx_last_be_sink_payload_error; +wire main_tx_last_be_sink_payload_last_be; +reg main_tx_last_be_sink_ready = 1'd0; +wire main_tx_last_be_sink_valid; +reg main_tx_last_be_source_first = 1'd0; +reg main_tx_last_be_source_last = 1'd0; +reg [7:0] main_tx_last_be_source_payload_data = 8'd0; +reg main_tx_last_be_source_payload_error = 1'd0; +reg main_tx_last_be_source_payload_last_be = 1'd0; +wire main_tx_last_be_source_ready; +reg main_tx_last_be_source_valid = 1'd0; +reg [15:0] main_tx_padding_counter = 16'd0; +reg [15:0] main_tx_padding_counter_clockdomainsrenamer0_next_value = 16'd0; +reg main_tx_padding_counter_clockdomainsrenamer0_next_value_ce = 1'd0; +wire main_tx_padding_counter_done; +wire main_tx_padding_sink_first; +wire main_tx_padding_sink_last; +wire [7:0] main_tx_padding_sink_payload_data; +wire main_tx_padding_sink_payload_error; +wire main_tx_padding_sink_payload_last_be; +reg main_tx_padding_sink_ready = 1'd0; +wire main_tx_padding_sink_valid; +reg main_tx_padding_source_first = 1'd0; +reg main_tx_padding_source_last = 1'd0; +reg [7:0] main_tx_padding_source_payload_data = 8'd0; +reg main_tx_padding_source_payload_error = 1'd0; +reg main_tx_padding_source_payload_last_be = 1'd0; +wire main_tx_padding_source_ready; +reg main_tx_padding_source_valid = 1'd0; +reg [2:0] main_tx_preamble_count = 3'd0; +reg [2:0] main_tx_preamble_count_clockdomainsrenamer2_next_value = 3'd0; +reg main_tx_preamble_count_clockdomainsrenamer2_next_value_ce = 1'd0; +reg [63:0] main_tx_preamble_preamble = 64'd15372286728091293013; +wire main_tx_preamble_sink_first; +wire main_tx_preamble_sink_last; +wire [7:0] main_tx_preamble_sink_payload_data; +wire main_tx_preamble_sink_payload_error; +wire main_tx_preamble_sink_payload_last_be; +reg main_tx_preamble_sink_ready = 1'd0; +wire main_tx_preamble_sink_valid; +reg main_tx_preamble_source_first = 1'd0; +reg main_tx_preamble_source_last = 1'd0; +reg [7:0] main_tx_preamble_source_payload_data = 8'd0; +reg main_tx_preamble_source_payload_error = 1'd0; +wire main_tx_preamble_source_payload_last_be; +wire main_tx_preamble_source_ready; +reg main_tx_preamble_source_valid = 1'd0; +wire main_wb_bus_ack; +wire [29:0] main_wb_bus_adr; +wire [1:0] main_wb_bus_bte; +wire [2:0] main_wb_bus_cti; +wire main_wb_bus_cyc; +wire [31:0] main_wb_bus_dat_r; +wire [31:0] main_wb_bus_dat_w; +wire main_wb_bus_err; +wire [3:0] main_wb_bus_sel; +wire main_wb_bus_stb; +wire main_wb_bus_we; +wire main_we; +wire [31:0] main_wr_data; +reg main_write = 1'd0; +wire por_clk; +(* dont_touch = "true" *) +wire sys_clk; +wire sys_rst; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + +assign main_wb_bus_adr = wishbone_adr; +assign main_wb_bus_dat_w = wishbone_dat_w; +assign wishbone_dat_r = main_wb_bus_dat_r; +assign main_wb_bus_sel = wishbone_sel; +assign main_wb_bus_cyc = wishbone_cyc; +assign main_wb_bus_stb = wishbone_stb; +assign wishbone_ack = main_wb_bus_ack; +assign main_wb_bus_we = wishbone_we; +assign main_wb_bus_cti = wishbone_cti; +assign main_wb_bus_bte = wishbone_bte; +assign wishbone_err = main_wb_bus_err; +assign interrupt = main_sram167_irq; +assign main_maccore_maccore_bus_error = builder_error; +assign builder_shared_adr = builder_self0; +assign builder_shared_dat_w = builder_self1; +assign builder_shared_sel = builder_self2; +assign builder_shared_cyc = builder_self3; +assign builder_shared_stb = builder_self4; +assign builder_shared_we = builder_self5; +assign builder_shared_cti = builder_self6; +assign builder_shared_bte = builder_self7; +assign main_wb_bus_dat_r = builder_shared_dat_r; +assign main_wb_bus_ack = (builder_shared_ack & (builder_grant == 1'd0)); +assign main_wb_bus_err = (builder_shared_err & (builder_grant == 1'd0)); +assign builder_request = {main_wb_bus_cyc}; +assign builder_grant = 1'd0; +always @(*) begin + builder_slave_sel <= 2'd0; + builder_slave_sel[0] <= (builder_shared_adr[29:11] == 4'd8); + builder_slave_sel[1] <= (builder_shared_adr[29:14] == 1'd0); +end +assign main_bus_adr = builder_shared_adr; +assign main_bus_dat_w = builder_shared_dat_w; +assign main_bus_sel = builder_shared_sel; +assign main_bus_stb = builder_shared_stb; +assign main_bus_we = builder_shared_we; +assign main_bus_cti = builder_shared_cti; +assign main_bus_bte = builder_shared_bte; +assign builder_interface0_adr = builder_shared_adr; +assign builder_interface0_dat_w = builder_shared_dat_w; +assign builder_interface0_sel = builder_shared_sel; +assign builder_interface0_stb = builder_shared_stb; +assign builder_interface0_we = builder_shared_we; +assign builder_interface0_cti = builder_shared_cti; +assign builder_interface0_bte = builder_shared_bte; +assign main_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]); +assign builder_interface0_cyc = (builder_shared_cyc & builder_slave_sel[1]); +assign builder_shared_err = (main_bus_err | builder_interface0_err); +assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack)); +always @(*) begin + builder_error <= 1'd0; + builder_shared_ack <= 1'd0; + builder_shared_dat_r <= 32'd0; + builder_shared_ack <= (main_bus_ack | builder_interface0_ack); + builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & builder_interface0_dat_r)); + if (builder_done) begin + builder_shared_dat_r <= 32'd4294967295; + builder_shared_ack <= 1'd1; + builder_error <= 1'd1; + end +end +assign builder_done = (builder_count == 1'd0); +assign main_maccore_maccore_bus_errors_status = main_maccore_maccore_bus_errors; assign sys_clk = sys_clock; assign por_clk = sys_clock; -assign sys_rst = maccore_int_rst; -assign maccore_ethphy_mode_status = maccore_ethphy_mode0; -assign maccore_ethphy_eth_tick = (maccore_ethphy_eth_counter == 1'd0); -assign maccore_ethphy_i = maccore_ethphy_eth_tick; -assign maccore_ethphy_sys_tick = maccore_ethphy_o; -assign maccore_ethphy_o = (maccore_ethphy_toggle_o ^ maccore_ethphy_toggle_o_r); -always @(*) begin - subfragments_next_state <= 2'd0; - maccore_ethphy_sys_counter_reset <= 1'd0; - maccore_ethphy_sys_counter_ce <= 1'd0; - maccore_ethphy_mode1 <= 1'd0; - maccore_ethphy_update_mode <= 1'd0; - subfragments_next_state <= subfragments_state; - case (subfragments_state) - 1'd1: begin - maccore_ethphy_sys_counter_ce <= 1'd1; - if (maccore_ethphy_sys_tick) begin - subfragments_next_state <= 2'd2; - end - end - 2'd2: begin - maccore_ethphy_update_mode <= 1'd1; - if ((maccore_ethphy_sys_counter > 10'd860)) begin - maccore_ethphy_mode1 <= 1'd1; - end else begin - maccore_ethphy_mode1 <= 1'd0; - end - subfragments_next_state <= 1'd0; - end - default: begin - maccore_ethphy_sys_counter_reset <= 1'd1; - if (maccore_ethphy_sys_tick) begin - subfragments_next_state <= 1'd1; - end - end - endcase -end -always @(*) begin - maccore_ethphy_eth_tx_clk <= 1'd0; - if ((maccore_ethphy_mode0 == 1'd1)) begin - maccore_ethphy_eth_tx_clk <= gmii_eth_clocks_tx; - end else begin - maccore_ethphy_eth_tx_clk <= gmii_eth_clocks_rx; - end -end -assign maccore_ethphy_reset0 = (maccore_ethphy_reset_storage | maccore_ethphy_reset1); -assign gmii_eth_rst_n = (~maccore_ethphy_reset0); -assign maccore_ethphy_counter_done = (maccore_ethphy_counter == 9'd256); -assign maccore_ethphy_counter_ce = (~maccore_ethphy_counter_done); -assign maccore_ethphy_reset1 = (~maccore_ethphy_counter_done); -assign maccore_ethphy_liteethphygmiimiitx_demux_sel = (maccore_ethphy_mode0 == 1'd1); -assign maccore_ethphy_liteethphygmiimiitx_demux_sink_valid = maccore_ethphy_liteethphygmiimiitx_sink_sink_valid0; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_ready0 = maccore_ethphy_liteethphygmiimiitx_demux_sink_ready; -assign maccore_ethphy_liteethphygmiimiitx_demux_sink_first = maccore_ethphy_liteethphygmiimiitx_sink_sink_first0; -assign maccore_ethphy_liteethphygmiimiitx_demux_sink_last = maccore_ethphy_liteethphygmiimiitx_sink_sink_last0; -assign maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_data = maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_data0; -assign maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_last_be = maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_last_be0; -assign maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_error = maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_error0; -assign maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_valid = maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_valid; -assign maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_ready = maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_ready; -assign maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_first = maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_first; -assign maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_last = maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_last; -assign maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_data = maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_data; -assign maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_last_be = maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_last_be; -assign maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_error = maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_error; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_valid1 = maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_valid; -assign maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_ready = maccore_ethphy_liteethphygmiimiitx_sink_sink_ready1; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_first1 = maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_first; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_last1 = maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_last; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_data1 = maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_data; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_last_be1 = maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_last_be; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_error1 = maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_error; -assign gmii_eth_tx_er = 1'd0; -assign maccore_ethphy_liteethphygmiimiitx_converter_sink_valid = maccore_ethphy_liteethphygmiimiitx_sink_sink_valid1; -assign maccore_ethphy_liteethphygmiimiitx_converter_sink_payload_data = maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_data1; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_ready1 = maccore_ethphy_liteethphygmiimiitx_converter_sink_ready; -assign maccore_ethphy_liteethphygmiimiitx_converter_source_ready = 1'd1; -assign maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_valid = maccore_ethphy_liteethphygmiimiitx_converter_sink_valid; -assign maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_first = maccore_ethphy_liteethphygmiimiitx_converter_sink_first; -assign maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_last = maccore_ethphy_liteethphygmiimiitx_converter_sink_last; -assign maccore_ethphy_liteethphygmiimiitx_converter_sink_ready = maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_ready; -always @(*) begin - maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_payload_data <= 8'd0; - maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_payload_data[3:0] <= maccore_ethphy_liteethphygmiimiitx_converter_sink_payload_data[3:0]; - maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_payload_data[7:4] <= maccore_ethphy_liteethphygmiimiitx_converter_sink_payload_data[7:4]; -end -assign maccore_ethphy_liteethphygmiimiitx_converter_source_valid = maccore_ethphy_liteethphygmiimiitx_converter_source_source_valid; -assign maccore_ethphy_liteethphygmiimiitx_converter_source_first = maccore_ethphy_liteethphygmiimiitx_converter_source_source_first; -assign maccore_ethphy_liteethphygmiimiitx_converter_source_last = maccore_ethphy_liteethphygmiimiitx_converter_source_source_last; -assign maccore_ethphy_liteethphygmiimiitx_converter_source_source_ready = maccore_ethphy_liteethphygmiimiitx_converter_source_ready; -assign {maccore_ethphy_liteethphygmiimiitx_converter_source_payload_data} = maccore_ethphy_liteethphygmiimiitx_converter_source_source_payload_data; -assign maccore_ethphy_liteethphygmiimiitx_converter_source_source_valid = maccore_ethphy_liteethphygmiimiitx_converter_converter_source_valid; -assign maccore_ethphy_liteethphygmiimiitx_converter_converter_source_ready = maccore_ethphy_liteethphygmiimiitx_converter_source_source_ready; -assign maccore_ethphy_liteethphygmiimiitx_converter_source_source_first = maccore_ethphy_liteethphygmiimiitx_converter_converter_source_first; -assign maccore_ethphy_liteethphygmiimiitx_converter_source_source_last = maccore_ethphy_liteethphygmiimiitx_converter_converter_source_last; -assign maccore_ethphy_liteethphygmiimiitx_converter_source_source_payload_data = maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_data; -assign maccore_ethphy_liteethphygmiimiitx_converter_converter_first = (maccore_ethphy_liteethphygmiimiitx_converter_converter_mux == 1'd0); -assign maccore_ethphy_liteethphygmiimiitx_converter_converter_last = (maccore_ethphy_liteethphygmiimiitx_converter_converter_mux == 1'd1); -assign maccore_ethphy_liteethphygmiimiitx_converter_converter_source_valid = maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_valid; -assign maccore_ethphy_liteethphygmiimiitx_converter_converter_source_first = (maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_first & maccore_ethphy_liteethphygmiimiitx_converter_converter_first); -assign maccore_ethphy_liteethphygmiimiitx_converter_converter_source_last = (maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_last & maccore_ethphy_liteethphygmiimiitx_converter_converter_last); -assign maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_ready = (maccore_ethphy_liteethphygmiimiitx_converter_converter_last & maccore_ethphy_liteethphygmiimiitx_converter_converter_source_ready); -always @(*) begin - maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_data <= 4'd0; - case (maccore_ethphy_liteethphygmiimiitx_converter_converter_mux) - 1'd0: begin - maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_data <= maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_payload_data[3:0]; - end - default: begin - maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_data <= maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_payload_data[7:4]; - end - endcase -end -assign maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_valid_token_count = maccore_ethphy_liteethphygmiimiitx_converter_converter_last; -always @(*) begin - maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_data <= 8'd0; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_last <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_last_be <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_error <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_valid <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_first <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_last <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_data <= 8'd0; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_last_be <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_error <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_valid <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_first <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_demux_sink_ready <= 1'd0; - case (maccore_ethphy_liteethphygmiimiitx_demux_sel) - 1'd0: begin - maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_valid <= maccore_ethphy_liteethphygmiimiitx_demux_sink_valid; - maccore_ethphy_liteethphygmiimiitx_demux_sink_ready <= maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_ready; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_first <= maccore_ethphy_liteethphygmiimiitx_demux_sink_first; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_last <= maccore_ethphy_liteethphygmiimiitx_demux_sink_last; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_data <= maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_data; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_last_be <= maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_last_be; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_error <= maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_error; - end - 1'd1: begin - maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_valid <= maccore_ethphy_liteethphygmiimiitx_demux_sink_valid; - maccore_ethphy_liteethphygmiimiitx_demux_sink_ready <= maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_ready; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_first <= maccore_ethphy_liteethphygmiimiitx_demux_sink_first; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_last <= maccore_ethphy_liteethphygmiimiitx_demux_sink_last; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_data <= maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_data; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_last_be <= maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_last_be; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_error <= maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_error; - end - endcase -end -assign maccore_ethphy_liteethphygmiimiirx_mux_sel = (maccore_ethphy_mode0 == 1'd1); -assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_valid = maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_valid; -assign maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_ready = maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_ready; -assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_first = maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_first; -assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_last = maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_last; -assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_data = maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_data; -assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_last_be = maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_last_be; -assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_error = maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_error; -assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_valid = maccore_ethphy_liteethphygmiimiirx_source_source_valid1; -assign maccore_ethphy_liteethphygmiimiirx_source_source_ready1 = maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_ready; -assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_first = maccore_ethphy_liteethphygmiimiirx_source_source_first1; -assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_last = maccore_ethphy_liteethphygmiimiirx_source_source_last1; -assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_data = maccore_ethphy_liteethphygmiimiirx_source_source_payload_data1; -assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_last_be = maccore_ethphy_liteethphygmiimiirx_source_source_payload_last_be1; -assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_error = maccore_ethphy_liteethphygmiimiirx_source_source_payload_error1; -assign maccore_ethphy_liteethphygmiimiirx_source_source_valid0 = maccore_ethphy_liteethphygmiimiirx_mux_source_valid; -assign maccore_ethphy_liteethphygmiimiirx_mux_source_ready = maccore_ethphy_liteethphygmiimiirx_source_source_ready0; -assign maccore_ethphy_liteethphygmiimiirx_source_source_first0 = maccore_ethphy_liteethphygmiimiirx_mux_source_first; -assign maccore_ethphy_liteethphygmiimiirx_source_source_last0 = maccore_ethphy_liteethphygmiimiirx_mux_source_last; -assign maccore_ethphy_liteethphygmiimiirx_source_source_payload_data0 = maccore_ethphy_liteethphygmiimiirx_mux_source_payload_data; -assign maccore_ethphy_liteethphygmiimiirx_source_source_payload_last_be0 = maccore_ethphy_liteethphygmiimiirx_mux_source_payload_last_be; -assign maccore_ethphy_liteethphygmiimiirx_source_source_payload_error0 = maccore_ethphy_liteethphygmiimiirx_mux_source_payload_error; -assign maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_last = ((~maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv) & maccore_ethphy_liteethphygmiimiirx_gmii_rx_dv_d); -assign maccore_ethphy_liteethphygmiimiirx_converter_sink_last = (~maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv); -assign maccore_ethphy_liteethphygmiimiirx_source_source_valid1 = maccore_ethphy_liteethphygmiimiirx_converter_source_valid; -assign maccore_ethphy_liteethphygmiimiirx_converter_source_ready = maccore_ethphy_liteethphygmiimiirx_source_source_ready1; -assign maccore_ethphy_liteethphygmiimiirx_source_source_first1 = maccore_ethphy_liteethphygmiimiirx_converter_source_first; -assign maccore_ethphy_liteethphygmiimiirx_source_source_last1 = maccore_ethphy_liteethphygmiimiirx_converter_source_last; -assign maccore_ethphy_liteethphygmiimiirx_source_source_payload_data1 = maccore_ethphy_liteethphygmiimiirx_converter_source_payload_data; -assign maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_valid = maccore_ethphy_liteethphygmiimiirx_converter_sink_valid; -assign maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_first = maccore_ethphy_liteethphygmiimiirx_converter_sink_first; -assign maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_last = maccore_ethphy_liteethphygmiimiirx_converter_sink_last; -assign maccore_ethphy_liteethphygmiimiirx_converter_sink_ready = maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_ready; -assign maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_payload_data = {maccore_ethphy_liteethphygmiimiirx_converter_sink_payload_data}; -assign maccore_ethphy_liteethphygmiimiirx_converter_source_valid = maccore_ethphy_liteethphygmiimiirx_converter_source_source_valid; -assign maccore_ethphy_liteethphygmiimiirx_converter_source_first = maccore_ethphy_liteethphygmiimiirx_converter_source_source_first; -assign maccore_ethphy_liteethphygmiimiirx_converter_source_last = maccore_ethphy_liteethphygmiimiirx_converter_source_source_last; -assign maccore_ethphy_liteethphygmiimiirx_converter_source_source_ready = maccore_ethphy_liteethphygmiimiirx_converter_source_ready; -always @(*) begin - maccore_ethphy_liteethphygmiimiirx_converter_source_payload_data <= 8'd0; - maccore_ethphy_liteethphygmiimiirx_converter_source_payload_data[3:0] <= maccore_ethphy_liteethphygmiimiirx_converter_source_source_payload_data[3:0]; - maccore_ethphy_liteethphygmiimiirx_converter_source_payload_data[7:4] <= maccore_ethphy_liteethphygmiimiirx_converter_source_source_payload_data[7:4]; -end -assign maccore_ethphy_liteethphygmiimiirx_converter_source_source_valid = maccore_ethphy_liteethphygmiimiirx_converter_converter_source_valid; -assign maccore_ethphy_liteethphygmiimiirx_converter_converter_source_ready = maccore_ethphy_liteethphygmiimiirx_converter_source_source_ready; -assign maccore_ethphy_liteethphygmiimiirx_converter_source_source_first = maccore_ethphy_liteethphygmiimiirx_converter_converter_source_first; -assign maccore_ethphy_liteethphygmiimiirx_converter_source_source_last = maccore_ethphy_liteethphygmiimiirx_converter_converter_source_last; -assign maccore_ethphy_liteethphygmiimiirx_converter_source_source_payload_data = maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_data; -assign maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_ready = ((~maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all) | maccore_ethphy_liteethphygmiimiirx_converter_converter_source_ready); -assign maccore_ethphy_liteethphygmiimiirx_converter_converter_source_valid = maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all; -assign maccore_ethphy_liteethphygmiimiirx_converter_converter_load_part = (maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_valid & maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_ready); -always @(*) begin - maccore_ethphy_liteethphygmiimiirx_mux_source_valid <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_mux_source_first <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_mux_source_last <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_mux_source_payload_data <= 8'd0; - maccore_ethphy_liteethphygmiimiirx_mux_source_payload_last_be <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_mux_source_payload_error <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_ready <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_ready <= 1'd0; - case (maccore_ethphy_liteethphygmiimiirx_mux_sel) - 1'd0: begin - maccore_ethphy_liteethphygmiimiirx_mux_source_valid <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_valid; - maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_ready <= maccore_ethphy_liteethphygmiimiirx_mux_source_ready; - maccore_ethphy_liteethphygmiimiirx_mux_source_first <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_first; - maccore_ethphy_liteethphygmiimiirx_mux_source_last <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_last; - maccore_ethphy_liteethphygmiimiirx_mux_source_payload_data <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_data; - maccore_ethphy_liteethphygmiimiirx_mux_source_payload_last_be <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_last_be; - maccore_ethphy_liteethphygmiimiirx_mux_source_payload_error <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_error; - end - 1'd1: begin - maccore_ethphy_liteethphygmiimiirx_mux_source_valid <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_valid; - maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_ready <= maccore_ethphy_liteethphygmiimiirx_mux_source_ready; - maccore_ethphy_liteethphygmiimiirx_mux_source_first <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_first; - maccore_ethphy_liteethphygmiimiirx_mux_source_last <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_last; - maccore_ethphy_liteethphygmiimiirx_mux_source_payload_data <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_data; - maccore_ethphy_liteethphygmiimiirx_mux_source_payload_last_be <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_last_be; - maccore_ethphy_liteethphygmiimiirx_mux_source_payload_error <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_error; - end - endcase -end -assign gmii_eth_mdc = maccore_ethphy__w_storage[0]; -assign maccore_ethphy_data_oe = maccore_ethphy__w_storage[1]; -assign maccore_ethphy_data_w = maccore_ethphy__w_storage[2]; -assign tx_cdc_sink_sink_valid = source_valid; -assign source_ready = tx_cdc_sink_sink_ready; -assign tx_cdc_sink_sink_first = source_first; -assign tx_cdc_sink_sink_last = source_last; -assign tx_cdc_sink_sink_payload_data = source_payload_data; -assign tx_cdc_sink_sink_payload_last_be = source_payload_last_be; -assign tx_cdc_sink_sink_payload_error = source_payload_error; -assign sink_valid = rx_cdc_source_source_valid; -assign rx_cdc_source_source_ready = sink_ready; -assign sink_first = rx_cdc_source_source_first; -assign sink_last = rx_cdc_source_source_last; -assign sink_payload_data = rx_cdc_source_source_payload_data; -assign sink_payload_last_be = rx_cdc_source_source_payload_last_be; -assign sink_payload_error = rx_cdc_source_source_payload_error; -assign ps_preamble_error_i = preamble_checker_error; -assign ps_crc_error_i = liteethmaccrc32checker_error; -always @(*) begin - tx_gap_inserter_source_valid <= 1'd0; - tx_gap_inserter_source_first <= 1'd0; - tx_gap_inserter_source_last <= 1'd0; - tx_gap_inserter_source_payload_data <= 8'd0; - tx_gap_inserter_source_payload_last_be <= 1'd0; - tx_gap_inserter_source_payload_error <= 1'd0; - subfragments_liteethmacgap_next_state <= 1'd0; - tx_gap_inserter_counter_liteethmacgap_next_value <= 4'd0; - tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd0; - tx_gap_inserter_sink_ready <= 1'd0; - subfragments_liteethmacgap_next_state <= subfragments_liteethmacgap_state; - case (subfragments_liteethmacgap_state) - 1'd1: begin - tx_gap_inserter_counter_liteethmacgap_next_value <= (tx_gap_inserter_counter + 1'd1); - tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1; - if ((tx_gap_inserter_counter == 4'd11)) begin - subfragments_liteethmacgap_next_state <= 1'd0; - end - end - default: begin - tx_gap_inserter_counter_liteethmacgap_next_value <= 1'd0; - tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1; - tx_gap_inserter_source_valid <= tx_gap_inserter_sink_valid; - tx_gap_inserter_sink_ready <= tx_gap_inserter_source_ready; - tx_gap_inserter_source_first <= tx_gap_inserter_sink_first; - tx_gap_inserter_source_last <= tx_gap_inserter_sink_last; - tx_gap_inserter_source_payload_data <= tx_gap_inserter_sink_payload_data; - tx_gap_inserter_source_payload_last_be <= tx_gap_inserter_sink_payload_last_be; - tx_gap_inserter_source_payload_error <= tx_gap_inserter_sink_payload_error; - if (((tx_gap_inserter_sink_valid & tx_gap_inserter_sink_last) & tx_gap_inserter_sink_ready)) begin - subfragments_liteethmacgap_next_state <= 1'd1; - end - end - endcase -end -assign preamble_inserter_source_payload_last_be = preamble_inserter_sink_payload_last_be; -always @(*) begin - preamble_inserter_source_first <= 1'd0; - preamble_inserter_source_last <= 1'd0; - preamble_inserter_source_payload_data <= 8'd0; - subfragments_liteethmacpreambleinserter_next_state <= 2'd0; - preamble_inserter_source_payload_error <= 1'd0; - preamble_inserter_count_liteethmacpreambleinserter_next_value <= 3'd0; - preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd0; - preamble_inserter_sink_ready <= 1'd0; - preamble_inserter_source_valid <= 1'd0; - preamble_inserter_source_payload_data <= preamble_inserter_sink_payload_data; - subfragments_liteethmacpreambleinserter_next_state <= subfragments_liteethmacpreambleinserter_state; - case (subfragments_liteethmacpreambleinserter_state) - 1'd1: begin - preamble_inserter_source_valid <= 1'd1; - case (preamble_inserter_count) - 1'd0: begin - preamble_inserter_source_payload_data <= preamble_inserter_preamble[7:0]; - end - 1'd1: begin - preamble_inserter_source_payload_data <= preamble_inserter_preamble[15:8]; - end - 2'd2: begin - preamble_inserter_source_payload_data <= preamble_inserter_preamble[23:16]; - end - 2'd3: begin - preamble_inserter_source_payload_data <= preamble_inserter_preamble[31:24]; - end - 3'd4: begin - preamble_inserter_source_payload_data <= preamble_inserter_preamble[39:32]; - end - 3'd5: begin - preamble_inserter_source_payload_data <= preamble_inserter_preamble[47:40]; - end - 3'd6: begin - preamble_inserter_source_payload_data <= preamble_inserter_preamble[55:48]; - end - default: begin - preamble_inserter_source_payload_data <= preamble_inserter_preamble[63:56]; - end - endcase - if (preamble_inserter_source_ready) begin - if ((preamble_inserter_count == 3'd7)) begin - subfragments_liteethmacpreambleinserter_next_state <= 2'd2; - end else begin - preamble_inserter_count_liteethmacpreambleinserter_next_value <= (preamble_inserter_count + 1'd1); - preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1; - end - end - end - 2'd2: begin - preamble_inserter_source_valid <= preamble_inserter_sink_valid; - preamble_inserter_sink_ready <= preamble_inserter_source_ready; - preamble_inserter_source_first <= preamble_inserter_sink_first; - preamble_inserter_source_last <= preamble_inserter_sink_last; - preamble_inserter_source_payload_error <= preamble_inserter_sink_payload_error; - if (((preamble_inserter_sink_valid & preamble_inserter_sink_last) & preamble_inserter_source_ready)) begin - subfragments_liteethmacpreambleinserter_next_state <= 1'd0; - end - end - default: begin - preamble_inserter_sink_ready <= 1'd1; - preamble_inserter_count_liteethmacpreambleinserter_next_value <= 1'd0; - preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1; - if (preamble_inserter_sink_valid) begin - preamble_inserter_sink_ready <= 1'd0; - subfragments_liteethmacpreambleinserter_next_state <= 1'd1; - end - end - endcase -end -assign preamble_checker_source_payload_data = preamble_checker_sink_payload_data; -assign preamble_checker_source_payload_last_be = preamble_checker_sink_payload_last_be; -always @(*) begin - preamble_checker_source_payload_error <= 1'd0; - preamble_checker_error <= 1'd0; - preamble_checker_source_first <= 1'd0; - preamble_checker_source_valid <= 1'd0; - subfragments_liteethmacpreamblechecker_next_state <= 1'd0; - preamble_checker_sink_ready <= 1'd0; - preamble_checker_source_last <= 1'd0; - subfragments_liteethmacpreamblechecker_next_state <= subfragments_liteethmacpreamblechecker_state; - case (subfragments_liteethmacpreamblechecker_state) - 1'd1: begin - preamble_checker_source_valid <= preamble_checker_sink_valid; - preamble_checker_sink_ready <= preamble_checker_source_ready; - preamble_checker_source_first <= preamble_checker_sink_first; - preamble_checker_source_last <= preamble_checker_sink_last; - preamble_checker_source_payload_error <= preamble_checker_sink_payload_error; - if (((preamble_checker_source_valid & preamble_checker_source_last) & preamble_checker_source_ready)) begin - subfragments_liteethmacpreamblechecker_next_state <= 1'd0; - end - end - default: begin - preamble_checker_sink_ready <= 1'd1; - if (((preamble_checker_sink_valid & (~preamble_checker_sink_last)) & (preamble_checker_sink_payload_data == 8'd213))) begin - subfragments_liteethmacpreamblechecker_next_state <= 1'd1; - end - if ((preamble_checker_sink_valid & preamble_checker_sink_last)) begin - preamble_checker_error <= 1'd1; - end - end - endcase -end -assign liteethmaccrc32inserter_cnt_done = (liteethmaccrc32inserter_cnt == 1'd0); -assign liteethmaccrc32inserter_sink_valid = crc32_inserter_source_valid; -assign crc32_inserter_source_ready = liteethmaccrc32inserter_sink_ready; -assign liteethmaccrc32inserter_sink_first = crc32_inserter_source_first; -assign liteethmaccrc32inserter_sink_last = crc32_inserter_source_last; -assign liteethmaccrc32inserter_sink_payload_data = crc32_inserter_source_payload_data; -assign liteethmaccrc32inserter_sink_payload_last_be = crc32_inserter_source_payload_last_be; -assign liteethmaccrc32inserter_sink_payload_error = crc32_inserter_source_payload_error; -assign liteethmaccrc32inserter_data1 = liteethmaccrc32inserter_data0; -assign liteethmaccrc32inserter_last = liteethmaccrc32inserter_reg; -assign liteethmaccrc32inserter_value = (~{liteethmaccrc32inserter_reg[0], liteethmaccrc32inserter_reg[1], liteethmaccrc32inserter_reg[2], liteethmaccrc32inserter_reg[3], liteethmaccrc32inserter_reg[4], liteethmaccrc32inserter_reg[5], liteethmaccrc32inserter_reg[6], liteethmaccrc32inserter_reg[7], liteethmaccrc32inserter_reg[8], liteethmaccrc32inserter_reg[9], liteethmaccrc32inserter_reg[10], liteethmaccrc32inserter_reg[11], liteethmaccrc32inserter_reg[12], liteethmaccrc32inserter_reg[13], liteethmaccrc32inserter_reg[14], liteethmaccrc32inserter_reg[15], liteethmaccrc32inserter_reg[16], liteethmaccrc32inserter_reg[17], liteethmaccrc32inserter_reg[18], liteethmaccrc32inserter_reg[19], liteethmaccrc32inserter_reg[20], liteethmaccrc32inserter_reg[21], liteethmaccrc32inserter_reg[22], liteethmaccrc32inserter_reg[23], liteethmaccrc32inserter_reg[24], liteethmaccrc32inserter_reg[25], liteethmaccrc32inserter_reg[26], liteethmaccrc32inserter_reg[27], liteethmaccrc32inserter_reg[28], liteethmaccrc32inserter_reg[29], liteethmaccrc32inserter_reg[30], liteethmaccrc32inserter_reg[31]}); -assign liteethmaccrc32inserter_error = (liteethmaccrc32inserter_next != 32'd3338984827); -always @(*) begin - liteethmaccrc32inserter_next <= 32'd0; - liteethmaccrc32inserter_next[0] <= (((liteethmaccrc32inserter_last[24] ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[1] <= (((((((liteethmaccrc32inserter_last[25] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[2] <= (((((((((liteethmaccrc32inserter_last[26] ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[3] <= (((((((liteethmaccrc32inserter_last[27] ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]); - liteethmaccrc32inserter_next[4] <= (((((((((liteethmaccrc32inserter_last[28] ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[5] <= (((((((((((((liteethmaccrc32inserter_last[29] ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[6] <= (((((((((((liteethmaccrc32inserter_last[30] ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]); - liteethmaccrc32inserter_next[7] <= (((((((((liteethmaccrc32inserter_last[31] ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[8] <= ((((((((liteethmaccrc32inserter_last[0] ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[9] <= ((((((((liteethmaccrc32inserter_last[1] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_data1[6]); - liteethmaccrc32inserter_next[10] <= ((((((((liteethmaccrc32inserter_last[2] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[11] <= ((((((((liteethmaccrc32inserter_last[3] ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[12] <= ((((((((((((liteethmaccrc32inserter_last[4] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[13] <= ((((((((((((liteethmaccrc32inserter_last[5] ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]); - liteethmaccrc32inserter_next[14] <= ((((((((((liteethmaccrc32inserter_last[6] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]); - liteethmaccrc32inserter_next[15] <= ((((((((liteethmaccrc32inserter_last[7] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]); - liteethmaccrc32inserter_next[16] <= ((((((liteethmaccrc32inserter_last[8] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[17] <= ((((((liteethmaccrc32inserter_last[9] ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_data1[6]); - liteethmaccrc32inserter_next[18] <= ((((((liteethmaccrc32inserter_last[10] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]); - liteethmaccrc32inserter_next[19] <= ((((liteethmaccrc32inserter_last[11] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]); - liteethmaccrc32inserter_next[20] <= ((liteethmaccrc32inserter_last[12] ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]); - liteethmaccrc32inserter_next[21] <= ((liteethmaccrc32inserter_last[13] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]); - liteethmaccrc32inserter_next[22] <= ((liteethmaccrc32inserter_last[14] ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[23] <= ((((((liteethmaccrc32inserter_last[15] ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[24] <= ((((((liteethmaccrc32inserter_last[16] ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]); - liteethmaccrc32inserter_next[25] <= ((((liteethmaccrc32inserter_last[17] ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]); - liteethmaccrc32inserter_next[26] <= ((((((((liteethmaccrc32inserter_last[18] ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[27] <= ((((((((liteethmaccrc32inserter_last[19] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]); - liteethmaccrc32inserter_next[28] <= ((((((liteethmaccrc32inserter_last[20] ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]); - liteethmaccrc32inserter_next[29] <= ((((((liteethmaccrc32inserter_last[21] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]); - liteethmaccrc32inserter_next[30] <= ((((liteethmaccrc32inserter_last[22] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]); - liteethmaccrc32inserter_next[31] <= ((liteethmaccrc32inserter_last[23] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]); -end -always @(*) begin - liteethmaccrc32inserter_source_first <= 1'd0; - liteethmaccrc32inserter_source_last <= 1'd0; - liteethmaccrc32inserter_source_payload_data <= 8'd0; - liteethmaccrc32inserter_source_payload_last_be <= 1'd0; - liteethmaccrc32inserter_source_payload_error <= 1'd0; - liteethmaccrc32inserter_data0 <= 8'd0; - liteethmaccrc32inserter_is_ongoing0 <= 1'd0; - liteethmaccrc32inserter_sink_ready <= 1'd0; - liteethmaccrc32inserter_is_ongoing1 <= 1'd0; - liteethmaccrc32inserter_ce <= 1'd0; - liteethmaccrc32inserter_reset <= 1'd0; - subfragments_liteethmaccrc32inserter_next_state <= 2'd0; - liteethmaccrc32inserter_source_valid <= 1'd0; - subfragments_liteethmaccrc32inserter_next_state <= subfragments_liteethmaccrc32inserter_state; - case (subfragments_liteethmaccrc32inserter_state) - 1'd1: begin - liteethmaccrc32inserter_ce <= (liteethmaccrc32inserter_sink_valid & liteethmaccrc32inserter_source_ready); - liteethmaccrc32inserter_data0 <= liteethmaccrc32inserter_sink_payload_data; - liteethmaccrc32inserter_source_valid <= liteethmaccrc32inserter_sink_valid; - liteethmaccrc32inserter_sink_ready <= liteethmaccrc32inserter_source_ready; - liteethmaccrc32inserter_source_first <= liteethmaccrc32inserter_sink_first; - liteethmaccrc32inserter_source_last <= liteethmaccrc32inserter_sink_last; - liteethmaccrc32inserter_source_payload_data <= liteethmaccrc32inserter_sink_payload_data; - liteethmaccrc32inserter_source_payload_last_be <= liteethmaccrc32inserter_sink_payload_last_be; - liteethmaccrc32inserter_source_payload_error <= liteethmaccrc32inserter_sink_payload_error; - liteethmaccrc32inserter_source_last <= 1'd0; - if (((liteethmaccrc32inserter_sink_valid & liteethmaccrc32inserter_sink_last) & liteethmaccrc32inserter_source_ready)) begin - subfragments_liteethmaccrc32inserter_next_state <= 2'd2; - end - end - 2'd2: begin - liteethmaccrc32inserter_source_valid <= 1'd1; - case (liteethmaccrc32inserter_cnt) - 1'd0: begin - liteethmaccrc32inserter_source_payload_data <= liteethmaccrc32inserter_value[31:24]; - end - 1'd1: begin - liteethmaccrc32inserter_source_payload_data <= liteethmaccrc32inserter_value[23:16]; - end - 2'd2: begin - liteethmaccrc32inserter_source_payload_data <= liteethmaccrc32inserter_value[15:8]; - end - default: begin - liteethmaccrc32inserter_source_payload_data <= liteethmaccrc32inserter_value[7:0]; - end - endcase - if (liteethmaccrc32inserter_cnt_done) begin - liteethmaccrc32inserter_source_last <= 1'd1; - if (liteethmaccrc32inserter_source_ready) begin - subfragments_liteethmaccrc32inserter_next_state <= 1'd0; - end - end - liteethmaccrc32inserter_is_ongoing1 <= 1'd1; - end - default: begin - liteethmaccrc32inserter_reset <= 1'd1; - liteethmaccrc32inserter_sink_ready <= 1'd1; - if (liteethmaccrc32inserter_sink_valid) begin - liteethmaccrc32inserter_sink_ready <= 1'd0; - subfragments_liteethmaccrc32inserter_next_state <= 1'd1; - end - liteethmaccrc32inserter_is_ongoing0 <= 1'd1; - end - endcase -end -assign crc32_inserter_sink_ready = ((~crc32_inserter_source_valid) | crc32_inserter_source_ready); -assign liteethmaccrc32checker_fifo_full = (liteethmaccrc32checker_syncfifo_level == 3'd4); -assign liteethmaccrc32checker_fifo_in = (liteethmaccrc32checker_sink_sink_valid & ((~liteethmaccrc32checker_fifo_full) | liteethmaccrc32checker_fifo_out)); -assign liteethmaccrc32checker_fifo_out = (liteethmaccrc32checker_source_source_valid & liteethmaccrc32checker_source_source_ready); -assign liteethmaccrc32checker_syncfifo_sink_first = liteethmaccrc32checker_sink_sink_first; -assign liteethmaccrc32checker_syncfifo_sink_last = liteethmaccrc32checker_sink_sink_last; -assign liteethmaccrc32checker_syncfifo_sink_payload_data = liteethmaccrc32checker_sink_sink_payload_data; -assign liteethmaccrc32checker_syncfifo_sink_payload_last_be = liteethmaccrc32checker_sink_sink_payload_last_be; -assign liteethmaccrc32checker_syncfifo_sink_payload_error = liteethmaccrc32checker_sink_sink_payload_error; -always @(*) begin - liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; - liteethmaccrc32checker_syncfifo_sink_valid <= liteethmaccrc32checker_sink_sink_valid; - liteethmaccrc32checker_syncfifo_sink_valid <= liteethmaccrc32checker_fifo_in; -end -always @(*) begin - liteethmaccrc32checker_sink_sink_ready <= 1'd0; - liteethmaccrc32checker_sink_sink_ready <= liteethmaccrc32checker_syncfifo_sink_ready; - liteethmaccrc32checker_sink_sink_ready <= liteethmaccrc32checker_fifo_in; -end -assign liteethmaccrc32checker_source_source_valid = (liteethmaccrc32checker_sink_sink_valid & liteethmaccrc32checker_fifo_full); -assign liteethmaccrc32checker_source_source_last = liteethmaccrc32checker_sink_sink_last; -assign liteethmaccrc32checker_syncfifo_source_ready = liteethmaccrc32checker_fifo_out; -assign liteethmaccrc32checker_source_source_payload_data = liteethmaccrc32checker_syncfifo_source_payload_data; -assign liteethmaccrc32checker_source_source_payload_last_be = liteethmaccrc32checker_syncfifo_source_payload_last_be; -always @(*) begin - liteethmaccrc32checker_source_source_payload_error <= 1'd0; - liteethmaccrc32checker_source_source_payload_error <= liteethmaccrc32checker_syncfifo_source_payload_error; - liteethmaccrc32checker_source_source_payload_error <= (liteethmaccrc32checker_sink_sink_payload_error | liteethmaccrc32checker_crc_error); -end -assign liteethmaccrc32checker_error = ((liteethmaccrc32checker_source_source_valid & liteethmaccrc32checker_source_source_last) & liteethmaccrc32checker_crc_error); -assign liteethmaccrc32checker_crc_data0 = liteethmaccrc32checker_sink_sink_payload_data; -assign liteethmaccrc32checker_sink_sink_valid = crc32_checker_source_valid; -assign crc32_checker_source_ready = liteethmaccrc32checker_sink_sink_ready; -assign liteethmaccrc32checker_sink_sink_first = crc32_checker_source_first; -assign liteethmaccrc32checker_sink_sink_last = crc32_checker_source_last; -assign liteethmaccrc32checker_sink_sink_payload_data = crc32_checker_source_payload_data; -assign liteethmaccrc32checker_sink_sink_payload_last_be = crc32_checker_source_payload_last_be; -assign liteethmaccrc32checker_sink_sink_payload_error = crc32_checker_source_payload_error; -assign liteethmaccrc32checker_crc_data1 = liteethmaccrc32checker_crc_data0; -assign liteethmaccrc32checker_crc_last = liteethmaccrc32checker_crc_reg; -assign liteethmaccrc32checker_crc_value = (~{liteethmaccrc32checker_crc_reg[0], liteethmaccrc32checker_crc_reg[1], liteethmaccrc32checker_crc_reg[2], liteethmaccrc32checker_crc_reg[3], liteethmaccrc32checker_crc_reg[4], liteethmaccrc32checker_crc_reg[5], liteethmaccrc32checker_crc_reg[6], liteethmaccrc32checker_crc_reg[7], liteethmaccrc32checker_crc_reg[8], liteethmaccrc32checker_crc_reg[9], liteethmaccrc32checker_crc_reg[10], liteethmaccrc32checker_crc_reg[11], liteethmaccrc32checker_crc_reg[12], liteethmaccrc32checker_crc_reg[13], liteethmaccrc32checker_crc_reg[14], liteethmaccrc32checker_crc_reg[15], liteethmaccrc32checker_crc_reg[16], liteethmaccrc32checker_crc_reg[17], liteethmaccrc32checker_crc_reg[18], liteethmaccrc32checker_crc_reg[19], liteethmaccrc32checker_crc_reg[20], liteethmaccrc32checker_crc_reg[21], liteethmaccrc32checker_crc_reg[22], liteethmaccrc32checker_crc_reg[23], liteethmaccrc32checker_crc_reg[24], liteethmaccrc32checker_crc_reg[25], liteethmaccrc32checker_crc_reg[26], liteethmaccrc32checker_crc_reg[27], liteethmaccrc32checker_crc_reg[28], liteethmaccrc32checker_crc_reg[29], liteethmaccrc32checker_crc_reg[30], liteethmaccrc32checker_crc_reg[31]}); -assign liteethmaccrc32checker_crc_error = (liteethmaccrc32checker_crc_next != 32'd3338984827); -always @(*) begin - liteethmaccrc32checker_crc_next <= 32'd0; - liteethmaccrc32checker_crc_next[0] <= (((liteethmaccrc32checker_crc_last[24] ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[1] <= (((((((liteethmaccrc32checker_crc_last[25] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[2] <= (((((((((liteethmaccrc32checker_crc_last[26] ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[3] <= (((((((liteethmaccrc32checker_crc_last[27] ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]); - liteethmaccrc32checker_crc_next[4] <= (((((((((liteethmaccrc32checker_crc_last[28] ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[5] <= (((((((((((((liteethmaccrc32checker_crc_last[29] ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[6] <= (((((((((((liteethmaccrc32checker_crc_last[30] ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]); - liteethmaccrc32checker_crc_next[7] <= (((((((((liteethmaccrc32checker_crc_last[31] ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[8] <= ((((((((liteethmaccrc32checker_crc_last[0] ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[9] <= ((((((((liteethmaccrc32checker_crc_last[1] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_data1[6]); - liteethmaccrc32checker_crc_next[10] <= ((((((((liteethmaccrc32checker_crc_last[2] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[11] <= ((((((((liteethmaccrc32checker_crc_last[3] ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[12] <= ((((((((((((liteethmaccrc32checker_crc_last[4] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[13] <= ((((((((((((liteethmaccrc32checker_crc_last[5] ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]); - liteethmaccrc32checker_crc_next[14] <= ((((((((((liteethmaccrc32checker_crc_last[6] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]); - liteethmaccrc32checker_crc_next[15] <= ((((((((liteethmaccrc32checker_crc_last[7] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]); - liteethmaccrc32checker_crc_next[16] <= ((((((liteethmaccrc32checker_crc_last[8] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[17] <= ((((((liteethmaccrc32checker_crc_last[9] ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_data1[6]); - liteethmaccrc32checker_crc_next[18] <= ((((((liteethmaccrc32checker_crc_last[10] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]); - liteethmaccrc32checker_crc_next[19] <= ((((liteethmaccrc32checker_crc_last[11] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]); - liteethmaccrc32checker_crc_next[20] <= ((liteethmaccrc32checker_crc_last[12] ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]); - liteethmaccrc32checker_crc_next[21] <= ((liteethmaccrc32checker_crc_last[13] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]); - liteethmaccrc32checker_crc_next[22] <= ((liteethmaccrc32checker_crc_last[14] ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[23] <= ((((((liteethmaccrc32checker_crc_last[15] ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[24] <= ((((((liteethmaccrc32checker_crc_last[16] ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]); - liteethmaccrc32checker_crc_next[25] <= ((((liteethmaccrc32checker_crc_last[17] ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]); - liteethmaccrc32checker_crc_next[26] <= ((((((((liteethmaccrc32checker_crc_last[18] ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[27] <= ((((((((liteethmaccrc32checker_crc_last[19] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]); - liteethmaccrc32checker_crc_next[28] <= ((((((liteethmaccrc32checker_crc_last[20] ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]); - liteethmaccrc32checker_crc_next[29] <= ((((((liteethmaccrc32checker_crc_last[21] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]); - liteethmaccrc32checker_crc_next[30] <= ((((liteethmaccrc32checker_crc_last[22] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]); - liteethmaccrc32checker_crc_next[31] <= ((liteethmaccrc32checker_crc_last[23] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]); -end -assign liteethmaccrc32checker_syncfifo_syncfifo_din = {liteethmaccrc32checker_syncfifo_fifo_in_last, liteethmaccrc32checker_syncfifo_fifo_in_first, liteethmaccrc32checker_syncfifo_fifo_in_payload_error, liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, liteethmaccrc32checker_syncfifo_fifo_in_payload_data}; -assign {liteethmaccrc32checker_syncfifo_fifo_out_last, liteethmaccrc32checker_syncfifo_fifo_out_first, liteethmaccrc32checker_syncfifo_fifo_out_payload_error, liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = liteethmaccrc32checker_syncfifo_syncfifo_dout; -assign liteethmaccrc32checker_syncfifo_sink_ready = liteethmaccrc32checker_syncfifo_syncfifo_writable; -assign liteethmaccrc32checker_syncfifo_syncfifo_we = liteethmaccrc32checker_syncfifo_sink_valid; -assign liteethmaccrc32checker_syncfifo_fifo_in_first = liteethmaccrc32checker_syncfifo_sink_first; -assign liteethmaccrc32checker_syncfifo_fifo_in_last = liteethmaccrc32checker_syncfifo_sink_last; -assign liteethmaccrc32checker_syncfifo_fifo_in_payload_data = liteethmaccrc32checker_syncfifo_sink_payload_data; -assign liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be = liteethmaccrc32checker_syncfifo_sink_payload_last_be; -assign liteethmaccrc32checker_syncfifo_fifo_in_payload_error = liteethmaccrc32checker_syncfifo_sink_payload_error; -assign liteethmaccrc32checker_syncfifo_source_valid = liteethmaccrc32checker_syncfifo_syncfifo_readable; -assign liteethmaccrc32checker_syncfifo_source_first = liteethmaccrc32checker_syncfifo_fifo_out_first; -assign liteethmaccrc32checker_syncfifo_source_last = liteethmaccrc32checker_syncfifo_fifo_out_last; -assign liteethmaccrc32checker_syncfifo_source_payload_data = liteethmaccrc32checker_syncfifo_fifo_out_payload_data; -assign liteethmaccrc32checker_syncfifo_source_payload_last_be = liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; -assign liteethmaccrc32checker_syncfifo_source_payload_error = liteethmaccrc32checker_syncfifo_fifo_out_payload_error; -assign liteethmaccrc32checker_syncfifo_syncfifo_re = liteethmaccrc32checker_syncfifo_source_ready; -always @(*) begin - liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; - if (liteethmaccrc32checker_syncfifo_replace) begin - liteethmaccrc32checker_syncfifo_wrport_adr <= (liteethmaccrc32checker_syncfifo_produce - 1'd1); - end else begin - liteethmaccrc32checker_syncfifo_wrport_adr <= liteethmaccrc32checker_syncfifo_produce; - end -end -assign liteethmaccrc32checker_syncfifo_wrport_dat_w = liteethmaccrc32checker_syncfifo_syncfifo_din; -assign liteethmaccrc32checker_syncfifo_wrport_we = (liteethmaccrc32checker_syncfifo_syncfifo_we & (liteethmaccrc32checker_syncfifo_syncfifo_writable | liteethmaccrc32checker_syncfifo_replace)); -assign liteethmaccrc32checker_syncfifo_do_read = (liteethmaccrc32checker_syncfifo_syncfifo_readable & liteethmaccrc32checker_syncfifo_syncfifo_re); -assign liteethmaccrc32checker_syncfifo_rdport_adr = liteethmaccrc32checker_syncfifo_consume; -assign liteethmaccrc32checker_syncfifo_syncfifo_dout = liteethmaccrc32checker_syncfifo_rdport_dat_r; -assign liteethmaccrc32checker_syncfifo_syncfifo_writable = (liteethmaccrc32checker_syncfifo_level != 3'd5); -assign liteethmaccrc32checker_syncfifo_syncfifo_readable = (liteethmaccrc32checker_syncfifo_level != 1'd0); -always @(*) begin - liteethmaccrc32checker_crc_ce <= 1'd0; - liteethmaccrc32checker_crc_reset <= 1'd0; - subfragments_liteethmaccrc32checker_next_state <= 2'd0; - liteethmaccrc32checker_fifo_reset <= 1'd0; - subfragments_liteethmaccrc32checker_next_state <= subfragments_liteethmaccrc32checker_state; - case (subfragments_liteethmaccrc32checker_state) - 1'd1: begin - if ((liteethmaccrc32checker_sink_sink_valid & liteethmaccrc32checker_sink_sink_ready)) begin - liteethmaccrc32checker_crc_ce <= 1'd1; - subfragments_liteethmaccrc32checker_next_state <= 2'd2; - end - end - 2'd2: begin - if ((liteethmaccrc32checker_sink_sink_valid & liteethmaccrc32checker_sink_sink_ready)) begin - liteethmaccrc32checker_crc_ce <= 1'd1; - if (liteethmaccrc32checker_sink_sink_last) begin - subfragments_liteethmaccrc32checker_next_state <= 1'd0; - end - end - end - default: begin - liteethmaccrc32checker_crc_reset <= 1'd1; - liteethmaccrc32checker_fifo_reset <= 1'd1; - subfragments_liteethmaccrc32checker_next_state <= 1'd1; - end - endcase -end -assign crc32_checker_sink_ready = ((~crc32_checker_source_valid) | crc32_checker_source_ready); -assign ps_preamble_error_o = (ps_preamble_error_toggle_o ^ ps_preamble_error_toggle_o_r); -assign ps_crc_error_o = (ps_crc_error_toggle_o ^ ps_crc_error_toggle_o_r); -assign padding_inserter_counter_done = (padding_inserter_counter >= 6'd59); -always @(*) begin - padding_inserter_source_valid <= 1'd0; - padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd0; - padding_inserter_source_first <= 1'd0; - padding_inserter_source_last <= 1'd0; - padding_inserter_source_payload_data <= 8'd0; - padding_inserter_source_payload_last_be <= 1'd0; - padding_inserter_source_payload_error <= 1'd0; - padding_inserter_sink_ready <= 1'd0; - subfragments_liteethmacpaddinginserter_next_state <= 1'd0; - padding_inserter_counter_liteethmacpaddinginserter_next_value <= 16'd0; - subfragments_liteethmacpaddinginserter_next_state <= subfragments_liteethmacpaddinginserter_state; - case (subfragments_liteethmacpaddinginserter_state) - 1'd1: begin - padding_inserter_source_valid <= 1'd1; - padding_inserter_source_last <= padding_inserter_counter_done; - padding_inserter_source_payload_data <= 1'd0; - if ((padding_inserter_source_valid & padding_inserter_source_ready)) begin - padding_inserter_counter_liteethmacpaddinginserter_next_value <= (padding_inserter_counter + 1'd1); - padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; - if (padding_inserter_counter_done) begin - padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0; - padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; - subfragments_liteethmacpaddinginserter_next_state <= 1'd0; - end - end - end - default: begin - padding_inserter_source_valid <= padding_inserter_sink_valid; - padding_inserter_sink_ready <= padding_inserter_source_ready; - padding_inserter_source_first <= padding_inserter_sink_first; - padding_inserter_source_last <= padding_inserter_sink_last; - padding_inserter_source_payload_data <= padding_inserter_sink_payload_data; - padding_inserter_source_payload_last_be <= padding_inserter_sink_payload_last_be; - padding_inserter_source_payload_error <= padding_inserter_sink_payload_error; - if ((padding_inserter_source_valid & padding_inserter_source_ready)) begin - padding_inserter_counter_liteethmacpaddinginserter_next_value <= (padding_inserter_counter + 1'd1); - padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; - if (padding_inserter_sink_last) begin - if ((~padding_inserter_counter_done)) begin - padding_inserter_source_last <= 1'd0; - subfragments_liteethmacpaddinginserter_next_state <= 1'd1; - end else begin - padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0; - padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; - end - end - end - end - endcase -end -assign padding_checker_source_valid = padding_checker_sink_valid; -assign padding_checker_sink_ready = padding_checker_source_ready; -assign padding_checker_source_first = padding_checker_sink_first; -assign padding_checker_source_last = padding_checker_sink_last; -assign padding_checker_source_payload_data = padding_checker_sink_payload_data; -assign padding_checker_source_payload_last_be = padding_checker_sink_payload_last_be; -assign padding_checker_source_payload_error = padding_checker_sink_payload_error; -always @(*) begin - tx_last_be_source_payload_data <= 8'd0; - subfragments_liteethmactxlastbe_next_state <= 1'd0; - tx_last_be_source_payload_error <= 1'd0; - tx_last_be_sink_ready <= 1'd0; - tx_last_be_source_valid <= 1'd0; - tx_last_be_source_first <= 1'd0; - tx_last_be_source_last <= 1'd0; - subfragments_liteethmactxlastbe_next_state <= subfragments_liteethmactxlastbe_state; - case (subfragments_liteethmactxlastbe_state) - 1'd1: begin - tx_last_be_sink_ready <= 1'd1; - if ((tx_last_be_sink_valid & tx_last_be_sink_last)) begin - subfragments_liteethmactxlastbe_next_state <= 1'd0; - end - end - default: begin - tx_last_be_source_valid <= tx_last_be_sink_valid; - tx_last_be_sink_ready <= tx_last_be_source_ready; - tx_last_be_source_first <= tx_last_be_sink_first; - tx_last_be_source_payload_data <= tx_last_be_sink_payload_data; - tx_last_be_source_payload_error <= tx_last_be_sink_payload_error; - tx_last_be_source_last <= tx_last_be_sink_payload_last_be; - if ((tx_last_be_sink_valid & tx_last_be_sink_ready)) begin - if ((tx_last_be_sink_payload_last_be & (~tx_last_be_sink_last))) begin - subfragments_liteethmactxlastbe_next_state <= 1'd1; - end - end - end - endcase -end -assign rx_last_be_source_valid = rx_last_be_sink_valid; -assign rx_last_be_sink_ready = rx_last_be_source_ready; -assign rx_last_be_source_first = rx_last_be_sink_first; -assign rx_last_be_source_last = rx_last_be_sink_last; -assign rx_last_be_source_payload_data = rx_last_be_sink_payload_data; -assign rx_last_be_source_payload_error = rx_last_be_sink_payload_error; -always @(*) begin - rx_last_be_source_payload_last_be <= 1'd0; - rx_last_be_source_payload_last_be <= rx_last_be_sink_payload_last_be; - rx_last_be_source_payload_last_be <= rx_last_be_sink_last; -end -assign tx_converter_converter_sink_valid = tx_converter_sink_valid; -assign tx_converter_converter_sink_first = tx_converter_sink_first; -assign tx_converter_converter_sink_last = tx_converter_sink_last; -assign tx_converter_sink_ready = tx_converter_converter_sink_ready; -always @(*) begin - tx_converter_converter_sink_payload_data <= 40'd0; - tx_converter_converter_sink_payload_data[7:0] <= tx_converter_sink_payload_data[7:0]; - tx_converter_converter_sink_payload_data[8] <= tx_converter_sink_payload_last_be[0]; - tx_converter_converter_sink_payload_data[9] <= tx_converter_sink_payload_error[0]; - tx_converter_converter_sink_payload_data[17:10] <= tx_converter_sink_payload_data[15:8]; - tx_converter_converter_sink_payload_data[18] <= tx_converter_sink_payload_last_be[1]; - tx_converter_converter_sink_payload_data[19] <= tx_converter_sink_payload_error[1]; - tx_converter_converter_sink_payload_data[27:20] <= tx_converter_sink_payload_data[23:16]; - tx_converter_converter_sink_payload_data[28] <= tx_converter_sink_payload_last_be[2]; - tx_converter_converter_sink_payload_data[29] <= tx_converter_sink_payload_error[2]; - tx_converter_converter_sink_payload_data[37:30] <= tx_converter_sink_payload_data[31:24]; - tx_converter_converter_sink_payload_data[38] <= tx_converter_sink_payload_last_be[3]; - tx_converter_converter_sink_payload_data[39] <= tx_converter_sink_payload_error[3]; -end -assign tx_converter_source_valid = tx_converter_source_source_valid; -assign tx_converter_source_first = tx_converter_source_source_first; -assign tx_converter_source_last = tx_converter_source_source_last; -assign tx_converter_source_source_ready = tx_converter_source_ready; -assign {tx_converter_source_payload_error, tx_converter_source_payload_last_be, tx_converter_source_payload_data} = tx_converter_source_source_payload_data; -assign tx_converter_source_source_valid = tx_converter_converter_source_valid; -assign tx_converter_converter_source_ready = tx_converter_source_source_ready; -assign tx_converter_source_source_first = tx_converter_converter_source_first; -assign tx_converter_source_source_last = tx_converter_converter_source_last; -assign tx_converter_source_source_payload_data = tx_converter_converter_source_payload_data; -assign tx_converter_converter_first = (tx_converter_converter_mux == 1'd0); -assign tx_converter_converter_last = (tx_converter_converter_mux == 2'd3); -assign tx_converter_converter_source_valid = tx_converter_converter_sink_valid; -assign tx_converter_converter_source_first = (tx_converter_converter_sink_first & tx_converter_converter_first); -assign tx_converter_converter_source_last = (tx_converter_converter_sink_last & tx_converter_converter_last); -assign tx_converter_converter_sink_ready = (tx_converter_converter_last & tx_converter_converter_source_ready); -always @(*) begin - tx_converter_converter_source_payload_data <= 10'd0; - case (tx_converter_converter_mux) - 1'd0: begin - tx_converter_converter_source_payload_data <= tx_converter_converter_sink_payload_data[9:0]; - end - 1'd1: begin - tx_converter_converter_source_payload_data <= tx_converter_converter_sink_payload_data[19:10]; - end - 2'd2: begin - tx_converter_converter_source_payload_data <= tx_converter_converter_sink_payload_data[29:20]; - end - default: begin - tx_converter_converter_source_payload_data <= tx_converter_converter_sink_payload_data[39:30]; - end - endcase -end -assign tx_converter_converter_source_payload_valid_token_count = tx_converter_converter_last; -assign rx_converter_converter_sink_valid = rx_converter_sink_valid; -assign rx_converter_converter_sink_first = rx_converter_sink_first; -assign rx_converter_converter_sink_last = rx_converter_sink_last; -assign rx_converter_sink_ready = rx_converter_converter_sink_ready; -assign rx_converter_converter_sink_payload_data = {rx_converter_sink_payload_error, rx_converter_sink_payload_last_be, rx_converter_sink_payload_data}; -assign rx_converter_source_valid = rx_converter_source_source_valid; -assign rx_converter_source_first = rx_converter_source_source_first; -assign rx_converter_source_last = rx_converter_source_source_last; -assign rx_converter_source_source_ready = rx_converter_source_ready; -always @(*) begin - rx_converter_source_payload_data <= 32'd0; - rx_converter_source_payload_data[7:0] <= rx_converter_source_source_payload_data[7:0]; - rx_converter_source_payload_data[15:8] <= rx_converter_source_source_payload_data[17:10]; - rx_converter_source_payload_data[23:16] <= rx_converter_source_source_payload_data[27:20]; - rx_converter_source_payload_data[31:24] <= rx_converter_source_source_payload_data[37:30]; -end -always @(*) begin - rx_converter_source_payload_last_be <= 4'd0; - rx_converter_source_payload_last_be[0] <= rx_converter_source_source_payload_data[8]; - rx_converter_source_payload_last_be[1] <= rx_converter_source_source_payload_data[18]; - rx_converter_source_payload_last_be[2] <= rx_converter_source_source_payload_data[28]; - rx_converter_source_payload_last_be[3] <= rx_converter_source_source_payload_data[38]; -end -always @(*) begin - rx_converter_source_payload_error <= 4'd0; - rx_converter_source_payload_error[0] <= rx_converter_source_source_payload_data[9]; - rx_converter_source_payload_error[1] <= rx_converter_source_source_payload_data[19]; - rx_converter_source_payload_error[2] <= rx_converter_source_source_payload_data[29]; - rx_converter_source_payload_error[3] <= rx_converter_source_source_payload_data[39]; -end -assign rx_converter_source_source_valid = rx_converter_converter_source_valid; -assign rx_converter_converter_source_ready = rx_converter_source_source_ready; -assign rx_converter_source_source_first = rx_converter_converter_source_first; -assign rx_converter_source_source_last = rx_converter_converter_source_last; -assign rx_converter_source_source_payload_data = rx_converter_converter_source_payload_data; -assign rx_converter_converter_sink_ready = ((~rx_converter_converter_strobe_all) | rx_converter_converter_source_ready); -assign rx_converter_converter_source_valid = rx_converter_converter_strobe_all; -assign rx_converter_converter_load_part = (rx_converter_converter_sink_valid & rx_converter_converter_sink_ready); -assign tx_cdc_cdc_sink_valid = tx_cdc_sink_sink_valid; -assign tx_cdc_sink_sink_ready = tx_cdc_cdc_sink_ready; -assign tx_cdc_cdc_sink_first = tx_cdc_sink_sink_first; -assign tx_cdc_cdc_sink_last = tx_cdc_sink_sink_last; -assign tx_cdc_cdc_sink_payload_data = tx_cdc_sink_sink_payload_data; -assign tx_cdc_cdc_sink_payload_last_be = tx_cdc_sink_sink_payload_last_be; -assign tx_cdc_cdc_sink_payload_error = tx_cdc_sink_sink_payload_error; -assign tx_cdc_source_source_valid = tx_cdc_cdc_source_valid; -assign tx_cdc_cdc_source_ready = tx_cdc_source_source_ready; -assign tx_cdc_source_source_first = tx_cdc_cdc_source_first; -assign tx_cdc_source_source_last = tx_cdc_cdc_source_last; -assign tx_cdc_source_source_payload_data = tx_cdc_cdc_source_payload_data; -assign tx_cdc_source_source_payload_last_be = tx_cdc_cdc_source_payload_last_be; -assign tx_cdc_source_source_payload_error = tx_cdc_cdc_source_payload_error; -assign tx_cdc_cdc_asyncfifo_din = {tx_cdc_cdc_fifo_in_last, tx_cdc_cdc_fifo_in_first, tx_cdc_cdc_fifo_in_payload_error, tx_cdc_cdc_fifo_in_payload_last_be, tx_cdc_cdc_fifo_in_payload_data}; -assign {tx_cdc_cdc_fifo_out_last, tx_cdc_cdc_fifo_out_first, tx_cdc_cdc_fifo_out_payload_error, tx_cdc_cdc_fifo_out_payload_last_be, tx_cdc_cdc_fifo_out_payload_data} = tx_cdc_cdc_asyncfifo_dout; -assign tx_cdc_cdc_sink_ready = tx_cdc_cdc_asyncfifo_writable; -assign tx_cdc_cdc_asyncfifo_we = tx_cdc_cdc_sink_valid; -assign tx_cdc_cdc_fifo_in_first = tx_cdc_cdc_sink_first; -assign tx_cdc_cdc_fifo_in_last = tx_cdc_cdc_sink_last; -assign tx_cdc_cdc_fifo_in_payload_data = tx_cdc_cdc_sink_payload_data; -assign tx_cdc_cdc_fifo_in_payload_last_be = tx_cdc_cdc_sink_payload_last_be; -assign tx_cdc_cdc_fifo_in_payload_error = tx_cdc_cdc_sink_payload_error; -assign tx_cdc_cdc_source_valid = tx_cdc_cdc_asyncfifo_readable; -assign tx_cdc_cdc_source_first = tx_cdc_cdc_fifo_out_first; -assign tx_cdc_cdc_source_last = tx_cdc_cdc_fifo_out_last; -assign tx_cdc_cdc_source_payload_data = tx_cdc_cdc_fifo_out_payload_data; -assign tx_cdc_cdc_source_payload_last_be = tx_cdc_cdc_fifo_out_payload_last_be; -assign tx_cdc_cdc_source_payload_error = tx_cdc_cdc_fifo_out_payload_error; -assign tx_cdc_cdc_asyncfifo_re = tx_cdc_cdc_source_ready; -assign tx_cdc_cdc_graycounter0_ce = (tx_cdc_cdc_asyncfifo_writable & tx_cdc_cdc_asyncfifo_we); -assign tx_cdc_cdc_graycounter1_ce = (tx_cdc_cdc_asyncfifo_readable & tx_cdc_cdc_asyncfifo_re); -assign tx_cdc_cdc_asyncfifo_writable = (((tx_cdc_cdc_graycounter0_q[5] == tx_cdc_cdc_consume_wdomain[5]) | (tx_cdc_cdc_graycounter0_q[4] == tx_cdc_cdc_consume_wdomain[4])) | (tx_cdc_cdc_graycounter0_q[3:0] != tx_cdc_cdc_consume_wdomain[3:0])); -assign tx_cdc_cdc_asyncfifo_readable = (tx_cdc_cdc_graycounter1_q != tx_cdc_cdc_produce_rdomain); -assign tx_cdc_cdc_wrport_adr = tx_cdc_cdc_graycounter0_q_binary[4:0]; -assign tx_cdc_cdc_wrport_dat_w = tx_cdc_cdc_asyncfifo_din; -assign tx_cdc_cdc_wrport_we = tx_cdc_cdc_graycounter0_ce; -assign tx_cdc_cdc_rdport_adr = tx_cdc_cdc_graycounter1_q_next_binary[4:0]; -assign tx_cdc_cdc_asyncfifo_dout = tx_cdc_cdc_rdport_dat_r; -always @(*) begin - tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; - if (tx_cdc_cdc_graycounter0_ce) begin - tx_cdc_cdc_graycounter0_q_next_binary <= (tx_cdc_cdc_graycounter0_q_binary + 1'd1); - end else begin - tx_cdc_cdc_graycounter0_q_next_binary <= tx_cdc_cdc_graycounter0_q_binary; - end -end -assign tx_cdc_cdc_graycounter0_q_next = (tx_cdc_cdc_graycounter0_q_next_binary ^ tx_cdc_cdc_graycounter0_q_next_binary[5:1]); -always @(*) begin - tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; - if (tx_cdc_cdc_graycounter1_ce) begin - tx_cdc_cdc_graycounter1_q_next_binary <= (tx_cdc_cdc_graycounter1_q_binary + 1'd1); - end else begin - tx_cdc_cdc_graycounter1_q_next_binary <= tx_cdc_cdc_graycounter1_q_binary; - end -end -assign tx_cdc_cdc_graycounter1_q_next = (tx_cdc_cdc_graycounter1_q_next_binary ^ tx_cdc_cdc_graycounter1_q_next_binary[5:1]); -assign rx_cdc_cdc_sink_valid = rx_cdc_sink_sink_valid; -assign rx_cdc_sink_sink_ready = rx_cdc_cdc_sink_ready; -assign rx_cdc_cdc_sink_first = rx_cdc_sink_sink_first; -assign rx_cdc_cdc_sink_last = rx_cdc_sink_sink_last; -assign rx_cdc_cdc_sink_payload_data = rx_cdc_sink_sink_payload_data; -assign rx_cdc_cdc_sink_payload_last_be = rx_cdc_sink_sink_payload_last_be; -assign rx_cdc_cdc_sink_payload_error = rx_cdc_sink_sink_payload_error; -assign rx_cdc_source_source_valid = rx_cdc_cdc_source_valid; -assign rx_cdc_cdc_source_ready = rx_cdc_source_source_ready; -assign rx_cdc_source_source_first = rx_cdc_cdc_source_first; -assign rx_cdc_source_source_last = rx_cdc_cdc_source_last; -assign rx_cdc_source_source_payload_data = rx_cdc_cdc_source_payload_data; -assign rx_cdc_source_source_payload_last_be = rx_cdc_cdc_source_payload_last_be; -assign rx_cdc_source_source_payload_error = rx_cdc_cdc_source_payload_error; -assign rx_cdc_cdc_asyncfifo_din = {rx_cdc_cdc_fifo_in_last, rx_cdc_cdc_fifo_in_first, rx_cdc_cdc_fifo_in_payload_error, rx_cdc_cdc_fifo_in_payload_last_be, rx_cdc_cdc_fifo_in_payload_data}; -assign {rx_cdc_cdc_fifo_out_last, rx_cdc_cdc_fifo_out_first, rx_cdc_cdc_fifo_out_payload_error, rx_cdc_cdc_fifo_out_payload_last_be, rx_cdc_cdc_fifo_out_payload_data} = rx_cdc_cdc_asyncfifo_dout; -assign rx_cdc_cdc_sink_ready = rx_cdc_cdc_asyncfifo_writable; -assign rx_cdc_cdc_asyncfifo_we = rx_cdc_cdc_sink_valid; -assign rx_cdc_cdc_fifo_in_first = rx_cdc_cdc_sink_first; -assign rx_cdc_cdc_fifo_in_last = rx_cdc_cdc_sink_last; -assign rx_cdc_cdc_fifo_in_payload_data = rx_cdc_cdc_sink_payload_data; -assign rx_cdc_cdc_fifo_in_payload_last_be = rx_cdc_cdc_sink_payload_last_be; -assign rx_cdc_cdc_fifo_in_payload_error = rx_cdc_cdc_sink_payload_error; -assign rx_cdc_cdc_source_valid = rx_cdc_cdc_asyncfifo_readable; -assign rx_cdc_cdc_source_first = rx_cdc_cdc_fifo_out_first; -assign rx_cdc_cdc_source_last = rx_cdc_cdc_fifo_out_last; -assign rx_cdc_cdc_source_payload_data = rx_cdc_cdc_fifo_out_payload_data; -assign rx_cdc_cdc_source_payload_last_be = rx_cdc_cdc_fifo_out_payload_last_be; -assign rx_cdc_cdc_source_payload_error = rx_cdc_cdc_fifo_out_payload_error; -assign rx_cdc_cdc_asyncfifo_re = rx_cdc_cdc_source_ready; -assign rx_cdc_cdc_graycounter0_ce = (rx_cdc_cdc_asyncfifo_writable & rx_cdc_cdc_asyncfifo_we); -assign rx_cdc_cdc_graycounter1_ce = (rx_cdc_cdc_asyncfifo_readable & rx_cdc_cdc_asyncfifo_re); -assign rx_cdc_cdc_asyncfifo_writable = (((rx_cdc_cdc_graycounter0_q[5] == rx_cdc_cdc_consume_wdomain[5]) | (rx_cdc_cdc_graycounter0_q[4] == rx_cdc_cdc_consume_wdomain[4])) | (rx_cdc_cdc_graycounter0_q[3:0] != rx_cdc_cdc_consume_wdomain[3:0])); -assign rx_cdc_cdc_asyncfifo_readable = (rx_cdc_cdc_graycounter1_q != rx_cdc_cdc_produce_rdomain); -assign rx_cdc_cdc_wrport_adr = rx_cdc_cdc_graycounter0_q_binary[4:0]; -assign rx_cdc_cdc_wrport_dat_w = rx_cdc_cdc_asyncfifo_din; -assign rx_cdc_cdc_wrport_we = rx_cdc_cdc_graycounter0_ce; -assign rx_cdc_cdc_rdport_adr = rx_cdc_cdc_graycounter1_q_next_binary[4:0]; -assign rx_cdc_cdc_asyncfifo_dout = rx_cdc_cdc_rdport_dat_r; -always @(*) begin - rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; - if (rx_cdc_cdc_graycounter0_ce) begin - rx_cdc_cdc_graycounter0_q_next_binary <= (rx_cdc_cdc_graycounter0_q_binary + 1'd1); - end else begin - rx_cdc_cdc_graycounter0_q_next_binary <= rx_cdc_cdc_graycounter0_q_binary; - end -end -assign rx_cdc_cdc_graycounter0_q_next = (rx_cdc_cdc_graycounter0_q_next_binary ^ rx_cdc_cdc_graycounter0_q_next_binary[5:1]); -always @(*) begin - rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; - if (rx_cdc_cdc_graycounter1_ce) begin - rx_cdc_cdc_graycounter1_q_next_binary <= (rx_cdc_cdc_graycounter1_q_binary + 1'd1); - end else begin - rx_cdc_cdc_graycounter1_q_next_binary <= rx_cdc_cdc_graycounter1_q_binary; - end -end -assign rx_cdc_cdc_graycounter1_q_next = (rx_cdc_cdc_graycounter1_q_next_binary ^ rx_cdc_cdc_graycounter1_q_next_binary[5:1]); -assign tx_converter_sink_valid = tx_cdc_source_source_valid; -assign tx_cdc_source_source_ready = tx_converter_sink_ready; -assign tx_converter_sink_first = tx_cdc_source_source_first; -assign tx_converter_sink_last = tx_cdc_source_source_last; -assign tx_converter_sink_payload_data = tx_cdc_source_source_payload_data; -assign tx_converter_sink_payload_last_be = tx_cdc_source_source_payload_last_be; -assign tx_converter_sink_payload_error = tx_cdc_source_source_payload_error; -assign tx_last_be_sink_valid = tx_converter_source_valid; -assign tx_converter_source_ready = tx_last_be_sink_ready; -assign tx_last_be_sink_first = tx_converter_source_first; -assign tx_last_be_sink_last = tx_converter_source_last; -assign tx_last_be_sink_payload_data = tx_converter_source_payload_data; -assign tx_last_be_sink_payload_last_be = tx_converter_source_payload_last_be; -assign tx_last_be_sink_payload_error = tx_converter_source_payload_error; -assign padding_inserter_sink_valid = tx_last_be_source_valid; -assign tx_last_be_source_ready = padding_inserter_sink_ready; -assign padding_inserter_sink_first = tx_last_be_source_first; -assign padding_inserter_sink_last = tx_last_be_source_last; -assign padding_inserter_sink_payload_data = tx_last_be_source_payload_data; -assign padding_inserter_sink_payload_last_be = tx_last_be_source_payload_last_be; -assign padding_inserter_sink_payload_error = tx_last_be_source_payload_error; -assign crc32_inserter_sink_valid = padding_inserter_source_valid; -assign padding_inserter_source_ready = crc32_inserter_sink_ready; -assign crc32_inserter_sink_first = padding_inserter_source_first; -assign crc32_inserter_sink_last = padding_inserter_source_last; -assign crc32_inserter_sink_payload_data = padding_inserter_source_payload_data; -assign crc32_inserter_sink_payload_last_be = padding_inserter_source_payload_last_be; -assign crc32_inserter_sink_payload_error = padding_inserter_source_payload_error; -assign preamble_inserter_sink_valid = liteethmaccrc32inserter_source_valid; -assign liteethmaccrc32inserter_source_ready = preamble_inserter_sink_ready; -assign preamble_inserter_sink_first = liteethmaccrc32inserter_source_first; -assign preamble_inserter_sink_last = liteethmaccrc32inserter_source_last; -assign preamble_inserter_sink_payload_data = liteethmaccrc32inserter_source_payload_data; -assign preamble_inserter_sink_payload_last_be = liteethmaccrc32inserter_source_payload_last_be; -assign preamble_inserter_sink_payload_error = liteethmaccrc32inserter_source_payload_error; -assign tx_gap_inserter_sink_valid = preamble_inserter_source_valid; -assign preamble_inserter_source_ready = tx_gap_inserter_sink_ready; -assign tx_gap_inserter_sink_first = preamble_inserter_source_first; -assign tx_gap_inserter_sink_last = preamble_inserter_source_last; -assign tx_gap_inserter_sink_payload_data = preamble_inserter_source_payload_data; -assign tx_gap_inserter_sink_payload_last_be = preamble_inserter_source_payload_last_be; -assign tx_gap_inserter_sink_payload_error = preamble_inserter_source_payload_error; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_valid0 = tx_gap_inserter_source_valid; -assign tx_gap_inserter_source_ready = maccore_ethphy_liteethphygmiimiitx_sink_sink_ready0; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_first0 = tx_gap_inserter_source_first; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_last0 = tx_gap_inserter_source_last; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_data0 = tx_gap_inserter_source_payload_data; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_last_be0 = tx_gap_inserter_source_payload_last_be; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_error0 = tx_gap_inserter_source_payload_error; -assign preamble_checker_sink_valid = maccore_ethphy_liteethphygmiimiirx_source_source_valid0; -assign maccore_ethphy_liteethphygmiimiirx_source_source_ready0 = preamble_checker_sink_ready; -assign preamble_checker_sink_first = maccore_ethphy_liteethphygmiimiirx_source_source_first0; -assign preamble_checker_sink_last = maccore_ethphy_liteethphygmiimiirx_source_source_last0; -assign preamble_checker_sink_payload_data = maccore_ethphy_liteethphygmiimiirx_source_source_payload_data0; -assign preamble_checker_sink_payload_last_be = maccore_ethphy_liteethphygmiimiirx_source_source_payload_last_be0; -assign preamble_checker_sink_payload_error = maccore_ethphy_liteethphygmiimiirx_source_source_payload_error0; -assign crc32_checker_sink_valid = preamble_checker_source_valid; -assign preamble_checker_source_ready = crc32_checker_sink_ready; -assign crc32_checker_sink_first = preamble_checker_source_first; -assign crc32_checker_sink_last = preamble_checker_source_last; -assign crc32_checker_sink_payload_data = preamble_checker_source_payload_data; -assign crc32_checker_sink_payload_last_be = preamble_checker_source_payload_last_be; -assign crc32_checker_sink_payload_error = preamble_checker_source_payload_error; -assign padding_checker_sink_valid = liteethmaccrc32checker_source_source_valid; -assign liteethmaccrc32checker_source_source_ready = padding_checker_sink_ready; -assign padding_checker_sink_first = liteethmaccrc32checker_source_source_first; -assign padding_checker_sink_last = liteethmaccrc32checker_source_source_last; -assign padding_checker_sink_payload_data = liteethmaccrc32checker_source_source_payload_data; -assign padding_checker_sink_payload_last_be = liteethmaccrc32checker_source_source_payload_last_be; -assign padding_checker_sink_payload_error = liteethmaccrc32checker_source_source_payload_error; -assign rx_last_be_sink_valid = padding_checker_source_valid; -assign padding_checker_source_ready = rx_last_be_sink_ready; -assign rx_last_be_sink_first = padding_checker_source_first; -assign rx_last_be_sink_last = padding_checker_source_last; -assign rx_last_be_sink_payload_data = padding_checker_source_payload_data; -assign rx_last_be_sink_payload_last_be = padding_checker_source_payload_last_be; -assign rx_last_be_sink_payload_error = padding_checker_source_payload_error; -assign rx_converter_sink_valid = rx_last_be_source_valid; -assign rx_last_be_source_ready = rx_converter_sink_ready; -assign rx_converter_sink_first = rx_last_be_source_first; -assign rx_converter_sink_last = rx_last_be_source_last; -assign rx_converter_sink_payload_data = rx_last_be_source_payload_data; -assign rx_converter_sink_payload_last_be = rx_last_be_source_payload_last_be; -assign rx_converter_sink_payload_error = rx_last_be_source_payload_error; -assign rx_cdc_sink_sink_valid = rx_converter_source_valid; -assign rx_converter_source_ready = rx_cdc_sink_sink_ready; -assign rx_cdc_sink_sink_first = rx_converter_source_first; -assign rx_cdc_sink_sink_last = rx_converter_source_last; -assign rx_cdc_sink_sink_payload_data = rx_converter_source_payload_data; -assign rx_cdc_sink_sink_payload_last_be = rx_converter_source_payload_last_be; -assign rx_cdc_sink_sink_payload_error = rx_converter_source_payload_error; -assign writer_sink_sink_valid = sink_valid; -assign sink_ready = writer_sink_sink_ready; -assign writer_sink_sink_first = sink_first; -assign writer_sink_sink_last = sink_last; -assign writer_sink_sink_payload_data = sink_payload_data; -assign writer_sink_sink_payload_last_be = sink_payload_last_be; -assign writer_sink_sink_payload_error = sink_payload_error; -assign source_valid = reader_source_source_valid; -assign reader_source_source_ready = source_ready; -assign source_first = reader_source_source_first; -assign source_last = reader_source_source_last; -assign source_payload_data = reader_source_source_payload_data; -assign source_payload_last_be = reader_source_source_payload_last_be; -assign source_payload_error = reader_source_source_payload_error; -always @(*) begin - writer_inc <= 3'd0; - case (writer_sink_sink_payload_last_be) - 1'd1: begin - writer_inc <= 1'd1; - end - 2'd2: begin - writer_inc <= 2'd2; - end - 3'd4: begin - writer_inc <= 2'd3; - end - default: begin - writer_inc <= 3'd4; - end - endcase -end -assign writer_stat_fifo_sink_payload_slot = writer_slot; -assign writer_stat_fifo_sink_payload_length = writer_counter; -assign writer_stat_fifo_source_ready = writer_available_clear; -assign writer_available_trigger = writer_stat_fifo_source_valid; -assign writer_slot_status = writer_stat_fifo_source_payload_slot; -assign writer_length_status = writer_stat_fifo_source_payload_length; -always @(*) begin - writer_memory1_adr <= 9'd0; - writer_memory1_we <= 1'd0; - writer_memory0_adr <= 9'd0; - writer_memory1_dat_w <= 32'd0; - writer_memory0_we <= 1'd0; - writer_memory0_dat_w <= 32'd0; - case (writer_slot) - 1'd0: begin - writer_memory0_adr <= writer_counter[31:2]; - writer_memory0_dat_w <= writer_sink_sink_payload_data; - if ((writer_sink_sink_valid & writer_ongoing)) begin - writer_memory0_we <= 4'd15; - end - end - 1'd1: begin - writer_memory1_adr <= writer_counter[31:2]; - writer_memory1_dat_w <= writer_sink_sink_payload_data; - if ((writer_sink_sink_valid & writer_ongoing)) begin - writer_memory1_we <= 4'd15; - end - end - endcase -end -assign writer_available0 = writer_available_status; -assign writer_available1 = writer_available_pending; -always @(*) begin - writer_available_clear <= 1'd0; - if ((writer_pending_re & writer_pending_r)) begin - writer_available_clear <= 1'd1; - end -end -assign writer_irq = (writer_pending_status & writer_enable_storage); -assign writer_available_status = writer_available_trigger; -assign writer_available_pending = writer_available_trigger; -assign writer_stat_fifo_syncfifo_din = {writer_stat_fifo_fifo_in_last, writer_stat_fifo_fifo_in_first, writer_stat_fifo_fifo_in_payload_length, writer_stat_fifo_fifo_in_payload_slot}; -assign {writer_stat_fifo_fifo_out_last, writer_stat_fifo_fifo_out_first, writer_stat_fifo_fifo_out_payload_length, writer_stat_fifo_fifo_out_payload_slot} = writer_stat_fifo_syncfifo_dout; -assign writer_stat_fifo_sink_ready = writer_stat_fifo_syncfifo_writable; -assign writer_stat_fifo_syncfifo_we = writer_stat_fifo_sink_valid; -assign writer_stat_fifo_fifo_in_first = writer_stat_fifo_sink_first; -assign writer_stat_fifo_fifo_in_last = writer_stat_fifo_sink_last; -assign writer_stat_fifo_fifo_in_payload_slot = writer_stat_fifo_sink_payload_slot; -assign writer_stat_fifo_fifo_in_payload_length = writer_stat_fifo_sink_payload_length; -assign writer_stat_fifo_source_valid = writer_stat_fifo_syncfifo_readable; -assign writer_stat_fifo_source_first = writer_stat_fifo_fifo_out_first; -assign writer_stat_fifo_source_last = writer_stat_fifo_fifo_out_last; -assign writer_stat_fifo_source_payload_slot = writer_stat_fifo_fifo_out_payload_slot; -assign writer_stat_fifo_source_payload_length = writer_stat_fifo_fifo_out_payload_length; -assign writer_stat_fifo_syncfifo_re = writer_stat_fifo_source_ready; -always @(*) begin - writer_stat_fifo_wrport_adr <= 1'd0; - if (writer_stat_fifo_replace) begin - writer_stat_fifo_wrport_adr <= (writer_stat_fifo_produce - 1'd1); - end else begin - writer_stat_fifo_wrport_adr <= writer_stat_fifo_produce; - end -end -assign writer_stat_fifo_wrport_dat_w = writer_stat_fifo_syncfifo_din; -assign writer_stat_fifo_wrport_we = (writer_stat_fifo_syncfifo_we & (writer_stat_fifo_syncfifo_writable | writer_stat_fifo_replace)); -assign writer_stat_fifo_do_read = (writer_stat_fifo_syncfifo_readable & writer_stat_fifo_syncfifo_re); -assign writer_stat_fifo_rdport_adr = writer_stat_fifo_consume; -assign writer_stat_fifo_syncfifo_dout = writer_stat_fifo_rdport_dat_r; -assign writer_stat_fifo_syncfifo_writable = (writer_stat_fifo_level != 2'd2); -assign writer_stat_fifo_syncfifo_readable = (writer_stat_fifo_level != 1'd0); -always @(*) begin - subfragments_liteethmacsramwriter_next_state <= 3'd0; - writer_counter_t_next_value <= 32'd0; - writer_counter_t_next_value_ce <= 1'd0; - writer_errors_status_f_next_value <= 32'd0; - writer_errors_status_f_next_value_ce <= 1'd0; - writer_slot_ce <= 1'd0; - writer_start <= 1'd0; - writer_ongoing <= 1'd0; - writer_stat_fifo_sink_valid <= 1'd0; - subfragments_liteethmacsramwriter_next_state <= subfragments_liteethmacsramwriter_state; - case (subfragments_liteethmacsramwriter_state) - 1'd1: begin - if (writer_sink_sink_valid) begin - if ((writer_counter == 11'd1530)) begin - subfragments_liteethmacsramwriter_next_state <= 2'd3; - end else begin - writer_counter_t_next_value <= (writer_counter + writer_inc); - writer_counter_t_next_value_ce <= 1'd1; - writer_ongoing <= 1'd1; - end - if (writer_sink_sink_last) begin - if (((writer_sink_sink_payload_error & writer_sink_sink_payload_last_be) != 1'd0)) begin - subfragments_liteethmacsramwriter_next_state <= 2'd2; - end else begin - subfragments_liteethmacsramwriter_next_state <= 3'd4; - end - end - end - end - 2'd2: begin - writer_counter_t_next_value <= 1'd0; - writer_counter_t_next_value_ce <= 1'd1; - subfragments_liteethmacsramwriter_next_state <= 1'd0; - end - 2'd3: begin - if ((writer_sink_sink_valid & writer_sink_sink_last)) begin - subfragments_liteethmacsramwriter_next_state <= 3'd4; - end - end - 3'd4: begin - writer_counter_t_next_value <= 1'd0; - writer_counter_t_next_value_ce <= 1'd1; - writer_slot_ce <= 1'd1; - writer_stat_fifo_sink_valid <= 1'd1; - subfragments_liteethmacsramwriter_next_state <= 1'd0; - end - default: begin - if (writer_sink_sink_valid) begin - if (writer_stat_fifo_sink_ready) begin - writer_start <= 1'd1; - writer_ongoing <= 1'd1; - writer_counter_t_next_value <= (writer_counter + writer_inc); - writer_counter_t_next_value_ce <= 1'd1; - subfragments_liteethmacsramwriter_next_state <= 1'd1; - end else begin - writer_errors_status_f_next_value <= (writer_errors_status + 1'd1); - writer_errors_status_f_next_value_ce <= 1'd1; - subfragments_liteethmacsramwriter_next_state <= 2'd3; - end - end - end - endcase -end -assign reader_cmd_fifo_sink_valid = reader_start_start_re; -assign reader_cmd_fifo_sink_payload_slot = reader_slot_storage; -assign reader_cmd_fifo_sink_payload_length = reader_length_storage; -assign reader_ready_status = reader_cmd_fifo_sink_ready; -assign reader_level_status = reader_cmd_fifo_level; -always @(*) begin - reader_source_source_payload_last_be <= 4'd0; - if (reader_source_source_last) begin - case (reader_cmd_fifo_source_payload_length[1:0]) - 1'd0: begin - reader_source_source_payload_last_be <= 4'd8; - end - 1'd1: begin - reader_source_source_payload_last_be <= 1'd1; - end - 2'd2: begin - reader_source_source_payload_last_be <= 2'd2; - end - 2'd3: begin - reader_source_source_payload_last_be <= 3'd4; - end - endcase - end -end -assign reader_memory0_adr = reader_read_address[10:2]; -assign reader_memory1_adr = reader_read_address[10:2]; -always @(*) begin - reader_source_source_payload_data <= 32'd0; - case (reader_cmd_fifo_source_payload_slot) - 1'd0: begin - reader_source_source_payload_data <= reader_memory0_dat_r; - end - 1'd1: begin - reader_source_source_payload_data <= reader_memory1_dat_r; - end - endcase -end -assign reader_event00 = reader_eventsourcepulse_status; -assign reader_event01 = reader_eventsourcepulse_pending; -always @(*) begin - reader_eventsourcepulse_clear <= 1'd0; - if ((reader_pending_re & reader_pending_r)) begin - reader_eventsourcepulse_clear <= 1'd1; - end -end -assign reader_irq = (reader_pending_status & reader_enable_storage); -assign reader_eventsourcepulse_status = 1'd0; -assign reader_cmd_fifo_syncfifo_din = {reader_cmd_fifo_fifo_in_last, reader_cmd_fifo_fifo_in_first, reader_cmd_fifo_fifo_in_payload_length, reader_cmd_fifo_fifo_in_payload_slot}; -assign {reader_cmd_fifo_fifo_out_last, reader_cmd_fifo_fifo_out_first, reader_cmd_fifo_fifo_out_payload_length, reader_cmd_fifo_fifo_out_payload_slot} = reader_cmd_fifo_syncfifo_dout; -assign reader_cmd_fifo_sink_ready = reader_cmd_fifo_syncfifo_writable; -assign reader_cmd_fifo_syncfifo_we = reader_cmd_fifo_sink_valid; -assign reader_cmd_fifo_fifo_in_first = reader_cmd_fifo_sink_first; -assign reader_cmd_fifo_fifo_in_last = reader_cmd_fifo_sink_last; -assign reader_cmd_fifo_fifo_in_payload_slot = reader_cmd_fifo_sink_payload_slot; -assign reader_cmd_fifo_fifo_in_payload_length = reader_cmd_fifo_sink_payload_length; -assign reader_cmd_fifo_source_valid = reader_cmd_fifo_syncfifo_readable; -assign reader_cmd_fifo_source_first = reader_cmd_fifo_fifo_out_first; -assign reader_cmd_fifo_source_last = reader_cmd_fifo_fifo_out_last; -assign reader_cmd_fifo_source_payload_slot = reader_cmd_fifo_fifo_out_payload_slot; -assign reader_cmd_fifo_source_payload_length = reader_cmd_fifo_fifo_out_payload_length; -assign reader_cmd_fifo_syncfifo_re = reader_cmd_fifo_source_ready; -always @(*) begin - reader_cmd_fifo_wrport_adr <= 1'd0; - if (reader_cmd_fifo_replace) begin - reader_cmd_fifo_wrport_adr <= (reader_cmd_fifo_produce - 1'd1); - end else begin - reader_cmd_fifo_wrport_adr <= reader_cmd_fifo_produce; - end -end -assign reader_cmd_fifo_wrport_dat_w = reader_cmd_fifo_syncfifo_din; -assign reader_cmd_fifo_wrport_we = (reader_cmd_fifo_syncfifo_we & (reader_cmd_fifo_syncfifo_writable | reader_cmd_fifo_replace)); -assign reader_cmd_fifo_do_read = (reader_cmd_fifo_syncfifo_readable & reader_cmd_fifo_syncfifo_re); -assign reader_cmd_fifo_rdport_adr = reader_cmd_fifo_consume; -assign reader_cmd_fifo_syncfifo_dout = reader_cmd_fifo_rdport_dat_r; -assign reader_cmd_fifo_syncfifo_writable = (reader_cmd_fifo_level != 2'd2); -assign reader_cmd_fifo_syncfifo_readable = (reader_cmd_fifo_level != 1'd0); -always @(*) begin - reader_cmd_fifo_source_ready <= 1'd0; - reader_eventsourcepulse_trigger <= 1'd0; - subfragments_liteethmacsramreader_next_state <= 2'd0; - reader_counter_next_value <= 11'd0; - reader_counter_next_value_ce <= 1'd0; - reader_source_source_valid <= 1'd0; - reader_start <= 1'd0; - reader_source_source_last <= 1'd0; - reader_read_address <= 11'd0; - subfragments_liteethmacsramreader_next_state <= subfragments_liteethmacsramreader_state; - case (subfragments_liteethmacsramreader_state) - 1'd1: begin - reader_source_source_valid <= 1'd1; - reader_source_source_last <= (reader_counter >= (reader_cmd_fifo_source_payload_length - 3'd4)); - reader_read_address <= reader_counter; - if (reader_source_source_ready) begin - reader_read_address <= (reader_counter + 3'd4); - reader_counter_next_value <= (reader_counter + 3'd4); - reader_counter_next_value_ce <= 1'd1; - if (reader_source_source_last) begin - subfragments_liteethmacsramreader_next_state <= 2'd2; - end - end - end - 2'd2: begin - reader_eventsourcepulse_trigger <= 1'd1; - reader_cmd_fifo_source_ready <= 1'd1; - subfragments_liteethmacsramreader_next_state <= 1'd0; - end - default: begin - reader_counter_next_value <= 1'd0; - reader_counter_next_value_ce <= 1'd1; - if (reader_cmd_fifo_source_valid) begin - reader_start <= 1'd1; - subfragments_liteethmacsramreader_next_state <= 1'd1; - end - end - endcase -end -assign ev_irq = (writer_irq | reader_irq); -assign sram0_adr0 = sram0_bus_adr0[8:0]; -assign sram0_bus_dat_r0 = sram0_dat_r0; -assign sram1_adr0 = sram1_bus_adr0[8:0]; -assign sram1_bus_dat_r0 = sram1_dat_r0; -always @(*) begin - sram0_we <= 4'd0; - sram0_we[0] <= (((sram0_bus_cyc1 & sram0_bus_stb1) & sram0_bus_we1) & sram0_bus_sel1[0]); - sram0_we[1] <= (((sram0_bus_cyc1 & sram0_bus_stb1) & sram0_bus_we1) & sram0_bus_sel1[1]); - sram0_we[2] <= (((sram0_bus_cyc1 & sram0_bus_stb1) & sram0_bus_we1) & sram0_bus_sel1[2]); - sram0_we[3] <= (((sram0_bus_cyc1 & sram0_bus_stb1) & sram0_bus_we1) & sram0_bus_sel1[3]); -end -assign sram0_adr1 = sram0_bus_adr1[8:0]; -assign sram0_bus_dat_r1 = sram0_dat_r1; -assign sram0_dat_w = sram0_bus_dat_w1; -always @(*) begin - sram1_we <= 4'd0; - sram1_we[0] <= (((sram1_bus_cyc1 & sram1_bus_stb1) & sram1_bus_we1) & sram1_bus_sel1[0]); - sram1_we[1] <= (((sram1_bus_cyc1 & sram1_bus_stb1) & sram1_bus_we1) & sram1_bus_sel1[1]); - sram1_we[2] <= (((sram1_bus_cyc1 & sram1_bus_stb1) & sram1_bus_we1) & sram1_bus_sel1[2]); - sram1_we[3] <= (((sram1_bus_cyc1 & sram1_bus_stb1) & sram1_bus_we1) & sram1_bus_sel1[3]); -end -assign sram1_adr1 = sram1_bus_adr1[8:0]; -assign sram1_bus_dat_r1 = sram1_dat_r1; -assign sram1_dat_w = sram1_bus_dat_w1; -always @(*) begin - slave_sel <= 4'd0; - slave_sel[0] <= (bus_adr[10:9] == 1'd0); - slave_sel[1] <= (bus_adr[10:9] == 1'd1); - slave_sel[2] <= (bus_adr[10:9] == 2'd2); - slave_sel[3] <= (bus_adr[10:9] == 2'd3); -end -assign sram0_bus_adr0 = bus_adr; -assign sram0_bus_dat_w0 = bus_dat_w; -assign sram0_bus_sel0 = bus_sel; -assign sram0_bus_stb0 = bus_stb; -assign sram0_bus_we0 = bus_we; -assign sram0_bus_cti0 = bus_cti; -assign sram0_bus_bte0 = bus_bte; -assign sram1_bus_adr0 = bus_adr; -assign sram1_bus_dat_w0 = bus_dat_w; -assign sram1_bus_sel0 = bus_sel; -assign sram1_bus_stb0 = bus_stb; -assign sram1_bus_we0 = bus_we; -assign sram1_bus_cti0 = bus_cti; -assign sram1_bus_bte0 = bus_bte; -assign sram0_bus_adr1 = bus_adr; -assign sram0_bus_dat_w1 = bus_dat_w; -assign sram0_bus_sel1 = bus_sel; -assign sram0_bus_stb1 = bus_stb; -assign sram0_bus_we1 = bus_we; -assign sram0_bus_cti1 = bus_cti; -assign sram0_bus_bte1 = bus_bte; -assign sram1_bus_adr1 = bus_adr; -assign sram1_bus_dat_w1 = bus_dat_w; -assign sram1_bus_sel1 = bus_sel; -assign sram1_bus_stb1 = bus_stb; -assign sram1_bus_we1 = bus_we; -assign sram1_bus_cti1 = bus_cti; -assign sram1_bus_bte1 = bus_bte; -assign sram0_bus_cyc0 = (bus_cyc & slave_sel[0]); -assign sram1_bus_cyc0 = (bus_cyc & slave_sel[1]); -assign sram0_bus_cyc1 = (bus_cyc & slave_sel[2]); -assign sram1_bus_cyc1 = (bus_cyc & slave_sel[3]); -assign bus_ack = (((sram0_bus_ack0 | sram1_bus_ack0) | sram0_bus_ack1) | sram1_bus_ack1); -assign bus_err = (((sram0_bus_err0 | sram1_bus_err0) | sram0_bus_err1) | sram1_bus_err1); -assign bus_dat_r = (((({32{slave_sel_r[0]}} & sram0_bus_dat_r0) | ({32{slave_sel_r[1]}} & sram1_bus_dat_r0)) | ({32{slave_sel_r[2]}} & sram0_bus_dat_r1)) | ({32{slave_sel_r[3]}} & sram1_bus_dat_r1)); -always @(*) begin - maccore_maccore_we <= 1'd0; - maccore_maccore_dat_w <= 32'd0; - maccore_maccore_wishbone_ack <= 1'd0; - maccore_next_state <= 1'd0; - maccore_maccore_wishbone_dat_r <= 32'd0; - maccore_maccore_adr <= 14'd0; - maccore_next_state <= maccore_state; - case (maccore_state) - 1'd1: begin - maccore_maccore_wishbone_ack <= 1'd1; - maccore_maccore_wishbone_dat_r <= maccore_maccore_dat_r; - maccore_next_state <= 1'd0; - end - default: begin - maccore_maccore_dat_w <= maccore_maccore_wishbone_dat_w; - if ((maccore_maccore_wishbone_cyc & maccore_maccore_wishbone_stb)) begin - maccore_maccore_adr <= maccore_maccore_wishbone_adr; - maccore_maccore_we <= (maccore_maccore_wishbone_we & (maccore_maccore_wishbone_sel != 1'd0)); - maccore_next_state <= 1'd1; - end - end - endcase -end -assign maccore_shared_adr = array_muxed0; -assign maccore_shared_dat_w = array_muxed1; -assign maccore_shared_sel = array_muxed2; -assign maccore_shared_cyc = array_muxed3; -assign maccore_shared_stb = array_muxed4; -assign maccore_shared_we = array_muxed5; -assign maccore_shared_cti = array_muxed6; -assign maccore_shared_bte = array_muxed7; -assign wb_bus_dat_r = maccore_shared_dat_r; -assign wb_bus_ack = (maccore_shared_ack & (maccore_grant == 1'd0)); -assign wb_bus_err = (maccore_shared_err & (maccore_grant == 1'd0)); -assign maccore_request = {wb_bus_cyc}; -assign maccore_grant = 1'd0; -always @(*) begin - maccore_slave_sel <= 2'd0; - maccore_slave_sel[0] <= (maccore_shared_adr[29:11] == 4'd8); - maccore_slave_sel[1] <= (maccore_shared_adr[29:14] == 1'd0); -end -assign bus_adr = maccore_shared_adr; -assign bus_dat_w = maccore_shared_dat_w; -assign bus_sel = maccore_shared_sel; -assign bus_stb = maccore_shared_stb; -assign bus_we = maccore_shared_we; -assign bus_cti = maccore_shared_cti; -assign bus_bte = maccore_shared_bte; -assign maccore_maccore_wishbone_adr = maccore_shared_adr; -assign maccore_maccore_wishbone_dat_w = maccore_shared_dat_w; -assign maccore_maccore_wishbone_sel = maccore_shared_sel; -assign maccore_maccore_wishbone_stb = maccore_shared_stb; -assign maccore_maccore_wishbone_we = maccore_shared_we; -assign maccore_maccore_wishbone_cti = maccore_shared_cti; -assign maccore_maccore_wishbone_bte = maccore_shared_bte; -assign bus_cyc = (maccore_shared_cyc & maccore_slave_sel[0]); -assign maccore_maccore_wishbone_cyc = (maccore_shared_cyc & maccore_slave_sel[1]); -assign maccore_shared_err = (bus_err | maccore_maccore_wishbone_err); -assign maccore_wait = ((maccore_shared_stb & maccore_shared_cyc) & (~maccore_shared_ack)); -always @(*) begin - maccore_error <= 1'd0; - maccore_shared_dat_r <= 32'd0; - maccore_shared_ack <= 1'd0; - maccore_shared_ack <= (bus_ack | maccore_maccore_wishbone_ack); - maccore_shared_dat_r <= (({32{maccore_slave_sel_r[0]}} & bus_dat_r) | ({32{maccore_slave_sel_r[1]}} & maccore_maccore_wishbone_dat_r)); - if (maccore_done) begin - maccore_shared_dat_r <= 32'd4294967295; - maccore_shared_ack <= 1'd1; - maccore_error <= 1'd1; - end -end -assign maccore_done = (maccore_count == 1'd0); -assign maccore_csrbank0_sel = (maccore_interface0_bank_bus_adr[13:9] == 1'd0); -assign maccore_csrbank0_reset0_r = maccore_interface0_bank_bus_dat_w[1:0]; -always @(*) begin - maccore_csrbank0_reset0_re <= 1'd0; - maccore_csrbank0_reset0_we <= 1'd0; - if ((maccore_csrbank0_sel & (maccore_interface0_bank_bus_adr[8:0] == 1'd0))) begin - maccore_csrbank0_reset0_re <= maccore_interface0_bank_bus_we; - maccore_csrbank0_reset0_we <= (~maccore_interface0_bank_bus_we); - end -end -assign maccore_csrbank0_scratch0_r = maccore_interface0_bank_bus_dat_w[31:0]; -always @(*) begin - maccore_csrbank0_scratch0_re <= 1'd0; - maccore_csrbank0_scratch0_we <= 1'd0; - if ((maccore_csrbank0_sel & (maccore_interface0_bank_bus_adr[8:0] == 1'd1))) begin - maccore_csrbank0_scratch0_re <= maccore_interface0_bank_bus_we; - maccore_csrbank0_scratch0_we <= (~maccore_interface0_bank_bus_we); - end -end -assign maccore_csrbank0_bus_errors_r = maccore_interface0_bank_bus_dat_w[31:0]; -always @(*) begin - maccore_csrbank0_bus_errors_we <= 1'd0; - maccore_csrbank0_bus_errors_re <= 1'd0; - if ((maccore_csrbank0_sel & (maccore_interface0_bank_bus_adr[8:0] == 2'd2))) begin - maccore_csrbank0_bus_errors_re <= maccore_interface0_bank_bus_we; - maccore_csrbank0_bus_errors_we <= (~maccore_interface0_bank_bus_we); - end -end -always @(*) begin - maccore_maccore_soc_rst <= 1'd0; - if (maccore_maccore_reset_re) begin - maccore_maccore_soc_rst <= maccore_maccore_reset_storage[0]; - end -end -assign maccore_maccore_cpu_rst = maccore_maccore_reset_storage[1]; -assign maccore_csrbank0_reset0_w = maccore_maccore_reset_storage[1:0]; -assign maccore_csrbank0_scratch0_w = maccore_maccore_scratch_storage[31:0]; -assign maccore_csrbank0_bus_errors_w = maccore_maccore_bus_errors_status[31:0]; -assign maccore_maccore_bus_errors_we = maccore_csrbank0_bus_errors_we; -assign maccore_csrbank1_sel = (maccore_interface1_bank_bus_adr[13:9] == 2'd2); -assign maccore_csrbank1_sram_writer_slot_r = maccore_interface1_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank1_sram_writer_slot_we <= 1'd0; - maccore_csrbank1_sram_writer_slot_re <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 1'd0))) begin - maccore_csrbank1_sram_writer_slot_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_writer_slot_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_writer_length_r = maccore_interface1_bank_bus_dat_w[31:0]; -always @(*) begin - maccore_csrbank1_sram_writer_length_we <= 1'd0; - maccore_csrbank1_sram_writer_length_re <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 1'd1))) begin - maccore_csrbank1_sram_writer_length_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_writer_length_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_writer_errors_r = maccore_interface1_bank_bus_dat_w[31:0]; -always @(*) begin - maccore_csrbank1_sram_writer_errors_re <= 1'd0; - maccore_csrbank1_sram_writer_errors_we <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 2'd2))) begin - maccore_csrbank1_sram_writer_errors_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_writer_errors_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_writer_ev_status_r = maccore_interface1_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank1_sram_writer_ev_status_re <= 1'd0; - maccore_csrbank1_sram_writer_ev_status_we <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 2'd3))) begin - maccore_csrbank1_sram_writer_ev_status_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_writer_ev_status_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_writer_ev_pending_r = maccore_interface1_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank1_sram_writer_ev_pending_we <= 1'd0; - maccore_csrbank1_sram_writer_ev_pending_re <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 3'd4))) begin - maccore_csrbank1_sram_writer_ev_pending_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_writer_ev_pending_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_writer_ev_enable0_r = maccore_interface1_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank1_sram_writer_ev_enable0_we <= 1'd0; - maccore_csrbank1_sram_writer_ev_enable0_re <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 3'd5))) begin - maccore_csrbank1_sram_writer_ev_enable0_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_writer_ev_enable0_we <= (~maccore_interface1_bank_bus_we); - end -end -assign reader_start_start_r = maccore_interface1_bank_bus_dat_w[0]; -always @(*) begin - reader_start_start_re <= 1'd0; - reader_start_start_we <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 3'd6))) begin - reader_start_start_re <= maccore_interface1_bank_bus_we; - reader_start_start_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_reader_ready_r = maccore_interface1_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank1_sram_reader_ready_re <= 1'd0; - maccore_csrbank1_sram_reader_ready_we <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 3'd7))) begin - maccore_csrbank1_sram_reader_ready_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_reader_ready_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_reader_level_r = maccore_interface1_bank_bus_dat_w[1:0]; -always @(*) begin - maccore_csrbank1_sram_reader_level_we <= 1'd0; - maccore_csrbank1_sram_reader_level_re <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd8))) begin - maccore_csrbank1_sram_reader_level_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_reader_level_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_reader_slot0_r = maccore_interface1_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank1_sram_reader_slot0_we <= 1'd0; - maccore_csrbank1_sram_reader_slot0_re <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd9))) begin - maccore_csrbank1_sram_reader_slot0_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_reader_slot0_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_reader_length0_r = maccore_interface1_bank_bus_dat_w[10:0]; -always @(*) begin - maccore_csrbank1_sram_reader_length0_re <= 1'd0; - maccore_csrbank1_sram_reader_length0_we <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd10))) begin - maccore_csrbank1_sram_reader_length0_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_reader_length0_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_reader_ev_status_r = maccore_interface1_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank1_sram_reader_ev_status_we <= 1'd0; - maccore_csrbank1_sram_reader_ev_status_re <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd11))) begin - maccore_csrbank1_sram_reader_ev_status_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_reader_ev_status_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_reader_ev_pending_r = maccore_interface1_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank1_sram_reader_ev_pending_we <= 1'd0; - maccore_csrbank1_sram_reader_ev_pending_re <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd12))) begin - maccore_csrbank1_sram_reader_ev_pending_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_reader_ev_pending_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_reader_ev_enable0_r = maccore_interface1_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank1_sram_reader_ev_enable0_re <= 1'd0; - maccore_csrbank1_sram_reader_ev_enable0_we <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd13))) begin - maccore_csrbank1_sram_reader_ev_enable0_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_reader_ev_enable0_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_preamble_crc_r = maccore_interface1_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank1_preamble_crc_we <= 1'd0; - maccore_csrbank1_preamble_crc_re <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd14))) begin - maccore_csrbank1_preamble_crc_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_preamble_crc_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_preamble_errors_r = maccore_interface1_bank_bus_dat_w[31:0]; -always @(*) begin - maccore_csrbank1_preamble_errors_we <= 1'd0; - maccore_csrbank1_preamble_errors_re <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd15))) begin - maccore_csrbank1_preamble_errors_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_preamble_errors_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_crc_errors_r = maccore_interface1_bank_bus_dat_w[31:0]; -always @(*) begin - maccore_csrbank1_crc_errors_re <= 1'd0; - maccore_csrbank1_crc_errors_we <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 5'd16))) begin - maccore_csrbank1_crc_errors_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_crc_errors_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_writer_slot_w = writer_slot_status; -assign writer_slot_we = maccore_csrbank1_sram_writer_slot_we; -assign maccore_csrbank1_sram_writer_length_w = writer_length_status[31:0]; -assign writer_length_we = maccore_csrbank1_sram_writer_length_we; -assign maccore_csrbank1_sram_writer_errors_w = writer_errors_status[31:0]; -assign writer_errors_we = maccore_csrbank1_sram_writer_errors_we; -assign writer_status_status = writer_available0; -assign maccore_csrbank1_sram_writer_ev_status_w = writer_status_status; -assign writer_status_we = maccore_csrbank1_sram_writer_ev_status_we; -assign writer_pending_status = writer_available1; -assign maccore_csrbank1_sram_writer_ev_pending_w = writer_pending_status; -assign writer_pending_we = maccore_csrbank1_sram_writer_ev_pending_we; -assign writer_available2 = writer_enable_storage; -assign maccore_csrbank1_sram_writer_ev_enable0_w = writer_enable_storage; -assign maccore_csrbank1_sram_reader_ready_w = reader_ready_status; -assign reader_ready_we = maccore_csrbank1_sram_reader_ready_we; -assign maccore_csrbank1_sram_reader_level_w = reader_level_status[1:0]; -assign reader_level_we = maccore_csrbank1_sram_reader_level_we; -assign maccore_csrbank1_sram_reader_slot0_w = reader_slot_storage; -assign maccore_csrbank1_sram_reader_length0_w = reader_length_storage[10:0]; -assign reader_status_status = reader_event00; -assign maccore_csrbank1_sram_reader_ev_status_w = reader_status_status; -assign reader_status_we = maccore_csrbank1_sram_reader_ev_status_we; -assign reader_pending_status = reader_event01; -assign maccore_csrbank1_sram_reader_ev_pending_w = reader_pending_status; -assign reader_pending_we = maccore_csrbank1_sram_reader_ev_pending_we; -assign reader_event02 = reader_enable_storage; -assign maccore_csrbank1_sram_reader_ev_enable0_w = reader_enable_storage; -assign maccore_csrbank1_preamble_crc_w = preamble_crc_status; -assign preamble_crc_we = maccore_csrbank1_preamble_crc_we; -assign maccore_csrbank1_preamble_errors_w = preamble_errors_status[31:0]; -assign preamble_errors_we = maccore_csrbank1_preamble_errors_we; -assign maccore_csrbank1_crc_errors_w = crc_errors_status[31:0]; -assign crc_errors_we = maccore_csrbank1_crc_errors_we; -assign maccore_csrbank2_sel = (maccore_interface2_bank_bus_adr[13:9] == 1'd1); -assign maccore_csrbank2_mode_detection_mode_r = maccore_interface2_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank2_mode_detection_mode_re <= 1'd0; - maccore_csrbank2_mode_detection_mode_we <= 1'd0; - if ((maccore_csrbank2_sel & (maccore_interface2_bank_bus_adr[8:0] == 1'd0))) begin - maccore_csrbank2_mode_detection_mode_re <= maccore_interface2_bank_bus_we; - maccore_csrbank2_mode_detection_mode_we <= (~maccore_interface2_bank_bus_we); - end -end -assign maccore_csrbank2_crg_reset0_r = maccore_interface2_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank2_crg_reset0_re <= 1'd0; - maccore_csrbank2_crg_reset0_we <= 1'd0; - if ((maccore_csrbank2_sel & (maccore_interface2_bank_bus_adr[8:0] == 1'd1))) begin - maccore_csrbank2_crg_reset0_re <= maccore_interface2_bank_bus_we; - maccore_csrbank2_crg_reset0_we <= (~maccore_interface2_bank_bus_we); - end -end -assign maccore_csrbank2_mdio_w0_r = maccore_interface2_bank_bus_dat_w[2:0]; -always @(*) begin - maccore_csrbank2_mdio_w0_we <= 1'd0; - maccore_csrbank2_mdio_w0_re <= 1'd0; - if ((maccore_csrbank2_sel & (maccore_interface2_bank_bus_adr[8:0] == 2'd2))) begin - maccore_csrbank2_mdio_w0_re <= maccore_interface2_bank_bus_we; - maccore_csrbank2_mdio_w0_we <= (~maccore_interface2_bank_bus_we); - end -end -assign maccore_csrbank2_mdio_r_r = maccore_interface2_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank2_mdio_r_re <= 1'd0; - maccore_csrbank2_mdio_r_we <= 1'd0; - if ((maccore_csrbank2_sel & (maccore_interface2_bank_bus_adr[8:0] == 2'd3))) begin - maccore_csrbank2_mdio_r_re <= maccore_interface2_bank_bus_we; - maccore_csrbank2_mdio_r_we <= (~maccore_interface2_bank_bus_we); - end -end -assign maccore_csrbank2_mode_detection_mode_w = maccore_ethphy_mode_status; -assign maccore_ethphy_mode_we = maccore_csrbank2_mode_detection_mode_we; -assign maccore_csrbank2_crg_reset0_w = maccore_ethphy_reset_storage; -assign maccore_ethphy_mdc = maccore_ethphy__w_storage[0]; -assign maccore_ethphy_oe = maccore_ethphy__w_storage[1]; -assign maccore_ethphy_w = maccore_ethphy__w_storage[2]; -assign maccore_csrbank2_mdio_w0_w = maccore_ethphy__w_storage[2:0]; -assign maccore_csrbank2_mdio_r_w = maccore_ethphy__r_status; -assign maccore_ethphy__r_we = maccore_csrbank2_mdio_r_we; -assign maccore_csr_interconnect_adr = maccore_maccore_adr; -assign maccore_csr_interconnect_we = maccore_maccore_we; -assign maccore_csr_interconnect_dat_w = maccore_maccore_dat_w; -assign maccore_maccore_dat_r = maccore_csr_interconnect_dat_r; -assign maccore_interface0_bank_bus_adr = maccore_csr_interconnect_adr; -assign maccore_interface1_bank_bus_adr = maccore_csr_interconnect_adr; -assign maccore_interface2_bank_bus_adr = maccore_csr_interconnect_adr; -assign maccore_interface0_bank_bus_we = maccore_csr_interconnect_we; -assign maccore_interface1_bank_bus_we = maccore_csr_interconnect_we; -assign maccore_interface2_bank_bus_we = maccore_csr_interconnect_we; -assign maccore_interface0_bank_bus_dat_w = maccore_csr_interconnect_dat_w; -assign maccore_interface1_bank_bus_dat_w = maccore_csr_interconnect_dat_w; -assign maccore_interface2_bank_bus_dat_w = maccore_csr_interconnect_dat_w; -assign maccore_csr_interconnect_dat_r = ((maccore_interface0_bank_bus_dat_r | maccore_interface1_bank_bus_dat_r) | maccore_interface2_bank_bus_dat_r); -always @(*) begin - array_muxed0 <= 30'd0; - case (maccore_grant) - default: begin - array_muxed0 <= wb_bus_adr; - end - endcase -end -always @(*) begin - array_muxed1 <= 32'd0; - case (maccore_grant) - default: begin - array_muxed1 <= wb_bus_dat_w; - end - endcase -end -always @(*) begin - array_muxed2 <= 4'd0; - case (maccore_grant) - default: begin - array_muxed2 <= wb_bus_sel; - end - endcase -end -always @(*) begin - array_muxed3 <= 1'd0; - case (maccore_grant) - default: begin - array_muxed3 <= wb_bus_cyc; - end - endcase -end -always @(*) begin - array_muxed4 <= 1'd0; - case (maccore_grant) - default: begin - array_muxed4 <= wb_bus_stb; - end - endcase -end -always @(*) begin - array_muxed5 <= 1'd0; - case (maccore_grant) - default: begin - array_muxed5 <= wb_bus_we; - end - endcase -end -always @(*) begin - array_muxed6 <= 3'd0; - case (maccore_grant) - default: begin - array_muxed6 <= wb_bus_cti; - end - endcase -end -always @(*) begin - array_muxed7 <= 2'd0; - case (maccore_grant) - default: begin - array_muxed7 <= wb_bus_bte; - end - endcase -end -assign maccore_ethphy_toggle_o = xilinxmultiregimpl0_regs1; -always @(*) begin - maccore_ethphy__r_status <= 1'd0; - maccore_ethphy__r_status <= maccore_ethphy_r; - maccore_ethphy__r_status <= xilinxmultiregimpl1_regs1; -end -assign ps_preamble_error_toggle_o = xilinxmultiregimpl2_regs1; -assign ps_crc_error_toggle_o = xilinxmultiregimpl3_regs1; -assign tx_cdc_cdc_produce_rdomain = xilinxmultiregimpl4_regs1; -assign tx_cdc_cdc_consume_wdomain = xilinxmultiregimpl5_regs1; -assign rx_cdc_cdc_produce_rdomain = xilinxmultiregimpl6_regs1; -assign rx_cdc_cdc_consume_wdomain = xilinxmultiregimpl7_regs1; +assign sys_rst = main_maccore_int_rst; +assign main_maccore_ethphy_mode_status = main_maccore_ethphy_mode0; +assign main_maccore_ethphy_eth_tick = (main_maccore_ethphy_eth_counter == 1'd0); +assign main_maccore_ethphy_i = main_maccore_ethphy_eth_tick; +assign main_maccore_ethphy_sys_tick = main_maccore_ethphy_o; +assign main_maccore_ethphy_o = (main_maccore_ethphy_toggle_o ^ main_maccore_ethphy_toggle_o_r); +always @(*) begin + builder_liteethphygmiimii_next_state <= 2'd0; + main_maccore_ethphy_mode1 <= 1'd0; + main_maccore_ethphy_sys_counter_ce <= 1'd0; + main_maccore_ethphy_sys_counter_reset <= 1'd0; + main_maccore_ethphy_update_mode <= 1'd0; + builder_liteethphygmiimii_next_state <= builder_liteethphygmiimii_state; + case (builder_liteethphygmiimii_state) + 1'd1: begin + main_maccore_ethphy_sys_counter_ce <= 1'd1; + if (main_maccore_ethphy_sys_tick) begin + builder_liteethphygmiimii_next_state <= 2'd2; + end + end + 2'd2: begin + main_maccore_ethphy_update_mode <= 1'd1; + if ((main_maccore_ethphy_sys_counter > 10'd860)) begin + main_maccore_ethphy_mode1 <= 1'd1; + end else begin + main_maccore_ethphy_mode1 <= 1'd0; + end + builder_liteethphygmiimii_next_state <= 1'd0; + end + default: begin + main_maccore_ethphy_sys_counter_reset <= 1'd1; + if (main_maccore_ethphy_sys_tick) begin + builder_liteethphygmiimii_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + main_maccore_ethphy_eth_tx_clk <= 1'd0; + if ((main_maccore_ethphy_mode0 == 1'd1)) begin + main_maccore_ethphy_eth_tx_clk <= gmii_clocks_tx; + end else begin + main_maccore_ethphy_eth_tx_clk <= gmii_clocks_rx; + end +end +assign main_maccore_ethphy_reset0 = (main_maccore_ethphy_reset_storage | main_maccore_ethphy_reset1); +assign gmii_rst_n = (~main_maccore_ethphy_reset0); +assign main_maccore_ethphy_counter_done = (main_maccore_ethphy_counter == 9'd256); +assign main_maccore_ethphy_counter_ce = (~main_maccore_ethphy_counter_done); +assign main_maccore_ethphy_reset1 = (~main_maccore_ethphy_counter_done); +assign main_maccore_ethphy_demux_sel = (main_maccore_ethphy_mode0 == 1'd1); +assign main_maccore_ethphy_demux_sink_valid = main_maccore_ethphy_sink_sink_valid; +assign main_maccore_ethphy_sink_sink_ready = main_maccore_ethphy_demux_sink_ready; +assign main_maccore_ethphy_demux_sink_first = main_maccore_ethphy_sink_sink_first; +assign main_maccore_ethphy_demux_sink_last = main_maccore_ethphy_sink_sink_last; +assign main_maccore_ethphy_demux_sink_payload_data = main_maccore_ethphy_sink_sink_payload_data; +assign main_maccore_ethphy_demux_sink_payload_last_be = main_maccore_ethphy_sink_sink_payload_last_be; +assign main_maccore_ethphy_demux_sink_payload_error = main_maccore_ethphy_sink_sink_payload_error; +assign main_maccore_ethphy_gmii_tx_sink_valid = main_maccore_ethphy_demux_endpoint0_source_valid; +assign main_maccore_ethphy_demux_endpoint0_source_ready = main_maccore_ethphy_gmii_tx_sink_ready; +assign main_maccore_ethphy_gmii_tx_sink_first = main_maccore_ethphy_demux_endpoint0_source_first; +assign main_maccore_ethphy_gmii_tx_sink_last = main_maccore_ethphy_demux_endpoint0_source_last; +assign main_maccore_ethphy_gmii_tx_sink_payload_data = main_maccore_ethphy_demux_endpoint0_source_payload_data; +assign main_maccore_ethphy_gmii_tx_sink_payload_last_be = main_maccore_ethphy_demux_endpoint0_source_payload_last_be; +assign main_maccore_ethphy_gmii_tx_sink_payload_error = main_maccore_ethphy_demux_endpoint0_source_payload_error; +assign main_maccore_ethphy_mii_tx_sink_valid = main_maccore_ethphy_demux_endpoint1_source_valid; +assign main_maccore_ethphy_demux_endpoint1_source_ready = main_maccore_ethphy_mii_tx_sink_ready; +assign main_maccore_ethphy_mii_tx_sink_first = main_maccore_ethphy_demux_endpoint1_source_first; +assign main_maccore_ethphy_mii_tx_sink_last = main_maccore_ethphy_demux_endpoint1_source_last; +assign main_maccore_ethphy_mii_tx_sink_payload_data = main_maccore_ethphy_demux_endpoint1_source_payload_data; +assign main_maccore_ethphy_mii_tx_sink_payload_last_be = main_maccore_ethphy_demux_endpoint1_source_payload_last_be; +assign main_maccore_ethphy_mii_tx_sink_payload_error = main_maccore_ethphy_demux_endpoint1_source_payload_error; +assign gmii_tx_er = 1'd0; +assign main_maccore_ethphy_mii_tx_converter_sink_valid = main_maccore_ethphy_mii_tx_sink_valid; +assign main_maccore_ethphy_mii_tx_converter_sink_payload_data = main_maccore_ethphy_mii_tx_sink_payload_data; +assign main_maccore_ethphy_mii_tx_sink_ready = main_maccore_ethphy_mii_tx_converter_sink_ready; +assign main_maccore_ethphy_mii_tx_source_source_ready = 1'd1; +assign main_maccore_ethphy_mii_tx_source_source_valid = main_maccore_ethphy_mii_tx_converter_source_valid; +assign main_maccore_ethphy_mii_tx_converter_source_ready = main_maccore_ethphy_mii_tx_source_source_ready; +assign main_maccore_ethphy_mii_tx_source_source_first = main_maccore_ethphy_mii_tx_converter_source_first; +assign main_maccore_ethphy_mii_tx_source_source_last = main_maccore_ethphy_mii_tx_converter_source_last; +assign main_maccore_ethphy_mii_tx_source_source_payload_data = main_maccore_ethphy_mii_tx_converter_source_payload_data; +assign main_maccore_ethphy_mii_tx_converter_first = (main_maccore_ethphy_mii_tx_converter_mux == 1'd0); +assign main_maccore_ethphy_mii_tx_converter_last = (main_maccore_ethphy_mii_tx_converter_mux == 1'd1); +assign main_maccore_ethphy_mii_tx_converter_source_valid = main_maccore_ethphy_mii_tx_converter_sink_valid; +assign main_maccore_ethphy_mii_tx_converter_source_first = (main_maccore_ethphy_mii_tx_converter_sink_first & main_maccore_ethphy_mii_tx_converter_first); +assign main_maccore_ethphy_mii_tx_converter_source_last = (main_maccore_ethphy_mii_tx_converter_sink_last & main_maccore_ethphy_mii_tx_converter_last); +assign main_maccore_ethphy_mii_tx_converter_sink_ready = (main_maccore_ethphy_mii_tx_converter_last & main_maccore_ethphy_mii_tx_converter_source_ready); +always @(*) begin + main_maccore_ethphy_mii_tx_converter_source_payload_data <= 4'd0; + case (main_maccore_ethphy_mii_tx_converter_mux) + 1'd0: begin + main_maccore_ethphy_mii_tx_converter_source_payload_data <= main_maccore_ethphy_mii_tx_converter_sink_payload_data[3:0]; + end + default: begin + main_maccore_ethphy_mii_tx_converter_source_payload_data <= main_maccore_ethphy_mii_tx_converter_sink_payload_data[7:4]; + end + endcase +end +assign main_maccore_ethphy_mii_tx_converter_source_payload_valid_token_count = main_maccore_ethphy_mii_tx_converter_last; +always @(*) begin + main_maccore_ethphy_demux_endpoint0_source_first <= 1'd0; + main_maccore_ethphy_demux_endpoint0_source_last <= 1'd0; + main_maccore_ethphy_demux_endpoint0_source_payload_data <= 8'd0; + main_maccore_ethphy_demux_endpoint0_source_payload_error <= 1'd0; + main_maccore_ethphy_demux_endpoint0_source_payload_last_be <= 1'd0; + main_maccore_ethphy_demux_endpoint0_source_valid <= 1'd0; + main_maccore_ethphy_demux_endpoint1_source_first <= 1'd0; + main_maccore_ethphy_demux_endpoint1_source_last <= 1'd0; + main_maccore_ethphy_demux_endpoint1_source_payload_data <= 8'd0; + main_maccore_ethphy_demux_endpoint1_source_payload_error <= 1'd0; + main_maccore_ethphy_demux_endpoint1_source_payload_last_be <= 1'd0; + main_maccore_ethphy_demux_endpoint1_source_valid <= 1'd0; + main_maccore_ethphy_demux_sink_ready <= 1'd0; + case (main_maccore_ethphy_demux_sel) + 1'd0: begin + main_maccore_ethphy_demux_endpoint0_source_valid <= main_maccore_ethphy_demux_sink_valid; + main_maccore_ethphy_demux_sink_ready <= main_maccore_ethphy_demux_endpoint0_source_ready; + main_maccore_ethphy_demux_endpoint0_source_first <= main_maccore_ethphy_demux_sink_first; + main_maccore_ethphy_demux_endpoint0_source_last <= main_maccore_ethphy_demux_sink_last; + main_maccore_ethphy_demux_endpoint0_source_payload_data <= main_maccore_ethphy_demux_sink_payload_data; + main_maccore_ethphy_demux_endpoint0_source_payload_last_be <= main_maccore_ethphy_demux_sink_payload_last_be; + main_maccore_ethphy_demux_endpoint0_source_payload_error <= main_maccore_ethphy_demux_sink_payload_error; + end + 1'd1: begin + main_maccore_ethphy_demux_endpoint1_source_valid <= main_maccore_ethphy_demux_sink_valid; + main_maccore_ethphy_demux_sink_ready <= main_maccore_ethphy_demux_endpoint1_source_ready; + main_maccore_ethphy_demux_endpoint1_source_first <= main_maccore_ethphy_demux_sink_first; + main_maccore_ethphy_demux_endpoint1_source_last <= main_maccore_ethphy_demux_sink_last; + main_maccore_ethphy_demux_endpoint1_source_payload_data <= main_maccore_ethphy_demux_sink_payload_data; + main_maccore_ethphy_demux_endpoint1_source_payload_last_be <= main_maccore_ethphy_demux_sink_payload_last_be; + main_maccore_ethphy_demux_endpoint1_source_payload_error <= main_maccore_ethphy_demux_sink_payload_error; + end + endcase +end +assign main_maccore_ethphy_mux_sel = (main_maccore_ethphy_mode0 == 1'd1); +assign main_maccore_ethphy_mux_endpoint0_sink_valid = main_maccore_ethphy_gmii_rx_source_valid; +assign main_maccore_ethphy_gmii_rx_source_ready = main_maccore_ethphy_mux_endpoint0_sink_ready; +assign main_maccore_ethphy_mux_endpoint0_sink_first = main_maccore_ethphy_gmii_rx_source_first; +assign main_maccore_ethphy_mux_endpoint0_sink_last = main_maccore_ethphy_gmii_rx_source_last; +assign main_maccore_ethphy_mux_endpoint0_sink_payload_data = main_maccore_ethphy_gmii_rx_source_payload_data; +assign main_maccore_ethphy_mux_endpoint0_sink_payload_last_be = main_maccore_ethphy_gmii_rx_source_payload_last_be; +assign main_maccore_ethphy_mux_endpoint0_sink_payload_error = main_maccore_ethphy_gmii_rx_source_payload_error; +assign main_maccore_ethphy_mux_endpoint1_sink_valid = main_maccore_ethphy_mii_rx_source_valid; +assign main_maccore_ethphy_mii_rx_source_ready = main_maccore_ethphy_mux_endpoint1_sink_ready; +assign main_maccore_ethphy_mux_endpoint1_sink_first = main_maccore_ethphy_mii_rx_source_first; +assign main_maccore_ethphy_mux_endpoint1_sink_last = main_maccore_ethphy_mii_rx_source_last; +assign main_maccore_ethphy_mux_endpoint1_sink_payload_data = main_maccore_ethphy_mii_rx_source_payload_data; +assign main_maccore_ethphy_mux_endpoint1_sink_payload_last_be = main_maccore_ethphy_mii_rx_source_payload_last_be; +assign main_maccore_ethphy_mux_endpoint1_sink_payload_error = main_maccore_ethphy_mii_rx_source_payload_error; +assign main_maccore_ethphy_source_source_valid = main_maccore_ethphy_mux_source_valid; +assign main_maccore_ethphy_mux_source_ready = main_maccore_ethphy_source_source_ready; +assign main_maccore_ethphy_source_source_first = main_maccore_ethphy_mux_source_first; +assign main_maccore_ethphy_source_source_last = main_maccore_ethphy_mux_source_last; +assign main_maccore_ethphy_source_source_payload_data = main_maccore_ethphy_mux_source_payload_data; +assign main_maccore_ethphy_source_source_payload_last_be = main_maccore_ethphy_mux_source_payload_last_be; +assign main_maccore_ethphy_source_source_payload_error = main_maccore_ethphy_mux_source_payload_error; +assign main_maccore_ethphy_gmii_rx_source_last = ((~main_maccore_ethphy_pads_d_rx_dv) & main_maccore_ethphy_gmii_rx_dv_d); +assign main_maccore_ethphy_mii_rx_converter_sink_last = (~main_maccore_ethphy_pads_d_rx_dv); +assign main_maccore_ethphy_mii_rx_source_valid = main_maccore_ethphy_mii_rx_source_source_valid; +assign main_maccore_ethphy_mii_rx_source_source_ready = main_maccore_ethphy_mii_rx_source_ready; +assign main_maccore_ethphy_mii_rx_source_first = main_maccore_ethphy_mii_rx_source_source_first; +assign main_maccore_ethphy_mii_rx_source_last = main_maccore_ethphy_mii_rx_source_source_last; +assign main_maccore_ethphy_mii_rx_source_payload_data = main_maccore_ethphy_mii_rx_source_source_payload_data; +assign main_maccore_ethphy_mii_rx_source_source_valid = main_maccore_ethphy_mii_rx_converter_source_valid; +assign main_maccore_ethphy_mii_rx_converter_source_ready = main_maccore_ethphy_mii_rx_source_source_ready; +assign main_maccore_ethphy_mii_rx_source_source_first = main_maccore_ethphy_mii_rx_converter_source_first; +assign main_maccore_ethphy_mii_rx_source_source_last = main_maccore_ethphy_mii_rx_converter_source_last; +assign main_maccore_ethphy_mii_rx_source_source_payload_data = main_maccore_ethphy_mii_rx_converter_source_payload_data; +assign main_maccore_ethphy_mii_rx_converter_sink_ready = ((~main_maccore_ethphy_mii_rx_converter_strobe_all) | main_maccore_ethphy_mii_rx_converter_source_ready); +assign main_maccore_ethphy_mii_rx_converter_source_valid = main_maccore_ethphy_mii_rx_converter_strobe_all; +assign main_maccore_ethphy_mii_rx_converter_load_part = (main_maccore_ethphy_mii_rx_converter_sink_valid & main_maccore_ethphy_mii_rx_converter_sink_ready); +always @(*) begin + main_maccore_ethphy_mux_endpoint0_sink_ready <= 1'd0; + main_maccore_ethphy_mux_endpoint1_sink_ready <= 1'd0; + main_maccore_ethphy_mux_source_first <= 1'd0; + main_maccore_ethphy_mux_source_last <= 1'd0; + main_maccore_ethphy_mux_source_payload_data <= 8'd0; + main_maccore_ethphy_mux_source_payload_error <= 1'd0; + main_maccore_ethphy_mux_source_payload_last_be <= 1'd0; + main_maccore_ethphy_mux_source_valid <= 1'd0; + case (main_maccore_ethphy_mux_sel) + 1'd0: begin + main_maccore_ethphy_mux_source_valid <= main_maccore_ethphy_mux_endpoint0_sink_valid; + main_maccore_ethphy_mux_endpoint0_sink_ready <= main_maccore_ethphy_mux_source_ready; + main_maccore_ethphy_mux_source_first <= main_maccore_ethphy_mux_endpoint0_sink_first; + main_maccore_ethphy_mux_source_last <= main_maccore_ethphy_mux_endpoint0_sink_last; + main_maccore_ethphy_mux_source_payload_data <= main_maccore_ethphy_mux_endpoint0_sink_payload_data; + main_maccore_ethphy_mux_source_payload_last_be <= main_maccore_ethphy_mux_endpoint0_sink_payload_last_be; + main_maccore_ethphy_mux_source_payload_error <= main_maccore_ethphy_mux_endpoint0_sink_payload_error; + end + 1'd1: begin + main_maccore_ethphy_mux_source_valid <= main_maccore_ethphy_mux_endpoint1_sink_valid; + main_maccore_ethphy_mux_endpoint1_sink_ready <= main_maccore_ethphy_mux_source_ready; + main_maccore_ethphy_mux_source_first <= main_maccore_ethphy_mux_endpoint1_sink_first; + main_maccore_ethphy_mux_source_last <= main_maccore_ethphy_mux_endpoint1_sink_last; + main_maccore_ethphy_mux_source_payload_data <= main_maccore_ethphy_mux_endpoint1_sink_payload_data; + main_maccore_ethphy_mux_source_payload_last_be <= main_maccore_ethphy_mux_endpoint1_sink_payload_last_be; + main_maccore_ethphy_mux_source_payload_error <= main_maccore_ethphy_mux_endpoint1_sink_payload_error; + end + endcase +end +assign gmii_mdc = main_maccore_ethphy__w_storage[0]; +assign main_maccore_ethphy_data_oe = main_maccore_ethphy__w_storage[1]; +assign main_maccore_ethphy_data_w = main_maccore_ethphy__w_storage[2]; +assign main_sink_valid = main_source_source_valid; +assign main_source_source_ready = main_sink_ready; +assign main_sink_first = main_source_source_first; +assign main_sink_last = main_source_source_last; +assign main_sink_payload_data = main_source_source_payload_data; +assign main_sink_payload_last_be = main_source_source_payload_last_be; +assign main_sink_payload_error = main_source_source_payload_error; +assign main_sink_sink_valid = main_source_valid; +assign main_source_ready = main_sink_sink_ready; +assign main_sink_sink_first = main_source_first; +assign main_sink_sink_last = main_source_last; +assign main_sink_sink_payload_data = main_source_payload_data; +assign main_sink_sink_payload_last_be = main_source_payload_last_be; +assign main_sink_sink_payload_error = main_source_payload_error; +assign main_tx_cdc_cdc_sink_valid = main_tx_cdc_sink_sink_valid; +assign main_tx_cdc_sink_sink_ready = main_tx_cdc_cdc_sink_ready; +assign main_tx_cdc_cdc_sink_first = main_tx_cdc_sink_sink_first; +assign main_tx_cdc_cdc_sink_last = main_tx_cdc_sink_sink_last; +assign main_tx_cdc_cdc_sink_payload_data = main_tx_cdc_sink_sink_payload_data; +assign main_tx_cdc_cdc_sink_payload_last_be = main_tx_cdc_sink_sink_payload_last_be; +assign main_tx_cdc_cdc_sink_payload_error = main_tx_cdc_sink_sink_payload_error; +assign main_tx_cdc_source_source_valid = main_tx_cdc_cdc_source_valid; +assign main_tx_cdc_cdc_source_ready = main_tx_cdc_source_source_ready; +assign main_tx_cdc_source_source_first = main_tx_cdc_cdc_source_first; +assign main_tx_cdc_source_source_last = main_tx_cdc_cdc_source_last; +assign main_tx_cdc_source_source_payload_data = main_tx_cdc_cdc_source_payload_data; +assign main_tx_cdc_source_source_payload_last_be = main_tx_cdc_cdc_source_payload_last_be; +assign main_tx_cdc_source_source_payload_error = main_tx_cdc_cdc_source_payload_error; +assign main_tx_cdc_cdc_asyncfifo_din = {main_tx_cdc_cdc_fifo_in_last, main_tx_cdc_cdc_fifo_in_first, main_tx_cdc_cdc_fifo_in_payload_error, main_tx_cdc_cdc_fifo_in_payload_last_be, main_tx_cdc_cdc_fifo_in_payload_data}; +assign {main_tx_cdc_cdc_fifo_out_last, main_tx_cdc_cdc_fifo_out_first, main_tx_cdc_cdc_fifo_out_payload_error, main_tx_cdc_cdc_fifo_out_payload_last_be, main_tx_cdc_cdc_fifo_out_payload_data} = main_tx_cdc_cdc_asyncfifo_dout; +assign main_tx_cdc_cdc_sink_ready = main_tx_cdc_cdc_asyncfifo_writable; +assign main_tx_cdc_cdc_asyncfifo_we = main_tx_cdc_cdc_sink_valid; +assign main_tx_cdc_cdc_fifo_in_first = main_tx_cdc_cdc_sink_first; +assign main_tx_cdc_cdc_fifo_in_last = main_tx_cdc_cdc_sink_last; +assign main_tx_cdc_cdc_fifo_in_payload_data = main_tx_cdc_cdc_sink_payload_data; +assign main_tx_cdc_cdc_fifo_in_payload_last_be = main_tx_cdc_cdc_sink_payload_last_be; +assign main_tx_cdc_cdc_fifo_in_payload_error = main_tx_cdc_cdc_sink_payload_error; +assign main_tx_cdc_cdc_source_valid = main_tx_cdc_cdc_asyncfifo_readable; +assign main_tx_cdc_cdc_source_first = main_tx_cdc_cdc_fifo_out_first; +assign main_tx_cdc_cdc_source_last = main_tx_cdc_cdc_fifo_out_last; +assign main_tx_cdc_cdc_source_payload_data = main_tx_cdc_cdc_fifo_out_payload_data; +assign main_tx_cdc_cdc_source_payload_last_be = main_tx_cdc_cdc_fifo_out_payload_last_be; +assign main_tx_cdc_cdc_source_payload_error = main_tx_cdc_cdc_fifo_out_payload_error; +assign main_tx_cdc_cdc_asyncfifo_re = main_tx_cdc_cdc_source_ready; +assign main_tx_cdc_cdc_graycounter0_ce = (main_tx_cdc_cdc_asyncfifo_writable & main_tx_cdc_cdc_asyncfifo_we); +assign main_tx_cdc_cdc_graycounter1_ce = (main_tx_cdc_cdc_asyncfifo_readable & main_tx_cdc_cdc_asyncfifo_re); +assign main_tx_cdc_cdc_asyncfifo_writable = (((main_tx_cdc_cdc_graycounter0_q[5] == main_tx_cdc_cdc_consume_wdomain[5]) | (main_tx_cdc_cdc_graycounter0_q[4] == main_tx_cdc_cdc_consume_wdomain[4])) | (main_tx_cdc_cdc_graycounter0_q[3:0] != main_tx_cdc_cdc_consume_wdomain[3:0])); +assign main_tx_cdc_cdc_asyncfifo_readable = (main_tx_cdc_cdc_graycounter1_q != main_tx_cdc_cdc_produce_rdomain); +assign main_tx_cdc_cdc_wrport_adr = main_tx_cdc_cdc_graycounter0_q_binary[4:0]; +assign main_tx_cdc_cdc_wrport_dat_w = main_tx_cdc_cdc_asyncfifo_din; +assign main_tx_cdc_cdc_wrport_we = main_tx_cdc_cdc_graycounter0_ce; +assign main_tx_cdc_cdc_rdport_adr = main_tx_cdc_cdc_graycounter1_q_next_binary[4:0]; +assign main_tx_cdc_cdc_asyncfifo_dout = main_tx_cdc_cdc_rdport_dat_r; +always @(*) begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (main_tx_cdc_cdc_graycounter0_ce) begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= (main_tx_cdc_cdc_graycounter0_q_binary + 1'd1); + end else begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= main_tx_cdc_cdc_graycounter0_q_binary; + end +end +assign main_tx_cdc_cdc_graycounter0_q_next = (main_tx_cdc_cdc_graycounter0_q_next_binary ^ main_tx_cdc_cdc_graycounter0_q_next_binary[5:1]); +always @(*) begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (main_tx_cdc_cdc_graycounter1_ce) begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= (main_tx_cdc_cdc_graycounter1_q_binary + 1'd1); + end else begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= main_tx_cdc_cdc_graycounter1_q_binary; + end +end +assign main_tx_cdc_cdc_graycounter1_q_next = (main_tx_cdc_cdc_graycounter1_q_next_binary ^ main_tx_cdc_cdc_graycounter1_q_next_binary[5:1]); +assign main_tx_converter_converter_sink_valid = main_tx_converter_sink_valid; +assign main_tx_converter_converter_sink_first = main_tx_converter_sink_first; +assign main_tx_converter_converter_sink_last = main_tx_converter_sink_last; +assign main_tx_converter_sink_ready = main_tx_converter_converter_sink_ready; +always @(*) begin + main_tx_converter_converter_sink_payload_data <= 40'd0; + main_tx_converter_converter_sink_payload_data[7:0] <= main_tx_converter_sink_payload_data[7:0]; + main_tx_converter_converter_sink_payload_data[8] <= main_tx_converter_sink_payload_last_be[0]; + main_tx_converter_converter_sink_payload_data[9] <= main_tx_converter_sink_payload_error[0]; + main_tx_converter_converter_sink_payload_data[17:10] <= main_tx_converter_sink_payload_data[15:8]; + main_tx_converter_converter_sink_payload_data[18] <= main_tx_converter_sink_payload_last_be[1]; + main_tx_converter_converter_sink_payload_data[19] <= main_tx_converter_sink_payload_error[1]; + main_tx_converter_converter_sink_payload_data[27:20] <= main_tx_converter_sink_payload_data[23:16]; + main_tx_converter_converter_sink_payload_data[28] <= main_tx_converter_sink_payload_last_be[2]; + main_tx_converter_converter_sink_payload_data[29] <= main_tx_converter_sink_payload_error[2]; + main_tx_converter_converter_sink_payload_data[37:30] <= main_tx_converter_sink_payload_data[31:24]; + main_tx_converter_converter_sink_payload_data[38] <= main_tx_converter_sink_payload_last_be[3]; + main_tx_converter_converter_sink_payload_data[39] <= main_tx_converter_sink_payload_error[3]; +end +assign main_tx_converter_source_valid = main_tx_converter_source_source_valid; +assign main_tx_converter_source_first = main_tx_converter_source_source_first; +assign main_tx_converter_source_last = main_tx_converter_source_source_last; +assign main_tx_converter_source_source_ready = main_tx_converter_source_ready; +assign {main_tx_converter_source_payload_error, main_tx_converter_source_payload_last_be, main_tx_converter_source_payload_data} = main_tx_converter_source_source_payload_data; +assign main_tx_converter_source_source_valid = main_tx_converter_converter_source_valid; +assign main_tx_converter_converter_source_ready = main_tx_converter_source_source_ready; +assign main_tx_converter_source_source_first = main_tx_converter_converter_source_first; +assign main_tx_converter_source_source_last = main_tx_converter_converter_source_last; +assign main_tx_converter_source_source_payload_data = main_tx_converter_converter_source_payload_data; +assign main_tx_converter_converter_first = (main_tx_converter_converter_mux == 1'd0); +assign main_tx_converter_converter_last = (main_tx_converter_converter_mux == 2'd3); +assign main_tx_converter_converter_source_valid = main_tx_converter_converter_sink_valid; +assign main_tx_converter_converter_source_first = (main_tx_converter_converter_sink_first & main_tx_converter_converter_first); +assign main_tx_converter_converter_source_last = (main_tx_converter_converter_sink_last & main_tx_converter_converter_last); +assign main_tx_converter_converter_sink_ready = (main_tx_converter_converter_last & main_tx_converter_converter_source_ready); +always @(*) begin + main_tx_converter_converter_source_payload_data <= 10'd0; + case (main_tx_converter_converter_mux) + 1'd0: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[9:0]; + end + 1'd1: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[19:10]; + end + 2'd2: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[29:20]; + end + default: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[39:30]; + end + endcase +end +assign main_tx_converter_converter_source_payload_valid_token_count = main_tx_converter_converter_last; +always @(*) begin + builder_txdatapath_liteethmactxlastbe_next_state <= 1'd0; + main_tx_last_be_sink_ready <= 1'd0; + main_tx_last_be_source_first <= 1'd0; + main_tx_last_be_source_last <= 1'd0; + main_tx_last_be_source_payload_data <= 8'd0; + main_tx_last_be_source_payload_error <= 1'd0; + main_tx_last_be_source_payload_last_be <= 1'd0; + main_tx_last_be_source_valid <= 1'd0; + builder_txdatapath_liteethmactxlastbe_next_state <= builder_txdatapath_liteethmactxlastbe_state; + case (builder_txdatapath_liteethmactxlastbe_state) + 1'd1: begin + main_tx_last_be_sink_ready <= 1'd1; + if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_last)) begin + builder_txdatapath_liteethmactxlastbe_next_state <= 1'd0; + end + end + default: begin + main_tx_last_be_source_valid <= main_tx_last_be_sink_valid; + main_tx_last_be_sink_ready <= main_tx_last_be_source_ready; + main_tx_last_be_source_first <= main_tx_last_be_sink_first; + main_tx_last_be_source_last <= main_tx_last_be_sink_last; + main_tx_last_be_source_payload_data <= main_tx_last_be_sink_payload_data; + main_tx_last_be_source_payload_last_be <= main_tx_last_be_sink_payload_last_be; + main_tx_last_be_source_payload_error <= main_tx_last_be_sink_payload_error; + main_tx_last_be_source_last <= (main_tx_last_be_sink_payload_last_be != 1'd0); + if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_ready)) begin + if ((main_tx_last_be_source_last & (~main_tx_last_be_sink_last))) begin + builder_txdatapath_liteethmactxlastbe_next_state <= 1'd1; + end + end + end + endcase +end +assign main_tx_padding_counter_done = (main_tx_padding_counter >= 6'd59); +always @(*) begin + builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 16'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd0; + main_tx_padding_sink_ready <= 1'd0; + main_tx_padding_source_first <= 1'd0; + main_tx_padding_source_last <= 1'd0; + main_tx_padding_source_payload_data <= 8'd0; + main_tx_padding_source_payload_error <= 1'd0; + main_tx_padding_source_payload_last_be <= 1'd0; + main_tx_padding_source_valid <= 1'd0; + builder_txdatapath_liteethmacpaddinginserter_next_state <= builder_txdatapath_liteethmacpaddinginserter_state; + case (builder_txdatapath_liteethmacpaddinginserter_state) + 1'd1: begin + main_tx_padding_source_valid <= 1'd1; + if (main_tx_padding_counter_done) begin + main_tx_padding_source_payload_last_be <= 1'd1; + main_tx_padding_source_last <= 1'd1; + end + main_tx_padding_source_payload_data <= 1'd0; + if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (main_tx_padding_counter_done) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + end + end + end + default: begin + main_tx_padding_source_valid <= main_tx_padding_sink_valid; + main_tx_padding_sink_ready <= main_tx_padding_source_ready; + main_tx_padding_source_first <= main_tx_padding_sink_first; + main_tx_padding_source_last <= main_tx_padding_sink_last; + main_tx_padding_source_payload_data <= main_tx_padding_sink_payload_data; + main_tx_padding_source_payload_last_be <= main_tx_padding_sink_payload_last_be; + main_tx_padding_source_payload_error <= main_tx_padding_sink_payload_error; + if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (main_tx_padding_sink_last) begin + if ((~main_tx_padding_counter_done)) begin + main_tx_padding_source_last <= 1'd0; + main_tx_padding_source_payload_last_be <= 1'd0; + builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd1; + end else begin + if (((main_tx_padding_counter == 6'd59) & (main_tx_padding_sink_payload_last_be < 1'd1))) begin + main_tx_padding_source_payload_last_be <= 1'd1; + end else begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + end + end + end + end + end + endcase +end +assign main_tx_crc_data0 = main_tx_crc_sink_payload_data; +assign main_tx_crc_be = main_tx_crc_sink_payload_last_be; +assign main_tx_crc_cnt_done = (main_tx_crc_cnt == 1'd0); +assign main_tx_crc_sink_valid = main_tx_crc_source_source_valid; +assign main_tx_crc_source_source_ready = main_tx_crc_sink_ready; +assign main_tx_crc_sink_first = main_tx_crc_source_source_first; +assign main_tx_crc_sink_last = main_tx_crc_source_source_last; +assign main_tx_crc_sink_payload_data = main_tx_crc_source_source_payload_data; +assign main_tx_crc_sink_payload_last_be = main_tx_crc_source_source_payload_last_be; +assign main_tx_crc_sink_payload_error = main_tx_crc_source_source_payload_error; +assign main_tx_crc_data1 = main_tx_crc_data0[7:0]; +assign main_tx_crc_crc_prev = main_tx_crc_reg; +always @(*) begin + main_tx_crc_error <= 1'd0; + main_tx_crc_value <= 32'd0; + if (main_tx_crc_be) begin + main_tx_crc_value <= {builder_t_slice_proxy31[0], builder_t_slice_proxy30[1], builder_t_slice_proxy29[2], builder_t_slice_proxy28[3], builder_t_slice_proxy27[4], builder_t_slice_proxy26[5], builder_t_slice_proxy25[6], builder_t_slice_proxy24[7], builder_t_slice_proxy23[8], builder_t_slice_proxy22[9], builder_t_slice_proxy21[10], builder_t_slice_proxy20[11], builder_t_slice_proxy19[12], builder_t_slice_proxy18[13], builder_t_slice_proxy17[14], builder_t_slice_proxy16[15], builder_t_slice_proxy15[16], builder_t_slice_proxy14[17], builder_t_slice_proxy13[18], builder_t_slice_proxy12[19], builder_t_slice_proxy11[20], builder_t_slice_proxy10[21], builder_t_slice_proxy9[22], builder_t_slice_proxy8[23], builder_t_slice_proxy7[24], builder_t_slice_proxy6[25], builder_t_slice_proxy5[26], builder_t_slice_proxy4[27], builder_t_slice_proxy3[28], builder_t_slice_proxy2[29], builder_t_slice_proxy1[30], builder_t_slice_proxy0[31]}; + main_tx_crc_error <= (main_tx_crc_crc_next != 32'd3338984827); + end +end +always @(*) begin + main_tx_crc_crc_next <= 32'd0; + main_tx_crc_crc_next[0] <= (((main_tx_crc_crc_prev[24] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[1] <= (((((((main_tx_crc_crc_prev[25] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[2] <= (((((((((main_tx_crc_crc_prev[26] ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[3] <= (((((((main_tx_crc_crc_prev[27] ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[4] <= (((((((((main_tx_crc_crc_prev[28] ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[5] <= (((((((((((((main_tx_crc_crc_prev[29] ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[6] <= (((((((((((main_tx_crc_crc_prev[30] ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[7] <= (((((((((main_tx_crc_crc_prev[31] ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[8] <= ((((((((main_tx_crc_crc_prev[0] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[9] <= ((((((((main_tx_crc_crc_prev[1] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[10] <= ((((((((main_tx_crc_crc_prev[2] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[11] <= ((((((((main_tx_crc_crc_prev[3] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[12] <= ((((((((((((main_tx_crc_crc_prev[4] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[13] <= ((((((((((((main_tx_crc_crc_prev[5] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[14] <= ((((((((((main_tx_crc_crc_prev[6] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[15] <= ((((((((main_tx_crc_crc_prev[7] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); + main_tx_crc_crc_next[16] <= ((((((main_tx_crc_crc_prev[8] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[17] <= ((((((main_tx_crc_crc_prev[9] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[18] <= ((((((main_tx_crc_crc_prev[10] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[19] <= ((((main_tx_crc_crc_prev[11] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); + main_tx_crc_crc_next[20] <= ((main_tx_crc_crc_prev[12] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]); + main_tx_crc_crc_next[21] <= ((main_tx_crc_crc_prev[13] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]); + main_tx_crc_crc_next[22] <= ((main_tx_crc_crc_prev[14] ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[23] <= ((((((main_tx_crc_crc_prev[15] ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[24] <= ((((((main_tx_crc_crc_prev[16] ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[25] <= ((((main_tx_crc_crc_prev[17] ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[26] <= ((((((((main_tx_crc_crc_prev[18] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[27] <= ((((((((main_tx_crc_crc_prev[19] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[28] <= ((((((main_tx_crc_crc_prev[20] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[29] <= ((((((main_tx_crc_crc_prev[21] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); + main_tx_crc_crc_next[30] <= ((((main_tx_crc_crc_prev[22] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]); + main_tx_crc_crc_next[31] <= ((main_tx_crc_crc_prev[23] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]); +end +always @(*) begin + builder_txdatapath_bufferizeendpoints_next_state <= 2'd0; + main_tx_crc_ce <= 1'd0; + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= 32'd0; + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd0; + main_tx_crc_is_ongoing0 <= 1'd0; + main_tx_crc_is_ongoing1 <= 1'd0; + main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= 1'd0; + main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd0; + main_tx_crc_reset <= 1'd0; + main_tx_crc_sink_ready <= 1'd0; + main_tx_crc_source_first <= 1'd0; + main_tx_crc_source_last <= 1'd0; + main_tx_crc_source_payload_data <= 8'd0; + main_tx_crc_source_payload_error <= 1'd0; + main_tx_crc_source_payload_last_be <= 1'd0; + main_tx_crc_source_valid <= 1'd0; + builder_txdatapath_bufferizeendpoints_next_state <= builder_txdatapath_bufferizeendpoints_state; + case (builder_txdatapath_bufferizeendpoints_state) + 1'd1: begin + main_tx_crc_ce <= (main_tx_crc_sink_valid & main_tx_crc_source_ready); + main_tx_crc_source_valid <= main_tx_crc_sink_valid; + main_tx_crc_sink_ready <= main_tx_crc_source_ready; + main_tx_crc_source_first <= main_tx_crc_sink_first; + main_tx_crc_source_last <= main_tx_crc_sink_last; + main_tx_crc_source_payload_data <= main_tx_crc_sink_payload_data; + main_tx_crc_source_payload_last_be <= main_tx_crc_sink_payload_last_be; + main_tx_crc_source_payload_error <= main_tx_crc_sink_payload_error; + main_tx_crc_source_last <= 1'd0; + main_tx_crc_source_payload_last_be <= 1'd0; + if (main_tx_crc_sink_last) begin + if (main_tx_crc_sink_payload_last_be) begin + main_tx_crc_source_payload_data <= builder_complexslicelowerer_slice_proxy[7:0]; + end + if ((1'd0 & (main_tx_crc_sink_payload_last_be <= 4'd15))) begin + main_tx_crc_source_last <= 1'd1; + main_tx_crc_source_payload_last_be <= (main_tx_crc_sink_payload_last_be <<< -3'd3); + end + end else begin + main_tx_crc_ce <= (main_tx_crc_sink_valid & main_tx_crc_source_ready); + end + if (((main_tx_crc_sink_valid & main_tx_crc_sink_last) & main_tx_crc_source_ready)) begin + if ((1'd0 & (main_tx_crc_sink_payload_last_be <= 4'd15))) begin + builder_txdatapath_bufferizeendpoints_next_state <= 1'd0; + end else begin + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= main_tx_crc_value; + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd1; + if (1'd0) begin + main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= (main_tx_crc_sink_payload_last_be >>> 3'd4); + main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + end else begin + main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= main_tx_crc_sink_payload_last_be; + main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + end + builder_txdatapath_bufferizeendpoints_next_state <= 2'd2; + end + end + end + 2'd2: begin + main_tx_crc_source_valid <= 1'd1; + case (main_tx_crc_cnt) + 1'd0: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[31:24]; + end + 1'd1: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[23:16]; + end + 2'd2: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[15:8]; + end + default: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[7:0]; + end + endcase + if (main_tx_crc_cnt_done) begin + main_tx_crc_source_last <= 1'd1; + if (main_tx_crc_source_ready) begin + builder_txdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + main_tx_crc_is_ongoing1 <= 1'd1; + end + default: begin + main_tx_crc_reset <= 1'd1; + main_tx_crc_sink_ready <= 1'd1; + if (main_tx_crc_sink_valid) begin + main_tx_crc_sink_ready <= 1'd0; + builder_txdatapath_bufferizeendpoints_next_state <= 1'd1; + end + main_tx_crc_is_ongoing0 <= 1'd1; + end + endcase +end +assign main_tx_crc_pipe_valid_sink_ready = ((~main_tx_crc_pipe_valid_source_valid) | main_tx_crc_pipe_valid_source_ready); +assign main_tx_crc_pipe_valid_sink_valid = main_tx_crc_sink_sink_valid; +assign main_tx_crc_sink_sink_ready = main_tx_crc_pipe_valid_sink_ready; +assign main_tx_crc_pipe_valid_sink_first = main_tx_crc_sink_sink_first; +assign main_tx_crc_pipe_valid_sink_last = main_tx_crc_sink_sink_last; +assign main_tx_crc_pipe_valid_sink_payload_data = main_tx_crc_sink_sink_payload_data; +assign main_tx_crc_pipe_valid_sink_payload_last_be = main_tx_crc_sink_sink_payload_last_be; +assign main_tx_crc_pipe_valid_sink_payload_error = main_tx_crc_sink_sink_payload_error; +assign main_tx_crc_source_source_valid = main_tx_crc_pipe_valid_source_valid; +assign main_tx_crc_pipe_valid_source_ready = main_tx_crc_source_source_ready; +assign main_tx_crc_source_source_first = main_tx_crc_pipe_valid_source_first; +assign main_tx_crc_source_source_last = main_tx_crc_pipe_valid_source_last; +assign main_tx_crc_source_source_payload_data = main_tx_crc_pipe_valid_source_payload_data; +assign main_tx_crc_source_source_payload_last_be = main_tx_crc_pipe_valid_source_payload_last_be; +assign main_tx_crc_source_source_payload_error = main_tx_crc_pipe_valid_source_payload_error; +assign main_tx_preamble_source_payload_last_be = main_tx_preamble_sink_payload_last_be; +always @(*) begin + builder_txdatapath_liteethmacpreambleinserter_next_state <= 2'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value <= 3'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd0; + main_tx_preamble_sink_ready <= 1'd0; + main_tx_preamble_source_first <= 1'd0; + main_tx_preamble_source_last <= 1'd0; + main_tx_preamble_source_payload_data <= 8'd0; + main_tx_preamble_source_payload_error <= 1'd0; + main_tx_preamble_source_valid <= 1'd0; + main_tx_preamble_source_payload_data <= main_tx_preamble_sink_payload_data; + builder_txdatapath_liteethmacpreambleinserter_next_state <= builder_txdatapath_liteethmacpreambleinserter_state; + case (builder_txdatapath_liteethmacpreambleinserter_state) + 1'd1: begin + main_tx_preamble_source_valid <= 1'd1; + case (main_tx_preamble_count) + 1'd0: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[7:0]; + end + 1'd1: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[15:8]; + end + 2'd2: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[23:16]; + end + 2'd3: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[31:24]; + end + 3'd4: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[39:32]; + end + 3'd5: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[47:40]; + end + 3'd6: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[55:48]; + end + default: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[63:56]; + end + endcase + if (main_tx_preamble_source_ready) begin + if ((main_tx_preamble_count == 3'd7)) begin + builder_txdatapath_liteethmacpreambleinserter_next_state <= 2'd2; + end else begin + main_tx_preamble_count_clockdomainsrenamer2_next_value <= (main_tx_preamble_count + 1'd1); + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + end + end + end + 2'd2: begin + main_tx_preamble_source_valid <= main_tx_preamble_sink_valid; + main_tx_preamble_sink_ready <= main_tx_preamble_source_ready; + main_tx_preamble_source_first <= main_tx_preamble_sink_first; + main_tx_preamble_source_last <= main_tx_preamble_sink_last; + main_tx_preamble_source_payload_error <= main_tx_preamble_sink_payload_error; + if (((main_tx_preamble_sink_valid & main_tx_preamble_sink_last) & main_tx_preamble_source_ready)) begin + builder_txdatapath_liteethmacpreambleinserter_next_state <= 1'd0; + end + end + default: begin + main_tx_preamble_sink_ready <= 1'd1; + main_tx_preamble_count_clockdomainsrenamer2_next_value <= 1'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + if (main_tx_preamble_sink_valid) begin + main_tx_preamble_sink_ready <= 1'd0; + builder_txdatapath_liteethmacpreambleinserter_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + builder_txdatapath_liteethmacgap_next_state <= 1'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value <= 4'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd0; + main_tx_gap_sink_ready <= 1'd0; + main_tx_gap_source_first <= 1'd0; + main_tx_gap_source_last <= 1'd0; + main_tx_gap_source_payload_data <= 8'd0; + main_tx_gap_source_payload_error <= 1'd0; + main_tx_gap_source_payload_last_be <= 1'd0; + main_tx_gap_source_valid <= 1'd0; + builder_txdatapath_liteethmacgap_next_state <= builder_txdatapath_liteethmacgap_state; + case (builder_txdatapath_liteethmacgap_state) + 1'd1: begin + main_tx_gap_counter_clockdomainsrenamer3_next_value <= (main_tx_gap_counter + 1'd1); + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + if ((main_tx_gap_counter == 4'd11)) begin + builder_txdatapath_liteethmacgap_next_state <= 1'd0; + end + end + default: begin + main_tx_gap_counter_clockdomainsrenamer3_next_value <= 1'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + main_tx_gap_source_valid <= main_tx_gap_sink_valid; + main_tx_gap_sink_ready <= main_tx_gap_source_ready; + main_tx_gap_source_first <= main_tx_gap_sink_first; + main_tx_gap_source_last <= main_tx_gap_sink_last; + main_tx_gap_source_payload_data <= main_tx_gap_sink_payload_data; + main_tx_gap_source_payload_last_be <= main_tx_gap_sink_payload_last_be; + main_tx_gap_source_payload_error <= main_tx_gap_sink_payload_error; + if (((main_tx_gap_sink_valid & main_tx_gap_sink_last) & main_tx_gap_sink_ready)) begin + builder_txdatapath_liteethmacgap_next_state <= 1'd1; + end + end + endcase +end +assign main_tx_cdc_sink_sink_valid = main_sink_valid; +assign main_sink_ready = main_tx_cdc_sink_sink_ready; +assign main_tx_cdc_sink_sink_first = main_sink_first; +assign main_tx_cdc_sink_sink_last = main_sink_last; +assign main_tx_cdc_sink_sink_payload_data = main_sink_payload_data; +assign main_tx_cdc_sink_sink_payload_last_be = main_sink_payload_last_be; +assign main_tx_cdc_sink_sink_payload_error = main_sink_payload_error; +assign main_tx_converter_sink_valid = main_tx_cdc_source_source_valid; +assign main_tx_cdc_source_source_ready = main_tx_converter_sink_ready; +assign main_tx_converter_sink_first = main_tx_cdc_source_source_first; +assign main_tx_converter_sink_last = main_tx_cdc_source_source_last; +assign main_tx_converter_sink_payload_data = main_tx_cdc_source_source_payload_data; +assign main_tx_converter_sink_payload_last_be = main_tx_cdc_source_source_payload_last_be; +assign main_tx_converter_sink_payload_error = main_tx_cdc_source_source_payload_error; +assign main_tx_last_be_sink_valid = main_tx_converter_source_valid; +assign main_tx_converter_source_ready = main_tx_last_be_sink_ready; +assign main_tx_last_be_sink_first = main_tx_converter_source_first; +assign main_tx_last_be_sink_last = main_tx_converter_source_last; +assign main_tx_last_be_sink_payload_data = main_tx_converter_source_payload_data; +assign main_tx_last_be_sink_payload_last_be = main_tx_converter_source_payload_last_be; +assign main_tx_last_be_sink_payload_error = main_tx_converter_source_payload_error; +assign main_tx_padding_sink_valid = main_tx_last_be_source_valid; +assign main_tx_last_be_source_ready = main_tx_padding_sink_ready; +assign main_tx_padding_sink_first = main_tx_last_be_source_first; +assign main_tx_padding_sink_last = main_tx_last_be_source_last; +assign main_tx_padding_sink_payload_data = main_tx_last_be_source_payload_data; +assign main_tx_padding_sink_payload_last_be = main_tx_last_be_source_payload_last_be; +assign main_tx_padding_sink_payload_error = main_tx_last_be_source_payload_error; +assign main_tx_crc_sink_sink_valid = main_tx_padding_source_valid; +assign main_tx_padding_source_ready = main_tx_crc_sink_sink_ready; +assign main_tx_crc_sink_sink_first = main_tx_padding_source_first; +assign main_tx_crc_sink_sink_last = main_tx_padding_source_last; +assign main_tx_crc_sink_sink_payload_data = main_tx_padding_source_payload_data; +assign main_tx_crc_sink_sink_payload_last_be = main_tx_padding_source_payload_last_be; +assign main_tx_crc_sink_sink_payload_error = main_tx_padding_source_payload_error; +assign main_tx_preamble_sink_valid = main_tx_crc_source_valid; +assign main_tx_crc_source_ready = main_tx_preamble_sink_ready; +assign main_tx_preamble_sink_first = main_tx_crc_source_first; +assign main_tx_preamble_sink_last = main_tx_crc_source_last; +assign main_tx_preamble_sink_payload_data = main_tx_crc_source_payload_data; +assign main_tx_preamble_sink_payload_last_be = main_tx_crc_source_payload_last_be; +assign main_tx_preamble_sink_payload_error = main_tx_crc_source_payload_error; +assign main_tx_gap_sink_valid = main_tx_preamble_source_valid; +assign main_tx_preamble_source_ready = main_tx_gap_sink_ready; +assign main_tx_gap_sink_first = main_tx_preamble_source_first; +assign main_tx_gap_sink_last = main_tx_preamble_source_last; +assign main_tx_gap_sink_payload_data = main_tx_preamble_source_payload_data; +assign main_tx_gap_sink_payload_last_be = main_tx_preamble_source_payload_last_be; +assign main_tx_gap_sink_payload_error = main_tx_preamble_source_payload_error; +assign main_maccore_ethphy_sink_sink_valid = main_tx_gap_source_valid; +assign main_tx_gap_source_ready = main_maccore_ethphy_sink_sink_ready; +assign main_maccore_ethphy_sink_sink_first = main_tx_gap_source_first; +assign main_maccore_ethphy_sink_sink_last = main_tx_gap_source_last; +assign main_maccore_ethphy_sink_sink_payload_data = main_tx_gap_source_payload_data; +assign main_maccore_ethphy_sink_sink_payload_last_be = main_tx_gap_source_payload_last_be; +assign main_maccore_ethphy_sink_sink_payload_error = main_tx_gap_source_payload_error; +assign main_pulsesynchronizer0_i = main_rx_preamble_error; +assign main_pulsesynchronizer1_i = main_liteethmaccrc32checker_error; +assign main_rx_preamble_source_payload_data = main_rx_preamble_sink_payload_data; +assign main_rx_preamble_source_payload_last_be = main_rx_preamble_sink_payload_last_be; +always @(*) begin + builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + main_rx_preamble_error <= 1'd0; + main_rx_preamble_sink_ready <= 1'd0; + main_rx_preamble_source_first <= 1'd0; + main_rx_preamble_source_last <= 1'd0; + main_rx_preamble_source_payload_error <= 1'd0; + main_rx_preamble_source_valid <= 1'd0; + builder_rxdatapath_liteethmacpreamblechecker_next_state <= builder_rxdatapath_liteethmacpreamblechecker_state; + case (builder_rxdatapath_liteethmacpreamblechecker_state) + 1'd1: begin + main_rx_preamble_source_valid <= main_rx_preamble_sink_valid; + main_rx_preamble_sink_ready <= main_rx_preamble_source_ready; + main_rx_preamble_source_first <= main_rx_preamble_sink_first; + main_rx_preamble_source_last <= main_rx_preamble_sink_last; + main_rx_preamble_source_payload_error <= main_rx_preamble_sink_payload_error; + if (((main_rx_preamble_source_valid & main_rx_preamble_source_last) & main_rx_preamble_source_ready)) begin + builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + end + end + default: begin + main_rx_preamble_sink_ready <= 1'd1; + if (((main_rx_preamble_sink_valid & (~main_rx_preamble_sink_last)) & (main_rx_preamble_sink_payload_data == main_rx_preamble_preamble[63:56]))) begin + builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd1; + end + if ((main_rx_preamble_sink_valid & main_rx_preamble_sink_last)) begin + main_rx_preamble_error <= 1'd1; + end + end + endcase +end +assign main_pulsesynchronizer0_o = (main_pulsesynchronizer0_toggle_o ^ main_pulsesynchronizer0_toggle_o_r); +assign main_liteethmaccrc32checker_fifo_full = (main_liteethmaccrc32checker_syncfifo_level == 3'd4); +assign main_liteethmaccrc32checker_fifo_in = (main_liteethmaccrc32checker_sink_sink_valid & ((~main_liteethmaccrc32checker_fifo_full) | main_liteethmaccrc32checker_fifo_out)); +assign main_liteethmaccrc32checker_fifo_out = (main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready); +assign main_liteethmaccrc32checker_syncfifo_sink_first = main_liteethmaccrc32checker_sink_sink_first; +assign main_liteethmaccrc32checker_syncfifo_sink_last = main_liteethmaccrc32checker_sink_sink_last; +assign main_liteethmaccrc32checker_syncfifo_sink_payload_data = main_liteethmaccrc32checker_sink_sink_payload_data; +assign main_liteethmaccrc32checker_syncfifo_sink_payload_last_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; +assign main_liteethmaccrc32checker_syncfifo_sink_payload_error = main_liteethmaccrc32checker_sink_sink_payload_error; +always @(*) begin + main_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; + main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_sink_sink_valid; + main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_fifo_in; +end +always @(*) begin + main_liteethmaccrc32checker_sink_sink_ready <= 1'd0; + main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_syncfifo_sink_ready; + main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_fifo_in; +end +assign main_liteethmaccrc32checker_crc_data0 = main_liteethmaccrc32checker_sink_sink_payload_data; +assign main_liteethmaccrc32checker_crc_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; +assign main_liteethmaccrc32checker_source_source_first = main_liteethmaccrc32checker_syncfifo_source_first; +assign main_liteethmaccrc32checker_source_source_payload_data = main_liteethmaccrc32checker_syncfifo_source_payload_data; +assign main_liteethmaccrc32checker_sink_sink_valid = main_bufferizeendpoints_source_source_valid; +assign main_bufferizeendpoints_source_source_ready = main_liteethmaccrc32checker_sink_sink_ready; +assign main_liteethmaccrc32checker_sink_sink_first = main_bufferizeendpoints_source_source_first; +assign main_liteethmaccrc32checker_sink_sink_last = main_bufferizeendpoints_source_source_last; +assign main_liteethmaccrc32checker_sink_sink_payload_data = main_bufferizeendpoints_source_source_payload_data; +assign main_liteethmaccrc32checker_sink_sink_payload_last_be = main_bufferizeendpoints_source_source_payload_last_be; +assign main_liteethmaccrc32checker_sink_sink_payload_error = main_bufferizeendpoints_source_source_payload_error; +assign main_liteethmaccrc32checker_crc_data1 = main_liteethmaccrc32checker_crc_data0[7:0]; +assign main_liteethmaccrc32checker_crc_crc_prev = main_liteethmaccrc32checker_crc_reg; +always @(*) begin + main_liteethmaccrc32checker_crc_error0 <= 1'd0; + main_liteethmaccrc32checker_crc_value <= 32'd0; + if (main_liteethmaccrc32checker_crc_be) begin + main_liteethmaccrc32checker_crc_value <= {builder_t_slice_proxy63[0], builder_t_slice_proxy62[1], builder_t_slice_proxy61[2], builder_t_slice_proxy60[3], builder_t_slice_proxy59[4], builder_t_slice_proxy58[5], builder_t_slice_proxy57[6], builder_t_slice_proxy56[7], builder_t_slice_proxy55[8], builder_t_slice_proxy54[9], builder_t_slice_proxy53[10], builder_t_slice_proxy52[11], builder_t_slice_proxy51[12], builder_t_slice_proxy50[13], builder_t_slice_proxy49[14], builder_t_slice_proxy48[15], builder_t_slice_proxy47[16], builder_t_slice_proxy46[17], builder_t_slice_proxy45[18], builder_t_slice_proxy44[19], builder_t_slice_proxy43[20], builder_t_slice_proxy42[21], builder_t_slice_proxy41[22], builder_t_slice_proxy40[23], builder_t_slice_proxy39[24], builder_t_slice_proxy38[25], builder_t_slice_proxy37[26], builder_t_slice_proxy36[27], builder_t_slice_proxy35[28], builder_t_slice_proxy34[29], builder_t_slice_proxy33[30], builder_t_slice_proxy32[31]}; + main_liteethmaccrc32checker_crc_error0 <= (main_liteethmaccrc32checker_crc_crc_next != 32'd3338984827); + end +end +always @(*) begin + main_liteethmaccrc32checker_crc_crc_next <= 32'd0; + main_liteethmaccrc32checker_crc_crc_next[0] <= (((main_liteethmaccrc32checker_crc_crc_prev[24] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[1] <= (((((((main_liteethmaccrc32checker_crc_crc_prev[25] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[2] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[26] ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[3] <= (((((((main_liteethmaccrc32checker_crc_crc_prev[27] ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[4] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[28] ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[5] <= (((((((((((((main_liteethmaccrc32checker_crc_crc_prev[29] ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[6] <= (((((((((((main_liteethmaccrc32checker_crc_crc_prev[30] ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[7] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[31] ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[8] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[0] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[9] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[1] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[10] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[2] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[11] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[3] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[12] <= ((((((((((((main_liteethmaccrc32checker_crc_crc_prev[4] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[13] <= ((((((((((((main_liteethmaccrc32checker_crc_crc_prev[5] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[14] <= ((((((((((main_liteethmaccrc32checker_crc_crc_prev[6] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[15] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[7] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); + main_liteethmaccrc32checker_crc_crc_next[16] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[8] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[17] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[9] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[18] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[10] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[19] <= ((((main_liteethmaccrc32checker_crc_crc_prev[11] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); + main_liteethmaccrc32checker_crc_crc_next[20] <= ((main_liteethmaccrc32checker_crc_crc_prev[12] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); + main_liteethmaccrc32checker_crc_crc_next[21] <= ((main_liteethmaccrc32checker_crc_crc_prev[13] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); + main_liteethmaccrc32checker_crc_crc_next[22] <= ((main_liteethmaccrc32checker_crc_crc_prev[14] ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[23] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[15] ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[24] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[16] ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[25] <= ((((main_liteethmaccrc32checker_crc_crc_prev[17] ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[26] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[18] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[27] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[19] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[28] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[20] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[29] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[21] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); + main_liteethmaccrc32checker_crc_crc_next[30] <= ((((main_liteethmaccrc32checker_crc_crc_prev[22] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); + main_liteethmaccrc32checker_crc_crc_next[31] <= ((main_liteethmaccrc32checker_crc_crc_prev[23] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); +end +assign main_liteethmaccrc32checker_syncfifo_syncfifo_din = {main_liteethmaccrc32checker_syncfifo_fifo_in_last, main_liteethmaccrc32checker_syncfifo_fifo_in_first, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data}; +assign {main_liteethmaccrc32checker_syncfifo_fifo_out_last, main_liteethmaccrc32checker_syncfifo_fifo_out_first, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = main_liteethmaccrc32checker_syncfifo_syncfifo_dout; +assign main_liteethmaccrc32checker_syncfifo_sink_ready = main_liteethmaccrc32checker_syncfifo_syncfifo_writable; +assign main_liteethmaccrc32checker_syncfifo_syncfifo_we = main_liteethmaccrc32checker_syncfifo_sink_valid; +assign main_liteethmaccrc32checker_syncfifo_fifo_in_first = main_liteethmaccrc32checker_syncfifo_sink_first; +assign main_liteethmaccrc32checker_syncfifo_fifo_in_last = main_liteethmaccrc32checker_syncfifo_sink_last; +assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data = main_liteethmaccrc32checker_syncfifo_sink_payload_data; +assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be = main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; +assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error = main_liteethmaccrc32checker_syncfifo_sink_payload_error; +assign main_liteethmaccrc32checker_syncfifo_source_valid = main_liteethmaccrc32checker_syncfifo_syncfifo_readable; +assign main_liteethmaccrc32checker_syncfifo_source_first = main_liteethmaccrc32checker_syncfifo_fifo_out_first; +assign main_liteethmaccrc32checker_syncfifo_source_last = main_liteethmaccrc32checker_syncfifo_fifo_out_last; +assign main_liteethmaccrc32checker_syncfifo_source_payload_data = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; +assign main_liteethmaccrc32checker_syncfifo_source_payload_last_be = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; +assign main_liteethmaccrc32checker_syncfifo_source_payload_error = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; +assign main_liteethmaccrc32checker_syncfifo_syncfifo_re = main_liteethmaccrc32checker_syncfifo_source_ready; +always @(*) begin + main_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; + if (main_liteethmaccrc32checker_syncfifo_replace) begin + main_liteethmaccrc32checker_syncfifo_wrport_adr <= (main_liteethmaccrc32checker_syncfifo_produce - 1'd1); + end else begin + main_liteethmaccrc32checker_syncfifo_wrport_adr <= main_liteethmaccrc32checker_syncfifo_produce; + end +end +assign main_liteethmaccrc32checker_syncfifo_wrport_dat_w = main_liteethmaccrc32checker_syncfifo_syncfifo_din; +assign main_liteethmaccrc32checker_syncfifo_wrport_we = (main_liteethmaccrc32checker_syncfifo_syncfifo_we & (main_liteethmaccrc32checker_syncfifo_syncfifo_writable | main_liteethmaccrc32checker_syncfifo_replace)); +assign main_liteethmaccrc32checker_syncfifo_do_read = (main_liteethmaccrc32checker_syncfifo_syncfifo_readable & main_liteethmaccrc32checker_syncfifo_syncfifo_re); +assign main_liteethmaccrc32checker_syncfifo_rdport_adr = main_liteethmaccrc32checker_syncfifo_consume; +assign main_liteethmaccrc32checker_syncfifo_syncfifo_dout = main_liteethmaccrc32checker_syncfifo_rdport_dat_r; +assign main_liteethmaccrc32checker_syncfifo_syncfifo_writable = (main_liteethmaccrc32checker_syncfifo_level != 3'd5); +assign main_liteethmaccrc32checker_syncfifo_syncfifo_readable = (main_liteethmaccrc32checker_syncfifo_level != 1'd0); +always @(*) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 2'd0; + main_liteethmaccrc32checker_crc_ce <= 1'd0; + main_liteethmaccrc32checker_crc_error1_next_value1 <= 1'd0; + main_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd0; + main_liteethmaccrc32checker_crc_reset <= 1'd0; + main_liteethmaccrc32checker_error <= 1'd0; + main_liteethmaccrc32checker_fifo_reset <= 1'd0; + main_liteethmaccrc32checker_last_be_next_value0 <= 1'd0; + main_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd0; + main_liteethmaccrc32checker_source_source_last <= 1'd0; + main_liteethmaccrc32checker_source_source_payload_error <= 1'd0; + main_liteethmaccrc32checker_source_source_payload_last_be <= 1'd0; + main_liteethmaccrc32checker_source_source_valid <= 1'd0; + main_liteethmaccrc32checker_syncfifo_source_ready <= 1'd0; + main_liteethmaccrc32checker_source_source_payload_error <= main_liteethmaccrc32checker_syncfifo_source_payload_error; + builder_rxdatapath_bufferizeendpoints_next_state <= builder_rxdatapath_bufferizeendpoints_state; + case (builder_rxdatapath_bufferizeendpoints_state) + 1'd1: begin + if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin + main_liteethmaccrc32checker_crc_ce <= 1'd1; + builder_rxdatapath_bufferizeendpoints_next_state <= 2'd2; + end + end + 2'd2: begin + main_liteethmaccrc32checker_syncfifo_source_ready <= main_liteethmaccrc32checker_fifo_out; + main_liteethmaccrc32checker_source_source_valid <= (main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_fifo_full); + if (1'd1) begin + main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_sink_sink_last; + main_liteethmaccrc32checker_source_source_payload_last_be <= main_liteethmaccrc32checker_sink_sink_payload_last_be; + end else begin + if ((main_liteethmaccrc32checker_sink_sink_payload_last_be & 4'd15)) begin + main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_sink_sink_last; + main_liteethmaccrc32checker_source_source_payload_last_be <= (main_liteethmaccrc32checker_sink_sink_payload_last_be <<< -3'd3); + end else begin + main_liteethmaccrc32checker_last_be_next_value0 <= (main_liteethmaccrc32checker_sink_sink_payload_last_be >>> 3'd4); + main_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd1; + main_liteethmaccrc32checker_crc_error1_next_value1 <= main_liteethmaccrc32checker_crc_error0; + main_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd1; + end + end + main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_sink_sink_payload_error | {1{(main_liteethmaccrc32checker_crc_error0 & main_liteethmaccrc32checker_sink_sink_last)}}); + main_liteethmaccrc32checker_error <= ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_last) & main_liteethmaccrc32checker_crc_error0); + if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin + main_liteethmaccrc32checker_crc_ce <= 1'd1; + if ((main_liteethmaccrc32checker_sink_sink_last & (main_liteethmaccrc32checker_sink_sink_payload_last_be > 4'd15))) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 2'd3; + end else begin + if (main_liteethmaccrc32checker_sink_sink_last) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + end + end + 2'd3: begin + main_liteethmaccrc32checker_source_source_valid <= main_liteethmaccrc32checker_syncfifo_source_valid; + main_liteethmaccrc32checker_syncfifo_source_ready <= main_liteethmaccrc32checker_source_source_ready; + main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_syncfifo_source_last; + main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_syncfifo_source_payload_error | {1{main_liteethmaccrc32checker_crc_error1}}); + main_liteethmaccrc32checker_source_source_payload_last_be <= main_liteethmaccrc32checker_last_be; + if ((main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready)) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + default: begin + main_liteethmaccrc32checker_crc_reset <= 1'd1; + main_liteethmaccrc32checker_fifo_reset <= 1'd1; + builder_rxdatapath_bufferizeendpoints_next_state <= 1'd1; + end + endcase +end +assign main_bufferizeendpoints_pipe_valid_sink_ready = ((~main_bufferizeendpoints_pipe_valid_source_valid) | main_bufferizeendpoints_pipe_valid_source_ready); +assign main_bufferizeendpoints_pipe_valid_sink_valid = main_bufferizeendpoints_sink_sink_valid; +assign main_bufferizeendpoints_sink_sink_ready = main_bufferizeendpoints_pipe_valid_sink_ready; +assign main_bufferizeendpoints_pipe_valid_sink_first = main_bufferizeendpoints_sink_sink_first; +assign main_bufferizeendpoints_pipe_valid_sink_last = main_bufferizeendpoints_sink_sink_last; +assign main_bufferizeendpoints_pipe_valid_sink_payload_data = main_bufferizeendpoints_sink_sink_payload_data; +assign main_bufferizeendpoints_pipe_valid_sink_payload_last_be = main_bufferizeendpoints_sink_sink_payload_last_be; +assign main_bufferizeendpoints_pipe_valid_sink_payload_error = main_bufferizeendpoints_sink_sink_payload_error; +assign main_bufferizeendpoints_source_source_valid = main_bufferizeendpoints_pipe_valid_source_valid; +assign main_bufferizeendpoints_pipe_valid_source_ready = main_bufferizeendpoints_source_source_ready; +assign main_bufferizeendpoints_source_source_first = main_bufferizeendpoints_pipe_valid_source_first; +assign main_bufferizeendpoints_source_source_last = main_bufferizeendpoints_pipe_valid_source_last; +assign main_bufferizeendpoints_source_source_payload_data = main_bufferizeendpoints_pipe_valid_source_payload_data; +assign main_bufferizeendpoints_source_source_payload_last_be = main_bufferizeendpoints_pipe_valid_source_payload_last_be; +assign main_bufferizeendpoints_source_source_payload_error = main_bufferizeendpoints_pipe_valid_source_payload_error; +assign main_pulsesynchronizer1_o = (main_pulsesynchronizer1_toggle_o ^ main_pulsesynchronizer1_toggle_o_r); +assign main_rx_padding_source_valid = main_rx_padding_sink_valid; +assign main_rx_padding_sink_ready = main_rx_padding_source_ready; +assign main_rx_padding_source_first = main_rx_padding_sink_first; +assign main_rx_padding_source_last = main_rx_padding_sink_last; +assign main_rx_padding_source_payload_data = main_rx_padding_sink_payload_data; +assign main_rx_padding_source_payload_last_be = main_rx_padding_sink_payload_last_be; +assign main_rx_padding_source_payload_error = main_rx_padding_sink_payload_error; +assign main_rx_last_be_source_valid = main_rx_last_be_sink_valid; +assign main_rx_last_be_sink_ready = main_rx_last_be_source_ready; +assign main_rx_last_be_source_first = main_rx_last_be_sink_first; +assign main_rx_last_be_source_last = main_rx_last_be_sink_last; +assign main_rx_last_be_source_payload_data = main_rx_last_be_sink_payload_data; +assign main_rx_last_be_source_payload_error = main_rx_last_be_sink_payload_error; +always @(*) begin + main_rx_last_be_source_payload_last_be <= 1'd0; + main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_payload_last_be; + if (1'd1) begin + main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_last; + end +end +assign main_rx_converter_converter_sink_valid = main_rx_converter_sink_valid; +assign main_rx_converter_converter_sink_first = main_rx_converter_sink_first; +assign main_rx_converter_converter_sink_last = main_rx_converter_sink_last; +assign main_rx_converter_sink_ready = main_rx_converter_converter_sink_ready; +assign main_rx_converter_converter_sink_payload_data = {main_rx_converter_sink_payload_error, main_rx_converter_sink_payload_last_be, main_rx_converter_sink_payload_data}; +assign main_rx_converter_source_valid = main_rx_converter_source_source_valid; +assign main_rx_converter_source_first = main_rx_converter_source_source_first; +assign main_rx_converter_source_last = main_rx_converter_source_source_last; +assign main_rx_converter_source_source_ready = main_rx_converter_source_ready; +always @(*) begin + main_rx_converter_source_payload_data <= 32'd0; + main_rx_converter_source_payload_data[7:0] <= main_rx_converter_source_source_payload_data[7:0]; + main_rx_converter_source_payload_data[15:8] <= main_rx_converter_source_source_payload_data[17:10]; + main_rx_converter_source_payload_data[23:16] <= main_rx_converter_source_source_payload_data[27:20]; + main_rx_converter_source_payload_data[31:24] <= main_rx_converter_source_source_payload_data[37:30]; +end +always @(*) begin + main_rx_converter_source_payload_last_be <= 4'd0; + main_rx_converter_source_payload_last_be[0] <= main_rx_converter_source_source_payload_data[8]; + main_rx_converter_source_payload_last_be[1] <= main_rx_converter_source_source_payload_data[18]; + main_rx_converter_source_payload_last_be[2] <= main_rx_converter_source_source_payload_data[28]; + main_rx_converter_source_payload_last_be[3] <= main_rx_converter_source_source_payload_data[38]; +end +always @(*) begin + main_rx_converter_source_payload_error <= 4'd0; + main_rx_converter_source_payload_error[0] <= main_rx_converter_source_source_payload_data[9]; + main_rx_converter_source_payload_error[1] <= main_rx_converter_source_source_payload_data[19]; + main_rx_converter_source_payload_error[2] <= main_rx_converter_source_source_payload_data[29]; + main_rx_converter_source_payload_error[3] <= main_rx_converter_source_source_payload_data[39]; +end +assign main_rx_converter_source_source_valid = main_rx_converter_converter_source_valid; +assign main_rx_converter_converter_source_ready = main_rx_converter_source_source_ready; +assign main_rx_converter_source_source_first = main_rx_converter_converter_source_first; +assign main_rx_converter_source_source_last = main_rx_converter_converter_source_last; +assign main_rx_converter_source_source_payload_data = main_rx_converter_converter_source_payload_data; +assign main_rx_converter_converter_sink_ready = ((~main_rx_converter_converter_strobe_all) | main_rx_converter_converter_source_ready); +assign main_rx_converter_converter_source_valid = main_rx_converter_converter_strobe_all; +assign main_rx_converter_converter_load_part = (main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready); +assign main_rx_cdc_cdc_sink_valid = main_rx_cdc_sink_sink_valid; +assign main_rx_cdc_sink_sink_ready = main_rx_cdc_cdc_sink_ready; +assign main_rx_cdc_cdc_sink_first = main_rx_cdc_sink_sink_first; +assign main_rx_cdc_cdc_sink_last = main_rx_cdc_sink_sink_last; +assign main_rx_cdc_cdc_sink_payload_data = main_rx_cdc_sink_sink_payload_data; +assign main_rx_cdc_cdc_sink_payload_last_be = main_rx_cdc_sink_sink_payload_last_be; +assign main_rx_cdc_cdc_sink_payload_error = main_rx_cdc_sink_sink_payload_error; +assign main_rx_cdc_source_source_valid = main_rx_cdc_cdc_source_valid; +assign main_rx_cdc_cdc_source_ready = main_rx_cdc_source_source_ready; +assign main_rx_cdc_source_source_first = main_rx_cdc_cdc_source_first; +assign main_rx_cdc_source_source_last = main_rx_cdc_cdc_source_last; +assign main_rx_cdc_source_source_payload_data = main_rx_cdc_cdc_source_payload_data; +assign main_rx_cdc_source_source_payload_last_be = main_rx_cdc_cdc_source_payload_last_be; +assign main_rx_cdc_source_source_payload_error = main_rx_cdc_cdc_source_payload_error; +assign main_rx_cdc_cdc_asyncfifo_din = {main_rx_cdc_cdc_fifo_in_last, main_rx_cdc_cdc_fifo_in_first, main_rx_cdc_cdc_fifo_in_payload_error, main_rx_cdc_cdc_fifo_in_payload_last_be, main_rx_cdc_cdc_fifo_in_payload_data}; +assign {main_rx_cdc_cdc_fifo_out_last, main_rx_cdc_cdc_fifo_out_first, main_rx_cdc_cdc_fifo_out_payload_error, main_rx_cdc_cdc_fifo_out_payload_last_be, main_rx_cdc_cdc_fifo_out_payload_data} = main_rx_cdc_cdc_asyncfifo_dout; +assign main_rx_cdc_cdc_sink_ready = main_rx_cdc_cdc_asyncfifo_writable; +assign main_rx_cdc_cdc_asyncfifo_we = main_rx_cdc_cdc_sink_valid; +assign main_rx_cdc_cdc_fifo_in_first = main_rx_cdc_cdc_sink_first; +assign main_rx_cdc_cdc_fifo_in_last = main_rx_cdc_cdc_sink_last; +assign main_rx_cdc_cdc_fifo_in_payload_data = main_rx_cdc_cdc_sink_payload_data; +assign main_rx_cdc_cdc_fifo_in_payload_last_be = main_rx_cdc_cdc_sink_payload_last_be; +assign main_rx_cdc_cdc_fifo_in_payload_error = main_rx_cdc_cdc_sink_payload_error; +assign main_rx_cdc_cdc_source_valid = main_rx_cdc_cdc_asyncfifo_readable; +assign main_rx_cdc_cdc_source_first = main_rx_cdc_cdc_fifo_out_first; +assign main_rx_cdc_cdc_source_last = main_rx_cdc_cdc_fifo_out_last; +assign main_rx_cdc_cdc_source_payload_data = main_rx_cdc_cdc_fifo_out_payload_data; +assign main_rx_cdc_cdc_source_payload_last_be = main_rx_cdc_cdc_fifo_out_payload_last_be; +assign main_rx_cdc_cdc_source_payload_error = main_rx_cdc_cdc_fifo_out_payload_error; +assign main_rx_cdc_cdc_asyncfifo_re = main_rx_cdc_cdc_source_ready; +assign main_rx_cdc_cdc_graycounter0_ce = (main_rx_cdc_cdc_asyncfifo_writable & main_rx_cdc_cdc_asyncfifo_we); +assign main_rx_cdc_cdc_graycounter1_ce = (main_rx_cdc_cdc_asyncfifo_readable & main_rx_cdc_cdc_asyncfifo_re); +assign main_rx_cdc_cdc_asyncfifo_writable = (((main_rx_cdc_cdc_graycounter0_q[5] == main_rx_cdc_cdc_consume_wdomain[5]) | (main_rx_cdc_cdc_graycounter0_q[4] == main_rx_cdc_cdc_consume_wdomain[4])) | (main_rx_cdc_cdc_graycounter0_q[3:0] != main_rx_cdc_cdc_consume_wdomain[3:0])); +assign main_rx_cdc_cdc_asyncfifo_readable = (main_rx_cdc_cdc_graycounter1_q != main_rx_cdc_cdc_produce_rdomain); +assign main_rx_cdc_cdc_wrport_adr = main_rx_cdc_cdc_graycounter0_q_binary[4:0]; +assign main_rx_cdc_cdc_wrport_dat_w = main_rx_cdc_cdc_asyncfifo_din; +assign main_rx_cdc_cdc_wrport_we = main_rx_cdc_cdc_graycounter0_ce; +assign main_rx_cdc_cdc_rdport_adr = main_rx_cdc_cdc_graycounter1_q_next_binary[4:0]; +assign main_rx_cdc_cdc_asyncfifo_dout = main_rx_cdc_cdc_rdport_dat_r; +always @(*) begin + main_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (main_rx_cdc_cdc_graycounter0_ce) begin + main_rx_cdc_cdc_graycounter0_q_next_binary <= (main_rx_cdc_cdc_graycounter0_q_binary + 1'd1); + end else begin + main_rx_cdc_cdc_graycounter0_q_next_binary <= main_rx_cdc_cdc_graycounter0_q_binary; + end +end +assign main_rx_cdc_cdc_graycounter0_q_next = (main_rx_cdc_cdc_graycounter0_q_next_binary ^ main_rx_cdc_cdc_graycounter0_q_next_binary[5:1]); +always @(*) begin + main_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (main_rx_cdc_cdc_graycounter1_ce) begin + main_rx_cdc_cdc_graycounter1_q_next_binary <= (main_rx_cdc_cdc_graycounter1_q_binary + 1'd1); + end else begin + main_rx_cdc_cdc_graycounter1_q_next_binary <= main_rx_cdc_cdc_graycounter1_q_binary; + end +end +assign main_rx_cdc_cdc_graycounter1_q_next = (main_rx_cdc_cdc_graycounter1_q_next_binary ^ main_rx_cdc_cdc_graycounter1_q_next_binary[5:1]); +assign main_rx_preamble_sink_valid = main_maccore_ethphy_source_source_valid; +assign main_maccore_ethphy_source_source_ready = main_rx_preamble_sink_ready; +assign main_rx_preamble_sink_first = main_maccore_ethphy_source_source_first; +assign main_rx_preamble_sink_last = main_maccore_ethphy_source_source_last; +assign main_rx_preamble_sink_payload_data = main_maccore_ethphy_source_source_payload_data; +assign main_rx_preamble_sink_payload_last_be = main_maccore_ethphy_source_source_payload_last_be; +assign main_rx_preamble_sink_payload_error = main_maccore_ethphy_source_source_payload_error; +assign main_bufferizeendpoints_sink_sink_valid = main_rx_preamble_source_valid; +assign main_rx_preamble_source_ready = main_bufferizeendpoints_sink_sink_ready; +assign main_bufferizeendpoints_sink_sink_first = main_rx_preamble_source_first; +assign main_bufferizeendpoints_sink_sink_last = main_rx_preamble_source_last; +assign main_bufferizeendpoints_sink_sink_payload_data = main_rx_preamble_source_payload_data; +assign main_bufferizeendpoints_sink_sink_payload_last_be = main_rx_preamble_source_payload_last_be; +assign main_bufferizeendpoints_sink_sink_payload_error = main_rx_preamble_source_payload_error; +assign main_rx_padding_sink_valid = main_liteethmaccrc32checker_source_source_valid; +assign main_liteethmaccrc32checker_source_source_ready = main_rx_padding_sink_ready; +assign main_rx_padding_sink_first = main_liteethmaccrc32checker_source_source_first; +assign main_rx_padding_sink_last = main_liteethmaccrc32checker_source_source_last; +assign main_rx_padding_sink_payload_data = main_liteethmaccrc32checker_source_source_payload_data; +assign main_rx_padding_sink_payload_last_be = main_liteethmaccrc32checker_source_source_payload_last_be; +assign main_rx_padding_sink_payload_error = main_liteethmaccrc32checker_source_source_payload_error; +assign main_rx_last_be_sink_valid = main_rx_padding_source_valid; +assign main_rx_padding_source_ready = main_rx_last_be_sink_ready; +assign main_rx_last_be_sink_first = main_rx_padding_source_first; +assign main_rx_last_be_sink_last = main_rx_padding_source_last; +assign main_rx_last_be_sink_payload_data = main_rx_padding_source_payload_data; +assign main_rx_last_be_sink_payload_last_be = main_rx_padding_source_payload_last_be; +assign main_rx_last_be_sink_payload_error = main_rx_padding_source_payload_error; +assign main_rx_converter_sink_valid = main_rx_last_be_source_valid; +assign main_rx_last_be_source_ready = main_rx_converter_sink_ready; +assign main_rx_converter_sink_first = main_rx_last_be_source_first; +assign main_rx_converter_sink_last = main_rx_last_be_source_last; +assign main_rx_converter_sink_payload_data = main_rx_last_be_source_payload_data; +assign main_rx_converter_sink_payload_last_be = main_rx_last_be_source_payload_last_be; +assign main_rx_converter_sink_payload_error = main_rx_last_be_source_payload_error; +assign main_rx_cdc_sink_sink_valid = main_rx_converter_source_valid; +assign main_rx_converter_source_ready = main_rx_cdc_sink_sink_ready; +assign main_rx_cdc_sink_sink_first = main_rx_converter_source_first; +assign main_rx_cdc_sink_sink_last = main_rx_converter_source_last; +assign main_rx_cdc_sink_sink_payload_data = main_rx_converter_source_payload_data; +assign main_rx_cdc_sink_sink_payload_last_be = main_rx_converter_source_payload_last_be; +assign main_rx_cdc_sink_sink_payload_error = main_rx_converter_source_payload_error; +assign main_source_valid = main_rx_cdc_source_source_valid; +assign main_rx_cdc_source_source_ready = main_source_ready; +assign main_source_first = main_rx_cdc_source_source_first; +assign main_source_last = main_rx_cdc_source_source_last; +assign main_source_payload_data = main_rx_cdc_source_source_payload_data; +assign main_source_payload_last_be = main_rx_cdc_source_source_payload_last_be; +assign main_source_payload_error = main_rx_cdc_source_source_payload_error; +assign main_sram0_sink_valid = main_sink_sink_valid; +assign main_sink_sink_ready = main_sram1_sink_ready; +assign main_sram2_sink_first = main_sink_sink_first; +assign main_sram3_sink_last = main_sink_sink_last; +assign main_sram4_sink_payload_data = main_sink_sink_payload_data; +assign main_sram5_sink_payload_last_be = main_sink_sink_payload_last_be; +assign main_sram6_sink_payload_error = main_sink_sink_payload_error; +assign main_source_source_valid = main_sram83_source_valid; +assign main_sram84_source_ready = main_source_source_ready; +assign main_source_source_first = main_sram85_source_first; +assign main_source_source_last = main_sram86_source_last; +assign main_source_source_payload_data = main_sram87_source_payload_data; +assign main_source_source_payload_last_be = main_sram88_source_payload_last_be; +assign main_source_source_payload_error = main_sram89_source_payload_error; +always @(*) begin + main_length_inc <= 4'd0; + case (main_sram5_sink_payload_last_be) + 1'd1: begin + main_length_inc <= 1'd1; + end + 2'd2: begin + main_length_inc <= 2'd2; + end + 3'd4: begin + main_length_inc <= 2'd3; + end + 4'd8: begin + main_length_inc <= 3'd4; + end + 5'd16: begin + main_length_inc <= 3'd5; + end + 6'd32: begin + main_length_inc <= 3'd6; + end + 7'd64: begin + main_length_inc <= 3'd7; + end + default: begin + main_length_inc <= 3'd4; + end + endcase +end +assign main_sram44_source_ready = main_sram20_clear; +assign main_sram19_trigger = main_sram43_source_valid; +assign main_sram7_status = main_sram47_source_payload_slot; +assign main_sram10_status = main_sram48_source_payload_length; +assign main_wr_data = main_sram4_sink_payload_data; +always @(*) begin + main_sram75_adr <= 9'd0; + main_sram77_we <= 1'd0; + main_sram78_dat_w <= 32'd0; + main_sram79_adr <= 9'd0; + main_sram81_we <= 1'd0; + main_sram82_dat_w <= 32'd0; + case (main_slot) + 1'd0: begin + main_sram75_adr <= main_sram35_length[10:2]; + main_sram78_dat_w <= main_wr_data; + if ((main_sram0_sink_valid & main_write)) begin + main_sram77_we <= 1'd1; + end + end + 1'd1: begin + main_sram79_adr <= main_sram35_length[10:2]; + main_sram82_dat_w <= main_wr_data; + if ((main_sram0_sink_valid & main_write)) begin + main_sram81_we <= 1'd1; + end + end + endcase +end +assign main_sram21_available = main_sram17_status; +assign main_sram25_available = main_sram18_pending; +always @(*) begin + main_sram20_clear <= 1'd0; + if ((main_sram28_re & main_sram29_r)) begin + main_sram20_clear <= 1'd1; + end +end +assign main_sram16_irq = (main_sram26_status & main_sram31_storage); +assign main_sram17_status = main_sram19_trigger; +assign main_sram18_pending = main_sram19_trigger; +assign main_sram53_din = {main_sram69_fifo_in_last, main_sram68_fifo_in_first, main_sram67_fifo_in_payload_length, main_sram66_fifo_in_payload_slot}; +assign {main_sram73_fifo_out_last, main_sram72_fifo_out_first, main_sram71_fifo_out_payload_length, main_sram70_fifo_out_payload_slot} = main_sram54_dout; +assign main_sram38_sink_ready = main_sram50_writable; +assign main_sram49_we = main_sram37_sink_valid; +assign main_sram68_fifo_in_first = main_sram39_sink_first; +assign main_sram69_fifo_in_last = main_sram40_sink_last; +assign main_sram66_fifo_in_payload_slot = main_sram41_sink_payload_slot; +assign main_sram67_fifo_in_payload_length = main_sram42_sink_payload_length; +assign main_sram43_source_valid = main_sram52_readable; +assign main_sram45_source_first = main_sram72_fifo_out_first; +assign main_sram46_source_last = main_sram73_fifo_out_last; +assign main_sram47_source_payload_slot = main_sram70_fifo_out_payload_slot; +assign main_sram48_source_payload_length = main_sram71_fifo_out_payload_length; +assign main_sram51_re = main_sram44_source_ready; +always @(*) begin + main_sram59_adr <= 1'd0; + if (main_sram56_replace) begin + main_sram59_adr <= (main_sram57_produce - 1'd1); + end else begin + main_sram59_adr <= main_sram57_produce; + end +end +assign main_sram62_dat_w = main_sram53_din; +assign main_sram61_we = (main_sram49_we & (main_sram50_writable | main_sram56_replace)); +assign main_sram63_do_read = (main_sram52_readable & main_sram51_re); +assign main_sram64_adr = main_sram58_consume; +assign main_sram54_dout = main_sram65_dat_r; +assign main_sram50_writable = (main_sram55_level != 2'd2); +assign main_sram52_readable = (main_sram55_level != 1'd0); +always @(*) begin + builder_liteethmacsramwriter_next_state <= 3'd0; + main_slot_liteethmacsramwriter_next_value <= 1'd0; + main_slot_liteethmacsramwriter_next_value_ce <= 1'd0; + main_sram13_status_liteethmacsramwriter_f_next_value <= 32'd0; + main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value <= 11'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd0; + main_sram37_sink_valid <= 1'd0; + main_sram41_sink_payload_slot <= 1'd0; + main_sram42_sink_payload_length <= 11'd0; + main_write <= 1'd0; + builder_liteethmacsramwriter_next_state <= builder_liteethmacsramwriter_state; + case (builder_liteethmacsramwriter_state) + 1'd1: begin + if ((main_sram0_sink_valid & main_sram3_sink_last)) begin + if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + builder_liteethmacsramwriter_next_state <= 3'd4; + end + end + end + 2'd2: begin + if ((main_sram0_sink_valid & main_sram3_sink_last)) begin + if ((main_sram5_sink_payload_last_be != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + end + end + 2'd3: begin + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + 3'd4: begin + main_sram37_sink_valid <= 1'd1; + main_sram41_sink_payload_slot <= main_slot; + main_sram42_sink_payload_length <= main_sram35_length; + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + main_slot_liteethmacsramwriter_next_value <= (main_slot + 1'd1); + main_slot_liteethmacsramwriter_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + default: begin + if (main_sram0_sink_valid) begin + if (main_sram38_sink_ready) begin + main_write <= 1'd1; + main_sram35_length_liteethmacsramwriter_t_next_value <= (main_sram35_length + main_length_inc); + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + if ((main_sram35_length >= 11'd1530)) begin + builder_liteethmacsramwriter_next_state <= 1'd1; + end + if (main_sram3_sink_last) begin + if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + builder_liteethmacsramwriter_next_state <= 3'd4; + end + end + end else begin + main_sram13_status_liteethmacsramwriter_f_next_value <= (main_sram13_status + 1'd1); + main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 2'd2; + end + end + end + endcase +end +assign main_sram123_sink_valid = main_start_re; +assign main_sram127_sink_payload_slot = main_sram100_storage; +assign main_sram128_sink_payload_length = main_sram102_storage; +assign main_sram94_status = main_sram124_sink_ready; +assign main_sram97_status = main_sram141_level; +always @(*) begin + main_sram88_source_payload_last_be <= 4'd0; + if (main_sram86_source_last) begin + case (main_sram134_source_payload_length[1:0]) + 1'd1: begin + main_sram88_source_payload_last_be <= 1'd1; + end + 2'd2: begin + main_sram88_source_payload_last_be <= 2'd2; + end + 2'd3: begin + main_sram88_source_payload_last_be <= 3'd4; + end + 3'd4: begin + main_sram88_source_payload_last_be <= 4'd8; + end + 3'd5: begin + main_sram88_source_payload_last_be <= 5'd16; + end + 3'd6: begin + main_sram88_source_payload_last_be <= 6'd32; + end + 3'd7: begin + main_sram88_source_payload_last_be <= 7'd64; + end + default: begin + main_sram88_source_payload_last_be <= 4'd8; + end + endcase + end +end +assign main_sram163_re = main_read; +assign main_sram161_adr = main_sram122_length[10:2]; +assign main_sram166_re = main_read; +assign main_sram164_adr = main_sram122_length[10:2]; +always @(*) begin + main_rd_data <= 32'd0; + case (main_sram133_source_payload_slot) + 1'd0: begin + main_rd_data <= main_sram162_dat_r; + end + 1'd1: begin + main_rd_data <= main_sram165_dat_r; + end + endcase +end +assign main_sram87_source_payload_data = main_rd_data; +assign main_sram109_event0 = main_sram105_status; +assign main_sram113_event0 = main_sram106_pending; +always @(*) begin + main_sram108_clear <= 1'd0; + if ((main_sram116_re & main_sram117_r)) begin + main_sram108_clear <= 1'd1; + end +end +assign main_sram104_irq = (main_sram114_status & main_sram119_storage); +assign main_sram105_status = 1'd0; +assign main_sram139_din = {main_sram155_fifo_in_last, main_sram154_fifo_in_first, main_sram153_fifo_in_payload_length, main_sram152_fifo_in_payload_slot}; +assign {main_sram159_fifo_out_last, main_sram158_fifo_out_first, main_sram157_fifo_out_payload_length, main_sram156_fifo_out_payload_slot} = main_sram140_dout; +assign main_sram124_sink_ready = main_sram136_writable; +assign main_sram135_we = main_sram123_sink_valid; +assign main_sram154_fifo_in_first = main_sram125_sink_first; +assign main_sram155_fifo_in_last = main_sram126_sink_last; +assign main_sram152_fifo_in_payload_slot = main_sram127_sink_payload_slot; +assign main_sram153_fifo_in_payload_length = main_sram128_sink_payload_length; +assign main_sram129_source_valid = main_sram138_readable; +assign main_sram131_source_first = main_sram158_fifo_out_first; +assign main_sram132_source_last = main_sram159_fifo_out_last; +assign main_sram133_source_payload_slot = main_sram156_fifo_out_payload_slot; +assign main_sram134_source_payload_length = main_sram157_fifo_out_payload_length; +assign main_sram137_re = main_sram130_source_ready; +always @(*) begin + main_sram145_adr <= 1'd0; + if (main_sram142_replace) begin + main_sram145_adr <= (main_sram143_produce - 1'd1); + end else begin + main_sram145_adr <= main_sram143_produce; + end +end +assign main_sram148_dat_w = main_sram139_din; +assign main_sram147_we = (main_sram135_we & (main_sram136_writable | main_sram142_replace)); +assign main_sram149_do_read = (main_sram138_readable & main_sram137_re); +assign main_sram150_adr = main_sram144_consume; +assign main_sram140_dout = main_sram151_dat_r; +assign main_sram136_writable = (main_sram141_level != 2'd2); +assign main_sram138_readable = (main_sram141_level != 1'd0); +always @(*) begin + builder_liteethmacsramreader_next_state <= 2'd0; + main_read <= 1'd0; + main_sram107_trigger <= 1'd0; + main_sram122_length_liteethmacsramreader_next_value <= 11'd0; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd0; + main_sram130_source_ready <= 1'd0; + main_sram83_source_valid <= 1'd0; + main_sram86_source_last <= 1'd0; + builder_liteethmacsramreader_next_state <= builder_liteethmacsramreader_state; + case (builder_liteethmacsramreader_state) + 1'd1: begin + main_sram83_source_valid <= 1'd1; + main_sram86_source_last <= (main_sram122_length >= main_sram134_source_payload_length); + if (main_sram84_source_ready) begin + main_read <= 1'd1; + main_sram122_length_liteethmacsramreader_next_value <= (main_sram122_length + 3'd4); + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + if (main_sram86_source_last) begin + builder_liteethmacsramreader_next_state <= 2'd2; + end + end + end + 2'd2: begin + main_sram122_length_liteethmacsramreader_next_value <= 1'd0; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + main_sram107_trigger <= 1'd1; + main_sram130_source_ready <= 1'd1; + builder_liteethmacsramreader_next_state <= 1'd0; + end + default: begin + if (main_sram129_source_valid) begin + main_read <= 1'd1; + main_sram122_length_liteethmacsramreader_next_value <= 3'd4; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + builder_liteethmacsramreader_next_state <= 1'd1; + end + end + endcase +end +assign main_sram167_irq = (main_sram16_irq | main_sram104_irq); +assign main_sram0_adr = main_interface0_adr[8:0]; +assign main_interface0_dat_r = main_sram0_dat_r; +assign main_sram1_adr = main_interface1_adr[8:0]; +assign main_interface1_dat_r = main_sram1_dat_r; +always @(*) begin + main_sram2_we <= 4'd0; + main_sram2_we[0] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[0]); + main_sram2_we[1] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[1]); + main_sram2_we[2] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[2]); + main_sram2_we[3] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[3]); +end +assign main_sram2_adr = main_interface2_adr[8:0]; +assign main_interface2_dat_r = main_sram2_dat_r; +assign main_sram2_dat_w = main_interface2_dat_w; +always @(*) begin + main_sram3_we <= 4'd0; + main_sram3_we[0] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[0]); + main_sram3_we[1] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[1]); + main_sram3_we[2] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[2]); + main_sram3_we[3] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[3]); +end +assign main_sram3_adr = main_interface3_adr[8:0]; +assign main_interface3_dat_r = main_sram3_dat_r; +assign main_sram3_dat_w = main_interface3_dat_w; +always @(*) begin + main_slave_sel <= 4'd0; + main_slave_sel[0] <= (main_bus_adr[10:9] == 1'd0); + main_slave_sel[1] <= (main_bus_adr[10:9] == 1'd1); + main_slave_sel[2] <= (main_bus_adr[10:9] == 2'd2); + main_slave_sel[3] <= (main_bus_adr[10:9] == 2'd3); +end +assign main_interface0_adr = main_bus_adr; +assign main_interface0_dat_w = main_bus_dat_w; +assign main_interface0_sel = main_bus_sel; +assign main_interface0_stb = main_bus_stb; +assign main_interface0_we = main_bus_we; +assign main_interface0_cti = main_bus_cti; +assign main_interface0_bte = main_bus_bte; +assign main_interface1_adr = main_bus_adr; +assign main_interface1_dat_w = main_bus_dat_w; +assign main_interface1_sel = main_bus_sel; +assign main_interface1_stb = main_bus_stb; +assign main_interface1_we = main_bus_we; +assign main_interface1_cti = main_bus_cti; +assign main_interface1_bte = main_bus_bte; +assign main_interface2_adr = main_bus_adr; +assign main_interface2_dat_w = main_bus_dat_w; +assign main_interface2_sel = main_bus_sel; +assign main_interface2_stb = main_bus_stb; +assign main_interface2_we = main_bus_we; +assign main_interface2_cti = main_bus_cti; +assign main_interface2_bte = main_bus_bte; +assign main_interface3_adr = main_bus_adr; +assign main_interface3_dat_w = main_bus_dat_w; +assign main_interface3_sel = main_bus_sel; +assign main_interface3_stb = main_bus_stb; +assign main_interface3_we = main_bus_we; +assign main_interface3_cti = main_bus_cti; +assign main_interface3_bte = main_bus_bte; +assign main_interface0_cyc = (main_bus_cyc & main_slave_sel[0]); +assign main_interface1_cyc = (main_bus_cyc & main_slave_sel[1]); +assign main_interface2_cyc = (main_bus_cyc & main_slave_sel[2]); +assign main_interface3_cyc = (main_bus_cyc & main_slave_sel[3]); +assign main_bus_ack = (((main_interface0_ack | main_interface1_ack) | main_interface2_ack) | main_interface3_ack); +assign main_bus_err = (((main_interface0_err | main_interface1_err) | main_interface2_err) | main_interface3_err); +assign main_bus_dat_r = (((({32{main_slave_sel_r[0]}} & main_interface0_dat_r) | ({32{main_slave_sel_r[1]}} & main_interface1_dat_r)) | ({32{main_slave_sel_r[2]}} & main_interface2_dat_r)) | ({32{main_slave_sel_r[3]}} & main_interface3_dat_r)); +always @(*) begin + builder_interface0_ack <= 1'd0; + builder_interface0_dat_r <= 32'd0; + builder_interface1_adr <= 14'd0; + builder_interface1_dat_w <= 32'd0; + builder_interface1_we <= 1'd0; + builder_wishbone2csr_next_state <= 1'd0; + builder_wishbone2csr_next_state <= builder_wishbone2csr_state; + case (builder_wishbone2csr_state) + 1'd1: begin + builder_interface0_ack <= 1'd1; + builder_interface0_dat_r <= builder_interface1_dat_r; + builder_wishbone2csr_next_state <= 1'd0; + end + default: begin + builder_interface1_dat_w <= builder_interface0_dat_w; + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_adr <= builder_interface0_adr[29:0]; + builder_interface1_we <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); + builder_wishbone2csr_next_state <= 1'd1; + end + end + endcase +end +assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); +assign builder_csrbank0_reset0_r = builder_interface0_bank_bus_dat_w[1:0]; +always @(*) begin + builder_csrbank0_reset0_re <= 1'd0; + builder_csrbank0_reset0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_reset0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_reset0_we <= (~builder_interface0_bank_bus_we); + end +end +assign builder_csrbank0_scratch0_r = builder_interface0_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank0_scratch0_re <= 1'd0; + builder_csrbank0_scratch0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_scratch0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_scratch0_we <= (~builder_interface0_bank_bus_we); + end +end +assign builder_csrbank0_bus_errors_r = builder_interface0_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank0_bus_errors_re <= 1'd0; + builder_csrbank0_bus_errors_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank0_bus_errors_re <= builder_interface0_bank_bus_we; + builder_csrbank0_bus_errors_we <= (~builder_interface0_bank_bus_we); + end +end +always @(*) begin + main_maccore_maccore_soc_rst <= 1'd0; + if (main_maccore_maccore_reset_re) begin + main_maccore_maccore_soc_rst <= main_maccore_maccore_reset_storage[0]; + end +end +assign main_maccore_maccore_cpu_rst = main_maccore_maccore_reset_storage[1]; +assign builder_csrbank0_reset0_w = main_maccore_maccore_reset_storage[1:0]; +assign builder_csrbank0_scratch0_w = main_maccore_maccore_scratch_storage[31:0]; +assign builder_csrbank0_bus_errors_w = main_maccore_maccore_bus_errors_status[31:0]; +assign main_maccore_maccore_bus_errors_we = builder_csrbank0_bus_errors_we; +assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2); +assign builder_csrbank1_sram_writer_slot_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_writer_slot_re <= 1'd0; + builder_csrbank1_sram_writer_slot_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_sram_writer_slot_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_slot_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_length_r = builder_interface1_bank_bus_dat_w[10:0]; +always @(*) begin + builder_csrbank1_sram_writer_length_re <= 1'd0; + builder_csrbank1_sram_writer_length_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_sram_writer_length_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_length_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank1_sram_writer_errors_re <= 1'd0; + builder_csrbank1_sram_writer_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_sram_writer_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_errors_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_ev_status_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_writer_ev_status_re <= 1'd0; + builder_csrbank1_sram_writer_ev_status_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank1_sram_writer_ev_status_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_status_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_writer_ev_pending_re <= 1'd0; + builder_csrbank1_sram_writer_ev_pending_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank1_sram_writer_ev_pending_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_pending_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_writer_ev_enable0_re <= 1'd0; + builder_csrbank1_sram_writer_ev_enable0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank1_sram_writer_ev_enable0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_enable0_we <= (~builder_interface1_bank_bus_we); + end +end +assign main_start_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + main_start_re <= 1'd0; + main_start_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_start_re <= builder_interface1_bank_bus_we; + main_start_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_ready_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_ready_re <= 1'd0; + builder_csrbank1_sram_reader_ready_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank1_sram_reader_ready_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ready_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_level_r = builder_interface1_bank_bus_dat_w[1:0]; +always @(*) begin + builder_csrbank1_sram_reader_level_re <= 1'd0; + builder_csrbank1_sram_reader_level_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + builder_csrbank1_sram_reader_level_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_level_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_slot0_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_slot0_re <= 1'd0; + builder_csrbank1_sram_reader_slot0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank1_sram_reader_slot0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_slot0_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_length0_r = builder_interface1_bank_bus_dat_w[10:0]; +always @(*) begin + builder_csrbank1_sram_reader_length0_re <= 1'd0; + builder_csrbank1_sram_reader_length0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank1_sram_reader_length0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_length0_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_ev_status_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_ev_status_re <= 1'd0; + builder_csrbank1_sram_reader_ev_status_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank1_sram_reader_ev_status_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_status_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_ev_pending_re <= 1'd0; + builder_csrbank1_sram_reader_ev_pending_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank1_sram_reader_ev_pending_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_pending_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_ev_enable0_re <= 1'd0; + builder_csrbank1_sram_reader_ev_enable0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank1_sram_reader_ev_enable0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_enable0_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_preamble_crc_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_preamble_crc_re <= 1'd0; + builder_csrbank1_preamble_crc_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin + builder_csrbank1_preamble_crc_re <= builder_interface1_bank_bus_we; + builder_csrbank1_preamble_crc_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_rx_datapath_preamble_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank1_rx_datapath_preamble_errors_re <= 1'd0; + builder_csrbank1_rx_datapath_preamble_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin + builder_csrbank1_rx_datapath_preamble_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rx_datapath_preamble_errors_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_rx_datapath_crc_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank1_rx_datapath_crc_errors_re <= 1'd0; + builder_csrbank1_rx_datapath_crc_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank1_rx_datapath_crc_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rx_datapath_crc_errors_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_slot_w = main_sram7_status; +assign main_sram8_we = builder_csrbank1_sram_writer_slot_we; +assign builder_csrbank1_sram_writer_length_w = main_sram10_status[10:0]; +assign main_sram11_we = builder_csrbank1_sram_writer_length_we; +assign builder_csrbank1_sram_writer_errors_w = main_sram13_status[31:0]; +assign main_sram14_we = builder_csrbank1_sram_writer_errors_we; +always @(*) begin + main_sram22_status <= 1'd0; + main_sram22_status <= main_sram21_available; +end +assign builder_csrbank1_sram_writer_ev_status_w = main_sram22_status; +assign main_sram23_we = builder_csrbank1_sram_writer_ev_status_we; +always @(*) begin + main_sram26_status <= 1'd0; + main_sram26_status <= main_sram25_available; +end +assign builder_csrbank1_sram_writer_ev_pending_w = main_sram26_status; +assign main_sram27_we = builder_csrbank1_sram_writer_ev_pending_we; +assign main_sram30_available = main_sram31_storage; +assign builder_csrbank1_sram_writer_ev_enable0_w = main_sram31_storage; +assign builder_csrbank1_sram_reader_ready_w = main_sram94_status; +assign main_sram95_we = builder_csrbank1_sram_reader_ready_we; +assign builder_csrbank1_sram_reader_level_w = main_sram97_status[1:0]; +assign main_sram98_we = builder_csrbank1_sram_reader_level_we; +assign builder_csrbank1_sram_reader_slot0_w = main_sram100_storage; +assign builder_csrbank1_sram_reader_length0_w = main_sram102_storage[10:0]; +always @(*) begin + main_sram110_status <= 1'd0; + main_sram110_status <= main_sram109_event0; +end +assign builder_csrbank1_sram_reader_ev_status_w = main_sram110_status; +assign main_sram111_we = builder_csrbank1_sram_reader_ev_status_we; +always @(*) begin + main_sram114_status <= 1'd0; + main_sram114_status <= main_sram113_event0; +end +assign builder_csrbank1_sram_reader_ev_pending_w = main_sram114_status; +assign main_sram115_we = builder_csrbank1_sram_reader_ev_pending_we; +assign main_sram118_event0 = main_sram119_storage; +assign builder_csrbank1_sram_reader_ev_enable0_w = main_sram119_storage; +assign builder_csrbank1_preamble_crc_w = main_status; +assign main_we = builder_csrbank1_preamble_crc_we; +assign builder_csrbank1_rx_datapath_preamble_errors_w = main_preamble_errors_status[31:0]; +assign main_preamble_errors_we = builder_csrbank1_rx_datapath_preamble_errors_we; +assign builder_csrbank1_rx_datapath_crc_errors_w = main_crc_errors_status[31:0]; +assign main_crc_errors_we = builder_csrbank1_rx_datapath_crc_errors_we; +assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd1); +assign builder_csrbank2_mode_detection_mode_r = builder_interface2_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank2_mode_detection_mode_re <= 1'd0; + builder_csrbank2_mode_detection_mode_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_mode_detection_mode_re <= builder_interface2_bank_bus_we; + builder_csrbank2_mode_detection_mode_we <= (~builder_interface2_bank_bus_we); + end +end +assign builder_csrbank2_crg_reset0_r = builder_interface2_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank2_crg_reset0_re <= 1'd0; + builder_csrbank2_crg_reset0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_crg_reset0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_crg_reset0_we <= (~builder_interface2_bank_bus_we); + end +end +assign builder_csrbank2_mdio_w0_r = builder_interface2_bank_bus_dat_w[2:0]; +always @(*) begin + builder_csrbank2_mdio_w0_re <= 1'd0; + builder_csrbank2_mdio_w0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank2_mdio_w0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_mdio_w0_we <= (~builder_interface2_bank_bus_we); + end +end +assign builder_csrbank2_mdio_r_r = builder_interface2_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank2_mdio_r_re <= 1'd0; + builder_csrbank2_mdio_r_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank2_mdio_r_re <= builder_interface2_bank_bus_we; + builder_csrbank2_mdio_r_we <= (~builder_interface2_bank_bus_we); + end +end +assign builder_csrbank2_mode_detection_mode_w = main_maccore_ethphy_mode_status; +assign main_maccore_ethphy_mode_we = builder_csrbank2_mode_detection_mode_we; +assign builder_csrbank2_crg_reset0_w = main_maccore_ethphy_reset_storage; +assign main_maccore_ethphy_mdc = main_maccore_ethphy__w_storage[0]; +assign main_maccore_ethphy_oe = main_maccore_ethphy__w_storage[1]; +assign main_maccore_ethphy_w = main_maccore_ethphy__w_storage[2]; +assign builder_csrbank2_mdio_w0_w = main_maccore_ethphy__w_storage[2:0]; +assign builder_csrbank2_mdio_r_w = main_maccore_ethphy__r_status; +assign main_maccore_ethphy__r_we = builder_csrbank2_mdio_r_we; +assign builder_adr = builder_interface1_adr; +assign builder_we = builder_interface1_we; +assign builder_dat_w = builder_interface1_dat_w; +assign builder_interface1_dat_r = builder_dat_r; +assign builder_interface0_bank_bus_adr = builder_adr; +assign builder_interface1_bank_bus_adr = builder_adr; +assign builder_interface2_bank_bus_adr = builder_adr; +assign builder_interface0_bank_bus_we = builder_we; +assign builder_interface1_bank_bus_we = builder_we; +assign builder_interface2_bank_bus_we = builder_we; +assign builder_interface0_bank_bus_dat_w = builder_dat_w; +assign builder_interface1_bank_bus_dat_w = builder_dat_w; +assign builder_interface2_bank_bus_dat_w = builder_dat_w; +assign builder_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); +assign builder_t_slice_proxy0 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy1 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy2 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy3 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy4 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy5 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy6 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy7 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy8 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy9 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy10 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy11 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy12 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy13 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy14 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy15 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy16 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy17 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy18 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy19 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy20 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy21 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy22 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy23 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy24 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy25 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy26 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy27 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy28 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy29 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy30 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy31 = (~main_tx_crc_crc_next); +assign builder_complexslicelowerer_slice_proxy = {main_tx_crc_value, main_tx_crc_sink_payload_data[7:0]}; +assign builder_t_slice_proxy32 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy33 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy34 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy35 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy36 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy37 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy38 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy39 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy40 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy41 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy42 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy43 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy44 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy45 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy46 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy47 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy48 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy49 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy50 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy51 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy52 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy53 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy54 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy55 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy56 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy57 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy58 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy59 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy60 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy61 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy62 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy63 = (~main_liteethmaccrc32checker_crc_crc_next); +always @(*) begin + builder_self0 <= 30'd0; + case (builder_grant) + default: begin + builder_self0 <= main_wb_bus_adr; + end + endcase +end +always @(*) begin + builder_self1 <= 32'd0; + case (builder_grant) + default: begin + builder_self1 <= main_wb_bus_dat_w; + end + endcase +end +always @(*) begin + builder_self2 <= 4'd0; + case (builder_grant) + default: begin + builder_self2 <= main_wb_bus_sel; + end + endcase +end +always @(*) begin + builder_self3 <= 1'd0; + case (builder_grant) + default: begin + builder_self3 <= main_wb_bus_cyc; + end + endcase +end +always @(*) begin + builder_self4 <= 1'd0; + case (builder_grant) + default: begin + builder_self4 <= main_wb_bus_stb; + end + endcase +end +always @(*) begin + builder_self5 <= 1'd0; + case (builder_grant) + default: begin + builder_self5 <= main_wb_bus_we; + end + endcase +end +always @(*) begin + builder_self6 <= 3'd0; + case (builder_grant) + default: begin + builder_self6 <= main_wb_bus_cti; + end + endcase +end +always @(*) begin + builder_self7 <= 2'd0; + case (builder_grant) + default: begin + builder_self7 <= main_wb_bus_bte; + end + endcase +end +assign main_maccore_ethphy_toggle_o = builder_xilinxmultiregimpl01; +always @(*) begin + main_maccore_ethphy__r_status <= 1'd0; + main_maccore_ethphy__r_status <= main_maccore_ethphy_r; + main_maccore_ethphy__r_status <= builder_xilinxmultiregimpl11; +end +assign main_tx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl21; +assign main_tx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl31; +assign main_pulsesynchronizer0_toggle_o = builder_xilinxmultiregimpl41; +assign main_pulsesynchronizer1_toggle_o = builder_xilinxmultiregimpl51; +assign main_rx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl61; +assign main_rx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl71; + + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ always @(posedge eth_rx_clk) begin - maccore_ethphy_eth_counter <= (maccore_ethphy_eth_counter + 1'd1); - if (maccore_ethphy_i) begin - maccore_ethphy_toggle_i <= (~maccore_ethphy_toggle_i); - end - maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv <= gmii_eth_rx_dv; - maccore_ethphy_liteethphygmiimiirx_pads_d_rx_data <= gmii_eth_rx_data; - maccore_ethphy_liteethphygmiimiirx_gmii_rx_dv_d <= maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv; - maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_valid <= maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv; - maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_data <= maccore_ethphy_liteethphygmiimiirx_pads_d_rx_data; - maccore_ethphy_liteethphygmiimiirx_converter_reset <= (~maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv); - maccore_ethphy_liteethphygmiimiirx_converter_sink_valid <= 1'd1; - maccore_ethphy_liteethphygmiimiirx_converter_sink_payload_data <= maccore_ethphy_liteethphygmiimiirx_pads_d_rx_data; - if (maccore_ethphy_liteethphygmiimiirx_converter_converter_source_ready) begin - maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all <= 1'd0; - end - if (maccore_ethphy_liteethphygmiimiirx_converter_converter_load_part) begin - if (((maccore_ethphy_liteethphygmiimiirx_converter_converter_demux == 1'd1) | maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_last)) begin - maccore_ethphy_liteethphygmiimiirx_converter_converter_demux <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all <= 1'd1; - end else begin - maccore_ethphy_liteethphygmiimiirx_converter_converter_demux <= (maccore_ethphy_liteethphygmiimiirx_converter_converter_demux + 1'd1); - end - end - if ((maccore_ethphy_liteethphygmiimiirx_converter_converter_source_valid & maccore_ethphy_liteethphygmiimiirx_converter_converter_source_ready)) begin - if ((maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_valid & maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_ready)) begin - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_first <= maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_first; - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_last <= maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_last; - end else begin - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_first <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_last <= 1'd0; - end - end else begin - if ((maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_valid & maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_ready)) begin - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_first <= (maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_first | maccore_ethphy_liteethphygmiimiirx_converter_converter_source_first); - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_last <= (maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_last | maccore_ethphy_liteethphygmiimiirx_converter_converter_source_last); - end - end - if (maccore_ethphy_liteethphygmiimiirx_converter_converter_load_part) begin - case (maccore_ethphy_liteethphygmiimiirx_converter_converter_demux) - 1'd0: begin - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_data[3:0] <= maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_payload_data; - end - 1'd1: begin - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_data[7:4] <= maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_payload_data; - end - endcase - end - if (maccore_ethphy_liteethphygmiimiirx_converter_converter_load_part) begin - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_valid_token_count <= (maccore_ethphy_liteethphygmiimiirx_converter_converter_demux + 1'd1); - end - if (maccore_ethphy_liteethphygmiimiirx_converter_reset) begin - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_data <= 8'd0; - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_valid_token_count <= 2'd0; - maccore_ethphy_liteethphygmiimiirx_converter_converter_demux <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all <= 1'd0; - end - subfragments_liteethmacpreamblechecker_state <= subfragments_liteethmacpreamblechecker_next_state; - if (liteethmaccrc32checker_crc_ce) begin - liteethmaccrc32checker_crc_reg <= liteethmaccrc32checker_crc_next; - end - if (liteethmaccrc32checker_crc_reset) begin - liteethmaccrc32checker_crc_reg <= 32'd4294967295; - end - if (((liteethmaccrc32checker_syncfifo_syncfifo_we & liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~liteethmaccrc32checker_syncfifo_replace))) begin - if ((liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin - liteethmaccrc32checker_syncfifo_produce <= 1'd0; - end else begin - liteethmaccrc32checker_syncfifo_produce <= (liteethmaccrc32checker_syncfifo_produce + 1'd1); - end - end - if (liteethmaccrc32checker_syncfifo_do_read) begin - if ((liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin - liteethmaccrc32checker_syncfifo_consume <= 1'd0; - end else begin - liteethmaccrc32checker_syncfifo_consume <= (liteethmaccrc32checker_syncfifo_consume + 1'd1); - end - end - if (((liteethmaccrc32checker_syncfifo_syncfifo_we & liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~liteethmaccrc32checker_syncfifo_replace))) begin - if ((~liteethmaccrc32checker_syncfifo_do_read)) begin - liteethmaccrc32checker_syncfifo_level <= (liteethmaccrc32checker_syncfifo_level + 1'd1); - end - end else begin - if (liteethmaccrc32checker_syncfifo_do_read) begin - liteethmaccrc32checker_syncfifo_level <= (liteethmaccrc32checker_syncfifo_level - 1'd1); - end - end - if (liteethmaccrc32checker_fifo_reset) begin - liteethmaccrc32checker_syncfifo_level <= 3'd0; - liteethmaccrc32checker_syncfifo_produce <= 3'd0; - liteethmaccrc32checker_syncfifo_consume <= 3'd0; - end - subfragments_liteethmaccrc32checker_state <= subfragments_liteethmaccrc32checker_next_state; - if (((~crc32_checker_source_valid) | crc32_checker_source_ready)) begin - crc32_checker_source_valid <= crc32_checker_sink_valid; - crc32_checker_source_first <= crc32_checker_sink_first; - crc32_checker_source_last <= crc32_checker_sink_last; - crc32_checker_source_payload_data <= crc32_checker_sink_payload_data; - crc32_checker_source_payload_last_be <= crc32_checker_sink_payload_last_be; - crc32_checker_source_payload_error <= crc32_checker_sink_payload_error; - end - if (ps_preamble_error_i) begin - ps_preamble_error_toggle_i <= (~ps_preamble_error_toggle_i); - end - if (ps_crc_error_i) begin - ps_crc_error_toggle_i <= (~ps_crc_error_toggle_i); - end - if (rx_converter_converter_source_ready) begin - rx_converter_converter_strobe_all <= 1'd0; - end - if (rx_converter_converter_load_part) begin - if (((rx_converter_converter_demux == 2'd3) | rx_converter_converter_sink_last)) begin - rx_converter_converter_demux <= 1'd0; - rx_converter_converter_strobe_all <= 1'd1; - end else begin - rx_converter_converter_demux <= (rx_converter_converter_demux + 1'd1); - end - end - if ((rx_converter_converter_source_valid & rx_converter_converter_source_ready)) begin - if ((rx_converter_converter_sink_valid & rx_converter_converter_sink_ready)) begin - rx_converter_converter_source_first <= rx_converter_converter_sink_first; - rx_converter_converter_source_last <= rx_converter_converter_sink_last; - end else begin - rx_converter_converter_source_first <= 1'd0; - rx_converter_converter_source_last <= 1'd0; - end - end else begin - if ((rx_converter_converter_sink_valid & rx_converter_converter_sink_ready)) begin - rx_converter_converter_source_first <= (rx_converter_converter_sink_first | rx_converter_converter_source_first); - rx_converter_converter_source_last <= (rx_converter_converter_sink_last | rx_converter_converter_source_last); - end - end - if (rx_converter_converter_load_part) begin - case (rx_converter_converter_demux) - 1'd0: begin - rx_converter_converter_source_payload_data[9:0] <= rx_converter_converter_sink_payload_data; - end - 1'd1: begin - rx_converter_converter_source_payload_data[19:10] <= rx_converter_converter_sink_payload_data; - end - 2'd2: begin - rx_converter_converter_source_payload_data[29:20] <= rx_converter_converter_sink_payload_data; - end - 2'd3: begin - rx_converter_converter_source_payload_data[39:30] <= rx_converter_converter_sink_payload_data; - end - endcase - end - if (rx_converter_converter_load_part) begin - rx_converter_converter_source_payload_valid_token_count <= (rx_converter_converter_demux + 1'd1); - end - rx_cdc_cdc_graycounter0_q_binary <= rx_cdc_cdc_graycounter0_q_next_binary; - rx_cdc_cdc_graycounter0_q <= rx_cdc_cdc_graycounter0_q_next; - if (eth_rx_rst) begin - maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_valid <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_data <= 8'd0; - maccore_ethphy_liteethphygmiimiirx_gmii_rx_dv_d <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_converter_sink_valid <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_converter_sink_payload_data <= 4'd0; - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_data <= 8'd0; - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_valid_token_count <= 2'd0; - maccore_ethphy_liteethphygmiimiirx_converter_converter_demux <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_converter_reset <= 1'd0; - liteethmaccrc32checker_crc_reg <= 32'd4294967295; - liteethmaccrc32checker_syncfifo_level <= 3'd0; - liteethmaccrc32checker_syncfifo_produce <= 3'd0; - liteethmaccrc32checker_syncfifo_consume <= 3'd0; - crc32_checker_source_valid <= 1'd0; - crc32_checker_source_payload_data <= 8'd0; - crc32_checker_source_payload_last_be <= 1'd0; - crc32_checker_source_payload_error <= 1'd0; - rx_converter_converter_source_payload_data <= 40'd0; - rx_converter_converter_source_payload_valid_token_count <= 3'd0; - rx_converter_converter_demux <= 2'd0; - rx_converter_converter_strobe_all <= 1'd0; - rx_cdc_cdc_graycounter0_q <= 6'd0; - rx_cdc_cdc_graycounter0_q_binary <= 6'd0; - subfragments_liteethmacpreamblechecker_state <= 1'd0; - subfragments_liteethmaccrc32checker_state <= 2'd0; - end - xilinxmultiregimpl7_regs0 <= rx_cdc_cdc_graycounter1_q; - xilinxmultiregimpl7_regs1 <= xilinxmultiregimpl7_regs0; + main_maccore_ethphy_eth_counter <= (main_maccore_ethphy_eth_counter + 1'd1); + if (main_maccore_ethphy_i) begin + main_maccore_ethphy_toggle_i <= (~main_maccore_ethphy_toggle_i); + end + main_maccore_ethphy_pads_d_rx_dv <= gmii_rx_dv; + main_maccore_ethphy_pads_d_rx_data <= gmii_rx_data; + main_maccore_ethphy_gmii_rx_dv_d <= main_maccore_ethphy_pads_d_rx_dv; + main_maccore_ethphy_gmii_rx_source_valid <= main_maccore_ethphy_pads_d_rx_dv; + main_maccore_ethphy_gmii_rx_source_payload_data <= main_maccore_ethphy_pads_d_rx_data; + main_maccore_ethphy_mii_rx_reset <= (~main_maccore_ethphy_pads_d_rx_dv); + main_maccore_ethphy_mii_rx_converter_sink_valid <= 1'd1; + main_maccore_ethphy_mii_rx_converter_sink_payload_data <= main_maccore_ethphy_pads_d_rx_data; + if (main_maccore_ethphy_mii_rx_converter_source_ready) begin + main_maccore_ethphy_mii_rx_converter_strobe_all <= 1'd0; + end + if (main_maccore_ethphy_mii_rx_converter_load_part) begin + if (((main_maccore_ethphy_mii_rx_converter_demux == 1'd1) | main_maccore_ethphy_mii_rx_converter_sink_last)) begin + main_maccore_ethphy_mii_rx_converter_demux <= 1'd0; + main_maccore_ethphy_mii_rx_converter_strobe_all <= 1'd1; + end else begin + main_maccore_ethphy_mii_rx_converter_demux <= (main_maccore_ethphy_mii_rx_converter_demux + 1'd1); + end + end + if ((main_maccore_ethphy_mii_rx_converter_source_valid & main_maccore_ethphy_mii_rx_converter_source_ready)) begin + if ((main_maccore_ethphy_mii_rx_converter_sink_valid & main_maccore_ethphy_mii_rx_converter_sink_ready)) begin + main_maccore_ethphy_mii_rx_converter_source_first <= main_maccore_ethphy_mii_rx_converter_sink_first; + main_maccore_ethphy_mii_rx_converter_source_last <= main_maccore_ethphy_mii_rx_converter_sink_last; + end else begin + main_maccore_ethphy_mii_rx_converter_source_first <= 1'd0; + main_maccore_ethphy_mii_rx_converter_source_last <= 1'd0; + end + end else begin + if ((main_maccore_ethphy_mii_rx_converter_sink_valid & main_maccore_ethphy_mii_rx_converter_sink_ready)) begin + main_maccore_ethphy_mii_rx_converter_source_first <= (main_maccore_ethphy_mii_rx_converter_sink_first | main_maccore_ethphy_mii_rx_converter_source_first); + main_maccore_ethphy_mii_rx_converter_source_last <= (main_maccore_ethphy_mii_rx_converter_sink_last | main_maccore_ethphy_mii_rx_converter_source_last); + end + end + if (main_maccore_ethphy_mii_rx_converter_load_part) begin + case (main_maccore_ethphy_mii_rx_converter_demux) + 1'd0: begin + main_maccore_ethphy_mii_rx_converter_source_payload_data[3:0] <= main_maccore_ethphy_mii_rx_converter_sink_payload_data; + end + 1'd1: begin + main_maccore_ethphy_mii_rx_converter_source_payload_data[7:4] <= main_maccore_ethphy_mii_rx_converter_sink_payload_data; + end + endcase + end + if (main_maccore_ethphy_mii_rx_converter_load_part) begin + main_maccore_ethphy_mii_rx_converter_source_payload_valid_token_count <= (main_maccore_ethphy_mii_rx_converter_demux + 1'd1); + end + if (main_maccore_ethphy_mii_rx_reset) begin + main_maccore_ethphy_mii_rx_converter_source_payload_data <= 8'd0; + main_maccore_ethphy_mii_rx_converter_source_payload_valid_token_count <= 2'd0; + main_maccore_ethphy_mii_rx_converter_demux <= 1'd0; + main_maccore_ethphy_mii_rx_converter_strobe_all <= 1'd0; + end + builder_rxdatapath_liteethmacpreamblechecker_state <= builder_rxdatapath_liteethmacpreamblechecker_next_state; + if (main_pulsesynchronizer0_i) begin + main_pulsesynchronizer0_toggle_i <= (~main_pulsesynchronizer0_toggle_i); + end + if (main_liteethmaccrc32checker_crc_ce) begin + main_liteethmaccrc32checker_crc_reg <= main_liteethmaccrc32checker_crc_crc_next; + end + if (main_liteethmaccrc32checker_crc_reset) begin + main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + end + if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin + if ((main_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin + main_liteethmaccrc32checker_syncfifo_produce <= 1'd0; + end else begin + main_liteethmaccrc32checker_syncfifo_produce <= (main_liteethmaccrc32checker_syncfifo_produce + 1'd1); + end + end + if (main_liteethmaccrc32checker_syncfifo_do_read) begin + if ((main_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin + main_liteethmaccrc32checker_syncfifo_consume <= 1'd0; + end else begin + main_liteethmaccrc32checker_syncfifo_consume <= (main_liteethmaccrc32checker_syncfifo_consume + 1'd1); + end + end + if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin + if ((~main_liteethmaccrc32checker_syncfifo_do_read)) begin + main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level + 1'd1); + end + end else begin + if (main_liteethmaccrc32checker_syncfifo_do_read) begin + main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level - 1'd1); + end + end + if (main_liteethmaccrc32checker_fifo_reset) begin + main_liteethmaccrc32checker_syncfifo_level <= 3'd0; + main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + end + builder_rxdatapath_bufferizeendpoints_state <= builder_rxdatapath_bufferizeendpoints_next_state; + if (main_liteethmaccrc32checker_last_be_next_value_ce0) begin + main_liteethmaccrc32checker_last_be <= main_liteethmaccrc32checker_last_be_next_value0; + end + if (main_liteethmaccrc32checker_crc_error1_next_value_ce1) begin + main_liteethmaccrc32checker_crc_error1 <= main_liteethmaccrc32checker_crc_error1_next_value1; + end + if (((~main_bufferizeendpoints_pipe_valid_source_valid) | main_bufferizeendpoints_pipe_valid_source_ready)) begin + main_bufferizeendpoints_pipe_valid_source_valid <= main_bufferizeendpoints_pipe_valid_sink_valid; + main_bufferizeendpoints_pipe_valid_source_first <= main_bufferizeendpoints_pipe_valid_sink_first; + main_bufferizeendpoints_pipe_valid_source_last <= main_bufferizeendpoints_pipe_valid_sink_last; + main_bufferizeendpoints_pipe_valid_source_payload_data <= main_bufferizeendpoints_pipe_valid_sink_payload_data; + main_bufferizeendpoints_pipe_valid_source_payload_last_be <= main_bufferizeendpoints_pipe_valid_sink_payload_last_be; + main_bufferizeendpoints_pipe_valid_source_payload_error <= main_bufferizeendpoints_pipe_valid_sink_payload_error; + end + if (main_pulsesynchronizer1_i) begin + main_pulsesynchronizer1_toggle_i <= (~main_pulsesynchronizer1_toggle_i); + end + if (main_rx_converter_converter_source_ready) begin + main_rx_converter_converter_strobe_all <= 1'd0; + end + if (main_rx_converter_converter_load_part) begin + if (((main_rx_converter_converter_demux == 2'd3) | main_rx_converter_converter_sink_last)) begin + main_rx_converter_converter_demux <= 1'd0; + main_rx_converter_converter_strobe_all <= 1'd1; + end else begin + main_rx_converter_converter_demux <= (main_rx_converter_converter_demux + 1'd1); + end + end + if ((main_rx_converter_converter_source_valid & main_rx_converter_converter_source_ready)) begin + if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin + main_rx_converter_converter_source_first <= main_rx_converter_converter_sink_first; + main_rx_converter_converter_source_last <= main_rx_converter_converter_sink_last; + end else begin + main_rx_converter_converter_source_first <= 1'd0; + main_rx_converter_converter_source_last <= 1'd0; + end + end else begin + if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin + main_rx_converter_converter_source_first <= (main_rx_converter_converter_sink_first | main_rx_converter_converter_source_first); + main_rx_converter_converter_source_last <= (main_rx_converter_converter_sink_last | main_rx_converter_converter_source_last); + end + end + if (main_rx_converter_converter_load_part) begin + case (main_rx_converter_converter_demux) + 1'd0: begin + main_rx_converter_converter_source_payload_data[9:0] <= main_rx_converter_converter_sink_payload_data; + end + 1'd1: begin + main_rx_converter_converter_source_payload_data[19:10] <= main_rx_converter_converter_sink_payload_data; + end + 2'd2: begin + main_rx_converter_converter_source_payload_data[29:20] <= main_rx_converter_converter_sink_payload_data; + end + 2'd3: begin + main_rx_converter_converter_source_payload_data[39:30] <= main_rx_converter_converter_sink_payload_data; + end + endcase + end + if (main_rx_converter_converter_load_part) begin + main_rx_converter_converter_source_payload_valid_token_count <= (main_rx_converter_converter_demux + 1'd1); + end + main_rx_cdc_cdc_graycounter0_q_binary <= main_rx_cdc_cdc_graycounter0_q_next_binary; + main_rx_cdc_cdc_graycounter0_q <= main_rx_cdc_cdc_graycounter0_q_next; + if (eth_rx_rst) begin + main_maccore_ethphy_gmii_rx_source_valid <= 1'd0; + main_maccore_ethphy_gmii_rx_source_payload_data <= 8'd0; + main_maccore_ethphy_gmii_rx_dv_d <= 1'd0; + main_maccore_ethphy_mii_rx_converter_sink_valid <= 1'd0; + main_maccore_ethphy_mii_rx_converter_sink_payload_data <= 4'd0; + main_maccore_ethphy_mii_rx_converter_source_payload_data <= 8'd0; + main_maccore_ethphy_mii_rx_converter_source_payload_valid_token_count <= 2'd0; + main_maccore_ethphy_mii_rx_converter_demux <= 1'd0; + main_maccore_ethphy_mii_rx_converter_strobe_all <= 1'd0; + main_maccore_ethphy_mii_rx_reset <= 1'd0; + main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + main_liteethmaccrc32checker_syncfifo_level <= 3'd0; + main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + main_liteethmaccrc32checker_last_be <= 1'd0; + main_liteethmaccrc32checker_crc_error1 <= 1'd0; + main_bufferizeendpoints_pipe_valid_source_valid <= 1'd0; + main_bufferizeendpoints_pipe_valid_source_payload_data <= 8'd0; + main_bufferizeendpoints_pipe_valid_source_payload_last_be <= 1'd0; + main_bufferizeendpoints_pipe_valid_source_payload_error <= 1'd0; + main_rx_converter_converter_source_payload_data <= 40'd0; + main_rx_converter_converter_source_payload_valid_token_count <= 3'd0; + main_rx_converter_converter_demux <= 2'd0; + main_rx_converter_converter_strobe_all <= 1'd0; + main_rx_cdc_cdc_graycounter0_q <= 6'd0; + main_rx_cdc_cdc_graycounter0_q_binary <= 6'd0; + builder_rxdatapath_liteethmacpreamblechecker_state <= 1'd0; + builder_rxdatapath_bufferizeendpoints_state <= 2'd0; + end + builder_xilinxmultiregimpl70 <= main_rx_cdc_cdc_graycounter1_q; + builder_xilinxmultiregimpl71 <= builder_xilinxmultiregimpl70; end always @(posedge eth_tx_clk) begin - if ((maccore_ethphy_mode0 == 1'd1)) begin - gmii_eth_tx_en <= maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_en; - gmii_eth_tx_data <= maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_data; - end else begin - gmii_eth_tx_en <= maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_en; - gmii_eth_tx_data <= maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_data; - end - maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_er <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_en <= maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_valid; - maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_data <= maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_data; - maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_ready <= 1'd1; - maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_er <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_en <= maccore_ethphy_liteethphygmiimiitx_converter_source_valid; - maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_data <= maccore_ethphy_liteethphygmiimiitx_converter_source_payload_data; - if ((maccore_ethphy_liteethphygmiimiitx_converter_converter_source_valid & maccore_ethphy_liteethphygmiimiitx_converter_converter_source_ready)) begin - if (maccore_ethphy_liteethphygmiimiitx_converter_converter_last) begin - maccore_ethphy_liteethphygmiimiitx_converter_converter_mux <= 1'd0; - end else begin - maccore_ethphy_liteethphygmiimiitx_converter_converter_mux <= (maccore_ethphy_liteethphygmiimiitx_converter_converter_mux + 1'd1); - end - end - subfragments_liteethmacgap_state <= subfragments_liteethmacgap_next_state; - if (tx_gap_inserter_counter_liteethmacgap_next_value_ce) begin - tx_gap_inserter_counter <= tx_gap_inserter_counter_liteethmacgap_next_value; - end - subfragments_liteethmacpreambleinserter_state <= subfragments_liteethmacpreambleinserter_next_state; - if (preamble_inserter_count_liteethmacpreambleinserter_next_value_ce) begin - preamble_inserter_count <= preamble_inserter_count_liteethmacpreambleinserter_next_value; - end - if (liteethmaccrc32inserter_is_ongoing0) begin - liteethmaccrc32inserter_cnt <= 2'd3; - end else begin - if ((liteethmaccrc32inserter_is_ongoing1 & (~liteethmaccrc32inserter_cnt_done))) begin - liteethmaccrc32inserter_cnt <= (liteethmaccrc32inserter_cnt - liteethmaccrc32inserter_source_ready); - end - end - if (liteethmaccrc32inserter_ce) begin - liteethmaccrc32inserter_reg <= liteethmaccrc32inserter_next; - end - if (liteethmaccrc32inserter_reset) begin - liteethmaccrc32inserter_reg <= 32'd4294967295; - end - subfragments_liteethmaccrc32inserter_state <= subfragments_liteethmaccrc32inserter_next_state; - if (((~crc32_inserter_source_valid) | crc32_inserter_source_ready)) begin - crc32_inserter_source_valid <= crc32_inserter_sink_valid; - crc32_inserter_source_first <= crc32_inserter_sink_first; - crc32_inserter_source_last <= crc32_inserter_sink_last; - crc32_inserter_source_payload_data <= crc32_inserter_sink_payload_data; - crc32_inserter_source_payload_last_be <= crc32_inserter_sink_payload_last_be; - crc32_inserter_source_payload_error <= crc32_inserter_sink_payload_error; - end - subfragments_liteethmacpaddinginserter_state <= subfragments_liteethmacpaddinginserter_next_state; - if (padding_inserter_counter_liteethmacpaddinginserter_next_value_ce) begin - padding_inserter_counter <= padding_inserter_counter_liteethmacpaddinginserter_next_value; - end - subfragments_liteethmactxlastbe_state <= subfragments_liteethmactxlastbe_next_state; - if ((tx_converter_converter_source_valid & tx_converter_converter_source_ready)) begin - if (tx_converter_converter_last) begin - tx_converter_converter_mux <= 1'd0; - end else begin - tx_converter_converter_mux <= (tx_converter_converter_mux + 1'd1); - end - end - tx_cdc_cdc_graycounter1_q_binary <= tx_cdc_cdc_graycounter1_q_next_binary; - tx_cdc_cdc_graycounter1_q <= tx_cdc_cdc_graycounter1_q_next; - if (eth_tx_rst) begin - maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_ready <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_converter_converter_mux <= 1'd0; - liteethmaccrc32inserter_reg <= 32'd4294967295; - liteethmaccrc32inserter_cnt <= 2'd3; - crc32_inserter_source_valid <= 1'd0; - crc32_inserter_source_payload_data <= 8'd0; - crc32_inserter_source_payload_last_be <= 1'd0; - crc32_inserter_source_payload_error <= 1'd0; - padding_inserter_counter <= 16'd0; - tx_converter_converter_mux <= 2'd0; - tx_cdc_cdc_graycounter1_q <= 6'd0; - tx_cdc_cdc_graycounter1_q_binary <= 6'd0; - subfragments_liteethmacgap_state <= 1'd0; - subfragments_liteethmacpreambleinserter_state <= 2'd0; - subfragments_liteethmaccrc32inserter_state <= 2'd0; - subfragments_liteethmacpaddinginserter_state <= 1'd0; - subfragments_liteethmactxlastbe_state <= 1'd0; - end - xilinxmultiregimpl4_regs0 <= tx_cdc_cdc_graycounter0_q; - xilinxmultiregimpl4_regs1 <= xilinxmultiregimpl4_regs0; + if ((main_maccore_ethphy_mode0 == 1'd1)) begin + gmii_tx_en <= main_maccore_ethphy_mii_tx_pads_tx_en; + gmii_tx_data <= main_maccore_ethphy_mii_tx_pads_tx_data; + end else begin + gmii_tx_en <= main_maccore_ethphy_gmii_tx_pads_tx_en; + gmii_tx_data <= main_maccore_ethphy_gmii_tx_pads_tx_data; + end + main_maccore_ethphy_gmii_tx_pads_tx_er <= 1'd0; + main_maccore_ethphy_gmii_tx_pads_tx_en <= main_maccore_ethphy_gmii_tx_sink_valid; + main_maccore_ethphy_gmii_tx_pads_tx_data <= main_maccore_ethphy_gmii_tx_sink_payload_data; + main_maccore_ethphy_gmii_tx_sink_ready <= 1'd1; + main_maccore_ethphy_mii_tx_pads_tx_er <= 1'd0; + main_maccore_ethphy_mii_tx_pads_tx_en <= main_maccore_ethphy_mii_tx_source_source_valid; + main_maccore_ethphy_mii_tx_pads_tx_data <= main_maccore_ethphy_mii_tx_source_source_payload_data; + if ((main_maccore_ethphy_mii_tx_converter_source_valid & main_maccore_ethphy_mii_tx_converter_source_ready)) begin + if (main_maccore_ethphy_mii_tx_converter_last) begin + main_maccore_ethphy_mii_tx_converter_mux <= 1'd0; + end else begin + main_maccore_ethphy_mii_tx_converter_mux <= (main_maccore_ethphy_mii_tx_converter_mux + 1'd1); + end + end + main_tx_cdc_cdc_graycounter1_q_binary <= main_tx_cdc_cdc_graycounter1_q_next_binary; + main_tx_cdc_cdc_graycounter1_q <= main_tx_cdc_cdc_graycounter1_q_next; + if ((main_tx_converter_converter_source_valid & main_tx_converter_converter_source_ready)) begin + if (main_tx_converter_converter_last) begin + main_tx_converter_converter_mux <= 1'd0; + end else begin + main_tx_converter_converter_mux <= (main_tx_converter_converter_mux + 1'd1); + end + end + builder_txdatapath_liteethmactxlastbe_state <= builder_txdatapath_liteethmactxlastbe_next_state; + builder_txdatapath_liteethmacpaddinginserter_state <= builder_txdatapath_liteethmacpaddinginserter_next_state; + if (main_tx_padding_counter_clockdomainsrenamer0_next_value_ce) begin + main_tx_padding_counter <= main_tx_padding_counter_clockdomainsrenamer0_next_value; + end + if (main_tx_crc_is_ongoing0) begin + main_tx_crc_cnt <= 2'd3; + end else begin + if ((main_tx_crc_is_ongoing1 & (~main_tx_crc_cnt_done))) begin + main_tx_crc_cnt <= (main_tx_crc_cnt - main_tx_crc_source_ready); + end + end + if (main_tx_crc_ce) begin + main_tx_crc_reg <= main_tx_crc_crc_next; + end + if (main_tx_crc_reset) begin + main_tx_crc_reg <= 32'd4294967295; + end + builder_txdatapath_bufferizeendpoints_state <= builder_txdatapath_bufferizeendpoints_next_state; + if (main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0) begin + main_tx_crc_crc_packet <= main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0; + end + if (main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1) begin + main_tx_crc_last_be <= main_tx_crc_last_be_clockdomainsrenamer1_next_value1; + end + if (((~main_tx_crc_pipe_valid_source_valid) | main_tx_crc_pipe_valid_source_ready)) begin + main_tx_crc_pipe_valid_source_valid <= main_tx_crc_pipe_valid_sink_valid; + main_tx_crc_pipe_valid_source_first <= main_tx_crc_pipe_valid_sink_first; + main_tx_crc_pipe_valid_source_last <= main_tx_crc_pipe_valid_sink_last; + main_tx_crc_pipe_valid_source_payload_data <= main_tx_crc_pipe_valid_sink_payload_data; + main_tx_crc_pipe_valid_source_payload_last_be <= main_tx_crc_pipe_valid_sink_payload_last_be; + main_tx_crc_pipe_valid_source_payload_error <= main_tx_crc_pipe_valid_sink_payload_error; + end + builder_txdatapath_liteethmacpreambleinserter_state <= builder_txdatapath_liteethmacpreambleinserter_next_state; + if (main_tx_preamble_count_clockdomainsrenamer2_next_value_ce) begin + main_tx_preamble_count <= main_tx_preamble_count_clockdomainsrenamer2_next_value; + end + builder_txdatapath_liteethmacgap_state <= builder_txdatapath_liteethmacgap_next_state; + if (main_tx_gap_counter_clockdomainsrenamer3_next_value_ce) begin + main_tx_gap_counter <= main_tx_gap_counter_clockdomainsrenamer3_next_value; + end + if (eth_tx_rst) begin + main_maccore_ethphy_gmii_tx_sink_ready <= 1'd0; + main_maccore_ethphy_mii_tx_converter_mux <= 1'd0; + main_tx_cdc_cdc_graycounter1_q <= 6'd0; + main_tx_cdc_cdc_graycounter1_q_binary <= 6'd0; + main_tx_converter_converter_mux <= 2'd0; + main_tx_padding_counter <= 16'd0; + main_tx_crc_crc_packet <= 32'd0; + main_tx_crc_last_be <= 1'd0; + main_tx_crc_reg <= 32'd4294967295; + main_tx_crc_cnt <= 2'd3; + main_tx_crc_pipe_valid_source_valid <= 1'd0; + main_tx_crc_pipe_valid_source_payload_data <= 8'd0; + main_tx_crc_pipe_valid_source_payload_last_be <= 1'd0; + main_tx_crc_pipe_valid_source_payload_error <= 1'd0; + builder_txdatapath_liteethmactxlastbe_state <= 1'd0; + builder_txdatapath_liteethmacpaddinginserter_state <= 1'd0; + builder_txdatapath_bufferizeendpoints_state <= 2'd0; + builder_txdatapath_liteethmacpreambleinserter_state <= 2'd0; + builder_txdatapath_liteethmacgap_state <= 1'd0; + end + builder_xilinxmultiregimpl20 <= main_tx_cdc_cdc_graycounter0_q; + builder_xilinxmultiregimpl21 <= builder_xilinxmultiregimpl20; end always @(posedge por_clk) begin - maccore_int_rst <= sys_reset; + main_maccore_int_rst <= sys_reset; end always @(posedge sys_clk) begin - if ((maccore_maccore_bus_errors != 32'd4294967295)) begin - if (maccore_maccore_bus_error) begin - maccore_maccore_bus_errors <= (maccore_maccore_bus_errors + 1'd1); - end - end - if (maccore_ethphy_update_mode) begin - maccore_ethphy_mode0 <= maccore_ethphy_mode1; - end - if (maccore_ethphy_sys_counter_reset) begin - maccore_ethphy_sys_counter <= 1'd0; - end else begin - if (maccore_ethphy_sys_counter_ce) begin - maccore_ethphy_sys_counter <= (maccore_ethphy_sys_counter + 1'd1); - end - end - maccore_ethphy_toggle_o_r <= maccore_ethphy_toggle_o; - subfragments_state <= subfragments_next_state; - if (maccore_ethphy_counter_ce) begin - maccore_ethphy_counter <= (maccore_ethphy_counter + 1'd1); - end - if (ps_preamble_error_o) begin - preamble_errors_status <= (preamble_errors_status + 1'd1); - end - if (ps_crc_error_o) begin - crc_errors_status <= (crc_errors_status + 1'd1); - end - ps_preamble_error_toggle_o_r <= ps_preamble_error_toggle_o; - ps_crc_error_toggle_o_r <= ps_crc_error_toggle_o; - tx_cdc_cdc_graycounter0_q_binary <= tx_cdc_cdc_graycounter0_q_next_binary; - tx_cdc_cdc_graycounter0_q <= tx_cdc_cdc_graycounter0_q_next; - rx_cdc_cdc_graycounter1_q_binary <= rx_cdc_cdc_graycounter1_q_next_binary; - rx_cdc_cdc_graycounter1_q <= rx_cdc_cdc_graycounter1_q_next; - if (writer_slot_ce) begin - writer_slot <= (writer_slot + 1'd1); - end - if (((writer_stat_fifo_syncfifo_we & writer_stat_fifo_syncfifo_writable) & (~writer_stat_fifo_replace))) begin - writer_stat_fifo_produce <= (writer_stat_fifo_produce + 1'd1); - end - if (writer_stat_fifo_do_read) begin - writer_stat_fifo_consume <= (writer_stat_fifo_consume + 1'd1); - end - if (((writer_stat_fifo_syncfifo_we & writer_stat_fifo_syncfifo_writable) & (~writer_stat_fifo_replace))) begin - if ((~writer_stat_fifo_do_read)) begin - writer_stat_fifo_level <= (writer_stat_fifo_level + 1'd1); - end - end else begin - if (writer_stat_fifo_do_read) begin - writer_stat_fifo_level <= (writer_stat_fifo_level - 1'd1); - end - end - subfragments_liteethmacsramwriter_state <= subfragments_liteethmacsramwriter_next_state; - if (writer_counter_t_next_value_ce) begin - writer_counter <= writer_counter_t_next_value; - end - if (writer_errors_status_f_next_value_ce) begin - writer_errors_status <= writer_errors_status_f_next_value; - end - if (reader_eventsourcepulse_clear) begin - reader_eventsourcepulse_pending <= 1'd0; - end - if (reader_eventsourcepulse_trigger) begin - reader_eventsourcepulse_pending <= 1'd1; - end - if (((reader_cmd_fifo_syncfifo_we & reader_cmd_fifo_syncfifo_writable) & (~reader_cmd_fifo_replace))) begin - reader_cmd_fifo_produce <= (reader_cmd_fifo_produce + 1'd1); - end - if (reader_cmd_fifo_do_read) begin - reader_cmd_fifo_consume <= (reader_cmd_fifo_consume + 1'd1); - end - if (((reader_cmd_fifo_syncfifo_we & reader_cmd_fifo_syncfifo_writable) & (~reader_cmd_fifo_replace))) begin - if ((~reader_cmd_fifo_do_read)) begin - reader_cmd_fifo_level <= (reader_cmd_fifo_level + 1'd1); - end - end else begin - if (reader_cmd_fifo_do_read) begin - reader_cmd_fifo_level <= (reader_cmd_fifo_level - 1'd1); - end - end - subfragments_liteethmacsramreader_state <= subfragments_liteethmacsramreader_next_state; - if (reader_counter_next_value_ce) begin - reader_counter <= reader_counter_next_value; - end - sram0_bus_ack0 <= 1'd0; - if (((sram0_bus_cyc0 & sram0_bus_stb0) & (~sram0_bus_ack0))) begin - sram0_bus_ack0 <= 1'd1; - end - sram1_bus_ack0 <= 1'd0; - if (((sram1_bus_cyc0 & sram1_bus_stb0) & (~sram1_bus_ack0))) begin - sram1_bus_ack0 <= 1'd1; - end - sram0_bus_ack1 <= 1'd0; - if (((sram0_bus_cyc1 & sram0_bus_stb1) & (~sram0_bus_ack1))) begin - sram0_bus_ack1 <= 1'd1; - end - sram1_bus_ack1 <= 1'd0; - if (((sram1_bus_cyc1 & sram1_bus_stb1) & (~sram1_bus_ack1))) begin - sram1_bus_ack1 <= 1'd1; - end - slave_sel_r <= slave_sel; - maccore_state <= maccore_next_state; - maccore_slave_sel_r <= maccore_slave_sel; - if (maccore_wait) begin - if ((~maccore_done)) begin - maccore_count <= (maccore_count - 1'd1); - end - end else begin - maccore_count <= 20'd1000000; - end - maccore_interface0_bank_bus_dat_r <= 1'd0; - if (maccore_csrbank0_sel) begin - case (maccore_interface0_bank_bus_adr[8:0]) - 1'd0: begin - maccore_interface0_bank_bus_dat_r <= maccore_csrbank0_reset0_w; - end - 1'd1: begin - maccore_interface0_bank_bus_dat_r <= maccore_csrbank0_scratch0_w; - end - 2'd2: begin - maccore_interface0_bank_bus_dat_r <= maccore_csrbank0_bus_errors_w; - end - endcase - end - if (maccore_csrbank0_reset0_re) begin - maccore_maccore_reset_storage[1:0] <= maccore_csrbank0_reset0_r; - end - maccore_maccore_reset_re <= maccore_csrbank0_reset0_re; - if (maccore_csrbank0_scratch0_re) begin - maccore_maccore_scratch_storage[31:0] <= maccore_csrbank0_scratch0_r; - end - maccore_maccore_scratch_re <= maccore_csrbank0_scratch0_re; - maccore_maccore_bus_errors_re <= maccore_csrbank0_bus_errors_re; - maccore_interface1_bank_bus_dat_r <= 1'd0; - if (maccore_csrbank1_sel) begin - case (maccore_interface1_bank_bus_adr[8:0]) - 1'd0: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_writer_slot_w; - end - 1'd1: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_writer_length_w; - end - 2'd2: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_writer_errors_w; - end - 2'd3: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_writer_ev_status_w; - end - 3'd4: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_writer_ev_pending_w; - end - 3'd5: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_writer_ev_enable0_w; - end - 3'd6: begin - maccore_interface1_bank_bus_dat_r <= reader_start_start_w; - end - 3'd7: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_ready_w; - end - 4'd8: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_level_w; - end - 4'd9: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_slot0_w; - end - 4'd10: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_length0_w; - end - 4'd11: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_ev_status_w; - end - 4'd12: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_ev_pending_w; - end - 4'd13: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_ev_enable0_w; - end - 4'd14: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_preamble_crc_w; - end - 4'd15: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_preamble_errors_w; - end - 5'd16: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_crc_errors_w; - end - endcase - end - writer_slot_re <= maccore_csrbank1_sram_writer_slot_re; - writer_length_re <= maccore_csrbank1_sram_writer_length_re; - writer_errors_re <= maccore_csrbank1_sram_writer_errors_re; - writer_status_re <= maccore_csrbank1_sram_writer_ev_status_re; - if (maccore_csrbank1_sram_writer_ev_pending_re) begin - writer_pending_r <= maccore_csrbank1_sram_writer_ev_pending_r; - end - writer_pending_re <= maccore_csrbank1_sram_writer_ev_pending_re; - if (maccore_csrbank1_sram_writer_ev_enable0_re) begin - writer_enable_storage <= maccore_csrbank1_sram_writer_ev_enable0_r; - end - writer_enable_re <= maccore_csrbank1_sram_writer_ev_enable0_re; - reader_ready_re <= maccore_csrbank1_sram_reader_ready_re; - reader_level_re <= maccore_csrbank1_sram_reader_level_re; - if (maccore_csrbank1_sram_reader_slot0_re) begin - reader_slot_storage <= maccore_csrbank1_sram_reader_slot0_r; - end - reader_slot_re <= maccore_csrbank1_sram_reader_slot0_re; - if (maccore_csrbank1_sram_reader_length0_re) begin - reader_length_storage[10:0] <= maccore_csrbank1_sram_reader_length0_r; - end - reader_length_re <= maccore_csrbank1_sram_reader_length0_re; - reader_status_re <= maccore_csrbank1_sram_reader_ev_status_re; - if (maccore_csrbank1_sram_reader_ev_pending_re) begin - reader_pending_r <= maccore_csrbank1_sram_reader_ev_pending_r; - end - reader_pending_re <= maccore_csrbank1_sram_reader_ev_pending_re; - if (maccore_csrbank1_sram_reader_ev_enable0_re) begin - reader_enable_storage <= maccore_csrbank1_sram_reader_ev_enable0_r; - end - reader_enable_re <= maccore_csrbank1_sram_reader_ev_enable0_re; - preamble_crc_re <= maccore_csrbank1_preamble_crc_re; - preamble_errors_re <= maccore_csrbank1_preamble_errors_re; - crc_errors_re <= maccore_csrbank1_crc_errors_re; - maccore_interface2_bank_bus_dat_r <= 1'd0; - if (maccore_csrbank2_sel) begin - case (maccore_interface2_bank_bus_adr[8:0]) - 1'd0: begin - maccore_interface2_bank_bus_dat_r <= maccore_csrbank2_mode_detection_mode_w; - end - 1'd1: begin - maccore_interface2_bank_bus_dat_r <= maccore_csrbank2_crg_reset0_w; - end - 2'd2: begin - maccore_interface2_bank_bus_dat_r <= maccore_csrbank2_mdio_w0_w; - end - 2'd3: begin - maccore_interface2_bank_bus_dat_r <= maccore_csrbank2_mdio_r_w; - end - endcase - end - maccore_ethphy_mode_re <= maccore_csrbank2_mode_detection_mode_re; - if (maccore_csrbank2_crg_reset0_re) begin - maccore_ethphy_reset_storage <= maccore_csrbank2_crg_reset0_r; - end - maccore_ethphy_reset_re <= maccore_csrbank2_crg_reset0_re; - if (maccore_csrbank2_mdio_w0_re) begin - maccore_ethphy__w_storage[2:0] <= maccore_csrbank2_mdio_w0_r; - end - maccore_ethphy__w_re <= maccore_csrbank2_mdio_w0_re; - maccore_ethphy__r_re <= maccore_csrbank2_mdio_r_re; - if (sys_rst) begin - maccore_maccore_reset_storage <= 2'd0; - maccore_maccore_reset_re <= 1'd0; - maccore_maccore_scratch_storage <= 32'd305419896; - maccore_maccore_scratch_re <= 1'd0; - maccore_maccore_bus_errors_re <= 1'd0; - maccore_maccore_bus_errors <= 32'd0; - maccore_ethphy_mode0 <= 1'd0; - maccore_ethphy_mode_re <= 1'd0; - maccore_ethphy_reset_storage <= 1'd0; - maccore_ethphy_reset_re <= 1'd0; - maccore_ethphy_counter <= 9'd0; - maccore_ethphy__w_storage <= 3'd0; - maccore_ethphy__w_re <= 1'd0; - maccore_ethphy__r_re <= 1'd0; - preamble_crc_re <= 1'd0; - preamble_errors_status <= 32'd0; - preamble_errors_re <= 1'd0; - crc_errors_status <= 32'd0; - crc_errors_re <= 1'd0; - tx_cdc_cdc_graycounter0_q <= 6'd0; - tx_cdc_cdc_graycounter0_q_binary <= 6'd0; - rx_cdc_cdc_graycounter1_q <= 6'd0; - rx_cdc_cdc_graycounter1_q_binary <= 6'd0; - writer_slot_re <= 1'd0; - writer_length_re <= 1'd0; - writer_errors_status <= 32'd0; - writer_errors_re <= 1'd0; - writer_status_re <= 1'd0; - writer_pending_re <= 1'd0; - writer_pending_r <= 1'd0; - writer_enable_storage <= 1'd0; - writer_enable_re <= 1'd0; - writer_counter <= 32'd0; - writer_slot <= 1'd0; - writer_stat_fifo_level <= 2'd0; - writer_stat_fifo_produce <= 1'd0; - writer_stat_fifo_consume <= 1'd0; - reader_ready_re <= 1'd0; - reader_level_re <= 1'd0; - reader_slot_re <= 1'd0; - reader_length_re <= 1'd0; - reader_eventsourcepulse_pending <= 1'd0; - reader_status_re <= 1'd0; - reader_pending_re <= 1'd0; - reader_pending_r <= 1'd0; - reader_enable_storage <= 1'd0; - reader_enable_re <= 1'd0; - reader_cmd_fifo_level <= 2'd0; - reader_cmd_fifo_produce <= 1'd0; - reader_cmd_fifo_consume <= 1'd0; - reader_counter <= 11'd0; - sram0_bus_ack0 <= 1'd0; - sram1_bus_ack0 <= 1'd0; - sram0_bus_ack1 <= 1'd0; - sram1_bus_ack1 <= 1'd0; - slave_sel_r <= 4'd0; - subfragments_state <= 2'd0; - subfragments_liteethmacsramwriter_state <= 3'd0; - subfragments_liteethmacsramreader_state <= 2'd0; - maccore_slave_sel_r <= 2'd0; - maccore_count <= 20'd1000000; - maccore_state <= 1'd0; - end - xilinxmultiregimpl0_regs0 <= maccore_ethphy_toggle_i; - xilinxmultiregimpl0_regs1 <= xilinxmultiregimpl0_regs0; - xilinxmultiregimpl1_regs0 <= maccore_ethphy_data_r; - xilinxmultiregimpl1_regs1 <= xilinxmultiregimpl1_regs0; - xilinxmultiregimpl2_regs0 <= ps_preamble_error_toggle_i; - xilinxmultiregimpl2_regs1 <= xilinxmultiregimpl2_regs0; - xilinxmultiregimpl3_regs0 <= ps_crc_error_toggle_i; - xilinxmultiregimpl3_regs1 <= xilinxmultiregimpl3_regs0; - xilinxmultiregimpl5_regs0 <= tx_cdc_cdc_graycounter1_q; - xilinxmultiregimpl5_regs1 <= xilinxmultiregimpl5_regs0; - xilinxmultiregimpl6_regs0 <= rx_cdc_cdc_graycounter0_q; - xilinxmultiregimpl6_regs1 <= xilinxmultiregimpl6_regs0; + builder_slave_sel_r <= builder_slave_sel; + if (builder_wait) begin + if ((~builder_done)) begin + builder_count <= (builder_count - 1'd1); + end + end else begin + builder_count <= 20'd1000000; + end + if ((main_maccore_maccore_bus_errors != 32'd4294967295)) begin + if (main_maccore_maccore_bus_error) begin + main_maccore_maccore_bus_errors <= (main_maccore_maccore_bus_errors + 1'd1); + end + end + if (main_maccore_ethphy_update_mode) begin + main_maccore_ethphy_mode0 <= main_maccore_ethphy_mode1; + end + if (main_maccore_ethphy_sys_counter_reset) begin + main_maccore_ethphy_sys_counter <= 1'd0; + end else begin + if (main_maccore_ethphy_sys_counter_ce) begin + main_maccore_ethphy_sys_counter <= (main_maccore_ethphy_sys_counter + 1'd1); + end + end + main_maccore_ethphy_toggle_o_r <= main_maccore_ethphy_toggle_o; + builder_liteethphygmiimii_state <= builder_liteethphygmiimii_next_state; + if (main_maccore_ethphy_counter_ce) begin + main_maccore_ethphy_counter <= (main_maccore_ethphy_counter + 1'd1); + end + main_tx_cdc_cdc_graycounter0_q_binary <= main_tx_cdc_cdc_graycounter0_q_next_binary; + main_tx_cdc_cdc_graycounter0_q <= main_tx_cdc_cdc_graycounter0_q_next; + if (main_pulsesynchronizer0_o) begin + main_preamble_errors_status <= (main_preamble_errors_status + 1'd1); + end + if (main_pulsesynchronizer1_o) begin + main_crc_errors_status <= (main_crc_errors_status + 1'd1); + end + main_pulsesynchronizer0_toggle_o_r <= main_pulsesynchronizer0_toggle_o; + main_pulsesynchronizer1_toggle_o_r <= main_pulsesynchronizer1_toggle_o; + main_rx_cdc_cdc_graycounter1_q_binary <= main_rx_cdc_cdc_graycounter1_q_next_binary; + main_rx_cdc_cdc_graycounter1_q <= main_rx_cdc_cdc_graycounter1_q_next; + if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin + main_sram57_produce <= (main_sram57_produce + 1'd1); + end + if (main_sram63_do_read) begin + main_sram58_consume <= (main_sram58_consume + 1'd1); + end + if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin + if ((~main_sram63_do_read)) begin + main_sram55_level <= (main_sram55_level + 1'd1); + end + end else begin + if (main_sram63_do_read) begin + main_sram55_level <= (main_sram55_level - 1'd1); + end + end + builder_liteethmacsramwriter_state <= builder_liteethmacsramwriter_next_state; + if (main_sram35_length_liteethmacsramwriter_t_next_value_ce) begin + main_sram35_length <= main_sram35_length_liteethmacsramwriter_t_next_value; + end + if (main_sram13_status_liteethmacsramwriter_f_next_value_ce) begin + main_sram13_status <= main_sram13_status_liteethmacsramwriter_f_next_value; + end + if (main_slot_liteethmacsramwriter_next_value_ce) begin + main_slot <= main_slot_liteethmacsramwriter_next_value; + end + if (main_sram108_clear) begin + main_sram106_pending <= 1'd0; + end + if (main_sram107_trigger) begin + main_sram106_pending <= 1'd1; + end + if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin + main_sram143_produce <= (main_sram143_produce + 1'd1); + end + if (main_sram149_do_read) begin + main_sram144_consume <= (main_sram144_consume + 1'd1); + end + if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin + if ((~main_sram149_do_read)) begin + main_sram141_level <= (main_sram141_level + 1'd1); + end + end else begin + if (main_sram149_do_read) begin + main_sram141_level <= (main_sram141_level - 1'd1); + end + end + builder_liteethmacsramreader_state <= builder_liteethmacsramreader_next_state; + if (main_sram122_length_liteethmacsramreader_next_value_ce) begin + main_sram122_length <= main_sram122_length_liteethmacsramreader_next_value; + end + main_interface0_ack <= 1'd0; + if (((main_interface0_cyc & main_interface0_stb) & ((~main_interface0_ack) | main_sram0_adr_burst))) begin + main_interface0_ack <= 1'd1; + end + main_interface1_ack <= 1'd0; + if (((main_interface1_cyc & main_interface1_stb) & ((~main_interface1_ack) | main_sram1_adr_burst))) begin + main_interface1_ack <= 1'd1; + end + main_interface2_ack <= 1'd0; + if (((main_interface2_cyc & main_interface2_stb) & ((~main_interface2_ack) | main_sram2_adr_burst))) begin + main_interface2_ack <= 1'd1; + end + main_interface3_ack <= 1'd0; + if (((main_interface3_cyc & main_interface3_stb) & ((~main_interface3_ack) | main_sram3_adr_burst))) begin + main_interface3_ack <= 1'd1; + end + main_slave_sel_r <= main_slave_sel; + builder_wishbone2csr_state <= builder_wishbone2csr_next_state; + builder_interface0_bank_bus_dat_r <= 1'd0; + if (builder_csrbank0_sel) begin + case (builder_interface0_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_reset0_w; + end + 1'd1: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_scratch0_w; + end + 2'd2: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_bus_errors_w; + end + endcase + end + if (builder_csrbank0_reset0_re) begin + main_maccore_maccore_reset_storage[1:0] <= builder_csrbank0_reset0_r; + end + main_maccore_maccore_reset_re <= builder_csrbank0_reset0_re; + if (builder_csrbank0_scratch0_re) begin + main_maccore_maccore_scratch_storage[31:0] <= builder_csrbank0_scratch0_r; + end + main_maccore_maccore_scratch_re <= builder_csrbank0_scratch0_re; + main_maccore_maccore_bus_errors_re <= builder_csrbank0_bus_errors_re; + builder_interface1_bank_bus_dat_r <= 1'd0; + if (builder_csrbank1_sel) begin + case (builder_interface1_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_slot_w; + end + 1'd1: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_length_w; + end + 2'd2: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_errors_w; + end + 2'd3: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_status_w; + end + 3'd4: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_pending_w; + end + 3'd5: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_enable0_w; + end + 3'd6: begin + builder_interface1_bank_bus_dat_r <= main_start_w; + end + 3'd7: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ready_w; + end + 4'd8: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_level_w; + end + 4'd9: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_slot0_w; + end + 4'd10: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_length0_w; + end + 4'd11: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_status_w; + end + 4'd12: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_pending_w; + end + 4'd13: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_enable0_w; + end + 4'd14: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_crc_w; + end + 4'd15: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_preamble_errors_w; + end + 5'd16: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_crc_errors_w; + end + endcase + end + main_sram9_re <= builder_csrbank1_sram_writer_slot_re; + main_sram12_re <= builder_csrbank1_sram_writer_length_re; + main_sram15_re <= builder_csrbank1_sram_writer_errors_re; + main_sram24_re <= builder_csrbank1_sram_writer_ev_status_re; + if (builder_csrbank1_sram_writer_ev_pending_re) begin + main_sram29_r <= builder_csrbank1_sram_writer_ev_pending_r; + end + main_sram28_re <= builder_csrbank1_sram_writer_ev_pending_re; + if (builder_csrbank1_sram_writer_ev_enable0_re) begin + main_sram31_storage <= builder_csrbank1_sram_writer_ev_enable0_r; + end + main_sram32_re <= builder_csrbank1_sram_writer_ev_enable0_re; + main_sram96_re <= builder_csrbank1_sram_reader_ready_re; + main_sram99_re <= builder_csrbank1_sram_reader_level_re; + if (builder_csrbank1_sram_reader_slot0_re) begin + main_sram100_storage <= builder_csrbank1_sram_reader_slot0_r; + end + main_sram101_re <= builder_csrbank1_sram_reader_slot0_re; + if (builder_csrbank1_sram_reader_length0_re) begin + main_sram102_storage[10:0] <= builder_csrbank1_sram_reader_length0_r; + end + main_sram103_re <= builder_csrbank1_sram_reader_length0_re; + main_sram112_re <= builder_csrbank1_sram_reader_ev_status_re; + if (builder_csrbank1_sram_reader_ev_pending_re) begin + main_sram117_r <= builder_csrbank1_sram_reader_ev_pending_r; + end + main_sram116_re <= builder_csrbank1_sram_reader_ev_pending_re; + if (builder_csrbank1_sram_reader_ev_enable0_re) begin + main_sram119_storage <= builder_csrbank1_sram_reader_ev_enable0_r; + end + main_sram120_re <= builder_csrbank1_sram_reader_ev_enable0_re; + main_re <= builder_csrbank1_preamble_crc_re; + main_preamble_errors_re <= builder_csrbank1_rx_datapath_preamble_errors_re; + main_crc_errors_re <= builder_csrbank1_rx_datapath_crc_errors_re; + builder_interface2_bank_bus_dat_r <= 1'd0; + if (builder_csrbank2_sel) begin + case (builder_interface2_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_mode_detection_mode_w; + end + 1'd1: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_crg_reset0_w; + end + 2'd2: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_w0_w; + end + 2'd3: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_r_w; + end + endcase + end + main_maccore_ethphy_mode_re <= builder_csrbank2_mode_detection_mode_re; + if (builder_csrbank2_crg_reset0_re) begin + main_maccore_ethphy_reset_storage <= builder_csrbank2_crg_reset0_r; + end + main_maccore_ethphy_reset_re <= builder_csrbank2_crg_reset0_re; + if (builder_csrbank2_mdio_w0_re) begin + main_maccore_ethphy__w_storage[2:0] <= builder_csrbank2_mdio_w0_r; + end + main_maccore_ethphy__w_re <= builder_csrbank2_mdio_w0_re; + main_maccore_ethphy__r_re <= builder_csrbank2_mdio_r_re; + if (sys_rst) begin + main_maccore_maccore_reset_storage <= 2'd0; + main_maccore_maccore_reset_re <= 1'd0; + main_maccore_maccore_scratch_storage <= 32'd305419896; + main_maccore_maccore_scratch_re <= 1'd0; + main_maccore_maccore_bus_errors_re <= 1'd0; + main_maccore_maccore_bus_errors <= 32'd0; + main_maccore_ethphy_mode0 <= 1'd0; + main_maccore_ethphy_mode_re <= 1'd0; + main_maccore_ethphy_reset_storage <= 1'd0; + main_maccore_ethphy_reset_re <= 1'd0; + main_maccore_ethphy_counter <= 9'd0; + main_maccore_ethphy__w_storage <= 3'd0; + main_maccore_ethphy__w_re <= 1'd0; + main_maccore_ethphy__r_re <= 1'd0; + main_re <= 1'd0; + main_tx_cdc_cdc_graycounter0_q <= 6'd0; + main_tx_cdc_cdc_graycounter0_q_binary <= 6'd0; + main_preamble_errors_status <= 32'd0; + main_preamble_errors_re <= 1'd0; + main_crc_errors_status <= 32'd0; + main_crc_errors_re <= 1'd0; + main_rx_cdc_cdc_graycounter1_q <= 6'd0; + main_rx_cdc_cdc_graycounter1_q_binary <= 6'd0; + main_sram9_re <= 1'd0; + main_sram12_re <= 1'd0; + main_sram13_status <= 32'd0; + main_sram15_re <= 1'd0; + main_sram24_re <= 1'd0; + main_sram28_re <= 1'd0; + main_sram29_r <= 1'd0; + main_sram31_storage <= 1'd0; + main_sram32_re <= 1'd0; + main_slot <= 1'd0; + main_sram35_length <= 11'd0; + main_sram55_level <= 2'd0; + main_sram57_produce <= 1'd0; + main_sram58_consume <= 1'd0; + main_sram96_re <= 1'd0; + main_sram99_re <= 1'd0; + main_sram101_re <= 1'd0; + main_sram103_re <= 1'd0; + main_sram106_pending <= 1'd0; + main_sram112_re <= 1'd0; + main_sram116_re <= 1'd0; + main_sram117_r <= 1'd0; + main_sram119_storage <= 1'd0; + main_sram120_re <= 1'd0; + main_sram122_length <= 11'd0; + main_sram141_level <= 2'd0; + main_sram143_produce <= 1'd0; + main_sram144_consume <= 1'd0; + main_interface0_ack <= 1'd0; + main_interface1_ack <= 1'd0; + main_interface2_ack <= 1'd0; + main_interface3_ack <= 1'd0; + main_slave_sel_r <= 4'd0; + builder_slave_sel_r <= 2'd0; + builder_count <= 20'd1000000; + builder_liteethphygmiimii_state <= 2'd0; + builder_liteethmacsramwriter_state <= 3'd0; + builder_liteethmacsramreader_state <= 2'd0; + builder_wishbone2csr_state <= 1'd0; + end + builder_xilinxmultiregimpl00 <= main_maccore_ethphy_toggle_i; + builder_xilinxmultiregimpl01 <= builder_xilinxmultiregimpl00; + builder_xilinxmultiregimpl10 <= main_maccore_ethphy_data_r; + builder_xilinxmultiregimpl11 <= builder_xilinxmultiregimpl10; + builder_xilinxmultiregimpl30 <= main_tx_cdc_cdc_graycounter1_q; + builder_xilinxmultiregimpl31 <= builder_xilinxmultiregimpl30; + builder_xilinxmultiregimpl40 <= main_pulsesynchronizer0_toggle_i; + builder_xilinxmultiregimpl41 <= builder_xilinxmultiregimpl40; + builder_xilinxmultiregimpl50 <= main_pulsesynchronizer1_toggle_i; + builder_xilinxmultiregimpl51 <= builder_xilinxmultiregimpl50; + builder_xilinxmultiregimpl60 <= main_rx_cdc_cdc_graycounter0_q; + builder_xilinxmultiregimpl61 <= builder_xilinxmultiregimpl60; end + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Instance BUFG of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG( - .I(gmii_eth_clocks_rx), - .O(eth_rx_clk) + // Inputs. + .I (gmii_clocks_rx), + + // Outputs. + .O (eth_rx_clk) ); +//------------------------------------------------------------------------------ +// Instance BUFG_1 of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG_1( - .I(maccore_ethphy_eth_tx_clk), - .O(eth_tx_clk) + // Inputs. + .I (main_maccore_ethphy_eth_tx_clk), + + // Outputs. + .O (eth_tx_clk) ); -assign gmii_eth_mdio = maccore_ethphy_data_oe ? maccore_ethphy_data_w : 1'bz; -assign maccore_ethphy_data_r = gmii_eth_mdio; +assign gmii_mdio = main_maccore_ethphy_data_oe ? main_maccore_ethphy_data_w : 1'bz; +assign main_maccore_ethphy_data_r = gmii_mdio; -reg [11:0] storage[0:4]; -reg [11:0] memdat; -always @(posedge eth_rx_clk) begin - if (liteethmaccrc32checker_syncfifo_wrport_we) - storage[liteethmaccrc32checker_syncfifo_wrport_adr] <= liteethmaccrc32checker_syncfifo_wrport_dat_w; - memdat <= storage[liteethmaccrc32checker_syncfifo_wrport_adr]; +//------------------------------------------------------------------------------ +// Memory storage: 32-words x 42-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 42 +// Port 1 | Read: Sync | Write: ---- | +reg [41:0] storage[0:31]; +reg [41:0] storage_dat0; +reg [41:0] storage_dat1; +always @(posedge sys_clk) begin + if (main_tx_cdc_cdc_wrport_we) + storage[main_tx_cdc_cdc_wrport_adr] <= main_tx_cdc_cdc_wrport_dat_w; + storage_dat0 <= storage[main_tx_cdc_cdc_wrport_adr]; end - -always @(posedge eth_rx_clk) begin +always @(posedge eth_tx_clk) begin + storage_dat1 <= storage[main_tx_cdc_cdc_rdport_adr]; end +assign main_tx_cdc_cdc_wrport_dat_r = storage_dat0; +assign main_tx_cdc_cdc_rdport_dat_r = storage_dat1; -assign liteethmaccrc32checker_syncfifo_wrport_dat_r = memdat; -assign liteethmaccrc32checker_syncfifo_rdport_dat_r = storage[liteethmaccrc32checker_syncfifo_rdport_adr]; -reg [41:0] storage_1[0:31]; -reg [4:0] memadr; -reg [4:0] memadr_1; -always @(posedge sys_clk) begin - if (tx_cdc_cdc_wrport_we) - storage_1[tx_cdc_cdc_wrport_adr] <= tx_cdc_cdc_wrport_dat_w; - memadr <= tx_cdc_cdc_wrport_adr; +//------------------------------------------------------------------------------ +// Memory storage_1: 5-words x 12-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 12 +// Port 1 | Read: Async | Write: ---- | +reg [11:0] storage_1[0:4]; +reg [11:0] storage_1_dat0; +always @(posedge eth_rx_clk) begin + if (main_liteethmaccrc32checker_syncfifo_wrport_we) + storage_1[main_liteethmaccrc32checker_syncfifo_wrport_adr] <= main_liteethmaccrc32checker_syncfifo_wrport_dat_w; + storage_1_dat0 <= storage_1[main_liteethmaccrc32checker_syncfifo_wrport_adr]; end - -always @(posedge eth_tx_clk) begin - memadr_1 <= tx_cdc_cdc_rdport_adr; +always @(posedge eth_rx_clk) begin end +assign main_liteethmaccrc32checker_syncfifo_wrport_dat_r = storage_1_dat0; +assign main_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage_1[main_liteethmaccrc32checker_syncfifo_rdport_adr]; -assign tx_cdc_cdc_wrport_dat_r = storage_1[memadr]; -assign tx_cdc_cdc_rdport_dat_r = storage_1[memadr_1]; +//------------------------------------------------------------------------------ +// Memory storage_2: 32-words x 42-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 42 +// Port 1 | Read: Sync | Write: ---- | reg [41:0] storage_2[0:31]; -reg [4:0] memadr_2; -reg [4:0] memadr_3; +reg [41:0] storage_2_dat0; +reg [41:0] storage_2_dat1; always @(posedge eth_rx_clk) begin - if (rx_cdc_cdc_wrport_we) - storage_2[rx_cdc_cdc_wrport_adr] <= rx_cdc_cdc_wrport_dat_w; - memadr_2 <= rx_cdc_cdc_wrport_adr; + if (main_rx_cdc_cdc_wrport_we) + storage_2[main_rx_cdc_cdc_wrport_adr] <= main_rx_cdc_cdc_wrport_dat_w; + storage_2_dat0 <= storage_2[main_rx_cdc_cdc_wrport_adr]; end - always @(posedge sys_clk) begin - memadr_3 <= rx_cdc_cdc_rdport_adr; + storage_2_dat1 <= storage_2[main_rx_cdc_cdc_rdport_adr]; end +assign main_rx_cdc_cdc_wrport_dat_r = storage_2_dat0; +assign main_rx_cdc_cdc_rdport_dat_r = storage_2_dat1; -assign rx_cdc_cdc_wrport_dat_r = storage_2[memadr_2]; -assign rx_cdc_cdc_rdport_dat_r = storage_2[memadr_3]; -reg [34:0] storage_3[0:1]; -reg [34:0] memdat_1; +//------------------------------------------------------------------------------ +// Memory storage_3: 2-words x 14-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 14 +// Port 1 | Read: Async | Write: ---- | +reg [13:0] storage_3[0:1]; +reg [13:0] storage_3_dat0; always @(posedge sys_clk) begin - if (writer_stat_fifo_wrport_we) - storage_3[writer_stat_fifo_wrport_adr] <= writer_stat_fifo_wrport_dat_w; - memdat_1 <= storage_3[writer_stat_fifo_wrport_adr]; + if (main_sram61_we) + storage_3[main_sram59_adr] <= main_sram62_dat_w; + storage_3_dat0 <= storage_3[main_sram59_adr]; end - always @(posedge sys_clk) begin end +assign main_sram60_dat_r = storage_3_dat0; +assign main_sram65_dat_r = storage_3[main_sram64_adr]; -assign writer_stat_fifo_wrport_dat_r = memdat_1; -assign writer_stat_fifo_rdport_dat_r = storage_3[writer_stat_fifo_rdport_adr]; -reg [31:0] mem[0:381]; -reg [8:0] memadr_4; -reg [31:0] memdat_2; +//------------------------------------------------------------------------------ +// Memory mem: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 32 +// Port 1 | Read: Sync | Write: ---- | +reg [31:0] mem[0:382]; +reg [8:0] mem_adr0; +reg [31:0] mem_dat1; always @(posedge sys_clk) begin - if (writer_memory0_we) - mem[writer_memory0_adr] <= writer_memory0_dat_w; - memadr_4 <= writer_memory0_adr; + if (main_sram77_we) + mem[main_sram75_adr] <= main_sram78_dat_w; + mem_adr0 <= main_sram75_adr; end - always @(posedge sys_clk) begin - memdat_2 <= mem[sram0_adr0]; + mem_dat1 <= mem[main_sram0_adr]; end +assign main_sram76_dat_r = mem[mem_adr0]; +assign main_sram0_dat_r = mem_dat1; -assign writer_memory0_dat_r = mem[memadr_4]; -assign sram0_dat_r0 = memdat_2; -reg [31:0] mem_1[0:381]; -reg [8:0] memadr_5; -reg [31:0] memdat_3; +//------------------------------------------------------------------------------ +// Memory mem_1: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 32 +// Port 1 | Read: Sync | Write: ---- | +reg [31:0] mem_1[0:382]; +reg [8:0] mem_1_adr0; +reg [31:0] mem_1_dat1; always @(posedge sys_clk) begin - if (writer_memory1_we) - mem_1[writer_memory1_adr] <= writer_memory1_dat_w; - memadr_5 <= writer_memory1_adr; + if (main_sram81_we) + mem_1[main_sram79_adr] <= main_sram82_dat_w; + mem_1_adr0 <= main_sram79_adr; end - always @(posedge sys_clk) begin - memdat_3 <= mem_1[sram1_adr0]; + mem_1_dat1 <= mem_1[main_sram1_adr]; end +assign main_sram80_dat_r = mem_1[mem_1_adr0]; +assign main_sram1_dat_r = mem_1_dat1; -assign writer_memory1_dat_r = mem_1[memadr_5]; -assign sram1_dat_r0 = memdat_3; +//------------------------------------------------------------------------------ +// Memory storage_4: 2-words x 14-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 14 +// Port 1 | Read: Async | Write: ---- | reg [13:0] storage_4[0:1]; -reg [13:0] memdat_4; +reg [13:0] storage_4_dat0; always @(posedge sys_clk) begin - if (reader_cmd_fifo_wrport_we) - storage_4[reader_cmd_fifo_wrport_adr] <= reader_cmd_fifo_wrport_dat_w; - memdat_4 <= storage_4[reader_cmd_fifo_wrport_adr]; + if (main_sram147_we) + storage_4[main_sram145_adr] <= main_sram148_dat_w; + storage_4_dat0 <= storage_4[main_sram145_adr]; end - always @(posedge sys_clk) begin end +assign main_sram146_dat_r = storage_4_dat0; +assign main_sram151_dat_r = storage_4[main_sram150_adr]; -assign reader_cmd_fifo_wrport_dat_r = memdat_4; -assign reader_cmd_fifo_rdport_dat_r = storage_4[reader_cmd_fifo_rdport_adr]; -reg [31:0] mem_2[0:381]; -reg [8:0] memadr_6; -reg [8:0] memadr_7; +//------------------------------------------------------------------------------ +// Memory mem_2: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +reg [31:0] mem_2[0:382]; +reg [31:0] mem_2_dat0; +reg [8:0] mem_2_adr1; always @(posedge sys_clk) begin - memadr_6 <= reader_memory0_adr; + if (main_sram163_re) + mem_2_dat0 <= mem_2[main_sram161_adr]; end - always @(posedge sys_clk) begin - if (sram0_we[0]) - mem_2[sram0_adr1][7:0] <= sram0_dat_w[7:0]; - if (sram0_we[1]) - mem_2[sram0_adr1][15:8] <= sram0_dat_w[15:8]; - if (sram0_we[2]) - mem_2[sram0_adr1][23:16] <= sram0_dat_w[23:16]; - if (sram0_we[3]) - mem_2[sram0_adr1][31:24] <= sram0_dat_w[31:24]; - memadr_7 <= sram0_adr1; + if (main_sram2_we[0]) + mem_2[main_sram2_adr][7:0] <= main_sram2_dat_w[7:0]; + if (main_sram2_we[1]) + mem_2[main_sram2_adr][15:8] <= main_sram2_dat_w[15:8]; + if (main_sram2_we[2]) + mem_2[main_sram2_adr][23:16] <= main_sram2_dat_w[23:16]; + if (main_sram2_we[3]) + mem_2[main_sram2_adr][31:24] <= main_sram2_dat_w[31:24]; + mem_2_adr1 <= main_sram2_adr; end +assign main_sram162_dat_r = mem_2_dat0; +assign main_sram2_dat_r = mem_2[mem_2_adr1]; -assign reader_memory0_dat_r = mem_2[memadr_6]; -assign sram0_dat_r1 = mem_2[memadr_7]; -reg [31:0] mem_3[0:381]; -reg [8:0] memadr_8; -reg [8:0] memadr_9; +//------------------------------------------------------------------------------ +// Memory mem_3: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +reg [31:0] mem_3[0:382]; +reg [31:0] mem_3_dat0; +reg [8:0] mem_3_adr1; always @(posedge sys_clk) begin - memadr_8 <= reader_memory1_adr; + if (main_sram166_re) + mem_3_dat0 <= mem_3[main_sram164_adr]; end - always @(posedge sys_clk) begin - if (sram1_we[0]) - mem_3[sram1_adr1][7:0] <= sram1_dat_w[7:0]; - if (sram1_we[1]) - mem_3[sram1_adr1][15:8] <= sram1_dat_w[15:8]; - if (sram1_we[2]) - mem_3[sram1_adr1][23:16] <= sram1_dat_w[23:16]; - if (sram1_we[3]) - mem_3[sram1_adr1][31:24] <= sram1_dat_w[31:24]; - memadr_9 <= sram1_adr1; + if (main_sram3_we[0]) + mem_3[main_sram3_adr][7:0] <= main_sram3_dat_w[7:0]; + if (main_sram3_we[1]) + mem_3[main_sram3_adr][15:8] <= main_sram3_dat_w[15:8]; + if (main_sram3_we[2]) + mem_3[main_sram3_adr][23:16] <= main_sram3_dat_w[23:16]; + if (main_sram3_we[3]) + mem_3[main_sram3_adr][31:24] <= main_sram3_dat_w[31:24]; + mem_3_adr1 <= main_sram3_adr; end +assign main_sram165_dat_r = mem_3_dat0; +assign main_sram3_dat_r = mem_3[mem_3_adr1]; -assign reader_memory1_dat_r = mem_3[memadr_8]; -assign sram1_dat_r1 = mem_3[memadr_9]; +//------------------------------------------------------------------------------ +// Instance ODDR of ODDR Module. +//------------------------------------------------------------------------------ ODDR #( - .DDR_CLK_EDGE("SAME_EDGE") + // Parameters. + .DDR_CLK_EDGE ("SAME_EDGE") ) ODDR ( - .C(eth_tx_clk), - .CE(1'd1), - .D1(1'd1), - .D2((maccore_ethphy_mode0 == 1'd1)), - .R(1'd0), - .S(1'd0), - .Q(gmii_eth_clocks_gtx) + // Inputs. + .C (eth_tx_clk), + .CE (1'd1), + .D1 (1'd1), + .D2 ((main_maccore_ethphy_mode0 == 1'd1)), + .R (1'd0), + .S (1'd0), + + // Outputs. + .Q (gmii_clocks_gtx) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE ( - .C(eth_tx_clk), - .CE(1'd1), - .D(1'd0), - .PRE(maccore_ethphy_reset0), - .Q(rst_meta0) + // Inputs. + .C (eth_tx_clk), + .CE (1'd1), + .D (1'd0), + .PRE (main_maccore_ethphy_reset0), + + // Outputs. + .Q (builder_rst_meta0) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_1 of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE_1 ( - .C(eth_tx_clk), - .CE(1'd1), - .D(rst_meta0), - .PRE(maccore_ethphy_reset0), - .Q(eth_tx_rst) + // Inputs. + .C (eth_tx_clk), + .CE (1'd1), + .D (builder_rst_meta0), + .PRE (main_maccore_ethphy_reset0), + + // Outputs. + .Q (eth_tx_rst) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_2 of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE_2 ( - .C(eth_rx_clk), - .CE(1'd1), - .D(1'd0), - .PRE(maccore_ethphy_reset0), - .Q(rst_meta1) + // Inputs. + .C (eth_rx_clk), + .CE (1'd1), + .D (1'd0), + .PRE (main_maccore_ethphy_reset0), + + // Outputs. + .Q (builder_rst_meta1) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_3 of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE_3 ( - .C(eth_rx_clk), - .CE(1'd1), - .D(rst_meta1), - .PRE(maccore_ethphy_reset0), - .Q(eth_rx_rst) + // Inputs. + .C (eth_rx_clk), + .CE (1'd1), + .D (builder_rst_meta1), + .PRE (main_maccore_ethphy_reset0), + + // Outputs. + .Q (eth_rx_rst) ); endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2024-04-05 17:38:50. +//------------------------------------------------------------------------------ diff --git a/litesdcard/fusesoc-add-files.py b/litesdcard/fusesoc-add-files.py index 53449e8..3cc0b50 100644 --- a/litesdcard/fusesoc-add-files.py +++ b/litesdcard/fusesoc-add-files.py @@ -7,10 +7,12 @@ import pathlib class LiteSDCardGenerator(Generator): def run(self): vendor = self.config.get('vendor') + clk = self.config.get('frequency') + vf = vendor + "." + clk # Collect a bunch of directory path script_dir = os.path.dirname(sys.argv[0]) - gen_dir = os.path.join(script_dir, "generated", vendor) + gen_dir = os.path.join(script_dir, "generated", vf) print("Adding LiteSDCard for vendor... ", vendor) diff --git a/litesdcard/gen-src/generate.sh b/litesdcard/gen-src/generate.sh index 18c34bc..9c629ff 100755 --- a/litesdcard/gen-src/generate.sh +++ b/litesdcard/gen-src/generate.sh @@ -1,7 +1,7 @@ #!/bin/bash # vendor:sysclk -VENDORS="xilinx:100e6 lattice:48e6" +VENDORS="xilinx:100e6 lattice:48e6 lattice:50e6" ME=$(realpath $0) echo ME=$ME @@ -18,8 +18,8 @@ for i_clk in $VENDORS do i=$(echo $i_clk | cut -d : -f 1) clk=$(echo $i_clk | cut -d : -f 2) - TARGET_BUILD_PATH=$BUILD_PATH/$i - TARGET_GEN_PATH=$GEN_PATH/$i + TARGET_BUILD_PATH=$BUILD_PATH/$i.$clk + TARGET_GEN_PATH=$GEN_PATH/$i.$clk rm -rf $TARGET_BUILD_PATH rm -rf $TARGET_GEN_PATH mkdir -p $TARGET_BUILD_PATH diff --git a/litesdcard/generated/lattice.48e6/litesdcard_core.v b/litesdcard/generated/lattice.48e6/litesdcard_core.v new file mode 100644 index 0000000..1fa5b17 --- /dev/null +++ b/litesdcard/generated/lattice.48e6/litesdcard_core.v @@ -0,0 +1,4679 @@ +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : litesdcard_core.v +// Device : +// LiteX sha1 : 87137c30 +// Date : 2024-04-03 20:02:06 +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ps + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module litesdcard_core ( + input wire clk, + output wire irq, + input wire rst, + input wire sdcard_cd, + output wire sdcard_clk, + inout wire sdcard_cmd, + output wire sdcard_cmd_dir, + output wire sdcard_dat0_dir, + output wire sdcard_dat13_dir, + inout wire [3:0] sdcard_data, + output wire wb_ctrl_ack, + input wire [29:0] wb_ctrl_adr, + input wire [1:0] wb_ctrl_bte, + input wire [2:0] wb_ctrl_cti, + input wire wb_ctrl_cyc, + output wire [31:0] wb_ctrl_dat_r, + input wire [31:0] wb_ctrl_dat_w, + output wire wb_ctrl_err, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_stb, + input wire wb_ctrl_we, + input wire wb_dma_ack, + output wire [29:0] wb_dma_adr, + output wire [1:0] wb_dma_bte, + output wire [2:0] wb_dma_cti, + output wire wb_dma_cyc, + input wire [31:0] wb_dma_dat_r, + output wire [31:0] wb_dma_dat_w, + input wire wb_dma_err, + output wire [3:0] wb_dma_sel, + output wire wb_dma_stb, + output wire wb_dma_we +); + + +//------------------------------------------------------------------------------ +// Hierarchy +//------------------------------------------------------------------------------ + +/* +LiteSDCardCore +└─── crg (CRG) +└─── bus (SoCBusHandler) +│ └─── _interconnect (InterconnectPointToPoint) +└─── csr (SoCCSRHandler) +└─── irq (SoCIRQHandler) +└─── ctrl (SoCController) +└─── cpu (CPUNone) +└─── dma_bus (SoCBusHandler) +│ └─── _interconnect (InterconnectShared) +│ │ └─── arbiter (Arbiter) +│ │ │ └─── rr (RoundRobin) +│ │ └─── decoder (Decoder) +│ │ └─── timeout (Timeout) +│ │ │ └─── waittimer_0* (WaitTimer) +└─── sdcard_phy (SDPHY) +│ └─── clocker (SDPHYClocker) +│ └─── init (SDPHYInit) +│ │ └─── fsm_0* (FSM) +│ └─── cmdw (SDPHYCMDW) +│ │ └─── fsm_0* (FSM) +│ └─── cmdr (SDPHYCMDR) +│ │ └─── sdphyr_0* (SDPHYR) +│ │ │ └─── converter_0* (Converter) +│ │ │ │ └─── _upconverter_0* (_UpConverter) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ └─── fsm_0* (FSM) +│ └─── dataw (SDPHYDATAW) +│ │ └─── crc (SDPHYR) +│ │ │ └─── converter_0* (Converter) +│ │ │ │ └─── _upconverter_0* (_UpConverter) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ └─── fsm (FSM) +│ └─── datar (SDPHYDATAR) +│ │ └─── sdphyr_0* (SDPHYR) +│ │ │ └─── converter_0* (Converter) +│ │ │ │ └─── _upconverter_0* (_UpConverter) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ └─── fsm_0* (FSM) +│ └─── io (SDPHYIOGen) +└─── sdcard_core (SDCore) +│ └─── crc7_inserter (CRC) +│ └─── crc16_inserter (CRC16Inserter) +│ │ └─── crc_0* (CRC) +│ │ └─── crc_1* (CRC) +│ │ └─── crc_2* (CRC) +│ │ └─── crc_3* (CRC) +│ │ └─── fsm (FSM) +│ └─── crc16_checker (CRC16Checker) +│ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ └─── fifo (SyncFIFO) +│ └─── fsm (FSM) +└─── sdcard_block2mem (SDBlock2MemDMA) +│ └─── syncfifo_0* (SyncFIFO) +│ │ └─── fifo (SyncFIFOBuffered) +│ │ │ └─── fifo (SyncFIFO) +│ └─── converter_0* (Converter) +│ │ └─── _upconverter_0* (_UpConverter) +│ └─── dma (WishboneDMAWriter) +│ │ └─── fsm (FSM) +└─── sdcard_mem2block (SDMem2BlockDMA) +│ └─── dma (WishboneDMAReader) +│ │ └─── fifo (SyncFIFO) +│ │ │ └─── fifo (SyncFIFO) +│ │ └─── fsm (FSM) +│ └─── converter_0* (Converter) +│ │ └─── _downconverter_0* (_DownConverter) +│ └─── syncfifo_0* (SyncFIFO) +│ │ └─── fifo (SyncFIFOBuffered) +│ │ │ └─── fifo (SyncFIFO) +└─── sdcard_irq (EventManager) +│ └─── eventsourcepulse_0* (EventSourcePulse) +│ └─── eventsourcepulse_1* (EventSourcePulse) +│ └─── eventsourcepulse_2* (EventSourcePulse) +│ └─── eventsourcelevel_0* (EventSourceLevel) +└─── csr_bridge (Wishbone2CSR) +│ └─── fsm (FSM) +└─── csr_bankarray (CSRBankArray) +│ └─── csrbank_0* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ └─── csrbank_1* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstatus_1* (CSRStatus) +│ └─── csrbank_2* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstatus_1* (CSRStatus) +│ │ └─── csrstatus_2* (CSRStatus) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstorage_4* (CSRStorage) +│ └─── csrbank_3* (CSRBank) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstatus_1* (CSRStatus) +│ │ └─── csrstorage_0* (CSRStorage) +│ └─── csrbank_4* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstatus_1* (CSRStatus) +│ └─── csrbank_5* (CSRBank) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstatus_1* (CSRStatus) +└─── csr_interconnect (InterconnectShared) +└─── [IFS1P3BX] +└─── [OFS1P3BX] +└─── [IFS1P3BX] +└─── [OFS1P3BX] +└─── [IFS1P3BX] +└─── [IFS1P3BX] +└─── [OFS1P3BX] +└─── [IFS1P3BX] +└─── [OFS1P3BX] +└─── [OFS1P3BX] +└─── [OFS1P3BX] +└─── [OFS1P3BX] +└─── [OFS1P3BX] +└─── [OFS1P3BX] +* : Generated name. +[]: BlackBox. +*/ + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +wire [13:0] adr; +reg block2mem_dma_clear = 1'd0; +reg block2mem_dma_pending = 1'd0; +wire block2mem_dma_status; +wire block2mem_dma_trigger; +reg bus_error = 1'd0; +reg [31:0] bus_errors = 32'd0; +reg bus_errors_re = 1'd0; +wire [31:0] bus_errors_status; +wire bus_errors_we; +reg card_detect_clear = 1'd0; +reg card_detect_d = 1'd0; +reg card_detect_irq = 1'd0; +reg card_detect_pending = 1'd0; +reg card_detect_re = 1'd0; +wire card_detect_status0; +wire card_detect_status1; +wire card_detect_trigger; +wire card_detect_we; +wire clocker_ce; +reg clocker_ce_delayed = 1'd0; +reg clocker_ce_latched = 1'd0; +wire clocker_clk0; +reg clocker_clk1 = 1'd0; +reg clocker_clk_d = 1'd0; +reg [1:0] clocker_clk_delay = 2'd0; +wire clocker_clk_en; +reg [8:0] clocker_clks = 9'd0; +reg clocker_re = 1'd0; +wire clocker_stop; +reg [8:0] clocker_storage = 9'd256; +reg cmd_done_clear = 1'd0; +wire cmd_done_pending; +wire cmd_done_status; +wire cmd_done_trigger; +reg cmdr_busy = 1'd0; +reg cmdr_busy_sdphycmdr_next_value2 = 1'd0; +reg cmdr_busy_sdphycmdr_next_value_ce2 = 1'd0; +wire cmdr_cmdr_buf_pipe_valid_sink_first; +wire cmdr_cmdr_buf_pipe_valid_sink_last; +wire [7:0] cmdr_cmdr_buf_pipe_valid_sink_payload_data; +wire cmdr_cmdr_buf_pipe_valid_sink_ready; +wire cmdr_cmdr_buf_pipe_valid_sink_valid; +reg cmdr_cmdr_buf_pipe_valid_source_first = 1'd0; +reg cmdr_cmdr_buf_pipe_valid_source_last = 1'd0; +reg [7:0] cmdr_cmdr_buf_pipe_valid_source_payload_data = 8'd0; +wire cmdr_cmdr_buf_pipe_valid_source_ready; +reg cmdr_cmdr_buf_pipe_valid_source_valid = 1'd0; +wire cmdr_cmdr_buf_sink_sink_first; +wire cmdr_cmdr_buf_sink_sink_last; +wire [7:0] cmdr_cmdr_buf_sink_sink_payload_data; +wire cmdr_cmdr_buf_sink_sink_ready; +wire cmdr_cmdr_buf_sink_sink_valid; +wire cmdr_cmdr_buf_source_source_first; +wire cmdr_cmdr_buf_source_source_last; +wire [7:0] cmdr_cmdr_buf_source_source_payload_data; +wire cmdr_cmdr_buf_source_source_ready; +wire cmdr_cmdr_buf_source_source_valid; +reg [2:0] cmdr_cmdr_converter_converter_demux = 3'd0; +wire cmdr_cmdr_converter_converter_load_part; +reg cmdr_cmdr_converter_converter_sink_first = 1'd0; +reg cmdr_cmdr_converter_converter_sink_last = 1'd0; +wire cmdr_cmdr_converter_converter_sink_payload_data; +wire cmdr_cmdr_converter_converter_sink_ready; +wire cmdr_cmdr_converter_converter_sink_valid; +reg cmdr_cmdr_converter_converter_source_first = 1'd0; +reg cmdr_cmdr_converter_converter_source_last = 1'd0; +reg [7:0] cmdr_cmdr_converter_converter_source_payload_data = 8'd0; +reg [3:0] cmdr_cmdr_converter_converter_source_payload_valid_token_count = 4'd0; +wire cmdr_cmdr_converter_converter_source_ready; +wire cmdr_cmdr_converter_converter_source_valid; +reg cmdr_cmdr_converter_converter_strobe_all = 1'd0; +wire cmdr_cmdr_converter_source_source_first; +wire cmdr_cmdr_converter_source_source_last; +wire [7:0] cmdr_cmdr_converter_source_source_payload_data; +wire cmdr_cmdr_converter_source_source_ready; +wire cmdr_cmdr_converter_source_source_valid; +wire cmdr_cmdr_pads_in_first; +wire cmdr_cmdr_pads_in_last; +wire cmdr_cmdr_pads_in_payload_clk; +wire cmdr_cmdr_pads_in_payload_cmd_i; +wire cmdr_cmdr_pads_in_payload_cmd_o; +wire cmdr_cmdr_pads_in_payload_cmd_oe; +wire [3:0] cmdr_cmdr_pads_in_payload_data_i; +wire cmdr_cmdr_pads_in_payload_data_i_ce; +wire [3:0] cmdr_cmdr_pads_in_payload_data_o; +wire cmdr_cmdr_pads_in_payload_data_oe; +reg cmdr_cmdr_pads_in_ready = 1'd0; +wire cmdr_cmdr_pads_in_valid; +reg cmdr_cmdr_reset = 1'd0; +reg cmdr_cmdr_reset_sdphycmdr_next_value3 = 1'd0; +reg cmdr_cmdr_reset_sdphycmdr_next_value_ce3 = 1'd0; +reg cmdr_cmdr_run = 1'd0; +wire cmdr_cmdr_source_first; +wire cmdr_cmdr_source_last; +wire [7:0] cmdr_cmdr_source_payload_data; +reg cmdr_cmdr_source_ready = 1'd0; +wire cmdr_cmdr_source_valid; +wire cmdr_cmdr_start; +reg [7:0] cmdr_count = 8'd0; +reg [7:0] cmdr_count_sdphycmdr_next_value1 = 8'd0; +reg cmdr_count_sdphycmdr_next_value_ce1 = 1'd0; +reg cmdr_pads_in_pads_in_first = 1'd0; +reg cmdr_pads_in_pads_in_last = 1'd0; +reg cmdr_pads_in_pads_in_payload_clk = 1'd0; +wire cmdr_pads_in_pads_in_payload_cmd_i; +reg cmdr_pads_in_pads_in_payload_cmd_o = 1'd0; +reg cmdr_pads_in_pads_in_payload_cmd_oe = 1'd0; +wire [3:0] cmdr_pads_in_pads_in_payload_data_i; +reg cmdr_pads_in_pads_in_payload_data_i_ce = 1'd0; +reg [3:0] cmdr_pads_in_pads_in_payload_data_o = 4'd0; +reg cmdr_pads_in_pads_in_payload_data_oe = 1'd0; +wire cmdr_pads_in_pads_in_ready; +wire cmdr_pads_in_pads_in_valid; +reg cmdr_pads_out_payload_clk = 1'd0; +reg cmdr_pads_out_payload_cmd_o = 1'd0; +reg cmdr_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] cmdr_pads_out_payload_data_o = 4'd0; +reg cmdr_pads_out_payload_data_oe = 1'd0; +wire cmdr_pads_out_ready; +reg [1:0] cmdr_sink_payload_cmd_type = 2'd0; +reg [1:0] cmdr_sink_payload_data_type = 2'd0; +reg [7:0] cmdr_sink_payload_length = 8'd0; +reg cmdr_sink_ready = 1'd0; +reg cmdr_sink_valid = 1'd0; +reg cmdr_source_source_last = 1'd0; +reg [7:0] cmdr_source_source_payload_data = 8'd0; +reg [2:0] cmdr_source_source_payload_status = 3'd0; +reg cmdr_source_source_ready = 1'd0; +reg cmdr_source_source_valid = 1'd0; +reg [31:0] cmdr_timeout = 32'd48000000; +reg [31:0] cmdr_timeout_sdphycmdr_next_value0 = 32'd0; +reg cmdr_timeout_sdphycmdr_next_value_ce0 = 1'd0; +reg [7:0] cmdw_count = 8'd0; +reg [7:0] cmdw_count_sdphycmdw_next_value = 8'd0; +reg cmdw_count_sdphycmdw_next_value_ce = 1'd0; +reg cmdw_done = 1'd0; +wire cmdw_pads_in_payload_cmd_i; +wire [3:0] cmdw_pads_in_payload_data_i; +wire cmdw_pads_in_valid; +reg cmdw_pads_out_payload_clk = 1'd0; +reg cmdw_pads_out_payload_cmd_o = 1'd0; +reg cmdw_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] cmdw_pads_out_payload_data_o = 4'd0; +reg cmdw_pads_out_payload_data_oe = 1'd0; +wire cmdw_pads_out_ready; +reg cmdw_sink_last = 1'd0; +reg [1:0] cmdw_sink_payload_cmd_type = 2'd0; +reg [7:0] cmdw_sink_payload_data = 8'd0; +reg cmdw_sink_ready = 1'd0; +reg cmdw_sink_valid = 1'd0; +reg [19:0] count = 20'd1000000; +wire cpu_rst; +reg crc16inserter_next_state = 1'd0; +reg crc16inserter_state = 1'd0; +wire [31:0] csrbank0_bus_errors_r; +reg csrbank0_bus_errors_re = 1'd0; +wire [31:0] csrbank0_bus_errors_w; +reg csrbank0_bus_errors_we = 1'd0; +wire [1:0] csrbank0_reset0_r; +reg csrbank0_reset0_re = 1'd0; +wire [1:0] csrbank0_reset0_w; +reg csrbank0_reset0_we = 1'd0; +wire [31:0] csrbank0_scratch0_r; +reg csrbank0_scratch0_re = 1'd0; +wire [31:0] csrbank0_scratch0_w; +reg csrbank0_scratch0_we = 1'd0; +wire csrbank0_sel; +wire [31:0] csrbank1_dma_base0_r; +reg csrbank1_dma_base0_re = 1'd0; +wire [31:0] csrbank1_dma_base0_w; +reg csrbank1_dma_base0_we = 1'd0; +wire [31:0] csrbank1_dma_base1_r; +reg csrbank1_dma_base1_re = 1'd0; +wire [31:0] csrbank1_dma_base1_w; +reg csrbank1_dma_base1_we = 1'd0; +wire csrbank1_dma_done_r; +reg csrbank1_dma_done_re = 1'd0; +wire csrbank1_dma_done_w; +reg csrbank1_dma_done_we = 1'd0; +wire csrbank1_dma_enable0_r; +reg csrbank1_dma_enable0_re = 1'd0; +wire csrbank1_dma_enable0_w; +reg csrbank1_dma_enable0_we = 1'd0; +wire [31:0] csrbank1_dma_length0_r; +reg csrbank1_dma_length0_re = 1'd0; +wire [31:0] csrbank1_dma_length0_w; +reg csrbank1_dma_length0_we = 1'd0; +wire csrbank1_dma_loop0_r; +reg csrbank1_dma_loop0_re = 1'd0; +wire csrbank1_dma_loop0_w; +reg csrbank1_dma_loop0_we = 1'd0; +wire [31:0] csrbank1_dma_offset_r; +reg csrbank1_dma_offset_re = 1'd0; +wire [31:0] csrbank1_dma_offset_w; +reg csrbank1_dma_offset_we = 1'd0; +wire csrbank1_sel; +wire [31:0] csrbank2_block_count0_r; +reg csrbank2_block_count0_re = 1'd0; +wire [31:0] csrbank2_block_count0_w; +reg csrbank2_block_count0_we = 1'd0; +wire [9:0] csrbank2_block_length0_r; +reg csrbank2_block_length0_re = 1'd0; +wire [9:0] csrbank2_block_length0_w; +reg csrbank2_block_length0_we = 1'd0; +wire [31:0] csrbank2_cmd_argument0_r; +reg csrbank2_cmd_argument0_re = 1'd0; +wire [31:0] csrbank2_cmd_argument0_w; +reg csrbank2_cmd_argument0_we = 1'd0; +wire [13:0] csrbank2_cmd_command0_r; +reg csrbank2_cmd_command0_re = 1'd0; +wire [13:0] csrbank2_cmd_command0_w; +reg csrbank2_cmd_command0_we = 1'd0; +wire [3:0] csrbank2_cmd_event_r; +reg csrbank2_cmd_event_re = 1'd0; +wire [3:0] csrbank2_cmd_event_w; +reg csrbank2_cmd_event_we = 1'd0; +wire [31:0] csrbank2_cmd_response0_r; +reg csrbank2_cmd_response0_re = 1'd0; +wire [31:0] csrbank2_cmd_response0_w; +reg csrbank2_cmd_response0_we = 1'd0; +wire [31:0] csrbank2_cmd_response1_r; +reg csrbank2_cmd_response1_re = 1'd0; +wire [31:0] csrbank2_cmd_response1_w; +reg csrbank2_cmd_response1_we = 1'd0; +wire [31:0] csrbank2_cmd_response2_r; +reg csrbank2_cmd_response2_re = 1'd0; +wire [31:0] csrbank2_cmd_response2_w; +reg csrbank2_cmd_response2_we = 1'd0; +wire [31:0] csrbank2_cmd_response3_r; +reg csrbank2_cmd_response3_re = 1'd0; +wire [31:0] csrbank2_cmd_response3_w; +reg csrbank2_cmd_response3_we = 1'd0; +wire csrbank2_cmd_send0_r; +reg csrbank2_cmd_send0_re = 1'd0; +wire csrbank2_cmd_send0_w; +reg csrbank2_cmd_send0_we = 1'd0; +wire [3:0] csrbank2_data_event_r; +reg csrbank2_data_event_re = 1'd0; +wire [3:0] csrbank2_data_event_w; +reg csrbank2_data_event_we = 1'd0; +wire csrbank2_sel; +wire [3:0] csrbank3_enable0_r; +reg csrbank3_enable0_re = 1'd0; +wire [3:0] csrbank3_enable0_w; +reg csrbank3_enable0_we = 1'd0; +wire [3:0] csrbank3_pending_r; +reg csrbank3_pending_re = 1'd0; +wire [3:0] csrbank3_pending_w; +reg csrbank3_pending_we = 1'd0; +wire csrbank3_sel; +wire [3:0] csrbank3_status_r; +reg csrbank3_status_re = 1'd0; +wire [3:0] csrbank3_status_w; +reg csrbank3_status_we = 1'd0; +wire [31:0] csrbank4_dma_base0_r; +reg csrbank4_dma_base0_re = 1'd0; +wire [31:0] csrbank4_dma_base0_w; +reg csrbank4_dma_base0_we = 1'd0; +wire [31:0] csrbank4_dma_base1_r; +reg csrbank4_dma_base1_re = 1'd0; +wire [31:0] csrbank4_dma_base1_w; +reg csrbank4_dma_base1_we = 1'd0; +wire csrbank4_dma_done_r; +reg csrbank4_dma_done_re = 1'd0; +wire csrbank4_dma_done_w; +reg csrbank4_dma_done_we = 1'd0; +wire csrbank4_dma_enable0_r; +reg csrbank4_dma_enable0_re = 1'd0; +wire csrbank4_dma_enable0_w; +reg csrbank4_dma_enable0_we = 1'd0; +wire [31:0] csrbank4_dma_length0_r; +reg csrbank4_dma_length0_re = 1'd0; +wire [31:0] csrbank4_dma_length0_w; +reg csrbank4_dma_length0_we = 1'd0; +wire csrbank4_dma_loop0_r; +reg csrbank4_dma_loop0_re = 1'd0; +wire csrbank4_dma_loop0_w; +reg csrbank4_dma_loop0_we = 1'd0; +wire [31:0] csrbank4_dma_offset_r; +reg csrbank4_dma_offset_re = 1'd0; +wire [31:0] csrbank4_dma_offset_w; +reg csrbank4_dma_offset_we = 1'd0; +wire csrbank4_sel; +wire csrbank5_card_detect_r; +reg csrbank5_card_detect_re = 1'd0; +wire csrbank5_card_detect_w; +reg csrbank5_card_detect_we = 1'd0; +wire [8:0] csrbank5_clocker_divider0_r; +reg csrbank5_clocker_divider0_re = 1'd0; +wire [8:0] csrbank5_clocker_divider0_w; +reg csrbank5_clocker_divider0_we = 1'd0; +wire [2:0] csrbank5_dataw_status_r; +reg csrbank5_dataw_status_re = 1'd0; +wire [2:0] csrbank5_dataw_status_w; +reg csrbank5_dataw_status_we = 1'd0; +wire csrbank5_sel; +wire [31:0] dat_r; +wire [31:0] dat_w; +reg [9:0] datar_count = 10'd0; +reg [9:0] datar_count_sdphydatar_next_value0 = 10'd0; +reg datar_count_sdphydatar_next_value_ce0 = 1'd0; +wire datar_datar_buf_pipe_valid_sink_first; +wire datar_datar_buf_pipe_valid_sink_last; +wire [7:0] datar_datar_buf_pipe_valid_sink_payload_data; +wire datar_datar_buf_pipe_valid_sink_ready; +wire datar_datar_buf_pipe_valid_sink_valid; +reg datar_datar_buf_pipe_valid_source_first = 1'd0; +reg datar_datar_buf_pipe_valid_source_last = 1'd0; +reg [7:0] datar_datar_buf_pipe_valid_source_payload_data = 8'd0; +wire datar_datar_buf_pipe_valid_source_ready; +reg datar_datar_buf_pipe_valid_source_valid = 1'd0; +wire datar_datar_buf_sink_sink_first; +wire datar_datar_buf_sink_sink_last; +wire [7:0] datar_datar_buf_sink_sink_payload_data; +wire datar_datar_buf_sink_sink_ready; +wire datar_datar_buf_sink_sink_valid; +wire datar_datar_buf_source_source_first; +wire datar_datar_buf_source_source_last; +wire [7:0] datar_datar_buf_source_source_payload_data; +wire datar_datar_buf_source_source_ready; +wire datar_datar_buf_source_source_valid; +reg datar_datar_converter_converter_demux = 1'd0; +wire datar_datar_converter_converter_load_part; +reg datar_datar_converter_converter_sink_first = 1'd0; +reg datar_datar_converter_converter_sink_last = 1'd0; +wire [3:0] datar_datar_converter_converter_sink_payload_data; +wire datar_datar_converter_converter_sink_ready; +wire datar_datar_converter_converter_sink_valid; +reg datar_datar_converter_converter_source_first = 1'd0; +reg datar_datar_converter_converter_source_last = 1'd0; +reg [7:0] datar_datar_converter_converter_source_payload_data = 8'd0; +reg [1:0] datar_datar_converter_converter_source_payload_valid_token_count = 2'd0; +wire datar_datar_converter_converter_source_ready; +wire datar_datar_converter_converter_source_valid; +reg datar_datar_converter_converter_strobe_all = 1'd0; +wire datar_datar_converter_source_source_first; +wire datar_datar_converter_source_source_last; +wire [7:0] datar_datar_converter_source_source_payload_data; +wire datar_datar_converter_source_source_ready; +wire datar_datar_converter_source_source_valid; +wire datar_datar_pads_in_first; +wire datar_datar_pads_in_last; +wire datar_datar_pads_in_payload_clk; +wire datar_datar_pads_in_payload_cmd_i; +wire datar_datar_pads_in_payload_cmd_o; +wire datar_datar_pads_in_payload_cmd_oe; +wire [3:0] datar_datar_pads_in_payload_data_i; +wire datar_datar_pads_in_payload_data_i_ce; +wire [3:0] datar_datar_pads_in_payload_data_o; +wire datar_datar_pads_in_payload_data_oe; +reg datar_datar_pads_in_ready = 1'd0; +wire datar_datar_pads_in_valid; +reg datar_datar_reset = 1'd0; +reg datar_datar_reset_sdphydatar_next_value2 = 1'd0; +reg datar_datar_reset_sdphydatar_next_value_ce2 = 1'd0; +reg datar_datar_run = 1'd0; +wire datar_datar_source_first; +wire datar_datar_source_last; +wire [7:0] datar_datar_source_payload_data; +reg datar_datar_source_ready = 1'd0; +wire datar_datar_source_valid; +wire datar_datar_start; +reg datar_pads_in_pads_in_first = 1'd0; +reg datar_pads_in_pads_in_last = 1'd0; +reg datar_pads_in_pads_in_payload_clk = 1'd0; +wire datar_pads_in_pads_in_payload_cmd_i; +reg datar_pads_in_pads_in_payload_cmd_o = 1'd0; +reg datar_pads_in_pads_in_payload_cmd_oe = 1'd0; +wire [3:0] datar_pads_in_pads_in_payload_data_i; +reg datar_pads_in_pads_in_payload_data_i_ce = 1'd0; +reg [3:0] datar_pads_in_pads_in_payload_data_o = 4'd0; +reg datar_pads_in_pads_in_payload_data_oe = 1'd0; +wire datar_pads_in_pads_in_ready; +wire datar_pads_in_pads_in_valid; +reg datar_pads_out_payload_clk = 1'd0; +reg datar_pads_out_payload_cmd_o = 1'd0; +reg datar_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] datar_pads_out_payload_data_o = 4'd0; +reg datar_pads_out_payload_data_oe = 1'd0; +wire datar_pads_out_ready; +reg datar_sink_last = 1'd0; +reg [9:0] datar_sink_payload_block_length = 10'd0; +reg datar_sink_ready = 1'd0; +reg datar_sink_valid = 1'd0; +reg datar_source_source_first = 1'd0; +reg datar_source_source_last = 1'd0; +reg [7:0] datar_source_source_payload_data = 8'd0; +reg [2:0] datar_source_source_payload_status = 3'd0; +reg datar_source_source_ready = 1'd0; +reg datar_source_source_valid = 1'd0; +reg datar_stop = 1'd0; +reg [31:0] datar_timeout = 32'd48000000; +reg [31:0] datar_timeout_sdphydatar_next_value1 = 32'd0; +reg datar_timeout_sdphydatar_next_value_ce1 = 1'd0; +wire dataw_accepted0; +reg dataw_accepted1 = 1'd0; +reg dataw_accepted1_sdphydataw_next_value0 = 1'd0; +reg dataw_accepted1_sdphydataw_next_value_ce0 = 1'd0; +reg [7:0] dataw_count = 8'd0; +reg [7:0] dataw_count_sdphydataw_next_value3 = 8'd0; +reg dataw_count_sdphydataw_next_value_ce3 = 1'd0; +wire dataw_crc_buf_pipe_valid_sink_first; +wire dataw_crc_buf_pipe_valid_sink_last; +wire [7:0] dataw_crc_buf_pipe_valid_sink_payload_data; +wire dataw_crc_buf_pipe_valid_sink_ready; +wire dataw_crc_buf_pipe_valid_sink_valid; +reg dataw_crc_buf_pipe_valid_source_first = 1'd0; +reg dataw_crc_buf_pipe_valid_source_last = 1'd0; +reg [7:0] dataw_crc_buf_pipe_valid_source_payload_data = 8'd0; +wire dataw_crc_buf_pipe_valid_source_ready; +reg dataw_crc_buf_pipe_valid_source_valid = 1'd0; +wire dataw_crc_buf_sink_sink_first; +wire dataw_crc_buf_sink_sink_last; +wire [7:0] dataw_crc_buf_sink_sink_payload_data; +wire dataw_crc_buf_sink_sink_ready; +wire dataw_crc_buf_sink_sink_valid; +wire dataw_crc_buf_source_source_first; +wire dataw_crc_buf_source_source_last; +wire [7:0] dataw_crc_buf_source_source_payload_data; +wire dataw_crc_buf_source_source_ready; +wire dataw_crc_buf_source_source_valid; +reg [2:0] dataw_crc_converter_converter_demux = 3'd0; +wire dataw_crc_converter_converter_load_part; +reg dataw_crc_converter_converter_sink_first = 1'd0; +reg dataw_crc_converter_converter_sink_last = 1'd0; +wire dataw_crc_converter_converter_sink_payload_data; +wire dataw_crc_converter_converter_sink_ready; +wire dataw_crc_converter_converter_sink_valid; +reg dataw_crc_converter_converter_source_first = 1'd0; +reg dataw_crc_converter_converter_source_last = 1'd0; +reg [7:0] dataw_crc_converter_converter_source_payload_data = 8'd0; +reg [3:0] dataw_crc_converter_converter_source_payload_valid_token_count = 4'd0; +wire dataw_crc_converter_converter_source_ready; +wire dataw_crc_converter_converter_source_valid; +reg dataw_crc_converter_converter_strobe_all = 1'd0; +wire dataw_crc_converter_source_source_first; +wire dataw_crc_converter_source_source_last; +wire [7:0] dataw_crc_converter_source_source_payload_data; +wire dataw_crc_converter_source_source_ready; +wire dataw_crc_converter_source_source_valid; +wire dataw_crc_error0; +reg dataw_crc_error1 = 1'd0; +reg dataw_crc_error1_sdphydataw_next_value1 = 1'd0; +reg dataw_crc_error1_sdphydataw_next_value_ce1 = 1'd0; +wire dataw_crc_pads_in_first; +wire dataw_crc_pads_in_last; +wire dataw_crc_pads_in_payload_clk; +wire dataw_crc_pads_in_payload_cmd_i; +wire dataw_crc_pads_in_payload_cmd_o; +wire dataw_crc_pads_in_payload_cmd_oe; +wire [3:0] dataw_crc_pads_in_payload_data_i; +wire dataw_crc_pads_in_payload_data_i_ce; +wire [3:0] dataw_crc_pads_in_payload_data_o; +wire dataw_crc_pads_in_payload_data_oe; +wire dataw_crc_pads_in_ready; +wire dataw_crc_pads_in_valid; +reg dataw_crc_reset = 1'd0; +reg dataw_crc_run = 1'd0; +wire dataw_crc_source_first; +wire dataw_crc_source_last; +wire [7:0] dataw_crc_source_payload_data; +reg dataw_crc_source_ready = 1'd0; +wire dataw_crc_source_valid; +wire dataw_crc_start; +reg dataw_pads_in_pads_in_first = 1'd0; +reg dataw_pads_in_pads_in_last = 1'd0; +reg dataw_pads_in_pads_in_payload_clk = 1'd0; +wire dataw_pads_in_pads_in_payload_cmd_i; +reg dataw_pads_in_pads_in_payload_cmd_o = 1'd0; +reg dataw_pads_in_pads_in_payload_cmd_oe = 1'd0; +wire [3:0] dataw_pads_in_pads_in_payload_data_i; +reg dataw_pads_in_pads_in_payload_data_i_ce = 1'd0; +reg [3:0] dataw_pads_in_pads_in_payload_data_o = 4'd0; +reg dataw_pads_in_pads_in_payload_data_oe = 1'd0; +reg dataw_pads_in_pads_in_ready = 1'd0; +wire dataw_pads_in_pads_in_valid; +reg dataw_pads_out_payload_clk = 1'd0; +reg dataw_pads_out_payload_cmd_o = 1'd0; +reg dataw_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] dataw_pads_out_payload_data_o = 4'd0; +reg dataw_pads_out_payload_data_oe = 1'd0; +wire dataw_pads_out_ready; +reg dataw_re = 1'd0; +reg dataw_sink_first = 1'd0; +reg dataw_sink_last = 1'd0; +reg [7:0] dataw_sink_payload_data = 8'd0; +reg dataw_sink_ready = 1'd0; +reg dataw_sink_valid = 1'd0; +reg [2:0] dataw_status = 3'd0; +reg dataw_stop = 1'd0; +wire dataw_we; +wire dataw_write_error0; +reg dataw_write_error1 = 1'd0; +reg dataw_write_error1_sdphydataw_next_value2 = 1'd0; +reg dataw_write_error1_sdphydataw_next_value_ce2 = 1'd0; +wire done; +reg error = 1'd0; +wire eventmanager_block2mem_dma0; +wire eventmanager_block2mem_dma1; +wire eventmanager_block2mem_dma2; +wire eventmanager_card_detect0; +wire eventmanager_card_detect1; +wire eventmanager_card_detect2; +wire eventmanager_cmd_done0; +wire eventmanager_cmd_done1; +wire eventmanager_cmd_done2; +reg eventmanager_enable_re = 1'd0; +reg [3:0] eventmanager_enable_storage = 4'd0; +wire eventmanager_mem2block_dma0; +wire eventmanager_mem2block_dma1; +wire eventmanager_mem2block_dma2; +reg [3:0] eventmanager_pending_r = 4'd0; +reg eventmanager_pending_re = 1'd0; +reg [3:0] eventmanager_pending_status = 4'd0; +wire eventmanager_pending_we; +reg eventmanager_status_re = 1'd0; +reg [3:0] eventmanager_status_status = 4'd0; +wire eventmanager_status_we; +reg [2:0] fsm_next_state = 3'd0; +reg [2:0] fsm_state = 3'd0; +reg grant = 1'd0; +wire inferedsdrtristate0__i; +wire inferedsdrtristate0__o; +reg inferedsdrtristate0_oe = 1'd0; +wire inferedsdrtristate1__i; +wire inferedsdrtristate1__o; +reg inferedsdrtristate1_oe = 1'd0; +wire inferedsdrtristate2__i; +wire inferedsdrtristate2__o; +reg inferedsdrtristate2_oe = 1'd0; +wire inferedsdrtristate3__i; +wire inferedsdrtristate3__o; +reg inferedsdrtristate3_oe = 1'd0; +wire inferedsdrtristate4__i; +wire inferedsdrtristate4__o; +reg inferedsdrtristate4_oe = 1'd0; +reg [7:0] init_count = 8'd0; +reg [7:0] init_count_sdphyinit_next_value = 8'd0; +reg init_count_sdphyinit_next_value_ce = 1'd0; +wire init_initialize_r; +reg init_initialize_re = 1'd0; +reg init_initialize_w = 1'd0; +reg init_initialize_we = 1'd0; +wire init_pads_in_payload_cmd_i; +wire [3:0] init_pads_in_payload_data_i; +wire init_pads_in_valid; +reg init_pads_out_payload_clk = 1'd0; +reg init_pads_out_payload_cmd_o = 1'd0; +reg init_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] init_pads_out_payload_data_o = 4'd0; +reg init_pads_out_payload_data_oe = 1'd0; +wire init_pads_out_ready; +reg int_rst = 1'd1; +reg interface0_ack = 1'd0; +wire [29:0] interface0_adr; +wire [13:0] interface0_bank_bus_adr; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; +wire [31:0] interface0_bank_bus_dat_w; +wire interface0_bank_bus_we; +wire [1:0] interface0_bte; +wire interface0_bus_ack; +wire [31:0] interface0_bus_adr; +reg [1:0] interface0_bus_bte = 2'd0; +reg [2:0] interface0_bus_cti = 3'd0; +wire interface0_bus_cyc; +wire [31:0] interface0_bus_dat_r; +wire [31:0] interface0_bus_dat_w; +wire interface0_bus_err; +wire [3:0] interface0_bus_sel; +wire interface0_bus_stb; +wire interface0_bus_we; +wire [2:0] interface0_cti; +wire interface0_cyc; +reg [31:0] interface0_dat_r = 32'd0; +wire [31:0] interface0_dat_w; +reg interface0_err = 1'd0; +wire [3:0] interface0_sel; +wire interface0_stb; +wire interface0_we; +reg [13:0] interface1_adr = 14'd0; +wire [13:0] interface1_bank_bus_adr; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; +wire [31:0] interface1_bank_bus_dat_w; +wire interface1_bank_bus_we; +wire interface1_bus_ack; +wire [31:0] interface1_bus_adr; +reg [1:0] interface1_bus_bte = 2'd0; +reg [2:0] interface1_bus_cti = 3'd0; +wire interface1_bus_cyc; +wire [31:0] interface1_bus_dat_r; +reg [31:0] interface1_bus_dat_w = 32'd0; +wire interface1_bus_err; +wire [3:0] interface1_bus_sel; +wire interface1_bus_stb; +wire interface1_bus_we; +wire [31:0] interface1_dat_r; +reg [31:0] interface1_dat_w = 32'd0; +reg interface1_we = 1'd0; +wire [13:0] interface2_bank_bus_adr; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; +wire [31:0] interface2_bank_bus_dat_w; +wire interface2_bank_bus_we; +wire [13:0] interface3_bank_bus_adr; +reg [31:0] interface3_bank_bus_dat_r = 32'd0; +wire [31:0] interface3_bank_bus_dat_w; +wire interface3_bank_bus_we; +wire [13:0] interface4_bank_bus_adr; +reg [31:0] interface4_bank_bus_dat_r = 32'd0; +wire [31:0] interface4_bank_bus_dat_w; +wire interface4_bank_bus_we; +wire [13:0] interface5_bank_bus_adr; +reg [31:0] interface5_bank_bus_dat_r = 32'd0; +wire [31:0] interface5_bank_bus_dat_w; +wire interface5_bank_bus_we; +reg mem2block_dma_clear = 1'd0; +reg mem2block_dma_pending = 1'd0; +wire mem2block_dma_status; +wire mem2block_dma_trigger; +wire por_clk; +wire [1:0] request; +reg reset_re = 1'd0; +reg [1:0] reset_storage = 2'd0; +reg scratch_re = 1'd0; +reg [31:0] scratch_storage = 32'd305419896; +reg [1:0] sdblock2memdma_next_state = 2'd0; +reg [1:0] sdblock2memdma_state = 2'd0; +reg sdcard_block2mem_connect = 1'd0; +reg [1:0] sdcard_block2mem_converter_demux = 2'd0; +wire sdcard_block2mem_converter_load_part; +wire sdcard_block2mem_converter_sink_first; +wire sdcard_block2mem_converter_sink_last; +wire [7:0] sdcard_block2mem_converter_sink_payload_data; +wire sdcard_block2mem_converter_sink_ready; +wire sdcard_block2mem_converter_sink_valid; +reg sdcard_block2mem_converter_source_first = 1'd0; +reg sdcard_block2mem_converter_source_last = 1'd0; +reg [31:0] sdcard_block2mem_converter_source_payload_data = 32'd0; +reg [2:0] sdcard_block2mem_converter_source_payload_valid_token_count = 3'd0; +wire sdcard_block2mem_converter_source_ready; +wire sdcard_block2mem_converter_source_valid; +reg sdcard_block2mem_converter_strobe_all = 1'd0; +reg sdcard_block2mem_done_d = 1'd0; +reg [8:0] sdcard_block2mem_fifo_consume = 9'd0; +wire sdcard_block2mem_fifo_do_read; +wire sdcard_block2mem_fifo_fifo_in_first; +wire sdcard_block2mem_fifo_fifo_in_last; +wire [7:0] sdcard_block2mem_fifo_fifo_in_payload_data; +wire sdcard_block2mem_fifo_fifo_out_first; +wire sdcard_block2mem_fifo_fifo_out_last; +wire [7:0] sdcard_block2mem_fifo_fifo_out_payload_data; +reg [9:0] sdcard_block2mem_fifo_level0 = 10'd0; +wire [9:0] sdcard_block2mem_fifo_level1; +reg [8:0] sdcard_block2mem_fifo_produce = 9'd0; +wire [8:0] sdcard_block2mem_fifo_rdport_adr; +wire [9:0] sdcard_block2mem_fifo_rdport_dat_r; +wire sdcard_block2mem_fifo_rdport_re; +wire sdcard_block2mem_fifo_re; +reg sdcard_block2mem_fifo_readable = 1'd0; +reg sdcard_block2mem_fifo_replace = 1'd0; +reg sdcard_block2mem_fifo_sink_first = 1'd0; +reg sdcard_block2mem_fifo_sink_last = 1'd0; +reg [7:0] sdcard_block2mem_fifo_sink_payload_data = 8'd0; +wire sdcard_block2mem_fifo_sink_ready; +reg sdcard_block2mem_fifo_sink_valid = 1'd0; +wire sdcard_block2mem_fifo_source_first; +wire sdcard_block2mem_fifo_source_last; +wire [7:0] sdcard_block2mem_fifo_source_payload_data; +wire sdcard_block2mem_fifo_source_ready; +wire sdcard_block2mem_fifo_source_valid; +wire [9:0] sdcard_block2mem_fifo_syncfifo_din; +wire [9:0] sdcard_block2mem_fifo_syncfifo_dout; +wire sdcard_block2mem_fifo_syncfifo_re; +wire sdcard_block2mem_fifo_syncfifo_readable; +wire sdcard_block2mem_fifo_syncfifo_we; +wire sdcard_block2mem_fifo_syncfifo_writable; +reg [8:0] sdcard_block2mem_fifo_wrport_adr = 9'd0; +wire [9:0] sdcard_block2mem_fifo_wrport_dat_r; +wire [9:0] sdcard_block2mem_fifo_wrport_dat_w; +wire sdcard_block2mem_fifo_wrport_we; +reg sdcard_block2mem_irq = 1'd0; +wire sdcard_block2mem_sink_sink_first; +wire sdcard_block2mem_sink_sink_last0; +reg sdcard_block2mem_sink_sink_last1 = 1'd0; +reg [31:0] sdcard_block2mem_sink_sink_payload_address = 32'd0; +wire [7:0] sdcard_block2mem_sink_sink_payload_data0; +reg [31:0] sdcard_block2mem_sink_sink_payload_data1 = 32'd0; +reg sdcard_block2mem_sink_sink_ready0 = 1'd0; +wire sdcard_block2mem_sink_sink_ready1; +wire sdcard_block2mem_sink_sink_valid0; +reg sdcard_block2mem_sink_sink_valid1 = 1'd0; +wire sdcard_block2mem_source_source_first; +wire sdcard_block2mem_source_source_last; +wire [31:0] sdcard_block2mem_source_source_payload_data; +wire sdcard_block2mem_source_source_ready; +wire sdcard_block2mem_source_source_valid; +wire sdcard_block2mem_start; +wire [31:0] sdcard_block2mem_wishbonedmawriter_base; +reg sdcard_block2mem_wishbonedmawriter_base_re = 1'd0; +reg [63:0] sdcard_block2mem_wishbonedmawriter_base_storage = 64'd0; +reg sdcard_block2mem_wishbonedmawriter_done_re = 1'd0; +reg sdcard_block2mem_wishbonedmawriter_done_status = 1'd0; +wire sdcard_block2mem_wishbonedmawriter_done_we; +reg sdcard_block2mem_wishbonedmawriter_enable_re = 1'd0; +reg sdcard_block2mem_wishbonedmawriter_enable_storage = 1'd0; +wire [31:0] sdcard_block2mem_wishbonedmawriter_length; +reg sdcard_block2mem_wishbonedmawriter_length_re = 1'd0; +reg [31:0] sdcard_block2mem_wishbonedmawriter_length_storage = 32'd0; +reg sdcard_block2mem_wishbonedmawriter_loop_re = 1'd0; +reg sdcard_block2mem_wishbonedmawriter_loop_storage = 1'd0; +reg [31:0] sdcard_block2mem_wishbonedmawriter_offset = 32'd0; +reg sdcard_block2mem_wishbonedmawriter_offset_re = 1'd0; +reg [31:0] sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value = 32'd0; +reg sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce = 1'd0; +wire [31:0] sdcard_block2mem_wishbonedmawriter_offset_status; +wire sdcard_block2mem_wishbonedmawriter_offset_we; +wire sdcard_block2mem_wishbonedmawriter_reset; +wire sdcard_block2mem_wishbonedmawriter_sink_first; +wire sdcard_block2mem_wishbonedmawriter_sink_last; +wire [31:0] sdcard_block2mem_wishbonedmawriter_sink_payload_data; +reg sdcard_block2mem_wishbonedmawriter_sink_ready = 1'd0; +wire sdcard_block2mem_wishbonedmawriter_sink_valid; +reg sdcard_core_block_count_re = 1'd0; +reg [31:0] sdcard_core_block_count_storage = 32'd0; +reg sdcard_core_block_length_re = 1'd0; +reg [9:0] sdcard_core_block_length_storage = 10'd0; +wire [5:0] sdcard_core_cmd; +reg sdcard_core_cmd_argument_re = 1'd0; +reg [31:0] sdcard_core_cmd_argument_storage = 32'd0; +reg sdcard_core_cmd_command_re = 1'd0; +reg [13:0] sdcard_core_cmd_command_storage = 14'd0; +reg [2:0] sdcard_core_cmd_count = 3'd0; +reg [2:0] sdcard_core_cmd_count_fsm_next_value2 = 3'd0; +reg sdcard_core_cmd_count_fsm_next_value_ce2 = 1'd0; +reg sdcard_core_cmd_done = 1'd0; +reg sdcard_core_cmd_done_fsm_next_value0 = 1'd0; +reg sdcard_core_cmd_done_fsm_next_value_ce0 = 1'd0; +reg sdcard_core_cmd_error = 1'd0; +reg sdcard_core_cmd_error_fsm_next_value4 = 1'd0; +reg sdcard_core_cmd_error_fsm_next_value_ce4 = 1'd0; +reg sdcard_core_cmd_event_re = 1'd0; +reg [3:0] sdcard_core_cmd_event_status = 4'd0; +wire sdcard_core_cmd_event_we; +reg sdcard_core_cmd_response_re = 1'd0; +reg [127:0] sdcard_core_cmd_response_status = 128'd0; +reg [127:0] sdcard_core_cmd_response_status_fsm_next_value8 = 128'd0; +reg sdcard_core_cmd_response_status_fsm_next_value_ce8 = 1'd0; +wire sdcard_core_cmd_response_we; +reg sdcard_core_cmd_send_re = 1'd0; +reg sdcard_core_cmd_send_storage = 1'd0; +reg sdcard_core_cmd_timeout = 1'd0; +reg sdcard_core_cmd_timeout_fsm_next_value5 = 1'd0; +reg sdcard_core_cmd_timeout_fsm_next_value_ce5 = 1'd0; +wire [1:0] sdcard_core_cmd_type; +reg [2:0] sdcard_core_crc16_inserter_count = 3'd0; +reg [2:0] sdcard_core_crc16_inserter_count_crc16inserter_next_value = 3'd0; +reg sdcard_core_crc16_inserter_count_crc16inserter_next_value_ce = 1'd0; +reg [15:0] sdcard_core_crc16_inserter_crc00 = 16'd0; +wire [15:0] sdcard_core_crc16_inserter_crc01; +wire [15:0] sdcard_core_crc16_inserter_crc02; +reg [15:0] sdcard_core_crc16_inserter_crc0_crc = 16'd0; +reg [1:0] sdcard_core_crc16_inserter_crc0_din = 2'd0; +wire sdcard_core_crc16_inserter_crc0_enable; +wire sdcard_core_crc16_inserter_crc0_reset; +reg [15:0] sdcard_core_crc16_inserter_crc10 = 16'd0; +wire [15:0] sdcard_core_crc16_inserter_crc11; +wire [15:0] sdcard_core_crc16_inserter_crc12; +reg [15:0] sdcard_core_crc16_inserter_crc1_crc = 16'd0; +reg [1:0] sdcard_core_crc16_inserter_crc1_din = 2'd0; +wire sdcard_core_crc16_inserter_crc1_enable; +wire sdcard_core_crc16_inserter_crc1_reset; +reg [15:0] sdcard_core_crc16_inserter_crc20 = 16'd0; +wire [15:0] sdcard_core_crc16_inserter_crc21; +wire [15:0] sdcard_core_crc16_inserter_crc22; +reg [15:0] sdcard_core_crc16_inserter_crc2_crc = 16'd0; +reg [1:0] sdcard_core_crc16_inserter_crc2_din = 2'd0; +wire sdcard_core_crc16_inserter_crc2_enable; +wire sdcard_core_crc16_inserter_crc2_reset; +reg [15:0] sdcard_core_crc16_inserter_crc30 = 16'd0; +wire [15:0] sdcard_core_crc16_inserter_crc31; +wire [15:0] sdcard_core_crc16_inserter_crc32; +reg [15:0] sdcard_core_crc16_inserter_crc3_crc = 16'd0; +reg [1:0] sdcard_core_crc16_inserter_crc3_din = 2'd0; +wire sdcard_core_crc16_inserter_crc3_enable; +wire sdcard_core_crc16_inserter_crc3_reset; +wire sdcard_core_crc16_inserter_sink_first; +wire sdcard_core_crc16_inserter_sink_last; +wire [7:0] sdcard_core_crc16_inserter_sink_payload_data; +reg sdcard_core_crc16_inserter_sink_ready = 1'd0; +wire sdcard_core_crc16_inserter_sink_valid; +reg sdcard_core_crc16_inserter_source_first = 1'd0; +reg sdcard_core_crc16_inserter_source_last = 1'd0; +reg [7:0] sdcard_core_crc16_inserter_source_payload_data = 8'd0; +reg sdcard_core_crc16_inserter_source_ready = 1'd0; +reg sdcard_core_crc16_inserter_source_valid = 1'd0; +reg [6:0] sdcard_core_crc7_inserter_crc0 = 7'd0; +wire [6:0] sdcard_core_crc7_inserter_crc1; +wire [6:0] sdcard_core_crc7_inserter_crc10; +wire [6:0] sdcard_core_crc7_inserter_crc11; +wire [6:0] sdcard_core_crc7_inserter_crc12; +wire [6:0] sdcard_core_crc7_inserter_crc13; +wire [6:0] sdcard_core_crc7_inserter_crc14; +wire [6:0] sdcard_core_crc7_inserter_crc15; +wire [6:0] sdcard_core_crc7_inserter_crc16; +wire [6:0] sdcard_core_crc7_inserter_crc17; +wire [6:0] sdcard_core_crc7_inserter_crc18; +wire [6:0] sdcard_core_crc7_inserter_crc19; +wire [6:0] sdcard_core_crc7_inserter_crc2; +wire [6:0] sdcard_core_crc7_inserter_crc20; +wire [6:0] sdcard_core_crc7_inserter_crc21; +wire [6:0] sdcard_core_crc7_inserter_crc22; +wire [6:0] sdcard_core_crc7_inserter_crc23; +wire [6:0] sdcard_core_crc7_inserter_crc24; +wire [6:0] sdcard_core_crc7_inserter_crc25; +wire [6:0] sdcard_core_crc7_inserter_crc26; +wire [6:0] sdcard_core_crc7_inserter_crc27; +wire [6:0] sdcard_core_crc7_inserter_crc28; +wire [6:0] sdcard_core_crc7_inserter_crc29; +wire [6:0] sdcard_core_crc7_inserter_crc3; +wire [6:0] sdcard_core_crc7_inserter_crc30; +wire [6:0] sdcard_core_crc7_inserter_crc31; +wire [6:0] sdcard_core_crc7_inserter_crc32; +wire [6:0] sdcard_core_crc7_inserter_crc33; +wire [6:0] sdcard_core_crc7_inserter_crc34; +wire [6:0] sdcard_core_crc7_inserter_crc35; +wire [6:0] sdcard_core_crc7_inserter_crc36; +wire [6:0] sdcard_core_crc7_inserter_crc37; +wire [6:0] sdcard_core_crc7_inserter_crc38; +wire [6:0] sdcard_core_crc7_inserter_crc39; +wire [6:0] sdcard_core_crc7_inserter_crc4; +wire [6:0] sdcard_core_crc7_inserter_crc40; +wire [6:0] sdcard_core_crc7_inserter_crc5; +wire [6:0] sdcard_core_crc7_inserter_crc6; +wire [6:0] sdcard_core_crc7_inserter_crc7; +wire [6:0] sdcard_core_crc7_inserter_crc8; +wire [6:0] sdcard_core_crc7_inserter_crc9; +reg [6:0] sdcard_core_crc7_inserter_crc_crc = 7'd0; +wire [39:0] sdcard_core_crc7_inserter_crc_din; +wire sdcard_core_crc7_inserter_crc_enable; +wire sdcard_core_crc7_inserter_crc_reset; +wire [5:0] sdcard_core_csrfield_cmd; +wire [1:0] sdcard_core_csrfield_cmd_type; +wire sdcard_core_csrfield_crc0; +wire sdcard_core_csrfield_crc1; +wire [1:0] sdcard_core_csrfield_data_type; +wire sdcard_core_csrfield_done0; +wire sdcard_core_csrfield_done1; +wire sdcard_core_csrfield_error0; +wire sdcard_core_csrfield_error1; +wire sdcard_core_csrfield_timeout0; +wire sdcard_core_csrfield_timeout1; +reg [31:0] sdcard_core_data_count = 32'd0; +reg [31:0] sdcard_core_data_count_fsm_next_value3 = 32'd0; +reg sdcard_core_data_count_fsm_next_value_ce3 = 1'd0; +reg sdcard_core_data_done = 1'd0; +reg sdcard_core_data_done_fsm_next_value1 = 1'd0; +reg sdcard_core_data_done_fsm_next_value_ce1 = 1'd0; +reg sdcard_core_data_error = 1'd0; +reg sdcard_core_data_error_fsm_next_value6 = 1'd0; +reg sdcard_core_data_error_fsm_next_value_ce6 = 1'd0; +reg sdcard_core_data_event_re = 1'd0; +reg [3:0] sdcard_core_data_event_status = 4'd0; +wire sdcard_core_data_event_we; +reg sdcard_core_data_timeout = 1'd0; +reg sdcard_core_data_timeout_fsm_next_value7 = 1'd0; +reg sdcard_core_data_timeout_fsm_next_value_ce7 = 1'd0; +wire [1:0] sdcard_core_data_type; +reg sdcard_core_done_d = 1'd0; +reg [2:0] sdcard_core_fifo_consume = 3'd0; +wire sdcard_core_fifo_do_read; +wire sdcard_core_fifo_fifo_in_first; +wire sdcard_core_fifo_fifo_in_last; +wire [7:0] sdcard_core_fifo_fifo_in_payload_data; +wire sdcard_core_fifo_fifo_out_first; +wire sdcard_core_fifo_fifo_out_last; +wire [7:0] sdcard_core_fifo_fifo_out_payload_data; +reg [3:0] sdcard_core_fifo_level = 4'd0; +reg [2:0] sdcard_core_fifo_produce = 3'd0; +wire [2:0] sdcard_core_fifo_rdport_adr; +wire [9:0] sdcard_core_fifo_rdport_dat_r; +reg sdcard_core_fifo_replace = 1'd0; +wire sdcard_core_fifo_reset; +wire sdcard_core_fifo_sink_first; +wire sdcard_core_fifo_sink_last; +wire [7:0] sdcard_core_fifo_sink_payload_data; +wire sdcard_core_fifo_sink_ready; +wire sdcard_core_fifo_sink_valid; +wire sdcard_core_fifo_source_first; +wire sdcard_core_fifo_source_last; +wire [7:0] sdcard_core_fifo_source_payload_data; +wire sdcard_core_fifo_source_ready; +wire sdcard_core_fifo_source_valid; +wire [9:0] sdcard_core_fifo_syncfifo_din; +wire [9:0] sdcard_core_fifo_syncfifo_dout; +wire sdcard_core_fifo_syncfifo_re; +wire sdcard_core_fifo_syncfifo_readable; +wire sdcard_core_fifo_syncfifo_we; +wire sdcard_core_fifo_syncfifo_writable; +reg [2:0] sdcard_core_fifo_wrport_adr = 3'd0; +wire [9:0] sdcard_core_fifo_wrport_dat_r; +wire [9:0] sdcard_core_fifo_wrport_dat_w; +wire sdcard_core_fifo_wrport_we; +reg sdcard_core_irq = 1'd0; +wire sdcard_core_sink_sink_first0; +reg sdcard_core_sink_sink_first1 = 1'd0; +wire sdcard_core_sink_sink_last0; +reg sdcard_core_sink_sink_last1 = 1'd0; +wire [7:0] sdcard_core_sink_sink_payload_data0; +reg [7:0] sdcard_core_sink_sink_payload_data1 = 8'd0; +wire sdcard_core_sink_sink_ready0; +wire sdcard_core_sink_sink_ready1; +wire sdcard_core_sink_sink_valid0; +reg sdcard_core_sink_sink_valid1 = 1'd0; +wire sdcard_core_source_source_first0; +wire sdcard_core_source_source_first1; +wire sdcard_core_source_source_last0; +wire sdcard_core_source_source_last1; +wire [7:0] sdcard_core_source_source_payload_data0; +wire [7:0] sdcard_core_source_source_payload_data1; +wire sdcard_core_source_source_ready0; +wire sdcard_core_source_source_ready1; +wire sdcard_core_source_source_valid0; +wire sdcard_core_source_source_valid1; +wire sdcard_irq_irq; +wire sdcard_mem2block_converter_converter_first; +wire sdcard_mem2block_converter_converter_last; +reg [1:0] sdcard_mem2block_converter_converter_mux = 2'd0; +wire sdcard_mem2block_converter_converter_sink_first; +wire sdcard_mem2block_converter_converter_sink_last; +wire [31:0] sdcard_mem2block_converter_converter_sink_payload_data; +wire sdcard_mem2block_converter_converter_sink_ready; +wire sdcard_mem2block_converter_converter_sink_valid; +wire sdcard_mem2block_converter_converter_source_first; +wire sdcard_mem2block_converter_converter_source_last; +reg [7:0] sdcard_mem2block_converter_converter_source_payload_data = 8'd0; +wire sdcard_mem2block_converter_converter_source_payload_valid_token_count; +wire sdcard_mem2block_converter_converter_source_ready; +wire sdcard_mem2block_converter_converter_source_valid; +wire sdcard_mem2block_converter_source_source_first; +wire sdcard_mem2block_converter_source_source_last; +wire [7:0] sdcard_mem2block_converter_source_source_payload_data; +wire sdcard_mem2block_converter_source_source_ready; +wire sdcard_mem2block_converter_source_source_valid; +reg [8:0] sdcard_mem2block_count = 9'd0; +wire [31:0] sdcard_mem2block_dma_base; +reg sdcard_mem2block_dma_base_re = 1'd0; +reg [63:0] sdcard_mem2block_dma_base_storage = 64'd0; +reg sdcard_mem2block_dma_done_re = 1'd0; +reg sdcard_mem2block_dma_done_status = 1'd0; +wire sdcard_mem2block_dma_done_we; +reg sdcard_mem2block_dma_enable_re = 1'd0; +reg sdcard_mem2block_dma_enable_storage = 1'd0; +reg [3:0] sdcard_mem2block_dma_fifo_consume = 4'd0; +wire sdcard_mem2block_dma_fifo_do_read; +wire sdcard_mem2block_dma_fifo_fifo_in_first; +wire sdcard_mem2block_dma_fifo_fifo_in_last; +wire [31:0] sdcard_mem2block_dma_fifo_fifo_in_payload_data; +wire sdcard_mem2block_dma_fifo_fifo_out_first; +wire sdcard_mem2block_dma_fifo_fifo_out_last; +wire [31:0] sdcard_mem2block_dma_fifo_fifo_out_payload_data; +reg [4:0] sdcard_mem2block_dma_fifo_level = 5'd0; +reg [3:0] sdcard_mem2block_dma_fifo_produce = 4'd0; +wire [3:0] sdcard_mem2block_dma_fifo_rdport_adr; +wire [33:0] sdcard_mem2block_dma_fifo_rdport_dat_r; +reg sdcard_mem2block_dma_fifo_replace = 1'd0; +reg sdcard_mem2block_dma_fifo_sink_first = 1'd0; +wire sdcard_mem2block_dma_fifo_sink_last; +wire [31:0] sdcard_mem2block_dma_fifo_sink_payload_data; +wire sdcard_mem2block_dma_fifo_sink_ready; +reg sdcard_mem2block_dma_fifo_sink_valid = 1'd0; +wire sdcard_mem2block_dma_fifo_source_first; +wire sdcard_mem2block_dma_fifo_source_last; +wire [31:0] sdcard_mem2block_dma_fifo_source_payload_data; +wire sdcard_mem2block_dma_fifo_source_ready; +wire sdcard_mem2block_dma_fifo_source_valid; +wire [33:0] sdcard_mem2block_dma_fifo_syncfifo_din; +wire [33:0] sdcard_mem2block_dma_fifo_syncfifo_dout; +wire sdcard_mem2block_dma_fifo_syncfifo_re; +wire sdcard_mem2block_dma_fifo_syncfifo_readable; +wire sdcard_mem2block_dma_fifo_syncfifo_we; +wire sdcard_mem2block_dma_fifo_syncfifo_writable; +reg [3:0] sdcard_mem2block_dma_fifo_wrport_adr = 4'd0; +wire [33:0] sdcard_mem2block_dma_fifo_wrport_dat_r; +wire [33:0] sdcard_mem2block_dma_fifo_wrport_dat_w; +wire sdcard_mem2block_dma_fifo_wrport_we; +wire [31:0] sdcard_mem2block_dma_length; +reg sdcard_mem2block_dma_length_re = 1'd0; +reg [31:0] sdcard_mem2block_dma_length_storage = 32'd0; +reg sdcard_mem2block_dma_loop_re = 1'd0; +reg sdcard_mem2block_dma_loop_storage = 1'd0; +reg [31:0] sdcard_mem2block_dma_offset = 32'd0; +reg sdcard_mem2block_dma_offset_re = 1'd0; +reg [31:0] sdcard_mem2block_dma_offset_sdmem2blockdma_next_value = 32'd0; +reg sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce = 1'd0; +wire [31:0] sdcard_mem2block_dma_offset_status; +wire sdcard_mem2block_dma_offset_we; +wire sdcard_mem2block_dma_reset; +reg sdcard_mem2block_dma_sink_sink_last = 1'd0; +reg [31:0] sdcard_mem2block_dma_sink_sink_payload_address = 32'd0; +reg sdcard_mem2block_dma_sink_sink_ready = 1'd0; +reg sdcard_mem2block_dma_sink_sink_valid = 1'd0; +wire sdcard_mem2block_dma_source_source_first; +wire sdcard_mem2block_dma_source_source_last; +wire [31:0] sdcard_mem2block_dma_source_source_payload_data; +wire sdcard_mem2block_dma_source_source_ready; +wire sdcard_mem2block_dma_source_source_valid; +reg sdcard_mem2block_done_d = 1'd0; +reg [8:0] sdcard_mem2block_fifo_consume = 9'd0; +wire sdcard_mem2block_fifo_do_read; +wire sdcard_mem2block_fifo_fifo_in_first; +wire sdcard_mem2block_fifo_fifo_in_last; +wire [7:0] sdcard_mem2block_fifo_fifo_in_payload_data; +wire sdcard_mem2block_fifo_fifo_out_first; +wire sdcard_mem2block_fifo_fifo_out_last; +wire [7:0] sdcard_mem2block_fifo_fifo_out_payload_data; +reg [9:0] sdcard_mem2block_fifo_level0 = 10'd0; +wire [9:0] sdcard_mem2block_fifo_level1; +reg [8:0] sdcard_mem2block_fifo_produce = 9'd0; +wire [8:0] sdcard_mem2block_fifo_rdport_adr; +wire [9:0] sdcard_mem2block_fifo_rdport_dat_r; +wire sdcard_mem2block_fifo_rdport_re; +wire sdcard_mem2block_fifo_re; +reg sdcard_mem2block_fifo_readable = 1'd0; +reg sdcard_mem2block_fifo_replace = 1'd0; +wire sdcard_mem2block_fifo_sink_first; +wire sdcard_mem2block_fifo_sink_last; +wire [7:0] sdcard_mem2block_fifo_sink_payload_data; +wire sdcard_mem2block_fifo_sink_ready; +wire sdcard_mem2block_fifo_sink_valid; +wire sdcard_mem2block_fifo_source_first; +wire sdcard_mem2block_fifo_source_last; +wire [7:0] sdcard_mem2block_fifo_source_payload_data; +wire sdcard_mem2block_fifo_source_ready; +wire sdcard_mem2block_fifo_source_valid; +wire [9:0] sdcard_mem2block_fifo_syncfifo_din; +wire [9:0] sdcard_mem2block_fifo_syncfifo_dout; +wire sdcard_mem2block_fifo_syncfifo_re; +wire sdcard_mem2block_fifo_syncfifo_readable; +wire sdcard_mem2block_fifo_syncfifo_we; +wire sdcard_mem2block_fifo_syncfifo_writable; +reg [8:0] sdcard_mem2block_fifo_wrport_adr = 9'd0; +wire [9:0] sdcard_mem2block_fifo_wrport_dat_r; +wire [9:0] sdcard_mem2block_fifo_wrport_dat_w; +wire sdcard_mem2block_fifo_wrport_we; +reg sdcard_mem2block_irq = 1'd0; +wire sdcard_mem2block_source_source_first; +reg sdcard_mem2block_source_source_last = 1'd0; +wire [7:0] sdcard_mem2block_source_source_payload_data; +wire sdcard_mem2block_source_source_ready; +wire sdcard_mem2block_source_source_valid; +reg [1:0] sdmem2blockdma_next_state = 2'd0; +reg [1:0] sdmem2blockdma_state = 2'd0; +wire sdpads_clk; +wire sdpads_cmd_i; +wire sdpads_cmd_o; +wire sdpads_cmd_oe; +wire [3:0] sdpads_data_i; +reg sdpads_data_i_ce = 1'd0; +wire [3:0] sdpads_data_o; +wire sdpads_data_oe; +reg [2:0] sdphycmdr_next_state = 3'd0; +reg [2:0] sdphycmdr_state = 3'd0; +reg [1:0] sdphycmdw_next_state = 2'd0; +reg [1:0] sdphycmdw_state = 2'd0; +reg [2:0] sdphydatar_next_state = 3'd0; +reg [2:0] sdphydatar_state = 3'd0; +reg [2:0] sdphydataw_next_state = 3'd0; +reg [2:0] sdphydataw_state = 3'd0; +reg sdphyinit_next_state = 1'd0; +reg sdphyinit_state = 1'd0; +wire sdrio_clk; +wire sdrio_clk_1; +wire sdrio_clk_2; +wire sdrio_clk_3; +wire sdrio_clk_4; +reg [31:0] self0 = 32'd0; +reg [31:0] self1 = 32'd0; +reg [3:0] self2 = 4'd0; +reg self3 = 1'd0; +reg self4 = 1'd0; +reg self5 = 1'd0; +reg [2:0] self6 = 3'd0; +reg [1:0] self7 = 2'd0; +reg shared_ack = 1'd0; +wire [31:0] shared_adr; +wire [1:0] shared_bte; +wire [2:0] shared_cti; +wire shared_cyc; +reg [31:0] shared_dat_r = 32'd0; +wire [31:0] shared_dat_w; +wire shared_err; +wire [3:0] shared_sel; +wire shared_stb; +wire shared_we; +reg slave_sel = 1'd0; +reg slave_sel_r = 1'd0; +reg soc_rst = 1'd0; +wire sys_clk; +wire sys_rst; +wire wait_1; +wire wb_ctrl_ack_1; +wire [29:0] wb_ctrl_adr_1; +wire [1:0] wb_ctrl_bte_1; +wire [2:0] wb_ctrl_cti_1; +wire wb_ctrl_cyc_1; +wire [31:0] wb_ctrl_dat_r_1; +wire [31:0] wb_ctrl_dat_w_1; +wire wb_ctrl_err_1; +wire [3:0] wb_ctrl_sel_1; +wire wb_ctrl_stb_1; +wire wb_ctrl_we_1; +wire wb_dma_ack_1; +wire [29:0] wb_dma_adr_1; +wire [1:0] wb_dma_bte_1; +wire [2:0] wb_dma_cti_1; +wire wb_dma_cyc_1; +wire [31:0] wb_dma_dat_r_1; +wire [31:0] wb_dma_dat_w_1; +wire wb_dma_err_1; +wire [3:0] wb_dma_sel_1; +wire wb_dma_stb_1; +wire wb_dma_we_1; +wire we; +reg wishbone2csr_next_state = 1'd0; +reg wishbone2csr_state = 1'd0; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + +assign wb_ctrl_adr_1 = wb_ctrl_adr; +assign wb_ctrl_dat_w_1 = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = wb_ctrl_dat_r_1; +assign wb_ctrl_sel_1 = wb_ctrl_sel; +assign wb_ctrl_cyc_1 = wb_ctrl_cyc; +assign wb_ctrl_stb_1 = wb_ctrl_stb; +assign wb_ctrl_ack = wb_ctrl_ack_1; +assign wb_ctrl_we_1 = wb_ctrl_we; +assign wb_ctrl_cti_1 = wb_ctrl_cti; +assign wb_ctrl_bte_1 = wb_ctrl_bte; +assign wb_ctrl_err = wb_ctrl_err_1; +assign wb_dma_adr = wb_dma_adr_1; +assign wb_dma_dat_w = wb_dma_dat_w_1; +assign wb_dma_dat_r_1 = wb_dma_dat_r; +assign wb_dma_sel = wb_dma_sel_1; +assign wb_dma_cyc = wb_dma_cyc_1; +assign wb_dma_stb = wb_dma_stb_1; +assign wb_dma_ack_1 = wb_dma_ack; +assign wb_dma_we = wb_dma_we_1; +assign wb_dma_cti = wb_dma_cti_1; +assign wb_dma_bte = wb_dma_bte_1; +assign wb_dma_err_1 = wb_dma_err; +assign sdcard_block2mem_sink_sink_valid0 = sdcard_core_source_source_valid0; +assign sdcard_core_source_source_ready0 = sdcard_block2mem_sink_sink_ready0; +assign sdcard_block2mem_sink_sink_first = sdcard_core_source_source_first0; +assign sdcard_block2mem_sink_sink_last0 = sdcard_core_source_source_last0; +assign sdcard_block2mem_sink_sink_payload_data0 = sdcard_core_source_source_payload_data0; +assign sdcard_core_sink_sink_valid0 = sdcard_mem2block_source_source_valid; +assign sdcard_mem2block_source_source_ready = sdcard_core_sink_sink_ready0; +assign sdcard_core_sink_sink_first0 = sdcard_mem2block_source_source_first; +assign sdcard_core_sink_sink_last0 = sdcard_mem2block_source_source_last; +assign sdcard_core_sink_sink_payload_data0 = sdcard_mem2block_source_source_payload_data; +assign block2mem_dma_trigger = sdcard_block2mem_irq; +assign mem2block_dma_trigger = sdcard_mem2block_irq; +assign card_detect_trigger = card_detect_irq; +assign cmd_done_trigger = sdcard_core_csrfield_done0; +assign irq = sdcard_irq_irq; +assign sys_clk = clk; +assign por_clk = clk; +assign sys_rst = int_rst; +assign interface0_adr = wb_ctrl_adr_1; +assign interface0_dat_w = wb_ctrl_dat_w_1; +assign wb_ctrl_dat_r_1 = interface0_dat_r; +assign interface0_sel = wb_ctrl_sel_1; +assign interface0_cyc = wb_ctrl_cyc_1; +assign interface0_stb = wb_ctrl_stb_1; +assign wb_ctrl_ack_1 = interface0_ack; +assign interface0_we = wb_ctrl_we_1; +assign interface0_cti = wb_ctrl_cti_1; +assign interface0_bte = wb_ctrl_bte_1; +assign wb_ctrl_err_1 = interface0_err; +assign bus_errors_status = bus_errors; +assign shared_adr = self0; +assign shared_dat_w = self1; +assign shared_sel = self2; +assign shared_cyc = self3; +assign shared_stb = self4; +assign shared_we = self5; +assign shared_cti = self6; +assign shared_bte = self7; +assign interface0_bus_dat_r = shared_dat_r; +assign interface1_bus_dat_r = shared_dat_r; +assign interface0_bus_ack = (shared_ack & (grant == 1'd0)); +assign interface1_bus_ack = (shared_ack & (grant == 1'd1)); +assign interface0_bus_err = (shared_err & (grant == 1'd0)); +assign interface1_bus_err = (shared_err & (grant == 1'd1)); +assign request = {interface1_bus_cyc, interface0_bus_cyc}; +always @(*) begin + slave_sel <= 1'd0; + slave_sel <= 1'd1; +end +assign wb_dma_adr_1 = shared_adr; +assign wb_dma_dat_w_1 = shared_dat_w; +assign wb_dma_sel_1 = shared_sel; +assign wb_dma_stb_1 = shared_stb; +assign wb_dma_we_1 = shared_we; +assign wb_dma_cti_1 = shared_cti; +assign wb_dma_bte_1 = shared_bte; +assign wb_dma_cyc_1 = (shared_cyc & slave_sel); +assign shared_err = wb_dma_err_1; +assign wait_1 = ((shared_stb & shared_cyc) & (~shared_ack)); +always @(*) begin + error <= 1'd0; + shared_ack <= 1'd0; + shared_dat_r <= 32'd0; + shared_ack <= wb_dma_ack_1; + shared_dat_r <= ({32{slave_sel_r}} & wb_dma_dat_r_1); + if (done) begin + shared_dat_r <= 32'd4294967295; + shared_ack <= 1'd1; + error <= 1'd1; + end +end +assign done = (count == 1'd0); +assign card_detect_status0 = sdcard_cd; +assign sdpads_clk = ((((init_pads_out_payload_clk | cmdw_pads_out_payload_clk) | cmdr_pads_out_payload_clk) | dataw_pads_out_payload_clk) | datar_pads_out_payload_clk); +assign sdpads_cmd_oe = ((((init_pads_out_payload_cmd_oe | cmdw_pads_out_payload_cmd_oe) | cmdr_pads_out_payload_cmd_oe) | dataw_pads_out_payload_cmd_oe) | datar_pads_out_payload_cmd_oe); +assign sdpads_cmd_o = ((((init_pads_out_payload_cmd_o | cmdw_pads_out_payload_cmd_o) | cmdr_pads_out_payload_cmd_o) | dataw_pads_out_payload_cmd_o) | datar_pads_out_payload_cmd_o); +assign sdpads_data_oe = ((((init_pads_out_payload_data_oe | cmdw_pads_out_payload_data_oe) | cmdr_pads_out_payload_data_oe) | dataw_pads_out_payload_data_oe) | datar_pads_out_payload_data_oe); +assign sdpads_data_o = ((((init_pads_out_payload_data_o | cmdw_pads_out_payload_data_o) | cmdr_pads_out_payload_data_o) | dataw_pads_out_payload_data_o) | datar_pads_out_payload_data_o); +assign init_pads_out_ready = clocker_ce; +assign cmdw_pads_out_ready = clocker_ce; +assign cmdr_pads_out_ready = clocker_ce; +assign dataw_pads_out_ready = clocker_ce; +assign datar_pads_out_ready = clocker_ce; +assign clocker_clk_en = sdpads_clk; +assign init_pads_in_valid = sdpads_data_i_ce; +assign init_pads_in_payload_cmd_i = sdpads_cmd_i; +assign init_pads_in_payload_data_i = sdpads_data_i; +assign cmdw_pads_in_valid = sdpads_data_i_ce; +assign cmdw_pads_in_payload_cmd_i = sdpads_cmd_i; +assign cmdw_pads_in_payload_data_i = sdpads_data_i; +assign cmdr_pads_in_pads_in_valid = sdpads_data_i_ce; +assign cmdr_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; +assign cmdr_pads_in_pads_in_payload_data_i = sdpads_data_i; +assign dataw_pads_in_pads_in_valid = sdpads_data_i_ce; +assign dataw_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; +assign dataw_pads_in_pads_in_payload_data_i = sdpads_data_i; +assign datar_pads_in_pads_in_valid = sdpads_data_i_ce; +assign datar_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; +assign datar_pads_in_pads_in_payload_data_i = sdpads_data_i; +assign clocker_stop = (dataw_stop | datar_stop); +always @(*) begin + clocker_clk1 <= 1'd0; + case (clocker_storage) + 3'd4: begin + clocker_clk1 <= clocker_clks[1]; + end + 4'd8: begin + clocker_clk1 <= clocker_clks[2]; + end + 5'd16: begin + clocker_clk1 <= clocker_clks[3]; + end + 6'd32: begin + clocker_clk1 <= clocker_clks[4]; + end + 7'd64: begin + clocker_clk1 <= clocker_clks[5]; + end + 8'd128: begin + clocker_clk1 <= clocker_clks[6]; + end + 9'd256: begin + clocker_clk1 <= clocker_clks[7]; + end + default: begin + clocker_clk1 <= clocker_clks[0]; + end + endcase +end +assign clocker_ce = (clocker_clk1 & (~clocker_clk_d)); +always @(*) begin + clocker_ce_latched <= 1'd0; + if (clocker_clk_d) begin + clocker_ce_latched <= clocker_clk_en; + end else begin + clocker_ce_latched <= clocker_ce_delayed; + end +end +assign clocker_clk0 = ((~clocker_clk1) & clocker_ce_latched); +always @(*) begin + init_count_sdphyinit_next_value <= 8'd0; + init_count_sdphyinit_next_value_ce <= 1'd0; + init_pads_out_payload_clk <= 1'd0; + init_pads_out_payload_cmd_o <= 1'd0; + init_pads_out_payload_cmd_oe <= 1'd0; + init_pads_out_payload_data_o <= 4'd0; + init_pads_out_payload_data_oe <= 1'd0; + sdphyinit_next_state <= 1'd0; + sdphyinit_next_state <= sdphyinit_state; + case (sdphyinit_state) + 1'd1: begin + init_pads_out_payload_clk <= 1'd1; + init_pads_out_payload_cmd_oe <= 1'd1; + init_pads_out_payload_cmd_o <= 1'd1; + init_pads_out_payload_data_oe <= 1'd1; + init_pads_out_payload_data_o <= 4'd15; + if (init_pads_out_ready) begin + init_count_sdphyinit_next_value <= (init_count + 1'd1); + init_count_sdphyinit_next_value_ce <= 1'd1; + if ((init_count == 7'd79)) begin + sdphyinit_next_state <= 1'd0; + end + end + end + default: begin + init_count_sdphyinit_next_value <= 1'd0; + init_count_sdphyinit_next_value_ce <= 1'd1; + if (init_initialize_re) begin + sdphyinit_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + cmdw_count_sdphycmdw_next_value <= 8'd0; + cmdw_count_sdphycmdw_next_value_ce <= 1'd0; + cmdw_done <= 1'd0; + cmdw_pads_out_payload_clk <= 1'd0; + cmdw_pads_out_payload_cmd_o <= 1'd0; + cmdw_pads_out_payload_cmd_oe <= 1'd0; + cmdw_sink_ready <= 1'd0; + sdphycmdw_next_state <= 2'd0; + sdphycmdw_next_state <= sdphycmdw_state; + case (sdphycmdw_state) + 1'd1: begin + cmdw_pads_out_payload_clk <= 1'd1; + cmdw_pads_out_payload_cmd_oe <= 1'd1; + case (cmdw_count) + 1'd0: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[7]; + end + 1'd1: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[6]; + end + 2'd2: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[5]; + end + 2'd3: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[4]; + end + 3'd4: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[3]; + end + 3'd5: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[2]; + end + 3'd6: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[1]; + end + 3'd7: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[0]; + end + endcase + if (cmdw_pads_out_ready) begin + cmdw_count_sdphycmdw_next_value <= (cmdw_count + 1'd1); + cmdw_count_sdphycmdw_next_value_ce <= 1'd1; + if ((cmdw_count == 3'd7)) begin + if ((cmdw_sink_last & (cmdw_sink_payload_cmd_type == 1'd0))) begin + sdphycmdw_next_state <= 2'd2; + end else begin + cmdw_sink_ready <= 1'd1; + sdphycmdw_next_state <= 1'd0; + end + end + end + end + 2'd2: begin + cmdw_pads_out_payload_clk <= 1'd1; + cmdw_pads_out_payload_cmd_oe <= 1'd1; + cmdw_pads_out_payload_cmd_o <= 1'd1; + if (cmdw_pads_out_ready) begin + cmdw_count_sdphycmdw_next_value <= (cmdw_count + 1'd1); + cmdw_count_sdphycmdw_next_value_ce <= 1'd1; + if ((cmdw_count == 3'd7)) begin + cmdw_sink_ready <= 1'd1; + sdphycmdw_next_state <= 1'd0; + end + end + end + default: begin + cmdw_count_sdphycmdw_next_value <= 1'd0; + cmdw_count_sdphycmdw_next_value_ce <= 1'd1; + if ((cmdw_sink_valid & cmdw_pads_out_ready)) begin + sdphycmdw_next_state <= 1'd1; + end else begin + cmdw_done <= 1'd1; + end + end + endcase +end +assign cmdr_cmdr_pads_in_valid = cmdr_pads_in_pads_in_valid; +assign cmdr_pads_in_pads_in_ready = cmdr_cmdr_pads_in_ready; +assign cmdr_cmdr_pads_in_first = cmdr_pads_in_pads_in_first; +assign cmdr_cmdr_pads_in_last = cmdr_pads_in_pads_in_last; +assign cmdr_cmdr_pads_in_payload_clk = cmdr_pads_in_pads_in_payload_clk; +assign cmdr_cmdr_pads_in_payload_cmd_i = cmdr_pads_in_pads_in_payload_cmd_i; +assign cmdr_cmdr_pads_in_payload_cmd_o = cmdr_pads_in_pads_in_payload_cmd_o; +assign cmdr_cmdr_pads_in_payload_cmd_oe = cmdr_pads_in_pads_in_payload_cmd_oe; +assign cmdr_cmdr_pads_in_payload_data_i = cmdr_pads_in_pads_in_payload_data_i; +assign cmdr_cmdr_pads_in_payload_data_o = cmdr_pads_in_pads_in_payload_data_o; +assign cmdr_cmdr_pads_in_payload_data_oe = cmdr_pads_in_pads_in_payload_data_oe; +assign cmdr_cmdr_pads_in_payload_data_i_ce = cmdr_pads_in_pads_in_payload_data_i_ce; +assign cmdr_cmdr_start = (cmdr_cmdr_pads_in_payload_cmd_i == 1'd0); +assign cmdr_cmdr_converter_converter_sink_valid = (cmdr_cmdr_pads_in_valid & (cmdr_cmdr_start | cmdr_cmdr_run)); +assign cmdr_cmdr_converter_converter_sink_payload_data = cmdr_cmdr_pads_in_payload_cmd_i; +assign cmdr_cmdr_buf_sink_sink_valid = cmdr_cmdr_converter_source_source_valid; +assign cmdr_cmdr_converter_source_source_ready = cmdr_cmdr_buf_sink_sink_ready; +assign cmdr_cmdr_buf_sink_sink_first = cmdr_cmdr_converter_source_source_first; +assign cmdr_cmdr_buf_sink_sink_last = cmdr_cmdr_converter_source_source_last; +assign cmdr_cmdr_buf_sink_sink_payload_data = cmdr_cmdr_converter_source_source_payload_data; +assign cmdr_cmdr_source_valid = cmdr_cmdr_buf_source_source_valid; +assign cmdr_cmdr_buf_source_source_ready = cmdr_cmdr_source_ready; +assign cmdr_cmdr_source_first = cmdr_cmdr_buf_source_source_first; +assign cmdr_cmdr_source_last = cmdr_cmdr_buf_source_source_last; +assign cmdr_cmdr_source_payload_data = cmdr_cmdr_buf_source_source_payload_data; +assign cmdr_cmdr_converter_source_source_valid = cmdr_cmdr_converter_converter_source_valid; +assign cmdr_cmdr_converter_converter_source_ready = cmdr_cmdr_converter_source_source_ready; +assign cmdr_cmdr_converter_source_source_first = cmdr_cmdr_converter_converter_source_first; +assign cmdr_cmdr_converter_source_source_last = cmdr_cmdr_converter_converter_source_last; +assign cmdr_cmdr_converter_source_source_payload_data = cmdr_cmdr_converter_converter_source_payload_data; +assign cmdr_cmdr_converter_converter_sink_ready = ((~cmdr_cmdr_converter_converter_strobe_all) | cmdr_cmdr_converter_converter_source_ready); +assign cmdr_cmdr_converter_converter_source_valid = cmdr_cmdr_converter_converter_strobe_all; +assign cmdr_cmdr_converter_converter_load_part = (cmdr_cmdr_converter_converter_sink_valid & cmdr_cmdr_converter_converter_sink_ready); +assign cmdr_cmdr_buf_pipe_valid_sink_ready = ((~cmdr_cmdr_buf_pipe_valid_source_valid) | cmdr_cmdr_buf_pipe_valid_source_ready); +assign cmdr_cmdr_buf_pipe_valid_sink_valid = cmdr_cmdr_buf_sink_sink_valid; +assign cmdr_cmdr_buf_sink_sink_ready = cmdr_cmdr_buf_pipe_valid_sink_ready; +assign cmdr_cmdr_buf_pipe_valid_sink_first = cmdr_cmdr_buf_sink_sink_first; +assign cmdr_cmdr_buf_pipe_valid_sink_last = cmdr_cmdr_buf_sink_sink_last; +assign cmdr_cmdr_buf_pipe_valid_sink_payload_data = cmdr_cmdr_buf_sink_sink_payload_data; +assign cmdr_cmdr_buf_source_source_valid = cmdr_cmdr_buf_pipe_valid_source_valid; +assign cmdr_cmdr_buf_pipe_valid_source_ready = cmdr_cmdr_buf_source_source_ready; +assign cmdr_cmdr_buf_source_source_first = cmdr_cmdr_buf_pipe_valid_source_first; +assign cmdr_cmdr_buf_source_source_last = cmdr_cmdr_buf_pipe_valid_source_last; +assign cmdr_cmdr_buf_source_source_payload_data = cmdr_cmdr_buf_pipe_valid_source_payload_data; +always @(*) begin + cmdr_busy_sdphycmdr_next_value2 <= 1'd0; + cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd0; + cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd0; + cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd0; + cmdr_cmdr_source_ready <= 1'd0; + cmdr_count_sdphycmdr_next_value1 <= 8'd0; + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd0; + cmdr_pads_out_payload_clk <= 1'd0; + cmdr_pads_out_payload_cmd_o <= 1'd0; + cmdr_pads_out_payload_cmd_oe <= 1'd0; + cmdr_sink_ready <= 1'd0; + cmdr_source_source_last <= 1'd0; + cmdr_source_source_payload_data <= 8'd0; + cmdr_source_source_payload_status <= 3'd0; + cmdr_source_source_valid <= 1'd0; + cmdr_timeout_sdphycmdr_next_value0 <= 32'd0; + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd0; + sdphycmdr_next_state <= 3'd0; + sdphycmdr_next_state <= sdphycmdr_state; + case (sdphycmdr_state) + 1'd1: begin + cmdr_pads_out_payload_clk <= 1'd1; + cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd0; + cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd1; + if (cmdr_cmdr_source_valid) begin + sdphycmdr_next_state <= 2'd2; + end + cmdr_timeout_sdphycmdr_next_value0 <= (cmdr_timeout - 1'd1); + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + if ((cmdr_timeout == 1'd0)) begin + sdphycmdr_next_state <= 3'd5; + end + end + 2'd2: begin + cmdr_pads_out_payload_clk <= 1'd1; + cmdr_source_source_valid <= cmdr_cmdr_source_valid; + cmdr_source_source_payload_status <= 1'd0; + cmdr_source_source_last <= (cmdr_count == (cmdr_sink_payload_length - 1'd1)); + cmdr_source_source_payload_data <= cmdr_cmdr_source_payload_data; + if ((cmdr_cmdr_source_valid & cmdr_source_source_ready)) begin + cmdr_cmdr_source_ready <= 1'd1; + cmdr_count_sdphycmdr_next_value1 <= (cmdr_count + 1'd1); + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + if (cmdr_source_source_last) begin + cmdr_sink_ready <= 1'd1; + if ((cmdr_sink_payload_cmd_type == 2'd3)) begin + cmdr_source_source_valid <= 1'd0; + cmdr_timeout_sdphycmdr_next_value0 <= 26'd48000000; + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + sdphycmdr_next_state <= 2'd3; + end else begin + if ((cmdr_sink_payload_data_type == 1'd0)) begin + cmdr_count_sdphycmdr_next_value1 <= 1'd0; + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + sdphycmdr_next_state <= 3'd4; + end else begin + sdphycmdr_next_state <= 1'd0; + end + end + end + end + cmdr_timeout_sdphycmdr_next_value0 <= (cmdr_timeout - 1'd1); + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + if ((cmdr_timeout == 1'd0)) begin + sdphycmdr_next_state <= 3'd5; + end + end + 2'd3: begin + cmdr_pads_out_payload_clk <= 1'd1; + if ((cmdr_pads_in_pads_in_valid & cmdr_pads_in_pads_in_payload_data_i[0])) begin + cmdr_busy_sdphycmdr_next_value2 <= 1'd0; + cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd1; + end + if ((~cmdr_busy)) begin + cmdr_source_source_valid <= 1'd1; + cmdr_source_source_last <= 1'd1; + cmdr_source_source_payload_status <= 1'd0; + if (cmdr_source_source_ready) begin + cmdr_count_sdphycmdr_next_value1 <= 1'd0; + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + sdphycmdr_next_state <= 3'd4; + end + end + cmdr_timeout_sdphycmdr_next_value0 <= (cmdr_timeout - 1'd1); + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + if ((cmdr_timeout == 1'd0)) begin + sdphycmdr_next_state <= 3'd5; + end + end + 3'd4: begin + cmdr_pads_out_payload_clk <= 1'd1; + cmdr_pads_out_payload_cmd_oe <= 1'd1; + cmdr_pads_out_payload_cmd_o <= 1'd1; + if (cmdr_pads_out_ready) begin + cmdr_count_sdphycmdr_next_value1 <= (cmdr_count + 1'd1); + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + if ((cmdr_count == 3'd7)) begin + sdphycmdr_next_state <= 1'd0; + end + end + end + 3'd5: begin + cmdr_sink_ready <= 1'd1; + cmdr_source_source_valid <= 1'd1; + cmdr_source_source_last <= 1'd1; + cmdr_source_source_payload_status <= 1'd1; + if (cmdr_source_source_ready) begin + sdphycmdr_next_state <= 1'd0; + end + end + default: begin + cmdr_timeout_sdphycmdr_next_value0 <= 26'd48000000; + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + cmdr_count_sdphycmdr_next_value1 <= 1'd0; + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + cmdr_busy_sdphycmdr_next_value2 <= 1'd1; + cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd1; + if (((cmdr_sink_valid & cmdr_pads_out_ready) & cmdw_done)) begin + cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd1; + cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd1; + sdphycmdr_next_state <= 1'd1; + end + end + endcase +end +assign dataw_accepted0 = dataw_accepted1; +assign dataw_crc_error0 = dataw_crc_error1; +assign dataw_write_error0 = dataw_write_error1; +assign dataw_crc_pads_in_valid = dataw_pads_in_pads_in_valid; +assign dataw_crc_pads_in_ready = dataw_pads_in_pads_in_ready; +assign dataw_crc_pads_in_first = dataw_pads_in_pads_in_first; +assign dataw_crc_pads_in_last = dataw_pads_in_pads_in_last; +assign dataw_crc_pads_in_payload_clk = dataw_pads_in_pads_in_payload_clk; +assign dataw_crc_pads_in_payload_cmd_i = dataw_pads_in_pads_in_payload_cmd_i; +assign dataw_crc_pads_in_payload_cmd_o = dataw_pads_in_pads_in_payload_cmd_o; +assign dataw_crc_pads_in_payload_cmd_oe = dataw_pads_in_pads_in_payload_cmd_oe; +assign dataw_crc_pads_in_payload_data_i = dataw_pads_in_pads_in_payload_data_i; +assign dataw_crc_pads_in_payload_data_o = dataw_pads_in_pads_in_payload_data_o; +assign dataw_crc_pads_in_payload_data_oe = dataw_pads_in_pads_in_payload_data_oe; +assign dataw_crc_pads_in_payload_data_i_ce = dataw_pads_in_pads_in_payload_data_i_ce; +assign dataw_crc_start = (dataw_crc_pads_in_payload_data_i[0] == 1'd0); +assign dataw_crc_converter_converter_sink_valid = (dataw_crc_pads_in_valid & dataw_crc_run); +assign dataw_crc_converter_converter_sink_payload_data = dataw_crc_pads_in_payload_data_i[0]; +assign dataw_crc_buf_sink_sink_valid = dataw_crc_converter_source_source_valid; +assign dataw_crc_converter_source_source_ready = dataw_crc_buf_sink_sink_ready; +assign dataw_crc_buf_sink_sink_first = dataw_crc_converter_source_source_first; +assign dataw_crc_buf_sink_sink_last = dataw_crc_converter_source_source_last; +assign dataw_crc_buf_sink_sink_payload_data = dataw_crc_converter_source_source_payload_data; +assign dataw_crc_source_valid = dataw_crc_buf_source_source_valid; +assign dataw_crc_buf_source_source_ready = dataw_crc_source_ready; +assign dataw_crc_source_first = dataw_crc_buf_source_source_first; +assign dataw_crc_source_last = dataw_crc_buf_source_source_last; +assign dataw_crc_source_payload_data = dataw_crc_buf_source_source_payload_data; +assign dataw_crc_converter_source_source_valid = dataw_crc_converter_converter_source_valid; +assign dataw_crc_converter_converter_source_ready = dataw_crc_converter_source_source_ready; +assign dataw_crc_converter_source_source_first = dataw_crc_converter_converter_source_first; +assign dataw_crc_converter_source_source_last = dataw_crc_converter_converter_source_last; +assign dataw_crc_converter_source_source_payload_data = dataw_crc_converter_converter_source_payload_data; +assign dataw_crc_converter_converter_sink_ready = ((~dataw_crc_converter_converter_strobe_all) | dataw_crc_converter_converter_source_ready); +assign dataw_crc_converter_converter_source_valid = dataw_crc_converter_converter_strobe_all; +assign dataw_crc_converter_converter_load_part = (dataw_crc_converter_converter_sink_valid & dataw_crc_converter_converter_sink_ready); +assign dataw_crc_buf_pipe_valid_sink_ready = ((~dataw_crc_buf_pipe_valid_source_valid) | dataw_crc_buf_pipe_valid_source_ready); +assign dataw_crc_buf_pipe_valid_sink_valid = dataw_crc_buf_sink_sink_valid; +assign dataw_crc_buf_sink_sink_ready = dataw_crc_buf_pipe_valid_sink_ready; +assign dataw_crc_buf_pipe_valid_sink_first = dataw_crc_buf_sink_sink_first; +assign dataw_crc_buf_pipe_valid_sink_last = dataw_crc_buf_sink_sink_last; +assign dataw_crc_buf_pipe_valid_sink_payload_data = dataw_crc_buf_sink_sink_payload_data; +assign dataw_crc_buf_source_source_valid = dataw_crc_buf_pipe_valid_source_valid; +assign dataw_crc_buf_pipe_valid_source_ready = dataw_crc_buf_source_source_ready; +assign dataw_crc_buf_source_source_first = dataw_crc_buf_pipe_valid_source_first; +assign dataw_crc_buf_source_source_last = dataw_crc_buf_pipe_valid_source_last; +assign dataw_crc_buf_source_source_payload_data = dataw_crc_buf_pipe_valid_source_payload_data; +always @(*) begin + dataw_accepted1_sdphydataw_next_value0 <= 1'd0; + dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd0; + dataw_count_sdphydataw_next_value3 <= 8'd0; + dataw_count_sdphydataw_next_value_ce3 <= 1'd0; + dataw_crc_error1_sdphydataw_next_value1 <= 1'd0; + dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd0; + dataw_crc_reset <= 1'd0; + dataw_pads_out_payload_clk <= 1'd0; + dataw_pads_out_payload_cmd_o <= 1'd0; + dataw_pads_out_payload_cmd_oe <= 1'd0; + dataw_pads_out_payload_data_o <= 4'd0; + dataw_pads_out_payload_data_oe <= 1'd0; + dataw_sink_ready <= 1'd0; + dataw_stop <= 1'd0; + dataw_write_error1_sdphydataw_next_value2 <= 1'd0; + dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd0; + sdphydataw_next_state <= 3'd0; + sdphydataw_next_state <= sdphydataw_state; + case (sdphydataw_state) + 1'd1: begin + dataw_pads_out_payload_clk <= 1'd1; + dataw_pads_out_payload_cmd_oe <= 1'd1; + dataw_pads_out_payload_cmd_o <= 1'd1; + if (dataw_pads_out_ready) begin + dataw_count_sdphydataw_next_value3 <= (dataw_count + 1'd1); + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + if ((dataw_count == 3'd7)) begin + dataw_count_sdphydataw_next_value3 <= 1'd0; + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + sdphydataw_next_state <= 2'd2; + end + end + end + 2'd2: begin + dataw_pads_out_payload_clk <= 1'd1; + dataw_pads_out_payload_data_oe <= 1'd1; + dataw_pads_out_payload_data_o <= 1'd0; + if (dataw_pads_out_ready) begin + sdphydataw_next_state <= 2'd3; + end + end + 2'd3: begin + dataw_stop <= (~dataw_sink_valid); + dataw_pads_out_payload_clk <= 1'd1; + dataw_pads_out_payload_data_oe <= 1'd1; + case (dataw_count) + 1'd0: begin + dataw_pads_out_payload_data_o <= dataw_sink_payload_data[7:4]; + end + 1'd1: begin + dataw_pads_out_payload_data_o <= dataw_sink_payload_data[3:0]; + end + endcase + if (dataw_pads_out_ready) begin + dataw_count_sdphydataw_next_value3 <= (dataw_count + 1'd1); + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + if ((dataw_count == 1'd1)) begin + dataw_count_sdphydataw_next_value3 <= 1'd0; + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + if (dataw_sink_last) begin + sdphydataw_next_state <= 3'd4; + end else begin + dataw_sink_ready <= 1'd1; + end + end + end + end + 3'd4: begin + dataw_pads_out_payload_clk <= 1'd1; + dataw_pads_out_payload_data_oe <= 1'd1; + dataw_pads_out_payload_data_o <= 4'd15; + if (dataw_pads_out_ready) begin + dataw_crc_reset <= 1'd1; + sdphydataw_next_state <= 3'd5; + end + end + 3'd5: begin + dataw_pads_out_payload_clk <= 1'd1; + if (dataw_crc_source_valid) begin + dataw_accepted1_sdphydataw_next_value0 <= (dataw_crc_source_payload_data[7:5] == 2'd2); + dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd1; + dataw_crc_error1_sdphydataw_next_value1 <= (dataw_crc_source_payload_data[7:5] == 3'd5); + dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd1; + dataw_write_error1_sdphydataw_next_value2 <= (dataw_crc_source_payload_data[7:5] == 3'd6); + dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd1; + sdphydataw_next_state <= 3'd6; + end + end + 3'd6: begin + dataw_pads_out_payload_clk <= 1'd1; + if ((dataw_pads_in_pads_in_valid & dataw_pads_in_pads_in_payload_data_i[0])) begin + dataw_sink_ready <= 1'd1; + sdphydataw_next_state <= 1'd0; + end + end + default: begin + dataw_accepted1_sdphydataw_next_value0 <= 1'd0; + dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd1; + dataw_crc_error1_sdphydataw_next_value1 <= 1'd0; + dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd1; + dataw_write_error1_sdphydataw_next_value2 <= 1'd0; + dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd1; + dataw_count_sdphydataw_next_value3 <= 1'd0; + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + if ((dataw_sink_valid & dataw_pads_out_ready)) begin + sdphydataw_next_state <= 1'd1; + end + end + endcase +end +assign datar_datar_pads_in_valid = datar_pads_in_pads_in_valid; +assign datar_pads_in_pads_in_ready = datar_datar_pads_in_ready; +assign datar_datar_pads_in_first = datar_pads_in_pads_in_first; +assign datar_datar_pads_in_last = datar_pads_in_pads_in_last; +assign datar_datar_pads_in_payload_clk = datar_pads_in_pads_in_payload_clk; +assign datar_datar_pads_in_payload_cmd_i = datar_pads_in_pads_in_payload_cmd_i; +assign datar_datar_pads_in_payload_cmd_o = datar_pads_in_pads_in_payload_cmd_o; +assign datar_datar_pads_in_payload_cmd_oe = datar_pads_in_pads_in_payload_cmd_oe; +assign datar_datar_pads_in_payload_data_i = datar_pads_in_pads_in_payload_data_i; +assign datar_datar_pads_in_payload_data_o = datar_pads_in_pads_in_payload_data_o; +assign datar_datar_pads_in_payload_data_oe = datar_pads_in_pads_in_payload_data_oe; +assign datar_datar_pads_in_payload_data_i_ce = datar_pads_in_pads_in_payload_data_i_ce; +assign datar_datar_start = (datar_datar_pads_in_payload_data_i[3:0] == 1'd0); +assign datar_datar_converter_converter_sink_valid = (datar_datar_pads_in_valid & datar_datar_run); +assign datar_datar_converter_converter_sink_payload_data = datar_datar_pads_in_payload_data_i[3:0]; +assign datar_datar_buf_sink_sink_valid = datar_datar_converter_source_source_valid; +assign datar_datar_converter_source_source_ready = datar_datar_buf_sink_sink_ready; +assign datar_datar_buf_sink_sink_first = datar_datar_converter_source_source_first; +assign datar_datar_buf_sink_sink_last = datar_datar_converter_source_source_last; +assign datar_datar_buf_sink_sink_payload_data = datar_datar_converter_source_source_payload_data; +assign datar_datar_source_valid = datar_datar_buf_source_source_valid; +assign datar_datar_buf_source_source_ready = datar_datar_source_ready; +assign datar_datar_source_first = datar_datar_buf_source_source_first; +assign datar_datar_source_last = datar_datar_buf_source_source_last; +assign datar_datar_source_payload_data = datar_datar_buf_source_source_payload_data; +assign datar_datar_converter_source_source_valid = datar_datar_converter_converter_source_valid; +assign datar_datar_converter_converter_source_ready = datar_datar_converter_source_source_ready; +assign datar_datar_converter_source_source_first = datar_datar_converter_converter_source_first; +assign datar_datar_converter_source_source_last = datar_datar_converter_converter_source_last; +assign datar_datar_converter_source_source_payload_data = datar_datar_converter_converter_source_payload_data; +assign datar_datar_converter_converter_sink_ready = ((~datar_datar_converter_converter_strobe_all) | datar_datar_converter_converter_source_ready); +assign datar_datar_converter_converter_source_valid = datar_datar_converter_converter_strobe_all; +assign datar_datar_converter_converter_load_part = (datar_datar_converter_converter_sink_valid & datar_datar_converter_converter_sink_ready); +assign datar_datar_buf_pipe_valid_sink_ready = ((~datar_datar_buf_pipe_valid_source_valid) | datar_datar_buf_pipe_valid_source_ready); +assign datar_datar_buf_pipe_valid_sink_valid = datar_datar_buf_sink_sink_valid; +assign datar_datar_buf_sink_sink_ready = datar_datar_buf_pipe_valid_sink_ready; +assign datar_datar_buf_pipe_valid_sink_first = datar_datar_buf_sink_sink_first; +assign datar_datar_buf_pipe_valid_sink_last = datar_datar_buf_sink_sink_last; +assign datar_datar_buf_pipe_valid_sink_payload_data = datar_datar_buf_sink_sink_payload_data; +assign datar_datar_buf_source_source_valid = datar_datar_buf_pipe_valid_source_valid; +assign datar_datar_buf_pipe_valid_source_ready = datar_datar_buf_source_source_ready; +assign datar_datar_buf_source_source_first = datar_datar_buf_pipe_valid_source_first; +assign datar_datar_buf_source_source_last = datar_datar_buf_pipe_valid_source_last; +assign datar_datar_buf_source_source_payload_data = datar_datar_buf_pipe_valid_source_payload_data; +always @(*) begin + datar_count_sdphydatar_next_value0 <= 10'd0; + datar_count_sdphydatar_next_value_ce0 <= 1'd0; + datar_datar_reset_sdphydatar_next_value2 <= 1'd0; + datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd0; + datar_datar_source_ready <= 1'd0; + datar_pads_out_payload_clk <= 1'd0; + datar_sink_ready <= 1'd0; + datar_source_source_first <= 1'd0; + datar_source_source_last <= 1'd0; + datar_source_source_payload_data <= 8'd0; + datar_source_source_payload_status <= 3'd0; + datar_source_source_valid <= 1'd0; + datar_stop <= 1'd0; + datar_timeout_sdphydatar_next_value1 <= 32'd0; + datar_timeout_sdphydatar_next_value_ce1 <= 1'd0; + sdphydatar_next_state <= 3'd0; + sdphydatar_next_state <= sdphydatar_state; + case (sdphydatar_state) + 1'd1: begin + datar_pads_out_payload_clk <= 1'd1; + datar_datar_reset_sdphydatar_next_value2 <= 1'd0; + datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd1; + datar_timeout_sdphydatar_next_value1 <= (datar_timeout - 1'd1); + datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; + if (datar_datar_source_valid) begin + sdphydatar_next_state <= 2'd2; + end + datar_timeout_sdphydatar_next_value1 <= (datar_timeout - 1'd1); + datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; + if ((datar_timeout == 1'd0)) begin + datar_sink_ready <= 1'd1; + sdphydatar_next_state <= 3'd4; + end + end + 2'd2: begin + datar_pads_out_payload_clk <= 1'd1; + datar_source_source_valid <= datar_datar_source_valid; + datar_source_source_payload_status <= 1'd0; + datar_source_source_first <= (datar_count == 1'd0); + datar_source_source_last <= (datar_count == ((datar_sink_payload_block_length + 4'd8) - 1'd1)); + datar_source_source_payload_data <= datar_datar_source_payload_data; + if (datar_source_source_valid) begin + if (datar_source_source_ready) begin + datar_datar_source_ready <= 1'd1; + datar_count_sdphydatar_next_value0 <= (datar_count + 1'd1); + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + if (datar_source_source_last) begin + datar_sink_ready <= 1'd1; + if (datar_sink_last) begin + datar_count_sdphydatar_next_value0 <= 1'd0; + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + sdphydatar_next_state <= 2'd3; + end else begin + sdphydatar_next_state <= 1'd0; + end + end + end else begin + datar_stop <= 1'd1; + end + end + datar_timeout_sdphydatar_next_value1 <= (datar_timeout - 1'd1); + datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; + if ((datar_timeout == 1'd0)) begin + datar_sink_ready <= 1'd1; + sdphydatar_next_state <= 3'd4; + end + end + 2'd3: begin + datar_pads_out_payload_clk <= 1'd1; + if (datar_pads_out_ready) begin + datar_count_sdphydatar_next_value0 <= (datar_count + 1'd1); + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + if ((datar_count == 6'd39)) begin + sdphydatar_next_state <= 1'd0; + end + end + end + 3'd4: begin + datar_source_source_valid <= 1'd1; + datar_source_source_payload_status <= 1'd1; + datar_source_source_last <= 1'd1; + if (datar_source_source_ready) begin + sdphydatar_next_state <= 1'd0; + end + end + default: begin + datar_count_sdphydatar_next_value0 <= 1'd0; + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + if ((datar_sink_valid & datar_pads_out_ready)) begin + datar_pads_out_payload_clk <= 1'd1; + datar_timeout_sdphydatar_next_value1 <= 32'd48000000; + datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; + datar_count_sdphydatar_next_value0 <= 1'd0; + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + datar_datar_reset_sdphydatar_next_value2 <= 1'd1; + datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd1; + sdphydatar_next_state <= 1'd1; + end + end + endcase +end +assign sdcard_core_crc16_inserter_sink_valid = sdcard_core_sink_sink_valid0; +assign sdcard_core_sink_sink_ready0 = sdcard_core_crc16_inserter_sink_ready; +assign sdcard_core_crc16_inserter_sink_first = sdcard_core_sink_sink_first0; +assign sdcard_core_crc16_inserter_sink_last = sdcard_core_sink_sink_last0; +assign sdcard_core_crc16_inserter_sink_payload_data = sdcard_core_sink_sink_payload_data0; +assign sdcard_core_source_source_valid0 = sdcard_core_source_source_valid1; +assign sdcard_core_source_source_ready1 = sdcard_core_source_source_ready0; +assign sdcard_core_source_source_first0 = sdcard_core_source_source_first1; +assign sdcard_core_source_source_last0 = sdcard_core_source_source_last1; +assign sdcard_core_source_source_payload_data0 = sdcard_core_source_source_payload_data1; +assign sdcard_core_cmd_type = sdcard_core_csrfield_cmd_type; +assign sdcard_core_data_type = sdcard_core_csrfield_data_type; +assign sdcard_core_cmd = sdcard_core_csrfield_cmd; +assign sdcard_core_csrfield_done0 = sdcard_core_cmd_done; +assign sdcard_core_csrfield_error0 = sdcard_core_cmd_error; +assign sdcard_core_csrfield_timeout0 = sdcard_core_cmd_timeout; +assign sdcard_core_csrfield_crc0 = 1'd0; +assign sdcard_core_csrfield_done1 = sdcard_core_data_done; +assign sdcard_core_csrfield_error1 = sdcard_core_data_error; +assign sdcard_core_csrfield_timeout1 = sdcard_core_data_timeout; +assign sdcard_core_csrfield_crc1 = 1'd0; +assign sdcard_core_crc7_inserter_crc_din = {1'd0, 1'd1, sdcard_core_cmd, sdcard_core_cmd_argument_storage}; +assign sdcard_core_crc7_inserter_crc_reset = 1'd1; +assign sdcard_core_crc7_inserter_crc_enable = 1'd1; +assign sdcard_core_crc7_inserter_crc1 = {sdcard_core_crc7_inserter_crc0[5], sdcard_core_crc7_inserter_crc0[4], sdcard_core_crc7_inserter_crc0[3], (sdcard_core_crc7_inserter_crc0[2] ^ (sdcard_core_crc7_inserter_crc_din[39] ^ sdcard_core_crc7_inserter_crc0[6])), sdcard_core_crc7_inserter_crc0[1], sdcard_core_crc7_inserter_crc0[0], (sdcard_core_crc7_inserter_crc_din[39] ^ sdcard_core_crc7_inserter_crc0[6])}; +assign sdcard_core_crc7_inserter_crc2 = {sdcard_core_crc7_inserter_crc1[5], sdcard_core_crc7_inserter_crc1[4], sdcard_core_crc7_inserter_crc1[3], (sdcard_core_crc7_inserter_crc1[2] ^ (sdcard_core_crc7_inserter_crc_din[38] ^ sdcard_core_crc7_inserter_crc1[6])), sdcard_core_crc7_inserter_crc1[1], sdcard_core_crc7_inserter_crc1[0], (sdcard_core_crc7_inserter_crc_din[38] ^ sdcard_core_crc7_inserter_crc1[6])}; +assign sdcard_core_crc7_inserter_crc3 = {sdcard_core_crc7_inserter_crc2[5], sdcard_core_crc7_inserter_crc2[4], sdcard_core_crc7_inserter_crc2[3], (sdcard_core_crc7_inserter_crc2[2] ^ (sdcard_core_crc7_inserter_crc_din[37] ^ sdcard_core_crc7_inserter_crc2[6])), sdcard_core_crc7_inserter_crc2[1], sdcard_core_crc7_inserter_crc2[0], (sdcard_core_crc7_inserter_crc_din[37] ^ sdcard_core_crc7_inserter_crc2[6])}; +assign sdcard_core_crc7_inserter_crc4 = {sdcard_core_crc7_inserter_crc3[5], sdcard_core_crc7_inserter_crc3[4], sdcard_core_crc7_inserter_crc3[3], (sdcard_core_crc7_inserter_crc3[2] ^ (sdcard_core_crc7_inserter_crc_din[36] ^ sdcard_core_crc7_inserter_crc3[6])), sdcard_core_crc7_inserter_crc3[1], sdcard_core_crc7_inserter_crc3[0], (sdcard_core_crc7_inserter_crc_din[36] ^ sdcard_core_crc7_inserter_crc3[6])}; +assign sdcard_core_crc7_inserter_crc5 = {sdcard_core_crc7_inserter_crc4[5], sdcard_core_crc7_inserter_crc4[4], sdcard_core_crc7_inserter_crc4[3], (sdcard_core_crc7_inserter_crc4[2] ^ (sdcard_core_crc7_inserter_crc_din[35] ^ sdcard_core_crc7_inserter_crc4[6])), sdcard_core_crc7_inserter_crc4[1], sdcard_core_crc7_inserter_crc4[0], (sdcard_core_crc7_inserter_crc_din[35] ^ sdcard_core_crc7_inserter_crc4[6])}; +assign sdcard_core_crc7_inserter_crc6 = {sdcard_core_crc7_inserter_crc5[5], sdcard_core_crc7_inserter_crc5[4], sdcard_core_crc7_inserter_crc5[3], (sdcard_core_crc7_inserter_crc5[2] ^ (sdcard_core_crc7_inserter_crc_din[34] ^ sdcard_core_crc7_inserter_crc5[6])), sdcard_core_crc7_inserter_crc5[1], sdcard_core_crc7_inserter_crc5[0], (sdcard_core_crc7_inserter_crc_din[34] ^ sdcard_core_crc7_inserter_crc5[6])}; +assign sdcard_core_crc7_inserter_crc7 = {sdcard_core_crc7_inserter_crc6[5], sdcard_core_crc7_inserter_crc6[4], sdcard_core_crc7_inserter_crc6[3], (sdcard_core_crc7_inserter_crc6[2] ^ (sdcard_core_crc7_inserter_crc_din[33] ^ sdcard_core_crc7_inserter_crc6[6])), sdcard_core_crc7_inserter_crc6[1], sdcard_core_crc7_inserter_crc6[0], (sdcard_core_crc7_inserter_crc_din[33] ^ sdcard_core_crc7_inserter_crc6[6])}; +assign sdcard_core_crc7_inserter_crc8 = {sdcard_core_crc7_inserter_crc7[5], sdcard_core_crc7_inserter_crc7[4], sdcard_core_crc7_inserter_crc7[3], (sdcard_core_crc7_inserter_crc7[2] ^ (sdcard_core_crc7_inserter_crc_din[32] ^ sdcard_core_crc7_inserter_crc7[6])), sdcard_core_crc7_inserter_crc7[1], sdcard_core_crc7_inserter_crc7[0], (sdcard_core_crc7_inserter_crc_din[32] ^ sdcard_core_crc7_inserter_crc7[6])}; +assign sdcard_core_crc7_inserter_crc9 = {sdcard_core_crc7_inserter_crc8[5], sdcard_core_crc7_inserter_crc8[4], sdcard_core_crc7_inserter_crc8[3], (sdcard_core_crc7_inserter_crc8[2] ^ (sdcard_core_crc7_inserter_crc_din[31] ^ sdcard_core_crc7_inserter_crc8[6])), sdcard_core_crc7_inserter_crc8[1], sdcard_core_crc7_inserter_crc8[0], (sdcard_core_crc7_inserter_crc_din[31] ^ sdcard_core_crc7_inserter_crc8[6])}; +assign sdcard_core_crc7_inserter_crc10 = {sdcard_core_crc7_inserter_crc9[5], sdcard_core_crc7_inserter_crc9[4], sdcard_core_crc7_inserter_crc9[3], (sdcard_core_crc7_inserter_crc9[2] ^ (sdcard_core_crc7_inserter_crc_din[30] ^ sdcard_core_crc7_inserter_crc9[6])), sdcard_core_crc7_inserter_crc9[1], sdcard_core_crc7_inserter_crc9[0], (sdcard_core_crc7_inserter_crc_din[30] ^ sdcard_core_crc7_inserter_crc9[6])}; +assign sdcard_core_crc7_inserter_crc11 = {sdcard_core_crc7_inserter_crc10[5], sdcard_core_crc7_inserter_crc10[4], sdcard_core_crc7_inserter_crc10[3], (sdcard_core_crc7_inserter_crc10[2] ^ (sdcard_core_crc7_inserter_crc_din[29] ^ sdcard_core_crc7_inserter_crc10[6])), sdcard_core_crc7_inserter_crc10[1], sdcard_core_crc7_inserter_crc10[0], (sdcard_core_crc7_inserter_crc_din[29] ^ sdcard_core_crc7_inserter_crc10[6])}; +assign sdcard_core_crc7_inserter_crc12 = {sdcard_core_crc7_inserter_crc11[5], sdcard_core_crc7_inserter_crc11[4], sdcard_core_crc7_inserter_crc11[3], (sdcard_core_crc7_inserter_crc11[2] ^ (sdcard_core_crc7_inserter_crc_din[28] ^ sdcard_core_crc7_inserter_crc11[6])), sdcard_core_crc7_inserter_crc11[1], sdcard_core_crc7_inserter_crc11[0], (sdcard_core_crc7_inserter_crc_din[28] ^ sdcard_core_crc7_inserter_crc11[6])}; +assign sdcard_core_crc7_inserter_crc13 = {sdcard_core_crc7_inserter_crc12[5], sdcard_core_crc7_inserter_crc12[4], sdcard_core_crc7_inserter_crc12[3], (sdcard_core_crc7_inserter_crc12[2] ^ (sdcard_core_crc7_inserter_crc_din[27] ^ sdcard_core_crc7_inserter_crc12[6])), sdcard_core_crc7_inserter_crc12[1], sdcard_core_crc7_inserter_crc12[0], (sdcard_core_crc7_inserter_crc_din[27] ^ sdcard_core_crc7_inserter_crc12[6])}; +assign sdcard_core_crc7_inserter_crc14 = {sdcard_core_crc7_inserter_crc13[5], sdcard_core_crc7_inserter_crc13[4], sdcard_core_crc7_inserter_crc13[3], (sdcard_core_crc7_inserter_crc13[2] ^ (sdcard_core_crc7_inserter_crc_din[26] ^ sdcard_core_crc7_inserter_crc13[6])), sdcard_core_crc7_inserter_crc13[1], sdcard_core_crc7_inserter_crc13[0], (sdcard_core_crc7_inserter_crc_din[26] ^ sdcard_core_crc7_inserter_crc13[6])}; +assign sdcard_core_crc7_inserter_crc15 = {sdcard_core_crc7_inserter_crc14[5], sdcard_core_crc7_inserter_crc14[4], sdcard_core_crc7_inserter_crc14[3], (sdcard_core_crc7_inserter_crc14[2] ^ (sdcard_core_crc7_inserter_crc_din[25] ^ sdcard_core_crc7_inserter_crc14[6])), sdcard_core_crc7_inserter_crc14[1], sdcard_core_crc7_inserter_crc14[0], (sdcard_core_crc7_inserter_crc_din[25] ^ sdcard_core_crc7_inserter_crc14[6])}; +assign sdcard_core_crc7_inserter_crc16 = {sdcard_core_crc7_inserter_crc15[5], sdcard_core_crc7_inserter_crc15[4], sdcard_core_crc7_inserter_crc15[3], (sdcard_core_crc7_inserter_crc15[2] ^ (sdcard_core_crc7_inserter_crc_din[24] ^ sdcard_core_crc7_inserter_crc15[6])), sdcard_core_crc7_inserter_crc15[1], sdcard_core_crc7_inserter_crc15[0], (sdcard_core_crc7_inserter_crc_din[24] ^ sdcard_core_crc7_inserter_crc15[6])}; +assign sdcard_core_crc7_inserter_crc17 = {sdcard_core_crc7_inserter_crc16[5], sdcard_core_crc7_inserter_crc16[4], sdcard_core_crc7_inserter_crc16[3], (sdcard_core_crc7_inserter_crc16[2] ^ (sdcard_core_crc7_inserter_crc_din[23] ^ sdcard_core_crc7_inserter_crc16[6])), sdcard_core_crc7_inserter_crc16[1], sdcard_core_crc7_inserter_crc16[0], (sdcard_core_crc7_inserter_crc_din[23] ^ sdcard_core_crc7_inserter_crc16[6])}; +assign sdcard_core_crc7_inserter_crc18 = {sdcard_core_crc7_inserter_crc17[5], sdcard_core_crc7_inserter_crc17[4], sdcard_core_crc7_inserter_crc17[3], (sdcard_core_crc7_inserter_crc17[2] ^ (sdcard_core_crc7_inserter_crc_din[22] ^ sdcard_core_crc7_inserter_crc17[6])), sdcard_core_crc7_inserter_crc17[1], sdcard_core_crc7_inserter_crc17[0], (sdcard_core_crc7_inserter_crc_din[22] ^ sdcard_core_crc7_inserter_crc17[6])}; +assign sdcard_core_crc7_inserter_crc19 = {sdcard_core_crc7_inserter_crc18[5], sdcard_core_crc7_inserter_crc18[4], sdcard_core_crc7_inserter_crc18[3], (sdcard_core_crc7_inserter_crc18[2] ^ (sdcard_core_crc7_inserter_crc_din[21] ^ sdcard_core_crc7_inserter_crc18[6])), sdcard_core_crc7_inserter_crc18[1], sdcard_core_crc7_inserter_crc18[0], (sdcard_core_crc7_inserter_crc_din[21] ^ sdcard_core_crc7_inserter_crc18[6])}; +assign sdcard_core_crc7_inserter_crc20 = {sdcard_core_crc7_inserter_crc19[5], sdcard_core_crc7_inserter_crc19[4], sdcard_core_crc7_inserter_crc19[3], (sdcard_core_crc7_inserter_crc19[2] ^ (sdcard_core_crc7_inserter_crc_din[20] ^ sdcard_core_crc7_inserter_crc19[6])), sdcard_core_crc7_inserter_crc19[1], sdcard_core_crc7_inserter_crc19[0], (sdcard_core_crc7_inserter_crc_din[20] ^ sdcard_core_crc7_inserter_crc19[6])}; +assign sdcard_core_crc7_inserter_crc21 = {sdcard_core_crc7_inserter_crc20[5], sdcard_core_crc7_inserter_crc20[4], sdcard_core_crc7_inserter_crc20[3], (sdcard_core_crc7_inserter_crc20[2] ^ (sdcard_core_crc7_inserter_crc_din[19] ^ sdcard_core_crc7_inserter_crc20[6])), sdcard_core_crc7_inserter_crc20[1], sdcard_core_crc7_inserter_crc20[0], (sdcard_core_crc7_inserter_crc_din[19] ^ sdcard_core_crc7_inserter_crc20[6])}; +assign sdcard_core_crc7_inserter_crc22 = {sdcard_core_crc7_inserter_crc21[5], sdcard_core_crc7_inserter_crc21[4], sdcard_core_crc7_inserter_crc21[3], (sdcard_core_crc7_inserter_crc21[2] ^ (sdcard_core_crc7_inserter_crc_din[18] ^ sdcard_core_crc7_inserter_crc21[6])), sdcard_core_crc7_inserter_crc21[1], sdcard_core_crc7_inserter_crc21[0], (sdcard_core_crc7_inserter_crc_din[18] ^ sdcard_core_crc7_inserter_crc21[6])}; +assign sdcard_core_crc7_inserter_crc23 = {sdcard_core_crc7_inserter_crc22[5], sdcard_core_crc7_inserter_crc22[4], sdcard_core_crc7_inserter_crc22[3], (sdcard_core_crc7_inserter_crc22[2] ^ (sdcard_core_crc7_inserter_crc_din[17] ^ sdcard_core_crc7_inserter_crc22[6])), sdcard_core_crc7_inserter_crc22[1], sdcard_core_crc7_inserter_crc22[0], (sdcard_core_crc7_inserter_crc_din[17] ^ sdcard_core_crc7_inserter_crc22[6])}; +assign sdcard_core_crc7_inserter_crc24 = {sdcard_core_crc7_inserter_crc23[5], sdcard_core_crc7_inserter_crc23[4], sdcard_core_crc7_inserter_crc23[3], (sdcard_core_crc7_inserter_crc23[2] ^ (sdcard_core_crc7_inserter_crc_din[16] ^ sdcard_core_crc7_inserter_crc23[6])), sdcard_core_crc7_inserter_crc23[1], sdcard_core_crc7_inserter_crc23[0], (sdcard_core_crc7_inserter_crc_din[16] ^ sdcard_core_crc7_inserter_crc23[6])}; +assign sdcard_core_crc7_inserter_crc25 = {sdcard_core_crc7_inserter_crc24[5], sdcard_core_crc7_inserter_crc24[4], sdcard_core_crc7_inserter_crc24[3], (sdcard_core_crc7_inserter_crc24[2] ^ (sdcard_core_crc7_inserter_crc_din[15] ^ sdcard_core_crc7_inserter_crc24[6])), sdcard_core_crc7_inserter_crc24[1], sdcard_core_crc7_inserter_crc24[0], (sdcard_core_crc7_inserter_crc_din[15] ^ sdcard_core_crc7_inserter_crc24[6])}; +assign sdcard_core_crc7_inserter_crc26 = {sdcard_core_crc7_inserter_crc25[5], sdcard_core_crc7_inserter_crc25[4], sdcard_core_crc7_inserter_crc25[3], (sdcard_core_crc7_inserter_crc25[2] ^ (sdcard_core_crc7_inserter_crc_din[14] ^ sdcard_core_crc7_inserter_crc25[6])), sdcard_core_crc7_inserter_crc25[1], sdcard_core_crc7_inserter_crc25[0], (sdcard_core_crc7_inserter_crc_din[14] ^ sdcard_core_crc7_inserter_crc25[6])}; +assign sdcard_core_crc7_inserter_crc27 = {sdcard_core_crc7_inserter_crc26[5], sdcard_core_crc7_inserter_crc26[4], sdcard_core_crc7_inserter_crc26[3], (sdcard_core_crc7_inserter_crc26[2] ^ (sdcard_core_crc7_inserter_crc_din[13] ^ sdcard_core_crc7_inserter_crc26[6])), sdcard_core_crc7_inserter_crc26[1], sdcard_core_crc7_inserter_crc26[0], (sdcard_core_crc7_inserter_crc_din[13] ^ sdcard_core_crc7_inserter_crc26[6])}; +assign sdcard_core_crc7_inserter_crc28 = {sdcard_core_crc7_inserter_crc27[5], sdcard_core_crc7_inserter_crc27[4], sdcard_core_crc7_inserter_crc27[3], (sdcard_core_crc7_inserter_crc27[2] ^ (sdcard_core_crc7_inserter_crc_din[12] ^ sdcard_core_crc7_inserter_crc27[6])), sdcard_core_crc7_inserter_crc27[1], sdcard_core_crc7_inserter_crc27[0], (sdcard_core_crc7_inserter_crc_din[12] ^ sdcard_core_crc7_inserter_crc27[6])}; +assign sdcard_core_crc7_inserter_crc29 = {sdcard_core_crc7_inserter_crc28[5], sdcard_core_crc7_inserter_crc28[4], sdcard_core_crc7_inserter_crc28[3], (sdcard_core_crc7_inserter_crc28[2] ^ (sdcard_core_crc7_inserter_crc_din[11] ^ sdcard_core_crc7_inserter_crc28[6])), sdcard_core_crc7_inserter_crc28[1], sdcard_core_crc7_inserter_crc28[0], (sdcard_core_crc7_inserter_crc_din[11] ^ sdcard_core_crc7_inserter_crc28[6])}; +assign sdcard_core_crc7_inserter_crc30 = {sdcard_core_crc7_inserter_crc29[5], sdcard_core_crc7_inserter_crc29[4], sdcard_core_crc7_inserter_crc29[3], (sdcard_core_crc7_inserter_crc29[2] ^ (sdcard_core_crc7_inserter_crc_din[10] ^ sdcard_core_crc7_inserter_crc29[6])), sdcard_core_crc7_inserter_crc29[1], sdcard_core_crc7_inserter_crc29[0], (sdcard_core_crc7_inserter_crc_din[10] ^ sdcard_core_crc7_inserter_crc29[6])}; +assign sdcard_core_crc7_inserter_crc31 = {sdcard_core_crc7_inserter_crc30[5], sdcard_core_crc7_inserter_crc30[4], sdcard_core_crc7_inserter_crc30[3], (sdcard_core_crc7_inserter_crc30[2] ^ (sdcard_core_crc7_inserter_crc_din[9] ^ sdcard_core_crc7_inserter_crc30[6])), sdcard_core_crc7_inserter_crc30[1], sdcard_core_crc7_inserter_crc30[0], (sdcard_core_crc7_inserter_crc_din[9] ^ sdcard_core_crc7_inserter_crc30[6])}; +assign sdcard_core_crc7_inserter_crc32 = {sdcard_core_crc7_inserter_crc31[5], sdcard_core_crc7_inserter_crc31[4], sdcard_core_crc7_inserter_crc31[3], (sdcard_core_crc7_inserter_crc31[2] ^ (sdcard_core_crc7_inserter_crc_din[8] ^ sdcard_core_crc7_inserter_crc31[6])), sdcard_core_crc7_inserter_crc31[1], sdcard_core_crc7_inserter_crc31[0], (sdcard_core_crc7_inserter_crc_din[8] ^ sdcard_core_crc7_inserter_crc31[6])}; +assign sdcard_core_crc7_inserter_crc33 = {sdcard_core_crc7_inserter_crc32[5], sdcard_core_crc7_inserter_crc32[4], sdcard_core_crc7_inserter_crc32[3], (sdcard_core_crc7_inserter_crc32[2] ^ (sdcard_core_crc7_inserter_crc_din[7] ^ sdcard_core_crc7_inserter_crc32[6])), sdcard_core_crc7_inserter_crc32[1], sdcard_core_crc7_inserter_crc32[0], (sdcard_core_crc7_inserter_crc_din[7] ^ sdcard_core_crc7_inserter_crc32[6])}; +assign sdcard_core_crc7_inserter_crc34 = {sdcard_core_crc7_inserter_crc33[5], sdcard_core_crc7_inserter_crc33[4], sdcard_core_crc7_inserter_crc33[3], (sdcard_core_crc7_inserter_crc33[2] ^ (sdcard_core_crc7_inserter_crc_din[6] ^ sdcard_core_crc7_inserter_crc33[6])), sdcard_core_crc7_inserter_crc33[1], sdcard_core_crc7_inserter_crc33[0], (sdcard_core_crc7_inserter_crc_din[6] ^ sdcard_core_crc7_inserter_crc33[6])}; +assign sdcard_core_crc7_inserter_crc35 = {sdcard_core_crc7_inserter_crc34[5], sdcard_core_crc7_inserter_crc34[4], sdcard_core_crc7_inserter_crc34[3], (sdcard_core_crc7_inserter_crc34[2] ^ (sdcard_core_crc7_inserter_crc_din[5] ^ sdcard_core_crc7_inserter_crc34[6])), sdcard_core_crc7_inserter_crc34[1], sdcard_core_crc7_inserter_crc34[0], (sdcard_core_crc7_inserter_crc_din[5] ^ sdcard_core_crc7_inserter_crc34[6])}; +assign sdcard_core_crc7_inserter_crc36 = {sdcard_core_crc7_inserter_crc35[5], sdcard_core_crc7_inserter_crc35[4], sdcard_core_crc7_inserter_crc35[3], (sdcard_core_crc7_inserter_crc35[2] ^ (sdcard_core_crc7_inserter_crc_din[4] ^ sdcard_core_crc7_inserter_crc35[6])), sdcard_core_crc7_inserter_crc35[1], sdcard_core_crc7_inserter_crc35[0], (sdcard_core_crc7_inserter_crc_din[4] ^ sdcard_core_crc7_inserter_crc35[6])}; +assign sdcard_core_crc7_inserter_crc37 = {sdcard_core_crc7_inserter_crc36[5], sdcard_core_crc7_inserter_crc36[4], sdcard_core_crc7_inserter_crc36[3], (sdcard_core_crc7_inserter_crc36[2] ^ (sdcard_core_crc7_inserter_crc_din[3] ^ sdcard_core_crc7_inserter_crc36[6])), sdcard_core_crc7_inserter_crc36[1], sdcard_core_crc7_inserter_crc36[0], (sdcard_core_crc7_inserter_crc_din[3] ^ sdcard_core_crc7_inserter_crc36[6])}; +assign sdcard_core_crc7_inserter_crc38 = {sdcard_core_crc7_inserter_crc37[5], sdcard_core_crc7_inserter_crc37[4], sdcard_core_crc7_inserter_crc37[3], (sdcard_core_crc7_inserter_crc37[2] ^ (sdcard_core_crc7_inserter_crc_din[2] ^ sdcard_core_crc7_inserter_crc37[6])), sdcard_core_crc7_inserter_crc37[1], sdcard_core_crc7_inserter_crc37[0], (sdcard_core_crc7_inserter_crc_din[2] ^ sdcard_core_crc7_inserter_crc37[6])}; +assign sdcard_core_crc7_inserter_crc39 = {sdcard_core_crc7_inserter_crc38[5], sdcard_core_crc7_inserter_crc38[4], sdcard_core_crc7_inserter_crc38[3], (sdcard_core_crc7_inserter_crc38[2] ^ (sdcard_core_crc7_inserter_crc_din[1] ^ sdcard_core_crc7_inserter_crc38[6])), sdcard_core_crc7_inserter_crc38[1], sdcard_core_crc7_inserter_crc38[0], (sdcard_core_crc7_inserter_crc_din[1] ^ sdcard_core_crc7_inserter_crc38[6])}; +assign sdcard_core_crc7_inserter_crc40 = {sdcard_core_crc7_inserter_crc39[5], sdcard_core_crc7_inserter_crc39[4], sdcard_core_crc7_inserter_crc39[3], (sdcard_core_crc7_inserter_crc39[2] ^ (sdcard_core_crc7_inserter_crc_din[0] ^ sdcard_core_crc7_inserter_crc39[6])), sdcard_core_crc7_inserter_crc39[1], sdcard_core_crc7_inserter_crc39[0], (sdcard_core_crc7_inserter_crc_din[0] ^ sdcard_core_crc7_inserter_crc39[6])}; +always @(*) begin + sdcard_core_crc7_inserter_crc_crc <= 7'd0; + if (sdcard_core_crc7_inserter_crc_enable) begin + sdcard_core_crc7_inserter_crc_crc <= sdcard_core_crc7_inserter_crc40; + end else begin + sdcard_core_crc7_inserter_crc_crc <= sdcard_core_crc7_inserter_crc0; + end +end +assign sdcard_core_crc16_inserter_crc0_reset = ((sdcard_core_crc16_inserter_source_valid & sdcard_core_crc16_inserter_source_ready) & sdcard_core_crc16_inserter_source_last); +assign sdcard_core_crc16_inserter_crc0_enable = (sdcard_core_crc16_inserter_sink_valid & sdcard_core_crc16_inserter_sink_ready); +always @(*) begin + sdcard_core_crc16_inserter_crc0_din <= 2'd0; + sdcard_core_crc16_inserter_crc0_din[0] <= sdcard_core_crc16_inserter_sink_payload_data[0]; + sdcard_core_crc16_inserter_crc0_din[1] <= sdcard_core_crc16_inserter_sink_payload_data[4]; +end +assign sdcard_core_crc16_inserter_crc1_reset = ((sdcard_core_crc16_inserter_source_valid & sdcard_core_crc16_inserter_source_ready) & sdcard_core_crc16_inserter_source_last); +assign sdcard_core_crc16_inserter_crc1_enable = (sdcard_core_crc16_inserter_sink_valid & sdcard_core_crc16_inserter_sink_ready); +always @(*) begin + sdcard_core_crc16_inserter_crc1_din <= 2'd0; + sdcard_core_crc16_inserter_crc1_din[0] <= sdcard_core_crc16_inserter_sink_payload_data[1]; + sdcard_core_crc16_inserter_crc1_din[1] <= sdcard_core_crc16_inserter_sink_payload_data[5]; +end +assign sdcard_core_crc16_inserter_crc2_reset = ((sdcard_core_crc16_inserter_source_valid & sdcard_core_crc16_inserter_source_ready) & sdcard_core_crc16_inserter_source_last); +assign sdcard_core_crc16_inserter_crc2_enable = (sdcard_core_crc16_inserter_sink_valid & sdcard_core_crc16_inserter_sink_ready); +always @(*) begin + sdcard_core_crc16_inserter_crc2_din <= 2'd0; + sdcard_core_crc16_inserter_crc2_din[0] <= sdcard_core_crc16_inserter_sink_payload_data[2]; + sdcard_core_crc16_inserter_crc2_din[1] <= sdcard_core_crc16_inserter_sink_payload_data[6]; +end +assign sdcard_core_crc16_inserter_crc3_reset = ((sdcard_core_crc16_inserter_source_valid & sdcard_core_crc16_inserter_source_ready) & sdcard_core_crc16_inserter_source_last); +assign sdcard_core_crc16_inserter_crc3_enable = (sdcard_core_crc16_inserter_sink_valid & sdcard_core_crc16_inserter_sink_ready); +always @(*) begin + sdcard_core_crc16_inserter_crc3_din <= 2'd0; + sdcard_core_crc16_inserter_crc3_din[0] <= sdcard_core_crc16_inserter_sink_payload_data[3]; + sdcard_core_crc16_inserter_crc3_din[1] <= sdcard_core_crc16_inserter_sink_payload_data[7]; +end +assign sdcard_core_crc16_inserter_crc01 = {sdcard_core_crc16_inserter_crc00[14], sdcard_core_crc16_inserter_crc00[13], sdcard_core_crc16_inserter_crc00[12], (sdcard_core_crc16_inserter_crc00[11] ^ (sdcard_core_crc16_inserter_crc0_din[1] ^ sdcard_core_crc16_inserter_crc00[15])), sdcard_core_crc16_inserter_crc00[10], sdcard_core_crc16_inserter_crc00[9], sdcard_core_crc16_inserter_crc00[8], sdcard_core_crc16_inserter_crc00[7], sdcard_core_crc16_inserter_crc00[6], sdcard_core_crc16_inserter_crc00[5], (sdcard_core_crc16_inserter_crc00[4] ^ (sdcard_core_crc16_inserter_crc0_din[1] ^ sdcard_core_crc16_inserter_crc00[15])), sdcard_core_crc16_inserter_crc00[3], sdcard_core_crc16_inserter_crc00[2], sdcard_core_crc16_inserter_crc00[1], sdcard_core_crc16_inserter_crc00[0], (sdcard_core_crc16_inserter_crc0_din[1] ^ sdcard_core_crc16_inserter_crc00[15])}; +assign sdcard_core_crc16_inserter_crc02 = {sdcard_core_crc16_inserter_crc01[14], sdcard_core_crc16_inserter_crc01[13], sdcard_core_crc16_inserter_crc01[12], (sdcard_core_crc16_inserter_crc01[11] ^ (sdcard_core_crc16_inserter_crc0_din[0] ^ sdcard_core_crc16_inserter_crc01[15])), sdcard_core_crc16_inserter_crc01[10], sdcard_core_crc16_inserter_crc01[9], sdcard_core_crc16_inserter_crc01[8], sdcard_core_crc16_inserter_crc01[7], sdcard_core_crc16_inserter_crc01[6], sdcard_core_crc16_inserter_crc01[5], (sdcard_core_crc16_inserter_crc01[4] ^ (sdcard_core_crc16_inserter_crc0_din[0] ^ sdcard_core_crc16_inserter_crc01[15])), sdcard_core_crc16_inserter_crc01[3], sdcard_core_crc16_inserter_crc01[2], sdcard_core_crc16_inserter_crc01[1], sdcard_core_crc16_inserter_crc01[0], (sdcard_core_crc16_inserter_crc0_din[0] ^ sdcard_core_crc16_inserter_crc01[15])}; +always @(*) begin + sdcard_core_crc16_inserter_crc0_crc <= 16'd0; + if (sdcard_core_crc16_inserter_crc0_enable) begin + sdcard_core_crc16_inserter_crc0_crc <= sdcard_core_crc16_inserter_crc02; + end else begin + sdcard_core_crc16_inserter_crc0_crc <= sdcard_core_crc16_inserter_crc00; + end +end +assign sdcard_core_crc16_inserter_crc11 = {sdcard_core_crc16_inserter_crc10[14], sdcard_core_crc16_inserter_crc10[13], sdcard_core_crc16_inserter_crc10[12], (sdcard_core_crc16_inserter_crc10[11] ^ (sdcard_core_crc16_inserter_crc1_din[1] ^ sdcard_core_crc16_inserter_crc10[15])), sdcard_core_crc16_inserter_crc10[10], sdcard_core_crc16_inserter_crc10[9], sdcard_core_crc16_inserter_crc10[8], sdcard_core_crc16_inserter_crc10[7], sdcard_core_crc16_inserter_crc10[6], sdcard_core_crc16_inserter_crc10[5], (sdcard_core_crc16_inserter_crc10[4] ^ (sdcard_core_crc16_inserter_crc1_din[1] ^ sdcard_core_crc16_inserter_crc10[15])), sdcard_core_crc16_inserter_crc10[3], sdcard_core_crc16_inserter_crc10[2], sdcard_core_crc16_inserter_crc10[1], sdcard_core_crc16_inserter_crc10[0], (sdcard_core_crc16_inserter_crc1_din[1] ^ sdcard_core_crc16_inserter_crc10[15])}; +assign sdcard_core_crc16_inserter_crc12 = {sdcard_core_crc16_inserter_crc11[14], sdcard_core_crc16_inserter_crc11[13], sdcard_core_crc16_inserter_crc11[12], (sdcard_core_crc16_inserter_crc11[11] ^ (sdcard_core_crc16_inserter_crc1_din[0] ^ sdcard_core_crc16_inserter_crc11[15])), sdcard_core_crc16_inserter_crc11[10], sdcard_core_crc16_inserter_crc11[9], sdcard_core_crc16_inserter_crc11[8], sdcard_core_crc16_inserter_crc11[7], sdcard_core_crc16_inserter_crc11[6], sdcard_core_crc16_inserter_crc11[5], (sdcard_core_crc16_inserter_crc11[4] ^ (sdcard_core_crc16_inserter_crc1_din[0] ^ sdcard_core_crc16_inserter_crc11[15])), sdcard_core_crc16_inserter_crc11[3], sdcard_core_crc16_inserter_crc11[2], sdcard_core_crc16_inserter_crc11[1], sdcard_core_crc16_inserter_crc11[0], (sdcard_core_crc16_inserter_crc1_din[0] ^ sdcard_core_crc16_inserter_crc11[15])}; +always @(*) begin + sdcard_core_crc16_inserter_crc1_crc <= 16'd0; + if (sdcard_core_crc16_inserter_crc1_enable) begin + sdcard_core_crc16_inserter_crc1_crc <= sdcard_core_crc16_inserter_crc12; + end else begin + sdcard_core_crc16_inserter_crc1_crc <= sdcard_core_crc16_inserter_crc10; + end +end +assign sdcard_core_crc16_inserter_crc21 = {sdcard_core_crc16_inserter_crc20[14], sdcard_core_crc16_inserter_crc20[13], sdcard_core_crc16_inserter_crc20[12], (sdcard_core_crc16_inserter_crc20[11] ^ (sdcard_core_crc16_inserter_crc2_din[1] ^ sdcard_core_crc16_inserter_crc20[15])), sdcard_core_crc16_inserter_crc20[10], sdcard_core_crc16_inserter_crc20[9], sdcard_core_crc16_inserter_crc20[8], sdcard_core_crc16_inserter_crc20[7], sdcard_core_crc16_inserter_crc20[6], sdcard_core_crc16_inserter_crc20[5], (sdcard_core_crc16_inserter_crc20[4] ^ (sdcard_core_crc16_inserter_crc2_din[1] ^ sdcard_core_crc16_inserter_crc20[15])), sdcard_core_crc16_inserter_crc20[3], sdcard_core_crc16_inserter_crc20[2], sdcard_core_crc16_inserter_crc20[1], sdcard_core_crc16_inserter_crc20[0], (sdcard_core_crc16_inserter_crc2_din[1] ^ sdcard_core_crc16_inserter_crc20[15])}; +assign sdcard_core_crc16_inserter_crc22 = {sdcard_core_crc16_inserter_crc21[14], sdcard_core_crc16_inserter_crc21[13], sdcard_core_crc16_inserter_crc21[12], (sdcard_core_crc16_inserter_crc21[11] ^ (sdcard_core_crc16_inserter_crc2_din[0] ^ sdcard_core_crc16_inserter_crc21[15])), sdcard_core_crc16_inserter_crc21[10], sdcard_core_crc16_inserter_crc21[9], sdcard_core_crc16_inserter_crc21[8], sdcard_core_crc16_inserter_crc21[7], sdcard_core_crc16_inserter_crc21[6], sdcard_core_crc16_inserter_crc21[5], (sdcard_core_crc16_inserter_crc21[4] ^ (sdcard_core_crc16_inserter_crc2_din[0] ^ sdcard_core_crc16_inserter_crc21[15])), sdcard_core_crc16_inserter_crc21[3], sdcard_core_crc16_inserter_crc21[2], sdcard_core_crc16_inserter_crc21[1], sdcard_core_crc16_inserter_crc21[0], (sdcard_core_crc16_inserter_crc2_din[0] ^ sdcard_core_crc16_inserter_crc21[15])}; +always @(*) begin + sdcard_core_crc16_inserter_crc2_crc <= 16'd0; + if (sdcard_core_crc16_inserter_crc2_enable) begin + sdcard_core_crc16_inserter_crc2_crc <= sdcard_core_crc16_inserter_crc22; + end else begin + sdcard_core_crc16_inserter_crc2_crc <= sdcard_core_crc16_inserter_crc20; + end +end +assign sdcard_core_crc16_inserter_crc31 = {sdcard_core_crc16_inserter_crc30[14], sdcard_core_crc16_inserter_crc30[13], sdcard_core_crc16_inserter_crc30[12], (sdcard_core_crc16_inserter_crc30[11] ^ (sdcard_core_crc16_inserter_crc3_din[1] ^ sdcard_core_crc16_inserter_crc30[15])), sdcard_core_crc16_inserter_crc30[10], sdcard_core_crc16_inserter_crc30[9], sdcard_core_crc16_inserter_crc30[8], sdcard_core_crc16_inserter_crc30[7], sdcard_core_crc16_inserter_crc30[6], sdcard_core_crc16_inserter_crc30[5], (sdcard_core_crc16_inserter_crc30[4] ^ (sdcard_core_crc16_inserter_crc3_din[1] ^ sdcard_core_crc16_inserter_crc30[15])), sdcard_core_crc16_inserter_crc30[3], sdcard_core_crc16_inserter_crc30[2], sdcard_core_crc16_inserter_crc30[1], sdcard_core_crc16_inserter_crc30[0], (sdcard_core_crc16_inserter_crc3_din[1] ^ sdcard_core_crc16_inserter_crc30[15])}; +assign sdcard_core_crc16_inserter_crc32 = {sdcard_core_crc16_inserter_crc31[14], sdcard_core_crc16_inserter_crc31[13], sdcard_core_crc16_inserter_crc31[12], (sdcard_core_crc16_inserter_crc31[11] ^ (sdcard_core_crc16_inserter_crc3_din[0] ^ sdcard_core_crc16_inserter_crc31[15])), sdcard_core_crc16_inserter_crc31[10], sdcard_core_crc16_inserter_crc31[9], sdcard_core_crc16_inserter_crc31[8], sdcard_core_crc16_inserter_crc31[7], sdcard_core_crc16_inserter_crc31[6], sdcard_core_crc16_inserter_crc31[5], (sdcard_core_crc16_inserter_crc31[4] ^ (sdcard_core_crc16_inserter_crc3_din[0] ^ sdcard_core_crc16_inserter_crc31[15])), sdcard_core_crc16_inserter_crc31[3], sdcard_core_crc16_inserter_crc31[2], sdcard_core_crc16_inserter_crc31[1], sdcard_core_crc16_inserter_crc31[0], (sdcard_core_crc16_inserter_crc3_din[0] ^ sdcard_core_crc16_inserter_crc31[15])}; +always @(*) begin + sdcard_core_crc16_inserter_crc3_crc <= 16'd0; + if (sdcard_core_crc16_inserter_crc3_enable) begin + sdcard_core_crc16_inserter_crc3_crc <= sdcard_core_crc16_inserter_crc32; + end else begin + sdcard_core_crc16_inserter_crc3_crc <= sdcard_core_crc16_inserter_crc30; + end +end +always @(*) begin + crc16inserter_next_state <= 1'd0; + sdcard_core_crc16_inserter_count_crc16inserter_next_value <= 3'd0; + sdcard_core_crc16_inserter_count_crc16inserter_next_value_ce <= 1'd0; + sdcard_core_crc16_inserter_sink_ready <= 1'd0; + sdcard_core_crc16_inserter_source_first <= 1'd0; + sdcard_core_crc16_inserter_source_last <= 1'd0; + sdcard_core_crc16_inserter_source_payload_data <= 8'd0; + sdcard_core_crc16_inserter_source_valid <= 1'd0; + crc16inserter_next_state <= crc16inserter_state; + case (crc16inserter_state) + 1'd1: begin + sdcard_core_crc16_inserter_source_valid <= 1'd1; + sdcard_core_crc16_inserter_source_last <= (sdcard_core_crc16_inserter_count == 3'd7); + case (sdcard_core_crc16_inserter_count) + 1'd0: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[14]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[14]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[14]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[14]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[15]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[15]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[15]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[15]; + end + 1'd1: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[12]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[12]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[12]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[12]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[13]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[13]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[13]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[13]; + end + 2'd2: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[10]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[10]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[10]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[10]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[11]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[11]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[11]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[11]; + end + 2'd3: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[8]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[8]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[8]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[8]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[9]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[9]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[9]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[9]; + end + 3'd4: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[6]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[6]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[6]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[6]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[7]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[7]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[7]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[7]; + end + 3'd5: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[4]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[4]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[4]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[4]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[5]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[5]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[5]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[5]; + end + 3'd6: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[2]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[2]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[2]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[2]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[3]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[3]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[3]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[3]; + end + 3'd7: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[0]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[0]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[0]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[0]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[1]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[1]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[1]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[1]; + end + endcase + if ((sdcard_core_crc16_inserter_source_valid & sdcard_core_crc16_inserter_source_ready)) begin + sdcard_core_crc16_inserter_count_crc16inserter_next_value <= (sdcard_core_crc16_inserter_count + 1'd1); + sdcard_core_crc16_inserter_count_crc16inserter_next_value_ce <= 1'd1; + if (sdcard_core_crc16_inserter_source_last) begin + crc16inserter_next_state <= 1'd0; + end + end + end + default: begin + sdcard_core_crc16_inserter_count_crc16inserter_next_value <= 1'd0; + sdcard_core_crc16_inserter_count_crc16inserter_next_value_ce <= 1'd1; + sdcard_core_crc16_inserter_source_valid <= sdcard_core_crc16_inserter_sink_valid; + sdcard_core_crc16_inserter_sink_ready <= sdcard_core_crc16_inserter_source_ready; + sdcard_core_crc16_inserter_source_first <= sdcard_core_crc16_inserter_sink_first; + sdcard_core_crc16_inserter_source_payload_data <= sdcard_core_crc16_inserter_sink_payload_data; + sdcard_core_crc16_inserter_source_last <= 1'd0; + if ((sdcard_core_crc16_inserter_sink_valid & sdcard_core_crc16_inserter_sink_ready)) begin + if (sdcard_core_crc16_inserter_sink_last) begin + crc16inserter_next_state <= 1'd1; + end + end + end + endcase +end +assign sdcard_core_fifo_sink_valid = sdcard_core_sink_sink_valid1; +assign sdcard_core_sink_sink_ready1 = sdcard_core_fifo_sink_ready; +assign sdcard_core_fifo_sink_first = sdcard_core_sink_sink_first1; +assign sdcard_core_fifo_sink_last = sdcard_core_sink_sink_last1; +assign sdcard_core_fifo_sink_payload_data = sdcard_core_sink_sink_payload_data1; +assign sdcard_core_source_source_first1 = sdcard_core_fifo_source_first; +assign sdcard_core_source_source_last1 = sdcard_core_fifo_source_last; +assign sdcard_core_source_source_payload_data1 = sdcard_core_fifo_source_payload_data; +assign sdcard_core_source_source_valid1 = (sdcard_core_fifo_level >= 4'd8); +assign sdcard_core_fifo_source_ready = (sdcard_core_source_source_valid1 & sdcard_core_source_source_ready1); +assign sdcard_core_fifo_reset = ((sdcard_core_sink_sink_valid1 & sdcard_core_sink_sink_ready1) & sdcard_core_sink_sink_last1); +assign sdcard_core_fifo_syncfifo_din = {sdcard_core_fifo_fifo_in_last, sdcard_core_fifo_fifo_in_first, sdcard_core_fifo_fifo_in_payload_data}; +assign {sdcard_core_fifo_fifo_out_last, sdcard_core_fifo_fifo_out_first, sdcard_core_fifo_fifo_out_payload_data} = sdcard_core_fifo_syncfifo_dout; +assign sdcard_core_fifo_sink_ready = sdcard_core_fifo_syncfifo_writable; +assign sdcard_core_fifo_syncfifo_we = sdcard_core_fifo_sink_valid; +assign sdcard_core_fifo_fifo_in_first = sdcard_core_fifo_sink_first; +assign sdcard_core_fifo_fifo_in_last = sdcard_core_fifo_sink_last; +assign sdcard_core_fifo_fifo_in_payload_data = sdcard_core_fifo_sink_payload_data; +assign sdcard_core_fifo_source_valid = sdcard_core_fifo_syncfifo_readable; +assign sdcard_core_fifo_source_first = sdcard_core_fifo_fifo_out_first; +assign sdcard_core_fifo_source_last = sdcard_core_fifo_fifo_out_last; +assign sdcard_core_fifo_source_payload_data = sdcard_core_fifo_fifo_out_payload_data; +assign sdcard_core_fifo_syncfifo_re = sdcard_core_fifo_source_ready; +always @(*) begin + sdcard_core_fifo_wrport_adr <= 3'd0; + if (sdcard_core_fifo_replace) begin + sdcard_core_fifo_wrport_adr <= (sdcard_core_fifo_produce - 1'd1); + end else begin + sdcard_core_fifo_wrport_adr <= sdcard_core_fifo_produce; + end +end +assign sdcard_core_fifo_wrport_dat_w = sdcard_core_fifo_syncfifo_din; +assign sdcard_core_fifo_wrport_we = (sdcard_core_fifo_syncfifo_we & (sdcard_core_fifo_syncfifo_writable | sdcard_core_fifo_replace)); +assign sdcard_core_fifo_do_read = (sdcard_core_fifo_syncfifo_readable & sdcard_core_fifo_syncfifo_re); +assign sdcard_core_fifo_rdport_adr = sdcard_core_fifo_consume; +assign sdcard_core_fifo_syncfifo_dout = sdcard_core_fifo_rdport_dat_r; +assign sdcard_core_fifo_syncfifo_writable = (sdcard_core_fifo_level != 4'd8); +assign sdcard_core_fifo_syncfifo_readable = (sdcard_core_fifo_level != 1'd0); +always @(*) begin + cmdr_sink_payload_cmd_type <= 2'd0; + cmdr_sink_payload_data_type <= 2'd0; + cmdr_sink_payload_length <= 8'd0; + cmdr_sink_valid <= 1'd0; + cmdr_source_source_ready <= 1'd0; + cmdw_sink_last <= 1'd0; + cmdw_sink_payload_cmd_type <= 2'd0; + cmdw_sink_payload_data <= 8'd0; + cmdw_sink_valid <= 1'd0; + datar_sink_last <= 1'd0; + datar_sink_payload_block_length <= 10'd0; + datar_sink_valid <= 1'd0; + datar_source_source_ready <= 1'd0; + dataw_sink_first <= 1'd0; + dataw_sink_last <= 1'd0; + dataw_sink_payload_data <= 8'd0; + dataw_sink_valid <= 1'd0; + fsm_next_state <= 3'd0; + sdcard_core_cmd_count_fsm_next_value2 <= 3'd0; + sdcard_core_cmd_count_fsm_next_value_ce2 <= 1'd0; + sdcard_core_cmd_done_fsm_next_value0 <= 1'd0; + sdcard_core_cmd_done_fsm_next_value_ce0 <= 1'd0; + sdcard_core_cmd_error_fsm_next_value4 <= 1'd0; + sdcard_core_cmd_error_fsm_next_value_ce4 <= 1'd0; + sdcard_core_cmd_response_status_fsm_next_value8 <= 128'd0; + sdcard_core_cmd_response_status_fsm_next_value_ce8 <= 1'd0; + sdcard_core_cmd_timeout_fsm_next_value5 <= 1'd0; + sdcard_core_cmd_timeout_fsm_next_value_ce5 <= 1'd0; + sdcard_core_crc16_inserter_source_ready <= 1'd0; + sdcard_core_data_count_fsm_next_value3 <= 32'd0; + sdcard_core_data_count_fsm_next_value_ce3 <= 1'd0; + sdcard_core_data_done_fsm_next_value1 <= 1'd0; + sdcard_core_data_done_fsm_next_value_ce1 <= 1'd0; + sdcard_core_data_error_fsm_next_value6 <= 1'd0; + sdcard_core_data_error_fsm_next_value_ce6 <= 1'd0; + sdcard_core_data_timeout_fsm_next_value7 <= 1'd0; + sdcard_core_data_timeout_fsm_next_value_ce7 <= 1'd0; + sdcard_core_sink_sink_first1 <= 1'd0; + sdcard_core_sink_sink_last1 <= 1'd0; + sdcard_core_sink_sink_payload_data1 <= 8'd0; + sdcard_core_sink_sink_valid1 <= 1'd0; + fsm_next_state <= fsm_state; + case (fsm_state) + 1'd1: begin + cmdw_sink_valid <= 1'd1; + cmdw_sink_last <= (sdcard_core_cmd_count == 3'd5); + cmdw_sink_payload_cmd_type <= sdcard_core_cmd_type; + case (sdcard_core_cmd_count) + 1'd0: begin + cmdw_sink_payload_data <= {1'd0, 1'd1, sdcard_core_cmd}; + end + 1'd1: begin + cmdw_sink_payload_data <= sdcard_core_cmd_argument_storage[31:24]; + end + 2'd2: begin + cmdw_sink_payload_data <= sdcard_core_cmd_argument_storage[23:16]; + end + 2'd3: begin + cmdw_sink_payload_data <= sdcard_core_cmd_argument_storage[15:8]; + end + 3'd4: begin + cmdw_sink_payload_data <= sdcard_core_cmd_argument_storage[7:0]; + end + 3'd5: begin + cmdw_sink_payload_data <= {sdcard_core_crc7_inserter_crc_crc, 1'd1}; + end + endcase + if (cmdw_sink_ready) begin + sdcard_core_cmd_count_fsm_next_value2 <= (sdcard_core_cmd_count + 1'd1); + sdcard_core_cmd_count_fsm_next_value_ce2 <= 1'd1; + if (cmdw_sink_last) begin + if ((sdcard_core_cmd_type == 1'd0)) begin + fsm_next_state <= 1'd0; + end else begin + fsm_next_state <= 2'd2; + end + end + end + end + 2'd2: begin + cmdr_sink_valid <= 1'd1; + cmdr_sink_payload_cmd_type <= sdcard_core_cmd_type; + cmdr_sink_payload_data_type <= sdcard_core_data_type; + if ((sdcard_core_cmd_type == 2'd2)) begin + cmdr_sink_payload_length <= 5'd18; + end else begin + cmdr_sink_payload_length <= 3'd6; + end + cmdr_source_source_ready <= 1'd1; + if (cmdr_source_source_valid) begin + if ((cmdr_source_source_payload_status == 1'd1)) begin + sdcard_core_cmd_timeout_fsm_next_value5 <= 1'd1; + sdcard_core_cmd_timeout_fsm_next_value_ce5 <= 1'd1; + fsm_next_state <= 1'd0; + end else begin + if (cmdr_source_source_last) begin + if ((sdcard_core_data_type == 2'd2)) begin + fsm_next_state <= 2'd3; + end else begin + if ((sdcard_core_data_type == 1'd1)) begin + fsm_next_state <= 3'd4; + end else begin + fsm_next_state <= 1'd0; + end + end + end else begin + sdcard_core_cmd_response_status_fsm_next_value8 <= {sdcard_core_cmd_response_status, cmdr_source_source_payload_data}; + sdcard_core_cmd_response_status_fsm_next_value_ce8 <= 1'd1; + end + end + end + end + 2'd3: begin + dataw_sink_valid <= sdcard_core_crc16_inserter_source_valid; + sdcard_core_crc16_inserter_source_ready <= dataw_sink_ready; + dataw_sink_first <= sdcard_core_crc16_inserter_source_first; + dataw_sink_last <= sdcard_core_crc16_inserter_source_last; + dataw_sink_payload_data <= sdcard_core_crc16_inserter_source_payload_data; + if (((dataw_sink_valid & dataw_sink_ready) & dataw_sink_last)) begin + sdcard_core_data_count_fsm_next_value3 <= (sdcard_core_data_count + 1'd1); + sdcard_core_data_count_fsm_next_value_ce3 <= 1'd1; + if ((sdcard_core_data_count == (sdcard_core_block_count_storage - 1'd1))) begin + fsm_next_state <= 1'd0; + end + end + datar_source_source_ready <= 1'd1; + if (datar_source_source_valid) begin + if ((datar_source_source_payload_status != 2'd2)) begin + sdcard_core_data_error_fsm_next_value6 <= 1'd1; + sdcard_core_data_error_fsm_next_value_ce6 <= 1'd1; + end + end + end + 3'd4: begin + datar_sink_valid <= 1'd1; + datar_sink_payload_block_length <= sdcard_core_block_length_storage; + datar_sink_last <= (sdcard_core_data_count == (sdcard_core_block_count_storage - 1'd1)); + if (datar_source_source_valid) begin + if ((datar_source_source_payload_status == 1'd0)) begin + sdcard_core_sink_sink_valid1 <= datar_source_source_valid; + datar_source_source_ready <= sdcard_core_sink_sink_ready1; + sdcard_core_sink_sink_first1 <= datar_source_source_first; + sdcard_core_sink_sink_last1 <= datar_source_source_last; + sdcard_core_sink_sink_payload_data1 <= datar_source_source_payload_data; + if ((datar_source_source_last & datar_source_source_ready)) begin + sdcard_core_data_count_fsm_next_value3 <= (sdcard_core_data_count + 1'd1); + sdcard_core_data_count_fsm_next_value_ce3 <= 1'd1; + if ((sdcard_core_data_count == (sdcard_core_block_count_storage - 1'd1))) begin + fsm_next_state <= 1'd0; + end + end + end else begin + if ((datar_source_source_payload_status == 1'd1)) begin + sdcard_core_data_timeout_fsm_next_value7 <= 1'd1; + sdcard_core_data_timeout_fsm_next_value_ce7 <= 1'd1; + datar_source_source_ready <= 1'd1; + fsm_next_state <= 1'd0; + end + end + end + end + default: begin + sdcard_core_cmd_done_fsm_next_value0 <= 1'd1; + sdcard_core_cmd_done_fsm_next_value_ce0 <= 1'd1; + sdcard_core_data_done_fsm_next_value1 <= 1'd1; + sdcard_core_data_done_fsm_next_value_ce1 <= 1'd1; + sdcard_core_cmd_count_fsm_next_value2 <= 1'd0; + sdcard_core_cmd_count_fsm_next_value_ce2 <= 1'd1; + sdcard_core_data_count_fsm_next_value3 <= 1'd0; + sdcard_core_data_count_fsm_next_value_ce3 <= 1'd1; + if (sdcard_core_cmd_send_re) begin + sdcard_core_cmd_done_fsm_next_value0 <= 1'd0; + sdcard_core_cmd_done_fsm_next_value_ce0 <= 1'd1; + sdcard_core_cmd_error_fsm_next_value4 <= 1'd0; + sdcard_core_cmd_error_fsm_next_value_ce4 <= 1'd1; + sdcard_core_cmd_timeout_fsm_next_value5 <= 1'd0; + sdcard_core_cmd_timeout_fsm_next_value_ce5 <= 1'd1; + sdcard_core_data_done_fsm_next_value1 <= 1'd0; + sdcard_core_data_done_fsm_next_value_ce1 <= 1'd1; + sdcard_core_data_error_fsm_next_value6 <= 1'd0; + sdcard_core_data_error_fsm_next_value_ce6 <= 1'd1; + sdcard_core_data_timeout_fsm_next_value7 <= 1'd0; + sdcard_core_data_timeout_fsm_next_value_ce7 <= 1'd1; + fsm_next_state <= 1'd1; + end + end + endcase +end +assign sdcard_block2mem_start = (sdcard_block2mem_sink_sink_valid0 & sdcard_block2mem_sink_sink_first); +always @(*) begin + sdcard_block2mem_fifo_sink_first <= 1'd0; + sdcard_block2mem_fifo_sink_last <= 1'd0; + sdcard_block2mem_fifo_sink_payload_data <= 8'd0; + sdcard_block2mem_fifo_sink_valid <= 1'd0; + sdcard_block2mem_sink_sink_ready0 <= 1'd0; + if ((sdcard_block2mem_wishbonedmawriter_enable_storage & (sdcard_block2mem_start | sdcard_block2mem_connect))) begin + sdcard_block2mem_fifo_sink_valid <= sdcard_block2mem_sink_sink_valid0; + sdcard_block2mem_sink_sink_ready0 <= sdcard_block2mem_fifo_sink_ready; + sdcard_block2mem_fifo_sink_first <= sdcard_block2mem_sink_sink_first; + sdcard_block2mem_fifo_sink_last <= sdcard_block2mem_sink_sink_last0; + sdcard_block2mem_fifo_sink_payload_data <= sdcard_block2mem_sink_sink_payload_data0; + end else begin + sdcard_block2mem_sink_sink_ready0 <= 1'd1; + end +end +assign sdcard_block2mem_converter_sink_valid = sdcard_block2mem_fifo_source_valid; +assign sdcard_block2mem_fifo_source_ready = sdcard_block2mem_converter_sink_ready; +assign sdcard_block2mem_converter_sink_first = sdcard_block2mem_fifo_source_first; +assign sdcard_block2mem_converter_sink_last = sdcard_block2mem_fifo_source_last; +assign sdcard_block2mem_converter_sink_payload_data = sdcard_block2mem_fifo_source_payload_data; +assign sdcard_block2mem_wishbonedmawriter_sink_valid = sdcard_block2mem_source_source_valid; +assign sdcard_block2mem_source_source_ready = sdcard_block2mem_wishbonedmawriter_sink_ready; +assign sdcard_block2mem_wishbonedmawriter_sink_first = sdcard_block2mem_source_source_first; +assign sdcard_block2mem_wishbonedmawriter_sink_last = sdcard_block2mem_source_source_last; +assign sdcard_block2mem_wishbonedmawriter_sink_payload_data = sdcard_block2mem_source_source_payload_data; +assign sdcard_block2mem_fifo_syncfifo_din = {sdcard_block2mem_fifo_fifo_in_last, sdcard_block2mem_fifo_fifo_in_first, sdcard_block2mem_fifo_fifo_in_payload_data}; +assign {sdcard_block2mem_fifo_fifo_out_last, sdcard_block2mem_fifo_fifo_out_first, sdcard_block2mem_fifo_fifo_out_payload_data} = sdcard_block2mem_fifo_syncfifo_dout; +assign sdcard_block2mem_fifo_sink_ready = sdcard_block2mem_fifo_syncfifo_writable; +assign sdcard_block2mem_fifo_syncfifo_we = sdcard_block2mem_fifo_sink_valid; +assign sdcard_block2mem_fifo_fifo_in_first = sdcard_block2mem_fifo_sink_first; +assign sdcard_block2mem_fifo_fifo_in_last = sdcard_block2mem_fifo_sink_last; +assign sdcard_block2mem_fifo_fifo_in_payload_data = sdcard_block2mem_fifo_sink_payload_data; +assign sdcard_block2mem_fifo_source_valid = sdcard_block2mem_fifo_readable; +assign sdcard_block2mem_fifo_source_first = sdcard_block2mem_fifo_fifo_out_first; +assign sdcard_block2mem_fifo_source_last = sdcard_block2mem_fifo_fifo_out_last; +assign sdcard_block2mem_fifo_source_payload_data = sdcard_block2mem_fifo_fifo_out_payload_data; +assign sdcard_block2mem_fifo_re = sdcard_block2mem_fifo_source_ready; +assign sdcard_block2mem_fifo_syncfifo_re = (sdcard_block2mem_fifo_syncfifo_readable & ((~sdcard_block2mem_fifo_readable) | sdcard_block2mem_fifo_re)); +assign sdcard_block2mem_fifo_level1 = (sdcard_block2mem_fifo_level0 + sdcard_block2mem_fifo_readable); +always @(*) begin + sdcard_block2mem_fifo_wrport_adr <= 9'd0; + if (sdcard_block2mem_fifo_replace) begin + sdcard_block2mem_fifo_wrport_adr <= (sdcard_block2mem_fifo_produce - 1'd1); + end else begin + sdcard_block2mem_fifo_wrport_adr <= sdcard_block2mem_fifo_produce; + end +end +assign sdcard_block2mem_fifo_wrport_dat_w = sdcard_block2mem_fifo_syncfifo_din; +assign sdcard_block2mem_fifo_wrport_we = (sdcard_block2mem_fifo_syncfifo_we & (sdcard_block2mem_fifo_syncfifo_writable | sdcard_block2mem_fifo_replace)); +assign sdcard_block2mem_fifo_do_read = (sdcard_block2mem_fifo_syncfifo_readable & sdcard_block2mem_fifo_syncfifo_re); +assign sdcard_block2mem_fifo_rdport_adr = sdcard_block2mem_fifo_consume; +assign sdcard_block2mem_fifo_syncfifo_dout = sdcard_block2mem_fifo_rdport_dat_r; +assign sdcard_block2mem_fifo_rdport_re = sdcard_block2mem_fifo_do_read; +assign sdcard_block2mem_fifo_syncfifo_writable = (sdcard_block2mem_fifo_level0 != 10'd512); +assign sdcard_block2mem_fifo_syncfifo_readable = (sdcard_block2mem_fifo_level0 != 1'd0); +assign sdcard_block2mem_source_source_valid = sdcard_block2mem_converter_source_valid; +assign sdcard_block2mem_converter_source_ready = sdcard_block2mem_source_source_ready; +assign sdcard_block2mem_source_source_first = sdcard_block2mem_converter_source_first; +assign sdcard_block2mem_source_source_last = sdcard_block2mem_converter_source_last; +assign sdcard_block2mem_source_source_payload_data = sdcard_block2mem_converter_source_payload_data; +assign sdcard_block2mem_converter_sink_ready = ((~sdcard_block2mem_converter_strobe_all) | sdcard_block2mem_converter_source_ready); +assign sdcard_block2mem_converter_source_valid = sdcard_block2mem_converter_strobe_all; +assign sdcard_block2mem_converter_load_part = (sdcard_block2mem_converter_sink_valid & sdcard_block2mem_converter_sink_ready); +assign interface0_bus_stb = sdcard_block2mem_sink_sink_valid1; +assign interface0_bus_cyc = sdcard_block2mem_sink_sink_valid1; +assign interface0_bus_we = 1'd1; +assign interface0_bus_sel = 4'd15; +assign interface0_bus_adr = sdcard_block2mem_sink_sink_payload_address; +assign interface0_bus_dat_w = {sdcard_block2mem_sink_sink_payload_data1[7:0], sdcard_block2mem_sink_sink_payload_data1[15:8], sdcard_block2mem_sink_sink_payload_data1[23:16], sdcard_block2mem_sink_sink_payload_data1[31:24]}; +assign sdcard_block2mem_sink_sink_ready1 = interface0_bus_ack; +assign sdcard_block2mem_wishbonedmawriter_base = sdcard_block2mem_wishbonedmawriter_base_storage[63:2]; +assign sdcard_block2mem_wishbonedmawriter_length = sdcard_block2mem_wishbonedmawriter_length_storage[31:2]; +assign sdcard_block2mem_wishbonedmawriter_offset_status = sdcard_block2mem_wishbonedmawriter_offset; +assign sdcard_block2mem_wishbonedmawriter_reset = (~sdcard_block2mem_wishbonedmawriter_enable_storage); +always @(*) begin + sdblock2memdma_next_state <= 2'd0; + sdcard_block2mem_sink_sink_last1 <= 1'd0; + sdcard_block2mem_sink_sink_payload_address <= 32'd0; + sdcard_block2mem_sink_sink_payload_data1 <= 32'd0; + sdcard_block2mem_sink_sink_valid1 <= 1'd0; + sdcard_block2mem_wishbonedmawriter_done_status <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= 32'd0; + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd0; + sdcard_block2mem_wishbonedmawriter_sink_ready <= 1'd0; + sdblock2memdma_next_state <= sdblock2memdma_state; + case (sdblock2memdma_state) + 1'd1: begin + sdcard_block2mem_sink_sink_valid1 <= sdcard_block2mem_wishbonedmawriter_sink_valid; + sdcard_block2mem_sink_sink_last1 <= (sdcard_block2mem_wishbonedmawriter_sink_last | ((sdcard_block2mem_wishbonedmawriter_offset + 1'd1) == sdcard_block2mem_wishbonedmawriter_length)); + sdcard_block2mem_sink_sink_payload_address <= (sdcard_block2mem_wishbonedmawriter_base + sdcard_block2mem_wishbonedmawriter_offset); + sdcard_block2mem_sink_sink_payload_data1 <= sdcard_block2mem_wishbonedmawriter_sink_payload_data; + sdcard_block2mem_wishbonedmawriter_sink_ready <= sdcard_block2mem_sink_sink_ready1; + if ((sdcard_block2mem_wishbonedmawriter_sink_valid & sdcard_block2mem_wishbonedmawriter_sink_ready)) begin + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= (sdcard_block2mem_wishbonedmawriter_offset + 1'd1); + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd1; + if (sdcard_block2mem_sink_sink_last1) begin + if (sdcard_block2mem_wishbonedmawriter_loop_storage) begin + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd1; + end else begin + sdblock2memdma_next_state <= 2'd2; + end + end + end + end + 2'd2: begin + sdcard_block2mem_wishbonedmawriter_done_status <= 1'd1; + end + default: begin + sdcard_block2mem_wishbonedmawriter_sink_ready <= 1'd1; + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd1; + sdblock2memdma_next_state <= 1'd1; + end + endcase +end +assign sdcard_mem2block_converter_converter_sink_valid = sdcard_mem2block_dma_source_source_valid; +assign sdcard_mem2block_dma_source_source_ready = sdcard_mem2block_converter_converter_sink_ready; +assign sdcard_mem2block_converter_converter_sink_first = sdcard_mem2block_dma_source_source_first; +assign sdcard_mem2block_converter_converter_sink_last = sdcard_mem2block_dma_source_source_last; +assign sdcard_mem2block_converter_converter_sink_payload_data = sdcard_mem2block_dma_source_source_payload_data; +assign sdcard_mem2block_fifo_sink_valid = sdcard_mem2block_converter_source_source_valid; +assign sdcard_mem2block_converter_source_source_ready = sdcard_mem2block_fifo_sink_ready; +assign sdcard_mem2block_fifo_sink_first = sdcard_mem2block_converter_source_source_first; +assign sdcard_mem2block_fifo_sink_last = sdcard_mem2block_converter_source_source_last; +assign sdcard_mem2block_fifo_sink_payload_data = sdcard_mem2block_converter_source_source_payload_data; +assign sdcard_mem2block_source_source_valid = sdcard_mem2block_fifo_source_valid; +assign sdcard_mem2block_fifo_source_ready = sdcard_mem2block_source_source_ready; +assign sdcard_mem2block_source_source_first = sdcard_mem2block_fifo_source_first; +assign sdcard_mem2block_source_source_payload_data = sdcard_mem2block_fifo_source_payload_data; +always @(*) begin + sdcard_mem2block_source_source_last <= 1'd0; + sdcard_mem2block_source_source_last <= sdcard_mem2block_fifo_source_last; + if ((sdcard_mem2block_count == 9'd511)) begin + sdcard_mem2block_source_source_last <= 1'd1; + end +end +assign interface1_bus_stb = (sdcard_mem2block_dma_sink_sink_valid & sdcard_mem2block_dma_fifo_sink_ready); +assign interface1_bus_cyc = (sdcard_mem2block_dma_sink_sink_valid & sdcard_mem2block_dma_fifo_sink_ready); +assign interface1_bus_we = 1'd0; +assign interface1_bus_sel = 4'd15; +assign interface1_bus_adr = sdcard_mem2block_dma_sink_sink_payload_address; +assign sdcard_mem2block_dma_fifo_sink_last = sdcard_mem2block_dma_sink_sink_last; +assign sdcard_mem2block_dma_fifo_sink_payload_data = {interface1_bus_dat_r[7:0], interface1_bus_dat_r[15:8], interface1_bus_dat_r[23:16], interface1_bus_dat_r[31:24]}; +always @(*) begin + sdcard_mem2block_dma_fifo_sink_valid <= 1'd0; + sdcard_mem2block_dma_sink_sink_ready <= 1'd0; + if ((interface1_bus_stb & interface1_bus_ack)) begin + sdcard_mem2block_dma_sink_sink_ready <= 1'd1; + sdcard_mem2block_dma_fifo_sink_valid <= 1'd1; + end +end +assign sdcard_mem2block_dma_source_source_valid = sdcard_mem2block_dma_fifo_source_valid; +assign sdcard_mem2block_dma_fifo_source_ready = sdcard_mem2block_dma_source_source_ready; +assign sdcard_mem2block_dma_source_source_first = sdcard_mem2block_dma_fifo_source_first; +assign sdcard_mem2block_dma_source_source_last = sdcard_mem2block_dma_fifo_source_last; +assign sdcard_mem2block_dma_source_source_payload_data = sdcard_mem2block_dma_fifo_source_payload_data; +assign sdcard_mem2block_dma_base = sdcard_mem2block_dma_base_storage[63:2]; +assign sdcard_mem2block_dma_length = sdcard_mem2block_dma_length_storage[31:2]; +assign sdcard_mem2block_dma_offset_status = sdcard_mem2block_dma_offset; +assign sdcard_mem2block_dma_reset = (~sdcard_mem2block_dma_enable_storage); +assign sdcard_mem2block_dma_fifo_syncfifo_din = {sdcard_mem2block_dma_fifo_fifo_in_last, sdcard_mem2block_dma_fifo_fifo_in_first, sdcard_mem2block_dma_fifo_fifo_in_payload_data}; +assign {sdcard_mem2block_dma_fifo_fifo_out_last, sdcard_mem2block_dma_fifo_fifo_out_first, sdcard_mem2block_dma_fifo_fifo_out_payload_data} = sdcard_mem2block_dma_fifo_syncfifo_dout; +assign sdcard_mem2block_dma_fifo_sink_ready = sdcard_mem2block_dma_fifo_syncfifo_writable; +assign sdcard_mem2block_dma_fifo_syncfifo_we = sdcard_mem2block_dma_fifo_sink_valid; +assign sdcard_mem2block_dma_fifo_fifo_in_first = sdcard_mem2block_dma_fifo_sink_first; +assign sdcard_mem2block_dma_fifo_fifo_in_last = sdcard_mem2block_dma_fifo_sink_last; +assign sdcard_mem2block_dma_fifo_fifo_in_payload_data = sdcard_mem2block_dma_fifo_sink_payload_data; +assign sdcard_mem2block_dma_fifo_source_valid = sdcard_mem2block_dma_fifo_syncfifo_readable; +assign sdcard_mem2block_dma_fifo_source_first = sdcard_mem2block_dma_fifo_fifo_out_first; +assign sdcard_mem2block_dma_fifo_source_last = sdcard_mem2block_dma_fifo_fifo_out_last; +assign sdcard_mem2block_dma_fifo_source_payload_data = sdcard_mem2block_dma_fifo_fifo_out_payload_data; +assign sdcard_mem2block_dma_fifo_syncfifo_re = sdcard_mem2block_dma_fifo_source_ready; +always @(*) begin + sdcard_mem2block_dma_fifo_wrport_adr <= 4'd0; + if (sdcard_mem2block_dma_fifo_replace) begin + sdcard_mem2block_dma_fifo_wrport_adr <= (sdcard_mem2block_dma_fifo_produce - 1'd1); + end else begin + sdcard_mem2block_dma_fifo_wrport_adr <= sdcard_mem2block_dma_fifo_produce; + end +end +assign sdcard_mem2block_dma_fifo_wrport_dat_w = sdcard_mem2block_dma_fifo_syncfifo_din; +assign sdcard_mem2block_dma_fifo_wrport_we = (sdcard_mem2block_dma_fifo_syncfifo_we & (sdcard_mem2block_dma_fifo_syncfifo_writable | sdcard_mem2block_dma_fifo_replace)); +assign sdcard_mem2block_dma_fifo_do_read = (sdcard_mem2block_dma_fifo_syncfifo_readable & sdcard_mem2block_dma_fifo_syncfifo_re); +assign sdcard_mem2block_dma_fifo_rdport_adr = sdcard_mem2block_dma_fifo_consume; +assign sdcard_mem2block_dma_fifo_syncfifo_dout = sdcard_mem2block_dma_fifo_rdport_dat_r; +assign sdcard_mem2block_dma_fifo_syncfifo_writable = (sdcard_mem2block_dma_fifo_level != 5'd16); +assign sdcard_mem2block_dma_fifo_syncfifo_readable = (sdcard_mem2block_dma_fifo_level != 1'd0); +always @(*) begin + sdcard_mem2block_dma_done_status <= 1'd0; + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= 32'd0; + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd0; + sdcard_mem2block_dma_sink_sink_last <= 1'd0; + sdcard_mem2block_dma_sink_sink_payload_address <= 32'd0; + sdcard_mem2block_dma_sink_sink_valid <= 1'd0; + sdmem2blockdma_next_state <= 2'd0; + sdmem2blockdma_next_state <= sdmem2blockdma_state; + case (sdmem2blockdma_state) + 1'd1: begin + sdcard_mem2block_dma_sink_sink_valid <= 1'd1; + sdcard_mem2block_dma_sink_sink_last <= (sdcard_mem2block_dma_offset == (sdcard_mem2block_dma_length - 1'd1)); + sdcard_mem2block_dma_sink_sink_payload_address <= (sdcard_mem2block_dma_base + sdcard_mem2block_dma_offset); + if (sdcard_mem2block_dma_sink_sink_ready) begin + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= (sdcard_mem2block_dma_offset + 1'd1); + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd1; + if (sdcard_mem2block_dma_sink_sink_last) begin + if (sdcard_mem2block_dma_loop_storage) begin + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= 1'd0; + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd1; + end else begin + sdmem2blockdma_next_state <= 2'd2; + end + end + end + end + 2'd2: begin + sdcard_mem2block_dma_done_status <= 1'd1; + end + default: begin + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= 1'd0; + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd1; + sdmem2blockdma_next_state <= 1'd1; + end + endcase +end +assign sdcard_mem2block_converter_source_source_valid = sdcard_mem2block_converter_converter_source_valid; +assign sdcard_mem2block_converter_converter_source_ready = sdcard_mem2block_converter_source_source_ready; +assign sdcard_mem2block_converter_source_source_first = sdcard_mem2block_converter_converter_source_first; +assign sdcard_mem2block_converter_source_source_last = sdcard_mem2block_converter_converter_source_last; +assign sdcard_mem2block_converter_source_source_payload_data = sdcard_mem2block_converter_converter_source_payload_data; +assign sdcard_mem2block_converter_converter_first = (sdcard_mem2block_converter_converter_mux == 1'd0); +assign sdcard_mem2block_converter_converter_last = (sdcard_mem2block_converter_converter_mux == 2'd3); +assign sdcard_mem2block_converter_converter_source_valid = sdcard_mem2block_converter_converter_sink_valid; +assign sdcard_mem2block_converter_converter_source_first = (sdcard_mem2block_converter_converter_sink_first & sdcard_mem2block_converter_converter_first); +assign sdcard_mem2block_converter_converter_source_last = (sdcard_mem2block_converter_converter_sink_last & sdcard_mem2block_converter_converter_last); +assign sdcard_mem2block_converter_converter_sink_ready = (sdcard_mem2block_converter_converter_last & sdcard_mem2block_converter_converter_source_ready); +always @(*) begin + sdcard_mem2block_converter_converter_source_payload_data <= 8'd0; + case (sdcard_mem2block_converter_converter_mux) + 1'd0: begin + sdcard_mem2block_converter_converter_source_payload_data <= sdcard_mem2block_converter_converter_sink_payload_data[31:24]; + end + 1'd1: begin + sdcard_mem2block_converter_converter_source_payload_data <= sdcard_mem2block_converter_converter_sink_payload_data[23:16]; + end + 2'd2: begin + sdcard_mem2block_converter_converter_source_payload_data <= sdcard_mem2block_converter_converter_sink_payload_data[15:8]; + end + default: begin + sdcard_mem2block_converter_converter_source_payload_data <= sdcard_mem2block_converter_converter_sink_payload_data[7:0]; + end + endcase +end +assign sdcard_mem2block_converter_converter_source_payload_valid_token_count = sdcard_mem2block_converter_converter_last; +assign sdcard_mem2block_fifo_syncfifo_din = {sdcard_mem2block_fifo_fifo_in_last, sdcard_mem2block_fifo_fifo_in_first, sdcard_mem2block_fifo_fifo_in_payload_data}; +assign {sdcard_mem2block_fifo_fifo_out_last, sdcard_mem2block_fifo_fifo_out_first, sdcard_mem2block_fifo_fifo_out_payload_data} = sdcard_mem2block_fifo_syncfifo_dout; +assign sdcard_mem2block_fifo_sink_ready = sdcard_mem2block_fifo_syncfifo_writable; +assign sdcard_mem2block_fifo_syncfifo_we = sdcard_mem2block_fifo_sink_valid; +assign sdcard_mem2block_fifo_fifo_in_first = sdcard_mem2block_fifo_sink_first; +assign sdcard_mem2block_fifo_fifo_in_last = sdcard_mem2block_fifo_sink_last; +assign sdcard_mem2block_fifo_fifo_in_payload_data = sdcard_mem2block_fifo_sink_payload_data; +assign sdcard_mem2block_fifo_source_valid = sdcard_mem2block_fifo_readable; +assign sdcard_mem2block_fifo_source_first = sdcard_mem2block_fifo_fifo_out_first; +assign sdcard_mem2block_fifo_source_last = sdcard_mem2block_fifo_fifo_out_last; +assign sdcard_mem2block_fifo_source_payload_data = sdcard_mem2block_fifo_fifo_out_payload_data; +assign sdcard_mem2block_fifo_re = sdcard_mem2block_fifo_source_ready; +assign sdcard_mem2block_fifo_syncfifo_re = (sdcard_mem2block_fifo_syncfifo_readable & ((~sdcard_mem2block_fifo_readable) | sdcard_mem2block_fifo_re)); +assign sdcard_mem2block_fifo_level1 = (sdcard_mem2block_fifo_level0 + sdcard_mem2block_fifo_readable); +always @(*) begin + sdcard_mem2block_fifo_wrport_adr <= 9'd0; + if (sdcard_mem2block_fifo_replace) begin + sdcard_mem2block_fifo_wrport_adr <= (sdcard_mem2block_fifo_produce - 1'd1); + end else begin + sdcard_mem2block_fifo_wrport_adr <= sdcard_mem2block_fifo_produce; + end +end +assign sdcard_mem2block_fifo_wrport_dat_w = sdcard_mem2block_fifo_syncfifo_din; +assign sdcard_mem2block_fifo_wrport_we = (sdcard_mem2block_fifo_syncfifo_we & (sdcard_mem2block_fifo_syncfifo_writable | sdcard_mem2block_fifo_replace)); +assign sdcard_mem2block_fifo_do_read = (sdcard_mem2block_fifo_syncfifo_readable & sdcard_mem2block_fifo_syncfifo_re); +assign sdcard_mem2block_fifo_rdport_adr = sdcard_mem2block_fifo_consume; +assign sdcard_mem2block_fifo_syncfifo_dout = sdcard_mem2block_fifo_rdport_dat_r; +assign sdcard_mem2block_fifo_rdport_re = sdcard_mem2block_fifo_do_read; +assign sdcard_mem2block_fifo_syncfifo_writable = (sdcard_mem2block_fifo_level0 != 10'd512); +assign sdcard_mem2block_fifo_syncfifo_readable = (sdcard_mem2block_fifo_level0 != 1'd0); +assign eventmanager_card_detect0 = card_detect_status1; +assign eventmanager_card_detect1 = card_detect_pending; +always @(*) begin + card_detect_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[0])) begin + card_detect_clear <= 1'd1; + end +end +assign eventmanager_block2mem_dma0 = block2mem_dma_status; +assign eventmanager_block2mem_dma1 = block2mem_dma_pending; +always @(*) begin + block2mem_dma_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[1])) begin + block2mem_dma_clear <= 1'd1; + end +end +assign eventmanager_mem2block_dma0 = mem2block_dma_status; +assign eventmanager_mem2block_dma1 = mem2block_dma_pending; +always @(*) begin + mem2block_dma_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[2])) begin + mem2block_dma_clear <= 1'd1; + end +end +assign eventmanager_cmd_done0 = cmd_done_status; +assign eventmanager_cmd_done1 = cmd_done_pending; +always @(*) begin + cmd_done_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[3])) begin + cmd_done_clear <= 1'd1; + end +end +assign sdcard_irq_irq = ((((eventmanager_pending_status[0] & eventmanager_enable_storage[0]) | (eventmanager_pending_status[1] & eventmanager_enable_storage[1])) | (eventmanager_pending_status[2] & eventmanager_enable_storage[2])) | (eventmanager_pending_status[3] & eventmanager_enable_storage[3])); +assign card_detect_status1 = 1'd0; +assign block2mem_dma_status = 1'd0; +assign mem2block_dma_status = 1'd0; +assign cmd_done_status = cmd_done_trigger; +assign cmd_done_pending = cmd_done_trigger; +always @(*) begin + interface0_ack <= 1'd0; + interface0_dat_r <= 32'd0; + interface1_adr <= 14'd0; + interface1_dat_w <= 32'd0; + interface1_we <= 1'd0; + wishbone2csr_next_state <= 1'd0; + wishbone2csr_next_state <= wishbone2csr_state; + case (wishbone2csr_state) + 1'd1: begin + interface0_ack <= 1'd1; + interface0_dat_r <= interface1_dat_r; + wishbone2csr_next_state <= 1'd0; + end + default: begin + interface1_dat_w <= interface0_dat_w; + if ((interface0_cyc & interface0_stb)) begin + interface1_adr <= interface0_adr[29:0]; + interface1_we <= (interface0_we & (interface0_sel != 1'd0)); + wishbone2csr_next_state <= 1'd1; + end + end + endcase +end +assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); +assign csrbank0_reset0_r = interface0_bank_bus_dat_w[1:0]; +always @(*) begin + csrbank0_reset0_re <= 1'd0; + csrbank0_reset0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_reset0_re <= interface0_bank_bus_we; + csrbank0_reset0_we <= (~interface0_bank_bus_we); + end +end +assign csrbank0_scratch0_r = interface0_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank0_scratch0_re <= 1'd0; + csrbank0_scratch0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_scratch0_re <= interface0_bank_bus_we; + csrbank0_scratch0_we <= (~interface0_bank_bus_we); + end +end +assign csrbank0_bus_errors_r = interface0_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank0_bus_errors_re <= 1'd0; + csrbank0_bus_errors_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 2'd2))) begin + csrbank0_bus_errors_re <= interface0_bank_bus_we; + csrbank0_bus_errors_we <= (~interface0_bank_bus_we); + end +end +always @(*) begin + soc_rst <= 1'd0; + if (reset_re) begin + soc_rst <= reset_storage[0]; + end +end +assign cpu_rst = reset_storage[1]; +assign csrbank0_reset0_w = reset_storage[1:0]; +assign csrbank0_scratch0_w = scratch_storage[31:0]; +assign csrbank0_bus_errors_w = bus_errors_status[31:0]; +assign bus_errors_we = csrbank0_bus_errors_we; +assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); +assign csrbank1_dma_base1_r = interface1_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank1_dma_base1_re <= 1'd0; + csrbank1_dma_base1_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_dma_base1_re <= interface1_bank_bus_we; + csrbank1_dma_base1_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_base0_r = interface1_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank1_dma_base0_re <= 1'd0; + csrbank1_dma_base0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + csrbank1_dma_base0_re <= interface1_bank_bus_we; + csrbank1_dma_base0_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_length0_r = interface1_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank1_dma_length0_re <= 1'd0; + csrbank1_dma_length0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + csrbank1_dma_length0_re <= interface1_bank_bus_we; + csrbank1_dma_length0_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_enable0_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + csrbank1_dma_enable0_re <= 1'd0; + csrbank1_dma_enable0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + csrbank1_dma_enable0_re <= interface1_bank_bus_we; + csrbank1_dma_enable0_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_done_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + csrbank1_dma_done_re <= 1'd0; + csrbank1_dma_done_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + csrbank1_dma_done_re <= interface1_bank_bus_we; + csrbank1_dma_done_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_loop0_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + csrbank1_dma_loop0_re <= 1'd0; + csrbank1_dma_loop0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + csrbank1_dma_loop0_re <= interface1_bank_bus_we; + csrbank1_dma_loop0_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_offset_r = interface1_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank1_dma_offset_re <= 1'd0; + csrbank1_dma_offset_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + csrbank1_dma_offset_re <= interface1_bank_bus_we; + csrbank1_dma_offset_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_base1_w = sdcard_block2mem_wishbonedmawriter_base_storage[63:32]; +assign csrbank1_dma_base0_w = sdcard_block2mem_wishbonedmawriter_base_storage[31:0]; +assign csrbank1_dma_length0_w = sdcard_block2mem_wishbonedmawriter_length_storage[31:0]; +assign csrbank1_dma_enable0_w = sdcard_block2mem_wishbonedmawriter_enable_storage; +assign csrbank1_dma_done_w = sdcard_block2mem_wishbonedmawriter_done_status; +assign sdcard_block2mem_wishbonedmawriter_done_we = csrbank1_dma_done_we; +assign csrbank1_dma_loop0_w = sdcard_block2mem_wishbonedmawriter_loop_storage; +assign csrbank1_dma_offset_w = sdcard_block2mem_wishbonedmawriter_offset_status[31:0]; +assign sdcard_block2mem_wishbonedmawriter_offset_we = csrbank1_dma_offset_we; +assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); +assign csrbank2_cmd_argument0_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_cmd_argument0_re <= 1'd0; + csrbank2_cmd_argument0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_cmd_argument0_re <= interface2_bank_bus_we; + csrbank2_cmd_argument0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_command0_r = interface2_bank_bus_dat_w[13:0]; +always @(*) begin + csrbank2_cmd_command0_re <= 1'd0; + csrbank2_cmd_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_cmd_command0_re <= interface2_bank_bus_we; + csrbank2_cmd_command0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_send0_r = interface2_bank_bus_dat_w[0]; +always @(*) begin + csrbank2_cmd_send0_re <= 1'd0; + csrbank2_cmd_send0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + csrbank2_cmd_send0_re <= interface2_bank_bus_we; + csrbank2_cmd_send0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_response3_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_cmd_response3_re <= 1'd0; + csrbank2_cmd_response3_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin + csrbank2_cmd_response3_re <= interface2_bank_bus_we; + csrbank2_cmd_response3_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_response2_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_cmd_response2_re <= 1'd0; + csrbank2_cmd_response2_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin + csrbank2_cmd_response2_re <= interface2_bank_bus_we; + csrbank2_cmd_response2_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_response1_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_cmd_response1_re <= 1'd0; + csrbank2_cmd_response1_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin + csrbank2_cmd_response1_re <= interface2_bank_bus_we; + csrbank2_cmd_response1_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_response0_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_cmd_response0_re <= 1'd0; + csrbank2_cmd_response0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin + csrbank2_cmd_response0_re <= interface2_bank_bus_we; + csrbank2_cmd_response0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_event_r = interface2_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank2_cmd_event_re <= 1'd0; + csrbank2_cmd_event_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin + csrbank2_cmd_event_re <= interface2_bank_bus_we; + csrbank2_cmd_event_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_data_event_r = interface2_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank2_data_event_re <= 1'd0; + csrbank2_data_event_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin + csrbank2_data_event_re <= interface2_bank_bus_we; + csrbank2_data_event_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_block_length0_r = interface2_bank_bus_dat_w[9:0]; +always @(*) begin + csrbank2_block_length0_re <= 1'd0; + csrbank2_block_length0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin + csrbank2_block_length0_re <= interface2_bank_bus_we; + csrbank2_block_length0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_block_count0_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_block_count0_re <= 1'd0; + csrbank2_block_count0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin + csrbank2_block_count0_re <= interface2_bank_bus_we; + csrbank2_block_count0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_argument0_w = sdcard_core_cmd_argument_storage[31:0]; +assign sdcard_core_csrfield_cmd_type = sdcard_core_cmd_command_storage[1:0]; +assign sdcard_core_csrfield_data_type = sdcard_core_cmd_command_storage[6:5]; +assign sdcard_core_csrfield_cmd = sdcard_core_cmd_command_storage[13:8]; +assign csrbank2_cmd_command0_w = sdcard_core_cmd_command_storage[13:0]; +assign csrbank2_cmd_send0_w = sdcard_core_cmd_send_storage; +assign csrbank2_cmd_response3_w = sdcard_core_cmd_response_status[127:96]; +assign csrbank2_cmd_response2_w = sdcard_core_cmd_response_status[95:64]; +assign csrbank2_cmd_response1_w = sdcard_core_cmd_response_status[63:32]; +assign csrbank2_cmd_response0_w = sdcard_core_cmd_response_status[31:0]; +assign sdcard_core_cmd_response_we = csrbank2_cmd_response0_we; +always @(*) begin + sdcard_core_cmd_event_status <= 4'd0; + sdcard_core_cmd_event_status[0] <= sdcard_core_csrfield_done0; + sdcard_core_cmd_event_status[1] <= sdcard_core_csrfield_error0; + sdcard_core_cmd_event_status[2] <= sdcard_core_csrfield_timeout0; + sdcard_core_cmd_event_status[3] <= sdcard_core_csrfield_crc0; +end +assign csrbank2_cmd_event_w = sdcard_core_cmd_event_status[3:0]; +assign sdcard_core_cmd_event_we = csrbank2_cmd_event_we; +always @(*) begin + sdcard_core_data_event_status <= 4'd0; + sdcard_core_data_event_status[0] <= sdcard_core_csrfield_done1; + sdcard_core_data_event_status[1] <= sdcard_core_csrfield_error1; + sdcard_core_data_event_status[2] <= sdcard_core_csrfield_timeout1; + sdcard_core_data_event_status[3] <= sdcard_core_csrfield_crc1; +end +assign csrbank2_data_event_w = sdcard_core_data_event_status[3:0]; +assign sdcard_core_data_event_we = csrbank2_data_event_we; +assign csrbank2_block_length0_w = sdcard_core_block_length_storage[9:0]; +assign csrbank2_block_count0_w = sdcard_core_block_count_storage[31:0]; +assign csrbank3_sel = (interface3_bank_bus_adr[13:9] == 2'd3); +assign csrbank3_status_r = interface3_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank3_status_re <= 1'd0; + csrbank3_status_we <= 1'd0; + if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 1'd0))) begin + csrbank3_status_re <= interface3_bank_bus_we; + csrbank3_status_we <= (~interface3_bank_bus_we); + end +end +assign csrbank3_pending_r = interface3_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank3_pending_re <= 1'd0; + csrbank3_pending_we <= 1'd0; + if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 1'd1))) begin + csrbank3_pending_re <= interface3_bank_bus_we; + csrbank3_pending_we <= (~interface3_bank_bus_we); + end +end +assign csrbank3_enable0_r = interface3_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank3_enable0_re <= 1'd0; + csrbank3_enable0_we <= 1'd0; + if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 2'd2))) begin + csrbank3_enable0_re <= interface3_bank_bus_we; + csrbank3_enable0_we <= (~interface3_bank_bus_we); + end +end +always @(*) begin + eventmanager_status_status <= 4'd0; + eventmanager_status_status[0] <= eventmanager_card_detect0; + eventmanager_status_status[1] <= eventmanager_block2mem_dma0; + eventmanager_status_status[2] <= eventmanager_mem2block_dma0; + eventmanager_status_status[3] <= eventmanager_cmd_done0; +end +assign csrbank3_status_w = eventmanager_status_status[3:0]; +assign eventmanager_status_we = csrbank3_status_we; +always @(*) begin + eventmanager_pending_status <= 4'd0; + eventmanager_pending_status[0] <= eventmanager_card_detect1; + eventmanager_pending_status[1] <= eventmanager_block2mem_dma1; + eventmanager_pending_status[2] <= eventmanager_mem2block_dma1; + eventmanager_pending_status[3] <= eventmanager_cmd_done1; +end +assign csrbank3_pending_w = eventmanager_pending_status[3:0]; +assign eventmanager_pending_we = csrbank3_pending_we; +assign eventmanager_card_detect2 = eventmanager_enable_storage[0]; +assign eventmanager_block2mem_dma2 = eventmanager_enable_storage[1]; +assign eventmanager_mem2block_dma2 = eventmanager_enable_storage[2]; +assign eventmanager_cmd_done2 = eventmanager_enable_storage[3]; +assign csrbank3_enable0_w = eventmanager_enable_storage[3:0]; +assign csrbank4_sel = (interface4_bank_bus_adr[13:9] == 3'd4); +assign csrbank4_dma_base1_r = interface4_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank4_dma_base1_re <= 1'd0; + csrbank4_dma_base1_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 1'd0))) begin + csrbank4_dma_base1_re <= interface4_bank_bus_we; + csrbank4_dma_base1_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_base0_r = interface4_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank4_dma_base0_re <= 1'd0; + csrbank4_dma_base0_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 1'd1))) begin + csrbank4_dma_base0_re <= interface4_bank_bus_we; + csrbank4_dma_base0_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_length0_r = interface4_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank4_dma_length0_re <= 1'd0; + csrbank4_dma_length0_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 2'd2))) begin + csrbank4_dma_length0_re <= interface4_bank_bus_we; + csrbank4_dma_length0_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_enable0_r = interface4_bank_bus_dat_w[0]; +always @(*) begin + csrbank4_dma_enable0_re <= 1'd0; + csrbank4_dma_enable0_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 2'd3))) begin + csrbank4_dma_enable0_re <= interface4_bank_bus_we; + csrbank4_dma_enable0_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_done_r = interface4_bank_bus_dat_w[0]; +always @(*) begin + csrbank4_dma_done_re <= 1'd0; + csrbank4_dma_done_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd4))) begin + csrbank4_dma_done_re <= interface4_bank_bus_we; + csrbank4_dma_done_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_loop0_r = interface4_bank_bus_dat_w[0]; +always @(*) begin + csrbank4_dma_loop0_re <= 1'd0; + csrbank4_dma_loop0_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd5))) begin + csrbank4_dma_loop0_re <= interface4_bank_bus_we; + csrbank4_dma_loop0_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_offset_r = interface4_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank4_dma_offset_re <= 1'd0; + csrbank4_dma_offset_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd6))) begin + csrbank4_dma_offset_re <= interface4_bank_bus_we; + csrbank4_dma_offset_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_base1_w = sdcard_mem2block_dma_base_storage[63:32]; +assign csrbank4_dma_base0_w = sdcard_mem2block_dma_base_storage[31:0]; +assign csrbank4_dma_length0_w = sdcard_mem2block_dma_length_storage[31:0]; +assign csrbank4_dma_enable0_w = sdcard_mem2block_dma_enable_storage; +assign csrbank4_dma_done_w = sdcard_mem2block_dma_done_status; +assign sdcard_mem2block_dma_done_we = csrbank4_dma_done_we; +assign csrbank4_dma_loop0_w = sdcard_mem2block_dma_loop_storage; +assign csrbank4_dma_offset_w = sdcard_mem2block_dma_offset_status[31:0]; +assign sdcard_mem2block_dma_offset_we = csrbank4_dma_offset_we; +assign csrbank5_sel = (interface5_bank_bus_adr[13:9] == 3'd5); +assign csrbank5_card_detect_r = interface5_bank_bus_dat_w[0]; +always @(*) begin + csrbank5_card_detect_re <= 1'd0; + csrbank5_card_detect_we <= 1'd0; + if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 1'd0))) begin + csrbank5_card_detect_re <= interface5_bank_bus_we; + csrbank5_card_detect_we <= (~interface5_bank_bus_we); + end +end +assign csrbank5_clocker_divider0_r = interface5_bank_bus_dat_w[8:0]; +always @(*) begin + csrbank5_clocker_divider0_re <= 1'd0; + csrbank5_clocker_divider0_we <= 1'd0; + if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 1'd1))) begin + csrbank5_clocker_divider0_re <= interface5_bank_bus_we; + csrbank5_clocker_divider0_we <= (~interface5_bank_bus_we); + end +end +assign init_initialize_r = interface5_bank_bus_dat_w[0]; +always @(*) begin + init_initialize_re <= 1'd0; + init_initialize_we <= 1'd0; + if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 2'd2))) begin + init_initialize_re <= interface5_bank_bus_we; + init_initialize_we <= (~interface5_bank_bus_we); + end +end +assign csrbank5_dataw_status_r = interface5_bank_bus_dat_w[2:0]; +always @(*) begin + csrbank5_dataw_status_re <= 1'd0; + csrbank5_dataw_status_we <= 1'd0; + if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 2'd3))) begin + csrbank5_dataw_status_re <= interface5_bank_bus_we; + csrbank5_dataw_status_we <= (~interface5_bank_bus_we); + end +end +assign csrbank5_card_detect_w = card_detect_status0; +assign card_detect_we = csrbank5_card_detect_we; +assign csrbank5_clocker_divider0_w = clocker_storage[8:0]; +always @(*) begin + dataw_status <= 3'd0; + dataw_status[0] <= dataw_accepted0; + dataw_status[1] <= dataw_crc_error0; + dataw_status[2] <= dataw_write_error0; +end +assign csrbank5_dataw_status_w = dataw_status[2:0]; +assign dataw_we = csrbank5_dataw_status_we; +assign adr = interface1_adr; +assign we = interface1_we; +assign dat_w = interface1_dat_w; +assign interface1_dat_r = dat_r; +assign interface0_bank_bus_adr = adr; +assign interface1_bank_bus_adr = adr; +assign interface2_bank_bus_adr = adr; +assign interface3_bank_bus_adr = adr; +assign interface4_bank_bus_adr = adr; +assign interface5_bank_bus_adr = adr; +assign interface0_bank_bus_we = we; +assign interface1_bank_bus_we = we; +assign interface2_bank_bus_we = we; +assign interface3_bank_bus_we = we; +assign interface4_bank_bus_we = we; +assign interface5_bank_bus_we = we; +assign interface0_bank_bus_dat_w = dat_w; +assign interface1_bank_bus_dat_w = dat_w; +assign interface2_bank_bus_dat_w = dat_w; +assign interface3_bank_bus_dat_w = dat_w; +assign interface4_bank_bus_dat_w = dat_w; +assign interface5_bank_bus_dat_w = dat_w; +assign dat_r = (((((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r) | interface3_bank_bus_dat_r) | interface4_bank_bus_dat_r) | interface5_bank_bus_dat_r); +always @(*) begin + self0 <= 32'd0; + case (grant) + 1'd0: begin + self0 <= interface0_bus_adr; + end + default: begin + self0 <= interface1_bus_adr; + end + endcase +end +always @(*) begin + self1 <= 32'd0; + case (grant) + 1'd0: begin + self1 <= interface0_bus_dat_w; + end + default: begin + self1 <= interface1_bus_dat_w; + end + endcase +end +always @(*) begin + self2 <= 4'd0; + case (grant) + 1'd0: begin + self2 <= interface0_bus_sel; + end + default: begin + self2 <= interface1_bus_sel; + end + endcase +end +always @(*) begin + self3 <= 1'd0; + case (grant) + 1'd0: begin + self3 <= interface0_bus_cyc; + end + default: begin + self3 <= interface1_bus_cyc; + end + endcase +end +always @(*) begin + self4 <= 1'd0; + case (grant) + 1'd0: begin + self4 <= interface0_bus_stb; + end + default: begin + self4 <= interface1_bus_stb; + end + endcase +end +always @(*) begin + self5 <= 1'd0; + case (grant) + 1'd0: begin + self5 <= interface0_bus_we; + end + default: begin + self5 <= interface1_bus_we; + end + endcase +end +always @(*) begin + self6 <= 3'd0; + case (grant) + 1'd0: begin + self6 <= interface0_bus_cti; + end + default: begin + self6 <= interface1_bus_cti; + end + endcase +end +always @(*) begin + self7 <= 2'd0; + case (grant) + 1'd0: begin + self7 <= interface0_bus_bte; + end + default: begin + self7 <= interface1_bus_bte; + end + endcase +end +assign sdrio_clk = sys_clk; +assign sdrio_clk_1 = sys_clk; +assign sdrio_clk_2 = sys_clk; +assign sdrio_clk_3 = sys_clk; +assign sdrio_clk_4 = sys_clk; + + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + +always @(posedge por_clk) begin + int_rst <= rst; +end + +always @(posedge sdrio_clk) begin + inferedsdrtristate0_oe <= sdpads_cmd_oe; + inferedsdrtristate1_oe <= sdpads_data_oe; + inferedsdrtristate2_oe <= sdpads_data_oe; + inferedsdrtristate3_oe <= sdpads_data_oe; + inferedsdrtristate4_oe <= sdpads_data_oe; +end + +always @(posedge sys_clk) begin + if ((bus_errors != 32'd4294967295)) begin + if (bus_error) begin + bus_errors <= (bus_errors + 1'd1); + end + end + case (grant) + 1'd0: begin + if ((~request[0])) begin + if (request[1]) begin + grant <= 1'd1; + end + end + end + 1'd1: begin + if ((~request[1])) begin + if (request[0]) begin + grant <= 1'd0; + end + end + end + endcase + slave_sel_r <= slave_sel; + if (wait_1) begin + if ((~done)) begin + count <= (count - 1'd1); + end + end else begin + count <= 20'd1000000; + end + card_detect_d <= card_detect_status0; + card_detect_irq <= (card_detect_status0 ^ card_detect_d); + if ((~clocker_stop)) begin + clocker_clks <= (clocker_clks + 1'd1); + end + clocker_clk_d <= clocker_clk1; + if (clocker_clk_d) begin + clocker_ce_delayed <= clocker_clk_en; + end + sdphyinit_state <= sdphyinit_next_state; + if (init_count_sdphyinit_next_value_ce) begin + init_count <= init_count_sdphyinit_next_value; + end + sdphycmdw_state <= sdphycmdw_next_state; + if (cmdw_count_sdphycmdw_next_value_ce) begin + cmdw_count <= cmdw_count_sdphycmdw_next_value; + end + if (cmdr_cmdr_pads_in_valid) begin + cmdr_cmdr_run <= (cmdr_cmdr_start | cmdr_cmdr_run); + end + if (cmdr_cmdr_converter_converter_source_ready) begin + cmdr_cmdr_converter_converter_strobe_all <= 1'd0; + end + if (cmdr_cmdr_converter_converter_load_part) begin + if (((cmdr_cmdr_converter_converter_demux == 3'd7) | cmdr_cmdr_converter_converter_sink_last)) begin + cmdr_cmdr_converter_converter_demux <= 1'd0; + cmdr_cmdr_converter_converter_strobe_all <= 1'd1; + end else begin + cmdr_cmdr_converter_converter_demux <= (cmdr_cmdr_converter_converter_demux + 1'd1); + end + end + if ((cmdr_cmdr_converter_converter_source_valid & cmdr_cmdr_converter_converter_source_ready)) begin + if ((cmdr_cmdr_converter_converter_sink_valid & cmdr_cmdr_converter_converter_sink_ready)) begin + cmdr_cmdr_converter_converter_source_first <= cmdr_cmdr_converter_converter_sink_first; + cmdr_cmdr_converter_converter_source_last <= cmdr_cmdr_converter_converter_sink_last; + end else begin + cmdr_cmdr_converter_converter_source_first <= 1'd0; + cmdr_cmdr_converter_converter_source_last <= 1'd0; + end + end else begin + if ((cmdr_cmdr_converter_converter_sink_valid & cmdr_cmdr_converter_converter_sink_ready)) begin + cmdr_cmdr_converter_converter_source_first <= (cmdr_cmdr_converter_converter_sink_first | cmdr_cmdr_converter_converter_source_first); + cmdr_cmdr_converter_converter_source_last <= (cmdr_cmdr_converter_converter_sink_last | cmdr_cmdr_converter_converter_source_last); + end + end + if (cmdr_cmdr_converter_converter_load_part) begin + case (cmdr_cmdr_converter_converter_demux) + 1'd0: begin + cmdr_cmdr_converter_converter_source_payload_data[7] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 1'd1: begin + cmdr_cmdr_converter_converter_source_payload_data[6] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 2'd2: begin + cmdr_cmdr_converter_converter_source_payload_data[5] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 2'd3: begin + cmdr_cmdr_converter_converter_source_payload_data[4] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 3'd4: begin + cmdr_cmdr_converter_converter_source_payload_data[3] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 3'd5: begin + cmdr_cmdr_converter_converter_source_payload_data[2] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 3'd6: begin + cmdr_cmdr_converter_converter_source_payload_data[1] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 3'd7: begin + cmdr_cmdr_converter_converter_source_payload_data[0] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + endcase + end + if (cmdr_cmdr_converter_converter_load_part) begin + cmdr_cmdr_converter_converter_source_payload_valid_token_count <= (cmdr_cmdr_converter_converter_demux + 1'd1); + end + if (((~cmdr_cmdr_buf_pipe_valid_source_valid) | cmdr_cmdr_buf_pipe_valid_source_ready)) begin + cmdr_cmdr_buf_pipe_valid_source_valid <= cmdr_cmdr_buf_pipe_valid_sink_valid; + cmdr_cmdr_buf_pipe_valid_source_first <= cmdr_cmdr_buf_pipe_valid_sink_first; + cmdr_cmdr_buf_pipe_valid_source_last <= cmdr_cmdr_buf_pipe_valid_sink_last; + cmdr_cmdr_buf_pipe_valid_source_payload_data <= cmdr_cmdr_buf_pipe_valid_sink_payload_data; + end + if (cmdr_cmdr_reset) begin + cmdr_cmdr_run <= 1'd0; + cmdr_cmdr_converter_converter_source_payload_data <= 8'd0; + cmdr_cmdr_converter_converter_source_payload_valid_token_count <= 4'd0; + cmdr_cmdr_converter_converter_demux <= 3'd0; + cmdr_cmdr_converter_converter_strobe_all <= 1'd0; + cmdr_cmdr_buf_pipe_valid_source_valid <= 1'd0; + cmdr_cmdr_buf_pipe_valid_source_payload_data <= 8'd0; + end + sdphycmdr_state <= sdphycmdr_next_state; + if (cmdr_timeout_sdphycmdr_next_value_ce0) begin + cmdr_timeout <= cmdr_timeout_sdphycmdr_next_value0; + end + if (cmdr_count_sdphycmdr_next_value_ce1) begin + cmdr_count <= cmdr_count_sdphycmdr_next_value1; + end + if (cmdr_busy_sdphycmdr_next_value_ce2) begin + cmdr_busy <= cmdr_busy_sdphycmdr_next_value2; + end + if (cmdr_cmdr_reset_sdphycmdr_next_value_ce3) begin + cmdr_cmdr_reset <= cmdr_cmdr_reset_sdphycmdr_next_value3; + end + if (dataw_crc_pads_in_valid) begin + dataw_crc_run <= (dataw_crc_start | dataw_crc_run); + end + if (dataw_crc_converter_converter_source_ready) begin + dataw_crc_converter_converter_strobe_all <= 1'd0; + end + if (dataw_crc_converter_converter_load_part) begin + if (((dataw_crc_converter_converter_demux == 3'd7) | dataw_crc_converter_converter_sink_last)) begin + dataw_crc_converter_converter_demux <= 1'd0; + dataw_crc_converter_converter_strobe_all <= 1'd1; + end else begin + dataw_crc_converter_converter_demux <= (dataw_crc_converter_converter_demux + 1'd1); + end + end + if ((dataw_crc_converter_converter_source_valid & dataw_crc_converter_converter_source_ready)) begin + if ((dataw_crc_converter_converter_sink_valid & dataw_crc_converter_converter_sink_ready)) begin + dataw_crc_converter_converter_source_first <= dataw_crc_converter_converter_sink_first; + dataw_crc_converter_converter_source_last <= dataw_crc_converter_converter_sink_last; + end else begin + dataw_crc_converter_converter_source_first <= 1'd0; + dataw_crc_converter_converter_source_last <= 1'd0; + end + end else begin + if ((dataw_crc_converter_converter_sink_valid & dataw_crc_converter_converter_sink_ready)) begin + dataw_crc_converter_converter_source_first <= (dataw_crc_converter_converter_sink_first | dataw_crc_converter_converter_source_first); + dataw_crc_converter_converter_source_last <= (dataw_crc_converter_converter_sink_last | dataw_crc_converter_converter_source_last); + end + end + if (dataw_crc_converter_converter_load_part) begin + case (dataw_crc_converter_converter_demux) + 1'd0: begin + dataw_crc_converter_converter_source_payload_data[7] <= dataw_crc_converter_converter_sink_payload_data; + end + 1'd1: begin + dataw_crc_converter_converter_source_payload_data[6] <= dataw_crc_converter_converter_sink_payload_data; + end + 2'd2: begin + dataw_crc_converter_converter_source_payload_data[5] <= dataw_crc_converter_converter_sink_payload_data; + end + 2'd3: begin + dataw_crc_converter_converter_source_payload_data[4] <= dataw_crc_converter_converter_sink_payload_data; + end + 3'd4: begin + dataw_crc_converter_converter_source_payload_data[3] <= dataw_crc_converter_converter_sink_payload_data; + end + 3'd5: begin + dataw_crc_converter_converter_source_payload_data[2] <= dataw_crc_converter_converter_sink_payload_data; + end + 3'd6: begin + dataw_crc_converter_converter_source_payload_data[1] <= dataw_crc_converter_converter_sink_payload_data; + end + 3'd7: begin + dataw_crc_converter_converter_source_payload_data[0] <= dataw_crc_converter_converter_sink_payload_data; + end + endcase + end + if (dataw_crc_converter_converter_load_part) begin + dataw_crc_converter_converter_source_payload_valid_token_count <= (dataw_crc_converter_converter_demux + 1'd1); + end + if (((~dataw_crc_buf_pipe_valid_source_valid) | dataw_crc_buf_pipe_valid_source_ready)) begin + dataw_crc_buf_pipe_valid_source_valid <= dataw_crc_buf_pipe_valid_sink_valid; + dataw_crc_buf_pipe_valid_source_first <= dataw_crc_buf_pipe_valid_sink_first; + dataw_crc_buf_pipe_valid_source_last <= dataw_crc_buf_pipe_valid_sink_last; + dataw_crc_buf_pipe_valid_source_payload_data <= dataw_crc_buf_pipe_valid_sink_payload_data; + end + if (dataw_crc_reset) begin + dataw_crc_run <= 1'd0; + dataw_crc_converter_converter_source_payload_data <= 8'd0; + dataw_crc_converter_converter_source_payload_valid_token_count <= 4'd0; + dataw_crc_converter_converter_demux <= 3'd0; + dataw_crc_converter_converter_strobe_all <= 1'd0; + dataw_crc_buf_pipe_valid_source_valid <= 1'd0; + dataw_crc_buf_pipe_valid_source_payload_data <= 8'd0; + end + sdphydataw_state <= sdphydataw_next_state; + if (dataw_accepted1_sdphydataw_next_value_ce0) begin + dataw_accepted1 <= dataw_accepted1_sdphydataw_next_value0; + end + if (dataw_crc_error1_sdphydataw_next_value_ce1) begin + dataw_crc_error1 <= dataw_crc_error1_sdphydataw_next_value1; + end + if (dataw_write_error1_sdphydataw_next_value_ce2) begin + dataw_write_error1 <= dataw_write_error1_sdphydataw_next_value2; + end + if (dataw_count_sdphydataw_next_value_ce3) begin + dataw_count <= dataw_count_sdphydataw_next_value3; + end + if (datar_datar_pads_in_valid) begin + datar_datar_run <= (datar_datar_start | datar_datar_run); + end + if (datar_datar_converter_converter_source_ready) begin + datar_datar_converter_converter_strobe_all <= 1'd0; + end + if (datar_datar_converter_converter_load_part) begin + if (((datar_datar_converter_converter_demux == 1'd1) | datar_datar_converter_converter_sink_last)) begin + datar_datar_converter_converter_demux <= 1'd0; + datar_datar_converter_converter_strobe_all <= 1'd1; + end else begin + datar_datar_converter_converter_demux <= (datar_datar_converter_converter_demux + 1'd1); + end + end + if ((datar_datar_converter_converter_source_valid & datar_datar_converter_converter_source_ready)) begin + if ((datar_datar_converter_converter_sink_valid & datar_datar_converter_converter_sink_ready)) begin + datar_datar_converter_converter_source_first <= datar_datar_converter_converter_sink_first; + datar_datar_converter_converter_source_last <= datar_datar_converter_converter_sink_last; + end else begin + datar_datar_converter_converter_source_first <= 1'd0; + datar_datar_converter_converter_source_last <= 1'd0; + end + end else begin + if ((datar_datar_converter_converter_sink_valid & datar_datar_converter_converter_sink_ready)) begin + datar_datar_converter_converter_source_first <= (datar_datar_converter_converter_sink_first | datar_datar_converter_converter_source_first); + datar_datar_converter_converter_source_last <= (datar_datar_converter_converter_sink_last | datar_datar_converter_converter_source_last); + end + end + if (datar_datar_converter_converter_load_part) begin + case (datar_datar_converter_converter_demux) + 1'd0: begin + datar_datar_converter_converter_source_payload_data[7:4] <= datar_datar_converter_converter_sink_payload_data; + end + 1'd1: begin + datar_datar_converter_converter_source_payload_data[3:0] <= datar_datar_converter_converter_sink_payload_data; + end + endcase + end + if (datar_datar_converter_converter_load_part) begin + datar_datar_converter_converter_source_payload_valid_token_count <= (datar_datar_converter_converter_demux + 1'd1); + end + if (((~datar_datar_buf_pipe_valid_source_valid) | datar_datar_buf_pipe_valid_source_ready)) begin + datar_datar_buf_pipe_valid_source_valid <= datar_datar_buf_pipe_valid_sink_valid; + datar_datar_buf_pipe_valid_source_first <= datar_datar_buf_pipe_valid_sink_first; + datar_datar_buf_pipe_valid_source_last <= datar_datar_buf_pipe_valid_sink_last; + datar_datar_buf_pipe_valid_source_payload_data <= datar_datar_buf_pipe_valid_sink_payload_data; + end + if (datar_datar_reset) begin + datar_datar_run <= 1'd0; + datar_datar_converter_converter_source_payload_data <= 8'd0; + datar_datar_converter_converter_source_payload_valid_token_count <= 2'd0; + datar_datar_converter_converter_demux <= 1'd0; + datar_datar_converter_converter_strobe_all <= 1'd0; + datar_datar_buf_pipe_valid_source_valid <= 1'd0; + datar_datar_buf_pipe_valid_source_payload_data <= 8'd0; + end + sdphydatar_state <= sdphydatar_next_state; + if (datar_count_sdphydatar_next_value_ce0) begin + datar_count <= datar_count_sdphydatar_next_value0; + end + if (datar_timeout_sdphydatar_next_value_ce1) begin + datar_timeout <= datar_timeout_sdphydatar_next_value1; + end + if (datar_datar_reset_sdphydatar_next_value_ce2) begin + datar_datar_reset <= datar_datar_reset_sdphydatar_next_value2; + end + clocker_clk_delay <= {clocker_clk_delay, clocker_clk0}; + sdpads_data_i_ce <= (clocker_clk_delay[1] & (~clocker_clk_delay[0])); + sdcard_core_done_d <= sdcard_core_cmd_done; + sdcard_core_irq <= (sdcard_core_cmd_done & (~sdcard_core_done_d)); + if (sdcard_core_crc7_inserter_crc_reset) begin + sdcard_core_crc7_inserter_crc0 <= 1'd0; + end else begin + if (sdcard_core_crc7_inserter_crc_enable) begin + sdcard_core_crc7_inserter_crc0 <= sdcard_core_crc7_inserter_crc40; + end + end + if (sdcard_core_crc16_inserter_crc0_reset) begin + sdcard_core_crc16_inserter_crc00 <= 1'd0; + end else begin + if (sdcard_core_crc16_inserter_crc0_enable) begin + sdcard_core_crc16_inserter_crc00 <= sdcard_core_crc16_inserter_crc02; + end + end + if (sdcard_core_crc16_inserter_crc1_reset) begin + sdcard_core_crc16_inserter_crc10 <= 1'd0; + end else begin + if (sdcard_core_crc16_inserter_crc1_enable) begin + sdcard_core_crc16_inserter_crc10 <= sdcard_core_crc16_inserter_crc12; + end + end + if (sdcard_core_crc16_inserter_crc2_reset) begin + sdcard_core_crc16_inserter_crc20 <= 1'd0; + end else begin + if (sdcard_core_crc16_inserter_crc2_enable) begin + sdcard_core_crc16_inserter_crc20 <= sdcard_core_crc16_inserter_crc22; + end + end + if (sdcard_core_crc16_inserter_crc3_reset) begin + sdcard_core_crc16_inserter_crc30 <= 1'd0; + end else begin + if (sdcard_core_crc16_inserter_crc3_enable) begin + sdcard_core_crc16_inserter_crc30 <= sdcard_core_crc16_inserter_crc32; + end + end + crc16inserter_state <= crc16inserter_next_state; + if (sdcard_core_crc16_inserter_count_crc16inserter_next_value_ce) begin + sdcard_core_crc16_inserter_count <= sdcard_core_crc16_inserter_count_crc16inserter_next_value; + end + if (((sdcard_core_fifo_syncfifo_we & sdcard_core_fifo_syncfifo_writable) & (~sdcard_core_fifo_replace))) begin + sdcard_core_fifo_produce <= (sdcard_core_fifo_produce + 1'd1); + end + if (sdcard_core_fifo_do_read) begin + sdcard_core_fifo_consume <= (sdcard_core_fifo_consume + 1'd1); + end + if (((sdcard_core_fifo_syncfifo_we & sdcard_core_fifo_syncfifo_writable) & (~sdcard_core_fifo_replace))) begin + if ((~sdcard_core_fifo_do_read)) begin + sdcard_core_fifo_level <= (sdcard_core_fifo_level + 1'd1); + end + end else begin + if (sdcard_core_fifo_do_read) begin + sdcard_core_fifo_level <= (sdcard_core_fifo_level - 1'd1); + end + end + if (sdcard_core_fifo_reset) begin + sdcard_core_fifo_level <= 4'd0; + sdcard_core_fifo_produce <= 3'd0; + sdcard_core_fifo_consume <= 3'd0; + end + fsm_state <= fsm_next_state; + if (sdcard_core_cmd_done_fsm_next_value_ce0) begin + sdcard_core_cmd_done <= sdcard_core_cmd_done_fsm_next_value0; + end + if (sdcard_core_data_done_fsm_next_value_ce1) begin + sdcard_core_data_done <= sdcard_core_data_done_fsm_next_value1; + end + if (sdcard_core_cmd_count_fsm_next_value_ce2) begin + sdcard_core_cmd_count <= sdcard_core_cmd_count_fsm_next_value2; + end + if (sdcard_core_data_count_fsm_next_value_ce3) begin + sdcard_core_data_count <= sdcard_core_data_count_fsm_next_value3; + end + if (sdcard_core_cmd_error_fsm_next_value_ce4) begin + sdcard_core_cmd_error <= sdcard_core_cmd_error_fsm_next_value4; + end + if (sdcard_core_cmd_timeout_fsm_next_value_ce5) begin + sdcard_core_cmd_timeout <= sdcard_core_cmd_timeout_fsm_next_value5; + end + if (sdcard_core_data_error_fsm_next_value_ce6) begin + sdcard_core_data_error <= sdcard_core_data_error_fsm_next_value6; + end + if (sdcard_core_data_timeout_fsm_next_value_ce7) begin + sdcard_core_data_timeout <= sdcard_core_data_timeout_fsm_next_value7; + end + if (sdcard_core_cmd_response_status_fsm_next_value_ce8) begin + sdcard_core_cmd_response_status <= sdcard_core_cmd_response_status_fsm_next_value8; + end + if ((~sdcard_block2mem_wishbonedmawriter_enable_storage)) begin + sdcard_block2mem_connect <= 1'd0; + end else begin + if (sdcard_block2mem_start) begin + sdcard_block2mem_connect <= 1'd1; + end + end + sdcard_block2mem_done_d <= sdcard_block2mem_wishbonedmawriter_done_status; + sdcard_block2mem_irq <= (sdcard_block2mem_wishbonedmawriter_done_status & (~sdcard_block2mem_done_d)); + if (sdcard_block2mem_fifo_syncfifo_re) begin + sdcard_block2mem_fifo_readable <= 1'd1; + end else begin + if (sdcard_block2mem_fifo_re) begin + sdcard_block2mem_fifo_readable <= 1'd0; + end + end + if (((sdcard_block2mem_fifo_syncfifo_we & sdcard_block2mem_fifo_syncfifo_writable) & (~sdcard_block2mem_fifo_replace))) begin + sdcard_block2mem_fifo_produce <= (sdcard_block2mem_fifo_produce + 1'd1); + end + if (sdcard_block2mem_fifo_do_read) begin + sdcard_block2mem_fifo_consume <= (sdcard_block2mem_fifo_consume + 1'd1); + end + if (((sdcard_block2mem_fifo_syncfifo_we & sdcard_block2mem_fifo_syncfifo_writable) & (~sdcard_block2mem_fifo_replace))) begin + if ((~sdcard_block2mem_fifo_do_read)) begin + sdcard_block2mem_fifo_level0 <= (sdcard_block2mem_fifo_level0 + 1'd1); + end + end else begin + if (sdcard_block2mem_fifo_do_read) begin + sdcard_block2mem_fifo_level0 <= (sdcard_block2mem_fifo_level0 - 1'd1); + end + end + if (sdcard_block2mem_converter_source_ready) begin + sdcard_block2mem_converter_strobe_all <= 1'd0; + end + if (sdcard_block2mem_converter_load_part) begin + if (((sdcard_block2mem_converter_demux == 2'd3) | sdcard_block2mem_converter_sink_last)) begin + sdcard_block2mem_converter_demux <= 1'd0; + sdcard_block2mem_converter_strobe_all <= 1'd1; + end else begin + sdcard_block2mem_converter_demux <= (sdcard_block2mem_converter_demux + 1'd1); + end + end + if ((sdcard_block2mem_converter_source_valid & sdcard_block2mem_converter_source_ready)) begin + if ((sdcard_block2mem_converter_sink_valid & sdcard_block2mem_converter_sink_ready)) begin + sdcard_block2mem_converter_source_first <= sdcard_block2mem_converter_sink_first; + sdcard_block2mem_converter_source_last <= sdcard_block2mem_converter_sink_last; + end else begin + sdcard_block2mem_converter_source_first <= 1'd0; + sdcard_block2mem_converter_source_last <= 1'd0; + end + end else begin + if ((sdcard_block2mem_converter_sink_valid & sdcard_block2mem_converter_sink_ready)) begin + sdcard_block2mem_converter_source_first <= (sdcard_block2mem_converter_sink_first | sdcard_block2mem_converter_source_first); + sdcard_block2mem_converter_source_last <= (sdcard_block2mem_converter_sink_last | sdcard_block2mem_converter_source_last); + end + end + if (sdcard_block2mem_converter_load_part) begin + case (sdcard_block2mem_converter_demux) + 1'd0: begin + sdcard_block2mem_converter_source_payload_data[31:24] <= sdcard_block2mem_converter_sink_payload_data; + end + 1'd1: begin + sdcard_block2mem_converter_source_payload_data[23:16] <= sdcard_block2mem_converter_sink_payload_data; + end + 2'd2: begin + sdcard_block2mem_converter_source_payload_data[15:8] <= sdcard_block2mem_converter_sink_payload_data; + end + 2'd3: begin + sdcard_block2mem_converter_source_payload_data[7:0] <= sdcard_block2mem_converter_sink_payload_data; + end + endcase + end + if (sdcard_block2mem_converter_load_part) begin + sdcard_block2mem_converter_source_payload_valid_token_count <= (sdcard_block2mem_converter_demux + 1'd1); + end + sdblock2memdma_state <= sdblock2memdma_next_state; + if (sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce) begin + sdcard_block2mem_wishbonedmawriter_offset <= sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value; + end + if (sdcard_block2mem_wishbonedmawriter_reset) begin + sdcard_block2mem_wishbonedmawriter_offset <= 32'd0; + sdblock2memdma_state <= 2'd0; + end + if ((sdcard_mem2block_source_source_valid & sdcard_mem2block_source_source_ready)) begin + sdcard_mem2block_count <= (sdcard_mem2block_count + 1'd1); + if (sdcard_mem2block_source_source_last) begin + sdcard_mem2block_count <= 1'd0; + end + end + sdcard_mem2block_done_d <= sdcard_mem2block_dma_done_status; + sdcard_mem2block_irq <= (sdcard_mem2block_dma_done_status & (~sdcard_mem2block_done_d)); + if (((sdcard_mem2block_dma_fifo_syncfifo_we & sdcard_mem2block_dma_fifo_syncfifo_writable) & (~sdcard_mem2block_dma_fifo_replace))) begin + sdcard_mem2block_dma_fifo_produce <= (sdcard_mem2block_dma_fifo_produce + 1'd1); + end + if (sdcard_mem2block_dma_fifo_do_read) begin + sdcard_mem2block_dma_fifo_consume <= (sdcard_mem2block_dma_fifo_consume + 1'd1); + end + if (((sdcard_mem2block_dma_fifo_syncfifo_we & sdcard_mem2block_dma_fifo_syncfifo_writable) & (~sdcard_mem2block_dma_fifo_replace))) begin + if ((~sdcard_mem2block_dma_fifo_do_read)) begin + sdcard_mem2block_dma_fifo_level <= (sdcard_mem2block_dma_fifo_level + 1'd1); + end + end else begin + if (sdcard_mem2block_dma_fifo_do_read) begin + sdcard_mem2block_dma_fifo_level <= (sdcard_mem2block_dma_fifo_level - 1'd1); + end + end + sdmem2blockdma_state <= sdmem2blockdma_next_state; + if (sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce) begin + sdcard_mem2block_dma_offset <= sdcard_mem2block_dma_offset_sdmem2blockdma_next_value; + end + if (sdcard_mem2block_dma_reset) begin + sdcard_mem2block_dma_offset <= 32'd0; + sdmem2blockdma_state <= 2'd0; + end + if ((sdcard_mem2block_converter_converter_source_valid & sdcard_mem2block_converter_converter_source_ready)) begin + if (sdcard_mem2block_converter_converter_last) begin + sdcard_mem2block_converter_converter_mux <= 1'd0; + end else begin + sdcard_mem2block_converter_converter_mux <= (sdcard_mem2block_converter_converter_mux + 1'd1); + end + end + if (sdcard_mem2block_fifo_syncfifo_re) begin + sdcard_mem2block_fifo_readable <= 1'd1; + end else begin + if (sdcard_mem2block_fifo_re) begin + sdcard_mem2block_fifo_readable <= 1'd0; + end + end + if (((sdcard_mem2block_fifo_syncfifo_we & sdcard_mem2block_fifo_syncfifo_writable) & (~sdcard_mem2block_fifo_replace))) begin + sdcard_mem2block_fifo_produce <= (sdcard_mem2block_fifo_produce + 1'd1); + end + if (sdcard_mem2block_fifo_do_read) begin + sdcard_mem2block_fifo_consume <= (sdcard_mem2block_fifo_consume + 1'd1); + end + if (((sdcard_mem2block_fifo_syncfifo_we & sdcard_mem2block_fifo_syncfifo_writable) & (~sdcard_mem2block_fifo_replace))) begin + if ((~sdcard_mem2block_fifo_do_read)) begin + sdcard_mem2block_fifo_level0 <= (sdcard_mem2block_fifo_level0 + 1'd1); + end + end else begin + if (sdcard_mem2block_fifo_do_read) begin + sdcard_mem2block_fifo_level0 <= (sdcard_mem2block_fifo_level0 - 1'd1); + end + end + if (card_detect_clear) begin + card_detect_pending <= 1'd0; + end + if (card_detect_trigger) begin + card_detect_pending <= 1'd1; + end + if (block2mem_dma_clear) begin + block2mem_dma_pending <= 1'd0; + end + if (block2mem_dma_trigger) begin + block2mem_dma_pending <= 1'd1; + end + if (mem2block_dma_clear) begin + mem2block_dma_pending <= 1'd0; + end + if (mem2block_dma_trigger) begin + mem2block_dma_pending <= 1'd1; + end + wishbone2csr_state <= wishbone2csr_next_state; + interface0_bank_bus_dat_r <= 1'd0; + if (csrbank0_sel) begin + case (interface0_bank_bus_adr[8:0]) + 1'd0: begin + interface0_bank_bus_dat_r <= csrbank0_reset0_w; + end + 1'd1: begin + interface0_bank_bus_dat_r <= csrbank0_scratch0_w; + end + 2'd2: begin + interface0_bank_bus_dat_r <= csrbank0_bus_errors_w; + end + endcase + end + if (csrbank0_reset0_re) begin + reset_storage[1:0] <= csrbank0_reset0_r; + end + reset_re <= csrbank0_reset0_re; + if (csrbank0_scratch0_re) begin + scratch_storage[31:0] <= csrbank0_scratch0_r; + end + scratch_re <= csrbank0_scratch0_re; + bus_errors_re <= csrbank0_bus_errors_re; + interface1_bank_bus_dat_r <= 1'd0; + if (csrbank1_sel) begin + case (interface1_bank_bus_adr[8:0]) + 1'd0: begin + interface1_bank_bus_dat_r <= csrbank1_dma_base1_w; + end + 1'd1: begin + interface1_bank_bus_dat_r <= csrbank1_dma_base0_w; + end + 2'd2: begin + interface1_bank_bus_dat_r <= csrbank1_dma_length0_w; + end + 2'd3: begin + interface1_bank_bus_dat_r <= csrbank1_dma_enable0_w; + end + 3'd4: begin + interface1_bank_bus_dat_r <= csrbank1_dma_done_w; + end + 3'd5: begin + interface1_bank_bus_dat_r <= csrbank1_dma_loop0_w; + end + 3'd6: begin + interface1_bank_bus_dat_r <= csrbank1_dma_offset_w; + end + endcase + end + if (csrbank1_dma_base1_re) begin + sdcard_block2mem_wishbonedmawriter_base_storage[63:32] <= csrbank1_dma_base1_r; + end + if (csrbank1_dma_base0_re) begin + sdcard_block2mem_wishbonedmawriter_base_storage[31:0] <= csrbank1_dma_base0_r; + end + sdcard_block2mem_wishbonedmawriter_base_re <= csrbank1_dma_base0_re; + if (csrbank1_dma_length0_re) begin + sdcard_block2mem_wishbonedmawriter_length_storage[31:0] <= csrbank1_dma_length0_r; + end + sdcard_block2mem_wishbonedmawriter_length_re <= csrbank1_dma_length0_re; + if (csrbank1_dma_enable0_re) begin + sdcard_block2mem_wishbonedmawriter_enable_storage <= csrbank1_dma_enable0_r; + end + sdcard_block2mem_wishbonedmawriter_enable_re <= csrbank1_dma_enable0_re; + sdcard_block2mem_wishbonedmawriter_done_re <= csrbank1_dma_done_re; + if (csrbank1_dma_loop0_re) begin + sdcard_block2mem_wishbonedmawriter_loop_storage <= csrbank1_dma_loop0_r; + end + sdcard_block2mem_wishbonedmawriter_loop_re <= csrbank1_dma_loop0_re; + sdcard_block2mem_wishbonedmawriter_offset_re <= csrbank1_dma_offset_re; + interface2_bank_bus_dat_r <= 1'd0; + if (csrbank2_sel) begin + case (interface2_bank_bus_adr[8:0]) + 1'd0: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_argument0_w; + end + 1'd1: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_command0_w; + end + 2'd2: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_send0_w; + end + 2'd3: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_response3_w; + end + 3'd4: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_response2_w; + end + 3'd5: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_response1_w; + end + 3'd6: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_response0_w; + end + 3'd7: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_event_w; + end + 4'd8: begin + interface2_bank_bus_dat_r <= csrbank2_data_event_w; + end + 4'd9: begin + interface2_bank_bus_dat_r <= csrbank2_block_length0_w; + end + 4'd10: begin + interface2_bank_bus_dat_r <= csrbank2_block_count0_w; + end + endcase + end + if (csrbank2_cmd_argument0_re) begin + sdcard_core_cmd_argument_storage[31:0] <= csrbank2_cmd_argument0_r; + end + sdcard_core_cmd_argument_re <= csrbank2_cmd_argument0_re; + if (csrbank2_cmd_command0_re) begin + sdcard_core_cmd_command_storage[13:0] <= csrbank2_cmd_command0_r; + end + sdcard_core_cmd_command_re <= csrbank2_cmd_command0_re; + if (csrbank2_cmd_send0_re) begin + sdcard_core_cmd_send_storage <= csrbank2_cmd_send0_r; + end + sdcard_core_cmd_send_re <= csrbank2_cmd_send0_re; + sdcard_core_cmd_response_re <= csrbank2_cmd_response0_re; + sdcard_core_cmd_event_re <= csrbank2_cmd_event_re; + sdcard_core_data_event_re <= csrbank2_data_event_re; + if (csrbank2_block_length0_re) begin + sdcard_core_block_length_storage[9:0] <= csrbank2_block_length0_r; + end + sdcard_core_block_length_re <= csrbank2_block_length0_re; + if (csrbank2_block_count0_re) begin + sdcard_core_block_count_storage[31:0] <= csrbank2_block_count0_r; + end + sdcard_core_block_count_re <= csrbank2_block_count0_re; + interface3_bank_bus_dat_r <= 1'd0; + if (csrbank3_sel) begin + case (interface3_bank_bus_adr[8:0]) + 1'd0: begin + interface3_bank_bus_dat_r <= csrbank3_status_w; + end + 1'd1: begin + interface3_bank_bus_dat_r <= csrbank3_pending_w; + end + 2'd2: begin + interface3_bank_bus_dat_r <= csrbank3_enable0_w; + end + endcase + end + eventmanager_status_re <= csrbank3_status_re; + if (csrbank3_pending_re) begin + eventmanager_pending_r[3:0] <= csrbank3_pending_r; + end + eventmanager_pending_re <= csrbank3_pending_re; + if (csrbank3_enable0_re) begin + eventmanager_enable_storage[3:0] <= csrbank3_enable0_r; + end + eventmanager_enable_re <= csrbank3_enable0_re; + interface4_bank_bus_dat_r <= 1'd0; + if (csrbank4_sel) begin + case (interface4_bank_bus_adr[8:0]) + 1'd0: begin + interface4_bank_bus_dat_r <= csrbank4_dma_base1_w; + end + 1'd1: begin + interface4_bank_bus_dat_r <= csrbank4_dma_base0_w; + end + 2'd2: begin + interface4_bank_bus_dat_r <= csrbank4_dma_length0_w; + end + 2'd3: begin + interface4_bank_bus_dat_r <= csrbank4_dma_enable0_w; + end + 3'd4: begin + interface4_bank_bus_dat_r <= csrbank4_dma_done_w; + end + 3'd5: begin + interface4_bank_bus_dat_r <= csrbank4_dma_loop0_w; + end + 3'd6: begin + interface4_bank_bus_dat_r <= csrbank4_dma_offset_w; + end + endcase + end + if (csrbank4_dma_base1_re) begin + sdcard_mem2block_dma_base_storage[63:32] <= csrbank4_dma_base1_r; + end + if (csrbank4_dma_base0_re) begin + sdcard_mem2block_dma_base_storage[31:0] <= csrbank4_dma_base0_r; + end + sdcard_mem2block_dma_base_re <= csrbank4_dma_base0_re; + if (csrbank4_dma_length0_re) begin + sdcard_mem2block_dma_length_storage[31:0] <= csrbank4_dma_length0_r; + end + sdcard_mem2block_dma_length_re <= csrbank4_dma_length0_re; + if (csrbank4_dma_enable0_re) begin + sdcard_mem2block_dma_enable_storage <= csrbank4_dma_enable0_r; + end + sdcard_mem2block_dma_enable_re <= csrbank4_dma_enable0_re; + sdcard_mem2block_dma_done_re <= csrbank4_dma_done_re; + if (csrbank4_dma_loop0_re) begin + sdcard_mem2block_dma_loop_storage <= csrbank4_dma_loop0_r; + end + sdcard_mem2block_dma_loop_re <= csrbank4_dma_loop0_re; + sdcard_mem2block_dma_offset_re <= csrbank4_dma_offset_re; + interface5_bank_bus_dat_r <= 1'd0; + if (csrbank5_sel) begin + case (interface5_bank_bus_adr[8:0]) + 1'd0: begin + interface5_bank_bus_dat_r <= csrbank5_card_detect_w; + end + 1'd1: begin + interface5_bank_bus_dat_r <= csrbank5_clocker_divider0_w; + end + 2'd2: begin + interface5_bank_bus_dat_r <= init_initialize_w; + end + 2'd3: begin + interface5_bank_bus_dat_r <= csrbank5_dataw_status_w; + end + endcase + end + card_detect_re <= csrbank5_card_detect_re; + if (csrbank5_clocker_divider0_re) begin + clocker_storage[8:0] <= csrbank5_clocker_divider0_r; + end + clocker_re <= csrbank5_clocker_divider0_re; + dataw_re <= csrbank5_dataw_status_re; + if (sys_rst) begin + reset_storage <= 2'd0; + reset_re <= 1'd0; + scratch_storage <= 32'd305419896; + scratch_re <= 1'd0; + bus_errors_re <= 1'd0; + bus_errors <= 32'd0; + card_detect_re <= 1'd0; + clocker_storage <= 9'd256; + clocker_re <= 1'd0; + clocker_clks <= 9'd0; + clocker_clk_d <= 1'd0; + clocker_ce_delayed <= 1'd0; + init_count <= 8'd0; + cmdw_count <= 8'd0; + cmdr_timeout <= 32'd48000000; + cmdr_count <= 8'd0; + cmdr_busy <= 1'd0; + cmdr_cmdr_run <= 1'd0; + cmdr_cmdr_converter_converter_source_payload_data <= 8'd0; + cmdr_cmdr_converter_converter_source_payload_valid_token_count <= 4'd0; + cmdr_cmdr_converter_converter_demux <= 3'd0; + cmdr_cmdr_converter_converter_strobe_all <= 1'd0; + cmdr_cmdr_buf_pipe_valid_source_valid <= 1'd0; + cmdr_cmdr_buf_pipe_valid_source_payload_data <= 8'd0; + cmdr_cmdr_reset <= 1'd0; + dataw_re <= 1'd0; + dataw_count <= 8'd0; + dataw_accepted1 <= 1'd0; + dataw_crc_error1 <= 1'd0; + dataw_write_error1 <= 1'd0; + dataw_crc_run <= 1'd0; + dataw_crc_converter_converter_source_payload_data <= 8'd0; + dataw_crc_converter_converter_source_payload_valid_token_count <= 4'd0; + dataw_crc_converter_converter_demux <= 3'd0; + dataw_crc_converter_converter_strobe_all <= 1'd0; + dataw_crc_buf_pipe_valid_source_valid <= 1'd0; + dataw_crc_buf_pipe_valid_source_payload_data <= 8'd0; + datar_timeout <= 32'd48000000; + datar_count <= 10'd0; + datar_datar_run <= 1'd0; + datar_datar_converter_converter_source_payload_data <= 8'd0; + datar_datar_converter_converter_source_payload_valid_token_count <= 2'd0; + datar_datar_converter_converter_demux <= 1'd0; + datar_datar_converter_converter_strobe_all <= 1'd0; + datar_datar_buf_pipe_valid_source_valid <= 1'd0; + datar_datar_buf_pipe_valid_source_payload_data <= 8'd0; + datar_datar_reset <= 1'd0; + sdpads_data_i_ce <= 1'd0; + clocker_clk_delay <= 2'd0; + card_detect_irq <= 1'd0; + card_detect_d <= 1'd0; + sdcard_core_irq <= 1'd0; + sdcard_core_cmd_argument_storage <= 32'd0; + sdcard_core_cmd_argument_re <= 1'd0; + sdcard_core_cmd_command_storage <= 14'd0; + sdcard_core_cmd_command_re <= 1'd0; + sdcard_core_cmd_send_storage <= 1'd0; + sdcard_core_cmd_send_re <= 1'd0; + sdcard_core_cmd_response_status <= 128'd0; + sdcard_core_cmd_response_re <= 1'd0; + sdcard_core_cmd_event_re <= 1'd0; + sdcard_core_data_event_re <= 1'd0; + sdcard_core_block_length_storage <= 10'd0; + sdcard_core_block_length_re <= 1'd0; + sdcard_core_block_count_storage <= 32'd0; + sdcard_core_block_count_re <= 1'd0; + sdcard_core_crc7_inserter_crc0 <= 7'd0; + sdcard_core_crc16_inserter_count <= 3'd0; + sdcard_core_crc16_inserter_crc00 <= 16'd0; + sdcard_core_crc16_inserter_crc10 <= 16'd0; + sdcard_core_crc16_inserter_crc20 <= 16'd0; + sdcard_core_crc16_inserter_crc30 <= 16'd0; + sdcard_core_fifo_level <= 4'd0; + sdcard_core_fifo_produce <= 3'd0; + sdcard_core_fifo_consume <= 3'd0; + sdcard_core_cmd_count <= 3'd0; + sdcard_core_cmd_done <= 1'd0; + sdcard_core_cmd_error <= 1'd0; + sdcard_core_cmd_timeout <= 1'd0; + sdcard_core_data_count <= 32'd0; + sdcard_core_data_done <= 1'd0; + sdcard_core_data_error <= 1'd0; + sdcard_core_data_timeout <= 1'd0; + sdcard_core_done_d <= 1'd0; + sdcard_block2mem_irq <= 1'd0; + sdcard_block2mem_fifo_readable <= 1'd0; + sdcard_block2mem_fifo_level0 <= 10'd0; + sdcard_block2mem_fifo_produce <= 9'd0; + sdcard_block2mem_fifo_consume <= 9'd0; + sdcard_block2mem_converter_source_payload_data <= 32'd0; + sdcard_block2mem_converter_source_payload_valid_token_count <= 3'd0; + sdcard_block2mem_converter_demux <= 2'd0; + sdcard_block2mem_converter_strobe_all <= 1'd0; + sdcard_block2mem_wishbonedmawriter_base_storage <= 64'd0; + sdcard_block2mem_wishbonedmawriter_base_re <= 1'd0; + sdcard_block2mem_wishbonedmawriter_length_storage <= 32'd0; + sdcard_block2mem_wishbonedmawriter_length_re <= 1'd0; + sdcard_block2mem_wishbonedmawriter_enable_storage <= 1'd0; + sdcard_block2mem_wishbonedmawriter_enable_re <= 1'd0; + sdcard_block2mem_wishbonedmawriter_done_re <= 1'd0; + sdcard_block2mem_wishbonedmawriter_loop_storage <= 1'd0; + sdcard_block2mem_wishbonedmawriter_loop_re <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset_re <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset <= 32'd0; + sdcard_block2mem_connect <= 1'd0; + sdcard_block2mem_done_d <= 1'd0; + sdcard_mem2block_irq <= 1'd0; + sdcard_mem2block_dma_fifo_level <= 5'd0; + sdcard_mem2block_dma_fifo_produce <= 4'd0; + sdcard_mem2block_dma_fifo_consume <= 4'd0; + sdcard_mem2block_dma_base_storage <= 64'd0; + sdcard_mem2block_dma_base_re <= 1'd0; + sdcard_mem2block_dma_length_storage <= 32'd0; + sdcard_mem2block_dma_length_re <= 1'd0; + sdcard_mem2block_dma_enable_storage <= 1'd0; + sdcard_mem2block_dma_enable_re <= 1'd0; + sdcard_mem2block_dma_done_re <= 1'd0; + sdcard_mem2block_dma_loop_storage <= 1'd0; + sdcard_mem2block_dma_loop_re <= 1'd0; + sdcard_mem2block_dma_offset_re <= 1'd0; + sdcard_mem2block_dma_offset <= 32'd0; + sdcard_mem2block_converter_converter_mux <= 2'd0; + sdcard_mem2block_fifo_readable <= 1'd0; + sdcard_mem2block_fifo_level0 <= 10'd0; + sdcard_mem2block_fifo_produce <= 9'd0; + sdcard_mem2block_fifo_consume <= 9'd0; + sdcard_mem2block_count <= 9'd0; + sdcard_mem2block_done_d <= 1'd0; + card_detect_pending <= 1'd0; + block2mem_dma_pending <= 1'd0; + mem2block_dma_pending <= 1'd0; + eventmanager_status_re <= 1'd0; + eventmanager_pending_re <= 1'd0; + eventmanager_pending_r <= 4'd0; + eventmanager_enable_storage <= 4'd0; + eventmanager_enable_re <= 1'd0; + grant <= 1'd0; + slave_sel_r <= 1'd0; + count <= 20'd1000000; + sdphyinit_state <= 1'd0; + sdphycmdw_state <= 2'd0; + sdphycmdr_state <= 3'd0; + sdphydataw_state <= 3'd0; + sdphydatar_state <= 3'd0; + crc16inserter_state <= 1'd0; + fsm_state <= 3'd0; + sdblock2memdma_state <= 2'd0; + sdmem2blockdma_state <= 2'd0; + wishbone2csr_state <= 1'd0; + end +end + + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Memory storage: 8-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Async | Write: ---- | +reg [9:0] storage[0:7]; +reg [9:0] storage_dat0; +always @(posedge sys_clk) begin + if (sdcard_core_fifo_wrport_we) + storage[sdcard_core_fifo_wrport_adr] <= sdcard_core_fifo_wrport_dat_w; + storage_dat0 <= storage[sdcard_core_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign sdcard_core_fifo_wrport_dat_r = storage_dat0; +assign sdcard_core_fifo_rdport_dat_r = storage[sdcard_core_fifo_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_1: 512-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Sync | Write: ---- | +reg [9:0] storage_1[0:511]; +reg [9:0] storage_1_dat0; +reg [9:0] storage_1_dat1; +always @(posedge sys_clk) begin + if (sdcard_block2mem_fifo_wrport_we) + storage_1[sdcard_block2mem_fifo_wrport_adr] <= sdcard_block2mem_fifo_wrport_dat_w; + storage_1_dat0 <= storage_1[sdcard_block2mem_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin + if (sdcard_block2mem_fifo_rdport_re) + storage_1_dat1 <= storage_1[sdcard_block2mem_fifo_rdport_adr]; +end +assign sdcard_block2mem_fifo_wrport_dat_r = storage_1_dat0; +assign sdcard_block2mem_fifo_rdport_dat_r = storage_1_dat1; + + +//------------------------------------------------------------------------------ +// Memory storage_2: 16-words x 34-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 34 +// Port 1 | Read: Async | Write: ---- | +reg [33:0] storage_2[0:15]; +reg [33:0] storage_2_dat0; +always @(posedge sys_clk) begin + if (sdcard_mem2block_dma_fifo_wrport_we) + storage_2[sdcard_mem2block_dma_fifo_wrport_adr] <= sdcard_mem2block_dma_fifo_wrport_dat_w; + storage_2_dat0 <= storage_2[sdcard_mem2block_dma_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign sdcard_mem2block_dma_fifo_wrport_dat_r = storage_2_dat0; +assign sdcard_mem2block_dma_fifo_rdport_dat_r = storage_2[sdcard_mem2block_dma_fifo_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_3: 512-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Sync | Write: ---- | +reg [9:0] storage_3[0:511]; +reg [9:0] storage_3_dat0; +reg [9:0] storage_3_dat1; +always @(posedge sys_clk) begin + if (sdcard_mem2block_fifo_wrport_we) + storage_3[sdcard_mem2block_fifo_wrport_adr] <= sdcard_mem2block_fifo_wrport_dat_w; + storage_3_dat0 <= storage_3[sdcard_mem2block_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin + if (sdcard_mem2block_fifo_rdport_re) + storage_3_dat1 <= storage_3[sdcard_mem2block_fifo_rdport_adr]; +end +assign sdcard_mem2block_fifo_wrport_dat_r = storage_3_dat0; +assign sdcard_mem2block_fifo_rdport_dat_r = storage_3_dat1; + + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX( + // Inputs. + .D ((~clocker_clk0)), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdcard_clk) +); + +assign sdcard_cmd = inferedsdrtristate0_oe ? inferedsdrtristate0__o : 1'bz; +assign inferedsdrtristate0__i = sdcard_cmd; + +assign sdcard_data[0] = inferedsdrtristate1_oe ? inferedsdrtristate1__o : 1'bz; +assign inferedsdrtristate1__i = sdcard_data[0]; + +assign sdcard_data[1] = inferedsdrtristate2_oe ? inferedsdrtristate2__o : 1'bz; +assign inferedsdrtristate2__i = sdcard_data[1]; + +assign sdcard_data[2] = inferedsdrtristate3_oe ? inferedsdrtristate3__o : 1'bz; +assign inferedsdrtristate3__i = sdcard_data[2]; + +assign sdcard_data[3] = inferedsdrtristate4_oe ? inferedsdrtristate4__o : 1'bz; +assign inferedsdrtristate4__i = sdcard_data[3]; + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX_1 of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX_1( + // Inputs. + .D (sdpads_cmd_oe), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdcard_cmd_dir) +); + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX_2 of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX_2( + // Inputs. + .D (sdpads_data_oe), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdcard_dat0_dir) +); + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX_3 of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX_3( + // Inputs. + .D (sdpads_data_oe), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdcard_dat13_dir) +); + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX_4 of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX_4( + // Inputs. + .D (sdpads_cmd_o), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (inferedsdrtristate0__o) +); + +//------------------------------------------------------------------------------ +// Instance IFS1P3BX of IFS1P3BX Module. +//------------------------------------------------------------------------------ +IFS1P3BX IFS1P3BX( + // Inputs. + .D (inferedsdrtristate0__i), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdpads_cmd_i) +); + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX_5 of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX_5( + // Inputs. + .D (sdpads_data_o[0]), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (inferedsdrtristate1__o) +); + +//------------------------------------------------------------------------------ +// Instance IFS1P3BX_1 of IFS1P3BX Module. +//------------------------------------------------------------------------------ +IFS1P3BX IFS1P3BX_1( + // Inputs. + .D (inferedsdrtristate1__i), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdpads_data_i[0]) +); + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX_6 of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX_6( + // Inputs. + .D (sdpads_data_o[1]), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (inferedsdrtristate2__o) +); + +//------------------------------------------------------------------------------ +// Instance IFS1P3BX_2 of IFS1P3BX Module. +//------------------------------------------------------------------------------ +IFS1P3BX IFS1P3BX_2( + // Inputs. + .D (inferedsdrtristate2__i), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdpads_data_i[1]) +); + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX_7 of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX_7( + // Inputs. + .D (sdpads_data_o[2]), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (inferedsdrtristate3__o) +); + +//------------------------------------------------------------------------------ +// Instance IFS1P3BX_3 of IFS1P3BX Module. +//------------------------------------------------------------------------------ +IFS1P3BX IFS1P3BX_3( + // Inputs. + .D (inferedsdrtristate3__i), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdpads_data_i[2]) +); + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX_8 of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX_8( + // Inputs. + .D (sdpads_data_o[3]), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (inferedsdrtristate4__o) +); + +//------------------------------------------------------------------------------ +// Instance IFS1P3BX_4 of IFS1P3BX Module. +//------------------------------------------------------------------------------ +IFS1P3BX IFS1P3BX_4( + // Inputs. + .D (inferedsdrtristate4__i), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdpads_data_i[3]) +); + +endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2024-04-03 20:02:06. +//------------------------------------------------------------------------------ diff --git a/litesdcard/generated/lattice.50e6/litesdcard_core.v b/litesdcard/generated/lattice.50e6/litesdcard_core.v new file mode 100644 index 0000000..7412820 --- /dev/null +++ b/litesdcard/generated/lattice.50e6/litesdcard_core.v @@ -0,0 +1,4679 @@ +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : litesdcard_core.v +// Device : +// LiteX sha1 : 87137c30 +// Date : 2024-04-03 19:58:12 +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ps + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module litesdcard_core ( + input wire clk, + output wire irq, + input wire rst, + input wire sdcard_cd, + output wire sdcard_clk, + inout wire sdcard_cmd, + output wire sdcard_cmd_dir, + output wire sdcard_dat0_dir, + output wire sdcard_dat13_dir, + inout wire [3:0] sdcard_data, + output wire wb_ctrl_ack, + input wire [29:0] wb_ctrl_adr, + input wire [1:0] wb_ctrl_bte, + input wire [2:0] wb_ctrl_cti, + input wire wb_ctrl_cyc, + output wire [31:0] wb_ctrl_dat_r, + input wire [31:0] wb_ctrl_dat_w, + output wire wb_ctrl_err, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_stb, + input wire wb_ctrl_we, + input wire wb_dma_ack, + output wire [29:0] wb_dma_adr, + output wire [1:0] wb_dma_bte, + output wire [2:0] wb_dma_cti, + output wire wb_dma_cyc, + input wire [31:0] wb_dma_dat_r, + output wire [31:0] wb_dma_dat_w, + input wire wb_dma_err, + output wire [3:0] wb_dma_sel, + output wire wb_dma_stb, + output wire wb_dma_we +); + + +//------------------------------------------------------------------------------ +// Hierarchy +//------------------------------------------------------------------------------ + +/* +LiteSDCardCore +└─── crg (CRG) +└─── bus (SoCBusHandler) +│ └─── _interconnect (InterconnectPointToPoint) +└─── csr (SoCCSRHandler) +└─── irq (SoCIRQHandler) +└─── ctrl (SoCController) +└─── cpu (CPUNone) +└─── dma_bus (SoCBusHandler) +│ └─── _interconnect (InterconnectShared) +│ │ └─── arbiter (Arbiter) +│ │ │ └─── rr (RoundRobin) +│ │ └─── decoder (Decoder) +│ │ └─── timeout (Timeout) +│ │ │ └─── waittimer_0* (WaitTimer) +└─── sdcard_phy (SDPHY) +│ └─── clocker (SDPHYClocker) +│ └─── init (SDPHYInit) +│ │ └─── fsm_0* (FSM) +│ └─── cmdw (SDPHYCMDW) +│ │ └─── fsm_0* (FSM) +│ └─── cmdr (SDPHYCMDR) +│ │ └─── sdphyr_0* (SDPHYR) +│ │ │ └─── converter_0* (Converter) +│ │ │ │ └─── _upconverter_0* (_UpConverter) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ └─── fsm_0* (FSM) +│ └─── dataw (SDPHYDATAW) +│ │ └─── crc (SDPHYR) +│ │ │ └─── converter_0* (Converter) +│ │ │ │ └─── _upconverter_0* (_UpConverter) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ └─── fsm (FSM) +│ └─── datar (SDPHYDATAR) +│ │ └─── sdphyr_0* (SDPHYR) +│ │ │ └─── converter_0* (Converter) +│ │ │ │ └─── _upconverter_0* (_UpConverter) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ └─── fsm_0* (FSM) +│ └─── io (SDPHYIOGen) +└─── sdcard_core (SDCore) +│ └─── crc7_inserter (CRC) +│ └─── crc16_inserter (CRC16Inserter) +│ │ └─── crc_0* (CRC) +│ │ └─── crc_1* (CRC) +│ │ └─── crc_2* (CRC) +│ │ └─── crc_3* (CRC) +│ │ └─── fsm (FSM) +│ └─── crc16_checker (CRC16Checker) +│ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ └─── fifo (SyncFIFO) +│ └─── fsm (FSM) +└─── sdcard_block2mem (SDBlock2MemDMA) +│ └─── syncfifo_0* (SyncFIFO) +│ │ └─── fifo (SyncFIFOBuffered) +│ │ │ └─── fifo (SyncFIFO) +│ └─── converter_0* (Converter) +│ │ └─── _upconverter_0* (_UpConverter) +│ └─── dma (WishboneDMAWriter) +│ │ └─── fsm (FSM) +└─── sdcard_mem2block (SDMem2BlockDMA) +│ └─── dma (WishboneDMAReader) +│ │ └─── fifo (SyncFIFO) +│ │ │ └─── fifo (SyncFIFO) +│ │ └─── fsm (FSM) +│ └─── converter_0* (Converter) +│ │ └─── _downconverter_0* (_DownConverter) +│ └─── syncfifo_0* (SyncFIFO) +│ │ └─── fifo (SyncFIFOBuffered) +│ │ │ └─── fifo (SyncFIFO) +└─── sdcard_irq (EventManager) +│ └─── eventsourcepulse_0* (EventSourcePulse) +│ └─── eventsourcepulse_1* (EventSourcePulse) +│ └─── eventsourcepulse_2* (EventSourcePulse) +│ └─── eventsourcelevel_0* (EventSourceLevel) +└─── csr_bridge (Wishbone2CSR) +│ └─── fsm (FSM) +└─── csr_bankarray (CSRBankArray) +│ └─── csrbank_0* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ └─── csrbank_1* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstatus_1* (CSRStatus) +│ └─── csrbank_2* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstatus_1* (CSRStatus) +│ │ └─── csrstatus_2* (CSRStatus) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstorage_4* (CSRStorage) +│ └─── csrbank_3* (CSRBank) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstatus_1* (CSRStatus) +│ │ └─── csrstorage_0* (CSRStorage) +│ └─── csrbank_4* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstatus_1* (CSRStatus) +│ └─── csrbank_5* (CSRBank) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstatus_1* (CSRStatus) +└─── csr_interconnect (InterconnectShared) +└─── [IFS1P3BX] +└─── [OFS1P3BX] +└─── [IFS1P3BX] +└─── [OFS1P3BX] +└─── [IFS1P3BX] +└─── [IFS1P3BX] +└─── [OFS1P3BX] +└─── [IFS1P3BX] +└─── [OFS1P3BX] +└─── [OFS1P3BX] +└─── [OFS1P3BX] +└─── [OFS1P3BX] +└─── [OFS1P3BX] +└─── [OFS1P3BX] +* : Generated name. +[]: BlackBox. +*/ + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +wire [13:0] adr; +reg block2mem_dma_clear = 1'd0; +reg block2mem_dma_pending = 1'd0; +wire block2mem_dma_status; +wire block2mem_dma_trigger; +reg bus_error = 1'd0; +reg [31:0] bus_errors = 32'd0; +reg bus_errors_re = 1'd0; +wire [31:0] bus_errors_status; +wire bus_errors_we; +reg card_detect_clear = 1'd0; +reg card_detect_d = 1'd0; +reg card_detect_irq = 1'd0; +reg card_detect_pending = 1'd0; +reg card_detect_re = 1'd0; +wire card_detect_status0; +wire card_detect_status1; +wire card_detect_trigger; +wire card_detect_we; +wire clocker_ce; +reg clocker_ce_delayed = 1'd0; +reg clocker_ce_latched = 1'd0; +wire clocker_clk0; +reg clocker_clk1 = 1'd0; +reg clocker_clk_d = 1'd0; +reg [1:0] clocker_clk_delay = 2'd0; +wire clocker_clk_en; +reg [8:0] clocker_clks = 9'd0; +reg clocker_re = 1'd0; +wire clocker_stop; +reg [8:0] clocker_storage = 9'd256; +reg cmd_done_clear = 1'd0; +wire cmd_done_pending; +wire cmd_done_status; +wire cmd_done_trigger; +reg cmdr_busy = 1'd0; +reg cmdr_busy_sdphycmdr_next_value2 = 1'd0; +reg cmdr_busy_sdphycmdr_next_value_ce2 = 1'd0; +wire cmdr_cmdr_buf_pipe_valid_sink_first; +wire cmdr_cmdr_buf_pipe_valid_sink_last; +wire [7:0] cmdr_cmdr_buf_pipe_valid_sink_payload_data; +wire cmdr_cmdr_buf_pipe_valid_sink_ready; +wire cmdr_cmdr_buf_pipe_valid_sink_valid; +reg cmdr_cmdr_buf_pipe_valid_source_first = 1'd0; +reg cmdr_cmdr_buf_pipe_valid_source_last = 1'd0; +reg [7:0] cmdr_cmdr_buf_pipe_valid_source_payload_data = 8'd0; +wire cmdr_cmdr_buf_pipe_valid_source_ready; +reg cmdr_cmdr_buf_pipe_valid_source_valid = 1'd0; +wire cmdr_cmdr_buf_sink_sink_first; +wire cmdr_cmdr_buf_sink_sink_last; +wire [7:0] cmdr_cmdr_buf_sink_sink_payload_data; +wire cmdr_cmdr_buf_sink_sink_ready; +wire cmdr_cmdr_buf_sink_sink_valid; +wire cmdr_cmdr_buf_source_source_first; +wire cmdr_cmdr_buf_source_source_last; +wire [7:0] cmdr_cmdr_buf_source_source_payload_data; +wire cmdr_cmdr_buf_source_source_ready; +wire cmdr_cmdr_buf_source_source_valid; +reg [2:0] cmdr_cmdr_converter_converter_demux = 3'd0; +wire cmdr_cmdr_converter_converter_load_part; +reg cmdr_cmdr_converter_converter_sink_first = 1'd0; +reg cmdr_cmdr_converter_converter_sink_last = 1'd0; +wire cmdr_cmdr_converter_converter_sink_payload_data; +wire cmdr_cmdr_converter_converter_sink_ready; +wire cmdr_cmdr_converter_converter_sink_valid; +reg cmdr_cmdr_converter_converter_source_first = 1'd0; +reg cmdr_cmdr_converter_converter_source_last = 1'd0; +reg [7:0] cmdr_cmdr_converter_converter_source_payload_data = 8'd0; +reg [3:0] cmdr_cmdr_converter_converter_source_payload_valid_token_count = 4'd0; +wire cmdr_cmdr_converter_converter_source_ready; +wire cmdr_cmdr_converter_converter_source_valid; +reg cmdr_cmdr_converter_converter_strobe_all = 1'd0; +wire cmdr_cmdr_converter_source_source_first; +wire cmdr_cmdr_converter_source_source_last; +wire [7:0] cmdr_cmdr_converter_source_source_payload_data; +wire cmdr_cmdr_converter_source_source_ready; +wire cmdr_cmdr_converter_source_source_valid; +wire cmdr_cmdr_pads_in_first; +wire cmdr_cmdr_pads_in_last; +wire cmdr_cmdr_pads_in_payload_clk; +wire cmdr_cmdr_pads_in_payload_cmd_i; +wire cmdr_cmdr_pads_in_payload_cmd_o; +wire cmdr_cmdr_pads_in_payload_cmd_oe; +wire [3:0] cmdr_cmdr_pads_in_payload_data_i; +wire cmdr_cmdr_pads_in_payload_data_i_ce; +wire [3:0] cmdr_cmdr_pads_in_payload_data_o; +wire cmdr_cmdr_pads_in_payload_data_oe; +reg cmdr_cmdr_pads_in_ready = 1'd0; +wire cmdr_cmdr_pads_in_valid; +reg cmdr_cmdr_reset = 1'd0; +reg cmdr_cmdr_reset_sdphycmdr_next_value3 = 1'd0; +reg cmdr_cmdr_reset_sdphycmdr_next_value_ce3 = 1'd0; +reg cmdr_cmdr_run = 1'd0; +wire cmdr_cmdr_source_first; +wire cmdr_cmdr_source_last; +wire [7:0] cmdr_cmdr_source_payload_data; +reg cmdr_cmdr_source_ready = 1'd0; +wire cmdr_cmdr_source_valid; +wire cmdr_cmdr_start; +reg [7:0] cmdr_count = 8'd0; +reg [7:0] cmdr_count_sdphycmdr_next_value1 = 8'd0; +reg cmdr_count_sdphycmdr_next_value_ce1 = 1'd0; +reg cmdr_pads_in_pads_in_first = 1'd0; +reg cmdr_pads_in_pads_in_last = 1'd0; +reg cmdr_pads_in_pads_in_payload_clk = 1'd0; +wire cmdr_pads_in_pads_in_payload_cmd_i; +reg cmdr_pads_in_pads_in_payload_cmd_o = 1'd0; +reg cmdr_pads_in_pads_in_payload_cmd_oe = 1'd0; +wire [3:0] cmdr_pads_in_pads_in_payload_data_i; +reg cmdr_pads_in_pads_in_payload_data_i_ce = 1'd0; +reg [3:0] cmdr_pads_in_pads_in_payload_data_o = 4'd0; +reg cmdr_pads_in_pads_in_payload_data_oe = 1'd0; +wire cmdr_pads_in_pads_in_ready; +wire cmdr_pads_in_pads_in_valid; +reg cmdr_pads_out_payload_clk = 1'd0; +reg cmdr_pads_out_payload_cmd_o = 1'd0; +reg cmdr_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] cmdr_pads_out_payload_data_o = 4'd0; +reg cmdr_pads_out_payload_data_oe = 1'd0; +wire cmdr_pads_out_ready; +reg [1:0] cmdr_sink_payload_cmd_type = 2'd0; +reg [1:0] cmdr_sink_payload_data_type = 2'd0; +reg [7:0] cmdr_sink_payload_length = 8'd0; +reg cmdr_sink_ready = 1'd0; +reg cmdr_sink_valid = 1'd0; +reg cmdr_source_source_last = 1'd0; +reg [7:0] cmdr_source_source_payload_data = 8'd0; +reg [2:0] cmdr_source_source_payload_status = 3'd0; +reg cmdr_source_source_ready = 1'd0; +reg cmdr_source_source_valid = 1'd0; +reg [31:0] cmdr_timeout = 32'd50000000; +reg [31:0] cmdr_timeout_sdphycmdr_next_value0 = 32'd0; +reg cmdr_timeout_sdphycmdr_next_value_ce0 = 1'd0; +reg [7:0] cmdw_count = 8'd0; +reg [7:0] cmdw_count_sdphycmdw_next_value = 8'd0; +reg cmdw_count_sdphycmdw_next_value_ce = 1'd0; +reg cmdw_done = 1'd0; +wire cmdw_pads_in_payload_cmd_i; +wire [3:0] cmdw_pads_in_payload_data_i; +wire cmdw_pads_in_valid; +reg cmdw_pads_out_payload_clk = 1'd0; +reg cmdw_pads_out_payload_cmd_o = 1'd0; +reg cmdw_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] cmdw_pads_out_payload_data_o = 4'd0; +reg cmdw_pads_out_payload_data_oe = 1'd0; +wire cmdw_pads_out_ready; +reg cmdw_sink_last = 1'd0; +reg [1:0] cmdw_sink_payload_cmd_type = 2'd0; +reg [7:0] cmdw_sink_payload_data = 8'd0; +reg cmdw_sink_ready = 1'd0; +reg cmdw_sink_valid = 1'd0; +reg [19:0] count = 20'd1000000; +wire cpu_rst; +reg crc16inserter_next_state = 1'd0; +reg crc16inserter_state = 1'd0; +wire [31:0] csrbank0_bus_errors_r; +reg csrbank0_bus_errors_re = 1'd0; +wire [31:0] csrbank0_bus_errors_w; +reg csrbank0_bus_errors_we = 1'd0; +wire [1:0] csrbank0_reset0_r; +reg csrbank0_reset0_re = 1'd0; +wire [1:0] csrbank0_reset0_w; +reg csrbank0_reset0_we = 1'd0; +wire [31:0] csrbank0_scratch0_r; +reg csrbank0_scratch0_re = 1'd0; +wire [31:0] csrbank0_scratch0_w; +reg csrbank0_scratch0_we = 1'd0; +wire csrbank0_sel; +wire [31:0] csrbank1_dma_base0_r; +reg csrbank1_dma_base0_re = 1'd0; +wire [31:0] csrbank1_dma_base0_w; +reg csrbank1_dma_base0_we = 1'd0; +wire [31:0] csrbank1_dma_base1_r; +reg csrbank1_dma_base1_re = 1'd0; +wire [31:0] csrbank1_dma_base1_w; +reg csrbank1_dma_base1_we = 1'd0; +wire csrbank1_dma_done_r; +reg csrbank1_dma_done_re = 1'd0; +wire csrbank1_dma_done_w; +reg csrbank1_dma_done_we = 1'd0; +wire csrbank1_dma_enable0_r; +reg csrbank1_dma_enable0_re = 1'd0; +wire csrbank1_dma_enable0_w; +reg csrbank1_dma_enable0_we = 1'd0; +wire [31:0] csrbank1_dma_length0_r; +reg csrbank1_dma_length0_re = 1'd0; +wire [31:0] csrbank1_dma_length0_w; +reg csrbank1_dma_length0_we = 1'd0; +wire csrbank1_dma_loop0_r; +reg csrbank1_dma_loop0_re = 1'd0; +wire csrbank1_dma_loop0_w; +reg csrbank1_dma_loop0_we = 1'd0; +wire [31:0] csrbank1_dma_offset_r; +reg csrbank1_dma_offset_re = 1'd0; +wire [31:0] csrbank1_dma_offset_w; +reg csrbank1_dma_offset_we = 1'd0; +wire csrbank1_sel; +wire [31:0] csrbank2_block_count0_r; +reg csrbank2_block_count0_re = 1'd0; +wire [31:0] csrbank2_block_count0_w; +reg csrbank2_block_count0_we = 1'd0; +wire [9:0] csrbank2_block_length0_r; +reg csrbank2_block_length0_re = 1'd0; +wire [9:0] csrbank2_block_length0_w; +reg csrbank2_block_length0_we = 1'd0; +wire [31:0] csrbank2_cmd_argument0_r; +reg csrbank2_cmd_argument0_re = 1'd0; +wire [31:0] csrbank2_cmd_argument0_w; +reg csrbank2_cmd_argument0_we = 1'd0; +wire [13:0] csrbank2_cmd_command0_r; +reg csrbank2_cmd_command0_re = 1'd0; +wire [13:0] csrbank2_cmd_command0_w; +reg csrbank2_cmd_command0_we = 1'd0; +wire [3:0] csrbank2_cmd_event_r; +reg csrbank2_cmd_event_re = 1'd0; +wire [3:0] csrbank2_cmd_event_w; +reg csrbank2_cmd_event_we = 1'd0; +wire [31:0] csrbank2_cmd_response0_r; +reg csrbank2_cmd_response0_re = 1'd0; +wire [31:0] csrbank2_cmd_response0_w; +reg csrbank2_cmd_response0_we = 1'd0; +wire [31:0] csrbank2_cmd_response1_r; +reg csrbank2_cmd_response1_re = 1'd0; +wire [31:0] csrbank2_cmd_response1_w; +reg csrbank2_cmd_response1_we = 1'd0; +wire [31:0] csrbank2_cmd_response2_r; +reg csrbank2_cmd_response2_re = 1'd0; +wire [31:0] csrbank2_cmd_response2_w; +reg csrbank2_cmd_response2_we = 1'd0; +wire [31:0] csrbank2_cmd_response3_r; +reg csrbank2_cmd_response3_re = 1'd0; +wire [31:0] csrbank2_cmd_response3_w; +reg csrbank2_cmd_response3_we = 1'd0; +wire csrbank2_cmd_send0_r; +reg csrbank2_cmd_send0_re = 1'd0; +wire csrbank2_cmd_send0_w; +reg csrbank2_cmd_send0_we = 1'd0; +wire [3:0] csrbank2_data_event_r; +reg csrbank2_data_event_re = 1'd0; +wire [3:0] csrbank2_data_event_w; +reg csrbank2_data_event_we = 1'd0; +wire csrbank2_sel; +wire [3:0] csrbank3_enable0_r; +reg csrbank3_enable0_re = 1'd0; +wire [3:0] csrbank3_enable0_w; +reg csrbank3_enable0_we = 1'd0; +wire [3:0] csrbank3_pending_r; +reg csrbank3_pending_re = 1'd0; +wire [3:0] csrbank3_pending_w; +reg csrbank3_pending_we = 1'd0; +wire csrbank3_sel; +wire [3:0] csrbank3_status_r; +reg csrbank3_status_re = 1'd0; +wire [3:0] csrbank3_status_w; +reg csrbank3_status_we = 1'd0; +wire [31:0] csrbank4_dma_base0_r; +reg csrbank4_dma_base0_re = 1'd0; +wire [31:0] csrbank4_dma_base0_w; +reg csrbank4_dma_base0_we = 1'd0; +wire [31:0] csrbank4_dma_base1_r; +reg csrbank4_dma_base1_re = 1'd0; +wire [31:0] csrbank4_dma_base1_w; +reg csrbank4_dma_base1_we = 1'd0; +wire csrbank4_dma_done_r; +reg csrbank4_dma_done_re = 1'd0; +wire csrbank4_dma_done_w; +reg csrbank4_dma_done_we = 1'd0; +wire csrbank4_dma_enable0_r; +reg csrbank4_dma_enable0_re = 1'd0; +wire csrbank4_dma_enable0_w; +reg csrbank4_dma_enable0_we = 1'd0; +wire [31:0] csrbank4_dma_length0_r; +reg csrbank4_dma_length0_re = 1'd0; +wire [31:0] csrbank4_dma_length0_w; +reg csrbank4_dma_length0_we = 1'd0; +wire csrbank4_dma_loop0_r; +reg csrbank4_dma_loop0_re = 1'd0; +wire csrbank4_dma_loop0_w; +reg csrbank4_dma_loop0_we = 1'd0; +wire [31:0] csrbank4_dma_offset_r; +reg csrbank4_dma_offset_re = 1'd0; +wire [31:0] csrbank4_dma_offset_w; +reg csrbank4_dma_offset_we = 1'd0; +wire csrbank4_sel; +wire csrbank5_card_detect_r; +reg csrbank5_card_detect_re = 1'd0; +wire csrbank5_card_detect_w; +reg csrbank5_card_detect_we = 1'd0; +wire [8:0] csrbank5_clocker_divider0_r; +reg csrbank5_clocker_divider0_re = 1'd0; +wire [8:0] csrbank5_clocker_divider0_w; +reg csrbank5_clocker_divider0_we = 1'd0; +wire [2:0] csrbank5_dataw_status_r; +reg csrbank5_dataw_status_re = 1'd0; +wire [2:0] csrbank5_dataw_status_w; +reg csrbank5_dataw_status_we = 1'd0; +wire csrbank5_sel; +wire [31:0] dat_r; +wire [31:0] dat_w; +reg [9:0] datar_count = 10'd0; +reg [9:0] datar_count_sdphydatar_next_value0 = 10'd0; +reg datar_count_sdphydatar_next_value_ce0 = 1'd0; +wire datar_datar_buf_pipe_valid_sink_first; +wire datar_datar_buf_pipe_valid_sink_last; +wire [7:0] datar_datar_buf_pipe_valid_sink_payload_data; +wire datar_datar_buf_pipe_valid_sink_ready; +wire datar_datar_buf_pipe_valid_sink_valid; +reg datar_datar_buf_pipe_valid_source_first = 1'd0; +reg datar_datar_buf_pipe_valid_source_last = 1'd0; +reg [7:0] datar_datar_buf_pipe_valid_source_payload_data = 8'd0; +wire datar_datar_buf_pipe_valid_source_ready; +reg datar_datar_buf_pipe_valid_source_valid = 1'd0; +wire datar_datar_buf_sink_sink_first; +wire datar_datar_buf_sink_sink_last; +wire [7:0] datar_datar_buf_sink_sink_payload_data; +wire datar_datar_buf_sink_sink_ready; +wire datar_datar_buf_sink_sink_valid; +wire datar_datar_buf_source_source_first; +wire datar_datar_buf_source_source_last; +wire [7:0] datar_datar_buf_source_source_payload_data; +wire datar_datar_buf_source_source_ready; +wire datar_datar_buf_source_source_valid; +reg datar_datar_converter_converter_demux = 1'd0; +wire datar_datar_converter_converter_load_part; +reg datar_datar_converter_converter_sink_first = 1'd0; +reg datar_datar_converter_converter_sink_last = 1'd0; +wire [3:0] datar_datar_converter_converter_sink_payload_data; +wire datar_datar_converter_converter_sink_ready; +wire datar_datar_converter_converter_sink_valid; +reg datar_datar_converter_converter_source_first = 1'd0; +reg datar_datar_converter_converter_source_last = 1'd0; +reg [7:0] datar_datar_converter_converter_source_payload_data = 8'd0; +reg [1:0] datar_datar_converter_converter_source_payload_valid_token_count = 2'd0; +wire datar_datar_converter_converter_source_ready; +wire datar_datar_converter_converter_source_valid; +reg datar_datar_converter_converter_strobe_all = 1'd0; +wire datar_datar_converter_source_source_first; +wire datar_datar_converter_source_source_last; +wire [7:0] datar_datar_converter_source_source_payload_data; +wire datar_datar_converter_source_source_ready; +wire datar_datar_converter_source_source_valid; +wire datar_datar_pads_in_first; +wire datar_datar_pads_in_last; +wire datar_datar_pads_in_payload_clk; +wire datar_datar_pads_in_payload_cmd_i; +wire datar_datar_pads_in_payload_cmd_o; +wire datar_datar_pads_in_payload_cmd_oe; +wire [3:0] datar_datar_pads_in_payload_data_i; +wire datar_datar_pads_in_payload_data_i_ce; +wire [3:0] datar_datar_pads_in_payload_data_o; +wire datar_datar_pads_in_payload_data_oe; +reg datar_datar_pads_in_ready = 1'd0; +wire datar_datar_pads_in_valid; +reg datar_datar_reset = 1'd0; +reg datar_datar_reset_sdphydatar_next_value2 = 1'd0; +reg datar_datar_reset_sdphydatar_next_value_ce2 = 1'd0; +reg datar_datar_run = 1'd0; +wire datar_datar_source_first; +wire datar_datar_source_last; +wire [7:0] datar_datar_source_payload_data; +reg datar_datar_source_ready = 1'd0; +wire datar_datar_source_valid; +wire datar_datar_start; +reg datar_pads_in_pads_in_first = 1'd0; +reg datar_pads_in_pads_in_last = 1'd0; +reg datar_pads_in_pads_in_payload_clk = 1'd0; +wire datar_pads_in_pads_in_payload_cmd_i; +reg datar_pads_in_pads_in_payload_cmd_o = 1'd0; +reg datar_pads_in_pads_in_payload_cmd_oe = 1'd0; +wire [3:0] datar_pads_in_pads_in_payload_data_i; +reg datar_pads_in_pads_in_payload_data_i_ce = 1'd0; +reg [3:0] datar_pads_in_pads_in_payload_data_o = 4'd0; +reg datar_pads_in_pads_in_payload_data_oe = 1'd0; +wire datar_pads_in_pads_in_ready; +wire datar_pads_in_pads_in_valid; +reg datar_pads_out_payload_clk = 1'd0; +reg datar_pads_out_payload_cmd_o = 1'd0; +reg datar_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] datar_pads_out_payload_data_o = 4'd0; +reg datar_pads_out_payload_data_oe = 1'd0; +wire datar_pads_out_ready; +reg datar_sink_last = 1'd0; +reg [9:0] datar_sink_payload_block_length = 10'd0; +reg datar_sink_ready = 1'd0; +reg datar_sink_valid = 1'd0; +reg datar_source_source_first = 1'd0; +reg datar_source_source_last = 1'd0; +reg [7:0] datar_source_source_payload_data = 8'd0; +reg [2:0] datar_source_source_payload_status = 3'd0; +reg datar_source_source_ready = 1'd0; +reg datar_source_source_valid = 1'd0; +reg datar_stop = 1'd0; +reg [31:0] datar_timeout = 32'd50000000; +reg [31:0] datar_timeout_sdphydatar_next_value1 = 32'd0; +reg datar_timeout_sdphydatar_next_value_ce1 = 1'd0; +wire dataw_accepted0; +reg dataw_accepted1 = 1'd0; +reg dataw_accepted1_sdphydataw_next_value0 = 1'd0; +reg dataw_accepted1_sdphydataw_next_value_ce0 = 1'd0; +reg [7:0] dataw_count = 8'd0; +reg [7:0] dataw_count_sdphydataw_next_value3 = 8'd0; +reg dataw_count_sdphydataw_next_value_ce3 = 1'd0; +wire dataw_crc_buf_pipe_valid_sink_first; +wire dataw_crc_buf_pipe_valid_sink_last; +wire [7:0] dataw_crc_buf_pipe_valid_sink_payload_data; +wire dataw_crc_buf_pipe_valid_sink_ready; +wire dataw_crc_buf_pipe_valid_sink_valid; +reg dataw_crc_buf_pipe_valid_source_first = 1'd0; +reg dataw_crc_buf_pipe_valid_source_last = 1'd0; +reg [7:0] dataw_crc_buf_pipe_valid_source_payload_data = 8'd0; +wire dataw_crc_buf_pipe_valid_source_ready; +reg dataw_crc_buf_pipe_valid_source_valid = 1'd0; +wire dataw_crc_buf_sink_sink_first; +wire dataw_crc_buf_sink_sink_last; +wire [7:0] dataw_crc_buf_sink_sink_payload_data; +wire dataw_crc_buf_sink_sink_ready; +wire dataw_crc_buf_sink_sink_valid; +wire dataw_crc_buf_source_source_first; +wire dataw_crc_buf_source_source_last; +wire [7:0] dataw_crc_buf_source_source_payload_data; +wire dataw_crc_buf_source_source_ready; +wire dataw_crc_buf_source_source_valid; +reg [2:0] dataw_crc_converter_converter_demux = 3'd0; +wire dataw_crc_converter_converter_load_part; +reg dataw_crc_converter_converter_sink_first = 1'd0; +reg dataw_crc_converter_converter_sink_last = 1'd0; +wire dataw_crc_converter_converter_sink_payload_data; +wire dataw_crc_converter_converter_sink_ready; +wire dataw_crc_converter_converter_sink_valid; +reg dataw_crc_converter_converter_source_first = 1'd0; +reg dataw_crc_converter_converter_source_last = 1'd0; +reg [7:0] dataw_crc_converter_converter_source_payload_data = 8'd0; +reg [3:0] dataw_crc_converter_converter_source_payload_valid_token_count = 4'd0; +wire dataw_crc_converter_converter_source_ready; +wire dataw_crc_converter_converter_source_valid; +reg dataw_crc_converter_converter_strobe_all = 1'd0; +wire dataw_crc_converter_source_source_first; +wire dataw_crc_converter_source_source_last; +wire [7:0] dataw_crc_converter_source_source_payload_data; +wire dataw_crc_converter_source_source_ready; +wire dataw_crc_converter_source_source_valid; +wire dataw_crc_error0; +reg dataw_crc_error1 = 1'd0; +reg dataw_crc_error1_sdphydataw_next_value1 = 1'd0; +reg dataw_crc_error1_sdphydataw_next_value_ce1 = 1'd0; +wire dataw_crc_pads_in_first; +wire dataw_crc_pads_in_last; +wire dataw_crc_pads_in_payload_clk; +wire dataw_crc_pads_in_payload_cmd_i; +wire dataw_crc_pads_in_payload_cmd_o; +wire dataw_crc_pads_in_payload_cmd_oe; +wire [3:0] dataw_crc_pads_in_payload_data_i; +wire dataw_crc_pads_in_payload_data_i_ce; +wire [3:0] dataw_crc_pads_in_payload_data_o; +wire dataw_crc_pads_in_payload_data_oe; +wire dataw_crc_pads_in_ready; +wire dataw_crc_pads_in_valid; +reg dataw_crc_reset = 1'd0; +reg dataw_crc_run = 1'd0; +wire dataw_crc_source_first; +wire dataw_crc_source_last; +wire [7:0] dataw_crc_source_payload_data; +reg dataw_crc_source_ready = 1'd0; +wire dataw_crc_source_valid; +wire dataw_crc_start; +reg dataw_pads_in_pads_in_first = 1'd0; +reg dataw_pads_in_pads_in_last = 1'd0; +reg dataw_pads_in_pads_in_payload_clk = 1'd0; +wire dataw_pads_in_pads_in_payload_cmd_i; +reg dataw_pads_in_pads_in_payload_cmd_o = 1'd0; +reg dataw_pads_in_pads_in_payload_cmd_oe = 1'd0; +wire [3:0] dataw_pads_in_pads_in_payload_data_i; +reg dataw_pads_in_pads_in_payload_data_i_ce = 1'd0; +reg [3:0] dataw_pads_in_pads_in_payload_data_o = 4'd0; +reg dataw_pads_in_pads_in_payload_data_oe = 1'd0; +reg dataw_pads_in_pads_in_ready = 1'd0; +wire dataw_pads_in_pads_in_valid; +reg dataw_pads_out_payload_clk = 1'd0; +reg dataw_pads_out_payload_cmd_o = 1'd0; +reg dataw_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] dataw_pads_out_payload_data_o = 4'd0; +reg dataw_pads_out_payload_data_oe = 1'd0; +wire dataw_pads_out_ready; +reg dataw_re = 1'd0; +reg dataw_sink_first = 1'd0; +reg dataw_sink_last = 1'd0; +reg [7:0] dataw_sink_payload_data = 8'd0; +reg dataw_sink_ready = 1'd0; +reg dataw_sink_valid = 1'd0; +reg [2:0] dataw_status = 3'd0; +reg dataw_stop = 1'd0; +wire dataw_we; +wire dataw_write_error0; +reg dataw_write_error1 = 1'd0; +reg dataw_write_error1_sdphydataw_next_value2 = 1'd0; +reg dataw_write_error1_sdphydataw_next_value_ce2 = 1'd0; +wire done; +reg error = 1'd0; +wire eventmanager_block2mem_dma0; +wire eventmanager_block2mem_dma1; +wire eventmanager_block2mem_dma2; +wire eventmanager_card_detect0; +wire eventmanager_card_detect1; +wire eventmanager_card_detect2; +wire eventmanager_cmd_done0; +wire eventmanager_cmd_done1; +wire eventmanager_cmd_done2; +reg eventmanager_enable_re = 1'd0; +reg [3:0] eventmanager_enable_storage = 4'd0; +wire eventmanager_mem2block_dma0; +wire eventmanager_mem2block_dma1; +wire eventmanager_mem2block_dma2; +reg [3:0] eventmanager_pending_r = 4'd0; +reg eventmanager_pending_re = 1'd0; +reg [3:0] eventmanager_pending_status = 4'd0; +wire eventmanager_pending_we; +reg eventmanager_status_re = 1'd0; +reg [3:0] eventmanager_status_status = 4'd0; +wire eventmanager_status_we; +reg [2:0] fsm_next_state = 3'd0; +reg [2:0] fsm_state = 3'd0; +reg grant = 1'd0; +wire inferedsdrtristate0__i; +wire inferedsdrtristate0__o; +reg inferedsdrtristate0_oe = 1'd0; +wire inferedsdrtristate1__i; +wire inferedsdrtristate1__o; +reg inferedsdrtristate1_oe = 1'd0; +wire inferedsdrtristate2__i; +wire inferedsdrtristate2__o; +reg inferedsdrtristate2_oe = 1'd0; +wire inferedsdrtristate3__i; +wire inferedsdrtristate3__o; +reg inferedsdrtristate3_oe = 1'd0; +wire inferedsdrtristate4__i; +wire inferedsdrtristate4__o; +reg inferedsdrtristate4_oe = 1'd0; +reg [7:0] init_count = 8'd0; +reg [7:0] init_count_sdphyinit_next_value = 8'd0; +reg init_count_sdphyinit_next_value_ce = 1'd0; +wire init_initialize_r; +reg init_initialize_re = 1'd0; +reg init_initialize_w = 1'd0; +reg init_initialize_we = 1'd0; +wire init_pads_in_payload_cmd_i; +wire [3:0] init_pads_in_payload_data_i; +wire init_pads_in_valid; +reg init_pads_out_payload_clk = 1'd0; +reg init_pads_out_payload_cmd_o = 1'd0; +reg init_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] init_pads_out_payload_data_o = 4'd0; +reg init_pads_out_payload_data_oe = 1'd0; +wire init_pads_out_ready; +reg int_rst = 1'd1; +reg interface0_ack = 1'd0; +wire [29:0] interface0_adr; +wire [13:0] interface0_bank_bus_adr; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; +wire [31:0] interface0_bank_bus_dat_w; +wire interface0_bank_bus_we; +wire [1:0] interface0_bte; +wire interface0_bus_ack; +wire [31:0] interface0_bus_adr; +reg [1:0] interface0_bus_bte = 2'd0; +reg [2:0] interface0_bus_cti = 3'd0; +wire interface0_bus_cyc; +wire [31:0] interface0_bus_dat_r; +wire [31:0] interface0_bus_dat_w; +wire interface0_bus_err; +wire [3:0] interface0_bus_sel; +wire interface0_bus_stb; +wire interface0_bus_we; +wire [2:0] interface0_cti; +wire interface0_cyc; +reg [31:0] interface0_dat_r = 32'd0; +wire [31:0] interface0_dat_w; +reg interface0_err = 1'd0; +wire [3:0] interface0_sel; +wire interface0_stb; +wire interface0_we; +reg [13:0] interface1_adr = 14'd0; +wire [13:0] interface1_bank_bus_adr; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; +wire [31:0] interface1_bank_bus_dat_w; +wire interface1_bank_bus_we; +wire interface1_bus_ack; +wire [31:0] interface1_bus_adr; +reg [1:0] interface1_bus_bte = 2'd0; +reg [2:0] interface1_bus_cti = 3'd0; +wire interface1_bus_cyc; +wire [31:0] interface1_bus_dat_r; +reg [31:0] interface1_bus_dat_w = 32'd0; +wire interface1_bus_err; +wire [3:0] interface1_bus_sel; +wire interface1_bus_stb; +wire interface1_bus_we; +wire [31:0] interface1_dat_r; +reg [31:0] interface1_dat_w = 32'd0; +reg interface1_we = 1'd0; +wire [13:0] interface2_bank_bus_adr; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; +wire [31:0] interface2_bank_bus_dat_w; +wire interface2_bank_bus_we; +wire [13:0] interface3_bank_bus_adr; +reg [31:0] interface3_bank_bus_dat_r = 32'd0; +wire [31:0] interface3_bank_bus_dat_w; +wire interface3_bank_bus_we; +wire [13:0] interface4_bank_bus_adr; +reg [31:0] interface4_bank_bus_dat_r = 32'd0; +wire [31:0] interface4_bank_bus_dat_w; +wire interface4_bank_bus_we; +wire [13:0] interface5_bank_bus_adr; +reg [31:0] interface5_bank_bus_dat_r = 32'd0; +wire [31:0] interface5_bank_bus_dat_w; +wire interface5_bank_bus_we; +reg mem2block_dma_clear = 1'd0; +reg mem2block_dma_pending = 1'd0; +wire mem2block_dma_status; +wire mem2block_dma_trigger; +wire por_clk; +wire [1:0] request; +reg reset_re = 1'd0; +reg [1:0] reset_storage = 2'd0; +reg scratch_re = 1'd0; +reg [31:0] scratch_storage = 32'd305419896; +reg [1:0] sdblock2memdma_next_state = 2'd0; +reg [1:0] sdblock2memdma_state = 2'd0; +reg sdcard_block2mem_connect = 1'd0; +reg [1:0] sdcard_block2mem_converter_demux = 2'd0; +wire sdcard_block2mem_converter_load_part; +wire sdcard_block2mem_converter_sink_first; +wire sdcard_block2mem_converter_sink_last; +wire [7:0] sdcard_block2mem_converter_sink_payload_data; +wire sdcard_block2mem_converter_sink_ready; +wire sdcard_block2mem_converter_sink_valid; +reg sdcard_block2mem_converter_source_first = 1'd0; +reg sdcard_block2mem_converter_source_last = 1'd0; +reg [31:0] sdcard_block2mem_converter_source_payload_data = 32'd0; +reg [2:0] sdcard_block2mem_converter_source_payload_valid_token_count = 3'd0; +wire sdcard_block2mem_converter_source_ready; +wire sdcard_block2mem_converter_source_valid; +reg sdcard_block2mem_converter_strobe_all = 1'd0; +reg sdcard_block2mem_done_d = 1'd0; +reg [8:0] sdcard_block2mem_fifo_consume = 9'd0; +wire sdcard_block2mem_fifo_do_read; +wire sdcard_block2mem_fifo_fifo_in_first; +wire sdcard_block2mem_fifo_fifo_in_last; +wire [7:0] sdcard_block2mem_fifo_fifo_in_payload_data; +wire sdcard_block2mem_fifo_fifo_out_first; +wire sdcard_block2mem_fifo_fifo_out_last; +wire [7:0] sdcard_block2mem_fifo_fifo_out_payload_data; +reg [9:0] sdcard_block2mem_fifo_level0 = 10'd0; +wire [9:0] sdcard_block2mem_fifo_level1; +reg [8:0] sdcard_block2mem_fifo_produce = 9'd0; +wire [8:0] sdcard_block2mem_fifo_rdport_adr; +wire [9:0] sdcard_block2mem_fifo_rdport_dat_r; +wire sdcard_block2mem_fifo_rdport_re; +wire sdcard_block2mem_fifo_re; +reg sdcard_block2mem_fifo_readable = 1'd0; +reg sdcard_block2mem_fifo_replace = 1'd0; +reg sdcard_block2mem_fifo_sink_first = 1'd0; +reg sdcard_block2mem_fifo_sink_last = 1'd0; +reg [7:0] sdcard_block2mem_fifo_sink_payload_data = 8'd0; +wire sdcard_block2mem_fifo_sink_ready; +reg sdcard_block2mem_fifo_sink_valid = 1'd0; +wire sdcard_block2mem_fifo_source_first; +wire sdcard_block2mem_fifo_source_last; +wire [7:0] sdcard_block2mem_fifo_source_payload_data; +wire sdcard_block2mem_fifo_source_ready; +wire sdcard_block2mem_fifo_source_valid; +wire [9:0] sdcard_block2mem_fifo_syncfifo_din; +wire [9:0] sdcard_block2mem_fifo_syncfifo_dout; +wire sdcard_block2mem_fifo_syncfifo_re; +wire sdcard_block2mem_fifo_syncfifo_readable; +wire sdcard_block2mem_fifo_syncfifo_we; +wire sdcard_block2mem_fifo_syncfifo_writable; +reg [8:0] sdcard_block2mem_fifo_wrport_adr = 9'd0; +wire [9:0] sdcard_block2mem_fifo_wrport_dat_r; +wire [9:0] sdcard_block2mem_fifo_wrport_dat_w; +wire sdcard_block2mem_fifo_wrport_we; +reg sdcard_block2mem_irq = 1'd0; +wire sdcard_block2mem_sink_sink_first; +wire sdcard_block2mem_sink_sink_last0; +reg sdcard_block2mem_sink_sink_last1 = 1'd0; +reg [31:0] sdcard_block2mem_sink_sink_payload_address = 32'd0; +wire [7:0] sdcard_block2mem_sink_sink_payload_data0; +reg [31:0] sdcard_block2mem_sink_sink_payload_data1 = 32'd0; +reg sdcard_block2mem_sink_sink_ready0 = 1'd0; +wire sdcard_block2mem_sink_sink_ready1; +wire sdcard_block2mem_sink_sink_valid0; +reg sdcard_block2mem_sink_sink_valid1 = 1'd0; +wire sdcard_block2mem_source_source_first; +wire sdcard_block2mem_source_source_last; +wire [31:0] sdcard_block2mem_source_source_payload_data; +wire sdcard_block2mem_source_source_ready; +wire sdcard_block2mem_source_source_valid; +wire sdcard_block2mem_start; +wire [31:0] sdcard_block2mem_wishbonedmawriter_base; +reg sdcard_block2mem_wishbonedmawriter_base_re = 1'd0; +reg [63:0] sdcard_block2mem_wishbonedmawriter_base_storage = 64'd0; +reg sdcard_block2mem_wishbonedmawriter_done_re = 1'd0; +reg sdcard_block2mem_wishbonedmawriter_done_status = 1'd0; +wire sdcard_block2mem_wishbonedmawriter_done_we; +reg sdcard_block2mem_wishbonedmawriter_enable_re = 1'd0; +reg sdcard_block2mem_wishbonedmawriter_enable_storage = 1'd0; +wire [31:0] sdcard_block2mem_wishbonedmawriter_length; +reg sdcard_block2mem_wishbonedmawriter_length_re = 1'd0; +reg [31:0] sdcard_block2mem_wishbonedmawriter_length_storage = 32'd0; +reg sdcard_block2mem_wishbonedmawriter_loop_re = 1'd0; +reg sdcard_block2mem_wishbonedmawriter_loop_storage = 1'd0; +reg [31:0] sdcard_block2mem_wishbonedmawriter_offset = 32'd0; +reg sdcard_block2mem_wishbonedmawriter_offset_re = 1'd0; +reg [31:0] sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value = 32'd0; +reg sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce = 1'd0; +wire [31:0] sdcard_block2mem_wishbonedmawriter_offset_status; +wire sdcard_block2mem_wishbonedmawriter_offset_we; +wire sdcard_block2mem_wishbonedmawriter_reset; +wire sdcard_block2mem_wishbonedmawriter_sink_first; +wire sdcard_block2mem_wishbonedmawriter_sink_last; +wire [31:0] sdcard_block2mem_wishbonedmawriter_sink_payload_data; +reg sdcard_block2mem_wishbonedmawriter_sink_ready = 1'd0; +wire sdcard_block2mem_wishbonedmawriter_sink_valid; +reg sdcard_core_block_count_re = 1'd0; +reg [31:0] sdcard_core_block_count_storage = 32'd0; +reg sdcard_core_block_length_re = 1'd0; +reg [9:0] sdcard_core_block_length_storage = 10'd0; +wire [5:0] sdcard_core_cmd; +reg sdcard_core_cmd_argument_re = 1'd0; +reg [31:0] sdcard_core_cmd_argument_storage = 32'd0; +reg sdcard_core_cmd_command_re = 1'd0; +reg [13:0] sdcard_core_cmd_command_storage = 14'd0; +reg [2:0] sdcard_core_cmd_count = 3'd0; +reg [2:0] sdcard_core_cmd_count_fsm_next_value2 = 3'd0; +reg sdcard_core_cmd_count_fsm_next_value_ce2 = 1'd0; +reg sdcard_core_cmd_done = 1'd0; +reg sdcard_core_cmd_done_fsm_next_value0 = 1'd0; +reg sdcard_core_cmd_done_fsm_next_value_ce0 = 1'd0; +reg sdcard_core_cmd_error = 1'd0; +reg sdcard_core_cmd_error_fsm_next_value4 = 1'd0; +reg sdcard_core_cmd_error_fsm_next_value_ce4 = 1'd0; +reg sdcard_core_cmd_event_re = 1'd0; +reg [3:0] sdcard_core_cmd_event_status = 4'd0; +wire sdcard_core_cmd_event_we; +reg sdcard_core_cmd_response_re = 1'd0; +reg [127:0] sdcard_core_cmd_response_status = 128'd0; +reg [127:0] sdcard_core_cmd_response_status_fsm_next_value8 = 128'd0; +reg sdcard_core_cmd_response_status_fsm_next_value_ce8 = 1'd0; +wire sdcard_core_cmd_response_we; +reg sdcard_core_cmd_send_re = 1'd0; +reg sdcard_core_cmd_send_storage = 1'd0; +reg sdcard_core_cmd_timeout = 1'd0; +reg sdcard_core_cmd_timeout_fsm_next_value5 = 1'd0; +reg sdcard_core_cmd_timeout_fsm_next_value_ce5 = 1'd0; +wire [1:0] sdcard_core_cmd_type; +reg [2:0] sdcard_core_crc16_inserter_count = 3'd0; +reg [2:0] sdcard_core_crc16_inserter_count_crc16inserter_next_value = 3'd0; +reg sdcard_core_crc16_inserter_count_crc16inserter_next_value_ce = 1'd0; +reg [15:0] sdcard_core_crc16_inserter_crc00 = 16'd0; +wire [15:0] sdcard_core_crc16_inserter_crc01; +wire [15:0] sdcard_core_crc16_inserter_crc02; +reg [15:0] sdcard_core_crc16_inserter_crc0_crc = 16'd0; +reg [1:0] sdcard_core_crc16_inserter_crc0_din = 2'd0; +wire sdcard_core_crc16_inserter_crc0_enable; +wire sdcard_core_crc16_inserter_crc0_reset; +reg [15:0] sdcard_core_crc16_inserter_crc10 = 16'd0; +wire [15:0] sdcard_core_crc16_inserter_crc11; +wire [15:0] sdcard_core_crc16_inserter_crc12; +reg [15:0] sdcard_core_crc16_inserter_crc1_crc = 16'd0; +reg [1:0] sdcard_core_crc16_inserter_crc1_din = 2'd0; +wire sdcard_core_crc16_inserter_crc1_enable; +wire sdcard_core_crc16_inserter_crc1_reset; +reg [15:0] sdcard_core_crc16_inserter_crc20 = 16'd0; +wire [15:0] sdcard_core_crc16_inserter_crc21; +wire [15:0] sdcard_core_crc16_inserter_crc22; +reg [15:0] sdcard_core_crc16_inserter_crc2_crc = 16'd0; +reg [1:0] sdcard_core_crc16_inserter_crc2_din = 2'd0; +wire sdcard_core_crc16_inserter_crc2_enable; +wire sdcard_core_crc16_inserter_crc2_reset; +reg [15:0] sdcard_core_crc16_inserter_crc30 = 16'd0; +wire [15:0] sdcard_core_crc16_inserter_crc31; +wire [15:0] sdcard_core_crc16_inserter_crc32; +reg [15:0] sdcard_core_crc16_inserter_crc3_crc = 16'd0; +reg [1:0] sdcard_core_crc16_inserter_crc3_din = 2'd0; +wire sdcard_core_crc16_inserter_crc3_enable; +wire sdcard_core_crc16_inserter_crc3_reset; +wire sdcard_core_crc16_inserter_sink_first; +wire sdcard_core_crc16_inserter_sink_last; +wire [7:0] sdcard_core_crc16_inserter_sink_payload_data; +reg sdcard_core_crc16_inserter_sink_ready = 1'd0; +wire sdcard_core_crc16_inserter_sink_valid; +reg sdcard_core_crc16_inserter_source_first = 1'd0; +reg sdcard_core_crc16_inserter_source_last = 1'd0; +reg [7:0] sdcard_core_crc16_inserter_source_payload_data = 8'd0; +reg sdcard_core_crc16_inserter_source_ready = 1'd0; +reg sdcard_core_crc16_inserter_source_valid = 1'd0; +reg [6:0] sdcard_core_crc7_inserter_crc0 = 7'd0; +wire [6:0] sdcard_core_crc7_inserter_crc1; +wire [6:0] sdcard_core_crc7_inserter_crc10; +wire [6:0] sdcard_core_crc7_inserter_crc11; +wire [6:0] sdcard_core_crc7_inserter_crc12; +wire [6:0] sdcard_core_crc7_inserter_crc13; +wire [6:0] sdcard_core_crc7_inserter_crc14; +wire [6:0] sdcard_core_crc7_inserter_crc15; +wire [6:0] sdcard_core_crc7_inserter_crc16; +wire [6:0] sdcard_core_crc7_inserter_crc17; +wire [6:0] sdcard_core_crc7_inserter_crc18; +wire [6:0] sdcard_core_crc7_inserter_crc19; +wire [6:0] sdcard_core_crc7_inserter_crc2; +wire [6:0] sdcard_core_crc7_inserter_crc20; +wire [6:0] sdcard_core_crc7_inserter_crc21; +wire [6:0] sdcard_core_crc7_inserter_crc22; +wire [6:0] sdcard_core_crc7_inserter_crc23; +wire [6:0] sdcard_core_crc7_inserter_crc24; +wire [6:0] sdcard_core_crc7_inserter_crc25; +wire [6:0] sdcard_core_crc7_inserter_crc26; +wire [6:0] sdcard_core_crc7_inserter_crc27; +wire [6:0] sdcard_core_crc7_inserter_crc28; +wire [6:0] sdcard_core_crc7_inserter_crc29; +wire [6:0] sdcard_core_crc7_inserter_crc3; +wire [6:0] sdcard_core_crc7_inserter_crc30; +wire [6:0] sdcard_core_crc7_inserter_crc31; +wire [6:0] sdcard_core_crc7_inserter_crc32; +wire [6:0] sdcard_core_crc7_inserter_crc33; +wire [6:0] sdcard_core_crc7_inserter_crc34; +wire [6:0] sdcard_core_crc7_inserter_crc35; +wire [6:0] sdcard_core_crc7_inserter_crc36; +wire [6:0] sdcard_core_crc7_inserter_crc37; +wire [6:0] sdcard_core_crc7_inserter_crc38; +wire [6:0] sdcard_core_crc7_inserter_crc39; +wire [6:0] sdcard_core_crc7_inserter_crc4; +wire [6:0] sdcard_core_crc7_inserter_crc40; +wire [6:0] sdcard_core_crc7_inserter_crc5; +wire [6:0] sdcard_core_crc7_inserter_crc6; +wire [6:0] sdcard_core_crc7_inserter_crc7; +wire [6:0] sdcard_core_crc7_inserter_crc8; +wire [6:0] sdcard_core_crc7_inserter_crc9; +reg [6:0] sdcard_core_crc7_inserter_crc_crc = 7'd0; +wire [39:0] sdcard_core_crc7_inserter_crc_din; +wire sdcard_core_crc7_inserter_crc_enable; +wire sdcard_core_crc7_inserter_crc_reset; +wire [5:0] sdcard_core_csrfield_cmd; +wire [1:0] sdcard_core_csrfield_cmd_type; +wire sdcard_core_csrfield_crc0; +wire sdcard_core_csrfield_crc1; +wire [1:0] sdcard_core_csrfield_data_type; +wire sdcard_core_csrfield_done0; +wire sdcard_core_csrfield_done1; +wire sdcard_core_csrfield_error0; +wire sdcard_core_csrfield_error1; +wire sdcard_core_csrfield_timeout0; +wire sdcard_core_csrfield_timeout1; +reg [31:0] sdcard_core_data_count = 32'd0; +reg [31:0] sdcard_core_data_count_fsm_next_value3 = 32'd0; +reg sdcard_core_data_count_fsm_next_value_ce3 = 1'd0; +reg sdcard_core_data_done = 1'd0; +reg sdcard_core_data_done_fsm_next_value1 = 1'd0; +reg sdcard_core_data_done_fsm_next_value_ce1 = 1'd0; +reg sdcard_core_data_error = 1'd0; +reg sdcard_core_data_error_fsm_next_value6 = 1'd0; +reg sdcard_core_data_error_fsm_next_value_ce6 = 1'd0; +reg sdcard_core_data_event_re = 1'd0; +reg [3:0] sdcard_core_data_event_status = 4'd0; +wire sdcard_core_data_event_we; +reg sdcard_core_data_timeout = 1'd0; +reg sdcard_core_data_timeout_fsm_next_value7 = 1'd0; +reg sdcard_core_data_timeout_fsm_next_value_ce7 = 1'd0; +wire [1:0] sdcard_core_data_type; +reg sdcard_core_done_d = 1'd0; +reg [2:0] sdcard_core_fifo_consume = 3'd0; +wire sdcard_core_fifo_do_read; +wire sdcard_core_fifo_fifo_in_first; +wire sdcard_core_fifo_fifo_in_last; +wire [7:0] sdcard_core_fifo_fifo_in_payload_data; +wire sdcard_core_fifo_fifo_out_first; +wire sdcard_core_fifo_fifo_out_last; +wire [7:0] sdcard_core_fifo_fifo_out_payload_data; +reg [3:0] sdcard_core_fifo_level = 4'd0; +reg [2:0] sdcard_core_fifo_produce = 3'd0; +wire [2:0] sdcard_core_fifo_rdport_adr; +wire [9:0] sdcard_core_fifo_rdport_dat_r; +reg sdcard_core_fifo_replace = 1'd0; +wire sdcard_core_fifo_reset; +wire sdcard_core_fifo_sink_first; +wire sdcard_core_fifo_sink_last; +wire [7:0] sdcard_core_fifo_sink_payload_data; +wire sdcard_core_fifo_sink_ready; +wire sdcard_core_fifo_sink_valid; +wire sdcard_core_fifo_source_first; +wire sdcard_core_fifo_source_last; +wire [7:0] sdcard_core_fifo_source_payload_data; +wire sdcard_core_fifo_source_ready; +wire sdcard_core_fifo_source_valid; +wire [9:0] sdcard_core_fifo_syncfifo_din; +wire [9:0] sdcard_core_fifo_syncfifo_dout; +wire sdcard_core_fifo_syncfifo_re; +wire sdcard_core_fifo_syncfifo_readable; +wire sdcard_core_fifo_syncfifo_we; +wire sdcard_core_fifo_syncfifo_writable; +reg [2:0] sdcard_core_fifo_wrport_adr = 3'd0; +wire [9:0] sdcard_core_fifo_wrport_dat_r; +wire [9:0] sdcard_core_fifo_wrport_dat_w; +wire sdcard_core_fifo_wrport_we; +reg sdcard_core_irq = 1'd0; +wire sdcard_core_sink_sink_first0; +reg sdcard_core_sink_sink_first1 = 1'd0; +wire sdcard_core_sink_sink_last0; +reg sdcard_core_sink_sink_last1 = 1'd0; +wire [7:0] sdcard_core_sink_sink_payload_data0; +reg [7:0] sdcard_core_sink_sink_payload_data1 = 8'd0; +wire sdcard_core_sink_sink_ready0; +wire sdcard_core_sink_sink_ready1; +wire sdcard_core_sink_sink_valid0; +reg sdcard_core_sink_sink_valid1 = 1'd0; +wire sdcard_core_source_source_first0; +wire sdcard_core_source_source_first1; +wire sdcard_core_source_source_last0; +wire sdcard_core_source_source_last1; +wire [7:0] sdcard_core_source_source_payload_data0; +wire [7:0] sdcard_core_source_source_payload_data1; +wire sdcard_core_source_source_ready0; +wire sdcard_core_source_source_ready1; +wire sdcard_core_source_source_valid0; +wire sdcard_core_source_source_valid1; +wire sdcard_irq_irq; +wire sdcard_mem2block_converter_converter_first; +wire sdcard_mem2block_converter_converter_last; +reg [1:0] sdcard_mem2block_converter_converter_mux = 2'd0; +wire sdcard_mem2block_converter_converter_sink_first; +wire sdcard_mem2block_converter_converter_sink_last; +wire [31:0] sdcard_mem2block_converter_converter_sink_payload_data; +wire sdcard_mem2block_converter_converter_sink_ready; +wire sdcard_mem2block_converter_converter_sink_valid; +wire sdcard_mem2block_converter_converter_source_first; +wire sdcard_mem2block_converter_converter_source_last; +reg [7:0] sdcard_mem2block_converter_converter_source_payload_data = 8'd0; +wire sdcard_mem2block_converter_converter_source_payload_valid_token_count; +wire sdcard_mem2block_converter_converter_source_ready; +wire sdcard_mem2block_converter_converter_source_valid; +wire sdcard_mem2block_converter_source_source_first; +wire sdcard_mem2block_converter_source_source_last; +wire [7:0] sdcard_mem2block_converter_source_source_payload_data; +wire sdcard_mem2block_converter_source_source_ready; +wire sdcard_mem2block_converter_source_source_valid; +reg [8:0] sdcard_mem2block_count = 9'd0; +wire [31:0] sdcard_mem2block_dma_base; +reg sdcard_mem2block_dma_base_re = 1'd0; +reg [63:0] sdcard_mem2block_dma_base_storage = 64'd0; +reg sdcard_mem2block_dma_done_re = 1'd0; +reg sdcard_mem2block_dma_done_status = 1'd0; +wire sdcard_mem2block_dma_done_we; +reg sdcard_mem2block_dma_enable_re = 1'd0; +reg sdcard_mem2block_dma_enable_storage = 1'd0; +reg [3:0] sdcard_mem2block_dma_fifo_consume = 4'd0; +wire sdcard_mem2block_dma_fifo_do_read; +wire sdcard_mem2block_dma_fifo_fifo_in_first; +wire sdcard_mem2block_dma_fifo_fifo_in_last; +wire [31:0] sdcard_mem2block_dma_fifo_fifo_in_payload_data; +wire sdcard_mem2block_dma_fifo_fifo_out_first; +wire sdcard_mem2block_dma_fifo_fifo_out_last; +wire [31:0] sdcard_mem2block_dma_fifo_fifo_out_payload_data; +reg [4:0] sdcard_mem2block_dma_fifo_level = 5'd0; +reg [3:0] sdcard_mem2block_dma_fifo_produce = 4'd0; +wire [3:0] sdcard_mem2block_dma_fifo_rdport_adr; +wire [33:0] sdcard_mem2block_dma_fifo_rdport_dat_r; +reg sdcard_mem2block_dma_fifo_replace = 1'd0; +reg sdcard_mem2block_dma_fifo_sink_first = 1'd0; +wire sdcard_mem2block_dma_fifo_sink_last; +wire [31:0] sdcard_mem2block_dma_fifo_sink_payload_data; +wire sdcard_mem2block_dma_fifo_sink_ready; +reg sdcard_mem2block_dma_fifo_sink_valid = 1'd0; +wire sdcard_mem2block_dma_fifo_source_first; +wire sdcard_mem2block_dma_fifo_source_last; +wire [31:0] sdcard_mem2block_dma_fifo_source_payload_data; +wire sdcard_mem2block_dma_fifo_source_ready; +wire sdcard_mem2block_dma_fifo_source_valid; +wire [33:0] sdcard_mem2block_dma_fifo_syncfifo_din; +wire [33:0] sdcard_mem2block_dma_fifo_syncfifo_dout; +wire sdcard_mem2block_dma_fifo_syncfifo_re; +wire sdcard_mem2block_dma_fifo_syncfifo_readable; +wire sdcard_mem2block_dma_fifo_syncfifo_we; +wire sdcard_mem2block_dma_fifo_syncfifo_writable; +reg [3:0] sdcard_mem2block_dma_fifo_wrport_adr = 4'd0; +wire [33:0] sdcard_mem2block_dma_fifo_wrport_dat_r; +wire [33:0] sdcard_mem2block_dma_fifo_wrport_dat_w; +wire sdcard_mem2block_dma_fifo_wrport_we; +wire [31:0] sdcard_mem2block_dma_length; +reg sdcard_mem2block_dma_length_re = 1'd0; +reg [31:0] sdcard_mem2block_dma_length_storage = 32'd0; +reg sdcard_mem2block_dma_loop_re = 1'd0; +reg sdcard_mem2block_dma_loop_storage = 1'd0; +reg [31:0] sdcard_mem2block_dma_offset = 32'd0; +reg sdcard_mem2block_dma_offset_re = 1'd0; +reg [31:0] sdcard_mem2block_dma_offset_sdmem2blockdma_next_value = 32'd0; +reg sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce = 1'd0; +wire [31:0] sdcard_mem2block_dma_offset_status; +wire sdcard_mem2block_dma_offset_we; +wire sdcard_mem2block_dma_reset; +reg sdcard_mem2block_dma_sink_sink_last = 1'd0; +reg [31:0] sdcard_mem2block_dma_sink_sink_payload_address = 32'd0; +reg sdcard_mem2block_dma_sink_sink_ready = 1'd0; +reg sdcard_mem2block_dma_sink_sink_valid = 1'd0; +wire sdcard_mem2block_dma_source_source_first; +wire sdcard_mem2block_dma_source_source_last; +wire [31:0] sdcard_mem2block_dma_source_source_payload_data; +wire sdcard_mem2block_dma_source_source_ready; +wire sdcard_mem2block_dma_source_source_valid; +reg sdcard_mem2block_done_d = 1'd0; +reg [8:0] sdcard_mem2block_fifo_consume = 9'd0; +wire sdcard_mem2block_fifo_do_read; +wire sdcard_mem2block_fifo_fifo_in_first; +wire sdcard_mem2block_fifo_fifo_in_last; +wire [7:0] sdcard_mem2block_fifo_fifo_in_payload_data; +wire sdcard_mem2block_fifo_fifo_out_first; +wire sdcard_mem2block_fifo_fifo_out_last; +wire [7:0] sdcard_mem2block_fifo_fifo_out_payload_data; +reg [9:0] sdcard_mem2block_fifo_level0 = 10'd0; +wire [9:0] sdcard_mem2block_fifo_level1; +reg [8:0] sdcard_mem2block_fifo_produce = 9'd0; +wire [8:0] sdcard_mem2block_fifo_rdport_adr; +wire [9:0] sdcard_mem2block_fifo_rdport_dat_r; +wire sdcard_mem2block_fifo_rdport_re; +wire sdcard_mem2block_fifo_re; +reg sdcard_mem2block_fifo_readable = 1'd0; +reg sdcard_mem2block_fifo_replace = 1'd0; +wire sdcard_mem2block_fifo_sink_first; +wire sdcard_mem2block_fifo_sink_last; +wire [7:0] sdcard_mem2block_fifo_sink_payload_data; +wire sdcard_mem2block_fifo_sink_ready; +wire sdcard_mem2block_fifo_sink_valid; +wire sdcard_mem2block_fifo_source_first; +wire sdcard_mem2block_fifo_source_last; +wire [7:0] sdcard_mem2block_fifo_source_payload_data; +wire sdcard_mem2block_fifo_source_ready; +wire sdcard_mem2block_fifo_source_valid; +wire [9:0] sdcard_mem2block_fifo_syncfifo_din; +wire [9:0] sdcard_mem2block_fifo_syncfifo_dout; +wire sdcard_mem2block_fifo_syncfifo_re; +wire sdcard_mem2block_fifo_syncfifo_readable; +wire sdcard_mem2block_fifo_syncfifo_we; +wire sdcard_mem2block_fifo_syncfifo_writable; +reg [8:0] sdcard_mem2block_fifo_wrport_adr = 9'd0; +wire [9:0] sdcard_mem2block_fifo_wrport_dat_r; +wire [9:0] sdcard_mem2block_fifo_wrport_dat_w; +wire sdcard_mem2block_fifo_wrport_we; +reg sdcard_mem2block_irq = 1'd0; +wire sdcard_mem2block_source_source_first; +reg sdcard_mem2block_source_source_last = 1'd0; +wire [7:0] sdcard_mem2block_source_source_payload_data; +wire sdcard_mem2block_source_source_ready; +wire sdcard_mem2block_source_source_valid; +reg [1:0] sdmem2blockdma_next_state = 2'd0; +reg [1:0] sdmem2blockdma_state = 2'd0; +wire sdpads_clk; +wire sdpads_cmd_i; +wire sdpads_cmd_o; +wire sdpads_cmd_oe; +wire [3:0] sdpads_data_i; +reg sdpads_data_i_ce = 1'd0; +wire [3:0] sdpads_data_o; +wire sdpads_data_oe; +reg [2:0] sdphycmdr_next_state = 3'd0; +reg [2:0] sdphycmdr_state = 3'd0; +reg [1:0] sdphycmdw_next_state = 2'd0; +reg [1:0] sdphycmdw_state = 2'd0; +reg [2:0] sdphydatar_next_state = 3'd0; +reg [2:0] sdphydatar_state = 3'd0; +reg [2:0] sdphydataw_next_state = 3'd0; +reg [2:0] sdphydataw_state = 3'd0; +reg sdphyinit_next_state = 1'd0; +reg sdphyinit_state = 1'd0; +wire sdrio_clk; +wire sdrio_clk_1; +wire sdrio_clk_2; +wire sdrio_clk_3; +wire sdrio_clk_4; +reg [31:0] self0 = 32'd0; +reg [31:0] self1 = 32'd0; +reg [3:0] self2 = 4'd0; +reg self3 = 1'd0; +reg self4 = 1'd0; +reg self5 = 1'd0; +reg [2:0] self6 = 3'd0; +reg [1:0] self7 = 2'd0; +reg shared_ack = 1'd0; +wire [31:0] shared_adr; +wire [1:0] shared_bte; +wire [2:0] shared_cti; +wire shared_cyc; +reg [31:0] shared_dat_r = 32'd0; +wire [31:0] shared_dat_w; +wire shared_err; +wire [3:0] shared_sel; +wire shared_stb; +wire shared_we; +reg slave_sel = 1'd0; +reg slave_sel_r = 1'd0; +reg soc_rst = 1'd0; +wire sys_clk; +wire sys_rst; +wire wait_1; +wire wb_ctrl_ack_1; +wire [29:0] wb_ctrl_adr_1; +wire [1:0] wb_ctrl_bte_1; +wire [2:0] wb_ctrl_cti_1; +wire wb_ctrl_cyc_1; +wire [31:0] wb_ctrl_dat_r_1; +wire [31:0] wb_ctrl_dat_w_1; +wire wb_ctrl_err_1; +wire [3:0] wb_ctrl_sel_1; +wire wb_ctrl_stb_1; +wire wb_ctrl_we_1; +wire wb_dma_ack_1; +wire [29:0] wb_dma_adr_1; +wire [1:0] wb_dma_bte_1; +wire [2:0] wb_dma_cti_1; +wire wb_dma_cyc_1; +wire [31:0] wb_dma_dat_r_1; +wire [31:0] wb_dma_dat_w_1; +wire wb_dma_err_1; +wire [3:0] wb_dma_sel_1; +wire wb_dma_stb_1; +wire wb_dma_we_1; +wire we; +reg wishbone2csr_next_state = 1'd0; +reg wishbone2csr_state = 1'd0; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + +assign wb_ctrl_adr_1 = wb_ctrl_adr; +assign wb_ctrl_dat_w_1 = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = wb_ctrl_dat_r_1; +assign wb_ctrl_sel_1 = wb_ctrl_sel; +assign wb_ctrl_cyc_1 = wb_ctrl_cyc; +assign wb_ctrl_stb_1 = wb_ctrl_stb; +assign wb_ctrl_ack = wb_ctrl_ack_1; +assign wb_ctrl_we_1 = wb_ctrl_we; +assign wb_ctrl_cti_1 = wb_ctrl_cti; +assign wb_ctrl_bte_1 = wb_ctrl_bte; +assign wb_ctrl_err = wb_ctrl_err_1; +assign wb_dma_adr = wb_dma_adr_1; +assign wb_dma_dat_w = wb_dma_dat_w_1; +assign wb_dma_dat_r_1 = wb_dma_dat_r; +assign wb_dma_sel = wb_dma_sel_1; +assign wb_dma_cyc = wb_dma_cyc_1; +assign wb_dma_stb = wb_dma_stb_1; +assign wb_dma_ack_1 = wb_dma_ack; +assign wb_dma_we = wb_dma_we_1; +assign wb_dma_cti = wb_dma_cti_1; +assign wb_dma_bte = wb_dma_bte_1; +assign wb_dma_err_1 = wb_dma_err; +assign sdcard_block2mem_sink_sink_valid0 = sdcard_core_source_source_valid0; +assign sdcard_core_source_source_ready0 = sdcard_block2mem_sink_sink_ready0; +assign sdcard_block2mem_sink_sink_first = sdcard_core_source_source_first0; +assign sdcard_block2mem_sink_sink_last0 = sdcard_core_source_source_last0; +assign sdcard_block2mem_sink_sink_payload_data0 = sdcard_core_source_source_payload_data0; +assign sdcard_core_sink_sink_valid0 = sdcard_mem2block_source_source_valid; +assign sdcard_mem2block_source_source_ready = sdcard_core_sink_sink_ready0; +assign sdcard_core_sink_sink_first0 = sdcard_mem2block_source_source_first; +assign sdcard_core_sink_sink_last0 = sdcard_mem2block_source_source_last; +assign sdcard_core_sink_sink_payload_data0 = sdcard_mem2block_source_source_payload_data; +assign block2mem_dma_trigger = sdcard_block2mem_irq; +assign mem2block_dma_trigger = sdcard_mem2block_irq; +assign card_detect_trigger = card_detect_irq; +assign cmd_done_trigger = sdcard_core_csrfield_done0; +assign irq = sdcard_irq_irq; +assign sys_clk = clk; +assign por_clk = clk; +assign sys_rst = int_rst; +assign interface0_adr = wb_ctrl_adr_1; +assign interface0_dat_w = wb_ctrl_dat_w_1; +assign wb_ctrl_dat_r_1 = interface0_dat_r; +assign interface0_sel = wb_ctrl_sel_1; +assign interface0_cyc = wb_ctrl_cyc_1; +assign interface0_stb = wb_ctrl_stb_1; +assign wb_ctrl_ack_1 = interface0_ack; +assign interface0_we = wb_ctrl_we_1; +assign interface0_cti = wb_ctrl_cti_1; +assign interface0_bte = wb_ctrl_bte_1; +assign wb_ctrl_err_1 = interface0_err; +assign bus_errors_status = bus_errors; +assign shared_adr = self0; +assign shared_dat_w = self1; +assign shared_sel = self2; +assign shared_cyc = self3; +assign shared_stb = self4; +assign shared_we = self5; +assign shared_cti = self6; +assign shared_bte = self7; +assign interface0_bus_dat_r = shared_dat_r; +assign interface1_bus_dat_r = shared_dat_r; +assign interface0_bus_ack = (shared_ack & (grant == 1'd0)); +assign interface1_bus_ack = (shared_ack & (grant == 1'd1)); +assign interface0_bus_err = (shared_err & (grant == 1'd0)); +assign interface1_bus_err = (shared_err & (grant == 1'd1)); +assign request = {interface1_bus_cyc, interface0_bus_cyc}; +always @(*) begin + slave_sel <= 1'd0; + slave_sel <= 1'd1; +end +assign wb_dma_adr_1 = shared_adr; +assign wb_dma_dat_w_1 = shared_dat_w; +assign wb_dma_sel_1 = shared_sel; +assign wb_dma_stb_1 = shared_stb; +assign wb_dma_we_1 = shared_we; +assign wb_dma_cti_1 = shared_cti; +assign wb_dma_bte_1 = shared_bte; +assign wb_dma_cyc_1 = (shared_cyc & slave_sel); +assign shared_err = wb_dma_err_1; +assign wait_1 = ((shared_stb & shared_cyc) & (~shared_ack)); +always @(*) begin + error <= 1'd0; + shared_ack <= 1'd0; + shared_dat_r <= 32'd0; + shared_ack <= wb_dma_ack_1; + shared_dat_r <= ({32{slave_sel_r}} & wb_dma_dat_r_1); + if (done) begin + shared_dat_r <= 32'd4294967295; + shared_ack <= 1'd1; + error <= 1'd1; + end +end +assign done = (count == 1'd0); +assign card_detect_status0 = sdcard_cd; +assign sdpads_clk = ((((init_pads_out_payload_clk | cmdw_pads_out_payload_clk) | cmdr_pads_out_payload_clk) | dataw_pads_out_payload_clk) | datar_pads_out_payload_clk); +assign sdpads_cmd_oe = ((((init_pads_out_payload_cmd_oe | cmdw_pads_out_payload_cmd_oe) | cmdr_pads_out_payload_cmd_oe) | dataw_pads_out_payload_cmd_oe) | datar_pads_out_payload_cmd_oe); +assign sdpads_cmd_o = ((((init_pads_out_payload_cmd_o | cmdw_pads_out_payload_cmd_o) | cmdr_pads_out_payload_cmd_o) | dataw_pads_out_payload_cmd_o) | datar_pads_out_payload_cmd_o); +assign sdpads_data_oe = ((((init_pads_out_payload_data_oe | cmdw_pads_out_payload_data_oe) | cmdr_pads_out_payload_data_oe) | dataw_pads_out_payload_data_oe) | datar_pads_out_payload_data_oe); +assign sdpads_data_o = ((((init_pads_out_payload_data_o | cmdw_pads_out_payload_data_o) | cmdr_pads_out_payload_data_o) | dataw_pads_out_payload_data_o) | datar_pads_out_payload_data_o); +assign init_pads_out_ready = clocker_ce; +assign cmdw_pads_out_ready = clocker_ce; +assign cmdr_pads_out_ready = clocker_ce; +assign dataw_pads_out_ready = clocker_ce; +assign datar_pads_out_ready = clocker_ce; +assign clocker_clk_en = sdpads_clk; +assign init_pads_in_valid = sdpads_data_i_ce; +assign init_pads_in_payload_cmd_i = sdpads_cmd_i; +assign init_pads_in_payload_data_i = sdpads_data_i; +assign cmdw_pads_in_valid = sdpads_data_i_ce; +assign cmdw_pads_in_payload_cmd_i = sdpads_cmd_i; +assign cmdw_pads_in_payload_data_i = sdpads_data_i; +assign cmdr_pads_in_pads_in_valid = sdpads_data_i_ce; +assign cmdr_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; +assign cmdr_pads_in_pads_in_payload_data_i = sdpads_data_i; +assign dataw_pads_in_pads_in_valid = sdpads_data_i_ce; +assign dataw_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; +assign dataw_pads_in_pads_in_payload_data_i = sdpads_data_i; +assign datar_pads_in_pads_in_valid = sdpads_data_i_ce; +assign datar_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; +assign datar_pads_in_pads_in_payload_data_i = sdpads_data_i; +assign clocker_stop = (dataw_stop | datar_stop); +always @(*) begin + clocker_clk1 <= 1'd0; + case (clocker_storage) + 3'd4: begin + clocker_clk1 <= clocker_clks[1]; + end + 4'd8: begin + clocker_clk1 <= clocker_clks[2]; + end + 5'd16: begin + clocker_clk1 <= clocker_clks[3]; + end + 6'd32: begin + clocker_clk1 <= clocker_clks[4]; + end + 7'd64: begin + clocker_clk1 <= clocker_clks[5]; + end + 8'd128: begin + clocker_clk1 <= clocker_clks[6]; + end + 9'd256: begin + clocker_clk1 <= clocker_clks[7]; + end + default: begin + clocker_clk1 <= clocker_clks[0]; + end + endcase +end +assign clocker_ce = (clocker_clk1 & (~clocker_clk_d)); +always @(*) begin + clocker_ce_latched <= 1'd0; + if (clocker_clk_d) begin + clocker_ce_latched <= clocker_clk_en; + end else begin + clocker_ce_latched <= clocker_ce_delayed; + end +end +assign clocker_clk0 = ((~clocker_clk1) & clocker_ce_latched); +always @(*) begin + init_count_sdphyinit_next_value <= 8'd0; + init_count_sdphyinit_next_value_ce <= 1'd0; + init_pads_out_payload_clk <= 1'd0; + init_pads_out_payload_cmd_o <= 1'd0; + init_pads_out_payload_cmd_oe <= 1'd0; + init_pads_out_payload_data_o <= 4'd0; + init_pads_out_payload_data_oe <= 1'd0; + sdphyinit_next_state <= 1'd0; + sdphyinit_next_state <= sdphyinit_state; + case (sdphyinit_state) + 1'd1: begin + init_pads_out_payload_clk <= 1'd1; + init_pads_out_payload_cmd_oe <= 1'd1; + init_pads_out_payload_cmd_o <= 1'd1; + init_pads_out_payload_data_oe <= 1'd1; + init_pads_out_payload_data_o <= 4'd15; + if (init_pads_out_ready) begin + init_count_sdphyinit_next_value <= (init_count + 1'd1); + init_count_sdphyinit_next_value_ce <= 1'd1; + if ((init_count == 7'd79)) begin + sdphyinit_next_state <= 1'd0; + end + end + end + default: begin + init_count_sdphyinit_next_value <= 1'd0; + init_count_sdphyinit_next_value_ce <= 1'd1; + if (init_initialize_re) begin + sdphyinit_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + cmdw_count_sdphycmdw_next_value <= 8'd0; + cmdw_count_sdphycmdw_next_value_ce <= 1'd0; + cmdw_done <= 1'd0; + cmdw_pads_out_payload_clk <= 1'd0; + cmdw_pads_out_payload_cmd_o <= 1'd0; + cmdw_pads_out_payload_cmd_oe <= 1'd0; + cmdw_sink_ready <= 1'd0; + sdphycmdw_next_state <= 2'd0; + sdphycmdw_next_state <= sdphycmdw_state; + case (sdphycmdw_state) + 1'd1: begin + cmdw_pads_out_payload_clk <= 1'd1; + cmdw_pads_out_payload_cmd_oe <= 1'd1; + case (cmdw_count) + 1'd0: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[7]; + end + 1'd1: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[6]; + end + 2'd2: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[5]; + end + 2'd3: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[4]; + end + 3'd4: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[3]; + end + 3'd5: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[2]; + end + 3'd6: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[1]; + end + 3'd7: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[0]; + end + endcase + if (cmdw_pads_out_ready) begin + cmdw_count_sdphycmdw_next_value <= (cmdw_count + 1'd1); + cmdw_count_sdphycmdw_next_value_ce <= 1'd1; + if ((cmdw_count == 3'd7)) begin + if ((cmdw_sink_last & (cmdw_sink_payload_cmd_type == 1'd0))) begin + sdphycmdw_next_state <= 2'd2; + end else begin + cmdw_sink_ready <= 1'd1; + sdphycmdw_next_state <= 1'd0; + end + end + end + end + 2'd2: begin + cmdw_pads_out_payload_clk <= 1'd1; + cmdw_pads_out_payload_cmd_oe <= 1'd1; + cmdw_pads_out_payload_cmd_o <= 1'd1; + if (cmdw_pads_out_ready) begin + cmdw_count_sdphycmdw_next_value <= (cmdw_count + 1'd1); + cmdw_count_sdphycmdw_next_value_ce <= 1'd1; + if ((cmdw_count == 3'd7)) begin + cmdw_sink_ready <= 1'd1; + sdphycmdw_next_state <= 1'd0; + end + end + end + default: begin + cmdw_count_sdphycmdw_next_value <= 1'd0; + cmdw_count_sdphycmdw_next_value_ce <= 1'd1; + if ((cmdw_sink_valid & cmdw_pads_out_ready)) begin + sdphycmdw_next_state <= 1'd1; + end else begin + cmdw_done <= 1'd1; + end + end + endcase +end +assign cmdr_cmdr_pads_in_valid = cmdr_pads_in_pads_in_valid; +assign cmdr_pads_in_pads_in_ready = cmdr_cmdr_pads_in_ready; +assign cmdr_cmdr_pads_in_first = cmdr_pads_in_pads_in_first; +assign cmdr_cmdr_pads_in_last = cmdr_pads_in_pads_in_last; +assign cmdr_cmdr_pads_in_payload_clk = cmdr_pads_in_pads_in_payload_clk; +assign cmdr_cmdr_pads_in_payload_cmd_i = cmdr_pads_in_pads_in_payload_cmd_i; +assign cmdr_cmdr_pads_in_payload_cmd_o = cmdr_pads_in_pads_in_payload_cmd_o; +assign cmdr_cmdr_pads_in_payload_cmd_oe = cmdr_pads_in_pads_in_payload_cmd_oe; +assign cmdr_cmdr_pads_in_payload_data_i = cmdr_pads_in_pads_in_payload_data_i; +assign cmdr_cmdr_pads_in_payload_data_o = cmdr_pads_in_pads_in_payload_data_o; +assign cmdr_cmdr_pads_in_payload_data_oe = cmdr_pads_in_pads_in_payload_data_oe; +assign cmdr_cmdr_pads_in_payload_data_i_ce = cmdr_pads_in_pads_in_payload_data_i_ce; +assign cmdr_cmdr_start = (cmdr_cmdr_pads_in_payload_cmd_i == 1'd0); +assign cmdr_cmdr_converter_converter_sink_valid = (cmdr_cmdr_pads_in_valid & (cmdr_cmdr_start | cmdr_cmdr_run)); +assign cmdr_cmdr_converter_converter_sink_payload_data = cmdr_cmdr_pads_in_payload_cmd_i; +assign cmdr_cmdr_buf_sink_sink_valid = cmdr_cmdr_converter_source_source_valid; +assign cmdr_cmdr_converter_source_source_ready = cmdr_cmdr_buf_sink_sink_ready; +assign cmdr_cmdr_buf_sink_sink_first = cmdr_cmdr_converter_source_source_first; +assign cmdr_cmdr_buf_sink_sink_last = cmdr_cmdr_converter_source_source_last; +assign cmdr_cmdr_buf_sink_sink_payload_data = cmdr_cmdr_converter_source_source_payload_data; +assign cmdr_cmdr_source_valid = cmdr_cmdr_buf_source_source_valid; +assign cmdr_cmdr_buf_source_source_ready = cmdr_cmdr_source_ready; +assign cmdr_cmdr_source_first = cmdr_cmdr_buf_source_source_first; +assign cmdr_cmdr_source_last = cmdr_cmdr_buf_source_source_last; +assign cmdr_cmdr_source_payload_data = cmdr_cmdr_buf_source_source_payload_data; +assign cmdr_cmdr_converter_source_source_valid = cmdr_cmdr_converter_converter_source_valid; +assign cmdr_cmdr_converter_converter_source_ready = cmdr_cmdr_converter_source_source_ready; +assign cmdr_cmdr_converter_source_source_first = cmdr_cmdr_converter_converter_source_first; +assign cmdr_cmdr_converter_source_source_last = cmdr_cmdr_converter_converter_source_last; +assign cmdr_cmdr_converter_source_source_payload_data = cmdr_cmdr_converter_converter_source_payload_data; +assign cmdr_cmdr_converter_converter_sink_ready = ((~cmdr_cmdr_converter_converter_strobe_all) | cmdr_cmdr_converter_converter_source_ready); +assign cmdr_cmdr_converter_converter_source_valid = cmdr_cmdr_converter_converter_strobe_all; +assign cmdr_cmdr_converter_converter_load_part = (cmdr_cmdr_converter_converter_sink_valid & cmdr_cmdr_converter_converter_sink_ready); +assign cmdr_cmdr_buf_pipe_valid_sink_ready = ((~cmdr_cmdr_buf_pipe_valid_source_valid) | cmdr_cmdr_buf_pipe_valid_source_ready); +assign cmdr_cmdr_buf_pipe_valid_sink_valid = cmdr_cmdr_buf_sink_sink_valid; +assign cmdr_cmdr_buf_sink_sink_ready = cmdr_cmdr_buf_pipe_valid_sink_ready; +assign cmdr_cmdr_buf_pipe_valid_sink_first = cmdr_cmdr_buf_sink_sink_first; +assign cmdr_cmdr_buf_pipe_valid_sink_last = cmdr_cmdr_buf_sink_sink_last; +assign cmdr_cmdr_buf_pipe_valid_sink_payload_data = cmdr_cmdr_buf_sink_sink_payload_data; +assign cmdr_cmdr_buf_source_source_valid = cmdr_cmdr_buf_pipe_valid_source_valid; +assign cmdr_cmdr_buf_pipe_valid_source_ready = cmdr_cmdr_buf_source_source_ready; +assign cmdr_cmdr_buf_source_source_first = cmdr_cmdr_buf_pipe_valid_source_first; +assign cmdr_cmdr_buf_source_source_last = cmdr_cmdr_buf_pipe_valid_source_last; +assign cmdr_cmdr_buf_source_source_payload_data = cmdr_cmdr_buf_pipe_valid_source_payload_data; +always @(*) begin + cmdr_busy_sdphycmdr_next_value2 <= 1'd0; + cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd0; + cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd0; + cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd0; + cmdr_cmdr_source_ready <= 1'd0; + cmdr_count_sdphycmdr_next_value1 <= 8'd0; + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd0; + cmdr_pads_out_payload_clk <= 1'd0; + cmdr_pads_out_payload_cmd_o <= 1'd0; + cmdr_pads_out_payload_cmd_oe <= 1'd0; + cmdr_sink_ready <= 1'd0; + cmdr_source_source_last <= 1'd0; + cmdr_source_source_payload_data <= 8'd0; + cmdr_source_source_payload_status <= 3'd0; + cmdr_source_source_valid <= 1'd0; + cmdr_timeout_sdphycmdr_next_value0 <= 32'd0; + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd0; + sdphycmdr_next_state <= 3'd0; + sdphycmdr_next_state <= sdphycmdr_state; + case (sdphycmdr_state) + 1'd1: begin + cmdr_pads_out_payload_clk <= 1'd1; + cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd0; + cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd1; + if (cmdr_cmdr_source_valid) begin + sdphycmdr_next_state <= 2'd2; + end + cmdr_timeout_sdphycmdr_next_value0 <= (cmdr_timeout - 1'd1); + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + if ((cmdr_timeout == 1'd0)) begin + sdphycmdr_next_state <= 3'd5; + end + end + 2'd2: begin + cmdr_pads_out_payload_clk <= 1'd1; + cmdr_source_source_valid <= cmdr_cmdr_source_valid; + cmdr_source_source_payload_status <= 1'd0; + cmdr_source_source_last <= (cmdr_count == (cmdr_sink_payload_length - 1'd1)); + cmdr_source_source_payload_data <= cmdr_cmdr_source_payload_data; + if ((cmdr_cmdr_source_valid & cmdr_source_source_ready)) begin + cmdr_cmdr_source_ready <= 1'd1; + cmdr_count_sdphycmdr_next_value1 <= (cmdr_count + 1'd1); + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + if (cmdr_source_source_last) begin + cmdr_sink_ready <= 1'd1; + if ((cmdr_sink_payload_cmd_type == 2'd3)) begin + cmdr_source_source_valid <= 1'd0; + cmdr_timeout_sdphycmdr_next_value0 <= 26'd50000000; + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + sdphycmdr_next_state <= 2'd3; + end else begin + if ((cmdr_sink_payload_data_type == 1'd0)) begin + cmdr_count_sdphycmdr_next_value1 <= 1'd0; + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + sdphycmdr_next_state <= 3'd4; + end else begin + sdphycmdr_next_state <= 1'd0; + end + end + end + end + cmdr_timeout_sdphycmdr_next_value0 <= (cmdr_timeout - 1'd1); + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + if ((cmdr_timeout == 1'd0)) begin + sdphycmdr_next_state <= 3'd5; + end + end + 2'd3: begin + cmdr_pads_out_payload_clk <= 1'd1; + if ((cmdr_pads_in_pads_in_valid & cmdr_pads_in_pads_in_payload_data_i[0])) begin + cmdr_busy_sdphycmdr_next_value2 <= 1'd0; + cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd1; + end + if ((~cmdr_busy)) begin + cmdr_source_source_valid <= 1'd1; + cmdr_source_source_last <= 1'd1; + cmdr_source_source_payload_status <= 1'd0; + if (cmdr_source_source_ready) begin + cmdr_count_sdphycmdr_next_value1 <= 1'd0; + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + sdphycmdr_next_state <= 3'd4; + end + end + cmdr_timeout_sdphycmdr_next_value0 <= (cmdr_timeout - 1'd1); + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + if ((cmdr_timeout == 1'd0)) begin + sdphycmdr_next_state <= 3'd5; + end + end + 3'd4: begin + cmdr_pads_out_payload_clk <= 1'd1; + cmdr_pads_out_payload_cmd_oe <= 1'd1; + cmdr_pads_out_payload_cmd_o <= 1'd1; + if (cmdr_pads_out_ready) begin + cmdr_count_sdphycmdr_next_value1 <= (cmdr_count + 1'd1); + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + if ((cmdr_count == 3'd7)) begin + sdphycmdr_next_state <= 1'd0; + end + end + end + 3'd5: begin + cmdr_sink_ready <= 1'd1; + cmdr_source_source_valid <= 1'd1; + cmdr_source_source_last <= 1'd1; + cmdr_source_source_payload_status <= 1'd1; + if (cmdr_source_source_ready) begin + sdphycmdr_next_state <= 1'd0; + end + end + default: begin + cmdr_timeout_sdphycmdr_next_value0 <= 26'd50000000; + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + cmdr_count_sdphycmdr_next_value1 <= 1'd0; + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + cmdr_busy_sdphycmdr_next_value2 <= 1'd1; + cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd1; + if (((cmdr_sink_valid & cmdr_pads_out_ready) & cmdw_done)) begin + cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd1; + cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd1; + sdphycmdr_next_state <= 1'd1; + end + end + endcase +end +assign dataw_accepted0 = dataw_accepted1; +assign dataw_crc_error0 = dataw_crc_error1; +assign dataw_write_error0 = dataw_write_error1; +assign dataw_crc_pads_in_valid = dataw_pads_in_pads_in_valid; +assign dataw_crc_pads_in_ready = dataw_pads_in_pads_in_ready; +assign dataw_crc_pads_in_first = dataw_pads_in_pads_in_first; +assign dataw_crc_pads_in_last = dataw_pads_in_pads_in_last; +assign dataw_crc_pads_in_payload_clk = dataw_pads_in_pads_in_payload_clk; +assign dataw_crc_pads_in_payload_cmd_i = dataw_pads_in_pads_in_payload_cmd_i; +assign dataw_crc_pads_in_payload_cmd_o = dataw_pads_in_pads_in_payload_cmd_o; +assign dataw_crc_pads_in_payload_cmd_oe = dataw_pads_in_pads_in_payload_cmd_oe; +assign dataw_crc_pads_in_payload_data_i = dataw_pads_in_pads_in_payload_data_i; +assign dataw_crc_pads_in_payload_data_o = dataw_pads_in_pads_in_payload_data_o; +assign dataw_crc_pads_in_payload_data_oe = dataw_pads_in_pads_in_payload_data_oe; +assign dataw_crc_pads_in_payload_data_i_ce = dataw_pads_in_pads_in_payload_data_i_ce; +assign dataw_crc_start = (dataw_crc_pads_in_payload_data_i[0] == 1'd0); +assign dataw_crc_converter_converter_sink_valid = (dataw_crc_pads_in_valid & dataw_crc_run); +assign dataw_crc_converter_converter_sink_payload_data = dataw_crc_pads_in_payload_data_i[0]; +assign dataw_crc_buf_sink_sink_valid = dataw_crc_converter_source_source_valid; +assign dataw_crc_converter_source_source_ready = dataw_crc_buf_sink_sink_ready; +assign dataw_crc_buf_sink_sink_first = dataw_crc_converter_source_source_first; +assign dataw_crc_buf_sink_sink_last = dataw_crc_converter_source_source_last; +assign dataw_crc_buf_sink_sink_payload_data = dataw_crc_converter_source_source_payload_data; +assign dataw_crc_source_valid = dataw_crc_buf_source_source_valid; +assign dataw_crc_buf_source_source_ready = dataw_crc_source_ready; +assign dataw_crc_source_first = dataw_crc_buf_source_source_first; +assign dataw_crc_source_last = dataw_crc_buf_source_source_last; +assign dataw_crc_source_payload_data = dataw_crc_buf_source_source_payload_data; +assign dataw_crc_converter_source_source_valid = dataw_crc_converter_converter_source_valid; +assign dataw_crc_converter_converter_source_ready = dataw_crc_converter_source_source_ready; +assign dataw_crc_converter_source_source_first = dataw_crc_converter_converter_source_first; +assign dataw_crc_converter_source_source_last = dataw_crc_converter_converter_source_last; +assign dataw_crc_converter_source_source_payload_data = dataw_crc_converter_converter_source_payload_data; +assign dataw_crc_converter_converter_sink_ready = ((~dataw_crc_converter_converter_strobe_all) | dataw_crc_converter_converter_source_ready); +assign dataw_crc_converter_converter_source_valid = dataw_crc_converter_converter_strobe_all; +assign dataw_crc_converter_converter_load_part = (dataw_crc_converter_converter_sink_valid & dataw_crc_converter_converter_sink_ready); +assign dataw_crc_buf_pipe_valid_sink_ready = ((~dataw_crc_buf_pipe_valid_source_valid) | dataw_crc_buf_pipe_valid_source_ready); +assign dataw_crc_buf_pipe_valid_sink_valid = dataw_crc_buf_sink_sink_valid; +assign dataw_crc_buf_sink_sink_ready = dataw_crc_buf_pipe_valid_sink_ready; +assign dataw_crc_buf_pipe_valid_sink_first = dataw_crc_buf_sink_sink_first; +assign dataw_crc_buf_pipe_valid_sink_last = dataw_crc_buf_sink_sink_last; +assign dataw_crc_buf_pipe_valid_sink_payload_data = dataw_crc_buf_sink_sink_payload_data; +assign dataw_crc_buf_source_source_valid = dataw_crc_buf_pipe_valid_source_valid; +assign dataw_crc_buf_pipe_valid_source_ready = dataw_crc_buf_source_source_ready; +assign dataw_crc_buf_source_source_first = dataw_crc_buf_pipe_valid_source_first; +assign dataw_crc_buf_source_source_last = dataw_crc_buf_pipe_valid_source_last; +assign dataw_crc_buf_source_source_payload_data = dataw_crc_buf_pipe_valid_source_payload_data; +always @(*) begin + dataw_accepted1_sdphydataw_next_value0 <= 1'd0; + dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd0; + dataw_count_sdphydataw_next_value3 <= 8'd0; + dataw_count_sdphydataw_next_value_ce3 <= 1'd0; + dataw_crc_error1_sdphydataw_next_value1 <= 1'd0; + dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd0; + dataw_crc_reset <= 1'd0; + dataw_pads_out_payload_clk <= 1'd0; + dataw_pads_out_payload_cmd_o <= 1'd0; + dataw_pads_out_payload_cmd_oe <= 1'd0; + dataw_pads_out_payload_data_o <= 4'd0; + dataw_pads_out_payload_data_oe <= 1'd0; + dataw_sink_ready <= 1'd0; + dataw_stop <= 1'd0; + dataw_write_error1_sdphydataw_next_value2 <= 1'd0; + dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd0; + sdphydataw_next_state <= 3'd0; + sdphydataw_next_state <= sdphydataw_state; + case (sdphydataw_state) + 1'd1: begin + dataw_pads_out_payload_clk <= 1'd1; + dataw_pads_out_payload_cmd_oe <= 1'd1; + dataw_pads_out_payload_cmd_o <= 1'd1; + if (dataw_pads_out_ready) begin + dataw_count_sdphydataw_next_value3 <= (dataw_count + 1'd1); + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + if ((dataw_count == 3'd7)) begin + dataw_count_sdphydataw_next_value3 <= 1'd0; + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + sdphydataw_next_state <= 2'd2; + end + end + end + 2'd2: begin + dataw_pads_out_payload_clk <= 1'd1; + dataw_pads_out_payload_data_oe <= 1'd1; + dataw_pads_out_payload_data_o <= 1'd0; + if (dataw_pads_out_ready) begin + sdphydataw_next_state <= 2'd3; + end + end + 2'd3: begin + dataw_stop <= (~dataw_sink_valid); + dataw_pads_out_payload_clk <= 1'd1; + dataw_pads_out_payload_data_oe <= 1'd1; + case (dataw_count) + 1'd0: begin + dataw_pads_out_payload_data_o <= dataw_sink_payload_data[7:4]; + end + 1'd1: begin + dataw_pads_out_payload_data_o <= dataw_sink_payload_data[3:0]; + end + endcase + if (dataw_pads_out_ready) begin + dataw_count_sdphydataw_next_value3 <= (dataw_count + 1'd1); + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + if ((dataw_count == 1'd1)) begin + dataw_count_sdphydataw_next_value3 <= 1'd0; + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + if (dataw_sink_last) begin + sdphydataw_next_state <= 3'd4; + end else begin + dataw_sink_ready <= 1'd1; + end + end + end + end + 3'd4: begin + dataw_pads_out_payload_clk <= 1'd1; + dataw_pads_out_payload_data_oe <= 1'd1; + dataw_pads_out_payload_data_o <= 4'd15; + if (dataw_pads_out_ready) begin + dataw_crc_reset <= 1'd1; + sdphydataw_next_state <= 3'd5; + end + end + 3'd5: begin + dataw_pads_out_payload_clk <= 1'd1; + if (dataw_crc_source_valid) begin + dataw_accepted1_sdphydataw_next_value0 <= (dataw_crc_source_payload_data[7:5] == 2'd2); + dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd1; + dataw_crc_error1_sdphydataw_next_value1 <= (dataw_crc_source_payload_data[7:5] == 3'd5); + dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd1; + dataw_write_error1_sdphydataw_next_value2 <= (dataw_crc_source_payload_data[7:5] == 3'd6); + dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd1; + sdphydataw_next_state <= 3'd6; + end + end + 3'd6: begin + dataw_pads_out_payload_clk <= 1'd1; + if ((dataw_pads_in_pads_in_valid & dataw_pads_in_pads_in_payload_data_i[0])) begin + dataw_sink_ready <= 1'd1; + sdphydataw_next_state <= 1'd0; + end + end + default: begin + dataw_accepted1_sdphydataw_next_value0 <= 1'd0; + dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd1; + dataw_crc_error1_sdphydataw_next_value1 <= 1'd0; + dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd1; + dataw_write_error1_sdphydataw_next_value2 <= 1'd0; + dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd1; + dataw_count_sdphydataw_next_value3 <= 1'd0; + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + if ((dataw_sink_valid & dataw_pads_out_ready)) begin + sdphydataw_next_state <= 1'd1; + end + end + endcase +end +assign datar_datar_pads_in_valid = datar_pads_in_pads_in_valid; +assign datar_pads_in_pads_in_ready = datar_datar_pads_in_ready; +assign datar_datar_pads_in_first = datar_pads_in_pads_in_first; +assign datar_datar_pads_in_last = datar_pads_in_pads_in_last; +assign datar_datar_pads_in_payload_clk = datar_pads_in_pads_in_payload_clk; +assign datar_datar_pads_in_payload_cmd_i = datar_pads_in_pads_in_payload_cmd_i; +assign datar_datar_pads_in_payload_cmd_o = datar_pads_in_pads_in_payload_cmd_o; +assign datar_datar_pads_in_payload_cmd_oe = datar_pads_in_pads_in_payload_cmd_oe; +assign datar_datar_pads_in_payload_data_i = datar_pads_in_pads_in_payload_data_i; +assign datar_datar_pads_in_payload_data_o = datar_pads_in_pads_in_payload_data_o; +assign datar_datar_pads_in_payload_data_oe = datar_pads_in_pads_in_payload_data_oe; +assign datar_datar_pads_in_payload_data_i_ce = datar_pads_in_pads_in_payload_data_i_ce; +assign datar_datar_start = (datar_datar_pads_in_payload_data_i[3:0] == 1'd0); +assign datar_datar_converter_converter_sink_valid = (datar_datar_pads_in_valid & datar_datar_run); +assign datar_datar_converter_converter_sink_payload_data = datar_datar_pads_in_payload_data_i[3:0]; +assign datar_datar_buf_sink_sink_valid = datar_datar_converter_source_source_valid; +assign datar_datar_converter_source_source_ready = datar_datar_buf_sink_sink_ready; +assign datar_datar_buf_sink_sink_first = datar_datar_converter_source_source_first; +assign datar_datar_buf_sink_sink_last = datar_datar_converter_source_source_last; +assign datar_datar_buf_sink_sink_payload_data = datar_datar_converter_source_source_payload_data; +assign datar_datar_source_valid = datar_datar_buf_source_source_valid; +assign datar_datar_buf_source_source_ready = datar_datar_source_ready; +assign datar_datar_source_first = datar_datar_buf_source_source_first; +assign datar_datar_source_last = datar_datar_buf_source_source_last; +assign datar_datar_source_payload_data = datar_datar_buf_source_source_payload_data; +assign datar_datar_converter_source_source_valid = datar_datar_converter_converter_source_valid; +assign datar_datar_converter_converter_source_ready = datar_datar_converter_source_source_ready; +assign datar_datar_converter_source_source_first = datar_datar_converter_converter_source_first; +assign datar_datar_converter_source_source_last = datar_datar_converter_converter_source_last; +assign datar_datar_converter_source_source_payload_data = datar_datar_converter_converter_source_payload_data; +assign datar_datar_converter_converter_sink_ready = ((~datar_datar_converter_converter_strobe_all) | datar_datar_converter_converter_source_ready); +assign datar_datar_converter_converter_source_valid = datar_datar_converter_converter_strobe_all; +assign datar_datar_converter_converter_load_part = (datar_datar_converter_converter_sink_valid & datar_datar_converter_converter_sink_ready); +assign datar_datar_buf_pipe_valid_sink_ready = ((~datar_datar_buf_pipe_valid_source_valid) | datar_datar_buf_pipe_valid_source_ready); +assign datar_datar_buf_pipe_valid_sink_valid = datar_datar_buf_sink_sink_valid; +assign datar_datar_buf_sink_sink_ready = datar_datar_buf_pipe_valid_sink_ready; +assign datar_datar_buf_pipe_valid_sink_first = datar_datar_buf_sink_sink_first; +assign datar_datar_buf_pipe_valid_sink_last = datar_datar_buf_sink_sink_last; +assign datar_datar_buf_pipe_valid_sink_payload_data = datar_datar_buf_sink_sink_payload_data; +assign datar_datar_buf_source_source_valid = datar_datar_buf_pipe_valid_source_valid; +assign datar_datar_buf_pipe_valid_source_ready = datar_datar_buf_source_source_ready; +assign datar_datar_buf_source_source_first = datar_datar_buf_pipe_valid_source_first; +assign datar_datar_buf_source_source_last = datar_datar_buf_pipe_valid_source_last; +assign datar_datar_buf_source_source_payload_data = datar_datar_buf_pipe_valid_source_payload_data; +always @(*) begin + datar_count_sdphydatar_next_value0 <= 10'd0; + datar_count_sdphydatar_next_value_ce0 <= 1'd0; + datar_datar_reset_sdphydatar_next_value2 <= 1'd0; + datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd0; + datar_datar_source_ready <= 1'd0; + datar_pads_out_payload_clk <= 1'd0; + datar_sink_ready <= 1'd0; + datar_source_source_first <= 1'd0; + datar_source_source_last <= 1'd0; + datar_source_source_payload_data <= 8'd0; + datar_source_source_payload_status <= 3'd0; + datar_source_source_valid <= 1'd0; + datar_stop <= 1'd0; + datar_timeout_sdphydatar_next_value1 <= 32'd0; + datar_timeout_sdphydatar_next_value_ce1 <= 1'd0; + sdphydatar_next_state <= 3'd0; + sdphydatar_next_state <= sdphydatar_state; + case (sdphydatar_state) + 1'd1: begin + datar_pads_out_payload_clk <= 1'd1; + datar_datar_reset_sdphydatar_next_value2 <= 1'd0; + datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd1; + datar_timeout_sdphydatar_next_value1 <= (datar_timeout - 1'd1); + datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; + if (datar_datar_source_valid) begin + sdphydatar_next_state <= 2'd2; + end + datar_timeout_sdphydatar_next_value1 <= (datar_timeout - 1'd1); + datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; + if ((datar_timeout == 1'd0)) begin + datar_sink_ready <= 1'd1; + sdphydatar_next_state <= 3'd4; + end + end + 2'd2: begin + datar_pads_out_payload_clk <= 1'd1; + datar_source_source_valid <= datar_datar_source_valid; + datar_source_source_payload_status <= 1'd0; + datar_source_source_first <= (datar_count == 1'd0); + datar_source_source_last <= (datar_count == ((datar_sink_payload_block_length + 4'd8) - 1'd1)); + datar_source_source_payload_data <= datar_datar_source_payload_data; + if (datar_source_source_valid) begin + if (datar_source_source_ready) begin + datar_datar_source_ready <= 1'd1; + datar_count_sdphydatar_next_value0 <= (datar_count + 1'd1); + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + if (datar_source_source_last) begin + datar_sink_ready <= 1'd1; + if (datar_sink_last) begin + datar_count_sdphydatar_next_value0 <= 1'd0; + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + sdphydatar_next_state <= 2'd3; + end else begin + sdphydatar_next_state <= 1'd0; + end + end + end else begin + datar_stop <= 1'd1; + end + end + datar_timeout_sdphydatar_next_value1 <= (datar_timeout - 1'd1); + datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; + if ((datar_timeout == 1'd0)) begin + datar_sink_ready <= 1'd1; + sdphydatar_next_state <= 3'd4; + end + end + 2'd3: begin + datar_pads_out_payload_clk <= 1'd1; + if (datar_pads_out_ready) begin + datar_count_sdphydatar_next_value0 <= (datar_count + 1'd1); + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + if ((datar_count == 6'd39)) begin + sdphydatar_next_state <= 1'd0; + end + end + end + 3'd4: begin + datar_source_source_valid <= 1'd1; + datar_source_source_payload_status <= 1'd1; + datar_source_source_last <= 1'd1; + if (datar_source_source_ready) begin + sdphydatar_next_state <= 1'd0; + end + end + default: begin + datar_count_sdphydatar_next_value0 <= 1'd0; + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + if ((datar_sink_valid & datar_pads_out_ready)) begin + datar_pads_out_payload_clk <= 1'd1; + datar_timeout_sdphydatar_next_value1 <= 32'd50000000; + datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; + datar_count_sdphydatar_next_value0 <= 1'd0; + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + datar_datar_reset_sdphydatar_next_value2 <= 1'd1; + datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd1; + sdphydatar_next_state <= 1'd1; + end + end + endcase +end +assign sdcard_core_crc16_inserter_sink_valid = sdcard_core_sink_sink_valid0; +assign sdcard_core_sink_sink_ready0 = sdcard_core_crc16_inserter_sink_ready; +assign sdcard_core_crc16_inserter_sink_first = sdcard_core_sink_sink_first0; +assign sdcard_core_crc16_inserter_sink_last = sdcard_core_sink_sink_last0; +assign sdcard_core_crc16_inserter_sink_payload_data = sdcard_core_sink_sink_payload_data0; +assign sdcard_core_source_source_valid0 = sdcard_core_source_source_valid1; +assign sdcard_core_source_source_ready1 = sdcard_core_source_source_ready0; +assign sdcard_core_source_source_first0 = sdcard_core_source_source_first1; +assign sdcard_core_source_source_last0 = sdcard_core_source_source_last1; +assign sdcard_core_source_source_payload_data0 = sdcard_core_source_source_payload_data1; +assign sdcard_core_cmd_type = sdcard_core_csrfield_cmd_type; +assign sdcard_core_data_type = sdcard_core_csrfield_data_type; +assign sdcard_core_cmd = sdcard_core_csrfield_cmd; +assign sdcard_core_csrfield_done0 = sdcard_core_cmd_done; +assign sdcard_core_csrfield_error0 = sdcard_core_cmd_error; +assign sdcard_core_csrfield_timeout0 = sdcard_core_cmd_timeout; +assign sdcard_core_csrfield_crc0 = 1'd0; +assign sdcard_core_csrfield_done1 = sdcard_core_data_done; +assign sdcard_core_csrfield_error1 = sdcard_core_data_error; +assign sdcard_core_csrfield_timeout1 = sdcard_core_data_timeout; +assign sdcard_core_csrfield_crc1 = 1'd0; +assign sdcard_core_crc7_inserter_crc_din = {1'd0, 1'd1, sdcard_core_cmd, sdcard_core_cmd_argument_storage}; +assign sdcard_core_crc7_inserter_crc_reset = 1'd1; +assign sdcard_core_crc7_inserter_crc_enable = 1'd1; +assign sdcard_core_crc7_inserter_crc1 = {sdcard_core_crc7_inserter_crc0[5], sdcard_core_crc7_inserter_crc0[4], sdcard_core_crc7_inserter_crc0[3], (sdcard_core_crc7_inserter_crc0[2] ^ (sdcard_core_crc7_inserter_crc_din[39] ^ sdcard_core_crc7_inserter_crc0[6])), sdcard_core_crc7_inserter_crc0[1], sdcard_core_crc7_inserter_crc0[0], (sdcard_core_crc7_inserter_crc_din[39] ^ sdcard_core_crc7_inserter_crc0[6])}; +assign sdcard_core_crc7_inserter_crc2 = {sdcard_core_crc7_inserter_crc1[5], sdcard_core_crc7_inserter_crc1[4], sdcard_core_crc7_inserter_crc1[3], (sdcard_core_crc7_inserter_crc1[2] ^ (sdcard_core_crc7_inserter_crc_din[38] ^ sdcard_core_crc7_inserter_crc1[6])), sdcard_core_crc7_inserter_crc1[1], sdcard_core_crc7_inserter_crc1[0], (sdcard_core_crc7_inserter_crc_din[38] ^ sdcard_core_crc7_inserter_crc1[6])}; +assign sdcard_core_crc7_inserter_crc3 = {sdcard_core_crc7_inserter_crc2[5], sdcard_core_crc7_inserter_crc2[4], sdcard_core_crc7_inserter_crc2[3], (sdcard_core_crc7_inserter_crc2[2] ^ (sdcard_core_crc7_inserter_crc_din[37] ^ sdcard_core_crc7_inserter_crc2[6])), sdcard_core_crc7_inserter_crc2[1], sdcard_core_crc7_inserter_crc2[0], (sdcard_core_crc7_inserter_crc_din[37] ^ sdcard_core_crc7_inserter_crc2[6])}; +assign sdcard_core_crc7_inserter_crc4 = {sdcard_core_crc7_inserter_crc3[5], sdcard_core_crc7_inserter_crc3[4], sdcard_core_crc7_inserter_crc3[3], (sdcard_core_crc7_inserter_crc3[2] ^ (sdcard_core_crc7_inserter_crc_din[36] ^ sdcard_core_crc7_inserter_crc3[6])), sdcard_core_crc7_inserter_crc3[1], sdcard_core_crc7_inserter_crc3[0], (sdcard_core_crc7_inserter_crc_din[36] ^ sdcard_core_crc7_inserter_crc3[6])}; +assign sdcard_core_crc7_inserter_crc5 = {sdcard_core_crc7_inserter_crc4[5], sdcard_core_crc7_inserter_crc4[4], sdcard_core_crc7_inserter_crc4[3], (sdcard_core_crc7_inserter_crc4[2] ^ (sdcard_core_crc7_inserter_crc_din[35] ^ sdcard_core_crc7_inserter_crc4[6])), sdcard_core_crc7_inserter_crc4[1], sdcard_core_crc7_inserter_crc4[0], (sdcard_core_crc7_inserter_crc_din[35] ^ sdcard_core_crc7_inserter_crc4[6])}; +assign sdcard_core_crc7_inserter_crc6 = {sdcard_core_crc7_inserter_crc5[5], sdcard_core_crc7_inserter_crc5[4], sdcard_core_crc7_inserter_crc5[3], (sdcard_core_crc7_inserter_crc5[2] ^ (sdcard_core_crc7_inserter_crc_din[34] ^ sdcard_core_crc7_inserter_crc5[6])), sdcard_core_crc7_inserter_crc5[1], sdcard_core_crc7_inserter_crc5[0], (sdcard_core_crc7_inserter_crc_din[34] ^ sdcard_core_crc7_inserter_crc5[6])}; +assign sdcard_core_crc7_inserter_crc7 = {sdcard_core_crc7_inserter_crc6[5], sdcard_core_crc7_inserter_crc6[4], sdcard_core_crc7_inserter_crc6[3], (sdcard_core_crc7_inserter_crc6[2] ^ (sdcard_core_crc7_inserter_crc_din[33] ^ sdcard_core_crc7_inserter_crc6[6])), sdcard_core_crc7_inserter_crc6[1], sdcard_core_crc7_inserter_crc6[0], (sdcard_core_crc7_inserter_crc_din[33] ^ sdcard_core_crc7_inserter_crc6[6])}; +assign sdcard_core_crc7_inserter_crc8 = {sdcard_core_crc7_inserter_crc7[5], sdcard_core_crc7_inserter_crc7[4], sdcard_core_crc7_inserter_crc7[3], (sdcard_core_crc7_inserter_crc7[2] ^ (sdcard_core_crc7_inserter_crc_din[32] ^ sdcard_core_crc7_inserter_crc7[6])), sdcard_core_crc7_inserter_crc7[1], sdcard_core_crc7_inserter_crc7[0], (sdcard_core_crc7_inserter_crc_din[32] ^ sdcard_core_crc7_inserter_crc7[6])}; +assign sdcard_core_crc7_inserter_crc9 = {sdcard_core_crc7_inserter_crc8[5], sdcard_core_crc7_inserter_crc8[4], sdcard_core_crc7_inserter_crc8[3], (sdcard_core_crc7_inserter_crc8[2] ^ (sdcard_core_crc7_inserter_crc_din[31] ^ sdcard_core_crc7_inserter_crc8[6])), sdcard_core_crc7_inserter_crc8[1], sdcard_core_crc7_inserter_crc8[0], (sdcard_core_crc7_inserter_crc_din[31] ^ sdcard_core_crc7_inserter_crc8[6])}; +assign sdcard_core_crc7_inserter_crc10 = {sdcard_core_crc7_inserter_crc9[5], sdcard_core_crc7_inserter_crc9[4], sdcard_core_crc7_inserter_crc9[3], (sdcard_core_crc7_inserter_crc9[2] ^ (sdcard_core_crc7_inserter_crc_din[30] ^ sdcard_core_crc7_inserter_crc9[6])), sdcard_core_crc7_inserter_crc9[1], sdcard_core_crc7_inserter_crc9[0], (sdcard_core_crc7_inserter_crc_din[30] ^ sdcard_core_crc7_inserter_crc9[6])}; +assign sdcard_core_crc7_inserter_crc11 = {sdcard_core_crc7_inserter_crc10[5], sdcard_core_crc7_inserter_crc10[4], sdcard_core_crc7_inserter_crc10[3], (sdcard_core_crc7_inserter_crc10[2] ^ (sdcard_core_crc7_inserter_crc_din[29] ^ sdcard_core_crc7_inserter_crc10[6])), sdcard_core_crc7_inserter_crc10[1], sdcard_core_crc7_inserter_crc10[0], (sdcard_core_crc7_inserter_crc_din[29] ^ sdcard_core_crc7_inserter_crc10[6])}; +assign sdcard_core_crc7_inserter_crc12 = {sdcard_core_crc7_inserter_crc11[5], sdcard_core_crc7_inserter_crc11[4], sdcard_core_crc7_inserter_crc11[3], (sdcard_core_crc7_inserter_crc11[2] ^ (sdcard_core_crc7_inserter_crc_din[28] ^ sdcard_core_crc7_inserter_crc11[6])), sdcard_core_crc7_inserter_crc11[1], sdcard_core_crc7_inserter_crc11[0], (sdcard_core_crc7_inserter_crc_din[28] ^ sdcard_core_crc7_inserter_crc11[6])}; +assign sdcard_core_crc7_inserter_crc13 = {sdcard_core_crc7_inserter_crc12[5], sdcard_core_crc7_inserter_crc12[4], sdcard_core_crc7_inserter_crc12[3], (sdcard_core_crc7_inserter_crc12[2] ^ (sdcard_core_crc7_inserter_crc_din[27] ^ sdcard_core_crc7_inserter_crc12[6])), sdcard_core_crc7_inserter_crc12[1], sdcard_core_crc7_inserter_crc12[0], (sdcard_core_crc7_inserter_crc_din[27] ^ sdcard_core_crc7_inserter_crc12[6])}; +assign sdcard_core_crc7_inserter_crc14 = {sdcard_core_crc7_inserter_crc13[5], sdcard_core_crc7_inserter_crc13[4], sdcard_core_crc7_inserter_crc13[3], (sdcard_core_crc7_inserter_crc13[2] ^ (sdcard_core_crc7_inserter_crc_din[26] ^ sdcard_core_crc7_inserter_crc13[6])), sdcard_core_crc7_inserter_crc13[1], sdcard_core_crc7_inserter_crc13[0], (sdcard_core_crc7_inserter_crc_din[26] ^ sdcard_core_crc7_inserter_crc13[6])}; +assign sdcard_core_crc7_inserter_crc15 = {sdcard_core_crc7_inserter_crc14[5], sdcard_core_crc7_inserter_crc14[4], sdcard_core_crc7_inserter_crc14[3], (sdcard_core_crc7_inserter_crc14[2] ^ (sdcard_core_crc7_inserter_crc_din[25] ^ sdcard_core_crc7_inserter_crc14[6])), sdcard_core_crc7_inserter_crc14[1], sdcard_core_crc7_inserter_crc14[0], (sdcard_core_crc7_inserter_crc_din[25] ^ sdcard_core_crc7_inserter_crc14[6])}; +assign sdcard_core_crc7_inserter_crc16 = {sdcard_core_crc7_inserter_crc15[5], sdcard_core_crc7_inserter_crc15[4], sdcard_core_crc7_inserter_crc15[3], (sdcard_core_crc7_inserter_crc15[2] ^ (sdcard_core_crc7_inserter_crc_din[24] ^ sdcard_core_crc7_inserter_crc15[6])), sdcard_core_crc7_inserter_crc15[1], sdcard_core_crc7_inserter_crc15[0], (sdcard_core_crc7_inserter_crc_din[24] ^ sdcard_core_crc7_inserter_crc15[6])}; +assign sdcard_core_crc7_inserter_crc17 = {sdcard_core_crc7_inserter_crc16[5], sdcard_core_crc7_inserter_crc16[4], sdcard_core_crc7_inserter_crc16[3], (sdcard_core_crc7_inserter_crc16[2] ^ (sdcard_core_crc7_inserter_crc_din[23] ^ sdcard_core_crc7_inserter_crc16[6])), sdcard_core_crc7_inserter_crc16[1], sdcard_core_crc7_inserter_crc16[0], (sdcard_core_crc7_inserter_crc_din[23] ^ sdcard_core_crc7_inserter_crc16[6])}; +assign sdcard_core_crc7_inserter_crc18 = {sdcard_core_crc7_inserter_crc17[5], sdcard_core_crc7_inserter_crc17[4], sdcard_core_crc7_inserter_crc17[3], (sdcard_core_crc7_inserter_crc17[2] ^ (sdcard_core_crc7_inserter_crc_din[22] ^ sdcard_core_crc7_inserter_crc17[6])), sdcard_core_crc7_inserter_crc17[1], sdcard_core_crc7_inserter_crc17[0], (sdcard_core_crc7_inserter_crc_din[22] ^ sdcard_core_crc7_inserter_crc17[6])}; +assign sdcard_core_crc7_inserter_crc19 = {sdcard_core_crc7_inserter_crc18[5], sdcard_core_crc7_inserter_crc18[4], sdcard_core_crc7_inserter_crc18[3], (sdcard_core_crc7_inserter_crc18[2] ^ (sdcard_core_crc7_inserter_crc_din[21] ^ sdcard_core_crc7_inserter_crc18[6])), sdcard_core_crc7_inserter_crc18[1], sdcard_core_crc7_inserter_crc18[0], (sdcard_core_crc7_inserter_crc_din[21] ^ sdcard_core_crc7_inserter_crc18[6])}; +assign sdcard_core_crc7_inserter_crc20 = {sdcard_core_crc7_inserter_crc19[5], sdcard_core_crc7_inserter_crc19[4], sdcard_core_crc7_inserter_crc19[3], (sdcard_core_crc7_inserter_crc19[2] ^ (sdcard_core_crc7_inserter_crc_din[20] ^ sdcard_core_crc7_inserter_crc19[6])), sdcard_core_crc7_inserter_crc19[1], sdcard_core_crc7_inserter_crc19[0], (sdcard_core_crc7_inserter_crc_din[20] ^ sdcard_core_crc7_inserter_crc19[6])}; +assign sdcard_core_crc7_inserter_crc21 = {sdcard_core_crc7_inserter_crc20[5], sdcard_core_crc7_inserter_crc20[4], sdcard_core_crc7_inserter_crc20[3], (sdcard_core_crc7_inserter_crc20[2] ^ (sdcard_core_crc7_inserter_crc_din[19] ^ sdcard_core_crc7_inserter_crc20[6])), sdcard_core_crc7_inserter_crc20[1], sdcard_core_crc7_inserter_crc20[0], (sdcard_core_crc7_inserter_crc_din[19] ^ sdcard_core_crc7_inserter_crc20[6])}; +assign sdcard_core_crc7_inserter_crc22 = {sdcard_core_crc7_inserter_crc21[5], sdcard_core_crc7_inserter_crc21[4], sdcard_core_crc7_inserter_crc21[3], (sdcard_core_crc7_inserter_crc21[2] ^ (sdcard_core_crc7_inserter_crc_din[18] ^ sdcard_core_crc7_inserter_crc21[6])), sdcard_core_crc7_inserter_crc21[1], sdcard_core_crc7_inserter_crc21[0], (sdcard_core_crc7_inserter_crc_din[18] ^ sdcard_core_crc7_inserter_crc21[6])}; +assign sdcard_core_crc7_inserter_crc23 = {sdcard_core_crc7_inserter_crc22[5], sdcard_core_crc7_inserter_crc22[4], sdcard_core_crc7_inserter_crc22[3], (sdcard_core_crc7_inserter_crc22[2] ^ (sdcard_core_crc7_inserter_crc_din[17] ^ sdcard_core_crc7_inserter_crc22[6])), sdcard_core_crc7_inserter_crc22[1], sdcard_core_crc7_inserter_crc22[0], (sdcard_core_crc7_inserter_crc_din[17] ^ sdcard_core_crc7_inserter_crc22[6])}; +assign sdcard_core_crc7_inserter_crc24 = {sdcard_core_crc7_inserter_crc23[5], sdcard_core_crc7_inserter_crc23[4], sdcard_core_crc7_inserter_crc23[3], (sdcard_core_crc7_inserter_crc23[2] ^ (sdcard_core_crc7_inserter_crc_din[16] ^ sdcard_core_crc7_inserter_crc23[6])), sdcard_core_crc7_inserter_crc23[1], sdcard_core_crc7_inserter_crc23[0], (sdcard_core_crc7_inserter_crc_din[16] ^ sdcard_core_crc7_inserter_crc23[6])}; +assign sdcard_core_crc7_inserter_crc25 = {sdcard_core_crc7_inserter_crc24[5], sdcard_core_crc7_inserter_crc24[4], sdcard_core_crc7_inserter_crc24[3], (sdcard_core_crc7_inserter_crc24[2] ^ (sdcard_core_crc7_inserter_crc_din[15] ^ sdcard_core_crc7_inserter_crc24[6])), sdcard_core_crc7_inserter_crc24[1], sdcard_core_crc7_inserter_crc24[0], (sdcard_core_crc7_inserter_crc_din[15] ^ sdcard_core_crc7_inserter_crc24[6])}; +assign sdcard_core_crc7_inserter_crc26 = {sdcard_core_crc7_inserter_crc25[5], sdcard_core_crc7_inserter_crc25[4], sdcard_core_crc7_inserter_crc25[3], (sdcard_core_crc7_inserter_crc25[2] ^ (sdcard_core_crc7_inserter_crc_din[14] ^ sdcard_core_crc7_inserter_crc25[6])), sdcard_core_crc7_inserter_crc25[1], sdcard_core_crc7_inserter_crc25[0], (sdcard_core_crc7_inserter_crc_din[14] ^ sdcard_core_crc7_inserter_crc25[6])}; +assign sdcard_core_crc7_inserter_crc27 = {sdcard_core_crc7_inserter_crc26[5], sdcard_core_crc7_inserter_crc26[4], sdcard_core_crc7_inserter_crc26[3], (sdcard_core_crc7_inserter_crc26[2] ^ (sdcard_core_crc7_inserter_crc_din[13] ^ sdcard_core_crc7_inserter_crc26[6])), sdcard_core_crc7_inserter_crc26[1], sdcard_core_crc7_inserter_crc26[0], (sdcard_core_crc7_inserter_crc_din[13] ^ sdcard_core_crc7_inserter_crc26[6])}; +assign sdcard_core_crc7_inserter_crc28 = {sdcard_core_crc7_inserter_crc27[5], sdcard_core_crc7_inserter_crc27[4], sdcard_core_crc7_inserter_crc27[3], (sdcard_core_crc7_inserter_crc27[2] ^ (sdcard_core_crc7_inserter_crc_din[12] ^ sdcard_core_crc7_inserter_crc27[6])), sdcard_core_crc7_inserter_crc27[1], sdcard_core_crc7_inserter_crc27[0], (sdcard_core_crc7_inserter_crc_din[12] ^ sdcard_core_crc7_inserter_crc27[6])}; +assign sdcard_core_crc7_inserter_crc29 = {sdcard_core_crc7_inserter_crc28[5], sdcard_core_crc7_inserter_crc28[4], sdcard_core_crc7_inserter_crc28[3], (sdcard_core_crc7_inserter_crc28[2] ^ (sdcard_core_crc7_inserter_crc_din[11] ^ sdcard_core_crc7_inserter_crc28[6])), sdcard_core_crc7_inserter_crc28[1], sdcard_core_crc7_inserter_crc28[0], (sdcard_core_crc7_inserter_crc_din[11] ^ sdcard_core_crc7_inserter_crc28[6])}; +assign sdcard_core_crc7_inserter_crc30 = {sdcard_core_crc7_inserter_crc29[5], sdcard_core_crc7_inserter_crc29[4], sdcard_core_crc7_inserter_crc29[3], (sdcard_core_crc7_inserter_crc29[2] ^ (sdcard_core_crc7_inserter_crc_din[10] ^ sdcard_core_crc7_inserter_crc29[6])), sdcard_core_crc7_inserter_crc29[1], sdcard_core_crc7_inserter_crc29[0], (sdcard_core_crc7_inserter_crc_din[10] ^ sdcard_core_crc7_inserter_crc29[6])}; +assign sdcard_core_crc7_inserter_crc31 = {sdcard_core_crc7_inserter_crc30[5], sdcard_core_crc7_inserter_crc30[4], sdcard_core_crc7_inserter_crc30[3], (sdcard_core_crc7_inserter_crc30[2] ^ (sdcard_core_crc7_inserter_crc_din[9] ^ sdcard_core_crc7_inserter_crc30[6])), sdcard_core_crc7_inserter_crc30[1], sdcard_core_crc7_inserter_crc30[0], (sdcard_core_crc7_inserter_crc_din[9] ^ sdcard_core_crc7_inserter_crc30[6])}; +assign sdcard_core_crc7_inserter_crc32 = {sdcard_core_crc7_inserter_crc31[5], sdcard_core_crc7_inserter_crc31[4], sdcard_core_crc7_inserter_crc31[3], (sdcard_core_crc7_inserter_crc31[2] ^ (sdcard_core_crc7_inserter_crc_din[8] ^ sdcard_core_crc7_inserter_crc31[6])), sdcard_core_crc7_inserter_crc31[1], sdcard_core_crc7_inserter_crc31[0], (sdcard_core_crc7_inserter_crc_din[8] ^ sdcard_core_crc7_inserter_crc31[6])}; +assign sdcard_core_crc7_inserter_crc33 = {sdcard_core_crc7_inserter_crc32[5], sdcard_core_crc7_inserter_crc32[4], sdcard_core_crc7_inserter_crc32[3], (sdcard_core_crc7_inserter_crc32[2] ^ (sdcard_core_crc7_inserter_crc_din[7] ^ sdcard_core_crc7_inserter_crc32[6])), sdcard_core_crc7_inserter_crc32[1], sdcard_core_crc7_inserter_crc32[0], (sdcard_core_crc7_inserter_crc_din[7] ^ sdcard_core_crc7_inserter_crc32[6])}; +assign sdcard_core_crc7_inserter_crc34 = {sdcard_core_crc7_inserter_crc33[5], sdcard_core_crc7_inserter_crc33[4], sdcard_core_crc7_inserter_crc33[3], (sdcard_core_crc7_inserter_crc33[2] ^ (sdcard_core_crc7_inserter_crc_din[6] ^ sdcard_core_crc7_inserter_crc33[6])), sdcard_core_crc7_inserter_crc33[1], sdcard_core_crc7_inserter_crc33[0], (sdcard_core_crc7_inserter_crc_din[6] ^ sdcard_core_crc7_inserter_crc33[6])}; +assign sdcard_core_crc7_inserter_crc35 = {sdcard_core_crc7_inserter_crc34[5], sdcard_core_crc7_inserter_crc34[4], sdcard_core_crc7_inserter_crc34[3], (sdcard_core_crc7_inserter_crc34[2] ^ (sdcard_core_crc7_inserter_crc_din[5] ^ sdcard_core_crc7_inserter_crc34[6])), sdcard_core_crc7_inserter_crc34[1], sdcard_core_crc7_inserter_crc34[0], (sdcard_core_crc7_inserter_crc_din[5] ^ sdcard_core_crc7_inserter_crc34[6])}; +assign sdcard_core_crc7_inserter_crc36 = {sdcard_core_crc7_inserter_crc35[5], sdcard_core_crc7_inserter_crc35[4], sdcard_core_crc7_inserter_crc35[3], (sdcard_core_crc7_inserter_crc35[2] ^ (sdcard_core_crc7_inserter_crc_din[4] ^ sdcard_core_crc7_inserter_crc35[6])), sdcard_core_crc7_inserter_crc35[1], sdcard_core_crc7_inserter_crc35[0], (sdcard_core_crc7_inserter_crc_din[4] ^ sdcard_core_crc7_inserter_crc35[6])}; +assign sdcard_core_crc7_inserter_crc37 = {sdcard_core_crc7_inserter_crc36[5], sdcard_core_crc7_inserter_crc36[4], sdcard_core_crc7_inserter_crc36[3], (sdcard_core_crc7_inserter_crc36[2] ^ (sdcard_core_crc7_inserter_crc_din[3] ^ sdcard_core_crc7_inserter_crc36[6])), sdcard_core_crc7_inserter_crc36[1], sdcard_core_crc7_inserter_crc36[0], (sdcard_core_crc7_inserter_crc_din[3] ^ sdcard_core_crc7_inserter_crc36[6])}; +assign sdcard_core_crc7_inserter_crc38 = {sdcard_core_crc7_inserter_crc37[5], sdcard_core_crc7_inserter_crc37[4], sdcard_core_crc7_inserter_crc37[3], (sdcard_core_crc7_inserter_crc37[2] ^ (sdcard_core_crc7_inserter_crc_din[2] ^ sdcard_core_crc7_inserter_crc37[6])), sdcard_core_crc7_inserter_crc37[1], sdcard_core_crc7_inserter_crc37[0], (sdcard_core_crc7_inserter_crc_din[2] ^ sdcard_core_crc7_inserter_crc37[6])}; +assign sdcard_core_crc7_inserter_crc39 = {sdcard_core_crc7_inserter_crc38[5], sdcard_core_crc7_inserter_crc38[4], sdcard_core_crc7_inserter_crc38[3], (sdcard_core_crc7_inserter_crc38[2] ^ (sdcard_core_crc7_inserter_crc_din[1] ^ sdcard_core_crc7_inserter_crc38[6])), sdcard_core_crc7_inserter_crc38[1], sdcard_core_crc7_inserter_crc38[0], (sdcard_core_crc7_inserter_crc_din[1] ^ sdcard_core_crc7_inserter_crc38[6])}; +assign sdcard_core_crc7_inserter_crc40 = {sdcard_core_crc7_inserter_crc39[5], sdcard_core_crc7_inserter_crc39[4], sdcard_core_crc7_inserter_crc39[3], (sdcard_core_crc7_inserter_crc39[2] ^ (sdcard_core_crc7_inserter_crc_din[0] ^ sdcard_core_crc7_inserter_crc39[6])), sdcard_core_crc7_inserter_crc39[1], sdcard_core_crc7_inserter_crc39[0], (sdcard_core_crc7_inserter_crc_din[0] ^ sdcard_core_crc7_inserter_crc39[6])}; +always @(*) begin + sdcard_core_crc7_inserter_crc_crc <= 7'd0; + if (sdcard_core_crc7_inserter_crc_enable) begin + sdcard_core_crc7_inserter_crc_crc <= sdcard_core_crc7_inserter_crc40; + end else begin + sdcard_core_crc7_inserter_crc_crc <= sdcard_core_crc7_inserter_crc0; + end +end +assign sdcard_core_crc16_inserter_crc0_reset = ((sdcard_core_crc16_inserter_source_valid & sdcard_core_crc16_inserter_source_ready) & sdcard_core_crc16_inserter_source_last); +assign sdcard_core_crc16_inserter_crc0_enable = (sdcard_core_crc16_inserter_sink_valid & sdcard_core_crc16_inserter_sink_ready); +always @(*) begin + sdcard_core_crc16_inserter_crc0_din <= 2'd0; + sdcard_core_crc16_inserter_crc0_din[0] <= sdcard_core_crc16_inserter_sink_payload_data[0]; + sdcard_core_crc16_inserter_crc0_din[1] <= sdcard_core_crc16_inserter_sink_payload_data[4]; +end +assign sdcard_core_crc16_inserter_crc1_reset = ((sdcard_core_crc16_inserter_source_valid & sdcard_core_crc16_inserter_source_ready) & sdcard_core_crc16_inserter_source_last); +assign sdcard_core_crc16_inserter_crc1_enable = (sdcard_core_crc16_inserter_sink_valid & sdcard_core_crc16_inserter_sink_ready); +always @(*) begin + sdcard_core_crc16_inserter_crc1_din <= 2'd0; + sdcard_core_crc16_inserter_crc1_din[0] <= sdcard_core_crc16_inserter_sink_payload_data[1]; + sdcard_core_crc16_inserter_crc1_din[1] <= sdcard_core_crc16_inserter_sink_payload_data[5]; +end +assign sdcard_core_crc16_inserter_crc2_reset = ((sdcard_core_crc16_inserter_source_valid & sdcard_core_crc16_inserter_source_ready) & sdcard_core_crc16_inserter_source_last); +assign sdcard_core_crc16_inserter_crc2_enable = (sdcard_core_crc16_inserter_sink_valid & sdcard_core_crc16_inserter_sink_ready); +always @(*) begin + sdcard_core_crc16_inserter_crc2_din <= 2'd0; + sdcard_core_crc16_inserter_crc2_din[0] <= sdcard_core_crc16_inserter_sink_payload_data[2]; + sdcard_core_crc16_inserter_crc2_din[1] <= sdcard_core_crc16_inserter_sink_payload_data[6]; +end +assign sdcard_core_crc16_inserter_crc3_reset = ((sdcard_core_crc16_inserter_source_valid & sdcard_core_crc16_inserter_source_ready) & sdcard_core_crc16_inserter_source_last); +assign sdcard_core_crc16_inserter_crc3_enable = (sdcard_core_crc16_inserter_sink_valid & sdcard_core_crc16_inserter_sink_ready); +always @(*) begin + sdcard_core_crc16_inserter_crc3_din <= 2'd0; + sdcard_core_crc16_inserter_crc3_din[0] <= sdcard_core_crc16_inserter_sink_payload_data[3]; + sdcard_core_crc16_inserter_crc3_din[1] <= sdcard_core_crc16_inserter_sink_payload_data[7]; +end +assign sdcard_core_crc16_inserter_crc01 = {sdcard_core_crc16_inserter_crc00[14], sdcard_core_crc16_inserter_crc00[13], sdcard_core_crc16_inserter_crc00[12], (sdcard_core_crc16_inserter_crc00[11] ^ (sdcard_core_crc16_inserter_crc0_din[1] ^ sdcard_core_crc16_inserter_crc00[15])), sdcard_core_crc16_inserter_crc00[10], sdcard_core_crc16_inserter_crc00[9], sdcard_core_crc16_inserter_crc00[8], sdcard_core_crc16_inserter_crc00[7], sdcard_core_crc16_inserter_crc00[6], sdcard_core_crc16_inserter_crc00[5], (sdcard_core_crc16_inserter_crc00[4] ^ (sdcard_core_crc16_inserter_crc0_din[1] ^ sdcard_core_crc16_inserter_crc00[15])), sdcard_core_crc16_inserter_crc00[3], sdcard_core_crc16_inserter_crc00[2], sdcard_core_crc16_inserter_crc00[1], sdcard_core_crc16_inserter_crc00[0], (sdcard_core_crc16_inserter_crc0_din[1] ^ sdcard_core_crc16_inserter_crc00[15])}; +assign sdcard_core_crc16_inserter_crc02 = {sdcard_core_crc16_inserter_crc01[14], sdcard_core_crc16_inserter_crc01[13], sdcard_core_crc16_inserter_crc01[12], (sdcard_core_crc16_inserter_crc01[11] ^ (sdcard_core_crc16_inserter_crc0_din[0] ^ sdcard_core_crc16_inserter_crc01[15])), sdcard_core_crc16_inserter_crc01[10], sdcard_core_crc16_inserter_crc01[9], sdcard_core_crc16_inserter_crc01[8], sdcard_core_crc16_inserter_crc01[7], sdcard_core_crc16_inserter_crc01[6], sdcard_core_crc16_inserter_crc01[5], (sdcard_core_crc16_inserter_crc01[4] ^ (sdcard_core_crc16_inserter_crc0_din[0] ^ sdcard_core_crc16_inserter_crc01[15])), sdcard_core_crc16_inserter_crc01[3], sdcard_core_crc16_inserter_crc01[2], sdcard_core_crc16_inserter_crc01[1], sdcard_core_crc16_inserter_crc01[0], (sdcard_core_crc16_inserter_crc0_din[0] ^ sdcard_core_crc16_inserter_crc01[15])}; +always @(*) begin + sdcard_core_crc16_inserter_crc0_crc <= 16'd0; + if (sdcard_core_crc16_inserter_crc0_enable) begin + sdcard_core_crc16_inserter_crc0_crc <= sdcard_core_crc16_inserter_crc02; + end else begin + sdcard_core_crc16_inserter_crc0_crc <= sdcard_core_crc16_inserter_crc00; + end +end +assign sdcard_core_crc16_inserter_crc11 = {sdcard_core_crc16_inserter_crc10[14], sdcard_core_crc16_inserter_crc10[13], sdcard_core_crc16_inserter_crc10[12], (sdcard_core_crc16_inserter_crc10[11] ^ (sdcard_core_crc16_inserter_crc1_din[1] ^ sdcard_core_crc16_inserter_crc10[15])), sdcard_core_crc16_inserter_crc10[10], sdcard_core_crc16_inserter_crc10[9], sdcard_core_crc16_inserter_crc10[8], sdcard_core_crc16_inserter_crc10[7], sdcard_core_crc16_inserter_crc10[6], sdcard_core_crc16_inserter_crc10[5], (sdcard_core_crc16_inserter_crc10[4] ^ (sdcard_core_crc16_inserter_crc1_din[1] ^ sdcard_core_crc16_inserter_crc10[15])), sdcard_core_crc16_inserter_crc10[3], sdcard_core_crc16_inserter_crc10[2], sdcard_core_crc16_inserter_crc10[1], sdcard_core_crc16_inserter_crc10[0], (sdcard_core_crc16_inserter_crc1_din[1] ^ sdcard_core_crc16_inserter_crc10[15])}; +assign sdcard_core_crc16_inserter_crc12 = {sdcard_core_crc16_inserter_crc11[14], sdcard_core_crc16_inserter_crc11[13], sdcard_core_crc16_inserter_crc11[12], (sdcard_core_crc16_inserter_crc11[11] ^ (sdcard_core_crc16_inserter_crc1_din[0] ^ sdcard_core_crc16_inserter_crc11[15])), sdcard_core_crc16_inserter_crc11[10], sdcard_core_crc16_inserter_crc11[9], sdcard_core_crc16_inserter_crc11[8], sdcard_core_crc16_inserter_crc11[7], sdcard_core_crc16_inserter_crc11[6], sdcard_core_crc16_inserter_crc11[5], (sdcard_core_crc16_inserter_crc11[4] ^ (sdcard_core_crc16_inserter_crc1_din[0] ^ sdcard_core_crc16_inserter_crc11[15])), sdcard_core_crc16_inserter_crc11[3], sdcard_core_crc16_inserter_crc11[2], sdcard_core_crc16_inserter_crc11[1], sdcard_core_crc16_inserter_crc11[0], (sdcard_core_crc16_inserter_crc1_din[0] ^ sdcard_core_crc16_inserter_crc11[15])}; +always @(*) begin + sdcard_core_crc16_inserter_crc1_crc <= 16'd0; + if (sdcard_core_crc16_inserter_crc1_enable) begin + sdcard_core_crc16_inserter_crc1_crc <= sdcard_core_crc16_inserter_crc12; + end else begin + sdcard_core_crc16_inserter_crc1_crc <= sdcard_core_crc16_inserter_crc10; + end +end +assign sdcard_core_crc16_inserter_crc21 = {sdcard_core_crc16_inserter_crc20[14], sdcard_core_crc16_inserter_crc20[13], sdcard_core_crc16_inserter_crc20[12], (sdcard_core_crc16_inserter_crc20[11] ^ (sdcard_core_crc16_inserter_crc2_din[1] ^ sdcard_core_crc16_inserter_crc20[15])), sdcard_core_crc16_inserter_crc20[10], sdcard_core_crc16_inserter_crc20[9], sdcard_core_crc16_inserter_crc20[8], sdcard_core_crc16_inserter_crc20[7], sdcard_core_crc16_inserter_crc20[6], sdcard_core_crc16_inserter_crc20[5], (sdcard_core_crc16_inserter_crc20[4] ^ (sdcard_core_crc16_inserter_crc2_din[1] ^ sdcard_core_crc16_inserter_crc20[15])), sdcard_core_crc16_inserter_crc20[3], sdcard_core_crc16_inserter_crc20[2], sdcard_core_crc16_inserter_crc20[1], sdcard_core_crc16_inserter_crc20[0], (sdcard_core_crc16_inserter_crc2_din[1] ^ sdcard_core_crc16_inserter_crc20[15])}; +assign sdcard_core_crc16_inserter_crc22 = {sdcard_core_crc16_inserter_crc21[14], sdcard_core_crc16_inserter_crc21[13], sdcard_core_crc16_inserter_crc21[12], (sdcard_core_crc16_inserter_crc21[11] ^ (sdcard_core_crc16_inserter_crc2_din[0] ^ sdcard_core_crc16_inserter_crc21[15])), sdcard_core_crc16_inserter_crc21[10], sdcard_core_crc16_inserter_crc21[9], sdcard_core_crc16_inserter_crc21[8], sdcard_core_crc16_inserter_crc21[7], sdcard_core_crc16_inserter_crc21[6], sdcard_core_crc16_inserter_crc21[5], (sdcard_core_crc16_inserter_crc21[4] ^ (sdcard_core_crc16_inserter_crc2_din[0] ^ sdcard_core_crc16_inserter_crc21[15])), sdcard_core_crc16_inserter_crc21[3], sdcard_core_crc16_inserter_crc21[2], sdcard_core_crc16_inserter_crc21[1], sdcard_core_crc16_inserter_crc21[0], (sdcard_core_crc16_inserter_crc2_din[0] ^ sdcard_core_crc16_inserter_crc21[15])}; +always @(*) begin + sdcard_core_crc16_inserter_crc2_crc <= 16'd0; + if (sdcard_core_crc16_inserter_crc2_enable) begin + sdcard_core_crc16_inserter_crc2_crc <= sdcard_core_crc16_inserter_crc22; + end else begin + sdcard_core_crc16_inserter_crc2_crc <= sdcard_core_crc16_inserter_crc20; + end +end +assign sdcard_core_crc16_inserter_crc31 = {sdcard_core_crc16_inserter_crc30[14], sdcard_core_crc16_inserter_crc30[13], sdcard_core_crc16_inserter_crc30[12], (sdcard_core_crc16_inserter_crc30[11] ^ (sdcard_core_crc16_inserter_crc3_din[1] ^ sdcard_core_crc16_inserter_crc30[15])), sdcard_core_crc16_inserter_crc30[10], sdcard_core_crc16_inserter_crc30[9], sdcard_core_crc16_inserter_crc30[8], sdcard_core_crc16_inserter_crc30[7], sdcard_core_crc16_inserter_crc30[6], sdcard_core_crc16_inserter_crc30[5], (sdcard_core_crc16_inserter_crc30[4] ^ (sdcard_core_crc16_inserter_crc3_din[1] ^ sdcard_core_crc16_inserter_crc30[15])), sdcard_core_crc16_inserter_crc30[3], sdcard_core_crc16_inserter_crc30[2], sdcard_core_crc16_inserter_crc30[1], sdcard_core_crc16_inserter_crc30[0], (sdcard_core_crc16_inserter_crc3_din[1] ^ sdcard_core_crc16_inserter_crc30[15])}; +assign sdcard_core_crc16_inserter_crc32 = {sdcard_core_crc16_inserter_crc31[14], sdcard_core_crc16_inserter_crc31[13], sdcard_core_crc16_inserter_crc31[12], (sdcard_core_crc16_inserter_crc31[11] ^ (sdcard_core_crc16_inserter_crc3_din[0] ^ sdcard_core_crc16_inserter_crc31[15])), sdcard_core_crc16_inserter_crc31[10], sdcard_core_crc16_inserter_crc31[9], sdcard_core_crc16_inserter_crc31[8], sdcard_core_crc16_inserter_crc31[7], sdcard_core_crc16_inserter_crc31[6], sdcard_core_crc16_inserter_crc31[5], (sdcard_core_crc16_inserter_crc31[4] ^ (sdcard_core_crc16_inserter_crc3_din[0] ^ sdcard_core_crc16_inserter_crc31[15])), sdcard_core_crc16_inserter_crc31[3], sdcard_core_crc16_inserter_crc31[2], sdcard_core_crc16_inserter_crc31[1], sdcard_core_crc16_inserter_crc31[0], (sdcard_core_crc16_inserter_crc3_din[0] ^ sdcard_core_crc16_inserter_crc31[15])}; +always @(*) begin + sdcard_core_crc16_inserter_crc3_crc <= 16'd0; + if (sdcard_core_crc16_inserter_crc3_enable) begin + sdcard_core_crc16_inserter_crc3_crc <= sdcard_core_crc16_inserter_crc32; + end else begin + sdcard_core_crc16_inserter_crc3_crc <= sdcard_core_crc16_inserter_crc30; + end +end +always @(*) begin + crc16inserter_next_state <= 1'd0; + sdcard_core_crc16_inserter_count_crc16inserter_next_value <= 3'd0; + sdcard_core_crc16_inserter_count_crc16inserter_next_value_ce <= 1'd0; + sdcard_core_crc16_inserter_sink_ready <= 1'd0; + sdcard_core_crc16_inserter_source_first <= 1'd0; + sdcard_core_crc16_inserter_source_last <= 1'd0; + sdcard_core_crc16_inserter_source_payload_data <= 8'd0; + sdcard_core_crc16_inserter_source_valid <= 1'd0; + crc16inserter_next_state <= crc16inserter_state; + case (crc16inserter_state) + 1'd1: begin + sdcard_core_crc16_inserter_source_valid <= 1'd1; + sdcard_core_crc16_inserter_source_last <= (sdcard_core_crc16_inserter_count == 3'd7); + case (sdcard_core_crc16_inserter_count) + 1'd0: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[14]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[14]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[14]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[14]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[15]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[15]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[15]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[15]; + end + 1'd1: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[12]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[12]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[12]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[12]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[13]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[13]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[13]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[13]; + end + 2'd2: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[10]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[10]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[10]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[10]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[11]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[11]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[11]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[11]; + end + 2'd3: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[8]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[8]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[8]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[8]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[9]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[9]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[9]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[9]; + end + 3'd4: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[6]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[6]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[6]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[6]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[7]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[7]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[7]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[7]; + end + 3'd5: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[4]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[4]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[4]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[4]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[5]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[5]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[5]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[5]; + end + 3'd6: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[2]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[2]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[2]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[2]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[3]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[3]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[3]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[3]; + end + 3'd7: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[0]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[0]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[0]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[0]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[1]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[1]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[1]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[1]; + end + endcase + if ((sdcard_core_crc16_inserter_source_valid & sdcard_core_crc16_inserter_source_ready)) begin + sdcard_core_crc16_inserter_count_crc16inserter_next_value <= (sdcard_core_crc16_inserter_count + 1'd1); + sdcard_core_crc16_inserter_count_crc16inserter_next_value_ce <= 1'd1; + if (sdcard_core_crc16_inserter_source_last) begin + crc16inserter_next_state <= 1'd0; + end + end + end + default: begin + sdcard_core_crc16_inserter_count_crc16inserter_next_value <= 1'd0; + sdcard_core_crc16_inserter_count_crc16inserter_next_value_ce <= 1'd1; + sdcard_core_crc16_inserter_source_valid <= sdcard_core_crc16_inserter_sink_valid; + sdcard_core_crc16_inserter_sink_ready <= sdcard_core_crc16_inserter_source_ready; + sdcard_core_crc16_inserter_source_first <= sdcard_core_crc16_inserter_sink_first; + sdcard_core_crc16_inserter_source_payload_data <= sdcard_core_crc16_inserter_sink_payload_data; + sdcard_core_crc16_inserter_source_last <= 1'd0; + if ((sdcard_core_crc16_inserter_sink_valid & sdcard_core_crc16_inserter_sink_ready)) begin + if (sdcard_core_crc16_inserter_sink_last) begin + crc16inserter_next_state <= 1'd1; + end + end + end + endcase +end +assign sdcard_core_fifo_sink_valid = sdcard_core_sink_sink_valid1; +assign sdcard_core_sink_sink_ready1 = sdcard_core_fifo_sink_ready; +assign sdcard_core_fifo_sink_first = sdcard_core_sink_sink_first1; +assign sdcard_core_fifo_sink_last = sdcard_core_sink_sink_last1; +assign sdcard_core_fifo_sink_payload_data = sdcard_core_sink_sink_payload_data1; +assign sdcard_core_source_source_first1 = sdcard_core_fifo_source_first; +assign sdcard_core_source_source_last1 = sdcard_core_fifo_source_last; +assign sdcard_core_source_source_payload_data1 = sdcard_core_fifo_source_payload_data; +assign sdcard_core_source_source_valid1 = (sdcard_core_fifo_level >= 4'd8); +assign sdcard_core_fifo_source_ready = (sdcard_core_source_source_valid1 & sdcard_core_source_source_ready1); +assign sdcard_core_fifo_reset = ((sdcard_core_sink_sink_valid1 & sdcard_core_sink_sink_ready1) & sdcard_core_sink_sink_last1); +assign sdcard_core_fifo_syncfifo_din = {sdcard_core_fifo_fifo_in_last, sdcard_core_fifo_fifo_in_first, sdcard_core_fifo_fifo_in_payload_data}; +assign {sdcard_core_fifo_fifo_out_last, sdcard_core_fifo_fifo_out_first, sdcard_core_fifo_fifo_out_payload_data} = sdcard_core_fifo_syncfifo_dout; +assign sdcard_core_fifo_sink_ready = sdcard_core_fifo_syncfifo_writable; +assign sdcard_core_fifo_syncfifo_we = sdcard_core_fifo_sink_valid; +assign sdcard_core_fifo_fifo_in_first = sdcard_core_fifo_sink_first; +assign sdcard_core_fifo_fifo_in_last = sdcard_core_fifo_sink_last; +assign sdcard_core_fifo_fifo_in_payload_data = sdcard_core_fifo_sink_payload_data; +assign sdcard_core_fifo_source_valid = sdcard_core_fifo_syncfifo_readable; +assign sdcard_core_fifo_source_first = sdcard_core_fifo_fifo_out_first; +assign sdcard_core_fifo_source_last = sdcard_core_fifo_fifo_out_last; +assign sdcard_core_fifo_source_payload_data = sdcard_core_fifo_fifo_out_payload_data; +assign sdcard_core_fifo_syncfifo_re = sdcard_core_fifo_source_ready; +always @(*) begin + sdcard_core_fifo_wrport_adr <= 3'd0; + if (sdcard_core_fifo_replace) begin + sdcard_core_fifo_wrport_adr <= (sdcard_core_fifo_produce - 1'd1); + end else begin + sdcard_core_fifo_wrport_adr <= sdcard_core_fifo_produce; + end +end +assign sdcard_core_fifo_wrport_dat_w = sdcard_core_fifo_syncfifo_din; +assign sdcard_core_fifo_wrport_we = (sdcard_core_fifo_syncfifo_we & (sdcard_core_fifo_syncfifo_writable | sdcard_core_fifo_replace)); +assign sdcard_core_fifo_do_read = (sdcard_core_fifo_syncfifo_readable & sdcard_core_fifo_syncfifo_re); +assign sdcard_core_fifo_rdport_adr = sdcard_core_fifo_consume; +assign sdcard_core_fifo_syncfifo_dout = sdcard_core_fifo_rdport_dat_r; +assign sdcard_core_fifo_syncfifo_writable = (sdcard_core_fifo_level != 4'd8); +assign sdcard_core_fifo_syncfifo_readable = (sdcard_core_fifo_level != 1'd0); +always @(*) begin + cmdr_sink_payload_cmd_type <= 2'd0; + cmdr_sink_payload_data_type <= 2'd0; + cmdr_sink_payload_length <= 8'd0; + cmdr_sink_valid <= 1'd0; + cmdr_source_source_ready <= 1'd0; + cmdw_sink_last <= 1'd0; + cmdw_sink_payload_cmd_type <= 2'd0; + cmdw_sink_payload_data <= 8'd0; + cmdw_sink_valid <= 1'd0; + datar_sink_last <= 1'd0; + datar_sink_payload_block_length <= 10'd0; + datar_sink_valid <= 1'd0; + datar_source_source_ready <= 1'd0; + dataw_sink_first <= 1'd0; + dataw_sink_last <= 1'd0; + dataw_sink_payload_data <= 8'd0; + dataw_sink_valid <= 1'd0; + fsm_next_state <= 3'd0; + sdcard_core_cmd_count_fsm_next_value2 <= 3'd0; + sdcard_core_cmd_count_fsm_next_value_ce2 <= 1'd0; + sdcard_core_cmd_done_fsm_next_value0 <= 1'd0; + sdcard_core_cmd_done_fsm_next_value_ce0 <= 1'd0; + sdcard_core_cmd_error_fsm_next_value4 <= 1'd0; + sdcard_core_cmd_error_fsm_next_value_ce4 <= 1'd0; + sdcard_core_cmd_response_status_fsm_next_value8 <= 128'd0; + sdcard_core_cmd_response_status_fsm_next_value_ce8 <= 1'd0; + sdcard_core_cmd_timeout_fsm_next_value5 <= 1'd0; + sdcard_core_cmd_timeout_fsm_next_value_ce5 <= 1'd0; + sdcard_core_crc16_inserter_source_ready <= 1'd0; + sdcard_core_data_count_fsm_next_value3 <= 32'd0; + sdcard_core_data_count_fsm_next_value_ce3 <= 1'd0; + sdcard_core_data_done_fsm_next_value1 <= 1'd0; + sdcard_core_data_done_fsm_next_value_ce1 <= 1'd0; + sdcard_core_data_error_fsm_next_value6 <= 1'd0; + sdcard_core_data_error_fsm_next_value_ce6 <= 1'd0; + sdcard_core_data_timeout_fsm_next_value7 <= 1'd0; + sdcard_core_data_timeout_fsm_next_value_ce7 <= 1'd0; + sdcard_core_sink_sink_first1 <= 1'd0; + sdcard_core_sink_sink_last1 <= 1'd0; + sdcard_core_sink_sink_payload_data1 <= 8'd0; + sdcard_core_sink_sink_valid1 <= 1'd0; + fsm_next_state <= fsm_state; + case (fsm_state) + 1'd1: begin + cmdw_sink_valid <= 1'd1; + cmdw_sink_last <= (sdcard_core_cmd_count == 3'd5); + cmdw_sink_payload_cmd_type <= sdcard_core_cmd_type; + case (sdcard_core_cmd_count) + 1'd0: begin + cmdw_sink_payload_data <= {1'd0, 1'd1, sdcard_core_cmd}; + end + 1'd1: begin + cmdw_sink_payload_data <= sdcard_core_cmd_argument_storage[31:24]; + end + 2'd2: begin + cmdw_sink_payload_data <= sdcard_core_cmd_argument_storage[23:16]; + end + 2'd3: begin + cmdw_sink_payload_data <= sdcard_core_cmd_argument_storage[15:8]; + end + 3'd4: begin + cmdw_sink_payload_data <= sdcard_core_cmd_argument_storage[7:0]; + end + 3'd5: begin + cmdw_sink_payload_data <= {sdcard_core_crc7_inserter_crc_crc, 1'd1}; + end + endcase + if (cmdw_sink_ready) begin + sdcard_core_cmd_count_fsm_next_value2 <= (sdcard_core_cmd_count + 1'd1); + sdcard_core_cmd_count_fsm_next_value_ce2 <= 1'd1; + if (cmdw_sink_last) begin + if ((sdcard_core_cmd_type == 1'd0)) begin + fsm_next_state <= 1'd0; + end else begin + fsm_next_state <= 2'd2; + end + end + end + end + 2'd2: begin + cmdr_sink_valid <= 1'd1; + cmdr_sink_payload_cmd_type <= sdcard_core_cmd_type; + cmdr_sink_payload_data_type <= sdcard_core_data_type; + if ((sdcard_core_cmd_type == 2'd2)) begin + cmdr_sink_payload_length <= 5'd18; + end else begin + cmdr_sink_payload_length <= 3'd6; + end + cmdr_source_source_ready <= 1'd1; + if (cmdr_source_source_valid) begin + if ((cmdr_source_source_payload_status == 1'd1)) begin + sdcard_core_cmd_timeout_fsm_next_value5 <= 1'd1; + sdcard_core_cmd_timeout_fsm_next_value_ce5 <= 1'd1; + fsm_next_state <= 1'd0; + end else begin + if (cmdr_source_source_last) begin + if ((sdcard_core_data_type == 2'd2)) begin + fsm_next_state <= 2'd3; + end else begin + if ((sdcard_core_data_type == 1'd1)) begin + fsm_next_state <= 3'd4; + end else begin + fsm_next_state <= 1'd0; + end + end + end else begin + sdcard_core_cmd_response_status_fsm_next_value8 <= {sdcard_core_cmd_response_status, cmdr_source_source_payload_data}; + sdcard_core_cmd_response_status_fsm_next_value_ce8 <= 1'd1; + end + end + end + end + 2'd3: begin + dataw_sink_valid <= sdcard_core_crc16_inserter_source_valid; + sdcard_core_crc16_inserter_source_ready <= dataw_sink_ready; + dataw_sink_first <= sdcard_core_crc16_inserter_source_first; + dataw_sink_last <= sdcard_core_crc16_inserter_source_last; + dataw_sink_payload_data <= sdcard_core_crc16_inserter_source_payload_data; + if (((dataw_sink_valid & dataw_sink_ready) & dataw_sink_last)) begin + sdcard_core_data_count_fsm_next_value3 <= (sdcard_core_data_count + 1'd1); + sdcard_core_data_count_fsm_next_value_ce3 <= 1'd1; + if ((sdcard_core_data_count == (sdcard_core_block_count_storage - 1'd1))) begin + fsm_next_state <= 1'd0; + end + end + datar_source_source_ready <= 1'd1; + if (datar_source_source_valid) begin + if ((datar_source_source_payload_status != 2'd2)) begin + sdcard_core_data_error_fsm_next_value6 <= 1'd1; + sdcard_core_data_error_fsm_next_value_ce6 <= 1'd1; + end + end + end + 3'd4: begin + datar_sink_valid <= 1'd1; + datar_sink_payload_block_length <= sdcard_core_block_length_storage; + datar_sink_last <= (sdcard_core_data_count == (sdcard_core_block_count_storage - 1'd1)); + if (datar_source_source_valid) begin + if ((datar_source_source_payload_status == 1'd0)) begin + sdcard_core_sink_sink_valid1 <= datar_source_source_valid; + datar_source_source_ready <= sdcard_core_sink_sink_ready1; + sdcard_core_sink_sink_first1 <= datar_source_source_first; + sdcard_core_sink_sink_last1 <= datar_source_source_last; + sdcard_core_sink_sink_payload_data1 <= datar_source_source_payload_data; + if ((datar_source_source_last & datar_source_source_ready)) begin + sdcard_core_data_count_fsm_next_value3 <= (sdcard_core_data_count + 1'd1); + sdcard_core_data_count_fsm_next_value_ce3 <= 1'd1; + if ((sdcard_core_data_count == (sdcard_core_block_count_storage - 1'd1))) begin + fsm_next_state <= 1'd0; + end + end + end else begin + if ((datar_source_source_payload_status == 1'd1)) begin + sdcard_core_data_timeout_fsm_next_value7 <= 1'd1; + sdcard_core_data_timeout_fsm_next_value_ce7 <= 1'd1; + datar_source_source_ready <= 1'd1; + fsm_next_state <= 1'd0; + end + end + end + end + default: begin + sdcard_core_cmd_done_fsm_next_value0 <= 1'd1; + sdcard_core_cmd_done_fsm_next_value_ce0 <= 1'd1; + sdcard_core_data_done_fsm_next_value1 <= 1'd1; + sdcard_core_data_done_fsm_next_value_ce1 <= 1'd1; + sdcard_core_cmd_count_fsm_next_value2 <= 1'd0; + sdcard_core_cmd_count_fsm_next_value_ce2 <= 1'd1; + sdcard_core_data_count_fsm_next_value3 <= 1'd0; + sdcard_core_data_count_fsm_next_value_ce3 <= 1'd1; + if (sdcard_core_cmd_send_re) begin + sdcard_core_cmd_done_fsm_next_value0 <= 1'd0; + sdcard_core_cmd_done_fsm_next_value_ce0 <= 1'd1; + sdcard_core_cmd_error_fsm_next_value4 <= 1'd0; + sdcard_core_cmd_error_fsm_next_value_ce4 <= 1'd1; + sdcard_core_cmd_timeout_fsm_next_value5 <= 1'd0; + sdcard_core_cmd_timeout_fsm_next_value_ce5 <= 1'd1; + sdcard_core_data_done_fsm_next_value1 <= 1'd0; + sdcard_core_data_done_fsm_next_value_ce1 <= 1'd1; + sdcard_core_data_error_fsm_next_value6 <= 1'd0; + sdcard_core_data_error_fsm_next_value_ce6 <= 1'd1; + sdcard_core_data_timeout_fsm_next_value7 <= 1'd0; + sdcard_core_data_timeout_fsm_next_value_ce7 <= 1'd1; + fsm_next_state <= 1'd1; + end + end + endcase +end +assign sdcard_block2mem_start = (sdcard_block2mem_sink_sink_valid0 & sdcard_block2mem_sink_sink_first); +always @(*) begin + sdcard_block2mem_fifo_sink_first <= 1'd0; + sdcard_block2mem_fifo_sink_last <= 1'd0; + sdcard_block2mem_fifo_sink_payload_data <= 8'd0; + sdcard_block2mem_fifo_sink_valid <= 1'd0; + sdcard_block2mem_sink_sink_ready0 <= 1'd0; + if ((sdcard_block2mem_wishbonedmawriter_enable_storage & (sdcard_block2mem_start | sdcard_block2mem_connect))) begin + sdcard_block2mem_fifo_sink_valid <= sdcard_block2mem_sink_sink_valid0; + sdcard_block2mem_sink_sink_ready0 <= sdcard_block2mem_fifo_sink_ready; + sdcard_block2mem_fifo_sink_first <= sdcard_block2mem_sink_sink_first; + sdcard_block2mem_fifo_sink_last <= sdcard_block2mem_sink_sink_last0; + sdcard_block2mem_fifo_sink_payload_data <= sdcard_block2mem_sink_sink_payload_data0; + end else begin + sdcard_block2mem_sink_sink_ready0 <= 1'd1; + end +end +assign sdcard_block2mem_converter_sink_valid = sdcard_block2mem_fifo_source_valid; +assign sdcard_block2mem_fifo_source_ready = sdcard_block2mem_converter_sink_ready; +assign sdcard_block2mem_converter_sink_first = sdcard_block2mem_fifo_source_first; +assign sdcard_block2mem_converter_sink_last = sdcard_block2mem_fifo_source_last; +assign sdcard_block2mem_converter_sink_payload_data = sdcard_block2mem_fifo_source_payload_data; +assign sdcard_block2mem_wishbonedmawriter_sink_valid = sdcard_block2mem_source_source_valid; +assign sdcard_block2mem_source_source_ready = sdcard_block2mem_wishbonedmawriter_sink_ready; +assign sdcard_block2mem_wishbonedmawriter_sink_first = sdcard_block2mem_source_source_first; +assign sdcard_block2mem_wishbonedmawriter_sink_last = sdcard_block2mem_source_source_last; +assign sdcard_block2mem_wishbonedmawriter_sink_payload_data = sdcard_block2mem_source_source_payload_data; +assign sdcard_block2mem_fifo_syncfifo_din = {sdcard_block2mem_fifo_fifo_in_last, sdcard_block2mem_fifo_fifo_in_first, sdcard_block2mem_fifo_fifo_in_payload_data}; +assign {sdcard_block2mem_fifo_fifo_out_last, sdcard_block2mem_fifo_fifo_out_first, sdcard_block2mem_fifo_fifo_out_payload_data} = sdcard_block2mem_fifo_syncfifo_dout; +assign sdcard_block2mem_fifo_sink_ready = sdcard_block2mem_fifo_syncfifo_writable; +assign sdcard_block2mem_fifo_syncfifo_we = sdcard_block2mem_fifo_sink_valid; +assign sdcard_block2mem_fifo_fifo_in_first = sdcard_block2mem_fifo_sink_first; +assign sdcard_block2mem_fifo_fifo_in_last = sdcard_block2mem_fifo_sink_last; +assign sdcard_block2mem_fifo_fifo_in_payload_data = sdcard_block2mem_fifo_sink_payload_data; +assign sdcard_block2mem_fifo_source_valid = sdcard_block2mem_fifo_readable; +assign sdcard_block2mem_fifo_source_first = sdcard_block2mem_fifo_fifo_out_first; +assign sdcard_block2mem_fifo_source_last = sdcard_block2mem_fifo_fifo_out_last; +assign sdcard_block2mem_fifo_source_payload_data = sdcard_block2mem_fifo_fifo_out_payload_data; +assign sdcard_block2mem_fifo_re = sdcard_block2mem_fifo_source_ready; +assign sdcard_block2mem_fifo_syncfifo_re = (sdcard_block2mem_fifo_syncfifo_readable & ((~sdcard_block2mem_fifo_readable) | sdcard_block2mem_fifo_re)); +assign sdcard_block2mem_fifo_level1 = (sdcard_block2mem_fifo_level0 + sdcard_block2mem_fifo_readable); +always @(*) begin + sdcard_block2mem_fifo_wrport_adr <= 9'd0; + if (sdcard_block2mem_fifo_replace) begin + sdcard_block2mem_fifo_wrport_adr <= (sdcard_block2mem_fifo_produce - 1'd1); + end else begin + sdcard_block2mem_fifo_wrport_adr <= sdcard_block2mem_fifo_produce; + end +end +assign sdcard_block2mem_fifo_wrport_dat_w = sdcard_block2mem_fifo_syncfifo_din; +assign sdcard_block2mem_fifo_wrport_we = (sdcard_block2mem_fifo_syncfifo_we & (sdcard_block2mem_fifo_syncfifo_writable | sdcard_block2mem_fifo_replace)); +assign sdcard_block2mem_fifo_do_read = (sdcard_block2mem_fifo_syncfifo_readable & sdcard_block2mem_fifo_syncfifo_re); +assign sdcard_block2mem_fifo_rdport_adr = sdcard_block2mem_fifo_consume; +assign sdcard_block2mem_fifo_syncfifo_dout = sdcard_block2mem_fifo_rdport_dat_r; +assign sdcard_block2mem_fifo_rdport_re = sdcard_block2mem_fifo_do_read; +assign sdcard_block2mem_fifo_syncfifo_writable = (sdcard_block2mem_fifo_level0 != 10'd512); +assign sdcard_block2mem_fifo_syncfifo_readable = (sdcard_block2mem_fifo_level0 != 1'd0); +assign sdcard_block2mem_source_source_valid = sdcard_block2mem_converter_source_valid; +assign sdcard_block2mem_converter_source_ready = sdcard_block2mem_source_source_ready; +assign sdcard_block2mem_source_source_first = sdcard_block2mem_converter_source_first; +assign sdcard_block2mem_source_source_last = sdcard_block2mem_converter_source_last; +assign sdcard_block2mem_source_source_payload_data = sdcard_block2mem_converter_source_payload_data; +assign sdcard_block2mem_converter_sink_ready = ((~sdcard_block2mem_converter_strobe_all) | sdcard_block2mem_converter_source_ready); +assign sdcard_block2mem_converter_source_valid = sdcard_block2mem_converter_strobe_all; +assign sdcard_block2mem_converter_load_part = (sdcard_block2mem_converter_sink_valid & sdcard_block2mem_converter_sink_ready); +assign interface0_bus_stb = sdcard_block2mem_sink_sink_valid1; +assign interface0_bus_cyc = sdcard_block2mem_sink_sink_valid1; +assign interface0_bus_we = 1'd1; +assign interface0_bus_sel = 4'd15; +assign interface0_bus_adr = sdcard_block2mem_sink_sink_payload_address; +assign interface0_bus_dat_w = {sdcard_block2mem_sink_sink_payload_data1[7:0], sdcard_block2mem_sink_sink_payload_data1[15:8], sdcard_block2mem_sink_sink_payload_data1[23:16], sdcard_block2mem_sink_sink_payload_data1[31:24]}; +assign sdcard_block2mem_sink_sink_ready1 = interface0_bus_ack; +assign sdcard_block2mem_wishbonedmawriter_base = sdcard_block2mem_wishbonedmawriter_base_storage[63:2]; +assign sdcard_block2mem_wishbonedmawriter_length = sdcard_block2mem_wishbonedmawriter_length_storage[31:2]; +assign sdcard_block2mem_wishbonedmawriter_offset_status = sdcard_block2mem_wishbonedmawriter_offset; +assign sdcard_block2mem_wishbonedmawriter_reset = (~sdcard_block2mem_wishbonedmawriter_enable_storage); +always @(*) begin + sdblock2memdma_next_state <= 2'd0; + sdcard_block2mem_sink_sink_last1 <= 1'd0; + sdcard_block2mem_sink_sink_payload_address <= 32'd0; + sdcard_block2mem_sink_sink_payload_data1 <= 32'd0; + sdcard_block2mem_sink_sink_valid1 <= 1'd0; + sdcard_block2mem_wishbonedmawriter_done_status <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= 32'd0; + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd0; + sdcard_block2mem_wishbonedmawriter_sink_ready <= 1'd0; + sdblock2memdma_next_state <= sdblock2memdma_state; + case (sdblock2memdma_state) + 1'd1: begin + sdcard_block2mem_sink_sink_valid1 <= sdcard_block2mem_wishbonedmawriter_sink_valid; + sdcard_block2mem_sink_sink_last1 <= (sdcard_block2mem_wishbonedmawriter_sink_last | ((sdcard_block2mem_wishbonedmawriter_offset + 1'd1) == sdcard_block2mem_wishbonedmawriter_length)); + sdcard_block2mem_sink_sink_payload_address <= (sdcard_block2mem_wishbonedmawriter_base + sdcard_block2mem_wishbonedmawriter_offset); + sdcard_block2mem_sink_sink_payload_data1 <= sdcard_block2mem_wishbonedmawriter_sink_payload_data; + sdcard_block2mem_wishbonedmawriter_sink_ready <= sdcard_block2mem_sink_sink_ready1; + if ((sdcard_block2mem_wishbonedmawriter_sink_valid & sdcard_block2mem_wishbonedmawriter_sink_ready)) begin + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= (sdcard_block2mem_wishbonedmawriter_offset + 1'd1); + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd1; + if (sdcard_block2mem_sink_sink_last1) begin + if (sdcard_block2mem_wishbonedmawriter_loop_storage) begin + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd1; + end else begin + sdblock2memdma_next_state <= 2'd2; + end + end + end + end + 2'd2: begin + sdcard_block2mem_wishbonedmawriter_done_status <= 1'd1; + end + default: begin + sdcard_block2mem_wishbonedmawriter_sink_ready <= 1'd1; + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd1; + sdblock2memdma_next_state <= 1'd1; + end + endcase +end +assign sdcard_mem2block_converter_converter_sink_valid = sdcard_mem2block_dma_source_source_valid; +assign sdcard_mem2block_dma_source_source_ready = sdcard_mem2block_converter_converter_sink_ready; +assign sdcard_mem2block_converter_converter_sink_first = sdcard_mem2block_dma_source_source_first; +assign sdcard_mem2block_converter_converter_sink_last = sdcard_mem2block_dma_source_source_last; +assign sdcard_mem2block_converter_converter_sink_payload_data = sdcard_mem2block_dma_source_source_payload_data; +assign sdcard_mem2block_fifo_sink_valid = sdcard_mem2block_converter_source_source_valid; +assign sdcard_mem2block_converter_source_source_ready = sdcard_mem2block_fifo_sink_ready; +assign sdcard_mem2block_fifo_sink_first = sdcard_mem2block_converter_source_source_first; +assign sdcard_mem2block_fifo_sink_last = sdcard_mem2block_converter_source_source_last; +assign sdcard_mem2block_fifo_sink_payload_data = sdcard_mem2block_converter_source_source_payload_data; +assign sdcard_mem2block_source_source_valid = sdcard_mem2block_fifo_source_valid; +assign sdcard_mem2block_fifo_source_ready = sdcard_mem2block_source_source_ready; +assign sdcard_mem2block_source_source_first = sdcard_mem2block_fifo_source_first; +assign sdcard_mem2block_source_source_payload_data = sdcard_mem2block_fifo_source_payload_data; +always @(*) begin + sdcard_mem2block_source_source_last <= 1'd0; + sdcard_mem2block_source_source_last <= sdcard_mem2block_fifo_source_last; + if ((sdcard_mem2block_count == 9'd511)) begin + sdcard_mem2block_source_source_last <= 1'd1; + end +end +assign interface1_bus_stb = (sdcard_mem2block_dma_sink_sink_valid & sdcard_mem2block_dma_fifo_sink_ready); +assign interface1_bus_cyc = (sdcard_mem2block_dma_sink_sink_valid & sdcard_mem2block_dma_fifo_sink_ready); +assign interface1_bus_we = 1'd0; +assign interface1_bus_sel = 4'd15; +assign interface1_bus_adr = sdcard_mem2block_dma_sink_sink_payload_address; +assign sdcard_mem2block_dma_fifo_sink_last = sdcard_mem2block_dma_sink_sink_last; +assign sdcard_mem2block_dma_fifo_sink_payload_data = {interface1_bus_dat_r[7:0], interface1_bus_dat_r[15:8], interface1_bus_dat_r[23:16], interface1_bus_dat_r[31:24]}; +always @(*) begin + sdcard_mem2block_dma_fifo_sink_valid <= 1'd0; + sdcard_mem2block_dma_sink_sink_ready <= 1'd0; + if ((interface1_bus_stb & interface1_bus_ack)) begin + sdcard_mem2block_dma_sink_sink_ready <= 1'd1; + sdcard_mem2block_dma_fifo_sink_valid <= 1'd1; + end +end +assign sdcard_mem2block_dma_source_source_valid = sdcard_mem2block_dma_fifo_source_valid; +assign sdcard_mem2block_dma_fifo_source_ready = sdcard_mem2block_dma_source_source_ready; +assign sdcard_mem2block_dma_source_source_first = sdcard_mem2block_dma_fifo_source_first; +assign sdcard_mem2block_dma_source_source_last = sdcard_mem2block_dma_fifo_source_last; +assign sdcard_mem2block_dma_source_source_payload_data = sdcard_mem2block_dma_fifo_source_payload_data; +assign sdcard_mem2block_dma_base = sdcard_mem2block_dma_base_storage[63:2]; +assign sdcard_mem2block_dma_length = sdcard_mem2block_dma_length_storage[31:2]; +assign sdcard_mem2block_dma_offset_status = sdcard_mem2block_dma_offset; +assign sdcard_mem2block_dma_reset = (~sdcard_mem2block_dma_enable_storage); +assign sdcard_mem2block_dma_fifo_syncfifo_din = {sdcard_mem2block_dma_fifo_fifo_in_last, sdcard_mem2block_dma_fifo_fifo_in_first, sdcard_mem2block_dma_fifo_fifo_in_payload_data}; +assign {sdcard_mem2block_dma_fifo_fifo_out_last, sdcard_mem2block_dma_fifo_fifo_out_first, sdcard_mem2block_dma_fifo_fifo_out_payload_data} = sdcard_mem2block_dma_fifo_syncfifo_dout; +assign sdcard_mem2block_dma_fifo_sink_ready = sdcard_mem2block_dma_fifo_syncfifo_writable; +assign sdcard_mem2block_dma_fifo_syncfifo_we = sdcard_mem2block_dma_fifo_sink_valid; +assign sdcard_mem2block_dma_fifo_fifo_in_first = sdcard_mem2block_dma_fifo_sink_first; +assign sdcard_mem2block_dma_fifo_fifo_in_last = sdcard_mem2block_dma_fifo_sink_last; +assign sdcard_mem2block_dma_fifo_fifo_in_payload_data = sdcard_mem2block_dma_fifo_sink_payload_data; +assign sdcard_mem2block_dma_fifo_source_valid = sdcard_mem2block_dma_fifo_syncfifo_readable; +assign sdcard_mem2block_dma_fifo_source_first = sdcard_mem2block_dma_fifo_fifo_out_first; +assign sdcard_mem2block_dma_fifo_source_last = sdcard_mem2block_dma_fifo_fifo_out_last; +assign sdcard_mem2block_dma_fifo_source_payload_data = sdcard_mem2block_dma_fifo_fifo_out_payload_data; +assign sdcard_mem2block_dma_fifo_syncfifo_re = sdcard_mem2block_dma_fifo_source_ready; +always @(*) begin + sdcard_mem2block_dma_fifo_wrport_adr <= 4'd0; + if (sdcard_mem2block_dma_fifo_replace) begin + sdcard_mem2block_dma_fifo_wrport_adr <= (sdcard_mem2block_dma_fifo_produce - 1'd1); + end else begin + sdcard_mem2block_dma_fifo_wrport_adr <= sdcard_mem2block_dma_fifo_produce; + end +end +assign sdcard_mem2block_dma_fifo_wrport_dat_w = sdcard_mem2block_dma_fifo_syncfifo_din; +assign sdcard_mem2block_dma_fifo_wrport_we = (sdcard_mem2block_dma_fifo_syncfifo_we & (sdcard_mem2block_dma_fifo_syncfifo_writable | sdcard_mem2block_dma_fifo_replace)); +assign sdcard_mem2block_dma_fifo_do_read = (sdcard_mem2block_dma_fifo_syncfifo_readable & sdcard_mem2block_dma_fifo_syncfifo_re); +assign sdcard_mem2block_dma_fifo_rdport_adr = sdcard_mem2block_dma_fifo_consume; +assign sdcard_mem2block_dma_fifo_syncfifo_dout = sdcard_mem2block_dma_fifo_rdport_dat_r; +assign sdcard_mem2block_dma_fifo_syncfifo_writable = (sdcard_mem2block_dma_fifo_level != 5'd16); +assign sdcard_mem2block_dma_fifo_syncfifo_readable = (sdcard_mem2block_dma_fifo_level != 1'd0); +always @(*) begin + sdcard_mem2block_dma_done_status <= 1'd0; + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= 32'd0; + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd0; + sdcard_mem2block_dma_sink_sink_last <= 1'd0; + sdcard_mem2block_dma_sink_sink_payload_address <= 32'd0; + sdcard_mem2block_dma_sink_sink_valid <= 1'd0; + sdmem2blockdma_next_state <= 2'd0; + sdmem2blockdma_next_state <= sdmem2blockdma_state; + case (sdmem2blockdma_state) + 1'd1: begin + sdcard_mem2block_dma_sink_sink_valid <= 1'd1; + sdcard_mem2block_dma_sink_sink_last <= (sdcard_mem2block_dma_offset == (sdcard_mem2block_dma_length - 1'd1)); + sdcard_mem2block_dma_sink_sink_payload_address <= (sdcard_mem2block_dma_base + sdcard_mem2block_dma_offset); + if (sdcard_mem2block_dma_sink_sink_ready) begin + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= (sdcard_mem2block_dma_offset + 1'd1); + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd1; + if (sdcard_mem2block_dma_sink_sink_last) begin + if (sdcard_mem2block_dma_loop_storage) begin + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= 1'd0; + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd1; + end else begin + sdmem2blockdma_next_state <= 2'd2; + end + end + end + end + 2'd2: begin + sdcard_mem2block_dma_done_status <= 1'd1; + end + default: begin + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= 1'd0; + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd1; + sdmem2blockdma_next_state <= 1'd1; + end + endcase +end +assign sdcard_mem2block_converter_source_source_valid = sdcard_mem2block_converter_converter_source_valid; +assign sdcard_mem2block_converter_converter_source_ready = sdcard_mem2block_converter_source_source_ready; +assign sdcard_mem2block_converter_source_source_first = sdcard_mem2block_converter_converter_source_first; +assign sdcard_mem2block_converter_source_source_last = sdcard_mem2block_converter_converter_source_last; +assign sdcard_mem2block_converter_source_source_payload_data = sdcard_mem2block_converter_converter_source_payload_data; +assign sdcard_mem2block_converter_converter_first = (sdcard_mem2block_converter_converter_mux == 1'd0); +assign sdcard_mem2block_converter_converter_last = (sdcard_mem2block_converter_converter_mux == 2'd3); +assign sdcard_mem2block_converter_converter_source_valid = sdcard_mem2block_converter_converter_sink_valid; +assign sdcard_mem2block_converter_converter_source_first = (sdcard_mem2block_converter_converter_sink_first & sdcard_mem2block_converter_converter_first); +assign sdcard_mem2block_converter_converter_source_last = (sdcard_mem2block_converter_converter_sink_last & sdcard_mem2block_converter_converter_last); +assign sdcard_mem2block_converter_converter_sink_ready = (sdcard_mem2block_converter_converter_last & sdcard_mem2block_converter_converter_source_ready); +always @(*) begin + sdcard_mem2block_converter_converter_source_payload_data <= 8'd0; + case (sdcard_mem2block_converter_converter_mux) + 1'd0: begin + sdcard_mem2block_converter_converter_source_payload_data <= sdcard_mem2block_converter_converter_sink_payload_data[31:24]; + end + 1'd1: begin + sdcard_mem2block_converter_converter_source_payload_data <= sdcard_mem2block_converter_converter_sink_payload_data[23:16]; + end + 2'd2: begin + sdcard_mem2block_converter_converter_source_payload_data <= sdcard_mem2block_converter_converter_sink_payload_data[15:8]; + end + default: begin + sdcard_mem2block_converter_converter_source_payload_data <= sdcard_mem2block_converter_converter_sink_payload_data[7:0]; + end + endcase +end +assign sdcard_mem2block_converter_converter_source_payload_valid_token_count = sdcard_mem2block_converter_converter_last; +assign sdcard_mem2block_fifo_syncfifo_din = {sdcard_mem2block_fifo_fifo_in_last, sdcard_mem2block_fifo_fifo_in_first, sdcard_mem2block_fifo_fifo_in_payload_data}; +assign {sdcard_mem2block_fifo_fifo_out_last, sdcard_mem2block_fifo_fifo_out_first, sdcard_mem2block_fifo_fifo_out_payload_data} = sdcard_mem2block_fifo_syncfifo_dout; +assign sdcard_mem2block_fifo_sink_ready = sdcard_mem2block_fifo_syncfifo_writable; +assign sdcard_mem2block_fifo_syncfifo_we = sdcard_mem2block_fifo_sink_valid; +assign sdcard_mem2block_fifo_fifo_in_first = sdcard_mem2block_fifo_sink_first; +assign sdcard_mem2block_fifo_fifo_in_last = sdcard_mem2block_fifo_sink_last; +assign sdcard_mem2block_fifo_fifo_in_payload_data = sdcard_mem2block_fifo_sink_payload_data; +assign sdcard_mem2block_fifo_source_valid = sdcard_mem2block_fifo_readable; +assign sdcard_mem2block_fifo_source_first = sdcard_mem2block_fifo_fifo_out_first; +assign sdcard_mem2block_fifo_source_last = sdcard_mem2block_fifo_fifo_out_last; +assign sdcard_mem2block_fifo_source_payload_data = sdcard_mem2block_fifo_fifo_out_payload_data; +assign sdcard_mem2block_fifo_re = sdcard_mem2block_fifo_source_ready; +assign sdcard_mem2block_fifo_syncfifo_re = (sdcard_mem2block_fifo_syncfifo_readable & ((~sdcard_mem2block_fifo_readable) | sdcard_mem2block_fifo_re)); +assign sdcard_mem2block_fifo_level1 = (sdcard_mem2block_fifo_level0 + sdcard_mem2block_fifo_readable); +always @(*) begin + sdcard_mem2block_fifo_wrport_adr <= 9'd0; + if (sdcard_mem2block_fifo_replace) begin + sdcard_mem2block_fifo_wrport_adr <= (sdcard_mem2block_fifo_produce - 1'd1); + end else begin + sdcard_mem2block_fifo_wrport_adr <= sdcard_mem2block_fifo_produce; + end +end +assign sdcard_mem2block_fifo_wrport_dat_w = sdcard_mem2block_fifo_syncfifo_din; +assign sdcard_mem2block_fifo_wrport_we = (sdcard_mem2block_fifo_syncfifo_we & (sdcard_mem2block_fifo_syncfifo_writable | sdcard_mem2block_fifo_replace)); +assign sdcard_mem2block_fifo_do_read = (sdcard_mem2block_fifo_syncfifo_readable & sdcard_mem2block_fifo_syncfifo_re); +assign sdcard_mem2block_fifo_rdport_adr = sdcard_mem2block_fifo_consume; +assign sdcard_mem2block_fifo_syncfifo_dout = sdcard_mem2block_fifo_rdport_dat_r; +assign sdcard_mem2block_fifo_rdport_re = sdcard_mem2block_fifo_do_read; +assign sdcard_mem2block_fifo_syncfifo_writable = (sdcard_mem2block_fifo_level0 != 10'd512); +assign sdcard_mem2block_fifo_syncfifo_readable = (sdcard_mem2block_fifo_level0 != 1'd0); +assign eventmanager_card_detect0 = card_detect_status1; +assign eventmanager_card_detect1 = card_detect_pending; +always @(*) begin + card_detect_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[0])) begin + card_detect_clear <= 1'd1; + end +end +assign eventmanager_block2mem_dma0 = block2mem_dma_status; +assign eventmanager_block2mem_dma1 = block2mem_dma_pending; +always @(*) begin + block2mem_dma_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[1])) begin + block2mem_dma_clear <= 1'd1; + end +end +assign eventmanager_mem2block_dma0 = mem2block_dma_status; +assign eventmanager_mem2block_dma1 = mem2block_dma_pending; +always @(*) begin + mem2block_dma_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[2])) begin + mem2block_dma_clear <= 1'd1; + end +end +assign eventmanager_cmd_done0 = cmd_done_status; +assign eventmanager_cmd_done1 = cmd_done_pending; +always @(*) begin + cmd_done_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[3])) begin + cmd_done_clear <= 1'd1; + end +end +assign sdcard_irq_irq = ((((eventmanager_pending_status[0] & eventmanager_enable_storage[0]) | (eventmanager_pending_status[1] & eventmanager_enable_storage[1])) | (eventmanager_pending_status[2] & eventmanager_enable_storage[2])) | (eventmanager_pending_status[3] & eventmanager_enable_storage[3])); +assign card_detect_status1 = 1'd0; +assign block2mem_dma_status = 1'd0; +assign mem2block_dma_status = 1'd0; +assign cmd_done_status = cmd_done_trigger; +assign cmd_done_pending = cmd_done_trigger; +always @(*) begin + interface0_ack <= 1'd0; + interface0_dat_r <= 32'd0; + interface1_adr <= 14'd0; + interface1_dat_w <= 32'd0; + interface1_we <= 1'd0; + wishbone2csr_next_state <= 1'd0; + wishbone2csr_next_state <= wishbone2csr_state; + case (wishbone2csr_state) + 1'd1: begin + interface0_ack <= 1'd1; + interface0_dat_r <= interface1_dat_r; + wishbone2csr_next_state <= 1'd0; + end + default: begin + interface1_dat_w <= interface0_dat_w; + if ((interface0_cyc & interface0_stb)) begin + interface1_adr <= interface0_adr[29:0]; + interface1_we <= (interface0_we & (interface0_sel != 1'd0)); + wishbone2csr_next_state <= 1'd1; + end + end + endcase +end +assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); +assign csrbank0_reset0_r = interface0_bank_bus_dat_w[1:0]; +always @(*) begin + csrbank0_reset0_re <= 1'd0; + csrbank0_reset0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_reset0_re <= interface0_bank_bus_we; + csrbank0_reset0_we <= (~interface0_bank_bus_we); + end +end +assign csrbank0_scratch0_r = interface0_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank0_scratch0_re <= 1'd0; + csrbank0_scratch0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_scratch0_re <= interface0_bank_bus_we; + csrbank0_scratch0_we <= (~interface0_bank_bus_we); + end +end +assign csrbank0_bus_errors_r = interface0_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank0_bus_errors_re <= 1'd0; + csrbank0_bus_errors_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 2'd2))) begin + csrbank0_bus_errors_re <= interface0_bank_bus_we; + csrbank0_bus_errors_we <= (~interface0_bank_bus_we); + end +end +always @(*) begin + soc_rst <= 1'd0; + if (reset_re) begin + soc_rst <= reset_storage[0]; + end +end +assign cpu_rst = reset_storage[1]; +assign csrbank0_reset0_w = reset_storage[1:0]; +assign csrbank0_scratch0_w = scratch_storage[31:0]; +assign csrbank0_bus_errors_w = bus_errors_status[31:0]; +assign bus_errors_we = csrbank0_bus_errors_we; +assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); +assign csrbank1_dma_base1_r = interface1_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank1_dma_base1_re <= 1'd0; + csrbank1_dma_base1_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_dma_base1_re <= interface1_bank_bus_we; + csrbank1_dma_base1_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_base0_r = interface1_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank1_dma_base0_re <= 1'd0; + csrbank1_dma_base0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + csrbank1_dma_base0_re <= interface1_bank_bus_we; + csrbank1_dma_base0_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_length0_r = interface1_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank1_dma_length0_re <= 1'd0; + csrbank1_dma_length0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + csrbank1_dma_length0_re <= interface1_bank_bus_we; + csrbank1_dma_length0_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_enable0_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + csrbank1_dma_enable0_re <= 1'd0; + csrbank1_dma_enable0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + csrbank1_dma_enable0_re <= interface1_bank_bus_we; + csrbank1_dma_enable0_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_done_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + csrbank1_dma_done_re <= 1'd0; + csrbank1_dma_done_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + csrbank1_dma_done_re <= interface1_bank_bus_we; + csrbank1_dma_done_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_loop0_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + csrbank1_dma_loop0_re <= 1'd0; + csrbank1_dma_loop0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + csrbank1_dma_loop0_re <= interface1_bank_bus_we; + csrbank1_dma_loop0_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_offset_r = interface1_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank1_dma_offset_re <= 1'd0; + csrbank1_dma_offset_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + csrbank1_dma_offset_re <= interface1_bank_bus_we; + csrbank1_dma_offset_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_base1_w = sdcard_block2mem_wishbonedmawriter_base_storage[63:32]; +assign csrbank1_dma_base0_w = sdcard_block2mem_wishbonedmawriter_base_storage[31:0]; +assign csrbank1_dma_length0_w = sdcard_block2mem_wishbonedmawriter_length_storage[31:0]; +assign csrbank1_dma_enable0_w = sdcard_block2mem_wishbonedmawriter_enable_storage; +assign csrbank1_dma_done_w = sdcard_block2mem_wishbonedmawriter_done_status; +assign sdcard_block2mem_wishbonedmawriter_done_we = csrbank1_dma_done_we; +assign csrbank1_dma_loop0_w = sdcard_block2mem_wishbonedmawriter_loop_storage; +assign csrbank1_dma_offset_w = sdcard_block2mem_wishbonedmawriter_offset_status[31:0]; +assign sdcard_block2mem_wishbonedmawriter_offset_we = csrbank1_dma_offset_we; +assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); +assign csrbank2_cmd_argument0_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_cmd_argument0_re <= 1'd0; + csrbank2_cmd_argument0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_cmd_argument0_re <= interface2_bank_bus_we; + csrbank2_cmd_argument0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_command0_r = interface2_bank_bus_dat_w[13:0]; +always @(*) begin + csrbank2_cmd_command0_re <= 1'd0; + csrbank2_cmd_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_cmd_command0_re <= interface2_bank_bus_we; + csrbank2_cmd_command0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_send0_r = interface2_bank_bus_dat_w[0]; +always @(*) begin + csrbank2_cmd_send0_re <= 1'd0; + csrbank2_cmd_send0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + csrbank2_cmd_send0_re <= interface2_bank_bus_we; + csrbank2_cmd_send0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_response3_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_cmd_response3_re <= 1'd0; + csrbank2_cmd_response3_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin + csrbank2_cmd_response3_re <= interface2_bank_bus_we; + csrbank2_cmd_response3_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_response2_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_cmd_response2_re <= 1'd0; + csrbank2_cmd_response2_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin + csrbank2_cmd_response2_re <= interface2_bank_bus_we; + csrbank2_cmd_response2_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_response1_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_cmd_response1_re <= 1'd0; + csrbank2_cmd_response1_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin + csrbank2_cmd_response1_re <= interface2_bank_bus_we; + csrbank2_cmd_response1_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_response0_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_cmd_response0_re <= 1'd0; + csrbank2_cmd_response0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin + csrbank2_cmd_response0_re <= interface2_bank_bus_we; + csrbank2_cmd_response0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_event_r = interface2_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank2_cmd_event_re <= 1'd0; + csrbank2_cmd_event_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin + csrbank2_cmd_event_re <= interface2_bank_bus_we; + csrbank2_cmd_event_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_data_event_r = interface2_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank2_data_event_re <= 1'd0; + csrbank2_data_event_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin + csrbank2_data_event_re <= interface2_bank_bus_we; + csrbank2_data_event_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_block_length0_r = interface2_bank_bus_dat_w[9:0]; +always @(*) begin + csrbank2_block_length0_re <= 1'd0; + csrbank2_block_length0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin + csrbank2_block_length0_re <= interface2_bank_bus_we; + csrbank2_block_length0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_block_count0_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_block_count0_re <= 1'd0; + csrbank2_block_count0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin + csrbank2_block_count0_re <= interface2_bank_bus_we; + csrbank2_block_count0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_argument0_w = sdcard_core_cmd_argument_storage[31:0]; +assign sdcard_core_csrfield_cmd_type = sdcard_core_cmd_command_storage[1:0]; +assign sdcard_core_csrfield_data_type = sdcard_core_cmd_command_storage[6:5]; +assign sdcard_core_csrfield_cmd = sdcard_core_cmd_command_storage[13:8]; +assign csrbank2_cmd_command0_w = sdcard_core_cmd_command_storage[13:0]; +assign csrbank2_cmd_send0_w = sdcard_core_cmd_send_storage; +assign csrbank2_cmd_response3_w = sdcard_core_cmd_response_status[127:96]; +assign csrbank2_cmd_response2_w = sdcard_core_cmd_response_status[95:64]; +assign csrbank2_cmd_response1_w = sdcard_core_cmd_response_status[63:32]; +assign csrbank2_cmd_response0_w = sdcard_core_cmd_response_status[31:0]; +assign sdcard_core_cmd_response_we = csrbank2_cmd_response0_we; +always @(*) begin + sdcard_core_cmd_event_status <= 4'd0; + sdcard_core_cmd_event_status[0] <= sdcard_core_csrfield_done0; + sdcard_core_cmd_event_status[1] <= sdcard_core_csrfield_error0; + sdcard_core_cmd_event_status[2] <= sdcard_core_csrfield_timeout0; + sdcard_core_cmd_event_status[3] <= sdcard_core_csrfield_crc0; +end +assign csrbank2_cmd_event_w = sdcard_core_cmd_event_status[3:0]; +assign sdcard_core_cmd_event_we = csrbank2_cmd_event_we; +always @(*) begin + sdcard_core_data_event_status <= 4'd0; + sdcard_core_data_event_status[0] <= sdcard_core_csrfield_done1; + sdcard_core_data_event_status[1] <= sdcard_core_csrfield_error1; + sdcard_core_data_event_status[2] <= sdcard_core_csrfield_timeout1; + sdcard_core_data_event_status[3] <= sdcard_core_csrfield_crc1; +end +assign csrbank2_data_event_w = sdcard_core_data_event_status[3:0]; +assign sdcard_core_data_event_we = csrbank2_data_event_we; +assign csrbank2_block_length0_w = sdcard_core_block_length_storage[9:0]; +assign csrbank2_block_count0_w = sdcard_core_block_count_storage[31:0]; +assign csrbank3_sel = (interface3_bank_bus_adr[13:9] == 2'd3); +assign csrbank3_status_r = interface3_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank3_status_re <= 1'd0; + csrbank3_status_we <= 1'd0; + if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 1'd0))) begin + csrbank3_status_re <= interface3_bank_bus_we; + csrbank3_status_we <= (~interface3_bank_bus_we); + end +end +assign csrbank3_pending_r = interface3_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank3_pending_re <= 1'd0; + csrbank3_pending_we <= 1'd0; + if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 1'd1))) begin + csrbank3_pending_re <= interface3_bank_bus_we; + csrbank3_pending_we <= (~interface3_bank_bus_we); + end +end +assign csrbank3_enable0_r = interface3_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank3_enable0_re <= 1'd0; + csrbank3_enable0_we <= 1'd0; + if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 2'd2))) begin + csrbank3_enable0_re <= interface3_bank_bus_we; + csrbank3_enable0_we <= (~interface3_bank_bus_we); + end +end +always @(*) begin + eventmanager_status_status <= 4'd0; + eventmanager_status_status[0] <= eventmanager_card_detect0; + eventmanager_status_status[1] <= eventmanager_block2mem_dma0; + eventmanager_status_status[2] <= eventmanager_mem2block_dma0; + eventmanager_status_status[3] <= eventmanager_cmd_done0; +end +assign csrbank3_status_w = eventmanager_status_status[3:0]; +assign eventmanager_status_we = csrbank3_status_we; +always @(*) begin + eventmanager_pending_status <= 4'd0; + eventmanager_pending_status[0] <= eventmanager_card_detect1; + eventmanager_pending_status[1] <= eventmanager_block2mem_dma1; + eventmanager_pending_status[2] <= eventmanager_mem2block_dma1; + eventmanager_pending_status[3] <= eventmanager_cmd_done1; +end +assign csrbank3_pending_w = eventmanager_pending_status[3:0]; +assign eventmanager_pending_we = csrbank3_pending_we; +assign eventmanager_card_detect2 = eventmanager_enable_storage[0]; +assign eventmanager_block2mem_dma2 = eventmanager_enable_storage[1]; +assign eventmanager_mem2block_dma2 = eventmanager_enable_storage[2]; +assign eventmanager_cmd_done2 = eventmanager_enable_storage[3]; +assign csrbank3_enable0_w = eventmanager_enable_storage[3:0]; +assign csrbank4_sel = (interface4_bank_bus_adr[13:9] == 3'd4); +assign csrbank4_dma_base1_r = interface4_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank4_dma_base1_re <= 1'd0; + csrbank4_dma_base1_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 1'd0))) begin + csrbank4_dma_base1_re <= interface4_bank_bus_we; + csrbank4_dma_base1_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_base0_r = interface4_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank4_dma_base0_re <= 1'd0; + csrbank4_dma_base0_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 1'd1))) begin + csrbank4_dma_base0_re <= interface4_bank_bus_we; + csrbank4_dma_base0_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_length0_r = interface4_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank4_dma_length0_re <= 1'd0; + csrbank4_dma_length0_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 2'd2))) begin + csrbank4_dma_length0_re <= interface4_bank_bus_we; + csrbank4_dma_length0_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_enable0_r = interface4_bank_bus_dat_w[0]; +always @(*) begin + csrbank4_dma_enable0_re <= 1'd0; + csrbank4_dma_enable0_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 2'd3))) begin + csrbank4_dma_enable0_re <= interface4_bank_bus_we; + csrbank4_dma_enable0_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_done_r = interface4_bank_bus_dat_w[0]; +always @(*) begin + csrbank4_dma_done_re <= 1'd0; + csrbank4_dma_done_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd4))) begin + csrbank4_dma_done_re <= interface4_bank_bus_we; + csrbank4_dma_done_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_loop0_r = interface4_bank_bus_dat_w[0]; +always @(*) begin + csrbank4_dma_loop0_re <= 1'd0; + csrbank4_dma_loop0_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd5))) begin + csrbank4_dma_loop0_re <= interface4_bank_bus_we; + csrbank4_dma_loop0_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_offset_r = interface4_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank4_dma_offset_re <= 1'd0; + csrbank4_dma_offset_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd6))) begin + csrbank4_dma_offset_re <= interface4_bank_bus_we; + csrbank4_dma_offset_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_base1_w = sdcard_mem2block_dma_base_storage[63:32]; +assign csrbank4_dma_base0_w = sdcard_mem2block_dma_base_storage[31:0]; +assign csrbank4_dma_length0_w = sdcard_mem2block_dma_length_storage[31:0]; +assign csrbank4_dma_enable0_w = sdcard_mem2block_dma_enable_storage; +assign csrbank4_dma_done_w = sdcard_mem2block_dma_done_status; +assign sdcard_mem2block_dma_done_we = csrbank4_dma_done_we; +assign csrbank4_dma_loop0_w = sdcard_mem2block_dma_loop_storage; +assign csrbank4_dma_offset_w = sdcard_mem2block_dma_offset_status[31:0]; +assign sdcard_mem2block_dma_offset_we = csrbank4_dma_offset_we; +assign csrbank5_sel = (interface5_bank_bus_adr[13:9] == 3'd5); +assign csrbank5_card_detect_r = interface5_bank_bus_dat_w[0]; +always @(*) begin + csrbank5_card_detect_re <= 1'd0; + csrbank5_card_detect_we <= 1'd0; + if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 1'd0))) begin + csrbank5_card_detect_re <= interface5_bank_bus_we; + csrbank5_card_detect_we <= (~interface5_bank_bus_we); + end +end +assign csrbank5_clocker_divider0_r = interface5_bank_bus_dat_w[8:0]; +always @(*) begin + csrbank5_clocker_divider0_re <= 1'd0; + csrbank5_clocker_divider0_we <= 1'd0; + if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 1'd1))) begin + csrbank5_clocker_divider0_re <= interface5_bank_bus_we; + csrbank5_clocker_divider0_we <= (~interface5_bank_bus_we); + end +end +assign init_initialize_r = interface5_bank_bus_dat_w[0]; +always @(*) begin + init_initialize_re <= 1'd0; + init_initialize_we <= 1'd0; + if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 2'd2))) begin + init_initialize_re <= interface5_bank_bus_we; + init_initialize_we <= (~interface5_bank_bus_we); + end +end +assign csrbank5_dataw_status_r = interface5_bank_bus_dat_w[2:0]; +always @(*) begin + csrbank5_dataw_status_re <= 1'd0; + csrbank5_dataw_status_we <= 1'd0; + if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 2'd3))) begin + csrbank5_dataw_status_re <= interface5_bank_bus_we; + csrbank5_dataw_status_we <= (~interface5_bank_bus_we); + end +end +assign csrbank5_card_detect_w = card_detect_status0; +assign card_detect_we = csrbank5_card_detect_we; +assign csrbank5_clocker_divider0_w = clocker_storage[8:0]; +always @(*) begin + dataw_status <= 3'd0; + dataw_status[0] <= dataw_accepted0; + dataw_status[1] <= dataw_crc_error0; + dataw_status[2] <= dataw_write_error0; +end +assign csrbank5_dataw_status_w = dataw_status[2:0]; +assign dataw_we = csrbank5_dataw_status_we; +assign adr = interface1_adr; +assign we = interface1_we; +assign dat_w = interface1_dat_w; +assign interface1_dat_r = dat_r; +assign interface0_bank_bus_adr = adr; +assign interface1_bank_bus_adr = adr; +assign interface2_bank_bus_adr = adr; +assign interface3_bank_bus_adr = adr; +assign interface4_bank_bus_adr = adr; +assign interface5_bank_bus_adr = adr; +assign interface0_bank_bus_we = we; +assign interface1_bank_bus_we = we; +assign interface2_bank_bus_we = we; +assign interface3_bank_bus_we = we; +assign interface4_bank_bus_we = we; +assign interface5_bank_bus_we = we; +assign interface0_bank_bus_dat_w = dat_w; +assign interface1_bank_bus_dat_w = dat_w; +assign interface2_bank_bus_dat_w = dat_w; +assign interface3_bank_bus_dat_w = dat_w; +assign interface4_bank_bus_dat_w = dat_w; +assign interface5_bank_bus_dat_w = dat_w; +assign dat_r = (((((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r) | interface3_bank_bus_dat_r) | interface4_bank_bus_dat_r) | interface5_bank_bus_dat_r); +always @(*) begin + self0 <= 32'd0; + case (grant) + 1'd0: begin + self0 <= interface0_bus_adr; + end + default: begin + self0 <= interface1_bus_adr; + end + endcase +end +always @(*) begin + self1 <= 32'd0; + case (grant) + 1'd0: begin + self1 <= interface0_bus_dat_w; + end + default: begin + self1 <= interface1_bus_dat_w; + end + endcase +end +always @(*) begin + self2 <= 4'd0; + case (grant) + 1'd0: begin + self2 <= interface0_bus_sel; + end + default: begin + self2 <= interface1_bus_sel; + end + endcase +end +always @(*) begin + self3 <= 1'd0; + case (grant) + 1'd0: begin + self3 <= interface0_bus_cyc; + end + default: begin + self3 <= interface1_bus_cyc; + end + endcase +end +always @(*) begin + self4 <= 1'd0; + case (grant) + 1'd0: begin + self4 <= interface0_bus_stb; + end + default: begin + self4 <= interface1_bus_stb; + end + endcase +end +always @(*) begin + self5 <= 1'd0; + case (grant) + 1'd0: begin + self5 <= interface0_bus_we; + end + default: begin + self5 <= interface1_bus_we; + end + endcase +end +always @(*) begin + self6 <= 3'd0; + case (grant) + 1'd0: begin + self6 <= interface0_bus_cti; + end + default: begin + self6 <= interface1_bus_cti; + end + endcase +end +always @(*) begin + self7 <= 2'd0; + case (grant) + 1'd0: begin + self7 <= interface0_bus_bte; + end + default: begin + self7 <= interface1_bus_bte; + end + endcase +end +assign sdrio_clk = sys_clk; +assign sdrio_clk_1 = sys_clk; +assign sdrio_clk_2 = sys_clk; +assign sdrio_clk_3 = sys_clk; +assign sdrio_clk_4 = sys_clk; + + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + +always @(posedge por_clk) begin + int_rst <= rst; +end + +always @(posedge sdrio_clk) begin + inferedsdrtristate0_oe <= sdpads_cmd_oe; + inferedsdrtristate1_oe <= sdpads_data_oe; + inferedsdrtristate2_oe <= sdpads_data_oe; + inferedsdrtristate3_oe <= sdpads_data_oe; + inferedsdrtristate4_oe <= sdpads_data_oe; +end + +always @(posedge sys_clk) begin + if ((bus_errors != 32'd4294967295)) begin + if (bus_error) begin + bus_errors <= (bus_errors + 1'd1); + end + end + case (grant) + 1'd0: begin + if ((~request[0])) begin + if (request[1]) begin + grant <= 1'd1; + end + end + end + 1'd1: begin + if ((~request[1])) begin + if (request[0]) begin + grant <= 1'd0; + end + end + end + endcase + slave_sel_r <= slave_sel; + if (wait_1) begin + if ((~done)) begin + count <= (count - 1'd1); + end + end else begin + count <= 20'd1000000; + end + card_detect_d <= card_detect_status0; + card_detect_irq <= (card_detect_status0 ^ card_detect_d); + if ((~clocker_stop)) begin + clocker_clks <= (clocker_clks + 1'd1); + end + clocker_clk_d <= clocker_clk1; + if (clocker_clk_d) begin + clocker_ce_delayed <= clocker_clk_en; + end + sdphyinit_state <= sdphyinit_next_state; + if (init_count_sdphyinit_next_value_ce) begin + init_count <= init_count_sdphyinit_next_value; + end + sdphycmdw_state <= sdphycmdw_next_state; + if (cmdw_count_sdphycmdw_next_value_ce) begin + cmdw_count <= cmdw_count_sdphycmdw_next_value; + end + if (cmdr_cmdr_pads_in_valid) begin + cmdr_cmdr_run <= (cmdr_cmdr_start | cmdr_cmdr_run); + end + if (cmdr_cmdr_converter_converter_source_ready) begin + cmdr_cmdr_converter_converter_strobe_all <= 1'd0; + end + if (cmdr_cmdr_converter_converter_load_part) begin + if (((cmdr_cmdr_converter_converter_demux == 3'd7) | cmdr_cmdr_converter_converter_sink_last)) begin + cmdr_cmdr_converter_converter_demux <= 1'd0; + cmdr_cmdr_converter_converter_strobe_all <= 1'd1; + end else begin + cmdr_cmdr_converter_converter_demux <= (cmdr_cmdr_converter_converter_demux + 1'd1); + end + end + if ((cmdr_cmdr_converter_converter_source_valid & cmdr_cmdr_converter_converter_source_ready)) begin + if ((cmdr_cmdr_converter_converter_sink_valid & cmdr_cmdr_converter_converter_sink_ready)) begin + cmdr_cmdr_converter_converter_source_first <= cmdr_cmdr_converter_converter_sink_first; + cmdr_cmdr_converter_converter_source_last <= cmdr_cmdr_converter_converter_sink_last; + end else begin + cmdr_cmdr_converter_converter_source_first <= 1'd0; + cmdr_cmdr_converter_converter_source_last <= 1'd0; + end + end else begin + if ((cmdr_cmdr_converter_converter_sink_valid & cmdr_cmdr_converter_converter_sink_ready)) begin + cmdr_cmdr_converter_converter_source_first <= (cmdr_cmdr_converter_converter_sink_first | cmdr_cmdr_converter_converter_source_first); + cmdr_cmdr_converter_converter_source_last <= (cmdr_cmdr_converter_converter_sink_last | cmdr_cmdr_converter_converter_source_last); + end + end + if (cmdr_cmdr_converter_converter_load_part) begin + case (cmdr_cmdr_converter_converter_demux) + 1'd0: begin + cmdr_cmdr_converter_converter_source_payload_data[7] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 1'd1: begin + cmdr_cmdr_converter_converter_source_payload_data[6] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 2'd2: begin + cmdr_cmdr_converter_converter_source_payload_data[5] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 2'd3: begin + cmdr_cmdr_converter_converter_source_payload_data[4] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 3'd4: begin + cmdr_cmdr_converter_converter_source_payload_data[3] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 3'd5: begin + cmdr_cmdr_converter_converter_source_payload_data[2] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 3'd6: begin + cmdr_cmdr_converter_converter_source_payload_data[1] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 3'd7: begin + cmdr_cmdr_converter_converter_source_payload_data[0] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + endcase + end + if (cmdr_cmdr_converter_converter_load_part) begin + cmdr_cmdr_converter_converter_source_payload_valid_token_count <= (cmdr_cmdr_converter_converter_demux + 1'd1); + end + if (((~cmdr_cmdr_buf_pipe_valid_source_valid) | cmdr_cmdr_buf_pipe_valid_source_ready)) begin + cmdr_cmdr_buf_pipe_valid_source_valid <= cmdr_cmdr_buf_pipe_valid_sink_valid; + cmdr_cmdr_buf_pipe_valid_source_first <= cmdr_cmdr_buf_pipe_valid_sink_first; + cmdr_cmdr_buf_pipe_valid_source_last <= cmdr_cmdr_buf_pipe_valid_sink_last; + cmdr_cmdr_buf_pipe_valid_source_payload_data <= cmdr_cmdr_buf_pipe_valid_sink_payload_data; + end + if (cmdr_cmdr_reset) begin + cmdr_cmdr_run <= 1'd0; + cmdr_cmdr_converter_converter_source_payload_data <= 8'd0; + cmdr_cmdr_converter_converter_source_payload_valid_token_count <= 4'd0; + cmdr_cmdr_converter_converter_demux <= 3'd0; + cmdr_cmdr_converter_converter_strobe_all <= 1'd0; + cmdr_cmdr_buf_pipe_valid_source_valid <= 1'd0; + cmdr_cmdr_buf_pipe_valid_source_payload_data <= 8'd0; + end + sdphycmdr_state <= sdphycmdr_next_state; + if (cmdr_timeout_sdphycmdr_next_value_ce0) begin + cmdr_timeout <= cmdr_timeout_sdphycmdr_next_value0; + end + if (cmdr_count_sdphycmdr_next_value_ce1) begin + cmdr_count <= cmdr_count_sdphycmdr_next_value1; + end + if (cmdr_busy_sdphycmdr_next_value_ce2) begin + cmdr_busy <= cmdr_busy_sdphycmdr_next_value2; + end + if (cmdr_cmdr_reset_sdphycmdr_next_value_ce3) begin + cmdr_cmdr_reset <= cmdr_cmdr_reset_sdphycmdr_next_value3; + end + if (dataw_crc_pads_in_valid) begin + dataw_crc_run <= (dataw_crc_start | dataw_crc_run); + end + if (dataw_crc_converter_converter_source_ready) begin + dataw_crc_converter_converter_strobe_all <= 1'd0; + end + if (dataw_crc_converter_converter_load_part) begin + if (((dataw_crc_converter_converter_demux == 3'd7) | dataw_crc_converter_converter_sink_last)) begin + dataw_crc_converter_converter_demux <= 1'd0; + dataw_crc_converter_converter_strobe_all <= 1'd1; + end else begin + dataw_crc_converter_converter_demux <= (dataw_crc_converter_converter_demux + 1'd1); + end + end + if ((dataw_crc_converter_converter_source_valid & dataw_crc_converter_converter_source_ready)) begin + if ((dataw_crc_converter_converter_sink_valid & dataw_crc_converter_converter_sink_ready)) begin + dataw_crc_converter_converter_source_first <= dataw_crc_converter_converter_sink_first; + dataw_crc_converter_converter_source_last <= dataw_crc_converter_converter_sink_last; + end else begin + dataw_crc_converter_converter_source_first <= 1'd0; + dataw_crc_converter_converter_source_last <= 1'd0; + end + end else begin + if ((dataw_crc_converter_converter_sink_valid & dataw_crc_converter_converter_sink_ready)) begin + dataw_crc_converter_converter_source_first <= (dataw_crc_converter_converter_sink_first | dataw_crc_converter_converter_source_first); + dataw_crc_converter_converter_source_last <= (dataw_crc_converter_converter_sink_last | dataw_crc_converter_converter_source_last); + end + end + if (dataw_crc_converter_converter_load_part) begin + case (dataw_crc_converter_converter_demux) + 1'd0: begin + dataw_crc_converter_converter_source_payload_data[7] <= dataw_crc_converter_converter_sink_payload_data; + end + 1'd1: begin + dataw_crc_converter_converter_source_payload_data[6] <= dataw_crc_converter_converter_sink_payload_data; + end + 2'd2: begin + dataw_crc_converter_converter_source_payload_data[5] <= dataw_crc_converter_converter_sink_payload_data; + end + 2'd3: begin + dataw_crc_converter_converter_source_payload_data[4] <= dataw_crc_converter_converter_sink_payload_data; + end + 3'd4: begin + dataw_crc_converter_converter_source_payload_data[3] <= dataw_crc_converter_converter_sink_payload_data; + end + 3'd5: begin + dataw_crc_converter_converter_source_payload_data[2] <= dataw_crc_converter_converter_sink_payload_data; + end + 3'd6: begin + dataw_crc_converter_converter_source_payload_data[1] <= dataw_crc_converter_converter_sink_payload_data; + end + 3'd7: begin + dataw_crc_converter_converter_source_payload_data[0] <= dataw_crc_converter_converter_sink_payload_data; + end + endcase + end + if (dataw_crc_converter_converter_load_part) begin + dataw_crc_converter_converter_source_payload_valid_token_count <= (dataw_crc_converter_converter_demux + 1'd1); + end + if (((~dataw_crc_buf_pipe_valid_source_valid) | dataw_crc_buf_pipe_valid_source_ready)) begin + dataw_crc_buf_pipe_valid_source_valid <= dataw_crc_buf_pipe_valid_sink_valid; + dataw_crc_buf_pipe_valid_source_first <= dataw_crc_buf_pipe_valid_sink_first; + dataw_crc_buf_pipe_valid_source_last <= dataw_crc_buf_pipe_valid_sink_last; + dataw_crc_buf_pipe_valid_source_payload_data <= dataw_crc_buf_pipe_valid_sink_payload_data; + end + if (dataw_crc_reset) begin + dataw_crc_run <= 1'd0; + dataw_crc_converter_converter_source_payload_data <= 8'd0; + dataw_crc_converter_converter_source_payload_valid_token_count <= 4'd0; + dataw_crc_converter_converter_demux <= 3'd0; + dataw_crc_converter_converter_strobe_all <= 1'd0; + dataw_crc_buf_pipe_valid_source_valid <= 1'd0; + dataw_crc_buf_pipe_valid_source_payload_data <= 8'd0; + end + sdphydataw_state <= sdphydataw_next_state; + if (dataw_accepted1_sdphydataw_next_value_ce0) begin + dataw_accepted1 <= dataw_accepted1_sdphydataw_next_value0; + end + if (dataw_crc_error1_sdphydataw_next_value_ce1) begin + dataw_crc_error1 <= dataw_crc_error1_sdphydataw_next_value1; + end + if (dataw_write_error1_sdphydataw_next_value_ce2) begin + dataw_write_error1 <= dataw_write_error1_sdphydataw_next_value2; + end + if (dataw_count_sdphydataw_next_value_ce3) begin + dataw_count <= dataw_count_sdphydataw_next_value3; + end + if (datar_datar_pads_in_valid) begin + datar_datar_run <= (datar_datar_start | datar_datar_run); + end + if (datar_datar_converter_converter_source_ready) begin + datar_datar_converter_converter_strobe_all <= 1'd0; + end + if (datar_datar_converter_converter_load_part) begin + if (((datar_datar_converter_converter_demux == 1'd1) | datar_datar_converter_converter_sink_last)) begin + datar_datar_converter_converter_demux <= 1'd0; + datar_datar_converter_converter_strobe_all <= 1'd1; + end else begin + datar_datar_converter_converter_demux <= (datar_datar_converter_converter_demux + 1'd1); + end + end + if ((datar_datar_converter_converter_source_valid & datar_datar_converter_converter_source_ready)) begin + if ((datar_datar_converter_converter_sink_valid & datar_datar_converter_converter_sink_ready)) begin + datar_datar_converter_converter_source_first <= datar_datar_converter_converter_sink_first; + datar_datar_converter_converter_source_last <= datar_datar_converter_converter_sink_last; + end else begin + datar_datar_converter_converter_source_first <= 1'd0; + datar_datar_converter_converter_source_last <= 1'd0; + end + end else begin + if ((datar_datar_converter_converter_sink_valid & datar_datar_converter_converter_sink_ready)) begin + datar_datar_converter_converter_source_first <= (datar_datar_converter_converter_sink_first | datar_datar_converter_converter_source_first); + datar_datar_converter_converter_source_last <= (datar_datar_converter_converter_sink_last | datar_datar_converter_converter_source_last); + end + end + if (datar_datar_converter_converter_load_part) begin + case (datar_datar_converter_converter_demux) + 1'd0: begin + datar_datar_converter_converter_source_payload_data[7:4] <= datar_datar_converter_converter_sink_payload_data; + end + 1'd1: begin + datar_datar_converter_converter_source_payload_data[3:0] <= datar_datar_converter_converter_sink_payload_data; + end + endcase + end + if (datar_datar_converter_converter_load_part) begin + datar_datar_converter_converter_source_payload_valid_token_count <= (datar_datar_converter_converter_demux + 1'd1); + end + if (((~datar_datar_buf_pipe_valid_source_valid) | datar_datar_buf_pipe_valid_source_ready)) begin + datar_datar_buf_pipe_valid_source_valid <= datar_datar_buf_pipe_valid_sink_valid; + datar_datar_buf_pipe_valid_source_first <= datar_datar_buf_pipe_valid_sink_first; + datar_datar_buf_pipe_valid_source_last <= datar_datar_buf_pipe_valid_sink_last; + datar_datar_buf_pipe_valid_source_payload_data <= datar_datar_buf_pipe_valid_sink_payload_data; + end + if (datar_datar_reset) begin + datar_datar_run <= 1'd0; + datar_datar_converter_converter_source_payload_data <= 8'd0; + datar_datar_converter_converter_source_payload_valid_token_count <= 2'd0; + datar_datar_converter_converter_demux <= 1'd0; + datar_datar_converter_converter_strobe_all <= 1'd0; + datar_datar_buf_pipe_valid_source_valid <= 1'd0; + datar_datar_buf_pipe_valid_source_payload_data <= 8'd0; + end + sdphydatar_state <= sdphydatar_next_state; + if (datar_count_sdphydatar_next_value_ce0) begin + datar_count <= datar_count_sdphydatar_next_value0; + end + if (datar_timeout_sdphydatar_next_value_ce1) begin + datar_timeout <= datar_timeout_sdphydatar_next_value1; + end + if (datar_datar_reset_sdphydatar_next_value_ce2) begin + datar_datar_reset <= datar_datar_reset_sdphydatar_next_value2; + end + clocker_clk_delay <= {clocker_clk_delay, clocker_clk0}; + sdpads_data_i_ce <= (clocker_clk_delay[1] & (~clocker_clk_delay[0])); + sdcard_core_done_d <= sdcard_core_cmd_done; + sdcard_core_irq <= (sdcard_core_cmd_done & (~sdcard_core_done_d)); + if (sdcard_core_crc7_inserter_crc_reset) begin + sdcard_core_crc7_inserter_crc0 <= 1'd0; + end else begin + if (sdcard_core_crc7_inserter_crc_enable) begin + sdcard_core_crc7_inserter_crc0 <= sdcard_core_crc7_inserter_crc40; + end + end + if (sdcard_core_crc16_inserter_crc0_reset) begin + sdcard_core_crc16_inserter_crc00 <= 1'd0; + end else begin + if (sdcard_core_crc16_inserter_crc0_enable) begin + sdcard_core_crc16_inserter_crc00 <= sdcard_core_crc16_inserter_crc02; + end + end + if (sdcard_core_crc16_inserter_crc1_reset) begin + sdcard_core_crc16_inserter_crc10 <= 1'd0; + end else begin + if (sdcard_core_crc16_inserter_crc1_enable) begin + sdcard_core_crc16_inserter_crc10 <= sdcard_core_crc16_inserter_crc12; + end + end + if (sdcard_core_crc16_inserter_crc2_reset) begin + sdcard_core_crc16_inserter_crc20 <= 1'd0; + end else begin + if (sdcard_core_crc16_inserter_crc2_enable) begin + sdcard_core_crc16_inserter_crc20 <= sdcard_core_crc16_inserter_crc22; + end + end + if (sdcard_core_crc16_inserter_crc3_reset) begin + sdcard_core_crc16_inserter_crc30 <= 1'd0; + end else begin + if (sdcard_core_crc16_inserter_crc3_enable) begin + sdcard_core_crc16_inserter_crc30 <= sdcard_core_crc16_inserter_crc32; + end + end + crc16inserter_state <= crc16inserter_next_state; + if (sdcard_core_crc16_inserter_count_crc16inserter_next_value_ce) begin + sdcard_core_crc16_inserter_count <= sdcard_core_crc16_inserter_count_crc16inserter_next_value; + end + if (((sdcard_core_fifo_syncfifo_we & sdcard_core_fifo_syncfifo_writable) & (~sdcard_core_fifo_replace))) begin + sdcard_core_fifo_produce <= (sdcard_core_fifo_produce + 1'd1); + end + if (sdcard_core_fifo_do_read) begin + sdcard_core_fifo_consume <= (sdcard_core_fifo_consume + 1'd1); + end + if (((sdcard_core_fifo_syncfifo_we & sdcard_core_fifo_syncfifo_writable) & (~sdcard_core_fifo_replace))) begin + if ((~sdcard_core_fifo_do_read)) begin + sdcard_core_fifo_level <= (sdcard_core_fifo_level + 1'd1); + end + end else begin + if (sdcard_core_fifo_do_read) begin + sdcard_core_fifo_level <= (sdcard_core_fifo_level - 1'd1); + end + end + if (sdcard_core_fifo_reset) begin + sdcard_core_fifo_level <= 4'd0; + sdcard_core_fifo_produce <= 3'd0; + sdcard_core_fifo_consume <= 3'd0; + end + fsm_state <= fsm_next_state; + if (sdcard_core_cmd_done_fsm_next_value_ce0) begin + sdcard_core_cmd_done <= sdcard_core_cmd_done_fsm_next_value0; + end + if (sdcard_core_data_done_fsm_next_value_ce1) begin + sdcard_core_data_done <= sdcard_core_data_done_fsm_next_value1; + end + if (sdcard_core_cmd_count_fsm_next_value_ce2) begin + sdcard_core_cmd_count <= sdcard_core_cmd_count_fsm_next_value2; + end + if (sdcard_core_data_count_fsm_next_value_ce3) begin + sdcard_core_data_count <= sdcard_core_data_count_fsm_next_value3; + end + if (sdcard_core_cmd_error_fsm_next_value_ce4) begin + sdcard_core_cmd_error <= sdcard_core_cmd_error_fsm_next_value4; + end + if (sdcard_core_cmd_timeout_fsm_next_value_ce5) begin + sdcard_core_cmd_timeout <= sdcard_core_cmd_timeout_fsm_next_value5; + end + if (sdcard_core_data_error_fsm_next_value_ce6) begin + sdcard_core_data_error <= sdcard_core_data_error_fsm_next_value6; + end + if (sdcard_core_data_timeout_fsm_next_value_ce7) begin + sdcard_core_data_timeout <= sdcard_core_data_timeout_fsm_next_value7; + end + if (sdcard_core_cmd_response_status_fsm_next_value_ce8) begin + sdcard_core_cmd_response_status <= sdcard_core_cmd_response_status_fsm_next_value8; + end + if ((~sdcard_block2mem_wishbonedmawriter_enable_storage)) begin + sdcard_block2mem_connect <= 1'd0; + end else begin + if (sdcard_block2mem_start) begin + sdcard_block2mem_connect <= 1'd1; + end + end + sdcard_block2mem_done_d <= sdcard_block2mem_wishbonedmawriter_done_status; + sdcard_block2mem_irq <= (sdcard_block2mem_wishbonedmawriter_done_status & (~sdcard_block2mem_done_d)); + if (sdcard_block2mem_fifo_syncfifo_re) begin + sdcard_block2mem_fifo_readable <= 1'd1; + end else begin + if (sdcard_block2mem_fifo_re) begin + sdcard_block2mem_fifo_readable <= 1'd0; + end + end + if (((sdcard_block2mem_fifo_syncfifo_we & sdcard_block2mem_fifo_syncfifo_writable) & (~sdcard_block2mem_fifo_replace))) begin + sdcard_block2mem_fifo_produce <= (sdcard_block2mem_fifo_produce + 1'd1); + end + if (sdcard_block2mem_fifo_do_read) begin + sdcard_block2mem_fifo_consume <= (sdcard_block2mem_fifo_consume + 1'd1); + end + if (((sdcard_block2mem_fifo_syncfifo_we & sdcard_block2mem_fifo_syncfifo_writable) & (~sdcard_block2mem_fifo_replace))) begin + if ((~sdcard_block2mem_fifo_do_read)) begin + sdcard_block2mem_fifo_level0 <= (sdcard_block2mem_fifo_level0 + 1'd1); + end + end else begin + if (sdcard_block2mem_fifo_do_read) begin + sdcard_block2mem_fifo_level0 <= (sdcard_block2mem_fifo_level0 - 1'd1); + end + end + if (sdcard_block2mem_converter_source_ready) begin + sdcard_block2mem_converter_strobe_all <= 1'd0; + end + if (sdcard_block2mem_converter_load_part) begin + if (((sdcard_block2mem_converter_demux == 2'd3) | sdcard_block2mem_converter_sink_last)) begin + sdcard_block2mem_converter_demux <= 1'd0; + sdcard_block2mem_converter_strobe_all <= 1'd1; + end else begin + sdcard_block2mem_converter_demux <= (sdcard_block2mem_converter_demux + 1'd1); + end + end + if ((sdcard_block2mem_converter_source_valid & sdcard_block2mem_converter_source_ready)) begin + if ((sdcard_block2mem_converter_sink_valid & sdcard_block2mem_converter_sink_ready)) begin + sdcard_block2mem_converter_source_first <= sdcard_block2mem_converter_sink_first; + sdcard_block2mem_converter_source_last <= sdcard_block2mem_converter_sink_last; + end else begin + sdcard_block2mem_converter_source_first <= 1'd0; + sdcard_block2mem_converter_source_last <= 1'd0; + end + end else begin + if ((sdcard_block2mem_converter_sink_valid & sdcard_block2mem_converter_sink_ready)) begin + sdcard_block2mem_converter_source_first <= (sdcard_block2mem_converter_sink_first | sdcard_block2mem_converter_source_first); + sdcard_block2mem_converter_source_last <= (sdcard_block2mem_converter_sink_last | sdcard_block2mem_converter_source_last); + end + end + if (sdcard_block2mem_converter_load_part) begin + case (sdcard_block2mem_converter_demux) + 1'd0: begin + sdcard_block2mem_converter_source_payload_data[31:24] <= sdcard_block2mem_converter_sink_payload_data; + end + 1'd1: begin + sdcard_block2mem_converter_source_payload_data[23:16] <= sdcard_block2mem_converter_sink_payload_data; + end + 2'd2: begin + sdcard_block2mem_converter_source_payload_data[15:8] <= sdcard_block2mem_converter_sink_payload_data; + end + 2'd3: begin + sdcard_block2mem_converter_source_payload_data[7:0] <= sdcard_block2mem_converter_sink_payload_data; + end + endcase + end + if (sdcard_block2mem_converter_load_part) begin + sdcard_block2mem_converter_source_payload_valid_token_count <= (sdcard_block2mem_converter_demux + 1'd1); + end + sdblock2memdma_state <= sdblock2memdma_next_state; + if (sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce) begin + sdcard_block2mem_wishbonedmawriter_offset <= sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value; + end + if (sdcard_block2mem_wishbonedmawriter_reset) begin + sdcard_block2mem_wishbonedmawriter_offset <= 32'd0; + sdblock2memdma_state <= 2'd0; + end + if ((sdcard_mem2block_source_source_valid & sdcard_mem2block_source_source_ready)) begin + sdcard_mem2block_count <= (sdcard_mem2block_count + 1'd1); + if (sdcard_mem2block_source_source_last) begin + sdcard_mem2block_count <= 1'd0; + end + end + sdcard_mem2block_done_d <= sdcard_mem2block_dma_done_status; + sdcard_mem2block_irq <= (sdcard_mem2block_dma_done_status & (~sdcard_mem2block_done_d)); + if (((sdcard_mem2block_dma_fifo_syncfifo_we & sdcard_mem2block_dma_fifo_syncfifo_writable) & (~sdcard_mem2block_dma_fifo_replace))) begin + sdcard_mem2block_dma_fifo_produce <= (sdcard_mem2block_dma_fifo_produce + 1'd1); + end + if (sdcard_mem2block_dma_fifo_do_read) begin + sdcard_mem2block_dma_fifo_consume <= (sdcard_mem2block_dma_fifo_consume + 1'd1); + end + if (((sdcard_mem2block_dma_fifo_syncfifo_we & sdcard_mem2block_dma_fifo_syncfifo_writable) & (~sdcard_mem2block_dma_fifo_replace))) begin + if ((~sdcard_mem2block_dma_fifo_do_read)) begin + sdcard_mem2block_dma_fifo_level <= (sdcard_mem2block_dma_fifo_level + 1'd1); + end + end else begin + if (sdcard_mem2block_dma_fifo_do_read) begin + sdcard_mem2block_dma_fifo_level <= (sdcard_mem2block_dma_fifo_level - 1'd1); + end + end + sdmem2blockdma_state <= sdmem2blockdma_next_state; + if (sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce) begin + sdcard_mem2block_dma_offset <= sdcard_mem2block_dma_offset_sdmem2blockdma_next_value; + end + if (sdcard_mem2block_dma_reset) begin + sdcard_mem2block_dma_offset <= 32'd0; + sdmem2blockdma_state <= 2'd0; + end + if ((sdcard_mem2block_converter_converter_source_valid & sdcard_mem2block_converter_converter_source_ready)) begin + if (sdcard_mem2block_converter_converter_last) begin + sdcard_mem2block_converter_converter_mux <= 1'd0; + end else begin + sdcard_mem2block_converter_converter_mux <= (sdcard_mem2block_converter_converter_mux + 1'd1); + end + end + if (sdcard_mem2block_fifo_syncfifo_re) begin + sdcard_mem2block_fifo_readable <= 1'd1; + end else begin + if (sdcard_mem2block_fifo_re) begin + sdcard_mem2block_fifo_readable <= 1'd0; + end + end + if (((sdcard_mem2block_fifo_syncfifo_we & sdcard_mem2block_fifo_syncfifo_writable) & (~sdcard_mem2block_fifo_replace))) begin + sdcard_mem2block_fifo_produce <= (sdcard_mem2block_fifo_produce + 1'd1); + end + if (sdcard_mem2block_fifo_do_read) begin + sdcard_mem2block_fifo_consume <= (sdcard_mem2block_fifo_consume + 1'd1); + end + if (((sdcard_mem2block_fifo_syncfifo_we & sdcard_mem2block_fifo_syncfifo_writable) & (~sdcard_mem2block_fifo_replace))) begin + if ((~sdcard_mem2block_fifo_do_read)) begin + sdcard_mem2block_fifo_level0 <= (sdcard_mem2block_fifo_level0 + 1'd1); + end + end else begin + if (sdcard_mem2block_fifo_do_read) begin + sdcard_mem2block_fifo_level0 <= (sdcard_mem2block_fifo_level0 - 1'd1); + end + end + if (card_detect_clear) begin + card_detect_pending <= 1'd0; + end + if (card_detect_trigger) begin + card_detect_pending <= 1'd1; + end + if (block2mem_dma_clear) begin + block2mem_dma_pending <= 1'd0; + end + if (block2mem_dma_trigger) begin + block2mem_dma_pending <= 1'd1; + end + if (mem2block_dma_clear) begin + mem2block_dma_pending <= 1'd0; + end + if (mem2block_dma_trigger) begin + mem2block_dma_pending <= 1'd1; + end + wishbone2csr_state <= wishbone2csr_next_state; + interface0_bank_bus_dat_r <= 1'd0; + if (csrbank0_sel) begin + case (interface0_bank_bus_adr[8:0]) + 1'd0: begin + interface0_bank_bus_dat_r <= csrbank0_reset0_w; + end + 1'd1: begin + interface0_bank_bus_dat_r <= csrbank0_scratch0_w; + end + 2'd2: begin + interface0_bank_bus_dat_r <= csrbank0_bus_errors_w; + end + endcase + end + if (csrbank0_reset0_re) begin + reset_storage[1:0] <= csrbank0_reset0_r; + end + reset_re <= csrbank0_reset0_re; + if (csrbank0_scratch0_re) begin + scratch_storage[31:0] <= csrbank0_scratch0_r; + end + scratch_re <= csrbank0_scratch0_re; + bus_errors_re <= csrbank0_bus_errors_re; + interface1_bank_bus_dat_r <= 1'd0; + if (csrbank1_sel) begin + case (interface1_bank_bus_adr[8:0]) + 1'd0: begin + interface1_bank_bus_dat_r <= csrbank1_dma_base1_w; + end + 1'd1: begin + interface1_bank_bus_dat_r <= csrbank1_dma_base0_w; + end + 2'd2: begin + interface1_bank_bus_dat_r <= csrbank1_dma_length0_w; + end + 2'd3: begin + interface1_bank_bus_dat_r <= csrbank1_dma_enable0_w; + end + 3'd4: begin + interface1_bank_bus_dat_r <= csrbank1_dma_done_w; + end + 3'd5: begin + interface1_bank_bus_dat_r <= csrbank1_dma_loop0_w; + end + 3'd6: begin + interface1_bank_bus_dat_r <= csrbank1_dma_offset_w; + end + endcase + end + if (csrbank1_dma_base1_re) begin + sdcard_block2mem_wishbonedmawriter_base_storage[63:32] <= csrbank1_dma_base1_r; + end + if (csrbank1_dma_base0_re) begin + sdcard_block2mem_wishbonedmawriter_base_storage[31:0] <= csrbank1_dma_base0_r; + end + sdcard_block2mem_wishbonedmawriter_base_re <= csrbank1_dma_base0_re; + if (csrbank1_dma_length0_re) begin + sdcard_block2mem_wishbonedmawriter_length_storage[31:0] <= csrbank1_dma_length0_r; + end + sdcard_block2mem_wishbonedmawriter_length_re <= csrbank1_dma_length0_re; + if (csrbank1_dma_enable0_re) begin + sdcard_block2mem_wishbonedmawriter_enable_storage <= csrbank1_dma_enable0_r; + end + sdcard_block2mem_wishbonedmawriter_enable_re <= csrbank1_dma_enable0_re; + sdcard_block2mem_wishbonedmawriter_done_re <= csrbank1_dma_done_re; + if (csrbank1_dma_loop0_re) begin + sdcard_block2mem_wishbonedmawriter_loop_storage <= csrbank1_dma_loop0_r; + end + sdcard_block2mem_wishbonedmawriter_loop_re <= csrbank1_dma_loop0_re; + sdcard_block2mem_wishbonedmawriter_offset_re <= csrbank1_dma_offset_re; + interface2_bank_bus_dat_r <= 1'd0; + if (csrbank2_sel) begin + case (interface2_bank_bus_adr[8:0]) + 1'd0: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_argument0_w; + end + 1'd1: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_command0_w; + end + 2'd2: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_send0_w; + end + 2'd3: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_response3_w; + end + 3'd4: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_response2_w; + end + 3'd5: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_response1_w; + end + 3'd6: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_response0_w; + end + 3'd7: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_event_w; + end + 4'd8: begin + interface2_bank_bus_dat_r <= csrbank2_data_event_w; + end + 4'd9: begin + interface2_bank_bus_dat_r <= csrbank2_block_length0_w; + end + 4'd10: begin + interface2_bank_bus_dat_r <= csrbank2_block_count0_w; + end + endcase + end + if (csrbank2_cmd_argument0_re) begin + sdcard_core_cmd_argument_storage[31:0] <= csrbank2_cmd_argument0_r; + end + sdcard_core_cmd_argument_re <= csrbank2_cmd_argument0_re; + if (csrbank2_cmd_command0_re) begin + sdcard_core_cmd_command_storage[13:0] <= csrbank2_cmd_command0_r; + end + sdcard_core_cmd_command_re <= csrbank2_cmd_command0_re; + if (csrbank2_cmd_send0_re) begin + sdcard_core_cmd_send_storage <= csrbank2_cmd_send0_r; + end + sdcard_core_cmd_send_re <= csrbank2_cmd_send0_re; + sdcard_core_cmd_response_re <= csrbank2_cmd_response0_re; + sdcard_core_cmd_event_re <= csrbank2_cmd_event_re; + sdcard_core_data_event_re <= csrbank2_data_event_re; + if (csrbank2_block_length0_re) begin + sdcard_core_block_length_storage[9:0] <= csrbank2_block_length0_r; + end + sdcard_core_block_length_re <= csrbank2_block_length0_re; + if (csrbank2_block_count0_re) begin + sdcard_core_block_count_storage[31:0] <= csrbank2_block_count0_r; + end + sdcard_core_block_count_re <= csrbank2_block_count0_re; + interface3_bank_bus_dat_r <= 1'd0; + if (csrbank3_sel) begin + case (interface3_bank_bus_adr[8:0]) + 1'd0: begin + interface3_bank_bus_dat_r <= csrbank3_status_w; + end + 1'd1: begin + interface3_bank_bus_dat_r <= csrbank3_pending_w; + end + 2'd2: begin + interface3_bank_bus_dat_r <= csrbank3_enable0_w; + end + endcase + end + eventmanager_status_re <= csrbank3_status_re; + if (csrbank3_pending_re) begin + eventmanager_pending_r[3:0] <= csrbank3_pending_r; + end + eventmanager_pending_re <= csrbank3_pending_re; + if (csrbank3_enable0_re) begin + eventmanager_enable_storage[3:0] <= csrbank3_enable0_r; + end + eventmanager_enable_re <= csrbank3_enable0_re; + interface4_bank_bus_dat_r <= 1'd0; + if (csrbank4_sel) begin + case (interface4_bank_bus_adr[8:0]) + 1'd0: begin + interface4_bank_bus_dat_r <= csrbank4_dma_base1_w; + end + 1'd1: begin + interface4_bank_bus_dat_r <= csrbank4_dma_base0_w; + end + 2'd2: begin + interface4_bank_bus_dat_r <= csrbank4_dma_length0_w; + end + 2'd3: begin + interface4_bank_bus_dat_r <= csrbank4_dma_enable0_w; + end + 3'd4: begin + interface4_bank_bus_dat_r <= csrbank4_dma_done_w; + end + 3'd5: begin + interface4_bank_bus_dat_r <= csrbank4_dma_loop0_w; + end + 3'd6: begin + interface4_bank_bus_dat_r <= csrbank4_dma_offset_w; + end + endcase + end + if (csrbank4_dma_base1_re) begin + sdcard_mem2block_dma_base_storage[63:32] <= csrbank4_dma_base1_r; + end + if (csrbank4_dma_base0_re) begin + sdcard_mem2block_dma_base_storage[31:0] <= csrbank4_dma_base0_r; + end + sdcard_mem2block_dma_base_re <= csrbank4_dma_base0_re; + if (csrbank4_dma_length0_re) begin + sdcard_mem2block_dma_length_storage[31:0] <= csrbank4_dma_length0_r; + end + sdcard_mem2block_dma_length_re <= csrbank4_dma_length0_re; + if (csrbank4_dma_enable0_re) begin + sdcard_mem2block_dma_enable_storage <= csrbank4_dma_enable0_r; + end + sdcard_mem2block_dma_enable_re <= csrbank4_dma_enable0_re; + sdcard_mem2block_dma_done_re <= csrbank4_dma_done_re; + if (csrbank4_dma_loop0_re) begin + sdcard_mem2block_dma_loop_storage <= csrbank4_dma_loop0_r; + end + sdcard_mem2block_dma_loop_re <= csrbank4_dma_loop0_re; + sdcard_mem2block_dma_offset_re <= csrbank4_dma_offset_re; + interface5_bank_bus_dat_r <= 1'd0; + if (csrbank5_sel) begin + case (interface5_bank_bus_adr[8:0]) + 1'd0: begin + interface5_bank_bus_dat_r <= csrbank5_card_detect_w; + end + 1'd1: begin + interface5_bank_bus_dat_r <= csrbank5_clocker_divider0_w; + end + 2'd2: begin + interface5_bank_bus_dat_r <= init_initialize_w; + end + 2'd3: begin + interface5_bank_bus_dat_r <= csrbank5_dataw_status_w; + end + endcase + end + card_detect_re <= csrbank5_card_detect_re; + if (csrbank5_clocker_divider0_re) begin + clocker_storage[8:0] <= csrbank5_clocker_divider0_r; + end + clocker_re <= csrbank5_clocker_divider0_re; + dataw_re <= csrbank5_dataw_status_re; + if (sys_rst) begin + reset_storage <= 2'd0; + reset_re <= 1'd0; + scratch_storage <= 32'd305419896; + scratch_re <= 1'd0; + bus_errors_re <= 1'd0; + bus_errors <= 32'd0; + card_detect_re <= 1'd0; + clocker_storage <= 9'd256; + clocker_re <= 1'd0; + clocker_clks <= 9'd0; + clocker_clk_d <= 1'd0; + clocker_ce_delayed <= 1'd0; + init_count <= 8'd0; + cmdw_count <= 8'd0; + cmdr_timeout <= 32'd50000000; + cmdr_count <= 8'd0; + cmdr_busy <= 1'd0; + cmdr_cmdr_run <= 1'd0; + cmdr_cmdr_converter_converter_source_payload_data <= 8'd0; + cmdr_cmdr_converter_converter_source_payload_valid_token_count <= 4'd0; + cmdr_cmdr_converter_converter_demux <= 3'd0; + cmdr_cmdr_converter_converter_strobe_all <= 1'd0; + cmdr_cmdr_buf_pipe_valid_source_valid <= 1'd0; + cmdr_cmdr_buf_pipe_valid_source_payload_data <= 8'd0; + cmdr_cmdr_reset <= 1'd0; + dataw_re <= 1'd0; + dataw_count <= 8'd0; + dataw_accepted1 <= 1'd0; + dataw_crc_error1 <= 1'd0; + dataw_write_error1 <= 1'd0; + dataw_crc_run <= 1'd0; + dataw_crc_converter_converter_source_payload_data <= 8'd0; + dataw_crc_converter_converter_source_payload_valid_token_count <= 4'd0; + dataw_crc_converter_converter_demux <= 3'd0; + dataw_crc_converter_converter_strobe_all <= 1'd0; + dataw_crc_buf_pipe_valid_source_valid <= 1'd0; + dataw_crc_buf_pipe_valid_source_payload_data <= 8'd0; + datar_timeout <= 32'd50000000; + datar_count <= 10'd0; + datar_datar_run <= 1'd0; + datar_datar_converter_converter_source_payload_data <= 8'd0; + datar_datar_converter_converter_source_payload_valid_token_count <= 2'd0; + datar_datar_converter_converter_demux <= 1'd0; + datar_datar_converter_converter_strobe_all <= 1'd0; + datar_datar_buf_pipe_valid_source_valid <= 1'd0; + datar_datar_buf_pipe_valid_source_payload_data <= 8'd0; + datar_datar_reset <= 1'd0; + sdpads_data_i_ce <= 1'd0; + clocker_clk_delay <= 2'd0; + card_detect_irq <= 1'd0; + card_detect_d <= 1'd0; + sdcard_core_irq <= 1'd0; + sdcard_core_cmd_argument_storage <= 32'd0; + sdcard_core_cmd_argument_re <= 1'd0; + sdcard_core_cmd_command_storage <= 14'd0; + sdcard_core_cmd_command_re <= 1'd0; + sdcard_core_cmd_send_storage <= 1'd0; + sdcard_core_cmd_send_re <= 1'd0; + sdcard_core_cmd_response_status <= 128'd0; + sdcard_core_cmd_response_re <= 1'd0; + sdcard_core_cmd_event_re <= 1'd0; + sdcard_core_data_event_re <= 1'd0; + sdcard_core_block_length_storage <= 10'd0; + sdcard_core_block_length_re <= 1'd0; + sdcard_core_block_count_storage <= 32'd0; + sdcard_core_block_count_re <= 1'd0; + sdcard_core_crc7_inserter_crc0 <= 7'd0; + sdcard_core_crc16_inserter_count <= 3'd0; + sdcard_core_crc16_inserter_crc00 <= 16'd0; + sdcard_core_crc16_inserter_crc10 <= 16'd0; + sdcard_core_crc16_inserter_crc20 <= 16'd0; + sdcard_core_crc16_inserter_crc30 <= 16'd0; + sdcard_core_fifo_level <= 4'd0; + sdcard_core_fifo_produce <= 3'd0; + sdcard_core_fifo_consume <= 3'd0; + sdcard_core_cmd_count <= 3'd0; + sdcard_core_cmd_done <= 1'd0; + sdcard_core_cmd_error <= 1'd0; + sdcard_core_cmd_timeout <= 1'd0; + sdcard_core_data_count <= 32'd0; + sdcard_core_data_done <= 1'd0; + sdcard_core_data_error <= 1'd0; + sdcard_core_data_timeout <= 1'd0; + sdcard_core_done_d <= 1'd0; + sdcard_block2mem_irq <= 1'd0; + sdcard_block2mem_fifo_readable <= 1'd0; + sdcard_block2mem_fifo_level0 <= 10'd0; + sdcard_block2mem_fifo_produce <= 9'd0; + sdcard_block2mem_fifo_consume <= 9'd0; + sdcard_block2mem_converter_source_payload_data <= 32'd0; + sdcard_block2mem_converter_source_payload_valid_token_count <= 3'd0; + sdcard_block2mem_converter_demux <= 2'd0; + sdcard_block2mem_converter_strobe_all <= 1'd0; + sdcard_block2mem_wishbonedmawriter_base_storage <= 64'd0; + sdcard_block2mem_wishbonedmawriter_base_re <= 1'd0; + sdcard_block2mem_wishbonedmawriter_length_storage <= 32'd0; + sdcard_block2mem_wishbonedmawriter_length_re <= 1'd0; + sdcard_block2mem_wishbonedmawriter_enable_storage <= 1'd0; + sdcard_block2mem_wishbonedmawriter_enable_re <= 1'd0; + sdcard_block2mem_wishbonedmawriter_done_re <= 1'd0; + sdcard_block2mem_wishbonedmawriter_loop_storage <= 1'd0; + sdcard_block2mem_wishbonedmawriter_loop_re <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset_re <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset <= 32'd0; + sdcard_block2mem_connect <= 1'd0; + sdcard_block2mem_done_d <= 1'd0; + sdcard_mem2block_irq <= 1'd0; + sdcard_mem2block_dma_fifo_level <= 5'd0; + sdcard_mem2block_dma_fifo_produce <= 4'd0; + sdcard_mem2block_dma_fifo_consume <= 4'd0; + sdcard_mem2block_dma_base_storage <= 64'd0; + sdcard_mem2block_dma_base_re <= 1'd0; + sdcard_mem2block_dma_length_storage <= 32'd0; + sdcard_mem2block_dma_length_re <= 1'd0; + sdcard_mem2block_dma_enable_storage <= 1'd0; + sdcard_mem2block_dma_enable_re <= 1'd0; + sdcard_mem2block_dma_done_re <= 1'd0; + sdcard_mem2block_dma_loop_storage <= 1'd0; + sdcard_mem2block_dma_loop_re <= 1'd0; + sdcard_mem2block_dma_offset_re <= 1'd0; + sdcard_mem2block_dma_offset <= 32'd0; + sdcard_mem2block_converter_converter_mux <= 2'd0; + sdcard_mem2block_fifo_readable <= 1'd0; + sdcard_mem2block_fifo_level0 <= 10'd0; + sdcard_mem2block_fifo_produce <= 9'd0; + sdcard_mem2block_fifo_consume <= 9'd0; + sdcard_mem2block_count <= 9'd0; + sdcard_mem2block_done_d <= 1'd0; + card_detect_pending <= 1'd0; + block2mem_dma_pending <= 1'd0; + mem2block_dma_pending <= 1'd0; + eventmanager_status_re <= 1'd0; + eventmanager_pending_re <= 1'd0; + eventmanager_pending_r <= 4'd0; + eventmanager_enable_storage <= 4'd0; + eventmanager_enable_re <= 1'd0; + grant <= 1'd0; + slave_sel_r <= 1'd0; + count <= 20'd1000000; + sdphyinit_state <= 1'd0; + sdphycmdw_state <= 2'd0; + sdphycmdr_state <= 3'd0; + sdphydataw_state <= 3'd0; + sdphydatar_state <= 3'd0; + crc16inserter_state <= 1'd0; + fsm_state <= 3'd0; + sdblock2memdma_state <= 2'd0; + sdmem2blockdma_state <= 2'd0; + wishbone2csr_state <= 1'd0; + end +end + + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Memory storage: 8-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Async | Write: ---- | +reg [9:0] storage[0:7]; +reg [9:0] storage_dat0; +always @(posedge sys_clk) begin + if (sdcard_core_fifo_wrport_we) + storage[sdcard_core_fifo_wrport_adr] <= sdcard_core_fifo_wrport_dat_w; + storage_dat0 <= storage[sdcard_core_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign sdcard_core_fifo_wrport_dat_r = storage_dat0; +assign sdcard_core_fifo_rdport_dat_r = storage[sdcard_core_fifo_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_1: 512-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Sync | Write: ---- | +reg [9:0] storage_1[0:511]; +reg [9:0] storage_1_dat0; +reg [9:0] storage_1_dat1; +always @(posedge sys_clk) begin + if (sdcard_block2mem_fifo_wrport_we) + storage_1[sdcard_block2mem_fifo_wrport_adr] <= sdcard_block2mem_fifo_wrport_dat_w; + storage_1_dat0 <= storage_1[sdcard_block2mem_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin + if (sdcard_block2mem_fifo_rdport_re) + storage_1_dat1 <= storage_1[sdcard_block2mem_fifo_rdport_adr]; +end +assign sdcard_block2mem_fifo_wrport_dat_r = storage_1_dat0; +assign sdcard_block2mem_fifo_rdport_dat_r = storage_1_dat1; + + +//------------------------------------------------------------------------------ +// Memory storage_2: 16-words x 34-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 34 +// Port 1 | Read: Async | Write: ---- | +reg [33:0] storage_2[0:15]; +reg [33:0] storage_2_dat0; +always @(posedge sys_clk) begin + if (sdcard_mem2block_dma_fifo_wrport_we) + storage_2[sdcard_mem2block_dma_fifo_wrport_adr] <= sdcard_mem2block_dma_fifo_wrport_dat_w; + storage_2_dat0 <= storage_2[sdcard_mem2block_dma_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign sdcard_mem2block_dma_fifo_wrport_dat_r = storage_2_dat0; +assign sdcard_mem2block_dma_fifo_rdport_dat_r = storage_2[sdcard_mem2block_dma_fifo_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_3: 512-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Sync | Write: ---- | +reg [9:0] storage_3[0:511]; +reg [9:0] storage_3_dat0; +reg [9:0] storage_3_dat1; +always @(posedge sys_clk) begin + if (sdcard_mem2block_fifo_wrport_we) + storage_3[sdcard_mem2block_fifo_wrport_adr] <= sdcard_mem2block_fifo_wrport_dat_w; + storage_3_dat0 <= storage_3[sdcard_mem2block_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin + if (sdcard_mem2block_fifo_rdport_re) + storage_3_dat1 <= storage_3[sdcard_mem2block_fifo_rdport_adr]; +end +assign sdcard_mem2block_fifo_wrport_dat_r = storage_3_dat0; +assign sdcard_mem2block_fifo_rdport_dat_r = storage_3_dat1; + + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX( + // Inputs. + .D ((~clocker_clk0)), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdcard_clk) +); + +assign sdcard_cmd = inferedsdrtristate0_oe ? inferedsdrtristate0__o : 1'bz; +assign inferedsdrtristate0__i = sdcard_cmd; + +assign sdcard_data[0] = inferedsdrtristate1_oe ? inferedsdrtristate1__o : 1'bz; +assign inferedsdrtristate1__i = sdcard_data[0]; + +assign sdcard_data[1] = inferedsdrtristate2_oe ? inferedsdrtristate2__o : 1'bz; +assign inferedsdrtristate2__i = sdcard_data[1]; + +assign sdcard_data[2] = inferedsdrtristate3_oe ? inferedsdrtristate3__o : 1'bz; +assign inferedsdrtristate3__i = sdcard_data[2]; + +assign sdcard_data[3] = inferedsdrtristate4_oe ? inferedsdrtristate4__o : 1'bz; +assign inferedsdrtristate4__i = sdcard_data[3]; + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX_1 of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX_1( + // Inputs. + .D (sdpads_cmd_oe), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdcard_cmd_dir) +); + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX_2 of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX_2( + // Inputs. + .D (sdpads_data_oe), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdcard_dat0_dir) +); + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX_3 of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX_3( + // Inputs. + .D (sdpads_data_oe), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdcard_dat13_dir) +); + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX_4 of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX_4( + // Inputs. + .D (sdpads_cmd_o), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (inferedsdrtristate0__o) +); + +//------------------------------------------------------------------------------ +// Instance IFS1P3BX of IFS1P3BX Module. +//------------------------------------------------------------------------------ +IFS1P3BX IFS1P3BX( + // Inputs. + .D (inferedsdrtristate0__i), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdpads_cmd_i) +); + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX_5 of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX_5( + // Inputs. + .D (sdpads_data_o[0]), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (inferedsdrtristate1__o) +); + +//------------------------------------------------------------------------------ +// Instance IFS1P3BX_1 of IFS1P3BX Module. +//------------------------------------------------------------------------------ +IFS1P3BX IFS1P3BX_1( + // Inputs. + .D (inferedsdrtristate1__i), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdpads_data_i[0]) +); + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX_6 of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX_6( + // Inputs. + .D (sdpads_data_o[1]), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (inferedsdrtristate2__o) +); + +//------------------------------------------------------------------------------ +// Instance IFS1P3BX_2 of IFS1P3BX Module. +//------------------------------------------------------------------------------ +IFS1P3BX IFS1P3BX_2( + // Inputs. + .D (inferedsdrtristate2__i), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdpads_data_i[1]) +); + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX_7 of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX_7( + // Inputs. + .D (sdpads_data_o[2]), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (inferedsdrtristate3__o) +); + +//------------------------------------------------------------------------------ +// Instance IFS1P3BX_3 of IFS1P3BX Module. +//------------------------------------------------------------------------------ +IFS1P3BX IFS1P3BX_3( + // Inputs. + .D (inferedsdrtristate3__i), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdpads_data_i[2]) +); + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX_8 of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX_8( + // Inputs. + .D (sdpads_data_o[3]), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (inferedsdrtristate4__o) +); + +//------------------------------------------------------------------------------ +// Instance IFS1P3BX_4 of IFS1P3BX Module. +//------------------------------------------------------------------------------ +IFS1P3BX IFS1P3BX_4( + // Inputs. + .D (inferedsdrtristate4__i), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdpads_data_i[3]) +); + +endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2024-04-03 19:58:12. +//------------------------------------------------------------------------------ diff --git a/litesdcard/generated/lattice/litesdcard_core.v b/litesdcard/generated/lattice/litesdcard_core.v deleted file mode 100644 index f4d44e6..0000000 --- a/litesdcard/generated/lattice/litesdcard_core.v +++ /dev/null @@ -1,4288 +0,0 @@ -// ----------------------------------------------------------------------------- -// Auto-Generated by: __ _ __ _ __ -// / / (_) /____ | |/_/ -// / /__/ / __/ -_)> < -// /____/_/\__/\__/_/|_| -// Build your hardware, easily! -// https://github.com/enjoy-digital/litex -// -// Filename : litesdcard_core.v -// Device : -// LiteX sha1 : 6932fc51 -// Date : 2022-08-04 18:14:15 -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// Module -//------------------------------------------------------------------------------ - -module litesdcard_core ( - input wire clk, - input wire rst, - input wire [29:0] wb_ctrl_adr, - input wire [31:0] wb_ctrl_dat_w, - output wire [31:0] wb_ctrl_dat_r, - input wire [3:0] wb_ctrl_sel, - input wire wb_ctrl_cyc, - input wire wb_ctrl_stb, - output wire wb_ctrl_ack, - input wire wb_ctrl_we, - input wire [2:0] wb_ctrl_cti, - input wire [1:0] wb_ctrl_bte, - output wire wb_ctrl_err, - output wire [29:0] wb_dma_adr, - output wire [31:0] wb_dma_dat_w, - input wire [31:0] wb_dma_dat_r, - output wire [3:0] wb_dma_sel, - output wire wb_dma_cyc, - output wire wb_dma_stb, - input wire wb_dma_ack, - output wire wb_dma_we, - output wire [2:0] wb_dma_cti, - output wire [1:0] wb_dma_bte, - input wire wb_dma_err, - inout wire [3:0] sdcard_data, - inout wire sdcard_cmd, - output wire sdcard_clk, - input wire sdcard_cd, - output wire irq -); - - -//------------------------------------------------------------------------------ -// Signals -//------------------------------------------------------------------------------ - -wire sys_clk; -wire sys_rst; -wire por_clk; -reg int_rst = 1'd1; -reg soc_rst = 1'd0; -wire cpu_rst; -reg [1:0] reset_storage = 2'd0; -reg reset_re = 1'd0; -reg [31:0] scratch_storage = 32'd305419896; -reg scratch_re = 1'd0; -wire [31:0] bus_errors_status; -wire bus_errors_we; -reg bus_errors_re = 1'd0; -reg bus_error = 1'd0; -reg [31:0] bus_errors = 32'd0; -wire [29:0] wb_ctrl_adr_1; -wire [31:0] wb_ctrl_dat_w_1; -wire [31:0] wb_ctrl_dat_r_1; -wire [3:0] wb_ctrl_sel_1; -wire wb_ctrl_cyc_1; -wire wb_ctrl_stb_1; -wire wb_ctrl_ack_1; -wire wb_ctrl_we_1; -wire [2:0] wb_ctrl_cti_1; -wire [1:0] wb_ctrl_bte_1; -wire wb_ctrl_err_1; -wire [29:0] wb_dma_adr_1; -wire [31:0] wb_dma_dat_w_1; -wire [31:0] wb_dma_dat_r_1; -wire [3:0] wb_dma_sel_1; -wire wb_dma_cyc_1; -wire wb_dma_stb_1; -wire wb_dma_ack_1; -wire wb_dma_we_1; -wire [2:0] wb_dma_cti_1; -wire [1:0] wb_dma_bte_1; -wire wb_dma_err_1; -wire card_detect_status0; -wire card_detect_we; -reg card_detect_re = 1'd0; -reg [8:0] clocker_storage = 9'd256; -reg clocker_re = 1'd0; -wire clocker_stop; -wire clocker_ce; -wire clocker_clk_en; -wire clocker_clk0; -reg [8:0] clocker_clks = 9'd0; -reg clocker_clk1 = 1'd0; -reg clocker_clk_d = 1'd0; -reg clocker_ce_delayed = 1'd0; -reg clocker_ce_latched = 1'd0; -reg init_initialize_re = 1'd0; -wire init_initialize_r; -reg init_initialize_we = 1'd0; -reg init_initialize_w = 1'd0; -wire init_pads_in_valid; -wire init_pads_in_payload_cmd_i; -wire [3:0] init_pads_in_payload_data_i; -wire init_pads_out_ready; -reg init_pads_out_payload_clk = 1'd0; -reg init_pads_out_payload_cmd_o = 1'd0; -reg init_pads_out_payload_cmd_oe = 1'd0; -reg [3:0] init_pads_out_payload_data_o = 4'd0; -reg init_pads_out_payload_data_oe = 1'd0; -reg [7:0] init_count = 8'd0; -wire cmdw_pads_in_valid; -wire cmdw_pads_in_payload_cmd_i; -wire [3:0] cmdw_pads_in_payload_data_i; -wire cmdw_pads_out_ready; -reg cmdw_pads_out_payload_clk = 1'd0; -reg cmdw_pads_out_payload_cmd_o = 1'd0; -reg cmdw_pads_out_payload_cmd_oe = 1'd0; -reg [3:0] cmdw_pads_out_payload_data_o = 4'd0; -reg cmdw_pads_out_payload_data_oe = 1'd0; -reg cmdw_sink_valid = 1'd0; -reg cmdw_sink_ready = 1'd0; -reg cmdw_sink_last = 1'd0; -reg [7:0] cmdw_sink_payload_data = 8'd0; -reg [1:0] cmdw_sink_payload_cmd_type = 2'd0; -reg cmdw_done = 1'd0; -reg [7:0] cmdw_count = 8'd0; -wire cmdr_pads_in_pads_in_valid; -wire cmdr_pads_in_pads_in_ready; -reg cmdr_pads_in_pads_in_first = 1'd0; -reg cmdr_pads_in_pads_in_last = 1'd0; -reg cmdr_pads_in_pads_in_payload_clk = 1'd0; -wire cmdr_pads_in_pads_in_payload_cmd_i; -reg cmdr_pads_in_pads_in_payload_cmd_o = 1'd0; -reg cmdr_pads_in_pads_in_payload_cmd_oe = 1'd0; -wire [3:0] cmdr_pads_in_pads_in_payload_data_i; -reg [3:0] cmdr_pads_in_pads_in_payload_data_o = 4'd0; -reg cmdr_pads_in_pads_in_payload_data_oe = 1'd0; -reg cmdr_pads_in_pads_in_payload_data_i_ce = 1'd0; -wire cmdr_pads_out_ready; -reg cmdr_pads_out_payload_clk = 1'd0; -reg cmdr_pads_out_payload_cmd_o = 1'd0; -reg cmdr_pads_out_payload_cmd_oe = 1'd0; -reg [3:0] cmdr_pads_out_payload_data_o = 4'd0; -reg cmdr_pads_out_payload_data_oe = 1'd0; -reg cmdr_sink_valid = 1'd0; -reg cmdr_sink_ready = 1'd0; -reg [1:0] cmdr_sink_payload_cmd_type = 2'd0; -reg [1:0] cmdr_sink_payload_data_type = 2'd0; -reg [7:0] cmdr_sink_payload_length = 8'd0; -reg cmdr_source_valid = 1'd0; -reg cmdr_source_ready = 1'd0; -reg cmdr_source_last = 1'd0; -reg [7:0] cmdr_source_payload_data = 8'd0; -reg [2:0] cmdr_source_payload_status = 3'd0; -reg [31:0] cmdr_timeout = 32'd48000000; -reg [7:0] cmdr_count = 8'd0; -reg cmdr_busy = 1'd0; -wire cmdr_cmdr_pads_in_valid; -reg cmdr_cmdr_pads_in_ready = 1'd0; -wire cmdr_cmdr_pads_in_first; -wire cmdr_cmdr_pads_in_last; -wire cmdr_cmdr_pads_in_payload_clk; -wire cmdr_cmdr_pads_in_payload_cmd_i; -wire cmdr_cmdr_pads_in_payload_cmd_o; -wire cmdr_cmdr_pads_in_payload_cmd_oe; -wire [3:0] cmdr_cmdr_pads_in_payload_data_i; -wire [3:0] cmdr_cmdr_pads_in_payload_data_o; -wire cmdr_cmdr_pads_in_payload_data_oe; -wire cmdr_cmdr_pads_in_payload_data_i_ce; -wire cmdr_cmdr_source_source_valid0; -reg cmdr_cmdr_source_source_ready0 = 1'd0; -wire cmdr_cmdr_source_source_first0; -wire cmdr_cmdr_source_source_last0; -wire [7:0] cmdr_cmdr_source_source_payload_data0; -wire cmdr_cmdr_start; -reg cmdr_cmdr_run = 1'd0; -wire cmdr_cmdr_converter_sink_valid; -wire cmdr_cmdr_converter_sink_ready; -reg cmdr_cmdr_converter_sink_first = 1'd0; -reg cmdr_cmdr_converter_sink_last = 1'd0; -wire cmdr_cmdr_converter_sink_payload_data; -wire cmdr_cmdr_converter_source_valid; -wire cmdr_cmdr_converter_source_ready; -reg cmdr_cmdr_converter_source_first = 1'd0; -reg cmdr_cmdr_converter_source_last = 1'd0; -reg [7:0] cmdr_cmdr_converter_source_payload_data = 8'd0; -reg [3:0] cmdr_cmdr_converter_source_payload_valid_token_count = 4'd0; -reg [2:0] cmdr_cmdr_converter_demux = 3'd0; -wire cmdr_cmdr_converter_load_part; -reg cmdr_cmdr_converter_strobe_all = 1'd0; -wire cmdr_cmdr_source_source_valid1; -wire cmdr_cmdr_source_source_ready1; -wire cmdr_cmdr_source_source_first1; -wire cmdr_cmdr_source_source_last1; -wire [7:0] cmdr_cmdr_source_source_payload_data1; -wire cmdr_cmdr_buf_sink_valid; -wire cmdr_cmdr_buf_sink_ready; -wire cmdr_cmdr_buf_sink_first; -wire cmdr_cmdr_buf_sink_last; -wire [7:0] cmdr_cmdr_buf_sink_payload_data; -reg cmdr_cmdr_buf_source_valid = 1'd0; -wire cmdr_cmdr_buf_source_ready; -reg cmdr_cmdr_buf_source_first = 1'd0; -reg cmdr_cmdr_buf_source_last = 1'd0; -reg [7:0] cmdr_cmdr_buf_source_payload_data = 8'd0; -reg cmdr_cmdr_reset = 1'd0; -wire dataw_pads_in_pads_in_valid; -reg dataw_pads_in_pads_in_ready = 1'd0; -reg dataw_pads_in_pads_in_first = 1'd0; -reg dataw_pads_in_pads_in_last = 1'd0; -reg dataw_pads_in_pads_in_payload_clk = 1'd0; -wire dataw_pads_in_pads_in_payload_cmd_i; -reg dataw_pads_in_pads_in_payload_cmd_o = 1'd0; -reg dataw_pads_in_pads_in_payload_cmd_oe = 1'd0; -wire [3:0] dataw_pads_in_pads_in_payload_data_i; -reg [3:0] dataw_pads_in_pads_in_payload_data_o = 4'd0; -reg dataw_pads_in_pads_in_payload_data_oe = 1'd0; -reg dataw_pads_in_pads_in_payload_data_i_ce = 1'd0; -wire dataw_pads_out_ready; -reg dataw_pads_out_payload_clk = 1'd0; -reg dataw_pads_out_payload_cmd_o = 1'd0; -reg dataw_pads_out_payload_cmd_oe = 1'd0; -reg [3:0] dataw_pads_out_payload_data_o = 4'd0; -reg dataw_pads_out_payload_data_oe = 1'd0; -reg dataw_sink_valid = 1'd0; -reg dataw_sink_ready = 1'd0; -reg dataw_sink_first = 1'd0; -reg dataw_sink_last = 1'd0; -reg [7:0] dataw_sink_payload_data = 8'd0; -reg dataw_stop = 1'd0; -wire dataw_accepted0; -wire dataw_crc_error0; -wire dataw_write_error0; -reg [2:0] dataw_status = 3'd0; -wire dataw_we; -reg dataw_re = 1'd0; -reg [7:0] dataw_count = 8'd0; -reg dataw_accepted1 = 1'd0; -reg dataw_crc_error1 = 1'd0; -reg dataw_write_error1 = 1'd0; -wire dataw_crc_pads_in_valid; -wire dataw_crc_pads_in_ready; -wire dataw_crc_pads_in_first; -wire dataw_crc_pads_in_last; -wire dataw_crc_pads_in_payload_clk; -wire dataw_crc_pads_in_payload_cmd_i; -wire dataw_crc_pads_in_payload_cmd_o; -wire dataw_crc_pads_in_payload_cmd_oe; -wire [3:0] dataw_crc_pads_in_payload_data_i; -wire [3:0] dataw_crc_pads_in_payload_data_o; -wire dataw_crc_pads_in_payload_data_oe; -wire dataw_crc_pads_in_payload_data_i_ce; -wire dataw_crc_source_source_valid0; -reg dataw_crc_source_source_ready0 = 1'd0; -wire dataw_crc_source_source_first0; -wire dataw_crc_source_source_last0; -wire [7:0] dataw_crc_source_source_payload_data0; -wire dataw_crc_start; -reg dataw_crc_run = 1'd0; -wire dataw_crc_converter_sink_valid; -wire dataw_crc_converter_sink_ready; -reg dataw_crc_converter_sink_first = 1'd0; -reg dataw_crc_converter_sink_last = 1'd0; -wire dataw_crc_converter_sink_payload_data; -wire dataw_crc_converter_source_valid; -wire dataw_crc_converter_source_ready; -reg dataw_crc_converter_source_first = 1'd0; -reg dataw_crc_converter_source_last = 1'd0; -reg [7:0] dataw_crc_converter_source_payload_data = 8'd0; -reg [3:0] dataw_crc_converter_source_payload_valid_token_count = 4'd0; -reg [2:0] dataw_crc_converter_demux = 3'd0; -wire dataw_crc_converter_load_part; -reg dataw_crc_converter_strobe_all = 1'd0; -wire dataw_crc_source_source_valid1; -wire dataw_crc_source_source_ready1; -wire dataw_crc_source_source_first1; -wire dataw_crc_source_source_last1; -wire [7:0] dataw_crc_source_source_payload_data1; -wire dataw_crc_buf_sink_valid; -wire dataw_crc_buf_sink_ready; -wire dataw_crc_buf_sink_first; -wire dataw_crc_buf_sink_last; -wire [7:0] dataw_crc_buf_sink_payload_data; -reg dataw_crc_buf_source_valid = 1'd0; -wire dataw_crc_buf_source_ready; -reg dataw_crc_buf_source_first = 1'd0; -reg dataw_crc_buf_source_last = 1'd0; -reg [7:0] dataw_crc_buf_source_payload_data = 8'd0; -reg dataw_crc_reset = 1'd0; -wire datar_pads_in_pads_in_valid; -wire datar_pads_in_pads_in_ready; -reg datar_pads_in_pads_in_first = 1'd0; -reg datar_pads_in_pads_in_last = 1'd0; -reg datar_pads_in_pads_in_payload_clk = 1'd0; -wire datar_pads_in_pads_in_payload_cmd_i; -reg datar_pads_in_pads_in_payload_cmd_o = 1'd0; -reg datar_pads_in_pads_in_payload_cmd_oe = 1'd0; -wire [3:0] datar_pads_in_pads_in_payload_data_i; -reg [3:0] datar_pads_in_pads_in_payload_data_o = 4'd0; -reg datar_pads_in_pads_in_payload_data_oe = 1'd0; -reg datar_pads_in_pads_in_payload_data_i_ce = 1'd0; -wire datar_pads_out_ready; -reg datar_pads_out_payload_clk = 1'd0; -reg datar_pads_out_payload_cmd_o = 1'd0; -reg datar_pads_out_payload_cmd_oe = 1'd0; -reg [3:0] datar_pads_out_payload_data_o = 4'd0; -reg datar_pads_out_payload_data_oe = 1'd0; -reg datar_sink_valid = 1'd0; -reg datar_sink_ready = 1'd0; -reg datar_sink_last = 1'd0; -reg [9:0] datar_sink_payload_block_length = 10'd0; -reg datar_source_valid = 1'd0; -reg datar_source_ready = 1'd0; -reg datar_source_first = 1'd0; -reg datar_source_last = 1'd0; -reg [7:0] datar_source_payload_data = 8'd0; -reg [2:0] datar_source_payload_status = 3'd0; -reg datar_stop = 1'd0; -reg [31:0] datar_timeout = 32'd48000000; -reg [9:0] datar_count = 10'd0; -wire datar_datar_pads_in_valid; -reg datar_datar_pads_in_ready = 1'd0; -wire datar_datar_pads_in_first; -wire datar_datar_pads_in_last; -wire datar_datar_pads_in_payload_clk; -wire datar_datar_pads_in_payload_cmd_i; -wire datar_datar_pads_in_payload_cmd_o; -wire datar_datar_pads_in_payload_cmd_oe; -wire [3:0] datar_datar_pads_in_payload_data_i; -wire [3:0] datar_datar_pads_in_payload_data_o; -wire datar_datar_pads_in_payload_data_oe; -wire datar_datar_pads_in_payload_data_i_ce; -wire datar_datar_source_source_valid0; -reg datar_datar_source_source_ready0 = 1'd0; -wire datar_datar_source_source_first0; -wire datar_datar_source_source_last0; -wire [7:0] datar_datar_source_source_payload_data0; -wire datar_datar_start; -reg datar_datar_run = 1'd0; -wire datar_datar_converter_sink_valid; -wire datar_datar_converter_sink_ready; -reg datar_datar_converter_sink_first = 1'd0; -reg datar_datar_converter_sink_last = 1'd0; -wire [3:0] datar_datar_converter_sink_payload_data; -wire datar_datar_converter_source_valid; -wire datar_datar_converter_source_ready; -reg datar_datar_converter_source_first = 1'd0; -reg datar_datar_converter_source_last = 1'd0; -reg [7:0] datar_datar_converter_source_payload_data = 8'd0; -reg [1:0] datar_datar_converter_source_payload_valid_token_count = 2'd0; -reg datar_datar_converter_demux = 1'd0; -wire datar_datar_converter_load_part; -reg datar_datar_converter_strobe_all = 1'd0; -wire datar_datar_source_source_valid1; -wire datar_datar_source_source_ready1; -wire datar_datar_source_source_first1; -wire datar_datar_source_source_last1; -wire [7:0] datar_datar_source_source_payload_data1; -wire datar_datar_buf_sink_valid; -wire datar_datar_buf_sink_ready; -wire datar_datar_buf_sink_first; -wire datar_datar_buf_sink_last; -wire [7:0] datar_datar_buf_sink_payload_data; -reg datar_datar_buf_source_valid = 1'd0; -wire datar_datar_buf_source_ready; -reg datar_datar_buf_source_first = 1'd0; -reg datar_datar_buf_source_last = 1'd0; -reg [7:0] datar_datar_buf_source_payload_data = 8'd0; -reg datar_datar_reset = 1'd0; -wire sdpads_clk; -wire sdpads_cmd_i; -wire sdpads_cmd_o; -wire sdpads_cmd_oe; -wire [3:0] sdpads_data_i; -wire [3:0] sdpads_data_o; -wire sdpads_data_oe; -reg sdpads_data_i_ce = 1'd0; -reg [1:0] clocker_clk_delay = 2'd0; -reg card_detect_irq = 1'd0; -reg card_detect_d = 1'd0; -wire sdcore_sink_sink_valid0; -wire sdcore_sink_sink_ready0; -wire sdcore_sink_sink_first0; -wire sdcore_sink_sink_last0; -wire [7:0] sdcore_sink_sink_payload_data0; -wire sdcore_source_source_valid0; -wire sdcore_source_source_ready0; -wire sdcore_source_source_first0; -wire sdcore_source_source_last0; -wire [7:0] sdcore_source_source_payload_data0; -reg [31:0] sdcore_cmd_argument_storage = 32'd0; -reg sdcore_cmd_argument_re = 1'd0; -wire [1:0] sdcore_csrfield_cmd_type; -wire [1:0] sdcore_csrfield_data_type; -wire [5:0] sdcore_csrfield_cmd; -reg [13:0] sdcore_cmd_command_storage = 14'd0; -reg sdcore_cmd_command_re = 1'd0; -reg sdcore_cmd_send_storage = 1'd0; -reg sdcore_cmd_send_re = 1'd0; -reg [127:0] sdcore_cmd_response_status = 128'd0; -wire sdcore_cmd_response_we; -reg sdcore_cmd_response_re = 1'd0; -wire sdcore_csrfield_done0; -wire sdcore_csrfield_error0; -wire sdcore_csrfield_timeout0; -wire sdcore_csrfield_crc0; -reg [3:0] sdcore_cmd_event_status = 4'd0; -wire sdcore_cmd_event_we; -reg sdcore_cmd_event_re = 1'd0; -wire sdcore_csrfield_done1; -wire sdcore_csrfield_error1; -wire sdcore_csrfield_timeout1; -wire sdcore_csrfield_crc1; -reg [3:0] sdcore_data_event_status = 4'd0; -wire sdcore_data_event_we; -reg sdcore_data_event_re = 1'd0; -reg [9:0] sdcore_block_length_storage = 10'd0; -reg sdcore_block_length_re = 1'd0; -reg [31:0] sdcore_block_count_storage = 32'd0; -reg sdcore_block_count_re = 1'd0; -wire sdcore_crc7_inserter_reset; -wire sdcore_crc7_inserter_enable; -wire [39:0] sdcore_crc7_inserter_din; -reg [6:0] sdcore_crc7_inserter_crc = 7'd0; -reg [6:0] sdcore_crc7_inserter_reg0 = 7'd0; -wire [6:0] sdcore_crc7_inserter_reg1; -wire [6:0] sdcore_crc7_inserter_reg2; -wire [6:0] sdcore_crc7_inserter_reg3; -wire [6:0] sdcore_crc7_inserter_reg4; -wire [6:0] sdcore_crc7_inserter_reg5; -wire [6:0] sdcore_crc7_inserter_reg6; -wire [6:0] sdcore_crc7_inserter_reg7; -wire [6:0] sdcore_crc7_inserter_reg8; -wire [6:0] sdcore_crc7_inserter_reg9; -wire [6:0] sdcore_crc7_inserter_reg10; -wire [6:0] sdcore_crc7_inserter_reg11; -wire [6:0] sdcore_crc7_inserter_reg12; -wire [6:0] sdcore_crc7_inserter_reg13; -wire [6:0] sdcore_crc7_inserter_reg14; -wire [6:0] sdcore_crc7_inserter_reg15; -wire [6:0] sdcore_crc7_inserter_reg16; -wire [6:0] sdcore_crc7_inserter_reg17; -wire [6:0] sdcore_crc7_inserter_reg18; -wire [6:0] sdcore_crc7_inserter_reg19; -wire [6:0] sdcore_crc7_inserter_reg20; -wire [6:0] sdcore_crc7_inserter_reg21; -wire [6:0] sdcore_crc7_inserter_reg22; -wire [6:0] sdcore_crc7_inserter_reg23; -wire [6:0] sdcore_crc7_inserter_reg24; -wire [6:0] sdcore_crc7_inserter_reg25; -wire [6:0] sdcore_crc7_inserter_reg26; -wire [6:0] sdcore_crc7_inserter_reg27; -wire [6:0] sdcore_crc7_inserter_reg28; -wire [6:0] sdcore_crc7_inserter_reg29; -wire [6:0] sdcore_crc7_inserter_reg30; -wire [6:0] sdcore_crc7_inserter_reg31; -wire [6:0] sdcore_crc7_inserter_reg32; -wire [6:0] sdcore_crc7_inserter_reg33; -wire [6:0] sdcore_crc7_inserter_reg34; -wire [6:0] sdcore_crc7_inserter_reg35; -wire [6:0] sdcore_crc7_inserter_reg36; -wire [6:0] sdcore_crc7_inserter_reg37; -wire [6:0] sdcore_crc7_inserter_reg38; -wire [6:0] sdcore_crc7_inserter_reg39; -wire [6:0] sdcore_crc7_inserter_reg40; -wire sdcore_crc16_inserter_sink_valid; -reg sdcore_crc16_inserter_sink_ready = 1'd0; -wire sdcore_crc16_inserter_sink_first; -wire sdcore_crc16_inserter_sink_last; -wire [7:0] sdcore_crc16_inserter_sink_payload_data; -reg sdcore_crc16_inserter_source_valid = 1'd0; -reg sdcore_crc16_inserter_source_ready = 1'd0; -reg sdcore_crc16_inserter_source_first = 1'd0; -reg sdcore_crc16_inserter_source_last = 1'd0; -reg [7:0] sdcore_crc16_inserter_source_payload_data = 8'd0; -reg [2:0] sdcore_crc16_inserter_count = 3'd0; -wire sdcore_crc16_inserter_crc0_reset; -wire sdcore_crc16_inserter_crc0_enable; -reg [1:0] sdcore_crc16_inserter_crc0_din = 2'd0; -reg [15:0] sdcore_crc16_inserter_crc0_crc = 16'd0; -reg [15:0] sdcore_crc16_inserter_crc0_reg0 = 16'd0; -wire [15:0] sdcore_crc16_inserter_crc0_reg1; -wire [15:0] sdcore_crc16_inserter_crc0_reg2; -wire sdcore_crc16_inserter_crc1_reset; -wire sdcore_crc16_inserter_crc1_enable; -reg [1:0] sdcore_crc16_inserter_crc1_din = 2'd0; -reg [15:0] sdcore_crc16_inserter_crc1_crc = 16'd0; -reg [15:0] sdcore_crc16_inserter_crc1_reg0 = 16'd0; -wire [15:0] sdcore_crc16_inserter_crc1_reg1; -wire [15:0] sdcore_crc16_inserter_crc1_reg2; -wire sdcore_crc16_inserter_crc2_reset; -wire sdcore_crc16_inserter_crc2_enable; -reg [1:0] sdcore_crc16_inserter_crc2_din = 2'd0; -reg [15:0] sdcore_crc16_inserter_crc2_crc = 16'd0; -reg [15:0] sdcore_crc16_inserter_crc2_reg0 = 16'd0; -wire [15:0] sdcore_crc16_inserter_crc2_reg1; -wire [15:0] sdcore_crc16_inserter_crc2_reg2; -wire sdcore_crc16_inserter_crc3_reset; -wire sdcore_crc16_inserter_crc3_enable; -reg [1:0] sdcore_crc16_inserter_crc3_din = 2'd0; -reg [15:0] sdcore_crc16_inserter_crc3_crc = 16'd0; -reg [15:0] sdcore_crc16_inserter_crc3_reg0 = 16'd0; -wire [15:0] sdcore_crc16_inserter_crc3_reg1; -wire [15:0] sdcore_crc16_inserter_crc3_reg2; -reg sdcore_sink_sink_valid1 = 1'd0; -wire sdcore_sink_sink_ready1; -reg sdcore_sink_sink_first1 = 1'd0; -reg sdcore_sink_sink_last1 = 1'd0; -reg [7:0] sdcore_sink_sink_payload_data1 = 8'd0; -wire sdcore_source_source_valid1; -wire sdcore_source_source_ready1; -wire sdcore_source_source_first1; -wire sdcore_source_source_last1; -wire [7:0] sdcore_source_source_payload_data1; -wire sdcore_fifo_sink_valid; -wire sdcore_fifo_sink_ready; -wire sdcore_fifo_sink_first; -wire sdcore_fifo_sink_last; -wire [7:0] sdcore_fifo_sink_payload_data; -wire sdcore_fifo_source_valid; -wire sdcore_fifo_source_ready; -wire sdcore_fifo_source_first; -wire sdcore_fifo_source_last; -wire [7:0] sdcore_fifo_source_payload_data; -wire sdcore_fifo_syncfifo_we; -wire sdcore_fifo_syncfifo_writable; -wire sdcore_fifo_syncfifo_re; -wire sdcore_fifo_syncfifo_readable; -wire [9:0] sdcore_fifo_syncfifo_din; -wire [9:0] sdcore_fifo_syncfifo_dout; -reg [3:0] sdcore_fifo_level = 4'd0; -reg sdcore_fifo_replace = 1'd0; -reg [2:0] sdcore_fifo_produce = 3'd0; -reg [2:0] sdcore_fifo_consume = 3'd0; -reg [2:0] sdcore_fifo_wrport_adr = 3'd0; -wire [9:0] sdcore_fifo_wrport_dat_r; -wire sdcore_fifo_wrport_we; -wire [9:0] sdcore_fifo_wrport_dat_w; -wire sdcore_fifo_do_read; -wire [2:0] sdcore_fifo_rdport_adr; -wire [9:0] sdcore_fifo_rdport_dat_r; -wire [7:0] sdcore_fifo_fifo_in_payload_data; -wire sdcore_fifo_fifo_in_first; -wire sdcore_fifo_fifo_in_last; -wire [7:0] sdcore_fifo_fifo_out_payload_data; -wire sdcore_fifo_fifo_out_first; -wire sdcore_fifo_fifo_out_last; -wire sdcore_fifo_reset; -wire [1:0] sdcore_cmd_type; -reg [2:0] sdcore_cmd_count = 3'd0; -reg sdcore_cmd_done = 1'd0; -reg sdcore_cmd_error = 1'd0; -reg sdcore_cmd_timeout = 1'd0; -wire [1:0] sdcore_data_type; -reg [31:0] sdcore_data_count = 32'd0; -reg sdcore_data_done = 1'd0; -reg sdcore_data_error = 1'd0; -reg sdcore_data_timeout = 1'd0; -wire [5:0] sdcore_cmd; -wire [31:0] interface0_bus_adr; -wire [31:0] interface0_bus_dat_w; -wire [31:0] interface0_bus_dat_r; -wire [3:0] interface0_bus_sel; -wire interface0_bus_cyc; -wire interface0_bus_stb; -wire interface0_bus_ack; -wire interface0_bus_we; -reg [2:0] interface0_bus_cti = 3'd0; -reg [1:0] interface0_bus_bte = 2'd0; -wire interface0_bus_err; -wire sdblock2mem_sink_sink_valid0; -reg sdblock2mem_sink_sink_ready0 = 1'd0; -wire sdblock2mem_sink_sink_first; -wire sdblock2mem_sink_sink_last0; -wire [7:0] sdblock2mem_sink_sink_payload_data0; -reg sdblock2mem_irq = 1'd0; -reg sdblock2mem_fifo_sink_valid = 1'd0; -wire sdblock2mem_fifo_sink_ready; -reg sdblock2mem_fifo_sink_first = 1'd0; -reg sdblock2mem_fifo_sink_last = 1'd0; -reg [7:0] sdblock2mem_fifo_sink_payload_data = 8'd0; -wire sdblock2mem_fifo_source_valid; -wire sdblock2mem_fifo_source_ready; -wire sdblock2mem_fifo_source_first; -wire sdblock2mem_fifo_source_last; -wire [7:0] sdblock2mem_fifo_source_payload_data; -wire sdblock2mem_fifo_re; -reg sdblock2mem_fifo_readable = 1'd0; -wire sdblock2mem_fifo_syncfifo_we; -wire sdblock2mem_fifo_syncfifo_writable; -wire sdblock2mem_fifo_syncfifo_re; -wire sdblock2mem_fifo_syncfifo_readable; -wire [9:0] sdblock2mem_fifo_syncfifo_din; -wire [9:0] sdblock2mem_fifo_syncfifo_dout; -reg [9:0] sdblock2mem_fifo_level0 = 10'd0; -reg sdblock2mem_fifo_replace = 1'd0; -reg [8:0] sdblock2mem_fifo_produce = 9'd0; -reg [8:0] sdblock2mem_fifo_consume = 9'd0; -reg [8:0] sdblock2mem_fifo_wrport_adr = 9'd0; -wire [9:0] sdblock2mem_fifo_wrport_dat_r; -wire sdblock2mem_fifo_wrport_we; -wire [9:0] sdblock2mem_fifo_wrport_dat_w; -wire sdblock2mem_fifo_do_read; -wire [8:0] sdblock2mem_fifo_rdport_adr; -wire [9:0] sdblock2mem_fifo_rdport_dat_r; -wire sdblock2mem_fifo_rdport_re; -wire [9:0] sdblock2mem_fifo_level1; -wire [7:0] sdblock2mem_fifo_fifo_in_payload_data; -wire sdblock2mem_fifo_fifo_in_first; -wire sdblock2mem_fifo_fifo_in_last; -wire [7:0] sdblock2mem_fifo_fifo_out_payload_data; -wire sdblock2mem_fifo_fifo_out_first; -wire sdblock2mem_fifo_fifo_out_last; -wire sdblock2mem_converter_sink_valid; -wire sdblock2mem_converter_sink_ready; -wire sdblock2mem_converter_sink_first; -wire sdblock2mem_converter_sink_last; -wire [7:0] sdblock2mem_converter_sink_payload_data; -wire sdblock2mem_converter_source_valid; -wire sdblock2mem_converter_source_ready; -reg sdblock2mem_converter_source_first = 1'd0; -reg sdblock2mem_converter_source_last = 1'd0; -reg [31:0] sdblock2mem_converter_source_payload_data = 32'd0; -reg [2:0] sdblock2mem_converter_source_payload_valid_token_count = 3'd0; -reg [1:0] sdblock2mem_converter_demux = 2'd0; -wire sdblock2mem_converter_load_part; -reg sdblock2mem_converter_strobe_all = 1'd0; -wire sdblock2mem_source_source_valid; -wire sdblock2mem_source_source_ready; -wire sdblock2mem_source_source_first; -wire sdblock2mem_source_source_last; -wire [31:0] sdblock2mem_source_source_payload_data; -reg sdblock2mem_sink_sink_valid1 = 1'd0; -wire sdblock2mem_sink_sink_ready1; -reg sdblock2mem_sink_sink_last1 = 1'd0; -reg [31:0] sdblock2mem_sink_sink_payload_address = 32'd0; -reg [31:0] sdblock2mem_sink_sink_payload_data1 = 32'd0; -wire sdblock2mem_wishbonedmawriter_sink_valid; -reg sdblock2mem_wishbonedmawriter_sink_ready = 1'd0; -wire sdblock2mem_wishbonedmawriter_sink_first; -wire sdblock2mem_wishbonedmawriter_sink_last; -wire [31:0] sdblock2mem_wishbonedmawriter_sink_payload_data; -reg [63:0] sdblock2mem_wishbonedmawriter_base_storage = 64'd0; -reg sdblock2mem_wishbonedmawriter_base_re = 1'd0; -reg [31:0] sdblock2mem_wishbonedmawriter_length_storage = 32'd0; -reg sdblock2mem_wishbonedmawriter_length_re = 1'd0; -reg sdblock2mem_wishbonedmawriter_enable_storage = 1'd0; -reg sdblock2mem_wishbonedmawriter_enable_re = 1'd0; -reg sdblock2mem_wishbonedmawriter_done_status = 1'd0; -wire sdblock2mem_wishbonedmawriter_done_we; -reg sdblock2mem_wishbonedmawriter_done_re = 1'd0; -reg sdblock2mem_wishbonedmawriter_loop_storage = 1'd0; -reg sdblock2mem_wishbonedmawriter_loop_re = 1'd0; -wire [31:0] sdblock2mem_wishbonedmawriter_offset_status; -wire sdblock2mem_wishbonedmawriter_offset_we; -reg sdblock2mem_wishbonedmawriter_offset_re = 1'd0; -wire [31:0] sdblock2mem_wishbonedmawriter_base; -reg [31:0] sdblock2mem_wishbonedmawriter_offset = 32'd0; -wire [31:0] sdblock2mem_wishbonedmawriter_length; -wire sdblock2mem_wishbonedmawriter_reset; -wire sdblock2mem_start; -reg sdblock2mem_connect = 1'd0; -reg sdblock2mem_done_d = 1'd0; -reg [31:0] interface1_bus_adr = 32'd0; -reg [31:0] interface1_bus_dat_w = 32'd0; -wire [31:0] interface1_bus_dat_r; -reg [3:0] interface1_bus_sel = 4'd0; -reg interface1_bus_cyc = 1'd0; -reg interface1_bus_stb = 1'd0; -wire interface1_bus_ack; -reg interface1_bus_we = 1'd0; -reg [2:0] interface1_bus_cti = 3'd0; -reg [1:0] interface1_bus_bte = 2'd0; -wire interface1_bus_err; -wire sdmem2block_source_source_valid0; -wire sdmem2block_source_source_ready0; -wire sdmem2block_source_source_first0; -reg sdmem2block_source_source_last0 = 1'd0; -wire [7:0] sdmem2block_source_source_payload_data0; -reg sdmem2block_irq = 1'd0; -reg sdmem2block_dma_sink_valid = 1'd0; -reg sdmem2block_dma_sink_ready = 1'd0; -reg sdmem2block_dma_sink_last = 1'd0; -reg [31:0] sdmem2block_dma_sink_payload_address = 32'd0; -reg sdmem2block_dma_source_valid = 1'd0; -wire sdmem2block_dma_source_ready; -reg sdmem2block_dma_source_first = 1'd0; -reg sdmem2block_dma_source_last = 1'd0; -reg [31:0] sdmem2block_dma_source_payload_data = 32'd0; -reg [31:0] sdmem2block_dma_data = 32'd0; -reg [63:0] sdmem2block_dma_base_storage = 64'd0; -reg sdmem2block_dma_base_re = 1'd0; -reg [31:0] sdmem2block_dma_length_storage = 32'd0; -reg sdmem2block_dma_length_re = 1'd0; -reg sdmem2block_dma_enable_storage = 1'd0; -reg sdmem2block_dma_enable_re = 1'd0; -reg sdmem2block_dma_done_status = 1'd0; -wire sdmem2block_dma_done_we; -reg sdmem2block_dma_done_re = 1'd0; -reg sdmem2block_dma_loop_storage = 1'd0; -reg sdmem2block_dma_loop_re = 1'd0; -wire [31:0] sdmem2block_dma_offset_status; -wire sdmem2block_dma_offset_we; -reg sdmem2block_dma_offset_re = 1'd0; -wire [31:0] sdmem2block_dma_base; -reg [31:0] sdmem2block_dma_offset = 32'd0; -wire [31:0] sdmem2block_dma_length; -wire sdmem2block_dma_reset; -wire sdmem2block_converter_sink_valid; -wire sdmem2block_converter_sink_ready; -wire sdmem2block_converter_sink_first; -wire sdmem2block_converter_sink_last; -wire [31:0] sdmem2block_converter_sink_payload_data; -wire sdmem2block_converter_source_valid; -wire sdmem2block_converter_source_ready; -wire sdmem2block_converter_source_first; -wire sdmem2block_converter_source_last; -reg [7:0] sdmem2block_converter_source_payload_data = 8'd0; -wire sdmem2block_converter_source_payload_valid_token_count; -reg [1:0] sdmem2block_converter_mux = 2'd0; -wire sdmem2block_converter_first; -wire sdmem2block_converter_last; -wire sdmem2block_source_source_valid1; -wire sdmem2block_source_source_ready1; -wire sdmem2block_source_source_first1; -wire sdmem2block_source_source_last1; -wire [7:0] sdmem2block_source_source_payload_data1; -wire sdmem2block_fifo_sink_valid; -wire sdmem2block_fifo_sink_ready; -wire sdmem2block_fifo_sink_first; -wire sdmem2block_fifo_sink_last; -wire [7:0] sdmem2block_fifo_sink_payload_data; -wire sdmem2block_fifo_source_valid; -wire sdmem2block_fifo_source_ready; -wire sdmem2block_fifo_source_first; -wire sdmem2block_fifo_source_last; -wire [7:0] sdmem2block_fifo_source_payload_data; -wire sdmem2block_fifo_re; -reg sdmem2block_fifo_readable = 1'd0; -wire sdmem2block_fifo_syncfifo_we; -wire sdmem2block_fifo_syncfifo_writable; -wire sdmem2block_fifo_syncfifo_re; -wire sdmem2block_fifo_syncfifo_readable; -wire [9:0] sdmem2block_fifo_syncfifo_din; -wire [9:0] sdmem2block_fifo_syncfifo_dout; -reg [9:0] sdmem2block_fifo_level0 = 10'd0; -reg sdmem2block_fifo_replace = 1'd0; -reg [8:0] sdmem2block_fifo_produce = 9'd0; -reg [8:0] sdmem2block_fifo_consume = 9'd0; -reg [8:0] sdmem2block_fifo_wrport_adr = 9'd0; -wire [9:0] sdmem2block_fifo_wrport_dat_r; -wire sdmem2block_fifo_wrport_we; -wire [9:0] sdmem2block_fifo_wrport_dat_w; -wire sdmem2block_fifo_do_read; -wire [8:0] sdmem2block_fifo_rdport_adr; -wire [9:0] sdmem2block_fifo_rdport_dat_r; -wire sdmem2block_fifo_rdport_re; -wire [9:0] sdmem2block_fifo_level1; -wire [7:0] sdmem2block_fifo_fifo_in_payload_data; -wire sdmem2block_fifo_fifo_in_first; -wire sdmem2block_fifo_fifo_in_last; -wire [7:0] sdmem2block_fifo_fifo_out_payload_data; -wire sdmem2block_fifo_fifo_out_first; -wire sdmem2block_fifo_fifo_out_last; -reg [8:0] sdmem2block_count = 9'd0; -reg sdmem2block_done_d = 1'd0; -wire sdirq_irq; -wire card_detect_status1; -reg card_detect_pending = 1'd0; -wire card_detect_trigger; -reg card_detect_clear = 1'd0; -wire block2mem_dma_status; -reg block2mem_dma_pending = 1'd0; -wire block2mem_dma_trigger; -reg block2mem_dma_clear = 1'd0; -wire mem2block_dma_status; -reg mem2block_dma_pending = 1'd0; -wire mem2block_dma_trigger; -reg mem2block_dma_clear = 1'd0; -wire cmd_done_status; -wire cmd_done_pending; -wire cmd_done_trigger; -reg cmd_done_clear = 1'd0; -wire eventmanager_card_detect0; -wire eventmanager_block2mem_dma0; -wire eventmanager_mem2block_dma0; -wire eventmanager_cmd_done0; -reg [3:0] eventmanager_status_status = 4'd0; -wire eventmanager_status_we; -reg eventmanager_status_re = 1'd0; -wire eventmanager_card_detect1; -wire eventmanager_block2mem_dma1; -wire eventmanager_mem2block_dma1; -wire eventmanager_cmd_done1; -reg [3:0] eventmanager_pending_status = 4'd0; -wire eventmanager_pending_we; -reg eventmanager_pending_re = 1'd0; -reg [3:0] eventmanager_pending_r = 4'd0; -wire eventmanager_card_detect2; -wire eventmanager_block2mem_dma2; -wire eventmanager_mem2block_dma2; -wire eventmanager_cmd_done2; -reg [3:0] eventmanager_enable_storage = 4'd0; -reg eventmanager_enable_re = 1'd0; -reg [13:0] litesdcardcore_adr = 14'd0; -reg litesdcardcore_we = 1'd0; -reg [31:0] litesdcardcore_dat_w = 32'd0; -wire [31:0] litesdcardcore_dat_r; -wire [29:0] litesdcardcore_wishbone_adr; -wire [31:0] litesdcardcore_wishbone_dat_w; -reg [31:0] litesdcardcore_wishbone_dat_r = 32'd0; -wire [3:0] litesdcardcore_wishbone_sel; -wire litesdcardcore_wishbone_cyc; -wire litesdcardcore_wishbone_stb; -reg litesdcardcore_wishbone_ack = 1'd0; -wire litesdcardcore_wishbone_we; -wire [2:0] litesdcardcore_wishbone_cti; -wire [1:0] litesdcardcore_wishbone_bte; -reg litesdcardcore_wishbone_err = 1'd0; -wire [29:0] shared_adr; -wire [31:0] shared_dat_w; -reg [31:0] shared_dat_r = 32'd0; -wire [3:0] shared_sel; -wire shared_cyc; -wire shared_stb; -reg shared_ack = 1'd0; -wire shared_we; -wire [2:0] shared_cti; -wire [1:0] shared_bte; -wire shared_err; -wire [1:0] request; -reg grant = 1'd0; -wire slave_sel; -reg slave_sel_r = 1'd0; -reg error = 1'd0; -wire wait_1; -wire done; -reg [19:0] count = 20'd1000000; -wire [13:0] interface0_bank_bus_adr; -wire interface0_bank_bus_we; -wire [31:0] interface0_bank_bus_dat_w; -reg [31:0] interface0_bank_bus_dat_r = 32'd0; -reg csrbank0_reset0_re = 1'd0; -wire [1:0] csrbank0_reset0_r; -reg csrbank0_reset0_we = 1'd0; -wire [1:0] csrbank0_reset0_w; -reg csrbank0_scratch0_re = 1'd0; -wire [31:0] csrbank0_scratch0_r; -reg csrbank0_scratch0_we = 1'd0; -wire [31:0] csrbank0_scratch0_w; -reg csrbank0_bus_errors_re = 1'd0; -wire [31:0] csrbank0_bus_errors_r; -reg csrbank0_bus_errors_we = 1'd0; -wire [31:0] csrbank0_bus_errors_w; -wire csrbank0_sel; -wire [13:0] interface1_bank_bus_adr; -wire interface1_bank_bus_we; -wire [31:0] interface1_bank_bus_dat_w; -reg [31:0] interface1_bank_bus_dat_r = 32'd0; -reg csrbank1_dma_base1_re = 1'd0; -wire [31:0] csrbank1_dma_base1_r; -reg csrbank1_dma_base1_we = 1'd0; -wire [31:0] csrbank1_dma_base1_w; -reg csrbank1_dma_base0_re = 1'd0; -wire [31:0] csrbank1_dma_base0_r; -reg csrbank1_dma_base0_we = 1'd0; -wire [31:0] csrbank1_dma_base0_w; -reg csrbank1_dma_length0_re = 1'd0; -wire [31:0] csrbank1_dma_length0_r; -reg csrbank1_dma_length0_we = 1'd0; -wire [31:0] csrbank1_dma_length0_w; -reg csrbank1_dma_enable0_re = 1'd0; -wire csrbank1_dma_enable0_r; -reg csrbank1_dma_enable0_we = 1'd0; -wire csrbank1_dma_enable0_w; -reg csrbank1_dma_done_re = 1'd0; -wire csrbank1_dma_done_r; -reg csrbank1_dma_done_we = 1'd0; -wire csrbank1_dma_done_w; -reg csrbank1_dma_loop0_re = 1'd0; -wire csrbank1_dma_loop0_r; -reg csrbank1_dma_loop0_we = 1'd0; -wire csrbank1_dma_loop0_w; -reg csrbank1_dma_offset_re = 1'd0; -wire [31:0] csrbank1_dma_offset_r; -reg csrbank1_dma_offset_we = 1'd0; -wire [31:0] csrbank1_dma_offset_w; -wire csrbank1_sel; -wire [13:0] interface2_bank_bus_adr; -wire interface2_bank_bus_we; -wire [31:0] interface2_bank_bus_dat_w; -reg [31:0] interface2_bank_bus_dat_r = 32'd0; -reg csrbank2_cmd_argument0_re = 1'd0; -wire [31:0] csrbank2_cmd_argument0_r; -reg csrbank2_cmd_argument0_we = 1'd0; -wire [31:0] csrbank2_cmd_argument0_w; -reg csrbank2_cmd_command0_re = 1'd0; -wire [13:0] csrbank2_cmd_command0_r; -reg csrbank2_cmd_command0_we = 1'd0; -wire [13:0] csrbank2_cmd_command0_w; -reg csrbank2_cmd_send0_re = 1'd0; -wire csrbank2_cmd_send0_r; -reg csrbank2_cmd_send0_we = 1'd0; -wire csrbank2_cmd_send0_w; -reg csrbank2_cmd_response3_re = 1'd0; -wire [31:0] csrbank2_cmd_response3_r; -reg csrbank2_cmd_response3_we = 1'd0; -wire [31:0] csrbank2_cmd_response3_w; -reg csrbank2_cmd_response2_re = 1'd0; -wire [31:0] csrbank2_cmd_response2_r; -reg csrbank2_cmd_response2_we = 1'd0; -wire [31:0] csrbank2_cmd_response2_w; -reg csrbank2_cmd_response1_re = 1'd0; -wire [31:0] csrbank2_cmd_response1_r; -reg csrbank2_cmd_response1_we = 1'd0; -wire [31:0] csrbank2_cmd_response1_w; -reg csrbank2_cmd_response0_re = 1'd0; -wire [31:0] csrbank2_cmd_response0_r; -reg csrbank2_cmd_response0_we = 1'd0; -wire [31:0] csrbank2_cmd_response0_w; -reg csrbank2_cmd_event_re = 1'd0; -wire [3:0] csrbank2_cmd_event_r; -reg csrbank2_cmd_event_we = 1'd0; -wire [3:0] csrbank2_cmd_event_w; -reg csrbank2_data_event_re = 1'd0; -wire [3:0] csrbank2_data_event_r; -reg csrbank2_data_event_we = 1'd0; -wire [3:0] csrbank2_data_event_w; -reg csrbank2_block_length0_re = 1'd0; -wire [9:0] csrbank2_block_length0_r; -reg csrbank2_block_length0_we = 1'd0; -wire [9:0] csrbank2_block_length0_w; -reg csrbank2_block_count0_re = 1'd0; -wire [31:0] csrbank2_block_count0_r; -reg csrbank2_block_count0_we = 1'd0; -wire [31:0] csrbank2_block_count0_w; -wire csrbank2_sel; -wire [13:0] interface3_bank_bus_adr; -wire interface3_bank_bus_we; -wire [31:0] interface3_bank_bus_dat_w; -reg [31:0] interface3_bank_bus_dat_r = 32'd0; -reg csrbank3_status_re = 1'd0; -wire [3:0] csrbank3_status_r; -reg csrbank3_status_we = 1'd0; -wire [3:0] csrbank3_status_w; -reg csrbank3_pending_re = 1'd0; -wire [3:0] csrbank3_pending_r; -reg csrbank3_pending_we = 1'd0; -wire [3:0] csrbank3_pending_w; -reg csrbank3_enable0_re = 1'd0; -wire [3:0] csrbank3_enable0_r; -reg csrbank3_enable0_we = 1'd0; -wire [3:0] csrbank3_enable0_w; -wire csrbank3_sel; -wire [13:0] interface4_bank_bus_adr; -wire interface4_bank_bus_we; -wire [31:0] interface4_bank_bus_dat_w; -reg [31:0] interface4_bank_bus_dat_r = 32'd0; -reg csrbank4_dma_base1_re = 1'd0; -wire [31:0] csrbank4_dma_base1_r; -reg csrbank4_dma_base1_we = 1'd0; -wire [31:0] csrbank4_dma_base1_w; -reg csrbank4_dma_base0_re = 1'd0; -wire [31:0] csrbank4_dma_base0_r; -reg csrbank4_dma_base0_we = 1'd0; -wire [31:0] csrbank4_dma_base0_w; -reg csrbank4_dma_length0_re = 1'd0; -wire [31:0] csrbank4_dma_length0_r; -reg csrbank4_dma_length0_we = 1'd0; -wire [31:0] csrbank4_dma_length0_w; -reg csrbank4_dma_enable0_re = 1'd0; -wire csrbank4_dma_enable0_r; -reg csrbank4_dma_enable0_we = 1'd0; -wire csrbank4_dma_enable0_w; -reg csrbank4_dma_done_re = 1'd0; -wire csrbank4_dma_done_r; -reg csrbank4_dma_done_we = 1'd0; -wire csrbank4_dma_done_w; -reg csrbank4_dma_loop0_re = 1'd0; -wire csrbank4_dma_loop0_r; -reg csrbank4_dma_loop0_we = 1'd0; -wire csrbank4_dma_loop0_w; -reg csrbank4_dma_offset_re = 1'd0; -wire [31:0] csrbank4_dma_offset_r; -reg csrbank4_dma_offset_we = 1'd0; -wire [31:0] csrbank4_dma_offset_w; -wire csrbank4_sel; -wire [13:0] interface5_bank_bus_adr; -wire interface5_bank_bus_we; -wire [31:0] interface5_bank_bus_dat_w; -reg [31:0] interface5_bank_bus_dat_r = 32'd0; -reg csrbank5_card_detect_re = 1'd0; -wire csrbank5_card_detect_r; -reg csrbank5_card_detect_we = 1'd0; -wire csrbank5_card_detect_w; -reg csrbank5_clocker_divider0_re = 1'd0; -wire [8:0] csrbank5_clocker_divider0_r; -reg csrbank5_clocker_divider0_we = 1'd0; -wire [8:0] csrbank5_clocker_divider0_w; -reg csrbank5_dataw_status_re = 1'd0; -wire [2:0] csrbank5_dataw_status_r; -reg csrbank5_dataw_status_we = 1'd0; -wire [2:0] csrbank5_dataw_status_w; -wire csrbank5_sel; -wire [13:0] csr_interconnect_adr; -wire csr_interconnect_we; -wire [31:0] csr_interconnect_dat_w; -wire [31:0] csr_interconnect_dat_r; -reg litesdcardcore_sdphyinit_state = 1'd0; -reg litesdcardcore_sdphyinit_next_state = 1'd0; -reg [7:0] init_count_sdphyinit_next_value = 8'd0; -reg init_count_sdphyinit_next_value_ce = 1'd0; -reg [1:0] litesdcardcore_sdphycmdw_state = 2'd0; -reg [1:0] litesdcardcore_sdphycmdw_next_state = 2'd0; -reg [7:0] cmdw_count_sdphycmdw_next_value = 8'd0; -reg cmdw_count_sdphycmdw_next_value_ce = 1'd0; -reg [2:0] litesdcardcore_sdphycmdr_state = 3'd0; -reg [2:0] litesdcardcore_sdphycmdr_next_state = 3'd0; -reg [31:0] cmdr_timeout_sdphycmdr_next_value0 = 32'd0; -reg cmdr_timeout_sdphycmdr_next_value_ce0 = 1'd0; -reg [7:0] cmdr_count_sdphycmdr_next_value1 = 8'd0; -reg cmdr_count_sdphycmdr_next_value_ce1 = 1'd0; -reg cmdr_busy_sdphycmdr_next_value2 = 1'd0; -reg cmdr_busy_sdphycmdr_next_value_ce2 = 1'd0; -reg cmdr_cmdr_reset_sdphycmdr_next_value3 = 1'd0; -reg cmdr_cmdr_reset_sdphycmdr_next_value_ce3 = 1'd0; -reg [2:0] litesdcardcore_sdphydataw_state = 3'd0; -reg [2:0] litesdcardcore_sdphydataw_next_state = 3'd0; -reg dataw_accepted1_sdphydataw_next_value0 = 1'd0; -reg dataw_accepted1_sdphydataw_next_value_ce0 = 1'd0; -reg dataw_crc_error1_sdphydataw_next_value1 = 1'd0; -reg dataw_crc_error1_sdphydataw_next_value_ce1 = 1'd0; -reg dataw_write_error1_sdphydataw_next_value2 = 1'd0; -reg dataw_write_error1_sdphydataw_next_value_ce2 = 1'd0; -reg [7:0] dataw_count_sdphydataw_next_value3 = 8'd0; -reg dataw_count_sdphydataw_next_value_ce3 = 1'd0; -reg [2:0] litesdcardcore_sdphydatar_state = 3'd0; -reg [2:0] litesdcardcore_sdphydatar_next_state = 3'd0; -reg [9:0] datar_count_sdphydatar_next_value0 = 10'd0; -reg datar_count_sdphydatar_next_value_ce0 = 1'd0; -reg [31:0] datar_timeout_sdphydatar_next_value1 = 32'd0; -reg datar_timeout_sdphydatar_next_value_ce1 = 1'd0; -reg datar_datar_reset_sdphydatar_next_value2 = 1'd0; -reg datar_datar_reset_sdphydatar_next_value_ce2 = 1'd0; -reg litesdcardcore_sdcore_crc16inserter_state = 1'd0; -reg litesdcardcore_sdcore_crc16inserter_next_state = 1'd0; -reg [2:0] sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value = 3'd0; -reg sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value_ce = 1'd0; -reg [2:0] litesdcardcore_sdcore_fsm_state = 3'd0; -reg [2:0] litesdcardcore_sdcore_fsm_next_state = 3'd0; -reg sdcore_cmd_done_sdcore_fsm_next_value0 = 1'd0; -reg sdcore_cmd_done_sdcore_fsm_next_value_ce0 = 1'd0; -reg sdcore_data_done_sdcore_fsm_next_value1 = 1'd0; -reg sdcore_data_done_sdcore_fsm_next_value_ce1 = 1'd0; -reg [2:0] sdcore_cmd_count_sdcore_fsm_next_value2 = 3'd0; -reg sdcore_cmd_count_sdcore_fsm_next_value_ce2 = 1'd0; -reg [31:0] sdcore_data_count_sdcore_fsm_next_value3 = 32'd0; -reg sdcore_data_count_sdcore_fsm_next_value_ce3 = 1'd0; -reg sdcore_cmd_error_sdcore_fsm_next_value4 = 1'd0; -reg sdcore_cmd_error_sdcore_fsm_next_value_ce4 = 1'd0; -reg sdcore_cmd_timeout_sdcore_fsm_next_value5 = 1'd0; -reg sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 = 1'd0; -reg sdcore_data_error_sdcore_fsm_next_value6 = 1'd0; -reg sdcore_data_error_sdcore_fsm_next_value_ce6 = 1'd0; -reg sdcore_data_timeout_sdcore_fsm_next_value7 = 1'd0; -reg sdcore_data_timeout_sdcore_fsm_next_value_ce7 = 1'd0; -reg [127:0] sdcore_cmd_response_status_sdcore_fsm_next_value8 = 128'd0; -reg sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 = 1'd0; -reg [1:0] litesdcardcore_sdblock2memdma_state = 2'd0; -reg [1:0] litesdcardcore_sdblock2memdma_next_state = 2'd0; -reg [31:0] sdblock2mem_wishbonedmawriter_offset_next_value = 32'd0; -reg sdblock2mem_wishbonedmawriter_offset_next_value_ce = 1'd0; -reg litesdcardcore_sdmem2blockdma_fsm_state = 1'd0; -reg litesdcardcore_sdmem2blockdma_fsm_next_state = 1'd0; -reg [31:0] sdmem2block_dma_data_sdmem2blockdma_fsm_next_value = 32'd0; -reg sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce = 1'd0; -reg [1:0] litesdcardcore_sdmem2blockdma_resetinserter_state = 2'd0; -reg [1:0] litesdcardcore_sdmem2blockdma_resetinserter_next_state = 2'd0; -reg [31:0] sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value = 32'd0; -reg sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce = 1'd0; -reg litesdcardcore_wishbone2csr_state = 1'd0; -reg litesdcardcore_wishbone2csr_next_state = 1'd0; -reg [31:0] array_muxed0 = 32'd0; -reg [31:0] array_muxed1 = 32'd0; -reg [3:0] array_muxed2 = 4'd0; -reg array_muxed3 = 1'd0; -reg array_muxed4 = 1'd0; -reg array_muxed5 = 1'd0; -reg [2:0] array_muxed6 = 3'd0; -reg [1:0] array_muxed7 = 2'd0; -wire inferedsdrtristate0__o; -reg inferedsdrtristate0_oe = 1'd0; -wire inferedsdrtristate0__i; -wire sdrio_clk; -wire inferedsdrtristate1__o; -reg inferedsdrtristate1_oe = 1'd0; -wire inferedsdrtristate1__i; -wire sdrio_clk_1; -wire inferedsdrtristate2__o; -reg inferedsdrtristate2_oe = 1'd0; -wire inferedsdrtristate2__i; -wire sdrio_clk_2; -wire inferedsdrtristate3__o; -reg inferedsdrtristate3_oe = 1'd0; -wire inferedsdrtristate3__i; -wire sdrio_clk_3; -wire inferedsdrtristate4__o; -reg inferedsdrtristate4_oe = 1'd0; -wire inferedsdrtristate4__i; -wire sdrio_clk_4; - -//------------------------------------------------------------------------------ -// Combinatorial Logic -//------------------------------------------------------------------------------ - -assign wb_ctrl_adr_1 = wb_ctrl_adr; -assign wb_ctrl_dat_w_1 = wb_ctrl_dat_w; -assign wb_ctrl_dat_r = wb_ctrl_dat_r_1; -assign wb_ctrl_sel_1 = wb_ctrl_sel; -assign wb_ctrl_cyc_1 = wb_ctrl_cyc; -assign wb_ctrl_stb_1 = wb_ctrl_stb; -assign wb_ctrl_ack = wb_ctrl_ack_1; -assign wb_ctrl_we_1 = wb_ctrl_we; -assign wb_ctrl_cti_1 = wb_ctrl_cti; -assign wb_ctrl_bte_1 = wb_ctrl_bte; -assign wb_ctrl_err = wb_ctrl_err_1; -assign wb_dma_adr = wb_dma_adr_1; -assign wb_dma_dat_w = wb_dma_dat_w_1; -assign wb_dma_dat_r_1 = wb_dma_dat_r; -assign wb_dma_sel = wb_dma_sel_1; -assign wb_dma_cyc = wb_dma_cyc_1; -assign wb_dma_stb = wb_dma_stb_1; -assign wb_dma_ack_1 = wb_dma_ack; -assign wb_dma_we = wb_dma_we_1; -assign wb_dma_cti = wb_dma_cti_1; -assign wb_dma_bte = wb_dma_bte_1; -assign wb_dma_err_1 = wb_dma_err; -assign sdblock2mem_sink_sink_valid0 = sdcore_source_source_valid0; -assign sdcore_source_source_ready0 = sdblock2mem_sink_sink_ready0; -assign sdblock2mem_sink_sink_first = sdcore_source_source_first0; -assign sdblock2mem_sink_sink_last0 = sdcore_source_source_last0; -assign sdblock2mem_sink_sink_payload_data0 = sdcore_source_source_payload_data0; -assign sdcore_sink_sink_valid0 = sdmem2block_source_source_valid0; -assign sdmem2block_source_source_ready0 = sdcore_sink_sink_ready0; -assign sdcore_sink_sink_first0 = sdmem2block_source_source_first0; -assign sdcore_sink_sink_last0 = sdmem2block_source_source_last0; -assign sdcore_sink_sink_payload_data0 = sdmem2block_source_source_payload_data0; -assign block2mem_dma_trigger = sdblock2mem_irq; -assign mem2block_dma_trigger = sdmem2block_irq; -assign card_detect_trigger = card_detect_irq; -assign cmd_done_trigger = sdcore_csrfield_done0; -assign irq = sdirq_irq; -assign sys_clk = clk; -assign por_clk = clk; -assign sys_rst = int_rst; -assign bus_errors_status = bus_errors; -assign card_detect_status0 = sdcard_cd; -assign sdpads_clk = ((((init_pads_out_payload_clk | cmdw_pads_out_payload_clk) | cmdr_pads_out_payload_clk) | dataw_pads_out_payload_clk) | datar_pads_out_payload_clk); -assign sdpads_cmd_oe = ((((init_pads_out_payload_cmd_oe | cmdw_pads_out_payload_cmd_oe) | cmdr_pads_out_payload_cmd_oe) | dataw_pads_out_payload_cmd_oe) | datar_pads_out_payload_cmd_oe); -assign sdpads_cmd_o = ((((init_pads_out_payload_cmd_o | cmdw_pads_out_payload_cmd_o) | cmdr_pads_out_payload_cmd_o) | dataw_pads_out_payload_cmd_o) | datar_pads_out_payload_cmd_o); -assign sdpads_data_oe = ((((init_pads_out_payload_data_oe | cmdw_pads_out_payload_data_oe) | cmdr_pads_out_payload_data_oe) | dataw_pads_out_payload_data_oe) | datar_pads_out_payload_data_oe); -assign sdpads_data_o = ((((init_pads_out_payload_data_o | cmdw_pads_out_payload_data_o) | cmdr_pads_out_payload_data_o) | dataw_pads_out_payload_data_o) | datar_pads_out_payload_data_o); -assign init_pads_out_ready = clocker_ce; -assign cmdw_pads_out_ready = clocker_ce; -assign cmdr_pads_out_ready = clocker_ce; -assign dataw_pads_out_ready = clocker_ce; -assign datar_pads_out_ready = clocker_ce; -assign clocker_clk_en = sdpads_clk; -assign init_pads_in_valid = sdpads_data_i_ce; -assign init_pads_in_payload_cmd_i = sdpads_cmd_i; -assign init_pads_in_payload_data_i = sdpads_data_i; -assign cmdw_pads_in_valid = sdpads_data_i_ce; -assign cmdw_pads_in_payload_cmd_i = sdpads_cmd_i; -assign cmdw_pads_in_payload_data_i = sdpads_data_i; -assign cmdr_pads_in_pads_in_valid = sdpads_data_i_ce; -assign cmdr_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; -assign cmdr_pads_in_pads_in_payload_data_i = sdpads_data_i; -assign dataw_pads_in_pads_in_valid = sdpads_data_i_ce; -assign dataw_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; -assign dataw_pads_in_pads_in_payload_data_i = sdpads_data_i; -assign datar_pads_in_pads_in_valid = sdpads_data_i_ce; -assign datar_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; -assign datar_pads_in_pads_in_payload_data_i = sdpads_data_i; -assign clocker_stop = (dataw_stop | datar_stop); -always @(*) begin - clocker_clk1 <= 1'd0; - case (clocker_storage) - 3'd4: begin - clocker_clk1 <= clocker_clks[1]; - end - 4'd8: begin - clocker_clk1 <= clocker_clks[2]; - end - 5'd16: begin - clocker_clk1 <= clocker_clks[3]; - end - 6'd32: begin - clocker_clk1 <= clocker_clks[4]; - end - 7'd64: begin - clocker_clk1 <= clocker_clks[5]; - end - 8'd128: begin - clocker_clk1 <= clocker_clks[6]; - end - 9'd256: begin - clocker_clk1 <= clocker_clks[7]; - end - default: begin - clocker_clk1 <= clocker_clks[0]; - end - endcase -end -assign clocker_ce = (clocker_clk1 & (~clocker_clk_d)); -always @(*) begin - clocker_ce_latched <= 1'd0; - if (clocker_clk_d) begin - clocker_ce_latched <= clocker_clk_en; - end else begin - clocker_ce_latched <= clocker_ce_delayed; - end -end -assign clocker_clk0 = ((~clocker_clk1) & clocker_ce_latched); -always @(*) begin - init_pads_out_payload_data_o <= 4'd0; - init_pads_out_payload_clk <= 1'd0; - litesdcardcore_sdphyinit_next_state <= 1'd0; - init_pads_out_payload_cmd_o <= 1'd0; - init_pads_out_payload_cmd_oe <= 1'd0; - init_count_sdphyinit_next_value <= 8'd0; - init_count_sdphyinit_next_value_ce <= 1'd0; - init_pads_out_payload_data_oe <= 1'd0; - litesdcardcore_sdphyinit_next_state <= litesdcardcore_sdphyinit_state; - case (litesdcardcore_sdphyinit_state) - 1'd1: begin - init_pads_out_payload_clk <= 1'd1; - init_pads_out_payload_cmd_oe <= 1'd1; - init_pads_out_payload_cmd_o <= 1'd1; - init_pads_out_payload_data_oe <= 1'd1; - init_pads_out_payload_data_o <= 4'd15; - if (init_pads_out_ready) begin - init_count_sdphyinit_next_value <= (init_count + 1'd1); - init_count_sdphyinit_next_value_ce <= 1'd1; - if ((init_count == 7'd79)) begin - litesdcardcore_sdphyinit_next_state <= 1'd0; - end - end - end - default: begin - init_count_sdphyinit_next_value <= 1'd0; - init_count_sdphyinit_next_value_ce <= 1'd1; - if (init_initialize_re) begin - litesdcardcore_sdphyinit_next_state <= 1'd1; - end - end - endcase -end -always @(*) begin - cmdw_done <= 1'd0; - litesdcardcore_sdphycmdw_next_state <= 2'd0; - cmdw_count_sdphycmdw_next_value <= 8'd0; - cmdw_pads_out_payload_clk <= 1'd0; - cmdw_count_sdphycmdw_next_value_ce <= 1'd0; - cmdw_pads_out_payload_cmd_o <= 1'd0; - cmdw_pads_out_payload_cmd_oe <= 1'd0; - cmdw_sink_ready <= 1'd0; - litesdcardcore_sdphycmdw_next_state <= litesdcardcore_sdphycmdw_state; - case (litesdcardcore_sdphycmdw_state) - 1'd1: begin - cmdw_pads_out_payload_clk <= 1'd1; - cmdw_pads_out_payload_cmd_oe <= 1'd1; - case (cmdw_count) - 1'd0: begin - cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[7]; - end - 1'd1: begin - cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[6]; - end - 2'd2: begin - cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[5]; - end - 2'd3: begin - cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[4]; - end - 3'd4: begin - cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[3]; - end - 3'd5: begin - cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[2]; - end - 3'd6: begin - cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[1]; - end - 3'd7: begin - cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[0]; - end - endcase - if (cmdw_pads_out_ready) begin - cmdw_count_sdphycmdw_next_value <= (cmdw_count + 1'd1); - cmdw_count_sdphycmdw_next_value_ce <= 1'd1; - if ((cmdw_count == 3'd7)) begin - if ((cmdw_sink_last & (cmdw_sink_payload_cmd_type == 1'd0))) begin - litesdcardcore_sdphycmdw_next_state <= 2'd2; - end else begin - cmdw_sink_ready <= 1'd1; - litesdcardcore_sdphycmdw_next_state <= 1'd0; - end - end - end - end - 2'd2: begin - cmdw_pads_out_payload_clk <= 1'd1; - cmdw_pads_out_payload_cmd_oe <= 1'd1; - cmdw_pads_out_payload_cmd_o <= 1'd1; - if (cmdw_pads_out_ready) begin - cmdw_count_sdphycmdw_next_value <= (cmdw_count + 1'd1); - cmdw_count_sdphycmdw_next_value_ce <= 1'd1; - if ((cmdw_count == 3'd7)) begin - cmdw_sink_ready <= 1'd1; - litesdcardcore_sdphycmdw_next_state <= 1'd0; - end - end - end - default: begin - cmdw_count_sdphycmdw_next_value <= 1'd0; - cmdw_count_sdphycmdw_next_value_ce <= 1'd1; - if ((cmdw_sink_valid & cmdw_pads_out_ready)) begin - litesdcardcore_sdphycmdw_next_state <= 1'd1; - end else begin - cmdw_done <= 1'd1; - end - end - endcase -end -assign cmdr_cmdr_pads_in_valid = cmdr_pads_in_pads_in_valid; -assign cmdr_pads_in_pads_in_ready = cmdr_cmdr_pads_in_ready; -assign cmdr_cmdr_pads_in_first = cmdr_pads_in_pads_in_first; -assign cmdr_cmdr_pads_in_last = cmdr_pads_in_pads_in_last; -assign cmdr_cmdr_pads_in_payload_clk = cmdr_pads_in_pads_in_payload_clk; -assign cmdr_cmdr_pads_in_payload_cmd_i = cmdr_pads_in_pads_in_payload_cmd_i; -assign cmdr_cmdr_pads_in_payload_cmd_o = cmdr_pads_in_pads_in_payload_cmd_o; -assign cmdr_cmdr_pads_in_payload_cmd_oe = cmdr_pads_in_pads_in_payload_cmd_oe; -assign cmdr_cmdr_pads_in_payload_data_i = cmdr_pads_in_pads_in_payload_data_i; -assign cmdr_cmdr_pads_in_payload_data_o = cmdr_pads_in_pads_in_payload_data_o; -assign cmdr_cmdr_pads_in_payload_data_oe = cmdr_pads_in_pads_in_payload_data_oe; -assign cmdr_cmdr_pads_in_payload_data_i_ce = cmdr_pads_in_pads_in_payload_data_i_ce; -assign cmdr_cmdr_start = (cmdr_cmdr_pads_in_payload_cmd_i == 1'd0); -assign cmdr_cmdr_converter_sink_valid = (cmdr_cmdr_pads_in_valid & (cmdr_cmdr_start | cmdr_cmdr_run)); -assign cmdr_cmdr_converter_sink_payload_data = cmdr_cmdr_pads_in_payload_cmd_i; -assign cmdr_cmdr_buf_sink_valid = cmdr_cmdr_source_source_valid1; -assign cmdr_cmdr_source_source_ready1 = cmdr_cmdr_buf_sink_ready; -assign cmdr_cmdr_buf_sink_first = cmdr_cmdr_source_source_first1; -assign cmdr_cmdr_buf_sink_last = cmdr_cmdr_source_source_last1; -assign cmdr_cmdr_buf_sink_payload_data = cmdr_cmdr_source_source_payload_data1; -assign cmdr_cmdr_source_source_valid0 = cmdr_cmdr_buf_source_valid; -assign cmdr_cmdr_buf_source_ready = cmdr_cmdr_source_source_ready0; -assign cmdr_cmdr_source_source_first0 = cmdr_cmdr_buf_source_first; -assign cmdr_cmdr_source_source_last0 = cmdr_cmdr_buf_source_last; -assign cmdr_cmdr_source_source_payload_data0 = cmdr_cmdr_buf_source_payload_data; -assign cmdr_cmdr_source_source_valid1 = cmdr_cmdr_converter_source_valid; -assign cmdr_cmdr_converter_source_ready = cmdr_cmdr_source_source_ready1; -assign cmdr_cmdr_source_source_first1 = cmdr_cmdr_converter_source_first; -assign cmdr_cmdr_source_source_last1 = cmdr_cmdr_converter_source_last; -assign cmdr_cmdr_source_source_payload_data1 = cmdr_cmdr_converter_source_payload_data; -assign cmdr_cmdr_converter_sink_ready = ((~cmdr_cmdr_converter_strobe_all) | cmdr_cmdr_converter_source_ready); -assign cmdr_cmdr_converter_source_valid = cmdr_cmdr_converter_strobe_all; -assign cmdr_cmdr_converter_load_part = (cmdr_cmdr_converter_sink_valid & cmdr_cmdr_converter_sink_ready); -assign cmdr_cmdr_buf_sink_ready = ((~cmdr_cmdr_buf_source_valid) | cmdr_cmdr_buf_source_ready); -always @(*) begin - litesdcardcore_sdphycmdr_next_state <= 3'd0; - cmdr_timeout_sdphycmdr_next_value0 <= 32'd0; - cmdr_pads_out_payload_clk <= 1'd0; - cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd0; - cmdr_pads_out_payload_cmd_o <= 1'd0; - cmdr_count_sdphycmdr_next_value1 <= 8'd0; - cmdr_pads_out_payload_cmd_oe <= 1'd0; - cmdr_count_sdphycmdr_next_value_ce1 <= 1'd0; - cmdr_cmdr_source_source_ready0 <= 1'd0; - cmdr_busy_sdphycmdr_next_value2 <= 1'd0; - cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd0; - cmdr_sink_ready <= 1'd0; - cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd0; - cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd0; - cmdr_source_valid <= 1'd0; - cmdr_source_last <= 1'd0; - cmdr_source_payload_data <= 8'd0; - cmdr_source_payload_status <= 3'd0; - litesdcardcore_sdphycmdr_next_state <= litesdcardcore_sdphycmdr_state; - case (litesdcardcore_sdphycmdr_state) - 1'd1: begin - cmdr_pads_out_payload_clk <= 1'd1; - cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd0; - cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd1; - if (cmdr_cmdr_source_source_valid0) begin - litesdcardcore_sdphycmdr_next_state <= 2'd2; - end - cmdr_timeout_sdphycmdr_next_value0 <= (cmdr_timeout - 1'd1); - cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; - if ((cmdr_timeout == 1'd0)) begin - litesdcardcore_sdphycmdr_next_state <= 3'd5; - end - end - 2'd2: begin - cmdr_pads_out_payload_clk <= 1'd1; - cmdr_source_valid <= cmdr_cmdr_source_source_valid0; - cmdr_source_payload_status <= 1'd0; - cmdr_source_last <= (cmdr_count == (cmdr_sink_payload_length - 1'd1)); - cmdr_source_payload_data <= cmdr_cmdr_source_source_payload_data0; - if ((cmdr_cmdr_source_source_valid0 & cmdr_source_ready)) begin - cmdr_cmdr_source_source_ready0 <= 1'd1; - cmdr_count_sdphycmdr_next_value1 <= (cmdr_count + 1'd1); - cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; - if (cmdr_source_last) begin - cmdr_sink_ready <= 1'd1; - if ((cmdr_sink_payload_cmd_type == 2'd3)) begin - cmdr_source_valid <= 1'd0; - cmdr_timeout_sdphycmdr_next_value0 <= 26'd48000000; - cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; - litesdcardcore_sdphycmdr_next_state <= 2'd3; - end else begin - if ((cmdr_sink_payload_data_type == 1'd0)) begin - cmdr_count_sdphycmdr_next_value1 <= 1'd0; - cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; - litesdcardcore_sdphycmdr_next_state <= 3'd4; - end else begin - litesdcardcore_sdphycmdr_next_state <= 1'd0; - end - end - end - end - cmdr_timeout_sdphycmdr_next_value0 <= (cmdr_timeout - 1'd1); - cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; - if ((cmdr_timeout == 1'd0)) begin - litesdcardcore_sdphycmdr_next_state <= 3'd5; - end - end - 2'd3: begin - cmdr_pads_out_payload_clk <= 1'd1; - if ((cmdr_pads_in_pads_in_valid & cmdr_pads_in_pads_in_payload_data_i[0])) begin - cmdr_busy_sdphycmdr_next_value2 <= 1'd0; - cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd1; - end - if ((~cmdr_busy)) begin - cmdr_source_valid <= 1'd1; - cmdr_source_last <= 1'd1; - cmdr_source_payload_status <= 1'd0; - if (cmdr_source_ready) begin - cmdr_count_sdphycmdr_next_value1 <= 1'd0; - cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; - litesdcardcore_sdphycmdr_next_state <= 3'd4; - end - end - cmdr_timeout_sdphycmdr_next_value0 <= (cmdr_timeout - 1'd1); - cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; - if ((cmdr_timeout == 1'd0)) begin - litesdcardcore_sdphycmdr_next_state <= 3'd5; - end - end - 3'd4: begin - cmdr_pads_out_payload_clk <= 1'd1; - cmdr_pads_out_payload_cmd_oe <= 1'd1; - cmdr_pads_out_payload_cmd_o <= 1'd1; - if (cmdr_pads_out_ready) begin - cmdr_count_sdphycmdr_next_value1 <= (cmdr_count + 1'd1); - cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; - if ((cmdr_count == 3'd7)) begin - litesdcardcore_sdphycmdr_next_state <= 1'd0; - end - end - end - 3'd5: begin - cmdr_sink_ready <= 1'd1; - cmdr_source_valid <= 1'd1; - cmdr_source_last <= 1'd1; - cmdr_source_payload_status <= 1'd1; - if (cmdr_source_ready) begin - litesdcardcore_sdphycmdr_next_state <= 1'd0; - end - end - default: begin - cmdr_timeout_sdphycmdr_next_value0 <= 26'd48000000; - cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; - cmdr_count_sdphycmdr_next_value1 <= 1'd0; - cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; - cmdr_busy_sdphycmdr_next_value2 <= 1'd1; - cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd1; - if (((cmdr_sink_valid & cmdr_pads_out_ready) & cmdw_done)) begin - cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd1; - cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd1; - litesdcardcore_sdphycmdr_next_state <= 1'd1; - end - end - endcase -end -assign dataw_accepted0 = dataw_accepted1; -assign dataw_crc_error0 = dataw_crc_error1; -assign dataw_write_error0 = dataw_write_error1; -assign dataw_crc_pads_in_valid = dataw_pads_in_pads_in_valid; -assign dataw_crc_pads_in_ready = dataw_pads_in_pads_in_ready; -assign dataw_crc_pads_in_first = dataw_pads_in_pads_in_first; -assign dataw_crc_pads_in_last = dataw_pads_in_pads_in_last; -assign dataw_crc_pads_in_payload_clk = dataw_pads_in_pads_in_payload_clk; -assign dataw_crc_pads_in_payload_cmd_i = dataw_pads_in_pads_in_payload_cmd_i; -assign dataw_crc_pads_in_payload_cmd_o = dataw_pads_in_pads_in_payload_cmd_o; -assign dataw_crc_pads_in_payload_cmd_oe = dataw_pads_in_pads_in_payload_cmd_oe; -assign dataw_crc_pads_in_payload_data_i = dataw_pads_in_pads_in_payload_data_i; -assign dataw_crc_pads_in_payload_data_o = dataw_pads_in_pads_in_payload_data_o; -assign dataw_crc_pads_in_payload_data_oe = dataw_pads_in_pads_in_payload_data_oe; -assign dataw_crc_pads_in_payload_data_i_ce = dataw_pads_in_pads_in_payload_data_i_ce; -assign dataw_crc_start = (dataw_crc_pads_in_payload_data_i[0] == 1'd0); -assign dataw_crc_converter_sink_valid = (dataw_crc_pads_in_valid & dataw_crc_run); -assign dataw_crc_converter_sink_payload_data = dataw_crc_pads_in_payload_data_i[0]; -assign dataw_crc_buf_sink_valid = dataw_crc_source_source_valid1; -assign dataw_crc_source_source_ready1 = dataw_crc_buf_sink_ready; -assign dataw_crc_buf_sink_first = dataw_crc_source_source_first1; -assign dataw_crc_buf_sink_last = dataw_crc_source_source_last1; -assign dataw_crc_buf_sink_payload_data = dataw_crc_source_source_payload_data1; -assign dataw_crc_source_source_valid0 = dataw_crc_buf_source_valid; -assign dataw_crc_buf_source_ready = dataw_crc_source_source_ready0; -assign dataw_crc_source_source_first0 = dataw_crc_buf_source_first; -assign dataw_crc_source_source_last0 = dataw_crc_buf_source_last; -assign dataw_crc_source_source_payload_data0 = dataw_crc_buf_source_payload_data; -assign dataw_crc_source_source_valid1 = dataw_crc_converter_source_valid; -assign dataw_crc_converter_source_ready = dataw_crc_source_source_ready1; -assign dataw_crc_source_source_first1 = dataw_crc_converter_source_first; -assign dataw_crc_source_source_last1 = dataw_crc_converter_source_last; -assign dataw_crc_source_source_payload_data1 = dataw_crc_converter_source_payload_data; -assign dataw_crc_converter_sink_ready = ((~dataw_crc_converter_strobe_all) | dataw_crc_converter_source_ready); -assign dataw_crc_converter_source_valid = dataw_crc_converter_strobe_all; -assign dataw_crc_converter_load_part = (dataw_crc_converter_sink_valid & dataw_crc_converter_sink_ready); -assign dataw_crc_buf_sink_ready = ((~dataw_crc_buf_source_valid) | dataw_crc_buf_source_ready); -always @(*) begin - litesdcardcore_sdphydataw_next_state <= 3'd0; - dataw_accepted1_sdphydataw_next_value0 <= 1'd0; - dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd0; - dataw_pads_out_payload_clk <= 1'd0; - dataw_crc_reset <= 1'd0; - dataw_crc_error1_sdphydataw_next_value1 <= 1'd0; - dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd0; - dataw_pads_out_payload_cmd_o <= 1'd0; - dataw_pads_out_payload_cmd_oe <= 1'd0; - dataw_write_error1_sdphydataw_next_value2 <= 1'd0; - dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd0; - dataw_pads_out_payload_data_o <= 4'd0; - dataw_pads_out_payload_data_oe <= 1'd0; - dataw_count_sdphydataw_next_value3 <= 8'd0; - dataw_count_sdphydataw_next_value_ce3 <= 1'd0; - dataw_sink_ready <= 1'd0; - dataw_stop <= 1'd0; - litesdcardcore_sdphydataw_next_state <= litesdcardcore_sdphydataw_state; - case (litesdcardcore_sdphydataw_state) - 1'd1: begin - dataw_pads_out_payload_clk <= 1'd1; - dataw_pads_out_payload_cmd_oe <= 1'd1; - dataw_pads_out_payload_cmd_o <= 1'd1; - if (dataw_pads_out_ready) begin - dataw_count_sdphydataw_next_value3 <= (dataw_count + 1'd1); - dataw_count_sdphydataw_next_value_ce3 <= 1'd1; - if ((dataw_count == 3'd7)) begin - dataw_count_sdphydataw_next_value3 <= 1'd0; - dataw_count_sdphydataw_next_value_ce3 <= 1'd1; - litesdcardcore_sdphydataw_next_state <= 2'd2; - end - end - end - 2'd2: begin - dataw_pads_out_payload_clk <= 1'd1; - dataw_pads_out_payload_data_oe <= 1'd1; - dataw_pads_out_payload_data_o <= 1'd0; - if (dataw_pads_out_ready) begin - litesdcardcore_sdphydataw_next_state <= 2'd3; - end - end - 2'd3: begin - dataw_stop <= (~dataw_sink_valid); - dataw_pads_out_payload_clk <= 1'd1; - dataw_pads_out_payload_data_oe <= 1'd1; - case (dataw_count) - 1'd0: begin - dataw_pads_out_payload_data_o <= dataw_sink_payload_data[7:4]; - end - 1'd1: begin - dataw_pads_out_payload_data_o <= dataw_sink_payload_data[3:0]; - end - endcase - if (dataw_pads_out_ready) begin - dataw_count_sdphydataw_next_value3 <= (dataw_count + 1'd1); - dataw_count_sdphydataw_next_value_ce3 <= 1'd1; - if ((dataw_count == 1'd1)) begin - dataw_count_sdphydataw_next_value3 <= 1'd0; - dataw_count_sdphydataw_next_value_ce3 <= 1'd1; - if (dataw_sink_last) begin - litesdcardcore_sdphydataw_next_state <= 3'd4; - end else begin - dataw_sink_ready <= 1'd1; - end - end - end - end - 3'd4: begin - dataw_pads_out_payload_clk <= 1'd1; - dataw_pads_out_payload_data_oe <= 1'd1; - dataw_pads_out_payload_data_o <= 4'd15; - if (dataw_pads_out_ready) begin - dataw_crc_reset <= 1'd1; - litesdcardcore_sdphydataw_next_state <= 3'd5; - end - end - 3'd5: begin - dataw_pads_out_payload_clk <= 1'd1; - if (dataw_crc_source_source_valid0) begin - dataw_accepted1_sdphydataw_next_value0 <= (dataw_crc_source_source_payload_data0[7:5] == 2'd2); - dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd1; - dataw_crc_error1_sdphydataw_next_value1 <= (dataw_crc_source_source_payload_data0[7:5] == 3'd5); - dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd1; - dataw_write_error1_sdphydataw_next_value2 <= (dataw_crc_source_source_payload_data0[7:5] == 3'd6); - dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd1; - litesdcardcore_sdphydataw_next_state <= 3'd6; - end - end - 3'd6: begin - dataw_pads_out_payload_clk <= 1'd1; - if ((dataw_pads_in_pads_in_valid & dataw_pads_in_pads_in_payload_data_i[0])) begin - dataw_sink_ready <= 1'd1; - litesdcardcore_sdphydataw_next_state <= 1'd0; - end - end - default: begin - dataw_accepted1_sdphydataw_next_value0 <= 1'd0; - dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd1; - dataw_crc_error1_sdphydataw_next_value1 <= 1'd0; - dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd1; - dataw_write_error1_sdphydataw_next_value2 <= 1'd0; - dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd1; - dataw_count_sdphydataw_next_value3 <= 1'd0; - dataw_count_sdphydataw_next_value_ce3 <= 1'd1; - if ((dataw_sink_valid & dataw_pads_out_ready)) begin - litesdcardcore_sdphydataw_next_state <= 1'd1; - end - end - endcase -end -assign datar_datar_pads_in_valid = datar_pads_in_pads_in_valid; -assign datar_pads_in_pads_in_ready = datar_datar_pads_in_ready; -assign datar_datar_pads_in_first = datar_pads_in_pads_in_first; -assign datar_datar_pads_in_last = datar_pads_in_pads_in_last; -assign datar_datar_pads_in_payload_clk = datar_pads_in_pads_in_payload_clk; -assign datar_datar_pads_in_payload_cmd_i = datar_pads_in_pads_in_payload_cmd_i; -assign datar_datar_pads_in_payload_cmd_o = datar_pads_in_pads_in_payload_cmd_o; -assign datar_datar_pads_in_payload_cmd_oe = datar_pads_in_pads_in_payload_cmd_oe; -assign datar_datar_pads_in_payload_data_i = datar_pads_in_pads_in_payload_data_i; -assign datar_datar_pads_in_payload_data_o = datar_pads_in_pads_in_payload_data_o; -assign datar_datar_pads_in_payload_data_oe = datar_pads_in_pads_in_payload_data_oe; -assign datar_datar_pads_in_payload_data_i_ce = datar_pads_in_pads_in_payload_data_i_ce; -assign datar_datar_start = (datar_datar_pads_in_payload_data_i[3:0] == 1'd0); -assign datar_datar_converter_sink_valid = (datar_datar_pads_in_valid & datar_datar_run); -assign datar_datar_converter_sink_payload_data = datar_datar_pads_in_payload_data_i[3:0]; -assign datar_datar_buf_sink_valid = datar_datar_source_source_valid1; -assign datar_datar_source_source_ready1 = datar_datar_buf_sink_ready; -assign datar_datar_buf_sink_first = datar_datar_source_source_first1; -assign datar_datar_buf_sink_last = datar_datar_source_source_last1; -assign datar_datar_buf_sink_payload_data = datar_datar_source_source_payload_data1; -assign datar_datar_source_source_valid0 = datar_datar_buf_source_valid; -assign datar_datar_buf_source_ready = datar_datar_source_source_ready0; -assign datar_datar_source_source_first0 = datar_datar_buf_source_first; -assign datar_datar_source_source_last0 = datar_datar_buf_source_last; -assign datar_datar_source_source_payload_data0 = datar_datar_buf_source_payload_data; -assign datar_datar_source_source_valid1 = datar_datar_converter_source_valid; -assign datar_datar_converter_source_ready = datar_datar_source_source_ready1; -assign datar_datar_source_source_first1 = datar_datar_converter_source_first; -assign datar_datar_source_source_last1 = datar_datar_converter_source_last; -assign datar_datar_source_source_payload_data1 = datar_datar_converter_source_payload_data; -assign datar_datar_converter_sink_ready = ((~datar_datar_converter_strobe_all) | datar_datar_converter_source_ready); -assign datar_datar_converter_source_valid = datar_datar_converter_strobe_all; -assign datar_datar_converter_load_part = (datar_datar_converter_sink_valid & datar_datar_converter_sink_ready); -assign datar_datar_buf_sink_ready = ((~datar_datar_buf_source_valid) | datar_datar_buf_source_ready); -always @(*) begin - datar_source_valid <= 1'd0; - datar_source_first <= 1'd0; - datar_source_last <= 1'd0; - datar_source_payload_data <= 8'd0; - datar_source_payload_status <= 3'd0; - datar_stop <= 1'd0; - litesdcardcore_sdphydatar_next_state <= 3'd0; - datar_count_sdphydatar_next_value0 <= 10'd0; - datar_count_sdphydatar_next_value_ce0 <= 1'd0; - datar_timeout_sdphydatar_next_value1 <= 32'd0; - datar_timeout_sdphydatar_next_value_ce1 <= 1'd0; - datar_datar_reset_sdphydatar_next_value2 <= 1'd0; - datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd0; - datar_pads_out_payload_clk <= 1'd0; - datar_datar_source_source_ready0 <= 1'd0; - datar_sink_ready <= 1'd0; - litesdcardcore_sdphydatar_next_state <= litesdcardcore_sdphydatar_state; - case (litesdcardcore_sdphydatar_state) - 1'd1: begin - datar_pads_out_payload_clk <= 1'd1; - datar_datar_reset_sdphydatar_next_value2 <= 1'd0; - datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd1; - datar_timeout_sdphydatar_next_value1 <= (datar_timeout - 1'd1); - datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; - if (datar_datar_source_source_valid0) begin - litesdcardcore_sdphydatar_next_state <= 2'd2; - end - datar_timeout_sdphydatar_next_value1 <= (datar_timeout - 1'd1); - datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; - if ((datar_timeout == 1'd0)) begin - datar_sink_ready <= 1'd1; - litesdcardcore_sdphydatar_next_state <= 3'd4; - end - end - 2'd2: begin - datar_pads_out_payload_clk <= 1'd1; - datar_source_valid <= datar_datar_source_source_valid0; - datar_source_payload_status <= 1'd0; - datar_source_first <= (datar_count == 1'd0); - datar_source_last <= (datar_count == ((datar_sink_payload_block_length + 4'd8) - 1'd1)); - datar_source_payload_data <= datar_datar_source_source_payload_data0; - if (datar_source_valid) begin - if (datar_source_ready) begin - datar_datar_source_source_ready0 <= 1'd1; - datar_count_sdphydatar_next_value0 <= (datar_count + 1'd1); - datar_count_sdphydatar_next_value_ce0 <= 1'd1; - if (datar_source_last) begin - datar_sink_ready <= 1'd1; - if (datar_sink_last) begin - datar_count_sdphydatar_next_value0 <= 1'd0; - datar_count_sdphydatar_next_value_ce0 <= 1'd1; - litesdcardcore_sdphydatar_next_state <= 2'd3; - end else begin - litesdcardcore_sdphydatar_next_state <= 1'd0; - end - end - end else begin - datar_stop <= 1'd1; - end - end - datar_timeout_sdphydatar_next_value1 <= (datar_timeout - 1'd1); - datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; - if ((datar_timeout == 1'd0)) begin - datar_sink_ready <= 1'd1; - litesdcardcore_sdphydatar_next_state <= 3'd4; - end - end - 2'd3: begin - datar_pads_out_payload_clk <= 1'd1; - if (datar_pads_out_ready) begin - datar_count_sdphydatar_next_value0 <= (datar_count + 1'd1); - datar_count_sdphydatar_next_value_ce0 <= 1'd1; - if ((datar_count == 6'd39)) begin - litesdcardcore_sdphydatar_next_state <= 1'd0; - end - end - end - 3'd4: begin - datar_source_valid <= 1'd1; - datar_source_payload_status <= 1'd1; - datar_source_last <= 1'd1; - if (datar_source_ready) begin - litesdcardcore_sdphydatar_next_state <= 1'd0; - end - end - default: begin - datar_count_sdphydatar_next_value0 <= 1'd0; - datar_count_sdphydatar_next_value_ce0 <= 1'd1; - if ((datar_sink_valid & datar_pads_out_ready)) begin - datar_pads_out_payload_clk <= 1'd1; - datar_timeout_sdphydatar_next_value1 <= 32'd48000000; - datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; - datar_count_sdphydatar_next_value0 <= 1'd0; - datar_count_sdphydatar_next_value_ce0 <= 1'd1; - datar_datar_reset_sdphydatar_next_value2 <= 1'd1; - datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd1; - litesdcardcore_sdphydatar_next_state <= 1'd1; - end - end - endcase -end -assign sdcore_crc16_inserter_sink_valid = sdcore_sink_sink_valid0; -assign sdcore_sink_sink_ready0 = sdcore_crc16_inserter_sink_ready; -assign sdcore_crc16_inserter_sink_first = sdcore_sink_sink_first0; -assign sdcore_crc16_inserter_sink_last = sdcore_sink_sink_last0; -assign sdcore_crc16_inserter_sink_payload_data = sdcore_sink_sink_payload_data0; -assign sdcore_source_source_valid0 = sdcore_source_source_valid1; -assign sdcore_source_source_ready1 = sdcore_source_source_ready0; -assign sdcore_source_source_first0 = sdcore_source_source_first1; -assign sdcore_source_source_last0 = sdcore_source_source_last1; -assign sdcore_source_source_payload_data0 = sdcore_source_source_payload_data1; -assign sdcore_cmd_type = sdcore_csrfield_cmd_type; -assign sdcore_data_type = sdcore_csrfield_data_type; -assign sdcore_cmd = sdcore_csrfield_cmd; -assign sdcore_csrfield_done0 = sdcore_cmd_done; -assign sdcore_csrfield_error0 = sdcore_cmd_error; -assign sdcore_csrfield_timeout0 = sdcore_cmd_timeout; -assign sdcore_csrfield_crc0 = 1'd0; -assign sdcore_csrfield_done1 = sdcore_data_done; -assign sdcore_csrfield_error1 = sdcore_data_error; -assign sdcore_csrfield_timeout1 = sdcore_data_timeout; -assign sdcore_csrfield_crc1 = 1'd0; -assign sdcore_crc7_inserter_din = {1'd0, 1'd1, sdcore_cmd, sdcore_cmd_argument_storage}; -assign sdcore_crc7_inserter_reset = 1'd1; -assign sdcore_crc7_inserter_enable = 1'd1; -assign sdcore_crc7_inserter_reg1 = {sdcore_crc7_inserter_reg0[5], sdcore_crc7_inserter_reg0[4], sdcore_crc7_inserter_reg0[3], (sdcore_crc7_inserter_reg0[2] ^ (sdcore_crc7_inserter_din[39] ^ sdcore_crc7_inserter_reg0[6])), sdcore_crc7_inserter_reg0[1], sdcore_crc7_inserter_reg0[0], (sdcore_crc7_inserter_din[39] ^ sdcore_crc7_inserter_reg0[6])}; -assign sdcore_crc7_inserter_reg2 = {sdcore_crc7_inserter_reg1[5], sdcore_crc7_inserter_reg1[4], sdcore_crc7_inserter_reg1[3], (sdcore_crc7_inserter_reg1[2] ^ (sdcore_crc7_inserter_din[38] ^ sdcore_crc7_inserter_reg1[6])), sdcore_crc7_inserter_reg1[1], sdcore_crc7_inserter_reg1[0], (sdcore_crc7_inserter_din[38] ^ sdcore_crc7_inserter_reg1[6])}; -assign sdcore_crc7_inserter_reg3 = {sdcore_crc7_inserter_reg2[5], sdcore_crc7_inserter_reg2[4], sdcore_crc7_inserter_reg2[3], (sdcore_crc7_inserter_reg2[2] ^ (sdcore_crc7_inserter_din[37] ^ sdcore_crc7_inserter_reg2[6])), sdcore_crc7_inserter_reg2[1], sdcore_crc7_inserter_reg2[0], (sdcore_crc7_inserter_din[37] ^ sdcore_crc7_inserter_reg2[6])}; -assign sdcore_crc7_inserter_reg4 = {sdcore_crc7_inserter_reg3[5], sdcore_crc7_inserter_reg3[4], sdcore_crc7_inserter_reg3[3], (sdcore_crc7_inserter_reg3[2] ^ (sdcore_crc7_inserter_din[36] ^ sdcore_crc7_inserter_reg3[6])), sdcore_crc7_inserter_reg3[1], sdcore_crc7_inserter_reg3[0], (sdcore_crc7_inserter_din[36] ^ sdcore_crc7_inserter_reg3[6])}; -assign sdcore_crc7_inserter_reg5 = {sdcore_crc7_inserter_reg4[5], sdcore_crc7_inserter_reg4[4], sdcore_crc7_inserter_reg4[3], (sdcore_crc7_inserter_reg4[2] ^ (sdcore_crc7_inserter_din[35] ^ sdcore_crc7_inserter_reg4[6])), sdcore_crc7_inserter_reg4[1], sdcore_crc7_inserter_reg4[0], (sdcore_crc7_inserter_din[35] ^ sdcore_crc7_inserter_reg4[6])}; -assign sdcore_crc7_inserter_reg6 = {sdcore_crc7_inserter_reg5[5], sdcore_crc7_inserter_reg5[4], sdcore_crc7_inserter_reg5[3], (sdcore_crc7_inserter_reg5[2] ^ (sdcore_crc7_inserter_din[34] ^ sdcore_crc7_inserter_reg5[6])), sdcore_crc7_inserter_reg5[1], sdcore_crc7_inserter_reg5[0], (sdcore_crc7_inserter_din[34] ^ sdcore_crc7_inserter_reg5[6])}; -assign sdcore_crc7_inserter_reg7 = {sdcore_crc7_inserter_reg6[5], sdcore_crc7_inserter_reg6[4], sdcore_crc7_inserter_reg6[3], (sdcore_crc7_inserter_reg6[2] ^ (sdcore_crc7_inserter_din[33] ^ sdcore_crc7_inserter_reg6[6])), sdcore_crc7_inserter_reg6[1], sdcore_crc7_inserter_reg6[0], (sdcore_crc7_inserter_din[33] ^ sdcore_crc7_inserter_reg6[6])}; -assign sdcore_crc7_inserter_reg8 = {sdcore_crc7_inserter_reg7[5], sdcore_crc7_inserter_reg7[4], sdcore_crc7_inserter_reg7[3], (sdcore_crc7_inserter_reg7[2] ^ (sdcore_crc7_inserter_din[32] ^ sdcore_crc7_inserter_reg7[6])), sdcore_crc7_inserter_reg7[1], sdcore_crc7_inserter_reg7[0], (sdcore_crc7_inserter_din[32] ^ sdcore_crc7_inserter_reg7[6])}; -assign sdcore_crc7_inserter_reg9 = {sdcore_crc7_inserter_reg8[5], sdcore_crc7_inserter_reg8[4], sdcore_crc7_inserter_reg8[3], (sdcore_crc7_inserter_reg8[2] ^ (sdcore_crc7_inserter_din[31] ^ sdcore_crc7_inserter_reg8[6])), sdcore_crc7_inserter_reg8[1], sdcore_crc7_inserter_reg8[0], (sdcore_crc7_inserter_din[31] ^ sdcore_crc7_inserter_reg8[6])}; -assign sdcore_crc7_inserter_reg10 = {sdcore_crc7_inserter_reg9[5], sdcore_crc7_inserter_reg9[4], sdcore_crc7_inserter_reg9[3], (sdcore_crc7_inserter_reg9[2] ^ (sdcore_crc7_inserter_din[30] ^ sdcore_crc7_inserter_reg9[6])), sdcore_crc7_inserter_reg9[1], sdcore_crc7_inserter_reg9[0], (sdcore_crc7_inserter_din[30] ^ sdcore_crc7_inserter_reg9[6])}; -assign sdcore_crc7_inserter_reg11 = {sdcore_crc7_inserter_reg10[5], sdcore_crc7_inserter_reg10[4], sdcore_crc7_inserter_reg10[3], (sdcore_crc7_inserter_reg10[2] ^ (sdcore_crc7_inserter_din[29] ^ sdcore_crc7_inserter_reg10[6])), sdcore_crc7_inserter_reg10[1], sdcore_crc7_inserter_reg10[0], (sdcore_crc7_inserter_din[29] ^ sdcore_crc7_inserter_reg10[6])}; -assign sdcore_crc7_inserter_reg12 = {sdcore_crc7_inserter_reg11[5], sdcore_crc7_inserter_reg11[4], sdcore_crc7_inserter_reg11[3], (sdcore_crc7_inserter_reg11[2] ^ (sdcore_crc7_inserter_din[28] ^ sdcore_crc7_inserter_reg11[6])), sdcore_crc7_inserter_reg11[1], sdcore_crc7_inserter_reg11[0], (sdcore_crc7_inserter_din[28] ^ sdcore_crc7_inserter_reg11[6])}; -assign sdcore_crc7_inserter_reg13 = {sdcore_crc7_inserter_reg12[5], sdcore_crc7_inserter_reg12[4], sdcore_crc7_inserter_reg12[3], (sdcore_crc7_inserter_reg12[2] ^ (sdcore_crc7_inserter_din[27] ^ sdcore_crc7_inserter_reg12[6])), sdcore_crc7_inserter_reg12[1], sdcore_crc7_inserter_reg12[0], (sdcore_crc7_inserter_din[27] ^ sdcore_crc7_inserter_reg12[6])}; -assign sdcore_crc7_inserter_reg14 = {sdcore_crc7_inserter_reg13[5], sdcore_crc7_inserter_reg13[4], sdcore_crc7_inserter_reg13[3], (sdcore_crc7_inserter_reg13[2] ^ (sdcore_crc7_inserter_din[26] ^ sdcore_crc7_inserter_reg13[6])), sdcore_crc7_inserter_reg13[1], sdcore_crc7_inserter_reg13[0], (sdcore_crc7_inserter_din[26] ^ sdcore_crc7_inserter_reg13[6])}; -assign sdcore_crc7_inserter_reg15 = {sdcore_crc7_inserter_reg14[5], sdcore_crc7_inserter_reg14[4], sdcore_crc7_inserter_reg14[3], (sdcore_crc7_inserter_reg14[2] ^ (sdcore_crc7_inserter_din[25] ^ sdcore_crc7_inserter_reg14[6])), sdcore_crc7_inserter_reg14[1], sdcore_crc7_inserter_reg14[0], (sdcore_crc7_inserter_din[25] ^ sdcore_crc7_inserter_reg14[6])}; -assign sdcore_crc7_inserter_reg16 = {sdcore_crc7_inserter_reg15[5], sdcore_crc7_inserter_reg15[4], sdcore_crc7_inserter_reg15[3], (sdcore_crc7_inserter_reg15[2] ^ (sdcore_crc7_inserter_din[24] ^ sdcore_crc7_inserter_reg15[6])), sdcore_crc7_inserter_reg15[1], sdcore_crc7_inserter_reg15[0], (sdcore_crc7_inserter_din[24] ^ sdcore_crc7_inserter_reg15[6])}; -assign sdcore_crc7_inserter_reg17 = {sdcore_crc7_inserter_reg16[5], sdcore_crc7_inserter_reg16[4], sdcore_crc7_inserter_reg16[3], (sdcore_crc7_inserter_reg16[2] ^ (sdcore_crc7_inserter_din[23] ^ sdcore_crc7_inserter_reg16[6])), sdcore_crc7_inserter_reg16[1], sdcore_crc7_inserter_reg16[0], (sdcore_crc7_inserter_din[23] ^ sdcore_crc7_inserter_reg16[6])}; -assign sdcore_crc7_inserter_reg18 = {sdcore_crc7_inserter_reg17[5], sdcore_crc7_inserter_reg17[4], sdcore_crc7_inserter_reg17[3], (sdcore_crc7_inserter_reg17[2] ^ (sdcore_crc7_inserter_din[22] ^ sdcore_crc7_inserter_reg17[6])), sdcore_crc7_inserter_reg17[1], sdcore_crc7_inserter_reg17[0], (sdcore_crc7_inserter_din[22] ^ sdcore_crc7_inserter_reg17[6])}; -assign sdcore_crc7_inserter_reg19 = {sdcore_crc7_inserter_reg18[5], sdcore_crc7_inserter_reg18[4], sdcore_crc7_inserter_reg18[3], (sdcore_crc7_inserter_reg18[2] ^ (sdcore_crc7_inserter_din[21] ^ sdcore_crc7_inserter_reg18[6])), sdcore_crc7_inserter_reg18[1], sdcore_crc7_inserter_reg18[0], (sdcore_crc7_inserter_din[21] ^ sdcore_crc7_inserter_reg18[6])}; -assign sdcore_crc7_inserter_reg20 = {sdcore_crc7_inserter_reg19[5], sdcore_crc7_inserter_reg19[4], sdcore_crc7_inserter_reg19[3], (sdcore_crc7_inserter_reg19[2] ^ (sdcore_crc7_inserter_din[20] ^ sdcore_crc7_inserter_reg19[6])), sdcore_crc7_inserter_reg19[1], sdcore_crc7_inserter_reg19[0], (sdcore_crc7_inserter_din[20] ^ sdcore_crc7_inserter_reg19[6])}; -assign sdcore_crc7_inserter_reg21 = {sdcore_crc7_inserter_reg20[5], sdcore_crc7_inserter_reg20[4], sdcore_crc7_inserter_reg20[3], (sdcore_crc7_inserter_reg20[2] ^ (sdcore_crc7_inserter_din[19] ^ sdcore_crc7_inserter_reg20[6])), sdcore_crc7_inserter_reg20[1], sdcore_crc7_inserter_reg20[0], (sdcore_crc7_inserter_din[19] ^ sdcore_crc7_inserter_reg20[6])}; -assign sdcore_crc7_inserter_reg22 = {sdcore_crc7_inserter_reg21[5], sdcore_crc7_inserter_reg21[4], sdcore_crc7_inserter_reg21[3], (sdcore_crc7_inserter_reg21[2] ^ (sdcore_crc7_inserter_din[18] ^ sdcore_crc7_inserter_reg21[6])), sdcore_crc7_inserter_reg21[1], sdcore_crc7_inserter_reg21[0], (sdcore_crc7_inserter_din[18] ^ sdcore_crc7_inserter_reg21[6])}; -assign sdcore_crc7_inserter_reg23 = {sdcore_crc7_inserter_reg22[5], sdcore_crc7_inserter_reg22[4], sdcore_crc7_inserter_reg22[3], (sdcore_crc7_inserter_reg22[2] ^ (sdcore_crc7_inserter_din[17] ^ sdcore_crc7_inserter_reg22[6])), sdcore_crc7_inserter_reg22[1], sdcore_crc7_inserter_reg22[0], (sdcore_crc7_inserter_din[17] ^ sdcore_crc7_inserter_reg22[6])}; -assign sdcore_crc7_inserter_reg24 = {sdcore_crc7_inserter_reg23[5], sdcore_crc7_inserter_reg23[4], sdcore_crc7_inserter_reg23[3], (sdcore_crc7_inserter_reg23[2] ^ (sdcore_crc7_inserter_din[16] ^ sdcore_crc7_inserter_reg23[6])), sdcore_crc7_inserter_reg23[1], sdcore_crc7_inserter_reg23[0], (sdcore_crc7_inserter_din[16] ^ sdcore_crc7_inserter_reg23[6])}; -assign sdcore_crc7_inserter_reg25 = {sdcore_crc7_inserter_reg24[5], sdcore_crc7_inserter_reg24[4], sdcore_crc7_inserter_reg24[3], (sdcore_crc7_inserter_reg24[2] ^ (sdcore_crc7_inserter_din[15] ^ sdcore_crc7_inserter_reg24[6])), sdcore_crc7_inserter_reg24[1], sdcore_crc7_inserter_reg24[0], (sdcore_crc7_inserter_din[15] ^ sdcore_crc7_inserter_reg24[6])}; -assign sdcore_crc7_inserter_reg26 = {sdcore_crc7_inserter_reg25[5], sdcore_crc7_inserter_reg25[4], sdcore_crc7_inserter_reg25[3], (sdcore_crc7_inserter_reg25[2] ^ (sdcore_crc7_inserter_din[14] ^ sdcore_crc7_inserter_reg25[6])), sdcore_crc7_inserter_reg25[1], sdcore_crc7_inserter_reg25[0], (sdcore_crc7_inserter_din[14] ^ sdcore_crc7_inserter_reg25[6])}; -assign sdcore_crc7_inserter_reg27 = {sdcore_crc7_inserter_reg26[5], sdcore_crc7_inserter_reg26[4], sdcore_crc7_inserter_reg26[3], (sdcore_crc7_inserter_reg26[2] ^ (sdcore_crc7_inserter_din[13] ^ sdcore_crc7_inserter_reg26[6])), sdcore_crc7_inserter_reg26[1], sdcore_crc7_inserter_reg26[0], (sdcore_crc7_inserter_din[13] ^ sdcore_crc7_inserter_reg26[6])}; -assign sdcore_crc7_inserter_reg28 = {sdcore_crc7_inserter_reg27[5], sdcore_crc7_inserter_reg27[4], sdcore_crc7_inserter_reg27[3], (sdcore_crc7_inserter_reg27[2] ^ (sdcore_crc7_inserter_din[12] ^ sdcore_crc7_inserter_reg27[6])), sdcore_crc7_inserter_reg27[1], sdcore_crc7_inserter_reg27[0], (sdcore_crc7_inserter_din[12] ^ sdcore_crc7_inserter_reg27[6])}; -assign sdcore_crc7_inserter_reg29 = {sdcore_crc7_inserter_reg28[5], sdcore_crc7_inserter_reg28[4], sdcore_crc7_inserter_reg28[3], (sdcore_crc7_inserter_reg28[2] ^ (sdcore_crc7_inserter_din[11] ^ sdcore_crc7_inserter_reg28[6])), sdcore_crc7_inserter_reg28[1], sdcore_crc7_inserter_reg28[0], (sdcore_crc7_inserter_din[11] ^ sdcore_crc7_inserter_reg28[6])}; -assign sdcore_crc7_inserter_reg30 = {sdcore_crc7_inserter_reg29[5], sdcore_crc7_inserter_reg29[4], sdcore_crc7_inserter_reg29[3], (sdcore_crc7_inserter_reg29[2] ^ (sdcore_crc7_inserter_din[10] ^ sdcore_crc7_inserter_reg29[6])), sdcore_crc7_inserter_reg29[1], sdcore_crc7_inserter_reg29[0], (sdcore_crc7_inserter_din[10] ^ sdcore_crc7_inserter_reg29[6])}; -assign sdcore_crc7_inserter_reg31 = {sdcore_crc7_inserter_reg30[5], sdcore_crc7_inserter_reg30[4], sdcore_crc7_inserter_reg30[3], (sdcore_crc7_inserter_reg30[2] ^ (sdcore_crc7_inserter_din[9] ^ sdcore_crc7_inserter_reg30[6])), sdcore_crc7_inserter_reg30[1], sdcore_crc7_inserter_reg30[0], (sdcore_crc7_inserter_din[9] ^ sdcore_crc7_inserter_reg30[6])}; -assign sdcore_crc7_inserter_reg32 = {sdcore_crc7_inserter_reg31[5], sdcore_crc7_inserter_reg31[4], sdcore_crc7_inserter_reg31[3], (sdcore_crc7_inserter_reg31[2] ^ (sdcore_crc7_inserter_din[8] ^ sdcore_crc7_inserter_reg31[6])), sdcore_crc7_inserter_reg31[1], sdcore_crc7_inserter_reg31[0], (sdcore_crc7_inserter_din[8] ^ sdcore_crc7_inserter_reg31[6])}; -assign sdcore_crc7_inserter_reg33 = {sdcore_crc7_inserter_reg32[5], sdcore_crc7_inserter_reg32[4], sdcore_crc7_inserter_reg32[3], (sdcore_crc7_inserter_reg32[2] ^ (sdcore_crc7_inserter_din[7] ^ sdcore_crc7_inserter_reg32[6])), sdcore_crc7_inserter_reg32[1], sdcore_crc7_inserter_reg32[0], (sdcore_crc7_inserter_din[7] ^ sdcore_crc7_inserter_reg32[6])}; -assign sdcore_crc7_inserter_reg34 = {sdcore_crc7_inserter_reg33[5], sdcore_crc7_inserter_reg33[4], sdcore_crc7_inserter_reg33[3], (sdcore_crc7_inserter_reg33[2] ^ (sdcore_crc7_inserter_din[6] ^ sdcore_crc7_inserter_reg33[6])), sdcore_crc7_inserter_reg33[1], sdcore_crc7_inserter_reg33[0], (sdcore_crc7_inserter_din[6] ^ sdcore_crc7_inserter_reg33[6])}; -assign sdcore_crc7_inserter_reg35 = {sdcore_crc7_inserter_reg34[5], sdcore_crc7_inserter_reg34[4], sdcore_crc7_inserter_reg34[3], (sdcore_crc7_inserter_reg34[2] ^ (sdcore_crc7_inserter_din[5] ^ sdcore_crc7_inserter_reg34[6])), sdcore_crc7_inserter_reg34[1], sdcore_crc7_inserter_reg34[0], (sdcore_crc7_inserter_din[5] ^ sdcore_crc7_inserter_reg34[6])}; -assign sdcore_crc7_inserter_reg36 = {sdcore_crc7_inserter_reg35[5], sdcore_crc7_inserter_reg35[4], sdcore_crc7_inserter_reg35[3], (sdcore_crc7_inserter_reg35[2] ^ (sdcore_crc7_inserter_din[4] ^ sdcore_crc7_inserter_reg35[6])), sdcore_crc7_inserter_reg35[1], sdcore_crc7_inserter_reg35[0], (sdcore_crc7_inserter_din[4] ^ sdcore_crc7_inserter_reg35[6])}; -assign sdcore_crc7_inserter_reg37 = {sdcore_crc7_inserter_reg36[5], sdcore_crc7_inserter_reg36[4], sdcore_crc7_inserter_reg36[3], (sdcore_crc7_inserter_reg36[2] ^ (sdcore_crc7_inserter_din[3] ^ sdcore_crc7_inserter_reg36[6])), sdcore_crc7_inserter_reg36[1], sdcore_crc7_inserter_reg36[0], (sdcore_crc7_inserter_din[3] ^ sdcore_crc7_inserter_reg36[6])}; -assign sdcore_crc7_inserter_reg38 = {sdcore_crc7_inserter_reg37[5], sdcore_crc7_inserter_reg37[4], sdcore_crc7_inserter_reg37[3], (sdcore_crc7_inserter_reg37[2] ^ (sdcore_crc7_inserter_din[2] ^ sdcore_crc7_inserter_reg37[6])), sdcore_crc7_inserter_reg37[1], sdcore_crc7_inserter_reg37[0], (sdcore_crc7_inserter_din[2] ^ sdcore_crc7_inserter_reg37[6])}; -assign sdcore_crc7_inserter_reg39 = {sdcore_crc7_inserter_reg38[5], sdcore_crc7_inserter_reg38[4], sdcore_crc7_inserter_reg38[3], (sdcore_crc7_inserter_reg38[2] ^ (sdcore_crc7_inserter_din[1] ^ sdcore_crc7_inserter_reg38[6])), sdcore_crc7_inserter_reg38[1], sdcore_crc7_inserter_reg38[0], (sdcore_crc7_inserter_din[1] ^ sdcore_crc7_inserter_reg38[6])}; -assign sdcore_crc7_inserter_reg40 = {sdcore_crc7_inserter_reg39[5], sdcore_crc7_inserter_reg39[4], sdcore_crc7_inserter_reg39[3], (sdcore_crc7_inserter_reg39[2] ^ (sdcore_crc7_inserter_din[0] ^ sdcore_crc7_inserter_reg39[6])), sdcore_crc7_inserter_reg39[1], sdcore_crc7_inserter_reg39[0], (sdcore_crc7_inserter_din[0] ^ sdcore_crc7_inserter_reg39[6])}; -always @(*) begin - sdcore_crc7_inserter_crc <= 7'd0; - if (sdcore_crc7_inserter_enable) begin - sdcore_crc7_inserter_crc <= sdcore_crc7_inserter_reg40; - end else begin - sdcore_crc7_inserter_crc <= sdcore_crc7_inserter_reg0; - end -end -assign sdcore_crc16_inserter_crc0_reset = ((sdcore_crc16_inserter_source_valid & sdcore_crc16_inserter_source_ready) & sdcore_crc16_inserter_source_last); -assign sdcore_crc16_inserter_crc0_enable = (sdcore_crc16_inserter_sink_valid & sdcore_crc16_inserter_sink_ready); -always @(*) begin - sdcore_crc16_inserter_crc0_din <= 2'd0; - sdcore_crc16_inserter_crc0_din[0] <= sdcore_crc16_inserter_sink_payload_data[0]; - sdcore_crc16_inserter_crc0_din[1] <= sdcore_crc16_inserter_sink_payload_data[4]; -end -assign sdcore_crc16_inserter_crc1_reset = ((sdcore_crc16_inserter_source_valid & sdcore_crc16_inserter_source_ready) & sdcore_crc16_inserter_source_last); -assign sdcore_crc16_inserter_crc1_enable = (sdcore_crc16_inserter_sink_valid & sdcore_crc16_inserter_sink_ready); -always @(*) begin - sdcore_crc16_inserter_crc1_din <= 2'd0; - sdcore_crc16_inserter_crc1_din[0] <= sdcore_crc16_inserter_sink_payload_data[1]; - sdcore_crc16_inserter_crc1_din[1] <= sdcore_crc16_inserter_sink_payload_data[5]; -end -assign sdcore_crc16_inserter_crc2_reset = ((sdcore_crc16_inserter_source_valid & sdcore_crc16_inserter_source_ready) & sdcore_crc16_inserter_source_last); -assign sdcore_crc16_inserter_crc2_enable = (sdcore_crc16_inserter_sink_valid & sdcore_crc16_inserter_sink_ready); -always @(*) begin - sdcore_crc16_inserter_crc2_din <= 2'd0; - sdcore_crc16_inserter_crc2_din[0] <= sdcore_crc16_inserter_sink_payload_data[2]; - sdcore_crc16_inserter_crc2_din[1] <= sdcore_crc16_inserter_sink_payload_data[6]; -end -assign sdcore_crc16_inserter_crc3_reset = ((sdcore_crc16_inserter_source_valid & sdcore_crc16_inserter_source_ready) & sdcore_crc16_inserter_source_last); -assign sdcore_crc16_inserter_crc3_enable = (sdcore_crc16_inserter_sink_valid & sdcore_crc16_inserter_sink_ready); -always @(*) begin - sdcore_crc16_inserter_crc3_din <= 2'd0; - sdcore_crc16_inserter_crc3_din[0] <= sdcore_crc16_inserter_sink_payload_data[3]; - sdcore_crc16_inserter_crc3_din[1] <= sdcore_crc16_inserter_sink_payload_data[7]; -end -assign sdcore_crc16_inserter_crc0_reg1 = {sdcore_crc16_inserter_crc0_reg0[14], sdcore_crc16_inserter_crc0_reg0[13], sdcore_crc16_inserter_crc0_reg0[12], (sdcore_crc16_inserter_crc0_reg0[11] ^ (sdcore_crc16_inserter_crc0_din[1] ^ sdcore_crc16_inserter_crc0_reg0[15])), sdcore_crc16_inserter_crc0_reg0[10], sdcore_crc16_inserter_crc0_reg0[9], sdcore_crc16_inserter_crc0_reg0[8], sdcore_crc16_inserter_crc0_reg0[7], sdcore_crc16_inserter_crc0_reg0[6], sdcore_crc16_inserter_crc0_reg0[5], (sdcore_crc16_inserter_crc0_reg0[4] ^ (sdcore_crc16_inserter_crc0_din[1] ^ sdcore_crc16_inserter_crc0_reg0[15])), sdcore_crc16_inserter_crc0_reg0[3], sdcore_crc16_inserter_crc0_reg0[2], sdcore_crc16_inserter_crc0_reg0[1], sdcore_crc16_inserter_crc0_reg0[0], (sdcore_crc16_inserter_crc0_din[1] ^ sdcore_crc16_inserter_crc0_reg0[15])}; -assign sdcore_crc16_inserter_crc0_reg2 = {sdcore_crc16_inserter_crc0_reg1[14], sdcore_crc16_inserter_crc0_reg1[13], sdcore_crc16_inserter_crc0_reg1[12], (sdcore_crc16_inserter_crc0_reg1[11] ^ (sdcore_crc16_inserter_crc0_din[0] ^ sdcore_crc16_inserter_crc0_reg1[15])), sdcore_crc16_inserter_crc0_reg1[10], sdcore_crc16_inserter_crc0_reg1[9], sdcore_crc16_inserter_crc0_reg1[8], sdcore_crc16_inserter_crc0_reg1[7], sdcore_crc16_inserter_crc0_reg1[6], sdcore_crc16_inserter_crc0_reg1[5], (sdcore_crc16_inserter_crc0_reg1[4] ^ (sdcore_crc16_inserter_crc0_din[0] ^ sdcore_crc16_inserter_crc0_reg1[15])), sdcore_crc16_inserter_crc0_reg1[3], sdcore_crc16_inserter_crc0_reg1[2], sdcore_crc16_inserter_crc0_reg1[1], sdcore_crc16_inserter_crc0_reg1[0], (sdcore_crc16_inserter_crc0_din[0] ^ sdcore_crc16_inserter_crc0_reg1[15])}; -always @(*) begin - sdcore_crc16_inserter_crc0_crc <= 16'd0; - if (sdcore_crc16_inserter_crc0_enable) begin - sdcore_crc16_inserter_crc0_crc <= sdcore_crc16_inserter_crc0_reg2; - end else begin - sdcore_crc16_inserter_crc0_crc <= sdcore_crc16_inserter_crc0_reg0; - end -end -assign sdcore_crc16_inserter_crc1_reg1 = {sdcore_crc16_inserter_crc1_reg0[14], sdcore_crc16_inserter_crc1_reg0[13], sdcore_crc16_inserter_crc1_reg0[12], (sdcore_crc16_inserter_crc1_reg0[11] ^ (sdcore_crc16_inserter_crc1_din[1] ^ sdcore_crc16_inserter_crc1_reg0[15])), sdcore_crc16_inserter_crc1_reg0[10], sdcore_crc16_inserter_crc1_reg0[9], sdcore_crc16_inserter_crc1_reg0[8], sdcore_crc16_inserter_crc1_reg0[7], sdcore_crc16_inserter_crc1_reg0[6], sdcore_crc16_inserter_crc1_reg0[5], (sdcore_crc16_inserter_crc1_reg0[4] ^ (sdcore_crc16_inserter_crc1_din[1] ^ sdcore_crc16_inserter_crc1_reg0[15])), sdcore_crc16_inserter_crc1_reg0[3], sdcore_crc16_inserter_crc1_reg0[2], sdcore_crc16_inserter_crc1_reg0[1], sdcore_crc16_inserter_crc1_reg0[0], (sdcore_crc16_inserter_crc1_din[1] ^ sdcore_crc16_inserter_crc1_reg0[15])}; -assign sdcore_crc16_inserter_crc1_reg2 = {sdcore_crc16_inserter_crc1_reg1[14], sdcore_crc16_inserter_crc1_reg1[13], sdcore_crc16_inserter_crc1_reg1[12], (sdcore_crc16_inserter_crc1_reg1[11] ^ (sdcore_crc16_inserter_crc1_din[0] ^ sdcore_crc16_inserter_crc1_reg1[15])), sdcore_crc16_inserter_crc1_reg1[10], sdcore_crc16_inserter_crc1_reg1[9], sdcore_crc16_inserter_crc1_reg1[8], sdcore_crc16_inserter_crc1_reg1[7], sdcore_crc16_inserter_crc1_reg1[6], sdcore_crc16_inserter_crc1_reg1[5], (sdcore_crc16_inserter_crc1_reg1[4] ^ (sdcore_crc16_inserter_crc1_din[0] ^ sdcore_crc16_inserter_crc1_reg1[15])), sdcore_crc16_inserter_crc1_reg1[3], sdcore_crc16_inserter_crc1_reg1[2], sdcore_crc16_inserter_crc1_reg1[1], sdcore_crc16_inserter_crc1_reg1[0], (sdcore_crc16_inserter_crc1_din[0] ^ sdcore_crc16_inserter_crc1_reg1[15])}; -always @(*) begin - sdcore_crc16_inserter_crc1_crc <= 16'd0; - if (sdcore_crc16_inserter_crc1_enable) begin - sdcore_crc16_inserter_crc1_crc <= sdcore_crc16_inserter_crc1_reg2; - end else begin - sdcore_crc16_inserter_crc1_crc <= sdcore_crc16_inserter_crc1_reg0; - end -end -assign sdcore_crc16_inserter_crc2_reg1 = {sdcore_crc16_inserter_crc2_reg0[14], sdcore_crc16_inserter_crc2_reg0[13], sdcore_crc16_inserter_crc2_reg0[12], (sdcore_crc16_inserter_crc2_reg0[11] ^ (sdcore_crc16_inserter_crc2_din[1] ^ sdcore_crc16_inserter_crc2_reg0[15])), sdcore_crc16_inserter_crc2_reg0[10], sdcore_crc16_inserter_crc2_reg0[9], sdcore_crc16_inserter_crc2_reg0[8], sdcore_crc16_inserter_crc2_reg0[7], sdcore_crc16_inserter_crc2_reg0[6], sdcore_crc16_inserter_crc2_reg0[5], (sdcore_crc16_inserter_crc2_reg0[4] ^ (sdcore_crc16_inserter_crc2_din[1] ^ sdcore_crc16_inserter_crc2_reg0[15])), sdcore_crc16_inserter_crc2_reg0[3], sdcore_crc16_inserter_crc2_reg0[2], sdcore_crc16_inserter_crc2_reg0[1], sdcore_crc16_inserter_crc2_reg0[0], (sdcore_crc16_inserter_crc2_din[1] ^ sdcore_crc16_inserter_crc2_reg0[15])}; -assign sdcore_crc16_inserter_crc2_reg2 = {sdcore_crc16_inserter_crc2_reg1[14], sdcore_crc16_inserter_crc2_reg1[13], sdcore_crc16_inserter_crc2_reg1[12], (sdcore_crc16_inserter_crc2_reg1[11] ^ (sdcore_crc16_inserter_crc2_din[0] ^ sdcore_crc16_inserter_crc2_reg1[15])), sdcore_crc16_inserter_crc2_reg1[10], sdcore_crc16_inserter_crc2_reg1[9], sdcore_crc16_inserter_crc2_reg1[8], sdcore_crc16_inserter_crc2_reg1[7], sdcore_crc16_inserter_crc2_reg1[6], sdcore_crc16_inserter_crc2_reg1[5], (sdcore_crc16_inserter_crc2_reg1[4] ^ (sdcore_crc16_inserter_crc2_din[0] ^ sdcore_crc16_inserter_crc2_reg1[15])), sdcore_crc16_inserter_crc2_reg1[3], sdcore_crc16_inserter_crc2_reg1[2], sdcore_crc16_inserter_crc2_reg1[1], sdcore_crc16_inserter_crc2_reg1[0], (sdcore_crc16_inserter_crc2_din[0] ^ sdcore_crc16_inserter_crc2_reg1[15])}; -always @(*) begin - sdcore_crc16_inserter_crc2_crc <= 16'd0; - if (sdcore_crc16_inserter_crc2_enable) begin - sdcore_crc16_inserter_crc2_crc <= sdcore_crc16_inserter_crc2_reg2; - end else begin - sdcore_crc16_inserter_crc2_crc <= sdcore_crc16_inserter_crc2_reg0; - end -end -assign sdcore_crc16_inserter_crc3_reg1 = {sdcore_crc16_inserter_crc3_reg0[14], sdcore_crc16_inserter_crc3_reg0[13], sdcore_crc16_inserter_crc3_reg0[12], (sdcore_crc16_inserter_crc3_reg0[11] ^ (sdcore_crc16_inserter_crc3_din[1] ^ sdcore_crc16_inserter_crc3_reg0[15])), sdcore_crc16_inserter_crc3_reg0[10], sdcore_crc16_inserter_crc3_reg0[9], sdcore_crc16_inserter_crc3_reg0[8], sdcore_crc16_inserter_crc3_reg0[7], sdcore_crc16_inserter_crc3_reg0[6], sdcore_crc16_inserter_crc3_reg0[5], (sdcore_crc16_inserter_crc3_reg0[4] ^ (sdcore_crc16_inserter_crc3_din[1] ^ sdcore_crc16_inserter_crc3_reg0[15])), sdcore_crc16_inserter_crc3_reg0[3], sdcore_crc16_inserter_crc3_reg0[2], sdcore_crc16_inserter_crc3_reg0[1], sdcore_crc16_inserter_crc3_reg0[0], (sdcore_crc16_inserter_crc3_din[1] ^ sdcore_crc16_inserter_crc3_reg0[15])}; -assign sdcore_crc16_inserter_crc3_reg2 = {sdcore_crc16_inserter_crc3_reg1[14], sdcore_crc16_inserter_crc3_reg1[13], sdcore_crc16_inserter_crc3_reg1[12], (sdcore_crc16_inserter_crc3_reg1[11] ^ (sdcore_crc16_inserter_crc3_din[0] ^ sdcore_crc16_inserter_crc3_reg1[15])), sdcore_crc16_inserter_crc3_reg1[10], sdcore_crc16_inserter_crc3_reg1[9], sdcore_crc16_inserter_crc3_reg1[8], sdcore_crc16_inserter_crc3_reg1[7], sdcore_crc16_inserter_crc3_reg1[6], sdcore_crc16_inserter_crc3_reg1[5], (sdcore_crc16_inserter_crc3_reg1[4] ^ (sdcore_crc16_inserter_crc3_din[0] ^ sdcore_crc16_inserter_crc3_reg1[15])), sdcore_crc16_inserter_crc3_reg1[3], sdcore_crc16_inserter_crc3_reg1[2], sdcore_crc16_inserter_crc3_reg1[1], sdcore_crc16_inserter_crc3_reg1[0], (sdcore_crc16_inserter_crc3_din[0] ^ sdcore_crc16_inserter_crc3_reg1[15])}; -always @(*) begin - sdcore_crc16_inserter_crc3_crc <= 16'd0; - if (sdcore_crc16_inserter_crc3_enable) begin - sdcore_crc16_inserter_crc3_crc <= sdcore_crc16_inserter_crc3_reg2; - end else begin - sdcore_crc16_inserter_crc3_crc <= sdcore_crc16_inserter_crc3_reg0; - end -end -always @(*) begin - sdcore_crc16_inserter_sink_ready <= 1'd0; - sdcore_crc16_inserter_source_valid <= 1'd0; - sdcore_crc16_inserter_source_first <= 1'd0; - sdcore_crc16_inserter_source_last <= 1'd0; - litesdcardcore_sdcore_crc16inserter_next_state <= 1'd0; - sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value <= 3'd0; - sdcore_crc16_inserter_source_payload_data <= 8'd0; - sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value_ce <= 1'd0; - litesdcardcore_sdcore_crc16inserter_next_state <= litesdcardcore_sdcore_crc16inserter_state; - case (litesdcardcore_sdcore_crc16inserter_state) - 1'd1: begin - sdcore_crc16_inserter_source_valid <= 1'd1; - sdcore_crc16_inserter_source_last <= (sdcore_crc16_inserter_count == 3'd7); - case (sdcore_crc16_inserter_count) - 1'd0: begin - sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[14]; - sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[14]; - sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[14]; - sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[14]; - sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[15]; - sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[15]; - sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[15]; - sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[15]; - end - 1'd1: begin - sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[12]; - sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[12]; - sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[12]; - sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[12]; - sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[13]; - sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[13]; - sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[13]; - sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[13]; - end - 2'd2: begin - sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[10]; - sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[10]; - sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[10]; - sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[10]; - sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[11]; - sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[11]; - sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[11]; - sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[11]; - end - 2'd3: begin - sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[8]; - sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[8]; - sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[8]; - sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[8]; - sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[9]; - sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[9]; - sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[9]; - sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[9]; - end - 3'd4: begin - sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[6]; - sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[6]; - sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[6]; - sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[6]; - sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[7]; - sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[7]; - sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[7]; - sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[7]; - end - 3'd5: begin - sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[4]; - sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[4]; - sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[4]; - sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[4]; - sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[5]; - sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[5]; - sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[5]; - sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[5]; - end - 3'd6: begin - sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[2]; - sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[2]; - sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[2]; - sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[2]; - sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[3]; - sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[3]; - sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[3]; - sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[3]; - end - 3'd7: begin - sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[0]; - sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[0]; - sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[0]; - sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[0]; - sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[1]; - sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[1]; - sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[1]; - sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[1]; - end - endcase - if ((sdcore_crc16_inserter_source_valid & sdcore_crc16_inserter_source_ready)) begin - sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value <= (sdcore_crc16_inserter_count + 1'd1); - sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value_ce <= 1'd1; - if (sdcore_crc16_inserter_source_last) begin - litesdcardcore_sdcore_crc16inserter_next_state <= 1'd0; - end - end - end - default: begin - sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value <= 1'd0; - sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value_ce <= 1'd1; - sdcore_crc16_inserter_source_valid <= sdcore_crc16_inserter_sink_valid; - sdcore_crc16_inserter_sink_ready <= sdcore_crc16_inserter_source_ready; - sdcore_crc16_inserter_source_first <= sdcore_crc16_inserter_sink_first; - sdcore_crc16_inserter_source_payload_data <= sdcore_crc16_inserter_sink_payload_data; - sdcore_crc16_inserter_source_last <= 1'd0; - if ((sdcore_crc16_inserter_sink_valid & sdcore_crc16_inserter_sink_ready)) begin - if (sdcore_crc16_inserter_sink_last) begin - litesdcardcore_sdcore_crc16inserter_next_state <= 1'd1; - end - end - end - endcase -end -assign sdcore_fifo_sink_valid = sdcore_sink_sink_valid1; -assign sdcore_sink_sink_ready1 = sdcore_fifo_sink_ready; -assign sdcore_fifo_sink_first = sdcore_sink_sink_first1; -assign sdcore_fifo_sink_last = sdcore_sink_sink_last1; -assign sdcore_fifo_sink_payload_data = sdcore_sink_sink_payload_data1; -assign sdcore_source_source_first1 = sdcore_fifo_source_first; -assign sdcore_source_source_last1 = sdcore_fifo_source_last; -assign sdcore_source_source_payload_data1 = sdcore_fifo_source_payload_data; -assign sdcore_source_source_valid1 = (sdcore_fifo_level >= 4'd8); -assign sdcore_fifo_source_ready = (sdcore_source_source_valid1 & sdcore_source_source_ready1); -assign sdcore_fifo_reset = ((sdcore_sink_sink_valid1 & sdcore_sink_sink_ready1) & sdcore_sink_sink_last1); -assign sdcore_fifo_syncfifo_din = {sdcore_fifo_fifo_in_last, sdcore_fifo_fifo_in_first, sdcore_fifo_fifo_in_payload_data}; -assign {sdcore_fifo_fifo_out_last, sdcore_fifo_fifo_out_first, sdcore_fifo_fifo_out_payload_data} = sdcore_fifo_syncfifo_dout; -assign sdcore_fifo_sink_ready = sdcore_fifo_syncfifo_writable; -assign sdcore_fifo_syncfifo_we = sdcore_fifo_sink_valid; -assign sdcore_fifo_fifo_in_first = sdcore_fifo_sink_first; -assign sdcore_fifo_fifo_in_last = sdcore_fifo_sink_last; -assign sdcore_fifo_fifo_in_payload_data = sdcore_fifo_sink_payload_data; -assign sdcore_fifo_source_valid = sdcore_fifo_syncfifo_readable; -assign sdcore_fifo_source_first = sdcore_fifo_fifo_out_first; -assign sdcore_fifo_source_last = sdcore_fifo_fifo_out_last; -assign sdcore_fifo_source_payload_data = sdcore_fifo_fifo_out_payload_data; -assign sdcore_fifo_syncfifo_re = sdcore_fifo_source_ready; -always @(*) begin - sdcore_fifo_wrport_adr <= 3'd0; - if (sdcore_fifo_replace) begin - sdcore_fifo_wrport_adr <= (sdcore_fifo_produce - 1'd1); - end else begin - sdcore_fifo_wrport_adr <= sdcore_fifo_produce; - end -end -assign sdcore_fifo_wrport_dat_w = sdcore_fifo_syncfifo_din; -assign sdcore_fifo_wrport_we = (sdcore_fifo_syncfifo_we & (sdcore_fifo_syncfifo_writable | sdcore_fifo_replace)); -assign sdcore_fifo_do_read = (sdcore_fifo_syncfifo_readable & sdcore_fifo_syncfifo_re); -assign sdcore_fifo_rdport_adr = sdcore_fifo_consume; -assign sdcore_fifo_syncfifo_dout = sdcore_fifo_rdport_dat_r; -assign sdcore_fifo_syncfifo_writable = (sdcore_fifo_level != 4'd8); -assign sdcore_fifo_syncfifo_readable = (sdcore_fifo_level != 1'd0); -always @(*) begin - cmdr_sink_valid <= 1'd0; - litesdcardcore_sdcore_fsm_next_state <= 3'd0; - sdcore_cmd_done_sdcore_fsm_next_value0 <= 1'd0; - cmdr_sink_payload_cmd_type <= 2'd0; - sdcore_cmd_done_sdcore_fsm_next_value_ce0 <= 1'd0; - cmdr_sink_payload_data_type <= 2'd0; - cmdr_sink_payload_length <= 8'd0; - sdcore_data_done_sdcore_fsm_next_value1 <= 1'd0; - sdcore_data_done_sdcore_fsm_next_value_ce1 <= 1'd0; - cmdr_source_ready <= 1'd0; - dataw_sink_valid <= 1'd0; - sdcore_cmd_count_sdcore_fsm_next_value2 <= 3'd0; - dataw_sink_first <= 1'd0; - sdcore_cmd_count_sdcore_fsm_next_value_ce2 <= 1'd0; - dataw_sink_last <= 1'd0; - dataw_sink_payload_data <= 8'd0; - sdcore_data_count_sdcore_fsm_next_value3 <= 32'd0; - sdcore_data_count_sdcore_fsm_next_value_ce3 <= 1'd0; - cmdw_sink_valid <= 1'd0; - datar_sink_valid <= 1'd0; - sdcore_cmd_error_sdcore_fsm_next_value4 <= 1'd0; - cmdw_sink_last <= 1'd0; - sdcore_cmd_error_sdcore_fsm_next_value_ce4 <= 1'd0; - cmdw_sink_payload_data <= 8'd0; - datar_sink_payload_block_length <= 10'd0; - cmdw_sink_payload_cmd_type <= 2'd0; - sdcore_cmd_timeout_sdcore_fsm_next_value5 <= 1'd0; - datar_source_ready <= 1'd0; - sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 <= 1'd0; - datar_sink_last <= 1'd0; - sdcore_crc16_inserter_source_ready <= 1'd0; - sdcore_data_error_sdcore_fsm_next_value6 <= 1'd0; - sdcore_data_error_sdcore_fsm_next_value_ce6 <= 1'd0; - sdcore_data_timeout_sdcore_fsm_next_value7 <= 1'd0; - sdcore_data_timeout_sdcore_fsm_next_value_ce7 <= 1'd0; - sdcore_sink_sink_valid1 <= 1'd0; - sdcore_sink_sink_first1 <= 1'd0; - sdcore_sink_sink_last1 <= 1'd0; - sdcore_sink_sink_payload_data1 <= 8'd0; - sdcore_cmd_response_status_sdcore_fsm_next_value8 <= 128'd0; - sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 <= 1'd0; - litesdcardcore_sdcore_fsm_next_state <= litesdcardcore_sdcore_fsm_state; - case (litesdcardcore_sdcore_fsm_state) - 1'd1: begin - cmdw_sink_valid <= 1'd1; - cmdw_sink_last <= (sdcore_cmd_count == 3'd5); - cmdw_sink_payload_cmd_type <= sdcore_cmd_type; - case (sdcore_cmd_count) - 1'd0: begin - cmdw_sink_payload_data <= {1'd0, 1'd1, sdcore_cmd}; - end - 1'd1: begin - cmdw_sink_payload_data <= sdcore_cmd_argument_storage[31:24]; - end - 2'd2: begin - cmdw_sink_payload_data <= sdcore_cmd_argument_storage[23:16]; - end - 2'd3: begin - cmdw_sink_payload_data <= sdcore_cmd_argument_storage[15:8]; - end - 3'd4: begin - cmdw_sink_payload_data <= sdcore_cmd_argument_storage[7:0]; - end - 3'd5: begin - cmdw_sink_payload_data <= {sdcore_crc7_inserter_crc, 1'd1}; - end - endcase - if (cmdw_sink_ready) begin - sdcore_cmd_count_sdcore_fsm_next_value2 <= (sdcore_cmd_count + 1'd1); - sdcore_cmd_count_sdcore_fsm_next_value_ce2 <= 1'd1; - if (cmdw_sink_last) begin - if ((sdcore_cmd_type == 1'd0)) begin - litesdcardcore_sdcore_fsm_next_state <= 1'd0; - end else begin - litesdcardcore_sdcore_fsm_next_state <= 2'd2; - end - end - end - end - 2'd2: begin - cmdr_sink_valid <= 1'd1; - cmdr_sink_payload_cmd_type <= sdcore_cmd_type; - cmdr_sink_payload_data_type <= sdcore_data_type; - if ((sdcore_cmd_type == 2'd2)) begin - cmdr_sink_payload_length <= 5'd18; - end else begin - cmdr_sink_payload_length <= 3'd6; - end - cmdr_source_ready <= 1'd1; - if (cmdr_source_valid) begin - if ((cmdr_source_payload_status == 1'd1)) begin - sdcore_cmd_timeout_sdcore_fsm_next_value5 <= 1'd1; - sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 <= 1'd1; - litesdcardcore_sdcore_fsm_next_state <= 1'd0; - end else begin - if (cmdr_source_last) begin - if ((sdcore_data_type == 2'd2)) begin - litesdcardcore_sdcore_fsm_next_state <= 2'd3; - end else begin - if ((sdcore_data_type == 1'd1)) begin - litesdcardcore_sdcore_fsm_next_state <= 3'd4; - end else begin - litesdcardcore_sdcore_fsm_next_state <= 1'd0; - end - end - end else begin - sdcore_cmd_response_status_sdcore_fsm_next_value8 <= {sdcore_cmd_response_status, cmdr_source_payload_data}; - sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 <= 1'd1; - end - end - end - end - 2'd3: begin - dataw_sink_valid <= sdcore_crc16_inserter_source_valid; - sdcore_crc16_inserter_source_ready <= dataw_sink_ready; - dataw_sink_first <= sdcore_crc16_inserter_source_first; - dataw_sink_last <= sdcore_crc16_inserter_source_last; - dataw_sink_payload_data <= sdcore_crc16_inserter_source_payload_data; - if (((dataw_sink_valid & dataw_sink_ready) & dataw_sink_last)) begin - sdcore_data_count_sdcore_fsm_next_value3 <= (sdcore_data_count + 1'd1); - sdcore_data_count_sdcore_fsm_next_value_ce3 <= 1'd1; - if ((sdcore_data_count == (sdcore_block_count_storage - 1'd1))) begin - litesdcardcore_sdcore_fsm_next_state <= 1'd0; - end - end - datar_source_ready <= 1'd1; - if (datar_source_valid) begin - if ((datar_source_payload_status != 2'd2)) begin - sdcore_data_error_sdcore_fsm_next_value6 <= 1'd1; - sdcore_data_error_sdcore_fsm_next_value_ce6 <= 1'd1; - end - end - end - 3'd4: begin - datar_sink_valid <= 1'd1; - datar_sink_payload_block_length <= sdcore_block_length_storage; - datar_sink_last <= (sdcore_data_count == (sdcore_block_count_storage - 1'd1)); - if (datar_source_valid) begin - if ((datar_source_payload_status == 1'd0)) begin - sdcore_sink_sink_valid1 <= datar_source_valid; - datar_source_ready <= sdcore_sink_sink_ready1; - sdcore_sink_sink_first1 <= datar_source_first; - sdcore_sink_sink_last1 <= datar_source_last; - sdcore_sink_sink_payload_data1 <= datar_source_payload_data; - if ((datar_source_last & datar_source_ready)) begin - sdcore_data_count_sdcore_fsm_next_value3 <= (sdcore_data_count + 1'd1); - sdcore_data_count_sdcore_fsm_next_value_ce3 <= 1'd1; - if ((sdcore_data_count == (sdcore_block_count_storage - 1'd1))) begin - litesdcardcore_sdcore_fsm_next_state <= 1'd0; - end - end - end else begin - if ((datar_source_payload_status == 1'd1)) begin - sdcore_data_timeout_sdcore_fsm_next_value7 <= 1'd1; - sdcore_data_timeout_sdcore_fsm_next_value_ce7 <= 1'd1; - datar_source_ready <= 1'd1; - litesdcardcore_sdcore_fsm_next_state <= 1'd0; - end - end - end - end - default: begin - sdcore_cmd_done_sdcore_fsm_next_value0 <= 1'd1; - sdcore_cmd_done_sdcore_fsm_next_value_ce0 <= 1'd1; - sdcore_data_done_sdcore_fsm_next_value1 <= 1'd1; - sdcore_data_done_sdcore_fsm_next_value_ce1 <= 1'd1; - sdcore_cmd_count_sdcore_fsm_next_value2 <= 1'd0; - sdcore_cmd_count_sdcore_fsm_next_value_ce2 <= 1'd1; - sdcore_data_count_sdcore_fsm_next_value3 <= 1'd0; - sdcore_data_count_sdcore_fsm_next_value_ce3 <= 1'd1; - if (sdcore_cmd_send_re) begin - sdcore_cmd_done_sdcore_fsm_next_value0 <= 1'd0; - sdcore_cmd_done_sdcore_fsm_next_value_ce0 <= 1'd1; - sdcore_cmd_error_sdcore_fsm_next_value4 <= 1'd0; - sdcore_cmd_error_sdcore_fsm_next_value_ce4 <= 1'd1; - sdcore_cmd_timeout_sdcore_fsm_next_value5 <= 1'd0; - sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 <= 1'd1; - sdcore_data_done_sdcore_fsm_next_value1 <= 1'd0; - sdcore_data_done_sdcore_fsm_next_value_ce1 <= 1'd1; - sdcore_data_error_sdcore_fsm_next_value6 <= 1'd0; - sdcore_data_error_sdcore_fsm_next_value_ce6 <= 1'd1; - sdcore_data_timeout_sdcore_fsm_next_value7 <= 1'd0; - sdcore_data_timeout_sdcore_fsm_next_value_ce7 <= 1'd1; - litesdcardcore_sdcore_fsm_next_state <= 1'd1; - end - end - endcase -end -assign sdblock2mem_start = (sdblock2mem_sink_sink_valid0 & sdblock2mem_sink_sink_first); -always @(*) begin - sdblock2mem_fifo_sink_first <= 1'd0; - sdblock2mem_fifo_sink_last <= 1'd0; - sdblock2mem_sink_sink_ready0 <= 1'd0; - sdblock2mem_fifo_sink_payload_data <= 8'd0; - sdblock2mem_fifo_sink_valid <= 1'd0; - if ((sdblock2mem_wishbonedmawriter_enable_storage & (sdblock2mem_start | sdblock2mem_connect))) begin - sdblock2mem_fifo_sink_valid <= sdblock2mem_sink_sink_valid0; - sdblock2mem_sink_sink_ready0 <= sdblock2mem_fifo_sink_ready; - sdblock2mem_fifo_sink_first <= sdblock2mem_sink_sink_first; - sdblock2mem_fifo_sink_last <= sdblock2mem_sink_sink_last0; - sdblock2mem_fifo_sink_payload_data <= sdblock2mem_sink_sink_payload_data0; - end else begin - sdblock2mem_sink_sink_ready0 <= 1'd1; - end -end -assign sdblock2mem_converter_sink_valid = sdblock2mem_fifo_source_valid; -assign sdblock2mem_fifo_source_ready = sdblock2mem_converter_sink_ready; -assign sdblock2mem_converter_sink_first = sdblock2mem_fifo_source_first; -assign sdblock2mem_converter_sink_last = sdblock2mem_fifo_source_last; -assign sdblock2mem_converter_sink_payload_data = sdblock2mem_fifo_source_payload_data; -assign sdblock2mem_wishbonedmawriter_sink_valid = sdblock2mem_source_source_valid; -assign sdblock2mem_source_source_ready = sdblock2mem_wishbonedmawriter_sink_ready; -assign sdblock2mem_wishbonedmawriter_sink_first = sdblock2mem_source_source_first; -assign sdblock2mem_wishbonedmawriter_sink_last = sdblock2mem_source_source_last; -assign sdblock2mem_wishbonedmawriter_sink_payload_data = sdblock2mem_source_source_payload_data; -assign sdblock2mem_fifo_syncfifo_din = {sdblock2mem_fifo_fifo_in_last, sdblock2mem_fifo_fifo_in_first, sdblock2mem_fifo_fifo_in_payload_data}; -assign {sdblock2mem_fifo_fifo_out_last, sdblock2mem_fifo_fifo_out_first, sdblock2mem_fifo_fifo_out_payload_data} = sdblock2mem_fifo_syncfifo_dout; -assign sdblock2mem_fifo_sink_ready = sdblock2mem_fifo_syncfifo_writable; -assign sdblock2mem_fifo_syncfifo_we = sdblock2mem_fifo_sink_valid; -assign sdblock2mem_fifo_fifo_in_first = sdblock2mem_fifo_sink_first; -assign sdblock2mem_fifo_fifo_in_last = sdblock2mem_fifo_sink_last; -assign sdblock2mem_fifo_fifo_in_payload_data = sdblock2mem_fifo_sink_payload_data; -assign sdblock2mem_fifo_source_valid = sdblock2mem_fifo_readable; -assign sdblock2mem_fifo_source_first = sdblock2mem_fifo_fifo_out_first; -assign sdblock2mem_fifo_source_last = sdblock2mem_fifo_fifo_out_last; -assign sdblock2mem_fifo_source_payload_data = sdblock2mem_fifo_fifo_out_payload_data; -assign sdblock2mem_fifo_re = sdblock2mem_fifo_source_ready; -assign sdblock2mem_fifo_syncfifo_re = (sdblock2mem_fifo_syncfifo_readable & ((~sdblock2mem_fifo_readable) | sdblock2mem_fifo_re)); -assign sdblock2mem_fifo_level1 = (sdblock2mem_fifo_level0 + sdblock2mem_fifo_readable); -always @(*) begin - sdblock2mem_fifo_wrport_adr <= 9'd0; - if (sdblock2mem_fifo_replace) begin - sdblock2mem_fifo_wrport_adr <= (sdblock2mem_fifo_produce - 1'd1); - end else begin - sdblock2mem_fifo_wrport_adr <= sdblock2mem_fifo_produce; - end -end -assign sdblock2mem_fifo_wrport_dat_w = sdblock2mem_fifo_syncfifo_din; -assign sdblock2mem_fifo_wrport_we = (sdblock2mem_fifo_syncfifo_we & (sdblock2mem_fifo_syncfifo_writable | sdblock2mem_fifo_replace)); -assign sdblock2mem_fifo_do_read = (sdblock2mem_fifo_syncfifo_readable & sdblock2mem_fifo_syncfifo_re); -assign sdblock2mem_fifo_rdport_adr = sdblock2mem_fifo_consume; -assign sdblock2mem_fifo_syncfifo_dout = sdblock2mem_fifo_rdport_dat_r; -assign sdblock2mem_fifo_rdport_re = sdblock2mem_fifo_do_read; -assign sdblock2mem_fifo_syncfifo_writable = (sdblock2mem_fifo_level0 != 10'd512); -assign sdblock2mem_fifo_syncfifo_readable = (sdblock2mem_fifo_level0 != 1'd0); -assign sdblock2mem_source_source_valid = sdblock2mem_converter_source_valid; -assign sdblock2mem_converter_source_ready = sdblock2mem_source_source_ready; -assign sdblock2mem_source_source_first = sdblock2mem_converter_source_first; -assign sdblock2mem_source_source_last = sdblock2mem_converter_source_last; -assign sdblock2mem_source_source_payload_data = sdblock2mem_converter_source_payload_data; -assign sdblock2mem_converter_sink_ready = ((~sdblock2mem_converter_strobe_all) | sdblock2mem_converter_source_ready); -assign sdblock2mem_converter_source_valid = sdblock2mem_converter_strobe_all; -assign sdblock2mem_converter_load_part = (sdblock2mem_converter_sink_valid & sdblock2mem_converter_sink_ready); -assign interface0_bus_stb = sdblock2mem_sink_sink_valid1; -assign interface0_bus_cyc = sdblock2mem_sink_sink_valid1; -assign interface0_bus_we = 1'd1; -assign interface0_bus_sel = 4'd15; -assign interface0_bus_adr = sdblock2mem_sink_sink_payload_address; -assign interface0_bus_dat_w = {sdblock2mem_sink_sink_payload_data1[7:0], sdblock2mem_sink_sink_payload_data1[15:8], sdblock2mem_sink_sink_payload_data1[23:16], sdblock2mem_sink_sink_payload_data1[31:24]}; -assign sdblock2mem_sink_sink_ready1 = interface0_bus_ack; -assign sdblock2mem_wishbonedmawriter_base = sdblock2mem_wishbonedmawriter_base_storage[63:2]; -assign sdblock2mem_wishbonedmawriter_length = sdblock2mem_wishbonedmawriter_length_storage[31:2]; -assign sdblock2mem_wishbonedmawriter_offset_status = sdblock2mem_wishbonedmawriter_offset; -assign sdblock2mem_wishbonedmawriter_reset = (~sdblock2mem_wishbonedmawriter_enable_storage); -always @(*) begin - sdblock2mem_sink_sink_payload_data1 <= 32'd0; - sdblock2mem_wishbonedmawriter_done_status <= 1'd0; - sdblock2mem_wishbonedmawriter_sink_ready <= 1'd0; - litesdcardcore_sdblock2memdma_next_state <= 2'd0; - sdblock2mem_sink_sink_valid1 <= 1'd0; - sdblock2mem_wishbonedmawriter_offset_next_value <= 32'd0; - sdblock2mem_wishbonedmawriter_offset_next_value_ce <= 1'd0; - sdblock2mem_sink_sink_last1 <= 1'd0; - sdblock2mem_sink_sink_payload_address <= 32'd0; - litesdcardcore_sdblock2memdma_next_state <= litesdcardcore_sdblock2memdma_state; - case (litesdcardcore_sdblock2memdma_state) - 1'd1: begin - sdblock2mem_sink_sink_valid1 <= sdblock2mem_wishbonedmawriter_sink_valid; - sdblock2mem_sink_sink_last1 <= (sdblock2mem_wishbonedmawriter_offset == (sdblock2mem_wishbonedmawriter_length - 1'd1)); - sdblock2mem_sink_sink_payload_address <= (sdblock2mem_wishbonedmawriter_base + sdblock2mem_wishbonedmawriter_offset); - sdblock2mem_sink_sink_payload_data1 <= sdblock2mem_wishbonedmawriter_sink_payload_data; - sdblock2mem_wishbonedmawriter_sink_ready <= sdblock2mem_sink_sink_ready1; - if ((sdblock2mem_wishbonedmawriter_sink_valid & sdblock2mem_wishbonedmawriter_sink_ready)) begin - sdblock2mem_wishbonedmawriter_offset_next_value <= (sdblock2mem_wishbonedmawriter_offset + 1'd1); - sdblock2mem_wishbonedmawriter_offset_next_value_ce <= 1'd1; - if (sdblock2mem_sink_sink_last1) begin - if (sdblock2mem_wishbonedmawriter_loop_storage) begin - sdblock2mem_wishbonedmawriter_offset_next_value <= 1'd0; - sdblock2mem_wishbonedmawriter_offset_next_value_ce <= 1'd1; - end else begin - litesdcardcore_sdblock2memdma_next_state <= 2'd2; - end - end - end - end - 2'd2: begin - sdblock2mem_wishbonedmawriter_done_status <= 1'd1; - end - default: begin - sdblock2mem_wishbonedmawriter_sink_ready <= 1'd1; - sdblock2mem_wishbonedmawriter_offset_next_value <= 1'd0; - sdblock2mem_wishbonedmawriter_offset_next_value_ce <= 1'd1; - litesdcardcore_sdblock2memdma_next_state <= 1'd1; - end - endcase -end -assign sdmem2block_converter_sink_valid = sdmem2block_dma_source_valid; -assign sdmem2block_dma_source_ready = sdmem2block_converter_sink_ready; -assign sdmem2block_converter_sink_first = sdmem2block_dma_source_first; -assign sdmem2block_converter_sink_last = sdmem2block_dma_source_last; -assign sdmem2block_converter_sink_payload_data = sdmem2block_dma_source_payload_data; -assign sdmem2block_fifo_sink_valid = sdmem2block_source_source_valid1; -assign sdmem2block_source_source_ready1 = sdmem2block_fifo_sink_ready; -assign sdmem2block_fifo_sink_first = sdmem2block_source_source_first1; -assign sdmem2block_fifo_sink_last = sdmem2block_source_source_last1; -assign sdmem2block_fifo_sink_payload_data = sdmem2block_source_source_payload_data1; -assign sdmem2block_source_source_valid0 = sdmem2block_fifo_source_valid; -assign sdmem2block_fifo_source_ready = sdmem2block_source_source_ready0; -assign sdmem2block_source_source_first0 = sdmem2block_fifo_source_first; -assign sdmem2block_source_source_payload_data0 = sdmem2block_fifo_source_payload_data; -always @(*) begin - sdmem2block_source_source_last0 <= 1'd0; - sdmem2block_source_source_last0 <= sdmem2block_fifo_source_last; - if ((sdmem2block_count == 9'd511)) begin - sdmem2block_source_source_last0 <= 1'd1; - end -end -assign sdmem2block_dma_base = sdmem2block_dma_base_storage[63:2]; -assign sdmem2block_dma_length = sdmem2block_dma_length_storage[31:2]; -assign sdmem2block_dma_offset_status = sdmem2block_dma_offset; -assign sdmem2block_dma_reset = (~sdmem2block_dma_enable_storage); -always @(*) begin - interface1_bus_sel <= 4'd0; - interface1_bus_cyc <= 1'd0; - interface1_bus_stb <= 1'd0; - sdmem2block_dma_source_valid <= 1'd0; - interface1_bus_we <= 1'd0; - sdmem2block_dma_source_last <= 1'd0; - litesdcardcore_sdmem2blockdma_fsm_next_state <= 1'd0; - sdmem2block_dma_source_payload_data <= 32'd0; - sdmem2block_dma_data_sdmem2blockdma_fsm_next_value <= 32'd0; - sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce <= 1'd0; - interface1_bus_adr <= 32'd0; - sdmem2block_dma_sink_ready <= 1'd0; - litesdcardcore_sdmem2blockdma_fsm_next_state <= litesdcardcore_sdmem2blockdma_fsm_state; - case (litesdcardcore_sdmem2blockdma_fsm_state) - 1'd1: begin - sdmem2block_dma_source_valid <= 1'd1; - sdmem2block_dma_source_last <= sdmem2block_dma_sink_last; - sdmem2block_dma_source_payload_data <= sdmem2block_dma_data; - if (sdmem2block_dma_source_ready) begin - sdmem2block_dma_sink_ready <= 1'd1; - litesdcardcore_sdmem2blockdma_fsm_next_state <= 1'd0; - end - end - default: begin - interface1_bus_stb <= sdmem2block_dma_sink_valid; - interface1_bus_cyc <= sdmem2block_dma_sink_valid; - interface1_bus_we <= 1'd0; - interface1_bus_sel <= 4'd15; - interface1_bus_adr <= sdmem2block_dma_sink_payload_address; - if ((interface1_bus_stb & interface1_bus_ack)) begin - sdmem2block_dma_data_sdmem2blockdma_fsm_next_value <= {interface1_bus_dat_r[7:0], interface1_bus_dat_r[15:8], interface1_bus_dat_r[23:16], interface1_bus_dat_r[31:24]}; - sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce <= 1'd1; - litesdcardcore_sdmem2blockdma_fsm_next_state <= 1'd1; - end - end - endcase -end -always @(*) begin - sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value <= 32'd0; - sdmem2block_dma_sink_last <= 1'd0; - sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce <= 1'd0; - sdmem2block_dma_sink_payload_address <= 32'd0; - sdmem2block_dma_sink_valid <= 1'd0; - sdmem2block_dma_done_status <= 1'd0; - litesdcardcore_sdmem2blockdma_resetinserter_next_state <= 2'd0; - litesdcardcore_sdmem2blockdma_resetinserter_next_state <= litesdcardcore_sdmem2blockdma_resetinserter_state; - case (litesdcardcore_sdmem2blockdma_resetinserter_state) - 1'd1: begin - sdmem2block_dma_sink_valid <= 1'd1; - sdmem2block_dma_sink_last <= (sdmem2block_dma_offset == (sdmem2block_dma_length - 1'd1)); - sdmem2block_dma_sink_payload_address <= (sdmem2block_dma_base + sdmem2block_dma_offset); - if (sdmem2block_dma_sink_ready) begin - sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value <= (sdmem2block_dma_offset + 1'd1); - sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce <= 1'd1; - if (sdmem2block_dma_sink_last) begin - if (sdmem2block_dma_loop_storage) begin - sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value <= 1'd0; - sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce <= 1'd1; - end else begin - litesdcardcore_sdmem2blockdma_resetinserter_next_state <= 2'd2; - end - end - end - end - 2'd2: begin - sdmem2block_dma_done_status <= 1'd1; - end - default: begin - sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value <= 1'd0; - sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce <= 1'd1; - litesdcardcore_sdmem2blockdma_resetinserter_next_state <= 1'd1; - end - endcase -end -assign sdmem2block_source_source_valid1 = sdmem2block_converter_source_valid; -assign sdmem2block_converter_source_ready = sdmem2block_source_source_ready1; -assign sdmem2block_source_source_first1 = sdmem2block_converter_source_first; -assign sdmem2block_source_source_last1 = sdmem2block_converter_source_last; -assign sdmem2block_source_source_payload_data1 = sdmem2block_converter_source_payload_data; -assign sdmem2block_converter_first = (sdmem2block_converter_mux == 1'd0); -assign sdmem2block_converter_last = (sdmem2block_converter_mux == 2'd3); -assign sdmem2block_converter_source_valid = sdmem2block_converter_sink_valid; -assign sdmem2block_converter_source_first = (sdmem2block_converter_sink_first & sdmem2block_converter_first); -assign sdmem2block_converter_source_last = (sdmem2block_converter_sink_last & sdmem2block_converter_last); -assign sdmem2block_converter_sink_ready = (sdmem2block_converter_last & sdmem2block_converter_source_ready); -always @(*) begin - sdmem2block_converter_source_payload_data <= 8'd0; - case (sdmem2block_converter_mux) - 1'd0: begin - sdmem2block_converter_source_payload_data <= sdmem2block_converter_sink_payload_data[31:24]; - end - 1'd1: begin - sdmem2block_converter_source_payload_data <= sdmem2block_converter_sink_payload_data[23:16]; - end - 2'd2: begin - sdmem2block_converter_source_payload_data <= sdmem2block_converter_sink_payload_data[15:8]; - end - default: begin - sdmem2block_converter_source_payload_data <= sdmem2block_converter_sink_payload_data[7:0]; - end - endcase -end -assign sdmem2block_converter_source_payload_valid_token_count = sdmem2block_converter_last; -assign sdmem2block_fifo_syncfifo_din = {sdmem2block_fifo_fifo_in_last, sdmem2block_fifo_fifo_in_first, sdmem2block_fifo_fifo_in_payload_data}; -assign {sdmem2block_fifo_fifo_out_last, sdmem2block_fifo_fifo_out_first, sdmem2block_fifo_fifo_out_payload_data} = sdmem2block_fifo_syncfifo_dout; -assign sdmem2block_fifo_sink_ready = sdmem2block_fifo_syncfifo_writable; -assign sdmem2block_fifo_syncfifo_we = sdmem2block_fifo_sink_valid; -assign sdmem2block_fifo_fifo_in_first = sdmem2block_fifo_sink_first; -assign sdmem2block_fifo_fifo_in_last = sdmem2block_fifo_sink_last; -assign sdmem2block_fifo_fifo_in_payload_data = sdmem2block_fifo_sink_payload_data; -assign sdmem2block_fifo_source_valid = sdmem2block_fifo_readable; -assign sdmem2block_fifo_source_first = sdmem2block_fifo_fifo_out_first; -assign sdmem2block_fifo_source_last = sdmem2block_fifo_fifo_out_last; -assign sdmem2block_fifo_source_payload_data = sdmem2block_fifo_fifo_out_payload_data; -assign sdmem2block_fifo_re = sdmem2block_fifo_source_ready; -assign sdmem2block_fifo_syncfifo_re = (sdmem2block_fifo_syncfifo_readable & ((~sdmem2block_fifo_readable) | sdmem2block_fifo_re)); -assign sdmem2block_fifo_level1 = (sdmem2block_fifo_level0 + sdmem2block_fifo_readable); -always @(*) begin - sdmem2block_fifo_wrport_adr <= 9'd0; - if (sdmem2block_fifo_replace) begin - sdmem2block_fifo_wrport_adr <= (sdmem2block_fifo_produce - 1'd1); - end else begin - sdmem2block_fifo_wrport_adr <= sdmem2block_fifo_produce; - end -end -assign sdmem2block_fifo_wrport_dat_w = sdmem2block_fifo_syncfifo_din; -assign sdmem2block_fifo_wrport_we = (sdmem2block_fifo_syncfifo_we & (sdmem2block_fifo_syncfifo_writable | sdmem2block_fifo_replace)); -assign sdmem2block_fifo_do_read = (sdmem2block_fifo_syncfifo_readable & sdmem2block_fifo_syncfifo_re); -assign sdmem2block_fifo_rdport_adr = sdmem2block_fifo_consume; -assign sdmem2block_fifo_syncfifo_dout = sdmem2block_fifo_rdport_dat_r; -assign sdmem2block_fifo_rdport_re = sdmem2block_fifo_do_read; -assign sdmem2block_fifo_syncfifo_writable = (sdmem2block_fifo_level0 != 10'd512); -assign sdmem2block_fifo_syncfifo_readable = (sdmem2block_fifo_level0 != 1'd0); -assign eventmanager_card_detect0 = card_detect_status1; -assign eventmanager_card_detect1 = card_detect_pending; -always @(*) begin - card_detect_clear <= 1'd0; - if ((eventmanager_pending_re & eventmanager_pending_r[0])) begin - card_detect_clear <= 1'd1; - end -end -assign eventmanager_block2mem_dma0 = block2mem_dma_status; -assign eventmanager_block2mem_dma1 = block2mem_dma_pending; -always @(*) begin - block2mem_dma_clear <= 1'd0; - if ((eventmanager_pending_re & eventmanager_pending_r[1])) begin - block2mem_dma_clear <= 1'd1; - end -end -assign eventmanager_mem2block_dma0 = mem2block_dma_status; -assign eventmanager_mem2block_dma1 = mem2block_dma_pending; -always @(*) begin - mem2block_dma_clear <= 1'd0; - if ((eventmanager_pending_re & eventmanager_pending_r[2])) begin - mem2block_dma_clear <= 1'd1; - end -end -assign eventmanager_cmd_done0 = cmd_done_status; -assign eventmanager_cmd_done1 = cmd_done_pending; -always @(*) begin - cmd_done_clear <= 1'd0; - if ((eventmanager_pending_re & eventmanager_pending_r[3])) begin - cmd_done_clear <= 1'd1; - end -end -assign sdirq_irq = ((((eventmanager_pending_status[0] & eventmanager_enable_storage[0]) | (eventmanager_pending_status[1] & eventmanager_enable_storage[1])) | (eventmanager_pending_status[2] & eventmanager_enable_storage[2])) | (eventmanager_pending_status[3] & eventmanager_enable_storage[3])); -assign card_detect_status1 = 1'd0; -assign block2mem_dma_status = 1'd0; -assign mem2block_dma_status = 1'd0; -assign cmd_done_status = cmd_done_trigger; -assign cmd_done_pending = cmd_done_trigger; -always @(*) begin - litesdcardcore_wishbone_dat_r <= 32'd0; - litesdcardcore_wishbone2csr_next_state <= 1'd0; - litesdcardcore_we <= 1'd0; - litesdcardcore_adr <= 14'd0; - litesdcardcore_wishbone_ack <= 1'd0; - litesdcardcore_dat_w <= 32'd0; - litesdcardcore_wishbone2csr_next_state <= litesdcardcore_wishbone2csr_state; - case (litesdcardcore_wishbone2csr_state) - 1'd1: begin - litesdcardcore_wishbone_ack <= 1'd1; - litesdcardcore_wishbone_dat_r <= litesdcardcore_dat_r; - litesdcardcore_wishbone2csr_next_state <= 1'd0; - end - default: begin - litesdcardcore_dat_w <= litesdcardcore_wishbone_dat_w; - if ((litesdcardcore_wishbone_cyc & litesdcardcore_wishbone_stb)) begin - litesdcardcore_adr <= litesdcardcore_wishbone_adr; - litesdcardcore_we <= (litesdcardcore_wishbone_we & (litesdcardcore_wishbone_sel != 1'd0)); - litesdcardcore_wishbone2csr_next_state <= 1'd1; - end - end - endcase -end -assign litesdcardcore_wishbone_adr = wb_ctrl_adr_1; -assign litesdcardcore_wishbone_dat_w = wb_ctrl_dat_w_1; -assign wb_ctrl_dat_r_1 = litesdcardcore_wishbone_dat_r; -assign litesdcardcore_wishbone_sel = wb_ctrl_sel_1; -assign litesdcardcore_wishbone_cyc = wb_ctrl_cyc_1; -assign litesdcardcore_wishbone_stb = wb_ctrl_stb_1; -assign wb_ctrl_ack_1 = litesdcardcore_wishbone_ack; -assign litesdcardcore_wishbone_we = wb_ctrl_we_1; -assign litesdcardcore_wishbone_cti = wb_ctrl_cti_1; -assign litesdcardcore_wishbone_bte = wb_ctrl_bte_1; -assign wb_ctrl_err_1 = litesdcardcore_wishbone_err; -assign shared_adr = array_muxed0; -assign shared_dat_w = array_muxed1; -assign shared_sel = array_muxed2; -assign shared_cyc = array_muxed3; -assign shared_stb = array_muxed4; -assign shared_we = array_muxed5; -assign shared_cti = array_muxed6; -assign shared_bte = array_muxed7; -assign interface0_bus_dat_r = shared_dat_r; -assign interface1_bus_dat_r = shared_dat_r; -assign interface0_bus_ack = (shared_ack & (grant == 1'd0)); -assign interface1_bus_ack = (shared_ack & (grant == 1'd1)); -assign interface0_bus_err = (shared_err & (grant == 1'd0)); -assign interface1_bus_err = (shared_err & (grant == 1'd1)); -assign request = {interface1_bus_cyc, interface0_bus_cyc}; -assign slave_sel = 1'd1; -assign wb_dma_adr_1 = shared_adr; -assign wb_dma_dat_w_1 = shared_dat_w; -assign wb_dma_sel_1 = shared_sel; -assign wb_dma_stb_1 = shared_stb; -assign wb_dma_we_1 = shared_we; -assign wb_dma_cti_1 = shared_cti; -assign wb_dma_bte_1 = shared_bte; -assign wb_dma_cyc_1 = (shared_cyc & slave_sel); -assign shared_err = wb_dma_err_1; -assign wait_1 = ((shared_stb & shared_cyc) & (~shared_ack)); -always @(*) begin - error <= 1'd0; - shared_dat_r <= 32'd0; - shared_ack <= 1'd0; - shared_ack <= wb_dma_ack_1; - shared_dat_r <= ({32{slave_sel_r}} & wb_dma_dat_r_1); - if (done) begin - shared_dat_r <= 32'd4294967295; - shared_ack <= 1'd1; - error <= 1'd1; - end -end -assign done = (count == 1'd0); -assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); -assign csrbank0_reset0_r = interface0_bank_bus_dat_w[1:0]; -always @(*) begin - csrbank0_reset0_re <= 1'd0; - csrbank0_reset0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_reset0_re <= interface0_bank_bus_we; - csrbank0_reset0_we <= (~interface0_bank_bus_we); - end -end -assign csrbank0_scratch0_r = interface0_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank0_scratch0_we <= 1'd0; - csrbank0_scratch0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_scratch0_re <= interface0_bank_bus_we; - csrbank0_scratch0_we <= (~interface0_bank_bus_we); - end -end -assign csrbank0_bus_errors_r = interface0_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank0_bus_errors_re <= 1'd0; - csrbank0_bus_errors_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 2'd2))) begin - csrbank0_bus_errors_re <= interface0_bank_bus_we; - csrbank0_bus_errors_we <= (~interface0_bank_bus_we); - end -end -always @(*) begin - soc_rst <= 1'd0; - if (reset_re) begin - soc_rst <= reset_storage[0]; - end -end -assign cpu_rst = reset_storage[1]; -assign csrbank0_reset0_w = reset_storage[1:0]; -assign csrbank0_scratch0_w = scratch_storage[31:0]; -assign csrbank0_bus_errors_w = bus_errors_status[31:0]; -assign bus_errors_we = csrbank0_bus_errors_we; -assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); -assign csrbank1_dma_base1_r = interface1_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank1_dma_base1_we <= 1'd0; - csrbank1_dma_base1_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_dma_base1_re <= interface1_bank_bus_we; - csrbank1_dma_base1_we <= (~interface1_bank_bus_we); - end -end -assign csrbank1_dma_base0_r = interface1_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank1_dma_base0_re <= 1'd0; - csrbank1_dma_base0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dma_base0_re <= interface1_bank_bus_we; - csrbank1_dma_base0_we <= (~interface1_bank_bus_we); - end -end -assign csrbank1_dma_length0_r = interface1_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank1_dma_length0_we <= 1'd0; - csrbank1_dma_length0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - csrbank1_dma_length0_re <= interface1_bank_bus_we; - csrbank1_dma_length0_we <= (~interface1_bank_bus_we); - end -end -assign csrbank1_dma_enable0_r = interface1_bank_bus_dat_w[0]; -always @(*) begin - csrbank1_dma_enable0_we <= 1'd0; - csrbank1_dma_enable0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_dma_enable0_re <= interface1_bank_bus_we; - csrbank1_dma_enable0_we <= (~interface1_bank_bus_we); - end -end -assign csrbank1_dma_done_r = interface1_bank_bus_dat_w[0]; -always @(*) begin - csrbank1_dma_done_re <= 1'd0; - csrbank1_dma_done_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - csrbank1_dma_done_re <= interface1_bank_bus_we; - csrbank1_dma_done_we <= (~interface1_bank_bus_we); - end -end -assign csrbank1_dma_loop0_r = interface1_bank_bus_dat_w[0]; -always @(*) begin - csrbank1_dma_loop0_we <= 1'd0; - csrbank1_dma_loop0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - csrbank1_dma_loop0_re <= interface1_bank_bus_we; - csrbank1_dma_loop0_we <= (~interface1_bank_bus_we); - end -end -assign csrbank1_dma_offset_r = interface1_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank1_dma_offset_we <= 1'd0; - csrbank1_dma_offset_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - csrbank1_dma_offset_re <= interface1_bank_bus_we; - csrbank1_dma_offset_we <= (~interface1_bank_bus_we); - end -end -assign csrbank1_dma_base1_w = sdblock2mem_wishbonedmawriter_base_storage[63:32]; -assign csrbank1_dma_base0_w = sdblock2mem_wishbonedmawriter_base_storage[31:0]; -assign csrbank1_dma_length0_w = sdblock2mem_wishbonedmawriter_length_storage[31:0]; -assign csrbank1_dma_enable0_w = sdblock2mem_wishbonedmawriter_enable_storage; -assign csrbank1_dma_done_w = sdblock2mem_wishbonedmawriter_done_status; -assign sdblock2mem_wishbonedmawriter_done_we = csrbank1_dma_done_we; -assign csrbank1_dma_loop0_w = sdblock2mem_wishbonedmawriter_loop_storage; -assign csrbank1_dma_offset_w = sdblock2mem_wishbonedmawriter_offset_status[31:0]; -assign sdblock2mem_wishbonedmawriter_offset_we = csrbank1_dma_offset_we; -assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); -assign csrbank2_cmd_argument0_r = interface2_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank2_cmd_argument0_re <= 1'd0; - csrbank2_cmd_argument0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_cmd_argument0_re <= interface2_bank_bus_we; - csrbank2_cmd_argument0_we <= (~interface2_bank_bus_we); - end -end -assign csrbank2_cmd_command0_r = interface2_bank_bus_dat_w[13:0]; -always @(*) begin - csrbank2_cmd_command0_we <= 1'd0; - csrbank2_cmd_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_cmd_command0_re <= interface2_bank_bus_we; - csrbank2_cmd_command0_we <= (~interface2_bank_bus_we); - end -end -assign csrbank2_cmd_send0_r = interface2_bank_bus_dat_w[0]; -always @(*) begin - csrbank2_cmd_send0_we <= 1'd0; - csrbank2_cmd_send0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - csrbank2_cmd_send0_re <= interface2_bank_bus_we; - csrbank2_cmd_send0_we <= (~interface2_bank_bus_we); - end -end -assign csrbank2_cmd_response3_r = interface2_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank2_cmd_response3_re <= 1'd0; - csrbank2_cmd_response3_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_cmd_response3_re <= interface2_bank_bus_we; - csrbank2_cmd_response3_we <= (~interface2_bank_bus_we); - end -end -assign csrbank2_cmd_response2_r = interface2_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank2_cmd_response2_we <= 1'd0; - csrbank2_cmd_response2_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_cmd_response2_re <= interface2_bank_bus_we; - csrbank2_cmd_response2_we <= (~interface2_bank_bus_we); - end -end -assign csrbank2_cmd_response1_r = interface2_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank2_cmd_response1_we <= 1'd0; - csrbank2_cmd_response1_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_cmd_response1_re <= interface2_bank_bus_we; - csrbank2_cmd_response1_we <= (~interface2_bank_bus_we); - end -end -assign csrbank2_cmd_response0_r = interface2_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank2_cmd_response0_re <= 1'd0; - csrbank2_cmd_response0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_cmd_response0_re <= interface2_bank_bus_we; - csrbank2_cmd_response0_we <= (~interface2_bank_bus_we); - end -end -assign csrbank2_cmd_event_r = interface2_bank_bus_dat_w[3:0]; -always @(*) begin - csrbank2_cmd_event_re <= 1'd0; - csrbank2_cmd_event_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_cmd_event_re <= interface2_bank_bus_we; - csrbank2_cmd_event_we <= (~interface2_bank_bus_we); - end -end -assign csrbank2_data_event_r = interface2_bank_bus_dat_w[3:0]; -always @(*) begin - csrbank2_data_event_we <= 1'd0; - csrbank2_data_event_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - csrbank2_data_event_re <= interface2_bank_bus_we; - csrbank2_data_event_we <= (~interface2_bank_bus_we); - end -end -assign csrbank2_block_length0_r = interface2_bank_bus_dat_w[9:0]; -always @(*) begin - csrbank2_block_length0_we <= 1'd0; - csrbank2_block_length0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_block_length0_re <= interface2_bank_bus_we; - csrbank2_block_length0_we <= (~interface2_bank_bus_we); - end -end -assign csrbank2_block_count0_r = interface2_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank2_block_count0_re <= 1'd0; - csrbank2_block_count0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - csrbank2_block_count0_re <= interface2_bank_bus_we; - csrbank2_block_count0_we <= (~interface2_bank_bus_we); - end -end -assign csrbank2_cmd_argument0_w = sdcore_cmd_argument_storage[31:0]; -assign sdcore_csrfield_cmd_type = sdcore_cmd_command_storage[1:0]; -assign sdcore_csrfield_data_type = sdcore_cmd_command_storage[6:5]; -assign sdcore_csrfield_cmd = sdcore_cmd_command_storage[13:8]; -assign csrbank2_cmd_command0_w = sdcore_cmd_command_storage[13:0]; -assign csrbank2_cmd_send0_w = sdcore_cmd_send_storage; -assign csrbank2_cmd_response3_w = sdcore_cmd_response_status[127:96]; -assign csrbank2_cmd_response2_w = sdcore_cmd_response_status[95:64]; -assign csrbank2_cmd_response1_w = sdcore_cmd_response_status[63:32]; -assign csrbank2_cmd_response0_w = sdcore_cmd_response_status[31:0]; -assign sdcore_cmd_response_we = csrbank2_cmd_response0_we; -always @(*) begin - sdcore_cmd_event_status <= 4'd0; - sdcore_cmd_event_status[0] <= sdcore_csrfield_done0; - sdcore_cmd_event_status[1] <= sdcore_csrfield_error0; - sdcore_cmd_event_status[2] <= sdcore_csrfield_timeout0; - sdcore_cmd_event_status[3] <= sdcore_csrfield_crc0; -end -assign csrbank2_cmd_event_w = sdcore_cmd_event_status[3:0]; -assign sdcore_cmd_event_we = csrbank2_cmd_event_we; -always @(*) begin - sdcore_data_event_status <= 4'd0; - sdcore_data_event_status[0] <= sdcore_csrfield_done1; - sdcore_data_event_status[1] <= sdcore_csrfield_error1; - sdcore_data_event_status[2] <= sdcore_csrfield_timeout1; - sdcore_data_event_status[3] <= sdcore_csrfield_crc1; -end -assign csrbank2_data_event_w = sdcore_data_event_status[3:0]; -assign sdcore_data_event_we = csrbank2_data_event_we; -assign csrbank2_block_length0_w = sdcore_block_length_storage[9:0]; -assign csrbank2_block_count0_w = sdcore_block_count_storage[31:0]; -assign csrbank3_sel = (interface3_bank_bus_adr[13:9] == 2'd3); -assign csrbank3_status_r = interface3_bank_bus_dat_w[3:0]; -always @(*) begin - csrbank3_status_re <= 1'd0; - csrbank3_status_we <= 1'd0; - if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 1'd0))) begin - csrbank3_status_re <= interface3_bank_bus_we; - csrbank3_status_we <= (~interface3_bank_bus_we); - end -end -assign csrbank3_pending_r = interface3_bank_bus_dat_w[3:0]; -always @(*) begin - csrbank3_pending_re <= 1'd0; - csrbank3_pending_we <= 1'd0; - if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 1'd1))) begin - csrbank3_pending_re <= interface3_bank_bus_we; - csrbank3_pending_we <= (~interface3_bank_bus_we); - end -end -assign csrbank3_enable0_r = interface3_bank_bus_dat_w[3:0]; -always @(*) begin - csrbank3_enable0_we <= 1'd0; - csrbank3_enable0_re <= 1'd0; - if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 2'd2))) begin - csrbank3_enable0_re <= interface3_bank_bus_we; - csrbank3_enable0_we <= (~interface3_bank_bus_we); - end -end -always @(*) begin - eventmanager_status_status <= 4'd0; - eventmanager_status_status[0] <= eventmanager_card_detect0; - eventmanager_status_status[1] <= eventmanager_block2mem_dma0; - eventmanager_status_status[2] <= eventmanager_mem2block_dma0; - eventmanager_status_status[3] <= eventmanager_cmd_done0; -end -assign csrbank3_status_w = eventmanager_status_status[3:0]; -assign eventmanager_status_we = csrbank3_status_we; -always @(*) begin - eventmanager_pending_status <= 4'd0; - eventmanager_pending_status[0] <= eventmanager_card_detect1; - eventmanager_pending_status[1] <= eventmanager_block2mem_dma1; - eventmanager_pending_status[2] <= eventmanager_mem2block_dma1; - eventmanager_pending_status[3] <= eventmanager_cmd_done1; -end -assign csrbank3_pending_w = eventmanager_pending_status[3:0]; -assign eventmanager_pending_we = csrbank3_pending_we; -assign eventmanager_card_detect2 = eventmanager_enable_storage[0]; -assign eventmanager_block2mem_dma2 = eventmanager_enable_storage[1]; -assign eventmanager_mem2block_dma2 = eventmanager_enable_storage[2]; -assign eventmanager_cmd_done2 = eventmanager_enable_storage[3]; -assign csrbank3_enable0_w = eventmanager_enable_storage[3:0]; -assign csrbank4_sel = (interface4_bank_bus_adr[13:9] == 3'd4); -assign csrbank4_dma_base1_r = interface4_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank4_dma_base1_we <= 1'd0; - csrbank4_dma_base1_re <= 1'd0; - if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 1'd0))) begin - csrbank4_dma_base1_re <= interface4_bank_bus_we; - csrbank4_dma_base1_we <= (~interface4_bank_bus_we); - end -end -assign csrbank4_dma_base0_r = interface4_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank4_dma_base0_we <= 1'd0; - csrbank4_dma_base0_re <= 1'd0; - if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 1'd1))) begin - csrbank4_dma_base0_re <= interface4_bank_bus_we; - csrbank4_dma_base0_we <= (~interface4_bank_bus_we); - end -end -assign csrbank4_dma_length0_r = interface4_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank4_dma_length0_re <= 1'd0; - csrbank4_dma_length0_we <= 1'd0; - if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 2'd2))) begin - csrbank4_dma_length0_re <= interface4_bank_bus_we; - csrbank4_dma_length0_we <= (~interface4_bank_bus_we); - end -end -assign csrbank4_dma_enable0_r = interface4_bank_bus_dat_w[0]; -always @(*) begin - csrbank4_dma_enable0_we <= 1'd0; - csrbank4_dma_enable0_re <= 1'd0; - if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 2'd3))) begin - csrbank4_dma_enable0_re <= interface4_bank_bus_we; - csrbank4_dma_enable0_we <= (~interface4_bank_bus_we); - end -end -assign csrbank4_dma_done_r = interface4_bank_bus_dat_w[0]; -always @(*) begin - csrbank4_dma_done_re <= 1'd0; - csrbank4_dma_done_we <= 1'd0; - if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd4))) begin - csrbank4_dma_done_re <= interface4_bank_bus_we; - csrbank4_dma_done_we <= (~interface4_bank_bus_we); - end -end -assign csrbank4_dma_loop0_r = interface4_bank_bus_dat_w[0]; -always @(*) begin - csrbank4_dma_loop0_re <= 1'd0; - csrbank4_dma_loop0_we <= 1'd0; - if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd5))) begin - csrbank4_dma_loop0_re <= interface4_bank_bus_we; - csrbank4_dma_loop0_we <= (~interface4_bank_bus_we); - end -end -assign csrbank4_dma_offset_r = interface4_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank4_dma_offset_we <= 1'd0; - csrbank4_dma_offset_re <= 1'd0; - if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd6))) begin - csrbank4_dma_offset_re <= interface4_bank_bus_we; - csrbank4_dma_offset_we <= (~interface4_bank_bus_we); - end -end -assign csrbank4_dma_base1_w = sdmem2block_dma_base_storage[63:32]; -assign csrbank4_dma_base0_w = sdmem2block_dma_base_storage[31:0]; -assign csrbank4_dma_length0_w = sdmem2block_dma_length_storage[31:0]; -assign csrbank4_dma_enable0_w = sdmem2block_dma_enable_storage; -assign csrbank4_dma_done_w = sdmem2block_dma_done_status; -assign sdmem2block_dma_done_we = csrbank4_dma_done_we; -assign csrbank4_dma_loop0_w = sdmem2block_dma_loop_storage; -assign csrbank4_dma_offset_w = sdmem2block_dma_offset_status[31:0]; -assign sdmem2block_dma_offset_we = csrbank4_dma_offset_we; -assign csrbank5_sel = (interface5_bank_bus_adr[13:9] == 3'd5); -assign csrbank5_card_detect_r = interface5_bank_bus_dat_w[0]; -always @(*) begin - csrbank5_card_detect_we <= 1'd0; - csrbank5_card_detect_re <= 1'd0; - if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 1'd0))) begin - csrbank5_card_detect_re <= interface5_bank_bus_we; - csrbank5_card_detect_we <= (~interface5_bank_bus_we); - end -end -assign csrbank5_clocker_divider0_r = interface5_bank_bus_dat_w[8:0]; -always @(*) begin - csrbank5_clocker_divider0_re <= 1'd0; - csrbank5_clocker_divider0_we <= 1'd0; - if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 1'd1))) begin - csrbank5_clocker_divider0_re <= interface5_bank_bus_we; - csrbank5_clocker_divider0_we <= (~interface5_bank_bus_we); - end -end -assign init_initialize_r = interface5_bank_bus_dat_w[0]; -always @(*) begin - init_initialize_re <= 1'd0; - init_initialize_we <= 1'd0; - if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 2'd2))) begin - init_initialize_re <= interface5_bank_bus_we; - init_initialize_we <= (~interface5_bank_bus_we); - end -end -assign csrbank5_dataw_status_r = interface5_bank_bus_dat_w[2:0]; -always @(*) begin - csrbank5_dataw_status_we <= 1'd0; - csrbank5_dataw_status_re <= 1'd0; - if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 2'd3))) begin - csrbank5_dataw_status_re <= interface5_bank_bus_we; - csrbank5_dataw_status_we <= (~interface5_bank_bus_we); - end -end -assign csrbank5_card_detect_w = card_detect_status0; -assign card_detect_we = csrbank5_card_detect_we; -assign csrbank5_clocker_divider0_w = clocker_storage[8:0]; -always @(*) begin - dataw_status <= 3'd0; - dataw_status[0] <= dataw_accepted0; - dataw_status[1] <= dataw_crc_error0; - dataw_status[2] <= dataw_write_error0; -end -assign csrbank5_dataw_status_w = dataw_status[2:0]; -assign dataw_we = csrbank5_dataw_status_we; -assign csr_interconnect_adr = litesdcardcore_adr; -assign csr_interconnect_we = litesdcardcore_we; -assign csr_interconnect_dat_w = litesdcardcore_dat_w; -assign litesdcardcore_dat_r = csr_interconnect_dat_r; -assign interface0_bank_bus_adr = csr_interconnect_adr; -assign interface1_bank_bus_adr = csr_interconnect_adr; -assign interface2_bank_bus_adr = csr_interconnect_adr; -assign interface3_bank_bus_adr = csr_interconnect_adr; -assign interface4_bank_bus_adr = csr_interconnect_adr; -assign interface5_bank_bus_adr = csr_interconnect_adr; -assign interface0_bank_bus_we = csr_interconnect_we; -assign interface1_bank_bus_we = csr_interconnect_we; -assign interface2_bank_bus_we = csr_interconnect_we; -assign interface3_bank_bus_we = csr_interconnect_we; -assign interface4_bank_bus_we = csr_interconnect_we; -assign interface5_bank_bus_we = csr_interconnect_we; -assign interface0_bank_bus_dat_w = csr_interconnect_dat_w; -assign interface1_bank_bus_dat_w = csr_interconnect_dat_w; -assign interface2_bank_bus_dat_w = csr_interconnect_dat_w; -assign interface3_bank_bus_dat_w = csr_interconnect_dat_w; -assign interface4_bank_bus_dat_w = csr_interconnect_dat_w; -assign interface5_bank_bus_dat_w = csr_interconnect_dat_w; -assign csr_interconnect_dat_r = (((((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r) | interface3_bank_bus_dat_r) | interface4_bank_bus_dat_r) | interface5_bank_bus_dat_r); -always @(*) begin - array_muxed0 <= 32'd0; - case (grant) - 1'd0: begin - array_muxed0 <= interface0_bus_adr; - end - default: begin - array_muxed0 <= interface1_bus_adr; - end - endcase -end -always @(*) begin - array_muxed1 <= 32'd0; - case (grant) - 1'd0: begin - array_muxed1 <= interface0_bus_dat_w; - end - default: begin - array_muxed1 <= interface1_bus_dat_w; - end - endcase -end -always @(*) begin - array_muxed2 <= 4'd0; - case (grant) - 1'd0: begin - array_muxed2 <= interface0_bus_sel; - end - default: begin - array_muxed2 <= interface1_bus_sel; - end - endcase -end -always @(*) begin - array_muxed3 <= 1'd0; - case (grant) - 1'd0: begin - array_muxed3 <= interface0_bus_cyc; - end - default: begin - array_muxed3 <= interface1_bus_cyc; - end - endcase -end -always @(*) begin - array_muxed4 <= 1'd0; - case (grant) - 1'd0: begin - array_muxed4 <= interface0_bus_stb; - end - default: begin - array_muxed4 <= interface1_bus_stb; - end - endcase -end -always @(*) begin - array_muxed5 <= 1'd0; - case (grant) - 1'd0: begin - array_muxed5 <= interface0_bus_we; - end - default: begin - array_muxed5 <= interface1_bus_we; - end - endcase -end -always @(*) begin - array_muxed6 <= 3'd0; - case (grant) - 1'd0: begin - array_muxed6 <= interface0_bus_cti; - end - default: begin - array_muxed6 <= interface1_bus_cti; - end - endcase -end -always @(*) begin - array_muxed7 <= 2'd0; - case (grant) - 1'd0: begin - array_muxed7 <= interface0_bus_bte; - end - default: begin - array_muxed7 <= interface1_bus_bte; - end - endcase -end -assign sdrio_clk = sys_clk; -assign sdrio_clk_1 = sys_clk; -assign sdrio_clk_2 = sys_clk; -assign sdrio_clk_3 = sys_clk; -assign sdrio_clk_4 = sys_clk; - - -//------------------------------------------------------------------------------ -// Synchronous Logic -//------------------------------------------------------------------------------ - -always @(posedge por_clk) begin - int_rst <= rst; -end - -always @(posedge sdrio_clk) begin - inferedsdrtristate0_oe <= sdpads_cmd_oe; - inferedsdrtristate1_oe <= sdpads_data_oe; - inferedsdrtristate2_oe <= sdpads_data_oe; - inferedsdrtristate3_oe <= sdpads_data_oe; - inferedsdrtristate4_oe <= sdpads_data_oe; -end - -always @(posedge sys_clk) begin - if ((bus_errors != 32'd4294967295)) begin - if (bus_error) begin - bus_errors <= (bus_errors + 1'd1); - end - end - card_detect_d <= card_detect_status0; - card_detect_irq <= (card_detect_status0 ^ card_detect_d); - if ((~clocker_stop)) begin - clocker_clks <= (clocker_clks + 1'd1); - end - clocker_clk_d <= clocker_clk1; - if (clocker_clk_d) begin - clocker_ce_delayed <= clocker_clk_en; - end - litesdcardcore_sdphyinit_state <= litesdcardcore_sdphyinit_next_state; - if (init_count_sdphyinit_next_value_ce) begin - init_count <= init_count_sdphyinit_next_value; - end - litesdcardcore_sdphycmdw_state <= litesdcardcore_sdphycmdw_next_state; - if (cmdw_count_sdphycmdw_next_value_ce) begin - cmdw_count <= cmdw_count_sdphycmdw_next_value; - end - if (cmdr_cmdr_pads_in_valid) begin - cmdr_cmdr_run <= (cmdr_cmdr_start | cmdr_cmdr_run); - end - if (cmdr_cmdr_converter_source_ready) begin - cmdr_cmdr_converter_strobe_all <= 1'd0; - end - if (cmdr_cmdr_converter_load_part) begin - if (((cmdr_cmdr_converter_demux == 3'd7) | cmdr_cmdr_converter_sink_last)) begin - cmdr_cmdr_converter_demux <= 1'd0; - cmdr_cmdr_converter_strobe_all <= 1'd1; - end else begin - cmdr_cmdr_converter_demux <= (cmdr_cmdr_converter_demux + 1'd1); - end - end - if ((cmdr_cmdr_converter_source_valid & cmdr_cmdr_converter_source_ready)) begin - if ((cmdr_cmdr_converter_sink_valid & cmdr_cmdr_converter_sink_ready)) begin - cmdr_cmdr_converter_source_first <= cmdr_cmdr_converter_sink_first; - cmdr_cmdr_converter_source_last <= cmdr_cmdr_converter_sink_last; - end else begin - cmdr_cmdr_converter_source_first <= 1'd0; - cmdr_cmdr_converter_source_last <= 1'd0; - end - end else begin - if ((cmdr_cmdr_converter_sink_valid & cmdr_cmdr_converter_sink_ready)) begin - cmdr_cmdr_converter_source_first <= (cmdr_cmdr_converter_sink_first | cmdr_cmdr_converter_source_first); - cmdr_cmdr_converter_source_last <= (cmdr_cmdr_converter_sink_last | cmdr_cmdr_converter_source_last); - end - end - if (cmdr_cmdr_converter_load_part) begin - case (cmdr_cmdr_converter_demux) - 1'd0: begin - cmdr_cmdr_converter_source_payload_data[7] <= cmdr_cmdr_converter_sink_payload_data; - end - 1'd1: begin - cmdr_cmdr_converter_source_payload_data[6] <= cmdr_cmdr_converter_sink_payload_data; - end - 2'd2: begin - cmdr_cmdr_converter_source_payload_data[5] <= cmdr_cmdr_converter_sink_payload_data; - end - 2'd3: begin - cmdr_cmdr_converter_source_payload_data[4] <= cmdr_cmdr_converter_sink_payload_data; - end - 3'd4: begin - cmdr_cmdr_converter_source_payload_data[3] <= cmdr_cmdr_converter_sink_payload_data; - end - 3'd5: begin - cmdr_cmdr_converter_source_payload_data[2] <= cmdr_cmdr_converter_sink_payload_data; - end - 3'd6: begin - cmdr_cmdr_converter_source_payload_data[1] <= cmdr_cmdr_converter_sink_payload_data; - end - 3'd7: begin - cmdr_cmdr_converter_source_payload_data[0] <= cmdr_cmdr_converter_sink_payload_data; - end - endcase - end - if (cmdr_cmdr_converter_load_part) begin - cmdr_cmdr_converter_source_payload_valid_token_count <= (cmdr_cmdr_converter_demux + 1'd1); - end - if (((~cmdr_cmdr_buf_source_valid) | cmdr_cmdr_buf_source_ready)) begin - cmdr_cmdr_buf_source_valid <= cmdr_cmdr_buf_sink_valid; - cmdr_cmdr_buf_source_first <= cmdr_cmdr_buf_sink_first; - cmdr_cmdr_buf_source_last <= cmdr_cmdr_buf_sink_last; - cmdr_cmdr_buf_source_payload_data <= cmdr_cmdr_buf_sink_payload_data; - end - if (cmdr_cmdr_reset) begin - cmdr_cmdr_run <= 1'd0; - cmdr_cmdr_converter_source_payload_data <= 8'd0; - cmdr_cmdr_converter_source_payload_valid_token_count <= 4'd0; - cmdr_cmdr_converter_demux <= 3'd0; - cmdr_cmdr_converter_strobe_all <= 1'd0; - cmdr_cmdr_buf_source_valid <= 1'd0; - cmdr_cmdr_buf_source_payload_data <= 8'd0; - end - litesdcardcore_sdphycmdr_state <= litesdcardcore_sdphycmdr_next_state; - if (cmdr_timeout_sdphycmdr_next_value_ce0) begin - cmdr_timeout <= cmdr_timeout_sdphycmdr_next_value0; - end - if (cmdr_count_sdphycmdr_next_value_ce1) begin - cmdr_count <= cmdr_count_sdphycmdr_next_value1; - end - if (cmdr_busy_sdphycmdr_next_value_ce2) begin - cmdr_busy <= cmdr_busy_sdphycmdr_next_value2; - end - if (cmdr_cmdr_reset_sdphycmdr_next_value_ce3) begin - cmdr_cmdr_reset <= cmdr_cmdr_reset_sdphycmdr_next_value3; - end - if (dataw_crc_pads_in_valid) begin - dataw_crc_run <= (dataw_crc_start | dataw_crc_run); - end - if (dataw_crc_converter_source_ready) begin - dataw_crc_converter_strobe_all <= 1'd0; - end - if (dataw_crc_converter_load_part) begin - if (((dataw_crc_converter_demux == 3'd7) | dataw_crc_converter_sink_last)) begin - dataw_crc_converter_demux <= 1'd0; - dataw_crc_converter_strobe_all <= 1'd1; - end else begin - dataw_crc_converter_demux <= (dataw_crc_converter_demux + 1'd1); - end - end - if ((dataw_crc_converter_source_valid & dataw_crc_converter_source_ready)) begin - if ((dataw_crc_converter_sink_valid & dataw_crc_converter_sink_ready)) begin - dataw_crc_converter_source_first <= dataw_crc_converter_sink_first; - dataw_crc_converter_source_last <= dataw_crc_converter_sink_last; - end else begin - dataw_crc_converter_source_first <= 1'd0; - dataw_crc_converter_source_last <= 1'd0; - end - end else begin - if ((dataw_crc_converter_sink_valid & dataw_crc_converter_sink_ready)) begin - dataw_crc_converter_source_first <= (dataw_crc_converter_sink_first | dataw_crc_converter_source_first); - dataw_crc_converter_source_last <= (dataw_crc_converter_sink_last | dataw_crc_converter_source_last); - end - end - if (dataw_crc_converter_load_part) begin - case (dataw_crc_converter_demux) - 1'd0: begin - dataw_crc_converter_source_payload_data[7] <= dataw_crc_converter_sink_payload_data; - end - 1'd1: begin - dataw_crc_converter_source_payload_data[6] <= dataw_crc_converter_sink_payload_data; - end - 2'd2: begin - dataw_crc_converter_source_payload_data[5] <= dataw_crc_converter_sink_payload_data; - end - 2'd3: begin - dataw_crc_converter_source_payload_data[4] <= dataw_crc_converter_sink_payload_data; - end - 3'd4: begin - dataw_crc_converter_source_payload_data[3] <= dataw_crc_converter_sink_payload_data; - end - 3'd5: begin - dataw_crc_converter_source_payload_data[2] <= dataw_crc_converter_sink_payload_data; - end - 3'd6: begin - dataw_crc_converter_source_payload_data[1] <= dataw_crc_converter_sink_payload_data; - end - 3'd7: begin - dataw_crc_converter_source_payload_data[0] <= dataw_crc_converter_sink_payload_data; - end - endcase - end - if (dataw_crc_converter_load_part) begin - dataw_crc_converter_source_payload_valid_token_count <= (dataw_crc_converter_demux + 1'd1); - end - if (((~dataw_crc_buf_source_valid) | dataw_crc_buf_source_ready)) begin - dataw_crc_buf_source_valid <= dataw_crc_buf_sink_valid; - dataw_crc_buf_source_first <= dataw_crc_buf_sink_first; - dataw_crc_buf_source_last <= dataw_crc_buf_sink_last; - dataw_crc_buf_source_payload_data <= dataw_crc_buf_sink_payload_data; - end - if (dataw_crc_reset) begin - dataw_crc_run <= 1'd0; - dataw_crc_converter_source_payload_data <= 8'd0; - dataw_crc_converter_source_payload_valid_token_count <= 4'd0; - dataw_crc_converter_demux <= 3'd0; - dataw_crc_converter_strobe_all <= 1'd0; - dataw_crc_buf_source_valid <= 1'd0; - dataw_crc_buf_source_payload_data <= 8'd0; - end - litesdcardcore_sdphydataw_state <= litesdcardcore_sdphydataw_next_state; - if (dataw_accepted1_sdphydataw_next_value_ce0) begin - dataw_accepted1 <= dataw_accepted1_sdphydataw_next_value0; - end - if (dataw_crc_error1_sdphydataw_next_value_ce1) begin - dataw_crc_error1 <= dataw_crc_error1_sdphydataw_next_value1; - end - if (dataw_write_error1_sdphydataw_next_value_ce2) begin - dataw_write_error1 <= dataw_write_error1_sdphydataw_next_value2; - end - if (dataw_count_sdphydataw_next_value_ce3) begin - dataw_count <= dataw_count_sdphydataw_next_value3; - end - if (datar_datar_pads_in_valid) begin - datar_datar_run <= (datar_datar_start | datar_datar_run); - end - if (datar_datar_converter_source_ready) begin - datar_datar_converter_strobe_all <= 1'd0; - end - if (datar_datar_converter_load_part) begin - if (((datar_datar_converter_demux == 1'd1) | datar_datar_converter_sink_last)) begin - datar_datar_converter_demux <= 1'd0; - datar_datar_converter_strobe_all <= 1'd1; - end else begin - datar_datar_converter_demux <= (datar_datar_converter_demux + 1'd1); - end - end - if ((datar_datar_converter_source_valid & datar_datar_converter_source_ready)) begin - if ((datar_datar_converter_sink_valid & datar_datar_converter_sink_ready)) begin - datar_datar_converter_source_first <= datar_datar_converter_sink_first; - datar_datar_converter_source_last <= datar_datar_converter_sink_last; - end else begin - datar_datar_converter_source_first <= 1'd0; - datar_datar_converter_source_last <= 1'd0; - end - end else begin - if ((datar_datar_converter_sink_valid & datar_datar_converter_sink_ready)) begin - datar_datar_converter_source_first <= (datar_datar_converter_sink_first | datar_datar_converter_source_first); - datar_datar_converter_source_last <= (datar_datar_converter_sink_last | datar_datar_converter_source_last); - end - end - if (datar_datar_converter_load_part) begin - case (datar_datar_converter_demux) - 1'd0: begin - datar_datar_converter_source_payload_data[7:4] <= datar_datar_converter_sink_payload_data; - end - 1'd1: begin - datar_datar_converter_source_payload_data[3:0] <= datar_datar_converter_sink_payload_data; - end - endcase - end - if (datar_datar_converter_load_part) begin - datar_datar_converter_source_payload_valid_token_count <= (datar_datar_converter_demux + 1'd1); - end - if (((~datar_datar_buf_source_valid) | datar_datar_buf_source_ready)) begin - datar_datar_buf_source_valid <= datar_datar_buf_sink_valid; - datar_datar_buf_source_first <= datar_datar_buf_sink_first; - datar_datar_buf_source_last <= datar_datar_buf_sink_last; - datar_datar_buf_source_payload_data <= datar_datar_buf_sink_payload_data; - end - if (datar_datar_reset) begin - datar_datar_run <= 1'd0; - datar_datar_converter_source_payload_data <= 8'd0; - datar_datar_converter_source_payload_valid_token_count <= 2'd0; - datar_datar_converter_demux <= 1'd0; - datar_datar_converter_strobe_all <= 1'd0; - datar_datar_buf_source_valid <= 1'd0; - datar_datar_buf_source_payload_data <= 8'd0; - end - litesdcardcore_sdphydatar_state <= litesdcardcore_sdphydatar_next_state; - if (datar_count_sdphydatar_next_value_ce0) begin - datar_count <= datar_count_sdphydatar_next_value0; - end - if (datar_timeout_sdphydatar_next_value_ce1) begin - datar_timeout <= datar_timeout_sdphydatar_next_value1; - end - if (datar_datar_reset_sdphydatar_next_value_ce2) begin - datar_datar_reset <= datar_datar_reset_sdphydatar_next_value2; - end - clocker_clk_delay <= {clocker_clk_delay, clocker_clk0}; - sdpads_data_i_ce <= (clocker_clk_delay[1] & (~clocker_clk_delay[0])); - if (sdcore_crc7_inserter_reset) begin - sdcore_crc7_inserter_reg0 <= 1'd0; - end else begin - if (sdcore_crc7_inserter_enable) begin - sdcore_crc7_inserter_reg0 <= sdcore_crc7_inserter_reg40; - end - end - if (sdcore_crc16_inserter_crc0_reset) begin - sdcore_crc16_inserter_crc0_reg0 <= 1'd0; - end else begin - if (sdcore_crc16_inserter_crc0_enable) begin - sdcore_crc16_inserter_crc0_reg0 <= sdcore_crc16_inserter_crc0_reg2; - end - end - if (sdcore_crc16_inserter_crc1_reset) begin - sdcore_crc16_inserter_crc1_reg0 <= 1'd0; - end else begin - if (sdcore_crc16_inserter_crc1_enable) begin - sdcore_crc16_inserter_crc1_reg0 <= sdcore_crc16_inserter_crc1_reg2; - end - end - if (sdcore_crc16_inserter_crc2_reset) begin - sdcore_crc16_inserter_crc2_reg0 <= 1'd0; - end else begin - if (sdcore_crc16_inserter_crc2_enable) begin - sdcore_crc16_inserter_crc2_reg0 <= sdcore_crc16_inserter_crc2_reg2; - end - end - if (sdcore_crc16_inserter_crc3_reset) begin - sdcore_crc16_inserter_crc3_reg0 <= 1'd0; - end else begin - if (sdcore_crc16_inserter_crc3_enable) begin - sdcore_crc16_inserter_crc3_reg0 <= sdcore_crc16_inserter_crc3_reg2; - end - end - litesdcardcore_sdcore_crc16inserter_state <= litesdcardcore_sdcore_crc16inserter_next_state; - if (sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value_ce) begin - sdcore_crc16_inserter_count <= sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value; - end - if (((sdcore_fifo_syncfifo_we & sdcore_fifo_syncfifo_writable) & (~sdcore_fifo_replace))) begin - sdcore_fifo_produce <= (sdcore_fifo_produce + 1'd1); - end - if (sdcore_fifo_do_read) begin - sdcore_fifo_consume <= (sdcore_fifo_consume + 1'd1); - end - if (((sdcore_fifo_syncfifo_we & sdcore_fifo_syncfifo_writable) & (~sdcore_fifo_replace))) begin - if ((~sdcore_fifo_do_read)) begin - sdcore_fifo_level <= (sdcore_fifo_level + 1'd1); - end - end else begin - if (sdcore_fifo_do_read) begin - sdcore_fifo_level <= (sdcore_fifo_level - 1'd1); - end - end - if (sdcore_fifo_reset) begin - sdcore_fifo_level <= 4'd0; - sdcore_fifo_produce <= 3'd0; - sdcore_fifo_consume <= 3'd0; - end - litesdcardcore_sdcore_fsm_state <= litesdcardcore_sdcore_fsm_next_state; - if (sdcore_cmd_done_sdcore_fsm_next_value_ce0) begin - sdcore_cmd_done <= sdcore_cmd_done_sdcore_fsm_next_value0; - end - if (sdcore_data_done_sdcore_fsm_next_value_ce1) begin - sdcore_data_done <= sdcore_data_done_sdcore_fsm_next_value1; - end - if (sdcore_cmd_count_sdcore_fsm_next_value_ce2) begin - sdcore_cmd_count <= sdcore_cmd_count_sdcore_fsm_next_value2; - end - if (sdcore_data_count_sdcore_fsm_next_value_ce3) begin - sdcore_data_count <= sdcore_data_count_sdcore_fsm_next_value3; - end - if (sdcore_cmd_error_sdcore_fsm_next_value_ce4) begin - sdcore_cmd_error <= sdcore_cmd_error_sdcore_fsm_next_value4; - end - if (sdcore_cmd_timeout_sdcore_fsm_next_value_ce5) begin - sdcore_cmd_timeout <= sdcore_cmd_timeout_sdcore_fsm_next_value5; - end - if (sdcore_data_error_sdcore_fsm_next_value_ce6) begin - sdcore_data_error <= sdcore_data_error_sdcore_fsm_next_value6; - end - if (sdcore_data_timeout_sdcore_fsm_next_value_ce7) begin - sdcore_data_timeout <= sdcore_data_timeout_sdcore_fsm_next_value7; - end - if (sdcore_cmd_response_status_sdcore_fsm_next_value_ce8) begin - sdcore_cmd_response_status <= sdcore_cmd_response_status_sdcore_fsm_next_value8; - end - if ((~sdblock2mem_wishbonedmawriter_enable_storage)) begin - sdblock2mem_connect <= 1'd0; - end else begin - if (sdblock2mem_start) begin - sdblock2mem_connect <= 1'd1; - end - end - sdblock2mem_done_d <= sdblock2mem_wishbonedmawriter_done_status; - sdblock2mem_irq <= (sdblock2mem_wishbonedmawriter_done_status & (~sdblock2mem_done_d)); - if (sdblock2mem_fifo_syncfifo_re) begin - sdblock2mem_fifo_readable <= 1'd1; - end else begin - if (sdblock2mem_fifo_re) begin - sdblock2mem_fifo_readable <= 1'd0; - end - end - if (((sdblock2mem_fifo_syncfifo_we & sdblock2mem_fifo_syncfifo_writable) & (~sdblock2mem_fifo_replace))) begin - sdblock2mem_fifo_produce <= (sdblock2mem_fifo_produce + 1'd1); - end - if (sdblock2mem_fifo_do_read) begin - sdblock2mem_fifo_consume <= (sdblock2mem_fifo_consume + 1'd1); - end - if (((sdblock2mem_fifo_syncfifo_we & sdblock2mem_fifo_syncfifo_writable) & (~sdblock2mem_fifo_replace))) begin - if ((~sdblock2mem_fifo_do_read)) begin - sdblock2mem_fifo_level0 <= (sdblock2mem_fifo_level0 + 1'd1); - end - end else begin - if (sdblock2mem_fifo_do_read) begin - sdblock2mem_fifo_level0 <= (sdblock2mem_fifo_level0 - 1'd1); - end - end - if (sdblock2mem_converter_source_ready) begin - sdblock2mem_converter_strobe_all <= 1'd0; - end - if (sdblock2mem_converter_load_part) begin - if (((sdblock2mem_converter_demux == 2'd3) | sdblock2mem_converter_sink_last)) begin - sdblock2mem_converter_demux <= 1'd0; - sdblock2mem_converter_strobe_all <= 1'd1; - end else begin - sdblock2mem_converter_demux <= (sdblock2mem_converter_demux + 1'd1); - end - end - if ((sdblock2mem_converter_source_valid & sdblock2mem_converter_source_ready)) begin - if ((sdblock2mem_converter_sink_valid & sdblock2mem_converter_sink_ready)) begin - sdblock2mem_converter_source_first <= sdblock2mem_converter_sink_first; - sdblock2mem_converter_source_last <= sdblock2mem_converter_sink_last; - end else begin - sdblock2mem_converter_source_first <= 1'd0; - sdblock2mem_converter_source_last <= 1'd0; - end - end else begin - if ((sdblock2mem_converter_sink_valid & sdblock2mem_converter_sink_ready)) begin - sdblock2mem_converter_source_first <= (sdblock2mem_converter_sink_first | sdblock2mem_converter_source_first); - sdblock2mem_converter_source_last <= (sdblock2mem_converter_sink_last | sdblock2mem_converter_source_last); - end - end - if (sdblock2mem_converter_load_part) begin - case (sdblock2mem_converter_demux) - 1'd0: begin - sdblock2mem_converter_source_payload_data[31:24] <= sdblock2mem_converter_sink_payload_data; - end - 1'd1: begin - sdblock2mem_converter_source_payload_data[23:16] <= sdblock2mem_converter_sink_payload_data; - end - 2'd2: begin - sdblock2mem_converter_source_payload_data[15:8] <= sdblock2mem_converter_sink_payload_data; - end - 2'd3: begin - sdblock2mem_converter_source_payload_data[7:0] <= sdblock2mem_converter_sink_payload_data; - end - endcase - end - if (sdblock2mem_converter_load_part) begin - sdblock2mem_converter_source_payload_valid_token_count <= (sdblock2mem_converter_demux + 1'd1); - end - litesdcardcore_sdblock2memdma_state <= litesdcardcore_sdblock2memdma_next_state; - if (sdblock2mem_wishbonedmawriter_offset_next_value_ce) begin - sdblock2mem_wishbonedmawriter_offset <= sdblock2mem_wishbonedmawriter_offset_next_value; - end - if (sdblock2mem_wishbonedmawriter_reset) begin - sdblock2mem_wishbonedmawriter_offset <= 32'd0; - litesdcardcore_sdblock2memdma_state <= 2'd0; - end - if ((sdmem2block_source_source_valid0 & sdmem2block_source_source_ready0)) begin - sdmem2block_count <= (sdmem2block_count + 1'd1); - if (sdmem2block_source_source_last0) begin - sdmem2block_count <= 1'd0; - end - end - sdmem2block_done_d <= sdmem2block_dma_done_status; - sdmem2block_irq <= (sdmem2block_dma_done_status & (~sdmem2block_done_d)); - litesdcardcore_sdmem2blockdma_fsm_state <= litesdcardcore_sdmem2blockdma_fsm_next_state; - if (sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce) begin - sdmem2block_dma_data <= sdmem2block_dma_data_sdmem2blockdma_fsm_next_value; - end - litesdcardcore_sdmem2blockdma_resetinserter_state <= litesdcardcore_sdmem2blockdma_resetinserter_next_state; - if (sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce) begin - sdmem2block_dma_offset <= sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value; - end - if (sdmem2block_dma_reset) begin - sdmem2block_dma_offset <= 32'd0; - litesdcardcore_sdmem2blockdma_resetinserter_state <= 2'd0; - end - if ((sdmem2block_converter_source_valid & sdmem2block_converter_source_ready)) begin - if (sdmem2block_converter_last) begin - sdmem2block_converter_mux <= 1'd0; - end else begin - sdmem2block_converter_mux <= (sdmem2block_converter_mux + 1'd1); - end - end - if (sdmem2block_fifo_syncfifo_re) begin - sdmem2block_fifo_readable <= 1'd1; - end else begin - if (sdmem2block_fifo_re) begin - sdmem2block_fifo_readable <= 1'd0; - end - end - if (((sdmem2block_fifo_syncfifo_we & sdmem2block_fifo_syncfifo_writable) & (~sdmem2block_fifo_replace))) begin - sdmem2block_fifo_produce <= (sdmem2block_fifo_produce + 1'd1); - end - if (sdmem2block_fifo_do_read) begin - sdmem2block_fifo_consume <= (sdmem2block_fifo_consume + 1'd1); - end - if (((sdmem2block_fifo_syncfifo_we & sdmem2block_fifo_syncfifo_writable) & (~sdmem2block_fifo_replace))) begin - if ((~sdmem2block_fifo_do_read)) begin - sdmem2block_fifo_level0 <= (sdmem2block_fifo_level0 + 1'd1); - end - end else begin - if (sdmem2block_fifo_do_read) begin - sdmem2block_fifo_level0 <= (sdmem2block_fifo_level0 - 1'd1); - end - end - if (card_detect_clear) begin - card_detect_pending <= 1'd0; - end - if (card_detect_trigger) begin - card_detect_pending <= 1'd1; - end - if (block2mem_dma_clear) begin - block2mem_dma_pending <= 1'd0; - end - if (block2mem_dma_trigger) begin - block2mem_dma_pending <= 1'd1; - end - if (mem2block_dma_clear) begin - mem2block_dma_pending <= 1'd0; - end - if (mem2block_dma_trigger) begin - mem2block_dma_pending <= 1'd1; - end - litesdcardcore_wishbone2csr_state <= litesdcardcore_wishbone2csr_next_state; - case (grant) - 1'd0: begin - if ((~request[0])) begin - if (request[1]) begin - grant <= 1'd1; - end - end - end - 1'd1: begin - if ((~request[1])) begin - if (request[0]) begin - grant <= 1'd0; - end - end - end - endcase - slave_sel_r <= slave_sel; - if (wait_1) begin - if ((~done)) begin - count <= (count - 1'd1); - end - end else begin - count <= 20'd1000000; - end - interface0_bank_bus_dat_r <= 1'd0; - if (csrbank0_sel) begin - case (interface0_bank_bus_adr[8:0]) - 1'd0: begin - interface0_bank_bus_dat_r <= csrbank0_reset0_w; - end - 1'd1: begin - interface0_bank_bus_dat_r <= csrbank0_scratch0_w; - end - 2'd2: begin - interface0_bank_bus_dat_r <= csrbank0_bus_errors_w; - end - endcase - end - if (csrbank0_reset0_re) begin - reset_storage[1:0] <= csrbank0_reset0_r; - end - reset_re <= csrbank0_reset0_re; - if (csrbank0_scratch0_re) begin - scratch_storage[31:0] <= csrbank0_scratch0_r; - end - scratch_re <= csrbank0_scratch0_re; - bus_errors_re <= csrbank0_bus_errors_re; - interface1_bank_bus_dat_r <= 1'd0; - if (csrbank1_sel) begin - case (interface1_bank_bus_adr[8:0]) - 1'd0: begin - interface1_bank_bus_dat_r <= csrbank1_dma_base1_w; - end - 1'd1: begin - interface1_bank_bus_dat_r <= csrbank1_dma_base0_w; - end - 2'd2: begin - interface1_bank_bus_dat_r <= csrbank1_dma_length0_w; - end - 2'd3: begin - interface1_bank_bus_dat_r <= csrbank1_dma_enable0_w; - end - 3'd4: begin - interface1_bank_bus_dat_r <= csrbank1_dma_done_w; - end - 3'd5: begin - interface1_bank_bus_dat_r <= csrbank1_dma_loop0_w; - end - 3'd6: begin - interface1_bank_bus_dat_r <= csrbank1_dma_offset_w; - end - endcase - end - if (csrbank1_dma_base1_re) begin - sdblock2mem_wishbonedmawriter_base_storage[63:32] <= csrbank1_dma_base1_r; - end - if (csrbank1_dma_base0_re) begin - sdblock2mem_wishbonedmawriter_base_storage[31:0] <= csrbank1_dma_base0_r; - end - sdblock2mem_wishbonedmawriter_base_re <= csrbank1_dma_base0_re; - if (csrbank1_dma_length0_re) begin - sdblock2mem_wishbonedmawriter_length_storage[31:0] <= csrbank1_dma_length0_r; - end - sdblock2mem_wishbonedmawriter_length_re <= csrbank1_dma_length0_re; - if (csrbank1_dma_enable0_re) begin - sdblock2mem_wishbonedmawriter_enable_storage <= csrbank1_dma_enable0_r; - end - sdblock2mem_wishbonedmawriter_enable_re <= csrbank1_dma_enable0_re; - sdblock2mem_wishbonedmawriter_done_re <= csrbank1_dma_done_re; - if (csrbank1_dma_loop0_re) begin - sdblock2mem_wishbonedmawriter_loop_storage <= csrbank1_dma_loop0_r; - end - sdblock2mem_wishbonedmawriter_loop_re <= csrbank1_dma_loop0_re; - sdblock2mem_wishbonedmawriter_offset_re <= csrbank1_dma_offset_re; - interface2_bank_bus_dat_r <= 1'd0; - if (csrbank2_sel) begin - case (interface2_bank_bus_adr[8:0]) - 1'd0: begin - interface2_bank_bus_dat_r <= csrbank2_cmd_argument0_w; - end - 1'd1: begin - interface2_bank_bus_dat_r <= csrbank2_cmd_command0_w; - end - 2'd2: begin - interface2_bank_bus_dat_r <= csrbank2_cmd_send0_w; - end - 2'd3: begin - interface2_bank_bus_dat_r <= csrbank2_cmd_response3_w; - end - 3'd4: begin - interface2_bank_bus_dat_r <= csrbank2_cmd_response2_w; - end - 3'd5: begin - interface2_bank_bus_dat_r <= csrbank2_cmd_response1_w; - end - 3'd6: begin - interface2_bank_bus_dat_r <= csrbank2_cmd_response0_w; - end - 3'd7: begin - interface2_bank_bus_dat_r <= csrbank2_cmd_event_w; - end - 4'd8: begin - interface2_bank_bus_dat_r <= csrbank2_data_event_w; - end - 4'd9: begin - interface2_bank_bus_dat_r <= csrbank2_block_length0_w; - end - 4'd10: begin - interface2_bank_bus_dat_r <= csrbank2_block_count0_w; - end - endcase - end - if (csrbank2_cmd_argument0_re) begin - sdcore_cmd_argument_storage[31:0] <= csrbank2_cmd_argument0_r; - end - sdcore_cmd_argument_re <= csrbank2_cmd_argument0_re; - if (csrbank2_cmd_command0_re) begin - sdcore_cmd_command_storage[13:0] <= csrbank2_cmd_command0_r; - end - sdcore_cmd_command_re <= csrbank2_cmd_command0_re; - if (csrbank2_cmd_send0_re) begin - sdcore_cmd_send_storage <= csrbank2_cmd_send0_r; - end - sdcore_cmd_send_re <= csrbank2_cmd_send0_re; - sdcore_cmd_response_re <= csrbank2_cmd_response0_re; - sdcore_cmd_event_re <= csrbank2_cmd_event_re; - sdcore_data_event_re <= csrbank2_data_event_re; - if (csrbank2_block_length0_re) begin - sdcore_block_length_storage[9:0] <= csrbank2_block_length0_r; - end - sdcore_block_length_re <= csrbank2_block_length0_re; - if (csrbank2_block_count0_re) begin - sdcore_block_count_storage[31:0] <= csrbank2_block_count0_r; - end - sdcore_block_count_re <= csrbank2_block_count0_re; - interface3_bank_bus_dat_r <= 1'd0; - if (csrbank3_sel) begin - case (interface3_bank_bus_adr[8:0]) - 1'd0: begin - interface3_bank_bus_dat_r <= csrbank3_status_w; - end - 1'd1: begin - interface3_bank_bus_dat_r <= csrbank3_pending_w; - end - 2'd2: begin - interface3_bank_bus_dat_r <= csrbank3_enable0_w; - end - endcase - end - eventmanager_status_re <= csrbank3_status_re; - if (csrbank3_pending_re) begin - eventmanager_pending_r[3:0] <= csrbank3_pending_r; - end - eventmanager_pending_re <= csrbank3_pending_re; - if (csrbank3_enable0_re) begin - eventmanager_enable_storage[3:0] <= csrbank3_enable0_r; - end - eventmanager_enable_re <= csrbank3_enable0_re; - interface4_bank_bus_dat_r <= 1'd0; - if (csrbank4_sel) begin - case (interface4_bank_bus_adr[8:0]) - 1'd0: begin - interface4_bank_bus_dat_r <= csrbank4_dma_base1_w; - end - 1'd1: begin - interface4_bank_bus_dat_r <= csrbank4_dma_base0_w; - end - 2'd2: begin - interface4_bank_bus_dat_r <= csrbank4_dma_length0_w; - end - 2'd3: begin - interface4_bank_bus_dat_r <= csrbank4_dma_enable0_w; - end - 3'd4: begin - interface4_bank_bus_dat_r <= csrbank4_dma_done_w; - end - 3'd5: begin - interface4_bank_bus_dat_r <= csrbank4_dma_loop0_w; - end - 3'd6: begin - interface4_bank_bus_dat_r <= csrbank4_dma_offset_w; - end - endcase - end - if (csrbank4_dma_base1_re) begin - sdmem2block_dma_base_storage[63:32] <= csrbank4_dma_base1_r; - end - if (csrbank4_dma_base0_re) begin - sdmem2block_dma_base_storage[31:0] <= csrbank4_dma_base0_r; - end - sdmem2block_dma_base_re <= csrbank4_dma_base0_re; - if (csrbank4_dma_length0_re) begin - sdmem2block_dma_length_storage[31:0] <= csrbank4_dma_length0_r; - end - sdmem2block_dma_length_re <= csrbank4_dma_length0_re; - if (csrbank4_dma_enable0_re) begin - sdmem2block_dma_enable_storage <= csrbank4_dma_enable0_r; - end - sdmem2block_dma_enable_re <= csrbank4_dma_enable0_re; - sdmem2block_dma_done_re <= csrbank4_dma_done_re; - if (csrbank4_dma_loop0_re) begin - sdmem2block_dma_loop_storage <= csrbank4_dma_loop0_r; - end - sdmem2block_dma_loop_re <= csrbank4_dma_loop0_re; - sdmem2block_dma_offset_re <= csrbank4_dma_offset_re; - interface5_bank_bus_dat_r <= 1'd0; - if (csrbank5_sel) begin - case (interface5_bank_bus_adr[8:0]) - 1'd0: begin - interface5_bank_bus_dat_r <= csrbank5_card_detect_w; - end - 1'd1: begin - interface5_bank_bus_dat_r <= csrbank5_clocker_divider0_w; - end - 2'd2: begin - interface5_bank_bus_dat_r <= init_initialize_w; - end - 2'd3: begin - interface5_bank_bus_dat_r <= csrbank5_dataw_status_w; - end - endcase - end - card_detect_re <= csrbank5_card_detect_re; - if (csrbank5_clocker_divider0_re) begin - clocker_storage[8:0] <= csrbank5_clocker_divider0_r; - end - clocker_re <= csrbank5_clocker_divider0_re; - dataw_re <= csrbank5_dataw_status_re; - if (sys_rst) begin - reset_storage <= 2'd0; - reset_re <= 1'd0; - scratch_storage <= 32'd305419896; - scratch_re <= 1'd0; - bus_errors_re <= 1'd0; - bus_errors <= 32'd0; - card_detect_re <= 1'd0; - clocker_storage <= 9'd256; - clocker_re <= 1'd0; - clocker_clks <= 9'd0; - clocker_clk_d <= 1'd0; - clocker_ce_delayed <= 1'd0; - init_count <= 8'd0; - cmdw_count <= 8'd0; - cmdr_timeout <= 32'd48000000; - cmdr_count <= 8'd0; - cmdr_busy <= 1'd0; - cmdr_cmdr_run <= 1'd0; - cmdr_cmdr_converter_source_payload_data <= 8'd0; - cmdr_cmdr_converter_source_payload_valid_token_count <= 4'd0; - cmdr_cmdr_converter_demux <= 3'd0; - cmdr_cmdr_converter_strobe_all <= 1'd0; - cmdr_cmdr_buf_source_valid <= 1'd0; - cmdr_cmdr_buf_source_payload_data <= 8'd0; - cmdr_cmdr_reset <= 1'd0; - dataw_re <= 1'd0; - dataw_count <= 8'd0; - dataw_accepted1 <= 1'd0; - dataw_crc_error1 <= 1'd0; - dataw_write_error1 <= 1'd0; - dataw_crc_run <= 1'd0; - dataw_crc_converter_source_payload_data <= 8'd0; - dataw_crc_converter_source_payload_valid_token_count <= 4'd0; - dataw_crc_converter_demux <= 3'd0; - dataw_crc_converter_strobe_all <= 1'd0; - dataw_crc_buf_source_valid <= 1'd0; - dataw_crc_buf_source_payload_data <= 8'd0; - datar_timeout <= 32'd48000000; - datar_count <= 10'd0; - datar_datar_run <= 1'd0; - datar_datar_converter_source_payload_data <= 8'd0; - datar_datar_converter_source_payload_valid_token_count <= 2'd0; - datar_datar_converter_demux <= 1'd0; - datar_datar_converter_strobe_all <= 1'd0; - datar_datar_buf_source_valid <= 1'd0; - datar_datar_buf_source_payload_data <= 8'd0; - datar_datar_reset <= 1'd0; - sdpads_data_i_ce <= 1'd0; - clocker_clk_delay <= 2'd0; - card_detect_irq <= 1'd0; - card_detect_d <= 1'd0; - sdcore_cmd_argument_storage <= 32'd0; - sdcore_cmd_argument_re <= 1'd0; - sdcore_cmd_command_storage <= 14'd0; - sdcore_cmd_command_re <= 1'd0; - sdcore_cmd_send_storage <= 1'd0; - sdcore_cmd_send_re <= 1'd0; - sdcore_cmd_response_status <= 128'd0; - sdcore_cmd_response_re <= 1'd0; - sdcore_cmd_event_re <= 1'd0; - sdcore_data_event_re <= 1'd0; - sdcore_block_length_storage <= 10'd0; - sdcore_block_length_re <= 1'd0; - sdcore_block_count_storage <= 32'd0; - sdcore_block_count_re <= 1'd0; - sdcore_crc7_inserter_reg0 <= 7'd0; - sdcore_crc16_inserter_count <= 3'd0; - sdcore_crc16_inserter_crc0_reg0 <= 16'd0; - sdcore_crc16_inserter_crc1_reg0 <= 16'd0; - sdcore_crc16_inserter_crc2_reg0 <= 16'd0; - sdcore_crc16_inserter_crc3_reg0 <= 16'd0; - sdcore_fifo_level <= 4'd0; - sdcore_fifo_produce <= 3'd0; - sdcore_fifo_consume <= 3'd0; - sdcore_cmd_count <= 3'd0; - sdcore_cmd_done <= 1'd0; - sdcore_cmd_error <= 1'd0; - sdcore_cmd_timeout <= 1'd0; - sdcore_data_count <= 32'd0; - sdcore_data_done <= 1'd0; - sdcore_data_error <= 1'd0; - sdcore_data_timeout <= 1'd0; - sdblock2mem_irq <= 1'd0; - sdblock2mem_fifo_readable <= 1'd0; - sdblock2mem_fifo_level0 <= 10'd0; - sdblock2mem_fifo_produce <= 9'd0; - sdblock2mem_fifo_consume <= 9'd0; - sdblock2mem_converter_source_payload_data <= 32'd0; - sdblock2mem_converter_source_payload_valid_token_count <= 3'd0; - sdblock2mem_converter_demux <= 2'd0; - sdblock2mem_converter_strobe_all <= 1'd0; - sdblock2mem_wishbonedmawriter_base_storage <= 64'd0; - sdblock2mem_wishbonedmawriter_base_re <= 1'd0; - sdblock2mem_wishbonedmawriter_length_storage <= 32'd0; - sdblock2mem_wishbonedmawriter_length_re <= 1'd0; - sdblock2mem_wishbonedmawriter_enable_storage <= 1'd0; - sdblock2mem_wishbonedmawriter_enable_re <= 1'd0; - sdblock2mem_wishbonedmawriter_done_re <= 1'd0; - sdblock2mem_wishbonedmawriter_loop_storage <= 1'd0; - sdblock2mem_wishbonedmawriter_loop_re <= 1'd0; - sdblock2mem_wishbonedmawriter_offset_re <= 1'd0; - sdblock2mem_wishbonedmawriter_offset <= 32'd0; - sdblock2mem_connect <= 1'd0; - sdblock2mem_done_d <= 1'd0; - sdmem2block_irq <= 1'd0; - sdmem2block_dma_data <= 32'd0; - sdmem2block_dma_base_storage <= 64'd0; - sdmem2block_dma_base_re <= 1'd0; - sdmem2block_dma_length_storage <= 32'd0; - sdmem2block_dma_length_re <= 1'd0; - sdmem2block_dma_enable_storage <= 1'd0; - sdmem2block_dma_enable_re <= 1'd0; - sdmem2block_dma_done_re <= 1'd0; - sdmem2block_dma_loop_storage <= 1'd0; - sdmem2block_dma_loop_re <= 1'd0; - sdmem2block_dma_offset_re <= 1'd0; - sdmem2block_dma_offset <= 32'd0; - sdmem2block_converter_mux <= 2'd0; - sdmem2block_fifo_readable <= 1'd0; - sdmem2block_fifo_level0 <= 10'd0; - sdmem2block_fifo_produce <= 9'd0; - sdmem2block_fifo_consume <= 9'd0; - sdmem2block_count <= 9'd0; - sdmem2block_done_d <= 1'd0; - card_detect_pending <= 1'd0; - block2mem_dma_pending <= 1'd0; - mem2block_dma_pending <= 1'd0; - eventmanager_status_re <= 1'd0; - eventmanager_pending_re <= 1'd0; - eventmanager_pending_r <= 4'd0; - eventmanager_enable_storage <= 4'd0; - eventmanager_enable_re <= 1'd0; - grant <= 1'd0; - slave_sel_r <= 1'd0; - count <= 20'd1000000; - litesdcardcore_sdphyinit_state <= 1'd0; - litesdcardcore_sdphycmdw_state <= 2'd0; - litesdcardcore_sdphycmdr_state <= 3'd0; - litesdcardcore_sdphydataw_state <= 3'd0; - litesdcardcore_sdphydatar_state <= 3'd0; - litesdcardcore_sdcore_crc16inserter_state <= 1'd0; - litesdcardcore_sdcore_fsm_state <= 3'd0; - litesdcardcore_sdblock2memdma_state <= 2'd0; - litesdcardcore_sdmem2blockdma_fsm_state <= 1'd0; - litesdcardcore_sdmem2blockdma_resetinserter_state <= 2'd0; - litesdcardcore_wishbone2csr_state <= 1'd0; - end -end - - -//------------------------------------------------------------------------------ -// Specialized Logic -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Memory storage: 8-words x 10-bit -//------------------------------------------------------------------------------ -// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 -// Port 1 | Read: Async | Write: ---- | -reg [9:0] storage[0:7]; -reg [9:0] storage_dat0; -always @(posedge sys_clk) begin - if (sdcore_fifo_wrport_we) - storage[sdcore_fifo_wrport_adr] <= sdcore_fifo_wrport_dat_w; - storage_dat0 <= storage[sdcore_fifo_wrport_adr]; -end -always @(posedge sys_clk) begin -end -assign sdcore_fifo_wrport_dat_r = storage_dat0; -assign sdcore_fifo_rdport_dat_r = storage[sdcore_fifo_rdport_adr]; - - -//------------------------------------------------------------------------------ -// Memory storage_1: 512-words x 10-bit -//------------------------------------------------------------------------------ -// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 -// Port 1 | Read: Sync | Write: ---- | -reg [9:0] storage_1[0:511]; -reg [9:0] storage_1_dat0; -reg [9:0] storage_1_dat1; -always @(posedge sys_clk) begin - if (sdblock2mem_fifo_wrport_we) - storage_1[sdblock2mem_fifo_wrport_adr] <= sdblock2mem_fifo_wrport_dat_w; - storage_1_dat0 <= storage_1[sdblock2mem_fifo_wrport_adr]; -end -always @(posedge sys_clk) begin - if (sdblock2mem_fifo_rdport_re) - storage_1_dat1 <= storage_1[sdblock2mem_fifo_rdport_adr]; -end -assign sdblock2mem_fifo_wrport_dat_r = storage_1_dat0; -assign sdblock2mem_fifo_rdport_dat_r = storage_1_dat1; - - -//------------------------------------------------------------------------------ -// Memory storage_2: 512-words x 10-bit -//------------------------------------------------------------------------------ -// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 -// Port 1 | Read: Sync | Write: ---- | -reg [9:0] storage_2[0:511]; -reg [9:0] storage_2_dat0; -reg [9:0] storage_2_dat1; -always @(posedge sys_clk) begin - if (sdmem2block_fifo_wrport_we) - storage_2[sdmem2block_fifo_wrport_adr] <= sdmem2block_fifo_wrport_dat_w; - storage_2_dat0 <= storage_2[sdmem2block_fifo_wrport_adr]; -end -always @(posedge sys_clk) begin - if (sdmem2block_fifo_rdport_re) - storage_2_dat1 <= storage_2[sdmem2block_fifo_rdport_adr]; -end -assign sdmem2block_fifo_wrport_dat_r = storage_2_dat0; -assign sdmem2block_fifo_rdport_dat_r = storage_2_dat1; - - -OFS1P3BX OFS1P3BX( - .D((~clocker_clk0)), - .PD(1'd0), - .SCLK(sys_clk), - .SP(1'd1), - .Q(sdcard_clk) -); - -assign sdcard_cmd = inferedsdrtristate0_oe ? inferedsdrtristate0__o : 1'bz; -assign inferedsdrtristate0__i = sdcard_cmd; - -assign sdcard_data[0] = inferedsdrtristate1_oe ? inferedsdrtristate1__o : 1'bz; -assign inferedsdrtristate1__i = sdcard_data[0]; - -assign sdcard_data[1] = inferedsdrtristate2_oe ? inferedsdrtristate2__o : 1'bz; -assign inferedsdrtristate2__i = sdcard_data[1]; - -assign sdcard_data[2] = inferedsdrtristate3_oe ? inferedsdrtristate3__o : 1'bz; -assign inferedsdrtristate3__i = sdcard_data[2]; - -assign sdcard_data[3] = inferedsdrtristate4_oe ? inferedsdrtristate4__o : 1'bz; -assign inferedsdrtristate4__i = sdcard_data[3]; - -OFS1P3BX OFS1P3BX_1( - .D(sdpads_cmd_o), - .PD(1'd0), - .SCLK(sys_clk), - .SP(1'd1), - .Q(inferedsdrtristate0__o) -); - -IFS1P3BX IFS1P3BX( - .D(inferedsdrtristate0__i), - .PD(1'd0), - .SCLK(sys_clk), - .SP(1'd1), - .Q(sdpads_cmd_i) -); - -OFS1P3BX OFS1P3BX_2( - .D(sdpads_data_o[0]), - .PD(1'd0), - .SCLK(sys_clk), - .SP(1'd1), - .Q(inferedsdrtristate1__o) -); - -IFS1P3BX IFS1P3BX_1( - .D(inferedsdrtristate1__i), - .PD(1'd0), - .SCLK(sys_clk), - .SP(1'd1), - .Q(sdpads_data_i[0]) -); - -OFS1P3BX OFS1P3BX_3( - .D(sdpads_data_o[1]), - .PD(1'd0), - .SCLK(sys_clk), - .SP(1'd1), - .Q(inferedsdrtristate2__o) -); - -IFS1P3BX IFS1P3BX_2( - .D(inferedsdrtristate2__i), - .PD(1'd0), - .SCLK(sys_clk), - .SP(1'd1), - .Q(sdpads_data_i[1]) -); - -OFS1P3BX OFS1P3BX_4( - .D(sdpads_data_o[2]), - .PD(1'd0), - .SCLK(sys_clk), - .SP(1'd1), - .Q(inferedsdrtristate3__o) -); - -IFS1P3BX IFS1P3BX_3( - .D(inferedsdrtristate3__i), - .PD(1'd0), - .SCLK(sys_clk), - .SP(1'd1), - .Q(sdpads_data_i[2]) -); - -OFS1P3BX OFS1P3BX_5( - .D(sdpads_data_o[3]), - .PD(1'd0), - .SCLK(sys_clk), - .SP(1'd1), - .Q(inferedsdrtristate4__o) -); - -IFS1P3BX IFS1P3BX_4( - .D(inferedsdrtristate4__i), - .PD(1'd0), - .SCLK(sys_clk), - .SP(1'd1), - .Q(sdpads_data_i[3]) -); - -endmodule - -// ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2022-08-04 18:14:15. -//------------------------------------------------------------------------------ diff --git a/litesdcard/generated/xilinx.100e6/litesdcard_core.v b/litesdcard/generated/xilinx.100e6/litesdcard_core.v new file mode 100644 index 0000000..5266241 --- /dev/null +++ b/litesdcard/generated/xilinx.100e6/litesdcard_core.v @@ -0,0 +1,4587 @@ +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : litesdcard_core.v +// Device : +// LiteX sha1 : 87137c30 +// Date : 2024-04-03 20:02:06 +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ps + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module litesdcard_core ( + input wire clk, + output wire irq, + input wire rst, + input wire sdcard_cd, + output reg sdcard_clk, + inout wire sdcard_cmd, + output reg sdcard_cmd_dir, + output reg sdcard_dat0_dir, + output reg sdcard_dat13_dir, + inout wire [3:0] sdcard_data, + output wire wb_ctrl_ack, + input wire [29:0] wb_ctrl_adr, + input wire [1:0] wb_ctrl_bte, + input wire [2:0] wb_ctrl_cti, + input wire wb_ctrl_cyc, + output wire [31:0] wb_ctrl_dat_r, + input wire [31:0] wb_ctrl_dat_w, + output wire wb_ctrl_err, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_stb, + input wire wb_ctrl_we, + input wire wb_dma_ack, + output wire [29:0] wb_dma_adr, + output wire [1:0] wb_dma_bte, + output wire [2:0] wb_dma_cti, + output wire wb_dma_cyc, + input wire [31:0] wb_dma_dat_r, + output wire [31:0] wb_dma_dat_w, + input wire wb_dma_err, + output wire [3:0] wb_dma_sel, + output wire wb_dma_stb, + output wire wb_dma_we +); + + +//------------------------------------------------------------------------------ +// Hierarchy +//------------------------------------------------------------------------------ + +/* +LiteSDCardCore +└─── crg (CRG) +└─── bus (SoCBusHandler) +│ └─── _interconnect (InterconnectPointToPoint) +└─── csr (SoCCSRHandler) +└─── irq (SoCIRQHandler) +└─── ctrl (SoCController) +└─── cpu (CPUNone) +└─── dma_bus (SoCBusHandler) +│ └─── _interconnect (InterconnectShared) +│ │ └─── arbiter (Arbiter) +│ │ │ └─── rr (RoundRobin) +│ │ └─── decoder (Decoder) +│ │ └─── timeout (Timeout) +│ │ │ └─── waittimer_0* (WaitTimer) +└─── sdcard_phy (SDPHY) +│ └─── clocker (SDPHYClocker) +│ │ └─── [BUFG] +│ └─── init (SDPHYInit) +│ │ └─── fsm_0* (FSM) +│ └─── cmdw (SDPHYCMDW) +│ │ └─── fsm_0* (FSM) +│ └─── cmdr (SDPHYCMDR) +│ │ └─── sdphyr_0* (SDPHYR) +│ │ │ └─── converter_0* (Converter) +│ │ │ │ └─── _upconverter_0* (_UpConverter) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ └─── fsm_0* (FSM) +│ └─── dataw (SDPHYDATAW) +│ │ └─── crc (SDPHYR) +│ │ │ └─── converter_0* (Converter) +│ │ │ │ └─── _upconverter_0* (_UpConverter) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ └─── fsm (FSM) +│ └─── datar (SDPHYDATAR) +│ │ └─── sdphyr_0* (SDPHYR) +│ │ │ └─── converter_0* (Converter) +│ │ │ │ └─── _upconverter_0* (_UpConverter) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ └─── fsm_0* (FSM) +│ └─── io (SDPHYIOGen) +└─── sdcard_core (SDCore) +│ └─── crc7_inserter (CRC) +│ └─── crc16_inserter (CRC16Inserter) +│ │ └─── crc_0* (CRC) +│ │ └─── crc_1* (CRC) +│ │ └─── crc_2* (CRC) +│ │ └─── crc_3* (CRC) +│ │ └─── fsm (FSM) +│ └─── crc16_checker (CRC16Checker) +│ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ └─── fifo (SyncFIFO) +│ └─── fsm (FSM) +└─── sdcard_block2mem (SDBlock2MemDMA) +│ └─── syncfifo_0* (SyncFIFO) +│ │ └─── fifo (SyncFIFOBuffered) +│ │ │ └─── fifo (SyncFIFO) +│ └─── converter_0* (Converter) +│ │ └─── _upconverter_0* (_UpConverter) +│ └─── dma (WishboneDMAWriter) +│ │ └─── fsm (FSM) +└─── sdcard_mem2block (SDMem2BlockDMA) +│ └─── dma (WishboneDMAReader) +│ │ └─── fifo (SyncFIFO) +│ │ │ └─── fifo (SyncFIFO) +│ │ └─── fsm (FSM) +│ └─── converter_0* (Converter) +│ │ └─── _downconverter_0* (_DownConverter) +│ └─── syncfifo_0* (SyncFIFO) +│ │ └─── fifo (SyncFIFOBuffered) +│ │ │ └─── fifo (SyncFIFO) +└─── sdcard_irq (EventManager) +│ └─── eventsourcepulse_0* (EventSourcePulse) +│ └─── eventsourcepulse_1* (EventSourcePulse) +│ └─── eventsourcepulse_2* (EventSourcePulse) +│ └─── eventsourcelevel_0* (EventSourceLevel) +└─── csr_bridge (Wishbone2CSR) +│ └─── fsm (FSM) +└─── csr_bankarray (CSRBankArray) +│ └─── csrbank_0* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ └─── csrbank_1* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstatus_1* (CSRStatus) +│ └─── csrbank_2* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstatus_1* (CSRStatus) +│ │ └─── csrstatus_2* (CSRStatus) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstorage_4* (CSRStorage) +│ └─── csrbank_3* (CSRBank) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstatus_1* (CSRStatus) +│ │ └─── csrstorage_0* (CSRStorage) +│ └─── csrbank_4* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstatus_1* (CSRStatus) +│ └─── csrbank_5* (CSRBank) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstatus_1* (CSRStatus) +└─── csr_interconnect (InterconnectShared) +└─── [IOBUF] +└─── [IOBUF] +└─── [IOBUF] +└─── [IOBUF] +└─── [IOBUF] +* : Generated name. +[]: BlackBox. +*/ + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +wire [13:0] adr; +reg block2mem_dma_clear = 1'd0; +reg block2mem_dma_pending = 1'd0; +wire block2mem_dma_status; +wire block2mem_dma_trigger; +reg bus_error = 1'd0; +reg [31:0] bus_errors = 32'd0; +reg bus_errors_re = 1'd0; +wire [31:0] bus_errors_status; +wire bus_errors_we; +reg card_detect_clear = 1'd0; +reg card_detect_d = 1'd0; +reg card_detect_irq = 1'd0; +reg card_detect_pending = 1'd0; +reg card_detect_re = 1'd0; +wire card_detect_status0; +wire card_detect_status1; +wire card_detect_trigger; +wire card_detect_we; +wire clocker_ce; +reg clocker_ce_delayed = 1'd0; +reg clocker_ce_latched = 1'd0; +wire clocker_clk0; +reg clocker_clk1 = 1'd0; +reg clocker_clk_d = 1'd0; +reg [1:0] clocker_clk_delay = 2'd0; +wire clocker_clk_en; +reg [8:0] clocker_clks = 9'd0; +reg clocker_re = 1'd0; +wire clocker_stop; +reg [8:0] clocker_storage = 9'd256; +reg cmd_done_clear = 1'd0; +wire cmd_done_pending; +wire cmd_done_status; +wire cmd_done_trigger; +reg cmdr_busy = 1'd0; +reg cmdr_busy_sdphycmdr_next_value2 = 1'd0; +reg cmdr_busy_sdphycmdr_next_value_ce2 = 1'd0; +wire cmdr_cmdr_buf_pipe_valid_sink_first; +wire cmdr_cmdr_buf_pipe_valid_sink_last; +wire [7:0] cmdr_cmdr_buf_pipe_valid_sink_payload_data; +wire cmdr_cmdr_buf_pipe_valid_sink_ready; +wire cmdr_cmdr_buf_pipe_valid_sink_valid; +reg cmdr_cmdr_buf_pipe_valid_source_first = 1'd0; +reg cmdr_cmdr_buf_pipe_valid_source_last = 1'd0; +reg [7:0] cmdr_cmdr_buf_pipe_valid_source_payload_data = 8'd0; +wire cmdr_cmdr_buf_pipe_valid_source_ready; +reg cmdr_cmdr_buf_pipe_valid_source_valid = 1'd0; +wire cmdr_cmdr_buf_sink_sink_first; +wire cmdr_cmdr_buf_sink_sink_last; +wire [7:0] cmdr_cmdr_buf_sink_sink_payload_data; +wire cmdr_cmdr_buf_sink_sink_ready; +wire cmdr_cmdr_buf_sink_sink_valid; +wire cmdr_cmdr_buf_source_source_first; +wire cmdr_cmdr_buf_source_source_last; +wire [7:0] cmdr_cmdr_buf_source_source_payload_data; +wire cmdr_cmdr_buf_source_source_ready; +wire cmdr_cmdr_buf_source_source_valid; +reg [2:0] cmdr_cmdr_converter_converter_demux = 3'd0; +wire cmdr_cmdr_converter_converter_load_part; +reg cmdr_cmdr_converter_converter_sink_first = 1'd0; +reg cmdr_cmdr_converter_converter_sink_last = 1'd0; +wire cmdr_cmdr_converter_converter_sink_payload_data; +wire cmdr_cmdr_converter_converter_sink_ready; +wire cmdr_cmdr_converter_converter_sink_valid; +reg cmdr_cmdr_converter_converter_source_first = 1'd0; +reg cmdr_cmdr_converter_converter_source_last = 1'd0; +reg [7:0] cmdr_cmdr_converter_converter_source_payload_data = 8'd0; +reg [3:0] cmdr_cmdr_converter_converter_source_payload_valid_token_count = 4'd0; +wire cmdr_cmdr_converter_converter_source_ready; +wire cmdr_cmdr_converter_converter_source_valid; +reg cmdr_cmdr_converter_converter_strobe_all = 1'd0; +wire cmdr_cmdr_converter_source_source_first; +wire cmdr_cmdr_converter_source_source_last; +wire [7:0] cmdr_cmdr_converter_source_source_payload_data; +wire cmdr_cmdr_converter_source_source_ready; +wire cmdr_cmdr_converter_source_source_valid; +wire cmdr_cmdr_pads_in_first; +wire cmdr_cmdr_pads_in_last; +wire cmdr_cmdr_pads_in_payload_clk; +wire cmdr_cmdr_pads_in_payload_cmd_i; +wire cmdr_cmdr_pads_in_payload_cmd_o; +wire cmdr_cmdr_pads_in_payload_cmd_oe; +wire [3:0] cmdr_cmdr_pads_in_payload_data_i; +wire cmdr_cmdr_pads_in_payload_data_i_ce; +wire [3:0] cmdr_cmdr_pads_in_payload_data_o; +wire cmdr_cmdr_pads_in_payload_data_oe; +reg cmdr_cmdr_pads_in_ready = 1'd0; +wire cmdr_cmdr_pads_in_valid; +reg cmdr_cmdr_reset = 1'd0; +reg cmdr_cmdr_reset_sdphycmdr_next_value3 = 1'd0; +reg cmdr_cmdr_reset_sdphycmdr_next_value_ce3 = 1'd0; +reg cmdr_cmdr_run = 1'd0; +wire cmdr_cmdr_source_first; +wire cmdr_cmdr_source_last; +wire [7:0] cmdr_cmdr_source_payload_data; +reg cmdr_cmdr_source_ready = 1'd0; +wire cmdr_cmdr_source_valid; +wire cmdr_cmdr_start; +reg [7:0] cmdr_count = 8'd0; +reg [7:0] cmdr_count_sdphycmdr_next_value1 = 8'd0; +reg cmdr_count_sdphycmdr_next_value_ce1 = 1'd0; +reg cmdr_pads_in_pads_in_first = 1'd0; +reg cmdr_pads_in_pads_in_last = 1'd0; +reg cmdr_pads_in_pads_in_payload_clk = 1'd0; +wire cmdr_pads_in_pads_in_payload_cmd_i; +reg cmdr_pads_in_pads_in_payload_cmd_o = 1'd0; +reg cmdr_pads_in_pads_in_payload_cmd_oe = 1'd0; +wire [3:0] cmdr_pads_in_pads_in_payload_data_i; +reg cmdr_pads_in_pads_in_payload_data_i_ce = 1'd0; +reg [3:0] cmdr_pads_in_pads_in_payload_data_o = 4'd0; +reg cmdr_pads_in_pads_in_payload_data_oe = 1'd0; +wire cmdr_pads_in_pads_in_ready; +wire cmdr_pads_in_pads_in_valid; +reg cmdr_pads_out_payload_clk = 1'd0; +reg cmdr_pads_out_payload_cmd_o = 1'd0; +reg cmdr_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] cmdr_pads_out_payload_data_o = 4'd0; +reg cmdr_pads_out_payload_data_oe = 1'd0; +wire cmdr_pads_out_ready; +reg [1:0] cmdr_sink_payload_cmd_type = 2'd0; +reg [1:0] cmdr_sink_payload_data_type = 2'd0; +reg [7:0] cmdr_sink_payload_length = 8'd0; +reg cmdr_sink_ready = 1'd0; +reg cmdr_sink_valid = 1'd0; +reg cmdr_source_source_last = 1'd0; +reg [7:0] cmdr_source_source_payload_data = 8'd0; +reg [2:0] cmdr_source_source_payload_status = 3'd0; +reg cmdr_source_source_ready = 1'd0; +reg cmdr_source_source_valid = 1'd0; +reg [31:0] cmdr_timeout = 32'd100000000; +reg [31:0] cmdr_timeout_sdphycmdr_next_value0 = 32'd0; +reg cmdr_timeout_sdphycmdr_next_value_ce0 = 1'd0; +reg [7:0] cmdw_count = 8'd0; +reg [7:0] cmdw_count_sdphycmdw_next_value = 8'd0; +reg cmdw_count_sdphycmdw_next_value_ce = 1'd0; +reg cmdw_done = 1'd0; +wire cmdw_pads_in_payload_cmd_i; +wire [3:0] cmdw_pads_in_payload_data_i; +wire cmdw_pads_in_valid; +reg cmdw_pads_out_payload_clk = 1'd0; +reg cmdw_pads_out_payload_cmd_o = 1'd0; +reg cmdw_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] cmdw_pads_out_payload_data_o = 4'd0; +reg cmdw_pads_out_payload_data_oe = 1'd0; +wire cmdw_pads_out_ready; +reg cmdw_sink_last = 1'd0; +reg [1:0] cmdw_sink_payload_cmd_type = 2'd0; +reg [7:0] cmdw_sink_payload_data = 8'd0; +reg cmdw_sink_ready = 1'd0; +reg cmdw_sink_valid = 1'd0; +reg [19:0] count = 20'd1000000; +wire cpu_rst; +reg crc16inserter_next_state = 1'd0; +reg crc16inserter_state = 1'd0; +wire [31:0] csrbank0_bus_errors_r; +reg csrbank0_bus_errors_re = 1'd0; +wire [31:0] csrbank0_bus_errors_w; +reg csrbank0_bus_errors_we = 1'd0; +wire [1:0] csrbank0_reset0_r; +reg csrbank0_reset0_re = 1'd0; +wire [1:0] csrbank0_reset0_w; +reg csrbank0_reset0_we = 1'd0; +wire [31:0] csrbank0_scratch0_r; +reg csrbank0_scratch0_re = 1'd0; +wire [31:0] csrbank0_scratch0_w; +reg csrbank0_scratch0_we = 1'd0; +wire csrbank0_sel; +wire [31:0] csrbank1_dma_base0_r; +reg csrbank1_dma_base0_re = 1'd0; +wire [31:0] csrbank1_dma_base0_w; +reg csrbank1_dma_base0_we = 1'd0; +wire [31:0] csrbank1_dma_base1_r; +reg csrbank1_dma_base1_re = 1'd0; +wire [31:0] csrbank1_dma_base1_w; +reg csrbank1_dma_base1_we = 1'd0; +wire csrbank1_dma_done_r; +reg csrbank1_dma_done_re = 1'd0; +wire csrbank1_dma_done_w; +reg csrbank1_dma_done_we = 1'd0; +wire csrbank1_dma_enable0_r; +reg csrbank1_dma_enable0_re = 1'd0; +wire csrbank1_dma_enable0_w; +reg csrbank1_dma_enable0_we = 1'd0; +wire [31:0] csrbank1_dma_length0_r; +reg csrbank1_dma_length0_re = 1'd0; +wire [31:0] csrbank1_dma_length0_w; +reg csrbank1_dma_length0_we = 1'd0; +wire csrbank1_dma_loop0_r; +reg csrbank1_dma_loop0_re = 1'd0; +wire csrbank1_dma_loop0_w; +reg csrbank1_dma_loop0_we = 1'd0; +wire [31:0] csrbank1_dma_offset_r; +reg csrbank1_dma_offset_re = 1'd0; +wire [31:0] csrbank1_dma_offset_w; +reg csrbank1_dma_offset_we = 1'd0; +wire csrbank1_sel; +wire [31:0] csrbank2_block_count0_r; +reg csrbank2_block_count0_re = 1'd0; +wire [31:0] csrbank2_block_count0_w; +reg csrbank2_block_count0_we = 1'd0; +wire [9:0] csrbank2_block_length0_r; +reg csrbank2_block_length0_re = 1'd0; +wire [9:0] csrbank2_block_length0_w; +reg csrbank2_block_length0_we = 1'd0; +wire [31:0] csrbank2_cmd_argument0_r; +reg csrbank2_cmd_argument0_re = 1'd0; +wire [31:0] csrbank2_cmd_argument0_w; +reg csrbank2_cmd_argument0_we = 1'd0; +wire [13:0] csrbank2_cmd_command0_r; +reg csrbank2_cmd_command0_re = 1'd0; +wire [13:0] csrbank2_cmd_command0_w; +reg csrbank2_cmd_command0_we = 1'd0; +wire [3:0] csrbank2_cmd_event_r; +reg csrbank2_cmd_event_re = 1'd0; +wire [3:0] csrbank2_cmd_event_w; +reg csrbank2_cmd_event_we = 1'd0; +wire [31:0] csrbank2_cmd_response0_r; +reg csrbank2_cmd_response0_re = 1'd0; +wire [31:0] csrbank2_cmd_response0_w; +reg csrbank2_cmd_response0_we = 1'd0; +wire [31:0] csrbank2_cmd_response1_r; +reg csrbank2_cmd_response1_re = 1'd0; +wire [31:0] csrbank2_cmd_response1_w; +reg csrbank2_cmd_response1_we = 1'd0; +wire [31:0] csrbank2_cmd_response2_r; +reg csrbank2_cmd_response2_re = 1'd0; +wire [31:0] csrbank2_cmd_response2_w; +reg csrbank2_cmd_response2_we = 1'd0; +wire [31:0] csrbank2_cmd_response3_r; +reg csrbank2_cmd_response3_re = 1'd0; +wire [31:0] csrbank2_cmd_response3_w; +reg csrbank2_cmd_response3_we = 1'd0; +wire csrbank2_cmd_send0_r; +reg csrbank2_cmd_send0_re = 1'd0; +wire csrbank2_cmd_send0_w; +reg csrbank2_cmd_send0_we = 1'd0; +wire [3:0] csrbank2_data_event_r; +reg csrbank2_data_event_re = 1'd0; +wire [3:0] csrbank2_data_event_w; +reg csrbank2_data_event_we = 1'd0; +wire csrbank2_sel; +wire [3:0] csrbank3_enable0_r; +reg csrbank3_enable0_re = 1'd0; +wire [3:0] csrbank3_enable0_w; +reg csrbank3_enable0_we = 1'd0; +wire [3:0] csrbank3_pending_r; +reg csrbank3_pending_re = 1'd0; +wire [3:0] csrbank3_pending_w; +reg csrbank3_pending_we = 1'd0; +wire csrbank3_sel; +wire [3:0] csrbank3_status_r; +reg csrbank3_status_re = 1'd0; +wire [3:0] csrbank3_status_w; +reg csrbank3_status_we = 1'd0; +wire [31:0] csrbank4_dma_base0_r; +reg csrbank4_dma_base0_re = 1'd0; +wire [31:0] csrbank4_dma_base0_w; +reg csrbank4_dma_base0_we = 1'd0; +wire [31:0] csrbank4_dma_base1_r; +reg csrbank4_dma_base1_re = 1'd0; +wire [31:0] csrbank4_dma_base1_w; +reg csrbank4_dma_base1_we = 1'd0; +wire csrbank4_dma_done_r; +reg csrbank4_dma_done_re = 1'd0; +wire csrbank4_dma_done_w; +reg csrbank4_dma_done_we = 1'd0; +wire csrbank4_dma_enable0_r; +reg csrbank4_dma_enable0_re = 1'd0; +wire csrbank4_dma_enable0_w; +reg csrbank4_dma_enable0_we = 1'd0; +wire [31:0] csrbank4_dma_length0_r; +reg csrbank4_dma_length0_re = 1'd0; +wire [31:0] csrbank4_dma_length0_w; +reg csrbank4_dma_length0_we = 1'd0; +wire csrbank4_dma_loop0_r; +reg csrbank4_dma_loop0_re = 1'd0; +wire csrbank4_dma_loop0_w; +reg csrbank4_dma_loop0_we = 1'd0; +wire [31:0] csrbank4_dma_offset_r; +reg csrbank4_dma_offset_re = 1'd0; +wire [31:0] csrbank4_dma_offset_w; +reg csrbank4_dma_offset_we = 1'd0; +wire csrbank4_sel; +wire csrbank5_card_detect_r; +reg csrbank5_card_detect_re = 1'd0; +wire csrbank5_card_detect_w; +reg csrbank5_card_detect_we = 1'd0; +wire [8:0] csrbank5_clocker_divider0_r; +reg csrbank5_clocker_divider0_re = 1'd0; +wire [8:0] csrbank5_clocker_divider0_w; +reg csrbank5_clocker_divider0_we = 1'd0; +wire [2:0] csrbank5_dataw_status_r; +reg csrbank5_dataw_status_re = 1'd0; +wire [2:0] csrbank5_dataw_status_w; +reg csrbank5_dataw_status_we = 1'd0; +wire csrbank5_sel; +wire [31:0] dat_r; +wire [31:0] dat_w; +reg [9:0] datar_count = 10'd0; +reg [9:0] datar_count_sdphydatar_next_value0 = 10'd0; +reg datar_count_sdphydatar_next_value_ce0 = 1'd0; +wire datar_datar_buf_pipe_valid_sink_first; +wire datar_datar_buf_pipe_valid_sink_last; +wire [7:0] datar_datar_buf_pipe_valid_sink_payload_data; +wire datar_datar_buf_pipe_valid_sink_ready; +wire datar_datar_buf_pipe_valid_sink_valid; +reg datar_datar_buf_pipe_valid_source_first = 1'd0; +reg datar_datar_buf_pipe_valid_source_last = 1'd0; +reg [7:0] datar_datar_buf_pipe_valid_source_payload_data = 8'd0; +wire datar_datar_buf_pipe_valid_source_ready; +reg datar_datar_buf_pipe_valid_source_valid = 1'd0; +wire datar_datar_buf_sink_sink_first; +wire datar_datar_buf_sink_sink_last; +wire [7:0] datar_datar_buf_sink_sink_payload_data; +wire datar_datar_buf_sink_sink_ready; +wire datar_datar_buf_sink_sink_valid; +wire datar_datar_buf_source_source_first; +wire datar_datar_buf_source_source_last; +wire [7:0] datar_datar_buf_source_source_payload_data; +wire datar_datar_buf_source_source_ready; +wire datar_datar_buf_source_source_valid; +reg datar_datar_converter_converter_demux = 1'd0; +wire datar_datar_converter_converter_load_part; +reg datar_datar_converter_converter_sink_first = 1'd0; +reg datar_datar_converter_converter_sink_last = 1'd0; +wire [3:0] datar_datar_converter_converter_sink_payload_data; +wire datar_datar_converter_converter_sink_ready; +wire datar_datar_converter_converter_sink_valid; +reg datar_datar_converter_converter_source_first = 1'd0; +reg datar_datar_converter_converter_source_last = 1'd0; +reg [7:0] datar_datar_converter_converter_source_payload_data = 8'd0; +reg [1:0] datar_datar_converter_converter_source_payload_valid_token_count = 2'd0; +wire datar_datar_converter_converter_source_ready; +wire datar_datar_converter_converter_source_valid; +reg datar_datar_converter_converter_strobe_all = 1'd0; +wire datar_datar_converter_source_source_first; +wire datar_datar_converter_source_source_last; +wire [7:0] datar_datar_converter_source_source_payload_data; +wire datar_datar_converter_source_source_ready; +wire datar_datar_converter_source_source_valid; +wire datar_datar_pads_in_first; +wire datar_datar_pads_in_last; +wire datar_datar_pads_in_payload_clk; +wire datar_datar_pads_in_payload_cmd_i; +wire datar_datar_pads_in_payload_cmd_o; +wire datar_datar_pads_in_payload_cmd_oe; +wire [3:0] datar_datar_pads_in_payload_data_i; +wire datar_datar_pads_in_payload_data_i_ce; +wire [3:0] datar_datar_pads_in_payload_data_o; +wire datar_datar_pads_in_payload_data_oe; +reg datar_datar_pads_in_ready = 1'd0; +wire datar_datar_pads_in_valid; +reg datar_datar_reset = 1'd0; +reg datar_datar_reset_sdphydatar_next_value2 = 1'd0; +reg datar_datar_reset_sdphydatar_next_value_ce2 = 1'd0; +reg datar_datar_run = 1'd0; +wire datar_datar_source_first; +wire datar_datar_source_last; +wire [7:0] datar_datar_source_payload_data; +reg datar_datar_source_ready = 1'd0; +wire datar_datar_source_valid; +wire datar_datar_start; +reg datar_pads_in_pads_in_first = 1'd0; +reg datar_pads_in_pads_in_last = 1'd0; +reg datar_pads_in_pads_in_payload_clk = 1'd0; +wire datar_pads_in_pads_in_payload_cmd_i; +reg datar_pads_in_pads_in_payload_cmd_o = 1'd0; +reg datar_pads_in_pads_in_payload_cmd_oe = 1'd0; +wire [3:0] datar_pads_in_pads_in_payload_data_i; +reg datar_pads_in_pads_in_payload_data_i_ce = 1'd0; +reg [3:0] datar_pads_in_pads_in_payload_data_o = 4'd0; +reg datar_pads_in_pads_in_payload_data_oe = 1'd0; +wire datar_pads_in_pads_in_ready; +wire datar_pads_in_pads_in_valid; +reg datar_pads_out_payload_clk = 1'd0; +reg datar_pads_out_payload_cmd_o = 1'd0; +reg datar_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] datar_pads_out_payload_data_o = 4'd0; +reg datar_pads_out_payload_data_oe = 1'd0; +wire datar_pads_out_ready; +reg datar_sink_last = 1'd0; +reg [9:0] datar_sink_payload_block_length = 10'd0; +reg datar_sink_ready = 1'd0; +reg datar_sink_valid = 1'd0; +reg datar_source_source_first = 1'd0; +reg datar_source_source_last = 1'd0; +reg [7:0] datar_source_source_payload_data = 8'd0; +reg [2:0] datar_source_source_payload_status = 3'd0; +reg datar_source_source_ready = 1'd0; +reg datar_source_source_valid = 1'd0; +reg datar_stop = 1'd0; +reg [31:0] datar_timeout = 32'd100000000; +reg [31:0] datar_timeout_sdphydatar_next_value1 = 32'd0; +reg datar_timeout_sdphydatar_next_value_ce1 = 1'd0; +wire dataw_accepted0; +reg dataw_accepted1 = 1'd0; +reg dataw_accepted1_sdphydataw_next_value0 = 1'd0; +reg dataw_accepted1_sdphydataw_next_value_ce0 = 1'd0; +reg [7:0] dataw_count = 8'd0; +reg [7:0] dataw_count_sdphydataw_next_value3 = 8'd0; +reg dataw_count_sdphydataw_next_value_ce3 = 1'd0; +wire dataw_crc_buf_pipe_valid_sink_first; +wire dataw_crc_buf_pipe_valid_sink_last; +wire [7:0] dataw_crc_buf_pipe_valid_sink_payload_data; +wire dataw_crc_buf_pipe_valid_sink_ready; +wire dataw_crc_buf_pipe_valid_sink_valid; +reg dataw_crc_buf_pipe_valid_source_first = 1'd0; +reg dataw_crc_buf_pipe_valid_source_last = 1'd0; +reg [7:0] dataw_crc_buf_pipe_valid_source_payload_data = 8'd0; +wire dataw_crc_buf_pipe_valid_source_ready; +reg dataw_crc_buf_pipe_valid_source_valid = 1'd0; +wire dataw_crc_buf_sink_sink_first; +wire dataw_crc_buf_sink_sink_last; +wire [7:0] dataw_crc_buf_sink_sink_payload_data; +wire dataw_crc_buf_sink_sink_ready; +wire dataw_crc_buf_sink_sink_valid; +wire dataw_crc_buf_source_source_first; +wire dataw_crc_buf_source_source_last; +wire [7:0] dataw_crc_buf_source_source_payload_data; +wire dataw_crc_buf_source_source_ready; +wire dataw_crc_buf_source_source_valid; +reg [2:0] dataw_crc_converter_converter_demux = 3'd0; +wire dataw_crc_converter_converter_load_part; +reg dataw_crc_converter_converter_sink_first = 1'd0; +reg dataw_crc_converter_converter_sink_last = 1'd0; +wire dataw_crc_converter_converter_sink_payload_data; +wire dataw_crc_converter_converter_sink_ready; +wire dataw_crc_converter_converter_sink_valid; +reg dataw_crc_converter_converter_source_first = 1'd0; +reg dataw_crc_converter_converter_source_last = 1'd0; +reg [7:0] dataw_crc_converter_converter_source_payload_data = 8'd0; +reg [3:0] dataw_crc_converter_converter_source_payload_valid_token_count = 4'd0; +wire dataw_crc_converter_converter_source_ready; +wire dataw_crc_converter_converter_source_valid; +reg dataw_crc_converter_converter_strobe_all = 1'd0; +wire dataw_crc_converter_source_source_first; +wire dataw_crc_converter_source_source_last; +wire [7:0] dataw_crc_converter_source_source_payload_data; +wire dataw_crc_converter_source_source_ready; +wire dataw_crc_converter_source_source_valid; +wire dataw_crc_error0; +reg dataw_crc_error1 = 1'd0; +reg dataw_crc_error1_sdphydataw_next_value1 = 1'd0; +reg dataw_crc_error1_sdphydataw_next_value_ce1 = 1'd0; +wire dataw_crc_pads_in_first; +wire dataw_crc_pads_in_last; +wire dataw_crc_pads_in_payload_clk; +wire dataw_crc_pads_in_payload_cmd_i; +wire dataw_crc_pads_in_payload_cmd_o; +wire dataw_crc_pads_in_payload_cmd_oe; +wire [3:0] dataw_crc_pads_in_payload_data_i; +wire dataw_crc_pads_in_payload_data_i_ce; +wire [3:0] dataw_crc_pads_in_payload_data_o; +wire dataw_crc_pads_in_payload_data_oe; +wire dataw_crc_pads_in_ready; +wire dataw_crc_pads_in_valid; +reg dataw_crc_reset = 1'd0; +reg dataw_crc_run = 1'd0; +wire dataw_crc_source_first; +wire dataw_crc_source_last; +wire [7:0] dataw_crc_source_payload_data; +reg dataw_crc_source_ready = 1'd0; +wire dataw_crc_source_valid; +wire dataw_crc_start; +reg dataw_pads_in_pads_in_first = 1'd0; +reg dataw_pads_in_pads_in_last = 1'd0; +reg dataw_pads_in_pads_in_payload_clk = 1'd0; +wire dataw_pads_in_pads_in_payload_cmd_i; +reg dataw_pads_in_pads_in_payload_cmd_o = 1'd0; +reg dataw_pads_in_pads_in_payload_cmd_oe = 1'd0; +wire [3:0] dataw_pads_in_pads_in_payload_data_i; +reg dataw_pads_in_pads_in_payload_data_i_ce = 1'd0; +reg [3:0] dataw_pads_in_pads_in_payload_data_o = 4'd0; +reg dataw_pads_in_pads_in_payload_data_oe = 1'd0; +reg dataw_pads_in_pads_in_ready = 1'd0; +wire dataw_pads_in_pads_in_valid; +reg dataw_pads_out_payload_clk = 1'd0; +reg dataw_pads_out_payload_cmd_o = 1'd0; +reg dataw_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] dataw_pads_out_payload_data_o = 4'd0; +reg dataw_pads_out_payload_data_oe = 1'd0; +wire dataw_pads_out_ready; +reg dataw_re = 1'd0; +reg dataw_sink_first = 1'd0; +reg dataw_sink_last = 1'd0; +reg [7:0] dataw_sink_payload_data = 8'd0; +reg dataw_sink_ready = 1'd0; +reg dataw_sink_valid = 1'd0; +reg [2:0] dataw_status = 3'd0; +reg dataw_stop = 1'd0; +wire dataw_we; +wire dataw_write_error0; +reg dataw_write_error1 = 1'd0; +reg dataw_write_error1_sdphydataw_next_value2 = 1'd0; +reg dataw_write_error1_sdphydataw_next_value_ce2 = 1'd0; +wire done; +reg error = 1'd0; +wire eventmanager_block2mem_dma0; +wire eventmanager_block2mem_dma1; +wire eventmanager_block2mem_dma2; +wire eventmanager_card_detect0; +wire eventmanager_card_detect1; +wire eventmanager_card_detect2; +wire eventmanager_cmd_done0; +wire eventmanager_cmd_done1; +wire eventmanager_cmd_done2; +reg eventmanager_enable_re = 1'd0; +reg [3:0] eventmanager_enable_storage = 4'd0; +wire eventmanager_mem2block_dma0; +wire eventmanager_mem2block_dma1; +wire eventmanager_mem2block_dma2; +reg [3:0] eventmanager_pending_r = 4'd0; +reg eventmanager_pending_re = 1'd0; +reg [3:0] eventmanager_pending_status = 4'd0; +wire eventmanager_pending_we; +reg eventmanager_status_re = 1'd0; +reg [3:0] eventmanager_status_status = 4'd0; +wire eventmanager_status_we; +reg [2:0] fsm_next_state = 3'd0; +reg [2:0] fsm_state = 3'd0; +reg grant = 1'd0; +reg [7:0] init_count = 8'd0; +reg [7:0] init_count_sdphyinit_next_value = 8'd0; +reg init_count_sdphyinit_next_value_ce = 1'd0; +wire init_initialize_r; +reg init_initialize_re = 1'd0; +reg init_initialize_w = 1'd0; +reg init_initialize_we = 1'd0; +wire init_pads_in_payload_cmd_i; +wire [3:0] init_pads_in_payload_data_i; +wire init_pads_in_valid; +reg init_pads_out_payload_clk = 1'd0; +reg init_pads_out_payload_cmd_o = 1'd0; +reg init_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] init_pads_out_payload_data_o = 4'd0; +reg init_pads_out_payload_data_oe = 1'd0; +wire init_pads_out_ready; +reg int_rst = 1'd1; +reg interface0_ack = 1'd0; +wire [29:0] interface0_adr; +wire [13:0] interface0_bank_bus_adr; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; +wire [31:0] interface0_bank_bus_dat_w; +wire interface0_bank_bus_we; +wire [1:0] interface0_bte; +wire interface0_bus_ack; +wire [31:0] interface0_bus_adr; +reg [1:0] interface0_bus_bte = 2'd0; +reg [2:0] interface0_bus_cti = 3'd0; +wire interface0_bus_cyc; +wire [31:0] interface0_bus_dat_r; +wire [31:0] interface0_bus_dat_w; +wire interface0_bus_err; +wire [3:0] interface0_bus_sel; +wire interface0_bus_stb; +wire interface0_bus_we; +wire [2:0] interface0_cti; +wire interface0_cyc; +reg [31:0] interface0_dat_r = 32'd0; +wire [31:0] interface0_dat_w; +reg interface0_err = 1'd0; +wire [3:0] interface0_sel; +wire interface0_stb; +wire interface0_we; +reg [13:0] interface1_adr = 14'd0; +wire [13:0] interface1_bank_bus_adr; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; +wire [31:0] interface1_bank_bus_dat_w; +wire interface1_bank_bus_we; +wire interface1_bus_ack; +wire [31:0] interface1_bus_adr; +reg [1:0] interface1_bus_bte = 2'd0; +reg [2:0] interface1_bus_cti = 3'd0; +wire interface1_bus_cyc; +wire [31:0] interface1_bus_dat_r; +reg [31:0] interface1_bus_dat_w = 32'd0; +wire interface1_bus_err; +wire [3:0] interface1_bus_sel; +wire interface1_bus_stb; +wire interface1_bus_we; +wire [31:0] interface1_dat_r; +reg [31:0] interface1_dat_w = 32'd0; +reg interface1_we = 1'd0; +wire [13:0] interface2_bank_bus_adr; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; +wire [31:0] interface2_bank_bus_dat_w; +wire interface2_bank_bus_we; +wire [13:0] interface3_bank_bus_adr; +reg [31:0] interface3_bank_bus_dat_r = 32'd0; +wire [31:0] interface3_bank_bus_dat_w; +wire interface3_bank_bus_we; +wire [13:0] interface4_bank_bus_adr; +reg [31:0] interface4_bank_bus_dat_r = 32'd0; +wire [31:0] interface4_bank_bus_dat_w; +wire interface4_bank_bus_we; +wire [13:0] interface5_bank_bus_adr; +reg [31:0] interface5_bank_bus_dat_r = 32'd0; +wire [31:0] interface5_bank_bus_dat_w; +wire interface5_bank_bus_we; +reg mem2block_dma_clear = 1'd0; +reg mem2block_dma_pending = 1'd0; +wire mem2block_dma_status; +wire mem2block_dma_trigger; +wire por_clk; +wire [1:0] request; +reg reset_re = 1'd0; +reg [1:0] reset_storage = 2'd0; +reg scratch_re = 1'd0; +reg [31:0] scratch_storage = 32'd305419896; +reg [1:0] sdblock2memdma_next_state = 2'd0; +reg [1:0] sdblock2memdma_state = 2'd0; +reg sdcard_block2mem_connect = 1'd0; +reg [1:0] sdcard_block2mem_converter_demux = 2'd0; +wire sdcard_block2mem_converter_load_part; +wire sdcard_block2mem_converter_sink_first; +wire sdcard_block2mem_converter_sink_last; +wire [7:0] sdcard_block2mem_converter_sink_payload_data; +wire sdcard_block2mem_converter_sink_ready; +wire sdcard_block2mem_converter_sink_valid; +reg sdcard_block2mem_converter_source_first = 1'd0; +reg sdcard_block2mem_converter_source_last = 1'd0; +reg [31:0] sdcard_block2mem_converter_source_payload_data = 32'd0; +reg [2:0] sdcard_block2mem_converter_source_payload_valid_token_count = 3'd0; +wire sdcard_block2mem_converter_source_ready; +wire sdcard_block2mem_converter_source_valid; +reg sdcard_block2mem_converter_strobe_all = 1'd0; +reg sdcard_block2mem_done_d = 1'd0; +reg [8:0] sdcard_block2mem_fifo_consume = 9'd0; +wire sdcard_block2mem_fifo_do_read; +wire sdcard_block2mem_fifo_fifo_in_first; +wire sdcard_block2mem_fifo_fifo_in_last; +wire [7:0] sdcard_block2mem_fifo_fifo_in_payload_data; +wire sdcard_block2mem_fifo_fifo_out_first; +wire sdcard_block2mem_fifo_fifo_out_last; +wire [7:0] sdcard_block2mem_fifo_fifo_out_payload_data; +reg [9:0] sdcard_block2mem_fifo_level0 = 10'd0; +wire [9:0] sdcard_block2mem_fifo_level1; +reg [8:0] sdcard_block2mem_fifo_produce = 9'd0; +wire [8:0] sdcard_block2mem_fifo_rdport_adr; +wire [9:0] sdcard_block2mem_fifo_rdport_dat_r; +wire sdcard_block2mem_fifo_rdport_re; +wire sdcard_block2mem_fifo_re; +reg sdcard_block2mem_fifo_readable = 1'd0; +reg sdcard_block2mem_fifo_replace = 1'd0; +reg sdcard_block2mem_fifo_sink_first = 1'd0; +reg sdcard_block2mem_fifo_sink_last = 1'd0; +reg [7:0] sdcard_block2mem_fifo_sink_payload_data = 8'd0; +wire sdcard_block2mem_fifo_sink_ready; +reg sdcard_block2mem_fifo_sink_valid = 1'd0; +wire sdcard_block2mem_fifo_source_first; +wire sdcard_block2mem_fifo_source_last; +wire [7:0] sdcard_block2mem_fifo_source_payload_data; +wire sdcard_block2mem_fifo_source_ready; +wire sdcard_block2mem_fifo_source_valid; +wire [9:0] sdcard_block2mem_fifo_syncfifo_din; +wire [9:0] sdcard_block2mem_fifo_syncfifo_dout; +wire sdcard_block2mem_fifo_syncfifo_re; +wire sdcard_block2mem_fifo_syncfifo_readable; +wire sdcard_block2mem_fifo_syncfifo_we; +wire sdcard_block2mem_fifo_syncfifo_writable; +reg [8:0] sdcard_block2mem_fifo_wrport_adr = 9'd0; +wire [9:0] sdcard_block2mem_fifo_wrport_dat_r; +wire [9:0] sdcard_block2mem_fifo_wrport_dat_w; +wire sdcard_block2mem_fifo_wrport_we; +reg sdcard_block2mem_irq = 1'd0; +wire sdcard_block2mem_sink_sink_first; +wire sdcard_block2mem_sink_sink_last0; +reg sdcard_block2mem_sink_sink_last1 = 1'd0; +reg [31:0] sdcard_block2mem_sink_sink_payload_address = 32'd0; +wire [7:0] sdcard_block2mem_sink_sink_payload_data0; +reg [31:0] sdcard_block2mem_sink_sink_payload_data1 = 32'd0; +reg sdcard_block2mem_sink_sink_ready0 = 1'd0; +wire sdcard_block2mem_sink_sink_ready1; +wire sdcard_block2mem_sink_sink_valid0; +reg sdcard_block2mem_sink_sink_valid1 = 1'd0; +wire sdcard_block2mem_source_source_first; +wire sdcard_block2mem_source_source_last; +wire [31:0] sdcard_block2mem_source_source_payload_data; +wire sdcard_block2mem_source_source_ready; +wire sdcard_block2mem_source_source_valid; +wire sdcard_block2mem_start; +wire [31:0] sdcard_block2mem_wishbonedmawriter_base; +reg sdcard_block2mem_wishbonedmawriter_base_re = 1'd0; +reg [63:0] sdcard_block2mem_wishbonedmawriter_base_storage = 64'd0; +reg sdcard_block2mem_wishbonedmawriter_done_re = 1'd0; +reg sdcard_block2mem_wishbonedmawriter_done_status = 1'd0; +wire sdcard_block2mem_wishbonedmawriter_done_we; +reg sdcard_block2mem_wishbonedmawriter_enable_re = 1'd0; +reg sdcard_block2mem_wishbonedmawriter_enable_storage = 1'd0; +wire [31:0] sdcard_block2mem_wishbonedmawriter_length; +reg sdcard_block2mem_wishbonedmawriter_length_re = 1'd0; +reg [31:0] sdcard_block2mem_wishbonedmawriter_length_storage = 32'd0; +reg sdcard_block2mem_wishbonedmawriter_loop_re = 1'd0; +reg sdcard_block2mem_wishbonedmawriter_loop_storage = 1'd0; +reg [31:0] sdcard_block2mem_wishbonedmawriter_offset = 32'd0; +reg sdcard_block2mem_wishbonedmawriter_offset_re = 1'd0; +reg [31:0] sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value = 32'd0; +reg sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce = 1'd0; +wire [31:0] sdcard_block2mem_wishbonedmawriter_offset_status; +wire sdcard_block2mem_wishbonedmawriter_offset_we; +wire sdcard_block2mem_wishbonedmawriter_reset; +wire sdcard_block2mem_wishbonedmawriter_sink_first; +wire sdcard_block2mem_wishbonedmawriter_sink_last; +wire [31:0] sdcard_block2mem_wishbonedmawriter_sink_payload_data; +reg sdcard_block2mem_wishbonedmawriter_sink_ready = 1'd0; +wire sdcard_block2mem_wishbonedmawriter_sink_valid; +reg sdcard_core_block_count_re = 1'd0; +reg [31:0] sdcard_core_block_count_storage = 32'd0; +reg sdcard_core_block_length_re = 1'd0; +reg [9:0] sdcard_core_block_length_storage = 10'd0; +wire [5:0] sdcard_core_cmd; +reg sdcard_core_cmd_argument_re = 1'd0; +reg [31:0] sdcard_core_cmd_argument_storage = 32'd0; +reg sdcard_core_cmd_command_re = 1'd0; +reg [13:0] sdcard_core_cmd_command_storage = 14'd0; +reg [2:0] sdcard_core_cmd_count = 3'd0; +reg [2:0] sdcard_core_cmd_count_fsm_next_value2 = 3'd0; +reg sdcard_core_cmd_count_fsm_next_value_ce2 = 1'd0; +reg sdcard_core_cmd_done = 1'd0; +reg sdcard_core_cmd_done_fsm_next_value0 = 1'd0; +reg sdcard_core_cmd_done_fsm_next_value_ce0 = 1'd0; +reg sdcard_core_cmd_error = 1'd0; +reg sdcard_core_cmd_error_fsm_next_value4 = 1'd0; +reg sdcard_core_cmd_error_fsm_next_value_ce4 = 1'd0; +reg sdcard_core_cmd_event_re = 1'd0; +reg [3:0] sdcard_core_cmd_event_status = 4'd0; +wire sdcard_core_cmd_event_we; +reg sdcard_core_cmd_response_re = 1'd0; +reg [127:0] sdcard_core_cmd_response_status = 128'd0; +reg [127:0] sdcard_core_cmd_response_status_fsm_next_value8 = 128'd0; +reg sdcard_core_cmd_response_status_fsm_next_value_ce8 = 1'd0; +wire sdcard_core_cmd_response_we; +reg sdcard_core_cmd_send_re = 1'd0; +reg sdcard_core_cmd_send_storage = 1'd0; +reg sdcard_core_cmd_timeout = 1'd0; +reg sdcard_core_cmd_timeout_fsm_next_value5 = 1'd0; +reg sdcard_core_cmd_timeout_fsm_next_value_ce5 = 1'd0; +wire [1:0] sdcard_core_cmd_type; +reg [2:0] sdcard_core_crc16_inserter_count = 3'd0; +reg [2:0] sdcard_core_crc16_inserter_count_crc16inserter_next_value = 3'd0; +reg sdcard_core_crc16_inserter_count_crc16inserter_next_value_ce = 1'd0; +reg [15:0] sdcard_core_crc16_inserter_crc00 = 16'd0; +wire [15:0] sdcard_core_crc16_inserter_crc01; +wire [15:0] sdcard_core_crc16_inserter_crc02; +reg [15:0] sdcard_core_crc16_inserter_crc0_crc = 16'd0; +reg [1:0] sdcard_core_crc16_inserter_crc0_din = 2'd0; +wire sdcard_core_crc16_inserter_crc0_enable; +wire sdcard_core_crc16_inserter_crc0_reset; +reg [15:0] sdcard_core_crc16_inserter_crc10 = 16'd0; +wire [15:0] sdcard_core_crc16_inserter_crc11; +wire [15:0] sdcard_core_crc16_inserter_crc12; +reg [15:0] sdcard_core_crc16_inserter_crc1_crc = 16'd0; +reg [1:0] sdcard_core_crc16_inserter_crc1_din = 2'd0; +wire sdcard_core_crc16_inserter_crc1_enable; +wire sdcard_core_crc16_inserter_crc1_reset; +reg [15:0] sdcard_core_crc16_inserter_crc20 = 16'd0; +wire [15:0] sdcard_core_crc16_inserter_crc21; +wire [15:0] sdcard_core_crc16_inserter_crc22; +reg [15:0] sdcard_core_crc16_inserter_crc2_crc = 16'd0; +reg [1:0] sdcard_core_crc16_inserter_crc2_din = 2'd0; +wire sdcard_core_crc16_inserter_crc2_enable; +wire sdcard_core_crc16_inserter_crc2_reset; +reg [15:0] sdcard_core_crc16_inserter_crc30 = 16'd0; +wire [15:0] sdcard_core_crc16_inserter_crc31; +wire [15:0] sdcard_core_crc16_inserter_crc32; +reg [15:0] sdcard_core_crc16_inserter_crc3_crc = 16'd0; +reg [1:0] sdcard_core_crc16_inserter_crc3_din = 2'd0; +wire sdcard_core_crc16_inserter_crc3_enable; +wire sdcard_core_crc16_inserter_crc3_reset; +wire sdcard_core_crc16_inserter_sink_first; +wire sdcard_core_crc16_inserter_sink_last; +wire [7:0] sdcard_core_crc16_inserter_sink_payload_data; +reg sdcard_core_crc16_inserter_sink_ready = 1'd0; +wire sdcard_core_crc16_inserter_sink_valid; +reg sdcard_core_crc16_inserter_source_first = 1'd0; +reg sdcard_core_crc16_inserter_source_last = 1'd0; +reg [7:0] sdcard_core_crc16_inserter_source_payload_data = 8'd0; +reg sdcard_core_crc16_inserter_source_ready = 1'd0; +reg sdcard_core_crc16_inserter_source_valid = 1'd0; +reg [6:0] sdcard_core_crc7_inserter_crc0 = 7'd0; +wire [6:0] sdcard_core_crc7_inserter_crc1; +wire [6:0] sdcard_core_crc7_inserter_crc10; +wire [6:0] sdcard_core_crc7_inserter_crc11; +wire [6:0] sdcard_core_crc7_inserter_crc12; +wire [6:0] sdcard_core_crc7_inserter_crc13; +wire [6:0] sdcard_core_crc7_inserter_crc14; +wire [6:0] sdcard_core_crc7_inserter_crc15; +wire [6:0] sdcard_core_crc7_inserter_crc16; +wire [6:0] sdcard_core_crc7_inserter_crc17; +wire [6:0] sdcard_core_crc7_inserter_crc18; +wire [6:0] sdcard_core_crc7_inserter_crc19; +wire [6:0] sdcard_core_crc7_inserter_crc2; +wire [6:0] sdcard_core_crc7_inserter_crc20; +wire [6:0] sdcard_core_crc7_inserter_crc21; +wire [6:0] sdcard_core_crc7_inserter_crc22; +wire [6:0] sdcard_core_crc7_inserter_crc23; +wire [6:0] sdcard_core_crc7_inserter_crc24; +wire [6:0] sdcard_core_crc7_inserter_crc25; +wire [6:0] sdcard_core_crc7_inserter_crc26; +wire [6:0] sdcard_core_crc7_inserter_crc27; +wire [6:0] sdcard_core_crc7_inserter_crc28; +wire [6:0] sdcard_core_crc7_inserter_crc29; +wire [6:0] sdcard_core_crc7_inserter_crc3; +wire [6:0] sdcard_core_crc7_inserter_crc30; +wire [6:0] sdcard_core_crc7_inserter_crc31; +wire [6:0] sdcard_core_crc7_inserter_crc32; +wire [6:0] sdcard_core_crc7_inserter_crc33; +wire [6:0] sdcard_core_crc7_inserter_crc34; +wire [6:0] sdcard_core_crc7_inserter_crc35; +wire [6:0] sdcard_core_crc7_inserter_crc36; +wire [6:0] sdcard_core_crc7_inserter_crc37; +wire [6:0] sdcard_core_crc7_inserter_crc38; +wire [6:0] sdcard_core_crc7_inserter_crc39; +wire [6:0] sdcard_core_crc7_inserter_crc4; +wire [6:0] sdcard_core_crc7_inserter_crc40; +wire [6:0] sdcard_core_crc7_inserter_crc5; +wire [6:0] sdcard_core_crc7_inserter_crc6; +wire [6:0] sdcard_core_crc7_inserter_crc7; +wire [6:0] sdcard_core_crc7_inserter_crc8; +wire [6:0] sdcard_core_crc7_inserter_crc9; +reg [6:0] sdcard_core_crc7_inserter_crc_crc = 7'd0; +wire [39:0] sdcard_core_crc7_inserter_crc_din; +wire sdcard_core_crc7_inserter_crc_enable; +wire sdcard_core_crc7_inserter_crc_reset; +wire [5:0] sdcard_core_csrfield_cmd; +wire [1:0] sdcard_core_csrfield_cmd_type; +wire sdcard_core_csrfield_crc0; +wire sdcard_core_csrfield_crc1; +wire [1:0] sdcard_core_csrfield_data_type; +wire sdcard_core_csrfield_done0; +wire sdcard_core_csrfield_done1; +wire sdcard_core_csrfield_error0; +wire sdcard_core_csrfield_error1; +wire sdcard_core_csrfield_timeout0; +wire sdcard_core_csrfield_timeout1; +reg [31:0] sdcard_core_data_count = 32'd0; +reg [31:0] sdcard_core_data_count_fsm_next_value3 = 32'd0; +reg sdcard_core_data_count_fsm_next_value_ce3 = 1'd0; +reg sdcard_core_data_done = 1'd0; +reg sdcard_core_data_done_fsm_next_value1 = 1'd0; +reg sdcard_core_data_done_fsm_next_value_ce1 = 1'd0; +reg sdcard_core_data_error = 1'd0; +reg sdcard_core_data_error_fsm_next_value6 = 1'd0; +reg sdcard_core_data_error_fsm_next_value_ce6 = 1'd0; +reg sdcard_core_data_event_re = 1'd0; +reg [3:0] sdcard_core_data_event_status = 4'd0; +wire sdcard_core_data_event_we; +reg sdcard_core_data_timeout = 1'd0; +reg sdcard_core_data_timeout_fsm_next_value7 = 1'd0; +reg sdcard_core_data_timeout_fsm_next_value_ce7 = 1'd0; +wire [1:0] sdcard_core_data_type; +reg sdcard_core_done_d = 1'd0; +reg [2:0] sdcard_core_fifo_consume = 3'd0; +wire sdcard_core_fifo_do_read; +wire sdcard_core_fifo_fifo_in_first; +wire sdcard_core_fifo_fifo_in_last; +wire [7:0] sdcard_core_fifo_fifo_in_payload_data; +wire sdcard_core_fifo_fifo_out_first; +wire sdcard_core_fifo_fifo_out_last; +wire [7:0] sdcard_core_fifo_fifo_out_payload_data; +reg [3:0] sdcard_core_fifo_level = 4'd0; +reg [2:0] sdcard_core_fifo_produce = 3'd0; +wire [2:0] sdcard_core_fifo_rdport_adr; +wire [9:0] sdcard_core_fifo_rdport_dat_r; +reg sdcard_core_fifo_replace = 1'd0; +wire sdcard_core_fifo_reset; +wire sdcard_core_fifo_sink_first; +wire sdcard_core_fifo_sink_last; +wire [7:0] sdcard_core_fifo_sink_payload_data; +wire sdcard_core_fifo_sink_ready; +wire sdcard_core_fifo_sink_valid; +wire sdcard_core_fifo_source_first; +wire sdcard_core_fifo_source_last; +wire [7:0] sdcard_core_fifo_source_payload_data; +wire sdcard_core_fifo_source_ready; +wire sdcard_core_fifo_source_valid; +wire [9:0] sdcard_core_fifo_syncfifo_din; +wire [9:0] sdcard_core_fifo_syncfifo_dout; +wire sdcard_core_fifo_syncfifo_re; +wire sdcard_core_fifo_syncfifo_readable; +wire sdcard_core_fifo_syncfifo_we; +wire sdcard_core_fifo_syncfifo_writable; +reg [2:0] sdcard_core_fifo_wrport_adr = 3'd0; +wire [9:0] sdcard_core_fifo_wrport_dat_r; +wire [9:0] sdcard_core_fifo_wrport_dat_w; +wire sdcard_core_fifo_wrport_we; +reg sdcard_core_irq = 1'd0; +wire sdcard_core_sink_sink_first0; +reg sdcard_core_sink_sink_first1 = 1'd0; +wire sdcard_core_sink_sink_last0; +reg sdcard_core_sink_sink_last1 = 1'd0; +wire [7:0] sdcard_core_sink_sink_payload_data0; +reg [7:0] sdcard_core_sink_sink_payload_data1 = 8'd0; +wire sdcard_core_sink_sink_ready0; +wire sdcard_core_sink_sink_ready1; +wire sdcard_core_sink_sink_valid0; +reg sdcard_core_sink_sink_valid1 = 1'd0; +wire sdcard_core_source_source_first0; +wire sdcard_core_source_source_first1; +wire sdcard_core_source_source_last0; +wire sdcard_core_source_source_last1; +wire [7:0] sdcard_core_source_source_payload_data0; +wire [7:0] sdcard_core_source_source_payload_data1; +wire sdcard_core_source_source_ready0; +wire sdcard_core_source_source_ready1; +wire sdcard_core_source_source_valid0; +wire sdcard_core_source_source_valid1; +wire sdcard_irq_irq; +wire sdcard_mem2block_converter_converter_first; +wire sdcard_mem2block_converter_converter_last; +reg [1:0] sdcard_mem2block_converter_converter_mux = 2'd0; +wire sdcard_mem2block_converter_converter_sink_first; +wire sdcard_mem2block_converter_converter_sink_last; +wire [31:0] sdcard_mem2block_converter_converter_sink_payload_data; +wire sdcard_mem2block_converter_converter_sink_ready; +wire sdcard_mem2block_converter_converter_sink_valid; +wire sdcard_mem2block_converter_converter_source_first; +wire sdcard_mem2block_converter_converter_source_last; +reg [7:0] sdcard_mem2block_converter_converter_source_payload_data = 8'd0; +wire sdcard_mem2block_converter_converter_source_payload_valid_token_count; +wire sdcard_mem2block_converter_converter_source_ready; +wire sdcard_mem2block_converter_converter_source_valid; +wire sdcard_mem2block_converter_source_source_first; +wire sdcard_mem2block_converter_source_source_last; +wire [7:0] sdcard_mem2block_converter_source_source_payload_data; +wire sdcard_mem2block_converter_source_source_ready; +wire sdcard_mem2block_converter_source_source_valid; +reg [8:0] sdcard_mem2block_count = 9'd0; +wire [31:0] sdcard_mem2block_dma_base; +reg sdcard_mem2block_dma_base_re = 1'd0; +reg [63:0] sdcard_mem2block_dma_base_storage = 64'd0; +reg sdcard_mem2block_dma_done_re = 1'd0; +reg sdcard_mem2block_dma_done_status = 1'd0; +wire sdcard_mem2block_dma_done_we; +reg sdcard_mem2block_dma_enable_re = 1'd0; +reg sdcard_mem2block_dma_enable_storage = 1'd0; +reg [3:0] sdcard_mem2block_dma_fifo_consume = 4'd0; +wire sdcard_mem2block_dma_fifo_do_read; +wire sdcard_mem2block_dma_fifo_fifo_in_first; +wire sdcard_mem2block_dma_fifo_fifo_in_last; +wire [31:0] sdcard_mem2block_dma_fifo_fifo_in_payload_data; +wire sdcard_mem2block_dma_fifo_fifo_out_first; +wire sdcard_mem2block_dma_fifo_fifo_out_last; +wire [31:0] sdcard_mem2block_dma_fifo_fifo_out_payload_data; +reg [4:0] sdcard_mem2block_dma_fifo_level = 5'd0; +reg [3:0] sdcard_mem2block_dma_fifo_produce = 4'd0; +wire [3:0] sdcard_mem2block_dma_fifo_rdport_adr; +wire [33:0] sdcard_mem2block_dma_fifo_rdport_dat_r; +reg sdcard_mem2block_dma_fifo_replace = 1'd0; +reg sdcard_mem2block_dma_fifo_sink_first = 1'd0; +wire sdcard_mem2block_dma_fifo_sink_last; +wire [31:0] sdcard_mem2block_dma_fifo_sink_payload_data; +wire sdcard_mem2block_dma_fifo_sink_ready; +reg sdcard_mem2block_dma_fifo_sink_valid = 1'd0; +wire sdcard_mem2block_dma_fifo_source_first; +wire sdcard_mem2block_dma_fifo_source_last; +wire [31:0] sdcard_mem2block_dma_fifo_source_payload_data; +wire sdcard_mem2block_dma_fifo_source_ready; +wire sdcard_mem2block_dma_fifo_source_valid; +wire [33:0] sdcard_mem2block_dma_fifo_syncfifo_din; +wire [33:0] sdcard_mem2block_dma_fifo_syncfifo_dout; +wire sdcard_mem2block_dma_fifo_syncfifo_re; +wire sdcard_mem2block_dma_fifo_syncfifo_readable; +wire sdcard_mem2block_dma_fifo_syncfifo_we; +wire sdcard_mem2block_dma_fifo_syncfifo_writable; +reg [3:0] sdcard_mem2block_dma_fifo_wrport_adr = 4'd0; +wire [33:0] sdcard_mem2block_dma_fifo_wrport_dat_r; +wire [33:0] sdcard_mem2block_dma_fifo_wrport_dat_w; +wire sdcard_mem2block_dma_fifo_wrport_we; +wire [31:0] sdcard_mem2block_dma_length; +reg sdcard_mem2block_dma_length_re = 1'd0; +reg [31:0] sdcard_mem2block_dma_length_storage = 32'd0; +reg sdcard_mem2block_dma_loop_re = 1'd0; +reg sdcard_mem2block_dma_loop_storage = 1'd0; +reg [31:0] sdcard_mem2block_dma_offset = 32'd0; +reg sdcard_mem2block_dma_offset_re = 1'd0; +reg [31:0] sdcard_mem2block_dma_offset_sdmem2blockdma_next_value = 32'd0; +reg sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce = 1'd0; +wire [31:0] sdcard_mem2block_dma_offset_status; +wire sdcard_mem2block_dma_offset_we; +wire sdcard_mem2block_dma_reset; +reg sdcard_mem2block_dma_sink_sink_last = 1'd0; +reg [31:0] sdcard_mem2block_dma_sink_sink_payload_address = 32'd0; +reg sdcard_mem2block_dma_sink_sink_ready = 1'd0; +reg sdcard_mem2block_dma_sink_sink_valid = 1'd0; +wire sdcard_mem2block_dma_source_source_first; +wire sdcard_mem2block_dma_source_source_last; +wire [31:0] sdcard_mem2block_dma_source_source_payload_data; +wire sdcard_mem2block_dma_source_source_ready; +wire sdcard_mem2block_dma_source_source_valid; +reg sdcard_mem2block_done_d = 1'd0; +reg [8:0] sdcard_mem2block_fifo_consume = 9'd0; +wire sdcard_mem2block_fifo_do_read; +wire sdcard_mem2block_fifo_fifo_in_first; +wire sdcard_mem2block_fifo_fifo_in_last; +wire [7:0] sdcard_mem2block_fifo_fifo_in_payload_data; +wire sdcard_mem2block_fifo_fifo_out_first; +wire sdcard_mem2block_fifo_fifo_out_last; +wire [7:0] sdcard_mem2block_fifo_fifo_out_payload_data; +reg [9:0] sdcard_mem2block_fifo_level0 = 10'd0; +wire [9:0] sdcard_mem2block_fifo_level1; +reg [8:0] sdcard_mem2block_fifo_produce = 9'd0; +wire [8:0] sdcard_mem2block_fifo_rdport_adr; +wire [9:0] sdcard_mem2block_fifo_rdport_dat_r; +wire sdcard_mem2block_fifo_rdport_re; +wire sdcard_mem2block_fifo_re; +reg sdcard_mem2block_fifo_readable = 1'd0; +reg sdcard_mem2block_fifo_replace = 1'd0; +wire sdcard_mem2block_fifo_sink_first; +wire sdcard_mem2block_fifo_sink_last; +wire [7:0] sdcard_mem2block_fifo_sink_payload_data; +wire sdcard_mem2block_fifo_sink_ready; +wire sdcard_mem2block_fifo_sink_valid; +wire sdcard_mem2block_fifo_source_first; +wire sdcard_mem2block_fifo_source_last; +wire [7:0] sdcard_mem2block_fifo_source_payload_data; +wire sdcard_mem2block_fifo_source_ready; +wire sdcard_mem2block_fifo_source_valid; +wire [9:0] sdcard_mem2block_fifo_syncfifo_din; +wire [9:0] sdcard_mem2block_fifo_syncfifo_dout; +wire sdcard_mem2block_fifo_syncfifo_re; +wire sdcard_mem2block_fifo_syncfifo_readable; +wire sdcard_mem2block_fifo_syncfifo_we; +wire sdcard_mem2block_fifo_syncfifo_writable; +reg [8:0] sdcard_mem2block_fifo_wrport_adr = 9'd0; +wire [9:0] sdcard_mem2block_fifo_wrport_dat_r; +wire [9:0] sdcard_mem2block_fifo_wrport_dat_w; +wire sdcard_mem2block_fifo_wrport_we; +reg sdcard_mem2block_irq = 1'd0; +wire sdcard_mem2block_source_source_first; +reg sdcard_mem2block_source_source_last = 1'd0; +wire [7:0] sdcard_mem2block_source_source_payload_data; +wire sdcard_mem2block_source_source_ready; +wire sdcard_mem2block_source_source_valid; +reg [1:0] sdmem2blockdma_next_state = 2'd0; +reg [1:0] sdmem2blockdma_state = 2'd0; +wire sdpads_clk; +reg sdpads_cmd_i = 1'd0; +wire sdpads_cmd_o; +wire sdpads_cmd_oe; +reg [3:0] sdpads_data_i = 4'd0; +reg sdpads_data_i_ce = 1'd0; +wire [3:0] sdpads_data_o; +wire sdpads_data_oe; +reg [2:0] sdphycmdr_next_state = 3'd0; +reg [2:0] sdphycmdr_state = 3'd0; +reg [1:0] sdphycmdw_next_state = 2'd0; +reg [1:0] sdphycmdw_state = 2'd0; +reg [2:0] sdphydatar_next_state = 3'd0; +reg [2:0] sdphydatar_state = 3'd0; +reg [2:0] sdphydataw_next_state = 3'd0; +reg [2:0] sdphydataw_state = 3'd0; +reg sdphyinit_next_state = 1'd0; +reg sdphyinit_state = 1'd0; +wire sdrio_clk; +wire sdrio_clk_1; +wire sdrio_clk_10; +wire sdrio_clk_11; +wire sdrio_clk_12; +wire sdrio_clk_13; +wire sdrio_clk_14; +wire sdrio_clk_15; +wire sdrio_clk_16; +wire sdrio_clk_17; +wire sdrio_clk_18; +wire sdrio_clk_2; +wire sdrio_clk_3; +wire sdrio_clk_4; +wire sdrio_clk_5; +wire sdrio_clk_6; +wire sdrio_clk_7; +wire sdrio_clk_8; +wire sdrio_clk_9; +reg [31:0] self0 = 32'd0; +reg [31:0] self1 = 32'd0; +reg [3:0] self2 = 4'd0; +reg self3 = 1'd0; +reg self4 = 1'd0; +reg self5 = 1'd0; +reg [2:0] self6 = 3'd0; +reg [1:0] self7 = 2'd0; +reg shared_ack = 1'd0; +wire [31:0] shared_adr; +wire [1:0] shared_bte; +wire [2:0] shared_cti; +wire shared_cyc; +reg [31:0] shared_dat_r = 32'd0; +wire [31:0] shared_dat_w; +wire shared_err; +wire [3:0] shared_sel; +wire shared_stb; +wire shared_we; +reg slave_sel = 1'd0; +reg slave_sel_r = 1'd0; +reg soc_rst = 1'd0; +wire sys_clk; +wire sys_rst; +wire wait_1; +wire wb_ctrl_ack_1; +wire [29:0] wb_ctrl_adr_1; +wire [1:0] wb_ctrl_bte_1; +wire [2:0] wb_ctrl_cti_1; +wire wb_ctrl_cyc_1; +wire [31:0] wb_ctrl_dat_r_1; +wire [31:0] wb_ctrl_dat_w_1; +wire wb_ctrl_err_1; +wire [3:0] wb_ctrl_sel_1; +wire wb_ctrl_stb_1; +wire wb_ctrl_we_1; +wire wb_dma_ack_1; +wire [29:0] wb_dma_adr_1; +wire [1:0] wb_dma_bte_1; +wire [2:0] wb_dma_cti_1; +wire wb_dma_cyc_1; +wire [31:0] wb_dma_dat_r_1; +wire [31:0] wb_dma_dat_w_1; +wire wb_dma_err_1; +wire [3:0] wb_dma_sel_1; +wire wb_dma_stb_1; +wire wb_dma_we_1; +wire we; +reg wishbone2csr_next_state = 1'd0; +reg wishbone2csr_state = 1'd0; +wire xilinxsdrtristateimpl0__i; +reg xilinxsdrtristateimpl0__o = 1'd0; +reg xilinxsdrtristateimpl0_oe_n = 1'd0; +wire xilinxsdrtristateimpl1__i; +reg xilinxsdrtristateimpl1__o = 1'd0; +reg xilinxsdrtristateimpl1_oe_n = 1'd0; +wire xilinxsdrtristateimpl2__i; +reg xilinxsdrtristateimpl2__o = 1'd0; +reg xilinxsdrtristateimpl2_oe_n = 1'd0; +wire xilinxsdrtristateimpl3__i; +reg xilinxsdrtristateimpl3__o = 1'd0; +reg xilinxsdrtristateimpl3_oe_n = 1'd0; +wire xilinxsdrtristateimpl4__i; +reg xilinxsdrtristateimpl4__o = 1'd0; +reg xilinxsdrtristateimpl4_oe_n = 1'd0; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + +assign wb_ctrl_adr_1 = wb_ctrl_adr; +assign wb_ctrl_dat_w_1 = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = wb_ctrl_dat_r_1; +assign wb_ctrl_sel_1 = wb_ctrl_sel; +assign wb_ctrl_cyc_1 = wb_ctrl_cyc; +assign wb_ctrl_stb_1 = wb_ctrl_stb; +assign wb_ctrl_ack = wb_ctrl_ack_1; +assign wb_ctrl_we_1 = wb_ctrl_we; +assign wb_ctrl_cti_1 = wb_ctrl_cti; +assign wb_ctrl_bte_1 = wb_ctrl_bte; +assign wb_ctrl_err = wb_ctrl_err_1; +assign wb_dma_adr = wb_dma_adr_1; +assign wb_dma_dat_w = wb_dma_dat_w_1; +assign wb_dma_dat_r_1 = wb_dma_dat_r; +assign wb_dma_sel = wb_dma_sel_1; +assign wb_dma_cyc = wb_dma_cyc_1; +assign wb_dma_stb = wb_dma_stb_1; +assign wb_dma_ack_1 = wb_dma_ack; +assign wb_dma_we = wb_dma_we_1; +assign wb_dma_cti = wb_dma_cti_1; +assign wb_dma_bte = wb_dma_bte_1; +assign wb_dma_err_1 = wb_dma_err; +assign sdcard_block2mem_sink_sink_valid0 = sdcard_core_source_source_valid0; +assign sdcard_core_source_source_ready0 = sdcard_block2mem_sink_sink_ready0; +assign sdcard_block2mem_sink_sink_first = sdcard_core_source_source_first0; +assign sdcard_block2mem_sink_sink_last0 = sdcard_core_source_source_last0; +assign sdcard_block2mem_sink_sink_payload_data0 = sdcard_core_source_source_payload_data0; +assign sdcard_core_sink_sink_valid0 = sdcard_mem2block_source_source_valid; +assign sdcard_mem2block_source_source_ready = sdcard_core_sink_sink_ready0; +assign sdcard_core_sink_sink_first0 = sdcard_mem2block_source_source_first; +assign sdcard_core_sink_sink_last0 = sdcard_mem2block_source_source_last; +assign sdcard_core_sink_sink_payload_data0 = sdcard_mem2block_source_source_payload_data; +assign block2mem_dma_trigger = sdcard_block2mem_irq; +assign mem2block_dma_trigger = sdcard_mem2block_irq; +assign card_detect_trigger = card_detect_irq; +assign cmd_done_trigger = sdcard_core_csrfield_done0; +assign irq = sdcard_irq_irq; +assign sys_clk = clk; +assign por_clk = clk; +assign sys_rst = int_rst; +assign interface0_adr = wb_ctrl_adr_1; +assign interface0_dat_w = wb_ctrl_dat_w_1; +assign wb_ctrl_dat_r_1 = interface0_dat_r; +assign interface0_sel = wb_ctrl_sel_1; +assign interface0_cyc = wb_ctrl_cyc_1; +assign interface0_stb = wb_ctrl_stb_1; +assign wb_ctrl_ack_1 = interface0_ack; +assign interface0_we = wb_ctrl_we_1; +assign interface0_cti = wb_ctrl_cti_1; +assign interface0_bte = wb_ctrl_bte_1; +assign wb_ctrl_err_1 = interface0_err; +assign bus_errors_status = bus_errors; +assign shared_adr = self0; +assign shared_dat_w = self1; +assign shared_sel = self2; +assign shared_cyc = self3; +assign shared_stb = self4; +assign shared_we = self5; +assign shared_cti = self6; +assign shared_bte = self7; +assign interface0_bus_dat_r = shared_dat_r; +assign interface1_bus_dat_r = shared_dat_r; +assign interface0_bus_ack = (shared_ack & (grant == 1'd0)); +assign interface1_bus_ack = (shared_ack & (grant == 1'd1)); +assign interface0_bus_err = (shared_err & (grant == 1'd0)); +assign interface1_bus_err = (shared_err & (grant == 1'd1)); +assign request = {interface1_bus_cyc, interface0_bus_cyc}; +always @(*) begin + slave_sel <= 1'd0; + slave_sel <= 1'd1; +end +assign wb_dma_adr_1 = shared_adr; +assign wb_dma_dat_w_1 = shared_dat_w; +assign wb_dma_sel_1 = shared_sel; +assign wb_dma_stb_1 = shared_stb; +assign wb_dma_we_1 = shared_we; +assign wb_dma_cti_1 = shared_cti; +assign wb_dma_bte_1 = shared_bte; +assign wb_dma_cyc_1 = (shared_cyc & slave_sel); +assign shared_err = wb_dma_err_1; +assign wait_1 = ((shared_stb & shared_cyc) & (~shared_ack)); +always @(*) begin + error <= 1'd0; + shared_ack <= 1'd0; + shared_dat_r <= 32'd0; + shared_ack <= wb_dma_ack_1; + shared_dat_r <= ({32{slave_sel_r}} & wb_dma_dat_r_1); + if (done) begin + shared_dat_r <= 32'd4294967295; + shared_ack <= 1'd1; + error <= 1'd1; + end +end +assign done = (count == 1'd0); +assign card_detect_status0 = sdcard_cd; +assign sdpads_clk = ((((init_pads_out_payload_clk | cmdw_pads_out_payload_clk) | cmdr_pads_out_payload_clk) | dataw_pads_out_payload_clk) | datar_pads_out_payload_clk); +assign sdpads_cmd_oe = ((((init_pads_out_payload_cmd_oe | cmdw_pads_out_payload_cmd_oe) | cmdr_pads_out_payload_cmd_oe) | dataw_pads_out_payload_cmd_oe) | datar_pads_out_payload_cmd_oe); +assign sdpads_cmd_o = ((((init_pads_out_payload_cmd_o | cmdw_pads_out_payload_cmd_o) | cmdr_pads_out_payload_cmd_o) | dataw_pads_out_payload_cmd_o) | datar_pads_out_payload_cmd_o); +assign sdpads_data_oe = ((((init_pads_out_payload_data_oe | cmdw_pads_out_payload_data_oe) | cmdr_pads_out_payload_data_oe) | dataw_pads_out_payload_data_oe) | datar_pads_out_payload_data_oe); +assign sdpads_data_o = ((((init_pads_out_payload_data_o | cmdw_pads_out_payload_data_o) | cmdr_pads_out_payload_data_o) | dataw_pads_out_payload_data_o) | datar_pads_out_payload_data_o); +assign init_pads_out_ready = clocker_ce; +assign cmdw_pads_out_ready = clocker_ce; +assign cmdr_pads_out_ready = clocker_ce; +assign dataw_pads_out_ready = clocker_ce; +assign datar_pads_out_ready = clocker_ce; +assign clocker_clk_en = sdpads_clk; +assign init_pads_in_valid = sdpads_data_i_ce; +assign init_pads_in_payload_cmd_i = sdpads_cmd_i; +assign init_pads_in_payload_data_i = sdpads_data_i; +assign cmdw_pads_in_valid = sdpads_data_i_ce; +assign cmdw_pads_in_payload_cmd_i = sdpads_cmd_i; +assign cmdw_pads_in_payload_data_i = sdpads_data_i; +assign cmdr_pads_in_pads_in_valid = sdpads_data_i_ce; +assign cmdr_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; +assign cmdr_pads_in_pads_in_payload_data_i = sdpads_data_i; +assign dataw_pads_in_pads_in_valid = sdpads_data_i_ce; +assign dataw_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; +assign dataw_pads_in_pads_in_payload_data_i = sdpads_data_i; +assign datar_pads_in_pads_in_valid = sdpads_data_i_ce; +assign datar_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; +assign datar_pads_in_pads_in_payload_data_i = sdpads_data_i; +assign clocker_stop = (dataw_stop | datar_stop); +always @(*) begin + clocker_clk1 <= 1'd0; + case (clocker_storage) + 3'd4: begin + clocker_clk1 <= clocker_clks[1]; + end + 4'd8: begin + clocker_clk1 <= clocker_clks[2]; + end + 5'd16: begin + clocker_clk1 <= clocker_clks[3]; + end + 6'd32: begin + clocker_clk1 <= clocker_clks[4]; + end + 7'd64: begin + clocker_clk1 <= clocker_clks[5]; + end + 8'd128: begin + clocker_clk1 <= clocker_clks[6]; + end + 9'd256: begin + clocker_clk1 <= clocker_clks[7]; + end + default: begin + clocker_clk1 <= clocker_clks[0]; + end + endcase +end +always @(*) begin + clocker_ce_latched <= 1'd0; + if (clocker_clk_d) begin + clocker_ce_latched <= clocker_clk_en; + end else begin + clocker_ce_latched <= clocker_ce_delayed; + end +end +assign clocker_clk0 = ((~clocker_clk1) & clocker_ce_latched); +always @(*) begin + init_count_sdphyinit_next_value <= 8'd0; + init_count_sdphyinit_next_value_ce <= 1'd0; + init_pads_out_payload_clk <= 1'd0; + init_pads_out_payload_cmd_o <= 1'd0; + init_pads_out_payload_cmd_oe <= 1'd0; + init_pads_out_payload_data_o <= 4'd0; + init_pads_out_payload_data_oe <= 1'd0; + sdphyinit_next_state <= 1'd0; + sdphyinit_next_state <= sdphyinit_state; + case (sdphyinit_state) + 1'd1: begin + init_pads_out_payload_clk <= 1'd1; + init_pads_out_payload_cmd_oe <= 1'd1; + init_pads_out_payload_cmd_o <= 1'd1; + init_pads_out_payload_data_oe <= 1'd1; + init_pads_out_payload_data_o <= 4'd15; + if (init_pads_out_ready) begin + init_count_sdphyinit_next_value <= (init_count + 1'd1); + init_count_sdphyinit_next_value_ce <= 1'd1; + if ((init_count == 7'd79)) begin + sdphyinit_next_state <= 1'd0; + end + end + end + default: begin + init_count_sdphyinit_next_value <= 1'd0; + init_count_sdphyinit_next_value_ce <= 1'd1; + if (init_initialize_re) begin + sdphyinit_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + cmdw_count_sdphycmdw_next_value <= 8'd0; + cmdw_count_sdphycmdw_next_value_ce <= 1'd0; + cmdw_done <= 1'd0; + cmdw_pads_out_payload_clk <= 1'd0; + cmdw_pads_out_payload_cmd_o <= 1'd0; + cmdw_pads_out_payload_cmd_oe <= 1'd0; + cmdw_sink_ready <= 1'd0; + sdphycmdw_next_state <= 2'd0; + sdphycmdw_next_state <= sdphycmdw_state; + case (sdphycmdw_state) + 1'd1: begin + cmdw_pads_out_payload_clk <= 1'd1; + cmdw_pads_out_payload_cmd_oe <= 1'd1; + case (cmdw_count) + 1'd0: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[7]; + end + 1'd1: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[6]; + end + 2'd2: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[5]; + end + 2'd3: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[4]; + end + 3'd4: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[3]; + end + 3'd5: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[2]; + end + 3'd6: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[1]; + end + 3'd7: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[0]; + end + endcase + if (cmdw_pads_out_ready) begin + cmdw_count_sdphycmdw_next_value <= (cmdw_count + 1'd1); + cmdw_count_sdphycmdw_next_value_ce <= 1'd1; + if ((cmdw_count == 3'd7)) begin + if ((cmdw_sink_last & (cmdw_sink_payload_cmd_type == 1'd0))) begin + sdphycmdw_next_state <= 2'd2; + end else begin + cmdw_sink_ready <= 1'd1; + sdphycmdw_next_state <= 1'd0; + end + end + end + end + 2'd2: begin + cmdw_pads_out_payload_clk <= 1'd1; + cmdw_pads_out_payload_cmd_oe <= 1'd1; + cmdw_pads_out_payload_cmd_o <= 1'd1; + if (cmdw_pads_out_ready) begin + cmdw_count_sdphycmdw_next_value <= (cmdw_count + 1'd1); + cmdw_count_sdphycmdw_next_value_ce <= 1'd1; + if ((cmdw_count == 3'd7)) begin + cmdw_sink_ready <= 1'd1; + sdphycmdw_next_state <= 1'd0; + end + end + end + default: begin + cmdw_count_sdphycmdw_next_value <= 1'd0; + cmdw_count_sdphycmdw_next_value_ce <= 1'd1; + if ((cmdw_sink_valid & cmdw_pads_out_ready)) begin + sdphycmdw_next_state <= 1'd1; + end else begin + cmdw_done <= 1'd1; + end + end + endcase +end +assign cmdr_cmdr_pads_in_valid = cmdr_pads_in_pads_in_valid; +assign cmdr_pads_in_pads_in_ready = cmdr_cmdr_pads_in_ready; +assign cmdr_cmdr_pads_in_first = cmdr_pads_in_pads_in_first; +assign cmdr_cmdr_pads_in_last = cmdr_pads_in_pads_in_last; +assign cmdr_cmdr_pads_in_payload_clk = cmdr_pads_in_pads_in_payload_clk; +assign cmdr_cmdr_pads_in_payload_cmd_i = cmdr_pads_in_pads_in_payload_cmd_i; +assign cmdr_cmdr_pads_in_payload_cmd_o = cmdr_pads_in_pads_in_payload_cmd_o; +assign cmdr_cmdr_pads_in_payload_cmd_oe = cmdr_pads_in_pads_in_payload_cmd_oe; +assign cmdr_cmdr_pads_in_payload_data_i = cmdr_pads_in_pads_in_payload_data_i; +assign cmdr_cmdr_pads_in_payload_data_o = cmdr_pads_in_pads_in_payload_data_o; +assign cmdr_cmdr_pads_in_payload_data_oe = cmdr_pads_in_pads_in_payload_data_oe; +assign cmdr_cmdr_pads_in_payload_data_i_ce = cmdr_pads_in_pads_in_payload_data_i_ce; +assign cmdr_cmdr_start = (cmdr_cmdr_pads_in_payload_cmd_i == 1'd0); +assign cmdr_cmdr_converter_converter_sink_valid = (cmdr_cmdr_pads_in_valid & (cmdr_cmdr_start | cmdr_cmdr_run)); +assign cmdr_cmdr_converter_converter_sink_payload_data = cmdr_cmdr_pads_in_payload_cmd_i; +assign cmdr_cmdr_buf_sink_sink_valid = cmdr_cmdr_converter_source_source_valid; +assign cmdr_cmdr_converter_source_source_ready = cmdr_cmdr_buf_sink_sink_ready; +assign cmdr_cmdr_buf_sink_sink_first = cmdr_cmdr_converter_source_source_first; +assign cmdr_cmdr_buf_sink_sink_last = cmdr_cmdr_converter_source_source_last; +assign cmdr_cmdr_buf_sink_sink_payload_data = cmdr_cmdr_converter_source_source_payload_data; +assign cmdr_cmdr_source_valid = cmdr_cmdr_buf_source_source_valid; +assign cmdr_cmdr_buf_source_source_ready = cmdr_cmdr_source_ready; +assign cmdr_cmdr_source_first = cmdr_cmdr_buf_source_source_first; +assign cmdr_cmdr_source_last = cmdr_cmdr_buf_source_source_last; +assign cmdr_cmdr_source_payload_data = cmdr_cmdr_buf_source_source_payload_data; +assign cmdr_cmdr_converter_source_source_valid = cmdr_cmdr_converter_converter_source_valid; +assign cmdr_cmdr_converter_converter_source_ready = cmdr_cmdr_converter_source_source_ready; +assign cmdr_cmdr_converter_source_source_first = cmdr_cmdr_converter_converter_source_first; +assign cmdr_cmdr_converter_source_source_last = cmdr_cmdr_converter_converter_source_last; +assign cmdr_cmdr_converter_source_source_payload_data = cmdr_cmdr_converter_converter_source_payload_data; +assign cmdr_cmdr_converter_converter_sink_ready = ((~cmdr_cmdr_converter_converter_strobe_all) | cmdr_cmdr_converter_converter_source_ready); +assign cmdr_cmdr_converter_converter_source_valid = cmdr_cmdr_converter_converter_strobe_all; +assign cmdr_cmdr_converter_converter_load_part = (cmdr_cmdr_converter_converter_sink_valid & cmdr_cmdr_converter_converter_sink_ready); +assign cmdr_cmdr_buf_pipe_valid_sink_ready = ((~cmdr_cmdr_buf_pipe_valid_source_valid) | cmdr_cmdr_buf_pipe_valid_source_ready); +assign cmdr_cmdr_buf_pipe_valid_sink_valid = cmdr_cmdr_buf_sink_sink_valid; +assign cmdr_cmdr_buf_sink_sink_ready = cmdr_cmdr_buf_pipe_valid_sink_ready; +assign cmdr_cmdr_buf_pipe_valid_sink_first = cmdr_cmdr_buf_sink_sink_first; +assign cmdr_cmdr_buf_pipe_valid_sink_last = cmdr_cmdr_buf_sink_sink_last; +assign cmdr_cmdr_buf_pipe_valid_sink_payload_data = cmdr_cmdr_buf_sink_sink_payload_data; +assign cmdr_cmdr_buf_source_source_valid = cmdr_cmdr_buf_pipe_valid_source_valid; +assign cmdr_cmdr_buf_pipe_valid_source_ready = cmdr_cmdr_buf_source_source_ready; +assign cmdr_cmdr_buf_source_source_first = cmdr_cmdr_buf_pipe_valid_source_first; +assign cmdr_cmdr_buf_source_source_last = cmdr_cmdr_buf_pipe_valid_source_last; +assign cmdr_cmdr_buf_source_source_payload_data = cmdr_cmdr_buf_pipe_valid_source_payload_data; +always @(*) begin + cmdr_busy_sdphycmdr_next_value2 <= 1'd0; + cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd0; + cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd0; + cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd0; + cmdr_cmdr_source_ready <= 1'd0; + cmdr_count_sdphycmdr_next_value1 <= 8'd0; + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd0; + cmdr_pads_out_payload_clk <= 1'd0; + cmdr_pads_out_payload_cmd_o <= 1'd0; + cmdr_pads_out_payload_cmd_oe <= 1'd0; + cmdr_sink_ready <= 1'd0; + cmdr_source_source_last <= 1'd0; + cmdr_source_source_payload_data <= 8'd0; + cmdr_source_source_payload_status <= 3'd0; + cmdr_source_source_valid <= 1'd0; + cmdr_timeout_sdphycmdr_next_value0 <= 32'd0; + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd0; + sdphycmdr_next_state <= 3'd0; + sdphycmdr_next_state <= sdphycmdr_state; + case (sdphycmdr_state) + 1'd1: begin + cmdr_pads_out_payload_clk <= 1'd1; + cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd0; + cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd1; + if (cmdr_cmdr_source_valid) begin + sdphycmdr_next_state <= 2'd2; + end + cmdr_timeout_sdphycmdr_next_value0 <= (cmdr_timeout - 1'd1); + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + if ((cmdr_timeout == 1'd0)) begin + sdphycmdr_next_state <= 3'd5; + end + end + 2'd2: begin + cmdr_pads_out_payload_clk <= 1'd1; + cmdr_source_source_valid <= cmdr_cmdr_source_valid; + cmdr_source_source_payload_status <= 1'd0; + cmdr_source_source_last <= (cmdr_count == (cmdr_sink_payload_length - 1'd1)); + cmdr_source_source_payload_data <= cmdr_cmdr_source_payload_data; + if ((cmdr_cmdr_source_valid & cmdr_source_source_ready)) begin + cmdr_cmdr_source_ready <= 1'd1; + cmdr_count_sdphycmdr_next_value1 <= (cmdr_count + 1'd1); + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + if (cmdr_source_source_last) begin + cmdr_sink_ready <= 1'd1; + if ((cmdr_sink_payload_cmd_type == 2'd3)) begin + cmdr_source_source_valid <= 1'd0; + cmdr_timeout_sdphycmdr_next_value0 <= 27'd100000000; + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + sdphycmdr_next_state <= 2'd3; + end else begin + if ((cmdr_sink_payload_data_type == 1'd0)) begin + cmdr_count_sdphycmdr_next_value1 <= 1'd0; + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + sdphycmdr_next_state <= 3'd4; + end else begin + sdphycmdr_next_state <= 1'd0; + end + end + end + end + cmdr_timeout_sdphycmdr_next_value0 <= (cmdr_timeout - 1'd1); + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + if ((cmdr_timeout == 1'd0)) begin + sdphycmdr_next_state <= 3'd5; + end + end + 2'd3: begin + cmdr_pads_out_payload_clk <= 1'd1; + if ((cmdr_pads_in_pads_in_valid & cmdr_pads_in_pads_in_payload_data_i[0])) begin + cmdr_busy_sdphycmdr_next_value2 <= 1'd0; + cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd1; + end + if ((~cmdr_busy)) begin + cmdr_source_source_valid <= 1'd1; + cmdr_source_source_last <= 1'd1; + cmdr_source_source_payload_status <= 1'd0; + if (cmdr_source_source_ready) begin + cmdr_count_sdphycmdr_next_value1 <= 1'd0; + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + sdphycmdr_next_state <= 3'd4; + end + end + cmdr_timeout_sdphycmdr_next_value0 <= (cmdr_timeout - 1'd1); + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + if ((cmdr_timeout == 1'd0)) begin + sdphycmdr_next_state <= 3'd5; + end + end + 3'd4: begin + cmdr_pads_out_payload_clk <= 1'd1; + cmdr_pads_out_payload_cmd_oe <= 1'd1; + cmdr_pads_out_payload_cmd_o <= 1'd1; + if (cmdr_pads_out_ready) begin + cmdr_count_sdphycmdr_next_value1 <= (cmdr_count + 1'd1); + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + if ((cmdr_count == 3'd7)) begin + sdphycmdr_next_state <= 1'd0; + end + end + end + 3'd5: begin + cmdr_sink_ready <= 1'd1; + cmdr_source_source_valid <= 1'd1; + cmdr_source_source_last <= 1'd1; + cmdr_source_source_payload_status <= 1'd1; + if (cmdr_source_source_ready) begin + sdphycmdr_next_state <= 1'd0; + end + end + default: begin + cmdr_timeout_sdphycmdr_next_value0 <= 27'd100000000; + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + cmdr_count_sdphycmdr_next_value1 <= 1'd0; + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + cmdr_busy_sdphycmdr_next_value2 <= 1'd1; + cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd1; + if (((cmdr_sink_valid & cmdr_pads_out_ready) & cmdw_done)) begin + cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd1; + cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd1; + sdphycmdr_next_state <= 1'd1; + end + end + endcase +end +assign dataw_accepted0 = dataw_accepted1; +assign dataw_crc_error0 = dataw_crc_error1; +assign dataw_write_error0 = dataw_write_error1; +assign dataw_crc_pads_in_valid = dataw_pads_in_pads_in_valid; +assign dataw_crc_pads_in_ready = dataw_pads_in_pads_in_ready; +assign dataw_crc_pads_in_first = dataw_pads_in_pads_in_first; +assign dataw_crc_pads_in_last = dataw_pads_in_pads_in_last; +assign dataw_crc_pads_in_payload_clk = dataw_pads_in_pads_in_payload_clk; +assign dataw_crc_pads_in_payload_cmd_i = dataw_pads_in_pads_in_payload_cmd_i; +assign dataw_crc_pads_in_payload_cmd_o = dataw_pads_in_pads_in_payload_cmd_o; +assign dataw_crc_pads_in_payload_cmd_oe = dataw_pads_in_pads_in_payload_cmd_oe; +assign dataw_crc_pads_in_payload_data_i = dataw_pads_in_pads_in_payload_data_i; +assign dataw_crc_pads_in_payload_data_o = dataw_pads_in_pads_in_payload_data_o; +assign dataw_crc_pads_in_payload_data_oe = dataw_pads_in_pads_in_payload_data_oe; +assign dataw_crc_pads_in_payload_data_i_ce = dataw_pads_in_pads_in_payload_data_i_ce; +assign dataw_crc_start = (dataw_crc_pads_in_payload_data_i[0] == 1'd0); +assign dataw_crc_converter_converter_sink_valid = (dataw_crc_pads_in_valid & dataw_crc_run); +assign dataw_crc_converter_converter_sink_payload_data = dataw_crc_pads_in_payload_data_i[0]; +assign dataw_crc_buf_sink_sink_valid = dataw_crc_converter_source_source_valid; +assign dataw_crc_converter_source_source_ready = dataw_crc_buf_sink_sink_ready; +assign dataw_crc_buf_sink_sink_first = dataw_crc_converter_source_source_first; +assign dataw_crc_buf_sink_sink_last = dataw_crc_converter_source_source_last; +assign dataw_crc_buf_sink_sink_payload_data = dataw_crc_converter_source_source_payload_data; +assign dataw_crc_source_valid = dataw_crc_buf_source_source_valid; +assign dataw_crc_buf_source_source_ready = dataw_crc_source_ready; +assign dataw_crc_source_first = dataw_crc_buf_source_source_first; +assign dataw_crc_source_last = dataw_crc_buf_source_source_last; +assign dataw_crc_source_payload_data = dataw_crc_buf_source_source_payload_data; +assign dataw_crc_converter_source_source_valid = dataw_crc_converter_converter_source_valid; +assign dataw_crc_converter_converter_source_ready = dataw_crc_converter_source_source_ready; +assign dataw_crc_converter_source_source_first = dataw_crc_converter_converter_source_first; +assign dataw_crc_converter_source_source_last = dataw_crc_converter_converter_source_last; +assign dataw_crc_converter_source_source_payload_data = dataw_crc_converter_converter_source_payload_data; +assign dataw_crc_converter_converter_sink_ready = ((~dataw_crc_converter_converter_strobe_all) | dataw_crc_converter_converter_source_ready); +assign dataw_crc_converter_converter_source_valid = dataw_crc_converter_converter_strobe_all; +assign dataw_crc_converter_converter_load_part = (dataw_crc_converter_converter_sink_valid & dataw_crc_converter_converter_sink_ready); +assign dataw_crc_buf_pipe_valid_sink_ready = ((~dataw_crc_buf_pipe_valid_source_valid) | dataw_crc_buf_pipe_valid_source_ready); +assign dataw_crc_buf_pipe_valid_sink_valid = dataw_crc_buf_sink_sink_valid; +assign dataw_crc_buf_sink_sink_ready = dataw_crc_buf_pipe_valid_sink_ready; +assign dataw_crc_buf_pipe_valid_sink_first = dataw_crc_buf_sink_sink_first; +assign dataw_crc_buf_pipe_valid_sink_last = dataw_crc_buf_sink_sink_last; +assign dataw_crc_buf_pipe_valid_sink_payload_data = dataw_crc_buf_sink_sink_payload_data; +assign dataw_crc_buf_source_source_valid = dataw_crc_buf_pipe_valid_source_valid; +assign dataw_crc_buf_pipe_valid_source_ready = dataw_crc_buf_source_source_ready; +assign dataw_crc_buf_source_source_first = dataw_crc_buf_pipe_valid_source_first; +assign dataw_crc_buf_source_source_last = dataw_crc_buf_pipe_valid_source_last; +assign dataw_crc_buf_source_source_payload_data = dataw_crc_buf_pipe_valid_source_payload_data; +always @(*) begin + dataw_accepted1_sdphydataw_next_value0 <= 1'd0; + dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd0; + dataw_count_sdphydataw_next_value3 <= 8'd0; + dataw_count_sdphydataw_next_value_ce3 <= 1'd0; + dataw_crc_error1_sdphydataw_next_value1 <= 1'd0; + dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd0; + dataw_crc_reset <= 1'd0; + dataw_pads_out_payload_clk <= 1'd0; + dataw_pads_out_payload_cmd_o <= 1'd0; + dataw_pads_out_payload_cmd_oe <= 1'd0; + dataw_pads_out_payload_data_o <= 4'd0; + dataw_pads_out_payload_data_oe <= 1'd0; + dataw_sink_ready <= 1'd0; + dataw_stop <= 1'd0; + dataw_write_error1_sdphydataw_next_value2 <= 1'd0; + dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd0; + sdphydataw_next_state <= 3'd0; + sdphydataw_next_state <= sdphydataw_state; + case (sdphydataw_state) + 1'd1: begin + dataw_pads_out_payload_clk <= 1'd1; + dataw_pads_out_payload_cmd_oe <= 1'd1; + dataw_pads_out_payload_cmd_o <= 1'd1; + if (dataw_pads_out_ready) begin + dataw_count_sdphydataw_next_value3 <= (dataw_count + 1'd1); + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + if ((dataw_count == 3'd7)) begin + dataw_count_sdphydataw_next_value3 <= 1'd0; + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + sdphydataw_next_state <= 2'd2; + end + end + end + 2'd2: begin + dataw_pads_out_payload_clk <= 1'd1; + dataw_pads_out_payload_data_oe <= 1'd1; + dataw_pads_out_payload_data_o <= 1'd0; + if (dataw_pads_out_ready) begin + sdphydataw_next_state <= 2'd3; + end + end + 2'd3: begin + dataw_stop <= (~dataw_sink_valid); + dataw_pads_out_payload_clk <= 1'd1; + dataw_pads_out_payload_data_oe <= 1'd1; + case (dataw_count) + 1'd0: begin + dataw_pads_out_payload_data_o <= dataw_sink_payload_data[7:4]; + end + 1'd1: begin + dataw_pads_out_payload_data_o <= dataw_sink_payload_data[3:0]; + end + endcase + if (dataw_pads_out_ready) begin + dataw_count_sdphydataw_next_value3 <= (dataw_count + 1'd1); + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + if ((dataw_count == 1'd1)) begin + dataw_count_sdphydataw_next_value3 <= 1'd0; + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + if (dataw_sink_last) begin + sdphydataw_next_state <= 3'd4; + end else begin + dataw_sink_ready <= 1'd1; + end + end + end + end + 3'd4: begin + dataw_pads_out_payload_clk <= 1'd1; + dataw_pads_out_payload_data_oe <= 1'd1; + dataw_pads_out_payload_data_o <= 4'd15; + if (dataw_pads_out_ready) begin + dataw_crc_reset <= 1'd1; + sdphydataw_next_state <= 3'd5; + end + end + 3'd5: begin + dataw_pads_out_payload_clk <= 1'd1; + if (dataw_crc_source_valid) begin + dataw_accepted1_sdphydataw_next_value0 <= (dataw_crc_source_payload_data[7:5] == 2'd2); + dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd1; + dataw_crc_error1_sdphydataw_next_value1 <= (dataw_crc_source_payload_data[7:5] == 3'd5); + dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd1; + dataw_write_error1_sdphydataw_next_value2 <= (dataw_crc_source_payload_data[7:5] == 3'd6); + dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd1; + sdphydataw_next_state <= 3'd6; + end + end + 3'd6: begin + dataw_pads_out_payload_clk <= 1'd1; + if ((dataw_pads_in_pads_in_valid & dataw_pads_in_pads_in_payload_data_i[0])) begin + dataw_sink_ready <= 1'd1; + sdphydataw_next_state <= 1'd0; + end + end + default: begin + dataw_accepted1_sdphydataw_next_value0 <= 1'd0; + dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd1; + dataw_crc_error1_sdphydataw_next_value1 <= 1'd0; + dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd1; + dataw_write_error1_sdphydataw_next_value2 <= 1'd0; + dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd1; + dataw_count_sdphydataw_next_value3 <= 1'd0; + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + if ((dataw_sink_valid & dataw_pads_out_ready)) begin + sdphydataw_next_state <= 1'd1; + end + end + endcase +end +assign datar_datar_pads_in_valid = datar_pads_in_pads_in_valid; +assign datar_pads_in_pads_in_ready = datar_datar_pads_in_ready; +assign datar_datar_pads_in_first = datar_pads_in_pads_in_first; +assign datar_datar_pads_in_last = datar_pads_in_pads_in_last; +assign datar_datar_pads_in_payload_clk = datar_pads_in_pads_in_payload_clk; +assign datar_datar_pads_in_payload_cmd_i = datar_pads_in_pads_in_payload_cmd_i; +assign datar_datar_pads_in_payload_cmd_o = datar_pads_in_pads_in_payload_cmd_o; +assign datar_datar_pads_in_payload_cmd_oe = datar_pads_in_pads_in_payload_cmd_oe; +assign datar_datar_pads_in_payload_data_i = datar_pads_in_pads_in_payload_data_i; +assign datar_datar_pads_in_payload_data_o = datar_pads_in_pads_in_payload_data_o; +assign datar_datar_pads_in_payload_data_oe = datar_pads_in_pads_in_payload_data_oe; +assign datar_datar_pads_in_payload_data_i_ce = datar_pads_in_pads_in_payload_data_i_ce; +assign datar_datar_start = (datar_datar_pads_in_payload_data_i[3:0] == 1'd0); +assign datar_datar_converter_converter_sink_valid = (datar_datar_pads_in_valid & datar_datar_run); +assign datar_datar_converter_converter_sink_payload_data = datar_datar_pads_in_payload_data_i[3:0]; +assign datar_datar_buf_sink_sink_valid = datar_datar_converter_source_source_valid; +assign datar_datar_converter_source_source_ready = datar_datar_buf_sink_sink_ready; +assign datar_datar_buf_sink_sink_first = datar_datar_converter_source_source_first; +assign datar_datar_buf_sink_sink_last = datar_datar_converter_source_source_last; +assign datar_datar_buf_sink_sink_payload_data = datar_datar_converter_source_source_payload_data; +assign datar_datar_source_valid = datar_datar_buf_source_source_valid; +assign datar_datar_buf_source_source_ready = datar_datar_source_ready; +assign datar_datar_source_first = datar_datar_buf_source_source_first; +assign datar_datar_source_last = datar_datar_buf_source_source_last; +assign datar_datar_source_payload_data = datar_datar_buf_source_source_payload_data; +assign datar_datar_converter_source_source_valid = datar_datar_converter_converter_source_valid; +assign datar_datar_converter_converter_source_ready = datar_datar_converter_source_source_ready; +assign datar_datar_converter_source_source_first = datar_datar_converter_converter_source_first; +assign datar_datar_converter_source_source_last = datar_datar_converter_converter_source_last; +assign datar_datar_converter_source_source_payload_data = datar_datar_converter_converter_source_payload_data; +assign datar_datar_converter_converter_sink_ready = ((~datar_datar_converter_converter_strobe_all) | datar_datar_converter_converter_source_ready); +assign datar_datar_converter_converter_source_valid = datar_datar_converter_converter_strobe_all; +assign datar_datar_converter_converter_load_part = (datar_datar_converter_converter_sink_valid & datar_datar_converter_converter_sink_ready); +assign datar_datar_buf_pipe_valid_sink_ready = ((~datar_datar_buf_pipe_valid_source_valid) | datar_datar_buf_pipe_valid_source_ready); +assign datar_datar_buf_pipe_valid_sink_valid = datar_datar_buf_sink_sink_valid; +assign datar_datar_buf_sink_sink_ready = datar_datar_buf_pipe_valid_sink_ready; +assign datar_datar_buf_pipe_valid_sink_first = datar_datar_buf_sink_sink_first; +assign datar_datar_buf_pipe_valid_sink_last = datar_datar_buf_sink_sink_last; +assign datar_datar_buf_pipe_valid_sink_payload_data = datar_datar_buf_sink_sink_payload_data; +assign datar_datar_buf_source_source_valid = datar_datar_buf_pipe_valid_source_valid; +assign datar_datar_buf_pipe_valid_source_ready = datar_datar_buf_source_source_ready; +assign datar_datar_buf_source_source_first = datar_datar_buf_pipe_valid_source_first; +assign datar_datar_buf_source_source_last = datar_datar_buf_pipe_valid_source_last; +assign datar_datar_buf_source_source_payload_data = datar_datar_buf_pipe_valid_source_payload_data; +always @(*) begin + datar_count_sdphydatar_next_value0 <= 10'd0; + datar_count_sdphydatar_next_value_ce0 <= 1'd0; + datar_datar_reset_sdphydatar_next_value2 <= 1'd0; + datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd0; + datar_datar_source_ready <= 1'd0; + datar_pads_out_payload_clk <= 1'd0; + datar_sink_ready <= 1'd0; + datar_source_source_first <= 1'd0; + datar_source_source_last <= 1'd0; + datar_source_source_payload_data <= 8'd0; + datar_source_source_payload_status <= 3'd0; + datar_source_source_valid <= 1'd0; + datar_stop <= 1'd0; + datar_timeout_sdphydatar_next_value1 <= 32'd0; + datar_timeout_sdphydatar_next_value_ce1 <= 1'd0; + sdphydatar_next_state <= 3'd0; + sdphydatar_next_state <= sdphydatar_state; + case (sdphydatar_state) + 1'd1: begin + datar_pads_out_payload_clk <= 1'd1; + datar_datar_reset_sdphydatar_next_value2 <= 1'd0; + datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd1; + datar_timeout_sdphydatar_next_value1 <= (datar_timeout - 1'd1); + datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; + if (datar_datar_source_valid) begin + sdphydatar_next_state <= 2'd2; + end + datar_timeout_sdphydatar_next_value1 <= (datar_timeout - 1'd1); + datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; + if ((datar_timeout == 1'd0)) begin + datar_sink_ready <= 1'd1; + sdphydatar_next_state <= 3'd4; + end + end + 2'd2: begin + datar_pads_out_payload_clk <= 1'd1; + datar_source_source_valid <= datar_datar_source_valid; + datar_source_source_payload_status <= 1'd0; + datar_source_source_first <= (datar_count == 1'd0); + datar_source_source_last <= (datar_count == ((datar_sink_payload_block_length + 4'd8) - 1'd1)); + datar_source_source_payload_data <= datar_datar_source_payload_data; + if (datar_source_source_valid) begin + if (datar_source_source_ready) begin + datar_datar_source_ready <= 1'd1; + datar_count_sdphydatar_next_value0 <= (datar_count + 1'd1); + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + if (datar_source_source_last) begin + datar_sink_ready <= 1'd1; + if (datar_sink_last) begin + datar_count_sdphydatar_next_value0 <= 1'd0; + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + sdphydatar_next_state <= 2'd3; + end else begin + sdphydatar_next_state <= 1'd0; + end + end + end else begin + datar_stop <= 1'd1; + end + end + datar_timeout_sdphydatar_next_value1 <= (datar_timeout - 1'd1); + datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; + if ((datar_timeout == 1'd0)) begin + datar_sink_ready <= 1'd1; + sdphydatar_next_state <= 3'd4; + end + end + 2'd3: begin + datar_pads_out_payload_clk <= 1'd1; + if (datar_pads_out_ready) begin + datar_count_sdphydatar_next_value0 <= (datar_count + 1'd1); + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + if ((datar_count == 6'd39)) begin + sdphydatar_next_state <= 1'd0; + end + end + end + 3'd4: begin + datar_source_source_valid <= 1'd1; + datar_source_source_payload_status <= 1'd1; + datar_source_source_last <= 1'd1; + if (datar_source_source_ready) begin + sdphydatar_next_state <= 1'd0; + end + end + default: begin + datar_count_sdphydatar_next_value0 <= 1'd0; + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + if ((datar_sink_valid & datar_pads_out_ready)) begin + datar_pads_out_payload_clk <= 1'd1; + datar_timeout_sdphydatar_next_value1 <= 32'd100000000; + datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; + datar_count_sdphydatar_next_value0 <= 1'd0; + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + datar_datar_reset_sdphydatar_next_value2 <= 1'd1; + datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd1; + sdphydatar_next_state <= 1'd1; + end + end + endcase +end +assign sdcard_core_crc16_inserter_sink_valid = sdcard_core_sink_sink_valid0; +assign sdcard_core_sink_sink_ready0 = sdcard_core_crc16_inserter_sink_ready; +assign sdcard_core_crc16_inserter_sink_first = sdcard_core_sink_sink_first0; +assign sdcard_core_crc16_inserter_sink_last = sdcard_core_sink_sink_last0; +assign sdcard_core_crc16_inserter_sink_payload_data = sdcard_core_sink_sink_payload_data0; +assign sdcard_core_source_source_valid0 = sdcard_core_source_source_valid1; +assign sdcard_core_source_source_ready1 = sdcard_core_source_source_ready0; +assign sdcard_core_source_source_first0 = sdcard_core_source_source_first1; +assign sdcard_core_source_source_last0 = sdcard_core_source_source_last1; +assign sdcard_core_source_source_payload_data0 = sdcard_core_source_source_payload_data1; +assign sdcard_core_cmd_type = sdcard_core_csrfield_cmd_type; +assign sdcard_core_data_type = sdcard_core_csrfield_data_type; +assign sdcard_core_cmd = sdcard_core_csrfield_cmd; +assign sdcard_core_csrfield_done0 = sdcard_core_cmd_done; +assign sdcard_core_csrfield_error0 = sdcard_core_cmd_error; +assign sdcard_core_csrfield_timeout0 = sdcard_core_cmd_timeout; +assign sdcard_core_csrfield_crc0 = 1'd0; +assign sdcard_core_csrfield_done1 = sdcard_core_data_done; +assign sdcard_core_csrfield_error1 = sdcard_core_data_error; +assign sdcard_core_csrfield_timeout1 = sdcard_core_data_timeout; +assign sdcard_core_csrfield_crc1 = 1'd0; +assign sdcard_core_crc7_inserter_crc_din = {1'd0, 1'd1, sdcard_core_cmd, sdcard_core_cmd_argument_storage}; +assign sdcard_core_crc7_inserter_crc_reset = 1'd1; +assign sdcard_core_crc7_inserter_crc_enable = 1'd1; +assign sdcard_core_crc7_inserter_crc1 = {sdcard_core_crc7_inserter_crc0[5], sdcard_core_crc7_inserter_crc0[4], sdcard_core_crc7_inserter_crc0[3], (sdcard_core_crc7_inserter_crc0[2] ^ (sdcard_core_crc7_inserter_crc_din[39] ^ sdcard_core_crc7_inserter_crc0[6])), sdcard_core_crc7_inserter_crc0[1], sdcard_core_crc7_inserter_crc0[0], (sdcard_core_crc7_inserter_crc_din[39] ^ sdcard_core_crc7_inserter_crc0[6])}; +assign sdcard_core_crc7_inserter_crc2 = {sdcard_core_crc7_inserter_crc1[5], sdcard_core_crc7_inserter_crc1[4], sdcard_core_crc7_inserter_crc1[3], (sdcard_core_crc7_inserter_crc1[2] ^ (sdcard_core_crc7_inserter_crc_din[38] ^ sdcard_core_crc7_inserter_crc1[6])), sdcard_core_crc7_inserter_crc1[1], sdcard_core_crc7_inserter_crc1[0], (sdcard_core_crc7_inserter_crc_din[38] ^ sdcard_core_crc7_inserter_crc1[6])}; +assign sdcard_core_crc7_inserter_crc3 = {sdcard_core_crc7_inserter_crc2[5], sdcard_core_crc7_inserter_crc2[4], sdcard_core_crc7_inserter_crc2[3], (sdcard_core_crc7_inserter_crc2[2] ^ (sdcard_core_crc7_inserter_crc_din[37] ^ sdcard_core_crc7_inserter_crc2[6])), sdcard_core_crc7_inserter_crc2[1], sdcard_core_crc7_inserter_crc2[0], (sdcard_core_crc7_inserter_crc_din[37] ^ sdcard_core_crc7_inserter_crc2[6])}; +assign sdcard_core_crc7_inserter_crc4 = {sdcard_core_crc7_inserter_crc3[5], sdcard_core_crc7_inserter_crc3[4], sdcard_core_crc7_inserter_crc3[3], (sdcard_core_crc7_inserter_crc3[2] ^ (sdcard_core_crc7_inserter_crc_din[36] ^ sdcard_core_crc7_inserter_crc3[6])), sdcard_core_crc7_inserter_crc3[1], sdcard_core_crc7_inserter_crc3[0], (sdcard_core_crc7_inserter_crc_din[36] ^ sdcard_core_crc7_inserter_crc3[6])}; +assign sdcard_core_crc7_inserter_crc5 = {sdcard_core_crc7_inserter_crc4[5], sdcard_core_crc7_inserter_crc4[4], sdcard_core_crc7_inserter_crc4[3], (sdcard_core_crc7_inserter_crc4[2] ^ (sdcard_core_crc7_inserter_crc_din[35] ^ sdcard_core_crc7_inserter_crc4[6])), sdcard_core_crc7_inserter_crc4[1], sdcard_core_crc7_inserter_crc4[0], (sdcard_core_crc7_inserter_crc_din[35] ^ sdcard_core_crc7_inserter_crc4[6])}; +assign sdcard_core_crc7_inserter_crc6 = {sdcard_core_crc7_inserter_crc5[5], sdcard_core_crc7_inserter_crc5[4], sdcard_core_crc7_inserter_crc5[3], (sdcard_core_crc7_inserter_crc5[2] ^ (sdcard_core_crc7_inserter_crc_din[34] ^ sdcard_core_crc7_inserter_crc5[6])), sdcard_core_crc7_inserter_crc5[1], sdcard_core_crc7_inserter_crc5[0], (sdcard_core_crc7_inserter_crc_din[34] ^ sdcard_core_crc7_inserter_crc5[6])}; +assign sdcard_core_crc7_inserter_crc7 = {sdcard_core_crc7_inserter_crc6[5], sdcard_core_crc7_inserter_crc6[4], sdcard_core_crc7_inserter_crc6[3], (sdcard_core_crc7_inserter_crc6[2] ^ (sdcard_core_crc7_inserter_crc_din[33] ^ sdcard_core_crc7_inserter_crc6[6])), sdcard_core_crc7_inserter_crc6[1], sdcard_core_crc7_inserter_crc6[0], (sdcard_core_crc7_inserter_crc_din[33] ^ sdcard_core_crc7_inserter_crc6[6])}; +assign sdcard_core_crc7_inserter_crc8 = {sdcard_core_crc7_inserter_crc7[5], sdcard_core_crc7_inserter_crc7[4], sdcard_core_crc7_inserter_crc7[3], (sdcard_core_crc7_inserter_crc7[2] ^ (sdcard_core_crc7_inserter_crc_din[32] ^ sdcard_core_crc7_inserter_crc7[6])), sdcard_core_crc7_inserter_crc7[1], sdcard_core_crc7_inserter_crc7[0], (sdcard_core_crc7_inserter_crc_din[32] ^ sdcard_core_crc7_inserter_crc7[6])}; +assign sdcard_core_crc7_inserter_crc9 = {sdcard_core_crc7_inserter_crc8[5], sdcard_core_crc7_inserter_crc8[4], sdcard_core_crc7_inserter_crc8[3], (sdcard_core_crc7_inserter_crc8[2] ^ (sdcard_core_crc7_inserter_crc_din[31] ^ sdcard_core_crc7_inserter_crc8[6])), sdcard_core_crc7_inserter_crc8[1], sdcard_core_crc7_inserter_crc8[0], (sdcard_core_crc7_inserter_crc_din[31] ^ sdcard_core_crc7_inserter_crc8[6])}; +assign sdcard_core_crc7_inserter_crc10 = {sdcard_core_crc7_inserter_crc9[5], sdcard_core_crc7_inserter_crc9[4], sdcard_core_crc7_inserter_crc9[3], (sdcard_core_crc7_inserter_crc9[2] ^ (sdcard_core_crc7_inserter_crc_din[30] ^ sdcard_core_crc7_inserter_crc9[6])), sdcard_core_crc7_inserter_crc9[1], sdcard_core_crc7_inserter_crc9[0], (sdcard_core_crc7_inserter_crc_din[30] ^ sdcard_core_crc7_inserter_crc9[6])}; +assign sdcard_core_crc7_inserter_crc11 = {sdcard_core_crc7_inserter_crc10[5], sdcard_core_crc7_inserter_crc10[4], sdcard_core_crc7_inserter_crc10[3], (sdcard_core_crc7_inserter_crc10[2] ^ (sdcard_core_crc7_inserter_crc_din[29] ^ sdcard_core_crc7_inserter_crc10[6])), sdcard_core_crc7_inserter_crc10[1], sdcard_core_crc7_inserter_crc10[0], (sdcard_core_crc7_inserter_crc_din[29] ^ sdcard_core_crc7_inserter_crc10[6])}; +assign sdcard_core_crc7_inserter_crc12 = {sdcard_core_crc7_inserter_crc11[5], sdcard_core_crc7_inserter_crc11[4], sdcard_core_crc7_inserter_crc11[3], (sdcard_core_crc7_inserter_crc11[2] ^ (sdcard_core_crc7_inserter_crc_din[28] ^ sdcard_core_crc7_inserter_crc11[6])), sdcard_core_crc7_inserter_crc11[1], sdcard_core_crc7_inserter_crc11[0], (sdcard_core_crc7_inserter_crc_din[28] ^ sdcard_core_crc7_inserter_crc11[6])}; +assign sdcard_core_crc7_inserter_crc13 = {sdcard_core_crc7_inserter_crc12[5], sdcard_core_crc7_inserter_crc12[4], sdcard_core_crc7_inserter_crc12[3], (sdcard_core_crc7_inserter_crc12[2] ^ (sdcard_core_crc7_inserter_crc_din[27] ^ sdcard_core_crc7_inserter_crc12[6])), sdcard_core_crc7_inserter_crc12[1], sdcard_core_crc7_inserter_crc12[0], (sdcard_core_crc7_inserter_crc_din[27] ^ sdcard_core_crc7_inserter_crc12[6])}; +assign sdcard_core_crc7_inserter_crc14 = {sdcard_core_crc7_inserter_crc13[5], sdcard_core_crc7_inserter_crc13[4], sdcard_core_crc7_inserter_crc13[3], (sdcard_core_crc7_inserter_crc13[2] ^ (sdcard_core_crc7_inserter_crc_din[26] ^ sdcard_core_crc7_inserter_crc13[6])), sdcard_core_crc7_inserter_crc13[1], sdcard_core_crc7_inserter_crc13[0], (sdcard_core_crc7_inserter_crc_din[26] ^ sdcard_core_crc7_inserter_crc13[6])}; +assign sdcard_core_crc7_inserter_crc15 = {sdcard_core_crc7_inserter_crc14[5], sdcard_core_crc7_inserter_crc14[4], sdcard_core_crc7_inserter_crc14[3], (sdcard_core_crc7_inserter_crc14[2] ^ (sdcard_core_crc7_inserter_crc_din[25] ^ sdcard_core_crc7_inserter_crc14[6])), sdcard_core_crc7_inserter_crc14[1], sdcard_core_crc7_inserter_crc14[0], (sdcard_core_crc7_inserter_crc_din[25] ^ sdcard_core_crc7_inserter_crc14[6])}; +assign sdcard_core_crc7_inserter_crc16 = {sdcard_core_crc7_inserter_crc15[5], sdcard_core_crc7_inserter_crc15[4], sdcard_core_crc7_inserter_crc15[3], (sdcard_core_crc7_inserter_crc15[2] ^ (sdcard_core_crc7_inserter_crc_din[24] ^ sdcard_core_crc7_inserter_crc15[6])), sdcard_core_crc7_inserter_crc15[1], sdcard_core_crc7_inserter_crc15[0], (sdcard_core_crc7_inserter_crc_din[24] ^ sdcard_core_crc7_inserter_crc15[6])}; +assign sdcard_core_crc7_inserter_crc17 = {sdcard_core_crc7_inserter_crc16[5], sdcard_core_crc7_inserter_crc16[4], sdcard_core_crc7_inserter_crc16[3], (sdcard_core_crc7_inserter_crc16[2] ^ (sdcard_core_crc7_inserter_crc_din[23] ^ sdcard_core_crc7_inserter_crc16[6])), sdcard_core_crc7_inserter_crc16[1], sdcard_core_crc7_inserter_crc16[0], (sdcard_core_crc7_inserter_crc_din[23] ^ sdcard_core_crc7_inserter_crc16[6])}; +assign sdcard_core_crc7_inserter_crc18 = {sdcard_core_crc7_inserter_crc17[5], sdcard_core_crc7_inserter_crc17[4], sdcard_core_crc7_inserter_crc17[3], (sdcard_core_crc7_inserter_crc17[2] ^ (sdcard_core_crc7_inserter_crc_din[22] ^ sdcard_core_crc7_inserter_crc17[6])), sdcard_core_crc7_inserter_crc17[1], sdcard_core_crc7_inserter_crc17[0], (sdcard_core_crc7_inserter_crc_din[22] ^ sdcard_core_crc7_inserter_crc17[6])}; +assign sdcard_core_crc7_inserter_crc19 = {sdcard_core_crc7_inserter_crc18[5], sdcard_core_crc7_inserter_crc18[4], sdcard_core_crc7_inserter_crc18[3], (sdcard_core_crc7_inserter_crc18[2] ^ (sdcard_core_crc7_inserter_crc_din[21] ^ sdcard_core_crc7_inserter_crc18[6])), sdcard_core_crc7_inserter_crc18[1], sdcard_core_crc7_inserter_crc18[0], (sdcard_core_crc7_inserter_crc_din[21] ^ sdcard_core_crc7_inserter_crc18[6])}; +assign sdcard_core_crc7_inserter_crc20 = {sdcard_core_crc7_inserter_crc19[5], sdcard_core_crc7_inserter_crc19[4], sdcard_core_crc7_inserter_crc19[3], (sdcard_core_crc7_inserter_crc19[2] ^ (sdcard_core_crc7_inserter_crc_din[20] ^ sdcard_core_crc7_inserter_crc19[6])), sdcard_core_crc7_inserter_crc19[1], sdcard_core_crc7_inserter_crc19[0], (sdcard_core_crc7_inserter_crc_din[20] ^ sdcard_core_crc7_inserter_crc19[6])}; +assign sdcard_core_crc7_inserter_crc21 = {sdcard_core_crc7_inserter_crc20[5], sdcard_core_crc7_inserter_crc20[4], sdcard_core_crc7_inserter_crc20[3], (sdcard_core_crc7_inserter_crc20[2] ^ (sdcard_core_crc7_inserter_crc_din[19] ^ sdcard_core_crc7_inserter_crc20[6])), sdcard_core_crc7_inserter_crc20[1], sdcard_core_crc7_inserter_crc20[0], (sdcard_core_crc7_inserter_crc_din[19] ^ sdcard_core_crc7_inserter_crc20[6])}; +assign sdcard_core_crc7_inserter_crc22 = {sdcard_core_crc7_inserter_crc21[5], sdcard_core_crc7_inserter_crc21[4], sdcard_core_crc7_inserter_crc21[3], (sdcard_core_crc7_inserter_crc21[2] ^ (sdcard_core_crc7_inserter_crc_din[18] ^ sdcard_core_crc7_inserter_crc21[6])), sdcard_core_crc7_inserter_crc21[1], sdcard_core_crc7_inserter_crc21[0], (sdcard_core_crc7_inserter_crc_din[18] ^ sdcard_core_crc7_inserter_crc21[6])}; +assign sdcard_core_crc7_inserter_crc23 = {sdcard_core_crc7_inserter_crc22[5], sdcard_core_crc7_inserter_crc22[4], sdcard_core_crc7_inserter_crc22[3], (sdcard_core_crc7_inserter_crc22[2] ^ (sdcard_core_crc7_inserter_crc_din[17] ^ sdcard_core_crc7_inserter_crc22[6])), sdcard_core_crc7_inserter_crc22[1], sdcard_core_crc7_inserter_crc22[0], (sdcard_core_crc7_inserter_crc_din[17] ^ sdcard_core_crc7_inserter_crc22[6])}; +assign sdcard_core_crc7_inserter_crc24 = {sdcard_core_crc7_inserter_crc23[5], sdcard_core_crc7_inserter_crc23[4], sdcard_core_crc7_inserter_crc23[3], (sdcard_core_crc7_inserter_crc23[2] ^ (sdcard_core_crc7_inserter_crc_din[16] ^ sdcard_core_crc7_inserter_crc23[6])), sdcard_core_crc7_inserter_crc23[1], sdcard_core_crc7_inserter_crc23[0], (sdcard_core_crc7_inserter_crc_din[16] ^ sdcard_core_crc7_inserter_crc23[6])}; +assign sdcard_core_crc7_inserter_crc25 = {sdcard_core_crc7_inserter_crc24[5], sdcard_core_crc7_inserter_crc24[4], sdcard_core_crc7_inserter_crc24[3], (sdcard_core_crc7_inserter_crc24[2] ^ (sdcard_core_crc7_inserter_crc_din[15] ^ sdcard_core_crc7_inserter_crc24[6])), sdcard_core_crc7_inserter_crc24[1], sdcard_core_crc7_inserter_crc24[0], (sdcard_core_crc7_inserter_crc_din[15] ^ sdcard_core_crc7_inserter_crc24[6])}; +assign sdcard_core_crc7_inserter_crc26 = {sdcard_core_crc7_inserter_crc25[5], sdcard_core_crc7_inserter_crc25[4], sdcard_core_crc7_inserter_crc25[3], (sdcard_core_crc7_inserter_crc25[2] ^ (sdcard_core_crc7_inserter_crc_din[14] ^ sdcard_core_crc7_inserter_crc25[6])), sdcard_core_crc7_inserter_crc25[1], sdcard_core_crc7_inserter_crc25[0], (sdcard_core_crc7_inserter_crc_din[14] ^ sdcard_core_crc7_inserter_crc25[6])}; +assign sdcard_core_crc7_inserter_crc27 = {sdcard_core_crc7_inserter_crc26[5], sdcard_core_crc7_inserter_crc26[4], sdcard_core_crc7_inserter_crc26[3], (sdcard_core_crc7_inserter_crc26[2] ^ (sdcard_core_crc7_inserter_crc_din[13] ^ sdcard_core_crc7_inserter_crc26[6])), sdcard_core_crc7_inserter_crc26[1], sdcard_core_crc7_inserter_crc26[0], (sdcard_core_crc7_inserter_crc_din[13] ^ sdcard_core_crc7_inserter_crc26[6])}; +assign sdcard_core_crc7_inserter_crc28 = {sdcard_core_crc7_inserter_crc27[5], sdcard_core_crc7_inserter_crc27[4], sdcard_core_crc7_inserter_crc27[3], (sdcard_core_crc7_inserter_crc27[2] ^ (sdcard_core_crc7_inserter_crc_din[12] ^ sdcard_core_crc7_inserter_crc27[6])), sdcard_core_crc7_inserter_crc27[1], sdcard_core_crc7_inserter_crc27[0], (sdcard_core_crc7_inserter_crc_din[12] ^ sdcard_core_crc7_inserter_crc27[6])}; +assign sdcard_core_crc7_inserter_crc29 = {sdcard_core_crc7_inserter_crc28[5], sdcard_core_crc7_inserter_crc28[4], sdcard_core_crc7_inserter_crc28[3], (sdcard_core_crc7_inserter_crc28[2] ^ (sdcard_core_crc7_inserter_crc_din[11] ^ sdcard_core_crc7_inserter_crc28[6])), sdcard_core_crc7_inserter_crc28[1], sdcard_core_crc7_inserter_crc28[0], (sdcard_core_crc7_inserter_crc_din[11] ^ sdcard_core_crc7_inserter_crc28[6])}; +assign sdcard_core_crc7_inserter_crc30 = {sdcard_core_crc7_inserter_crc29[5], sdcard_core_crc7_inserter_crc29[4], sdcard_core_crc7_inserter_crc29[3], (sdcard_core_crc7_inserter_crc29[2] ^ (sdcard_core_crc7_inserter_crc_din[10] ^ sdcard_core_crc7_inserter_crc29[6])), sdcard_core_crc7_inserter_crc29[1], sdcard_core_crc7_inserter_crc29[0], (sdcard_core_crc7_inserter_crc_din[10] ^ sdcard_core_crc7_inserter_crc29[6])}; +assign sdcard_core_crc7_inserter_crc31 = {sdcard_core_crc7_inserter_crc30[5], sdcard_core_crc7_inserter_crc30[4], sdcard_core_crc7_inserter_crc30[3], (sdcard_core_crc7_inserter_crc30[2] ^ (sdcard_core_crc7_inserter_crc_din[9] ^ sdcard_core_crc7_inserter_crc30[6])), sdcard_core_crc7_inserter_crc30[1], sdcard_core_crc7_inserter_crc30[0], (sdcard_core_crc7_inserter_crc_din[9] ^ sdcard_core_crc7_inserter_crc30[6])}; +assign sdcard_core_crc7_inserter_crc32 = {sdcard_core_crc7_inserter_crc31[5], sdcard_core_crc7_inserter_crc31[4], sdcard_core_crc7_inserter_crc31[3], (sdcard_core_crc7_inserter_crc31[2] ^ (sdcard_core_crc7_inserter_crc_din[8] ^ sdcard_core_crc7_inserter_crc31[6])), sdcard_core_crc7_inserter_crc31[1], sdcard_core_crc7_inserter_crc31[0], (sdcard_core_crc7_inserter_crc_din[8] ^ sdcard_core_crc7_inserter_crc31[6])}; +assign sdcard_core_crc7_inserter_crc33 = {sdcard_core_crc7_inserter_crc32[5], sdcard_core_crc7_inserter_crc32[4], sdcard_core_crc7_inserter_crc32[3], (sdcard_core_crc7_inserter_crc32[2] ^ (sdcard_core_crc7_inserter_crc_din[7] ^ sdcard_core_crc7_inserter_crc32[6])), sdcard_core_crc7_inserter_crc32[1], sdcard_core_crc7_inserter_crc32[0], (sdcard_core_crc7_inserter_crc_din[7] ^ sdcard_core_crc7_inserter_crc32[6])}; +assign sdcard_core_crc7_inserter_crc34 = {sdcard_core_crc7_inserter_crc33[5], sdcard_core_crc7_inserter_crc33[4], sdcard_core_crc7_inserter_crc33[3], (sdcard_core_crc7_inserter_crc33[2] ^ (sdcard_core_crc7_inserter_crc_din[6] ^ sdcard_core_crc7_inserter_crc33[6])), sdcard_core_crc7_inserter_crc33[1], sdcard_core_crc7_inserter_crc33[0], (sdcard_core_crc7_inserter_crc_din[6] ^ sdcard_core_crc7_inserter_crc33[6])}; +assign sdcard_core_crc7_inserter_crc35 = {sdcard_core_crc7_inserter_crc34[5], sdcard_core_crc7_inserter_crc34[4], sdcard_core_crc7_inserter_crc34[3], (sdcard_core_crc7_inserter_crc34[2] ^ (sdcard_core_crc7_inserter_crc_din[5] ^ sdcard_core_crc7_inserter_crc34[6])), sdcard_core_crc7_inserter_crc34[1], sdcard_core_crc7_inserter_crc34[0], (sdcard_core_crc7_inserter_crc_din[5] ^ sdcard_core_crc7_inserter_crc34[6])}; +assign sdcard_core_crc7_inserter_crc36 = {sdcard_core_crc7_inserter_crc35[5], sdcard_core_crc7_inserter_crc35[4], sdcard_core_crc7_inserter_crc35[3], (sdcard_core_crc7_inserter_crc35[2] ^ (sdcard_core_crc7_inserter_crc_din[4] ^ sdcard_core_crc7_inserter_crc35[6])), sdcard_core_crc7_inserter_crc35[1], sdcard_core_crc7_inserter_crc35[0], (sdcard_core_crc7_inserter_crc_din[4] ^ sdcard_core_crc7_inserter_crc35[6])}; +assign sdcard_core_crc7_inserter_crc37 = {sdcard_core_crc7_inserter_crc36[5], sdcard_core_crc7_inserter_crc36[4], sdcard_core_crc7_inserter_crc36[3], (sdcard_core_crc7_inserter_crc36[2] ^ (sdcard_core_crc7_inserter_crc_din[3] ^ sdcard_core_crc7_inserter_crc36[6])), sdcard_core_crc7_inserter_crc36[1], sdcard_core_crc7_inserter_crc36[0], (sdcard_core_crc7_inserter_crc_din[3] ^ sdcard_core_crc7_inserter_crc36[6])}; +assign sdcard_core_crc7_inserter_crc38 = {sdcard_core_crc7_inserter_crc37[5], sdcard_core_crc7_inserter_crc37[4], sdcard_core_crc7_inserter_crc37[3], (sdcard_core_crc7_inserter_crc37[2] ^ (sdcard_core_crc7_inserter_crc_din[2] ^ sdcard_core_crc7_inserter_crc37[6])), sdcard_core_crc7_inserter_crc37[1], sdcard_core_crc7_inserter_crc37[0], (sdcard_core_crc7_inserter_crc_din[2] ^ sdcard_core_crc7_inserter_crc37[6])}; +assign sdcard_core_crc7_inserter_crc39 = {sdcard_core_crc7_inserter_crc38[5], sdcard_core_crc7_inserter_crc38[4], sdcard_core_crc7_inserter_crc38[3], (sdcard_core_crc7_inserter_crc38[2] ^ (sdcard_core_crc7_inserter_crc_din[1] ^ sdcard_core_crc7_inserter_crc38[6])), sdcard_core_crc7_inserter_crc38[1], sdcard_core_crc7_inserter_crc38[0], (sdcard_core_crc7_inserter_crc_din[1] ^ sdcard_core_crc7_inserter_crc38[6])}; +assign sdcard_core_crc7_inserter_crc40 = {sdcard_core_crc7_inserter_crc39[5], sdcard_core_crc7_inserter_crc39[4], sdcard_core_crc7_inserter_crc39[3], (sdcard_core_crc7_inserter_crc39[2] ^ (sdcard_core_crc7_inserter_crc_din[0] ^ sdcard_core_crc7_inserter_crc39[6])), sdcard_core_crc7_inserter_crc39[1], sdcard_core_crc7_inserter_crc39[0], (sdcard_core_crc7_inserter_crc_din[0] ^ sdcard_core_crc7_inserter_crc39[6])}; +always @(*) begin + sdcard_core_crc7_inserter_crc_crc <= 7'd0; + if (sdcard_core_crc7_inserter_crc_enable) begin + sdcard_core_crc7_inserter_crc_crc <= sdcard_core_crc7_inserter_crc40; + end else begin + sdcard_core_crc7_inserter_crc_crc <= sdcard_core_crc7_inserter_crc0; + end +end +assign sdcard_core_crc16_inserter_crc0_reset = ((sdcard_core_crc16_inserter_source_valid & sdcard_core_crc16_inserter_source_ready) & sdcard_core_crc16_inserter_source_last); +assign sdcard_core_crc16_inserter_crc0_enable = (sdcard_core_crc16_inserter_sink_valid & sdcard_core_crc16_inserter_sink_ready); +always @(*) begin + sdcard_core_crc16_inserter_crc0_din <= 2'd0; + sdcard_core_crc16_inserter_crc0_din[0] <= sdcard_core_crc16_inserter_sink_payload_data[0]; + sdcard_core_crc16_inserter_crc0_din[1] <= sdcard_core_crc16_inserter_sink_payload_data[4]; +end +assign sdcard_core_crc16_inserter_crc1_reset = ((sdcard_core_crc16_inserter_source_valid & sdcard_core_crc16_inserter_source_ready) & sdcard_core_crc16_inserter_source_last); +assign sdcard_core_crc16_inserter_crc1_enable = (sdcard_core_crc16_inserter_sink_valid & sdcard_core_crc16_inserter_sink_ready); +always @(*) begin + sdcard_core_crc16_inserter_crc1_din <= 2'd0; + sdcard_core_crc16_inserter_crc1_din[0] <= sdcard_core_crc16_inserter_sink_payload_data[1]; + sdcard_core_crc16_inserter_crc1_din[1] <= sdcard_core_crc16_inserter_sink_payload_data[5]; +end +assign sdcard_core_crc16_inserter_crc2_reset = ((sdcard_core_crc16_inserter_source_valid & sdcard_core_crc16_inserter_source_ready) & sdcard_core_crc16_inserter_source_last); +assign sdcard_core_crc16_inserter_crc2_enable = (sdcard_core_crc16_inserter_sink_valid & sdcard_core_crc16_inserter_sink_ready); +always @(*) begin + sdcard_core_crc16_inserter_crc2_din <= 2'd0; + sdcard_core_crc16_inserter_crc2_din[0] <= sdcard_core_crc16_inserter_sink_payload_data[2]; + sdcard_core_crc16_inserter_crc2_din[1] <= sdcard_core_crc16_inserter_sink_payload_data[6]; +end +assign sdcard_core_crc16_inserter_crc3_reset = ((sdcard_core_crc16_inserter_source_valid & sdcard_core_crc16_inserter_source_ready) & sdcard_core_crc16_inserter_source_last); +assign sdcard_core_crc16_inserter_crc3_enable = (sdcard_core_crc16_inserter_sink_valid & sdcard_core_crc16_inserter_sink_ready); +always @(*) begin + sdcard_core_crc16_inserter_crc3_din <= 2'd0; + sdcard_core_crc16_inserter_crc3_din[0] <= sdcard_core_crc16_inserter_sink_payload_data[3]; + sdcard_core_crc16_inserter_crc3_din[1] <= sdcard_core_crc16_inserter_sink_payload_data[7]; +end +assign sdcard_core_crc16_inserter_crc01 = {sdcard_core_crc16_inserter_crc00[14], sdcard_core_crc16_inserter_crc00[13], sdcard_core_crc16_inserter_crc00[12], (sdcard_core_crc16_inserter_crc00[11] ^ (sdcard_core_crc16_inserter_crc0_din[1] ^ sdcard_core_crc16_inserter_crc00[15])), sdcard_core_crc16_inserter_crc00[10], sdcard_core_crc16_inserter_crc00[9], sdcard_core_crc16_inserter_crc00[8], sdcard_core_crc16_inserter_crc00[7], sdcard_core_crc16_inserter_crc00[6], sdcard_core_crc16_inserter_crc00[5], (sdcard_core_crc16_inserter_crc00[4] ^ (sdcard_core_crc16_inserter_crc0_din[1] ^ sdcard_core_crc16_inserter_crc00[15])), sdcard_core_crc16_inserter_crc00[3], sdcard_core_crc16_inserter_crc00[2], sdcard_core_crc16_inserter_crc00[1], sdcard_core_crc16_inserter_crc00[0], (sdcard_core_crc16_inserter_crc0_din[1] ^ sdcard_core_crc16_inserter_crc00[15])}; +assign sdcard_core_crc16_inserter_crc02 = {sdcard_core_crc16_inserter_crc01[14], sdcard_core_crc16_inserter_crc01[13], sdcard_core_crc16_inserter_crc01[12], (sdcard_core_crc16_inserter_crc01[11] ^ (sdcard_core_crc16_inserter_crc0_din[0] ^ sdcard_core_crc16_inserter_crc01[15])), sdcard_core_crc16_inserter_crc01[10], sdcard_core_crc16_inserter_crc01[9], sdcard_core_crc16_inserter_crc01[8], sdcard_core_crc16_inserter_crc01[7], sdcard_core_crc16_inserter_crc01[6], sdcard_core_crc16_inserter_crc01[5], (sdcard_core_crc16_inserter_crc01[4] ^ (sdcard_core_crc16_inserter_crc0_din[0] ^ sdcard_core_crc16_inserter_crc01[15])), sdcard_core_crc16_inserter_crc01[3], sdcard_core_crc16_inserter_crc01[2], sdcard_core_crc16_inserter_crc01[1], sdcard_core_crc16_inserter_crc01[0], (sdcard_core_crc16_inserter_crc0_din[0] ^ sdcard_core_crc16_inserter_crc01[15])}; +always @(*) begin + sdcard_core_crc16_inserter_crc0_crc <= 16'd0; + if (sdcard_core_crc16_inserter_crc0_enable) begin + sdcard_core_crc16_inserter_crc0_crc <= sdcard_core_crc16_inserter_crc02; + end else begin + sdcard_core_crc16_inserter_crc0_crc <= sdcard_core_crc16_inserter_crc00; + end +end +assign sdcard_core_crc16_inserter_crc11 = {sdcard_core_crc16_inserter_crc10[14], sdcard_core_crc16_inserter_crc10[13], sdcard_core_crc16_inserter_crc10[12], (sdcard_core_crc16_inserter_crc10[11] ^ (sdcard_core_crc16_inserter_crc1_din[1] ^ sdcard_core_crc16_inserter_crc10[15])), sdcard_core_crc16_inserter_crc10[10], sdcard_core_crc16_inserter_crc10[9], sdcard_core_crc16_inserter_crc10[8], sdcard_core_crc16_inserter_crc10[7], sdcard_core_crc16_inserter_crc10[6], sdcard_core_crc16_inserter_crc10[5], (sdcard_core_crc16_inserter_crc10[4] ^ (sdcard_core_crc16_inserter_crc1_din[1] ^ sdcard_core_crc16_inserter_crc10[15])), sdcard_core_crc16_inserter_crc10[3], sdcard_core_crc16_inserter_crc10[2], sdcard_core_crc16_inserter_crc10[1], sdcard_core_crc16_inserter_crc10[0], (sdcard_core_crc16_inserter_crc1_din[1] ^ sdcard_core_crc16_inserter_crc10[15])}; +assign sdcard_core_crc16_inserter_crc12 = {sdcard_core_crc16_inserter_crc11[14], sdcard_core_crc16_inserter_crc11[13], sdcard_core_crc16_inserter_crc11[12], (sdcard_core_crc16_inserter_crc11[11] ^ (sdcard_core_crc16_inserter_crc1_din[0] ^ sdcard_core_crc16_inserter_crc11[15])), sdcard_core_crc16_inserter_crc11[10], sdcard_core_crc16_inserter_crc11[9], sdcard_core_crc16_inserter_crc11[8], sdcard_core_crc16_inserter_crc11[7], sdcard_core_crc16_inserter_crc11[6], sdcard_core_crc16_inserter_crc11[5], (sdcard_core_crc16_inserter_crc11[4] ^ (sdcard_core_crc16_inserter_crc1_din[0] ^ sdcard_core_crc16_inserter_crc11[15])), sdcard_core_crc16_inserter_crc11[3], sdcard_core_crc16_inserter_crc11[2], sdcard_core_crc16_inserter_crc11[1], sdcard_core_crc16_inserter_crc11[0], (sdcard_core_crc16_inserter_crc1_din[0] ^ sdcard_core_crc16_inserter_crc11[15])}; +always @(*) begin + sdcard_core_crc16_inserter_crc1_crc <= 16'd0; + if (sdcard_core_crc16_inserter_crc1_enable) begin + sdcard_core_crc16_inserter_crc1_crc <= sdcard_core_crc16_inserter_crc12; + end else begin + sdcard_core_crc16_inserter_crc1_crc <= sdcard_core_crc16_inserter_crc10; + end +end +assign sdcard_core_crc16_inserter_crc21 = {sdcard_core_crc16_inserter_crc20[14], sdcard_core_crc16_inserter_crc20[13], sdcard_core_crc16_inserter_crc20[12], (sdcard_core_crc16_inserter_crc20[11] ^ (sdcard_core_crc16_inserter_crc2_din[1] ^ sdcard_core_crc16_inserter_crc20[15])), sdcard_core_crc16_inserter_crc20[10], sdcard_core_crc16_inserter_crc20[9], sdcard_core_crc16_inserter_crc20[8], sdcard_core_crc16_inserter_crc20[7], sdcard_core_crc16_inserter_crc20[6], sdcard_core_crc16_inserter_crc20[5], (sdcard_core_crc16_inserter_crc20[4] ^ (sdcard_core_crc16_inserter_crc2_din[1] ^ sdcard_core_crc16_inserter_crc20[15])), sdcard_core_crc16_inserter_crc20[3], sdcard_core_crc16_inserter_crc20[2], sdcard_core_crc16_inserter_crc20[1], sdcard_core_crc16_inserter_crc20[0], (sdcard_core_crc16_inserter_crc2_din[1] ^ sdcard_core_crc16_inserter_crc20[15])}; +assign sdcard_core_crc16_inserter_crc22 = {sdcard_core_crc16_inserter_crc21[14], sdcard_core_crc16_inserter_crc21[13], sdcard_core_crc16_inserter_crc21[12], (sdcard_core_crc16_inserter_crc21[11] ^ (sdcard_core_crc16_inserter_crc2_din[0] ^ sdcard_core_crc16_inserter_crc21[15])), sdcard_core_crc16_inserter_crc21[10], sdcard_core_crc16_inserter_crc21[9], sdcard_core_crc16_inserter_crc21[8], sdcard_core_crc16_inserter_crc21[7], sdcard_core_crc16_inserter_crc21[6], sdcard_core_crc16_inserter_crc21[5], (sdcard_core_crc16_inserter_crc21[4] ^ (sdcard_core_crc16_inserter_crc2_din[0] ^ sdcard_core_crc16_inserter_crc21[15])), sdcard_core_crc16_inserter_crc21[3], sdcard_core_crc16_inserter_crc21[2], sdcard_core_crc16_inserter_crc21[1], sdcard_core_crc16_inserter_crc21[0], (sdcard_core_crc16_inserter_crc2_din[0] ^ sdcard_core_crc16_inserter_crc21[15])}; +always @(*) begin + sdcard_core_crc16_inserter_crc2_crc <= 16'd0; + if (sdcard_core_crc16_inserter_crc2_enable) begin + sdcard_core_crc16_inserter_crc2_crc <= sdcard_core_crc16_inserter_crc22; + end else begin + sdcard_core_crc16_inserter_crc2_crc <= sdcard_core_crc16_inserter_crc20; + end +end +assign sdcard_core_crc16_inserter_crc31 = {sdcard_core_crc16_inserter_crc30[14], sdcard_core_crc16_inserter_crc30[13], sdcard_core_crc16_inserter_crc30[12], (sdcard_core_crc16_inserter_crc30[11] ^ (sdcard_core_crc16_inserter_crc3_din[1] ^ sdcard_core_crc16_inserter_crc30[15])), sdcard_core_crc16_inserter_crc30[10], sdcard_core_crc16_inserter_crc30[9], sdcard_core_crc16_inserter_crc30[8], sdcard_core_crc16_inserter_crc30[7], sdcard_core_crc16_inserter_crc30[6], sdcard_core_crc16_inserter_crc30[5], (sdcard_core_crc16_inserter_crc30[4] ^ (sdcard_core_crc16_inserter_crc3_din[1] ^ sdcard_core_crc16_inserter_crc30[15])), sdcard_core_crc16_inserter_crc30[3], sdcard_core_crc16_inserter_crc30[2], sdcard_core_crc16_inserter_crc30[1], sdcard_core_crc16_inserter_crc30[0], (sdcard_core_crc16_inserter_crc3_din[1] ^ sdcard_core_crc16_inserter_crc30[15])}; +assign sdcard_core_crc16_inserter_crc32 = {sdcard_core_crc16_inserter_crc31[14], sdcard_core_crc16_inserter_crc31[13], sdcard_core_crc16_inserter_crc31[12], (sdcard_core_crc16_inserter_crc31[11] ^ (sdcard_core_crc16_inserter_crc3_din[0] ^ sdcard_core_crc16_inserter_crc31[15])), sdcard_core_crc16_inserter_crc31[10], sdcard_core_crc16_inserter_crc31[9], sdcard_core_crc16_inserter_crc31[8], sdcard_core_crc16_inserter_crc31[7], sdcard_core_crc16_inserter_crc31[6], sdcard_core_crc16_inserter_crc31[5], (sdcard_core_crc16_inserter_crc31[4] ^ (sdcard_core_crc16_inserter_crc3_din[0] ^ sdcard_core_crc16_inserter_crc31[15])), sdcard_core_crc16_inserter_crc31[3], sdcard_core_crc16_inserter_crc31[2], sdcard_core_crc16_inserter_crc31[1], sdcard_core_crc16_inserter_crc31[0], (sdcard_core_crc16_inserter_crc3_din[0] ^ sdcard_core_crc16_inserter_crc31[15])}; +always @(*) begin + sdcard_core_crc16_inserter_crc3_crc <= 16'd0; + if (sdcard_core_crc16_inserter_crc3_enable) begin + sdcard_core_crc16_inserter_crc3_crc <= sdcard_core_crc16_inserter_crc32; + end else begin + sdcard_core_crc16_inserter_crc3_crc <= sdcard_core_crc16_inserter_crc30; + end +end +always @(*) begin + crc16inserter_next_state <= 1'd0; + sdcard_core_crc16_inserter_count_crc16inserter_next_value <= 3'd0; + sdcard_core_crc16_inserter_count_crc16inserter_next_value_ce <= 1'd0; + sdcard_core_crc16_inserter_sink_ready <= 1'd0; + sdcard_core_crc16_inserter_source_first <= 1'd0; + sdcard_core_crc16_inserter_source_last <= 1'd0; + sdcard_core_crc16_inserter_source_payload_data <= 8'd0; + sdcard_core_crc16_inserter_source_valid <= 1'd0; + crc16inserter_next_state <= crc16inserter_state; + case (crc16inserter_state) + 1'd1: begin + sdcard_core_crc16_inserter_source_valid <= 1'd1; + sdcard_core_crc16_inserter_source_last <= (sdcard_core_crc16_inserter_count == 3'd7); + case (sdcard_core_crc16_inserter_count) + 1'd0: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[14]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[14]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[14]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[14]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[15]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[15]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[15]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[15]; + end + 1'd1: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[12]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[12]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[12]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[12]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[13]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[13]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[13]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[13]; + end + 2'd2: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[10]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[10]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[10]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[10]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[11]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[11]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[11]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[11]; + end + 2'd3: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[8]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[8]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[8]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[8]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[9]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[9]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[9]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[9]; + end + 3'd4: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[6]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[6]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[6]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[6]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[7]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[7]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[7]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[7]; + end + 3'd5: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[4]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[4]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[4]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[4]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[5]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[5]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[5]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[5]; + end + 3'd6: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[2]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[2]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[2]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[2]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[3]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[3]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[3]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[3]; + end + 3'd7: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[0]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[0]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[0]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[0]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[1]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[1]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[1]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[1]; + end + endcase + if ((sdcard_core_crc16_inserter_source_valid & sdcard_core_crc16_inserter_source_ready)) begin + sdcard_core_crc16_inserter_count_crc16inserter_next_value <= (sdcard_core_crc16_inserter_count + 1'd1); + sdcard_core_crc16_inserter_count_crc16inserter_next_value_ce <= 1'd1; + if (sdcard_core_crc16_inserter_source_last) begin + crc16inserter_next_state <= 1'd0; + end + end + end + default: begin + sdcard_core_crc16_inserter_count_crc16inserter_next_value <= 1'd0; + sdcard_core_crc16_inserter_count_crc16inserter_next_value_ce <= 1'd1; + sdcard_core_crc16_inserter_source_valid <= sdcard_core_crc16_inserter_sink_valid; + sdcard_core_crc16_inserter_sink_ready <= sdcard_core_crc16_inserter_source_ready; + sdcard_core_crc16_inserter_source_first <= sdcard_core_crc16_inserter_sink_first; + sdcard_core_crc16_inserter_source_payload_data <= sdcard_core_crc16_inserter_sink_payload_data; + sdcard_core_crc16_inserter_source_last <= 1'd0; + if ((sdcard_core_crc16_inserter_sink_valid & sdcard_core_crc16_inserter_sink_ready)) begin + if (sdcard_core_crc16_inserter_sink_last) begin + crc16inserter_next_state <= 1'd1; + end + end + end + endcase +end +assign sdcard_core_fifo_sink_valid = sdcard_core_sink_sink_valid1; +assign sdcard_core_sink_sink_ready1 = sdcard_core_fifo_sink_ready; +assign sdcard_core_fifo_sink_first = sdcard_core_sink_sink_first1; +assign sdcard_core_fifo_sink_last = sdcard_core_sink_sink_last1; +assign sdcard_core_fifo_sink_payload_data = sdcard_core_sink_sink_payload_data1; +assign sdcard_core_source_source_first1 = sdcard_core_fifo_source_first; +assign sdcard_core_source_source_last1 = sdcard_core_fifo_source_last; +assign sdcard_core_source_source_payload_data1 = sdcard_core_fifo_source_payload_data; +assign sdcard_core_source_source_valid1 = (sdcard_core_fifo_level >= 4'd8); +assign sdcard_core_fifo_source_ready = (sdcard_core_source_source_valid1 & sdcard_core_source_source_ready1); +assign sdcard_core_fifo_reset = ((sdcard_core_sink_sink_valid1 & sdcard_core_sink_sink_ready1) & sdcard_core_sink_sink_last1); +assign sdcard_core_fifo_syncfifo_din = {sdcard_core_fifo_fifo_in_last, sdcard_core_fifo_fifo_in_first, sdcard_core_fifo_fifo_in_payload_data}; +assign {sdcard_core_fifo_fifo_out_last, sdcard_core_fifo_fifo_out_first, sdcard_core_fifo_fifo_out_payload_data} = sdcard_core_fifo_syncfifo_dout; +assign sdcard_core_fifo_sink_ready = sdcard_core_fifo_syncfifo_writable; +assign sdcard_core_fifo_syncfifo_we = sdcard_core_fifo_sink_valid; +assign sdcard_core_fifo_fifo_in_first = sdcard_core_fifo_sink_first; +assign sdcard_core_fifo_fifo_in_last = sdcard_core_fifo_sink_last; +assign sdcard_core_fifo_fifo_in_payload_data = sdcard_core_fifo_sink_payload_data; +assign sdcard_core_fifo_source_valid = sdcard_core_fifo_syncfifo_readable; +assign sdcard_core_fifo_source_first = sdcard_core_fifo_fifo_out_first; +assign sdcard_core_fifo_source_last = sdcard_core_fifo_fifo_out_last; +assign sdcard_core_fifo_source_payload_data = sdcard_core_fifo_fifo_out_payload_data; +assign sdcard_core_fifo_syncfifo_re = sdcard_core_fifo_source_ready; +always @(*) begin + sdcard_core_fifo_wrport_adr <= 3'd0; + if (sdcard_core_fifo_replace) begin + sdcard_core_fifo_wrport_adr <= (sdcard_core_fifo_produce - 1'd1); + end else begin + sdcard_core_fifo_wrport_adr <= sdcard_core_fifo_produce; + end +end +assign sdcard_core_fifo_wrport_dat_w = sdcard_core_fifo_syncfifo_din; +assign sdcard_core_fifo_wrport_we = (sdcard_core_fifo_syncfifo_we & (sdcard_core_fifo_syncfifo_writable | sdcard_core_fifo_replace)); +assign sdcard_core_fifo_do_read = (sdcard_core_fifo_syncfifo_readable & sdcard_core_fifo_syncfifo_re); +assign sdcard_core_fifo_rdport_adr = sdcard_core_fifo_consume; +assign sdcard_core_fifo_syncfifo_dout = sdcard_core_fifo_rdport_dat_r; +assign sdcard_core_fifo_syncfifo_writable = (sdcard_core_fifo_level != 4'd8); +assign sdcard_core_fifo_syncfifo_readable = (sdcard_core_fifo_level != 1'd0); +always @(*) begin + cmdr_sink_payload_cmd_type <= 2'd0; + cmdr_sink_payload_data_type <= 2'd0; + cmdr_sink_payload_length <= 8'd0; + cmdr_sink_valid <= 1'd0; + cmdr_source_source_ready <= 1'd0; + cmdw_sink_last <= 1'd0; + cmdw_sink_payload_cmd_type <= 2'd0; + cmdw_sink_payload_data <= 8'd0; + cmdw_sink_valid <= 1'd0; + datar_sink_last <= 1'd0; + datar_sink_payload_block_length <= 10'd0; + datar_sink_valid <= 1'd0; + datar_source_source_ready <= 1'd0; + dataw_sink_first <= 1'd0; + dataw_sink_last <= 1'd0; + dataw_sink_payload_data <= 8'd0; + dataw_sink_valid <= 1'd0; + fsm_next_state <= 3'd0; + sdcard_core_cmd_count_fsm_next_value2 <= 3'd0; + sdcard_core_cmd_count_fsm_next_value_ce2 <= 1'd0; + sdcard_core_cmd_done_fsm_next_value0 <= 1'd0; + sdcard_core_cmd_done_fsm_next_value_ce0 <= 1'd0; + sdcard_core_cmd_error_fsm_next_value4 <= 1'd0; + sdcard_core_cmd_error_fsm_next_value_ce4 <= 1'd0; + sdcard_core_cmd_response_status_fsm_next_value8 <= 128'd0; + sdcard_core_cmd_response_status_fsm_next_value_ce8 <= 1'd0; + sdcard_core_cmd_timeout_fsm_next_value5 <= 1'd0; + sdcard_core_cmd_timeout_fsm_next_value_ce5 <= 1'd0; + sdcard_core_crc16_inserter_source_ready <= 1'd0; + sdcard_core_data_count_fsm_next_value3 <= 32'd0; + sdcard_core_data_count_fsm_next_value_ce3 <= 1'd0; + sdcard_core_data_done_fsm_next_value1 <= 1'd0; + sdcard_core_data_done_fsm_next_value_ce1 <= 1'd0; + sdcard_core_data_error_fsm_next_value6 <= 1'd0; + sdcard_core_data_error_fsm_next_value_ce6 <= 1'd0; + sdcard_core_data_timeout_fsm_next_value7 <= 1'd0; + sdcard_core_data_timeout_fsm_next_value_ce7 <= 1'd0; + sdcard_core_sink_sink_first1 <= 1'd0; + sdcard_core_sink_sink_last1 <= 1'd0; + sdcard_core_sink_sink_payload_data1 <= 8'd0; + sdcard_core_sink_sink_valid1 <= 1'd0; + fsm_next_state <= fsm_state; + case (fsm_state) + 1'd1: begin + cmdw_sink_valid <= 1'd1; + cmdw_sink_last <= (sdcard_core_cmd_count == 3'd5); + cmdw_sink_payload_cmd_type <= sdcard_core_cmd_type; + case (sdcard_core_cmd_count) + 1'd0: begin + cmdw_sink_payload_data <= {1'd0, 1'd1, sdcard_core_cmd}; + end + 1'd1: begin + cmdw_sink_payload_data <= sdcard_core_cmd_argument_storage[31:24]; + end + 2'd2: begin + cmdw_sink_payload_data <= sdcard_core_cmd_argument_storage[23:16]; + end + 2'd3: begin + cmdw_sink_payload_data <= sdcard_core_cmd_argument_storage[15:8]; + end + 3'd4: begin + cmdw_sink_payload_data <= sdcard_core_cmd_argument_storage[7:0]; + end + 3'd5: begin + cmdw_sink_payload_data <= {sdcard_core_crc7_inserter_crc_crc, 1'd1}; + end + endcase + if (cmdw_sink_ready) begin + sdcard_core_cmd_count_fsm_next_value2 <= (sdcard_core_cmd_count + 1'd1); + sdcard_core_cmd_count_fsm_next_value_ce2 <= 1'd1; + if (cmdw_sink_last) begin + if ((sdcard_core_cmd_type == 1'd0)) begin + fsm_next_state <= 1'd0; + end else begin + fsm_next_state <= 2'd2; + end + end + end + end + 2'd2: begin + cmdr_sink_valid <= 1'd1; + cmdr_sink_payload_cmd_type <= sdcard_core_cmd_type; + cmdr_sink_payload_data_type <= sdcard_core_data_type; + if ((sdcard_core_cmd_type == 2'd2)) begin + cmdr_sink_payload_length <= 5'd18; + end else begin + cmdr_sink_payload_length <= 3'd6; + end + cmdr_source_source_ready <= 1'd1; + if (cmdr_source_source_valid) begin + if ((cmdr_source_source_payload_status == 1'd1)) begin + sdcard_core_cmd_timeout_fsm_next_value5 <= 1'd1; + sdcard_core_cmd_timeout_fsm_next_value_ce5 <= 1'd1; + fsm_next_state <= 1'd0; + end else begin + if (cmdr_source_source_last) begin + if ((sdcard_core_data_type == 2'd2)) begin + fsm_next_state <= 2'd3; + end else begin + if ((sdcard_core_data_type == 1'd1)) begin + fsm_next_state <= 3'd4; + end else begin + fsm_next_state <= 1'd0; + end + end + end else begin + sdcard_core_cmd_response_status_fsm_next_value8 <= {sdcard_core_cmd_response_status, cmdr_source_source_payload_data}; + sdcard_core_cmd_response_status_fsm_next_value_ce8 <= 1'd1; + end + end + end + end + 2'd3: begin + dataw_sink_valid <= sdcard_core_crc16_inserter_source_valid; + sdcard_core_crc16_inserter_source_ready <= dataw_sink_ready; + dataw_sink_first <= sdcard_core_crc16_inserter_source_first; + dataw_sink_last <= sdcard_core_crc16_inserter_source_last; + dataw_sink_payload_data <= sdcard_core_crc16_inserter_source_payload_data; + if (((dataw_sink_valid & dataw_sink_ready) & dataw_sink_last)) begin + sdcard_core_data_count_fsm_next_value3 <= (sdcard_core_data_count + 1'd1); + sdcard_core_data_count_fsm_next_value_ce3 <= 1'd1; + if ((sdcard_core_data_count == (sdcard_core_block_count_storage - 1'd1))) begin + fsm_next_state <= 1'd0; + end + end + datar_source_source_ready <= 1'd1; + if (datar_source_source_valid) begin + if ((datar_source_source_payload_status != 2'd2)) begin + sdcard_core_data_error_fsm_next_value6 <= 1'd1; + sdcard_core_data_error_fsm_next_value_ce6 <= 1'd1; + end + end + end + 3'd4: begin + datar_sink_valid <= 1'd1; + datar_sink_payload_block_length <= sdcard_core_block_length_storage; + datar_sink_last <= (sdcard_core_data_count == (sdcard_core_block_count_storage - 1'd1)); + if (datar_source_source_valid) begin + if ((datar_source_source_payload_status == 1'd0)) begin + sdcard_core_sink_sink_valid1 <= datar_source_source_valid; + datar_source_source_ready <= sdcard_core_sink_sink_ready1; + sdcard_core_sink_sink_first1 <= datar_source_source_first; + sdcard_core_sink_sink_last1 <= datar_source_source_last; + sdcard_core_sink_sink_payload_data1 <= datar_source_source_payload_data; + if ((datar_source_source_last & datar_source_source_ready)) begin + sdcard_core_data_count_fsm_next_value3 <= (sdcard_core_data_count + 1'd1); + sdcard_core_data_count_fsm_next_value_ce3 <= 1'd1; + if ((sdcard_core_data_count == (sdcard_core_block_count_storage - 1'd1))) begin + fsm_next_state <= 1'd0; + end + end + end else begin + if ((datar_source_source_payload_status == 1'd1)) begin + sdcard_core_data_timeout_fsm_next_value7 <= 1'd1; + sdcard_core_data_timeout_fsm_next_value_ce7 <= 1'd1; + datar_source_source_ready <= 1'd1; + fsm_next_state <= 1'd0; + end + end + end + end + default: begin + sdcard_core_cmd_done_fsm_next_value0 <= 1'd1; + sdcard_core_cmd_done_fsm_next_value_ce0 <= 1'd1; + sdcard_core_data_done_fsm_next_value1 <= 1'd1; + sdcard_core_data_done_fsm_next_value_ce1 <= 1'd1; + sdcard_core_cmd_count_fsm_next_value2 <= 1'd0; + sdcard_core_cmd_count_fsm_next_value_ce2 <= 1'd1; + sdcard_core_data_count_fsm_next_value3 <= 1'd0; + sdcard_core_data_count_fsm_next_value_ce3 <= 1'd1; + if (sdcard_core_cmd_send_re) begin + sdcard_core_cmd_done_fsm_next_value0 <= 1'd0; + sdcard_core_cmd_done_fsm_next_value_ce0 <= 1'd1; + sdcard_core_cmd_error_fsm_next_value4 <= 1'd0; + sdcard_core_cmd_error_fsm_next_value_ce4 <= 1'd1; + sdcard_core_cmd_timeout_fsm_next_value5 <= 1'd0; + sdcard_core_cmd_timeout_fsm_next_value_ce5 <= 1'd1; + sdcard_core_data_done_fsm_next_value1 <= 1'd0; + sdcard_core_data_done_fsm_next_value_ce1 <= 1'd1; + sdcard_core_data_error_fsm_next_value6 <= 1'd0; + sdcard_core_data_error_fsm_next_value_ce6 <= 1'd1; + sdcard_core_data_timeout_fsm_next_value7 <= 1'd0; + sdcard_core_data_timeout_fsm_next_value_ce7 <= 1'd1; + fsm_next_state <= 1'd1; + end + end + endcase +end +assign sdcard_block2mem_start = (sdcard_block2mem_sink_sink_valid0 & sdcard_block2mem_sink_sink_first); +always @(*) begin + sdcard_block2mem_fifo_sink_first <= 1'd0; + sdcard_block2mem_fifo_sink_last <= 1'd0; + sdcard_block2mem_fifo_sink_payload_data <= 8'd0; + sdcard_block2mem_fifo_sink_valid <= 1'd0; + sdcard_block2mem_sink_sink_ready0 <= 1'd0; + if ((sdcard_block2mem_wishbonedmawriter_enable_storage & (sdcard_block2mem_start | sdcard_block2mem_connect))) begin + sdcard_block2mem_fifo_sink_valid <= sdcard_block2mem_sink_sink_valid0; + sdcard_block2mem_sink_sink_ready0 <= sdcard_block2mem_fifo_sink_ready; + sdcard_block2mem_fifo_sink_first <= sdcard_block2mem_sink_sink_first; + sdcard_block2mem_fifo_sink_last <= sdcard_block2mem_sink_sink_last0; + sdcard_block2mem_fifo_sink_payload_data <= sdcard_block2mem_sink_sink_payload_data0; + end else begin + sdcard_block2mem_sink_sink_ready0 <= 1'd1; + end +end +assign sdcard_block2mem_converter_sink_valid = sdcard_block2mem_fifo_source_valid; +assign sdcard_block2mem_fifo_source_ready = sdcard_block2mem_converter_sink_ready; +assign sdcard_block2mem_converter_sink_first = sdcard_block2mem_fifo_source_first; +assign sdcard_block2mem_converter_sink_last = sdcard_block2mem_fifo_source_last; +assign sdcard_block2mem_converter_sink_payload_data = sdcard_block2mem_fifo_source_payload_data; +assign sdcard_block2mem_wishbonedmawriter_sink_valid = sdcard_block2mem_source_source_valid; +assign sdcard_block2mem_source_source_ready = sdcard_block2mem_wishbonedmawriter_sink_ready; +assign sdcard_block2mem_wishbonedmawriter_sink_first = sdcard_block2mem_source_source_first; +assign sdcard_block2mem_wishbonedmawriter_sink_last = sdcard_block2mem_source_source_last; +assign sdcard_block2mem_wishbonedmawriter_sink_payload_data = sdcard_block2mem_source_source_payload_data; +assign sdcard_block2mem_fifo_syncfifo_din = {sdcard_block2mem_fifo_fifo_in_last, sdcard_block2mem_fifo_fifo_in_first, sdcard_block2mem_fifo_fifo_in_payload_data}; +assign {sdcard_block2mem_fifo_fifo_out_last, sdcard_block2mem_fifo_fifo_out_first, sdcard_block2mem_fifo_fifo_out_payload_data} = sdcard_block2mem_fifo_syncfifo_dout; +assign sdcard_block2mem_fifo_sink_ready = sdcard_block2mem_fifo_syncfifo_writable; +assign sdcard_block2mem_fifo_syncfifo_we = sdcard_block2mem_fifo_sink_valid; +assign sdcard_block2mem_fifo_fifo_in_first = sdcard_block2mem_fifo_sink_first; +assign sdcard_block2mem_fifo_fifo_in_last = sdcard_block2mem_fifo_sink_last; +assign sdcard_block2mem_fifo_fifo_in_payload_data = sdcard_block2mem_fifo_sink_payload_data; +assign sdcard_block2mem_fifo_source_valid = sdcard_block2mem_fifo_readable; +assign sdcard_block2mem_fifo_source_first = sdcard_block2mem_fifo_fifo_out_first; +assign sdcard_block2mem_fifo_source_last = sdcard_block2mem_fifo_fifo_out_last; +assign sdcard_block2mem_fifo_source_payload_data = sdcard_block2mem_fifo_fifo_out_payload_data; +assign sdcard_block2mem_fifo_re = sdcard_block2mem_fifo_source_ready; +assign sdcard_block2mem_fifo_syncfifo_re = (sdcard_block2mem_fifo_syncfifo_readable & ((~sdcard_block2mem_fifo_readable) | sdcard_block2mem_fifo_re)); +assign sdcard_block2mem_fifo_level1 = (sdcard_block2mem_fifo_level0 + sdcard_block2mem_fifo_readable); +always @(*) begin + sdcard_block2mem_fifo_wrport_adr <= 9'd0; + if (sdcard_block2mem_fifo_replace) begin + sdcard_block2mem_fifo_wrport_adr <= (sdcard_block2mem_fifo_produce - 1'd1); + end else begin + sdcard_block2mem_fifo_wrport_adr <= sdcard_block2mem_fifo_produce; + end +end +assign sdcard_block2mem_fifo_wrport_dat_w = sdcard_block2mem_fifo_syncfifo_din; +assign sdcard_block2mem_fifo_wrport_we = (sdcard_block2mem_fifo_syncfifo_we & (sdcard_block2mem_fifo_syncfifo_writable | sdcard_block2mem_fifo_replace)); +assign sdcard_block2mem_fifo_do_read = (sdcard_block2mem_fifo_syncfifo_readable & sdcard_block2mem_fifo_syncfifo_re); +assign sdcard_block2mem_fifo_rdport_adr = sdcard_block2mem_fifo_consume; +assign sdcard_block2mem_fifo_syncfifo_dout = sdcard_block2mem_fifo_rdport_dat_r; +assign sdcard_block2mem_fifo_rdport_re = sdcard_block2mem_fifo_do_read; +assign sdcard_block2mem_fifo_syncfifo_writable = (sdcard_block2mem_fifo_level0 != 10'd512); +assign sdcard_block2mem_fifo_syncfifo_readable = (sdcard_block2mem_fifo_level0 != 1'd0); +assign sdcard_block2mem_source_source_valid = sdcard_block2mem_converter_source_valid; +assign sdcard_block2mem_converter_source_ready = sdcard_block2mem_source_source_ready; +assign sdcard_block2mem_source_source_first = sdcard_block2mem_converter_source_first; +assign sdcard_block2mem_source_source_last = sdcard_block2mem_converter_source_last; +assign sdcard_block2mem_source_source_payload_data = sdcard_block2mem_converter_source_payload_data; +assign sdcard_block2mem_converter_sink_ready = ((~sdcard_block2mem_converter_strobe_all) | sdcard_block2mem_converter_source_ready); +assign sdcard_block2mem_converter_source_valid = sdcard_block2mem_converter_strobe_all; +assign sdcard_block2mem_converter_load_part = (sdcard_block2mem_converter_sink_valid & sdcard_block2mem_converter_sink_ready); +assign interface0_bus_stb = sdcard_block2mem_sink_sink_valid1; +assign interface0_bus_cyc = sdcard_block2mem_sink_sink_valid1; +assign interface0_bus_we = 1'd1; +assign interface0_bus_sel = 4'd15; +assign interface0_bus_adr = sdcard_block2mem_sink_sink_payload_address; +assign interface0_bus_dat_w = {sdcard_block2mem_sink_sink_payload_data1[7:0], sdcard_block2mem_sink_sink_payload_data1[15:8], sdcard_block2mem_sink_sink_payload_data1[23:16], sdcard_block2mem_sink_sink_payload_data1[31:24]}; +assign sdcard_block2mem_sink_sink_ready1 = interface0_bus_ack; +assign sdcard_block2mem_wishbonedmawriter_base = sdcard_block2mem_wishbonedmawriter_base_storage[63:2]; +assign sdcard_block2mem_wishbonedmawriter_length = sdcard_block2mem_wishbonedmawriter_length_storage[31:2]; +assign sdcard_block2mem_wishbonedmawriter_offset_status = sdcard_block2mem_wishbonedmawriter_offset; +assign sdcard_block2mem_wishbonedmawriter_reset = (~sdcard_block2mem_wishbonedmawriter_enable_storage); +always @(*) begin + sdblock2memdma_next_state <= 2'd0; + sdcard_block2mem_sink_sink_last1 <= 1'd0; + sdcard_block2mem_sink_sink_payload_address <= 32'd0; + sdcard_block2mem_sink_sink_payload_data1 <= 32'd0; + sdcard_block2mem_sink_sink_valid1 <= 1'd0; + sdcard_block2mem_wishbonedmawriter_done_status <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= 32'd0; + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd0; + sdcard_block2mem_wishbonedmawriter_sink_ready <= 1'd0; + sdblock2memdma_next_state <= sdblock2memdma_state; + case (sdblock2memdma_state) + 1'd1: begin + sdcard_block2mem_sink_sink_valid1 <= sdcard_block2mem_wishbonedmawriter_sink_valid; + sdcard_block2mem_sink_sink_last1 <= (sdcard_block2mem_wishbonedmawriter_sink_last | ((sdcard_block2mem_wishbonedmawriter_offset + 1'd1) == sdcard_block2mem_wishbonedmawriter_length)); + sdcard_block2mem_sink_sink_payload_address <= (sdcard_block2mem_wishbonedmawriter_base + sdcard_block2mem_wishbonedmawriter_offset); + sdcard_block2mem_sink_sink_payload_data1 <= sdcard_block2mem_wishbonedmawriter_sink_payload_data; + sdcard_block2mem_wishbonedmawriter_sink_ready <= sdcard_block2mem_sink_sink_ready1; + if ((sdcard_block2mem_wishbonedmawriter_sink_valid & sdcard_block2mem_wishbonedmawriter_sink_ready)) begin + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= (sdcard_block2mem_wishbonedmawriter_offset + 1'd1); + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd1; + if (sdcard_block2mem_sink_sink_last1) begin + if (sdcard_block2mem_wishbonedmawriter_loop_storage) begin + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd1; + end else begin + sdblock2memdma_next_state <= 2'd2; + end + end + end + end + 2'd2: begin + sdcard_block2mem_wishbonedmawriter_done_status <= 1'd1; + end + default: begin + sdcard_block2mem_wishbonedmawriter_sink_ready <= 1'd1; + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd1; + sdblock2memdma_next_state <= 1'd1; + end + endcase +end +assign sdcard_mem2block_converter_converter_sink_valid = sdcard_mem2block_dma_source_source_valid; +assign sdcard_mem2block_dma_source_source_ready = sdcard_mem2block_converter_converter_sink_ready; +assign sdcard_mem2block_converter_converter_sink_first = sdcard_mem2block_dma_source_source_first; +assign sdcard_mem2block_converter_converter_sink_last = sdcard_mem2block_dma_source_source_last; +assign sdcard_mem2block_converter_converter_sink_payload_data = sdcard_mem2block_dma_source_source_payload_data; +assign sdcard_mem2block_fifo_sink_valid = sdcard_mem2block_converter_source_source_valid; +assign sdcard_mem2block_converter_source_source_ready = sdcard_mem2block_fifo_sink_ready; +assign sdcard_mem2block_fifo_sink_first = sdcard_mem2block_converter_source_source_first; +assign sdcard_mem2block_fifo_sink_last = sdcard_mem2block_converter_source_source_last; +assign sdcard_mem2block_fifo_sink_payload_data = sdcard_mem2block_converter_source_source_payload_data; +assign sdcard_mem2block_source_source_valid = sdcard_mem2block_fifo_source_valid; +assign sdcard_mem2block_fifo_source_ready = sdcard_mem2block_source_source_ready; +assign sdcard_mem2block_source_source_first = sdcard_mem2block_fifo_source_first; +assign sdcard_mem2block_source_source_payload_data = sdcard_mem2block_fifo_source_payload_data; +always @(*) begin + sdcard_mem2block_source_source_last <= 1'd0; + sdcard_mem2block_source_source_last <= sdcard_mem2block_fifo_source_last; + if ((sdcard_mem2block_count == 9'd511)) begin + sdcard_mem2block_source_source_last <= 1'd1; + end +end +assign interface1_bus_stb = (sdcard_mem2block_dma_sink_sink_valid & sdcard_mem2block_dma_fifo_sink_ready); +assign interface1_bus_cyc = (sdcard_mem2block_dma_sink_sink_valid & sdcard_mem2block_dma_fifo_sink_ready); +assign interface1_bus_we = 1'd0; +assign interface1_bus_sel = 4'd15; +assign interface1_bus_adr = sdcard_mem2block_dma_sink_sink_payload_address; +assign sdcard_mem2block_dma_fifo_sink_last = sdcard_mem2block_dma_sink_sink_last; +assign sdcard_mem2block_dma_fifo_sink_payload_data = {interface1_bus_dat_r[7:0], interface1_bus_dat_r[15:8], interface1_bus_dat_r[23:16], interface1_bus_dat_r[31:24]}; +always @(*) begin + sdcard_mem2block_dma_fifo_sink_valid <= 1'd0; + sdcard_mem2block_dma_sink_sink_ready <= 1'd0; + if ((interface1_bus_stb & interface1_bus_ack)) begin + sdcard_mem2block_dma_sink_sink_ready <= 1'd1; + sdcard_mem2block_dma_fifo_sink_valid <= 1'd1; + end +end +assign sdcard_mem2block_dma_source_source_valid = sdcard_mem2block_dma_fifo_source_valid; +assign sdcard_mem2block_dma_fifo_source_ready = sdcard_mem2block_dma_source_source_ready; +assign sdcard_mem2block_dma_source_source_first = sdcard_mem2block_dma_fifo_source_first; +assign sdcard_mem2block_dma_source_source_last = sdcard_mem2block_dma_fifo_source_last; +assign sdcard_mem2block_dma_source_source_payload_data = sdcard_mem2block_dma_fifo_source_payload_data; +assign sdcard_mem2block_dma_base = sdcard_mem2block_dma_base_storage[63:2]; +assign sdcard_mem2block_dma_length = sdcard_mem2block_dma_length_storage[31:2]; +assign sdcard_mem2block_dma_offset_status = sdcard_mem2block_dma_offset; +assign sdcard_mem2block_dma_reset = (~sdcard_mem2block_dma_enable_storage); +assign sdcard_mem2block_dma_fifo_syncfifo_din = {sdcard_mem2block_dma_fifo_fifo_in_last, sdcard_mem2block_dma_fifo_fifo_in_first, sdcard_mem2block_dma_fifo_fifo_in_payload_data}; +assign {sdcard_mem2block_dma_fifo_fifo_out_last, sdcard_mem2block_dma_fifo_fifo_out_first, sdcard_mem2block_dma_fifo_fifo_out_payload_data} = sdcard_mem2block_dma_fifo_syncfifo_dout; +assign sdcard_mem2block_dma_fifo_sink_ready = sdcard_mem2block_dma_fifo_syncfifo_writable; +assign sdcard_mem2block_dma_fifo_syncfifo_we = sdcard_mem2block_dma_fifo_sink_valid; +assign sdcard_mem2block_dma_fifo_fifo_in_first = sdcard_mem2block_dma_fifo_sink_first; +assign sdcard_mem2block_dma_fifo_fifo_in_last = sdcard_mem2block_dma_fifo_sink_last; +assign sdcard_mem2block_dma_fifo_fifo_in_payload_data = sdcard_mem2block_dma_fifo_sink_payload_data; +assign sdcard_mem2block_dma_fifo_source_valid = sdcard_mem2block_dma_fifo_syncfifo_readable; +assign sdcard_mem2block_dma_fifo_source_first = sdcard_mem2block_dma_fifo_fifo_out_first; +assign sdcard_mem2block_dma_fifo_source_last = sdcard_mem2block_dma_fifo_fifo_out_last; +assign sdcard_mem2block_dma_fifo_source_payload_data = sdcard_mem2block_dma_fifo_fifo_out_payload_data; +assign sdcard_mem2block_dma_fifo_syncfifo_re = sdcard_mem2block_dma_fifo_source_ready; +always @(*) begin + sdcard_mem2block_dma_fifo_wrport_adr <= 4'd0; + if (sdcard_mem2block_dma_fifo_replace) begin + sdcard_mem2block_dma_fifo_wrport_adr <= (sdcard_mem2block_dma_fifo_produce - 1'd1); + end else begin + sdcard_mem2block_dma_fifo_wrport_adr <= sdcard_mem2block_dma_fifo_produce; + end +end +assign sdcard_mem2block_dma_fifo_wrport_dat_w = sdcard_mem2block_dma_fifo_syncfifo_din; +assign sdcard_mem2block_dma_fifo_wrport_we = (sdcard_mem2block_dma_fifo_syncfifo_we & (sdcard_mem2block_dma_fifo_syncfifo_writable | sdcard_mem2block_dma_fifo_replace)); +assign sdcard_mem2block_dma_fifo_do_read = (sdcard_mem2block_dma_fifo_syncfifo_readable & sdcard_mem2block_dma_fifo_syncfifo_re); +assign sdcard_mem2block_dma_fifo_rdport_adr = sdcard_mem2block_dma_fifo_consume; +assign sdcard_mem2block_dma_fifo_syncfifo_dout = sdcard_mem2block_dma_fifo_rdport_dat_r; +assign sdcard_mem2block_dma_fifo_syncfifo_writable = (sdcard_mem2block_dma_fifo_level != 5'd16); +assign sdcard_mem2block_dma_fifo_syncfifo_readable = (sdcard_mem2block_dma_fifo_level != 1'd0); +always @(*) begin + sdcard_mem2block_dma_done_status <= 1'd0; + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= 32'd0; + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd0; + sdcard_mem2block_dma_sink_sink_last <= 1'd0; + sdcard_mem2block_dma_sink_sink_payload_address <= 32'd0; + sdcard_mem2block_dma_sink_sink_valid <= 1'd0; + sdmem2blockdma_next_state <= 2'd0; + sdmem2blockdma_next_state <= sdmem2blockdma_state; + case (sdmem2blockdma_state) + 1'd1: begin + sdcard_mem2block_dma_sink_sink_valid <= 1'd1; + sdcard_mem2block_dma_sink_sink_last <= (sdcard_mem2block_dma_offset == (sdcard_mem2block_dma_length - 1'd1)); + sdcard_mem2block_dma_sink_sink_payload_address <= (sdcard_mem2block_dma_base + sdcard_mem2block_dma_offset); + if (sdcard_mem2block_dma_sink_sink_ready) begin + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= (sdcard_mem2block_dma_offset + 1'd1); + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd1; + if (sdcard_mem2block_dma_sink_sink_last) begin + if (sdcard_mem2block_dma_loop_storage) begin + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= 1'd0; + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd1; + end else begin + sdmem2blockdma_next_state <= 2'd2; + end + end + end + end + 2'd2: begin + sdcard_mem2block_dma_done_status <= 1'd1; + end + default: begin + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= 1'd0; + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd1; + sdmem2blockdma_next_state <= 1'd1; + end + endcase +end +assign sdcard_mem2block_converter_source_source_valid = sdcard_mem2block_converter_converter_source_valid; +assign sdcard_mem2block_converter_converter_source_ready = sdcard_mem2block_converter_source_source_ready; +assign sdcard_mem2block_converter_source_source_first = sdcard_mem2block_converter_converter_source_first; +assign sdcard_mem2block_converter_source_source_last = sdcard_mem2block_converter_converter_source_last; +assign sdcard_mem2block_converter_source_source_payload_data = sdcard_mem2block_converter_converter_source_payload_data; +assign sdcard_mem2block_converter_converter_first = (sdcard_mem2block_converter_converter_mux == 1'd0); +assign sdcard_mem2block_converter_converter_last = (sdcard_mem2block_converter_converter_mux == 2'd3); +assign sdcard_mem2block_converter_converter_source_valid = sdcard_mem2block_converter_converter_sink_valid; +assign sdcard_mem2block_converter_converter_source_first = (sdcard_mem2block_converter_converter_sink_first & sdcard_mem2block_converter_converter_first); +assign sdcard_mem2block_converter_converter_source_last = (sdcard_mem2block_converter_converter_sink_last & sdcard_mem2block_converter_converter_last); +assign sdcard_mem2block_converter_converter_sink_ready = (sdcard_mem2block_converter_converter_last & sdcard_mem2block_converter_converter_source_ready); +always @(*) begin + sdcard_mem2block_converter_converter_source_payload_data <= 8'd0; + case (sdcard_mem2block_converter_converter_mux) + 1'd0: begin + sdcard_mem2block_converter_converter_source_payload_data <= sdcard_mem2block_converter_converter_sink_payload_data[31:24]; + end + 1'd1: begin + sdcard_mem2block_converter_converter_source_payload_data <= sdcard_mem2block_converter_converter_sink_payload_data[23:16]; + end + 2'd2: begin + sdcard_mem2block_converter_converter_source_payload_data <= sdcard_mem2block_converter_converter_sink_payload_data[15:8]; + end + default: begin + sdcard_mem2block_converter_converter_source_payload_data <= sdcard_mem2block_converter_converter_sink_payload_data[7:0]; + end + endcase +end +assign sdcard_mem2block_converter_converter_source_payload_valid_token_count = sdcard_mem2block_converter_converter_last; +assign sdcard_mem2block_fifo_syncfifo_din = {sdcard_mem2block_fifo_fifo_in_last, sdcard_mem2block_fifo_fifo_in_first, sdcard_mem2block_fifo_fifo_in_payload_data}; +assign {sdcard_mem2block_fifo_fifo_out_last, sdcard_mem2block_fifo_fifo_out_first, sdcard_mem2block_fifo_fifo_out_payload_data} = sdcard_mem2block_fifo_syncfifo_dout; +assign sdcard_mem2block_fifo_sink_ready = sdcard_mem2block_fifo_syncfifo_writable; +assign sdcard_mem2block_fifo_syncfifo_we = sdcard_mem2block_fifo_sink_valid; +assign sdcard_mem2block_fifo_fifo_in_first = sdcard_mem2block_fifo_sink_first; +assign sdcard_mem2block_fifo_fifo_in_last = sdcard_mem2block_fifo_sink_last; +assign sdcard_mem2block_fifo_fifo_in_payload_data = sdcard_mem2block_fifo_sink_payload_data; +assign sdcard_mem2block_fifo_source_valid = sdcard_mem2block_fifo_readable; +assign sdcard_mem2block_fifo_source_first = sdcard_mem2block_fifo_fifo_out_first; +assign sdcard_mem2block_fifo_source_last = sdcard_mem2block_fifo_fifo_out_last; +assign sdcard_mem2block_fifo_source_payload_data = sdcard_mem2block_fifo_fifo_out_payload_data; +assign sdcard_mem2block_fifo_re = sdcard_mem2block_fifo_source_ready; +assign sdcard_mem2block_fifo_syncfifo_re = (sdcard_mem2block_fifo_syncfifo_readable & ((~sdcard_mem2block_fifo_readable) | sdcard_mem2block_fifo_re)); +assign sdcard_mem2block_fifo_level1 = (sdcard_mem2block_fifo_level0 + sdcard_mem2block_fifo_readable); +always @(*) begin + sdcard_mem2block_fifo_wrport_adr <= 9'd0; + if (sdcard_mem2block_fifo_replace) begin + sdcard_mem2block_fifo_wrport_adr <= (sdcard_mem2block_fifo_produce - 1'd1); + end else begin + sdcard_mem2block_fifo_wrport_adr <= sdcard_mem2block_fifo_produce; + end +end +assign sdcard_mem2block_fifo_wrport_dat_w = sdcard_mem2block_fifo_syncfifo_din; +assign sdcard_mem2block_fifo_wrport_we = (sdcard_mem2block_fifo_syncfifo_we & (sdcard_mem2block_fifo_syncfifo_writable | sdcard_mem2block_fifo_replace)); +assign sdcard_mem2block_fifo_do_read = (sdcard_mem2block_fifo_syncfifo_readable & sdcard_mem2block_fifo_syncfifo_re); +assign sdcard_mem2block_fifo_rdport_adr = sdcard_mem2block_fifo_consume; +assign sdcard_mem2block_fifo_syncfifo_dout = sdcard_mem2block_fifo_rdport_dat_r; +assign sdcard_mem2block_fifo_rdport_re = sdcard_mem2block_fifo_do_read; +assign sdcard_mem2block_fifo_syncfifo_writable = (sdcard_mem2block_fifo_level0 != 10'd512); +assign sdcard_mem2block_fifo_syncfifo_readable = (sdcard_mem2block_fifo_level0 != 1'd0); +assign eventmanager_card_detect0 = card_detect_status1; +assign eventmanager_card_detect1 = card_detect_pending; +always @(*) begin + card_detect_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[0])) begin + card_detect_clear <= 1'd1; + end +end +assign eventmanager_block2mem_dma0 = block2mem_dma_status; +assign eventmanager_block2mem_dma1 = block2mem_dma_pending; +always @(*) begin + block2mem_dma_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[1])) begin + block2mem_dma_clear <= 1'd1; + end +end +assign eventmanager_mem2block_dma0 = mem2block_dma_status; +assign eventmanager_mem2block_dma1 = mem2block_dma_pending; +always @(*) begin + mem2block_dma_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[2])) begin + mem2block_dma_clear <= 1'd1; + end +end +assign eventmanager_cmd_done0 = cmd_done_status; +assign eventmanager_cmd_done1 = cmd_done_pending; +always @(*) begin + cmd_done_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[3])) begin + cmd_done_clear <= 1'd1; + end +end +assign sdcard_irq_irq = ((((eventmanager_pending_status[0] & eventmanager_enable_storage[0]) | (eventmanager_pending_status[1] & eventmanager_enable_storage[1])) | (eventmanager_pending_status[2] & eventmanager_enable_storage[2])) | (eventmanager_pending_status[3] & eventmanager_enable_storage[3])); +assign card_detect_status1 = 1'd0; +assign block2mem_dma_status = 1'd0; +assign mem2block_dma_status = 1'd0; +assign cmd_done_status = cmd_done_trigger; +assign cmd_done_pending = cmd_done_trigger; +always @(*) begin + interface0_ack <= 1'd0; + interface0_dat_r <= 32'd0; + interface1_adr <= 14'd0; + interface1_dat_w <= 32'd0; + interface1_we <= 1'd0; + wishbone2csr_next_state <= 1'd0; + wishbone2csr_next_state <= wishbone2csr_state; + case (wishbone2csr_state) + 1'd1: begin + interface0_ack <= 1'd1; + interface0_dat_r <= interface1_dat_r; + wishbone2csr_next_state <= 1'd0; + end + default: begin + interface1_dat_w <= interface0_dat_w; + if ((interface0_cyc & interface0_stb)) begin + interface1_adr <= interface0_adr[29:0]; + interface1_we <= (interface0_we & (interface0_sel != 1'd0)); + wishbone2csr_next_state <= 1'd1; + end + end + endcase +end +assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); +assign csrbank0_reset0_r = interface0_bank_bus_dat_w[1:0]; +always @(*) begin + csrbank0_reset0_re <= 1'd0; + csrbank0_reset0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_reset0_re <= interface0_bank_bus_we; + csrbank0_reset0_we <= (~interface0_bank_bus_we); + end +end +assign csrbank0_scratch0_r = interface0_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank0_scratch0_re <= 1'd0; + csrbank0_scratch0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_scratch0_re <= interface0_bank_bus_we; + csrbank0_scratch0_we <= (~interface0_bank_bus_we); + end +end +assign csrbank0_bus_errors_r = interface0_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank0_bus_errors_re <= 1'd0; + csrbank0_bus_errors_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 2'd2))) begin + csrbank0_bus_errors_re <= interface0_bank_bus_we; + csrbank0_bus_errors_we <= (~interface0_bank_bus_we); + end +end +always @(*) begin + soc_rst <= 1'd0; + if (reset_re) begin + soc_rst <= reset_storage[0]; + end +end +assign cpu_rst = reset_storage[1]; +assign csrbank0_reset0_w = reset_storage[1:0]; +assign csrbank0_scratch0_w = scratch_storage[31:0]; +assign csrbank0_bus_errors_w = bus_errors_status[31:0]; +assign bus_errors_we = csrbank0_bus_errors_we; +assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); +assign csrbank1_dma_base1_r = interface1_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank1_dma_base1_re <= 1'd0; + csrbank1_dma_base1_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_dma_base1_re <= interface1_bank_bus_we; + csrbank1_dma_base1_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_base0_r = interface1_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank1_dma_base0_re <= 1'd0; + csrbank1_dma_base0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + csrbank1_dma_base0_re <= interface1_bank_bus_we; + csrbank1_dma_base0_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_length0_r = interface1_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank1_dma_length0_re <= 1'd0; + csrbank1_dma_length0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + csrbank1_dma_length0_re <= interface1_bank_bus_we; + csrbank1_dma_length0_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_enable0_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + csrbank1_dma_enable0_re <= 1'd0; + csrbank1_dma_enable0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + csrbank1_dma_enable0_re <= interface1_bank_bus_we; + csrbank1_dma_enable0_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_done_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + csrbank1_dma_done_re <= 1'd0; + csrbank1_dma_done_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + csrbank1_dma_done_re <= interface1_bank_bus_we; + csrbank1_dma_done_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_loop0_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + csrbank1_dma_loop0_re <= 1'd0; + csrbank1_dma_loop0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + csrbank1_dma_loop0_re <= interface1_bank_bus_we; + csrbank1_dma_loop0_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_offset_r = interface1_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank1_dma_offset_re <= 1'd0; + csrbank1_dma_offset_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + csrbank1_dma_offset_re <= interface1_bank_bus_we; + csrbank1_dma_offset_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_base1_w = sdcard_block2mem_wishbonedmawriter_base_storage[63:32]; +assign csrbank1_dma_base0_w = sdcard_block2mem_wishbonedmawriter_base_storage[31:0]; +assign csrbank1_dma_length0_w = sdcard_block2mem_wishbonedmawriter_length_storage[31:0]; +assign csrbank1_dma_enable0_w = sdcard_block2mem_wishbonedmawriter_enable_storage; +assign csrbank1_dma_done_w = sdcard_block2mem_wishbonedmawriter_done_status; +assign sdcard_block2mem_wishbonedmawriter_done_we = csrbank1_dma_done_we; +assign csrbank1_dma_loop0_w = sdcard_block2mem_wishbonedmawriter_loop_storage; +assign csrbank1_dma_offset_w = sdcard_block2mem_wishbonedmawriter_offset_status[31:0]; +assign sdcard_block2mem_wishbonedmawriter_offset_we = csrbank1_dma_offset_we; +assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); +assign csrbank2_cmd_argument0_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_cmd_argument0_re <= 1'd0; + csrbank2_cmd_argument0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_cmd_argument0_re <= interface2_bank_bus_we; + csrbank2_cmd_argument0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_command0_r = interface2_bank_bus_dat_w[13:0]; +always @(*) begin + csrbank2_cmd_command0_re <= 1'd0; + csrbank2_cmd_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_cmd_command0_re <= interface2_bank_bus_we; + csrbank2_cmd_command0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_send0_r = interface2_bank_bus_dat_w[0]; +always @(*) begin + csrbank2_cmd_send0_re <= 1'd0; + csrbank2_cmd_send0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + csrbank2_cmd_send0_re <= interface2_bank_bus_we; + csrbank2_cmd_send0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_response3_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_cmd_response3_re <= 1'd0; + csrbank2_cmd_response3_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin + csrbank2_cmd_response3_re <= interface2_bank_bus_we; + csrbank2_cmd_response3_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_response2_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_cmd_response2_re <= 1'd0; + csrbank2_cmd_response2_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin + csrbank2_cmd_response2_re <= interface2_bank_bus_we; + csrbank2_cmd_response2_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_response1_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_cmd_response1_re <= 1'd0; + csrbank2_cmd_response1_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin + csrbank2_cmd_response1_re <= interface2_bank_bus_we; + csrbank2_cmd_response1_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_response0_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_cmd_response0_re <= 1'd0; + csrbank2_cmd_response0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin + csrbank2_cmd_response0_re <= interface2_bank_bus_we; + csrbank2_cmd_response0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_event_r = interface2_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank2_cmd_event_re <= 1'd0; + csrbank2_cmd_event_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin + csrbank2_cmd_event_re <= interface2_bank_bus_we; + csrbank2_cmd_event_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_data_event_r = interface2_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank2_data_event_re <= 1'd0; + csrbank2_data_event_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin + csrbank2_data_event_re <= interface2_bank_bus_we; + csrbank2_data_event_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_block_length0_r = interface2_bank_bus_dat_w[9:0]; +always @(*) begin + csrbank2_block_length0_re <= 1'd0; + csrbank2_block_length0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin + csrbank2_block_length0_re <= interface2_bank_bus_we; + csrbank2_block_length0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_block_count0_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_block_count0_re <= 1'd0; + csrbank2_block_count0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin + csrbank2_block_count0_re <= interface2_bank_bus_we; + csrbank2_block_count0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_argument0_w = sdcard_core_cmd_argument_storage[31:0]; +assign sdcard_core_csrfield_cmd_type = sdcard_core_cmd_command_storage[1:0]; +assign sdcard_core_csrfield_data_type = sdcard_core_cmd_command_storage[6:5]; +assign sdcard_core_csrfield_cmd = sdcard_core_cmd_command_storage[13:8]; +assign csrbank2_cmd_command0_w = sdcard_core_cmd_command_storage[13:0]; +assign csrbank2_cmd_send0_w = sdcard_core_cmd_send_storage; +assign csrbank2_cmd_response3_w = sdcard_core_cmd_response_status[127:96]; +assign csrbank2_cmd_response2_w = sdcard_core_cmd_response_status[95:64]; +assign csrbank2_cmd_response1_w = sdcard_core_cmd_response_status[63:32]; +assign csrbank2_cmd_response0_w = sdcard_core_cmd_response_status[31:0]; +assign sdcard_core_cmd_response_we = csrbank2_cmd_response0_we; +always @(*) begin + sdcard_core_cmd_event_status <= 4'd0; + sdcard_core_cmd_event_status[0] <= sdcard_core_csrfield_done0; + sdcard_core_cmd_event_status[1] <= sdcard_core_csrfield_error0; + sdcard_core_cmd_event_status[2] <= sdcard_core_csrfield_timeout0; + sdcard_core_cmd_event_status[3] <= sdcard_core_csrfield_crc0; +end +assign csrbank2_cmd_event_w = sdcard_core_cmd_event_status[3:0]; +assign sdcard_core_cmd_event_we = csrbank2_cmd_event_we; +always @(*) begin + sdcard_core_data_event_status <= 4'd0; + sdcard_core_data_event_status[0] <= sdcard_core_csrfield_done1; + sdcard_core_data_event_status[1] <= sdcard_core_csrfield_error1; + sdcard_core_data_event_status[2] <= sdcard_core_csrfield_timeout1; + sdcard_core_data_event_status[3] <= sdcard_core_csrfield_crc1; +end +assign csrbank2_data_event_w = sdcard_core_data_event_status[3:0]; +assign sdcard_core_data_event_we = csrbank2_data_event_we; +assign csrbank2_block_length0_w = sdcard_core_block_length_storage[9:0]; +assign csrbank2_block_count0_w = sdcard_core_block_count_storage[31:0]; +assign csrbank3_sel = (interface3_bank_bus_adr[13:9] == 2'd3); +assign csrbank3_status_r = interface3_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank3_status_re <= 1'd0; + csrbank3_status_we <= 1'd0; + if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 1'd0))) begin + csrbank3_status_re <= interface3_bank_bus_we; + csrbank3_status_we <= (~interface3_bank_bus_we); + end +end +assign csrbank3_pending_r = interface3_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank3_pending_re <= 1'd0; + csrbank3_pending_we <= 1'd0; + if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 1'd1))) begin + csrbank3_pending_re <= interface3_bank_bus_we; + csrbank3_pending_we <= (~interface3_bank_bus_we); + end +end +assign csrbank3_enable0_r = interface3_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank3_enable0_re <= 1'd0; + csrbank3_enable0_we <= 1'd0; + if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 2'd2))) begin + csrbank3_enable0_re <= interface3_bank_bus_we; + csrbank3_enable0_we <= (~interface3_bank_bus_we); + end +end +always @(*) begin + eventmanager_status_status <= 4'd0; + eventmanager_status_status[0] <= eventmanager_card_detect0; + eventmanager_status_status[1] <= eventmanager_block2mem_dma0; + eventmanager_status_status[2] <= eventmanager_mem2block_dma0; + eventmanager_status_status[3] <= eventmanager_cmd_done0; +end +assign csrbank3_status_w = eventmanager_status_status[3:0]; +assign eventmanager_status_we = csrbank3_status_we; +always @(*) begin + eventmanager_pending_status <= 4'd0; + eventmanager_pending_status[0] <= eventmanager_card_detect1; + eventmanager_pending_status[1] <= eventmanager_block2mem_dma1; + eventmanager_pending_status[2] <= eventmanager_mem2block_dma1; + eventmanager_pending_status[3] <= eventmanager_cmd_done1; +end +assign csrbank3_pending_w = eventmanager_pending_status[3:0]; +assign eventmanager_pending_we = csrbank3_pending_we; +assign eventmanager_card_detect2 = eventmanager_enable_storage[0]; +assign eventmanager_block2mem_dma2 = eventmanager_enable_storage[1]; +assign eventmanager_mem2block_dma2 = eventmanager_enable_storage[2]; +assign eventmanager_cmd_done2 = eventmanager_enable_storage[3]; +assign csrbank3_enable0_w = eventmanager_enable_storage[3:0]; +assign csrbank4_sel = (interface4_bank_bus_adr[13:9] == 3'd4); +assign csrbank4_dma_base1_r = interface4_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank4_dma_base1_re <= 1'd0; + csrbank4_dma_base1_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 1'd0))) begin + csrbank4_dma_base1_re <= interface4_bank_bus_we; + csrbank4_dma_base1_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_base0_r = interface4_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank4_dma_base0_re <= 1'd0; + csrbank4_dma_base0_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 1'd1))) begin + csrbank4_dma_base0_re <= interface4_bank_bus_we; + csrbank4_dma_base0_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_length0_r = interface4_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank4_dma_length0_re <= 1'd0; + csrbank4_dma_length0_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 2'd2))) begin + csrbank4_dma_length0_re <= interface4_bank_bus_we; + csrbank4_dma_length0_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_enable0_r = interface4_bank_bus_dat_w[0]; +always @(*) begin + csrbank4_dma_enable0_re <= 1'd0; + csrbank4_dma_enable0_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 2'd3))) begin + csrbank4_dma_enable0_re <= interface4_bank_bus_we; + csrbank4_dma_enable0_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_done_r = interface4_bank_bus_dat_w[0]; +always @(*) begin + csrbank4_dma_done_re <= 1'd0; + csrbank4_dma_done_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd4))) begin + csrbank4_dma_done_re <= interface4_bank_bus_we; + csrbank4_dma_done_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_loop0_r = interface4_bank_bus_dat_w[0]; +always @(*) begin + csrbank4_dma_loop0_re <= 1'd0; + csrbank4_dma_loop0_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd5))) begin + csrbank4_dma_loop0_re <= interface4_bank_bus_we; + csrbank4_dma_loop0_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_offset_r = interface4_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank4_dma_offset_re <= 1'd0; + csrbank4_dma_offset_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd6))) begin + csrbank4_dma_offset_re <= interface4_bank_bus_we; + csrbank4_dma_offset_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_base1_w = sdcard_mem2block_dma_base_storage[63:32]; +assign csrbank4_dma_base0_w = sdcard_mem2block_dma_base_storage[31:0]; +assign csrbank4_dma_length0_w = sdcard_mem2block_dma_length_storage[31:0]; +assign csrbank4_dma_enable0_w = sdcard_mem2block_dma_enable_storage; +assign csrbank4_dma_done_w = sdcard_mem2block_dma_done_status; +assign sdcard_mem2block_dma_done_we = csrbank4_dma_done_we; +assign csrbank4_dma_loop0_w = sdcard_mem2block_dma_loop_storage; +assign csrbank4_dma_offset_w = sdcard_mem2block_dma_offset_status[31:0]; +assign sdcard_mem2block_dma_offset_we = csrbank4_dma_offset_we; +assign csrbank5_sel = (interface5_bank_bus_adr[13:9] == 3'd5); +assign csrbank5_card_detect_r = interface5_bank_bus_dat_w[0]; +always @(*) begin + csrbank5_card_detect_re <= 1'd0; + csrbank5_card_detect_we <= 1'd0; + if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 1'd0))) begin + csrbank5_card_detect_re <= interface5_bank_bus_we; + csrbank5_card_detect_we <= (~interface5_bank_bus_we); + end +end +assign csrbank5_clocker_divider0_r = interface5_bank_bus_dat_w[8:0]; +always @(*) begin + csrbank5_clocker_divider0_re <= 1'd0; + csrbank5_clocker_divider0_we <= 1'd0; + if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 1'd1))) begin + csrbank5_clocker_divider0_re <= interface5_bank_bus_we; + csrbank5_clocker_divider0_we <= (~interface5_bank_bus_we); + end +end +assign init_initialize_r = interface5_bank_bus_dat_w[0]; +always @(*) begin + init_initialize_re <= 1'd0; + init_initialize_we <= 1'd0; + if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 2'd2))) begin + init_initialize_re <= interface5_bank_bus_we; + init_initialize_we <= (~interface5_bank_bus_we); + end +end +assign csrbank5_dataw_status_r = interface5_bank_bus_dat_w[2:0]; +always @(*) begin + csrbank5_dataw_status_re <= 1'd0; + csrbank5_dataw_status_we <= 1'd0; + if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 2'd3))) begin + csrbank5_dataw_status_re <= interface5_bank_bus_we; + csrbank5_dataw_status_we <= (~interface5_bank_bus_we); + end +end +assign csrbank5_card_detect_w = card_detect_status0; +assign card_detect_we = csrbank5_card_detect_we; +assign csrbank5_clocker_divider0_w = clocker_storage[8:0]; +always @(*) begin + dataw_status <= 3'd0; + dataw_status[0] <= dataw_accepted0; + dataw_status[1] <= dataw_crc_error0; + dataw_status[2] <= dataw_write_error0; +end +assign csrbank5_dataw_status_w = dataw_status[2:0]; +assign dataw_we = csrbank5_dataw_status_we; +assign adr = interface1_adr; +assign we = interface1_we; +assign dat_w = interface1_dat_w; +assign interface1_dat_r = dat_r; +assign interface0_bank_bus_adr = adr; +assign interface1_bank_bus_adr = adr; +assign interface2_bank_bus_adr = adr; +assign interface3_bank_bus_adr = adr; +assign interface4_bank_bus_adr = adr; +assign interface5_bank_bus_adr = adr; +assign interface0_bank_bus_we = we; +assign interface1_bank_bus_we = we; +assign interface2_bank_bus_we = we; +assign interface3_bank_bus_we = we; +assign interface4_bank_bus_we = we; +assign interface5_bank_bus_we = we; +assign interface0_bank_bus_dat_w = dat_w; +assign interface1_bank_bus_dat_w = dat_w; +assign interface2_bank_bus_dat_w = dat_w; +assign interface3_bank_bus_dat_w = dat_w; +assign interface4_bank_bus_dat_w = dat_w; +assign interface5_bank_bus_dat_w = dat_w; +assign dat_r = (((((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r) | interface3_bank_bus_dat_r) | interface4_bank_bus_dat_r) | interface5_bank_bus_dat_r); +always @(*) begin + self0 <= 32'd0; + case (grant) + 1'd0: begin + self0 <= interface0_bus_adr; + end + default: begin + self0 <= interface1_bus_adr; + end + endcase +end +always @(*) begin + self1 <= 32'd0; + case (grant) + 1'd0: begin + self1 <= interface0_bus_dat_w; + end + default: begin + self1 <= interface1_bus_dat_w; + end + endcase +end +always @(*) begin + self2 <= 4'd0; + case (grant) + 1'd0: begin + self2 <= interface0_bus_sel; + end + default: begin + self2 <= interface1_bus_sel; + end + endcase +end +always @(*) begin + self3 <= 1'd0; + case (grant) + 1'd0: begin + self3 <= interface0_bus_cyc; + end + default: begin + self3 <= interface1_bus_cyc; + end + endcase +end +always @(*) begin + self4 <= 1'd0; + case (grant) + 1'd0: begin + self4 <= interface0_bus_stb; + end + default: begin + self4 <= interface1_bus_stb; + end + endcase +end +always @(*) begin + self5 <= 1'd0; + case (grant) + 1'd0: begin + self5 <= interface0_bus_we; + end + default: begin + self5 <= interface1_bus_we; + end + endcase +end +always @(*) begin + self6 <= 3'd0; + case (grant) + 1'd0: begin + self6 <= interface0_bus_cti; + end + default: begin + self6 <= interface1_bus_cti; + end + endcase +end +always @(*) begin + self7 <= 2'd0; + case (grant) + 1'd0: begin + self7 <= interface0_bus_bte; + end + default: begin + self7 <= interface1_bus_bte; + end + endcase +end +assign sdrio_clk = sys_clk; +assign sdrio_clk_1 = sys_clk; +assign sdrio_clk_2 = sys_clk; +assign sdrio_clk_3 = sys_clk; +assign sdrio_clk_4 = sys_clk; +assign sdrio_clk_5 = sys_clk; +assign sdrio_clk_6 = sys_clk; +assign sdrio_clk_7 = sys_clk; +assign sdrio_clk_8 = sys_clk; +assign sdrio_clk_9 = sys_clk; +assign sdrio_clk_10 = sys_clk; +assign sdrio_clk_11 = sys_clk; +assign sdrio_clk_12 = sys_clk; +assign sdrio_clk_13 = sys_clk; +assign sdrio_clk_15 = sys_clk; +assign sdrio_clk_16 = sys_clk; +assign sdrio_clk_17 = sys_clk; +assign sdrio_clk_18 = sys_clk; +assign sdrio_clk_14 = sys_clk; + + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + +always @(posedge por_clk) begin + int_rst <= rst; +end + +always @(posedge sdrio_clk) begin + sdcard_clk <= (~clocker_clk0); + sdcard_cmd_dir <= sdpads_cmd_oe; + sdcard_dat0_dir <= sdpads_data_oe; + sdcard_dat13_dir <= sdpads_data_oe; + xilinxsdrtristateimpl0__o <= sdpads_cmd_o; + xilinxsdrtristateimpl0_oe_n <= (~sdpads_cmd_oe); + sdpads_cmd_i <= xilinxsdrtristateimpl0__i; + xilinxsdrtristateimpl1__o <= sdpads_data_o[0]; + xilinxsdrtristateimpl1_oe_n <= (~sdpads_data_oe); + sdpads_data_i[0] <= xilinxsdrtristateimpl1__i; + xilinxsdrtristateimpl2__o <= sdpads_data_o[1]; + xilinxsdrtristateimpl2_oe_n <= (~sdpads_data_oe); + sdpads_data_i[1] <= xilinxsdrtristateimpl2__i; + xilinxsdrtristateimpl3__o <= sdpads_data_o[2]; + xilinxsdrtristateimpl3_oe_n <= (~sdpads_data_oe); + sdpads_data_i[2] <= xilinxsdrtristateimpl3__i; + xilinxsdrtristateimpl4__o <= sdpads_data_o[3]; + xilinxsdrtristateimpl4_oe_n <= (~sdpads_data_oe); + sdpads_data_i[3] <= xilinxsdrtristateimpl4__i; +end + +always @(posedge sys_clk) begin + if ((bus_errors != 32'd4294967295)) begin + if (bus_error) begin + bus_errors <= (bus_errors + 1'd1); + end + end + case (grant) + 1'd0: begin + if ((~request[0])) begin + if (request[1]) begin + grant <= 1'd1; + end + end + end + 1'd1: begin + if ((~request[1])) begin + if (request[0]) begin + grant <= 1'd0; + end + end + end + endcase + slave_sel_r <= slave_sel; + if (wait_1) begin + if ((~done)) begin + count <= (count - 1'd1); + end + end else begin + count <= 20'd1000000; + end + card_detect_d <= card_detect_status0; + card_detect_irq <= (card_detect_status0 ^ card_detect_d); + if ((~clocker_stop)) begin + clocker_clks <= (clocker_clks + 1'd1); + end + clocker_clk_d <= clocker_clk1; + if (clocker_clk_d) begin + clocker_ce_delayed <= clocker_clk_en; + end + sdphyinit_state <= sdphyinit_next_state; + if (init_count_sdphyinit_next_value_ce) begin + init_count <= init_count_sdphyinit_next_value; + end + sdphycmdw_state <= sdphycmdw_next_state; + if (cmdw_count_sdphycmdw_next_value_ce) begin + cmdw_count <= cmdw_count_sdphycmdw_next_value; + end + if (cmdr_cmdr_pads_in_valid) begin + cmdr_cmdr_run <= (cmdr_cmdr_start | cmdr_cmdr_run); + end + if (cmdr_cmdr_converter_converter_source_ready) begin + cmdr_cmdr_converter_converter_strobe_all <= 1'd0; + end + if (cmdr_cmdr_converter_converter_load_part) begin + if (((cmdr_cmdr_converter_converter_demux == 3'd7) | cmdr_cmdr_converter_converter_sink_last)) begin + cmdr_cmdr_converter_converter_demux <= 1'd0; + cmdr_cmdr_converter_converter_strobe_all <= 1'd1; + end else begin + cmdr_cmdr_converter_converter_demux <= (cmdr_cmdr_converter_converter_demux + 1'd1); + end + end + if ((cmdr_cmdr_converter_converter_source_valid & cmdr_cmdr_converter_converter_source_ready)) begin + if ((cmdr_cmdr_converter_converter_sink_valid & cmdr_cmdr_converter_converter_sink_ready)) begin + cmdr_cmdr_converter_converter_source_first <= cmdr_cmdr_converter_converter_sink_first; + cmdr_cmdr_converter_converter_source_last <= cmdr_cmdr_converter_converter_sink_last; + end else begin + cmdr_cmdr_converter_converter_source_first <= 1'd0; + cmdr_cmdr_converter_converter_source_last <= 1'd0; + end + end else begin + if ((cmdr_cmdr_converter_converter_sink_valid & cmdr_cmdr_converter_converter_sink_ready)) begin + cmdr_cmdr_converter_converter_source_first <= (cmdr_cmdr_converter_converter_sink_first | cmdr_cmdr_converter_converter_source_first); + cmdr_cmdr_converter_converter_source_last <= (cmdr_cmdr_converter_converter_sink_last | cmdr_cmdr_converter_converter_source_last); + end + end + if (cmdr_cmdr_converter_converter_load_part) begin + case (cmdr_cmdr_converter_converter_demux) + 1'd0: begin + cmdr_cmdr_converter_converter_source_payload_data[7] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 1'd1: begin + cmdr_cmdr_converter_converter_source_payload_data[6] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 2'd2: begin + cmdr_cmdr_converter_converter_source_payload_data[5] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 2'd3: begin + cmdr_cmdr_converter_converter_source_payload_data[4] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 3'd4: begin + cmdr_cmdr_converter_converter_source_payload_data[3] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 3'd5: begin + cmdr_cmdr_converter_converter_source_payload_data[2] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 3'd6: begin + cmdr_cmdr_converter_converter_source_payload_data[1] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 3'd7: begin + cmdr_cmdr_converter_converter_source_payload_data[0] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + endcase + end + if (cmdr_cmdr_converter_converter_load_part) begin + cmdr_cmdr_converter_converter_source_payload_valid_token_count <= (cmdr_cmdr_converter_converter_demux + 1'd1); + end + if (((~cmdr_cmdr_buf_pipe_valid_source_valid) | cmdr_cmdr_buf_pipe_valid_source_ready)) begin + cmdr_cmdr_buf_pipe_valid_source_valid <= cmdr_cmdr_buf_pipe_valid_sink_valid; + cmdr_cmdr_buf_pipe_valid_source_first <= cmdr_cmdr_buf_pipe_valid_sink_first; + cmdr_cmdr_buf_pipe_valid_source_last <= cmdr_cmdr_buf_pipe_valid_sink_last; + cmdr_cmdr_buf_pipe_valid_source_payload_data <= cmdr_cmdr_buf_pipe_valid_sink_payload_data; + end + if (cmdr_cmdr_reset) begin + cmdr_cmdr_run <= 1'd0; + cmdr_cmdr_converter_converter_source_payload_data <= 8'd0; + cmdr_cmdr_converter_converter_source_payload_valid_token_count <= 4'd0; + cmdr_cmdr_converter_converter_demux <= 3'd0; + cmdr_cmdr_converter_converter_strobe_all <= 1'd0; + cmdr_cmdr_buf_pipe_valid_source_valid <= 1'd0; + cmdr_cmdr_buf_pipe_valid_source_payload_data <= 8'd0; + end + sdphycmdr_state <= sdphycmdr_next_state; + if (cmdr_timeout_sdphycmdr_next_value_ce0) begin + cmdr_timeout <= cmdr_timeout_sdphycmdr_next_value0; + end + if (cmdr_count_sdphycmdr_next_value_ce1) begin + cmdr_count <= cmdr_count_sdphycmdr_next_value1; + end + if (cmdr_busy_sdphycmdr_next_value_ce2) begin + cmdr_busy <= cmdr_busy_sdphycmdr_next_value2; + end + if (cmdr_cmdr_reset_sdphycmdr_next_value_ce3) begin + cmdr_cmdr_reset <= cmdr_cmdr_reset_sdphycmdr_next_value3; + end + if (dataw_crc_pads_in_valid) begin + dataw_crc_run <= (dataw_crc_start | dataw_crc_run); + end + if (dataw_crc_converter_converter_source_ready) begin + dataw_crc_converter_converter_strobe_all <= 1'd0; + end + if (dataw_crc_converter_converter_load_part) begin + if (((dataw_crc_converter_converter_demux == 3'd7) | dataw_crc_converter_converter_sink_last)) begin + dataw_crc_converter_converter_demux <= 1'd0; + dataw_crc_converter_converter_strobe_all <= 1'd1; + end else begin + dataw_crc_converter_converter_demux <= (dataw_crc_converter_converter_demux + 1'd1); + end + end + if ((dataw_crc_converter_converter_source_valid & dataw_crc_converter_converter_source_ready)) begin + if ((dataw_crc_converter_converter_sink_valid & dataw_crc_converter_converter_sink_ready)) begin + dataw_crc_converter_converter_source_first <= dataw_crc_converter_converter_sink_first; + dataw_crc_converter_converter_source_last <= dataw_crc_converter_converter_sink_last; + end else begin + dataw_crc_converter_converter_source_first <= 1'd0; + dataw_crc_converter_converter_source_last <= 1'd0; + end + end else begin + if ((dataw_crc_converter_converter_sink_valid & dataw_crc_converter_converter_sink_ready)) begin + dataw_crc_converter_converter_source_first <= (dataw_crc_converter_converter_sink_first | dataw_crc_converter_converter_source_first); + dataw_crc_converter_converter_source_last <= (dataw_crc_converter_converter_sink_last | dataw_crc_converter_converter_source_last); + end + end + if (dataw_crc_converter_converter_load_part) begin + case (dataw_crc_converter_converter_demux) + 1'd0: begin + dataw_crc_converter_converter_source_payload_data[7] <= dataw_crc_converter_converter_sink_payload_data; + end + 1'd1: begin + dataw_crc_converter_converter_source_payload_data[6] <= dataw_crc_converter_converter_sink_payload_data; + end + 2'd2: begin + dataw_crc_converter_converter_source_payload_data[5] <= dataw_crc_converter_converter_sink_payload_data; + end + 2'd3: begin + dataw_crc_converter_converter_source_payload_data[4] <= dataw_crc_converter_converter_sink_payload_data; + end + 3'd4: begin + dataw_crc_converter_converter_source_payload_data[3] <= dataw_crc_converter_converter_sink_payload_data; + end + 3'd5: begin + dataw_crc_converter_converter_source_payload_data[2] <= dataw_crc_converter_converter_sink_payload_data; + end + 3'd6: begin + dataw_crc_converter_converter_source_payload_data[1] <= dataw_crc_converter_converter_sink_payload_data; + end + 3'd7: begin + dataw_crc_converter_converter_source_payload_data[0] <= dataw_crc_converter_converter_sink_payload_data; + end + endcase + end + if (dataw_crc_converter_converter_load_part) begin + dataw_crc_converter_converter_source_payload_valid_token_count <= (dataw_crc_converter_converter_demux + 1'd1); + end + if (((~dataw_crc_buf_pipe_valid_source_valid) | dataw_crc_buf_pipe_valid_source_ready)) begin + dataw_crc_buf_pipe_valid_source_valid <= dataw_crc_buf_pipe_valid_sink_valid; + dataw_crc_buf_pipe_valid_source_first <= dataw_crc_buf_pipe_valid_sink_first; + dataw_crc_buf_pipe_valid_source_last <= dataw_crc_buf_pipe_valid_sink_last; + dataw_crc_buf_pipe_valid_source_payload_data <= dataw_crc_buf_pipe_valid_sink_payload_data; + end + if (dataw_crc_reset) begin + dataw_crc_run <= 1'd0; + dataw_crc_converter_converter_source_payload_data <= 8'd0; + dataw_crc_converter_converter_source_payload_valid_token_count <= 4'd0; + dataw_crc_converter_converter_demux <= 3'd0; + dataw_crc_converter_converter_strobe_all <= 1'd0; + dataw_crc_buf_pipe_valid_source_valid <= 1'd0; + dataw_crc_buf_pipe_valid_source_payload_data <= 8'd0; + end + sdphydataw_state <= sdphydataw_next_state; + if (dataw_accepted1_sdphydataw_next_value_ce0) begin + dataw_accepted1 <= dataw_accepted1_sdphydataw_next_value0; + end + if (dataw_crc_error1_sdphydataw_next_value_ce1) begin + dataw_crc_error1 <= dataw_crc_error1_sdphydataw_next_value1; + end + if (dataw_write_error1_sdphydataw_next_value_ce2) begin + dataw_write_error1 <= dataw_write_error1_sdphydataw_next_value2; + end + if (dataw_count_sdphydataw_next_value_ce3) begin + dataw_count <= dataw_count_sdphydataw_next_value3; + end + if (datar_datar_pads_in_valid) begin + datar_datar_run <= (datar_datar_start | datar_datar_run); + end + if (datar_datar_converter_converter_source_ready) begin + datar_datar_converter_converter_strobe_all <= 1'd0; + end + if (datar_datar_converter_converter_load_part) begin + if (((datar_datar_converter_converter_demux == 1'd1) | datar_datar_converter_converter_sink_last)) begin + datar_datar_converter_converter_demux <= 1'd0; + datar_datar_converter_converter_strobe_all <= 1'd1; + end else begin + datar_datar_converter_converter_demux <= (datar_datar_converter_converter_demux + 1'd1); + end + end + if ((datar_datar_converter_converter_source_valid & datar_datar_converter_converter_source_ready)) begin + if ((datar_datar_converter_converter_sink_valid & datar_datar_converter_converter_sink_ready)) begin + datar_datar_converter_converter_source_first <= datar_datar_converter_converter_sink_first; + datar_datar_converter_converter_source_last <= datar_datar_converter_converter_sink_last; + end else begin + datar_datar_converter_converter_source_first <= 1'd0; + datar_datar_converter_converter_source_last <= 1'd0; + end + end else begin + if ((datar_datar_converter_converter_sink_valid & datar_datar_converter_converter_sink_ready)) begin + datar_datar_converter_converter_source_first <= (datar_datar_converter_converter_sink_first | datar_datar_converter_converter_source_first); + datar_datar_converter_converter_source_last <= (datar_datar_converter_converter_sink_last | datar_datar_converter_converter_source_last); + end + end + if (datar_datar_converter_converter_load_part) begin + case (datar_datar_converter_converter_demux) + 1'd0: begin + datar_datar_converter_converter_source_payload_data[7:4] <= datar_datar_converter_converter_sink_payload_data; + end + 1'd1: begin + datar_datar_converter_converter_source_payload_data[3:0] <= datar_datar_converter_converter_sink_payload_data; + end + endcase + end + if (datar_datar_converter_converter_load_part) begin + datar_datar_converter_converter_source_payload_valid_token_count <= (datar_datar_converter_converter_demux + 1'd1); + end + if (((~datar_datar_buf_pipe_valid_source_valid) | datar_datar_buf_pipe_valid_source_ready)) begin + datar_datar_buf_pipe_valid_source_valid <= datar_datar_buf_pipe_valid_sink_valid; + datar_datar_buf_pipe_valid_source_first <= datar_datar_buf_pipe_valid_sink_first; + datar_datar_buf_pipe_valid_source_last <= datar_datar_buf_pipe_valid_sink_last; + datar_datar_buf_pipe_valid_source_payload_data <= datar_datar_buf_pipe_valid_sink_payload_data; + end + if (datar_datar_reset) begin + datar_datar_run <= 1'd0; + datar_datar_converter_converter_source_payload_data <= 8'd0; + datar_datar_converter_converter_source_payload_valid_token_count <= 2'd0; + datar_datar_converter_converter_demux <= 1'd0; + datar_datar_converter_converter_strobe_all <= 1'd0; + datar_datar_buf_pipe_valid_source_valid <= 1'd0; + datar_datar_buf_pipe_valid_source_payload_data <= 8'd0; + end + sdphydatar_state <= sdphydatar_next_state; + if (datar_count_sdphydatar_next_value_ce0) begin + datar_count <= datar_count_sdphydatar_next_value0; + end + if (datar_timeout_sdphydatar_next_value_ce1) begin + datar_timeout <= datar_timeout_sdphydatar_next_value1; + end + if (datar_datar_reset_sdphydatar_next_value_ce2) begin + datar_datar_reset <= datar_datar_reset_sdphydatar_next_value2; + end + clocker_clk_delay <= {clocker_clk_delay, clocker_clk0}; + sdpads_data_i_ce <= (clocker_clk_delay[1] & (~clocker_clk_delay[0])); + sdcard_core_done_d <= sdcard_core_cmd_done; + sdcard_core_irq <= (sdcard_core_cmd_done & (~sdcard_core_done_d)); + if (sdcard_core_crc7_inserter_crc_reset) begin + sdcard_core_crc7_inserter_crc0 <= 1'd0; + end else begin + if (sdcard_core_crc7_inserter_crc_enable) begin + sdcard_core_crc7_inserter_crc0 <= sdcard_core_crc7_inserter_crc40; + end + end + if (sdcard_core_crc16_inserter_crc0_reset) begin + sdcard_core_crc16_inserter_crc00 <= 1'd0; + end else begin + if (sdcard_core_crc16_inserter_crc0_enable) begin + sdcard_core_crc16_inserter_crc00 <= sdcard_core_crc16_inserter_crc02; + end + end + if (sdcard_core_crc16_inserter_crc1_reset) begin + sdcard_core_crc16_inserter_crc10 <= 1'd0; + end else begin + if (sdcard_core_crc16_inserter_crc1_enable) begin + sdcard_core_crc16_inserter_crc10 <= sdcard_core_crc16_inserter_crc12; + end + end + if (sdcard_core_crc16_inserter_crc2_reset) begin + sdcard_core_crc16_inserter_crc20 <= 1'd0; + end else begin + if (sdcard_core_crc16_inserter_crc2_enable) begin + sdcard_core_crc16_inserter_crc20 <= sdcard_core_crc16_inserter_crc22; + end + end + if (sdcard_core_crc16_inserter_crc3_reset) begin + sdcard_core_crc16_inserter_crc30 <= 1'd0; + end else begin + if (sdcard_core_crc16_inserter_crc3_enable) begin + sdcard_core_crc16_inserter_crc30 <= sdcard_core_crc16_inserter_crc32; + end + end + crc16inserter_state <= crc16inserter_next_state; + if (sdcard_core_crc16_inserter_count_crc16inserter_next_value_ce) begin + sdcard_core_crc16_inserter_count <= sdcard_core_crc16_inserter_count_crc16inserter_next_value; + end + if (((sdcard_core_fifo_syncfifo_we & sdcard_core_fifo_syncfifo_writable) & (~sdcard_core_fifo_replace))) begin + sdcard_core_fifo_produce <= (sdcard_core_fifo_produce + 1'd1); + end + if (sdcard_core_fifo_do_read) begin + sdcard_core_fifo_consume <= (sdcard_core_fifo_consume + 1'd1); + end + if (((sdcard_core_fifo_syncfifo_we & sdcard_core_fifo_syncfifo_writable) & (~sdcard_core_fifo_replace))) begin + if ((~sdcard_core_fifo_do_read)) begin + sdcard_core_fifo_level <= (sdcard_core_fifo_level + 1'd1); + end + end else begin + if (sdcard_core_fifo_do_read) begin + sdcard_core_fifo_level <= (sdcard_core_fifo_level - 1'd1); + end + end + if (sdcard_core_fifo_reset) begin + sdcard_core_fifo_level <= 4'd0; + sdcard_core_fifo_produce <= 3'd0; + sdcard_core_fifo_consume <= 3'd0; + end + fsm_state <= fsm_next_state; + if (sdcard_core_cmd_done_fsm_next_value_ce0) begin + sdcard_core_cmd_done <= sdcard_core_cmd_done_fsm_next_value0; + end + if (sdcard_core_data_done_fsm_next_value_ce1) begin + sdcard_core_data_done <= sdcard_core_data_done_fsm_next_value1; + end + if (sdcard_core_cmd_count_fsm_next_value_ce2) begin + sdcard_core_cmd_count <= sdcard_core_cmd_count_fsm_next_value2; + end + if (sdcard_core_data_count_fsm_next_value_ce3) begin + sdcard_core_data_count <= sdcard_core_data_count_fsm_next_value3; + end + if (sdcard_core_cmd_error_fsm_next_value_ce4) begin + sdcard_core_cmd_error <= sdcard_core_cmd_error_fsm_next_value4; + end + if (sdcard_core_cmd_timeout_fsm_next_value_ce5) begin + sdcard_core_cmd_timeout <= sdcard_core_cmd_timeout_fsm_next_value5; + end + if (sdcard_core_data_error_fsm_next_value_ce6) begin + sdcard_core_data_error <= sdcard_core_data_error_fsm_next_value6; + end + if (sdcard_core_data_timeout_fsm_next_value_ce7) begin + sdcard_core_data_timeout <= sdcard_core_data_timeout_fsm_next_value7; + end + if (sdcard_core_cmd_response_status_fsm_next_value_ce8) begin + sdcard_core_cmd_response_status <= sdcard_core_cmd_response_status_fsm_next_value8; + end + if ((~sdcard_block2mem_wishbonedmawriter_enable_storage)) begin + sdcard_block2mem_connect <= 1'd0; + end else begin + if (sdcard_block2mem_start) begin + sdcard_block2mem_connect <= 1'd1; + end + end + sdcard_block2mem_done_d <= sdcard_block2mem_wishbonedmawriter_done_status; + sdcard_block2mem_irq <= (sdcard_block2mem_wishbonedmawriter_done_status & (~sdcard_block2mem_done_d)); + if (sdcard_block2mem_fifo_syncfifo_re) begin + sdcard_block2mem_fifo_readable <= 1'd1; + end else begin + if (sdcard_block2mem_fifo_re) begin + sdcard_block2mem_fifo_readable <= 1'd0; + end + end + if (((sdcard_block2mem_fifo_syncfifo_we & sdcard_block2mem_fifo_syncfifo_writable) & (~sdcard_block2mem_fifo_replace))) begin + sdcard_block2mem_fifo_produce <= (sdcard_block2mem_fifo_produce + 1'd1); + end + if (sdcard_block2mem_fifo_do_read) begin + sdcard_block2mem_fifo_consume <= (sdcard_block2mem_fifo_consume + 1'd1); + end + if (((sdcard_block2mem_fifo_syncfifo_we & sdcard_block2mem_fifo_syncfifo_writable) & (~sdcard_block2mem_fifo_replace))) begin + if ((~sdcard_block2mem_fifo_do_read)) begin + sdcard_block2mem_fifo_level0 <= (sdcard_block2mem_fifo_level0 + 1'd1); + end + end else begin + if (sdcard_block2mem_fifo_do_read) begin + sdcard_block2mem_fifo_level0 <= (sdcard_block2mem_fifo_level0 - 1'd1); + end + end + if (sdcard_block2mem_converter_source_ready) begin + sdcard_block2mem_converter_strobe_all <= 1'd0; + end + if (sdcard_block2mem_converter_load_part) begin + if (((sdcard_block2mem_converter_demux == 2'd3) | sdcard_block2mem_converter_sink_last)) begin + sdcard_block2mem_converter_demux <= 1'd0; + sdcard_block2mem_converter_strobe_all <= 1'd1; + end else begin + sdcard_block2mem_converter_demux <= (sdcard_block2mem_converter_demux + 1'd1); + end + end + if ((sdcard_block2mem_converter_source_valid & sdcard_block2mem_converter_source_ready)) begin + if ((sdcard_block2mem_converter_sink_valid & sdcard_block2mem_converter_sink_ready)) begin + sdcard_block2mem_converter_source_first <= sdcard_block2mem_converter_sink_first; + sdcard_block2mem_converter_source_last <= sdcard_block2mem_converter_sink_last; + end else begin + sdcard_block2mem_converter_source_first <= 1'd0; + sdcard_block2mem_converter_source_last <= 1'd0; + end + end else begin + if ((sdcard_block2mem_converter_sink_valid & sdcard_block2mem_converter_sink_ready)) begin + sdcard_block2mem_converter_source_first <= (sdcard_block2mem_converter_sink_first | sdcard_block2mem_converter_source_first); + sdcard_block2mem_converter_source_last <= (sdcard_block2mem_converter_sink_last | sdcard_block2mem_converter_source_last); + end + end + if (sdcard_block2mem_converter_load_part) begin + case (sdcard_block2mem_converter_demux) + 1'd0: begin + sdcard_block2mem_converter_source_payload_data[31:24] <= sdcard_block2mem_converter_sink_payload_data; + end + 1'd1: begin + sdcard_block2mem_converter_source_payload_data[23:16] <= sdcard_block2mem_converter_sink_payload_data; + end + 2'd2: begin + sdcard_block2mem_converter_source_payload_data[15:8] <= sdcard_block2mem_converter_sink_payload_data; + end + 2'd3: begin + sdcard_block2mem_converter_source_payload_data[7:0] <= sdcard_block2mem_converter_sink_payload_data; + end + endcase + end + if (sdcard_block2mem_converter_load_part) begin + sdcard_block2mem_converter_source_payload_valid_token_count <= (sdcard_block2mem_converter_demux + 1'd1); + end + sdblock2memdma_state <= sdblock2memdma_next_state; + if (sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce) begin + sdcard_block2mem_wishbonedmawriter_offset <= sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value; + end + if (sdcard_block2mem_wishbonedmawriter_reset) begin + sdcard_block2mem_wishbonedmawriter_offset <= 32'd0; + sdblock2memdma_state <= 2'd0; + end + if ((sdcard_mem2block_source_source_valid & sdcard_mem2block_source_source_ready)) begin + sdcard_mem2block_count <= (sdcard_mem2block_count + 1'd1); + if (sdcard_mem2block_source_source_last) begin + sdcard_mem2block_count <= 1'd0; + end + end + sdcard_mem2block_done_d <= sdcard_mem2block_dma_done_status; + sdcard_mem2block_irq <= (sdcard_mem2block_dma_done_status & (~sdcard_mem2block_done_d)); + if (((sdcard_mem2block_dma_fifo_syncfifo_we & sdcard_mem2block_dma_fifo_syncfifo_writable) & (~sdcard_mem2block_dma_fifo_replace))) begin + sdcard_mem2block_dma_fifo_produce <= (sdcard_mem2block_dma_fifo_produce + 1'd1); + end + if (sdcard_mem2block_dma_fifo_do_read) begin + sdcard_mem2block_dma_fifo_consume <= (sdcard_mem2block_dma_fifo_consume + 1'd1); + end + if (((sdcard_mem2block_dma_fifo_syncfifo_we & sdcard_mem2block_dma_fifo_syncfifo_writable) & (~sdcard_mem2block_dma_fifo_replace))) begin + if ((~sdcard_mem2block_dma_fifo_do_read)) begin + sdcard_mem2block_dma_fifo_level <= (sdcard_mem2block_dma_fifo_level + 1'd1); + end + end else begin + if (sdcard_mem2block_dma_fifo_do_read) begin + sdcard_mem2block_dma_fifo_level <= (sdcard_mem2block_dma_fifo_level - 1'd1); + end + end + sdmem2blockdma_state <= sdmem2blockdma_next_state; + if (sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce) begin + sdcard_mem2block_dma_offset <= sdcard_mem2block_dma_offset_sdmem2blockdma_next_value; + end + if (sdcard_mem2block_dma_reset) begin + sdcard_mem2block_dma_offset <= 32'd0; + sdmem2blockdma_state <= 2'd0; + end + if ((sdcard_mem2block_converter_converter_source_valid & sdcard_mem2block_converter_converter_source_ready)) begin + if (sdcard_mem2block_converter_converter_last) begin + sdcard_mem2block_converter_converter_mux <= 1'd0; + end else begin + sdcard_mem2block_converter_converter_mux <= (sdcard_mem2block_converter_converter_mux + 1'd1); + end + end + if (sdcard_mem2block_fifo_syncfifo_re) begin + sdcard_mem2block_fifo_readable <= 1'd1; + end else begin + if (sdcard_mem2block_fifo_re) begin + sdcard_mem2block_fifo_readable <= 1'd0; + end + end + if (((sdcard_mem2block_fifo_syncfifo_we & sdcard_mem2block_fifo_syncfifo_writable) & (~sdcard_mem2block_fifo_replace))) begin + sdcard_mem2block_fifo_produce <= (sdcard_mem2block_fifo_produce + 1'd1); + end + if (sdcard_mem2block_fifo_do_read) begin + sdcard_mem2block_fifo_consume <= (sdcard_mem2block_fifo_consume + 1'd1); + end + if (((sdcard_mem2block_fifo_syncfifo_we & sdcard_mem2block_fifo_syncfifo_writable) & (~sdcard_mem2block_fifo_replace))) begin + if ((~sdcard_mem2block_fifo_do_read)) begin + sdcard_mem2block_fifo_level0 <= (sdcard_mem2block_fifo_level0 + 1'd1); + end + end else begin + if (sdcard_mem2block_fifo_do_read) begin + sdcard_mem2block_fifo_level0 <= (sdcard_mem2block_fifo_level0 - 1'd1); + end + end + if (card_detect_clear) begin + card_detect_pending <= 1'd0; + end + if (card_detect_trigger) begin + card_detect_pending <= 1'd1; + end + if (block2mem_dma_clear) begin + block2mem_dma_pending <= 1'd0; + end + if (block2mem_dma_trigger) begin + block2mem_dma_pending <= 1'd1; + end + if (mem2block_dma_clear) begin + mem2block_dma_pending <= 1'd0; + end + if (mem2block_dma_trigger) begin + mem2block_dma_pending <= 1'd1; + end + wishbone2csr_state <= wishbone2csr_next_state; + interface0_bank_bus_dat_r <= 1'd0; + if (csrbank0_sel) begin + case (interface0_bank_bus_adr[8:0]) + 1'd0: begin + interface0_bank_bus_dat_r <= csrbank0_reset0_w; + end + 1'd1: begin + interface0_bank_bus_dat_r <= csrbank0_scratch0_w; + end + 2'd2: begin + interface0_bank_bus_dat_r <= csrbank0_bus_errors_w; + end + endcase + end + if (csrbank0_reset0_re) begin + reset_storage[1:0] <= csrbank0_reset0_r; + end + reset_re <= csrbank0_reset0_re; + if (csrbank0_scratch0_re) begin + scratch_storage[31:0] <= csrbank0_scratch0_r; + end + scratch_re <= csrbank0_scratch0_re; + bus_errors_re <= csrbank0_bus_errors_re; + interface1_bank_bus_dat_r <= 1'd0; + if (csrbank1_sel) begin + case (interface1_bank_bus_adr[8:0]) + 1'd0: begin + interface1_bank_bus_dat_r <= csrbank1_dma_base1_w; + end + 1'd1: begin + interface1_bank_bus_dat_r <= csrbank1_dma_base0_w; + end + 2'd2: begin + interface1_bank_bus_dat_r <= csrbank1_dma_length0_w; + end + 2'd3: begin + interface1_bank_bus_dat_r <= csrbank1_dma_enable0_w; + end + 3'd4: begin + interface1_bank_bus_dat_r <= csrbank1_dma_done_w; + end + 3'd5: begin + interface1_bank_bus_dat_r <= csrbank1_dma_loop0_w; + end + 3'd6: begin + interface1_bank_bus_dat_r <= csrbank1_dma_offset_w; + end + endcase + end + if (csrbank1_dma_base1_re) begin + sdcard_block2mem_wishbonedmawriter_base_storage[63:32] <= csrbank1_dma_base1_r; + end + if (csrbank1_dma_base0_re) begin + sdcard_block2mem_wishbonedmawriter_base_storage[31:0] <= csrbank1_dma_base0_r; + end + sdcard_block2mem_wishbonedmawriter_base_re <= csrbank1_dma_base0_re; + if (csrbank1_dma_length0_re) begin + sdcard_block2mem_wishbonedmawriter_length_storage[31:0] <= csrbank1_dma_length0_r; + end + sdcard_block2mem_wishbonedmawriter_length_re <= csrbank1_dma_length0_re; + if (csrbank1_dma_enable0_re) begin + sdcard_block2mem_wishbonedmawriter_enable_storage <= csrbank1_dma_enable0_r; + end + sdcard_block2mem_wishbonedmawriter_enable_re <= csrbank1_dma_enable0_re; + sdcard_block2mem_wishbonedmawriter_done_re <= csrbank1_dma_done_re; + if (csrbank1_dma_loop0_re) begin + sdcard_block2mem_wishbonedmawriter_loop_storage <= csrbank1_dma_loop0_r; + end + sdcard_block2mem_wishbonedmawriter_loop_re <= csrbank1_dma_loop0_re; + sdcard_block2mem_wishbonedmawriter_offset_re <= csrbank1_dma_offset_re; + interface2_bank_bus_dat_r <= 1'd0; + if (csrbank2_sel) begin + case (interface2_bank_bus_adr[8:0]) + 1'd0: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_argument0_w; + end + 1'd1: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_command0_w; + end + 2'd2: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_send0_w; + end + 2'd3: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_response3_w; + end + 3'd4: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_response2_w; + end + 3'd5: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_response1_w; + end + 3'd6: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_response0_w; + end + 3'd7: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_event_w; + end + 4'd8: begin + interface2_bank_bus_dat_r <= csrbank2_data_event_w; + end + 4'd9: begin + interface2_bank_bus_dat_r <= csrbank2_block_length0_w; + end + 4'd10: begin + interface2_bank_bus_dat_r <= csrbank2_block_count0_w; + end + endcase + end + if (csrbank2_cmd_argument0_re) begin + sdcard_core_cmd_argument_storage[31:0] <= csrbank2_cmd_argument0_r; + end + sdcard_core_cmd_argument_re <= csrbank2_cmd_argument0_re; + if (csrbank2_cmd_command0_re) begin + sdcard_core_cmd_command_storage[13:0] <= csrbank2_cmd_command0_r; + end + sdcard_core_cmd_command_re <= csrbank2_cmd_command0_re; + if (csrbank2_cmd_send0_re) begin + sdcard_core_cmd_send_storage <= csrbank2_cmd_send0_r; + end + sdcard_core_cmd_send_re <= csrbank2_cmd_send0_re; + sdcard_core_cmd_response_re <= csrbank2_cmd_response0_re; + sdcard_core_cmd_event_re <= csrbank2_cmd_event_re; + sdcard_core_data_event_re <= csrbank2_data_event_re; + if (csrbank2_block_length0_re) begin + sdcard_core_block_length_storage[9:0] <= csrbank2_block_length0_r; + end + sdcard_core_block_length_re <= csrbank2_block_length0_re; + if (csrbank2_block_count0_re) begin + sdcard_core_block_count_storage[31:0] <= csrbank2_block_count0_r; + end + sdcard_core_block_count_re <= csrbank2_block_count0_re; + interface3_bank_bus_dat_r <= 1'd0; + if (csrbank3_sel) begin + case (interface3_bank_bus_adr[8:0]) + 1'd0: begin + interface3_bank_bus_dat_r <= csrbank3_status_w; + end + 1'd1: begin + interface3_bank_bus_dat_r <= csrbank3_pending_w; + end + 2'd2: begin + interface3_bank_bus_dat_r <= csrbank3_enable0_w; + end + endcase + end + eventmanager_status_re <= csrbank3_status_re; + if (csrbank3_pending_re) begin + eventmanager_pending_r[3:0] <= csrbank3_pending_r; + end + eventmanager_pending_re <= csrbank3_pending_re; + if (csrbank3_enable0_re) begin + eventmanager_enable_storage[3:0] <= csrbank3_enable0_r; + end + eventmanager_enable_re <= csrbank3_enable0_re; + interface4_bank_bus_dat_r <= 1'd0; + if (csrbank4_sel) begin + case (interface4_bank_bus_adr[8:0]) + 1'd0: begin + interface4_bank_bus_dat_r <= csrbank4_dma_base1_w; + end + 1'd1: begin + interface4_bank_bus_dat_r <= csrbank4_dma_base0_w; + end + 2'd2: begin + interface4_bank_bus_dat_r <= csrbank4_dma_length0_w; + end + 2'd3: begin + interface4_bank_bus_dat_r <= csrbank4_dma_enable0_w; + end + 3'd4: begin + interface4_bank_bus_dat_r <= csrbank4_dma_done_w; + end + 3'd5: begin + interface4_bank_bus_dat_r <= csrbank4_dma_loop0_w; + end + 3'd6: begin + interface4_bank_bus_dat_r <= csrbank4_dma_offset_w; + end + endcase + end + if (csrbank4_dma_base1_re) begin + sdcard_mem2block_dma_base_storage[63:32] <= csrbank4_dma_base1_r; + end + if (csrbank4_dma_base0_re) begin + sdcard_mem2block_dma_base_storage[31:0] <= csrbank4_dma_base0_r; + end + sdcard_mem2block_dma_base_re <= csrbank4_dma_base0_re; + if (csrbank4_dma_length0_re) begin + sdcard_mem2block_dma_length_storage[31:0] <= csrbank4_dma_length0_r; + end + sdcard_mem2block_dma_length_re <= csrbank4_dma_length0_re; + if (csrbank4_dma_enable0_re) begin + sdcard_mem2block_dma_enable_storage <= csrbank4_dma_enable0_r; + end + sdcard_mem2block_dma_enable_re <= csrbank4_dma_enable0_re; + sdcard_mem2block_dma_done_re <= csrbank4_dma_done_re; + if (csrbank4_dma_loop0_re) begin + sdcard_mem2block_dma_loop_storage <= csrbank4_dma_loop0_r; + end + sdcard_mem2block_dma_loop_re <= csrbank4_dma_loop0_re; + sdcard_mem2block_dma_offset_re <= csrbank4_dma_offset_re; + interface5_bank_bus_dat_r <= 1'd0; + if (csrbank5_sel) begin + case (interface5_bank_bus_adr[8:0]) + 1'd0: begin + interface5_bank_bus_dat_r <= csrbank5_card_detect_w; + end + 1'd1: begin + interface5_bank_bus_dat_r <= csrbank5_clocker_divider0_w; + end + 2'd2: begin + interface5_bank_bus_dat_r <= init_initialize_w; + end + 2'd3: begin + interface5_bank_bus_dat_r <= csrbank5_dataw_status_w; + end + endcase + end + card_detect_re <= csrbank5_card_detect_re; + if (csrbank5_clocker_divider0_re) begin + clocker_storage[8:0] <= csrbank5_clocker_divider0_r; + end + clocker_re <= csrbank5_clocker_divider0_re; + dataw_re <= csrbank5_dataw_status_re; + if (sys_rst) begin + reset_storage <= 2'd0; + reset_re <= 1'd0; + scratch_storage <= 32'd305419896; + scratch_re <= 1'd0; + bus_errors_re <= 1'd0; + bus_errors <= 32'd0; + card_detect_re <= 1'd0; + clocker_storage <= 9'd256; + clocker_re <= 1'd0; + clocker_clks <= 9'd0; + clocker_clk_d <= 1'd0; + clocker_ce_delayed <= 1'd0; + init_count <= 8'd0; + cmdw_count <= 8'd0; + cmdr_timeout <= 32'd100000000; + cmdr_count <= 8'd0; + cmdr_busy <= 1'd0; + cmdr_cmdr_run <= 1'd0; + cmdr_cmdr_converter_converter_source_payload_data <= 8'd0; + cmdr_cmdr_converter_converter_source_payload_valid_token_count <= 4'd0; + cmdr_cmdr_converter_converter_demux <= 3'd0; + cmdr_cmdr_converter_converter_strobe_all <= 1'd0; + cmdr_cmdr_buf_pipe_valid_source_valid <= 1'd0; + cmdr_cmdr_buf_pipe_valid_source_payload_data <= 8'd0; + cmdr_cmdr_reset <= 1'd0; + dataw_re <= 1'd0; + dataw_count <= 8'd0; + dataw_accepted1 <= 1'd0; + dataw_crc_error1 <= 1'd0; + dataw_write_error1 <= 1'd0; + dataw_crc_run <= 1'd0; + dataw_crc_converter_converter_source_payload_data <= 8'd0; + dataw_crc_converter_converter_source_payload_valid_token_count <= 4'd0; + dataw_crc_converter_converter_demux <= 3'd0; + dataw_crc_converter_converter_strobe_all <= 1'd0; + dataw_crc_buf_pipe_valid_source_valid <= 1'd0; + dataw_crc_buf_pipe_valid_source_payload_data <= 8'd0; + datar_timeout <= 32'd100000000; + datar_count <= 10'd0; + datar_datar_run <= 1'd0; + datar_datar_converter_converter_source_payload_data <= 8'd0; + datar_datar_converter_converter_source_payload_valid_token_count <= 2'd0; + datar_datar_converter_converter_demux <= 1'd0; + datar_datar_converter_converter_strobe_all <= 1'd0; + datar_datar_buf_pipe_valid_source_valid <= 1'd0; + datar_datar_buf_pipe_valid_source_payload_data <= 8'd0; + datar_datar_reset <= 1'd0; + sdpads_data_i_ce <= 1'd0; + clocker_clk_delay <= 2'd0; + card_detect_irq <= 1'd0; + card_detect_d <= 1'd0; + sdcard_core_irq <= 1'd0; + sdcard_core_cmd_argument_storage <= 32'd0; + sdcard_core_cmd_argument_re <= 1'd0; + sdcard_core_cmd_command_storage <= 14'd0; + sdcard_core_cmd_command_re <= 1'd0; + sdcard_core_cmd_send_storage <= 1'd0; + sdcard_core_cmd_send_re <= 1'd0; + sdcard_core_cmd_response_status <= 128'd0; + sdcard_core_cmd_response_re <= 1'd0; + sdcard_core_cmd_event_re <= 1'd0; + sdcard_core_data_event_re <= 1'd0; + sdcard_core_block_length_storage <= 10'd0; + sdcard_core_block_length_re <= 1'd0; + sdcard_core_block_count_storage <= 32'd0; + sdcard_core_block_count_re <= 1'd0; + sdcard_core_crc7_inserter_crc0 <= 7'd0; + sdcard_core_crc16_inserter_count <= 3'd0; + sdcard_core_crc16_inserter_crc00 <= 16'd0; + sdcard_core_crc16_inserter_crc10 <= 16'd0; + sdcard_core_crc16_inserter_crc20 <= 16'd0; + sdcard_core_crc16_inserter_crc30 <= 16'd0; + sdcard_core_fifo_level <= 4'd0; + sdcard_core_fifo_produce <= 3'd0; + sdcard_core_fifo_consume <= 3'd0; + sdcard_core_cmd_count <= 3'd0; + sdcard_core_cmd_done <= 1'd0; + sdcard_core_cmd_error <= 1'd0; + sdcard_core_cmd_timeout <= 1'd0; + sdcard_core_data_count <= 32'd0; + sdcard_core_data_done <= 1'd0; + sdcard_core_data_error <= 1'd0; + sdcard_core_data_timeout <= 1'd0; + sdcard_core_done_d <= 1'd0; + sdcard_block2mem_irq <= 1'd0; + sdcard_block2mem_fifo_readable <= 1'd0; + sdcard_block2mem_fifo_level0 <= 10'd0; + sdcard_block2mem_fifo_produce <= 9'd0; + sdcard_block2mem_fifo_consume <= 9'd0; + sdcard_block2mem_converter_source_payload_data <= 32'd0; + sdcard_block2mem_converter_source_payload_valid_token_count <= 3'd0; + sdcard_block2mem_converter_demux <= 2'd0; + sdcard_block2mem_converter_strobe_all <= 1'd0; + sdcard_block2mem_wishbonedmawriter_base_storage <= 64'd0; + sdcard_block2mem_wishbonedmawriter_base_re <= 1'd0; + sdcard_block2mem_wishbonedmawriter_length_storage <= 32'd0; + sdcard_block2mem_wishbonedmawriter_length_re <= 1'd0; + sdcard_block2mem_wishbonedmawriter_enable_storage <= 1'd0; + sdcard_block2mem_wishbonedmawriter_enable_re <= 1'd0; + sdcard_block2mem_wishbonedmawriter_done_re <= 1'd0; + sdcard_block2mem_wishbonedmawriter_loop_storage <= 1'd0; + sdcard_block2mem_wishbonedmawriter_loop_re <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset_re <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset <= 32'd0; + sdcard_block2mem_connect <= 1'd0; + sdcard_block2mem_done_d <= 1'd0; + sdcard_mem2block_irq <= 1'd0; + sdcard_mem2block_dma_fifo_level <= 5'd0; + sdcard_mem2block_dma_fifo_produce <= 4'd0; + sdcard_mem2block_dma_fifo_consume <= 4'd0; + sdcard_mem2block_dma_base_storage <= 64'd0; + sdcard_mem2block_dma_base_re <= 1'd0; + sdcard_mem2block_dma_length_storage <= 32'd0; + sdcard_mem2block_dma_length_re <= 1'd0; + sdcard_mem2block_dma_enable_storage <= 1'd0; + sdcard_mem2block_dma_enable_re <= 1'd0; + sdcard_mem2block_dma_done_re <= 1'd0; + sdcard_mem2block_dma_loop_storage <= 1'd0; + sdcard_mem2block_dma_loop_re <= 1'd0; + sdcard_mem2block_dma_offset_re <= 1'd0; + sdcard_mem2block_dma_offset <= 32'd0; + sdcard_mem2block_converter_converter_mux <= 2'd0; + sdcard_mem2block_fifo_readable <= 1'd0; + sdcard_mem2block_fifo_level0 <= 10'd0; + sdcard_mem2block_fifo_produce <= 9'd0; + sdcard_mem2block_fifo_consume <= 9'd0; + sdcard_mem2block_count <= 9'd0; + sdcard_mem2block_done_d <= 1'd0; + card_detect_pending <= 1'd0; + block2mem_dma_pending <= 1'd0; + mem2block_dma_pending <= 1'd0; + eventmanager_status_re <= 1'd0; + eventmanager_pending_re <= 1'd0; + eventmanager_pending_r <= 4'd0; + eventmanager_enable_storage <= 4'd0; + eventmanager_enable_re <= 1'd0; + grant <= 1'd0; + slave_sel_r <= 1'd0; + count <= 20'd1000000; + sdphyinit_state <= 1'd0; + sdphycmdw_state <= 2'd0; + sdphycmdr_state <= 3'd0; + sdphydataw_state <= 3'd0; + sdphydatar_state <= 3'd0; + crc16inserter_state <= 1'd0; + fsm_state <= 3'd0; + sdblock2memdma_state <= 2'd0; + sdmem2blockdma_state <= 2'd0; + wishbone2csr_state <= 1'd0; + end +end + + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Instance BUFG of BUFG Module. +//------------------------------------------------------------------------------ +BUFG BUFG( + // Inputs. + .I ((clocker_clk1 & (~clocker_clk_d))), + + // Outputs. + .O (clocker_ce) +); + +//------------------------------------------------------------------------------ +// Memory storage: 8-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Async | Write: ---- | +reg [9:0] storage[0:7]; +reg [9:0] storage_dat0; +always @(posedge sys_clk) begin + if (sdcard_core_fifo_wrport_we) + storage[sdcard_core_fifo_wrport_adr] <= sdcard_core_fifo_wrport_dat_w; + storage_dat0 <= storage[sdcard_core_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign sdcard_core_fifo_wrport_dat_r = storage_dat0; +assign sdcard_core_fifo_rdport_dat_r = storage[sdcard_core_fifo_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_1: 512-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Sync | Write: ---- | +reg [9:0] storage_1[0:511]; +reg [9:0] storage_1_dat0; +reg [9:0] storage_1_dat1; +always @(posedge sys_clk) begin + if (sdcard_block2mem_fifo_wrport_we) + storage_1[sdcard_block2mem_fifo_wrport_adr] <= sdcard_block2mem_fifo_wrport_dat_w; + storage_1_dat0 <= storage_1[sdcard_block2mem_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin + if (sdcard_block2mem_fifo_rdport_re) + storage_1_dat1 <= storage_1[sdcard_block2mem_fifo_rdport_adr]; +end +assign sdcard_block2mem_fifo_wrport_dat_r = storage_1_dat0; +assign sdcard_block2mem_fifo_rdport_dat_r = storage_1_dat1; + + +//------------------------------------------------------------------------------ +// Memory storage_2: 16-words x 34-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 34 +// Port 1 | Read: Async | Write: ---- | +reg [33:0] storage_2[0:15]; +reg [33:0] storage_2_dat0; +always @(posedge sys_clk) begin + if (sdcard_mem2block_dma_fifo_wrport_we) + storage_2[sdcard_mem2block_dma_fifo_wrport_adr] <= sdcard_mem2block_dma_fifo_wrport_dat_w; + storage_2_dat0 <= storage_2[sdcard_mem2block_dma_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign sdcard_mem2block_dma_fifo_wrport_dat_r = storage_2_dat0; +assign sdcard_mem2block_dma_fifo_rdport_dat_r = storage_2[sdcard_mem2block_dma_fifo_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_3: 512-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Sync | Write: ---- | +reg [9:0] storage_3[0:511]; +reg [9:0] storage_3_dat0; +reg [9:0] storage_3_dat1; +always @(posedge sys_clk) begin + if (sdcard_mem2block_fifo_wrport_we) + storage_3[sdcard_mem2block_fifo_wrport_adr] <= sdcard_mem2block_fifo_wrport_dat_w; + storage_3_dat0 <= storage_3[sdcard_mem2block_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin + if (sdcard_mem2block_fifo_rdport_re) + storage_3_dat1 <= storage_3[sdcard_mem2block_fifo_rdport_adr]; +end +assign sdcard_mem2block_fifo_wrport_dat_r = storage_3_dat0; +assign sdcard_mem2block_fifo_rdport_dat_r = storage_3_dat1; + + +//------------------------------------------------------------------------------ +// Instance IOBUF of IOBUF Module. +//------------------------------------------------------------------------------ +IOBUF IOBUF( + // Inputs. + .I (xilinxsdrtristateimpl0__o), + .T (xilinxsdrtristateimpl0_oe_n), + + // Outputs. + .O (xilinxsdrtristateimpl0__i), + + // InOuts. + .IO (sdcard_cmd) +); + +//------------------------------------------------------------------------------ +// Instance IOBUF_1 of IOBUF Module. +//------------------------------------------------------------------------------ +IOBUF IOBUF_1( + // Inputs. + .I (xilinxsdrtristateimpl1__o), + .T (xilinxsdrtristateimpl1_oe_n), + + // Outputs. + .O (xilinxsdrtristateimpl1__i), + + // InOuts. + .IO (sdcard_data[0]) +); + +//------------------------------------------------------------------------------ +// Instance IOBUF_2 of IOBUF Module. +//------------------------------------------------------------------------------ +IOBUF IOBUF_2( + // Inputs. + .I (xilinxsdrtristateimpl2__o), + .T (xilinxsdrtristateimpl2_oe_n), + + // Outputs. + .O (xilinxsdrtristateimpl2__i), + + // InOuts. + .IO (sdcard_data[1]) +); + +//------------------------------------------------------------------------------ +// Instance IOBUF_3 of IOBUF Module. +//------------------------------------------------------------------------------ +IOBUF IOBUF_3( + // Inputs. + .I (xilinxsdrtristateimpl3__o), + .T (xilinxsdrtristateimpl3_oe_n), + + // Outputs. + .O (xilinxsdrtristateimpl3__i), + + // InOuts. + .IO (sdcard_data[2]) +); + +//------------------------------------------------------------------------------ +// Instance IOBUF_4 of IOBUF Module. +//------------------------------------------------------------------------------ +IOBUF IOBUF_4( + // Inputs. + .I (xilinxsdrtristateimpl4__o), + .T (xilinxsdrtristateimpl4_oe_n), + + // Outputs. + .O (xilinxsdrtristateimpl4__i), + + // InOuts. + .IO (sdcard_data[3]) +); + +endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2024-04-03 20:02:06. +//------------------------------------------------------------------------------ diff --git a/litesdcard/generated/xilinx/litesdcard_core.v b/litesdcard/generated/xilinx/litesdcard_core.v deleted file mode 100644 index 7c81e48..0000000 --- a/litesdcard/generated/xilinx/litesdcard_core.v +++ /dev/null @@ -1,4253 +0,0 @@ -// ----------------------------------------------------------------------------- -// Auto-Generated by: __ _ __ _ __ -// / / (_) /____ | |/_/ -// / /__/ / __/ -_)> < -// /____/_/\__/\__/_/|_| -// Build your hardware, easily! -// https://github.com/enjoy-digital/litex -// -// Filename : litesdcard_core.v -// Device : -// LiteX sha1 : 6932fc51 -// Date : 2022-08-04 18:14:15 -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// Module -//------------------------------------------------------------------------------ - -module litesdcard_core ( - input wire clk, - input wire rst, - input wire [29:0] wb_ctrl_adr, - input wire [31:0] wb_ctrl_dat_w, - output wire [31:0] wb_ctrl_dat_r, - input wire [3:0] wb_ctrl_sel, - input wire wb_ctrl_cyc, - input wire wb_ctrl_stb, - output wire wb_ctrl_ack, - input wire wb_ctrl_we, - input wire [2:0] wb_ctrl_cti, - input wire [1:0] wb_ctrl_bte, - output wire wb_ctrl_err, - output wire [29:0] wb_dma_adr, - output wire [31:0] wb_dma_dat_w, - input wire [31:0] wb_dma_dat_r, - output wire [3:0] wb_dma_sel, - output wire wb_dma_cyc, - output wire wb_dma_stb, - input wire wb_dma_ack, - output wire wb_dma_we, - output wire [2:0] wb_dma_cti, - output wire [1:0] wb_dma_bte, - input wire wb_dma_err, - inout wire [3:0] sdcard_data, - inout wire sdcard_cmd, - output reg sdcard_clk, - input wire sdcard_cd, - output wire irq -); - - -//------------------------------------------------------------------------------ -// Signals -//------------------------------------------------------------------------------ - -wire sys_clk; -wire sys_rst; -wire por_clk; -reg int_rst = 1'd1; -reg soc_rst = 1'd0; -wire cpu_rst; -reg [1:0] reset_storage = 2'd0; -reg reset_re = 1'd0; -reg [31:0] scratch_storage = 32'd305419896; -reg scratch_re = 1'd0; -wire [31:0] bus_errors_status; -wire bus_errors_we; -reg bus_errors_re = 1'd0; -reg bus_error = 1'd0; -reg [31:0] bus_errors = 32'd0; -wire [29:0] wb_ctrl_adr_1; -wire [31:0] wb_ctrl_dat_w_1; -wire [31:0] wb_ctrl_dat_r_1; -wire [3:0] wb_ctrl_sel_1; -wire wb_ctrl_cyc_1; -wire wb_ctrl_stb_1; -wire wb_ctrl_ack_1; -wire wb_ctrl_we_1; -wire [2:0] wb_ctrl_cti_1; -wire [1:0] wb_ctrl_bte_1; -wire wb_ctrl_err_1; -wire [29:0] wb_dma_adr_1; -wire [31:0] wb_dma_dat_w_1; -wire [31:0] wb_dma_dat_r_1; -wire [3:0] wb_dma_sel_1; -wire wb_dma_cyc_1; -wire wb_dma_stb_1; -wire wb_dma_ack_1; -wire wb_dma_we_1; -wire [2:0] wb_dma_cti_1; -wire [1:0] wb_dma_bte_1; -wire wb_dma_err_1; -wire card_detect_status0; -wire card_detect_we; -reg card_detect_re = 1'd0; -reg [8:0] clocker_storage = 9'd256; -reg clocker_re = 1'd0; -wire clocker_stop; -wire clocker_ce; -wire clocker_clk_en; -wire clocker_clk0; -reg [8:0] clocker_clks = 9'd0; -reg clocker_clk1 = 1'd0; -reg clocker_clk_d = 1'd0; -reg clocker_ce_delayed = 1'd0; -reg clocker_ce_latched = 1'd0; -reg init_initialize_re = 1'd0; -wire init_initialize_r; -reg init_initialize_we = 1'd0; -reg init_initialize_w = 1'd0; -wire init_pads_in_valid; -wire init_pads_in_payload_cmd_i; -wire [3:0] init_pads_in_payload_data_i; -wire init_pads_out_ready; -reg init_pads_out_payload_clk = 1'd0; -reg init_pads_out_payload_cmd_o = 1'd0; -reg init_pads_out_payload_cmd_oe = 1'd0; -reg [3:0] init_pads_out_payload_data_o = 4'd0; -reg init_pads_out_payload_data_oe = 1'd0; -reg [7:0] init_count = 8'd0; -wire cmdw_pads_in_valid; -wire cmdw_pads_in_payload_cmd_i; -wire [3:0] cmdw_pads_in_payload_data_i; -wire cmdw_pads_out_ready; -reg cmdw_pads_out_payload_clk = 1'd0; -reg cmdw_pads_out_payload_cmd_o = 1'd0; -reg cmdw_pads_out_payload_cmd_oe = 1'd0; -reg [3:0] cmdw_pads_out_payload_data_o = 4'd0; -reg cmdw_pads_out_payload_data_oe = 1'd0; -reg cmdw_sink_valid = 1'd0; -reg cmdw_sink_ready = 1'd0; -reg cmdw_sink_last = 1'd0; -reg [7:0] cmdw_sink_payload_data = 8'd0; -reg [1:0] cmdw_sink_payload_cmd_type = 2'd0; -reg cmdw_done = 1'd0; -reg [7:0] cmdw_count = 8'd0; -wire cmdr_pads_in_pads_in_valid; -wire cmdr_pads_in_pads_in_ready; -reg cmdr_pads_in_pads_in_first = 1'd0; -reg cmdr_pads_in_pads_in_last = 1'd0; -reg cmdr_pads_in_pads_in_payload_clk = 1'd0; -wire cmdr_pads_in_pads_in_payload_cmd_i; -reg cmdr_pads_in_pads_in_payload_cmd_o = 1'd0; -reg cmdr_pads_in_pads_in_payload_cmd_oe = 1'd0; -wire [3:0] cmdr_pads_in_pads_in_payload_data_i; -reg [3:0] cmdr_pads_in_pads_in_payload_data_o = 4'd0; -reg cmdr_pads_in_pads_in_payload_data_oe = 1'd0; -reg cmdr_pads_in_pads_in_payload_data_i_ce = 1'd0; -wire cmdr_pads_out_ready; -reg cmdr_pads_out_payload_clk = 1'd0; -reg cmdr_pads_out_payload_cmd_o = 1'd0; -reg cmdr_pads_out_payload_cmd_oe = 1'd0; -reg [3:0] cmdr_pads_out_payload_data_o = 4'd0; -reg cmdr_pads_out_payload_data_oe = 1'd0; -reg cmdr_sink_valid = 1'd0; -reg cmdr_sink_ready = 1'd0; -reg [1:0] cmdr_sink_payload_cmd_type = 2'd0; -reg [1:0] cmdr_sink_payload_data_type = 2'd0; -reg [7:0] cmdr_sink_payload_length = 8'd0; -reg cmdr_source_valid = 1'd0; -reg cmdr_source_ready = 1'd0; -reg cmdr_source_last = 1'd0; -reg [7:0] cmdr_source_payload_data = 8'd0; -reg [2:0] cmdr_source_payload_status = 3'd0; -reg [31:0] cmdr_timeout = 32'd100000000; -reg [7:0] cmdr_count = 8'd0; -reg cmdr_busy = 1'd0; -wire cmdr_cmdr_pads_in_valid; -reg cmdr_cmdr_pads_in_ready = 1'd0; -wire cmdr_cmdr_pads_in_first; -wire cmdr_cmdr_pads_in_last; -wire cmdr_cmdr_pads_in_payload_clk; -wire cmdr_cmdr_pads_in_payload_cmd_i; -wire cmdr_cmdr_pads_in_payload_cmd_o; -wire cmdr_cmdr_pads_in_payload_cmd_oe; -wire [3:0] cmdr_cmdr_pads_in_payload_data_i; -wire [3:0] cmdr_cmdr_pads_in_payload_data_o; -wire cmdr_cmdr_pads_in_payload_data_oe; -wire cmdr_cmdr_pads_in_payload_data_i_ce; -wire cmdr_cmdr_source_source_valid0; -reg cmdr_cmdr_source_source_ready0 = 1'd0; -wire cmdr_cmdr_source_source_first0; -wire cmdr_cmdr_source_source_last0; -wire [7:0] cmdr_cmdr_source_source_payload_data0; -wire cmdr_cmdr_start; -reg cmdr_cmdr_run = 1'd0; -wire cmdr_cmdr_converter_sink_valid; -wire cmdr_cmdr_converter_sink_ready; -reg cmdr_cmdr_converter_sink_first = 1'd0; -reg cmdr_cmdr_converter_sink_last = 1'd0; -wire cmdr_cmdr_converter_sink_payload_data; -wire cmdr_cmdr_converter_source_valid; -wire cmdr_cmdr_converter_source_ready; -reg cmdr_cmdr_converter_source_first = 1'd0; -reg cmdr_cmdr_converter_source_last = 1'd0; -reg [7:0] cmdr_cmdr_converter_source_payload_data = 8'd0; -reg [3:0] cmdr_cmdr_converter_source_payload_valid_token_count = 4'd0; -reg [2:0] cmdr_cmdr_converter_demux = 3'd0; -wire cmdr_cmdr_converter_load_part; -reg cmdr_cmdr_converter_strobe_all = 1'd0; -wire cmdr_cmdr_source_source_valid1; -wire cmdr_cmdr_source_source_ready1; -wire cmdr_cmdr_source_source_first1; -wire cmdr_cmdr_source_source_last1; -wire [7:0] cmdr_cmdr_source_source_payload_data1; -wire cmdr_cmdr_buf_sink_valid; -wire cmdr_cmdr_buf_sink_ready; -wire cmdr_cmdr_buf_sink_first; -wire cmdr_cmdr_buf_sink_last; -wire [7:0] cmdr_cmdr_buf_sink_payload_data; -reg cmdr_cmdr_buf_source_valid = 1'd0; -wire cmdr_cmdr_buf_source_ready; -reg cmdr_cmdr_buf_source_first = 1'd0; -reg cmdr_cmdr_buf_source_last = 1'd0; -reg [7:0] cmdr_cmdr_buf_source_payload_data = 8'd0; -reg cmdr_cmdr_reset = 1'd0; -wire dataw_pads_in_pads_in_valid; -reg dataw_pads_in_pads_in_ready = 1'd0; -reg dataw_pads_in_pads_in_first = 1'd0; -reg dataw_pads_in_pads_in_last = 1'd0; -reg dataw_pads_in_pads_in_payload_clk = 1'd0; -wire dataw_pads_in_pads_in_payload_cmd_i; -reg dataw_pads_in_pads_in_payload_cmd_o = 1'd0; -reg dataw_pads_in_pads_in_payload_cmd_oe = 1'd0; -wire [3:0] dataw_pads_in_pads_in_payload_data_i; -reg [3:0] dataw_pads_in_pads_in_payload_data_o = 4'd0; -reg dataw_pads_in_pads_in_payload_data_oe = 1'd0; -reg dataw_pads_in_pads_in_payload_data_i_ce = 1'd0; -wire dataw_pads_out_ready; -reg dataw_pads_out_payload_clk = 1'd0; -reg dataw_pads_out_payload_cmd_o = 1'd0; -reg dataw_pads_out_payload_cmd_oe = 1'd0; -reg [3:0] dataw_pads_out_payload_data_o = 4'd0; -reg dataw_pads_out_payload_data_oe = 1'd0; -reg dataw_sink_valid = 1'd0; -reg dataw_sink_ready = 1'd0; -reg dataw_sink_first = 1'd0; -reg dataw_sink_last = 1'd0; -reg [7:0] dataw_sink_payload_data = 8'd0; -reg dataw_stop = 1'd0; -wire dataw_accepted0; -wire dataw_crc_error0; -wire dataw_write_error0; -reg [2:0] dataw_status = 3'd0; -wire dataw_we; -reg dataw_re = 1'd0; -reg [7:0] dataw_count = 8'd0; -reg dataw_accepted1 = 1'd0; -reg dataw_crc_error1 = 1'd0; -reg dataw_write_error1 = 1'd0; -wire dataw_crc_pads_in_valid; -wire dataw_crc_pads_in_ready; -wire dataw_crc_pads_in_first; -wire dataw_crc_pads_in_last; -wire dataw_crc_pads_in_payload_clk; -wire dataw_crc_pads_in_payload_cmd_i; -wire dataw_crc_pads_in_payload_cmd_o; -wire dataw_crc_pads_in_payload_cmd_oe; -wire [3:0] dataw_crc_pads_in_payload_data_i; -wire [3:0] dataw_crc_pads_in_payload_data_o; -wire dataw_crc_pads_in_payload_data_oe; -wire dataw_crc_pads_in_payload_data_i_ce; -wire dataw_crc_source_source_valid0; -reg dataw_crc_source_source_ready0 = 1'd0; -wire dataw_crc_source_source_first0; -wire dataw_crc_source_source_last0; -wire [7:0] dataw_crc_source_source_payload_data0; -wire dataw_crc_start; -reg dataw_crc_run = 1'd0; -wire dataw_crc_converter_sink_valid; -wire dataw_crc_converter_sink_ready; -reg dataw_crc_converter_sink_first = 1'd0; -reg dataw_crc_converter_sink_last = 1'd0; -wire dataw_crc_converter_sink_payload_data; -wire dataw_crc_converter_source_valid; -wire dataw_crc_converter_source_ready; -reg dataw_crc_converter_source_first = 1'd0; -reg dataw_crc_converter_source_last = 1'd0; -reg [7:0] dataw_crc_converter_source_payload_data = 8'd0; -reg [3:0] dataw_crc_converter_source_payload_valid_token_count = 4'd0; -reg [2:0] dataw_crc_converter_demux = 3'd0; -wire dataw_crc_converter_load_part; -reg dataw_crc_converter_strobe_all = 1'd0; -wire dataw_crc_source_source_valid1; -wire dataw_crc_source_source_ready1; -wire dataw_crc_source_source_first1; -wire dataw_crc_source_source_last1; -wire [7:0] dataw_crc_source_source_payload_data1; -wire dataw_crc_buf_sink_valid; -wire dataw_crc_buf_sink_ready; -wire dataw_crc_buf_sink_first; -wire dataw_crc_buf_sink_last; -wire [7:0] dataw_crc_buf_sink_payload_data; -reg dataw_crc_buf_source_valid = 1'd0; -wire dataw_crc_buf_source_ready; -reg dataw_crc_buf_source_first = 1'd0; -reg dataw_crc_buf_source_last = 1'd0; -reg [7:0] dataw_crc_buf_source_payload_data = 8'd0; -reg dataw_crc_reset = 1'd0; -wire datar_pads_in_pads_in_valid; -wire datar_pads_in_pads_in_ready; -reg datar_pads_in_pads_in_first = 1'd0; -reg datar_pads_in_pads_in_last = 1'd0; -reg datar_pads_in_pads_in_payload_clk = 1'd0; -wire datar_pads_in_pads_in_payload_cmd_i; -reg datar_pads_in_pads_in_payload_cmd_o = 1'd0; -reg datar_pads_in_pads_in_payload_cmd_oe = 1'd0; -wire [3:0] datar_pads_in_pads_in_payload_data_i; -reg [3:0] datar_pads_in_pads_in_payload_data_o = 4'd0; -reg datar_pads_in_pads_in_payload_data_oe = 1'd0; -reg datar_pads_in_pads_in_payload_data_i_ce = 1'd0; -wire datar_pads_out_ready; -reg datar_pads_out_payload_clk = 1'd0; -reg datar_pads_out_payload_cmd_o = 1'd0; -reg datar_pads_out_payload_cmd_oe = 1'd0; -reg [3:0] datar_pads_out_payload_data_o = 4'd0; -reg datar_pads_out_payload_data_oe = 1'd0; -reg datar_sink_valid = 1'd0; -reg datar_sink_ready = 1'd0; -reg datar_sink_last = 1'd0; -reg [9:0] datar_sink_payload_block_length = 10'd0; -reg datar_source_valid = 1'd0; -reg datar_source_ready = 1'd0; -reg datar_source_first = 1'd0; -reg datar_source_last = 1'd0; -reg [7:0] datar_source_payload_data = 8'd0; -reg [2:0] datar_source_payload_status = 3'd0; -reg datar_stop = 1'd0; -reg [31:0] datar_timeout = 32'd100000000; -reg [9:0] datar_count = 10'd0; -wire datar_datar_pads_in_valid; -reg datar_datar_pads_in_ready = 1'd0; -wire datar_datar_pads_in_first; -wire datar_datar_pads_in_last; -wire datar_datar_pads_in_payload_clk; -wire datar_datar_pads_in_payload_cmd_i; -wire datar_datar_pads_in_payload_cmd_o; -wire datar_datar_pads_in_payload_cmd_oe; -wire [3:0] datar_datar_pads_in_payload_data_i; -wire [3:0] datar_datar_pads_in_payload_data_o; -wire datar_datar_pads_in_payload_data_oe; -wire datar_datar_pads_in_payload_data_i_ce; -wire datar_datar_source_source_valid0; -reg datar_datar_source_source_ready0 = 1'd0; -wire datar_datar_source_source_first0; -wire datar_datar_source_source_last0; -wire [7:0] datar_datar_source_source_payload_data0; -wire datar_datar_start; -reg datar_datar_run = 1'd0; -wire datar_datar_converter_sink_valid; -wire datar_datar_converter_sink_ready; -reg datar_datar_converter_sink_first = 1'd0; -reg datar_datar_converter_sink_last = 1'd0; -wire [3:0] datar_datar_converter_sink_payload_data; -wire datar_datar_converter_source_valid; -wire datar_datar_converter_source_ready; -reg datar_datar_converter_source_first = 1'd0; -reg datar_datar_converter_source_last = 1'd0; -reg [7:0] datar_datar_converter_source_payload_data = 8'd0; -reg [1:0] datar_datar_converter_source_payload_valid_token_count = 2'd0; -reg datar_datar_converter_demux = 1'd0; -wire datar_datar_converter_load_part; -reg datar_datar_converter_strobe_all = 1'd0; -wire datar_datar_source_source_valid1; -wire datar_datar_source_source_ready1; -wire datar_datar_source_source_first1; -wire datar_datar_source_source_last1; -wire [7:0] datar_datar_source_source_payload_data1; -wire datar_datar_buf_sink_valid; -wire datar_datar_buf_sink_ready; -wire datar_datar_buf_sink_first; -wire datar_datar_buf_sink_last; -wire [7:0] datar_datar_buf_sink_payload_data; -reg datar_datar_buf_source_valid = 1'd0; -wire datar_datar_buf_source_ready; -reg datar_datar_buf_source_first = 1'd0; -reg datar_datar_buf_source_last = 1'd0; -reg [7:0] datar_datar_buf_source_payload_data = 8'd0; -reg datar_datar_reset = 1'd0; -wire sdpads_clk; -reg sdpads_cmd_i = 1'd0; -wire sdpads_cmd_o; -wire sdpads_cmd_oe; -reg [3:0] sdpads_data_i = 4'd0; -wire [3:0] sdpads_data_o; -wire sdpads_data_oe; -reg sdpads_data_i_ce = 1'd0; -reg [1:0] clocker_clk_delay = 2'd0; -reg card_detect_irq = 1'd0; -reg card_detect_d = 1'd0; -wire sdcore_sink_sink_valid0; -wire sdcore_sink_sink_ready0; -wire sdcore_sink_sink_first0; -wire sdcore_sink_sink_last0; -wire [7:0] sdcore_sink_sink_payload_data0; -wire sdcore_source_source_valid0; -wire sdcore_source_source_ready0; -wire sdcore_source_source_first0; -wire sdcore_source_source_last0; -wire [7:0] sdcore_source_source_payload_data0; -reg [31:0] sdcore_cmd_argument_storage = 32'd0; -reg sdcore_cmd_argument_re = 1'd0; -wire [1:0] sdcore_csrfield_cmd_type; -wire [1:0] sdcore_csrfield_data_type; -wire [5:0] sdcore_csrfield_cmd; -reg [13:0] sdcore_cmd_command_storage = 14'd0; -reg sdcore_cmd_command_re = 1'd0; -reg sdcore_cmd_send_storage = 1'd0; -reg sdcore_cmd_send_re = 1'd0; -reg [127:0] sdcore_cmd_response_status = 128'd0; -wire sdcore_cmd_response_we; -reg sdcore_cmd_response_re = 1'd0; -wire sdcore_csrfield_done0; -wire sdcore_csrfield_error0; -wire sdcore_csrfield_timeout0; -wire sdcore_csrfield_crc0; -reg [3:0] sdcore_cmd_event_status = 4'd0; -wire sdcore_cmd_event_we; -reg sdcore_cmd_event_re = 1'd0; -wire sdcore_csrfield_done1; -wire sdcore_csrfield_error1; -wire sdcore_csrfield_timeout1; -wire sdcore_csrfield_crc1; -reg [3:0] sdcore_data_event_status = 4'd0; -wire sdcore_data_event_we; -reg sdcore_data_event_re = 1'd0; -reg [9:0] sdcore_block_length_storage = 10'd0; -reg sdcore_block_length_re = 1'd0; -reg [31:0] sdcore_block_count_storage = 32'd0; -reg sdcore_block_count_re = 1'd0; -wire sdcore_crc7_inserter_reset; -wire sdcore_crc7_inserter_enable; -wire [39:0] sdcore_crc7_inserter_din; -reg [6:0] sdcore_crc7_inserter_crc = 7'd0; -reg [6:0] sdcore_crc7_inserter_reg0 = 7'd0; -wire [6:0] sdcore_crc7_inserter_reg1; -wire [6:0] sdcore_crc7_inserter_reg2; -wire [6:0] sdcore_crc7_inserter_reg3; -wire [6:0] sdcore_crc7_inserter_reg4; -wire [6:0] sdcore_crc7_inserter_reg5; -wire [6:0] sdcore_crc7_inserter_reg6; -wire [6:0] sdcore_crc7_inserter_reg7; -wire [6:0] sdcore_crc7_inserter_reg8; -wire [6:0] sdcore_crc7_inserter_reg9; -wire [6:0] sdcore_crc7_inserter_reg10; -wire [6:0] sdcore_crc7_inserter_reg11; -wire [6:0] sdcore_crc7_inserter_reg12; -wire [6:0] sdcore_crc7_inserter_reg13; -wire [6:0] sdcore_crc7_inserter_reg14; -wire [6:0] sdcore_crc7_inserter_reg15; -wire [6:0] sdcore_crc7_inserter_reg16; -wire [6:0] sdcore_crc7_inserter_reg17; -wire [6:0] sdcore_crc7_inserter_reg18; -wire [6:0] sdcore_crc7_inserter_reg19; -wire [6:0] sdcore_crc7_inserter_reg20; -wire [6:0] sdcore_crc7_inserter_reg21; -wire [6:0] sdcore_crc7_inserter_reg22; -wire [6:0] sdcore_crc7_inserter_reg23; -wire [6:0] sdcore_crc7_inserter_reg24; -wire [6:0] sdcore_crc7_inserter_reg25; -wire [6:0] sdcore_crc7_inserter_reg26; -wire [6:0] sdcore_crc7_inserter_reg27; -wire [6:0] sdcore_crc7_inserter_reg28; -wire [6:0] sdcore_crc7_inserter_reg29; -wire [6:0] sdcore_crc7_inserter_reg30; -wire [6:0] sdcore_crc7_inserter_reg31; -wire [6:0] sdcore_crc7_inserter_reg32; -wire [6:0] sdcore_crc7_inserter_reg33; -wire [6:0] sdcore_crc7_inserter_reg34; -wire [6:0] sdcore_crc7_inserter_reg35; -wire [6:0] sdcore_crc7_inserter_reg36; -wire [6:0] sdcore_crc7_inserter_reg37; -wire [6:0] sdcore_crc7_inserter_reg38; -wire [6:0] sdcore_crc7_inserter_reg39; -wire [6:0] sdcore_crc7_inserter_reg40; -wire sdcore_crc16_inserter_sink_valid; -reg sdcore_crc16_inserter_sink_ready = 1'd0; -wire sdcore_crc16_inserter_sink_first; -wire sdcore_crc16_inserter_sink_last; -wire [7:0] sdcore_crc16_inserter_sink_payload_data; -reg sdcore_crc16_inserter_source_valid = 1'd0; -reg sdcore_crc16_inserter_source_ready = 1'd0; -reg sdcore_crc16_inserter_source_first = 1'd0; -reg sdcore_crc16_inserter_source_last = 1'd0; -reg [7:0] sdcore_crc16_inserter_source_payload_data = 8'd0; -reg [2:0] sdcore_crc16_inserter_count = 3'd0; -wire sdcore_crc16_inserter_crc0_reset; -wire sdcore_crc16_inserter_crc0_enable; -reg [1:0] sdcore_crc16_inserter_crc0_din = 2'd0; -reg [15:0] sdcore_crc16_inserter_crc0_crc = 16'd0; -reg [15:0] sdcore_crc16_inserter_crc0_reg0 = 16'd0; -wire [15:0] sdcore_crc16_inserter_crc0_reg1; -wire [15:0] sdcore_crc16_inserter_crc0_reg2; -wire sdcore_crc16_inserter_crc1_reset; -wire sdcore_crc16_inserter_crc1_enable; -reg [1:0] sdcore_crc16_inserter_crc1_din = 2'd0; -reg [15:0] sdcore_crc16_inserter_crc1_crc = 16'd0; -reg [15:0] sdcore_crc16_inserter_crc1_reg0 = 16'd0; -wire [15:0] sdcore_crc16_inserter_crc1_reg1; -wire [15:0] sdcore_crc16_inserter_crc1_reg2; -wire sdcore_crc16_inserter_crc2_reset; -wire sdcore_crc16_inserter_crc2_enable; -reg [1:0] sdcore_crc16_inserter_crc2_din = 2'd0; -reg [15:0] sdcore_crc16_inserter_crc2_crc = 16'd0; -reg [15:0] sdcore_crc16_inserter_crc2_reg0 = 16'd0; -wire [15:0] sdcore_crc16_inserter_crc2_reg1; -wire [15:0] sdcore_crc16_inserter_crc2_reg2; -wire sdcore_crc16_inserter_crc3_reset; -wire sdcore_crc16_inserter_crc3_enable; -reg [1:0] sdcore_crc16_inserter_crc3_din = 2'd0; -reg [15:0] sdcore_crc16_inserter_crc3_crc = 16'd0; -reg [15:0] sdcore_crc16_inserter_crc3_reg0 = 16'd0; -wire [15:0] sdcore_crc16_inserter_crc3_reg1; -wire [15:0] sdcore_crc16_inserter_crc3_reg2; -reg sdcore_sink_sink_valid1 = 1'd0; -wire sdcore_sink_sink_ready1; -reg sdcore_sink_sink_first1 = 1'd0; -reg sdcore_sink_sink_last1 = 1'd0; -reg [7:0] sdcore_sink_sink_payload_data1 = 8'd0; -wire sdcore_source_source_valid1; -wire sdcore_source_source_ready1; -wire sdcore_source_source_first1; -wire sdcore_source_source_last1; -wire [7:0] sdcore_source_source_payload_data1; -wire sdcore_fifo_sink_valid; -wire sdcore_fifo_sink_ready; -wire sdcore_fifo_sink_first; -wire sdcore_fifo_sink_last; -wire [7:0] sdcore_fifo_sink_payload_data; -wire sdcore_fifo_source_valid; -wire sdcore_fifo_source_ready; -wire sdcore_fifo_source_first; -wire sdcore_fifo_source_last; -wire [7:0] sdcore_fifo_source_payload_data; -wire sdcore_fifo_syncfifo_we; -wire sdcore_fifo_syncfifo_writable; -wire sdcore_fifo_syncfifo_re; -wire sdcore_fifo_syncfifo_readable; -wire [9:0] sdcore_fifo_syncfifo_din; -wire [9:0] sdcore_fifo_syncfifo_dout; -reg [3:0] sdcore_fifo_level = 4'd0; -reg sdcore_fifo_replace = 1'd0; -reg [2:0] sdcore_fifo_produce = 3'd0; -reg [2:0] sdcore_fifo_consume = 3'd0; -reg [2:0] sdcore_fifo_wrport_adr = 3'd0; -wire [9:0] sdcore_fifo_wrport_dat_r; -wire sdcore_fifo_wrport_we; -wire [9:0] sdcore_fifo_wrport_dat_w; -wire sdcore_fifo_do_read; -wire [2:0] sdcore_fifo_rdport_adr; -wire [9:0] sdcore_fifo_rdport_dat_r; -wire [7:0] sdcore_fifo_fifo_in_payload_data; -wire sdcore_fifo_fifo_in_first; -wire sdcore_fifo_fifo_in_last; -wire [7:0] sdcore_fifo_fifo_out_payload_data; -wire sdcore_fifo_fifo_out_first; -wire sdcore_fifo_fifo_out_last; -wire sdcore_fifo_reset; -wire [1:0] sdcore_cmd_type; -reg [2:0] sdcore_cmd_count = 3'd0; -reg sdcore_cmd_done = 1'd0; -reg sdcore_cmd_error = 1'd0; -reg sdcore_cmd_timeout = 1'd0; -wire [1:0] sdcore_data_type; -reg [31:0] sdcore_data_count = 32'd0; -reg sdcore_data_done = 1'd0; -reg sdcore_data_error = 1'd0; -reg sdcore_data_timeout = 1'd0; -wire [5:0] sdcore_cmd; -wire [31:0] interface0_bus_adr; -wire [31:0] interface0_bus_dat_w; -wire [31:0] interface0_bus_dat_r; -wire [3:0] interface0_bus_sel; -wire interface0_bus_cyc; -wire interface0_bus_stb; -wire interface0_bus_ack; -wire interface0_bus_we; -reg [2:0] interface0_bus_cti = 3'd0; -reg [1:0] interface0_bus_bte = 2'd0; -wire interface0_bus_err; -wire sdblock2mem_sink_sink_valid0; -reg sdblock2mem_sink_sink_ready0 = 1'd0; -wire sdblock2mem_sink_sink_first; -wire sdblock2mem_sink_sink_last0; -wire [7:0] sdblock2mem_sink_sink_payload_data0; -reg sdblock2mem_irq = 1'd0; -reg sdblock2mem_fifo_sink_valid = 1'd0; -wire sdblock2mem_fifo_sink_ready; -reg sdblock2mem_fifo_sink_first = 1'd0; -reg sdblock2mem_fifo_sink_last = 1'd0; -reg [7:0] sdblock2mem_fifo_sink_payload_data = 8'd0; -wire sdblock2mem_fifo_source_valid; -wire sdblock2mem_fifo_source_ready; -wire sdblock2mem_fifo_source_first; -wire sdblock2mem_fifo_source_last; -wire [7:0] sdblock2mem_fifo_source_payload_data; -wire sdblock2mem_fifo_re; -reg sdblock2mem_fifo_readable = 1'd0; -wire sdblock2mem_fifo_syncfifo_we; -wire sdblock2mem_fifo_syncfifo_writable; -wire sdblock2mem_fifo_syncfifo_re; -wire sdblock2mem_fifo_syncfifo_readable; -wire [9:0] sdblock2mem_fifo_syncfifo_din; -wire [9:0] sdblock2mem_fifo_syncfifo_dout; -reg [9:0] sdblock2mem_fifo_level0 = 10'd0; -reg sdblock2mem_fifo_replace = 1'd0; -reg [8:0] sdblock2mem_fifo_produce = 9'd0; -reg [8:0] sdblock2mem_fifo_consume = 9'd0; -reg [8:0] sdblock2mem_fifo_wrport_adr = 9'd0; -wire [9:0] sdblock2mem_fifo_wrport_dat_r; -wire sdblock2mem_fifo_wrport_we; -wire [9:0] sdblock2mem_fifo_wrport_dat_w; -wire sdblock2mem_fifo_do_read; -wire [8:0] sdblock2mem_fifo_rdport_adr; -wire [9:0] sdblock2mem_fifo_rdport_dat_r; -wire sdblock2mem_fifo_rdport_re; -wire [9:0] sdblock2mem_fifo_level1; -wire [7:0] sdblock2mem_fifo_fifo_in_payload_data; -wire sdblock2mem_fifo_fifo_in_first; -wire sdblock2mem_fifo_fifo_in_last; -wire [7:0] sdblock2mem_fifo_fifo_out_payload_data; -wire sdblock2mem_fifo_fifo_out_first; -wire sdblock2mem_fifo_fifo_out_last; -wire sdblock2mem_converter_sink_valid; -wire sdblock2mem_converter_sink_ready; -wire sdblock2mem_converter_sink_first; -wire sdblock2mem_converter_sink_last; -wire [7:0] sdblock2mem_converter_sink_payload_data; -wire sdblock2mem_converter_source_valid; -wire sdblock2mem_converter_source_ready; -reg sdblock2mem_converter_source_first = 1'd0; -reg sdblock2mem_converter_source_last = 1'd0; -reg [31:0] sdblock2mem_converter_source_payload_data = 32'd0; -reg [2:0] sdblock2mem_converter_source_payload_valid_token_count = 3'd0; -reg [1:0] sdblock2mem_converter_demux = 2'd0; -wire sdblock2mem_converter_load_part; -reg sdblock2mem_converter_strobe_all = 1'd0; -wire sdblock2mem_source_source_valid; -wire sdblock2mem_source_source_ready; -wire sdblock2mem_source_source_first; -wire sdblock2mem_source_source_last; -wire [31:0] sdblock2mem_source_source_payload_data; -reg sdblock2mem_sink_sink_valid1 = 1'd0; -wire sdblock2mem_sink_sink_ready1; -reg sdblock2mem_sink_sink_last1 = 1'd0; -reg [31:0] sdblock2mem_sink_sink_payload_address = 32'd0; -reg [31:0] sdblock2mem_sink_sink_payload_data1 = 32'd0; -wire sdblock2mem_wishbonedmawriter_sink_valid; -reg sdblock2mem_wishbonedmawriter_sink_ready = 1'd0; -wire sdblock2mem_wishbonedmawriter_sink_first; -wire sdblock2mem_wishbonedmawriter_sink_last; -wire [31:0] sdblock2mem_wishbonedmawriter_sink_payload_data; -reg [63:0] sdblock2mem_wishbonedmawriter_base_storage = 64'd0; -reg sdblock2mem_wishbonedmawriter_base_re = 1'd0; -reg [31:0] sdblock2mem_wishbonedmawriter_length_storage = 32'd0; -reg sdblock2mem_wishbonedmawriter_length_re = 1'd0; -reg sdblock2mem_wishbonedmawriter_enable_storage = 1'd0; -reg sdblock2mem_wishbonedmawriter_enable_re = 1'd0; -reg sdblock2mem_wishbonedmawriter_done_status = 1'd0; -wire sdblock2mem_wishbonedmawriter_done_we; -reg sdblock2mem_wishbonedmawriter_done_re = 1'd0; -reg sdblock2mem_wishbonedmawriter_loop_storage = 1'd0; -reg sdblock2mem_wishbonedmawriter_loop_re = 1'd0; -wire [31:0] sdblock2mem_wishbonedmawriter_offset_status; -wire sdblock2mem_wishbonedmawriter_offset_we; -reg sdblock2mem_wishbonedmawriter_offset_re = 1'd0; -wire [31:0] sdblock2mem_wishbonedmawriter_base; -reg [31:0] sdblock2mem_wishbonedmawriter_offset = 32'd0; -wire [31:0] sdblock2mem_wishbonedmawriter_length; -wire sdblock2mem_wishbonedmawriter_reset; -wire sdblock2mem_start; -reg sdblock2mem_connect = 1'd0; -reg sdblock2mem_done_d = 1'd0; -reg [31:0] interface1_bus_adr = 32'd0; -reg [31:0] interface1_bus_dat_w = 32'd0; -wire [31:0] interface1_bus_dat_r; -reg [3:0] interface1_bus_sel = 4'd0; -reg interface1_bus_cyc = 1'd0; -reg interface1_bus_stb = 1'd0; -wire interface1_bus_ack; -reg interface1_bus_we = 1'd0; -reg [2:0] interface1_bus_cti = 3'd0; -reg [1:0] interface1_bus_bte = 2'd0; -wire interface1_bus_err; -wire sdmem2block_source_source_valid0; -wire sdmem2block_source_source_ready0; -wire sdmem2block_source_source_first0; -reg sdmem2block_source_source_last0 = 1'd0; -wire [7:0] sdmem2block_source_source_payload_data0; -reg sdmem2block_irq = 1'd0; -reg sdmem2block_dma_sink_valid = 1'd0; -reg sdmem2block_dma_sink_ready = 1'd0; -reg sdmem2block_dma_sink_last = 1'd0; -reg [31:0] sdmem2block_dma_sink_payload_address = 32'd0; -reg sdmem2block_dma_source_valid = 1'd0; -wire sdmem2block_dma_source_ready; -reg sdmem2block_dma_source_first = 1'd0; -reg sdmem2block_dma_source_last = 1'd0; -reg [31:0] sdmem2block_dma_source_payload_data = 32'd0; -reg [31:0] sdmem2block_dma_data = 32'd0; -reg [63:0] sdmem2block_dma_base_storage = 64'd0; -reg sdmem2block_dma_base_re = 1'd0; -reg [31:0] sdmem2block_dma_length_storage = 32'd0; -reg sdmem2block_dma_length_re = 1'd0; -reg sdmem2block_dma_enable_storage = 1'd0; -reg sdmem2block_dma_enable_re = 1'd0; -reg sdmem2block_dma_done_status = 1'd0; -wire sdmem2block_dma_done_we; -reg sdmem2block_dma_done_re = 1'd0; -reg sdmem2block_dma_loop_storage = 1'd0; -reg sdmem2block_dma_loop_re = 1'd0; -wire [31:0] sdmem2block_dma_offset_status; -wire sdmem2block_dma_offset_we; -reg sdmem2block_dma_offset_re = 1'd0; -wire [31:0] sdmem2block_dma_base; -reg [31:0] sdmem2block_dma_offset = 32'd0; -wire [31:0] sdmem2block_dma_length; -wire sdmem2block_dma_reset; -wire sdmem2block_converter_sink_valid; -wire sdmem2block_converter_sink_ready; -wire sdmem2block_converter_sink_first; -wire sdmem2block_converter_sink_last; -wire [31:0] sdmem2block_converter_sink_payload_data; -wire sdmem2block_converter_source_valid; -wire sdmem2block_converter_source_ready; -wire sdmem2block_converter_source_first; -wire sdmem2block_converter_source_last; -reg [7:0] sdmem2block_converter_source_payload_data = 8'd0; -wire sdmem2block_converter_source_payload_valid_token_count; -reg [1:0] sdmem2block_converter_mux = 2'd0; -wire sdmem2block_converter_first; -wire sdmem2block_converter_last; -wire sdmem2block_source_source_valid1; -wire sdmem2block_source_source_ready1; -wire sdmem2block_source_source_first1; -wire sdmem2block_source_source_last1; -wire [7:0] sdmem2block_source_source_payload_data1; -wire sdmem2block_fifo_sink_valid; -wire sdmem2block_fifo_sink_ready; -wire sdmem2block_fifo_sink_first; -wire sdmem2block_fifo_sink_last; -wire [7:0] sdmem2block_fifo_sink_payload_data; -wire sdmem2block_fifo_source_valid; -wire sdmem2block_fifo_source_ready; -wire sdmem2block_fifo_source_first; -wire sdmem2block_fifo_source_last; -wire [7:0] sdmem2block_fifo_source_payload_data; -wire sdmem2block_fifo_re; -reg sdmem2block_fifo_readable = 1'd0; -wire sdmem2block_fifo_syncfifo_we; -wire sdmem2block_fifo_syncfifo_writable; -wire sdmem2block_fifo_syncfifo_re; -wire sdmem2block_fifo_syncfifo_readable; -wire [9:0] sdmem2block_fifo_syncfifo_din; -wire [9:0] sdmem2block_fifo_syncfifo_dout; -reg [9:0] sdmem2block_fifo_level0 = 10'd0; -reg sdmem2block_fifo_replace = 1'd0; -reg [8:0] sdmem2block_fifo_produce = 9'd0; -reg [8:0] sdmem2block_fifo_consume = 9'd0; -reg [8:0] sdmem2block_fifo_wrport_adr = 9'd0; -wire [9:0] sdmem2block_fifo_wrport_dat_r; -wire sdmem2block_fifo_wrport_we; -wire [9:0] sdmem2block_fifo_wrport_dat_w; -wire sdmem2block_fifo_do_read; -wire [8:0] sdmem2block_fifo_rdport_adr; -wire [9:0] sdmem2block_fifo_rdport_dat_r; -wire sdmem2block_fifo_rdport_re; -wire [9:0] sdmem2block_fifo_level1; -wire [7:0] sdmem2block_fifo_fifo_in_payload_data; -wire sdmem2block_fifo_fifo_in_first; -wire sdmem2block_fifo_fifo_in_last; -wire [7:0] sdmem2block_fifo_fifo_out_payload_data; -wire sdmem2block_fifo_fifo_out_first; -wire sdmem2block_fifo_fifo_out_last; -reg [8:0] sdmem2block_count = 9'd0; -reg sdmem2block_done_d = 1'd0; -wire sdirq_irq; -wire card_detect_status1; -reg card_detect_pending = 1'd0; -wire card_detect_trigger; -reg card_detect_clear = 1'd0; -wire block2mem_dma_status; -reg block2mem_dma_pending = 1'd0; -wire block2mem_dma_trigger; -reg block2mem_dma_clear = 1'd0; -wire mem2block_dma_status; -reg mem2block_dma_pending = 1'd0; -wire mem2block_dma_trigger; -reg mem2block_dma_clear = 1'd0; -wire cmd_done_status; -wire cmd_done_pending; -wire cmd_done_trigger; -reg cmd_done_clear = 1'd0; -wire eventmanager_card_detect0; -wire eventmanager_block2mem_dma0; -wire eventmanager_mem2block_dma0; -wire eventmanager_cmd_done0; -reg [3:0] eventmanager_status_status = 4'd0; -wire eventmanager_status_we; -reg eventmanager_status_re = 1'd0; -wire eventmanager_card_detect1; -wire eventmanager_block2mem_dma1; -wire eventmanager_mem2block_dma1; -wire eventmanager_cmd_done1; -reg [3:0] eventmanager_pending_status = 4'd0; -wire eventmanager_pending_we; -reg eventmanager_pending_re = 1'd0; -reg [3:0] eventmanager_pending_r = 4'd0; -wire eventmanager_card_detect2; -wire eventmanager_block2mem_dma2; -wire eventmanager_mem2block_dma2; -wire eventmanager_cmd_done2; -reg [3:0] eventmanager_enable_storage = 4'd0; -reg eventmanager_enable_re = 1'd0; -reg [13:0] litesdcardcore_adr = 14'd0; -reg litesdcardcore_we = 1'd0; -reg [31:0] litesdcardcore_dat_w = 32'd0; -wire [31:0] litesdcardcore_dat_r; -wire [29:0] litesdcardcore_wishbone_adr; -wire [31:0] litesdcardcore_wishbone_dat_w; -reg [31:0] litesdcardcore_wishbone_dat_r = 32'd0; -wire [3:0] litesdcardcore_wishbone_sel; -wire litesdcardcore_wishbone_cyc; -wire litesdcardcore_wishbone_stb; -reg litesdcardcore_wishbone_ack = 1'd0; -wire litesdcardcore_wishbone_we; -wire [2:0] litesdcardcore_wishbone_cti; -wire [1:0] litesdcardcore_wishbone_bte; -reg litesdcardcore_wishbone_err = 1'd0; -wire [29:0] shared_adr; -wire [31:0] shared_dat_w; -reg [31:0] shared_dat_r = 32'd0; -wire [3:0] shared_sel; -wire shared_cyc; -wire shared_stb; -reg shared_ack = 1'd0; -wire shared_we; -wire [2:0] shared_cti; -wire [1:0] shared_bte; -wire shared_err; -wire [1:0] request; -reg grant = 1'd0; -wire slave_sel; -reg slave_sel_r = 1'd0; -reg error = 1'd0; -wire wait_1; -wire done; -reg [19:0] count = 20'd1000000; -wire [13:0] interface0_bank_bus_adr; -wire interface0_bank_bus_we; -wire [31:0] interface0_bank_bus_dat_w; -reg [31:0] interface0_bank_bus_dat_r = 32'd0; -reg csrbank0_reset0_re = 1'd0; -wire [1:0] csrbank0_reset0_r; -reg csrbank0_reset0_we = 1'd0; -wire [1:0] csrbank0_reset0_w; -reg csrbank0_scratch0_re = 1'd0; -wire [31:0] csrbank0_scratch0_r; -reg csrbank0_scratch0_we = 1'd0; -wire [31:0] csrbank0_scratch0_w; -reg csrbank0_bus_errors_re = 1'd0; -wire [31:0] csrbank0_bus_errors_r; -reg csrbank0_bus_errors_we = 1'd0; -wire [31:0] csrbank0_bus_errors_w; -wire csrbank0_sel; -wire [13:0] interface1_bank_bus_adr; -wire interface1_bank_bus_we; -wire [31:0] interface1_bank_bus_dat_w; -reg [31:0] interface1_bank_bus_dat_r = 32'd0; -reg csrbank1_dma_base1_re = 1'd0; -wire [31:0] csrbank1_dma_base1_r; -reg csrbank1_dma_base1_we = 1'd0; -wire [31:0] csrbank1_dma_base1_w; -reg csrbank1_dma_base0_re = 1'd0; -wire [31:0] csrbank1_dma_base0_r; -reg csrbank1_dma_base0_we = 1'd0; -wire [31:0] csrbank1_dma_base0_w; -reg csrbank1_dma_length0_re = 1'd0; -wire [31:0] csrbank1_dma_length0_r; -reg csrbank1_dma_length0_we = 1'd0; -wire [31:0] csrbank1_dma_length0_w; -reg csrbank1_dma_enable0_re = 1'd0; -wire csrbank1_dma_enable0_r; -reg csrbank1_dma_enable0_we = 1'd0; -wire csrbank1_dma_enable0_w; -reg csrbank1_dma_done_re = 1'd0; -wire csrbank1_dma_done_r; -reg csrbank1_dma_done_we = 1'd0; -wire csrbank1_dma_done_w; -reg csrbank1_dma_loop0_re = 1'd0; -wire csrbank1_dma_loop0_r; -reg csrbank1_dma_loop0_we = 1'd0; -wire csrbank1_dma_loop0_w; -reg csrbank1_dma_offset_re = 1'd0; -wire [31:0] csrbank1_dma_offset_r; -reg csrbank1_dma_offset_we = 1'd0; -wire [31:0] csrbank1_dma_offset_w; -wire csrbank1_sel; -wire [13:0] interface2_bank_bus_adr; -wire interface2_bank_bus_we; -wire [31:0] interface2_bank_bus_dat_w; -reg [31:0] interface2_bank_bus_dat_r = 32'd0; -reg csrbank2_cmd_argument0_re = 1'd0; -wire [31:0] csrbank2_cmd_argument0_r; -reg csrbank2_cmd_argument0_we = 1'd0; -wire [31:0] csrbank2_cmd_argument0_w; -reg csrbank2_cmd_command0_re = 1'd0; -wire [13:0] csrbank2_cmd_command0_r; -reg csrbank2_cmd_command0_we = 1'd0; -wire [13:0] csrbank2_cmd_command0_w; -reg csrbank2_cmd_send0_re = 1'd0; -wire csrbank2_cmd_send0_r; -reg csrbank2_cmd_send0_we = 1'd0; -wire csrbank2_cmd_send0_w; -reg csrbank2_cmd_response3_re = 1'd0; -wire [31:0] csrbank2_cmd_response3_r; -reg csrbank2_cmd_response3_we = 1'd0; -wire [31:0] csrbank2_cmd_response3_w; -reg csrbank2_cmd_response2_re = 1'd0; -wire [31:0] csrbank2_cmd_response2_r; -reg csrbank2_cmd_response2_we = 1'd0; -wire [31:0] csrbank2_cmd_response2_w; -reg csrbank2_cmd_response1_re = 1'd0; -wire [31:0] csrbank2_cmd_response1_r; -reg csrbank2_cmd_response1_we = 1'd0; -wire [31:0] csrbank2_cmd_response1_w; -reg csrbank2_cmd_response0_re = 1'd0; -wire [31:0] csrbank2_cmd_response0_r; -reg csrbank2_cmd_response0_we = 1'd0; -wire [31:0] csrbank2_cmd_response0_w; -reg csrbank2_cmd_event_re = 1'd0; -wire [3:0] csrbank2_cmd_event_r; -reg csrbank2_cmd_event_we = 1'd0; -wire [3:0] csrbank2_cmd_event_w; -reg csrbank2_data_event_re = 1'd0; -wire [3:0] csrbank2_data_event_r; -reg csrbank2_data_event_we = 1'd0; -wire [3:0] csrbank2_data_event_w; -reg csrbank2_block_length0_re = 1'd0; -wire [9:0] csrbank2_block_length0_r; -reg csrbank2_block_length0_we = 1'd0; -wire [9:0] csrbank2_block_length0_w; -reg csrbank2_block_count0_re = 1'd0; -wire [31:0] csrbank2_block_count0_r; -reg csrbank2_block_count0_we = 1'd0; -wire [31:0] csrbank2_block_count0_w; -wire csrbank2_sel; -wire [13:0] interface3_bank_bus_adr; -wire interface3_bank_bus_we; -wire [31:0] interface3_bank_bus_dat_w; -reg [31:0] interface3_bank_bus_dat_r = 32'd0; -reg csrbank3_status_re = 1'd0; -wire [3:0] csrbank3_status_r; -reg csrbank3_status_we = 1'd0; -wire [3:0] csrbank3_status_w; -reg csrbank3_pending_re = 1'd0; -wire [3:0] csrbank3_pending_r; -reg csrbank3_pending_we = 1'd0; -wire [3:0] csrbank3_pending_w; -reg csrbank3_enable0_re = 1'd0; -wire [3:0] csrbank3_enable0_r; -reg csrbank3_enable0_we = 1'd0; -wire [3:0] csrbank3_enable0_w; -wire csrbank3_sel; -wire [13:0] interface4_bank_bus_adr; -wire interface4_bank_bus_we; -wire [31:0] interface4_bank_bus_dat_w; -reg [31:0] interface4_bank_bus_dat_r = 32'd0; -reg csrbank4_dma_base1_re = 1'd0; -wire [31:0] csrbank4_dma_base1_r; -reg csrbank4_dma_base1_we = 1'd0; -wire [31:0] csrbank4_dma_base1_w; -reg csrbank4_dma_base0_re = 1'd0; -wire [31:0] csrbank4_dma_base0_r; -reg csrbank4_dma_base0_we = 1'd0; -wire [31:0] csrbank4_dma_base0_w; -reg csrbank4_dma_length0_re = 1'd0; -wire [31:0] csrbank4_dma_length0_r; -reg csrbank4_dma_length0_we = 1'd0; -wire [31:0] csrbank4_dma_length0_w; -reg csrbank4_dma_enable0_re = 1'd0; -wire csrbank4_dma_enable0_r; -reg csrbank4_dma_enable0_we = 1'd0; -wire csrbank4_dma_enable0_w; -reg csrbank4_dma_done_re = 1'd0; -wire csrbank4_dma_done_r; -reg csrbank4_dma_done_we = 1'd0; -wire csrbank4_dma_done_w; -reg csrbank4_dma_loop0_re = 1'd0; -wire csrbank4_dma_loop0_r; -reg csrbank4_dma_loop0_we = 1'd0; -wire csrbank4_dma_loop0_w; -reg csrbank4_dma_offset_re = 1'd0; -wire [31:0] csrbank4_dma_offset_r; -reg csrbank4_dma_offset_we = 1'd0; -wire [31:0] csrbank4_dma_offset_w; -wire csrbank4_sel; -wire [13:0] interface5_bank_bus_adr; -wire interface5_bank_bus_we; -wire [31:0] interface5_bank_bus_dat_w; -reg [31:0] interface5_bank_bus_dat_r = 32'd0; -reg csrbank5_card_detect_re = 1'd0; -wire csrbank5_card_detect_r; -reg csrbank5_card_detect_we = 1'd0; -wire csrbank5_card_detect_w; -reg csrbank5_clocker_divider0_re = 1'd0; -wire [8:0] csrbank5_clocker_divider0_r; -reg csrbank5_clocker_divider0_we = 1'd0; -wire [8:0] csrbank5_clocker_divider0_w; -reg csrbank5_dataw_status_re = 1'd0; -wire [2:0] csrbank5_dataw_status_r; -reg csrbank5_dataw_status_we = 1'd0; -wire [2:0] csrbank5_dataw_status_w; -wire csrbank5_sel; -wire [13:0] csr_interconnect_adr; -wire csr_interconnect_we; -wire [31:0] csr_interconnect_dat_w; -wire [31:0] csr_interconnect_dat_r; -reg litesdcardcore_sdphyinit_state = 1'd0; -reg litesdcardcore_sdphyinit_next_state = 1'd0; -reg [7:0] init_count_sdphyinit_next_value = 8'd0; -reg init_count_sdphyinit_next_value_ce = 1'd0; -reg [1:0] litesdcardcore_sdphycmdw_state = 2'd0; -reg [1:0] litesdcardcore_sdphycmdw_next_state = 2'd0; -reg [7:0] cmdw_count_sdphycmdw_next_value = 8'd0; -reg cmdw_count_sdphycmdw_next_value_ce = 1'd0; -reg [2:0] litesdcardcore_sdphycmdr_state = 3'd0; -reg [2:0] litesdcardcore_sdphycmdr_next_state = 3'd0; -reg [31:0] cmdr_timeout_sdphycmdr_next_value0 = 32'd0; -reg cmdr_timeout_sdphycmdr_next_value_ce0 = 1'd0; -reg [7:0] cmdr_count_sdphycmdr_next_value1 = 8'd0; -reg cmdr_count_sdphycmdr_next_value_ce1 = 1'd0; -reg cmdr_busy_sdphycmdr_next_value2 = 1'd0; -reg cmdr_busy_sdphycmdr_next_value_ce2 = 1'd0; -reg cmdr_cmdr_reset_sdphycmdr_next_value3 = 1'd0; -reg cmdr_cmdr_reset_sdphycmdr_next_value_ce3 = 1'd0; -reg [2:0] litesdcardcore_sdphydataw_state = 3'd0; -reg [2:0] litesdcardcore_sdphydataw_next_state = 3'd0; -reg dataw_accepted1_sdphydataw_next_value0 = 1'd0; -reg dataw_accepted1_sdphydataw_next_value_ce0 = 1'd0; -reg dataw_crc_error1_sdphydataw_next_value1 = 1'd0; -reg dataw_crc_error1_sdphydataw_next_value_ce1 = 1'd0; -reg dataw_write_error1_sdphydataw_next_value2 = 1'd0; -reg dataw_write_error1_sdphydataw_next_value_ce2 = 1'd0; -reg [7:0] dataw_count_sdphydataw_next_value3 = 8'd0; -reg dataw_count_sdphydataw_next_value_ce3 = 1'd0; -reg [2:0] litesdcardcore_sdphydatar_state = 3'd0; -reg [2:0] litesdcardcore_sdphydatar_next_state = 3'd0; -reg [9:0] datar_count_sdphydatar_next_value0 = 10'd0; -reg datar_count_sdphydatar_next_value_ce0 = 1'd0; -reg [31:0] datar_timeout_sdphydatar_next_value1 = 32'd0; -reg datar_timeout_sdphydatar_next_value_ce1 = 1'd0; -reg datar_datar_reset_sdphydatar_next_value2 = 1'd0; -reg datar_datar_reset_sdphydatar_next_value_ce2 = 1'd0; -reg litesdcardcore_sdcore_crc16inserter_state = 1'd0; -reg litesdcardcore_sdcore_crc16inserter_next_state = 1'd0; -reg [2:0] sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value = 3'd0; -reg sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value_ce = 1'd0; -reg [2:0] litesdcardcore_sdcore_fsm_state = 3'd0; -reg [2:0] litesdcardcore_sdcore_fsm_next_state = 3'd0; -reg sdcore_cmd_done_sdcore_fsm_next_value0 = 1'd0; -reg sdcore_cmd_done_sdcore_fsm_next_value_ce0 = 1'd0; -reg sdcore_data_done_sdcore_fsm_next_value1 = 1'd0; -reg sdcore_data_done_sdcore_fsm_next_value_ce1 = 1'd0; -reg [2:0] sdcore_cmd_count_sdcore_fsm_next_value2 = 3'd0; -reg sdcore_cmd_count_sdcore_fsm_next_value_ce2 = 1'd0; -reg [31:0] sdcore_data_count_sdcore_fsm_next_value3 = 32'd0; -reg sdcore_data_count_sdcore_fsm_next_value_ce3 = 1'd0; -reg sdcore_cmd_error_sdcore_fsm_next_value4 = 1'd0; -reg sdcore_cmd_error_sdcore_fsm_next_value_ce4 = 1'd0; -reg sdcore_cmd_timeout_sdcore_fsm_next_value5 = 1'd0; -reg sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 = 1'd0; -reg sdcore_data_error_sdcore_fsm_next_value6 = 1'd0; -reg sdcore_data_error_sdcore_fsm_next_value_ce6 = 1'd0; -reg sdcore_data_timeout_sdcore_fsm_next_value7 = 1'd0; -reg sdcore_data_timeout_sdcore_fsm_next_value_ce7 = 1'd0; -reg [127:0] sdcore_cmd_response_status_sdcore_fsm_next_value8 = 128'd0; -reg sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 = 1'd0; -reg [1:0] litesdcardcore_sdblock2memdma_state = 2'd0; -reg [1:0] litesdcardcore_sdblock2memdma_next_state = 2'd0; -reg [31:0] sdblock2mem_wishbonedmawriter_offset_next_value = 32'd0; -reg sdblock2mem_wishbonedmawriter_offset_next_value_ce = 1'd0; -reg litesdcardcore_sdmem2blockdma_fsm_state = 1'd0; -reg litesdcardcore_sdmem2blockdma_fsm_next_state = 1'd0; -reg [31:0] sdmem2block_dma_data_sdmem2blockdma_fsm_next_value = 32'd0; -reg sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce = 1'd0; -reg [1:0] litesdcardcore_sdmem2blockdma_resetinserter_state = 2'd0; -reg [1:0] litesdcardcore_sdmem2blockdma_resetinserter_next_state = 2'd0; -reg [31:0] sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value = 32'd0; -reg sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce = 1'd0; -reg litesdcardcore_wishbone2csr_state = 1'd0; -reg litesdcardcore_wishbone2csr_next_state = 1'd0; -reg [31:0] array_muxed0 = 32'd0; -reg [31:0] array_muxed1 = 32'd0; -reg [3:0] array_muxed2 = 4'd0; -reg array_muxed3 = 1'd0; -reg array_muxed4 = 1'd0; -reg array_muxed5 = 1'd0; -reg [2:0] array_muxed6 = 3'd0; -reg [1:0] array_muxed7 = 2'd0; -wire sdrio_clk; -reg xilinxsdrtristateimpl0__o = 1'd0; -reg xilinxsdrtristateimpl0_oe_n = 1'd0; -wire xilinxsdrtristateimpl0__i; -reg xilinxsdrtristateimpl1__o = 1'd0; -reg xilinxsdrtristateimpl1_oe_n = 1'd0; -wire xilinxsdrtristateimpl1__i; -reg xilinxsdrtristateimpl2__o = 1'd0; -reg xilinxsdrtristateimpl2_oe_n = 1'd0; -wire xilinxsdrtristateimpl2__i; -reg xilinxsdrtristateimpl3__o = 1'd0; -reg xilinxsdrtristateimpl3_oe_n = 1'd0; -wire xilinxsdrtristateimpl3__i; -reg xilinxsdrtristateimpl4__o = 1'd0; -reg xilinxsdrtristateimpl4_oe_n = 1'd0; -wire xilinxsdrtristateimpl4__i; -wire sdrio_clk_1; -wire sdrio_clk_2; -wire sdrio_clk_3; -wire sdrio_clk_4; -wire sdrio_clk_5; -wire sdrio_clk_6; -wire sdrio_clk_7; -wire sdrio_clk_8; -wire sdrio_clk_9; -wire sdrio_clk_10; -wire sdrio_clk_11; -wire sdrio_clk_12; -wire sdrio_clk_13; -wire sdrio_clk_14; -wire sdrio_clk_15; - -//------------------------------------------------------------------------------ -// Combinatorial Logic -//------------------------------------------------------------------------------ - -assign wb_ctrl_adr_1 = wb_ctrl_adr; -assign wb_ctrl_dat_w_1 = wb_ctrl_dat_w; -assign wb_ctrl_dat_r = wb_ctrl_dat_r_1; -assign wb_ctrl_sel_1 = wb_ctrl_sel; -assign wb_ctrl_cyc_1 = wb_ctrl_cyc; -assign wb_ctrl_stb_1 = wb_ctrl_stb; -assign wb_ctrl_ack = wb_ctrl_ack_1; -assign wb_ctrl_we_1 = wb_ctrl_we; -assign wb_ctrl_cti_1 = wb_ctrl_cti; -assign wb_ctrl_bte_1 = wb_ctrl_bte; -assign wb_ctrl_err = wb_ctrl_err_1; -assign wb_dma_adr = wb_dma_adr_1; -assign wb_dma_dat_w = wb_dma_dat_w_1; -assign wb_dma_dat_r_1 = wb_dma_dat_r; -assign wb_dma_sel = wb_dma_sel_1; -assign wb_dma_cyc = wb_dma_cyc_1; -assign wb_dma_stb = wb_dma_stb_1; -assign wb_dma_ack_1 = wb_dma_ack; -assign wb_dma_we = wb_dma_we_1; -assign wb_dma_cti = wb_dma_cti_1; -assign wb_dma_bte = wb_dma_bte_1; -assign wb_dma_err_1 = wb_dma_err; -assign sdblock2mem_sink_sink_valid0 = sdcore_source_source_valid0; -assign sdcore_source_source_ready0 = sdblock2mem_sink_sink_ready0; -assign sdblock2mem_sink_sink_first = sdcore_source_source_first0; -assign sdblock2mem_sink_sink_last0 = sdcore_source_source_last0; -assign sdblock2mem_sink_sink_payload_data0 = sdcore_source_source_payload_data0; -assign sdcore_sink_sink_valid0 = sdmem2block_source_source_valid0; -assign sdmem2block_source_source_ready0 = sdcore_sink_sink_ready0; -assign sdcore_sink_sink_first0 = sdmem2block_source_source_first0; -assign sdcore_sink_sink_last0 = sdmem2block_source_source_last0; -assign sdcore_sink_sink_payload_data0 = sdmem2block_source_source_payload_data0; -assign block2mem_dma_trigger = sdblock2mem_irq; -assign mem2block_dma_trigger = sdmem2block_irq; -assign card_detect_trigger = card_detect_irq; -assign cmd_done_trigger = sdcore_csrfield_done0; -assign irq = sdirq_irq; -assign sys_clk = clk; -assign por_clk = clk; -assign sys_rst = int_rst; -assign bus_errors_status = bus_errors; -assign card_detect_status0 = sdcard_cd; -assign sdpads_clk = ((((init_pads_out_payload_clk | cmdw_pads_out_payload_clk) | cmdr_pads_out_payload_clk) | dataw_pads_out_payload_clk) | datar_pads_out_payload_clk); -assign sdpads_cmd_oe = ((((init_pads_out_payload_cmd_oe | cmdw_pads_out_payload_cmd_oe) | cmdr_pads_out_payload_cmd_oe) | dataw_pads_out_payload_cmd_oe) | datar_pads_out_payload_cmd_oe); -assign sdpads_cmd_o = ((((init_pads_out_payload_cmd_o | cmdw_pads_out_payload_cmd_o) | cmdr_pads_out_payload_cmd_o) | dataw_pads_out_payload_cmd_o) | datar_pads_out_payload_cmd_o); -assign sdpads_data_oe = ((((init_pads_out_payload_data_oe | cmdw_pads_out_payload_data_oe) | cmdr_pads_out_payload_data_oe) | dataw_pads_out_payload_data_oe) | datar_pads_out_payload_data_oe); -assign sdpads_data_o = ((((init_pads_out_payload_data_o | cmdw_pads_out_payload_data_o) | cmdr_pads_out_payload_data_o) | dataw_pads_out_payload_data_o) | datar_pads_out_payload_data_o); -assign init_pads_out_ready = clocker_ce; -assign cmdw_pads_out_ready = clocker_ce; -assign cmdr_pads_out_ready = clocker_ce; -assign dataw_pads_out_ready = clocker_ce; -assign datar_pads_out_ready = clocker_ce; -assign clocker_clk_en = sdpads_clk; -assign init_pads_in_valid = sdpads_data_i_ce; -assign init_pads_in_payload_cmd_i = sdpads_cmd_i; -assign init_pads_in_payload_data_i = sdpads_data_i; -assign cmdw_pads_in_valid = sdpads_data_i_ce; -assign cmdw_pads_in_payload_cmd_i = sdpads_cmd_i; -assign cmdw_pads_in_payload_data_i = sdpads_data_i; -assign cmdr_pads_in_pads_in_valid = sdpads_data_i_ce; -assign cmdr_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; -assign cmdr_pads_in_pads_in_payload_data_i = sdpads_data_i; -assign dataw_pads_in_pads_in_valid = sdpads_data_i_ce; -assign dataw_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; -assign dataw_pads_in_pads_in_payload_data_i = sdpads_data_i; -assign datar_pads_in_pads_in_valid = sdpads_data_i_ce; -assign datar_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; -assign datar_pads_in_pads_in_payload_data_i = sdpads_data_i; -assign clocker_stop = (dataw_stop | datar_stop); -always @(*) begin - clocker_clk1 <= 1'd0; - case (clocker_storage) - 3'd4: begin - clocker_clk1 <= clocker_clks[1]; - end - 4'd8: begin - clocker_clk1 <= clocker_clks[2]; - end - 5'd16: begin - clocker_clk1 <= clocker_clks[3]; - end - 6'd32: begin - clocker_clk1 <= clocker_clks[4]; - end - 7'd64: begin - clocker_clk1 <= clocker_clks[5]; - end - 8'd128: begin - clocker_clk1 <= clocker_clks[6]; - end - 9'd256: begin - clocker_clk1 <= clocker_clks[7]; - end - default: begin - clocker_clk1 <= clocker_clks[0]; - end - endcase -end -assign clocker_ce = (clocker_clk1 & (~clocker_clk_d)); -always @(*) begin - clocker_ce_latched <= 1'd0; - if (clocker_clk_d) begin - clocker_ce_latched <= clocker_clk_en; - end else begin - clocker_ce_latched <= clocker_ce_delayed; - end -end -assign clocker_clk0 = ((~clocker_clk1) & clocker_ce_latched); -always @(*) begin - init_pads_out_payload_data_o <= 4'd0; - init_pads_out_payload_clk <= 1'd0; - litesdcardcore_sdphyinit_next_state <= 1'd0; - init_pads_out_payload_cmd_o <= 1'd0; - init_pads_out_payload_cmd_oe <= 1'd0; - init_count_sdphyinit_next_value <= 8'd0; - init_count_sdphyinit_next_value_ce <= 1'd0; - init_pads_out_payload_data_oe <= 1'd0; - litesdcardcore_sdphyinit_next_state <= litesdcardcore_sdphyinit_state; - case (litesdcardcore_sdphyinit_state) - 1'd1: begin - init_pads_out_payload_clk <= 1'd1; - init_pads_out_payload_cmd_oe <= 1'd1; - init_pads_out_payload_cmd_o <= 1'd1; - init_pads_out_payload_data_oe <= 1'd1; - init_pads_out_payload_data_o <= 4'd15; - if (init_pads_out_ready) begin - init_count_sdphyinit_next_value <= (init_count + 1'd1); - init_count_sdphyinit_next_value_ce <= 1'd1; - if ((init_count == 7'd79)) begin - litesdcardcore_sdphyinit_next_state <= 1'd0; - end - end - end - default: begin - init_count_sdphyinit_next_value <= 1'd0; - init_count_sdphyinit_next_value_ce <= 1'd1; - if (init_initialize_re) begin - litesdcardcore_sdphyinit_next_state <= 1'd1; - end - end - endcase -end -always @(*) begin - cmdw_done <= 1'd0; - litesdcardcore_sdphycmdw_next_state <= 2'd0; - cmdw_count_sdphycmdw_next_value <= 8'd0; - cmdw_pads_out_payload_clk <= 1'd0; - cmdw_count_sdphycmdw_next_value_ce <= 1'd0; - cmdw_pads_out_payload_cmd_o <= 1'd0; - cmdw_pads_out_payload_cmd_oe <= 1'd0; - cmdw_sink_ready <= 1'd0; - litesdcardcore_sdphycmdw_next_state <= litesdcardcore_sdphycmdw_state; - case (litesdcardcore_sdphycmdw_state) - 1'd1: begin - cmdw_pads_out_payload_clk <= 1'd1; - cmdw_pads_out_payload_cmd_oe <= 1'd1; - case (cmdw_count) - 1'd0: begin - cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[7]; - end - 1'd1: begin - cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[6]; - end - 2'd2: begin - cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[5]; - end - 2'd3: begin - cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[4]; - end - 3'd4: begin - cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[3]; - end - 3'd5: begin - cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[2]; - end - 3'd6: begin - cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[1]; - end - 3'd7: begin - cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[0]; - end - endcase - if (cmdw_pads_out_ready) begin - cmdw_count_sdphycmdw_next_value <= (cmdw_count + 1'd1); - cmdw_count_sdphycmdw_next_value_ce <= 1'd1; - if ((cmdw_count == 3'd7)) begin - if ((cmdw_sink_last & (cmdw_sink_payload_cmd_type == 1'd0))) begin - litesdcardcore_sdphycmdw_next_state <= 2'd2; - end else begin - cmdw_sink_ready <= 1'd1; - litesdcardcore_sdphycmdw_next_state <= 1'd0; - end - end - end - end - 2'd2: begin - cmdw_pads_out_payload_clk <= 1'd1; - cmdw_pads_out_payload_cmd_oe <= 1'd1; - cmdw_pads_out_payload_cmd_o <= 1'd1; - if (cmdw_pads_out_ready) begin - cmdw_count_sdphycmdw_next_value <= (cmdw_count + 1'd1); - cmdw_count_sdphycmdw_next_value_ce <= 1'd1; - if ((cmdw_count == 3'd7)) begin - cmdw_sink_ready <= 1'd1; - litesdcardcore_sdphycmdw_next_state <= 1'd0; - end - end - end - default: begin - cmdw_count_sdphycmdw_next_value <= 1'd0; - cmdw_count_sdphycmdw_next_value_ce <= 1'd1; - if ((cmdw_sink_valid & cmdw_pads_out_ready)) begin - litesdcardcore_sdphycmdw_next_state <= 1'd1; - end else begin - cmdw_done <= 1'd1; - end - end - endcase -end -assign cmdr_cmdr_pads_in_valid = cmdr_pads_in_pads_in_valid; -assign cmdr_pads_in_pads_in_ready = cmdr_cmdr_pads_in_ready; -assign cmdr_cmdr_pads_in_first = cmdr_pads_in_pads_in_first; -assign cmdr_cmdr_pads_in_last = cmdr_pads_in_pads_in_last; -assign cmdr_cmdr_pads_in_payload_clk = cmdr_pads_in_pads_in_payload_clk; -assign cmdr_cmdr_pads_in_payload_cmd_i = cmdr_pads_in_pads_in_payload_cmd_i; -assign cmdr_cmdr_pads_in_payload_cmd_o = cmdr_pads_in_pads_in_payload_cmd_o; -assign cmdr_cmdr_pads_in_payload_cmd_oe = cmdr_pads_in_pads_in_payload_cmd_oe; -assign cmdr_cmdr_pads_in_payload_data_i = cmdr_pads_in_pads_in_payload_data_i; -assign cmdr_cmdr_pads_in_payload_data_o = cmdr_pads_in_pads_in_payload_data_o; -assign cmdr_cmdr_pads_in_payload_data_oe = cmdr_pads_in_pads_in_payload_data_oe; -assign cmdr_cmdr_pads_in_payload_data_i_ce = cmdr_pads_in_pads_in_payload_data_i_ce; -assign cmdr_cmdr_start = (cmdr_cmdr_pads_in_payload_cmd_i == 1'd0); -assign cmdr_cmdr_converter_sink_valid = (cmdr_cmdr_pads_in_valid & (cmdr_cmdr_start | cmdr_cmdr_run)); -assign cmdr_cmdr_converter_sink_payload_data = cmdr_cmdr_pads_in_payload_cmd_i; -assign cmdr_cmdr_buf_sink_valid = cmdr_cmdr_source_source_valid1; -assign cmdr_cmdr_source_source_ready1 = cmdr_cmdr_buf_sink_ready; -assign cmdr_cmdr_buf_sink_first = cmdr_cmdr_source_source_first1; -assign cmdr_cmdr_buf_sink_last = cmdr_cmdr_source_source_last1; -assign cmdr_cmdr_buf_sink_payload_data = cmdr_cmdr_source_source_payload_data1; -assign cmdr_cmdr_source_source_valid0 = cmdr_cmdr_buf_source_valid; -assign cmdr_cmdr_buf_source_ready = cmdr_cmdr_source_source_ready0; -assign cmdr_cmdr_source_source_first0 = cmdr_cmdr_buf_source_first; -assign cmdr_cmdr_source_source_last0 = cmdr_cmdr_buf_source_last; -assign cmdr_cmdr_source_source_payload_data0 = cmdr_cmdr_buf_source_payload_data; -assign cmdr_cmdr_source_source_valid1 = cmdr_cmdr_converter_source_valid; -assign cmdr_cmdr_converter_source_ready = cmdr_cmdr_source_source_ready1; -assign cmdr_cmdr_source_source_first1 = cmdr_cmdr_converter_source_first; -assign cmdr_cmdr_source_source_last1 = cmdr_cmdr_converter_source_last; -assign cmdr_cmdr_source_source_payload_data1 = cmdr_cmdr_converter_source_payload_data; -assign cmdr_cmdr_converter_sink_ready = ((~cmdr_cmdr_converter_strobe_all) | cmdr_cmdr_converter_source_ready); -assign cmdr_cmdr_converter_source_valid = cmdr_cmdr_converter_strobe_all; -assign cmdr_cmdr_converter_load_part = (cmdr_cmdr_converter_sink_valid & cmdr_cmdr_converter_sink_ready); -assign cmdr_cmdr_buf_sink_ready = ((~cmdr_cmdr_buf_source_valid) | cmdr_cmdr_buf_source_ready); -always @(*) begin - litesdcardcore_sdphycmdr_next_state <= 3'd0; - cmdr_timeout_sdphycmdr_next_value0 <= 32'd0; - cmdr_pads_out_payload_clk <= 1'd0; - cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd0; - cmdr_pads_out_payload_cmd_o <= 1'd0; - cmdr_count_sdphycmdr_next_value1 <= 8'd0; - cmdr_pads_out_payload_cmd_oe <= 1'd0; - cmdr_count_sdphycmdr_next_value_ce1 <= 1'd0; - cmdr_cmdr_source_source_ready0 <= 1'd0; - cmdr_busy_sdphycmdr_next_value2 <= 1'd0; - cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd0; - cmdr_sink_ready <= 1'd0; - cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd0; - cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd0; - cmdr_source_valid <= 1'd0; - cmdr_source_last <= 1'd0; - cmdr_source_payload_data <= 8'd0; - cmdr_source_payload_status <= 3'd0; - litesdcardcore_sdphycmdr_next_state <= litesdcardcore_sdphycmdr_state; - case (litesdcardcore_sdphycmdr_state) - 1'd1: begin - cmdr_pads_out_payload_clk <= 1'd1; - cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd0; - cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd1; - if (cmdr_cmdr_source_source_valid0) begin - litesdcardcore_sdphycmdr_next_state <= 2'd2; - end - cmdr_timeout_sdphycmdr_next_value0 <= (cmdr_timeout - 1'd1); - cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; - if ((cmdr_timeout == 1'd0)) begin - litesdcardcore_sdphycmdr_next_state <= 3'd5; - end - end - 2'd2: begin - cmdr_pads_out_payload_clk <= 1'd1; - cmdr_source_valid <= cmdr_cmdr_source_source_valid0; - cmdr_source_payload_status <= 1'd0; - cmdr_source_last <= (cmdr_count == (cmdr_sink_payload_length - 1'd1)); - cmdr_source_payload_data <= cmdr_cmdr_source_source_payload_data0; - if ((cmdr_cmdr_source_source_valid0 & cmdr_source_ready)) begin - cmdr_cmdr_source_source_ready0 <= 1'd1; - cmdr_count_sdphycmdr_next_value1 <= (cmdr_count + 1'd1); - cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; - if (cmdr_source_last) begin - cmdr_sink_ready <= 1'd1; - if ((cmdr_sink_payload_cmd_type == 2'd3)) begin - cmdr_source_valid <= 1'd0; - cmdr_timeout_sdphycmdr_next_value0 <= 27'd100000000; - cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; - litesdcardcore_sdphycmdr_next_state <= 2'd3; - end else begin - if ((cmdr_sink_payload_data_type == 1'd0)) begin - cmdr_count_sdphycmdr_next_value1 <= 1'd0; - cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; - litesdcardcore_sdphycmdr_next_state <= 3'd4; - end else begin - litesdcardcore_sdphycmdr_next_state <= 1'd0; - end - end - end - end - cmdr_timeout_sdphycmdr_next_value0 <= (cmdr_timeout - 1'd1); - cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; - if ((cmdr_timeout == 1'd0)) begin - litesdcardcore_sdphycmdr_next_state <= 3'd5; - end - end - 2'd3: begin - cmdr_pads_out_payload_clk <= 1'd1; - if ((cmdr_pads_in_pads_in_valid & cmdr_pads_in_pads_in_payload_data_i[0])) begin - cmdr_busy_sdphycmdr_next_value2 <= 1'd0; - cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd1; - end - if ((~cmdr_busy)) begin - cmdr_source_valid <= 1'd1; - cmdr_source_last <= 1'd1; - cmdr_source_payload_status <= 1'd0; - if (cmdr_source_ready) begin - cmdr_count_sdphycmdr_next_value1 <= 1'd0; - cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; - litesdcardcore_sdphycmdr_next_state <= 3'd4; - end - end - cmdr_timeout_sdphycmdr_next_value0 <= (cmdr_timeout - 1'd1); - cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; - if ((cmdr_timeout == 1'd0)) begin - litesdcardcore_sdphycmdr_next_state <= 3'd5; - end - end - 3'd4: begin - cmdr_pads_out_payload_clk <= 1'd1; - cmdr_pads_out_payload_cmd_oe <= 1'd1; - cmdr_pads_out_payload_cmd_o <= 1'd1; - if (cmdr_pads_out_ready) begin - cmdr_count_sdphycmdr_next_value1 <= (cmdr_count + 1'd1); - cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; - if ((cmdr_count == 3'd7)) begin - litesdcardcore_sdphycmdr_next_state <= 1'd0; - end - end - end - 3'd5: begin - cmdr_sink_ready <= 1'd1; - cmdr_source_valid <= 1'd1; - cmdr_source_last <= 1'd1; - cmdr_source_payload_status <= 1'd1; - if (cmdr_source_ready) begin - litesdcardcore_sdphycmdr_next_state <= 1'd0; - end - end - default: begin - cmdr_timeout_sdphycmdr_next_value0 <= 27'd100000000; - cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; - cmdr_count_sdphycmdr_next_value1 <= 1'd0; - cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; - cmdr_busy_sdphycmdr_next_value2 <= 1'd1; - cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd1; - if (((cmdr_sink_valid & cmdr_pads_out_ready) & cmdw_done)) begin - cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd1; - cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd1; - litesdcardcore_sdphycmdr_next_state <= 1'd1; - end - end - endcase -end -assign dataw_accepted0 = dataw_accepted1; -assign dataw_crc_error0 = dataw_crc_error1; -assign dataw_write_error0 = dataw_write_error1; -assign dataw_crc_pads_in_valid = dataw_pads_in_pads_in_valid; -assign dataw_crc_pads_in_ready = dataw_pads_in_pads_in_ready; -assign dataw_crc_pads_in_first = dataw_pads_in_pads_in_first; -assign dataw_crc_pads_in_last = dataw_pads_in_pads_in_last; -assign dataw_crc_pads_in_payload_clk = dataw_pads_in_pads_in_payload_clk; -assign dataw_crc_pads_in_payload_cmd_i = dataw_pads_in_pads_in_payload_cmd_i; -assign dataw_crc_pads_in_payload_cmd_o = dataw_pads_in_pads_in_payload_cmd_o; -assign dataw_crc_pads_in_payload_cmd_oe = dataw_pads_in_pads_in_payload_cmd_oe; -assign dataw_crc_pads_in_payload_data_i = dataw_pads_in_pads_in_payload_data_i; -assign dataw_crc_pads_in_payload_data_o = dataw_pads_in_pads_in_payload_data_o; -assign dataw_crc_pads_in_payload_data_oe = dataw_pads_in_pads_in_payload_data_oe; -assign dataw_crc_pads_in_payload_data_i_ce = dataw_pads_in_pads_in_payload_data_i_ce; -assign dataw_crc_start = (dataw_crc_pads_in_payload_data_i[0] == 1'd0); -assign dataw_crc_converter_sink_valid = (dataw_crc_pads_in_valid & dataw_crc_run); -assign dataw_crc_converter_sink_payload_data = dataw_crc_pads_in_payload_data_i[0]; -assign dataw_crc_buf_sink_valid = dataw_crc_source_source_valid1; -assign dataw_crc_source_source_ready1 = dataw_crc_buf_sink_ready; -assign dataw_crc_buf_sink_first = dataw_crc_source_source_first1; -assign dataw_crc_buf_sink_last = dataw_crc_source_source_last1; -assign dataw_crc_buf_sink_payload_data = dataw_crc_source_source_payload_data1; -assign dataw_crc_source_source_valid0 = dataw_crc_buf_source_valid; -assign dataw_crc_buf_source_ready = dataw_crc_source_source_ready0; -assign dataw_crc_source_source_first0 = dataw_crc_buf_source_first; -assign dataw_crc_source_source_last0 = dataw_crc_buf_source_last; -assign dataw_crc_source_source_payload_data0 = dataw_crc_buf_source_payload_data; -assign dataw_crc_source_source_valid1 = dataw_crc_converter_source_valid; -assign dataw_crc_converter_source_ready = dataw_crc_source_source_ready1; -assign dataw_crc_source_source_first1 = dataw_crc_converter_source_first; -assign dataw_crc_source_source_last1 = dataw_crc_converter_source_last; -assign dataw_crc_source_source_payload_data1 = dataw_crc_converter_source_payload_data; -assign dataw_crc_converter_sink_ready = ((~dataw_crc_converter_strobe_all) | dataw_crc_converter_source_ready); -assign dataw_crc_converter_source_valid = dataw_crc_converter_strobe_all; -assign dataw_crc_converter_load_part = (dataw_crc_converter_sink_valid & dataw_crc_converter_sink_ready); -assign dataw_crc_buf_sink_ready = ((~dataw_crc_buf_source_valid) | dataw_crc_buf_source_ready); -always @(*) begin - litesdcardcore_sdphydataw_next_state <= 3'd0; - dataw_accepted1_sdphydataw_next_value0 <= 1'd0; - dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd0; - dataw_pads_out_payload_clk <= 1'd0; - dataw_crc_reset <= 1'd0; - dataw_crc_error1_sdphydataw_next_value1 <= 1'd0; - dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd0; - dataw_pads_out_payload_cmd_o <= 1'd0; - dataw_pads_out_payload_cmd_oe <= 1'd0; - dataw_write_error1_sdphydataw_next_value2 <= 1'd0; - dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd0; - dataw_pads_out_payload_data_o <= 4'd0; - dataw_pads_out_payload_data_oe <= 1'd0; - dataw_count_sdphydataw_next_value3 <= 8'd0; - dataw_count_sdphydataw_next_value_ce3 <= 1'd0; - dataw_sink_ready <= 1'd0; - dataw_stop <= 1'd0; - litesdcardcore_sdphydataw_next_state <= litesdcardcore_sdphydataw_state; - case (litesdcardcore_sdphydataw_state) - 1'd1: begin - dataw_pads_out_payload_clk <= 1'd1; - dataw_pads_out_payload_cmd_oe <= 1'd1; - dataw_pads_out_payload_cmd_o <= 1'd1; - if (dataw_pads_out_ready) begin - dataw_count_sdphydataw_next_value3 <= (dataw_count + 1'd1); - dataw_count_sdphydataw_next_value_ce3 <= 1'd1; - if ((dataw_count == 3'd7)) begin - dataw_count_sdphydataw_next_value3 <= 1'd0; - dataw_count_sdphydataw_next_value_ce3 <= 1'd1; - litesdcardcore_sdphydataw_next_state <= 2'd2; - end - end - end - 2'd2: begin - dataw_pads_out_payload_clk <= 1'd1; - dataw_pads_out_payload_data_oe <= 1'd1; - dataw_pads_out_payload_data_o <= 1'd0; - if (dataw_pads_out_ready) begin - litesdcardcore_sdphydataw_next_state <= 2'd3; - end - end - 2'd3: begin - dataw_stop <= (~dataw_sink_valid); - dataw_pads_out_payload_clk <= 1'd1; - dataw_pads_out_payload_data_oe <= 1'd1; - case (dataw_count) - 1'd0: begin - dataw_pads_out_payload_data_o <= dataw_sink_payload_data[7:4]; - end - 1'd1: begin - dataw_pads_out_payload_data_o <= dataw_sink_payload_data[3:0]; - end - endcase - if (dataw_pads_out_ready) begin - dataw_count_sdphydataw_next_value3 <= (dataw_count + 1'd1); - dataw_count_sdphydataw_next_value_ce3 <= 1'd1; - if ((dataw_count == 1'd1)) begin - dataw_count_sdphydataw_next_value3 <= 1'd0; - dataw_count_sdphydataw_next_value_ce3 <= 1'd1; - if (dataw_sink_last) begin - litesdcardcore_sdphydataw_next_state <= 3'd4; - end else begin - dataw_sink_ready <= 1'd1; - end - end - end - end - 3'd4: begin - dataw_pads_out_payload_clk <= 1'd1; - dataw_pads_out_payload_data_oe <= 1'd1; - dataw_pads_out_payload_data_o <= 4'd15; - if (dataw_pads_out_ready) begin - dataw_crc_reset <= 1'd1; - litesdcardcore_sdphydataw_next_state <= 3'd5; - end - end - 3'd5: begin - dataw_pads_out_payload_clk <= 1'd1; - if (dataw_crc_source_source_valid0) begin - dataw_accepted1_sdphydataw_next_value0 <= (dataw_crc_source_source_payload_data0[7:5] == 2'd2); - dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd1; - dataw_crc_error1_sdphydataw_next_value1 <= (dataw_crc_source_source_payload_data0[7:5] == 3'd5); - dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd1; - dataw_write_error1_sdphydataw_next_value2 <= (dataw_crc_source_source_payload_data0[7:5] == 3'd6); - dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd1; - litesdcardcore_sdphydataw_next_state <= 3'd6; - end - end - 3'd6: begin - dataw_pads_out_payload_clk <= 1'd1; - if ((dataw_pads_in_pads_in_valid & dataw_pads_in_pads_in_payload_data_i[0])) begin - dataw_sink_ready <= 1'd1; - litesdcardcore_sdphydataw_next_state <= 1'd0; - end - end - default: begin - dataw_accepted1_sdphydataw_next_value0 <= 1'd0; - dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd1; - dataw_crc_error1_sdphydataw_next_value1 <= 1'd0; - dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd1; - dataw_write_error1_sdphydataw_next_value2 <= 1'd0; - dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd1; - dataw_count_sdphydataw_next_value3 <= 1'd0; - dataw_count_sdphydataw_next_value_ce3 <= 1'd1; - if ((dataw_sink_valid & dataw_pads_out_ready)) begin - litesdcardcore_sdphydataw_next_state <= 1'd1; - end - end - endcase -end -assign datar_datar_pads_in_valid = datar_pads_in_pads_in_valid; -assign datar_pads_in_pads_in_ready = datar_datar_pads_in_ready; -assign datar_datar_pads_in_first = datar_pads_in_pads_in_first; -assign datar_datar_pads_in_last = datar_pads_in_pads_in_last; -assign datar_datar_pads_in_payload_clk = datar_pads_in_pads_in_payload_clk; -assign datar_datar_pads_in_payload_cmd_i = datar_pads_in_pads_in_payload_cmd_i; -assign datar_datar_pads_in_payload_cmd_o = datar_pads_in_pads_in_payload_cmd_o; -assign datar_datar_pads_in_payload_cmd_oe = datar_pads_in_pads_in_payload_cmd_oe; -assign datar_datar_pads_in_payload_data_i = datar_pads_in_pads_in_payload_data_i; -assign datar_datar_pads_in_payload_data_o = datar_pads_in_pads_in_payload_data_o; -assign datar_datar_pads_in_payload_data_oe = datar_pads_in_pads_in_payload_data_oe; -assign datar_datar_pads_in_payload_data_i_ce = datar_pads_in_pads_in_payload_data_i_ce; -assign datar_datar_start = (datar_datar_pads_in_payload_data_i[3:0] == 1'd0); -assign datar_datar_converter_sink_valid = (datar_datar_pads_in_valid & datar_datar_run); -assign datar_datar_converter_sink_payload_data = datar_datar_pads_in_payload_data_i[3:0]; -assign datar_datar_buf_sink_valid = datar_datar_source_source_valid1; -assign datar_datar_source_source_ready1 = datar_datar_buf_sink_ready; -assign datar_datar_buf_sink_first = datar_datar_source_source_first1; -assign datar_datar_buf_sink_last = datar_datar_source_source_last1; -assign datar_datar_buf_sink_payload_data = datar_datar_source_source_payload_data1; -assign datar_datar_source_source_valid0 = datar_datar_buf_source_valid; -assign datar_datar_buf_source_ready = datar_datar_source_source_ready0; -assign datar_datar_source_source_first0 = datar_datar_buf_source_first; -assign datar_datar_source_source_last0 = datar_datar_buf_source_last; -assign datar_datar_source_source_payload_data0 = datar_datar_buf_source_payload_data; -assign datar_datar_source_source_valid1 = datar_datar_converter_source_valid; -assign datar_datar_converter_source_ready = datar_datar_source_source_ready1; -assign datar_datar_source_source_first1 = datar_datar_converter_source_first; -assign datar_datar_source_source_last1 = datar_datar_converter_source_last; -assign datar_datar_source_source_payload_data1 = datar_datar_converter_source_payload_data; -assign datar_datar_converter_sink_ready = ((~datar_datar_converter_strobe_all) | datar_datar_converter_source_ready); -assign datar_datar_converter_source_valid = datar_datar_converter_strobe_all; -assign datar_datar_converter_load_part = (datar_datar_converter_sink_valid & datar_datar_converter_sink_ready); -assign datar_datar_buf_sink_ready = ((~datar_datar_buf_source_valid) | datar_datar_buf_source_ready); -always @(*) begin - datar_source_valid <= 1'd0; - datar_source_first <= 1'd0; - datar_source_last <= 1'd0; - datar_source_payload_data <= 8'd0; - datar_source_payload_status <= 3'd0; - datar_stop <= 1'd0; - litesdcardcore_sdphydatar_next_state <= 3'd0; - datar_count_sdphydatar_next_value0 <= 10'd0; - datar_count_sdphydatar_next_value_ce0 <= 1'd0; - datar_timeout_sdphydatar_next_value1 <= 32'd0; - datar_timeout_sdphydatar_next_value_ce1 <= 1'd0; - datar_datar_reset_sdphydatar_next_value2 <= 1'd0; - datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd0; - datar_pads_out_payload_clk <= 1'd0; - datar_datar_source_source_ready0 <= 1'd0; - datar_sink_ready <= 1'd0; - litesdcardcore_sdphydatar_next_state <= litesdcardcore_sdphydatar_state; - case (litesdcardcore_sdphydatar_state) - 1'd1: begin - datar_pads_out_payload_clk <= 1'd1; - datar_datar_reset_sdphydatar_next_value2 <= 1'd0; - datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd1; - datar_timeout_sdphydatar_next_value1 <= (datar_timeout - 1'd1); - datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; - if (datar_datar_source_source_valid0) begin - litesdcardcore_sdphydatar_next_state <= 2'd2; - end - datar_timeout_sdphydatar_next_value1 <= (datar_timeout - 1'd1); - datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; - if ((datar_timeout == 1'd0)) begin - datar_sink_ready <= 1'd1; - litesdcardcore_sdphydatar_next_state <= 3'd4; - end - end - 2'd2: begin - datar_pads_out_payload_clk <= 1'd1; - datar_source_valid <= datar_datar_source_source_valid0; - datar_source_payload_status <= 1'd0; - datar_source_first <= (datar_count == 1'd0); - datar_source_last <= (datar_count == ((datar_sink_payload_block_length + 4'd8) - 1'd1)); - datar_source_payload_data <= datar_datar_source_source_payload_data0; - if (datar_source_valid) begin - if (datar_source_ready) begin - datar_datar_source_source_ready0 <= 1'd1; - datar_count_sdphydatar_next_value0 <= (datar_count + 1'd1); - datar_count_sdphydatar_next_value_ce0 <= 1'd1; - if (datar_source_last) begin - datar_sink_ready <= 1'd1; - if (datar_sink_last) begin - datar_count_sdphydatar_next_value0 <= 1'd0; - datar_count_sdphydatar_next_value_ce0 <= 1'd1; - litesdcardcore_sdphydatar_next_state <= 2'd3; - end else begin - litesdcardcore_sdphydatar_next_state <= 1'd0; - end - end - end else begin - datar_stop <= 1'd1; - end - end - datar_timeout_sdphydatar_next_value1 <= (datar_timeout - 1'd1); - datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; - if ((datar_timeout == 1'd0)) begin - datar_sink_ready <= 1'd1; - litesdcardcore_sdphydatar_next_state <= 3'd4; - end - end - 2'd3: begin - datar_pads_out_payload_clk <= 1'd1; - if (datar_pads_out_ready) begin - datar_count_sdphydatar_next_value0 <= (datar_count + 1'd1); - datar_count_sdphydatar_next_value_ce0 <= 1'd1; - if ((datar_count == 6'd39)) begin - litesdcardcore_sdphydatar_next_state <= 1'd0; - end - end - end - 3'd4: begin - datar_source_valid <= 1'd1; - datar_source_payload_status <= 1'd1; - datar_source_last <= 1'd1; - if (datar_source_ready) begin - litesdcardcore_sdphydatar_next_state <= 1'd0; - end - end - default: begin - datar_count_sdphydatar_next_value0 <= 1'd0; - datar_count_sdphydatar_next_value_ce0 <= 1'd1; - if ((datar_sink_valid & datar_pads_out_ready)) begin - datar_pads_out_payload_clk <= 1'd1; - datar_timeout_sdphydatar_next_value1 <= 32'd100000000; - datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; - datar_count_sdphydatar_next_value0 <= 1'd0; - datar_count_sdphydatar_next_value_ce0 <= 1'd1; - datar_datar_reset_sdphydatar_next_value2 <= 1'd1; - datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd1; - litesdcardcore_sdphydatar_next_state <= 1'd1; - end - end - endcase -end -assign sdcore_crc16_inserter_sink_valid = sdcore_sink_sink_valid0; -assign sdcore_sink_sink_ready0 = sdcore_crc16_inserter_sink_ready; -assign sdcore_crc16_inserter_sink_first = sdcore_sink_sink_first0; -assign sdcore_crc16_inserter_sink_last = sdcore_sink_sink_last0; -assign sdcore_crc16_inserter_sink_payload_data = sdcore_sink_sink_payload_data0; -assign sdcore_source_source_valid0 = sdcore_source_source_valid1; -assign sdcore_source_source_ready1 = sdcore_source_source_ready0; -assign sdcore_source_source_first0 = sdcore_source_source_first1; -assign sdcore_source_source_last0 = sdcore_source_source_last1; -assign sdcore_source_source_payload_data0 = sdcore_source_source_payload_data1; -assign sdcore_cmd_type = sdcore_csrfield_cmd_type; -assign sdcore_data_type = sdcore_csrfield_data_type; -assign sdcore_cmd = sdcore_csrfield_cmd; -assign sdcore_csrfield_done0 = sdcore_cmd_done; -assign sdcore_csrfield_error0 = sdcore_cmd_error; -assign sdcore_csrfield_timeout0 = sdcore_cmd_timeout; -assign sdcore_csrfield_crc0 = 1'd0; -assign sdcore_csrfield_done1 = sdcore_data_done; -assign sdcore_csrfield_error1 = sdcore_data_error; -assign sdcore_csrfield_timeout1 = sdcore_data_timeout; -assign sdcore_csrfield_crc1 = 1'd0; -assign sdcore_crc7_inserter_din = {1'd0, 1'd1, sdcore_cmd, sdcore_cmd_argument_storage}; -assign sdcore_crc7_inserter_reset = 1'd1; -assign sdcore_crc7_inserter_enable = 1'd1; -assign sdcore_crc7_inserter_reg1 = {sdcore_crc7_inserter_reg0[5], sdcore_crc7_inserter_reg0[4], sdcore_crc7_inserter_reg0[3], (sdcore_crc7_inserter_reg0[2] ^ (sdcore_crc7_inserter_din[39] ^ sdcore_crc7_inserter_reg0[6])), sdcore_crc7_inserter_reg0[1], sdcore_crc7_inserter_reg0[0], (sdcore_crc7_inserter_din[39] ^ sdcore_crc7_inserter_reg0[6])}; -assign sdcore_crc7_inserter_reg2 = {sdcore_crc7_inserter_reg1[5], sdcore_crc7_inserter_reg1[4], sdcore_crc7_inserter_reg1[3], (sdcore_crc7_inserter_reg1[2] ^ (sdcore_crc7_inserter_din[38] ^ sdcore_crc7_inserter_reg1[6])), sdcore_crc7_inserter_reg1[1], sdcore_crc7_inserter_reg1[0], (sdcore_crc7_inserter_din[38] ^ sdcore_crc7_inserter_reg1[6])}; -assign sdcore_crc7_inserter_reg3 = {sdcore_crc7_inserter_reg2[5], sdcore_crc7_inserter_reg2[4], sdcore_crc7_inserter_reg2[3], (sdcore_crc7_inserter_reg2[2] ^ (sdcore_crc7_inserter_din[37] ^ sdcore_crc7_inserter_reg2[6])), sdcore_crc7_inserter_reg2[1], sdcore_crc7_inserter_reg2[0], (sdcore_crc7_inserter_din[37] ^ sdcore_crc7_inserter_reg2[6])}; -assign sdcore_crc7_inserter_reg4 = {sdcore_crc7_inserter_reg3[5], sdcore_crc7_inserter_reg3[4], sdcore_crc7_inserter_reg3[3], (sdcore_crc7_inserter_reg3[2] ^ (sdcore_crc7_inserter_din[36] ^ sdcore_crc7_inserter_reg3[6])), sdcore_crc7_inserter_reg3[1], sdcore_crc7_inserter_reg3[0], (sdcore_crc7_inserter_din[36] ^ sdcore_crc7_inserter_reg3[6])}; -assign sdcore_crc7_inserter_reg5 = {sdcore_crc7_inserter_reg4[5], sdcore_crc7_inserter_reg4[4], sdcore_crc7_inserter_reg4[3], (sdcore_crc7_inserter_reg4[2] ^ (sdcore_crc7_inserter_din[35] ^ sdcore_crc7_inserter_reg4[6])), sdcore_crc7_inserter_reg4[1], sdcore_crc7_inserter_reg4[0], (sdcore_crc7_inserter_din[35] ^ sdcore_crc7_inserter_reg4[6])}; -assign sdcore_crc7_inserter_reg6 = {sdcore_crc7_inserter_reg5[5], sdcore_crc7_inserter_reg5[4], sdcore_crc7_inserter_reg5[3], (sdcore_crc7_inserter_reg5[2] ^ (sdcore_crc7_inserter_din[34] ^ sdcore_crc7_inserter_reg5[6])), sdcore_crc7_inserter_reg5[1], sdcore_crc7_inserter_reg5[0], (sdcore_crc7_inserter_din[34] ^ sdcore_crc7_inserter_reg5[6])}; -assign sdcore_crc7_inserter_reg7 = {sdcore_crc7_inserter_reg6[5], sdcore_crc7_inserter_reg6[4], sdcore_crc7_inserter_reg6[3], (sdcore_crc7_inserter_reg6[2] ^ (sdcore_crc7_inserter_din[33] ^ sdcore_crc7_inserter_reg6[6])), sdcore_crc7_inserter_reg6[1], sdcore_crc7_inserter_reg6[0], (sdcore_crc7_inserter_din[33] ^ sdcore_crc7_inserter_reg6[6])}; -assign sdcore_crc7_inserter_reg8 = {sdcore_crc7_inserter_reg7[5], sdcore_crc7_inserter_reg7[4], sdcore_crc7_inserter_reg7[3], (sdcore_crc7_inserter_reg7[2] ^ (sdcore_crc7_inserter_din[32] ^ sdcore_crc7_inserter_reg7[6])), sdcore_crc7_inserter_reg7[1], sdcore_crc7_inserter_reg7[0], (sdcore_crc7_inserter_din[32] ^ sdcore_crc7_inserter_reg7[6])}; -assign sdcore_crc7_inserter_reg9 = {sdcore_crc7_inserter_reg8[5], sdcore_crc7_inserter_reg8[4], sdcore_crc7_inserter_reg8[3], (sdcore_crc7_inserter_reg8[2] ^ (sdcore_crc7_inserter_din[31] ^ sdcore_crc7_inserter_reg8[6])), sdcore_crc7_inserter_reg8[1], sdcore_crc7_inserter_reg8[0], (sdcore_crc7_inserter_din[31] ^ sdcore_crc7_inserter_reg8[6])}; -assign sdcore_crc7_inserter_reg10 = {sdcore_crc7_inserter_reg9[5], sdcore_crc7_inserter_reg9[4], sdcore_crc7_inserter_reg9[3], (sdcore_crc7_inserter_reg9[2] ^ (sdcore_crc7_inserter_din[30] ^ sdcore_crc7_inserter_reg9[6])), sdcore_crc7_inserter_reg9[1], sdcore_crc7_inserter_reg9[0], (sdcore_crc7_inserter_din[30] ^ sdcore_crc7_inserter_reg9[6])}; -assign sdcore_crc7_inserter_reg11 = {sdcore_crc7_inserter_reg10[5], sdcore_crc7_inserter_reg10[4], sdcore_crc7_inserter_reg10[3], (sdcore_crc7_inserter_reg10[2] ^ (sdcore_crc7_inserter_din[29] ^ sdcore_crc7_inserter_reg10[6])), sdcore_crc7_inserter_reg10[1], sdcore_crc7_inserter_reg10[0], (sdcore_crc7_inserter_din[29] ^ sdcore_crc7_inserter_reg10[6])}; -assign sdcore_crc7_inserter_reg12 = {sdcore_crc7_inserter_reg11[5], sdcore_crc7_inserter_reg11[4], sdcore_crc7_inserter_reg11[3], (sdcore_crc7_inserter_reg11[2] ^ (sdcore_crc7_inserter_din[28] ^ sdcore_crc7_inserter_reg11[6])), sdcore_crc7_inserter_reg11[1], sdcore_crc7_inserter_reg11[0], (sdcore_crc7_inserter_din[28] ^ sdcore_crc7_inserter_reg11[6])}; -assign sdcore_crc7_inserter_reg13 = {sdcore_crc7_inserter_reg12[5], sdcore_crc7_inserter_reg12[4], sdcore_crc7_inserter_reg12[3], (sdcore_crc7_inserter_reg12[2] ^ (sdcore_crc7_inserter_din[27] ^ sdcore_crc7_inserter_reg12[6])), sdcore_crc7_inserter_reg12[1], sdcore_crc7_inserter_reg12[0], (sdcore_crc7_inserter_din[27] ^ sdcore_crc7_inserter_reg12[6])}; -assign sdcore_crc7_inserter_reg14 = {sdcore_crc7_inserter_reg13[5], sdcore_crc7_inserter_reg13[4], sdcore_crc7_inserter_reg13[3], (sdcore_crc7_inserter_reg13[2] ^ (sdcore_crc7_inserter_din[26] ^ sdcore_crc7_inserter_reg13[6])), sdcore_crc7_inserter_reg13[1], sdcore_crc7_inserter_reg13[0], (sdcore_crc7_inserter_din[26] ^ sdcore_crc7_inserter_reg13[6])}; -assign sdcore_crc7_inserter_reg15 = {sdcore_crc7_inserter_reg14[5], sdcore_crc7_inserter_reg14[4], sdcore_crc7_inserter_reg14[3], (sdcore_crc7_inserter_reg14[2] ^ (sdcore_crc7_inserter_din[25] ^ sdcore_crc7_inserter_reg14[6])), sdcore_crc7_inserter_reg14[1], sdcore_crc7_inserter_reg14[0], (sdcore_crc7_inserter_din[25] ^ sdcore_crc7_inserter_reg14[6])}; -assign sdcore_crc7_inserter_reg16 = {sdcore_crc7_inserter_reg15[5], sdcore_crc7_inserter_reg15[4], sdcore_crc7_inserter_reg15[3], (sdcore_crc7_inserter_reg15[2] ^ (sdcore_crc7_inserter_din[24] ^ sdcore_crc7_inserter_reg15[6])), sdcore_crc7_inserter_reg15[1], sdcore_crc7_inserter_reg15[0], (sdcore_crc7_inserter_din[24] ^ sdcore_crc7_inserter_reg15[6])}; -assign sdcore_crc7_inserter_reg17 = {sdcore_crc7_inserter_reg16[5], sdcore_crc7_inserter_reg16[4], sdcore_crc7_inserter_reg16[3], (sdcore_crc7_inserter_reg16[2] ^ (sdcore_crc7_inserter_din[23] ^ sdcore_crc7_inserter_reg16[6])), sdcore_crc7_inserter_reg16[1], sdcore_crc7_inserter_reg16[0], (sdcore_crc7_inserter_din[23] ^ sdcore_crc7_inserter_reg16[6])}; -assign sdcore_crc7_inserter_reg18 = {sdcore_crc7_inserter_reg17[5], sdcore_crc7_inserter_reg17[4], sdcore_crc7_inserter_reg17[3], (sdcore_crc7_inserter_reg17[2] ^ (sdcore_crc7_inserter_din[22] ^ sdcore_crc7_inserter_reg17[6])), sdcore_crc7_inserter_reg17[1], sdcore_crc7_inserter_reg17[0], (sdcore_crc7_inserter_din[22] ^ sdcore_crc7_inserter_reg17[6])}; -assign sdcore_crc7_inserter_reg19 = {sdcore_crc7_inserter_reg18[5], sdcore_crc7_inserter_reg18[4], sdcore_crc7_inserter_reg18[3], (sdcore_crc7_inserter_reg18[2] ^ (sdcore_crc7_inserter_din[21] ^ sdcore_crc7_inserter_reg18[6])), sdcore_crc7_inserter_reg18[1], sdcore_crc7_inserter_reg18[0], (sdcore_crc7_inserter_din[21] ^ sdcore_crc7_inserter_reg18[6])}; -assign sdcore_crc7_inserter_reg20 = {sdcore_crc7_inserter_reg19[5], sdcore_crc7_inserter_reg19[4], sdcore_crc7_inserter_reg19[3], (sdcore_crc7_inserter_reg19[2] ^ (sdcore_crc7_inserter_din[20] ^ sdcore_crc7_inserter_reg19[6])), sdcore_crc7_inserter_reg19[1], sdcore_crc7_inserter_reg19[0], (sdcore_crc7_inserter_din[20] ^ sdcore_crc7_inserter_reg19[6])}; -assign sdcore_crc7_inserter_reg21 = {sdcore_crc7_inserter_reg20[5], sdcore_crc7_inserter_reg20[4], sdcore_crc7_inserter_reg20[3], (sdcore_crc7_inserter_reg20[2] ^ (sdcore_crc7_inserter_din[19] ^ sdcore_crc7_inserter_reg20[6])), sdcore_crc7_inserter_reg20[1], sdcore_crc7_inserter_reg20[0], (sdcore_crc7_inserter_din[19] ^ sdcore_crc7_inserter_reg20[6])}; -assign sdcore_crc7_inserter_reg22 = {sdcore_crc7_inserter_reg21[5], sdcore_crc7_inserter_reg21[4], sdcore_crc7_inserter_reg21[3], (sdcore_crc7_inserter_reg21[2] ^ (sdcore_crc7_inserter_din[18] ^ sdcore_crc7_inserter_reg21[6])), sdcore_crc7_inserter_reg21[1], sdcore_crc7_inserter_reg21[0], (sdcore_crc7_inserter_din[18] ^ sdcore_crc7_inserter_reg21[6])}; -assign sdcore_crc7_inserter_reg23 = {sdcore_crc7_inserter_reg22[5], sdcore_crc7_inserter_reg22[4], sdcore_crc7_inserter_reg22[3], (sdcore_crc7_inserter_reg22[2] ^ (sdcore_crc7_inserter_din[17] ^ sdcore_crc7_inserter_reg22[6])), sdcore_crc7_inserter_reg22[1], sdcore_crc7_inserter_reg22[0], (sdcore_crc7_inserter_din[17] ^ sdcore_crc7_inserter_reg22[6])}; -assign sdcore_crc7_inserter_reg24 = {sdcore_crc7_inserter_reg23[5], sdcore_crc7_inserter_reg23[4], sdcore_crc7_inserter_reg23[3], (sdcore_crc7_inserter_reg23[2] ^ (sdcore_crc7_inserter_din[16] ^ sdcore_crc7_inserter_reg23[6])), sdcore_crc7_inserter_reg23[1], sdcore_crc7_inserter_reg23[0], (sdcore_crc7_inserter_din[16] ^ sdcore_crc7_inserter_reg23[6])}; -assign sdcore_crc7_inserter_reg25 = {sdcore_crc7_inserter_reg24[5], sdcore_crc7_inserter_reg24[4], sdcore_crc7_inserter_reg24[3], (sdcore_crc7_inserter_reg24[2] ^ (sdcore_crc7_inserter_din[15] ^ sdcore_crc7_inserter_reg24[6])), sdcore_crc7_inserter_reg24[1], sdcore_crc7_inserter_reg24[0], (sdcore_crc7_inserter_din[15] ^ sdcore_crc7_inserter_reg24[6])}; -assign sdcore_crc7_inserter_reg26 = {sdcore_crc7_inserter_reg25[5], sdcore_crc7_inserter_reg25[4], sdcore_crc7_inserter_reg25[3], (sdcore_crc7_inserter_reg25[2] ^ (sdcore_crc7_inserter_din[14] ^ sdcore_crc7_inserter_reg25[6])), sdcore_crc7_inserter_reg25[1], sdcore_crc7_inserter_reg25[0], (sdcore_crc7_inserter_din[14] ^ sdcore_crc7_inserter_reg25[6])}; -assign sdcore_crc7_inserter_reg27 = {sdcore_crc7_inserter_reg26[5], sdcore_crc7_inserter_reg26[4], sdcore_crc7_inserter_reg26[3], (sdcore_crc7_inserter_reg26[2] ^ (sdcore_crc7_inserter_din[13] ^ sdcore_crc7_inserter_reg26[6])), sdcore_crc7_inserter_reg26[1], sdcore_crc7_inserter_reg26[0], (sdcore_crc7_inserter_din[13] ^ sdcore_crc7_inserter_reg26[6])}; -assign sdcore_crc7_inserter_reg28 = {sdcore_crc7_inserter_reg27[5], sdcore_crc7_inserter_reg27[4], sdcore_crc7_inserter_reg27[3], (sdcore_crc7_inserter_reg27[2] ^ (sdcore_crc7_inserter_din[12] ^ sdcore_crc7_inserter_reg27[6])), sdcore_crc7_inserter_reg27[1], sdcore_crc7_inserter_reg27[0], (sdcore_crc7_inserter_din[12] ^ sdcore_crc7_inserter_reg27[6])}; -assign sdcore_crc7_inserter_reg29 = {sdcore_crc7_inserter_reg28[5], sdcore_crc7_inserter_reg28[4], sdcore_crc7_inserter_reg28[3], (sdcore_crc7_inserter_reg28[2] ^ (sdcore_crc7_inserter_din[11] ^ sdcore_crc7_inserter_reg28[6])), sdcore_crc7_inserter_reg28[1], sdcore_crc7_inserter_reg28[0], (sdcore_crc7_inserter_din[11] ^ sdcore_crc7_inserter_reg28[6])}; -assign sdcore_crc7_inserter_reg30 = {sdcore_crc7_inserter_reg29[5], sdcore_crc7_inserter_reg29[4], sdcore_crc7_inserter_reg29[3], (sdcore_crc7_inserter_reg29[2] ^ (sdcore_crc7_inserter_din[10] ^ sdcore_crc7_inserter_reg29[6])), sdcore_crc7_inserter_reg29[1], sdcore_crc7_inserter_reg29[0], (sdcore_crc7_inserter_din[10] ^ sdcore_crc7_inserter_reg29[6])}; -assign sdcore_crc7_inserter_reg31 = {sdcore_crc7_inserter_reg30[5], sdcore_crc7_inserter_reg30[4], sdcore_crc7_inserter_reg30[3], (sdcore_crc7_inserter_reg30[2] ^ (sdcore_crc7_inserter_din[9] ^ sdcore_crc7_inserter_reg30[6])), sdcore_crc7_inserter_reg30[1], sdcore_crc7_inserter_reg30[0], (sdcore_crc7_inserter_din[9] ^ sdcore_crc7_inserter_reg30[6])}; -assign sdcore_crc7_inserter_reg32 = {sdcore_crc7_inserter_reg31[5], sdcore_crc7_inserter_reg31[4], sdcore_crc7_inserter_reg31[3], (sdcore_crc7_inserter_reg31[2] ^ (sdcore_crc7_inserter_din[8] ^ sdcore_crc7_inserter_reg31[6])), sdcore_crc7_inserter_reg31[1], sdcore_crc7_inserter_reg31[0], (sdcore_crc7_inserter_din[8] ^ sdcore_crc7_inserter_reg31[6])}; -assign sdcore_crc7_inserter_reg33 = {sdcore_crc7_inserter_reg32[5], sdcore_crc7_inserter_reg32[4], sdcore_crc7_inserter_reg32[3], (sdcore_crc7_inserter_reg32[2] ^ (sdcore_crc7_inserter_din[7] ^ sdcore_crc7_inserter_reg32[6])), sdcore_crc7_inserter_reg32[1], sdcore_crc7_inserter_reg32[0], (sdcore_crc7_inserter_din[7] ^ sdcore_crc7_inserter_reg32[6])}; -assign sdcore_crc7_inserter_reg34 = {sdcore_crc7_inserter_reg33[5], sdcore_crc7_inserter_reg33[4], sdcore_crc7_inserter_reg33[3], (sdcore_crc7_inserter_reg33[2] ^ (sdcore_crc7_inserter_din[6] ^ sdcore_crc7_inserter_reg33[6])), sdcore_crc7_inserter_reg33[1], sdcore_crc7_inserter_reg33[0], (sdcore_crc7_inserter_din[6] ^ sdcore_crc7_inserter_reg33[6])}; -assign sdcore_crc7_inserter_reg35 = {sdcore_crc7_inserter_reg34[5], sdcore_crc7_inserter_reg34[4], sdcore_crc7_inserter_reg34[3], (sdcore_crc7_inserter_reg34[2] ^ (sdcore_crc7_inserter_din[5] ^ sdcore_crc7_inserter_reg34[6])), sdcore_crc7_inserter_reg34[1], sdcore_crc7_inserter_reg34[0], (sdcore_crc7_inserter_din[5] ^ sdcore_crc7_inserter_reg34[6])}; -assign sdcore_crc7_inserter_reg36 = {sdcore_crc7_inserter_reg35[5], sdcore_crc7_inserter_reg35[4], sdcore_crc7_inserter_reg35[3], (sdcore_crc7_inserter_reg35[2] ^ (sdcore_crc7_inserter_din[4] ^ sdcore_crc7_inserter_reg35[6])), sdcore_crc7_inserter_reg35[1], sdcore_crc7_inserter_reg35[0], (sdcore_crc7_inserter_din[4] ^ sdcore_crc7_inserter_reg35[6])}; -assign sdcore_crc7_inserter_reg37 = {sdcore_crc7_inserter_reg36[5], sdcore_crc7_inserter_reg36[4], sdcore_crc7_inserter_reg36[3], (sdcore_crc7_inserter_reg36[2] ^ (sdcore_crc7_inserter_din[3] ^ sdcore_crc7_inserter_reg36[6])), sdcore_crc7_inserter_reg36[1], sdcore_crc7_inserter_reg36[0], (sdcore_crc7_inserter_din[3] ^ sdcore_crc7_inserter_reg36[6])}; -assign sdcore_crc7_inserter_reg38 = {sdcore_crc7_inserter_reg37[5], sdcore_crc7_inserter_reg37[4], sdcore_crc7_inserter_reg37[3], (sdcore_crc7_inserter_reg37[2] ^ (sdcore_crc7_inserter_din[2] ^ sdcore_crc7_inserter_reg37[6])), sdcore_crc7_inserter_reg37[1], sdcore_crc7_inserter_reg37[0], (sdcore_crc7_inserter_din[2] ^ sdcore_crc7_inserter_reg37[6])}; -assign sdcore_crc7_inserter_reg39 = {sdcore_crc7_inserter_reg38[5], sdcore_crc7_inserter_reg38[4], sdcore_crc7_inserter_reg38[3], (sdcore_crc7_inserter_reg38[2] ^ (sdcore_crc7_inserter_din[1] ^ sdcore_crc7_inserter_reg38[6])), sdcore_crc7_inserter_reg38[1], sdcore_crc7_inserter_reg38[0], (sdcore_crc7_inserter_din[1] ^ sdcore_crc7_inserter_reg38[6])}; -assign sdcore_crc7_inserter_reg40 = {sdcore_crc7_inserter_reg39[5], sdcore_crc7_inserter_reg39[4], sdcore_crc7_inserter_reg39[3], (sdcore_crc7_inserter_reg39[2] ^ (sdcore_crc7_inserter_din[0] ^ sdcore_crc7_inserter_reg39[6])), sdcore_crc7_inserter_reg39[1], sdcore_crc7_inserter_reg39[0], (sdcore_crc7_inserter_din[0] ^ sdcore_crc7_inserter_reg39[6])}; -always @(*) begin - sdcore_crc7_inserter_crc <= 7'd0; - if (sdcore_crc7_inserter_enable) begin - sdcore_crc7_inserter_crc <= sdcore_crc7_inserter_reg40; - end else begin - sdcore_crc7_inserter_crc <= sdcore_crc7_inserter_reg0; - end -end -assign sdcore_crc16_inserter_crc0_reset = ((sdcore_crc16_inserter_source_valid & sdcore_crc16_inserter_source_ready) & sdcore_crc16_inserter_source_last); -assign sdcore_crc16_inserter_crc0_enable = (sdcore_crc16_inserter_sink_valid & sdcore_crc16_inserter_sink_ready); -always @(*) begin - sdcore_crc16_inserter_crc0_din <= 2'd0; - sdcore_crc16_inserter_crc0_din[0] <= sdcore_crc16_inserter_sink_payload_data[0]; - sdcore_crc16_inserter_crc0_din[1] <= sdcore_crc16_inserter_sink_payload_data[4]; -end -assign sdcore_crc16_inserter_crc1_reset = ((sdcore_crc16_inserter_source_valid & sdcore_crc16_inserter_source_ready) & sdcore_crc16_inserter_source_last); -assign sdcore_crc16_inserter_crc1_enable = (sdcore_crc16_inserter_sink_valid & sdcore_crc16_inserter_sink_ready); -always @(*) begin - sdcore_crc16_inserter_crc1_din <= 2'd0; - sdcore_crc16_inserter_crc1_din[0] <= sdcore_crc16_inserter_sink_payload_data[1]; - sdcore_crc16_inserter_crc1_din[1] <= sdcore_crc16_inserter_sink_payload_data[5]; -end -assign sdcore_crc16_inserter_crc2_reset = ((sdcore_crc16_inserter_source_valid & sdcore_crc16_inserter_source_ready) & sdcore_crc16_inserter_source_last); -assign sdcore_crc16_inserter_crc2_enable = (sdcore_crc16_inserter_sink_valid & sdcore_crc16_inserter_sink_ready); -always @(*) begin - sdcore_crc16_inserter_crc2_din <= 2'd0; - sdcore_crc16_inserter_crc2_din[0] <= sdcore_crc16_inserter_sink_payload_data[2]; - sdcore_crc16_inserter_crc2_din[1] <= sdcore_crc16_inserter_sink_payload_data[6]; -end -assign sdcore_crc16_inserter_crc3_reset = ((sdcore_crc16_inserter_source_valid & sdcore_crc16_inserter_source_ready) & sdcore_crc16_inserter_source_last); -assign sdcore_crc16_inserter_crc3_enable = (sdcore_crc16_inserter_sink_valid & sdcore_crc16_inserter_sink_ready); -always @(*) begin - sdcore_crc16_inserter_crc3_din <= 2'd0; - sdcore_crc16_inserter_crc3_din[0] <= sdcore_crc16_inserter_sink_payload_data[3]; - sdcore_crc16_inserter_crc3_din[1] <= sdcore_crc16_inserter_sink_payload_data[7]; -end -assign sdcore_crc16_inserter_crc0_reg1 = {sdcore_crc16_inserter_crc0_reg0[14], sdcore_crc16_inserter_crc0_reg0[13], sdcore_crc16_inserter_crc0_reg0[12], (sdcore_crc16_inserter_crc0_reg0[11] ^ (sdcore_crc16_inserter_crc0_din[1] ^ sdcore_crc16_inserter_crc0_reg0[15])), sdcore_crc16_inserter_crc0_reg0[10], sdcore_crc16_inserter_crc0_reg0[9], sdcore_crc16_inserter_crc0_reg0[8], sdcore_crc16_inserter_crc0_reg0[7], sdcore_crc16_inserter_crc0_reg0[6], sdcore_crc16_inserter_crc0_reg0[5], (sdcore_crc16_inserter_crc0_reg0[4] ^ (sdcore_crc16_inserter_crc0_din[1] ^ sdcore_crc16_inserter_crc0_reg0[15])), sdcore_crc16_inserter_crc0_reg0[3], sdcore_crc16_inserter_crc0_reg0[2], sdcore_crc16_inserter_crc0_reg0[1], sdcore_crc16_inserter_crc0_reg0[0], (sdcore_crc16_inserter_crc0_din[1] ^ sdcore_crc16_inserter_crc0_reg0[15])}; -assign sdcore_crc16_inserter_crc0_reg2 = {sdcore_crc16_inserter_crc0_reg1[14], sdcore_crc16_inserter_crc0_reg1[13], sdcore_crc16_inserter_crc0_reg1[12], (sdcore_crc16_inserter_crc0_reg1[11] ^ (sdcore_crc16_inserter_crc0_din[0] ^ sdcore_crc16_inserter_crc0_reg1[15])), sdcore_crc16_inserter_crc0_reg1[10], sdcore_crc16_inserter_crc0_reg1[9], sdcore_crc16_inserter_crc0_reg1[8], sdcore_crc16_inserter_crc0_reg1[7], sdcore_crc16_inserter_crc0_reg1[6], sdcore_crc16_inserter_crc0_reg1[5], (sdcore_crc16_inserter_crc0_reg1[4] ^ (sdcore_crc16_inserter_crc0_din[0] ^ sdcore_crc16_inserter_crc0_reg1[15])), sdcore_crc16_inserter_crc0_reg1[3], sdcore_crc16_inserter_crc0_reg1[2], sdcore_crc16_inserter_crc0_reg1[1], sdcore_crc16_inserter_crc0_reg1[0], (sdcore_crc16_inserter_crc0_din[0] ^ sdcore_crc16_inserter_crc0_reg1[15])}; -always @(*) begin - sdcore_crc16_inserter_crc0_crc <= 16'd0; - if (sdcore_crc16_inserter_crc0_enable) begin - sdcore_crc16_inserter_crc0_crc <= sdcore_crc16_inserter_crc0_reg2; - end else begin - sdcore_crc16_inserter_crc0_crc <= sdcore_crc16_inserter_crc0_reg0; - end -end -assign sdcore_crc16_inserter_crc1_reg1 = {sdcore_crc16_inserter_crc1_reg0[14], sdcore_crc16_inserter_crc1_reg0[13], sdcore_crc16_inserter_crc1_reg0[12], (sdcore_crc16_inserter_crc1_reg0[11] ^ (sdcore_crc16_inserter_crc1_din[1] ^ sdcore_crc16_inserter_crc1_reg0[15])), sdcore_crc16_inserter_crc1_reg0[10], sdcore_crc16_inserter_crc1_reg0[9], sdcore_crc16_inserter_crc1_reg0[8], sdcore_crc16_inserter_crc1_reg0[7], sdcore_crc16_inserter_crc1_reg0[6], sdcore_crc16_inserter_crc1_reg0[5], (sdcore_crc16_inserter_crc1_reg0[4] ^ (sdcore_crc16_inserter_crc1_din[1] ^ sdcore_crc16_inserter_crc1_reg0[15])), sdcore_crc16_inserter_crc1_reg0[3], sdcore_crc16_inserter_crc1_reg0[2], sdcore_crc16_inserter_crc1_reg0[1], sdcore_crc16_inserter_crc1_reg0[0], (sdcore_crc16_inserter_crc1_din[1] ^ sdcore_crc16_inserter_crc1_reg0[15])}; -assign sdcore_crc16_inserter_crc1_reg2 = {sdcore_crc16_inserter_crc1_reg1[14], sdcore_crc16_inserter_crc1_reg1[13], sdcore_crc16_inserter_crc1_reg1[12], (sdcore_crc16_inserter_crc1_reg1[11] ^ (sdcore_crc16_inserter_crc1_din[0] ^ sdcore_crc16_inserter_crc1_reg1[15])), sdcore_crc16_inserter_crc1_reg1[10], sdcore_crc16_inserter_crc1_reg1[9], sdcore_crc16_inserter_crc1_reg1[8], sdcore_crc16_inserter_crc1_reg1[7], sdcore_crc16_inserter_crc1_reg1[6], sdcore_crc16_inserter_crc1_reg1[5], (sdcore_crc16_inserter_crc1_reg1[4] ^ (sdcore_crc16_inserter_crc1_din[0] ^ sdcore_crc16_inserter_crc1_reg1[15])), sdcore_crc16_inserter_crc1_reg1[3], sdcore_crc16_inserter_crc1_reg1[2], sdcore_crc16_inserter_crc1_reg1[1], sdcore_crc16_inserter_crc1_reg1[0], (sdcore_crc16_inserter_crc1_din[0] ^ sdcore_crc16_inserter_crc1_reg1[15])}; -always @(*) begin - sdcore_crc16_inserter_crc1_crc <= 16'd0; - if (sdcore_crc16_inserter_crc1_enable) begin - sdcore_crc16_inserter_crc1_crc <= sdcore_crc16_inserter_crc1_reg2; - end else begin - sdcore_crc16_inserter_crc1_crc <= sdcore_crc16_inserter_crc1_reg0; - end -end -assign sdcore_crc16_inserter_crc2_reg1 = {sdcore_crc16_inserter_crc2_reg0[14], sdcore_crc16_inserter_crc2_reg0[13], sdcore_crc16_inserter_crc2_reg0[12], (sdcore_crc16_inserter_crc2_reg0[11] ^ (sdcore_crc16_inserter_crc2_din[1] ^ sdcore_crc16_inserter_crc2_reg0[15])), sdcore_crc16_inserter_crc2_reg0[10], sdcore_crc16_inserter_crc2_reg0[9], sdcore_crc16_inserter_crc2_reg0[8], sdcore_crc16_inserter_crc2_reg0[7], sdcore_crc16_inserter_crc2_reg0[6], sdcore_crc16_inserter_crc2_reg0[5], (sdcore_crc16_inserter_crc2_reg0[4] ^ (sdcore_crc16_inserter_crc2_din[1] ^ sdcore_crc16_inserter_crc2_reg0[15])), sdcore_crc16_inserter_crc2_reg0[3], sdcore_crc16_inserter_crc2_reg0[2], sdcore_crc16_inserter_crc2_reg0[1], sdcore_crc16_inserter_crc2_reg0[0], (sdcore_crc16_inserter_crc2_din[1] ^ sdcore_crc16_inserter_crc2_reg0[15])}; -assign sdcore_crc16_inserter_crc2_reg2 = {sdcore_crc16_inserter_crc2_reg1[14], sdcore_crc16_inserter_crc2_reg1[13], sdcore_crc16_inserter_crc2_reg1[12], (sdcore_crc16_inserter_crc2_reg1[11] ^ (sdcore_crc16_inserter_crc2_din[0] ^ sdcore_crc16_inserter_crc2_reg1[15])), sdcore_crc16_inserter_crc2_reg1[10], sdcore_crc16_inserter_crc2_reg1[9], sdcore_crc16_inserter_crc2_reg1[8], sdcore_crc16_inserter_crc2_reg1[7], sdcore_crc16_inserter_crc2_reg1[6], sdcore_crc16_inserter_crc2_reg1[5], (sdcore_crc16_inserter_crc2_reg1[4] ^ (sdcore_crc16_inserter_crc2_din[0] ^ sdcore_crc16_inserter_crc2_reg1[15])), sdcore_crc16_inserter_crc2_reg1[3], sdcore_crc16_inserter_crc2_reg1[2], sdcore_crc16_inserter_crc2_reg1[1], sdcore_crc16_inserter_crc2_reg1[0], (sdcore_crc16_inserter_crc2_din[0] ^ sdcore_crc16_inserter_crc2_reg1[15])}; -always @(*) begin - sdcore_crc16_inserter_crc2_crc <= 16'd0; - if (sdcore_crc16_inserter_crc2_enable) begin - sdcore_crc16_inserter_crc2_crc <= sdcore_crc16_inserter_crc2_reg2; - end else begin - sdcore_crc16_inserter_crc2_crc <= sdcore_crc16_inserter_crc2_reg0; - end -end -assign sdcore_crc16_inserter_crc3_reg1 = {sdcore_crc16_inserter_crc3_reg0[14], sdcore_crc16_inserter_crc3_reg0[13], sdcore_crc16_inserter_crc3_reg0[12], (sdcore_crc16_inserter_crc3_reg0[11] ^ (sdcore_crc16_inserter_crc3_din[1] ^ sdcore_crc16_inserter_crc3_reg0[15])), sdcore_crc16_inserter_crc3_reg0[10], sdcore_crc16_inserter_crc3_reg0[9], sdcore_crc16_inserter_crc3_reg0[8], sdcore_crc16_inserter_crc3_reg0[7], sdcore_crc16_inserter_crc3_reg0[6], sdcore_crc16_inserter_crc3_reg0[5], (sdcore_crc16_inserter_crc3_reg0[4] ^ (sdcore_crc16_inserter_crc3_din[1] ^ sdcore_crc16_inserter_crc3_reg0[15])), sdcore_crc16_inserter_crc3_reg0[3], sdcore_crc16_inserter_crc3_reg0[2], sdcore_crc16_inserter_crc3_reg0[1], sdcore_crc16_inserter_crc3_reg0[0], (sdcore_crc16_inserter_crc3_din[1] ^ sdcore_crc16_inserter_crc3_reg0[15])}; -assign sdcore_crc16_inserter_crc3_reg2 = {sdcore_crc16_inserter_crc3_reg1[14], sdcore_crc16_inserter_crc3_reg1[13], sdcore_crc16_inserter_crc3_reg1[12], (sdcore_crc16_inserter_crc3_reg1[11] ^ (sdcore_crc16_inserter_crc3_din[0] ^ sdcore_crc16_inserter_crc3_reg1[15])), sdcore_crc16_inserter_crc3_reg1[10], sdcore_crc16_inserter_crc3_reg1[9], sdcore_crc16_inserter_crc3_reg1[8], sdcore_crc16_inserter_crc3_reg1[7], sdcore_crc16_inserter_crc3_reg1[6], sdcore_crc16_inserter_crc3_reg1[5], (sdcore_crc16_inserter_crc3_reg1[4] ^ (sdcore_crc16_inserter_crc3_din[0] ^ sdcore_crc16_inserter_crc3_reg1[15])), sdcore_crc16_inserter_crc3_reg1[3], sdcore_crc16_inserter_crc3_reg1[2], sdcore_crc16_inserter_crc3_reg1[1], sdcore_crc16_inserter_crc3_reg1[0], (sdcore_crc16_inserter_crc3_din[0] ^ sdcore_crc16_inserter_crc3_reg1[15])}; -always @(*) begin - sdcore_crc16_inserter_crc3_crc <= 16'd0; - if (sdcore_crc16_inserter_crc3_enable) begin - sdcore_crc16_inserter_crc3_crc <= sdcore_crc16_inserter_crc3_reg2; - end else begin - sdcore_crc16_inserter_crc3_crc <= sdcore_crc16_inserter_crc3_reg0; - end -end -always @(*) begin - sdcore_crc16_inserter_sink_ready <= 1'd0; - sdcore_crc16_inserter_source_valid <= 1'd0; - sdcore_crc16_inserter_source_first <= 1'd0; - sdcore_crc16_inserter_source_last <= 1'd0; - litesdcardcore_sdcore_crc16inserter_next_state <= 1'd0; - sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value <= 3'd0; - sdcore_crc16_inserter_source_payload_data <= 8'd0; - sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value_ce <= 1'd0; - litesdcardcore_sdcore_crc16inserter_next_state <= litesdcardcore_sdcore_crc16inserter_state; - case (litesdcardcore_sdcore_crc16inserter_state) - 1'd1: begin - sdcore_crc16_inserter_source_valid <= 1'd1; - sdcore_crc16_inserter_source_last <= (sdcore_crc16_inserter_count == 3'd7); - case (sdcore_crc16_inserter_count) - 1'd0: begin - sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[14]; - sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[14]; - sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[14]; - sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[14]; - sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[15]; - sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[15]; - sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[15]; - sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[15]; - end - 1'd1: begin - sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[12]; - sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[12]; - sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[12]; - sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[12]; - sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[13]; - sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[13]; - sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[13]; - sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[13]; - end - 2'd2: begin - sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[10]; - sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[10]; - sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[10]; - sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[10]; - sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[11]; - sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[11]; - sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[11]; - sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[11]; - end - 2'd3: begin - sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[8]; - sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[8]; - sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[8]; - sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[8]; - sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[9]; - sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[9]; - sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[9]; - sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[9]; - end - 3'd4: begin - sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[6]; - sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[6]; - sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[6]; - sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[6]; - sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[7]; - sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[7]; - sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[7]; - sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[7]; - end - 3'd5: begin - sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[4]; - sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[4]; - sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[4]; - sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[4]; - sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[5]; - sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[5]; - sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[5]; - sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[5]; - end - 3'd6: begin - sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[2]; - sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[2]; - sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[2]; - sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[2]; - sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[3]; - sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[3]; - sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[3]; - sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[3]; - end - 3'd7: begin - sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[0]; - sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[0]; - sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[0]; - sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[0]; - sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[1]; - sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[1]; - sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[1]; - sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[1]; - end - endcase - if ((sdcore_crc16_inserter_source_valid & sdcore_crc16_inserter_source_ready)) begin - sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value <= (sdcore_crc16_inserter_count + 1'd1); - sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value_ce <= 1'd1; - if (sdcore_crc16_inserter_source_last) begin - litesdcardcore_sdcore_crc16inserter_next_state <= 1'd0; - end - end - end - default: begin - sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value <= 1'd0; - sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value_ce <= 1'd1; - sdcore_crc16_inserter_source_valid <= sdcore_crc16_inserter_sink_valid; - sdcore_crc16_inserter_sink_ready <= sdcore_crc16_inserter_source_ready; - sdcore_crc16_inserter_source_first <= sdcore_crc16_inserter_sink_first; - sdcore_crc16_inserter_source_payload_data <= sdcore_crc16_inserter_sink_payload_data; - sdcore_crc16_inserter_source_last <= 1'd0; - if ((sdcore_crc16_inserter_sink_valid & sdcore_crc16_inserter_sink_ready)) begin - if (sdcore_crc16_inserter_sink_last) begin - litesdcardcore_sdcore_crc16inserter_next_state <= 1'd1; - end - end - end - endcase -end -assign sdcore_fifo_sink_valid = sdcore_sink_sink_valid1; -assign sdcore_sink_sink_ready1 = sdcore_fifo_sink_ready; -assign sdcore_fifo_sink_first = sdcore_sink_sink_first1; -assign sdcore_fifo_sink_last = sdcore_sink_sink_last1; -assign sdcore_fifo_sink_payload_data = sdcore_sink_sink_payload_data1; -assign sdcore_source_source_first1 = sdcore_fifo_source_first; -assign sdcore_source_source_last1 = sdcore_fifo_source_last; -assign sdcore_source_source_payload_data1 = sdcore_fifo_source_payload_data; -assign sdcore_source_source_valid1 = (sdcore_fifo_level >= 4'd8); -assign sdcore_fifo_source_ready = (sdcore_source_source_valid1 & sdcore_source_source_ready1); -assign sdcore_fifo_reset = ((sdcore_sink_sink_valid1 & sdcore_sink_sink_ready1) & sdcore_sink_sink_last1); -assign sdcore_fifo_syncfifo_din = {sdcore_fifo_fifo_in_last, sdcore_fifo_fifo_in_first, sdcore_fifo_fifo_in_payload_data}; -assign {sdcore_fifo_fifo_out_last, sdcore_fifo_fifo_out_first, sdcore_fifo_fifo_out_payload_data} = sdcore_fifo_syncfifo_dout; -assign sdcore_fifo_sink_ready = sdcore_fifo_syncfifo_writable; -assign sdcore_fifo_syncfifo_we = sdcore_fifo_sink_valid; -assign sdcore_fifo_fifo_in_first = sdcore_fifo_sink_first; -assign sdcore_fifo_fifo_in_last = sdcore_fifo_sink_last; -assign sdcore_fifo_fifo_in_payload_data = sdcore_fifo_sink_payload_data; -assign sdcore_fifo_source_valid = sdcore_fifo_syncfifo_readable; -assign sdcore_fifo_source_first = sdcore_fifo_fifo_out_first; -assign sdcore_fifo_source_last = sdcore_fifo_fifo_out_last; -assign sdcore_fifo_source_payload_data = sdcore_fifo_fifo_out_payload_data; -assign sdcore_fifo_syncfifo_re = sdcore_fifo_source_ready; -always @(*) begin - sdcore_fifo_wrport_adr <= 3'd0; - if (sdcore_fifo_replace) begin - sdcore_fifo_wrport_adr <= (sdcore_fifo_produce - 1'd1); - end else begin - sdcore_fifo_wrport_adr <= sdcore_fifo_produce; - end -end -assign sdcore_fifo_wrport_dat_w = sdcore_fifo_syncfifo_din; -assign sdcore_fifo_wrport_we = (sdcore_fifo_syncfifo_we & (sdcore_fifo_syncfifo_writable | sdcore_fifo_replace)); -assign sdcore_fifo_do_read = (sdcore_fifo_syncfifo_readable & sdcore_fifo_syncfifo_re); -assign sdcore_fifo_rdport_adr = sdcore_fifo_consume; -assign sdcore_fifo_syncfifo_dout = sdcore_fifo_rdport_dat_r; -assign sdcore_fifo_syncfifo_writable = (sdcore_fifo_level != 4'd8); -assign sdcore_fifo_syncfifo_readable = (sdcore_fifo_level != 1'd0); -always @(*) begin - cmdr_sink_valid <= 1'd0; - litesdcardcore_sdcore_fsm_next_state <= 3'd0; - sdcore_cmd_done_sdcore_fsm_next_value0 <= 1'd0; - cmdr_sink_payload_cmd_type <= 2'd0; - sdcore_cmd_done_sdcore_fsm_next_value_ce0 <= 1'd0; - cmdr_sink_payload_data_type <= 2'd0; - cmdr_sink_payload_length <= 8'd0; - sdcore_data_done_sdcore_fsm_next_value1 <= 1'd0; - sdcore_data_done_sdcore_fsm_next_value_ce1 <= 1'd0; - cmdr_source_ready <= 1'd0; - dataw_sink_valid <= 1'd0; - sdcore_cmd_count_sdcore_fsm_next_value2 <= 3'd0; - dataw_sink_first <= 1'd0; - sdcore_cmd_count_sdcore_fsm_next_value_ce2 <= 1'd0; - dataw_sink_last <= 1'd0; - dataw_sink_payload_data <= 8'd0; - sdcore_data_count_sdcore_fsm_next_value3 <= 32'd0; - sdcore_data_count_sdcore_fsm_next_value_ce3 <= 1'd0; - cmdw_sink_valid <= 1'd0; - datar_sink_valid <= 1'd0; - sdcore_cmd_error_sdcore_fsm_next_value4 <= 1'd0; - cmdw_sink_last <= 1'd0; - sdcore_cmd_error_sdcore_fsm_next_value_ce4 <= 1'd0; - cmdw_sink_payload_data <= 8'd0; - datar_sink_payload_block_length <= 10'd0; - cmdw_sink_payload_cmd_type <= 2'd0; - sdcore_cmd_timeout_sdcore_fsm_next_value5 <= 1'd0; - datar_source_ready <= 1'd0; - sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 <= 1'd0; - datar_sink_last <= 1'd0; - sdcore_crc16_inserter_source_ready <= 1'd0; - sdcore_data_error_sdcore_fsm_next_value6 <= 1'd0; - sdcore_data_error_sdcore_fsm_next_value_ce6 <= 1'd0; - sdcore_data_timeout_sdcore_fsm_next_value7 <= 1'd0; - sdcore_data_timeout_sdcore_fsm_next_value_ce7 <= 1'd0; - sdcore_sink_sink_valid1 <= 1'd0; - sdcore_sink_sink_first1 <= 1'd0; - sdcore_sink_sink_last1 <= 1'd0; - sdcore_sink_sink_payload_data1 <= 8'd0; - sdcore_cmd_response_status_sdcore_fsm_next_value8 <= 128'd0; - sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 <= 1'd0; - litesdcardcore_sdcore_fsm_next_state <= litesdcardcore_sdcore_fsm_state; - case (litesdcardcore_sdcore_fsm_state) - 1'd1: begin - cmdw_sink_valid <= 1'd1; - cmdw_sink_last <= (sdcore_cmd_count == 3'd5); - cmdw_sink_payload_cmd_type <= sdcore_cmd_type; - case (sdcore_cmd_count) - 1'd0: begin - cmdw_sink_payload_data <= {1'd0, 1'd1, sdcore_cmd}; - end - 1'd1: begin - cmdw_sink_payload_data <= sdcore_cmd_argument_storage[31:24]; - end - 2'd2: begin - cmdw_sink_payload_data <= sdcore_cmd_argument_storage[23:16]; - end - 2'd3: begin - cmdw_sink_payload_data <= sdcore_cmd_argument_storage[15:8]; - end - 3'd4: begin - cmdw_sink_payload_data <= sdcore_cmd_argument_storage[7:0]; - end - 3'd5: begin - cmdw_sink_payload_data <= {sdcore_crc7_inserter_crc, 1'd1}; - end - endcase - if (cmdw_sink_ready) begin - sdcore_cmd_count_sdcore_fsm_next_value2 <= (sdcore_cmd_count + 1'd1); - sdcore_cmd_count_sdcore_fsm_next_value_ce2 <= 1'd1; - if (cmdw_sink_last) begin - if ((sdcore_cmd_type == 1'd0)) begin - litesdcardcore_sdcore_fsm_next_state <= 1'd0; - end else begin - litesdcardcore_sdcore_fsm_next_state <= 2'd2; - end - end - end - end - 2'd2: begin - cmdr_sink_valid <= 1'd1; - cmdr_sink_payload_cmd_type <= sdcore_cmd_type; - cmdr_sink_payload_data_type <= sdcore_data_type; - if ((sdcore_cmd_type == 2'd2)) begin - cmdr_sink_payload_length <= 5'd18; - end else begin - cmdr_sink_payload_length <= 3'd6; - end - cmdr_source_ready <= 1'd1; - if (cmdr_source_valid) begin - if ((cmdr_source_payload_status == 1'd1)) begin - sdcore_cmd_timeout_sdcore_fsm_next_value5 <= 1'd1; - sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 <= 1'd1; - litesdcardcore_sdcore_fsm_next_state <= 1'd0; - end else begin - if (cmdr_source_last) begin - if ((sdcore_data_type == 2'd2)) begin - litesdcardcore_sdcore_fsm_next_state <= 2'd3; - end else begin - if ((sdcore_data_type == 1'd1)) begin - litesdcardcore_sdcore_fsm_next_state <= 3'd4; - end else begin - litesdcardcore_sdcore_fsm_next_state <= 1'd0; - end - end - end else begin - sdcore_cmd_response_status_sdcore_fsm_next_value8 <= {sdcore_cmd_response_status, cmdr_source_payload_data}; - sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 <= 1'd1; - end - end - end - end - 2'd3: begin - dataw_sink_valid <= sdcore_crc16_inserter_source_valid; - sdcore_crc16_inserter_source_ready <= dataw_sink_ready; - dataw_sink_first <= sdcore_crc16_inserter_source_first; - dataw_sink_last <= sdcore_crc16_inserter_source_last; - dataw_sink_payload_data <= sdcore_crc16_inserter_source_payload_data; - if (((dataw_sink_valid & dataw_sink_ready) & dataw_sink_last)) begin - sdcore_data_count_sdcore_fsm_next_value3 <= (sdcore_data_count + 1'd1); - sdcore_data_count_sdcore_fsm_next_value_ce3 <= 1'd1; - if ((sdcore_data_count == (sdcore_block_count_storage - 1'd1))) begin - litesdcardcore_sdcore_fsm_next_state <= 1'd0; - end - end - datar_source_ready <= 1'd1; - if (datar_source_valid) begin - if ((datar_source_payload_status != 2'd2)) begin - sdcore_data_error_sdcore_fsm_next_value6 <= 1'd1; - sdcore_data_error_sdcore_fsm_next_value_ce6 <= 1'd1; - end - end - end - 3'd4: begin - datar_sink_valid <= 1'd1; - datar_sink_payload_block_length <= sdcore_block_length_storage; - datar_sink_last <= (sdcore_data_count == (sdcore_block_count_storage - 1'd1)); - if (datar_source_valid) begin - if ((datar_source_payload_status == 1'd0)) begin - sdcore_sink_sink_valid1 <= datar_source_valid; - datar_source_ready <= sdcore_sink_sink_ready1; - sdcore_sink_sink_first1 <= datar_source_first; - sdcore_sink_sink_last1 <= datar_source_last; - sdcore_sink_sink_payload_data1 <= datar_source_payload_data; - if ((datar_source_last & datar_source_ready)) begin - sdcore_data_count_sdcore_fsm_next_value3 <= (sdcore_data_count + 1'd1); - sdcore_data_count_sdcore_fsm_next_value_ce3 <= 1'd1; - if ((sdcore_data_count == (sdcore_block_count_storage - 1'd1))) begin - litesdcardcore_sdcore_fsm_next_state <= 1'd0; - end - end - end else begin - if ((datar_source_payload_status == 1'd1)) begin - sdcore_data_timeout_sdcore_fsm_next_value7 <= 1'd1; - sdcore_data_timeout_sdcore_fsm_next_value_ce7 <= 1'd1; - datar_source_ready <= 1'd1; - litesdcardcore_sdcore_fsm_next_state <= 1'd0; - end - end - end - end - default: begin - sdcore_cmd_done_sdcore_fsm_next_value0 <= 1'd1; - sdcore_cmd_done_sdcore_fsm_next_value_ce0 <= 1'd1; - sdcore_data_done_sdcore_fsm_next_value1 <= 1'd1; - sdcore_data_done_sdcore_fsm_next_value_ce1 <= 1'd1; - sdcore_cmd_count_sdcore_fsm_next_value2 <= 1'd0; - sdcore_cmd_count_sdcore_fsm_next_value_ce2 <= 1'd1; - sdcore_data_count_sdcore_fsm_next_value3 <= 1'd0; - sdcore_data_count_sdcore_fsm_next_value_ce3 <= 1'd1; - if (sdcore_cmd_send_re) begin - sdcore_cmd_done_sdcore_fsm_next_value0 <= 1'd0; - sdcore_cmd_done_sdcore_fsm_next_value_ce0 <= 1'd1; - sdcore_cmd_error_sdcore_fsm_next_value4 <= 1'd0; - sdcore_cmd_error_sdcore_fsm_next_value_ce4 <= 1'd1; - sdcore_cmd_timeout_sdcore_fsm_next_value5 <= 1'd0; - sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 <= 1'd1; - sdcore_data_done_sdcore_fsm_next_value1 <= 1'd0; - sdcore_data_done_sdcore_fsm_next_value_ce1 <= 1'd1; - sdcore_data_error_sdcore_fsm_next_value6 <= 1'd0; - sdcore_data_error_sdcore_fsm_next_value_ce6 <= 1'd1; - sdcore_data_timeout_sdcore_fsm_next_value7 <= 1'd0; - sdcore_data_timeout_sdcore_fsm_next_value_ce7 <= 1'd1; - litesdcardcore_sdcore_fsm_next_state <= 1'd1; - end - end - endcase -end -assign sdblock2mem_start = (sdblock2mem_sink_sink_valid0 & sdblock2mem_sink_sink_first); -always @(*) begin - sdblock2mem_fifo_sink_first <= 1'd0; - sdblock2mem_fifo_sink_last <= 1'd0; - sdblock2mem_sink_sink_ready0 <= 1'd0; - sdblock2mem_fifo_sink_payload_data <= 8'd0; - sdblock2mem_fifo_sink_valid <= 1'd0; - if ((sdblock2mem_wishbonedmawriter_enable_storage & (sdblock2mem_start | sdblock2mem_connect))) begin - sdblock2mem_fifo_sink_valid <= sdblock2mem_sink_sink_valid0; - sdblock2mem_sink_sink_ready0 <= sdblock2mem_fifo_sink_ready; - sdblock2mem_fifo_sink_first <= sdblock2mem_sink_sink_first; - sdblock2mem_fifo_sink_last <= sdblock2mem_sink_sink_last0; - sdblock2mem_fifo_sink_payload_data <= sdblock2mem_sink_sink_payload_data0; - end else begin - sdblock2mem_sink_sink_ready0 <= 1'd1; - end -end -assign sdblock2mem_converter_sink_valid = sdblock2mem_fifo_source_valid; -assign sdblock2mem_fifo_source_ready = sdblock2mem_converter_sink_ready; -assign sdblock2mem_converter_sink_first = sdblock2mem_fifo_source_first; -assign sdblock2mem_converter_sink_last = sdblock2mem_fifo_source_last; -assign sdblock2mem_converter_sink_payload_data = sdblock2mem_fifo_source_payload_data; -assign sdblock2mem_wishbonedmawriter_sink_valid = sdblock2mem_source_source_valid; -assign sdblock2mem_source_source_ready = sdblock2mem_wishbonedmawriter_sink_ready; -assign sdblock2mem_wishbonedmawriter_sink_first = sdblock2mem_source_source_first; -assign sdblock2mem_wishbonedmawriter_sink_last = sdblock2mem_source_source_last; -assign sdblock2mem_wishbonedmawriter_sink_payload_data = sdblock2mem_source_source_payload_data; -assign sdblock2mem_fifo_syncfifo_din = {sdblock2mem_fifo_fifo_in_last, sdblock2mem_fifo_fifo_in_first, sdblock2mem_fifo_fifo_in_payload_data}; -assign {sdblock2mem_fifo_fifo_out_last, sdblock2mem_fifo_fifo_out_first, sdblock2mem_fifo_fifo_out_payload_data} = sdblock2mem_fifo_syncfifo_dout; -assign sdblock2mem_fifo_sink_ready = sdblock2mem_fifo_syncfifo_writable; -assign sdblock2mem_fifo_syncfifo_we = sdblock2mem_fifo_sink_valid; -assign sdblock2mem_fifo_fifo_in_first = sdblock2mem_fifo_sink_first; -assign sdblock2mem_fifo_fifo_in_last = sdblock2mem_fifo_sink_last; -assign sdblock2mem_fifo_fifo_in_payload_data = sdblock2mem_fifo_sink_payload_data; -assign sdblock2mem_fifo_source_valid = sdblock2mem_fifo_readable; -assign sdblock2mem_fifo_source_first = sdblock2mem_fifo_fifo_out_first; -assign sdblock2mem_fifo_source_last = sdblock2mem_fifo_fifo_out_last; -assign sdblock2mem_fifo_source_payload_data = sdblock2mem_fifo_fifo_out_payload_data; -assign sdblock2mem_fifo_re = sdblock2mem_fifo_source_ready; -assign sdblock2mem_fifo_syncfifo_re = (sdblock2mem_fifo_syncfifo_readable & ((~sdblock2mem_fifo_readable) | sdblock2mem_fifo_re)); -assign sdblock2mem_fifo_level1 = (sdblock2mem_fifo_level0 + sdblock2mem_fifo_readable); -always @(*) begin - sdblock2mem_fifo_wrport_adr <= 9'd0; - if (sdblock2mem_fifo_replace) begin - sdblock2mem_fifo_wrport_adr <= (sdblock2mem_fifo_produce - 1'd1); - end else begin - sdblock2mem_fifo_wrport_adr <= sdblock2mem_fifo_produce; - end -end -assign sdblock2mem_fifo_wrport_dat_w = sdblock2mem_fifo_syncfifo_din; -assign sdblock2mem_fifo_wrport_we = (sdblock2mem_fifo_syncfifo_we & (sdblock2mem_fifo_syncfifo_writable | sdblock2mem_fifo_replace)); -assign sdblock2mem_fifo_do_read = (sdblock2mem_fifo_syncfifo_readable & sdblock2mem_fifo_syncfifo_re); -assign sdblock2mem_fifo_rdport_adr = sdblock2mem_fifo_consume; -assign sdblock2mem_fifo_syncfifo_dout = sdblock2mem_fifo_rdport_dat_r; -assign sdblock2mem_fifo_rdport_re = sdblock2mem_fifo_do_read; -assign sdblock2mem_fifo_syncfifo_writable = (sdblock2mem_fifo_level0 != 10'd512); -assign sdblock2mem_fifo_syncfifo_readable = (sdblock2mem_fifo_level0 != 1'd0); -assign sdblock2mem_source_source_valid = sdblock2mem_converter_source_valid; -assign sdblock2mem_converter_source_ready = sdblock2mem_source_source_ready; -assign sdblock2mem_source_source_first = sdblock2mem_converter_source_first; -assign sdblock2mem_source_source_last = sdblock2mem_converter_source_last; -assign sdblock2mem_source_source_payload_data = sdblock2mem_converter_source_payload_data; -assign sdblock2mem_converter_sink_ready = ((~sdblock2mem_converter_strobe_all) | sdblock2mem_converter_source_ready); -assign sdblock2mem_converter_source_valid = sdblock2mem_converter_strobe_all; -assign sdblock2mem_converter_load_part = (sdblock2mem_converter_sink_valid & sdblock2mem_converter_sink_ready); -assign interface0_bus_stb = sdblock2mem_sink_sink_valid1; -assign interface0_bus_cyc = sdblock2mem_sink_sink_valid1; -assign interface0_bus_we = 1'd1; -assign interface0_bus_sel = 4'd15; -assign interface0_bus_adr = sdblock2mem_sink_sink_payload_address; -assign interface0_bus_dat_w = {sdblock2mem_sink_sink_payload_data1[7:0], sdblock2mem_sink_sink_payload_data1[15:8], sdblock2mem_sink_sink_payload_data1[23:16], sdblock2mem_sink_sink_payload_data1[31:24]}; -assign sdblock2mem_sink_sink_ready1 = interface0_bus_ack; -assign sdblock2mem_wishbonedmawriter_base = sdblock2mem_wishbonedmawriter_base_storage[63:2]; -assign sdblock2mem_wishbonedmawriter_length = sdblock2mem_wishbonedmawriter_length_storage[31:2]; -assign sdblock2mem_wishbonedmawriter_offset_status = sdblock2mem_wishbonedmawriter_offset; -assign sdblock2mem_wishbonedmawriter_reset = (~sdblock2mem_wishbonedmawriter_enable_storage); -always @(*) begin - sdblock2mem_sink_sink_payload_data1 <= 32'd0; - sdblock2mem_wishbonedmawriter_done_status <= 1'd0; - sdblock2mem_wishbonedmawriter_sink_ready <= 1'd0; - litesdcardcore_sdblock2memdma_next_state <= 2'd0; - sdblock2mem_sink_sink_valid1 <= 1'd0; - sdblock2mem_wishbonedmawriter_offset_next_value <= 32'd0; - sdblock2mem_wishbonedmawriter_offset_next_value_ce <= 1'd0; - sdblock2mem_sink_sink_last1 <= 1'd0; - sdblock2mem_sink_sink_payload_address <= 32'd0; - litesdcardcore_sdblock2memdma_next_state <= litesdcardcore_sdblock2memdma_state; - case (litesdcardcore_sdblock2memdma_state) - 1'd1: begin - sdblock2mem_sink_sink_valid1 <= sdblock2mem_wishbonedmawriter_sink_valid; - sdblock2mem_sink_sink_last1 <= (sdblock2mem_wishbonedmawriter_offset == (sdblock2mem_wishbonedmawriter_length - 1'd1)); - sdblock2mem_sink_sink_payload_address <= (sdblock2mem_wishbonedmawriter_base + sdblock2mem_wishbonedmawriter_offset); - sdblock2mem_sink_sink_payload_data1 <= sdblock2mem_wishbonedmawriter_sink_payload_data; - sdblock2mem_wishbonedmawriter_sink_ready <= sdblock2mem_sink_sink_ready1; - if ((sdblock2mem_wishbonedmawriter_sink_valid & sdblock2mem_wishbonedmawriter_sink_ready)) begin - sdblock2mem_wishbonedmawriter_offset_next_value <= (sdblock2mem_wishbonedmawriter_offset + 1'd1); - sdblock2mem_wishbonedmawriter_offset_next_value_ce <= 1'd1; - if (sdblock2mem_sink_sink_last1) begin - if (sdblock2mem_wishbonedmawriter_loop_storage) begin - sdblock2mem_wishbonedmawriter_offset_next_value <= 1'd0; - sdblock2mem_wishbonedmawriter_offset_next_value_ce <= 1'd1; - end else begin - litesdcardcore_sdblock2memdma_next_state <= 2'd2; - end - end - end - end - 2'd2: begin - sdblock2mem_wishbonedmawriter_done_status <= 1'd1; - end - default: begin - sdblock2mem_wishbonedmawriter_sink_ready <= 1'd1; - sdblock2mem_wishbonedmawriter_offset_next_value <= 1'd0; - sdblock2mem_wishbonedmawriter_offset_next_value_ce <= 1'd1; - litesdcardcore_sdblock2memdma_next_state <= 1'd1; - end - endcase -end -assign sdmem2block_converter_sink_valid = sdmem2block_dma_source_valid; -assign sdmem2block_dma_source_ready = sdmem2block_converter_sink_ready; -assign sdmem2block_converter_sink_first = sdmem2block_dma_source_first; -assign sdmem2block_converter_sink_last = sdmem2block_dma_source_last; -assign sdmem2block_converter_sink_payload_data = sdmem2block_dma_source_payload_data; -assign sdmem2block_fifo_sink_valid = sdmem2block_source_source_valid1; -assign sdmem2block_source_source_ready1 = sdmem2block_fifo_sink_ready; -assign sdmem2block_fifo_sink_first = sdmem2block_source_source_first1; -assign sdmem2block_fifo_sink_last = sdmem2block_source_source_last1; -assign sdmem2block_fifo_sink_payload_data = sdmem2block_source_source_payload_data1; -assign sdmem2block_source_source_valid0 = sdmem2block_fifo_source_valid; -assign sdmem2block_fifo_source_ready = sdmem2block_source_source_ready0; -assign sdmem2block_source_source_first0 = sdmem2block_fifo_source_first; -assign sdmem2block_source_source_payload_data0 = sdmem2block_fifo_source_payload_data; -always @(*) begin - sdmem2block_source_source_last0 <= 1'd0; - sdmem2block_source_source_last0 <= sdmem2block_fifo_source_last; - if ((sdmem2block_count == 9'd511)) begin - sdmem2block_source_source_last0 <= 1'd1; - end -end -assign sdmem2block_dma_base = sdmem2block_dma_base_storage[63:2]; -assign sdmem2block_dma_length = sdmem2block_dma_length_storage[31:2]; -assign sdmem2block_dma_offset_status = sdmem2block_dma_offset; -assign sdmem2block_dma_reset = (~sdmem2block_dma_enable_storage); -always @(*) begin - interface1_bus_sel <= 4'd0; - interface1_bus_cyc <= 1'd0; - interface1_bus_stb <= 1'd0; - sdmem2block_dma_source_valid <= 1'd0; - interface1_bus_we <= 1'd0; - sdmem2block_dma_source_last <= 1'd0; - litesdcardcore_sdmem2blockdma_fsm_next_state <= 1'd0; - sdmem2block_dma_source_payload_data <= 32'd0; - sdmem2block_dma_data_sdmem2blockdma_fsm_next_value <= 32'd0; - sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce <= 1'd0; - interface1_bus_adr <= 32'd0; - sdmem2block_dma_sink_ready <= 1'd0; - litesdcardcore_sdmem2blockdma_fsm_next_state <= litesdcardcore_sdmem2blockdma_fsm_state; - case (litesdcardcore_sdmem2blockdma_fsm_state) - 1'd1: begin - sdmem2block_dma_source_valid <= 1'd1; - sdmem2block_dma_source_last <= sdmem2block_dma_sink_last; - sdmem2block_dma_source_payload_data <= sdmem2block_dma_data; - if (sdmem2block_dma_source_ready) begin - sdmem2block_dma_sink_ready <= 1'd1; - litesdcardcore_sdmem2blockdma_fsm_next_state <= 1'd0; - end - end - default: begin - interface1_bus_stb <= sdmem2block_dma_sink_valid; - interface1_bus_cyc <= sdmem2block_dma_sink_valid; - interface1_bus_we <= 1'd0; - interface1_bus_sel <= 4'd15; - interface1_bus_adr <= sdmem2block_dma_sink_payload_address; - if ((interface1_bus_stb & interface1_bus_ack)) begin - sdmem2block_dma_data_sdmem2blockdma_fsm_next_value <= {interface1_bus_dat_r[7:0], interface1_bus_dat_r[15:8], interface1_bus_dat_r[23:16], interface1_bus_dat_r[31:24]}; - sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce <= 1'd1; - litesdcardcore_sdmem2blockdma_fsm_next_state <= 1'd1; - end - end - endcase -end -always @(*) begin - sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value <= 32'd0; - sdmem2block_dma_sink_last <= 1'd0; - sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce <= 1'd0; - sdmem2block_dma_sink_payload_address <= 32'd0; - sdmem2block_dma_sink_valid <= 1'd0; - sdmem2block_dma_done_status <= 1'd0; - litesdcardcore_sdmem2blockdma_resetinserter_next_state <= 2'd0; - litesdcardcore_sdmem2blockdma_resetinserter_next_state <= litesdcardcore_sdmem2blockdma_resetinserter_state; - case (litesdcardcore_sdmem2blockdma_resetinserter_state) - 1'd1: begin - sdmem2block_dma_sink_valid <= 1'd1; - sdmem2block_dma_sink_last <= (sdmem2block_dma_offset == (sdmem2block_dma_length - 1'd1)); - sdmem2block_dma_sink_payload_address <= (sdmem2block_dma_base + sdmem2block_dma_offset); - if (sdmem2block_dma_sink_ready) begin - sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value <= (sdmem2block_dma_offset + 1'd1); - sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce <= 1'd1; - if (sdmem2block_dma_sink_last) begin - if (sdmem2block_dma_loop_storage) begin - sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value <= 1'd0; - sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce <= 1'd1; - end else begin - litesdcardcore_sdmem2blockdma_resetinserter_next_state <= 2'd2; - end - end - end - end - 2'd2: begin - sdmem2block_dma_done_status <= 1'd1; - end - default: begin - sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value <= 1'd0; - sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce <= 1'd1; - litesdcardcore_sdmem2blockdma_resetinserter_next_state <= 1'd1; - end - endcase -end -assign sdmem2block_source_source_valid1 = sdmem2block_converter_source_valid; -assign sdmem2block_converter_source_ready = sdmem2block_source_source_ready1; -assign sdmem2block_source_source_first1 = sdmem2block_converter_source_first; -assign sdmem2block_source_source_last1 = sdmem2block_converter_source_last; -assign sdmem2block_source_source_payload_data1 = sdmem2block_converter_source_payload_data; -assign sdmem2block_converter_first = (sdmem2block_converter_mux == 1'd0); -assign sdmem2block_converter_last = (sdmem2block_converter_mux == 2'd3); -assign sdmem2block_converter_source_valid = sdmem2block_converter_sink_valid; -assign sdmem2block_converter_source_first = (sdmem2block_converter_sink_first & sdmem2block_converter_first); -assign sdmem2block_converter_source_last = (sdmem2block_converter_sink_last & sdmem2block_converter_last); -assign sdmem2block_converter_sink_ready = (sdmem2block_converter_last & sdmem2block_converter_source_ready); -always @(*) begin - sdmem2block_converter_source_payload_data <= 8'd0; - case (sdmem2block_converter_mux) - 1'd0: begin - sdmem2block_converter_source_payload_data <= sdmem2block_converter_sink_payload_data[31:24]; - end - 1'd1: begin - sdmem2block_converter_source_payload_data <= sdmem2block_converter_sink_payload_data[23:16]; - end - 2'd2: begin - sdmem2block_converter_source_payload_data <= sdmem2block_converter_sink_payload_data[15:8]; - end - default: begin - sdmem2block_converter_source_payload_data <= sdmem2block_converter_sink_payload_data[7:0]; - end - endcase -end -assign sdmem2block_converter_source_payload_valid_token_count = sdmem2block_converter_last; -assign sdmem2block_fifo_syncfifo_din = {sdmem2block_fifo_fifo_in_last, sdmem2block_fifo_fifo_in_first, sdmem2block_fifo_fifo_in_payload_data}; -assign {sdmem2block_fifo_fifo_out_last, sdmem2block_fifo_fifo_out_first, sdmem2block_fifo_fifo_out_payload_data} = sdmem2block_fifo_syncfifo_dout; -assign sdmem2block_fifo_sink_ready = sdmem2block_fifo_syncfifo_writable; -assign sdmem2block_fifo_syncfifo_we = sdmem2block_fifo_sink_valid; -assign sdmem2block_fifo_fifo_in_first = sdmem2block_fifo_sink_first; -assign sdmem2block_fifo_fifo_in_last = sdmem2block_fifo_sink_last; -assign sdmem2block_fifo_fifo_in_payload_data = sdmem2block_fifo_sink_payload_data; -assign sdmem2block_fifo_source_valid = sdmem2block_fifo_readable; -assign sdmem2block_fifo_source_first = sdmem2block_fifo_fifo_out_first; -assign sdmem2block_fifo_source_last = sdmem2block_fifo_fifo_out_last; -assign sdmem2block_fifo_source_payload_data = sdmem2block_fifo_fifo_out_payload_data; -assign sdmem2block_fifo_re = sdmem2block_fifo_source_ready; -assign sdmem2block_fifo_syncfifo_re = (sdmem2block_fifo_syncfifo_readable & ((~sdmem2block_fifo_readable) | sdmem2block_fifo_re)); -assign sdmem2block_fifo_level1 = (sdmem2block_fifo_level0 + sdmem2block_fifo_readable); -always @(*) begin - sdmem2block_fifo_wrport_adr <= 9'd0; - if (sdmem2block_fifo_replace) begin - sdmem2block_fifo_wrport_adr <= (sdmem2block_fifo_produce - 1'd1); - end else begin - sdmem2block_fifo_wrport_adr <= sdmem2block_fifo_produce; - end -end -assign sdmem2block_fifo_wrport_dat_w = sdmem2block_fifo_syncfifo_din; -assign sdmem2block_fifo_wrport_we = (sdmem2block_fifo_syncfifo_we & (sdmem2block_fifo_syncfifo_writable | sdmem2block_fifo_replace)); -assign sdmem2block_fifo_do_read = (sdmem2block_fifo_syncfifo_readable & sdmem2block_fifo_syncfifo_re); -assign sdmem2block_fifo_rdport_adr = sdmem2block_fifo_consume; -assign sdmem2block_fifo_syncfifo_dout = sdmem2block_fifo_rdport_dat_r; -assign sdmem2block_fifo_rdport_re = sdmem2block_fifo_do_read; -assign sdmem2block_fifo_syncfifo_writable = (sdmem2block_fifo_level0 != 10'd512); -assign sdmem2block_fifo_syncfifo_readable = (sdmem2block_fifo_level0 != 1'd0); -assign eventmanager_card_detect0 = card_detect_status1; -assign eventmanager_card_detect1 = card_detect_pending; -always @(*) begin - card_detect_clear <= 1'd0; - if ((eventmanager_pending_re & eventmanager_pending_r[0])) begin - card_detect_clear <= 1'd1; - end -end -assign eventmanager_block2mem_dma0 = block2mem_dma_status; -assign eventmanager_block2mem_dma1 = block2mem_dma_pending; -always @(*) begin - block2mem_dma_clear <= 1'd0; - if ((eventmanager_pending_re & eventmanager_pending_r[1])) begin - block2mem_dma_clear <= 1'd1; - end -end -assign eventmanager_mem2block_dma0 = mem2block_dma_status; -assign eventmanager_mem2block_dma1 = mem2block_dma_pending; -always @(*) begin - mem2block_dma_clear <= 1'd0; - if ((eventmanager_pending_re & eventmanager_pending_r[2])) begin - mem2block_dma_clear <= 1'd1; - end -end -assign eventmanager_cmd_done0 = cmd_done_status; -assign eventmanager_cmd_done1 = cmd_done_pending; -always @(*) begin - cmd_done_clear <= 1'd0; - if ((eventmanager_pending_re & eventmanager_pending_r[3])) begin - cmd_done_clear <= 1'd1; - end -end -assign sdirq_irq = ((((eventmanager_pending_status[0] & eventmanager_enable_storage[0]) | (eventmanager_pending_status[1] & eventmanager_enable_storage[1])) | (eventmanager_pending_status[2] & eventmanager_enable_storage[2])) | (eventmanager_pending_status[3] & eventmanager_enable_storage[3])); -assign card_detect_status1 = 1'd0; -assign block2mem_dma_status = 1'd0; -assign mem2block_dma_status = 1'd0; -assign cmd_done_status = cmd_done_trigger; -assign cmd_done_pending = cmd_done_trigger; -always @(*) begin - litesdcardcore_wishbone_dat_r <= 32'd0; - litesdcardcore_wishbone2csr_next_state <= 1'd0; - litesdcardcore_we <= 1'd0; - litesdcardcore_adr <= 14'd0; - litesdcardcore_wishbone_ack <= 1'd0; - litesdcardcore_dat_w <= 32'd0; - litesdcardcore_wishbone2csr_next_state <= litesdcardcore_wishbone2csr_state; - case (litesdcardcore_wishbone2csr_state) - 1'd1: begin - litesdcardcore_wishbone_ack <= 1'd1; - litesdcardcore_wishbone_dat_r <= litesdcardcore_dat_r; - litesdcardcore_wishbone2csr_next_state <= 1'd0; - end - default: begin - litesdcardcore_dat_w <= litesdcardcore_wishbone_dat_w; - if ((litesdcardcore_wishbone_cyc & litesdcardcore_wishbone_stb)) begin - litesdcardcore_adr <= litesdcardcore_wishbone_adr; - litesdcardcore_we <= (litesdcardcore_wishbone_we & (litesdcardcore_wishbone_sel != 1'd0)); - litesdcardcore_wishbone2csr_next_state <= 1'd1; - end - end - endcase -end -assign litesdcardcore_wishbone_adr = wb_ctrl_adr_1; -assign litesdcardcore_wishbone_dat_w = wb_ctrl_dat_w_1; -assign wb_ctrl_dat_r_1 = litesdcardcore_wishbone_dat_r; -assign litesdcardcore_wishbone_sel = wb_ctrl_sel_1; -assign litesdcardcore_wishbone_cyc = wb_ctrl_cyc_1; -assign litesdcardcore_wishbone_stb = wb_ctrl_stb_1; -assign wb_ctrl_ack_1 = litesdcardcore_wishbone_ack; -assign litesdcardcore_wishbone_we = wb_ctrl_we_1; -assign litesdcardcore_wishbone_cti = wb_ctrl_cti_1; -assign litesdcardcore_wishbone_bte = wb_ctrl_bte_1; -assign wb_ctrl_err_1 = litesdcardcore_wishbone_err; -assign shared_adr = array_muxed0; -assign shared_dat_w = array_muxed1; -assign shared_sel = array_muxed2; -assign shared_cyc = array_muxed3; -assign shared_stb = array_muxed4; -assign shared_we = array_muxed5; -assign shared_cti = array_muxed6; -assign shared_bte = array_muxed7; -assign interface0_bus_dat_r = shared_dat_r; -assign interface1_bus_dat_r = shared_dat_r; -assign interface0_bus_ack = (shared_ack & (grant == 1'd0)); -assign interface1_bus_ack = (shared_ack & (grant == 1'd1)); -assign interface0_bus_err = (shared_err & (grant == 1'd0)); -assign interface1_bus_err = (shared_err & (grant == 1'd1)); -assign request = {interface1_bus_cyc, interface0_bus_cyc}; -assign slave_sel = 1'd1; -assign wb_dma_adr_1 = shared_adr; -assign wb_dma_dat_w_1 = shared_dat_w; -assign wb_dma_sel_1 = shared_sel; -assign wb_dma_stb_1 = shared_stb; -assign wb_dma_we_1 = shared_we; -assign wb_dma_cti_1 = shared_cti; -assign wb_dma_bte_1 = shared_bte; -assign wb_dma_cyc_1 = (shared_cyc & slave_sel); -assign shared_err = wb_dma_err_1; -assign wait_1 = ((shared_stb & shared_cyc) & (~shared_ack)); -always @(*) begin - error <= 1'd0; - shared_dat_r <= 32'd0; - shared_ack <= 1'd0; - shared_ack <= wb_dma_ack_1; - shared_dat_r <= ({32{slave_sel_r}} & wb_dma_dat_r_1); - if (done) begin - shared_dat_r <= 32'd4294967295; - shared_ack <= 1'd1; - error <= 1'd1; - end -end -assign done = (count == 1'd0); -assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); -assign csrbank0_reset0_r = interface0_bank_bus_dat_w[1:0]; -always @(*) begin - csrbank0_reset0_re <= 1'd0; - csrbank0_reset0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_reset0_re <= interface0_bank_bus_we; - csrbank0_reset0_we <= (~interface0_bank_bus_we); - end -end -assign csrbank0_scratch0_r = interface0_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank0_scratch0_we <= 1'd0; - csrbank0_scratch0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_scratch0_re <= interface0_bank_bus_we; - csrbank0_scratch0_we <= (~interface0_bank_bus_we); - end -end -assign csrbank0_bus_errors_r = interface0_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank0_bus_errors_re <= 1'd0; - csrbank0_bus_errors_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 2'd2))) begin - csrbank0_bus_errors_re <= interface0_bank_bus_we; - csrbank0_bus_errors_we <= (~interface0_bank_bus_we); - end -end -always @(*) begin - soc_rst <= 1'd0; - if (reset_re) begin - soc_rst <= reset_storage[0]; - end -end -assign cpu_rst = reset_storage[1]; -assign csrbank0_reset0_w = reset_storage[1:0]; -assign csrbank0_scratch0_w = scratch_storage[31:0]; -assign csrbank0_bus_errors_w = bus_errors_status[31:0]; -assign bus_errors_we = csrbank0_bus_errors_we; -assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); -assign csrbank1_dma_base1_r = interface1_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank1_dma_base1_we <= 1'd0; - csrbank1_dma_base1_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_dma_base1_re <= interface1_bank_bus_we; - csrbank1_dma_base1_we <= (~interface1_bank_bus_we); - end -end -assign csrbank1_dma_base0_r = interface1_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank1_dma_base0_re <= 1'd0; - csrbank1_dma_base0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dma_base0_re <= interface1_bank_bus_we; - csrbank1_dma_base0_we <= (~interface1_bank_bus_we); - end -end -assign csrbank1_dma_length0_r = interface1_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank1_dma_length0_we <= 1'd0; - csrbank1_dma_length0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - csrbank1_dma_length0_re <= interface1_bank_bus_we; - csrbank1_dma_length0_we <= (~interface1_bank_bus_we); - end -end -assign csrbank1_dma_enable0_r = interface1_bank_bus_dat_w[0]; -always @(*) begin - csrbank1_dma_enable0_we <= 1'd0; - csrbank1_dma_enable0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_dma_enable0_re <= interface1_bank_bus_we; - csrbank1_dma_enable0_we <= (~interface1_bank_bus_we); - end -end -assign csrbank1_dma_done_r = interface1_bank_bus_dat_w[0]; -always @(*) begin - csrbank1_dma_done_re <= 1'd0; - csrbank1_dma_done_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - csrbank1_dma_done_re <= interface1_bank_bus_we; - csrbank1_dma_done_we <= (~interface1_bank_bus_we); - end -end -assign csrbank1_dma_loop0_r = interface1_bank_bus_dat_w[0]; -always @(*) begin - csrbank1_dma_loop0_we <= 1'd0; - csrbank1_dma_loop0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - csrbank1_dma_loop0_re <= interface1_bank_bus_we; - csrbank1_dma_loop0_we <= (~interface1_bank_bus_we); - end -end -assign csrbank1_dma_offset_r = interface1_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank1_dma_offset_we <= 1'd0; - csrbank1_dma_offset_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - csrbank1_dma_offset_re <= interface1_bank_bus_we; - csrbank1_dma_offset_we <= (~interface1_bank_bus_we); - end -end -assign csrbank1_dma_base1_w = sdblock2mem_wishbonedmawriter_base_storage[63:32]; -assign csrbank1_dma_base0_w = sdblock2mem_wishbonedmawriter_base_storage[31:0]; -assign csrbank1_dma_length0_w = sdblock2mem_wishbonedmawriter_length_storage[31:0]; -assign csrbank1_dma_enable0_w = sdblock2mem_wishbonedmawriter_enable_storage; -assign csrbank1_dma_done_w = sdblock2mem_wishbonedmawriter_done_status; -assign sdblock2mem_wishbonedmawriter_done_we = csrbank1_dma_done_we; -assign csrbank1_dma_loop0_w = sdblock2mem_wishbonedmawriter_loop_storage; -assign csrbank1_dma_offset_w = sdblock2mem_wishbonedmawriter_offset_status[31:0]; -assign sdblock2mem_wishbonedmawriter_offset_we = csrbank1_dma_offset_we; -assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); -assign csrbank2_cmd_argument0_r = interface2_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank2_cmd_argument0_re <= 1'd0; - csrbank2_cmd_argument0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_cmd_argument0_re <= interface2_bank_bus_we; - csrbank2_cmd_argument0_we <= (~interface2_bank_bus_we); - end -end -assign csrbank2_cmd_command0_r = interface2_bank_bus_dat_w[13:0]; -always @(*) begin - csrbank2_cmd_command0_we <= 1'd0; - csrbank2_cmd_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_cmd_command0_re <= interface2_bank_bus_we; - csrbank2_cmd_command0_we <= (~interface2_bank_bus_we); - end -end -assign csrbank2_cmd_send0_r = interface2_bank_bus_dat_w[0]; -always @(*) begin - csrbank2_cmd_send0_we <= 1'd0; - csrbank2_cmd_send0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - csrbank2_cmd_send0_re <= interface2_bank_bus_we; - csrbank2_cmd_send0_we <= (~interface2_bank_bus_we); - end -end -assign csrbank2_cmd_response3_r = interface2_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank2_cmd_response3_re <= 1'd0; - csrbank2_cmd_response3_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_cmd_response3_re <= interface2_bank_bus_we; - csrbank2_cmd_response3_we <= (~interface2_bank_bus_we); - end -end -assign csrbank2_cmd_response2_r = interface2_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank2_cmd_response2_we <= 1'd0; - csrbank2_cmd_response2_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_cmd_response2_re <= interface2_bank_bus_we; - csrbank2_cmd_response2_we <= (~interface2_bank_bus_we); - end -end -assign csrbank2_cmd_response1_r = interface2_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank2_cmd_response1_we <= 1'd0; - csrbank2_cmd_response1_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_cmd_response1_re <= interface2_bank_bus_we; - csrbank2_cmd_response1_we <= (~interface2_bank_bus_we); - end -end -assign csrbank2_cmd_response0_r = interface2_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank2_cmd_response0_re <= 1'd0; - csrbank2_cmd_response0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_cmd_response0_re <= interface2_bank_bus_we; - csrbank2_cmd_response0_we <= (~interface2_bank_bus_we); - end -end -assign csrbank2_cmd_event_r = interface2_bank_bus_dat_w[3:0]; -always @(*) begin - csrbank2_cmd_event_re <= 1'd0; - csrbank2_cmd_event_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_cmd_event_re <= interface2_bank_bus_we; - csrbank2_cmd_event_we <= (~interface2_bank_bus_we); - end -end -assign csrbank2_data_event_r = interface2_bank_bus_dat_w[3:0]; -always @(*) begin - csrbank2_data_event_we <= 1'd0; - csrbank2_data_event_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - csrbank2_data_event_re <= interface2_bank_bus_we; - csrbank2_data_event_we <= (~interface2_bank_bus_we); - end -end -assign csrbank2_block_length0_r = interface2_bank_bus_dat_w[9:0]; -always @(*) begin - csrbank2_block_length0_we <= 1'd0; - csrbank2_block_length0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_block_length0_re <= interface2_bank_bus_we; - csrbank2_block_length0_we <= (~interface2_bank_bus_we); - end -end -assign csrbank2_block_count0_r = interface2_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank2_block_count0_re <= 1'd0; - csrbank2_block_count0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - csrbank2_block_count0_re <= interface2_bank_bus_we; - csrbank2_block_count0_we <= (~interface2_bank_bus_we); - end -end -assign csrbank2_cmd_argument0_w = sdcore_cmd_argument_storage[31:0]; -assign sdcore_csrfield_cmd_type = sdcore_cmd_command_storage[1:0]; -assign sdcore_csrfield_data_type = sdcore_cmd_command_storage[6:5]; -assign sdcore_csrfield_cmd = sdcore_cmd_command_storage[13:8]; -assign csrbank2_cmd_command0_w = sdcore_cmd_command_storage[13:0]; -assign csrbank2_cmd_send0_w = sdcore_cmd_send_storage; -assign csrbank2_cmd_response3_w = sdcore_cmd_response_status[127:96]; -assign csrbank2_cmd_response2_w = sdcore_cmd_response_status[95:64]; -assign csrbank2_cmd_response1_w = sdcore_cmd_response_status[63:32]; -assign csrbank2_cmd_response0_w = sdcore_cmd_response_status[31:0]; -assign sdcore_cmd_response_we = csrbank2_cmd_response0_we; -always @(*) begin - sdcore_cmd_event_status <= 4'd0; - sdcore_cmd_event_status[0] <= sdcore_csrfield_done0; - sdcore_cmd_event_status[1] <= sdcore_csrfield_error0; - sdcore_cmd_event_status[2] <= sdcore_csrfield_timeout0; - sdcore_cmd_event_status[3] <= sdcore_csrfield_crc0; -end -assign csrbank2_cmd_event_w = sdcore_cmd_event_status[3:0]; -assign sdcore_cmd_event_we = csrbank2_cmd_event_we; -always @(*) begin - sdcore_data_event_status <= 4'd0; - sdcore_data_event_status[0] <= sdcore_csrfield_done1; - sdcore_data_event_status[1] <= sdcore_csrfield_error1; - sdcore_data_event_status[2] <= sdcore_csrfield_timeout1; - sdcore_data_event_status[3] <= sdcore_csrfield_crc1; -end -assign csrbank2_data_event_w = sdcore_data_event_status[3:0]; -assign sdcore_data_event_we = csrbank2_data_event_we; -assign csrbank2_block_length0_w = sdcore_block_length_storage[9:0]; -assign csrbank2_block_count0_w = sdcore_block_count_storage[31:0]; -assign csrbank3_sel = (interface3_bank_bus_adr[13:9] == 2'd3); -assign csrbank3_status_r = interface3_bank_bus_dat_w[3:0]; -always @(*) begin - csrbank3_status_re <= 1'd0; - csrbank3_status_we <= 1'd0; - if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 1'd0))) begin - csrbank3_status_re <= interface3_bank_bus_we; - csrbank3_status_we <= (~interface3_bank_bus_we); - end -end -assign csrbank3_pending_r = interface3_bank_bus_dat_w[3:0]; -always @(*) begin - csrbank3_pending_re <= 1'd0; - csrbank3_pending_we <= 1'd0; - if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 1'd1))) begin - csrbank3_pending_re <= interface3_bank_bus_we; - csrbank3_pending_we <= (~interface3_bank_bus_we); - end -end -assign csrbank3_enable0_r = interface3_bank_bus_dat_w[3:0]; -always @(*) begin - csrbank3_enable0_we <= 1'd0; - csrbank3_enable0_re <= 1'd0; - if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 2'd2))) begin - csrbank3_enable0_re <= interface3_bank_bus_we; - csrbank3_enable0_we <= (~interface3_bank_bus_we); - end -end -always @(*) begin - eventmanager_status_status <= 4'd0; - eventmanager_status_status[0] <= eventmanager_card_detect0; - eventmanager_status_status[1] <= eventmanager_block2mem_dma0; - eventmanager_status_status[2] <= eventmanager_mem2block_dma0; - eventmanager_status_status[3] <= eventmanager_cmd_done0; -end -assign csrbank3_status_w = eventmanager_status_status[3:0]; -assign eventmanager_status_we = csrbank3_status_we; -always @(*) begin - eventmanager_pending_status <= 4'd0; - eventmanager_pending_status[0] <= eventmanager_card_detect1; - eventmanager_pending_status[1] <= eventmanager_block2mem_dma1; - eventmanager_pending_status[2] <= eventmanager_mem2block_dma1; - eventmanager_pending_status[3] <= eventmanager_cmd_done1; -end -assign csrbank3_pending_w = eventmanager_pending_status[3:0]; -assign eventmanager_pending_we = csrbank3_pending_we; -assign eventmanager_card_detect2 = eventmanager_enable_storage[0]; -assign eventmanager_block2mem_dma2 = eventmanager_enable_storage[1]; -assign eventmanager_mem2block_dma2 = eventmanager_enable_storage[2]; -assign eventmanager_cmd_done2 = eventmanager_enable_storage[3]; -assign csrbank3_enable0_w = eventmanager_enable_storage[3:0]; -assign csrbank4_sel = (interface4_bank_bus_adr[13:9] == 3'd4); -assign csrbank4_dma_base1_r = interface4_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank4_dma_base1_we <= 1'd0; - csrbank4_dma_base1_re <= 1'd0; - if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 1'd0))) begin - csrbank4_dma_base1_re <= interface4_bank_bus_we; - csrbank4_dma_base1_we <= (~interface4_bank_bus_we); - end -end -assign csrbank4_dma_base0_r = interface4_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank4_dma_base0_we <= 1'd0; - csrbank4_dma_base0_re <= 1'd0; - if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 1'd1))) begin - csrbank4_dma_base0_re <= interface4_bank_bus_we; - csrbank4_dma_base0_we <= (~interface4_bank_bus_we); - end -end -assign csrbank4_dma_length0_r = interface4_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank4_dma_length0_re <= 1'd0; - csrbank4_dma_length0_we <= 1'd0; - if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 2'd2))) begin - csrbank4_dma_length0_re <= interface4_bank_bus_we; - csrbank4_dma_length0_we <= (~interface4_bank_bus_we); - end -end -assign csrbank4_dma_enable0_r = interface4_bank_bus_dat_w[0]; -always @(*) begin - csrbank4_dma_enable0_we <= 1'd0; - csrbank4_dma_enable0_re <= 1'd0; - if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 2'd3))) begin - csrbank4_dma_enable0_re <= interface4_bank_bus_we; - csrbank4_dma_enable0_we <= (~interface4_bank_bus_we); - end -end -assign csrbank4_dma_done_r = interface4_bank_bus_dat_w[0]; -always @(*) begin - csrbank4_dma_done_re <= 1'd0; - csrbank4_dma_done_we <= 1'd0; - if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd4))) begin - csrbank4_dma_done_re <= interface4_bank_bus_we; - csrbank4_dma_done_we <= (~interface4_bank_bus_we); - end -end -assign csrbank4_dma_loop0_r = interface4_bank_bus_dat_w[0]; -always @(*) begin - csrbank4_dma_loop0_re <= 1'd0; - csrbank4_dma_loop0_we <= 1'd0; - if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd5))) begin - csrbank4_dma_loop0_re <= interface4_bank_bus_we; - csrbank4_dma_loop0_we <= (~interface4_bank_bus_we); - end -end -assign csrbank4_dma_offset_r = interface4_bank_bus_dat_w[31:0]; -always @(*) begin - csrbank4_dma_offset_we <= 1'd0; - csrbank4_dma_offset_re <= 1'd0; - if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd6))) begin - csrbank4_dma_offset_re <= interface4_bank_bus_we; - csrbank4_dma_offset_we <= (~interface4_bank_bus_we); - end -end -assign csrbank4_dma_base1_w = sdmem2block_dma_base_storage[63:32]; -assign csrbank4_dma_base0_w = sdmem2block_dma_base_storage[31:0]; -assign csrbank4_dma_length0_w = sdmem2block_dma_length_storage[31:0]; -assign csrbank4_dma_enable0_w = sdmem2block_dma_enable_storage; -assign csrbank4_dma_done_w = sdmem2block_dma_done_status; -assign sdmem2block_dma_done_we = csrbank4_dma_done_we; -assign csrbank4_dma_loop0_w = sdmem2block_dma_loop_storage; -assign csrbank4_dma_offset_w = sdmem2block_dma_offset_status[31:0]; -assign sdmem2block_dma_offset_we = csrbank4_dma_offset_we; -assign csrbank5_sel = (interface5_bank_bus_adr[13:9] == 3'd5); -assign csrbank5_card_detect_r = interface5_bank_bus_dat_w[0]; -always @(*) begin - csrbank5_card_detect_we <= 1'd0; - csrbank5_card_detect_re <= 1'd0; - if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 1'd0))) begin - csrbank5_card_detect_re <= interface5_bank_bus_we; - csrbank5_card_detect_we <= (~interface5_bank_bus_we); - end -end -assign csrbank5_clocker_divider0_r = interface5_bank_bus_dat_w[8:0]; -always @(*) begin - csrbank5_clocker_divider0_re <= 1'd0; - csrbank5_clocker_divider0_we <= 1'd0; - if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 1'd1))) begin - csrbank5_clocker_divider0_re <= interface5_bank_bus_we; - csrbank5_clocker_divider0_we <= (~interface5_bank_bus_we); - end -end -assign init_initialize_r = interface5_bank_bus_dat_w[0]; -always @(*) begin - init_initialize_re <= 1'd0; - init_initialize_we <= 1'd0; - if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 2'd2))) begin - init_initialize_re <= interface5_bank_bus_we; - init_initialize_we <= (~interface5_bank_bus_we); - end -end -assign csrbank5_dataw_status_r = interface5_bank_bus_dat_w[2:0]; -always @(*) begin - csrbank5_dataw_status_we <= 1'd0; - csrbank5_dataw_status_re <= 1'd0; - if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 2'd3))) begin - csrbank5_dataw_status_re <= interface5_bank_bus_we; - csrbank5_dataw_status_we <= (~interface5_bank_bus_we); - end -end -assign csrbank5_card_detect_w = card_detect_status0; -assign card_detect_we = csrbank5_card_detect_we; -assign csrbank5_clocker_divider0_w = clocker_storage[8:0]; -always @(*) begin - dataw_status <= 3'd0; - dataw_status[0] <= dataw_accepted0; - dataw_status[1] <= dataw_crc_error0; - dataw_status[2] <= dataw_write_error0; -end -assign csrbank5_dataw_status_w = dataw_status[2:0]; -assign dataw_we = csrbank5_dataw_status_we; -assign csr_interconnect_adr = litesdcardcore_adr; -assign csr_interconnect_we = litesdcardcore_we; -assign csr_interconnect_dat_w = litesdcardcore_dat_w; -assign litesdcardcore_dat_r = csr_interconnect_dat_r; -assign interface0_bank_bus_adr = csr_interconnect_adr; -assign interface1_bank_bus_adr = csr_interconnect_adr; -assign interface2_bank_bus_adr = csr_interconnect_adr; -assign interface3_bank_bus_adr = csr_interconnect_adr; -assign interface4_bank_bus_adr = csr_interconnect_adr; -assign interface5_bank_bus_adr = csr_interconnect_adr; -assign interface0_bank_bus_we = csr_interconnect_we; -assign interface1_bank_bus_we = csr_interconnect_we; -assign interface2_bank_bus_we = csr_interconnect_we; -assign interface3_bank_bus_we = csr_interconnect_we; -assign interface4_bank_bus_we = csr_interconnect_we; -assign interface5_bank_bus_we = csr_interconnect_we; -assign interface0_bank_bus_dat_w = csr_interconnect_dat_w; -assign interface1_bank_bus_dat_w = csr_interconnect_dat_w; -assign interface2_bank_bus_dat_w = csr_interconnect_dat_w; -assign interface3_bank_bus_dat_w = csr_interconnect_dat_w; -assign interface4_bank_bus_dat_w = csr_interconnect_dat_w; -assign interface5_bank_bus_dat_w = csr_interconnect_dat_w; -assign csr_interconnect_dat_r = (((((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r) | interface3_bank_bus_dat_r) | interface4_bank_bus_dat_r) | interface5_bank_bus_dat_r); -always @(*) begin - array_muxed0 <= 32'd0; - case (grant) - 1'd0: begin - array_muxed0 <= interface0_bus_adr; - end - default: begin - array_muxed0 <= interface1_bus_adr; - end - endcase -end -always @(*) begin - array_muxed1 <= 32'd0; - case (grant) - 1'd0: begin - array_muxed1 <= interface0_bus_dat_w; - end - default: begin - array_muxed1 <= interface1_bus_dat_w; - end - endcase -end -always @(*) begin - array_muxed2 <= 4'd0; - case (grant) - 1'd0: begin - array_muxed2 <= interface0_bus_sel; - end - default: begin - array_muxed2 <= interface1_bus_sel; - end - endcase -end -always @(*) begin - array_muxed3 <= 1'd0; - case (grant) - 1'd0: begin - array_muxed3 <= interface0_bus_cyc; - end - default: begin - array_muxed3 <= interface1_bus_cyc; - end - endcase -end -always @(*) begin - array_muxed4 <= 1'd0; - case (grant) - 1'd0: begin - array_muxed4 <= interface0_bus_stb; - end - default: begin - array_muxed4 <= interface1_bus_stb; - end - endcase -end -always @(*) begin - array_muxed5 <= 1'd0; - case (grant) - 1'd0: begin - array_muxed5 <= interface0_bus_we; - end - default: begin - array_muxed5 <= interface1_bus_we; - end - endcase -end -always @(*) begin - array_muxed6 <= 3'd0; - case (grant) - 1'd0: begin - array_muxed6 <= interface0_bus_cti; - end - default: begin - array_muxed6 <= interface1_bus_cti; - end - endcase -end -always @(*) begin - array_muxed7 <= 2'd0; - case (grant) - 1'd0: begin - array_muxed7 <= interface0_bus_bte; - end - default: begin - array_muxed7 <= interface1_bus_bte; - end - endcase -end -assign sdrio_clk = sys_clk; -assign sdrio_clk_1 = sys_clk; -assign sdrio_clk_2 = sys_clk; -assign sdrio_clk_3 = sys_clk; -assign sdrio_clk_4 = sys_clk; -assign sdrio_clk_5 = sys_clk; -assign sdrio_clk_6 = sys_clk; -assign sdrio_clk_7 = sys_clk; -assign sdrio_clk_8 = sys_clk; -assign sdrio_clk_9 = sys_clk; -assign sdrio_clk_10 = sys_clk; -assign sdrio_clk_11 = sys_clk; -assign sdrio_clk_12 = sys_clk; -assign sdrio_clk_13 = sys_clk; -assign sdrio_clk_14 = sys_clk; -assign sdrio_clk_15 = sys_clk; - - -//------------------------------------------------------------------------------ -// Synchronous Logic -//------------------------------------------------------------------------------ - -always @(posedge por_clk) begin - int_rst <= rst; -end - -always @(posedge sdrio_clk) begin - sdcard_clk <= (~clocker_clk0); - xilinxsdrtristateimpl0__o <= sdpads_cmd_o; - xilinxsdrtristateimpl0_oe_n <= (~sdpads_cmd_oe); - sdpads_cmd_i <= xilinxsdrtristateimpl0__i; - xilinxsdrtristateimpl1__o <= sdpads_data_o[0]; - xilinxsdrtristateimpl1_oe_n <= (~sdpads_data_oe); - sdpads_data_i[0] <= xilinxsdrtristateimpl1__i; - xilinxsdrtristateimpl2__o <= sdpads_data_o[1]; - xilinxsdrtristateimpl2_oe_n <= (~sdpads_data_oe); - sdpads_data_i[1] <= xilinxsdrtristateimpl2__i; - xilinxsdrtristateimpl3__o <= sdpads_data_o[2]; - xilinxsdrtristateimpl3_oe_n <= (~sdpads_data_oe); - sdpads_data_i[2] <= xilinxsdrtristateimpl3__i; - xilinxsdrtristateimpl4__o <= sdpads_data_o[3]; - xilinxsdrtristateimpl4_oe_n <= (~sdpads_data_oe); - sdpads_data_i[3] <= xilinxsdrtristateimpl4__i; -end - -always @(posedge sys_clk) begin - if ((bus_errors != 32'd4294967295)) begin - if (bus_error) begin - bus_errors <= (bus_errors + 1'd1); - end - end - card_detect_d <= card_detect_status0; - card_detect_irq <= (card_detect_status0 ^ card_detect_d); - if ((~clocker_stop)) begin - clocker_clks <= (clocker_clks + 1'd1); - end - clocker_clk_d <= clocker_clk1; - if (clocker_clk_d) begin - clocker_ce_delayed <= clocker_clk_en; - end - litesdcardcore_sdphyinit_state <= litesdcardcore_sdphyinit_next_state; - if (init_count_sdphyinit_next_value_ce) begin - init_count <= init_count_sdphyinit_next_value; - end - litesdcardcore_sdphycmdw_state <= litesdcardcore_sdphycmdw_next_state; - if (cmdw_count_sdphycmdw_next_value_ce) begin - cmdw_count <= cmdw_count_sdphycmdw_next_value; - end - if (cmdr_cmdr_pads_in_valid) begin - cmdr_cmdr_run <= (cmdr_cmdr_start | cmdr_cmdr_run); - end - if (cmdr_cmdr_converter_source_ready) begin - cmdr_cmdr_converter_strobe_all <= 1'd0; - end - if (cmdr_cmdr_converter_load_part) begin - if (((cmdr_cmdr_converter_demux == 3'd7) | cmdr_cmdr_converter_sink_last)) begin - cmdr_cmdr_converter_demux <= 1'd0; - cmdr_cmdr_converter_strobe_all <= 1'd1; - end else begin - cmdr_cmdr_converter_demux <= (cmdr_cmdr_converter_demux + 1'd1); - end - end - if ((cmdr_cmdr_converter_source_valid & cmdr_cmdr_converter_source_ready)) begin - if ((cmdr_cmdr_converter_sink_valid & cmdr_cmdr_converter_sink_ready)) begin - cmdr_cmdr_converter_source_first <= cmdr_cmdr_converter_sink_first; - cmdr_cmdr_converter_source_last <= cmdr_cmdr_converter_sink_last; - end else begin - cmdr_cmdr_converter_source_first <= 1'd0; - cmdr_cmdr_converter_source_last <= 1'd0; - end - end else begin - if ((cmdr_cmdr_converter_sink_valid & cmdr_cmdr_converter_sink_ready)) begin - cmdr_cmdr_converter_source_first <= (cmdr_cmdr_converter_sink_first | cmdr_cmdr_converter_source_first); - cmdr_cmdr_converter_source_last <= (cmdr_cmdr_converter_sink_last | cmdr_cmdr_converter_source_last); - end - end - if (cmdr_cmdr_converter_load_part) begin - case (cmdr_cmdr_converter_demux) - 1'd0: begin - cmdr_cmdr_converter_source_payload_data[7] <= cmdr_cmdr_converter_sink_payload_data; - end - 1'd1: begin - cmdr_cmdr_converter_source_payload_data[6] <= cmdr_cmdr_converter_sink_payload_data; - end - 2'd2: begin - cmdr_cmdr_converter_source_payload_data[5] <= cmdr_cmdr_converter_sink_payload_data; - end - 2'd3: begin - cmdr_cmdr_converter_source_payload_data[4] <= cmdr_cmdr_converter_sink_payload_data; - end - 3'd4: begin - cmdr_cmdr_converter_source_payload_data[3] <= cmdr_cmdr_converter_sink_payload_data; - end - 3'd5: begin - cmdr_cmdr_converter_source_payload_data[2] <= cmdr_cmdr_converter_sink_payload_data; - end - 3'd6: begin - cmdr_cmdr_converter_source_payload_data[1] <= cmdr_cmdr_converter_sink_payload_data; - end - 3'd7: begin - cmdr_cmdr_converter_source_payload_data[0] <= cmdr_cmdr_converter_sink_payload_data; - end - endcase - end - if (cmdr_cmdr_converter_load_part) begin - cmdr_cmdr_converter_source_payload_valid_token_count <= (cmdr_cmdr_converter_demux + 1'd1); - end - if (((~cmdr_cmdr_buf_source_valid) | cmdr_cmdr_buf_source_ready)) begin - cmdr_cmdr_buf_source_valid <= cmdr_cmdr_buf_sink_valid; - cmdr_cmdr_buf_source_first <= cmdr_cmdr_buf_sink_first; - cmdr_cmdr_buf_source_last <= cmdr_cmdr_buf_sink_last; - cmdr_cmdr_buf_source_payload_data <= cmdr_cmdr_buf_sink_payload_data; - end - if (cmdr_cmdr_reset) begin - cmdr_cmdr_run <= 1'd0; - cmdr_cmdr_converter_source_payload_data <= 8'd0; - cmdr_cmdr_converter_source_payload_valid_token_count <= 4'd0; - cmdr_cmdr_converter_demux <= 3'd0; - cmdr_cmdr_converter_strobe_all <= 1'd0; - cmdr_cmdr_buf_source_valid <= 1'd0; - cmdr_cmdr_buf_source_payload_data <= 8'd0; - end - litesdcardcore_sdphycmdr_state <= litesdcardcore_sdphycmdr_next_state; - if (cmdr_timeout_sdphycmdr_next_value_ce0) begin - cmdr_timeout <= cmdr_timeout_sdphycmdr_next_value0; - end - if (cmdr_count_sdphycmdr_next_value_ce1) begin - cmdr_count <= cmdr_count_sdphycmdr_next_value1; - end - if (cmdr_busy_sdphycmdr_next_value_ce2) begin - cmdr_busy <= cmdr_busy_sdphycmdr_next_value2; - end - if (cmdr_cmdr_reset_sdphycmdr_next_value_ce3) begin - cmdr_cmdr_reset <= cmdr_cmdr_reset_sdphycmdr_next_value3; - end - if (dataw_crc_pads_in_valid) begin - dataw_crc_run <= (dataw_crc_start | dataw_crc_run); - end - if (dataw_crc_converter_source_ready) begin - dataw_crc_converter_strobe_all <= 1'd0; - end - if (dataw_crc_converter_load_part) begin - if (((dataw_crc_converter_demux == 3'd7) | dataw_crc_converter_sink_last)) begin - dataw_crc_converter_demux <= 1'd0; - dataw_crc_converter_strobe_all <= 1'd1; - end else begin - dataw_crc_converter_demux <= (dataw_crc_converter_demux + 1'd1); - end - end - if ((dataw_crc_converter_source_valid & dataw_crc_converter_source_ready)) begin - if ((dataw_crc_converter_sink_valid & dataw_crc_converter_sink_ready)) begin - dataw_crc_converter_source_first <= dataw_crc_converter_sink_first; - dataw_crc_converter_source_last <= dataw_crc_converter_sink_last; - end else begin - dataw_crc_converter_source_first <= 1'd0; - dataw_crc_converter_source_last <= 1'd0; - end - end else begin - if ((dataw_crc_converter_sink_valid & dataw_crc_converter_sink_ready)) begin - dataw_crc_converter_source_first <= (dataw_crc_converter_sink_first | dataw_crc_converter_source_first); - dataw_crc_converter_source_last <= (dataw_crc_converter_sink_last | dataw_crc_converter_source_last); - end - end - if (dataw_crc_converter_load_part) begin - case (dataw_crc_converter_demux) - 1'd0: begin - dataw_crc_converter_source_payload_data[7] <= dataw_crc_converter_sink_payload_data; - end - 1'd1: begin - dataw_crc_converter_source_payload_data[6] <= dataw_crc_converter_sink_payload_data; - end - 2'd2: begin - dataw_crc_converter_source_payload_data[5] <= dataw_crc_converter_sink_payload_data; - end - 2'd3: begin - dataw_crc_converter_source_payload_data[4] <= dataw_crc_converter_sink_payload_data; - end - 3'd4: begin - dataw_crc_converter_source_payload_data[3] <= dataw_crc_converter_sink_payload_data; - end - 3'd5: begin - dataw_crc_converter_source_payload_data[2] <= dataw_crc_converter_sink_payload_data; - end - 3'd6: begin - dataw_crc_converter_source_payload_data[1] <= dataw_crc_converter_sink_payload_data; - end - 3'd7: begin - dataw_crc_converter_source_payload_data[0] <= dataw_crc_converter_sink_payload_data; - end - endcase - end - if (dataw_crc_converter_load_part) begin - dataw_crc_converter_source_payload_valid_token_count <= (dataw_crc_converter_demux + 1'd1); - end - if (((~dataw_crc_buf_source_valid) | dataw_crc_buf_source_ready)) begin - dataw_crc_buf_source_valid <= dataw_crc_buf_sink_valid; - dataw_crc_buf_source_first <= dataw_crc_buf_sink_first; - dataw_crc_buf_source_last <= dataw_crc_buf_sink_last; - dataw_crc_buf_source_payload_data <= dataw_crc_buf_sink_payload_data; - end - if (dataw_crc_reset) begin - dataw_crc_run <= 1'd0; - dataw_crc_converter_source_payload_data <= 8'd0; - dataw_crc_converter_source_payload_valid_token_count <= 4'd0; - dataw_crc_converter_demux <= 3'd0; - dataw_crc_converter_strobe_all <= 1'd0; - dataw_crc_buf_source_valid <= 1'd0; - dataw_crc_buf_source_payload_data <= 8'd0; - end - litesdcardcore_sdphydataw_state <= litesdcardcore_sdphydataw_next_state; - if (dataw_accepted1_sdphydataw_next_value_ce0) begin - dataw_accepted1 <= dataw_accepted1_sdphydataw_next_value0; - end - if (dataw_crc_error1_sdphydataw_next_value_ce1) begin - dataw_crc_error1 <= dataw_crc_error1_sdphydataw_next_value1; - end - if (dataw_write_error1_sdphydataw_next_value_ce2) begin - dataw_write_error1 <= dataw_write_error1_sdphydataw_next_value2; - end - if (dataw_count_sdphydataw_next_value_ce3) begin - dataw_count <= dataw_count_sdphydataw_next_value3; - end - if (datar_datar_pads_in_valid) begin - datar_datar_run <= (datar_datar_start | datar_datar_run); - end - if (datar_datar_converter_source_ready) begin - datar_datar_converter_strobe_all <= 1'd0; - end - if (datar_datar_converter_load_part) begin - if (((datar_datar_converter_demux == 1'd1) | datar_datar_converter_sink_last)) begin - datar_datar_converter_demux <= 1'd0; - datar_datar_converter_strobe_all <= 1'd1; - end else begin - datar_datar_converter_demux <= (datar_datar_converter_demux + 1'd1); - end - end - if ((datar_datar_converter_source_valid & datar_datar_converter_source_ready)) begin - if ((datar_datar_converter_sink_valid & datar_datar_converter_sink_ready)) begin - datar_datar_converter_source_first <= datar_datar_converter_sink_first; - datar_datar_converter_source_last <= datar_datar_converter_sink_last; - end else begin - datar_datar_converter_source_first <= 1'd0; - datar_datar_converter_source_last <= 1'd0; - end - end else begin - if ((datar_datar_converter_sink_valid & datar_datar_converter_sink_ready)) begin - datar_datar_converter_source_first <= (datar_datar_converter_sink_first | datar_datar_converter_source_first); - datar_datar_converter_source_last <= (datar_datar_converter_sink_last | datar_datar_converter_source_last); - end - end - if (datar_datar_converter_load_part) begin - case (datar_datar_converter_demux) - 1'd0: begin - datar_datar_converter_source_payload_data[7:4] <= datar_datar_converter_sink_payload_data; - end - 1'd1: begin - datar_datar_converter_source_payload_data[3:0] <= datar_datar_converter_sink_payload_data; - end - endcase - end - if (datar_datar_converter_load_part) begin - datar_datar_converter_source_payload_valid_token_count <= (datar_datar_converter_demux + 1'd1); - end - if (((~datar_datar_buf_source_valid) | datar_datar_buf_source_ready)) begin - datar_datar_buf_source_valid <= datar_datar_buf_sink_valid; - datar_datar_buf_source_first <= datar_datar_buf_sink_first; - datar_datar_buf_source_last <= datar_datar_buf_sink_last; - datar_datar_buf_source_payload_data <= datar_datar_buf_sink_payload_data; - end - if (datar_datar_reset) begin - datar_datar_run <= 1'd0; - datar_datar_converter_source_payload_data <= 8'd0; - datar_datar_converter_source_payload_valid_token_count <= 2'd0; - datar_datar_converter_demux <= 1'd0; - datar_datar_converter_strobe_all <= 1'd0; - datar_datar_buf_source_valid <= 1'd0; - datar_datar_buf_source_payload_data <= 8'd0; - end - litesdcardcore_sdphydatar_state <= litesdcardcore_sdphydatar_next_state; - if (datar_count_sdphydatar_next_value_ce0) begin - datar_count <= datar_count_sdphydatar_next_value0; - end - if (datar_timeout_sdphydatar_next_value_ce1) begin - datar_timeout <= datar_timeout_sdphydatar_next_value1; - end - if (datar_datar_reset_sdphydatar_next_value_ce2) begin - datar_datar_reset <= datar_datar_reset_sdphydatar_next_value2; - end - clocker_clk_delay <= {clocker_clk_delay, clocker_clk0}; - sdpads_data_i_ce <= (clocker_clk_delay[1] & (~clocker_clk_delay[0])); - if (sdcore_crc7_inserter_reset) begin - sdcore_crc7_inserter_reg0 <= 1'd0; - end else begin - if (sdcore_crc7_inserter_enable) begin - sdcore_crc7_inserter_reg0 <= sdcore_crc7_inserter_reg40; - end - end - if (sdcore_crc16_inserter_crc0_reset) begin - sdcore_crc16_inserter_crc0_reg0 <= 1'd0; - end else begin - if (sdcore_crc16_inserter_crc0_enable) begin - sdcore_crc16_inserter_crc0_reg0 <= sdcore_crc16_inserter_crc0_reg2; - end - end - if (sdcore_crc16_inserter_crc1_reset) begin - sdcore_crc16_inserter_crc1_reg0 <= 1'd0; - end else begin - if (sdcore_crc16_inserter_crc1_enable) begin - sdcore_crc16_inserter_crc1_reg0 <= sdcore_crc16_inserter_crc1_reg2; - end - end - if (sdcore_crc16_inserter_crc2_reset) begin - sdcore_crc16_inserter_crc2_reg0 <= 1'd0; - end else begin - if (sdcore_crc16_inserter_crc2_enable) begin - sdcore_crc16_inserter_crc2_reg0 <= sdcore_crc16_inserter_crc2_reg2; - end - end - if (sdcore_crc16_inserter_crc3_reset) begin - sdcore_crc16_inserter_crc3_reg0 <= 1'd0; - end else begin - if (sdcore_crc16_inserter_crc3_enable) begin - sdcore_crc16_inserter_crc3_reg0 <= sdcore_crc16_inserter_crc3_reg2; - end - end - litesdcardcore_sdcore_crc16inserter_state <= litesdcardcore_sdcore_crc16inserter_next_state; - if (sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value_ce) begin - sdcore_crc16_inserter_count <= sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value; - end - if (((sdcore_fifo_syncfifo_we & sdcore_fifo_syncfifo_writable) & (~sdcore_fifo_replace))) begin - sdcore_fifo_produce <= (sdcore_fifo_produce + 1'd1); - end - if (sdcore_fifo_do_read) begin - sdcore_fifo_consume <= (sdcore_fifo_consume + 1'd1); - end - if (((sdcore_fifo_syncfifo_we & sdcore_fifo_syncfifo_writable) & (~sdcore_fifo_replace))) begin - if ((~sdcore_fifo_do_read)) begin - sdcore_fifo_level <= (sdcore_fifo_level + 1'd1); - end - end else begin - if (sdcore_fifo_do_read) begin - sdcore_fifo_level <= (sdcore_fifo_level - 1'd1); - end - end - if (sdcore_fifo_reset) begin - sdcore_fifo_level <= 4'd0; - sdcore_fifo_produce <= 3'd0; - sdcore_fifo_consume <= 3'd0; - end - litesdcardcore_sdcore_fsm_state <= litesdcardcore_sdcore_fsm_next_state; - if (sdcore_cmd_done_sdcore_fsm_next_value_ce0) begin - sdcore_cmd_done <= sdcore_cmd_done_sdcore_fsm_next_value0; - end - if (sdcore_data_done_sdcore_fsm_next_value_ce1) begin - sdcore_data_done <= sdcore_data_done_sdcore_fsm_next_value1; - end - if (sdcore_cmd_count_sdcore_fsm_next_value_ce2) begin - sdcore_cmd_count <= sdcore_cmd_count_sdcore_fsm_next_value2; - end - if (sdcore_data_count_sdcore_fsm_next_value_ce3) begin - sdcore_data_count <= sdcore_data_count_sdcore_fsm_next_value3; - end - if (sdcore_cmd_error_sdcore_fsm_next_value_ce4) begin - sdcore_cmd_error <= sdcore_cmd_error_sdcore_fsm_next_value4; - end - if (sdcore_cmd_timeout_sdcore_fsm_next_value_ce5) begin - sdcore_cmd_timeout <= sdcore_cmd_timeout_sdcore_fsm_next_value5; - end - if (sdcore_data_error_sdcore_fsm_next_value_ce6) begin - sdcore_data_error <= sdcore_data_error_sdcore_fsm_next_value6; - end - if (sdcore_data_timeout_sdcore_fsm_next_value_ce7) begin - sdcore_data_timeout <= sdcore_data_timeout_sdcore_fsm_next_value7; - end - if (sdcore_cmd_response_status_sdcore_fsm_next_value_ce8) begin - sdcore_cmd_response_status <= sdcore_cmd_response_status_sdcore_fsm_next_value8; - end - if ((~sdblock2mem_wishbonedmawriter_enable_storage)) begin - sdblock2mem_connect <= 1'd0; - end else begin - if (sdblock2mem_start) begin - sdblock2mem_connect <= 1'd1; - end - end - sdblock2mem_done_d <= sdblock2mem_wishbonedmawriter_done_status; - sdblock2mem_irq <= (sdblock2mem_wishbonedmawriter_done_status & (~sdblock2mem_done_d)); - if (sdblock2mem_fifo_syncfifo_re) begin - sdblock2mem_fifo_readable <= 1'd1; - end else begin - if (sdblock2mem_fifo_re) begin - sdblock2mem_fifo_readable <= 1'd0; - end - end - if (((sdblock2mem_fifo_syncfifo_we & sdblock2mem_fifo_syncfifo_writable) & (~sdblock2mem_fifo_replace))) begin - sdblock2mem_fifo_produce <= (sdblock2mem_fifo_produce + 1'd1); - end - if (sdblock2mem_fifo_do_read) begin - sdblock2mem_fifo_consume <= (sdblock2mem_fifo_consume + 1'd1); - end - if (((sdblock2mem_fifo_syncfifo_we & sdblock2mem_fifo_syncfifo_writable) & (~sdblock2mem_fifo_replace))) begin - if ((~sdblock2mem_fifo_do_read)) begin - sdblock2mem_fifo_level0 <= (sdblock2mem_fifo_level0 + 1'd1); - end - end else begin - if (sdblock2mem_fifo_do_read) begin - sdblock2mem_fifo_level0 <= (sdblock2mem_fifo_level0 - 1'd1); - end - end - if (sdblock2mem_converter_source_ready) begin - sdblock2mem_converter_strobe_all <= 1'd0; - end - if (sdblock2mem_converter_load_part) begin - if (((sdblock2mem_converter_demux == 2'd3) | sdblock2mem_converter_sink_last)) begin - sdblock2mem_converter_demux <= 1'd0; - sdblock2mem_converter_strobe_all <= 1'd1; - end else begin - sdblock2mem_converter_demux <= (sdblock2mem_converter_demux + 1'd1); - end - end - if ((sdblock2mem_converter_source_valid & sdblock2mem_converter_source_ready)) begin - if ((sdblock2mem_converter_sink_valid & sdblock2mem_converter_sink_ready)) begin - sdblock2mem_converter_source_first <= sdblock2mem_converter_sink_first; - sdblock2mem_converter_source_last <= sdblock2mem_converter_sink_last; - end else begin - sdblock2mem_converter_source_first <= 1'd0; - sdblock2mem_converter_source_last <= 1'd0; - end - end else begin - if ((sdblock2mem_converter_sink_valid & sdblock2mem_converter_sink_ready)) begin - sdblock2mem_converter_source_first <= (sdblock2mem_converter_sink_first | sdblock2mem_converter_source_first); - sdblock2mem_converter_source_last <= (sdblock2mem_converter_sink_last | sdblock2mem_converter_source_last); - end - end - if (sdblock2mem_converter_load_part) begin - case (sdblock2mem_converter_demux) - 1'd0: begin - sdblock2mem_converter_source_payload_data[31:24] <= sdblock2mem_converter_sink_payload_data; - end - 1'd1: begin - sdblock2mem_converter_source_payload_data[23:16] <= sdblock2mem_converter_sink_payload_data; - end - 2'd2: begin - sdblock2mem_converter_source_payload_data[15:8] <= sdblock2mem_converter_sink_payload_data; - end - 2'd3: begin - sdblock2mem_converter_source_payload_data[7:0] <= sdblock2mem_converter_sink_payload_data; - end - endcase - end - if (sdblock2mem_converter_load_part) begin - sdblock2mem_converter_source_payload_valid_token_count <= (sdblock2mem_converter_demux + 1'd1); - end - litesdcardcore_sdblock2memdma_state <= litesdcardcore_sdblock2memdma_next_state; - if (sdblock2mem_wishbonedmawriter_offset_next_value_ce) begin - sdblock2mem_wishbonedmawriter_offset <= sdblock2mem_wishbonedmawriter_offset_next_value; - end - if (sdblock2mem_wishbonedmawriter_reset) begin - sdblock2mem_wishbonedmawriter_offset <= 32'd0; - litesdcardcore_sdblock2memdma_state <= 2'd0; - end - if ((sdmem2block_source_source_valid0 & sdmem2block_source_source_ready0)) begin - sdmem2block_count <= (sdmem2block_count + 1'd1); - if (sdmem2block_source_source_last0) begin - sdmem2block_count <= 1'd0; - end - end - sdmem2block_done_d <= sdmem2block_dma_done_status; - sdmem2block_irq <= (sdmem2block_dma_done_status & (~sdmem2block_done_d)); - litesdcardcore_sdmem2blockdma_fsm_state <= litesdcardcore_sdmem2blockdma_fsm_next_state; - if (sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce) begin - sdmem2block_dma_data <= sdmem2block_dma_data_sdmem2blockdma_fsm_next_value; - end - litesdcardcore_sdmem2blockdma_resetinserter_state <= litesdcardcore_sdmem2blockdma_resetinserter_next_state; - if (sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce) begin - sdmem2block_dma_offset <= sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value; - end - if (sdmem2block_dma_reset) begin - sdmem2block_dma_offset <= 32'd0; - litesdcardcore_sdmem2blockdma_resetinserter_state <= 2'd0; - end - if ((sdmem2block_converter_source_valid & sdmem2block_converter_source_ready)) begin - if (sdmem2block_converter_last) begin - sdmem2block_converter_mux <= 1'd0; - end else begin - sdmem2block_converter_mux <= (sdmem2block_converter_mux + 1'd1); - end - end - if (sdmem2block_fifo_syncfifo_re) begin - sdmem2block_fifo_readable <= 1'd1; - end else begin - if (sdmem2block_fifo_re) begin - sdmem2block_fifo_readable <= 1'd0; - end - end - if (((sdmem2block_fifo_syncfifo_we & sdmem2block_fifo_syncfifo_writable) & (~sdmem2block_fifo_replace))) begin - sdmem2block_fifo_produce <= (sdmem2block_fifo_produce + 1'd1); - end - if (sdmem2block_fifo_do_read) begin - sdmem2block_fifo_consume <= (sdmem2block_fifo_consume + 1'd1); - end - if (((sdmem2block_fifo_syncfifo_we & sdmem2block_fifo_syncfifo_writable) & (~sdmem2block_fifo_replace))) begin - if ((~sdmem2block_fifo_do_read)) begin - sdmem2block_fifo_level0 <= (sdmem2block_fifo_level0 + 1'd1); - end - end else begin - if (sdmem2block_fifo_do_read) begin - sdmem2block_fifo_level0 <= (sdmem2block_fifo_level0 - 1'd1); - end - end - if (card_detect_clear) begin - card_detect_pending <= 1'd0; - end - if (card_detect_trigger) begin - card_detect_pending <= 1'd1; - end - if (block2mem_dma_clear) begin - block2mem_dma_pending <= 1'd0; - end - if (block2mem_dma_trigger) begin - block2mem_dma_pending <= 1'd1; - end - if (mem2block_dma_clear) begin - mem2block_dma_pending <= 1'd0; - end - if (mem2block_dma_trigger) begin - mem2block_dma_pending <= 1'd1; - end - litesdcardcore_wishbone2csr_state <= litesdcardcore_wishbone2csr_next_state; - case (grant) - 1'd0: begin - if ((~request[0])) begin - if (request[1]) begin - grant <= 1'd1; - end - end - end - 1'd1: begin - if ((~request[1])) begin - if (request[0]) begin - grant <= 1'd0; - end - end - end - endcase - slave_sel_r <= slave_sel; - if (wait_1) begin - if ((~done)) begin - count <= (count - 1'd1); - end - end else begin - count <= 20'd1000000; - end - interface0_bank_bus_dat_r <= 1'd0; - if (csrbank0_sel) begin - case (interface0_bank_bus_adr[8:0]) - 1'd0: begin - interface0_bank_bus_dat_r <= csrbank0_reset0_w; - end - 1'd1: begin - interface0_bank_bus_dat_r <= csrbank0_scratch0_w; - end - 2'd2: begin - interface0_bank_bus_dat_r <= csrbank0_bus_errors_w; - end - endcase - end - if (csrbank0_reset0_re) begin - reset_storage[1:0] <= csrbank0_reset0_r; - end - reset_re <= csrbank0_reset0_re; - if (csrbank0_scratch0_re) begin - scratch_storage[31:0] <= csrbank0_scratch0_r; - end - scratch_re <= csrbank0_scratch0_re; - bus_errors_re <= csrbank0_bus_errors_re; - interface1_bank_bus_dat_r <= 1'd0; - if (csrbank1_sel) begin - case (interface1_bank_bus_adr[8:0]) - 1'd0: begin - interface1_bank_bus_dat_r <= csrbank1_dma_base1_w; - end - 1'd1: begin - interface1_bank_bus_dat_r <= csrbank1_dma_base0_w; - end - 2'd2: begin - interface1_bank_bus_dat_r <= csrbank1_dma_length0_w; - end - 2'd3: begin - interface1_bank_bus_dat_r <= csrbank1_dma_enable0_w; - end - 3'd4: begin - interface1_bank_bus_dat_r <= csrbank1_dma_done_w; - end - 3'd5: begin - interface1_bank_bus_dat_r <= csrbank1_dma_loop0_w; - end - 3'd6: begin - interface1_bank_bus_dat_r <= csrbank1_dma_offset_w; - end - endcase - end - if (csrbank1_dma_base1_re) begin - sdblock2mem_wishbonedmawriter_base_storage[63:32] <= csrbank1_dma_base1_r; - end - if (csrbank1_dma_base0_re) begin - sdblock2mem_wishbonedmawriter_base_storage[31:0] <= csrbank1_dma_base0_r; - end - sdblock2mem_wishbonedmawriter_base_re <= csrbank1_dma_base0_re; - if (csrbank1_dma_length0_re) begin - sdblock2mem_wishbonedmawriter_length_storage[31:0] <= csrbank1_dma_length0_r; - end - sdblock2mem_wishbonedmawriter_length_re <= csrbank1_dma_length0_re; - if (csrbank1_dma_enable0_re) begin - sdblock2mem_wishbonedmawriter_enable_storage <= csrbank1_dma_enable0_r; - end - sdblock2mem_wishbonedmawriter_enable_re <= csrbank1_dma_enable0_re; - sdblock2mem_wishbonedmawriter_done_re <= csrbank1_dma_done_re; - if (csrbank1_dma_loop0_re) begin - sdblock2mem_wishbonedmawriter_loop_storage <= csrbank1_dma_loop0_r; - end - sdblock2mem_wishbonedmawriter_loop_re <= csrbank1_dma_loop0_re; - sdblock2mem_wishbonedmawriter_offset_re <= csrbank1_dma_offset_re; - interface2_bank_bus_dat_r <= 1'd0; - if (csrbank2_sel) begin - case (interface2_bank_bus_adr[8:0]) - 1'd0: begin - interface2_bank_bus_dat_r <= csrbank2_cmd_argument0_w; - end - 1'd1: begin - interface2_bank_bus_dat_r <= csrbank2_cmd_command0_w; - end - 2'd2: begin - interface2_bank_bus_dat_r <= csrbank2_cmd_send0_w; - end - 2'd3: begin - interface2_bank_bus_dat_r <= csrbank2_cmd_response3_w; - end - 3'd4: begin - interface2_bank_bus_dat_r <= csrbank2_cmd_response2_w; - end - 3'd5: begin - interface2_bank_bus_dat_r <= csrbank2_cmd_response1_w; - end - 3'd6: begin - interface2_bank_bus_dat_r <= csrbank2_cmd_response0_w; - end - 3'd7: begin - interface2_bank_bus_dat_r <= csrbank2_cmd_event_w; - end - 4'd8: begin - interface2_bank_bus_dat_r <= csrbank2_data_event_w; - end - 4'd9: begin - interface2_bank_bus_dat_r <= csrbank2_block_length0_w; - end - 4'd10: begin - interface2_bank_bus_dat_r <= csrbank2_block_count0_w; - end - endcase - end - if (csrbank2_cmd_argument0_re) begin - sdcore_cmd_argument_storage[31:0] <= csrbank2_cmd_argument0_r; - end - sdcore_cmd_argument_re <= csrbank2_cmd_argument0_re; - if (csrbank2_cmd_command0_re) begin - sdcore_cmd_command_storage[13:0] <= csrbank2_cmd_command0_r; - end - sdcore_cmd_command_re <= csrbank2_cmd_command0_re; - if (csrbank2_cmd_send0_re) begin - sdcore_cmd_send_storage <= csrbank2_cmd_send0_r; - end - sdcore_cmd_send_re <= csrbank2_cmd_send0_re; - sdcore_cmd_response_re <= csrbank2_cmd_response0_re; - sdcore_cmd_event_re <= csrbank2_cmd_event_re; - sdcore_data_event_re <= csrbank2_data_event_re; - if (csrbank2_block_length0_re) begin - sdcore_block_length_storage[9:0] <= csrbank2_block_length0_r; - end - sdcore_block_length_re <= csrbank2_block_length0_re; - if (csrbank2_block_count0_re) begin - sdcore_block_count_storage[31:0] <= csrbank2_block_count0_r; - end - sdcore_block_count_re <= csrbank2_block_count0_re; - interface3_bank_bus_dat_r <= 1'd0; - if (csrbank3_sel) begin - case (interface3_bank_bus_adr[8:0]) - 1'd0: begin - interface3_bank_bus_dat_r <= csrbank3_status_w; - end - 1'd1: begin - interface3_bank_bus_dat_r <= csrbank3_pending_w; - end - 2'd2: begin - interface3_bank_bus_dat_r <= csrbank3_enable0_w; - end - endcase - end - eventmanager_status_re <= csrbank3_status_re; - if (csrbank3_pending_re) begin - eventmanager_pending_r[3:0] <= csrbank3_pending_r; - end - eventmanager_pending_re <= csrbank3_pending_re; - if (csrbank3_enable0_re) begin - eventmanager_enable_storage[3:0] <= csrbank3_enable0_r; - end - eventmanager_enable_re <= csrbank3_enable0_re; - interface4_bank_bus_dat_r <= 1'd0; - if (csrbank4_sel) begin - case (interface4_bank_bus_adr[8:0]) - 1'd0: begin - interface4_bank_bus_dat_r <= csrbank4_dma_base1_w; - end - 1'd1: begin - interface4_bank_bus_dat_r <= csrbank4_dma_base0_w; - end - 2'd2: begin - interface4_bank_bus_dat_r <= csrbank4_dma_length0_w; - end - 2'd3: begin - interface4_bank_bus_dat_r <= csrbank4_dma_enable0_w; - end - 3'd4: begin - interface4_bank_bus_dat_r <= csrbank4_dma_done_w; - end - 3'd5: begin - interface4_bank_bus_dat_r <= csrbank4_dma_loop0_w; - end - 3'd6: begin - interface4_bank_bus_dat_r <= csrbank4_dma_offset_w; - end - endcase - end - if (csrbank4_dma_base1_re) begin - sdmem2block_dma_base_storage[63:32] <= csrbank4_dma_base1_r; - end - if (csrbank4_dma_base0_re) begin - sdmem2block_dma_base_storage[31:0] <= csrbank4_dma_base0_r; - end - sdmem2block_dma_base_re <= csrbank4_dma_base0_re; - if (csrbank4_dma_length0_re) begin - sdmem2block_dma_length_storage[31:0] <= csrbank4_dma_length0_r; - end - sdmem2block_dma_length_re <= csrbank4_dma_length0_re; - if (csrbank4_dma_enable0_re) begin - sdmem2block_dma_enable_storage <= csrbank4_dma_enable0_r; - end - sdmem2block_dma_enable_re <= csrbank4_dma_enable0_re; - sdmem2block_dma_done_re <= csrbank4_dma_done_re; - if (csrbank4_dma_loop0_re) begin - sdmem2block_dma_loop_storage <= csrbank4_dma_loop0_r; - end - sdmem2block_dma_loop_re <= csrbank4_dma_loop0_re; - sdmem2block_dma_offset_re <= csrbank4_dma_offset_re; - interface5_bank_bus_dat_r <= 1'd0; - if (csrbank5_sel) begin - case (interface5_bank_bus_adr[8:0]) - 1'd0: begin - interface5_bank_bus_dat_r <= csrbank5_card_detect_w; - end - 1'd1: begin - interface5_bank_bus_dat_r <= csrbank5_clocker_divider0_w; - end - 2'd2: begin - interface5_bank_bus_dat_r <= init_initialize_w; - end - 2'd3: begin - interface5_bank_bus_dat_r <= csrbank5_dataw_status_w; - end - endcase - end - card_detect_re <= csrbank5_card_detect_re; - if (csrbank5_clocker_divider0_re) begin - clocker_storage[8:0] <= csrbank5_clocker_divider0_r; - end - clocker_re <= csrbank5_clocker_divider0_re; - dataw_re <= csrbank5_dataw_status_re; - if (sys_rst) begin - reset_storage <= 2'd0; - reset_re <= 1'd0; - scratch_storage <= 32'd305419896; - scratch_re <= 1'd0; - bus_errors_re <= 1'd0; - bus_errors <= 32'd0; - card_detect_re <= 1'd0; - clocker_storage <= 9'd256; - clocker_re <= 1'd0; - clocker_clks <= 9'd0; - clocker_clk_d <= 1'd0; - clocker_ce_delayed <= 1'd0; - init_count <= 8'd0; - cmdw_count <= 8'd0; - cmdr_timeout <= 32'd100000000; - cmdr_count <= 8'd0; - cmdr_busy <= 1'd0; - cmdr_cmdr_run <= 1'd0; - cmdr_cmdr_converter_source_payload_data <= 8'd0; - cmdr_cmdr_converter_source_payload_valid_token_count <= 4'd0; - cmdr_cmdr_converter_demux <= 3'd0; - cmdr_cmdr_converter_strobe_all <= 1'd0; - cmdr_cmdr_buf_source_valid <= 1'd0; - cmdr_cmdr_buf_source_payload_data <= 8'd0; - cmdr_cmdr_reset <= 1'd0; - dataw_re <= 1'd0; - dataw_count <= 8'd0; - dataw_accepted1 <= 1'd0; - dataw_crc_error1 <= 1'd0; - dataw_write_error1 <= 1'd0; - dataw_crc_run <= 1'd0; - dataw_crc_converter_source_payload_data <= 8'd0; - dataw_crc_converter_source_payload_valid_token_count <= 4'd0; - dataw_crc_converter_demux <= 3'd0; - dataw_crc_converter_strobe_all <= 1'd0; - dataw_crc_buf_source_valid <= 1'd0; - dataw_crc_buf_source_payload_data <= 8'd0; - datar_timeout <= 32'd100000000; - datar_count <= 10'd0; - datar_datar_run <= 1'd0; - datar_datar_converter_source_payload_data <= 8'd0; - datar_datar_converter_source_payload_valid_token_count <= 2'd0; - datar_datar_converter_demux <= 1'd0; - datar_datar_converter_strobe_all <= 1'd0; - datar_datar_buf_source_valid <= 1'd0; - datar_datar_buf_source_payload_data <= 8'd0; - datar_datar_reset <= 1'd0; - sdpads_data_i_ce <= 1'd0; - clocker_clk_delay <= 2'd0; - card_detect_irq <= 1'd0; - card_detect_d <= 1'd0; - sdcore_cmd_argument_storage <= 32'd0; - sdcore_cmd_argument_re <= 1'd0; - sdcore_cmd_command_storage <= 14'd0; - sdcore_cmd_command_re <= 1'd0; - sdcore_cmd_send_storage <= 1'd0; - sdcore_cmd_send_re <= 1'd0; - sdcore_cmd_response_status <= 128'd0; - sdcore_cmd_response_re <= 1'd0; - sdcore_cmd_event_re <= 1'd0; - sdcore_data_event_re <= 1'd0; - sdcore_block_length_storage <= 10'd0; - sdcore_block_length_re <= 1'd0; - sdcore_block_count_storage <= 32'd0; - sdcore_block_count_re <= 1'd0; - sdcore_crc7_inserter_reg0 <= 7'd0; - sdcore_crc16_inserter_count <= 3'd0; - sdcore_crc16_inserter_crc0_reg0 <= 16'd0; - sdcore_crc16_inserter_crc1_reg0 <= 16'd0; - sdcore_crc16_inserter_crc2_reg0 <= 16'd0; - sdcore_crc16_inserter_crc3_reg0 <= 16'd0; - sdcore_fifo_level <= 4'd0; - sdcore_fifo_produce <= 3'd0; - sdcore_fifo_consume <= 3'd0; - sdcore_cmd_count <= 3'd0; - sdcore_cmd_done <= 1'd0; - sdcore_cmd_error <= 1'd0; - sdcore_cmd_timeout <= 1'd0; - sdcore_data_count <= 32'd0; - sdcore_data_done <= 1'd0; - sdcore_data_error <= 1'd0; - sdcore_data_timeout <= 1'd0; - sdblock2mem_irq <= 1'd0; - sdblock2mem_fifo_readable <= 1'd0; - sdblock2mem_fifo_level0 <= 10'd0; - sdblock2mem_fifo_produce <= 9'd0; - sdblock2mem_fifo_consume <= 9'd0; - sdblock2mem_converter_source_payload_data <= 32'd0; - sdblock2mem_converter_source_payload_valid_token_count <= 3'd0; - sdblock2mem_converter_demux <= 2'd0; - sdblock2mem_converter_strobe_all <= 1'd0; - sdblock2mem_wishbonedmawriter_base_storage <= 64'd0; - sdblock2mem_wishbonedmawriter_base_re <= 1'd0; - sdblock2mem_wishbonedmawriter_length_storage <= 32'd0; - sdblock2mem_wishbonedmawriter_length_re <= 1'd0; - sdblock2mem_wishbonedmawriter_enable_storage <= 1'd0; - sdblock2mem_wishbonedmawriter_enable_re <= 1'd0; - sdblock2mem_wishbonedmawriter_done_re <= 1'd0; - sdblock2mem_wishbonedmawriter_loop_storage <= 1'd0; - sdblock2mem_wishbonedmawriter_loop_re <= 1'd0; - sdblock2mem_wishbonedmawriter_offset_re <= 1'd0; - sdblock2mem_wishbonedmawriter_offset <= 32'd0; - sdblock2mem_connect <= 1'd0; - sdblock2mem_done_d <= 1'd0; - sdmem2block_irq <= 1'd0; - sdmem2block_dma_data <= 32'd0; - sdmem2block_dma_base_storage <= 64'd0; - sdmem2block_dma_base_re <= 1'd0; - sdmem2block_dma_length_storage <= 32'd0; - sdmem2block_dma_length_re <= 1'd0; - sdmem2block_dma_enable_storage <= 1'd0; - sdmem2block_dma_enable_re <= 1'd0; - sdmem2block_dma_done_re <= 1'd0; - sdmem2block_dma_loop_storage <= 1'd0; - sdmem2block_dma_loop_re <= 1'd0; - sdmem2block_dma_offset_re <= 1'd0; - sdmem2block_dma_offset <= 32'd0; - sdmem2block_converter_mux <= 2'd0; - sdmem2block_fifo_readable <= 1'd0; - sdmem2block_fifo_level0 <= 10'd0; - sdmem2block_fifo_produce <= 9'd0; - sdmem2block_fifo_consume <= 9'd0; - sdmem2block_count <= 9'd0; - sdmem2block_done_d <= 1'd0; - card_detect_pending <= 1'd0; - block2mem_dma_pending <= 1'd0; - mem2block_dma_pending <= 1'd0; - eventmanager_status_re <= 1'd0; - eventmanager_pending_re <= 1'd0; - eventmanager_pending_r <= 4'd0; - eventmanager_enable_storage <= 4'd0; - eventmanager_enable_re <= 1'd0; - grant <= 1'd0; - slave_sel_r <= 1'd0; - count <= 20'd1000000; - litesdcardcore_sdphyinit_state <= 1'd0; - litesdcardcore_sdphycmdw_state <= 2'd0; - litesdcardcore_sdphycmdr_state <= 3'd0; - litesdcardcore_sdphydataw_state <= 3'd0; - litesdcardcore_sdphydatar_state <= 3'd0; - litesdcardcore_sdcore_crc16inserter_state <= 1'd0; - litesdcardcore_sdcore_fsm_state <= 3'd0; - litesdcardcore_sdblock2memdma_state <= 2'd0; - litesdcardcore_sdmem2blockdma_fsm_state <= 1'd0; - litesdcardcore_sdmem2blockdma_resetinserter_state <= 2'd0; - litesdcardcore_wishbone2csr_state <= 1'd0; - end -end - - -//------------------------------------------------------------------------------ -// Specialized Logic -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Memory storage: 8-words x 10-bit -//------------------------------------------------------------------------------ -// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 -// Port 1 | Read: Async | Write: ---- | -reg [9:0] storage[0:7]; -reg [9:0] storage_dat0; -always @(posedge sys_clk) begin - if (sdcore_fifo_wrport_we) - storage[sdcore_fifo_wrport_adr] <= sdcore_fifo_wrport_dat_w; - storage_dat0 <= storage[sdcore_fifo_wrport_adr]; -end -always @(posedge sys_clk) begin -end -assign sdcore_fifo_wrport_dat_r = storage_dat0; -assign sdcore_fifo_rdport_dat_r = storage[sdcore_fifo_rdport_adr]; - - -//------------------------------------------------------------------------------ -// Memory storage_1: 512-words x 10-bit -//------------------------------------------------------------------------------ -// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 -// Port 1 | Read: Sync | Write: ---- | -reg [9:0] storage_1[0:511]; -reg [9:0] storage_1_dat0; -reg [9:0] storage_1_dat1; -always @(posedge sys_clk) begin - if (sdblock2mem_fifo_wrport_we) - storage_1[sdblock2mem_fifo_wrport_adr] <= sdblock2mem_fifo_wrport_dat_w; - storage_1_dat0 <= storage_1[sdblock2mem_fifo_wrport_adr]; -end -always @(posedge sys_clk) begin - if (sdblock2mem_fifo_rdport_re) - storage_1_dat1 <= storage_1[sdblock2mem_fifo_rdport_adr]; -end -assign sdblock2mem_fifo_wrport_dat_r = storage_1_dat0; -assign sdblock2mem_fifo_rdport_dat_r = storage_1_dat1; - - -//------------------------------------------------------------------------------ -// Memory storage_2: 512-words x 10-bit -//------------------------------------------------------------------------------ -// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 -// Port 1 | Read: Sync | Write: ---- | -reg [9:0] storage_2[0:511]; -reg [9:0] storage_2_dat0; -reg [9:0] storage_2_dat1; -always @(posedge sys_clk) begin - if (sdmem2block_fifo_wrport_we) - storage_2[sdmem2block_fifo_wrport_adr] <= sdmem2block_fifo_wrport_dat_w; - storage_2_dat0 <= storage_2[sdmem2block_fifo_wrport_adr]; -end -always @(posedge sys_clk) begin - if (sdmem2block_fifo_rdport_re) - storage_2_dat1 <= storage_2[sdmem2block_fifo_rdport_adr]; -end -assign sdmem2block_fifo_wrport_dat_r = storage_2_dat0; -assign sdmem2block_fifo_rdport_dat_r = storage_2_dat1; - - -IOBUF IOBUF( - .I(xilinxsdrtristateimpl0__o), - .T(xilinxsdrtristateimpl0_oe_n), - .IO(sdcard_cmd), - .O(xilinxsdrtristateimpl0__i) -); - -IOBUF IOBUF_1( - .I(xilinxsdrtristateimpl1__o), - .T(xilinxsdrtristateimpl1_oe_n), - .IO(sdcard_data[0]), - .O(xilinxsdrtristateimpl1__i) -); - -IOBUF IOBUF_2( - .I(xilinxsdrtristateimpl2__o), - .T(xilinxsdrtristateimpl2_oe_n), - .IO(sdcard_data[1]), - .O(xilinxsdrtristateimpl2__i) -); - -IOBUF IOBUF_3( - .I(xilinxsdrtristateimpl3__o), - .T(xilinxsdrtristateimpl3_oe_n), - .IO(sdcard_data[2]), - .O(xilinxsdrtristateimpl3__i) -); - -IOBUF IOBUF_4( - .I(xilinxsdrtristateimpl4__o), - .T(xilinxsdrtristateimpl4_oe_n), - .IO(sdcard_data[3]), - .O(xilinxsdrtristateimpl4__i) -); - -endmodule - -// ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2022-08-04 18:14:15. -//------------------------------------------------------------------------------ diff --git a/microwatt.core b/microwatt.core index 508b346..dad180f 100644 --- a/microwatt.core +++ b/microwatt.core @@ -460,11 +460,11 @@ generate: litesdcard_arty: generator: litesdcard_gen - parameters: {vendor : xilinx} + parameters: {vendor : xilinx, frequency : 100e6} litesdcard_nexys_video: generator: litesdcard_gen - parameters: {vendor : xilinx} + parameters: {vendor : xilinx, frequency : 100e6} litedram_nexys_video: generator: litedram_gen @@ -492,7 +492,7 @@ generate: litesdcard_wukong-v2: generator: litesdcard_gen - parameters: {vendor : xilinx} + parameters: {vendor : xilinx, frequency : 100e6} parameters: memory_size: diff --git a/openocd/ecpix-5.cfg b/openocd/ecpix-5.cfg new file mode 100644 index 0000000..bab2db8 --- /dev/null +++ b/openocd/ecpix-5.cfg @@ -0,0 +1,6 @@ +adapter driver ftdi +ftdi vid_pid 0x0403 0x6011 +ftdi channel 0 +ftdi layout_init 0xfff8 0xfffb +reset_config none +adapter speed 25000